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d85861d7 LE |
1 | /** @file\r |
2 | OVMF's instance of the PCI Host Bridge Library.\r | |
3 | \r | |
4 | Copyright (C) 2016, Red Hat, Inc.\r | |
5 | Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>\r | |
6 | \r | |
b26f0cf9 | 7 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
d85861d7 LE |
8 | \r |
9 | **/\r | |
32fef035 LE |
10 | #include <IndustryStandard/Pci.h> // PCI_MAX_BUS\r |
11 | #include <IndustryStandard/Q35MchIch9.h> // INTEL_Q35_MCH_DEVIC...\r | |
12 | #include <Library/BaseMemoryLib.h> // ZeroMem()\r | |
13 | #include <Library/PcdLib.h> // PcdGet64()\r | |
14 | #include <Library/PciHostBridgeLib.h> // PCI_ROOT_BRIDGE_APE...\r | |
15 | #include <Library/PciHostBridgeUtilityLib.h> // PciHostBridgeUtilit...\r | |
16 | #include <Protocol/PciHostBridgeResourceAllocation.h> // EFI_PCI_HOST_BRIDGE...\r | |
17 | #include <Protocol/PciRootBridgeIo.h> // EFI_PCI_ATTRIBUTE_I...\r | |
46e46eaf | 18 | \r |
ac0a286f | 19 | STATIC PCI_ROOT_BRIDGE_APERTURE mNonExistAperture = { MAX_UINT64, 0 };\r |
46e46eaf | 20 | \r |
d85861d7 LE |
21 | /**\r |
22 | Return all the root bridge instances in an array.\r | |
23 | \r | |
24 | @param Count Return the count of root bridge instances.\r | |
25 | \r | |
26 | @return All the root bridge instances in an array.\r | |
27 | The array should be passed into PciHostBridgeFreeRootBridges()\r | |
28 | when it's not used.\r | |
29 | **/\r | |
30 | PCI_ROOT_BRIDGE *\r | |
31 | EFIAPI\r | |
32 | PciHostBridgeGetRootBridges (\r | |
ac0a286f | 33 | UINTN *Count\r |
d85861d7 LE |
34 | )\r |
35 | {\r | |
ac0a286f MK |
36 | UINT64 Attributes;\r |
37 | UINT64 AllocationAttributes;\r | |
38 | PCI_ROOT_BRIDGE_APERTURE Io;\r | |
39 | PCI_ROOT_BRIDGE_APERTURE Mem;\r | |
40 | PCI_ROOT_BRIDGE_APERTURE MemAbove4G;\r | |
c0a2591b | 41 | \r |
e33305ea HG |
42 | ZeroMem (&Io, sizeof (Io));\r |
43 | ZeroMem (&Mem, sizeof (Mem));\r | |
44 | ZeroMem (&MemAbove4G, sizeof (MemAbove4G));\r | |
45 | \r | |
c0a2591b | 46 | Attributes = EFI_PCI_ATTRIBUTE_IDE_PRIMARY_IO |\r |
ac0a286f MK |
47 | EFI_PCI_ATTRIBUTE_IDE_SECONDARY_IO |\r |
48 | EFI_PCI_ATTRIBUTE_ISA_IO_16 |\r | |
49 | EFI_PCI_ATTRIBUTE_ISA_MOTHERBOARD_IO |\r | |
50 | EFI_PCI_ATTRIBUTE_VGA_MEMORY |\r | |
51 | EFI_PCI_ATTRIBUTE_VGA_IO_16 |\r | |
52 | EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16;\r | |
c0a2591b RN |
53 | \r |
54 | AllocationAttributes = EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM;\r | |
55 | if (PcdGet64 (PcdPciMmio64Size) > 0) {\r | |
56 | AllocationAttributes |= EFI_PCI_HOST_BRIDGE_MEM64_DECODE;\r | |
ac0a286f MK |
57 | MemAbove4G.Base = PcdGet64 (PcdPciMmio64Base);\r |
58 | MemAbove4G.Limit = PcdGet64 (PcdPciMmio64Base) +\r | |
59 | PcdGet64 (PcdPciMmio64Size) - 1;\r | |
c0a2591b RN |
60 | } else {\r |
61 | CopyMem (&MemAbove4G, &mNonExistAperture, sizeof (mNonExistAperture));\r | |
62 | }\r | |
63 | \r | |
ac0a286f MK |
64 | Io.Base = PcdGet64 (PcdPciIoBase);\r |
65 | Io.Limit = PcdGet64 (PcdPciIoBase) + (PcdGet64 (PcdPciIoSize) - 1);\r | |
66 | Mem.Base = PcdGet64 (PcdPciMmio32Base);\r | |
c0a2591b | 67 | Mem.Limit = PcdGet64 (PcdPciMmio32Base) + (PcdGet64 (PcdPciMmio32Size) - 1);\r |
46e46eaf | 68 | \r |
4edba296 | 69 | return PciHostBridgeUtilityGetRootBridges (\r |
ac0a286f MK |
70 | Count,\r |
71 | Attributes,\r | |
72 | AllocationAttributes,\r | |
73 | FALSE,\r | |
74 | PcdGet16 (PcdOvmfHostBridgePciDevId) != INTEL_Q35_MCH_DEVICE_ID,\r | |
75 | 0,\r | |
76 | PCI_MAX_BUS,\r | |
77 | &Io,\r | |
78 | &Mem,\r | |
79 | &MemAbove4G,\r | |
80 | &mNonExistAperture,\r | |
81 | &mNonExistAperture\r | |
82 | );\r | |
d85861d7 LE |
83 | }\r |
84 | \r | |
85 | /**\r | |
86 | Free the root bridge instances array returned from\r | |
87 | PciHostBridgeGetRootBridges().\r | |
88 | \r | |
89 | @param The root bridge instances array.\r | |
90 | @param The count of the array.\r | |
91 | **/\r | |
92 | VOID\r | |
93 | EFIAPI\r | |
94 | PciHostBridgeFreeRootBridges (\r | |
ac0a286f MK |
95 | PCI_ROOT_BRIDGE *Bridges,\r |
96 | UINTN Count\r | |
d85861d7 LE |
97 | )\r |
98 | {\r | |
4edba296 | 99 | PciHostBridgeUtilityFreeRootBridges (Bridges, Count);\r |
d85861d7 LE |
100 | }\r |
101 | \r | |
102 | /**\r | |
103 | Inform the platform that the resource conflict happens.\r | |
104 | \r | |
105 | @param HostBridgeHandle Handle of the Host Bridge.\r | |
106 | @param Configuration Pointer to PCI I/O and PCI memory resource\r | |
107 | descriptors. The Configuration contains the resources\r | |
108 | for all the root bridges. The resource for each root\r | |
109 | bridge is terminated with END descriptor and an\r | |
110 | additional END is appended indicating the end of the\r | |
111 | entire resources. The resource descriptor field\r | |
112 | values follow the description in\r | |
113 | EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL\r | |
114 | .SubmitResources().\r | |
115 | **/\r | |
116 | VOID\r | |
117 | EFIAPI\r | |
118 | PciHostBridgeResourceConflict (\r | |
ac0a286f MK |
119 | EFI_HANDLE HostBridgeHandle,\r |
120 | VOID *Configuration\r | |
d85861d7 LE |
121 | )\r |
122 | {\r | |
7a6172f8 | 123 | PciHostBridgeUtilityResourceConflict (Configuration);\r |
d85861d7 | 124 | }\r |