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1 | /** @file\r |
2 | OVMF's instance of the PCI Host Bridge Library.\r | |
3 | \r | |
4 | Copyright (C) 2016-2021, Red Hat, Inc.\r | |
5 | Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>\r | |
6 | \r | |
7 | SPDX-License-Identifier: BSD-2-Clause-Patent\r | |
8 | \r | |
9 | **/\r | |
10 | #include <IndustryStandard/Pci.h> // PCI_MAX_BUS\r | |
11 | #include <IndustryStandard/Q35MchIch9.h> // INTEL_Q35_MCH_DEVIC...\r | |
12 | #include <Library/BaseMemoryLib.h> // ZeroMem()\r | |
13 | #include <Library/PcdLib.h> // PcdGet64()\r | |
14 | #include <Library/PciHostBridgeLib.h> // PCI_ROOT_BRIDGE_APE...\r | |
15 | #include <Library/PciHostBridgeUtilityLib.h> // PciHostBridgeUtilit...\r | |
16 | #include <Protocol/PciHostBridgeResourceAllocation.h> // EFI_PCI_HOST_BRIDGE...\r | |
17 | #include <Protocol/PciRootBridgeIo.h> // EFI_PCI_ATTRIBUTE_I...\r | |
18 | \r | |
19 | #include "PciHostBridge.h"\r | |
20 | \r | |
21 | STATIC PCI_ROOT_BRIDGE_APERTURE mNonExistAperture = { MAX_UINT64, 0 };\r | |
22 | \r | |
23 | \r | |
24 | /**\r | |
25 | Return all the root bridge instances in an array.\r | |
26 | \r | |
27 | @param Count Return the count of root bridge instances.\r | |
28 | \r | |
29 | @return All the root bridge instances in an array.\r | |
30 | The array should be passed into PciHostBridgeFreeRootBridges()\r | |
31 | when it's not used.\r | |
32 | **/\r | |
33 | PCI_ROOT_BRIDGE *\r | |
34 | EFIAPI\r | |
35 | PciHostBridgeGetRootBridges (\r | |
36 | UINTN *Count\r | |
37 | )\r | |
38 | {\r | |
39 | UINT64 Attributes;\r | |
40 | UINT64 AllocationAttributes;\r | |
41 | PCI_ROOT_BRIDGE_APERTURE Io;\r | |
42 | PCI_ROOT_BRIDGE_APERTURE Mem;\r | |
43 | PCI_ROOT_BRIDGE_APERTURE MemAbove4G;\r | |
44 | \r | |
45 | if (PcdGetBool (PcdPciDisableBusEnumeration)) {\r | |
46 | return ScanForRootBridges (Count);\r | |
47 | }\r | |
48 | \r | |
49 | ZeroMem (&Io, sizeof (Io));\r | |
50 | ZeroMem (&Mem, sizeof (Mem));\r | |
51 | ZeroMem (&MemAbove4G, sizeof (MemAbove4G));\r | |
52 | \r | |
53 | Attributes = EFI_PCI_ATTRIBUTE_IDE_PRIMARY_IO |\r | |
54 | EFI_PCI_ATTRIBUTE_IDE_SECONDARY_IO |\r | |
55 | EFI_PCI_ATTRIBUTE_ISA_IO_16 |\r | |
56 | EFI_PCI_ATTRIBUTE_ISA_MOTHERBOARD_IO |\r | |
57 | EFI_PCI_ATTRIBUTE_VGA_MEMORY |\r | |
58 | EFI_PCI_ATTRIBUTE_VGA_IO_16 |\r | |
59 | EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16;\r | |
60 | \r | |
61 | AllocationAttributes = EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM;\r | |
62 | if (PcdGet64 (PcdPciMmio64Size) > 0) {\r | |
63 | AllocationAttributes |= EFI_PCI_HOST_BRIDGE_MEM64_DECODE;\r | |
64 | MemAbove4G.Base = PcdGet64 (PcdPciMmio64Base);\r | |
65 | MemAbove4G.Limit = PcdGet64 (PcdPciMmio64Base) +\r | |
66 | PcdGet64 (PcdPciMmio64Size) - 1;\r | |
67 | } else {\r | |
68 | CopyMem (&MemAbove4G, &mNonExistAperture, sizeof (mNonExistAperture));\r | |
69 | }\r | |
70 | \r | |
71 | Io.Base = PcdGet64 (PcdPciIoBase);\r | |
72 | Io.Limit = PcdGet64 (PcdPciIoBase) + (PcdGet64 (PcdPciIoSize) - 1);\r | |
73 | Mem.Base = PcdGet64 (PcdPciMmio32Base);\r | |
74 | Mem.Limit = PcdGet64 (PcdPciMmio32Base) + (PcdGet64 (PcdPciMmio32Size) - 1);\r | |
75 | \r | |
76 | return PciHostBridgeUtilityGetRootBridges (\r | |
77 | Count,\r | |
78 | Attributes,\r | |
79 | AllocationAttributes,\r | |
80 | FALSE,\r | |
81 | PcdGet16 (PcdOvmfHostBridgePciDevId) != INTEL_Q35_MCH_DEVICE_ID,\r | |
82 | 0,\r | |
83 | PCI_MAX_BUS,\r | |
84 | &Io,\r | |
85 | &Mem,\r | |
86 | &MemAbove4G,\r | |
87 | &mNonExistAperture,\r | |
88 | &mNonExistAperture\r | |
89 | );\r | |
90 | }\r | |
91 | \r | |
92 | \r | |
93 | /**\r | |
94 | Free the root bridge instances array returned from\r | |
95 | PciHostBridgeGetRootBridges().\r | |
96 | \r | |
97 | @param The root bridge instances array.\r | |
98 | @param The count of the array.\r | |
99 | **/\r | |
100 | VOID\r | |
101 | EFIAPI\r | |
102 | PciHostBridgeFreeRootBridges (\r | |
103 | PCI_ROOT_BRIDGE *Bridges,\r | |
104 | UINTN Count\r | |
105 | )\r | |
106 | {\r | |
107 | PciHostBridgeUtilityFreeRootBridges (Bridges, Count);\r | |
108 | }\r | |
109 | \r | |
110 | \r | |
111 | /**\r | |
112 | Inform the platform that the resource conflict happens.\r | |
113 | \r | |
114 | @param HostBridgeHandle Handle of the Host Bridge.\r | |
115 | @param Configuration Pointer to PCI I/O and PCI memory resource\r | |
116 | descriptors. The Configuration contains the resources\r | |
117 | for all the root bridges. The resource for each root\r | |
118 | bridge is terminated with END descriptor and an\r | |
119 | additional END is appended indicating the end of the\r | |
120 | entire resources. The resource descriptor field\r | |
121 | values follow the description in\r | |
122 | EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL\r | |
123 | .SubmitResources().\r | |
124 | **/\r | |
125 | VOID\r | |
126 | EFIAPI\r | |
127 | PciHostBridgeResourceConflict (\r | |
128 | EFI_HANDLE HostBridgeHandle,\r | |
129 | VOID *Configuration\r | |
130 | )\r | |
131 | {\r | |
132 | PciHostBridgeUtilityResourceConflict (Configuration);\r | |
133 | }\r |