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8aba40b7 LE |
1 | /** @file\r |
2 | This driver implements EFI_PCI_HOT_PLUG_INIT_PROTOCOL, providing the PCI bus\r | |
3 | driver with resource padding information, for PCIe hotplug purposes.\r | |
4 | \r | |
5 | Copyright (C) 2016, Red Hat, Inc.\r | |
6 | \r | |
7 | This program and the accompanying materials are licensed and made available\r | |
8 | under the terms and conditions of the BSD License which accompanies this\r | |
9 | distribution. The full text of the license may be found at\r | |
10 | http://opensource.org/licenses/bsd-license.php\r | |
11 | \r | |
12 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT\r | |
13 | WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
14 | **/\r | |
15 | \r | |
16 | #include <IndustryStandard/Acpi10.h>\r | |
fe404947 | 17 | #include <IndustryStandard/QemuPciBridgeCapabilities.h>\r |
8aba40b7 | 18 | \r |
4776d5cb | 19 | #include <Library/BaseLib.h>\r |
a9803247 | 20 | #include <Library/BaseMemoryLib.h>\r |
8aba40b7 LE |
21 | #include <Library/DebugLib.h>\r |
22 | #include <Library/DevicePathLib.h>\r | |
23 | #include <Library/MemoryAllocationLib.h>\r | |
fe404947 | 24 | #include <Library/PciLib.h>\r |
8aba40b7 LE |
25 | #include <Library/UefiBootServicesTableLib.h>\r |
26 | \r | |
27 | #include <Protocol/PciHotPlugInit.h>\r | |
28 | #include <Protocol/PciRootBridgeIo.h>\r | |
29 | \r | |
30 | //\r | |
31 | // The protocol interface this driver produces.\r | |
32 | //\r | |
33 | // Refer to 12.6 "PCI Hot Plug PCI Initialization Protocol" in the Platform\r | |
34 | // Init 1.4a Spec, Volume 5.\r | |
35 | //\r | |
36 | STATIC EFI_PCI_HOT_PLUG_INIT_PROTOCOL mPciHotPlugInit;\r | |
37 | \r | |
38 | \r | |
39 | //\r | |
40 | // Resource padding template for the GetResourcePadding() protocol member\r | |
41 | // function.\r | |
42 | //\r | |
43 | // Refer to Table 8 "ACPI 2.0 & 3.0 QWORD Address Space Descriptor Usage" in\r | |
44 | // the Platform Init 1.4a Spec, Volume 5.\r | |
45 | //\r | |
46 | // This structure is interpreted by the ApplyResourcePadding() function in the\r | |
47 | // edk2 PCI Bus UEFI_DRIVER.\r | |
48 | //\r | |
a9803247 LE |
49 | // We can request padding for at most four resource types, each of which is\r |
50 | // optional, independently of the others:\r | |
51 | // (a) bus numbers,\r | |
52 | // (b) IO space,\r | |
53 | // (c) non-prefetchable MMIO space (32-bit only),\r | |
54 | // (d) prefetchable MMIO space (either 32-bit or 64-bit, never both).\r | |
55 | //\r | |
8aba40b7 LE |
56 | #pragma pack (1)\r |
57 | typedef struct {\r | |
a9803247 | 58 | EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR Padding[4];\r |
8aba40b7 LE |
59 | EFI_ACPI_END_TAG_DESCRIPTOR EndDesc;\r |
60 | } RESOURCE_PADDING;\r | |
61 | #pragma pack ()\r | |
62 | \r | |
a9803247 LE |
63 | \r |
64 | /**\r | |
65 | Initialize a RESOURCE_PADDING object.\r | |
66 | \r | |
67 | @param[out] ResourcePadding The caller-allocated RESOURCE_PADDING object to\r | |
68 | initialize.\r | |
69 | **/\r | |
70 | STATIC\r | |
71 | VOID\r | |
72 | InitializeResourcePadding (\r | |
73 | OUT RESOURCE_PADDING *ResourcePadding\r | |
74 | )\r | |
75 | {\r | |
76 | UINTN Index;\r | |
77 | \r | |
78 | ZeroMem (ResourcePadding, sizeof *ResourcePadding);\r | |
8aba40b7 LE |
79 | \r |
80 | //\r | |
a9803247 | 81 | // Fill in the Padding fields that don't vary across resource types.\r |
8aba40b7 | 82 | //\r |
a9803247 LE |
83 | for (Index = 0; Index < ARRAY_SIZE (ResourcePadding->Padding); ++Index) {\r |
84 | EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptor;\r | |
85 | \r | |
86 | Descriptor = ResourcePadding->Padding + Index;\r | |
87 | Descriptor->Desc = ACPI_ADDRESS_SPACE_DESCRIPTOR;\r | |
88 | Descriptor->Len = (UINT16)(\r | |
89 | sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) -\r | |
90 | OFFSET_OF (\r | |
91 | EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR,\r | |
92 | ResType\r | |
93 | )\r | |
94 | );\r | |
95 | }\r | |
8aba40b7 LE |
96 | \r |
97 | //\r | |
a9803247 | 98 | // Fill in the End Tag.\r |
8aba40b7 | 99 | //\r |
a9803247 LE |
100 | ResourcePadding->EndDesc.Desc = ACPI_END_TAG_DESCRIPTOR;\r |
101 | }\r | |
8aba40b7 LE |
102 | \r |
103 | \r | |
4776d5cb LE |
104 | /**\r |
105 | Set up a descriptor entry for reserving IO space.\r | |
106 | \r | |
107 | @param[in,out] Descriptor The descriptor to configure. The caller shall have\r | |
108 | initialized Descriptor earlier, with\r | |
109 | InitializeResourcePadding().\r | |
110 | \r | |
111 | @param[in] SizeExponent The size and natural alignment of the reservation\r | |
112 | are determined by raising two to this power.\r | |
113 | **/\r | |
114 | STATIC\r | |
115 | VOID\r | |
116 | SetIoPadding (\r | |
117 | IN OUT EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptor,\r | |
118 | IN UINTN SizeExponent\r | |
119 | )\r | |
120 | {\r | |
121 | Descriptor->ResType = ACPI_ADDRESS_SPACE_TYPE_IO;\r | |
122 | Descriptor->AddrLen = LShiftU64 (1, SizeExponent);\r | |
123 | Descriptor->AddrRangeMax = Descriptor->AddrLen - 1;\r | |
124 | }\r | |
125 | \r | |
126 | \r | |
127 | /**\r | |
128 | Set up a descriptor entry for reserving MMIO space.\r | |
129 | \r | |
130 | @param[in,out] Descriptor The descriptor to configure. The caller shall\r | |
131 | have initialized Descriptor earlier, with\r | |
132 | InitializeResourcePadding().\r | |
133 | \r | |
134 | @param[in] Prefetchable TRUE if the descriptor should reserve\r | |
135 | prefetchable MMIO space. Pass FALSE for\r | |
136 | reserving non-prefetchable MMIO space.\r | |
137 | \r | |
138 | @param[in] ThirtyTwoBitOnly TRUE if the reservation should be limited to\r | |
139 | 32-bit address space. FALSE if the reservation\r | |
140 | can be satisfied from 64-bit address space.\r | |
141 | ThirtyTwoBitOnly is ignored if Prefetchable is\r | |
142 | FALSE; in that case ThirtyTwoBitOnly is always\r | |
143 | considered TRUE.\r | |
144 | \r | |
145 | @param[in] SizeExponent The size and natural alignment of the\r | |
146 | reservation are determined by raising two to\r | |
147 | this power.\r | |
148 | **/\r | |
149 | STATIC\r | |
150 | VOID\r | |
151 | SetMmioPadding (\r | |
152 | IN OUT EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptor,\r | |
153 | IN BOOLEAN Prefetchable,\r | |
154 | IN BOOLEAN ThirtyTwoBitOnly,\r | |
155 | IN UINTN SizeExponent\r | |
156 | )\r | |
157 | {\r | |
158 | Descriptor->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;\r | |
159 | if (Prefetchable) {\r | |
160 | Descriptor->SpecificFlag =\r | |
161 | EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE;\r | |
162 | Descriptor->AddrSpaceGranularity = ThirtyTwoBitOnly ? 32 : 64;\r | |
163 | } else {\r | |
164 | Descriptor->SpecificFlag =\r | |
165 | EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_NON_CACHEABLE;\r | |
166 | Descriptor->AddrSpaceGranularity = 32;\r | |
167 | }\r | |
168 | Descriptor->AddrLen = LShiftU64 (1, SizeExponent);\r | |
169 | Descriptor->AddrRangeMax = Descriptor->AddrLen - 1;\r | |
170 | }\r | |
171 | \r | |
172 | \r | |
173 | /**\r | |
174 | Round up a positive 32-bit value to the next whole power of two, and return\r | |
175 | the bit position of the highest bit set in the result. Equivalent to\r | |
176 | ceil(log2(x)).\r | |
177 | \r | |
178 | @param[in] Operand The 32-bit operand to evaluate.\r | |
179 | \r | |
180 | @retval -1 Operand is zero.\r | |
181 | \r | |
182 | @retval -1 Operand is positive, not a whole power of two, and rounding it\r | |
183 | up to the next power of two does not fit into 32 bits.\r | |
184 | \r | |
185 | @retval 0..31 Otherwise, return ceil(log2(Value)).\r | |
186 | **/\r | |
187 | STATIC\r | |
188 | INTN\r | |
189 | HighBitSetRoundUp32 (\r | |
190 | IN UINT32 Operand\r | |
191 | )\r | |
192 | {\r | |
193 | INTN HighBit;\r | |
194 | \r | |
195 | HighBit = HighBitSet32 (Operand);\r | |
196 | if (HighBit == -1) {\r | |
197 | //\r | |
198 | // Operand is zero.\r | |
199 | //\r | |
200 | return HighBit;\r | |
201 | }\r | |
202 | if ((Operand & (Operand - 1)) != 0) {\r | |
203 | //\r | |
204 | // Operand is not a whole power of two.\r | |
205 | //\r | |
206 | ++HighBit;\r | |
207 | }\r | |
208 | return (HighBit < 32) ? HighBit : -1;\r | |
209 | }\r | |
210 | \r | |
211 | \r | |
212 | /**\r | |
213 | Round up a positive 64-bit value to the next whole power of two, and return\r | |
214 | the bit position of the highest bit set in the result. Equivalent to\r | |
215 | ceil(log2(x)).\r | |
216 | \r | |
217 | @param[in] Operand The 64-bit operand to evaluate.\r | |
218 | \r | |
219 | @retval -1 Operand is zero.\r | |
220 | \r | |
221 | @retval -1 Operand is positive, not a whole power of two, and rounding it\r | |
222 | up to the next power of two does not fit into 64 bits.\r | |
223 | \r | |
224 | @retval 0..63 Otherwise, return ceil(log2(Value)).\r | |
225 | **/\r | |
226 | STATIC\r | |
227 | INTN\r | |
228 | HighBitSetRoundUp64 (\r | |
229 | IN UINT64 Operand\r | |
230 | )\r | |
231 | {\r | |
232 | INTN HighBit;\r | |
233 | \r | |
234 | HighBit = HighBitSet64 (Operand);\r | |
235 | if (HighBit == -1) {\r | |
236 | //\r | |
237 | // Operand is zero.\r | |
238 | //\r | |
239 | return HighBit;\r | |
240 | }\r | |
241 | if ((Operand & (Operand - 1)) != 0) {\r | |
242 | //\r | |
243 | // Operand is not a whole power of two.\r | |
244 | //\r | |
245 | ++HighBit;\r | |
246 | }\r | |
247 | return (HighBit < 64) ? HighBit : -1;\r | |
248 | }\r | |
249 | \r | |
250 | \r | |
fe404947 LE |
251 | /**\r |
252 | Read a slice from conventional PCI config space at the given offset, then\r | |
253 | advance the offset.\r | |
254 | \r | |
255 | @param[in] PciAddress The address of the PCI Device -- Bus, Device, Function\r | |
256 | -- in UEFI (not PciLib) encoding.\r | |
257 | \r | |
258 | @param[in,out] Offset On input, the offset in conventional PCI config space\r | |
259 | to start reading from. On output, the offset of the\r | |
260 | first byte that was not read.\r | |
261 | \r | |
262 | @param[in] Size The number of bytes to read.\r | |
263 | \r | |
264 | @param[out] Buffer On output, the bytes read from PCI config space are\r | |
265 | stored in this object.\r | |
266 | **/\r | |
267 | STATIC\r | |
268 | VOID\r | |
269 | ReadConfigSpace (\r | |
270 | IN CONST EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS *PciAddress,\r | |
271 | IN OUT UINT8 *Offset,\r | |
272 | IN UINT8 Size,\r | |
273 | OUT VOID *Buffer\r | |
274 | )\r | |
275 | {\r | |
276 | PciReadBuffer (\r | |
277 | PCI_LIB_ADDRESS (\r | |
278 | PciAddress->Bus,\r | |
279 | PciAddress->Device,\r | |
280 | PciAddress->Function,\r | |
281 | *Offset\r | |
282 | ),\r | |
283 | Size,\r | |
284 | Buffer\r | |
285 | );\r | |
286 | *Offset += Size;\r | |
287 | }\r | |
288 | \r | |
289 | \r | |
290 | /**\r | |
291 | Convenience wrapper macro for ReadConfigSpace().\r | |
292 | \r | |
293 | Given the following conditions:\r | |
294 | \r | |
295 | - HeaderField is the first field in the structure pointed-to by Struct,\r | |
296 | \r | |
297 | - Struct->HeaderField has been populated from the conventional PCI config\r | |
298 | space of the PCI device identified by PciAddress,\r | |
299 | \r | |
300 | - *Offset points one past HeaderField in the conventional PCI config space of\r | |
301 | the PCI device identified by PciAddress,\r | |
302 | \r | |
303 | populate the rest of *Struct from conventional PCI config space, starting at\r | |
304 | *Offset. Finally, increment *Offset so that it point one past *Struct.\r | |
305 | \r | |
306 | @param[in] PciAddress The address of the PCI Device -- Bus, Device, Function\r | |
307 | -- in UEFI (not PciLib) encoding. Type: pointer to\r | |
308 | CONST EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS.\r | |
309 | \r | |
310 | @param[in,out] Offset On input, the offset in conventional PCI config space\r | |
311 | to start reading from; one past Struct->HeaderField.\r | |
312 | On output, the offset of the first byte that was not\r | |
313 | read; one past *Struct. Type: pointer to UINT8.\r | |
314 | \r | |
315 | @param[out] Struct The structure to complete. Type: pointer to structure\r | |
316 | object.\r | |
317 | \r | |
318 | @param[in] HeaderField The name of the first field in *Struct, after which\r | |
319 | *Struct should be populated. Type: structure member\r | |
320 | identifier.\r | |
321 | **/\r | |
322 | #define COMPLETE_CONFIG_SPACE_STRUCT(PciAddress, Offset, Struct, HeaderField) \\r | |
323 | ReadConfigSpace ( \\r | |
324 | (PciAddress), \\r | |
325 | (Offset), \\r | |
326 | (UINT8)(sizeof *(Struct) - sizeof ((Struct)->HeaderField)), \\r | |
327 | &((Struct)->HeaderField) + 1 \\r | |
328 | )\r | |
329 | \r | |
330 | \r | |
331 | /**\r | |
332 | Look up the QEMU-specific Resource Reservation capability in the conventional\r | |
333 | config space of a Hotplug Controller (that is, PCI Bridge).\r | |
334 | \r | |
335 | This function performs as few config space reads as possible.\r | |
336 | \r | |
337 | @param[in] HpcPciAddress The address of the PCI Bridge -- Bus, Device,\r | |
338 | Function -- in UEFI (not PciLib) encoding.\r | |
339 | \r | |
340 | @param[out] ReservationHint The caller-allocated capability structure to\r | |
341 | populate from the PCI Bridge's config space.\r | |
342 | \r | |
343 | @retval EFI_SUCCESS The capability has been found, ReservationHint has\r | |
344 | been populated.\r | |
345 | \r | |
346 | @retval EFI_NOT_FOUND The capability is missing. The contents of\r | |
347 | ReservationHint are now indeterminate.\r | |
348 | **/\r | |
349 | STATIC\r | |
350 | EFI_STATUS\r | |
351 | QueryReservationHint (\r | |
352 | IN CONST EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS *HpcPciAddress,\r | |
353 | OUT QEMU_PCI_BRIDGE_CAPABILITY_RESOURCE_RESERVATION *ReservationHint\r | |
354 | )\r | |
355 | {\r | |
356 | UINT16 PciVendorId;\r | |
357 | UINT16 PciStatus;\r | |
358 | UINT8 PciCapPtr;\r | |
359 | UINT8 Offset;\r | |
360 | \r | |
361 | //\r | |
362 | // Check the vendor identifier.\r | |
363 | //\r | |
364 | PciVendorId = PciRead16 (\r | |
365 | PCI_LIB_ADDRESS (\r | |
366 | HpcPciAddress->Bus,\r | |
367 | HpcPciAddress->Device,\r | |
368 | HpcPciAddress->Function,\r | |
369 | PCI_VENDOR_ID_OFFSET\r | |
370 | )\r | |
371 | );\r | |
372 | if (PciVendorId != QEMU_PCI_BRIDGE_VENDOR_ID_REDHAT) {\r | |
373 | return EFI_NOT_FOUND;\r | |
374 | }\r | |
375 | \r | |
376 | //\r | |
377 | // Check the Capabilities List bit in the PCI Status Register.\r | |
378 | //\r | |
379 | PciStatus = PciRead16 (\r | |
380 | PCI_LIB_ADDRESS (\r | |
381 | HpcPciAddress->Bus,\r | |
382 | HpcPciAddress->Device,\r | |
383 | HpcPciAddress->Function,\r | |
384 | PCI_PRIMARY_STATUS_OFFSET\r | |
385 | )\r | |
386 | );\r | |
387 | if ((PciStatus & EFI_PCI_STATUS_CAPABILITY) == 0) {\r | |
388 | return EFI_NOT_FOUND;\r | |
389 | }\r | |
390 | \r | |
391 | //\r | |
392 | // Fetch the start of the Capabilities List.\r | |
393 | //\r | |
394 | PciCapPtr = PciRead8 (\r | |
395 | PCI_LIB_ADDRESS (\r | |
396 | HpcPciAddress->Bus,\r | |
397 | HpcPciAddress->Device,\r | |
398 | HpcPciAddress->Function,\r | |
399 | PCI_CAPBILITY_POINTER_OFFSET\r | |
400 | )\r | |
401 | );\r | |
402 | \r | |
403 | //\r | |
404 | // Scan the Capabilities List until we find the terminator element, or the\r | |
405 | // Resource Reservation capability.\r | |
406 | //\r | |
407 | for (Offset = PciCapPtr & 0xFC;\r | |
408 | Offset > 0;\r | |
409 | Offset = ReservationHint->BridgeHdr.VendorHdr.Hdr.NextItemPtr & 0xFC) {\r | |
410 | BOOLEAN EnoughRoom;\r | |
411 | \r | |
412 | //\r | |
413 | // Check if the Resource Reservation capability would fit into config space\r | |
414 | // at this offset.\r | |
415 | //\r | |
416 | EnoughRoom = (BOOLEAN)(\r | |
417 | Offset <= PCI_MAX_CONFIG_OFFSET - sizeof *ReservationHint\r | |
418 | );\r | |
419 | \r | |
420 | //\r | |
421 | // Read the standard capability header so we can check the capability ID\r | |
422 | // (if necessary) and advance to the next capability.\r | |
423 | //\r | |
424 | ReadConfigSpace (\r | |
425 | HpcPciAddress,\r | |
426 | &Offset,\r | |
427 | (UINT8)sizeof ReservationHint->BridgeHdr.VendorHdr.Hdr,\r | |
428 | &ReservationHint->BridgeHdr.VendorHdr.Hdr\r | |
429 | );\r | |
430 | if (!EnoughRoom ||\r | |
431 | (ReservationHint->BridgeHdr.VendorHdr.Hdr.CapabilityID !=\r | |
432 | EFI_PCI_CAPABILITY_ID_VENDOR)) {\r | |
433 | continue;\r | |
434 | }\r | |
435 | \r | |
436 | //\r | |
437 | // Read the rest of the vendor capability header so we can check the\r | |
438 | // capability length.\r | |
439 | //\r | |
440 | COMPLETE_CONFIG_SPACE_STRUCT (\r | |
441 | HpcPciAddress,\r | |
442 | &Offset,\r | |
443 | &ReservationHint->BridgeHdr.VendorHdr,\r | |
444 | Hdr\r | |
445 | );\r | |
446 | if (ReservationHint->BridgeHdr.VendorHdr.Length !=\r | |
447 | sizeof *ReservationHint) {\r | |
448 | continue;\r | |
449 | }\r | |
450 | \r | |
451 | //\r | |
452 | // Read the rest of the QEMU bridge capability header so we can check the\r | |
453 | // capability type.\r | |
454 | //\r | |
455 | COMPLETE_CONFIG_SPACE_STRUCT (\r | |
456 | HpcPciAddress,\r | |
457 | &Offset,\r | |
458 | &ReservationHint->BridgeHdr,\r | |
459 | VendorHdr\r | |
460 | );\r | |
461 | if (ReservationHint->BridgeHdr.Type !=\r | |
462 | QEMU_PCI_BRIDGE_CAPABILITY_TYPE_RESOURCE_RESERVATION) {\r | |
463 | continue;\r | |
464 | }\r | |
465 | \r | |
466 | //\r | |
467 | // Read the body of the reservation hint.\r | |
468 | //\r | |
469 | COMPLETE_CONFIG_SPACE_STRUCT (\r | |
470 | HpcPciAddress,\r | |
471 | &Offset,\r | |
472 | ReservationHint,\r | |
473 | BridgeHdr\r | |
474 | );\r | |
475 | return EFI_SUCCESS;\r | |
476 | }\r | |
477 | \r | |
478 | return EFI_NOT_FOUND;\r | |
479 | }\r | |
480 | \r | |
481 | \r | |
8aba40b7 LE |
482 | /**\r |
483 | Returns a list of root Hot Plug Controllers (HPCs) that require\r | |
484 | initialization during the boot process.\r | |
485 | \r | |
486 | This procedure returns a list of root HPCs. The PCI bus driver must\r | |
487 | initialize these controllers during the boot process. The PCI bus driver may\r | |
488 | or may not be able to detect these HPCs. If the platform includes a\r | |
489 | PCI-to-CardBus bridge, it can be included in this list if it requires\r | |
490 | initialization. The HpcList must be self consistent. An HPC cannot control\r | |
491 | any of its parent buses. Only one HPC can control a PCI bus. Because this\r | |
492 | list includes only root HPCs, no HPC in the list can be a child of another\r | |
493 | HPC. This policy must be enforced by the EFI_PCI_HOT_PLUG_INIT_PROTOCOL.\r | |
494 | The PCI bus driver may not check for such invalid conditions. The callee\r | |
495 | allocates the buffer HpcList\r | |
496 | \r | |
497 | @param[in] This Pointer to the EFI_PCI_HOT_PLUG_INIT_PROTOCOL\r | |
498 | instance.\r | |
499 | @param[out] HpcCount The number of root HPCs that were returned.\r | |
500 | @param[out] HpcList The list of root HPCs. HpcCount defines the number of\r | |
501 | elements in this list.\r | |
502 | \r | |
503 | @retval EFI_SUCCESS HpcList was returned.\r | |
504 | @retval EFI_OUT_OF_RESOURCES HpcList was not returned due to insufficient\r | |
505 | resources.\r | |
506 | @retval EFI_INVALID_PARAMETER HpcCount is NULL or HpcList is NULL.\r | |
507 | **/\r | |
508 | STATIC\r | |
509 | EFI_STATUS\r | |
510 | EFIAPI\r | |
511 | GetRootHpcList (\r | |
512 | IN EFI_PCI_HOT_PLUG_INIT_PROTOCOL *This,\r | |
513 | OUT UINTN *HpcCount,\r | |
514 | OUT EFI_HPC_LOCATION **HpcList\r | |
515 | )\r | |
516 | {\r | |
517 | if (HpcCount == NULL || HpcList == NULL) {\r | |
518 | return EFI_INVALID_PARAMETER;\r | |
519 | }\r | |
520 | \r | |
521 | //\r | |
522 | // There are no top-level (i.e., un-enumerable) hot-plug controllers in QEMU\r | |
523 | // that would require special initialization.\r | |
524 | //\r | |
525 | *HpcCount = 0;\r | |
526 | *HpcList = NULL;\r | |
527 | return EFI_SUCCESS;\r | |
528 | }\r | |
529 | \r | |
530 | \r | |
531 | /**\r | |
532 | Initializes one root Hot Plug Controller (HPC). This process may causes\r | |
533 | initialization of its subordinate buses.\r | |
534 | \r | |
535 | This function initializes the specified HPC. At the end of initialization,\r | |
536 | the hot-plug slots or sockets (controlled by this HPC) are powered and are\r | |
537 | connected to the bus. All the necessary registers in the HPC are set up. For\r | |
538 | a Standard (PCI) Hot Plug Controller (SHPC), the registers that must be set\r | |
539 | up are defined in the PCI Standard Hot Plug Controller and Subsystem\r | |
540 | Specification.\r | |
541 | \r | |
542 | @param[in] This Pointer to the EFI_PCI_HOT_PLUG_INIT_PROTOCOL\r | |
543 | instance.\r | |
544 | @param[in] HpcDevicePath The device path to the HPC that is being\r | |
545 | initialized.\r | |
546 | @param[in] HpcPciAddress The address of the HPC function on the PCI bus.\r | |
547 | @param[in] Event The event that should be signaled when the HPC\r | |
548 | initialization is complete. Set to NULL if the\r | |
549 | caller wants to wait until the entire\r | |
550 | initialization process is complete.\r | |
551 | @param[out] HpcState The state of the HPC hardware. The state is\r | |
552 | EFI_HPC_STATE_INITIALIZED or\r | |
553 | EFI_HPC_STATE_ENABLED.\r | |
554 | \r | |
555 | @retval EFI_SUCCESS If Event is NULL, the specific HPC was\r | |
556 | successfully initialized. If Event is not\r | |
557 | NULL, Event will be signaled at a later time\r | |
558 | when initialization is complete.\r | |
559 | @retval EFI_UNSUPPORTED This instance of\r | |
560 | EFI_PCI_HOT_PLUG_INIT_PROTOCOL does not\r | |
561 | support the specified HPC.\r | |
562 | @retval EFI_OUT_OF_RESOURCES Initialization failed due to insufficient\r | |
563 | resources.\r | |
564 | @retval EFI_INVALID_PARAMETER HpcState is NULL.\r | |
565 | **/\r | |
566 | STATIC\r | |
567 | EFI_STATUS\r | |
568 | EFIAPI\r | |
569 | InitializeRootHpc (\r | |
570 | IN EFI_PCI_HOT_PLUG_INIT_PROTOCOL *This,\r | |
571 | IN EFI_DEVICE_PATH_PROTOCOL *HpcDevicePath,\r | |
572 | IN UINT64 HpcPciAddress,\r | |
573 | IN EFI_EVENT Event, OPTIONAL\r | |
574 | OUT EFI_HPC_STATE *HpcState\r | |
575 | )\r | |
576 | {\r | |
577 | //\r | |
578 | // This function should never be called, due to the information returned by\r | |
579 | // GetRootHpcList().\r | |
580 | //\r | |
581 | ASSERT (FALSE);\r | |
582 | \r | |
583 | if (HpcState == NULL) {\r | |
584 | return EFI_INVALID_PARAMETER;\r | |
585 | }\r | |
586 | return EFI_UNSUPPORTED;\r | |
587 | }\r | |
588 | \r | |
589 | \r | |
590 | /**\r | |
591 | Returns the resource padding that is required by the PCI bus that is\r | |
592 | controlled by the specified Hot Plug Controller (HPC).\r | |
593 | \r | |
594 | This function returns the resource padding that is required by the PCI bus\r | |
595 | that is controlled by the specified HPC. This member function is called for\r | |
596 | all the root HPCs and nonroot HPCs that are detected by the PCI bus\r | |
597 | enumerator. This function will be called before PCI resource allocation is\r | |
598 | completed. This function must be called after all the root HPCs, with the\r | |
599 | possible exception of a PCI-to-CardBus bridge, have completed\r | |
600 | initialization.\r | |
601 | \r | |
602 | @param[in] This Pointer to the EFI_PCI_HOT_PLUG_INIT_PROTOCOL\r | |
603 | instance.\r | |
604 | @param[in] HpcDevicePath The device path to the HPC.\r | |
605 | @param[in] HpcPciAddress The address of the HPC function on the PCI bus.\r | |
606 | @param[in] HpcState The state of the HPC hardware.\r | |
607 | @param[out] Padding The amount of resource padding that is required\r | |
608 | by the PCI bus under the control of the specified\r | |
609 | HPC.\r | |
610 | @param[out] Attributes Describes how padding is accounted for. The\r | |
611 | padding is returned in the form of ACPI 2.0\r | |
612 | resource descriptors.\r | |
613 | \r | |
614 | @retval EFI_SUCCESS The resource padding was successfully\r | |
615 | returned.\r | |
616 | @retval EFI_UNSUPPORTED This instance of the\r | |
617 | EFI_PCI_HOT_PLUG_INIT_PROTOCOL does not\r | |
618 | support the specified HPC.\r | |
619 | @retval EFI_NOT_READY This function was called before HPC\r | |
620 | initialization is complete.\r | |
621 | @retval EFI_INVALID_PARAMETER HpcState or Padding or Attributes is NULL.\r | |
622 | @retval EFI_OUT_OF_RESOURCES ACPI 2.0 resource descriptors for Padding\r | |
623 | cannot be allocated due to insufficient\r | |
624 | resources.\r | |
625 | **/\r | |
626 | STATIC\r | |
627 | EFI_STATUS\r | |
628 | EFIAPI\r | |
629 | GetResourcePadding (\r | |
630 | IN EFI_PCI_HOT_PLUG_INIT_PROTOCOL *This,\r | |
631 | IN EFI_DEVICE_PATH_PROTOCOL *HpcDevicePath,\r | |
632 | IN UINT64 HpcPciAddress,\r | |
633 | OUT EFI_HPC_STATE *HpcState,\r | |
634 | OUT VOID **Padding,\r | |
635 | OUT EFI_HPC_PADDING_ATTRIBUTES *Attributes\r | |
636 | )\r | |
637 | {\r | |
fe404947 | 638 | EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS *Address;\r |
a9803247 LE |
639 | BOOLEAN DefaultIo;\r |
640 | BOOLEAN DefaultMmio;\r | |
641 | RESOURCE_PADDING ReservationRequest;\r | |
642 | EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *FirstResource;\r | |
fe404947 LE |
643 | EFI_STATUS ReservationHintStatus;\r |
644 | QEMU_PCI_BRIDGE_CAPABILITY_RESOURCE_RESERVATION ReservationHint;\r | |
645 | \r | |
646 | Address = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS *)&HpcPciAddress;\r | |
a9803247 | 647 | \r |
8aba40b7 | 648 | DEBUG_CODE (\r |
8aba40b7 LE |
649 | CHAR16 *DevicePathString;\r |
650 | \r | |
8aba40b7 LE |
651 | DevicePathString = ConvertDevicePathToText (HpcDevicePath, FALSE, FALSE);\r |
652 | \r | |
653 | DEBUG ((EFI_D_VERBOSE, "%a: Address=%02x:%02x.%x DevicePath=%s\n",\r | |
654 | __FUNCTION__, Address->Bus, Address->Device, Address->Function,\r | |
655 | (DevicePathString == NULL) ? L"<unavailable>" : DevicePathString));\r | |
656 | \r | |
657 | if (DevicePathString != NULL) {\r | |
658 | FreePool (DevicePathString);\r | |
659 | }\r | |
660 | );\r | |
661 | \r | |
662 | if (HpcState == NULL || Padding == NULL || Attributes == NULL) {\r | |
663 | return EFI_INVALID_PARAMETER;\r | |
664 | }\r | |
665 | \r | |
a9803247 LE |
666 | DefaultIo = TRUE;\r |
667 | DefaultMmio = TRUE;\r | |
668 | \r | |
669 | //\r | |
670 | // Init ReservationRequest, and point FirstResource one past the last\r | |
671 | // descriptor entry. We're going to build the entries backwards from\r | |
672 | // ReservationRequest.EndDesc.\r | |
673 | //\r | |
674 | InitializeResourcePadding (&ReservationRequest);\r | |
675 | FirstResource = ReservationRequest.Padding +\r | |
676 | ARRAY_SIZE (ReservationRequest.Padding);\r | |
677 | \r | |
678 | //\r | |
fe404947 | 679 | // Try to get the QEMU-specific Resource Reservation capability.\r |
a9803247 | 680 | //\r |
fe404947 LE |
681 | ReservationHintStatus = QueryReservationHint (Address, &ReservationHint);\r |
682 | if (!EFI_ERROR (ReservationHintStatus)) {\r | |
683 | INTN HighBit;\r | |
684 | \r | |
685 | DEBUG ((\r | |
686 | DEBUG_VERBOSE,\r | |
687 | "%a: BusNumbers=0x%x Io=0x%Lx NonPrefetchable32BitMmio=0x%x\n"\r | |
688 | "%a: Prefetchable32BitMmio=0x%x Prefetchable64BitMmio=0x%Lx\n",\r | |
689 | __FUNCTION__,\r | |
690 | ReservationHint.BusNumbers,\r | |
691 | ReservationHint.Io,\r | |
692 | ReservationHint.NonPrefetchable32BitMmio,\r | |
693 | __FUNCTION__,\r | |
694 | ReservationHint.Prefetchable32BitMmio,\r | |
695 | ReservationHint.Prefetchable64BitMmio\r | |
696 | ));\r | |
697 | \r | |
698 | //\r | |
699 | // (a) Reserve bus numbers.\r | |
700 | //\r | |
701 | switch (ReservationHint.BusNumbers) {\r | |
702 | case 0:\r | |
703 | //\r | |
704 | // No reservation needed.\r | |
705 | //\r | |
706 | break;\r | |
707 | case MAX_UINT32:\r | |
708 | //\r | |
709 | // Firmware default (unspecified). Treat it as "no reservation needed".\r | |
710 | //\r | |
711 | break;\r | |
712 | default:\r | |
713 | //\r | |
714 | // Request the specified amount.\r | |
715 | //\r | |
716 | --FirstResource;\r | |
717 | FirstResource->ResType = ACPI_ADDRESS_SPACE_TYPE_BUS;\r | |
718 | FirstResource->AddrLen = ReservationHint.BusNumbers;\r | |
719 | break;\r | |
720 | }\r | |
721 | \r | |
722 | //\r | |
723 | // (b) Reserve IO space.\r | |
724 | //\r | |
725 | switch (ReservationHint.Io) {\r | |
726 | case 0:\r | |
727 | //\r | |
728 | // No reservation needed, disable our built-in.\r | |
729 | //\r | |
730 | DefaultIo = FALSE;\r | |
731 | break;\r | |
732 | case MAX_UINT64:\r | |
733 | //\r | |
734 | // Firmware default (unspecified). Stick with our built-in.\r | |
735 | //\r | |
736 | break;\r | |
737 | default:\r | |
738 | //\r | |
739 | // Round the specified amount up to the next power of two. If rounding is\r | |
740 | // successful, reserve the rounded value. Fall back to the default\r | |
741 | // otherwise.\r | |
742 | //\r | |
743 | HighBit = HighBitSetRoundUp64 (ReservationHint.Io);\r | |
744 | if (HighBit != -1) {\r | |
745 | SetIoPadding (--FirstResource, (UINTN)HighBit);\r | |
746 | DefaultIo = FALSE;\r | |
747 | }\r | |
748 | break;\r | |
749 | }\r | |
750 | \r | |
751 | //\r | |
752 | // (c) Reserve non-prefetchable MMIO space (32-bit only).\r | |
753 | //\r | |
754 | switch (ReservationHint.NonPrefetchable32BitMmio) {\r | |
755 | case 0:\r | |
756 | //\r | |
757 | // No reservation needed, disable our built-in.\r | |
758 | //\r | |
759 | DefaultMmio = FALSE;\r | |
760 | break;\r | |
761 | case MAX_UINT32:\r | |
762 | //\r | |
763 | // Firmware default (unspecified). Stick with our built-in.\r | |
764 | //\r | |
765 | break;\r | |
766 | default:\r | |
767 | //\r | |
768 | // Round the specified amount up to the next power of two. If rounding is\r | |
769 | // successful, reserve the rounded value. Fall back to the default\r | |
770 | // otherwise.\r | |
771 | //\r | |
772 | HighBit = HighBitSetRoundUp32 (ReservationHint.NonPrefetchable32BitMmio);\r | |
773 | if (HighBit != -1) {\r | |
774 | SetMmioPadding (--FirstResource, FALSE, TRUE, (UINTN)HighBit);\r | |
775 | DefaultMmio = FALSE;\r | |
776 | }\r | |
777 | break;\r | |
778 | }\r | |
779 | \r | |
780 | //\r | |
781 | // (d) Reserve prefetchable MMIO space (either 32-bit or 64-bit, never\r | |
782 | // both).\r | |
783 | //\r | |
784 | // For either space, we treat 0 as "no reservation needed", and the maximum\r | |
785 | // value as "firmware default". The latter is unspecified, and we interpret\r | |
786 | // it as the former.\r | |
787 | //\r | |
788 | // Otherwise, round the specified amount up to the next power of two. If\r | |
789 | // rounding is successful, reserve the rounded value. Do not reserve\r | |
790 | // prefetchable MMIO space otherwise.\r | |
791 | //\r | |
792 | if (ReservationHint.Prefetchable32BitMmio > 0 &&\r | |
793 | ReservationHint.Prefetchable32BitMmio < MAX_UINT32) {\r | |
794 | HighBit = HighBitSetRoundUp32 (ReservationHint.Prefetchable32BitMmio);\r | |
795 | if (HighBit != -1) {\r | |
796 | SetMmioPadding (--FirstResource, TRUE, TRUE, (UINTN)HighBit);\r | |
797 | }\r | |
798 | } else if (ReservationHint.Prefetchable64BitMmio > 0 &&\r | |
799 | ReservationHint.Prefetchable64BitMmio < MAX_UINT64) {\r | |
800 | HighBit = HighBitSetRoundUp64 (ReservationHint.Prefetchable64BitMmio);\r | |
801 | if (HighBit != -1) {\r | |
802 | SetMmioPadding (--FirstResource, TRUE, FALSE, (UINTN)HighBit);\r | |
803 | }\r | |
804 | }\r | |
805 | }\r | |
806 | \r | |
a9803247 LE |
807 | if (DefaultIo) {\r |
808 | //\r | |
809 | // Request defaults.\r | |
810 | //\r | |
4776d5cb | 811 | SetIoPadding (--FirstResource, (UINTN)HighBitSetRoundUp64 (512));\r |
a9803247 LE |
812 | }\r |
813 | \r | |
a9803247 LE |
814 | if (DefaultMmio) {\r |
815 | //\r | |
816 | // Request defaults.\r | |
817 | //\r | |
4776d5cb LE |
818 | SetMmioPadding (\r |
819 | --FirstResource,\r | |
820 | FALSE,\r | |
821 | TRUE,\r | |
822 | (UINTN)HighBitSetRoundUp32 (SIZE_2MB)\r | |
823 | );\r | |
a9803247 LE |
824 | }\r |
825 | \r | |
826 | //\r | |
827 | // Output a copy of ReservationRequest from the lowest-address populated\r | |
828 | // entry until the end of the structure (including\r | |
829 | // ReservationRequest.EndDesc). If no reservations are necessary, we'll only\r | |
830 | // output the End Tag.\r | |
831 | //\r | |
832 | *Padding = AllocateCopyPool (\r | |
833 | (UINT8 *)(&ReservationRequest + 1) - (UINT8 *)FirstResource,\r | |
834 | FirstResource\r | |
835 | );\r | |
8aba40b7 LE |
836 | if (*Padding == NULL) {\r |
837 | return EFI_OUT_OF_RESOURCES;\r | |
838 | }\r | |
839 | \r | |
840 | //\r | |
841 | // Resource padding is required.\r | |
842 | //\r | |
843 | *HpcState = EFI_HPC_STATE_INITIALIZED | EFI_HPC_STATE_ENABLED;\r | |
844 | \r | |
845 | //\r | |
846 | // The padding should be applied at PCI bus level, and considered by upstream\r | |
847 | // bridges, recursively.\r | |
848 | //\r | |
849 | *Attributes = EfiPaddingPciBus;\r | |
850 | return EFI_SUCCESS;\r | |
851 | }\r | |
852 | \r | |
853 | \r | |
854 | /**\r | |
855 | Entry point for this driver.\r | |
856 | \r | |
857 | @param[in] ImageHandle Image handle of this driver.\r | |
858 | @param[in] SystemTable Pointer to SystemTable.\r | |
859 | \r | |
860 | @retval EFI_SUCESS Driver has loaded successfully.\r | |
861 | @return Error codes from lower level functions.\r | |
862 | \r | |
863 | **/\r | |
864 | EFI_STATUS\r | |
865 | EFIAPI\r | |
866 | DriverInitialize (\r | |
867 | IN EFI_HANDLE ImageHandle,\r | |
868 | IN EFI_SYSTEM_TABLE *SystemTable\r | |
869 | )\r | |
870 | {\r | |
871 | EFI_STATUS Status;\r | |
872 | \r | |
873 | mPciHotPlugInit.GetRootHpcList = GetRootHpcList;\r | |
874 | mPciHotPlugInit.InitializeRootHpc = InitializeRootHpc;\r | |
875 | mPciHotPlugInit.GetResourcePadding = GetResourcePadding;\r | |
876 | Status = gBS->InstallMultipleProtocolInterfaces (&ImageHandle,\r | |
877 | &gEfiPciHotPlugInitProtocolGuid, &mPciHotPlugInit, NULL);\r | |
878 | return Status;\r | |
879 | }\r |