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49ba9447 | 1 | /**@file\r |
2 | Memory Detection for Virtual Machines.\r | |
3 | \r | |
035ce3b3 | 4 | Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>\r |
b26f0cf9 | 5 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
49ba9447 | 6 | \r |
7 | Module Name:\r | |
8 | \r | |
9 | MemDetect.c\r | |
10 | \r | |
11 | **/\r | |
12 | \r | |
13 | //\r | |
14 | // The package level header files this module uses\r | |
15 | //\r | |
1fceaddb | 16 | #include <IndustryStandard/E820.h>\r |
49edde15 | 17 | #include <IndustryStandard/I440FxPiix4.h>\r |
d5e06444 | 18 | #include <IndustryStandard/Q35MchIch9.h>\r |
49ba9447 | 19 | #include <PiPei.h>\r |
adec2bd5 | 20 | #include <Register/Intel/SmramSaveStateMap.h>\r |
49ba9447 | 21 | \r |
22 | //\r | |
23 | // The Library classes this module consumes\r | |
24 | //\r | |
d5e06444 | 25 | #include <Library/BaseLib.h>\r |
6a7cba79 | 26 | #include <Library/BaseMemoryLib.h>\r |
49ba9447 | 27 | #include <Library/DebugLib.h>\r |
28 | #include <Library/HobLib.h>\r | |
29 | #include <Library/IoLib.h>\r | |
c1c2669c | 30 | #include <Library/PcdLib.h>\r |
d5e06444 | 31 | #include <Library/PciLib.h>\r |
49ba9447 | 32 | #include <Library/PeimEntryPoint.h>\r |
33 | #include <Library/ResourcePublicationLib.h>\r | |
e8e5cd4a | 34 | #include <Library/MtrrLib.h>\r |
7e5b1b67 | 35 | #include <Library/QemuFwCfgLib.h>\r |
49ba9447 | 36 | \r |
37 | #include "Platform.h"\r | |
38 | #include "Cmos.h"\r | |
39 | \r | |
bc89fe48 LE |
40 | UINT8 mPhysMemAddressWidth;\r |
41 | \r | |
45d87081 LE |
42 | STATIC UINT32 mS3AcpiReservedMemoryBase;\r |
43 | STATIC UINT32 mS3AcpiReservedMemorySize;\r | |
44 | \r | |
23bfb5c0 LE |
45 | STATIC UINT16 mQ35TsegMbytes;\r |
46 | \r | |
73974f80 LE |
47 | BOOLEAN mQ35SmramAtDefaultSmbase;\r |
48 | \r | |
49edde15 LE |
49 | UINT32 mQemuUc32Base;\r |
50 | \r | |
23bfb5c0 LE |
51 | VOID\r |
52 | Q35TsegMbytesInitialization (\r | |
53 | VOID\r | |
54 | )\r | |
55 | {\r | |
d5e06444 LE |
56 | UINT16 ExtendedTsegMbytes;\r |
57 | RETURN_STATUS PcdStatus;\r | |
58 | \r | |
e0ed7a9b | 59 | ASSERT (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID);\r |
d5e06444 LE |
60 | \r |
61 | //\r | |
62 | // Check if QEMU offers an extended TSEG.\r | |
63 | //\r | |
64 | // This can be seen from writing MCH_EXT_TSEG_MB_QUERY to the MCH_EXT_TSEG_MB\r | |
65 | // register, and reading back the register.\r | |
66 | //\r | |
67 | // On a QEMU machine type that does not offer an extended TSEG, the initial\r | |
68 | // write overwrites whatever value a malicious guest OS may have placed in\r | |
69 | // the (unimplemented) register, before entering S3 or rebooting.\r | |
70 | // Subsequently, the read returns MCH_EXT_TSEG_MB_QUERY unchanged.\r | |
71 | //\r | |
72 | // On a QEMU machine type that offers an extended TSEG, the initial write\r | |
73 | // triggers an update to the register. Subsequently, the value read back\r | |
74 | // (which is guaranteed to differ from MCH_EXT_TSEG_MB_QUERY) tells us the\r | |
75 | // number of megabytes.\r | |
76 | //\r | |
77 | PciWrite16 (DRAMC_REGISTER_Q35 (MCH_EXT_TSEG_MB), MCH_EXT_TSEG_MB_QUERY);\r | |
78 | ExtendedTsegMbytes = PciRead16 (DRAMC_REGISTER_Q35 (MCH_EXT_TSEG_MB));\r | |
79 | if (ExtendedTsegMbytes == MCH_EXT_TSEG_MB_QUERY) {\r | |
80 | mQ35TsegMbytes = PcdGet16 (PcdQ35TsegMbytes);\r | |
81 | return;\r | |
82 | }\r | |
83 | \r | |
84 | DEBUG ((\r | |
85 | DEBUG_INFO,\r | |
86 | "%a: QEMU offers an extended TSEG (%d MB)\n",\r | |
87 | __FUNCTION__,\r | |
88 | ExtendedTsegMbytes\r | |
89 | ));\r | |
90 | PcdStatus = PcdSet16S (PcdQ35TsegMbytes, ExtendedTsegMbytes);\r | |
91 | ASSERT_RETURN_ERROR (PcdStatus);\r | |
92 | mQ35TsegMbytes = ExtendedTsegMbytes;\r | |
23bfb5c0 LE |
93 | }\r |
94 | \r | |
95 | \r | |
73974f80 LE |
96 | VOID\r |
97 | Q35SmramAtDefaultSmbaseInitialization (\r | |
98 | VOID\r | |
99 | )\r | |
100 | {\r | |
101 | RETURN_STATUS PcdStatus;\r | |
102 | \r | |
103 | ASSERT (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID);\r | |
104 | \r | |
105 | mQ35SmramAtDefaultSmbase = FALSE;\r | |
106 | PcdStatus = PcdSetBoolS (PcdQ35SmramAtDefaultSmbase,\r | |
107 | mQ35SmramAtDefaultSmbase);\r | |
108 | ASSERT_RETURN_ERROR (PcdStatus);\r | |
109 | }\r | |
110 | \r | |
111 | \r | |
49edde15 LE |
112 | VOID\r |
113 | QemuUc32BaseInitialization (\r | |
114 | VOID\r | |
115 | )\r | |
116 | {\r | |
117 | UINT32 LowerMemorySize;\r | |
118 | UINT32 Uc32Size;\r | |
119 | \r | |
120 | if (mXen) {\r | |
121 | return;\r | |
122 | }\r | |
123 | \r | |
124 | if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {\r | |
125 | //\r | |
126 | // On q35, the 32-bit area that we'll mark as UC, through variable MTRRs,\r | |
127 | // starts at PcdPciExpressBaseAddress. The platform DSC is responsible for\r | |
128 | // setting PcdPciExpressBaseAddress such that describing the\r | |
129 | // [PcdPciExpressBaseAddress, 4GB) range require a very small number of\r | |
130 | // variable MTRRs (preferably 1 or 2).\r | |
131 | //\r | |
132 | ASSERT (FixedPcdGet64 (PcdPciExpressBaseAddress) <= MAX_UINT32);\r | |
133 | mQemuUc32Base = (UINT32)FixedPcdGet64 (PcdPciExpressBaseAddress);\r | |
134 | return;\r | |
135 | }\r | |
136 | \r | |
137 | ASSERT (mHostBridgeDevId == INTEL_82441_DEVICE_ID);\r | |
138 | //\r | |
139 | // On i440fx, start with the [LowerMemorySize, 4GB) range. Make sure one\r | |
140 | // variable MTRR suffices by truncating the size to a whole power of two,\r | |
141 | // while keeping the end affixed to 4GB. This will round the base up.\r | |
142 | //\r | |
143 | LowerMemorySize = GetSystemMemorySizeBelow4gb ();\r | |
144 | Uc32Size = GetPowerOfTwo32 ((UINT32)(SIZE_4GB - LowerMemorySize));\r | |
145 | mQemuUc32Base = (UINT32)(SIZE_4GB - Uc32Size);\r | |
146 | //\r | |
147 | // Assuming that LowerMemorySize is at least 1 byte, Uc32Size is at most 2GB.\r | |
148 | // Therefore mQemuUc32Base is at least 2GB.\r | |
149 | //\r | |
150 | ASSERT (mQemuUc32Base >= BASE_2GB);\r | |
151 | \r | |
152 | if (mQemuUc32Base != LowerMemorySize) {\r | |
153 | DEBUG ((DEBUG_VERBOSE, "%a: rounded UC32 base from 0x%x up to 0x%x, for "\r | |
154 | "an UC32 size of 0x%x\n", __FUNCTION__, LowerMemorySize, mQemuUc32Base,\r | |
155 | Uc32Size));\r | |
156 | }\r | |
157 | }\r | |
158 | \r | |
159 | \r | |
1fceaddb LE |
160 | /**\r |
161 | Iterate over the RAM entries in QEMU's fw_cfg E820 RAM map that start outside\r | |
162 | of the 32-bit address range.\r | |
163 | \r | |
164 | Find the highest exclusive >=4GB RAM address, or produce memory resource\r | |
165 | descriptor HOBs for RAM entries that start at or above 4GB.\r | |
166 | \r | |
167 | @param[out] MaxAddress If MaxAddress is NULL, then ScanOrAdd64BitE820Ram()\r | |
168 | produces memory resource descriptor HOBs for RAM\r | |
169 | entries that start at or above 4GB.\r | |
170 | \r | |
171 | Otherwise, MaxAddress holds the highest exclusive\r | |
172 | >=4GB RAM address on output. If QEMU's fw_cfg E820\r | |
173 | RAM map contains no RAM entry that starts outside of\r | |
174 | the 32-bit address range, then MaxAddress is exactly\r | |
175 | 4GB on output.\r | |
176 | \r | |
177 | @retval EFI_SUCCESS The fw_cfg E820 RAM map was found and processed.\r | |
178 | \r | |
179 | @retval EFI_PROTOCOL_ERROR The RAM map was found, but its size wasn't a\r | |
180 | whole multiple of sizeof(EFI_E820_ENTRY64). No\r | |
181 | RAM entry was processed.\r | |
182 | \r | |
183 | @return Error codes from QemuFwCfgFindFile(). No RAM\r | |
184 | entry was processed.\r | |
185 | **/\r | |
186 | STATIC\r | |
187 | EFI_STATUS\r | |
188 | ScanOrAdd64BitE820Ram (\r | |
189 | OUT UINT64 *MaxAddress OPTIONAL\r | |
190 | )\r | |
191 | {\r | |
192 | EFI_STATUS Status;\r | |
193 | FIRMWARE_CONFIG_ITEM FwCfgItem;\r | |
194 | UINTN FwCfgSize;\r | |
195 | EFI_E820_ENTRY64 E820Entry;\r | |
196 | UINTN Processed;\r | |
197 | \r | |
198 | Status = QemuFwCfgFindFile ("etc/e820", &FwCfgItem, &FwCfgSize);\r | |
199 | if (EFI_ERROR (Status)) {\r | |
200 | return Status;\r | |
201 | }\r | |
202 | if (FwCfgSize % sizeof E820Entry != 0) {\r | |
203 | return EFI_PROTOCOL_ERROR;\r | |
204 | }\r | |
205 | \r | |
206 | if (MaxAddress != NULL) {\r | |
207 | *MaxAddress = BASE_4GB;\r | |
208 | }\r | |
209 | \r | |
210 | QemuFwCfgSelectItem (FwCfgItem);\r | |
211 | for (Processed = 0; Processed < FwCfgSize; Processed += sizeof E820Entry) {\r | |
212 | QemuFwCfgReadBytes (sizeof E820Entry, &E820Entry);\r | |
213 | DEBUG ((\r | |
214 | DEBUG_VERBOSE,\r | |
215 | "%a: Base=0x%Lx Length=0x%Lx Type=%u\n",\r | |
216 | __FUNCTION__,\r | |
217 | E820Entry.BaseAddr,\r | |
218 | E820Entry.Length,\r | |
219 | E820Entry.Type\r | |
220 | ));\r | |
221 | if (E820Entry.Type == EfiAcpiAddressRangeMemory &&\r | |
222 | E820Entry.BaseAddr >= BASE_4GB) {\r | |
223 | if (MaxAddress == NULL) {\r | |
224 | UINT64 Base;\r | |
225 | UINT64 End;\r | |
226 | \r | |
227 | //\r | |
228 | // Round up the start address, and round down the end address.\r | |
229 | //\r | |
230 | Base = ALIGN_VALUE (E820Entry.BaseAddr, (UINT64)EFI_PAGE_SIZE);\r | |
231 | End = (E820Entry.BaseAddr + E820Entry.Length) &\r | |
232 | ~(UINT64)EFI_PAGE_MASK;\r | |
233 | if (Base < End) {\r | |
234 | AddMemoryRangeHob (Base, End);\r | |
235 | DEBUG ((\r | |
236 | DEBUG_VERBOSE,\r | |
237 | "%a: AddMemoryRangeHob [0x%Lx, 0x%Lx)\n",\r | |
238 | __FUNCTION__,\r | |
239 | Base,\r | |
240 | End\r | |
241 | ));\r | |
242 | }\r | |
243 | } else {\r | |
244 | UINT64 Candidate;\r | |
245 | \r | |
246 | Candidate = E820Entry.BaseAddr + E820Entry.Length;\r | |
247 | if (Candidate > *MaxAddress) {\r | |
248 | *MaxAddress = Candidate;\r | |
249 | DEBUG ((\r | |
250 | DEBUG_VERBOSE,\r | |
251 | "%a: MaxAddress=0x%Lx\n",\r | |
252 | __FUNCTION__,\r | |
253 | *MaxAddress\r | |
254 | ));\r | |
255 | }\r | |
256 | }\r | |
257 | }\r | |
258 | }\r | |
259 | return EFI_SUCCESS;\r | |
260 | }\r | |
261 | \r | |
262 | \r | |
4b455f7b | 263 | UINT32\r |
c0e10976 | 264 | GetSystemMemorySizeBelow4gb (\r |
4b455f7b | 265 | VOID\r |
49ba9447 | 266 | )\r |
267 | {\r | |
268 | UINT8 Cmos0x34;\r | |
269 | UINT8 Cmos0x35;\r | |
270 | \r | |
271 | //\r | |
272 | // CMOS 0x34/0x35 specifies the system memory above 16 MB.\r | |
273 | // * CMOS(0x35) is the high byte\r | |
274 | // * CMOS(0x34) is the low byte\r | |
275 | // * The size is specified in 64kb chunks\r | |
276 | // * Since this is memory above 16MB, the 16MB must be added\r | |
277 | // into the calculation to get the total memory size.\r | |
278 | //\r | |
279 | \r | |
280 | Cmos0x34 = (UINT8) CmosRead8 (0x34);\r | |
281 | Cmos0x35 = (UINT8) CmosRead8 (0x35);\r | |
282 | \r | |
c4046161 | 283 | return (UINT32) (((UINTN)((Cmos0x35 << 8) + Cmos0x34) << 16) + SIZE_16MB);\r |
49ba9447 | 284 | }\r |
285 | \r | |
286 | \r | |
c0e10976 | 287 | STATIC\r |
288 | UINT64\r | |
289 | GetSystemMemorySizeAbove4gb (\r | |
290 | )\r | |
291 | {\r | |
292 | UINT32 Size;\r | |
293 | UINTN CmosIndex;\r | |
294 | \r | |
295 | //\r | |
296 | // CMOS 0x5b-0x5d specifies the system memory above 4GB MB.\r | |
297 | // * CMOS(0x5d) is the most significant size byte\r | |
298 | // * CMOS(0x5c) is the middle size byte\r | |
299 | // * CMOS(0x5b) is the least significant size byte\r | |
300 | // * The size is specified in 64kb chunks\r | |
301 | //\r | |
302 | \r | |
303 | Size = 0;\r | |
304 | for (CmosIndex = 0x5d; CmosIndex >= 0x5b; CmosIndex--) {\r | |
305 | Size = (UINT32) (Size << 8) + (UINT32) CmosRead8 (CmosIndex);\r | |
306 | }\r | |
307 | \r | |
308 | return LShiftU64 (Size, 16);\r | |
309 | }\r | |
310 | \r | |
bc89fe48 | 311 | \r |
d5371680 LE |
312 | /**\r |
313 | Return the highest address that DXE could possibly use, plus one.\r | |
314 | **/\r | |
315 | STATIC\r | |
316 | UINT64\r | |
317 | GetFirstNonAddress (\r | |
318 | VOID\r | |
319 | )\r | |
320 | {\r | |
321 | UINT64 FirstNonAddress;\r | |
7e5b1b67 LE |
322 | UINT64 Pci64Base, Pci64Size;\r |
323 | CHAR8 MbString[7 + 1];\r | |
324 | EFI_STATUS Status;\r | |
325 | FIRMWARE_CONFIG_ITEM FwCfgItem;\r | |
326 | UINTN FwCfgSize;\r | |
327 | UINT64 HotPlugMemoryEnd;\r | |
32e083c7 | 328 | RETURN_STATUS PcdStatus;\r |
d5371680 | 329 | \r |
1fceaddb LE |
330 | //\r |
331 | // set FirstNonAddress to suppress incorrect compiler/analyzer warnings\r | |
332 | //\r | |
333 | FirstNonAddress = 0;\r | |
334 | \r | |
335 | //\r | |
336 | // If QEMU presents an E820 map, then get the highest exclusive >=4GB RAM\r | |
337 | // address from it. This can express an address >= 4GB+1TB.\r | |
338 | //\r | |
339 | // Otherwise, get the flat size of the memory above 4GB from the CMOS (which\r | |
340 | // can only express a size smaller than 1TB), and add it to 4GB.\r | |
341 | //\r | |
342 | Status = ScanOrAdd64BitE820Ram (&FirstNonAddress);\r | |
343 | if (EFI_ERROR (Status)) {\r | |
344 | FirstNonAddress = BASE_4GB + GetSystemMemorySizeAbove4gb ();\r | |
345 | }\r | |
7e5b1b67 LE |
346 | \r |
347 | //\r | |
348 | // If DXE is 32-bit, then we're done; PciBusDxe will degrade 64-bit MMIO\r | |
349 | // resources to 32-bit anyway. See DegradeResource() in\r | |
350 | // "PciResourceSupport.c".\r | |
351 | //\r | |
352 | #ifdef MDE_CPU_IA32\r | |
353 | if (!FeaturePcdGet (PcdDxeIplSwitchToLongMode)) {\r | |
354 | return FirstNonAddress;\r | |
355 | }\r | |
356 | #endif\r | |
357 | \r | |
358 | //\r | |
359 | // Otherwise, in order to calculate the highest address plus one, we must\r | |
360 | // consider the 64-bit PCI host aperture too. Fetch the default size.\r | |
361 | //\r | |
362 | Pci64Size = PcdGet64 (PcdPciMmio64Size);\r | |
363 | \r | |
364 | //\r | |
365 | // See if the user specified the number of megabytes for the 64-bit PCI host\r | |
366 | // aperture. The number of non-NUL characters in MbString allows for\r | |
367 | // 9,999,999 MB, which is approximately 10 TB.\r | |
368 | //\r | |
369 | // As signaled by the "X-" prefix, this knob is experimental, and might go\r | |
370 | // away at any time.\r | |
371 | //\r | |
372 | Status = QemuFwCfgFindFile ("opt/ovmf/X-PciMmio64Mb", &FwCfgItem,\r | |
373 | &FwCfgSize);\r | |
374 | if (!EFI_ERROR (Status)) {\r | |
375 | if (FwCfgSize >= sizeof MbString) {\r | |
376 | DEBUG ((EFI_D_WARN,\r | |
377 | "%a: ignoring malformed 64-bit PCI host aperture size from fw_cfg\n",\r | |
378 | __FUNCTION__));\r | |
379 | } else {\r | |
380 | QemuFwCfgSelectItem (FwCfgItem);\r | |
381 | QemuFwCfgReadBytes (FwCfgSize, MbString);\r | |
382 | MbString[FwCfgSize] = '\0';\r | |
383 | Pci64Size = LShiftU64 (AsciiStrDecimalToUint64 (MbString), 20);\r | |
384 | }\r | |
385 | }\r | |
386 | \r | |
387 | if (Pci64Size == 0) {\r | |
388 | if (mBootMode != BOOT_ON_S3_RESUME) {\r | |
389 | DEBUG ((EFI_D_INFO, "%a: disabling 64-bit PCI host aperture\n",\r | |
390 | __FUNCTION__));\r | |
32e083c7 LE |
391 | PcdStatus = PcdSet64S (PcdPciMmio64Size, 0);\r |
392 | ASSERT_RETURN_ERROR (PcdStatus);\r | |
7e5b1b67 LE |
393 | }\r |
394 | \r | |
395 | //\r | |
396 | // There's nothing more to do; the amount of memory above 4GB fully\r | |
397 | // determines the highest address plus one. The memory hotplug area (see\r | |
398 | // below) plays no role for the firmware in this case.\r | |
399 | //\r | |
400 | return FirstNonAddress;\r | |
401 | }\r | |
402 | \r | |
403 | //\r | |
404 | // The "etc/reserved-memory-end" fw_cfg file, when present, contains an\r | |
405 | // absolute, exclusive end address for the memory hotplug area. This area\r | |
406 | // starts right at the end of the memory above 4GB. The 64-bit PCI host\r | |
407 | // aperture must be placed above it.\r | |
408 | //\r | |
409 | Status = QemuFwCfgFindFile ("etc/reserved-memory-end", &FwCfgItem,\r | |
410 | &FwCfgSize);\r | |
411 | if (!EFI_ERROR (Status) && FwCfgSize == sizeof HotPlugMemoryEnd) {\r | |
412 | QemuFwCfgSelectItem (FwCfgItem);\r | |
413 | QemuFwCfgReadBytes (FwCfgSize, &HotPlugMemoryEnd);\r | |
c27c0003 LE |
414 | DEBUG ((DEBUG_VERBOSE, "%a: HotPlugMemoryEnd=0x%Lx\n", __FUNCTION__,\r |
415 | HotPlugMemoryEnd));\r | |
7e5b1b67 LE |
416 | \r |
417 | ASSERT (HotPlugMemoryEnd >= FirstNonAddress);\r | |
418 | FirstNonAddress = HotPlugMemoryEnd;\r | |
419 | }\r | |
420 | \r | |
421 | //\r | |
422 | // SeaBIOS aligns both boundaries of the 64-bit PCI host aperture to 1GB, so\r | |
423 | // that the host can map it with 1GB hugepages. Follow suit.\r | |
424 | //\r | |
425 | Pci64Base = ALIGN_VALUE (FirstNonAddress, (UINT64)SIZE_1GB);\r | |
426 | Pci64Size = ALIGN_VALUE (Pci64Size, (UINT64)SIZE_1GB);\r | |
427 | \r | |
428 | //\r | |
429 | // The 64-bit PCI host aperture should also be "naturally" aligned. The\r | |
430 | // alignment is determined by rounding the size of the aperture down to the\r | |
431 | // next smaller or equal power of two. That is, align the aperture by the\r | |
432 | // largest BAR size that can fit into it.\r | |
433 | //\r | |
434 | Pci64Base = ALIGN_VALUE (Pci64Base, GetPowerOfTwo64 (Pci64Size));\r | |
435 | \r | |
436 | if (mBootMode != BOOT_ON_S3_RESUME) {\r | |
437 | //\r | |
438 | // The core PciHostBridgeDxe driver will automatically add this range to\r | |
439 | // the GCD memory space map through our PciHostBridgeLib instance; here we\r | |
440 | // only need to set the PCDs.\r | |
441 | //\r | |
32e083c7 LE |
442 | PcdStatus = PcdSet64S (PcdPciMmio64Base, Pci64Base);\r |
443 | ASSERT_RETURN_ERROR (PcdStatus);\r | |
444 | PcdStatus = PcdSet64S (PcdPciMmio64Size, Pci64Size);\r | |
445 | ASSERT_RETURN_ERROR (PcdStatus);\r | |
446 | \r | |
7e5b1b67 LE |
447 | DEBUG ((EFI_D_INFO, "%a: Pci64Base=0x%Lx Pci64Size=0x%Lx\n",\r |
448 | __FUNCTION__, Pci64Base, Pci64Size));\r | |
449 | }\r | |
450 | \r | |
451 | //\r | |
452 | // The useful address space ends with the 64-bit PCI host aperture.\r | |
453 | //\r | |
454 | FirstNonAddress = Pci64Base + Pci64Size;\r | |
d5371680 LE |
455 | return FirstNonAddress;\r |
456 | }\r | |
457 | \r | |
458 | \r | |
bc89fe48 LE |
459 | /**\r |
460 | Initialize the mPhysMemAddressWidth variable, based on guest RAM size.\r | |
461 | **/\r | |
462 | VOID\r | |
463 | AddressWidthInitialization (\r | |
464 | VOID\r | |
465 | )\r | |
466 | {\r | |
467 | UINT64 FirstNonAddress;\r | |
468 | \r | |
469 | //\r | |
470 | // As guest-physical memory size grows, the permanent PEI RAM requirements\r | |
471 | // are dominated by the identity-mapping page tables built by the DXE IPL.\r | |
472 | // The DXL IPL keys off of the physical address bits advertized in the CPU\r | |
473 | // HOB. To conserve memory, we calculate the minimum address width here.\r | |
474 | //\r | |
d5371680 | 475 | FirstNonAddress = GetFirstNonAddress ();\r |
bc89fe48 LE |
476 | mPhysMemAddressWidth = (UINT8)HighBitSet64 (FirstNonAddress);\r |
477 | \r | |
478 | //\r | |
479 | // If FirstNonAddress is not an integral power of two, then we need an\r | |
480 | // additional bit.\r | |
481 | //\r | |
482 | if ((FirstNonAddress & (FirstNonAddress - 1)) != 0) {\r | |
483 | ++mPhysMemAddressWidth;\r | |
484 | }\r | |
485 | \r | |
486 | //\r | |
487 | // The minimum address width is 36 (covers up to and excluding 64 GB, which\r | |
488 | // is the maximum for Ia32 + PAE). The theoretical architecture maximum for\r | |
489 | // X64 long mode is 52 bits, but the DXE IPL clamps that down to 48 bits. We\r | |
490 | // can simply assert that here, since 48 bits are good enough for 256 TB.\r | |
491 | //\r | |
492 | if (mPhysMemAddressWidth <= 36) {\r | |
493 | mPhysMemAddressWidth = 36;\r | |
494 | }\r | |
495 | ASSERT (mPhysMemAddressWidth <= 48);\r | |
496 | }\r | |
497 | \r | |
498 | \r | |
499 | /**\r | |
500 | Calculate the cap for the permanent PEI memory.\r | |
501 | **/\r | |
502 | STATIC\r | |
503 | UINT32\r | |
504 | GetPeiMemoryCap (\r | |
505 | VOID\r | |
506 | )\r | |
507 | {\r | |
508 | BOOLEAN Page1GSupport;\r | |
509 | UINT32 RegEax;\r | |
510 | UINT32 RegEdx;\r | |
511 | UINT32 Pml4Entries;\r | |
512 | UINT32 PdpEntries;\r | |
513 | UINTN TotalPages;\r | |
514 | \r | |
515 | //\r | |
516 | // If DXE is 32-bit, then just return the traditional 64 MB cap.\r | |
517 | //\r | |
518 | #ifdef MDE_CPU_IA32\r | |
519 | if (!FeaturePcdGet (PcdDxeIplSwitchToLongMode)) {\r | |
520 | return SIZE_64MB;\r | |
521 | }\r | |
522 | #endif\r | |
523 | \r | |
524 | //\r | |
525 | // Dependent on physical address width, PEI memory allocations can be\r | |
526 | // dominated by the page tables built for 64-bit DXE. So we key the cap off\r | |
527 | // of those. The code below is based on CreateIdentityMappingPageTables() in\r | |
528 | // "MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c".\r | |
529 | //\r | |
530 | Page1GSupport = FALSE;\r | |
531 | if (PcdGetBool (PcdUse1GPageTable)) {\r | |
532 | AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL);\r | |
533 | if (RegEax >= 0x80000001) {\r | |
534 | AsmCpuid (0x80000001, NULL, NULL, NULL, &RegEdx);\r | |
535 | if ((RegEdx & BIT26) != 0) {\r | |
536 | Page1GSupport = TRUE;\r | |
537 | }\r | |
538 | }\r | |
539 | }\r | |
540 | \r | |
541 | if (mPhysMemAddressWidth <= 39) {\r | |
542 | Pml4Entries = 1;\r | |
543 | PdpEntries = 1 << (mPhysMemAddressWidth - 30);\r | |
544 | ASSERT (PdpEntries <= 0x200);\r | |
545 | } else {\r | |
546 | Pml4Entries = 1 << (mPhysMemAddressWidth - 39);\r | |
547 | ASSERT (Pml4Entries <= 0x200);\r | |
548 | PdpEntries = 512;\r | |
549 | }\r | |
550 | \r | |
551 | TotalPages = Page1GSupport ? Pml4Entries + 1 :\r | |
552 | (PdpEntries + 1) * Pml4Entries + 1;\r | |
553 | ASSERT (TotalPages <= 0x40201);\r | |
554 | \r | |
555 | //\r | |
556 | // Add 64 MB for miscellaneous allocations. Note that for\r | |
557 | // mPhysMemAddressWidth values close to 36, the cap will actually be\r | |
558 | // dominated by this increment.\r | |
559 | //\r | |
560 | return (UINT32)(EFI_PAGES_TO_SIZE (TotalPages) + SIZE_64MB);\r | |
561 | }\r | |
562 | \r | |
563 | \r | |
36658fff WL |
564 | /**\r |
565 | Publish PEI core memory\r | |
566 | \r | |
567 | @return EFI_SUCCESS The PEIM initialized successfully.\r | |
568 | \r | |
569 | **/\r | |
570 | EFI_STATUS\r | |
571 | PublishPeiMemory (\r | |
572 | VOID\r | |
573 | )\r | |
574 | {\r | |
575 | EFI_STATUS Status;\r | |
576 | EFI_PHYSICAL_ADDRESS MemoryBase;\r | |
577 | UINT64 MemorySize;\r | |
fc3f005a | 578 | UINT32 LowerMemorySize;\r |
bc89fe48 | 579 | UINT32 PeiMemoryCap;\r |
36658fff | 580 | \r |
45d87081 LE |
581 | LowerMemorySize = GetSystemMemorySizeBelow4gb ();\r |
582 | if (FeaturePcdGet (PcdSmmSmramRequire)) {\r | |
583 | //\r | |
584 | // TSEG is chipped from the end of low RAM\r | |
585 | //\r | |
23bfb5c0 | 586 | LowerMemorySize -= mQ35TsegMbytes * SIZE_1MB;\r |
45d87081 LE |
587 | }\r |
588 | \r | |
589 | //\r | |
590 | // If S3 is supported, then the S3 permanent PEI memory is placed next,\r | |
591 | // downwards. Its size is primarily dictated by CpuMpPei. The formula below\r | |
592 | // is an approximation.\r | |
593 | //\r | |
594 | if (mS3Supported) {\r | |
595 | mS3AcpiReservedMemorySize = SIZE_512KB +\r | |
45a70db3 | 596 | mMaxCpuCount *\r |
45d87081 LE |
597 | PcdGet32 (PcdCpuApStackSize);\r |
598 | mS3AcpiReservedMemoryBase = LowerMemorySize - mS3AcpiReservedMemorySize;\r | |
599 | LowerMemorySize = mS3AcpiReservedMemoryBase;\r | |
600 | }\r | |
601 | \r | |
8e54500f | 602 | if (mBootMode == BOOT_ON_S3_RESUME) {\r |
45d87081 LE |
603 | MemoryBase = mS3AcpiReservedMemoryBase;\r |
604 | MemorySize = mS3AcpiReservedMemorySize;\r | |
8e54500f | 605 | } else {\r |
bc89fe48 LE |
606 | PeiMemoryCap = GetPeiMemoryCap ();\r |
607 | DEBUG ((EFI_D_INFO, "%a: mPhysMemAddressWidth=%d PeiMemoryCap=%u KB\n",\r | |
608 | __FUNCTION__, mPhysMemAddressWidth, PeiMemoryCap >> 10));\r | |
609 | \r | |
8e54500f JJ |
610 | //\r |
611 | // Determine the range of memory to use during PEI\r | |
612 | //\r | |
efb0f16e LE |
613 | // Technically we could lay the permanent PEI RAM over SEC's temporary\r |
614 | // decompression and scratch buffer even if "secure S3" is needed, since\r | |
615 | // their lifetimes don't overlap. However, PeiFvInitialization() will cover\r | |
616 | // RAM up to PcdOvmfDecompressionScratchEnd with an EfiACPIMemoryNVS memory\r | |
617 | // allocation HOB, and other allocations served from the permanent PEI RAM\r | |
618 | // shouldn't overlap with that HOB.\r | |
619 | //\r | |
620 | MemoryBase = mS3Supported && FeaturePcdGet (PcdSmmSmramRequire) ?\r | |
621 | PcdGet32 (PcdOvmfDecompressionScratchEnd) :\r | |
622 | PcdGet32 (PcdOvmfDxeMemFvBase) + PcdGet32 (PcdOvmfDxeMemFvSize);\r | |
8e54500f | 623 | MemorySize = LowerMemorySize - MemoryBase;\r |
bc89fe48 LE |
624 | if (MemorySize > PeiMemoryCap) {\r |
625 | MemoryBase = LowerMemorySize - PeiMemoryCap;\r | |
626 | MemorySize = PeiMemoryCap;\r | |
8e54500f | 627 | }\r |
36658fff WL |
628 | }\r |
629 | \r | |
adec2bd5 LE |
630 | //\r |
631 | // MEMFD_BASE_ADDRESS separates the SMRAM at the default SMBASE from the\r | |
632 | // normal boot permanent PEI RAM. Regarding the S3 boot path, the S3\r | |
633 | // permanent PEI RAM is located even higher.\r | |
634 | //\r | |
635 | if (FeaturePcdGet (PcdSmmSmramRequire) && mQ35SmramAtDefaultSmbase) {\r | |
636 | ASSERT (SMM_DEFAULT_SMBASE + MCH_DEFAULT_SMBASE_SIZE <= MemoryBase);\r | |
637 | }\r | |
638 | \r | |
36658fff WL |
639 | //\r |
640 | // Publish this memory to the PEI Core\r | |
641 | //\r | |
642 | Status = PublishSystemMemory(MemoryBase, MemorySize);\r | |
643 | ASSERT_EFI_ERROR (Status);\r | |
644 | \r | |
645 | return Status;\r | |
646 | }\r | |
647 | \r | |
c0e10976 | 648 | \r |
49ba9447 | 649 | /**\r |
c034906e | 650 | Peform Memory Detection for QEMU / KVM\r |
49ba9447 | 651 | \r |
652 | **/\r | |
c034906e JJ |
653 | STATIC\r |
654 | VOID\r | |
655 | QemuInitializeRam (\r | |
656 | VOID\r | |
49ba9447 | 657 | )\r |
658 | {\r | |
c0e10976 | 659 | UINT64 LowerMemorySize;\r |
660 | UINT64 UpperMemorySize;\r | |
79d274b8 LE |
661 | MTRR_SETTINGS MtrrSettings;\r |
662 | EFI_STATUS Status;\r | |
49ba9447 | 663 | \r |
c034906e | 664 | DEBUG ((EFI_D_INFO, "%a called\n", __FUNCTION__));\r |
49ba9447 | 665 | \r |
666 | //\r | |
667 | // Determine total memory size available\r | |
668 | //\r | |
c0e10976 | 669 | LowerMemorySize = GetSystemMemorySizeBelow4gb ();\r |
670 | UpperMemorySize = GetSystemMemorySizeAbove4gb ();\r | |
49ba9447 | 671 | \r |
e3e3090a LE |
672 | if (mBootMode == BOOT_ON_S3_RESUME) {\r |
673 | //\r | |
674 | // Create the following memory HOB as an exception on the S3 boot path.\r | |
675 | //\r | |
676 | // Normally we'd create memory HOBs only on the normal boot path. However,\r | |
677 | // CpuMpPei specifically needs such a low-memory HOB on the S3 path as\r | |
678 | // well, for "borrowing" a subset of it temporarily, for the AP startup\r | |
679 | // vector.\r | |
680 | //\r | |
681 | // CpuMpPei saves the original contents of the borrowed area in permanent\r | |
682 | // PEI RAM, in a backup buffer allocated with the normal PEI services.\r | |
683 | // CpuMpPei restores the original contents ("returns" the borrowed area) at\r | |
684 | // End-of-PEI. End-of-PEI in turn is emitted by S3Resume2Pei before\r | |
8c0b0b34 | 685 | // transferring control to the OS's wakeup vector in the FACS.\r |
e3e3090a LE |
686 | //\r |
687 | // We expect any other PEIMs that "borrow" memory similarly to CpuMpPei to\r | |
688 | // restore the original contents. Furthermore, we expect all such PEIMs\r | |
689 | // (CpuMpPei included) to claim the borrowed areas by producing memory\r | |
690 | // allocation HOBs, and to honor preexistent memory allocation HOBs when\r | |
691 | // looking for an area to borrow.\r | |
692 | //\r | |
693 | AddMemoryRangeHob (0, BASE_512KB + BASE_128KB);\r | |
694 | } else {\r | |
bd386eaf JJ |
695 | //\r |
696 | // Create memory HOBs\r | |
697 | //\r | |
bd386eaf | 698 | AddMemoryRangeHob (0, BASE_512KB + BASE_128KB);\r |
b09c1c6f LE |
699 | \r |
700 | if (FeaturePcdGet (PcdSmmSmramRequire)) {\r | |
701 | UINT32 TsegSize;\r | |
702 | \r | |
23bfb5c0 | 703 | TsegSize = mQ35TsegMbytes * SIZE_1MB;\r |
b09c1c6f LE |
704 | AddMemoryRangeHob (BASE_1MB, LowerMemorySize - TsegSize);\r |
705 | AddReservedMemoryBaseSizeHob (LowerMemorySize - TsegSize, TsegSize,\r | |
706 | TRUE);\r | |
707 | } else {\r | |
708 | AddMemoryRangeHob (BASE_1MB, LowerMemorySize);\r | |
709 | }\r | |
710 | \r | |
1fceaddb LE |
711 | //\r |
712 | // If QEMU presents an E820 map, then create memory HOBs for the >=4GB RAM\r | |
713 | // entries. Otherwise, create a single memory HOB with the flat >=4GB\r | |
714 | // memory size read from the CMOS.\r | |
715 | //\r | |
716 | Status = ScanOrAdd64BitE820Ram (NULL);\r | |
717 | if (EFI_ERROR (Status) && UpperMemorySize != 0) {\r | |
035ce3b3 | 718 | AddMemoryBaseSizeHob (BASE_4GB, UpperMemorySize);\r |
cfc80e2e | 719 | }\r |
bd386eaf | 720 | }\r |
49ba9447 | 721 | \r |
79d274b8 LE |
722 | //\r |
723 | // We'd like to keep the following ranges uncached:\r | |
724 | // - [640 KB, 1 MB)\r | |
725 | // - [LowerMemorySize, 4 GB)\r | |
726 | //\r | |
727 | // Everything else should be WB. Unfortunately, programming the inverse (ie.\r | |
728 | // keeping the default UC, and configuring the complement set of the above as\r | |
729 | // WB) is not reliable in general, because the end of the upper RAM can have\r | |
730 | // practically any alignment, and we may not have enough variable MTRRs to\r | |
731 | // cover it exactly.\r | |
732 | //\r | |
733 | if (IsMtrrSupported ()) {\r | |
734 | MtrrGetAllMtrrs (&MtrrSettings);\r | |
735 | \r | |
736 | //\r | |
737 | // MTRRs disabled, fixed MTRRs disabled, default type is uncached\r | |
738 | //\r | |
739 | ASSERT ((MtrrSettings.MtrrDefType & BIT11) == 0);\r | |
740 | ASSERT ((MtrrSettings.MtrrDefType & BIT10) == 0);\r | |
741 | ASSERT ((MtrrSettings.MtrrDefType & 0xFF) == 0);\r | |
742 | \r | |
743 | //\r | |
744 | // flip default type to writeback\r | |
745 | //\r | |
746 | SetMem (&MtrrSettings.Fixed, sizeof MtrrSettings.Fixed, 0x06);\r | |
747 | ZeroMem (&MtrrSettings.Variables, sizeof MtrrSettings.Variables);\r | |
748 | MtrrSettings.MtrrDefType |= BIT11 | BIT10 | 6;\r | |
749 | MtrrSetAllMtrrs (&MtrrSettings);\r | |
e8e5cd4a | 750 | \r |
79d274b8 LE |
751 | //\r |
752 | // Set memory range from 640KB to 1MB to uncacheable\r | |
753 | //\r | |
754 | Status = MtrrSetMemoryAttribute (BASE_512KB + BASE_128KB,\r | |
755 | BASE_1MB - (BASE_512KB + BASE_128KB), CacheUncacheable);\r | |
756 | ASSERT_EFI_ERROR (Status);\r | |
e8e5cd4a | 757 | \r |
79d274b8 | 758 | //\r |
49edde15 LE |
759 | // Set the memory range from the start of the 32-bit MMIO area (32-bit PCI\r |
760 | // MMIO aperture on i440fx, PCIEXBAR on q35) to 4GB as uncacheable.\r | |
79d274b8 | 761 | //\r |
49edde15 LE |
762 | Status = MtrrSetMemoryAttribute (mQemuUc32Base, SIZE_4GB - mQemuUc32Base,\r |
763 | CacheUncacheable);\r | |
79d274b8 | 764 | ASSERT_EFI_ERROR (Status);\r |
c0e10976 | 765 | }\r |
49ba9447 | 766 | }\r |
767 | \r | |
c034906e JJ |
768 | /**\r |
769 | Publish system RAM and reserve memory regions\r | |
770 | \r | |
771 | **/\r | |
772 | VOID\r | |
773 | InitializeRamRegions (\r | |
774 | VOID\r | |
775 | )\r | |
776 | {\r | |
2818c158 JJ |
777 | if (!mXen) {\r |
778 | QemuInitializeRam ();\r | |
779 | } else {\r | |
2818c158 JJ |
780 | XenPublishRamRegions ();\r |
781 | }\r | |
8e54500f JJ |
782 | \r |
783 | if (mS3Supported && mBootMode != BOOT_ON_S3_RESUME) {\r | |
784 | //\r | |
785 | // This is the memory range that will be used for PEI on S3 resume\r | |
786 | //\r | |
787 | BuildMemoryAllocationHob (\r | |
45d87081 LE |
788 | mS3AcpiReservedMemoryBase,\r |
789 | mS3AcpiReservedMemorySize,\r | |
8e54500f JJ |
790 | EfiACPIMemoryNVS\r |
791 | );\r | |
e249f906 LE |
792 | \r |
793 | //\r | |
794 | // Cover the initial RAM area used as stack and temporary PEI heap.\r | |
795 | //\r | |
796 | // This is reserved as ACPI NVS so it can be used on S3 resume.\r | |
797 | //\r | |
798 | BuildMemoryAllocationHob (\r | |
799 | PcdGet32 (PcdOvmfSecPeiTempRamBase),\r | |
800 | PcdGet32 (PcdOvmfSecPeiTempRamSize),\r | |
801 | EfiACPIMemoryNVS\r | |
802 | );\r | |
78a38b73 | 803 | \r |
ad43bc6b LE |
804 | //\r |
805 | // SEC stores its table of GUIDed section handlers here.\r | |
806 | //\r | |
807 | BuildMemoryAllocationHob (\r | |
808 | PcdGet64 (PcdGuidedExtractHandlerTableAddress),\r | |
809 | PcdGet32 (PcdGuidedExtractHandlerTableSize),\r | |
810 | EfiACPIMemoryNVS\r | |
811 | );\r | |
812 | \r | |
78a38b73 LE |
813 | #ifdef MDE_CPU_X64\r |
814 | //\r | |
815 | // Reserve the initial page tables built by the reset vector code.\r | |
816 | //\r | |
817 | // Since this memory range will be used by the Reset Vector on S3\r | |
818 | // resume, it must be reserved as ACPI NVS.\r | |
819 | //\r | |
820 | BuildMemoryAllocationHob (\r | |
821 | (EFI_PHYSICAL_ADDRESS)(UINTN) PcdGet32 (PcdOvmfSecPageTablesBase),\r | |
822 | (UINT64)(UINTN) PcdGet32 (PcdOvmfSecPageTablesSize),\r | |
823 | EfiACPIMemoryNVS\r | |
824 | );\r | |
825 | #endif\r | |
0e8a31f5 | 826 | }\r |
6a7cba79 | 827 | \r |
0e8a31f5 | 828 | if (mBootMode != BOOT_ON_S3_RESUME) {\r |
1a7edbbc LE |
829 | if (!FeaturePcdGet (PcdSmmSmramRequire)) {\r |
830 | //\r | |
831 | // Reserve the lock box storage area\r | |
832 | //\r | |
833 | // Since this memory range will be used on S3 resume, it must be\r | |
834 | // reserved as ACPI NVS.\r | |
835 | //\r | |
836 | // If S3 is unsupported, then various drivers might still write to the\r | |
837 | // LockBox area. We ought to prevent DXE from serving allocation requests\r | |
838 | // such that they would overlap the LockBox storage.\r | |
839 | //\r | |
840 | ZeroMem (\r | |
841 | (VOID*)(UINTN) PcdGet32 (PcdOvmfLockBoxStorageBase),\r | |
842 | (UINTN) PcdGet32 (PcdOvmfLockBoxStorageSize)\r | |
843 | );\r | |
844 | BuildMemoryAllocationHob (\r | |
845 | (EFI_PHYSICAL_ADDRESS)(UINTN) PcdGet32 (PcdOvmfLockBoxStorageBase),\r | |
846 | (UINT64)(UINTN) PcdGet32 (PcdOvmfLockBoxStorageSize),\r | |
847 | mS3Supported ? EfiACPIMemoryNVS : EfiBootServicesData\r | |
848 | );\r | |
849 | }\r | |
b09c1c6f LE |
850 | \r |
851 | if (FeaturePcdGet (PcdSmmSmramRequire)) {\r | |
852 | UINT32 TsegSize;\r | |
853 | \r | |
854 | //\r | |
855 | // Make sure the TSEG area that we reported as a reserved memory resource\r | |
856 | // cannot be used for reserved memory allocations.\r | |
857 | //\r | |
23bfb5c0 | 858 | TsegSize = mQ35TsegMbytes * SIZE_1MB;\r |
b09c1c6f LE |
859 | BuildMemoryAllocationHob (\r |
860 | GetSystemMemorySizeBelow4gb() - TsegSize,\r | |
861 | TsegSize,\r | |
862 | EfiReservedMemoryType\r | |
863 | );\r | |
864 | }\r | |
8e54500f | 865 | }\r |
c034906e | 866 | }\r |