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Commit | Line | Data |
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c90e37b5 JJ |
1 | ;------------------------------------------------------------------------------\r |
2 | ; @file\r | |
3 | ; Sets the CR3 register for 64-bit paging\r | |
4 | ;\r | |
5 | ; Copyright (c) 2008 - 2013, Intel Corporation. All rights reserved.<BR>\r | |
a91b700e | 6 | ; Copyright (c) 2017 - 2020, Advanced Micro Devices, Inc. All rights reserved.<BR>\r |
b26f0cf9 | 7 | ; SPDX-License-Identifier: BSD-2-Clause-Patent\r |
c90e37b5 JJ |
8 | ;\r |
9 | ;------------------------------------------------------------------------------\r | |
10 | \r | |
11 | BITS 32\r | |
12 | \r | |
13 | %define PAGE_PRESENT 0x01\r | |
14 | %define PAGE_READ_WRITE 0x02\r | |
15 | %define PAGE_USER_SUPERVISOR 0x04\r | |
16 | %define PAGE_WRITE_THROUGH 0x08\r | |
17 | %define PAGE_CACHE_DISABLE 0x010\r | |
18 | %define PAGE_ACCESSED 0x020\r | |
19 | %define PAGE_DIRTY 0x040\r | |
20 | %define PAGE_PAT 0x080\r | |
21 | %define PAGE_GLOBAL 0x0100\r | |
22 | %define PAGE_2M_MBO 0x080\r | |
23 | %define PAGE_2M_PAT 0x01000\r | |
24 | \r | |
6995a1b7 TL |
25 | %define PAGE_4K_PDE_ATTR (PAGE_ACCESSED + \\r |
26 | PAGE_DIRTY + \\r | |
27 | PAGE_READ_WRITE + \\r | |
28 | PAGE_PRESENT)\r | |
29 | \r | |
c90e37b5 | 30 | %define PAGE_2M_PDE_ATTR (PAGE_2M_MBO + \\r |
c90e37b5 JJ |
31 | PAGE_ACCESSED + \\r |
32 | PAGE_DIRTY + \\r | |
33 | PAGE_READ_WRITE + \\r | |
34 | PAGE_PRESENT)\r | |
35 | \r | |
98f378a7 | 36 | %define PAGE_PDP_ATTR (PAGE_ACCESSED + \\r |
c90e37b5 JJ |
37 | PAGE_READ_WRITE + \\r |
38 | PAGE_PRESENT)\r | |
39 | \r | |
8b76f235 MX |
40 | %define TDX_BSP 1\r |
41 | %define TDX_AP 2\r | |
42 | \r | |
c90e37b5 | 43 | ;\r |
e60af8a1 | 44 | ; Modified: EAX, EBX, ECX, EDX\r |
c90e37b5 JJ |
45 | ;\r |
46 | SetCr3ForPageTables64:\r | |
8b76f235 MX |
47 | ; Check the TDX features.\r |
48 | ; If it is TDX APs, then jump to SetCr3 directly.\r | |
49 | ; In TD guest the initialization is done by BSP, including building\r | |
50 | ; the page tables. APs will spin on until byte[TDX_WORK_AREA_PGTBL_READY]\r | |
51 | ; is set.\r | |
52 | OneTimeCall CheckTdxFeaturesBeforeBuildPagetables\r | |
53 | cmp eax, TDX_BSP\r | |
54 | je ClearOvmfPageTables\r | |
55 | cmp eax, TDX_AP\r | |
56 | je SetCr3\r | |
c90e37b5 | 57 | \r |
b9af5037 | 58 | ; Check whether the SEV is active and populate the SevEsWorkArea\r |
a91b700e | 59 | OneTimeCall CheckSevFeatures\r |
e60af8a1 | 60 | \r |
b9af5037 BS |
61 | ; If SEV is enabled, the C-bit position is always above 31.\r |
62 | ; The mask will be saved in the EDX and applied during the\r | |
63 | ; the page table build below.\r | |
64 | OneTimeCall GetSevCBitMaskAbove31\r | |
e60af8a1 | 65 | \r |
8b76f235 | 66 | ClearOvmfPageTables:\r |
c90e37b5 | 67 | ;\r |
73d66c58 MH |
68 | ; For OVMF, build some initial page tables at\r |
69 | ; PcdOvmfSecPageTablesBase - (PcdOvmfSecPageTablesBase + 0x6000).\r | |
b382ede3 | 70 | ;\r |
73d66c58 MH |
71 | ; This range should match with PcdOvmfSecPageTablesSize which is\r |
72 | ; declared in the FDF files.\r | |
c90e37b5 JJ |
73 | ;\r |
74 | ; At the end of PEI, the pages tables will be rebuilt into a\r | |
75 | ; more permanent location by DxeIpl.\r | |
76 | ;\r | |
77 | \r | |
78 | mov ecx, 6 * 0x1000 / 4\r | |
79 | xor eax, eax\r | |
80 | clearPageTablesMemoryLoop:\r | |
73d66c58 | 81 | mov dword[ecx * 4 + PT_ADDR (0) - 4], eax\r |
c90e37b5 JJ |
82 | loop clearPageTablesMemoryLoop\r |
83 | \r | |
84 | ;\r | |
85 | ; Top level Page Directory Pointers (1 * 512GB entry)\r | |
86 | ;\r | |
73d66c58 | 87 | mov dword[PT_ADDR (0)], PT_ADDR (0x1000) + PAGE_PDP_ATTR\r |
e60af8a1 | 88 | mov dword[PT_ADDR (4)], edx\r |
c90e37b5 JJ |
89 | \r |
90 | ;\r | |
91 | ; Next level Page Directory Pointers (4 * 1GB entries => 4GB)\r | |
92 | ;\r | |
73d66c58 | 93 | mov dword[PT_ADDR (0x1000)], PT_ADDR (0x2000) + PAGE_PDP_ATTR\r |
e60af8a1 | 94 | mov dword[PT_ADDR (0x1004)], edx\r |
73d66c58 | 95 | mov dword[PT_ADDR (0x1008)], PT_ADDR (0x3000) + PAGE_PDP_ATTR\r |
e60af8a1 | 96 | mov dword[PT_ADDR (0x100C)], edx\r |
73d66c58 | 97 | mov dword[PT_ADDR (0x1010)], PT_ADDR (0x4000) + PAGE_PDP_ATTR\r |
e60af8a1 | 98 | mov dword[PT_ADDR (0x1014)], edx\r |
73d66c58 | 99 | mov dword[PT_ADDR (0x1018)], PT_ADDR (0x5000) + PAGE_PDP_ATTR\r |
e60af8a1 | 100 | mov dword[PT_ADDR (0x101C)], edx\r |
c90e37b5 JJ |
101 | \r |
102 | ;\r | |
103 | ; Page Table Entries (2048 * 2MB entries => 4GB)\r | |
104 | ;\r | |
105 | mov ecx, 0x800\r | |
106 | pageTableEntriesLoop:\r | |
107 | mov eax, ecx\r | |
108 | dec eax\r | |
109 | shl eax, 21\r | |
110 | add eax, PAGE_2M_PDE_ATTR\r | |
73d66c58 | 111 | mov [ecx * 8 + PT_ADDR (0x2000 - 8)], eax\r |
e60af8a1 | 112 | mov [(ecx * 8 + PT_ADDR (0x2000 - 8)) + 4], edx\r |
c90e37b5 JJ |
113 | loop pageTableEntriesLoop\r |
114 | \r | |
b9af5037 BS |
115 | ; Clear the C-bit from the GHCB page if the SEV-ES is enabled.\r |
116 | OneTimeCall SevClearPageEncMaskForGhcbPage\r | |
6995a1b7 | 117 | \r |
8b76f235 MX |
118 | ; TDX will do some PostBuildPages task, such as setting\r |
119 | ; byte[TDX_WORK_AREA_PGTBL_READY].\r | |
120 | OneTimeCall TdxPostBuildPageTables\r | |
121 | \r | |
6995a1b7 | 122 | SetCr3:\r |
c90e37b5 JJ |
123 | ;\r |
124 | ; Set CR3 now that the paging structures are available\r | |
125 | ;\r | |
73d66c58 | 126 | mov eax, PT_ADDR (0)\r |
c90e37b5 JJ |
127 | mov cr3, eax\r |
128 | \r | |
129 | OneTimeCallRet SetCr3ForPageTables64\r |