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c90e37b5 JJ |
1 | ;------------------------------------------------------------------------------\r |
2 | ; @file\r | |
3 | ; Sets the CR3 register for 64-bit paging\r | |
4 | ;\r | |
5 | ; Copyright (c) 2008 - 2013, Intel Corporation. All rights reserved.<BR>\r | |
6 | ; This program and the accompanying materials\r | |
7 | ; are licensed and made available under the terms and conditions of the BSD License\r | |
8 | ; which accompanies this distribution. The full text of the license may be found at\r | |
9 | ; http://opensource.org/licenses/bsd-license.php\r | |
10 | ;\r | |
11 | ; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
12 | ; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
13 | ;\r | |
14 | ;------------------------------------------------------------------------------\r | |
15 | \r | |
16 | BITS 32\r | |
17 | \r | |
18 | %define PAGE_PRESENT 0x01\r | |
19 | %define PAGE_READ_WRITE 0x02\r | |
20 | %define PAGE_USER_SUPERVISOR 0x04\r | |
21 | %define PAGE_WRITE_THROUGH 0x08\r | |
22 | %define PAGE_CACHE_DISABLE 0x010\r | |
23 | %define PAGE_ACCESSED 0x020\r | |
24 | %define PAGE_DIRTY 0x040\r | |
25 | %define PAGE_PAT 0x080\r | |
26 | %define PAGE_GLOBAL 0x0100\r | |
27 | %define PAGE_2M_MBO 0x080\r | |
28 | %define PAGE_2M_PAT 0x01000\r | |
29 | \r | |
30 | %define PAGE_2M_PDE_ATTR (PAGE_2M_MBO + \\r | |
c90e37b5 JJ |
31 | PAGE_ACCESSED + \\r |
32 | PAGE_DIRTY + \\r | |
33 | PAGE_READ_WRITE + \\r | |
34 | PAGE_PRESENT)\r | |
35 | \r | |
98f378a7 | 36 | %define PAGE_PDP_ATTR (PAGE_ACCESSED + \\r |
c90e37b5 JJ |
37 | PAGE_READ_WRITE + \\r |
38 | PAGE_PRESENT)\r | |
39 | \r | |
40 | \r | |
41 | ;\r | |
42 | ; Modified: EAX, ECX\r | |
43 | ;\r | |
44 | SetCr3ForPageTables64:\r | |
45 | \r | |
46 | ;\r | |
73d66c58 MH |
47 | ; For OVMF, build some initial page tables at\r |
48 | ; PcdOvmfSecPageTablesBase - (PcdOvmfSecPageTablesBase + 0x6000).\r | |
b382ede3 | 49 | ;\r |
73d66c58 MH |
50 | ; This range should match with PcdOvmfSecPageTablesSize which is\r |
51 | ; declared in the FDF files.\r | |
c90e37b5 JJ |
52 | ;\r |
53 | ; At the end of PEI, the pages tables will be rebuilt into a\r | |
54 | ; more permanent location by DxeIpl.\r | |
55 | ;\r | |
56 | \r | |
57 | mov ecx, 6 * 0x1000 / 4\r | |
58 | xor eax, eax\r | |
59 | clearPageTablesMemoryLoop:\r | |
73d66c58 | 60 | mov dword[ecx * 4 + PT_ADDR (0) - 4], eax\r |
c90e37b5 JJ |
61 | loop clearPageTablesMemoryLoop\r |
62 | \r | |
63 | ;\r | |
64 | ; Top level Page Directory Pointers (1 * 512GB entry)\r | |
65 | ;\r | |
73d66c58 | 66 | mov dword[PT_ADDR (0)], PT_ADDR (0x1000) + PAGE_PDP_ATTR\r |
c90e37b5 JJ |
67 | \r |
68 | ;\r | |
69 | ; Next level Page Directory Pointers (4 * 1GB entries => 4GB)\r | |
70 | ;\r | |
73d66c58 MH |
71 | mov dword[PT_ADDR (0x1000)], PT_ADDR (0x2000) + PAGE_PDP_ATTR\r |
72 | mov dword[PT_ADDR (0x1008)], PT_ADDR (0x3000) + PAGE_PDP_ATTR\r | |
73 | mov dword[PT_ADDR (0x1010)], PT_ADDR (0x4000) + PAGE_PDP_ATTR\r | |
74 | mov dword[PT_ADDR (0x1018)], PT_ADDR (0x5000) + PAGE_PDP_ATTR\r | |
c90e37b5 JJ |
75 | \r |
76 | ;\r | |
77 | ; Page Table Entries (2048 * 2MB entries => 4GB)\r | |
78 | ;\r | |
79 | mov ecx, 0x800\r | |
80 | pageTableEntriesLoop:\r | |
81 | mov eax, ecx\r | |
82 | dec eax\r | |
83 | shl eax, 21\r | |
84 | add eax, PAGE_2M_PDE_ATTR\r | |
73d66c58 | 85 | mov [ecx * 8 + PT_ADDR (0x2000 - 8)], eax\r |
c90e37b5 JJ |
86 | loop pageTableEntriesLoop\r |
87 | \r | |
88 | ;\r | |
89 | ; Set CR3 now that the paging structures are available\r | |
90 | ;\r | |
73d66c58 | 91 | mov eax, PT_ADDR (0)\r |
c90e37b5 JJ |
92 | mov cr3, eax\r |
93 | \r | |
94 | OneTimeCallRet SetCr3ForPageTables64\r |