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Commit | Line | Data |
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c90e37b5 JJ |
1 | ;------------------------------------------------------------------------------\r |
2 | ; @file\r | |
3 | ; Sets the CR3 register for 64-bit paging\r | |
4 | ;\r | |
5 | ; Copyright (c) 2008 - 2013, Intel Corporation. All rights reserved.<BR>\r | |
a91b700e | 6 | ; Copyright (c) 2017 - 2020, Advanced Micro Devices, Inc. All rights reserved.<BR>\r |
b26f0cf9 | 7 | ; SPDX-License-Identifier: BSD-2-Clause-Patent\r |
c90e37b5 JJ |
8 | ;\r |
9 | ;------------------------------------------------------------------------------\r | |
10 | \r | |
11 | BITS 32\r | |
12 | \r | |
13 | %define PAGE_PRESENT 0x01\r | |
14 | %define PAGE_READ_WRITE 0x02\r | |
15 | %define PAGE_USER_SUPERVISOR 0x04\r | |
16 | %define PAGE_WRITE_THROUGH 0x08\r | |
17 | %define PAGE_CACHE_DISABLE 0x010\r | |
18 | %define PAGE_ACCESSED 0x020\r | |
19 | %define PAGE_DIRTY 0x040\r | |
20 | %define PAGE_PAT 0x080\r | |
21 | %define PAGE_GLOBAL 0x0100\r | |
22 | %define PAGE_2M_MBO 0x080\r | |
23 | %define PAGE_2M_PAT 0x01000\r | |
24 | \r | |
6995a1b7 TL |
25 | %define PAGE_4K_PDE_ATTR (PAGE_ACCESSED + \\r |
26 | PAGE_DIRTY + \\r | |
27 | PAGE_READ_WRITE + \\r | |
28 | PAGE_PRESENT)\r | |
29 | \r | |
c90e37b5 | 30 | %define PAGE_2M_PDE_ATTR (PAGE_2M_MBO + \\r |
c90e37b5 JJ |
31 | PAGE_ACCESSED + \\r |
32 | PAGE_DIRTY + \\r | |
33 | PAGE_READ_WRITE + \\r | |
34 | PAGE_PRESENT)\r | |
35 | \r | |
98f378a7 | 36 | %define PAGE_PDP_ATTR (PAGE_ACCESSED + \\r |
c90e37b5 JJ |
37 | PAGE_READ_WRITE + \\r |
38 | PAGE_PRESENT)\r | |
39 | \r | |
c90e37b5 | 40 | ;\r |
e60af8a1 | 41 | ; Modified: EAX, EBX, ECX, EDX\r |
c90e37b5 JJ |
42 | ;\r |
43 | SetCr3ForPageTables64:\r | |
44 | \r | |
ab77b603 BS |
45 | ; Clear the WorkArea header. The SEV probe routines will populate the\r |
46 | ; work area when detected.\r | |
47 | mov byte[WORK_AREA_GUEST_TYPE], 0\r | |
48 | \r | |
a91b700e | 49 | OneTimeCall CheckSevFeatures\r |
e60af8a1 BS |
50 | xor edx, edx\r |
51 | test eax, eax\r | |
52 | jz SevNotActive\r | |
53 | \r | |
54 | ; If SEV is enabled, C-bit is always above 31\r | |
55 | sub eax, 32\r | |
56 | bts edx, eax\r | |
57 | \r | |
58 | SevNotActive:\r | |
59 | \r | |
c90e37b5 | 60 | ;\r |
73d66c58 MH |
61 | ; For OVMF, build some initial page tables at\r |
62 | ; PcdOvmfSecPageTablesBase - (PcdOvmfSecPageTablesBase + 0x6000).\r | |
b382ede3 | 63 | ;\r |
73d66c58 MH |
64 | ; This range should match with PcdOvmfSecPageTablesSize which is\r |
65 | ; declared in the FDF files.\r | |
c90e37b5 JJ |
66 | ;\r |
67 | ; At the end of PEI, the pages tables will be rebuilt into a\r | |
68 | ; more permanent location by DxeIpl.\r | |
69 | ;\r | |
70 | \r | |
71 | mov ecx, 6 * 0x1000 / 4\r | |
72 | xor eax, eax\r | |
73 | clearPageTablesMemoryLoop:\r | |
73d66c58 | 74 | mov dword[ecx * 4 + PT_ADDR (0) - 4], eax\r |
c90e37b5 JJ |
75 | loop clearPageTablesMemoryLoop\r |
76 | \r | |
77 | ;\r | |
78 | ; Top level Page Directory Pointers (1 * 512GB entry)\r | |
79 | ;\r | |
73d66c58 | 80 | mov dword[PT_ADDR (0)], PT_ADDR (0x1000) + PAGE_PDP_ATTR\r |
e60af8a1 | 81 | mov dword[PT_ADDR (4)], edx\r |
c90e37b5 JJ |
82 | \r |
83 | ;\r | |
84 | ; Next level Page Directory Pointers (4 * 1GB entries => 4GB)\r | |
85 | ;\r | |
73d66c58 | 86 | mov dword[PT_ADDR (0x1000)], PT_ADDR (0x2000) + PAGE_PDP_ATTR\r |
e60af8a1 | 87 | mov dword[PT_ADDR (0x1004)], edx\r |
73d66c58 | 88 | mov dword[PT_ADDR (0x1008)], PT_ADDR (0x3000) + PAGE_PDP_ATTR\r |
e60af8a1 | 89 | mov dword[PT_ADDR (0x100C)], edx\r |
73d66c58 | 90 | mov dword[PT_ADDR (0x1010)], PT_ADDR (0x4000) + PAGE_PDP_ATTR\r |
e60af8a1 | 91 | mov dword[PT_ADDR (0x1014)], edx\r |
73d66c58 | 92 | mov dword[PT_ADDR (0x1018)], PT_ADDR (0x5000) + PAGE_PDP_ATTR\r |
e60af8a1 | 93 | mov dword[PT_ADDR (0x101C)], edx\r |
c90e37b5 JJ |
94 | \r |
95 | ;\r | |
96 | ; Page Table Entries (2048 * 2MB entries => 4GB)\r | |
97 | ;\r | |
98 | mov ecx, 0x800\r | |
99 | pageTableEntriesLoop:\r | |
100 | mov eax, ecx\r | |
101 | dec eax\r | |
102 | shl eax, 21\r | |
103 | add eax, PAGE_2M_PDE_ATTR\r | |
73d66c58 | 104 | mov [ecx * 8 + PT_ADDR (0x2000 - 8)], eax\r |
e60af8a1 | 105 | mov [(ecx * 8 + PT_ADDR (0x2000 - 8)) + 4], edx\r |
c90e37b5 JJ |
106 | loop pageTableEntriesLoop\r |
107 | \r | |
a91b700e | 108 | OneTimeCall IsSevEsEnabled\r |
6995a1b7 TL |
109 | test eax, eax\r |
110 | jz SetCr3\r | |
111 | \r | |
112 | ;\r | |
113 | ; The initial GHCB will live at GHCB_BASE and needs to be un-encrypted.\r | |
114 | ; This requires the 2MB page for this range be broken down into 512 4KB\r | |
115 | ; pages. All will be marked encrypted, except for the GHCB.\r | |
116 | ;\r | |
117 | mov ecx, (GHCB_BASE >> 21)\r | |
118 | mov eax, GHCB_PT_ADDR + PAGE_PDP_ATTR\r | |
119 | mov [ecx * 8 + PT_ADDR (0x2000)], eax\r | |
120 | \r | |
121 | ;\r | |
122 | ; Page Table Entries (512 * 4KB entries => 2MB)\r | |
123 | ;\r | |
124 | mov ecx, 512\r | |
125 | pageTableEntries4kLoop:\r | |
126 | mov eax, ecx\r | |
127 | dec eax\r | |
128 | shl eax, 12\r | |
129 | add eax, GHCB_BASE & 0xFFE0_0000\r | |
130 | add eax, PAGE_4K_PDE_ATTR\r | |
131 | mov [ecx * 8 + GHCB_PT_ADDR - 8], eax\r | |
132 | mov [(ecx * 8 + GHCB_PT_ADDR - 8) + 4], edx\r | |
133 | loop pageTableEntries4kLoop\r | |
134 | \r | |
135 | ;\r | |
136 | ; Clear the encryption bit from the GHCB entry\r | |
137 | ;\r | |
138 | mov ecx, (GHCB_BASE & 0x1F_FFFF) >> 12\r | |
139 | mov [ecx * 8 + GHCB_PT_ADDR + 4], strict dword 0\r | |
140 | \r | |
141 | mov ecx, GHCB_SIZE / 4\r | |
142 | xor eax, eax\r | |
143 | clearGhcbMemoryLoop:\r | |
144 | mov dword[ecx * 4 + GHCB_BASE - 4], eax\r | |
145 | loop clearGhcbMemoryLoop\r | |
146 | \r | |
147 | SetCr3:\r | |
c90e37b5 JJ |
148 | ;\r |
149 | ; Set CR3 now that the paging structures are available\r | |
150 | ;\r | |
73d66c58 | 151 | mov eax, PT_ADDR (0)\r |
c90e37b5 JJ |
152 | mov cr3, eax\r |
153 | \r | |
154 | OneTimeCallRet SetCr3ForPageTables64\r |