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1 | /**@file\r |
2 | Memory Detection for Virtual Machines.\r | |
3 | \r | |
4 | Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>\r | |
5 | Copyright (c) 2019, Citrix Systems, Inc.\r | |
6 | \r | |
7 | SPDX-License-Identifier: BSD-2-Clause-Patent\r | |
8 | \r | |
9 | Module Name:\r | |
10 | \r | |
11 | MemDetect.c\r | |
12 | \r | |
13 | **/\r | |
14 | \r | |
15 | //\r | |
16 | // The package level header files this module uses\r | |
17 | //\r | |
18 | #include <IndustryStandard/Q35MchIch9.h>\r | |
19 | #include <PiPei.h>\r | |
20 | \r | |
21 | //\r | |
22 | // The Library classes this module consumes\r | |
23 | //\r | |
24 | #include <Library/BaseLib.h>\r | |
25 | #include <Library/BaseMemoryLib.h>\r | |
26 | #include <Library/DebugLib.h>\r | |
27 | #include <Library/HobLib.h>\r | |
28 | #include <Library/IoLib.h>\r | |
29 | #include <Library/PcdLib.h>\r | |
30 | #include <Library/PciLib.h>\r | |
31 | #include <Library/PeimEntryPoint.h>\r | |
32 | #include <Library/ResourcePublicationLib.h>\r | |
33 | \r | |
34 | #include "Platform.h"\r | |
35 | #include "Cmos.h"\r | |
36 | \r | |
37 | UINT8 mPhysMemAddressWidth;\r | |
38 | \r | |
39 | STATIC UINT32 mS3AcpiReservedMemoryBase;\r | |
40 | STATIC UINT32 mS3AcpiReservedMemorySize;\r | |
41 | \r | |
42 | STATIC UINT16 mQ35TsegMbytes;\r | |
43 | \r | |
44 | VOID\r | |
45 | Q35TsegMbytesInitialization (\r | |
46 | VOID\r | |
47 | )\r | |
48 | {\r | |
49 | UINT16 ExtendedTsegMbytes;\r | |
50 | RETURN_STATUS PcdStatus;\r | |
51 | \r | |
52 | if (mHostBridgeDevId != INTEL_Q35_MCH_DEVICE_ID) {\r | |
53 | DEBUG ((\r | |
54 | DEBUG_ERROR,\r | |
55 | "%a: no TSEG (SMRAM) on host bridge DID=0x%04x; "\r | |
56 | "only DID=0x%04x (Q35) is supported\n",\r | |
57 | __FUNCTION__,\r | |
58 | mHostBridgeDevId,\r | |
59 | INTEL_Q35_MCH_DEVICE_ID\r | |
60 | ));\r | |
61 | ASSERT (FALSE);\r | |
62 | CpuDeadLoop ();\r | |
63 | }\r | |
64 | \r | |
65 | //\r | |
66 | // Check if QEMU offers an extended TSEG.\r | |
67 | //\r | |
68 | // This can be seen from writing MCH_EXT_TSEG_MB_QUERY to the MCH_EXT_TSEG_MB\r | |
69 | // register, and reading back the register.\r | |
70 | //\r | |
71 | // On a QEMU machine type that does not offer an extended TSEG, the initial\r | |
72 | // write overwrites whatever value a malicious guest OS may have placed in\r | |
73 | // the (unimplemented) register, before entering S3 or rebooting.\r | |
74 | // Subsequently, the read returns MCH_EXT_TSEG_MB_QUERY unchanged.\r | |
75 | //\r | |
76 | // On a QEMU machine type that offers an extended TSEG, the initial write\r | |
77 | // triggers an update to the register. Subsequently, the value read back\r | |
78 | // (which is guaranteed to differ from MCH_EXT_TSEG_MB_QUERY) tells us the\r | |
79 | // number of megabytes.\r | |
80 | //\r | |
81 | PciWrite16 (DRAMC_REGISTER_Q35 (MCH_EXT_TSEG_MB), MCH_EXT_TSEG_MB_QUERY);\r | |
82 | ExtendedTsegMbytes = PciRead16 (DRAMC_REGISTER_Q35 (MCH_EXT_TSEG_MB));\r | |
83 | if (ExtendedTsegMbytes == MCH_EXT_TSEG_MB_QUERY) {\r | |
84 | mQ35TsegMbytes = PcdGet16 (PcdQ35TsegMbytes);\r | |
85 | return;\r | |
86 | }\r | |
87 | \r | |
88 | DEBUG ((\r | |
89 | DEBUG_INFO,\r | |
90 | "%a: QEMU offers an extended TSEG (%d MB)\n",\r | |
91 | __FUNCTION__,\r | |
92 | ExtendedTsegMbytes\r | |
93 | ));\r | |
94 | PcdStatus = PcdSet16S (PcdQ35TsegMbytes, ExtendedTsegMbytes);\r | |
95 | ASSERT_RETURN_ERROR (PcdStatus);\r | |
96 | mQ35TsegMbytes = ExtendedTsegMbytes;\r | |
97 | }\r | |
98 | \r | |
99 | \r | |
100 | UINT32\r | |
101 | GetSystemMemorySizeBelow4gb (\r | |
102 | VOID\r | |
103 | )\r | |
104 | {\r | |
105 | UINT8 Cmos0x34;\r | |
106 | UINT8 Cmos0x35;\r | |
107 | \r | |
108 | //\r | |
109 | // CMOS 0x34/0x35 specifies the system memory above 16 MB.\r | |
110 | // * CMOS(0x35) is the high byte\r | |
111 | // * CMOS(0x34) is the low byte\r | |
112 | // * The size is specified in 64kb chunks\r | |
113 | // * Since this is memory above 16MB, the 16MB must be added\r | |
114 | // into the calculation to get the total memory size.\r | |
115 | //\r | |
116 | \r | |
117 | Cmos0x34 = (UINT8) CmosRead8 (0x34);\r | |
118 | Cmos0x35 = (UINT8) CmosRead8 (0x35);\r | |
119 | \r | |
120 | return (UINT32) (((UINTN)((Cmos0x35 << 8) + Cmos0x34) << 16) + SIZE_16MB);\r | |
121 | }\r | |
122 | \r | |
123 | \r | |
124 | STATIC\r | |
125 | UINT64\r | |
126 | GetSystemMemorySizeAbove4gb (\r | |
127 | )\r | |
128 | {\r | |
129 | UINT32 Size;\r | |
130 | UINTN CmosIndex;\r | |
131 | \r | |
132 | //\r | |
133 | // CMOS 0x5b-0x5d specifies the system memory above 4GB MB.\r | |
134 | // * CMOS(0x5d) is the most significant size byte\r | |
135 | // * CMOS(0x5c) is the middle size byte\r | |
136 | // * CMOS(0x5b) is the least significant size byte\r | |
137 | // * The size is specified in 64kb chunks\r | |
138 | //\r | |
139 | \r | |
140 | Size = 0;\r | |
141 | for (CmosIndex = 0x5d; CmosIndex >= 0x5b; CmosIndex--) {\r | |
142 | Size = (UINT32) (Size << 8) + (UINT32) CmosRead8 (CmosIndex);\r | |
143 | }\r | |
144 | \r | |
145 | return LShiftU64 (Size, 16);\r | |
146 | }\r | |
147 | \r | |
148 | \r | |
149 | /**\r | |
150 | Return the highest address that DXE could possibly use, plus one.\r | |
151 | **/\r | |
152 | STATIC\r | |
153 | UINT64\r | |
154 | GetFirstNonAddress (\r | |
155 | VOID\r | |
156 | )\r | |
157 | {\r | |
158 | UINT64 FirstNonAddress;\r | |
159 | UINT64 Pci64Base, Pci64Size;\r | |
160 | RETURN_STATUS PcdStatus;\r | |
161 | \r | |
162 | FirstNonAddress = BASE_4GB + GetSystemMemorySizeAbove4gb ();\r | |
163 | \r | |
164 | //\r | |
165 | // If DXE is 32-bit, then we're done; PciBusDxe will degrade 64-bit MMIO\r | |
166 | // resources to 32-bit anyway. See DegradeResource() in\r | |
167 | // "PciResourceSupport.c".\r | |
168 | //\r | |
169 | #ifdef MDE_CPU_IA32\r | |
170 | if (!FeaturePcdGet (PcdDxeIplSwitchToLongMode)) {\r | |
171 | return FirstNonAddress;\r | |
172 | }\r | |
173 | #endif\r | |
174 | \r | |
175 | //\r | |
176 | // Otherwise, in order to calculate the highest address plus one, we must\r | |
177 | // consider the 64-bit PCI host aperture too. Fetch the default size.\r | |
178 | //\r | |
179 | Pci64Size = PcdGet64 (PcdPciMmio64Size);\r | |
180 | \r | |
181 | if (Pci64Size == 0) {\r | |
182 | if (mBootMode != BOOT_ON_S3_RESUME) {\r | |
183 | DEBUG ((DEBUG_INFO, "%a: disabling 64-bit PCI host aperture\n",\r | |
184 | __FUNCTION__));\r | |
185 | PcdStatus = PcdSet64S (PcdPciMmio64Size, 0);\r | |
186 | ASSERT_RETURN_ERROR (PcdStatus);\r | |
187 | }\r | |
188 | \r | |
189 | //\r | |
190 | // There's nothing more to do; the amount of memory above 4GB fully\r | |
191 | // determines the highest address plus one. The memory hotplug area (see\r | |
192 | // below) plays no role for the firmware in this case.\r | |
193 | //\r | |
194 | return FirstNonAddress;\r | |
195 | }\r | |
196 | \r | |
197 | //\r | |
198 | // SeaBIOS aligns both boundaries of the 64-bit PCI host aperture to 1GB, so\r | |
199 | // that the host can map it with 1GB hugepages. Follow suit.\r | |
200 | //\r | |
201 | Pci64Base = ALIGN_VALUE (FirstNonAddress, (UINT64)SIZE_1GB);\r | |
202 | Pci64Size = ALIGN_VALUE (Pci64Size, (UINT64)SIZE_1GB);\r | |
203 | \r | |
204 | //\r | |
205 | // The 64-bit PCI host aperture should also be "naturally" aligned. The\r | |
206 | // alignment is determined by rounding the size of the aperture down to the\r | |
207 | // next smaller or equal power of two. That is, align the aperture by the\r | |
208 | // largest BAR size that can fit into it.\r | |
209 | //\r | |
210 | Pci64Base = ALIGN_VALUE (Pci64Base, GetPowerOfTwo64 (Pci64Size));\r | |
211 | \r | |
212 | if (mBootMode != BOOT_ON_S3_RESUME) {\r | |
213 | //\r | |
214 | // The core PciHostBridgeDxe driver will automatically add this range to\r | |
215 | // the GCD memory space map through our PciHostBridgeLib instance; here we\r | |
216 | // only need to set the PCDs.\r | |
217 | //\r | |
218 | PcdStatus = PcdSet64S (PcdPciMmio64Base, Pci64Base);\r | |
219 | ASSERT_RETURN_ERROR (PcdStatus);\r | |
220 | PcdStatus = PcdSet64S (PcdPciMmio64Size, Pci64Size);\r | |
221 | ASSERT_RETURN_ERROR (PcdStatus);\r | |
222 | \r | |
223 | DEBUG ((DEBUG_INFO, "%a: Pci64Base=0x%Lx Pci64Size=0x%Lx\n",\r | |
224 | __FUNCTION__, Pci64Base, Pci64Size));\r | |
225 | }\r | |
226 | \r | |
227 | //\r | |
228 | // The useful address space ends with the 64-bit PCI host aperture.\r | |
229 | //\r | |
230 | FirstNonAddress = Pci64Base + Pci64Size;\r | |
231 | return FirstNonAddress;\r | |
232 | }\r | |
233 | \r | |
234 | \r | |
235 | /**\r | |
236 | Initialize the mPhysMemAddressWidth variable, based on guest RAM size.\r | |
237 | **/\r | |
238 | VOID\r | |
239 | AddressWidthInitialization (\r | |
240 | VOID\r | |
241 | )\r | |
242 | {\r | |
243 | UINT64 FirstNonAddress;\r | |
244 | \r | |
245 | //\r | |
246 | // As guest-physical memory size grows, the permanent PEI RAM requirements\r | |
247 | // are dominated by the identity-mapping page tables built by the DXE IPL.\r | |
248 | // The DXL IPL keys off of the physical address bits advertized in the CPU\r | |
249 | // HOB. To conserve memory, we calculate the minimum address width here.\r | |
250 | //\r | |
251 | FirstNonAddress = GetFirstNonAddress ();\r | |
252 | mPhysMemAddressWidth = (UINT8)HighBitSet64 (FirstNonAddress);\r | |
253 | \r | |
254 | //\r | |
255 | // If FirstNonAddress is not an integral power of two, then we need an\r | |
256 | // additional bit.\r | |
257 | //\r | |
258 | if ((FirstNonAddress & (FirstNonAddress - 1)) != 0) {\r | |
259 | ++mPhysMemAddressWidth;\r | |
260 | }\r | |
261 | \r | |
262 | //\r | |
263 | // The minimum address width is 36 (covers up to and excluding 64 GB, which\r | |
264 | // is the maximum for Ia32 + PAE). The theoretical architecture maximum for\r | |
265 | // X64 long mode is 52 bits, but the DXE IPL clamps that down to 48 bits. We\r | |
266 | // can simply assert that here, since 48 bits are good enough for 256 TB.\r | |
267 | //\r | |
268 | if (mPhysMemAddressWidth <= 36) {\r | |
269 | mPhysMemAddressWidth = 36;\r | |
270 | }\r | |
271 | ASSERT (mPhysMemAddressWidth <= 48);\r | |
272 | }\r | |
273 | \r | |
274 | \r | |
275 | /**\r | |
276 | Calculate the cap for the permanent PEI memory.\r | |
277 | **/\r | |
278 | STATIC\r | |
279 | UINT32\r | |
280 | GetPeiMemoryCap (\r | |
281 | VOID\r | |
282 | )\r | |
283 | {\r | |
284 | BOOLEAN Page1GSupport;\r | |
285 | UINT32 RegEax;\r | |
286 | UINT32 RegEdx;\r | |
287 | UINT32 Pml4Entries;\r | |
288 | UINT32 PdpEntries;\r | |
289 | UINTN TotalPages;\r | |
290 | \r | |
291 | //\r | |
292 | // If DXE is 32-bit, then just return the traditional 64 MB cap.\r | |
293 | //\r | |
294 | #ifdef MDE_CPU_IA32\r | |
295 | if (!FeaturePcdGet (PcdDxeIplSwitchToLongMode)) {\r | |
296 | return SIZE_64MB;\r | |
297 | }\r | |
298 | #endif\r | |
299 | \r | |
300 | //\r | |
301 | // Dependent on physical address width, PEI memory allocations can be\r | |
302 | // dominated by the page tables built for 64-bit DXE. So we key the cap off\r | |
303 | // of those. The code below is based on CreateIdentityMappingPageTables() in\r | |
304 | // "MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c".\r | |
305 | //\r | |
306 | Page1GSupport = FALSE;\r | |
307 | if (PcdGetBool (PcdUse1GPageTable)) {\r | |
308 | AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL);\r | |
309 | if (RegEax >= 0x80000001) {\r | |
310 | AsmCpuid (0x80000001, NULL, NULL, NULL, &RegEdx);\r | |
311 | if ((RegEdx & BIT26) != 0) {\r | |
312 | Page1GSupport = TRUE;\r | |
313 | }\r | |
314 | }\r | |
315 | }\r | |
316 | \r | |
317 | if (mPhysMemAddressWidth <= 39) {\r | |
318 | Pml4Entries = 1;\r | |
319 | PdpEntries = 1 << (mPhysMemAddressWidth - 30);\r | |
320 | ASSERT (PdpEntries <= 0x200);\r | |
321 | } else {\r | |
322 | Pml4Entries = 1 << (mPhysMemAddressWidth - 39);\r | |
323 | ASSERT (Pml4Entries <= 0x200);\r | |
324 | PdpEntries = 512;\r | |
325 | }\r | |
326 | \r | |
327 | TotalPages = Page1GSupport ? Pml4Entries + 1 :\r | |
328 | (PdpEntries + 1) * Pml4Entries + 1;\r | |
329 | ASSERT (TotalPages <= 0x40201);\r | |
330 | \r | |
331 | //\r | |
332 | // Add 64 MB for miscellaneous allocations. Note that for\r | |
333 | // mPhysMemAddressWidth values close to 36, the cap will actually be\r | |
334 | // dominated by this increment.\r | |
335 | //\r | |
336 | return (UINT32)(EFI_PAGES_TO_SIZE (TotalPages) + SIZE_64MB);\r | |
337 | }\r | |
338 | \r | |
339 | \r | |
340 | /**\r | |
341 | Publish PEI core memory\r | |
342 | \r | |
343 | @return EFI_SUCCESS The PEIM initialized successfully.\r | |
344 | \r | |
345 | **/\r | |
346 | EFI_STATUS\r | |
347 | PublishPeiMemory (\r | |
348 | VOID\r | |
349 | )\r | |
350 | {\r | |
351 | EFI_STATUS Status;\r | |
352 | EFI_PHYSICAL_ADDRESS MemoryBase;\r | |
353 | UINT64 MemorySize;\r | |
354 | UINT32 LowerMemorySize;\r | |
355 | UINT32 PeiMemoryCap;\r | |
356 | \r | |
357 | LowerMemorySize = GetSystemMemorySizeBelow4gb ();\r | |
358 | \r | |
359 | if (mBootMode == BOOT_ON_S3_RESUME) {\r | |
360 | MemoryBase = mS3AcpiReservedMemoryBase;\r | |
361 | MemorySize = mS3AcpiReservedMemorySize;\r | |
362 | } else {\r | |
363 | PeiMemoryCap = GetPeiMemoryCap ();\r | |
364 | DEBUG ((DEBUG_INFO, "%a: mPhysMemAddressWidth=%d PeiMemoryCap=%u KB\n",\r | |
365 | __FUNCTION__, mPhysMemAddressWidth, PeiMemoryCap >> 10));\r | |
366 | \r | |
367 | //\r | |
368 | // Determine the range of memory to use during PEI\r | |
369 | //\r | |
370 | MemoryBase =\r | |
371 | PcdGet32 (PcdOvmfDxeMemFvBase) + PcdGet32 (PcdOvmfDxeMemFvSize);\r | |
372 | MemorySize = LowerMemorySize - MemoryBase;\r | |
373 | if (MemorySize > PeiMemoryCap) {\r | |
374 | MemoryBase = LowerMemorySize - PeiMemoryCap;\r | |
375 | MemorySize = PeiMemoryCap;\r | |
376 | }\r | |
377 | }\r | |
378 | \r | |
379 | //\r | |
380 | // Publish this memory to the PEI Core\r | |
381 | //\r | |
382 | Status = PublishSystemMemory(MemoryBase, MemorySize);\r | |
383 | ASSERT_EFI_ERROR (Status);\r | |
384 | \r | |
385 | return Status;\r | |
386 | }\r | |
387 | \r | |
388 | \r | |
389 | /**\r | |
390 | Publish system RAM and reserve memory regions\r | |
391 | \r | |
392 | **/\r | |
393 | VOID\r | |
394 | InitializeRamRegions (\r | |
395 | VOID\r | |
396 | )\r | |
397 | {\r | |
398 | XenPublishRamRegions ();\r | |
399 | \r | |
400 | if (mBootMode != BOOT_ON_S3_RESUME) {\r | |
401 | //\r | |
402 | // Reserve the lock box storage area\r | |
403 | //\r | |
404 | // Since this memory range will be used on S3 resume, it must be\r | |
405 | // reserved as ACPI NVS.\r | |
406 | //\r | |
407 | // If S3 is unsupported, then various drivers might still write to the\r | |
408 | // LockBox area. We ought to prevent DXE from serving allocation requests\r | |
409 | // such that they would overlap the LockBox storage.\r | |
410 | //\r | |
411 | ZeroMem (\r | |
412 | (VOID*)(UINTN) PcdGet32 (PcdOvmfLockBoxStorageBase),\r | |
413 | (UINTN) PcdGet32 (PcdOvmfLockBoxStorageSize)\r | |
414 | );\r | |
415 | BuildMemoryAllocationHob (\r | |
416 | (EFI_PHYSICAL_ADDRESS)(UINTN) PcdGet32 (PcdOvmfLockBoxStorageBase),\r | |
417 | (UINT64)(UINTN) PcdGet32 (PcdOvmfLockBoxStorageSize),\r | |
418 | EfiBootServicesData\r | |
419 | );\r | |
420 | }\r | |
421 | }\r |