OvmfPkg/XenPlatformPei/MemDetect.c

   1 /**@file
   2   Memory Detection for Virtual Machines.
   3
   4   Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>
   5   Copyright (c) 2019, Citrix Systems, Inc.
   6
   7   SPDX-License-Identifier: BSD-2-Clause-Patent
   8
   9 Module Name:
  10
  11   MemDetect.c
  12
  13 **/
  14
  15 //
  16 // The package level header files this module uses
  17 //
  18 #include <IndustryStandard/Q35MchIch9.h>
  19 #include <PiPei.h>
  20
  21 //
  22 // The Library classes this module consumes
  23 //
  24 #include <Library/BaseLib.h>
  25 #include <Library/BaseMemoryLib.h>
  26 #include <Library/DebugLib.h>
  27 #include <Library/HobLib.h>
  28 #include <Library/IoLib.h>
  29 #include <Library/PcdLib.h>
  30 #include <Library/PciLib.h>
  31 #include <Library/PeimEntryPoint.h>
  32 #include <Library/ResourcePublicationLib.h>
  33
  34 #include "Platform.h"
  35 #include "Cmos.h"
  36
  37 UINT8 mPhysMemAddressWidth;
  38
  39 STATIC UINT32 mS3AcpiReservedMemoryBase;
  40 STATIC UINT32 mS3AcpiReservedMemorySize;
  41
  42 STATIC UINT16 mQ35TsegMbytes;
  43
  44 VOID
  45 Q35TsegMbytesInitialization (
  46   VOID
  47   )
  48 {
  49   UINT16        ExtendedTsegMbytes;
  50   RETURN_STATUS PcdStatus;
  51
  52   if (mHostBridgeDevId != INTEL_Q35_MCH_DEVICE_ID) {
  53     DEBUG ((
  54       DEBUG_ERROR,
  55       "%a: no TSEG (SMRAM) on host bridge DID=0x%04x; "
  56       "only DID=0x%04x (Q35) is supported\n",
  57       __FUNCTION__,
  58       mHostBridgeDevId,
  59       INTEL_Q35_MCH_DEVICE_ID
  60       ));
  61     ASSERT (FALSE);
  62     CpuDeadLoop ();
  63   }
  64
  65   //
  66   // Check if QEMU offers an extended TSEG.
  67   //
  68   // This can be seen from writing MCH_EXT_TSEG_MB_QUERY to the MCH_EXT_TSEG_MB
  69   // register, and reading back the register.
  70   //
  71   // On a QEMU machine type that does not offer an extended TSEG, the initial
  72   // write overwrites whatever value a malicious guest OS may have placed in
  73   // the (unimplemented) register, before entering S3 or rebooting.
  74   // Subsequently, the read returns MCH_EXT_TSEG_MB_QUERY unchanged.
  75   //
  76   // On a QEMU machine type that offers an extended TSEG, the initial write
  77   // triggers an update to the register. Subsequently, the value read back
  78   // (which is guaranteed to differ from MCH_EXT_TSEG_MB_QUERY) tells us the
  79   // number of megabytes.
  80   //
  81   PciWrite16 (DRAMC_REGISTER_Q35 (MCH_EXT_TSEG_MB), MCH_EXT_TSEG_MB_QUERY);
  82   ExtendedTsegMbytes = PciRead16 (DRAMC_REGISTER_Q35 (MCH_EXT_TSEG_MB));
  83   if (ExtendedTsegMbytes == MCH_EXT_TSEG_MB_QUERY) {
  84     mQ35TsegMbytes = PcdGet16 (PcdQ35TsegMbytes);
  85     return;
  86   }
  87
  88   DEBUG ((
  89     DEBUG_INFO,
  90     "%a: QEMU offers an extended TSEG (%d MB)\n",
  91     __FUNCTION__,
  92     ExtendedTsegMbytes
  93     ));
  94   PcdStatus = PcdSet16S (PcdQ35TsegMbytes, ExtendedTsegMbytes);
  95   ASSERT_RETURN_ERROR (PcdStatus);
  96   mQ35TsegMbytes = ExtendedTsegMbytes;
  97 }
  98
  99
 100 UINT32
 101 GetSystemMemorySizeBelow4gb (
 102   VOID
 103   )
 104 {
 105   UINT8 Cmos0x34;
 106   UINT8 Cmos0x35;
 107
 108   //
 109   // CMOS 0x34/0x35 specifies the system memory above 16 MB.
 110   // * CMOS(0x35) is the high byte
 111   // * CMOS(0x34) is the low byte
 112   // * The size is specified in 64kb chunks
 113   // * Since this is memory above 16MB, the 16MB must be added
 114   //   into the calculation to get the total memory size.
 115   //
 116
 117   Cmos0x34 = (UINT8) CmosRead8 (0x34);
 118   Cmos0x35 = (UINT8) CmosRead8 (0x35);
 119
 120   return (UINT32) (((UINTN)((Cmos0x35 << 8) + Cmos0x34) << 16) + SIZE_16MB);
 121 }
 122
 123
 124 STATIC
 125 UINT64
 126 GetSystemMemorySizeAbove4gb (
 127   )
 128 {
 129   UINT32 Size;
 130   UINTN  CmosIndex;
 131
 132   //
 133   // CMOS 0x5b-0x5d specifies the system memory above 4GB MB.
 134   // * CMOS(0x5d) is the most significant size byte
 135   // * CMOS(0x5c) is the middle size byte
 136   // * CMOS(0x5b) is the least significant size byte
 137   // * The size is specified in 64kb chunks
 138   //
 139
 140   Size = 0;
 141   for (CmosIndex = 0x5d; CmosIndex >= 0x5b; CmosIndex--) {
 142     Size = (UINT32) (Size << 8) + (UINT32) CmosRead8 (CmosIndex);
 143   }
 144
 145   return LShiftU64 (Size, 16);
 146 }
 147
 148
 149 /**
 150   Return the highest address that DXE could possibly use, plus one.
 151 **/
 152 STATIC
 153 UINT64
 154 GetFirstNonAddress (
 155   VOID
 156   )
 157 {
 158   UINT64               FirstNonAddress;
 159   UINT64               Pci64Base, Pci64Size;
 160   RETURN_STATUS        PcdStatus;
 161
 162   FirstNonAddress = BASE_4GB + GetSystemMemorySizeAbove4gb ();
 163
 164   //
 165   // If DXE is 32-bit, then we're done; PciBusDxe will degrade 64-bit MMIO
 166   // resources to 32-bit anyway. See DegradeResource() in
 167   // "PciResourceSupport.c".
 168   //
 169 #ifdef MDE_CPU_IA32
 170   if (!FeaturePcdGet (PcdDxeIplSwitchToLongMode)) {
 171     return FirstNonAddress;
 172   }
 173 #endif
 174
 175   //
 176   // Otherwise, in order to calculate the highest address plus one, we must
 177   // consider the 64-bit PCI host aperture too. Fetch the default size.
 178   //
 179   Pci64Size = PcdGet64 (PcdPciMmio64Size);
 180
 181   if (Pci64Size == 0) {
 182     if (mBootMode != BOOT_ON_S3_RESUME) {
 183       DEBUG ((DEBUG_INFO, "%a: disabling 64-bit PCI host aperture\n",
 184         __FUNCTION__));
 185       PcdStatus = PcdSet64S (PcdPciMmio64Size, 0);
 186       ASSERT_RETURN_ERROR (PcdStatus);
 187     }
 188
 189     //
 190     // There's nothing more to do; the amount of memory above 4GB fully
 191     // determines the highest address plus one. The memory hotplug area (see
 192     // below) plays no role for the firmware in this case.
 193     //
 194     return FirstNonAddress;
 195   }
 196
 197   //
 198   // SeaBIOS aligns both boundaries of the 64-bit PCI host aperture to 1GB, so
 199   // that the host can map it with 1GB hugepages. Follow suit.
 200   //
 201   Pci64Base = ALIGN_VALUE (FirstNonAddress, (UINT64)SIZE_1GB);
 202   Pci64Size = ALIGN_VALUE (Pci64Size, (UINT64)SIZE_1GB);
 203
 204   //
 205   // The 64-bit PCI host aperture should also be "naturally" aligned. The
 206   // alignment is determined by rounding the size of the aperture down to the
 207   // next smaller or equal power of two. That is, align the aperture by the
 208   // largest BAR size that can fit into it.
 209   //
 210   Pci64Base = ALIGN_VALUE (Pci64Base, GetPowerOfTwo64 (Pci64Size));
 211
 212   if (mBootMode != BOOT_ON_S3_RESUME) {
 213     //
 214     // The core PciHostBridgeDxe driver will automatically add this range to
 215     // the GCD memory space map through our PciHostBridgeLib instance; here we
 216     // only need to set the PCDs.
 217     //
 218     PcdStatus = PcdSet64S (PcdPciMmio64Base, Pci64Base);
 219     ASSERT_RETURN_ERROR (PcdStatus);
 220     PcdStatus = PcdSet64S (PcdPciMmio64Size, Pci64Size);
 221     ASSERT_RETURN_ERROR (PcdStatus);
 222
 223     DEBUG ((DEBUG_INFO, "%a: Pci64Base=0x%Lx Pci64Size=0x%Lx\n",
 224       __FUNCTION__, Pci64Base, Pci64Size));
 225   }
 226
 227   //
 228   // The useful address space ends with the 64-bit PCI host aperture.
 229   //
 230   FirstNonAddress = Pci64Base + Pci64Size;
 231   return FirstNonAddress;
 232 }
 233
 234
 235 /**
 236   Initialize the mPhysMemAddressWidth variable, based on guest RAM size.
 237 **/
 238 VOID
 239 AddressWidthInitialization (
 240   VOID
 241   )
 242 {
 243   UINT64 FirstNonAddress;
 244
 245   //
 246   // As guest-physical memory size grows, the permanent PEI RAM requirements
 247   // are dominated by the identity-mapping page tables built by the DXE IPL.
 248   // The DXL IPL keys off of the physical address bits advertized in the CPU
 249   // HOB. To conserve memory, we calculate the minimum address width here.
 250   //
 251   FirstNonAddress      = GetFirstNonAddress ();
 252   mPhysMemAddressWidth = (UINT8)HighBitSet64 (FirstNonAddress);
 253
 254   //
 255   // If FirstNonAddress is not an integral power of two, then we need an
 256   // additional bit.
 257   //
 258   if ((FirstNonAddress & (FirstNonAddress - 1)) != 0) {
 259     ++mPhysMemAddressWidth;
 260   }
 261
 262   //
 263   // The minimum address width is 36 (covers up to and excluding 64 GB, which
 264   // is the maximum for Ia32 + PAE). The theoretical architecture maximum for
 265   // X64 long mode is 52 bits, but the DXE IPL clamps that down to 48 bits. We
 266   // can simply assert that here, since 48 bits are good enough for 256 TB.
 267   //
 268   if (mPhysMemAddressWidth <= 36) {
 269     mPhysMemAddressWidth = 36;
 270   }
 271   ASSERT (mPhysMemAddressWidth <= 48);
 272 }
 273
 274
 275 /**
 276   Calculate the cap for the permanent PEI memory.
 277 **/
 278 STATIC
 279 UINT32
 280 GetPeiMemoryCap (
 281   VOID
 282   )
 283 {
 284   BOOLEAN Page1GSupport;
 285   UINT32  RegEax;
 286   UINT32  RegEdx;
 287   UINT32  Pml4Entries;
 288   UINT32  PdpEntries;
 289   UINTN   TotalPages;
 290
 291   //
 292   // If DXE is 32-bit, then just return the traditional 64 MB cap.
 293   //
 294 #ifdef MDE_CPU_IA32
 295   if (!FeaturePcdGet (PcdDxeIplSwitchToLongMode)) {
 296     return SIZE_64MB;
 297   }
 298 #endif
 299
 300   //
 301   // Dependent on physical address width, PEI memory allocations can be
 302   // dominated by the page tables built for 64-bit DXE. So we key the cap off
 303   // of those. The code below is based on CreateIdentityMappingPageTables() in
 304   // "MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c".
 305   //
 306   Page1GSupport = FALSE;
 307   if (PcdGetBool (PcdUse1GPageTable)) {
 308     AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL);
 309     if (RegEax >= 0x80000001) {
 310       AsmCpuid (0x80000001, NULL, NULL, NULL, &RegEdx);
 311       if ((RegEdx & BIT26) != 0) {
 312         Page1GSupport = TRUE;
 313       }
 314     }
 315   }
 316
 317   if (mPhysMemAddressWidth <= 39) {
 318     Pml4Entries = 1;
 319     PdpEntries = 1 << (mPhysMemAddressWidth - 30);
 320     ASSERT (PdpEntries <= 0x200);
 321   } else {
 322     Pml4Entries = 1 << (mPhysMemAddressWidth - 39);
 323     ASSERT (Pml4Entries <= 0x200);
 324     PdpEntries = 512;
 325   }
 326
 327   TotalPages = Page1GSupport ? Pml4Entries + 1 :
 328                                (PdpEntries + 1) * Pml4Entries + 1;
 329   ASSERT (TotalPages <= 0x40201);
 330
 331   //
 332   // Add 64 MB for miscellaneous allocations. Note that for
 333   // mPhysMemAddressWidth values close to 36, the cap will actually be
 334   // dominated by this increment.
 335   //
 336   return (UINT32)(EFI_PAGES_TO_SIZE (TotalPages) + SIZE_64MB);
 337 }
 338
 339
 340 /**
 341   Publish PEI core memory
 342
 343   @return EFI_SUCCESS     The PEIM initialized successfully.
 344
 345 **/
 346 EFI_STATUS
 347 PublishPeiMemory (
 348   VOID
 349   )
 350 {
 351   EFI_STATUS                  Status;
 352   EFI_PHYSICAL_ADDRESS        MemoryBase;
 353   UINT64                      MemorySize;
 354   UINT32                      LowerMemorySize;
 355   UINT32                      PeiMemoryCap;
 356
 357   LowerMemorySize = GetSystemMemorySizeBelow4gb ();
 358
 359   if (mBootMode == BOOT_ON_S3_RESUME) {
 360     MemoryBase = mS3AcpiReservedMemoryBase;
 361     MemorySize = mS3AcpiReservedMemorySize;
 362   } else {
 363     PeiMemoryCap = GetPeiMemoryCap ();
 364     DEBUG ((DEBUG_INFO, "%a: mPhysMemAddressWidth=%d PeiMemoryCap=%u KB\n",
 365       __FUNCTION__, mPhysMemAddressWidth, PeiMemoryCap >> 10));
 366
 367     //
 368     // Determine the range of memory to use during PEI
 369     //
 370     MemoryBase =
 371       PcdGet32 (PcdOvmfDxeMemFvBase) + PcdGet32 (PcdOvmfDxeMemFvSize);
 372     MemorySize = LowerMemorySize - MemoryBase;
 373     if (MemorySize > PeiMemoryCap) {
 374       MemoryBase = LowerMemorySize - PeiMemoryCap;
 375       MemorySize = PeiMemoryCap;
 376     }
 377   }
 378
 379   //
 380   // Publish this memory to the PEI Core
 381   //
 382   Status = PublishSystemMemory(MemoryBase, MemorySize);
 383   ASSERT_EFI_ERROR (Status);
 384
 385   return Status;
 386 }
 387
 388
 389 /**
 390   Publish system RAM and reserve memory regions
 391
 392 **/
 393 VOID
 394 InitializeRamRegions (
 395   VOID
 396   )
 397 {
 398   XenPublishRamRegions ();
 399
 400   if (mBootMode != BOOT_ON_S3_RESUME) {
 401     //
 402     // Reserve the lock box storage area
 403     //
 404     // Since this memory range will be used on S3 resume, it must be
 405     // reserved as ACPI NVS.
 406     //
 407     // If S3 is unsupported, then various drivers might still write to the
 408     // LockBox area. We ought to prevent DXE from serving allocation requests
 409     // such that they would overlap the LockBox storage.
 410     //
 411     ZeroMem (
 412       (VOID*)(UINTN) PcdGet32 (PcdOvmfLockBoxStorageBase),
 413       (UINTN) PcdGet32 (PcdOvmfLockBoxStorageSize)
 414       );
 415     BuildMemoryAllocationHob (
 416       (EFI_PHYSICAL_ADDRESS)(UINTN) PcdGet32 (PcdOvmfLockBoxStorageBase),
 417       (UINT64)(UINTN) PcdGet32 (PcdOvmfLockBoxStorageSize),
 418       EfiBootServicesData
 419       );
 420   }
 421 }