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Commit | Line | Data |
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dfaaa5a5 | 1 | /** @file\r |
1166d068 | 2 | This contains the installation function for the driver.\r |
47ca9c95 | 3 | \r |
5a702acd | 4 | Copyright (c) 2005 - 2018, Intel Corporation. All rights reserved.<BR>\r |
e1d302e5 | 5 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
1166d068 | 6 | \r |
7 | **/\r | |
8 | \r | |
9 | #include "8259.h"\r | |
10 | \r | |
1166d068 | 11 | //\r |
90b8b0ec | 12 | // Global for the Legacy 8259 Protocol that is produced by this driver\r |
1166d068 | 13 | //\r |
24115e44 | 14 | EFI_LEGACY_8259_PROTOCOL mInterrupt8259 = {\r |
1166d068 | 15 | Interrupt8259SetVectorBase,\r |
16 | Interrupt8259GetMask,\r | |
17 | Interrupt8259SetMask,\r | |
18 | Interrupt8259SetMode,\r | |
19 | Interrupt8259GetVector,\r | |
20 | Interrupt8259EnableIrq,\r | |
21 | Interrupt8259DisableIrq,\r | |
22 | Interrupt8259GetInterruptLine,\r | |
23 | Interrupt8259EndOfInterrupt\r | |
24 | };\r | |
25 | \r | |
26 | //\r | |
27 | // Global for the handle that the Legacy 8259 Protocol is installed\r | |
28 | //\r | |
29 | EFI_HANDLE m8259Handle = NULL;\r | |
30 | \r | |
31 | UINT8 mMasterBase = 0xff;\r | |
32 | UINT8 mSlaveBase = 0xff;\r | |
33 | EFI_8259_MODE mMode = Efi8259ProtectedMode;\r | |
34 | UINT16 mProtectedModeMask = 0xffff;\r | |
856f592c | 35 | UINT16 mLegacyModeMask;\r |
1166d068 | 36 | UINT16 mProtectedModeEdgeLevel = 0x0000;\r |
856f592c | 37 | UINT16 mLegacyModeEdgeLevel;\r |
1166d068 | 38 | \r |
39 | //\r | |
40 | // Worker Functions\r | |
41 | //\r | |
90b8b0ec | 42 | \r |
43 | /**\r | |
44 | Write to mask and edge/level triggered registers of master and slave PICs.\r | |
45 | \r | |
46 | @param[in] Mask low byte for master PIC mask register,\r | |
47 | high byte for slave PIC mask register.\r | |
48 | @param[in] EdgeLevel low byte for master PIC edge/level triggered register,\r | |
49 | high byte for slave PIC edge/level triggered register.\r | |
50 | \r | |
51 | **/\r | |
1166d068 | 52 | VOID\r |
53 | Interrupt8259WriteMask (\r | |
54 | IN UINT16 Mask,\r | |
55 | IN UINT16 EdgeLevel\r | |
56 | )\r | |
1166d068 | 57 | {\r |
58 | IoWrite8 (LEGACY_8259_MASK_REGISTER_MASTER, (UINT8) Mask);\r | |
59 | IoWrite8 (LEGACY_8259_MASK_REGISTER_SLAVE, (UINT8) (Mask >> 8));\r | |
60 | IoWrite8 (LEGACY_8259_EDGE_LEVEL_TRIGGERED_REGISTER_MASTER, (UINT8) EdgeLevel);\r | |
61 | IoWrite8 (LEGACY_8259_EDGE_LEVEL_TRIGGERED_REGISTER_SLAVE, (UINT8) (EdgeLevel >> 8));\r | |
62 | }\r | |
63 | \r | |
1166d068 | 64 | /**\r |
90b8b0ec | 65 | Read from mask and edge/level triggered registers of master and slave PICs.\r |
1166d068 | 66 | \r |
90b8b0ec | 67 | @param[out] Mask low byte for master PIC mask register,\r |
68 | high byte for slave PIC mask register.\r | |
69 | @param[out] EdgeLevel low byte for master PIC edge/level triggered register,\r | |
70 | high byte for slave PIC edge/level triggered register.\r | |
1166d068 | 71 | \r |
72 | **/\r | |
90b8b0ec | 73 | VOID\r |
74 | Interrupt8259ReadMask (\r | |
75 | OUT UINT16 *Mask,\r | |
76 | OUT UINT16 *EdgeLevel\r | |
77 | )\r | |
1166d068 | 78 | {\r |
a694b670 | 79 | UINT16 MasterValue;\r |
80 | UINT16 SlaveValue;\r | |
81 | \r | |
1166d068 | 82 | if (Mask != NULL) {\r |
a694b670 | 83 | MasterValue = IoRead8 (LEGACY_8259_MASK_REGISTER_MASTER);\r |
84 | SlaveValue = IoRead8 (LEGACY_8259_MASK_REGISTER_SLAVE);\r | |
85 | \r | |
86 | *Mask = (UINT16) (MasterValue | (SlaveValue << 8));\r | |
1166d068 | 87 | }\r |
88 | \r | |
89 | if (EdgeLevel != NULL) {\r | |
a694b670 | 90 | MasterValue = IoRead8 (LEGACY_8259_EDGE_LEVEL_TRIGGERED_REGISTER_MASTER);\r |
91 | SlaveValue = IoRead8 (LEGACY_8259_EDGE_LEVEL_TRIGGERED_REGISTER_SLAVE);\r | |
92 | \r | |
93 | *EdgeLevel = (UINT16) (MasterValue | (SlaveValue << 8));\r | |
1166d068 | 94 | }\r |
95 | }\r | |
90b8b0ec | 96 | \r |
1166d068 | 97 | //\r |
90b8b0ec | 98 | // Legacy 8259 Protocol Interface Functions\r |
1166d068 | 99 | //\r |
1166d068 | 100 | \r |
90b8b0ec | 101 | /**\r |
102 | Sets the base address for the 8259 master and slave PICs.\r | |
1166d068 | 103 | \r |
90b8b0ec | 104 | @param[in] This Indicates the EFI_LEGACY_8259_PROTOCOL instance.\r |
105 | @param[in] MasterBase Interrupt vectors for IRQ0-IRQ7.\r | |
106 | @param[in] SlaveBase Interrupt vectors for IRQ8-IRQ15.\r | |
1166d068 | 107 | \r |
90b8b0ec | 108 | @retval EFI_SUCCESS The 8259 PIC was programmed successfully.\r |
109 | @retval EFI_DEVICE_ERROR There was an error while writing to the 8259 PIC.\r | |
1166d068 | 110 | \r |
111 | **/\r | |
90b8b0ec | 112 | EFI_STATUS\r |
113 | EFIAPI\r | |
114 | Interrupt8259SetVectorBase (\r | |
115 | IN EFI_LEGACY_8259_PROTOCOL *This,\r | |
116 | IN UINT8 MasterBase,\r | |
117 | IN UINT8 SlaveBase\r | |
118 | )\r | |
1166d068 | 119 | {\r |
4fde0f15 | 120 | UINT8 Mask;\r |
121 | EFI_TPL OriginalTpl;\r | |
1166d068 | 122 | \r |
4fde0f15 | 123 | OriginalTpl = gBS->RaiseTPL (TPL_HIGH_LEVEL);\r |
90b8b0ec | 124 | //\r |
125 | // Set vector base for slave PIC\r | |
126 | //\r | |
1166d068 | 127 | if (SlaveBase != mSlaveBase) {\r |
128 | mSlaveBase = SlaveBase;\r | |
129 | \r | |
130 | //\r | |
90b8b0ec | 131 | // Initialization sequence is needed for setting vector base.\r |
132 | //\r | |
133 | \r | |
134 | //\r | |
135 | // Preserve interrtup mask register before initialization sequence\r | |
619ad10f | 136 | // because it will be cleared during initialization\r |
1166d068 | 137 | //\r |
138 | Mask = IoRead8 (LEGACY_8259_MASK_REGISTER_SLAVE);\r | |
90b8b0ec | 139 | \r |
140 | //\r | |
141 | // ICW1: cascade mode, ICW4 write required\r | |
142 | //\r | |
1166d068 | 143 | IoWrite8 (LEGACY_8259_CONTROL_REGISTER_SLAVE, 0x11);\r |
90b8b0ec | 144 | \r |
145 | //\r | |
146 | // ICW2: new vector base (must be multiple of 8)\r | |
147 | //\r | |
1166d068 | 148 | IoWrite8 (LEGACY_8259_MASK_REGISTER_SLAVE, mSlaveBase);\r |
90b8b0ec | 149 | \r |
150 | //\r | |
151 | // ICW3: slave indentification code must be 2\r | |
152 | //\r | |
1166d068 | 153 | IoWrite8 (LEGACY_8259_MASK_REGISTER_SLAVE, 0x02);\r |
90b8b0ec | 154 | \r |
155 | //\r | |
156 | // ICW4: fully nested mode, non-buffered mode, normal EOI, IA processor\r | |
157 | //\r | |
1166d068 | 158 | IoWrite8 (LEGACY_8259_MASK_REGISTER_SLAVE, 0x01);\r |
90b8b0ec | 159 | \r |
160 | //\r | |
161 | // Restore interrupt mask register\r | |
162 | //\r | |
1166d068 | 163 | IoWrite8 (LEGACY_8259_MASK_REGISTER_SLAVE, Mask);\r |
164 | }\r | |
165 | \r | |
90b8b0ec | 166 | //\r |
167 | // Set vector base for master PIC\r | |
168 | //\r | |
1166d068 | 169 | if (MasterBase != mMasterBase) {\r |
170 | mMasterBase = MasterBase;\r | |
171 | \r | |
172 | //\r | |
90b8b0ec | 173 | // Initialization sequence is needed for setting vector base.\r |
174 | //\r | |
175 | \r | |
176 | //\r | |
177 | // Preserve interrtup mask register before initialization sequence\r | |
619ad10f | 178 | // because it will be cleared during initialization\r |
1166d068 | 179 | //\r |
180 | Mask = IoRead8 (LEGACY_8259_MASK_REGISTER_MASTER);\r | |
90b8b0ec | 181 | \r |
182 | //\r | |
183 | // ICW1: cascade mode, ICW4 write required\r | |
184 | //\r | |
1166d068 | 185 | IoWrite8 (LEGACY_8259_CONTROL_REGISTER_MASTER, 0x11);\r |
90b8b0ec | 186 | \r |
187 | //\r | |
188 | // ICW2: new vector base (must be multiple of 8)\r | |
189 | //\r | |
1166d068 | 190 | IoWrite8 (LEGACY_8259_MASK_REGISTER_MASTER, mMasterBase);\r |
90b8b0ec | 191 | \r |
192 | //\r | |
193 | // ICW3: slave PIC is cascaded on IRQ2\r | |
194 | //\r | |
1166d068 | 195 | IoWrite8 (LEGACY_8259_MASK_REGISTER_MASTER, 0x04);\r |
90b8b0ec | 196 | \r |
197 | //\r | |
198 | // ICW4: fully nested mode, non-buffered mode, normal EOI, IA processor\r | |
199 | //\r | |
1166d068 | 200 | IoWrite8 (LEGACY_8259_MASK_REGISTER_MASTER, 0x01);\r |
90b8b0ec | 201 | \r |
202 | //\r | |
203 | // Restore interrupt mask register\r | |
204 | //\r | |
1166d068 | 205 | IoWrite8 (LEGACY_8259_MASK_REGISTER_MASTER, Mask);\r |
206 | }\r | |
207 | \r | |
ae6a37f0 | 208 | IoWrite8 (LEGACY_8259_CONTROL_REGISTER_SLAVE, LEGACY_8259_EOI);\r |
209 | IoWrite8 (LEGACY_8259_CONTROL_REGISTER_MASTER, LEGACY_8259_EOI);\r | |
5a702acd | 210 | \r |
4fde0f15 | 211 | gBS->RestoreTPL (OriginalTpl);\r |
1166d068 | 212 | \r |
213 | return EFI_SUCCESS;\r | |
214 | }\r | |
215 | \r | |
90b8b0ec | 216 | /**\r |
217 | Gets the current 16-bit real mode and 32-bit protected-mode IRQ masks.\r | |
218 | \r | |
219 | @param[in] This Indicates the EFI_LEGACY_8259_PROTOCOL instance.\r | |
220 | @param[out] LegacyMask 16-bit mode interrupt mask for IRQ0-IRQ15.\r | |
221 | @param[out] LegacyEdgeLevel 16-bit mode edge/level mask for IRQ-IRQ15.\r | |
222 | @param[out] ProtectedMask 32-bit mode interrupt mask for IRQ0-IRQ15.\r | |
223 | @param[out] ProtectedEdgeLevel 32-bit mode edge/level mask for IRQ0-IRQ15.\r | |
224 | \r | |
225 | @retval EFI_SUCCESS The 8259 PIC was programmed successfully.\r | |
226 | @retval EFI_DEVICE_ERROR There was an error while reading the 8259 PIC.\r | |
227 | \r | |
228 | **/\r | |
1166d068 | 229 | EFI_STATUS\r |
230 | EFIAPI\r | |
231 | Interrupt8259GetMask (\r | |
90b8b0ec | 232 | IN EFI_LEGACY_8259_PROTOCOL *This,\r |
1166d068 | 233 | OUT UINT16 *LegacyMask, OPTIONAL\r |
234 | OUT UINT16 *LegacyEdgeLevel, OPTIONAL\r | |
235 | OUT UINT16 *ProtectedMask, OPTIONAL\r | |
236 | OUT UINT16 *ProtectedEdgeLevel OPTIONAL\r | |
237 | )\r | |
1166d068 | 238 | {\r |
239 | if (LegacyMask != NULL) {\r | |
240 | *LegacyMask = mLegacyModeMask;\r | |
241 | }\r | |
242 | \r | |
243 | if (LegacyEdgeLevel != NULL) {\r | |
244 | *LegacyEdgeLevel = mLegacyModeEdgeLevel;\r | |
245 | }\r | |
246 | \r | |
247 | if (ProtectedMask != NULL) {\r | |
248 | *ProtectedMask = mProtectedModeMask;\r | |
249 | }\r | |
250 | \r | |
251 | if (ProtectedEdgeLevel != NULL) {\r | |
252 | *ProtectedEdgeLevel = mProtectedModeEdgeLevel;\r | |
253 | }\r | |
254 | \r | |
255 | return EFI_SUCCESS;\r | |
256 | }\r | |
257 | \r | |
1166d068 | 258 | /**\r |
90b8b0ec | 259 | Sets the current 16-bit real mode and 32-bit protected-mode IRQ masks.\r |
1166d068 | 260 | \r |
90b8b0ec | 261 | @param[in] This Indicates the EFI_LEGACY_8259_PROTOCOL instance.\r |
262 | @param[in] LegacyMask 16-bit mode interrupt mask for IRQ0-IRQ15.\r | |
263 | @param[in] LegacyEdgeLevel 16-bit mode edge/level mask for IRQ-IRQ15.\r | |
264 | @param[in] ProtectedMask 32-bit mode interrupt mask for IRQ0-IRQ15.\r | |
265 | @param[in] ProtectedEdgeLevel 32-bit mode edge/level mask for IRQ0-IRQ15.\r | |
1166d068 | 266 | \r |
90b8b0ec | 267 | @retval EFI_SUCCESS The 8259 PIC was programmed successfully.\r |
268 | @retval EFI_DEVICE_ERROR There was an error while writing the 8259 PIC.\r | |
1166d068 | 269 | \r |
270 | **/\r | |
90b8b0ec | 271 | EFI_STATUS\r |
272 | EFIAPI\r | |
273 | Interrupt8259SetMask (\r | |
274 | IN EFI_LEGACY_8259_PROTOCOL *This,\r | |
275 | IN UINT16 *LegacyMask, OPTIONAL\r | |
276 | IN UINT16 *LegacyEdgeLevel, OPTIONAL\r | |
277 | IN UINT16 *ProtectedMask, OPTIONAL\r | |
278 | IN UINT16 *ProtectedEdgeLevel OPTIONAL\r | |
279 | )\r | |
1166d068 | 280 | {\r |
281 | if (LegacyMask != NULL) {\r | |
282 | mLegacyModeMask = *LegacyMask;\r | |
283 | }\r | |
284 | \r | |
285 | if (LegacyEdgeLevel != NULL) {\r | |
286 | mLegacyModeEdgeLevel = *LegacyEdgeLevel;\r | |
287 | }\r | |
288 | \r | |
289 | if (ProtectedMask != NULL) {\r | |
290 | mProtectedModeMask = *ProtectedMask;\r | |
291 | }\r | |
292 | \r | |
293 | if (ProtectedEdgeLevel != NULL) {\r | |
294 | mProtectedModeEdgeLevel = *ProtectedEdgeLevel;\r | |
295 | }\r | |
296 | \r | |
297 | return EFI_SUCCESS;\r | |
298 | }\r | |
299 | \r | |
1166d068 | 300 | /**\r |
90b8b0ec | 301 | Sets the mode of the PICs.\r |
1166d068 | 302 | \r |
90b8b0ec | 303 | @param[in] This Indicates the EFI_LEGACY_8259_PROTOCOL instance.\r |
304 | @param[in] Mode 16-bit real or 32-bit protected mode.\r | |
305 | @param[in] Mask The value with which to set the interrupt mask.\r | |
306 | @param[in] EdgeLevel The value with which to set the edge/level mask.\r | |
1166d068 | 307 | \r |
90b8b0ec | 308 | @retval EFI_SUCCESS The mode was set successfully.\r |
309 | @retval EFI_INVALID_PARAMETER The mode was not set.\r | |
1166d068 | 310 | \r |
311 | **/\r | |
90b8b0ec | 312 | EFI_STATUS\r |
313 | EFIAPI\r | |
314 | Interrupt8259SetMode (\r | |
315 | IN EFI_LEGACY_8259_PROTOCOL *This,\r | |
316 | IN EFI_8259_MODE Mode,\r | |
317 | IN UINT16 *Mask, OPTIONAL\r | |
318 | IN UINT16 *EdgeLevel OPTIONAL\r | |
319 | )\r | |
1166d068 | 320 | {\r |
321 | if (Mode == mMode) {\r | |
322 | return EFI_SUCCESS;\r | |
323 | }\r | |
324 | \r | |
325 | if (Mode == Efi8259LegacyMode) {\r | |
326 | //\r | |
90b8b0ec | 327 | // In Efi8259ProtectedMode, mask and edge/level trigger registers should\r |
328 | // be changed through this protocol, so we can track them in the\r | |
329 | // corresponding module variables.\r | |
1166d068 | 330 | //\r |
331 | Interrupt8259ReadMask (&mProtectedModeMask, &mProtectedModeEdgeLevel);\r | |
332 | \r | |
333 | if (Mask != NULL) {\r | |
334 | //\r | |
335 | // Update the Mask for the new mode\r | |
336 | //\r | |
337 | mLegacyModeMask = *Mask;\r | |
338 | }\r | |
339 | \r | |
340 | if (EdgeLevel != NULL) {\r | |
341 | //\r | |
342 | // Update the Edge/Level triggered mask for the new mode\r | |
343 | //\r | |
344 | mLegacyModeEdgeLevel = *EdgeLevel;\r | |
345 | }\r | |
346 | \r | |
347 | mMode = Mode;\r | |
348 | \r | |
349 | //\r | |
90b8b0ec | 350 | // Write new legacy mode mask/trigger level\r |
1166d068 | 351 | //\r |
1166d068 | 352 | Interrupt8259WriteMask (mLegacyModeMask, mLegacyModeEdgeLevel);\r |
353 | \r | |
354 | return EFI_SUCCESS;\r | |
355 | }\r | |
356 | \r | |
357 | if (Mode == Efi8259ProtectedMode) {\r | |
358 | //\r | |
90b8b0ec | 359 | // Save the legacy mode mask/trigger level\r |
1166d068 | 360 | //\r |
361 | Interrupt8259ReadMask (&mLegacyModeMask, &mLegacyModeEdgeLevel);\r | |
362 | //\r | |
363 | // Always force Timer to be enabled after return from 16-bit code.\r | |
364 | // This always insures that on next entry, timer is counting.\r | |
365 | //\r | |
366 | mLegacyModeMask &= 0xFFFE;\r | |
367 | \r | |
368 | if (Mask != NULL) {\r | |
369 | //\r | |
370 | // Update the Mask for the new mode\r | |
371 | //\r | |
372 | mProtectedModeMask = *Mask;\r | |
373 | }\r | |
374 | \r | |
375 | if (EdgeLevel != NULL) {\r | |
376 | //\r | |
377 | // Update the Edge/Level triggered mask for the new mode\r | |
378 | //\r | |
379 | mProtectedModeEdgeLevel = *EdgeLevel;\r | |
380 | }\r | |
381 | \r | |
382 | mMode = Mode;\r | |
383 | \r | |
384 | //\r | |
90b8b0ec | 385 | // Write new protected mode mask/trigger level\r |
1166d068 | 386 | //\r |
1166d068 | 387 | Interrupt8259WriteMask (mProtectedModeMask, mProtectedModeEdgeLevel);\r |
388 | \r | |
389 | return EFI_SUCCESS;\r | |
390 | }\r | |
391 | \r | |
392 | return EFI_INVALID_PARAMETER;\r | |
393 | }\r | |
394 | \r | |
90b8b0ec | 395 | /**\r |
396 | Translates the IRQ into a vector.\r | |
397 | \r | |
398 | @param[in] This Indicates the EFI_LEGACY_8259_PROTOCOL instance.\r | |
399 | @param[in] Irq IRQ0-IRQ15.\r | |
400 | @param[out] Vector The vector that is assigned to the IRQ.\r | |
401 | \r | |
402 | @retval EFI_SUCCESS The Vector that matches Irq was returned.\r | |
403 | @retval EFI_INVALID_PARAMETER Irq is not valid.\r | |
404 | \r | |
405 | **/\r | |
1166d068 | 406 | EFI_STATUS\r |
407 | EFIAPI\r | |
408 | Interrupt8259GetVector (\r | |
409 | IN EFI_LEGACY_8259_PROTOCOL *This,\r | |
410 | IN EFI_8259_IRQ Irq,\r | |
411 | OUT UINT8 *Vector\r | |
412 | )\r | |
1166d068 | 413 | {\r |
3d78c020 | 414 | if ((UINT32)Irq > Efi8259Irq15) {\r |
1166d068 | 415 | return EFI_INVALID_PARAMETER;\r |
416 | }\r | |
417 | \r | |
418 | if (Irq <= Efi8259Irq7) {\r | |
419 | *Vector = (UINT8) (mMasterBase + Irq);\r | |
420 | } else {\r | |
421 | *Vector = (UINT8) (mSlaveBase + (Irq - Efi8259Irq8));\r | |
422 | }\r | |
423 | \r | |
424 | return EFI_SUCCESS;\r | |
425 | }\r | |
426 | \r | |
1166d068 | 427 | /**\r |
90b8b0ec | 428 | Enables the specified IRQ.\r |
1166d068 | 429 | \r |
90b8b0ec | 430 | @param[in] This Indicates the EFI_LEGACY_8259_PROTOCOL instance.\r |
431 | @param[in] Irq IRQ0-IRQ15.\r | |
432 | @param[in] LevelTriggered 0 = Edge triggered; 1 = Level triggered.\r | |
1166d068 | 433 | \r |
90b8b0ec | 434 | @retval EFI_SUCCESS The Irq was enabled on the 8259 PIC.\r |
435 | @retval EFI_INVALID_PARAMETER The Irq is not valid.\r | |
1166d068 | 436 | \r |
437 | **/\r | |
90b8b0ec | 438 | EFI_STATUS\r |
439 | EFIAPI\r | |
440 | Interrupt8259EnableIrq (\r | |
441 | IN EFI_LEGACY_8259_PROTOCOL *This,\r | |
442 | IN EFI_8259_IRQ Irq,\r | |
443 | IN BOOLEAN LevelTriggered\r | |
444 | )\r | |
1166d068 | 445 | {\r |
3d78c020 | 446 | if ((UINT32)Irq > Efi8259Irq15) {\r |
1166d068 | 447 | return EFI_INVALID_PARAMETER;\r |
448 | }\r | |
449 | \r | |
a694b670 | 450 | mProtectedModeMask = (UINT16) (mProtectedModeMask & ~(1 << Irq));\r |
1166d068 | 451 | if (LevelTriggered) {\r |
a694b670 | 452 | mProtectedModeEdgeLevel = (UINT16) (mProtectedModeEdgeLevel | (1 << Irq));\r |
1166d068 | 453 | } else {\r |
a694b670 | 454 | mProtectedModeEdgeLevel = (UINT16) (mProtectedModeEdgeLevel & ~(1 << Irq));\r |
1166d068 | 455 | }\r |
456 | \r | |
457 | Interrupt8259WriteMask (mProtectedModeMask, mProtectedModeEdgeLevel);\r | |
458 | \r | |
459 | return EFI_SUCCESS;\r | |
460 | }\r | |
461 | \r | |
1166d068 | 462 | /**\r |
90b8b0ec | 463 | Disables the specified IRQ.\r |
1166d068 | 464 | \r |
90b8b0ec | 465 | @param[in] This Indicates the EFI_LEGACY_8259_PROTOCOL instance.\r |
466 | @param[in] Irq IRQ0-IRQ15.\r | |
1166d068 | 467 | \r |
90b8b0ec | 468 | @retval EFI_SUCCESS The Irq was disabled on the 8259 PIC.\r |
469 | @retval EFI_INVALID_PARAMETER The Irq is not valid.\r | |
1166d068 | 470 | \r |
471 | **/\r | |
90b8b0ec | 472 | EFI_STATUS\r |
473 | EFIAPI\r | |
474 | Interrupt8259DisableIrq (\r | |
475 | IN EFI_LEGACY_8259_PROTOCOL *This,\r | |
476 | IN EFI_8259_IRQ Irq\r | |
477 | )\r | |
1166d068 | 478 | {\r |
3d78c020 | 479 | if ((UINT32)Irq > Efi8259Irq15) {\r |
1166d068 | 480 | return EFI_INVALID_PARAMETER;\r |
481 | }\r | |
482 | \r | |
90b8b0ec | 483 | mProtectedModeMask = (UINT16) (mProtectedModeMask | (1 << Irq));\r |
484 | \r | |
a694b670 | 485 | mProtectedModeEdgeLevel = (UINT16) (mProtectedModeEdgeLevel & ~(1 << Irq));\r |
1166d068 | 486 | \r |
487 | Interrupt8259WriteMask (mProtectedModeMask, mProtectedModeEdgeLevel);\r | |
488 | \r | |
489 | return EFI_SUCCESS;\r | |
490 | }\r | |
491 | \r | |
90b8b0ec | 492 | /**\r |
493 | Reads the PCI configuration space to get the interrupt number that is assigned to the card.\r | |
494 | \r | |
495 | @param[in] This Indicates the EFI_LEGACY_8259_PROTOCOL instance.\r | |
496 | @param[in] PciHandle PCI function for which to return the vector.\r | |
497 | @param[out] Vector IRQ number that corresponds to the interrupt line.\r | |
498 | \r | |
499 | @retval EFI_SUCCESS The interrupt line value was read successfully.\r | |
500 | \r | |
501 | **/\r | |
1166d068 | 502 | EFI_STATUS\r |
503 | EFIAPI\r | |
504 | Interrupt8259GetInterruptLine (\r | |
505 | IN EFI_LEGACY_8259_PROTOCOL *This,\r | |
506 | IN EFI_HANDLE PciHandle,\r | |
507 | OUT UINT8 *Vector\r | |
508 | )\r | |
1166d068 | 509 | {\r |
ae6a37f0 | 510 | EFI_PCI_IO_PROTOCOL *PciIo;\r |
511 | UINT8 InterruptLine;\r | |
512 | EFI_STATUS Status;\r | |
513 | \r | |
514 | Status = gBS->HandleProtocol (\r | |
515 | PciHandle,\r | |
516 | &gEfiPciIoProtocolGuid,\r | |
517 | (VOID **) &PciIo\r | |
518 | );\r | |
519 | if (EFI_ERROR (Status)) {\r | |
520 | return EFI_INVALID_PARAMETER;\r | |
521 | }\r | |
522 | \r | |
523 | PciIo->Pci.Read (\r | |
524 | PciIo,\r | |
525 | EfiPciIoWidthUint8,\r | |
526 | PCI_INT_LINE_OFFSET,\r | |
527 | 1,\r | |
528 | &InterruptLine\r | |
529 | );\r | |
530 | //\r | |
531 | // Interrupt line is same location for standard PCI cards, standard\r | |
532 | // bridge and CardBus bridge.\r | |
533 | //\r | |
534 | *Vector = InterruptLine;\r | |
535 | \r | |
536 | return EFI_SUCCESS;\r | |
1166d068 | 537 | }\r |
538 | \r | |
1166d068 | 539 | /**\r |
90b8b0ec | 540 | Issues the End of Interrupt (EOI) commands to PICs.\r |
1166d068 | 541 | \r |
90b8b0ec | 542 | @param[in] This Indicates the EFI_LEGACY_8259_PROTOCOL instance.\r |
543 | @param[in] Irq The interrupt for which to issue the EOI command.\r | |
1166d068 | 544 | \r |
90b8b0ec | 545 | @retval EFI_SUCCESS The EOI command was issued.\r |
546 | @retval EFI_INVALID_PARAMETER The Irq is not valid.\r | |
1166d068 | 547 | \r |
548 | **/\r | |
90b8b0ec | 549 | EFI_STATUS\r |
550 | EFIAPI\r | |
551 | Interrupt8259EndOfInterrupt (\r | |
552 | IN EFI_LEGACY_8259_PROTOCOL *This,\r | |
553 | IN EFI_8259_IRQ Irq\r | |
554 | )\r | |
1166d068 | 555 | {\r |
3d78c020 | 556 | if ((UINT32)Irq > Efi8259Irq15) {\r |
1166d068 | 557 | return EFI_INVALID_PARAMETER;\r |
558 | }\r | |
559 | \r | |
560 | if (Irq >= Efi8259Irq8) {\r | |
561 | IoWrite8 (LEGACY_8259_CONTROL_REGISTER_SLAVE, LEGACY_8259_EOI);\r | |
562 | }\r | |
563 | \r | |
564 | IoWrite8 (LEGACY_8259_CONTROL_REGISTER_MASTER, LEGACY_8259_EOI);\r | |
565 | \r | |
566 | return EFI_SUCCESS;\r | |
567 | }\r | |
568 | \r | |
90b8b0ec | 569 | /**\r |
570 | Driver Entry point.\r | |
571 | \r | |
572 | @param[in] ImageHandle ImageHandle of the loaded driver.\r | |
573 | @param[in] SystemTable Pointer to the EFI System Table.\r | |
574 | \r | |
575 | @retval EFI_SUCCESS One or more of the drivers returned a success code.\r | |
576 | @retval !EFI_SUCCESS Error installing Legacy 8259 Protocol.\r | |
577 | \r | |
578 | **/\r | |
1166d068 | 579 | EFI_STATUS\r |
580 | EFIAPI\r | |
581 | Install8259 (\r | |
582 | IN EFI_HANDLE ImageHandle,\r | |
583 | IN EFI_SYSTEM_TABLE *SystemTable\r | |
584 | )\r | |
1166d068 | 585 | {\r |
586 | EFI_STATUS Status;\r | |
587 | EFI_8259_IRQ Irq;\r | |
588 | \r | |
856f592c | 589 | //\r |
590 | // Initialze mask values from PCDs\r | |
591 | //\r | |
592 | mLegacyModeMask = PcdGet16 (Pcd8259LegacyModeMask);\r | |
593 | mLegacyModeEdgeLevel = PcdGet16 (Pcd8259LegacyModeEdgeLevel);\r | |
594 | \r | |
1166d068 | 595 | //\r |
596 | // Clear all pending interrupt\r | |
597 | //\r | |
598 | for (Irq = Efi8259Irq0; Irq <= Efi8259Irq15; Irq++) {\r | |
24115e44 | 599 | Interrupt8259EndOfInterrupt (&mInterrupt8259, Irq);\r |
1166d068 | 600 | }\r |
601 | \r | |
602 | //\r | |
603 | // Set the 8259 Master base to 0x68 and the 8259 Slave base to 0x70\r | |
604 | //\r | |
24115e44 | 605 | Status = Interrupt8259SetVectorBase (&mInterrupt8259, PROTECTED_MODE_BASE_VECTOR_MASTER, PROTECTED_MODE_BASE_VECTOR_SLAVE);\r |
1166d068 | 606 | \r |
607 | //\r | |
608 | // Set all 8259 interrupts to edge triggered and disabled\r | |
609 | //\r | |
610 | Interrupt8259WriteMask (mProtectedModeMask, mProtectedModeEdgeLevel);\r | |
611 | \r | |
612 | //\r | |
613 | // Install 8259 Protocol onto a new handle\r | |
614 | //\r | |
615 | Status = gBS->InstallProtocolInterface (\r | |
616 | &m8259Handle,\r | |
617 | &gEfiLegacy8259ProtocolGuid,\r | |
618 | EFI_NATIVE_INTERFACE,\r | |
24115e44 | 619 | &mInterrupt8259\r |
1166d068 | 620 | );\r |
1166d068 | 621 | return Status;\r |
622 | }\r |