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986d1dfb | 1 | /** @file\r |
5a702acd | 2 | HPET register definitions from the IA-PC HPET (High Precision Event Timers)\r |
986d1dfb | 3 | Specification, Revision 1.0a, October 2004.\r |
4 | \r | |
5a702acd | 5 | Copyright (c) 2011 - 2018, Intel Corporation. All rights reserved.<BR>\r |
986d1dfb | 6 | This program and the accompanying materials\r |
7 | are licensed and made available under the terms and conditions of the BSD License\r | |
8 | which accompanies this distribution. The full text of the license may be found at\r | |
9 | http://opensource.org/licenses/bsd-license.php\r | |
10 | \r | |
11 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
12 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
13 | \r | |
14 | **/\r | |
15 | \r | |
16 | #ifndef __HPET_REGISTER_H__\r | |
17 | #define __HPET_REGISTER_H__\r | |
18 | \r | |
19 | ///\r | |
20 | /// HPET General Register Offsets\r | |
21 | ///\r | |
22 | #define HPET_GENERAL_CAPABILITIES_ID_OFFSET 0x000\r | |
23 | #define HPET_GENERAL_CONFIGURATION_OFFSET 0x010\r | |
24 | #define HPET_GENERAL_INTERRUPT_STATUS_OFFSET 0x020\r | |
25 | \r | |
26 | ///\r | |
27 | /// HPET Timer Register Offsets\r | |
28 | ///\r | |
29 | #define HPET_MAIN_COUNTER_OFFSET 0x0F0\r | |
30 | #define HPET_TIMER_CONFIGURATION_OFFSET 0x100\r | |
31 | #define HPET_TIMER_COMPARATOR_OFFSET 0x108\r | |
32 | #define HPET_TIMER_MSI_ROUTE_OFFSET 0x110\r | |
33 | \r | |
34 | ///\r | |
35 | /// Stride between sets of HPET Timer Registers\r | |
36 | ///\r | |
37 | #define HPET_TIMER_STRIDE 0x20\r | |
38 | \r | |
39 | #pragma pack(1)\r | |
40 | \r | |
41 | ///\r | |
42 | /// HPET General Capabilities and ID Register\r | |
43 | ///\r | |
44 | typedef union {\r | |
45 | struct {\r | |
46 | UINT32 Revision:8;\r | |
47 | UINT32 NumberOfTimers:5;\r | |
48 | UINT32 CounterSize:1;\r | |
49 | UINT32 Reserved0:1;\r | |
50 | UINT32 LegacyRoute:1;\r | |
51 | UINT32 VendorId:16;\r | |
52 | UINT32 CounterClockPeriod:32;\r | |
53 | } Bits;\r | |
54 | UINT64 Uint64;\r | |
55 | } HPET_GENERAL_CAPABILITIES_ID_REGISTER;\r | |
56 | \r | |
57 | ///\r | |
58 | /// HPET General Configuration Register\r | |
59 | ///\r | |
60 | typedef union {\r | |
61 | struct {\r | |
62 | UINT32 MainCounterEnable:1;\r | |
63 | UINT32 LegacyRouteEnable:1;\r | |
64 | UINT32 Reserved0:30;\r | |
65 | UINT32 Reserved1:32;\r | |
66 | } Bits;\r | |
67 | UINT64 Uint64;\r | |
68 | } HPET_GENERAL_CONFIGURATION_REGISTER;\r | |
69 | \r | |
70 | ///\r | |
71 | /// HPET Timer Configuration Register\r | |
72 | ///\r | |
73 | typedef union {\r | |
74 | struct {\r | |
75 | UINT32 Reserved0:1;\r | |
76 | UINT32 LevelTriggeredInterrupt:1;\r | |
77 | UINT32 InterruptEnable:1;\r | |
78 | UINT32 PeriodicInterruptEnable:1;\r | |
79 | UINT32 PeriodicInterruptCapablity:1;\r | |
80 | UINT32 CounterSizeCapablity:1;\r | |
81 | UINT32 ValueSetEnable:1;\r | |
82 | UINT32 Reserved1:1;\r | |
83 | UINT32 CounterSizeEnable:1;\r | |
84 | UINT32 InterruptRoute:5;\r | |
85 | UINT32 MsiInterruptEnable:1;\r | |
86 | UINT32 MsiInterruptCapablity:1;\r | |
87 | UINT32 Reserved2:16;\r | |
88 | UINT32 InterruptRouteCapability;\r | |
89 | } Bits;\r | |
90 | UINT64 Uint64;\r | |
91 | } HPET_TIMER_CONFIGURATION_REGISTER;\r | |
92 | \r | |
93 | ///\r | |
94 | /// HPET Timer MSI Route Register\r | |
95 | ///\r | |
96 | typedef union {\r | |
97 | struct {\r | |
98 | UINT32 Value:32;\r | |
99 | UINT32 Address:32;\r | |
100 | } Bits;\r | |
101 | UINT64 Uint64;\r | |
102 | } HPET_TIMER_MSI_ROUTE_REGISTER;\r | |
103 | \r | |
104 | #pragma pack()\r | |
105 | \r | |
106 | #endif\r |