]>
Commit | Line | Data |
---|---|---|
986d1dfb | 1 | /** @file\r |
5a702acd | 2 | I/O APIC Register Definitions from 82093AA I/O Advanced Programmable Interrupt\r |
986d1dfb | 3 | Controller (IOAPIC), 1996.\r |
5a702acd LG |
4 | \r |
5 | Copyright (c) 2011 - 2018, Intel Corporation. All rights reserved.<BR>\r | |
e1d302e5 | 6 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
986d1dfb | 7 | \r |
8 | **/\r | |
9 | \r | |
10 | #ifndef __IO_APIC_H__\r | |
11 | #define __IO_APIC_H__\r | |
12 | \r | |
13 | ///\r | |
14 | /// I/O APIC Register Offsets\r | |
15 | ///\r | |
16 | #define IOAPIC_INDEX_OFFSET 0x00\r | |
17 | #define IOAPIC_DATA_OFFSET 0x10\r | |
18 | \r | |
19 | ///\r | |
20 | /// I/O APIC Indirect Register Indexes\r | |
21 | ///\r | |
22 | #define IO_APIC_IDENTIFICATION_REGISTER_INDEX 0x00\r | |
23 | #define IO_APIC_VERSION_REGISTER_INDEX 0x01\r | |
24 | #define IO_APIC_REDIRECTION_TABLE_ENTRY_INDEX 0x10\r | |
25 | \r | |
26 | ///\r | |
27 | /// I/O APIC Interrupt Deliver Modes\r | |
28 | ///\r | |
29 | #define IO_APIC_DELIVERY_MODE_FIXED 0\r | |
30 | #define IO_APIC_DELIVERY_MODE_LOWEST_PRIORITY 1\r | |
31 | #define IO_APIC_DELIVERY_MODE_SMI 2\r | |
32 | #define IO_APIC_DELIVERY_MODE_NMI 4\r | |
33 | #define IO_APIC_DELIVERY_MODE_INIT 5\r | |
34 | #define IO_APIC_DELIVERY_MODE_EXTINT 7\r | |
35 | \r | |
36 | #pragma pack(1)\r | |
37 | \r | |
38 | typedef union {\r | |
39 | struct {\r | |
40 | UINT32 Reserved0:24;\r | |
41 | UINT32 Identification:4;\r | |
42 | UINT32 Reserved1:4;\r | |
43 | } Bits;\r | |
44 | UINT32 Uint32;\r | |
45 | } IO_APIC_IDENTIFICATION_REGISTER;\r | |
46 | \r | |
47 | typedef union {\r | |
48 | struct {\r | |
49 | UINT32 Version:8;\r | |
50 | UINT32 Reserved0:8;\r | |
51 | UINT32 MaximumRedirectionEntry:8;\r | |
52 | UINT32 Reserved1:8;\r | |
53 | } Bits;\r | |
54 | UINT32 Uint32;\r | |
55 | } IO_APIC_VERSION_REGISTER;\r | |
56 | \r | |
57 | typedef union {\r | |
58 | struct {\r | |
59 | UINT32 Vector: 8;\r | |
60 | UINT32 DeliveryMode: 3;\r | |
61 | UINT32 DestinationMode: 1;\r | |
62 | UINT32 DeliveryStatus: 1;\r | |
63 | UINT32 Polarity: 1;\r | |
64 | UINT32 RemoteIRR: 1;\r | |
65 | UINT32 TriggerMode: 1;\r | |
66 | UINT32 Mask: 1;\r | |
67 | UINT32 Reserved0: 15;\r | |
68 | UINT32 Reserved1: 24;\r | |
69 | UINT32 DestinationID: 8;\r | |
70 | } Bits;\r | |
71 | struct {\r | |
72 | UINT32 Low;\r | |
73 | UINT32 High;\r | |
74 | } Uint32;\r | |
75 | UINT64 Uint64;\r | |
76 | } IO_APIC_REDIRECTION_TABLE_ENTRY;\r | |
77 | \r | |
78 | #pragma pack()\r | |
79 | \r | |
80 | #endif\r |