[mirror_edk2.git] / QuarkPlatformPkg / Acpi / AcpiTables / Cpu0Cst / Cpu0Cst.asl

/** @file\r
CPU C State control methods\r
\r
Copyright (c) 2013-2015 Intel Corporation.\r
\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution.  The full text of the license may be found at\r
http://opensource.org/licenses/bsd-license.php\r
\r
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
**/\r
\r
DefinitionBlock (\r
    "Cpu0Cst.aml",\r
    "SSDT",\r
    0x01,\r
    "SsgPmm",\r
    "Cpu0Cst",\r
    0x0011\r
    )\r
{\r
    External(\_PR.CPU0, DeviceObj)\r
    External (PDC0, IntObj)\r
    External (CFGD, FieldUnitObj)\r
\r
    Scope(\_PR.CPU0)\r
    {\r
        Method (_CST, 0)\r
        {\r
            // If CMP is supported, and OSPM is not capable of independent C1, P, T state\r
            // support for each processor for multi-processor configuration, we will just report\r
            // C1 halt\r
            //\r
            // PDCx[4] = Indicates whether OSPM is not capable of independent C1, P, T state\r
            // support for each processor for multi-processor configuration.\r
            //\r
            If(LAnd(And(CFGD,0x01000000), LNot(And(PDC0,0x10))))\r
            {\r
              Return(Package() {\r
                1,\r
                Package()\r
                { // C1 halt\r
                  ResourceTemplate(){Register(FFixedHW, 0, 0, 0)},\r
                  1,\r
                  157,\r
                  1000\r
                }\r
              })\r
            }\r
\r
            //\r
            // If MWAIT extensions is supported and OSPM is capable of performing\r
            // native C state instructions for the C2/C3 in multi-processor configuration,\r
            // we report every c state with MWAIT extensions.\r
            //\r
            // PDCx[9] = Indicates whether OSPM is capable of performing native C state instructions\r
            // for the C2/C3 in multi-processor configuration\r
            //\r
            If(LAnd(And(CFGD, 0x200000), And(PDC0,0x200)))\r
            {\r
              //\r
              // If C6 is supported, we report MWAIT C1,C2,C4,C6\r
              //\r
              If(And(CFGD,0x200))\r
              {\r
                Return( Package()\r
                {\r
                  4,\r
                  Package()\r
                  { // MWAIT C1, hardware coordinated with no bus master avoidance\r
                    ResourceTemplate(){Register(FFixedHW, 1, 2, 0x00, 1)},\r
                    1,\r
                    1,\r
                    1000\r
                  },\r
                  Package()\r
                  { // MWAIT C2, hardware coordinated with no bus master avoidance\r
                    ResourceTemplate(){Register(FFixedHW, 1, 2, 0x10, 1)},\r
                    2,\r
                    20,\r
                    500\r
                  },\r
                  Package()\r
                  { // MWAIT C4, hardware coordinated with bus master avoidance enabled\r
                    ResourceTemplate(){Register(FFixedHW, 1, 2, 0x30, 3)},\r
                    3,\r
                    100,\r
                    100\r
                  },\r
                  Package()\r
                  { // MWAIT C6, hardware coordinated with bus master avoidance enabled\r
                    ResourceTemplate(){Register(FFixedHW, 1, 2, 0x50, 3)},\r
                    3,\r
                    140,\r
                    10\r
                  }\r
                })\r
              }\r
              //\r
              // If C4 is supported, we report MWAIT C1,C2,C4\r
              //\r
              If(And(CFGD,0x080))\r
              {\r
                Return( Package()\r
                {\r
                  3,\r
                  Package()\r
                  { // MWAIT C1, hardware coordinated with no bus master avoidance\r
                    ResourceTemplate(){Register(FFixedHW, 1, 2, 0x00, 1)},\r
                    1,\r
                    1,\r
                    1000\r
                  },\r
                  Package()\r
                  { // MWAIT C2, hardware coordinated with no bus master avoidance\r
                    ResourceTemplate(){Register(FFixedHW, 1, 2, 0x10, 1)},\r
                    2,\r
                    20,\r
                    500\r
                  },\r
                  Package()\r
                  { // MWAIT C4, hardware coordinated with bus master avoidance enabled\r
                    ResourceTemplate(){Register(FFixedHW, 1, 2, 0x30, 3)},\r
                    3,\r
                    100,\r
                    100\r
                  }\r
                })\r
              }\r
              //\r
              // If C2 is supported, we report MWAIT C1,C2\r
              //\r
              If(And(CFGD,0x020))\r
              {\r
                Return( Package()\r
                {\r
                  2,\r
                  Package()\r
                  { // MWAIT C1, hardware coordinated with no bus master avoidance\r
                    ResourceTemplate(){Register(FFixedHW, 1, 2, 0x00, 1)},\r
                    1,\r
                    1,\r
                    1000\r
                  },\r
                  Package()\r
                  { // MWAIT C2, hardware coordinated with no bus master avoidance\r
                    ResourceTemplate(){Register(FFixedHW, 1, 2, 0x10, 1)},\r
                    2,\r
                    20,\r
                    500\r
                  }\r
                })\r
              }\r
              //\r
              // Else we only report MWAIT C1.\r
              //\r
              Return(Package()\r
              {\r
                1,\r
                Package()\r
                { // MWAIT C1, hardware coordinated with no bus master avoidance\r
                  ResourceTemplate () {Register(FFixedHW, 1, 2, 0x00, 1)},\r
                  1,\r
                  1,\r
                  1000\r
                }\r
              })\r
            }\r
\r
            // If OSPM is only capable of performing native C state instructions for\r
            // the C1 in multi-processor configuration, we report C1 with MWAIT, other\r
            // C states with IO method.\r
            //\r
            // PDCx[8] = Indicates whether OSPM is capable of performing native C state instructions\r
            // for the C1 in multi-processor configuration\r
            //\r
            If(LAnd(And(CFGD, 0x200000), And(PDC0,0x100)))\r
            {\r
              //\r
              // If C6 is supported, we report MWAIT C1, IO C2,C4,C6\r
              //\r
              If(And(CFGD,0x200))\r
              {\r
                Return( Package()\r
                {\r
                  4,\r
                  Package()\r
                  { // MWAIT C1, hardware coordinated with no bus master avoidance\r
                    ResourceTemplate () {Register(FFixedHW, 1, 2, 0x00, 1)},\r
                    1,\r
                    1,\r
                    1000\r
                  },\r
                  Package()\r
                  { // IO C2 ("PMBALVL2" will be updated at runtime)\r
                    ResourceTemplate () {Register(SystemIO, 8, 0, 0x324C564C41424D50)},\r
                    2,\r
                    20,\r
                    500\r
                    },\r
                  Package()\r
                  { // IO C4 ("PMBALVL4" will be updated at runtime)\r
                    ResourceTemplate () {Register(SystemIO, 8, 0, 0x344C564C41424D50)},\r
                    3,\r
                    100,\r
                    100\r
                  },\r
                  Package()\r
                  { // IO C6 ("PMBALVL6" will be updated at runtime)\r
                    ResourceTemplate () {Register(SystemIO, 8, 0, 0x364C564C41424D50)},\r
                    3,\r
                    140,\r
                    10\r
                  }\r
                })\r
              }\r
              //\r
              // If C4 is supported, we report MWAIT C1, IO C2,C4\r
              //\r
              If(And(CFGD,0x080))\r
              {\r
                Return( Package()\r
                {\r
                  3,\r
                  Package()\r
                  { // MWAIT C1, hardware coordinated with no bus master avoidance\r
                    ResourceTemplate () {Register(FFixedHW, 1, 2, 0x00, 1)},\r
                    1,\r
                    1,\r
                    1000\r
                  },\r
                  Package()\r
                  { // IO C2 ("PMBALVL2" will be updated at runtime)\r
                    ResourceTemplate () {Register(SystemIO, 8, 0, 0x324C564C41424D50)},\r
                    2,\r
                    20,\r
                    500\r
                    },\r
                  Package()\r
                  { // IO C4 ("PMBALVL4" will be updated at runtime)\r
                    ResourceTemplate () {Register(SystemIO, 8, 0, 0x344C564C41424D50)},\r
                    3,\r
                    100,\r
                    100\r
                  }\r
                })\r
              }\r
              //\r
              // If C2 is supported, we report MWAIT C1, IO C2\r
              //\r
              If(And(CFGD,0x020))\r
              {\r
                Return( Package()\r
                {\r
                  2,\r
                  Package()\r
                  { // MWAIT C1, hardware coordinated with no bus master avoidance\r
                    ResourceTemplate () {Register(FFixedHW, 1, 2, 0x00, 1)},\r
                    1,\r
                    1,\r
                    1000\r
                  },\r
                  Package()\r
                  { // IO C2 ("PMBALVL2" will be updated at runtime)\r
                    ResourceTemplate () {Register(SystemIO, 8, 0, 0x324C564C41424D50)},\r
                    2,\r
                    20,\r
                    500\r
                  }\r
                })\r
              }\r
              //\r
              // Else we only report MWAIT C1.\r
              //\r
              Return(Package()\r
              {\r
                1,\r
                Package()\r
                { // MWAIT C1, hardware coordinated with no bus master avoidance\r
                  ResourceTemplate () {Register(FFixedHW, 1, 2, 0x00, 1)},\r
                  1,\r
                  1,\r
                  1000\r
                }\r
              })\r
            }\r
\r
            //\r
            // If MWAIT is not supported, we report all the c states with IO method\r
            //\r
\r
            //\r
            // If C6 is supported, we report C1 halt, IO C2,C4,C6\r
            //\r
            If(And(CFGD,0x200))\r
            {\r
              Return(Package()\r
              {\r
                4,\r
                Package()\r
                { // C1 Halt\r
                  ResourceTemplate () {Register(FFixedHW, 0, 0, 0)},\r
                  1,\r
                  1,\r
                  1000\r
                },\r
                Package()\r
                { // IO C2 ("PMBALVL2" will be updated at runtime)\r
                  ResourceTemplate () {Register(SystemIO, 8, 0, 0x324C564C41424D50)},\r
                  2,\r
                  20,\r
                  500\r
                },\r
                Package()\r
                { // IO C4 ("PMBALVL4" will be updated at runtime)\r
                  ResourceTemplate () {Register(SystemIO, 8, 0, 0x344C564C41424D50)},\r
                  3,\r
                  100,\r
                  100\r
                },\r
                Package()\r
                { // IO C6 ("PMBALVL6" will be updated at runtime)\r
                  ResourceTemplate () {Register(SystemIO, 8, 0, 0x364C564C41424D50)},\r
                  3,\r
                  140,\r
                  10\r
                }\r
              })\r
            }\r
            //\r
            // If C4 is supported, we report C1 halt, IO C2,C4\r
            //\r
            If(And(CFGD,0x080))\r
            {\r
              Return(Package()\r
              {\r
                3,\r
                Package()\r
                { // C1 halt\r
                  ResourceTemplate () {Register(FFixedHW, 0, 0, 0)},\r
                  1,\r
                  1,\r
                  1000\r
                },\r
                Package()\r
                { // IO C2 ("PMBALVL2" will be updated at runtime)\r
                  ResourceTemplate () {Register(SystemIO, 8, 0, 0x324C564C41424D50)},\r
                  2,\r
                  20,\r
                  500\r
                },\r
                Package()\r
                { // IO C4 ("PMBALVL4" will be updated at runtime)\r
                  ResourceTemplate () {Register(SystemIO, 8, 0, 0x344C564C41424D50)},\r
                  3,\r
                  100,\r
                  100\r
                }\r
              })\r
            }\r
\r
            //\r
            // If C2 is supported, we report C1 halt, IO C2\r
            //\r
            If(And(CFGD,0x020))\r
            {\r
              Return(Package()\r
              {\r
                2,\r
                Package()\r
                { // C1 halt\r
                  ResourceTemplate () {Register(FFixedHW, 0, 0, 0)},\r
                  1,\r
                  1,\r
                  1000\r
                },\r
                Package()\r
                { // IO C2 ("PMBALVL2" will be updated at runtime)\r
                  ResourceTemplate () {Register(SystemIO, 8, 0, 0x324C564C41424D50)},\r
                  2,\r
                  20,\r
                  500\r
                }\r
              })\r
            }\r
            //\r
            // Else we only report C1 halt.\r
            //\r
            Return(Package()\r
            {\r
              1,\r
              Package()\r
              { // C1 halt\r
                ResourceTemplate () {Register(FFixedHW, 0, 0, 0)},\r
                1,\r
                1,\r
                1000\r
              }\r
            })\r
        }\r
    }\r
}\r
Commit	Line	Data
b303605e MK	1	/** @file\r
	2	CPU C State control methods\r
	3	\r
	4	Copyright (c) 2013-2015 Intel Corporation.\r
	5	\r
	6	This program and the accompanying materials\r
	7	are licensed and made available under the terms and conditions of the BSD License\r
	8	which accompanies this distribution. The full text of the license may be found at\r
	9	http://opensource.org/licenses/bsd-license.php\r
	10	\r
	11	THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
	12	WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
	13	\r
	14	**/\r
	15	\r
	16	DefinitionBlock (\r
	17	"Cpu0Cst.aml",\r
	18	"SSDT",\r
	19	0x01,\r
	20	"SsgPmm",\r
	21	"Cpu0Cst",\r
	22	0x0011\r
	23	)\r
	24	{\r
	25	External(\_PR.CPU0, DeviceObj)\r
	26	External (PDC0, IntObj)\r
	27	External (CFGD, FieldUnitObj)\r
	28	\r
	29	Scope(\_PR.CPU0)\r
	30	{\r
	31	Method (_CST, 0)\r
	32	{\r
	33	// If CMP is supported, and OSPM is not capable of independent C1, P, T state\r
	34	// support for each processor for multi-processor configuration, we will just report\r
	35	// C1 halt\r
	36	//\r
	37	// PDCx[4] = Indicates whether OSPM is not capable of independent C1, P, T state\r
	38	// support for each processor for multi-processor configuration.\r
	39	//\r
	40	If(LAnd(And(CFGD,0x01000000), LNot(And(PDC0,0x10))))\r
	41	{\r
	42	Return(Package() {\r
	43	1,\r
	44	Package()\r
	45	{ // C1 halt\r
	46	ResourceTemplate(){Register(FFixedHW, 0, 0, 0)},\r
	47	1,\r
	48	157,\r
	49	1000\r
	50	}\r
	51	})\r
	52	}\r
	53	\r
	54	//\r
	55	// If MWAIT extensions is supported and OSPM is capable of performing\r
	56	// native C state instructions for the C2/C3 in multi-processor configuration,\r
	57	// we report every c state with MWAIT extensions.\r
	58	//\r
	59	// PDCx[9] = Indicates whether OSPM is capable of performing native C state instructions\r
	60	// for the C2/C3 in multi-processor configuration\r
	61	//\r
	62	If(LAnd(And(CFGD, 0x200000), And(PDC0,0x200)))\r
	63	{\r
	64	//\r
65	// If C6 is supported, we report MWAIT C1,C2,C4,C6\r
66	//\r
67	If(And(CFGD,0x200))\r
68	{\r
69	Return( Package()\r
70	{\r
71	4,\r
72	Package()\r
73	{ // MWAIT C1, hardware coordinated with no bus master avoidance\r
74	ResourceTemplate(){Register(FFixedHW, 1, 2, 0x00, 1)},\r
75	1,\r
76	1,\r
77	1000\r
78	},\r
79	Package()\r
80	{ // MWAIT C2, hardware coordinated with no bus master avoidance\r
81	ResourceTemplate(){Register(FFixedHW, 1, 2, 0x10, 1)},\r
82	2,\r
83	20,\r
84	500\r
85	},\r
86	Package()\r
87	{ // MWAIT C4, hardware coordinated with bus master avoidance enabled\r
88	ResourceTemplate(){Register(FFixedHW, 1, 2, 0x30, 3)},\r
89	3,\r
90	100,\r
91	100\r
92	},\r
93	Package()\r
94	{ // MWAIT C6, hardware coordinated with bus master avoidance enabled\r
95	ResourceTemplate(){Register(FFixedHW, 1, 2, 0x50, 3)},\r
96	3,\r
97	140,\r
98	10\r
99	}\r
100	})\r
101	}\r
102	//\r
103	// If C4 is supported, we report MWAIT C1,C2,C4\r
104	//\r
105	If(And(CFGD,0x080))\r
106	{\r
107	Return( Package()\r
108	{\r
109	3,\r
110	Package()\r
111	{ // MWAIT C1, hardware coordinated with no bus master avoidance\r
112	ResourceTemplate(){Register(FFixedHW, 1, 2, 0x00, 1)},\r
113	1,\r
114	1,\r
115	1000\r
116	},\r
117	Package()\r
118	{ // MWAIT C2, hardware coordinated with no bus master avoidance\r
119	ResourceTemplate(){Register(FFixedHW, 1, 2, 0x10, 1)},\r
120	2,\r
121	20,\r
122	500\r
123	},\r
124	Package()\r
125	{ // MWAIT C4, hardware coordinated with bus master avoidance enabled\r
126	ResourceTemplate(){Register(FFixedHW, 1, 2, 0x30, 3)},\r
127	3,\r
128	100,\r
129	100\r
130	}\r
131	})\r
132	}\r
133	//\r
134	// If C2 is supported, we report MWAIT C1,C2\r
135	//\r
136	If(And(CFGD,0x020))\r
137	{\r
138	Return( Package()\r
139	{\r
140	2,\r
141	Package()\r
142	{ // MWAIT C1, hardware coordinated with no bus master avoidance\r
143	ResourceTemplate(){Register(FFixedHW, 1, 2, 0x00, 1)},\r
144	1,\r
145	1,\r
146	1000\r
147	},\r
148	Package()\r
149	{ // MWAIT C2, hardware coordinated with no bus master avoidance\r
150	ResourceTemplate(){Register(FFixedHW, 1, 2, 0x10, 1)},\r
151	2,\r
152	20,\r
153	500\r
154	}\r
155	})\r
156	}\r
157	//\r
158	// Else we only report MWAIT C1.\r
159	//\r
160	Return(Package()\r
161	{\r
162	1,\r
163	Package()\r
164	{ // MWAIT C1, hardware coordinated with no bus master avoidance\r
165	ResourceTemplate () {Register(FFixedHW, 1, 2, 0x00, 1)},\r
166	1,\r
167	1,\r
168	1000\r
169	}\r
170	})\r
171	}\r
172	\r
173	// If OSPM is only capable of performing native C state instructions for\r
174	// the C1 in multi-processor configuration, we report C1 with MWAIT, other\r
175	// C states with IO method.\r
176	//\r
177	// PDCx[8] = Indicates whether OSPM is capable of performing native C state instructions\r
178	// for the C1 in multi-processor configuration\r
179	//\r
180	If(LAnd(And(CFGD, 0x200000), And(PDC0,0x100)))\r
181	{\r
182	//\r
183	// If C6 is supported, we report MWAIT C1, IO C2,C4,C6\r
184	//\r
185	If(And(CFGD,0x200))\r
186	{\r
187	Return( Package()\r
188	{\r
189	4,\r
190	Package()\r
191	{ // MWAIT C1, hardware coordinated with no bus master avoidance\r
192	ResourceTemplate () {Register(FFixedHW, 1, 2, 0x00, 1)},\r
193	1,\r
194	1,\r
195	1000\r
196	},\r
197	Package()\r
198	{ // IO C2 ("PMBALVL2" will be updated at runtime)\r
199	ResourceTemplate () {Register(SystemIO, 8, 0, 0x324C564C41424D50)},\r
200	2,\r
201	20,\r
202	500\r
203	},\r
204	Package()\r
205	{ // IO C4 ("PMBALVL4" will be updated at runtime)\r
206	ResourceTemplate () {Register(SystemIO, 8, 0, 0x344C564C41424D50)},\r
207	3,\r
208	100,\r
209	100\r
210	},\r
211	Package()\r
212	{ // IO C6 ("PMBALVL6" will be updated at runtime)\r
213	ResourceTemplate () {Register(SystemIO, 8, 0, 0x364C564C41424D50)},\r
214	3,\r
215	140,\r
216	10\r
217	}\r
218	})\r
219	}\r
220	//\r
221	// If C4 is supported, we report MWAIT C1, IO C2,C4\r
222	//\r
223	If(And(CFGD,0x080))\r
224	{\r
225	Return( Package()\r
226	{\r
227	3,\r
228	Package()\r
229	{ // MWAIT C1, hardware coordinated with no bus master avoidance\r
230	ResourceTemplate () {Register(FFixedHW, 1, 2, 0x00, 1)},\r
231	1,\r
232	1,\r
233	1000\r
234	},\r
235	Package()\r
236	{ // IO C2 ("PMBALVL2" will be updated at runtime)\r
237	ResourceTemplate () {Register(SystemIO, 8, 0, 0x324C564C41424D50)},\r
238	2,\r
239	20,\r
240	500\r
241	},\r
242	Package()\r
243	{ // IO C4 ("PMBALVL4" will be updated at runtime)\r
244	ResourceTemplate () {Register(SystemIO, 8, 0, 0x344C564C41424D50)},\r
245	3,\r
246	100,\r
247	100\r
248	}\r
249	})\r
250	}\r
251	//\r
252	// If C2 is supported, we report MWAIT C1, IO C2\r
253	//\r
254	If(And(CFGD,0x020))\r
255	{\r
256	Return( Package()\r
257	{\r
258	2,\r
259	Package()\r
260	{ // MWAIT C1, hardware coordinated with no bus master avoidance\r
261	ResourceTemplate () {Register(FFixedHW, 1, 2, 0x00, 1)},\r
262	1,\r
263	1,\r
264	1000\r
265	},\r
266	Package()\r
267	{ // IO C2 ("PMBALVL2" will be updated at runtime)\r
268	ResourceTemplate () {Register(SystemIO, 8, 0, 0x324C564C41424D50)},\r
269	2,\r
270	20,\r
271	500\r
272	}\r
273	})\r
274	}\r
275	//\r
276	// Else we only report MWAIT C1.\r
277	//\r
278	Return(Package()\r
279	{\r
280	1,\r
281	Package()\r
282	{ // MWAIT C1, hardware coordinated with no bus master avoidance\r
283	ResourceTemplate () {Register(FFixedHW, 1, 2, 0x00, 1)},\r
284	1,\r
285	1,\r
286	1000\r
287	}\r
288	})\r
289	}\r
290	\r
291	//\r
292	// If MWAIT is not supported, we report all the c states with IO method\r
293	//\r
294	\r
295	//\r
296	// If C6 is supported, we report C1 halt, IO C2,C4,C6\r
297	//\r
298	If(And(CFGD,0x200))\r
299	{\r
300	Return(Package()\r
301	{\r
302	4,\r
303	Package()\r
304	{ // C1 Halt\r
305	ResourceTemplate () {Register(FFixedHW, 0, 0, 0)},\r
306	1,\r
307	1,\r
308	1000\r
309	},\r
310	Package()\r
311	{ // IO C2 ("PMBALVL2" will be updated at runtime)\r
312	ResourceTemplate () {Register(SystemIO, 8, 0, 0x324C564C41424D50)},\r
313	2,\r
314	20,\r
315	500\r
316	},\r
317	Package()\r
318	{ // IO C4 ("PMBALVL4" will be updated at runtime)\r
319	ResourceTemplate () {Register(SystemIO, 8, 0, 0x344C564C41424D50)},\r
320	3,\r
321	100,\r
322	100\r
323	},\r
324	Package()\r
325	{ // IO C6 ("PMBALVL6" will be updated at runtime)\r
326	ResourceTemplate () {Register(SystemIO, 8, 0, 0x364C564C41424D50)},\r
327	3,\r
328	140,\r
329	10\r
330	}\r
331	})\r
332	}\r
333	//\r
334	// If C4 is supported, we report C1 halt, IO C2,C4\r
335	//\r
336	If(And(CFGD,0x080))\r
337	{\r
338	Return(Package()\r
339	{\r
340	3,\r
341	Package()\r
342	{ // C1 halt\r
343	ResourceTemplate () {Register(FFixedHW, 0, 0, 0)},\r
344	1,\r
345	1,\r
346	1000\r
347	},\r
348	Package()\r
349	{ // IO C2 ("PMBALVL2" will be updated at runtime)\r
350	ResourceTemplate () {Register(SystemIO, 8, 0, 0x324C564C41424D50)},\r
351	2,\r
352	20,\r
353	500\r
354	},\r
355	Package()\r
356	{ // IO C4 ("PMBALVL4" will be updated at runtime)\r
357	ResourceTemplate () {Register(SystemIO, 8, 0, 0x344C564C41424D50)},\r
358	3,\r
359	100,\r
360	100\r
361	}\r
362	})\r
363	}\r
364	\r
365	//\r
366	// If C2 is supported, we report C1 halt, IO C2\r
367	//\r
368	If(And(CFGD,0x020))\r
369	{\r
370	Return(Package()\r
371	{\r
372	2,\r
373	Package()\r
374	{ // C1 halt\r
375	ResourceTemplate () {Register(FFixedHW, 0, 0, 0)},\r
376	1,\r
377	1,\r
378	1000\r
379	},\r
380	Package()\r
381	{ // IO C2 ("PMBALVL2" will be updated at runtime)\r
382	ResourceTemplate () {Register(SystemIO, 8, 0, 0x324C564C41424D50)},\r
383	2,\r
384	20,\r
385	500\r
386	}\r
387	})\r
388	}\r
389	//\r
390	// Else we only report C1 halt.\r
391	//\r
392	Return(Package()\r
393	{\r
394	1,\r
395	Package()\r
396	{ // C1 halt\r
397	ResourceTemplate () {Register(FFixedHW, 0, 0, 0)},\r
398	1,\r
399	1,\r
400	1000\r
401	}\r
402	})\r
403	}\r
404	}\r
405	}\r