QuarkPlatformPkg: Add new package for Galileo boards
authorMichael Kinney <michael.d.kinney@intel.com>
Tue, 15 Dec 2015 19:23:57 +0000 (19:23 +0000)
committermdkinney <mdkinney@Edk2>
Tue, 15 Dec 2015 19:23:57 +0000 (19:23 +0000)
Changes for V4
==============
1) Move delete of QuarkSocPkg\QuarkNorthCluster\Binary\QuarkMicrocode
   from QuarkPlatformPkg commit to QuarkSocPkg commit
2) Fix incorrect license header in PlatformSecLibModStrs.uni

Changes for V3
==============
1) Set PcdResetOnMemoryTypeInformationChange FALSE in QuarkMin.dsc
   This is required because QuarkMin.dsc uses the emulated variable
   driver that does not preserve any non-volatile UEFI variables
   across reset.  If the condition is met where the memory type
   information variable needs to be updated, then the system will reset
   every time the UEFI Shell is run.  By setting this PCD to FALSE,
   then reset action is disabled.
2) Move one binary file to QuarkSocBinPkg
3) Change RMU.bin FILE statements to INF statement in DSC FD region
   to be compatible with PACKAGES_PATH search for QuarkSocBinPkg

Changes for V2
==============
1) Use new generic PCI serial driver PciSioSerialDxe in MdeModulePkg
2) Configure PcdPciSerialParameters for PCI serial driver for Quark
3) Use new MtrrLib API to reduce time to set MTRRs for all DRAM
4) Convert all UNI files to utf-8
5) Replace tabs with spaces and remove trailing spaces
6) Add License.txt

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Acked-by: Jordan Justen <jordan.l.justen@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19287 6f19259b-4bc3-4df7-8a09-765794883524

190 files changed:
QuarkPlatformPkg/Acpi/AcpiTables/AcpiTables.inf [new file with mode: 0644]
QuarkPlatformPkg/Acpi/AcpiTables/Cpu0Cst/Cpu0Cst.asl [new file with mode: 0644]
QuarkPlatformPkg/Acpi/AcpiTables/Cpu0Ist/Cpu0Ist.asl [new file with mode: 0644]
QuarkPlatformPkg/Acpi/AcpiTables/Cpu0Tst/Cpu0Tst.asl [new file with mode: 0644]
QuarkPlatformPkg/Acpi/AcpiTables/CpuPm/CpuPm.asl [new file with mode: 0644]
QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/AD7298.asi [new file with mode: 0644]
QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/ADC108S102.asi [new file with mode: 0644]
QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/CAT24C08.asi [new file with mode: 0644]
QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/CY8C9540A.asi [new file with mode: 0644]
QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/GpioClient.asi [new file with mode: 0644]
QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/LpcDev.asi [new file with mode: 0644]
QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/PCA9685.asi [new file with mode: 0644]
QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/PCAL9555A.asi [new file with mode: 0644]
QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/PciHostBridge.asi [new file with mode: 0644]
QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/PciIrq.asi [new file with mode: 0644]
QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/PcieExpansionPrt.asi [new file with mode: 0644]
QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/Platform.asl [new file with mode: 0644]
QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/QNC.asi [new file with mode: 0644]
QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/QNCApic.asi [new file with mode: 0644]
QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/QNCLpc.asi [new file with mode: 0644]
QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/QuarkSouthCluster.asi [new file with mode: 0644]
QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/Tpm.asi [new file with mode: 0644]
QuarkPlatformPkg/Acpi/AcpiTables/Facs/Facs.aslc [new file with mode: 0644]
QuarkPlatformPkg/Acpi/AcpiTables/Facs/Facs.h [new file with mode: 0644]
QuarkPlatformPkg/Acpi/AcpiTables/Fadt/Fadt.h [new file with mode: 0644]
QuarkPlatformPkg/Acpi/AcpiTables/Fadt/Fadt1.0.aslc [new file with mode: 0644]
QuarkPlatformPkg/Acpi/AcpiTables/Fadt/Fadt2.0.aslc [new file with mode: 0644]
QuarkPlatformPkg/Acpi/AcpiTables/Hpet/Hpet.aslc [new file with mode: 0644]
QuarkPlatformPkg/Acpi/AcpiTables/Hpet/Hpet.h [new file with mode: 0644]
QuarkPlatformPkg/Acpi/AcpiTables/Mcfg/Mcfg.aslc [new file with mode: 0644]
QuarkPlatformPkg/Acpi/AcpiTables/Mcfg/Mcfg.h [new file with mode: 0644]
QuarkPlatformPkg/Acpi/Dxe/AcpiPlatform/AcpiPciUpdate.c [new file with mode: 0644]
QuarkPlatformPkg/Acpi/Dxe/AcpiPlatform/AcpiPciUpdate.h [new file with mode: 0644]
QuarkPlatformPkg/Acpi/Dxe/AcpiPlatform/AcpiPlatform.c [new file with mode: 0644]
QuarkPlatformPkg/Acpi/Dxe/AcpiPlatform/AcpiPlatform.h [new file with mode: 0644]
QuarkPlatformPkg/Acpi/Dxe/AcpiPlatform/AcpiPlatform.inf [new file with mode: 0644]
QuarkPlatformPkg/Acpi/Dxe/AcpiPlatform/Madt.h [new file with mode: 0644]
QuarkPlatformPkg/Acpi/Dxe/AcpiPlatform/MadtPlatform.c [new file with mode: 0644]
QuarkPlatformPkg/Acpi/Dxe/BootScriptExecutorDxe/BootScriptExecutorDxe.inf [new file with mode: 0644]
QuarkPlatformPkg/Acpi/Dxe/BootScriptExecutorDxe/IA32/S3Asm.S [new file with mode: 0644]
QuarkPlatformPkg/Acpi/Dxe/BootScriptExecutorDxe/IA32/S3Asm.asm [new file with mode: 0644]
QuarkPlatformPkg/Acpi/Dxe/BootScriptExecutorDxe/IA32/SetIdtEntry.c [new file with mode: 0644]
QuarkPlatformPkg/Acpi/Dxe/BootScriptExecutorDxe/ScriptExecute.c [new file with mode: 0644]
QuarkPlatformPkg/Acpi/Dxe/BootScriptExecutorDxe/ScriptExecute.h [new file with mode: 0644]
QuarkPlatformPkg/Acpi/DxeSmm/AcpiSmm/AcpiSmmPlatform.c [new file with mode: 0644]
QuarkPlatformPkg/Acpi/DxeSmm/AcpiSmm/AcpiSmmPlatform.h [new file with mode: 0644]
QuarkPlatformPkg/Acpi/DxeSmm/AcpiSmm/AcpiSmmPlatform.inf [new file with mode: 0644]
QuarkPlatformPkg/Acpi/DxeSmm/SmmPowerManagement/Ppm.c [new file with mode: 0644]
QuarkPlatformPkg/Acpi/DxeSmm/SmmPowerManagement/Ppm.h [new file with mode: 0644]
QuarkPlatformPkg/Acpi/DxeSmm/SmmPowerManagement/SmmPowerManagement.c [new file with mode: 0644]
QuarkPlatformPkg/Acpi/DxeSmm/SmmPowerManagement/SmmPowerManagement.h [new file with mode: 0644]
QuarkPlatformPkg/Acpi/DxeSmm/SmmPowerManagement/SmmPowerManagement.inf [new file with mode: 0644]
QuarkPlatformPkg/Contributions.txt [new file with mode: 0644]
QuarkPlatformPkg/Include/Guid/CapsuleOnDataCD.h [new file with mode: 0644]
QuarkPlatformPkg/Include/Guid/CapsuleOnFatFloppyDisk.h [new file with mode: 0644]
QuarkPlatformPkg/Include/Guid/CapsuleOnFatIdeDisk.h [new file with mode: 0644]
QuarkPlatformPkg/Include/Guid/CapsuleOnFatUsbDisk.h [new file with mode: 0644]
QuarkPlatformPkg/Include/Guid/MemoryConfigData.h [new file with mode: 0644]
QuarkPlatformPkg/Include/Guid/QuarkCapsuleGuid.h [new file with mode: 0644]
QuarkPlatformPkg/Include/Guid/QuarkVariableLock.h [new file with mode: 0644]
QuarkPlatformPkg/Include/Guid/SystemNvDataHobGuid.h [new file with mode: 0644]
QuarkPlatformPkg/Include/Library/PlatformHelperLib.h [new file with mode: 0644]
QuarkPlatformPkg/Include/Library/PlatformPcieHelperLib.h [new file with mode: 0644]
QuarkPlatformPkg/Include/Library/RecoveryOemHookLib.h [new file with mode: 0644]
QuarkPlatformPkg/Include/Pcal9555.h [new file with mode: 0644]
QuarkPlatformPkg/Include/Platform.h [new file with mode: 0644]
QuarkPlatformPkg/Include/PlatformBoards.h [new file with mode: 0644]
QuarkPlatformPkg/Include/Protocol/GlobalNvsArea.h [new file with mode: 0644]
QuarkPlatformPkg/Include/Protocol/PlatformSmmSpiReady.h [new file with mode: 0644]
QuarkPlatformPkg/Library/PlatformBootManagerLib/PlatformBootManager.c [new file with mode: 0644]
QuarkPlatformPkg/Library/PlatformBootManagerLib/PlatformBootManager.h [new file with mode: 0644]
QuarkPlatformPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf [new file with mode: 0644]
QuarkPlatformPkg/Library/PlatformBootManagerLib/PlatformData.c [new file with mode: 0644]
QuarkPlatformPkg/Library/PlatformHelperLib/CommonHeader.h [new file with mode: 0644]
QuarkPlatformPkg/Library/PlatformHelperLib/DxePlatformHelperLib.inf [new file with mode: 0644]
QuarkPlatformPkg/Library/PlatformHelperLib/PeiPlatformHelperLib.inf [new file with mode: 0644]
QuarkPlatformPkg/Library/PlatformHelperLib/PlatformHelperDxe.c [new file with mode: 0644]
QuarkPlatformPkg/Library/PlatformHelperLib/PlatformHelperLib.c [new file with mode: 0644]
QuarkPlatformPkg/Library/PlatformHelperLib/PlatformHelperPei.c [new file with mode: 0644]
QuarkPlatformPkg/Library/PlatformHelperLib/PlatformLeds.c [new file with mode: 0644]
QuarkPlatformPkg/Library/PlatformPcieHelperLib/CommonHeader.h [new file with mode: 0644]
QuarkPlatformPkg/Library/PlatformPcieHelperLib/PlatformPcieHelperLib.c [new file with mode: 0644]
QuarkPlatformPkg/Library/PlatformPcieHelperLib/SocUnit.c [new file with mode: 0644]
QuarkPlatformPkg/Library/PlatformSecLib/Ia32/Flat32.S [new file with mode: 0644]
QuarkPlatformPkg/Library/PlatformSecLib/Ia32/Flat32.asm [new file with mode: 0644]
QuarkPlatformPkg/Library/PlatformSecLib/Ia32/Platform.inc [new file with mode: 0644]
QuarkPlatformPkg/Library/PlatformSecLib/PlatformSecLib.c [new file with mode: 0644]
QuarkPlatformPkg/Library/PlatformSecLib/PlatformSecLib.inf [new file with mode: 0644]
QuarkPlatformPkg/Library/PlatformSecLib/PlatformSecLibModStrs.uni [new file with mode: 0644]
QuarkPlatformPkg/Library/PlatformSecureLib/PlatformSecureLib.c [new file with mode: 0644]
QuarkPlatformPkg/Library/PlatformSecureLib/PlatformSecureLib.inf [new file with mode: 0644]
QuarkPlatformPkg/Library/RecoveryOemHookLib/CommonHeader.h [new file with mode: 0644]
QuarkPlatformPkg/Library/RecoveryOemHookLib/RecoveryOemHookLib.c [new file with mode: 0644]
QuarkPlatformPkg/Library/RecoveryOemHookLib/RecoveryOemHookLib.inf [new file with mode: 0644]
QuarkPlatformPkg/License.txt [new file with mode: 0644]
QuarkPlatformPkg/Pci/Dxe/PciHostBridge/PciHostBridge.c [new file with mode: 0644]
QuarkPlatformPkg/Pci/Dxe/PciHostBridge/PciHostBridge.h [new file with mode: 0644]
QuarkPlatformPkg/Pci/Dxe/PciHostBridge/PciHostBridge.inf [new file with mode: 0644]
QuarkPlatformPkg/Pci/Dxe/PciHostBridge/PciHostBridgeSupport.c [new file with mode: 0644]
QuarkPlatformPkg/Pci/Dxe/PciHostBridge/PciHostResource.h [new file with mode: 0644]
QuarkPlatformPkg/Pci/Dxe/PciHostBridge/PciRootBridge.h [new file with mode: 0644]
QuarkPlatformPkg/Pci/Dxe/PciHostBridge/PciRootBridgeIo.c [new file with mode: 0644]
QuarkPlatformPkg/Pci/Dxe/PciPlatform/CommonHeader.h [new file with mode: 0644]
QuarkPlatformPkg/Pci/Dxe/PciPlatform/PciPlatform.c [new file with mode: 0644]
QuarkPlatformPkg/Pci/Dxe/PciPlatform/PciPlatform.h [new file with mode: 0644]
QuarkPlatformPkg/Pci/Dxe/PciPlatform/PciPlatform.inf [new file with mode: 0644]
QuarkPlatformPkg/Platform/Dxe/MemorySubClass/MemorySubClass.c [new file with mode: 0644]
QuarkPlatformPkg/Platform/Dxe/MemorySubClass/MemorySubClass.h [new file with mode: 0644]
QuarkPlatformPkg/Platform/Dxe/MemorySubClass/MemorySubClass.inf [new file with mode: 0644]
QuarkPlatformPkg/Platform/Dxe/MemorySubClass/MemorySubClassStrings.uni [new file with mode: 0644]
QuarkPlatformPkg/Platform/Dxe/PlatformInit/PlatformConfig.c [new file with mode: 0644]
QuarkPlatformPkg/Platform/Dxe/PlatformInit/PlatformInitDxe.c [new file with mode: 0644]
QuarkPlatformPkg/Platform/Dxe/PlatformInit/PlatformInitDxe.h [new file with mode: 0644]
QuarkPlatformPkg/Platform/Dxe/PlatformInit/PlatformInitDxe.inf [new file with mode: 0644]
QuarkPlatformPkg/Platform/Dxe/SaveMemoryConfig/SaveMemoryConfig.c [new file with mode: 0644]
QuarkPlatformPkg/Platform/Dxe/SaveMemoryConfig/SaveMemoryConfig.inf [new file with mode: 0644]
QuarkPlatformPkg/Platform/Dxe/Setup/CommonHeader.h [new file with mode: 0644]
QuarkPlatformPkg/Platform/Dxe/Setup/DxePlatform.inf [new file with mode: 0644]
QuarkPlatformPkg/Platform/Dxe/Setup/KeyboardLayout.c [new file with mode: 0644]
QuarkPlatformPkg/Platform/Dxe/Setup/QNCRegTable.c [new file with mode: 0644]
QuarkPlatformPkg/Platform/Dxe/Setup/SetupPlatform.c [new file with mode: 0644]
QuarkPlatformPkg/Platform/Dxe/Setup/SetupPlatform.h [new file with mode: 0644]
QuarkPlatformPkg/Platform/Dxe/Setup/Strings.uni [new file with mode: 0644]
QuarkPlatformPkg/Platform/Dxe/Setup/processor.c [new file with mode: 0644]
QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/CommonHeader.h [new file with mode: 0644]
QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscBaseBoardManufacturer.uni [new file with mode: 0644]
QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscBaseBoardManufacturerData.c [new file with mode: 0644]
QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscBaseBoardManufacturerFunction.c [new file with mode: 0644]
QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscBiosVendor.uni [new file with mode: 0644]
QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscBiosVendorData.c [new file with mode: 0644]
QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscBiosVendorFunction.c [new file with mode: 0644]
QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscBootInformationData.c [new file with mode: 0644]
QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscBootInformationFunction.c [new file with mode: 0644]
QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscChassisManufacturer.uni [new file with mode: 0644]
QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscChassisManufacturerData.c [new file with mode: 0644]
QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscChassisManufacturerFunction.c [new file with mode: 0644]
QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscDevicePath.h [new file with mode: 0644]
QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscNumberOfInstallableLanguagesData.c [new file with mode: 0644]
QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscNumberOfInstallableLanguagesFunction.c [new file with mode: 0644]
QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscOemString.uni [new file with mode: 0644]
QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscOemStringData.c [new file with mode: 0644]
QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscOemStringFunction.c [new file with mode: 0644]
QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscOnboardDevice.uni [new file with mode: 0644]
QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscOnboardDeviceData.c [new file with mode: 0644]
QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscOnboardDeviceFunction.c [new file with mode: 0644]
QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscPortInternalConnectorDesignator.uni [new file with mode: 0644]
QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscPortInternalConnectorDesignatorData.c [new file with mode: 0644]
QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscPortInternalConnectorDesignatorFunction.c [new file with mode: 0644]
QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscSystemManufacturer.uni [new file with mode: 0644]
QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscSystemManufacturerData.c [new file with mode: 0644]
QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscSystemManufacturerFunction.c [new file with mode: 0644]
QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscSystemOptionString.uni [new file with mode: 0644]
QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscSystemOptionStringData.c [new file with mode: 0644]
QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscSystemOptionStringFunction.c [new file with mode: 0644]
QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscSystemSlotDesignation.uni [new file with mode: 0644]
QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscSystemSlotDesignationData.c [new file with mode: 0644]
QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscSystemSlotDesignationFunction.c [new file with mode: 0644]
QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/MiscSystemSlotOnboardDevices.uni [new file with mode: 0644]
QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/SmbiosMisc.h [new file with mode: 0644]
QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/SmbiosMiscDataTable.c [new file with mode: 0644]
QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/SmbiosMiscDxe.inf [new file with mode: 0644]
QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/SmbiosMiscEntryPoint.c [new file with mode: 0644]
QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/SmbiosMiscStrings.uni [new file with mode: 0644]
QuarkPlatformPkg/Platform/Pei/PlatformConfig/PlatformConfigPei.c [new file with mode: 0644]
QuarkPlatformPkg/Platform/Pei/PlatformConfig/PlatformConfigPei.inf [new file with mode: 0644]
QuarkPlatformPkg/Platform/Pei/PlatformInit/BootMode.c [new file with mode: 0644]
QuarkPlatformPkg/Platform/Pei/PlatformInit/CommonHeader.h [new file with mode: 0644]
QuarkPlatformPkg/Platform/Pei/PlatformInit/Generic/Recovery.c [new file with mode: 0644]
QuarkPlatformPkg/Platform/Pei/PlatformInit/MemoryCallback.c [new file with mode: 0644]
QuarkPlatformPkg/Platform/Pei/PlatformInit/MrcWrapper.c [new file with mode: 0644]
QuarkPlatformPkg/Platform/Pei/PlatformInit/MrcWrapper.h [new file with mode: 0644]
QuarkPlatformPkg/Platform/Pei/PlatformInit/PeiFvSecurity.c [new file with mode: 0644]
QuarkPlatformPkg/Platform/Pei/PlatformInit/PeiFvSecurity.h [new file with mode: 0644]
QuarkPlatformPkg/Platform/Pei/PlatformInit/PlatformEarlyInit.c [new file with mode: 0644]
QuarkPlatformPkg/Platform/Pei/PlatformInit/PlatformEarlyInit.h [new file with mode: 0644]
QuarkPlatformPkg/Platform/Pei/PlatformInit/PlatformEarlyInit.inf [new file with mode: 0644]
QuarkPlatformPkg/Platform/Pei/PlatformInit/PlatformErratas.c [new file with mode: 0644]
QuarkPlatformPkg/Platform/SpiFvbServices/FvbInfo.c [new file with mode: 0644]
QuarkPlatformPkg/Platform/SpiFvbServices/FwBlockService.c [new file with mode: 0644]
QuarkPlatformPkg/Platform/SpiFvbServices/FwBlockService.h [new file with mode: 0644]
QuarkPlatformPkg/Platform/SpiFvbServices/PlatformSmmSpi.c [new file with mode: 0644]
QuarkPlatformPkg/Platform/SpiFvbServices/PlatformSmmSpi.inf [new file with mode: 0644]
QuarkPlatformPkg/Platform/SpiFvbServices/PlatformSpi.inf [new file with mode: 0644]
QuarkPlatformPkg/Platform/SpiFvbServices/SpiFlashDevice.c [new file with mode: 0644]
QuarkPlatformPkg/Platform/SpiFvbServices/SpiFlashDevice.h [new file with mode: 0644]
QuarkPlatformPkg/Quark.dsc [new file with mode: 0644]
QuarkPlatformPkg/Quark.fdf [new file with mode: 0644]
QuarkPlatformPkg/QuarkMin.dsc [new file with mode: 0644]
QuarkPlatformPkg/QuarkMin.fdf [new file with mode: 0644]
QuarkPlatformPkg/QuarkPlatformPkg.dec [new file with mode: 0644]

diff --git a/QuarkPlatformPkg/Acpi/AcpiTables/AcpiTables.inf b/QuarkPlatformPkg/Acpi/AcpiTables/AcpiTables.inf
new file mode 100644 (file)
index 0000000..be00853
--- /dev/null
@@ -0,0 +1,48 @@
+## @file\r
+# Component description file for PlatformAcpiTable module.\r
+#\r
+# Build acpi table data required by system boot.\r
+# All .asi files tagged with "ToolCode="DUMMY"" in following\r
+# file list are device description and are included by top\r
+# level ASL file which will be dealed with by asl.exe application.\r
+#\r
+# Copyright (c) 2013-2015 Intel Corporation.\r
+#\r
+# This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution.  The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php\r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+##\r
+\r
+[Defines]\r
+  INF_VERSION                    = 0x00010005\r
+  BASE_NAME                      = AcpiTables\r
+  FILE_GUID                      = 7E374E25-8E01-4FEE-87F2-390C23C606CD\r
+  MODULE_TYPE                    = USER_DEFINED\r
+  VERSION_STRING                 = 1.0\r
+\r
+#\r
+# The following information is for reference only and not required by the build tools.\r
+#\r
+#  VALID_ARCHITECTURES           = IA32 X64 IPF EBC\r
+#\r
+\r
+[Sources]\r
+  Facs/Facs.aslc\r
+  Fadt/Fadt2.0.aslc\r
+  Hpet/Hpet.aslc\r
+  Mcfg/Mcfg.aslc\r
+  Dsdt/Platform.asl\r
+  CpuPm/CpuPm.asl\r
+  Cpu0Cst/Cpu0Cst.asl\r
+  Cpu0Ist/Cpu0Ist.asl\r
+  Cpu0Tst/Cpu0Tst.asl\r
+\r
+[Packages]\r
+  MdePkg/MdePkg.dec\r
+  QuarkPlatformPkg/QuarkPlatformPkg.dec\r
+  QuarkSocPkg/QuarkSocPkg.dec\r
diff --git a/QuarkPlatformPkg/Acpi/AcpiTables/Cpu0Cst/Cpu0Cst.asl b/QuarkPlatformPkg/Acpi/AcpiTables/Cpu0Cst/Cpu0Cst.asl
new file mode 100644 (file)
index 0000000..d2f6eab
--- /dev/null
@@ -0,0 +1,405 @@
+/** @file\r
+CPU C State control methods\r
+\r
+Copyright (c) 2013-2015 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution.  The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+DefinitionBlock (\r
+    "Cpu0Cst.aml",\r
+    "SSDT",\r
+    0x01,\r
+    "SsgPmm",\r
+    "Cpu0Cst",\r
+    0x0011\r
+    )\r
+{\r
+    External(\_PR.CPU0, DeviceObj)\r
+    External (PDC0, IntObj)\r
+    External (CFGD, FieldUnitObj)\r
+\r
+    Scope(\_PR.CPU0)\r
+    {\r
+        Method (_CST, 0)\r
+        {\r
+            // If CMP is supported, and OSPM is not capable of independent C1, P, T state\r
+            // support for each processor for multi-processor configuration, we will just report\r
+            // C1 halt\r
+            //\r
+            // PDCx[4] = Indicates whether OSPM is not capable of independent C1, P, T state\r
+            // support for each processor for multi-processor configuration.\r
+            //\r
+            If(LAnd(And(CFGD,0x01000000), LNot(And(PDC0,0x10))))\r
+            {\r
+              Return(Package() {\r
+                1,\r
+                Package()\r
+                { // C1 halt\r
+                  ResourceTemplate(){Register(FFixedHW, 0, 0, 0)},\r
+                  1,\r
+                  157,\r
+                  1000\r
+                }\r
+              })\r
+            }\r
+\r
+            //\r
+            // If MWAIT extensions is supported and OSPM is capable of performing\r
+            // native C state instructions for the C2/C3 in multi-processor configuration,\r
+            // we report every c state with MWAIT extensions.\r
+            //\r
+            // PDCx[9] = Indicates whether OSPM is capable of performing native C state instructions\r
+            // for the C2/C3 in multi-processor configuration\r
+            //\r
+            If(LAnd(And(CFGD, 0x200000), And(PDC0,0x200)))\r
+            {\r
+              //\r
+              // If C6 is supported, we report MWAIT C1,C2,C4,C6\r
+              //\r
+              If(And(CFGD,0x200))\r
+              {\r
+                Return( Package()\r
+                {\r
+                  4,\r
+                  Package()\r
+                  { // MWAIT C1, hardware coordinated with no bus master avoidance\r
+                    ResourceTemplate(){Register(FFixedHW, 1, 2, 0x00, 1)},\r
+                    1,\r
+                    1,\r
+                    1000\r
+                  },\r
+                  Package()\r
+                  { // MWAIT C2, hardware coordinated with no bus master avoidance\r
+                    ResourceTemplate(){Register(FFixedHW, 1, 2, 0x10, 1)},\r
+                    2,\r
+                    20,\r
+                    500\r
+                  },\r
+                  Package()\r
+                  { // MWAIT C4, hardware coordinated with bus master avoidance enabled\r
+                    ResourceTemplate(){Register(FFixedHW, 1, 2, 0x30, 3)},\r
+                    3,\r
+                    100,\r
+                    100\r
+                  },\r
+                  Package()\r
+                  { // MWAIT C6, hardware coordinated with bus master avoidance enabled\r
+                    ResourceTemplate(){Register(FFixedHW, 1, 2, 0x50, 3)},\r
+                    3,\r
+                    140,\r
+                    10\r
+                  }\r
+                })\r
+              }\r
+              //\r
+              // If C4 is supported, we report MWAIT C1,C2,C4\r
+              //\r
+              If(And(CFGD,0x080))\r
+              {\r
+                Return( Package()\r
+                {\r
+                  3,\r
+                  Package()\r
+                  { // MWAIT C1, hardware coordinated with no bus master avoidance\r
+                    ResourceTemplate(){Register(FFixedHW, 1, 2, 0x00, 1)},\r
+                    1,\r
+                    1,\r
+                    1000\r
+                  },\r
+                  Package()\r
+                  { // MWAIT C2, hardware coordinated with no bus master avoidance\r
+                    ResourceTemplate(){Register(FFixedHW, 1, 2, 0x10, 1)},\r
+                    2,\r
+                    20,\r
+                    500\r
+                  },\r
+                  Package()\r
+                  { // MWAIT C4, hardware coordinated with bus master avoidance enabled\r
+                    ResourceTemplate(){Register(FFixedHW, 1, 2, 0x30, 3)},\r
+                    3,\r
+                    100,\r
+                    100\r
+                  }\r
+                })\r
+              }\r
+              //\r
+              // If C2 is supported, we report MWAIT C1,C2\r
+              //\r
+              If(And(CFGD,0x020))\r
+              {\r
+                Return( Package()\r
+                {\r
+                  2,\r
+                  Package()\r
+                  { // MWAIT C1, hardware coordinated with no bus master avoidance\r
+                    ResourceTemplate(){Register(FFixedHW, 1, 2, 0x00, 1)},\r
+                    1,\r
+                    1,\r
+                    1000\r
+                  },\r
+                  Package()\r
+                  { // MWAIT C2, hardware coordinated with no bus master avoidance\r
+                    ResourceTemplate(){Register(FFixedHW, 1, 2, 0x10, 1)},\r
+                    2,\r
+                    20,\r
+                    500\r
+                  }\r
+                })\r
+              }\r
+              //\r
+              // Else we only report MWAIT C1.\r
+              //\r
+              Return(Package()\r
+              {\r
+                1,\r
+                Package()\r
+                { // MWAIT C1, hardware coordinated with no bus master avoidance\r
+                  ResourceTemplate () {Register(FFixedHW, 1, 2, 0x00, 1)},\r
+                  1,\r
+                  1,\r
+                  1000\r
+                }\r
+              })\r
+            }\r
+\r
+            // If OSPM is only capable of performing native C state instructions for\r
+            // the C1 in multi-processor configuration, we report C1 with MWAIT, other\r
+            // C states with IO method.\r
+            //\r
+            // PDCx[8] = Indicates whether OSPM is capable of performing native C state instructions\r
+            // for the C1 in multi-processor configuration\r
+            //\r
+            If(LAnd(And(CFGD, 0x200000), And(PDC0,0x100)))\r
+            {\r
+              //\r
+              // If C6 is supported, we report MWAIT C1, IO C2,C4,C6\r
+              //\r
+              If(And(CFGD,0x200))\r
+              {\r
+                Return( Package()\r
+                {\r
+                  4,\r
+                  Package()\r
+                  { // MWAIT C1, hardware coordinated with no bus master avoidance\r
+                    ResourceTemplate () {Register(FFixedHW, 1, 2, 0x00, 1)},\r
+                    1,\r
+                    1,\r
+                    1000\r
+                  },\r
+                  Package()\r
+                  { // IO C2 ("PMBALVL2" will be updated at runtime)\r
+                    ResourceTemplate () {Register(SystemIO, 8, 0, 0x324C564C41424D50)},\r
+                    2,\r
+                    20,\r
+                    500\r
+                    },\r
+                  Package()\r
+                  { // IO C4 ("PMBALVL4" will be updated at runtime)\r
+                    ResourceTemplate () {Register(SystemIO, 8, 0, 0x344C564C41424D50)},\r
+                    3,\r
+                    100,\r
+                    100\r
+                  },\r
+                  Package()\r
+                  { // IO C6 ("PMBALVL6" will be updated at runtime)\r
+                    ResourceTemplate () {Register(SystemIO, 8, 0, 0x364C564C41424D50)},\r
+                    3,\r
+                    140,\r
+                    10\r
+                  }\r
+                })\r
+              }\r
+              //\r
+              // If C4 is supported, we report MWAIT C1, IO C2,C4\r
+              //\r
+              If(And(CFGD,0x080))\r
+              {\r
+                Return( Package()\r
+                {\r
+                  3,\r
+                  Package()\r
+                  { // MWAIT C1, hardware coordinated with no bus master avoidance\r
+                    ResourceTemplate () {Register(FFixedHW, 1, 2, 0x00, 1)},\r
+                    1,\r
+                    1,\r
+                    1000\r
+                  },\r
+                  Package()\r
+                  { // IO C2 ("PMBALVL2" will be updated at runtime)\r
+                    ResourceTemplate () {Register(SystemIO, 8, 0, 0x324C564C41424D50)},\r
+                    2,\r
+                    20,\r
+                    500\r
+                    },\r
+                  Package()\r
+                  { // IO C4 ("PMBALVL4" will be updated at runtime)\r
+                    ResourceTemplate () {Register(SystemIO, 8, 0, 0x344C564C41424D50)},\r
+                    3,\r
+                    100,\r
+                    100\r
+                  }\r
+                })\r
+              }\r
+              //\r
+              // If C2 is supported, we report MWAIT C1, IO C2\r
+              //\r
+              If(And(CFGD,0x020))\r
+              {\r
+                Return( Package()\r
+                {\r
+                  2,\r
+                  Package()\r
+                  { // MWAIT C1, hardware coordinated with no bus master avoidance\r
+                    ResourceTemplate () {Register(FFixedHW, 1, 2, 0x00, 1)},\r
+                    1,\r
+                    1,\r
+                    1000\r
+                  },\r
+                  Package()\r
+                  { // IO C2 ("PMBALVL2" will be updated at runtime)\r
+                    ResourceTemplate () {Register(SystemIO, 8, 0, 0x324C564C41424D50)},\r
+                    2,\r
+                    20,\r
+                    500\r
+                  }\r
+                })\r
+              }\r
+              //\r
+              // Else we only report MWAIT C1.\r
+              //\r
+              Return(Package()\r
+              {\r
+                1,\r
+                Package()\r
+                { // MWAIT C1, hardware coordinated with no bus master avoidance\r
+                  ResourceTemplate () {Register(FFixedHW, 1, 2, 0x00, 1)},\r
+                  1,\r
+                  1,\r
+                  1000\r
+                }\r
+              })\r
+            }\r
+\r
+            //\r
+            // If MWAIT is not supported, we report all the c states with IO method\r
+            //\r
+\r
+            //\r
+            // If C6 is supported, we report C1 halt, IO C2,C4,C6\r
+            //\r
+            If(And(CFGD,0x200))\r
+            {\r
+              Return(Package()\r
+              {\r
+                4,\r
+                Package()\r
+                { // C1 Halt\r
+                  ResourceTemplate () {Register(FFixedHW, 0, 0, 0)},\r
+                  1,\r
+                  1,\r
+                  1000\r
+                },\r
+                Package()\r
+                { // IO C2 ("PMBALVL2" will be updated at runtime)\r
+                  ResourceTemplate () {Register(SystemIO, 8, 0, 0x324C564C41424D50)},\r
+                  2,\r
+                  20,\r
+                  500\r
+                },\r
+                Package()\r
+                { // IO C4 ("PMBALVL4" will be updated at runtime)\r
+                  ResourceTemplate () {Register(SystemIO, 8, 0, 0x344C564C41424D50)},\r
+                  3,\r
+                  100,\r
+                  100\r
+                },\r
+                Package()\r
+                { // IO C6 ("PMBALVL6" will be updated at runtime)\r
+                  ResourceTemplate () {Register(SystemIO, 8, 0, 0x364C564C41424D50)},\r
+                  3,\r
+                  140,\r
+                  10\r
+                }\r
+              })\r
+            }\r
+            //\r
+            // If C4 is supported, we report C1 halt, IO C2,C4\r
+            //\r
+            If(And(CFGD,0x080))\r
+            {\r
+              Return(Package()\r
+              {\r
+                3,\r
+                Package()\r
+                { // C1 halt\r
+                  ResourceTemplate () {Register(FFixedHW, 0, 0, 0)},\r
+                  1,\r
+                  1,\r
+                  1000\r
+                },\r
+                Package()\r
+                { // IO C2 ("PMBALVL2" will be updated at runtime)\r
+                  ResourceTemplate () {Register(SystemIO, 8, 0, 0x324C564C41424D50)},\r
+                  2,\r
+                  20,\r
+                  500\r
+                },\r
+                Package()\r
+                { // IO C4 ("PMBALVL4" will be updated at runtime)\r
+                  ResourceTemplate () {Register(SystemIO, 8, 0, 0x344C564C41424D50)},\r
+                  3,\r
+                  100,\r
+                  100\r
+                }\r
+              })\r
+            }\r
+\r
+            //\r
+            // If C2 is supported, we report C1 halt, IO C2\r
+            //\r
+            If(And(CFGD,0x020))\r
+            {\r
+              Return(Package()\r
+              {\r
+                2,\r
+                Package()\r
+                { // C1 halt\r
+                  ResourceTemplate () {Register(FFixedHW, 0, 0, 0)},\r
+                  1,\r
+                  1,\r
+                  1000\r
+                },\r
+                Package()\r
+                { // IO C2 ("PMBALVL2" will be updated at runtime)\r
+                  ResourceTemplate () {Register(SystemIO, 8, 0, 0x324C564C41424D50)},\r
+                  2,\r
+                  20,\r
+                  500\r
+                }\r
+              })\r
+            }\r
+            //\r
+            // Else we only report C1 halt.\r
+            //\r
+            Return(Package()\r
+            {\r
+              1,\r
+              Package()\r
+              { // C1 halt\r
+                ResourceTemplate () {Register(FFixedHW, 0, 0, 0)},\r
+                1,\r
+                1,\r
+                1000\r
+              }\r
+            })\r
+        }\r
+    }\r
+}\r
diff --git a/QuarkPlatformPkg/Acpi/AcpiTables/Cpu0Ist/Cpu0Ist.asl b/QuarkPlatformPkg/Acpi/AcpiTables/Cpu0Ist/Cpu0Ist.asl
new file mode 100644 (file)
index 0000000..5abd5cb
--- /dev/null
@@ -0,0 +1,165 @@
+/** @file\r
+CPU EIST control methods\r
+\r
+Copyright (c) 2013-2015 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution.  The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+DefinitionBlock (\r
+    "CPU0IST.aml",\r
+    "SSDT",\r
+    0x01,\r
+    "SsgPmm",\r
+    "Cpu0Ist",\r
+    0x0012\r
+    )\r
+{\r
+    External (PDC0, IntObj)\r
+    External (CFGD, FieldUnitObj)\r
+    External(\_PR.CPU0, DeviceObj)\r
+\r
+    Scope(\_PR.CPU0)\r
+    {\r
+        Method(_PPC,0)\r
+        {\r
+            Return(ZERO)   // Return All States Available.\r
+        }\r
+\r
+        Method(_PCT,0)\r
+        {\r
+            //\r
+            // If GV3 is supported and OSPM is capable of direct access to\r
+            // performance state MSR, we use MSR method\r
+            //\r
+            //\r
+            // PDCx[0] = Indicates whether OSPM is capable of direct access to\r
+            // performance state MSR.\r
+            //\r
+            If(LAnd(And(CFGD,0x0001), And(PDC0,0x0001)))\r
+            {\r
+                Return(Package()    // MSR Method\r
+                {\r
+                    ResourceTemplate(){Register(FFixedHW, 0, 0, 0)},\r
+                    ResourceTemplate(){Register(FFixedHW, 0, 0, 0)}\r
+                })\r
+\r
+            }\r
+\r
+            //\r
+            // Otherwise, we use smi method\r
+            //\r
+            Return(Package()    // SMI Method\r
+                {\r
+                  ResourceTemplate(){Register(SystemIO,16,0,0xB2)},\r
+                  ResourceTemplate(){Register(SystemIO, 8,0,0xB3)}\r
+                })\r
+        }\r
+\r
+        Method(_PSS,0)\r
+        {\r
+            //\r
+            // If OSPM is capable of direct access to performance state MSR,\r
+            // we report NPSS, otherwise, we report SPSS.\r
+            If (And(PDC0,0x0001))\r
+            {\r
+                Return(NPSS)\r
+            }\r
+\r
+            Return(SPSS)\r
+        }\r
+\r
+        Name(SPSS,Package()\r
+        {\r
+            Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r
+            Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r
+            Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r
+            Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r
+            Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r
+            Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r
+            Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r
+            Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r
+            Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r
+            Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r
+            Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r
+            Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000}\r
+        })\r
+\r
+        Name(NPSS,Package()\r
+        {\r
+            Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r
+            Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r
+            Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r
+            Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r
+            Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r
+            Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r
+            Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r
+            Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r
+            Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r
+            Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r
+            Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r
+            Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000}\r
+        })\r
+\r
+        Method(_PSD,0)\r
+        {\r
+          //\r
+          // If CMP is suppored, we report the dependency with two processors\r
+          //\r
+          If(And(CFGD,0x1000000))\r
+          {\r
+            //\r
+            // If OSPM is capable of hardware coordination of P-states, we report\r
+            // the dependency with hardware coordination.\r
+            //\r
+            // PDCx[11] = Indicates whether OSPM is capable of hardware coordination of P-states\r
+            //\r
+            If(And(PDC0,0x0800))\r
+            {\r
+              Return(Package(){\r
+                Package(){\r
+                  5,  // # entries.\r
+                  0,  // Revision.\r
+                  0,  // Domain #.\r
+                  0xFE,  // Coord Type- HW_ALL.\r
+                  2  // # processors.\r
+                }\r
+              })\r
+            }\r
+\r
+            //\r
+            // Otherwise, the dependency with OSPM coordination\r
+            //\r
+            Return(Package(){\r
+              Package(){\r
+                5,    // # entries.\r
+                0,    // Revision.\r
+                0,    // Domain #.\r
+                0xFC, // Coord Type- SW_ALL.\r
+                2     // # processors.\r
+              }\r
+            })\r
+          }\r
+\r
+          //\r
+          //  Otherwise, we report the dependency with one processor\r
+          //\r
+          Return(Package(){\r
+            Package(){\r
+              5,      // # entries.\r
+              0,      // Revision.\r
+              0,      // Domain #.\r
+              0xFC,   // Coord Type- SW_ALL.\r
+              1       // # processors.\r
+            }\r
+          })\r
+        }\r
+    }\r
+}\r
diff --git a/QuarkPlatformPkg/Acpi/AcpiTables/Cpu0Tst/Cpu0Tst.asl b/QuarkPlatformPkg/Acpi/AcpiTables/Cpu0Tst/Cpu0Tst.asl
new file mode 100644 (file)
index 0000000..1c57408
--- /dev/null
@@ -0,0 +1,139 @@
+/** @file\r
+CPU T-state control methods\r
+\r
+Copyright (c) 2013-2015 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution.  The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+DefinitionBlock (\r
+    "CPU0TST.aml",\r
+    "SSDT",\r
+    0x01,\r
+    "SsgPmm",\r
+    "Cpu0Tst",\r
+    0x0013\r
+    )\r
+{\r
+    External (PDC0, IntObj)\r
+    External (CFGD, FieldUnitObj)\r
+    External(\_PR.CPU0, DeviceObj)\r
+    External(_PSS)\r
+\r
+    Scope(\_PR.CPU0)\r
+    {\r
+        Method(_TPC,0)\r
+        {\r
+            Return(ZERO)   // Return All States Available.\r
+        }\r
+\r
+        Name(TPTC, ResourceTemplate()\r
+        {\r
+            Memory32Fixed(ReadOnly, 0, 0, FIX1) // IO APIC\r
+        })\r
+\r
+        //\r
+        // If OSPM is capable of direct access to on demand throttling MSR,\r
+        // we use MSR method;otherwise we use IO method.\r
+        //\r
+        //\r
+        // PDCx[2] = Indicates whether OSPM is capable of direct access to\r
+        // on demand throttling MSR.\r
+        //\r
+        Method(_PTC, 0)\r
+        {\r
+          If(And(PDC0, 0x0004))\r
+          {\r
+            Return(Package() // MSR Method\r
+            {\r
+              ResourceTemplate(){Register(FFixedHW, 0, 0, 0)},\r
+              ResourceTemplate(){Register(FFixedHW, 0, 0, 0)}\r
+            }\r
+            )\r
+          }\r
+          Return(Package() // IO Method\r
+          {\r
+            //\r
+            // PM IO base ("PMBALVL0" will be updated at runtime)\r
+            //\r
+            ResourceTemplate(){Register(SystemIO, 4, 1, 0x304C564C41424D50)},\r
+            ResourceTemplate(){Register(SystemIO, 4, 1, 0x304C564C41424D50)}\r
+          }\r
+          )\r
+        }\r
+\r
+        //\r
+        // _TSS returned package for IO Method\r
+        //\r
+        Name(TSSI, Package()\r
+        {\r
+          Package(){100, 1000, 0, 0x00, 0}\r
+        }\r
+        )\r
+        //\r
+        // _TSS returned package for MSR Method\r
+        //\r
+        Name(TSSM, Package()\r
+        {\r
+          Package(){100, 1000, 0, 0x00, 0}\r
+        }\r
+        )\r
+\r
+        Method(_TSS, 0)\r
+        {\r
+          //\r
+          // If OSPM is capable of direct access to on demand throttling MSR,\r
+          // we report TSSM;otherwise report TSSI.\r
+          //\r
+          If(And(PDC0, 0x0004))\r
+          {\r
+            Return(TSSM)\r
+          }\r
+          Return(TSSI)\r
+        }\r
+\r
+        Method(_TSD, 0)\r
+        {\r
+          //\r
+          // If CMP is suppored, we report the dependency with two processors\r
+          //\r
+          If(LAnd(And(CFGD, 0x1000000), LNot(And(PDC0, 4))))\r
+          {\r
+            Return(Package()\r
+            {\r
+              Package()\r
+              {\r
+                5,    // # entries.\r
+                0,    // Revision.\r
+                0,    // Domain #.\r
+                0xFD, // Coord Type- SW_ANY\r
+                2     // # processors.\r
+              }\r
+            }\r
+            )\r
+          }\r
+          //\r
+          // Otherwise, we report the dependency with one processor\r
+          //\r
+          Return(Package()\r
+          {\r
+            Package()\r
+            {\r
+              5,        // # entries.\r
+              0,        // Revision.\r
+              0,        // Domain #.\r
+              0xFC,     // Coord Type- SW_ALL\r
+              1         // # processors.\r
+            }\r
+          }\r
+          )\r
+        }\r
+    }\r
+}\r
diff --git a/QuarkPlatformPkg/Acpi/AcpiTables/CpuPm/CpuPm.asl b/QuarkPlatformPkg/Acpi/AcpiTables/CpuPm/CpuPm.asl
new file mode 100644 (file)
index 0000000..a2d059b
--- /dev/null
@@ -0,0 +1,79 @@
+/** @file\r
+CPU power management control methods\r
+\r
+Copyright (c) 2013-2015 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution.  The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+DefinitionBlock (\r
+    "CPUPM.aml",\r
+    "SSDT",\r
+    0x01,\r
+    "SsgPmm",\r
+    "CpuPm",\r
+    0x0010\r
+    )\r
+{\r
+    External(\_PR.CPU0, DeviceObj)\r
+    External(CFGD, FieldUnitObj)\r
+\r
+    Scope(\)\r
+    {\r
+        // Config DWord, modified during POST\r
+        // Bit definitions are the same as PPMFlags:\r
+        //     CFGD[0] = PPM_GV3     = GV3\r
+        //     CFGD[1] = PPM_TURBO   = Turbo Mode\r
+        //     CFGD[2] = PPM_SUPER_LFM = N/2 Ratio\r
+        //     CFGD[4] = PPM_C1      = C1 Capable, Enabled\r
+        //     CFGD[5] = PPM_C2      = C2 Capable, Enabled\r
+        //     CFGD[6] = PPM_C3      = C3 Capable, Enabled\r
+        //     CFGD[7] = PPM_C4      = C4 Capable, Enabled\r
+        //     CFGD[8] = PPM_C5      = C5/Deep C4 Capable, Enabled\r
+        //     CFGD[9] = PPM_C6      = C6 Capable, Enabled\r
+        //     CFGD[10] = PPM_C1E    = C1E Enabled\r
+        //     CFGD[11] = PPM_C2E    = C2E Enabled\r
+        //     CFGD[12] = PPM_C3E    = C3E Enabled\r
+        //     CFGD[13] = PPM_C4E    = C4E Enabled\r
+        //     CFGD[14] = PPM_HARD_C4E = Hard C4E Capable, Enabled\r
+        //     CFGD[16] = PPM_TM1    = Thermal Monitor 1\r
+        //     CFGD[17] = PPM_TM2    = Thermal Monitor 2\r
+        //     CFGD[19] = PPM_PHOT   = Bi-directional ProcHot\r
+        //     CFGD[21] = PPM_MWAIT_EXT = MWAIT extensions supported\r
+        //     CFGD[24] = PPM_CMP    = CMP supported, Enabled\r
+        //     CFGD[28] = PPM_TSTATE = CPU T states supported\r
+        //\r
+        // Name(CFGD, 0x80000000)\r
+        // External Defined in GNVS\r
+\r
+        Name(PDC0,0x80000000)   // CPU0 _PDC Flags.\r
+\r
+        // We load it in AcpiPlatform\r
+        //Name(SSDT,Package()\r
+        //{\r
+        //    "CPU0IST ", 0x80000000, 0x80000000,\r
+        //    "CPU1IST ", 0x80000000, 0x80000000,\r
+        //    "CPU0CST ", 0x80000000, 0x80000000,\r
+        //    "CPU1CST ", 0x80000000, 0x80000000,\r
+        //})\r
+    }\r
+    Scope(\_PR.CPU0)\r
+    {\r
+        Method(_PDC, 1)\r
+        {\r
+          //\r
+          // Store result of PDC.\r
+          //\r
+          CreateDWordField(Arg0,8,CAP0)   // Point to 3rd DWORD.\r
+          Store(CAP0,PDC0)                // Store It in PDC0.\r
+        }\r
+    }\r
+\r
+}\r
diff --git a/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/AD7298.asi b/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/AD7298.asi
new file mode 100644 (file)
index 0000000..52b4886
--- /dev/null
@@ -0,0 +1,44 @@
+/** @file\r
+Analog devices AD7298 ADC.\r
+\r
+Copyright (c) 2013-2015 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution.  The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+Device(ADC1)\r
+{\r
+    Name(_HID, "INT3494") // Galileo Version 1 Low-Speed ADC.\r
+    Name(_CID, "INT3494")\r
+    Name(RBUF, ResourceTemplate()\r
+    {\r
+        // SPI0: mode 2, 4Mhz, 16-bit data length\r
+        SpiSerialBus (0x0000, PolarityLow, FourWireMode, 16, ControllerInitiated, 4000000, ClockPolarityHigh, ClockPhaseFirst, "\\_SB_.PCI0.SPI0",0x00, ResourceConsumer, ,)\r
+\r
+        // GPIO<0> is SPI0_CS_N\r
+        GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.PCI0.GIP0.GPO_", 0, ResourceConsumer, , ) {QUARK_GPIO0_MAPPING}\r
+    })\r
+    Method(_CRS, 0x0, NotSerialized)\r
+    {\r
+        Return(RBUF)\r
+    }\r
+    Method(_STA, 0x0, NotSerialized)\r
+    {\r
+        //\r
+        // Only Galileo platform has this device.\r
+        // EFI_PLATFORM_TYPE enum value Galileo = 6.\r
+        //\r
+        If(LNotEqual(PTYP, 6))\r
+        {\r
+          return (0)\r
+        }\r
+        Return(0xf)\r
+    }\r
+}\r
diff --git a/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/ADC108S102.asi b/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/ADC108S102.asi
new file mode 100644 (file)
index 0000000..47ee58e
--- /dev/null
@@ -0,0 +1,39 @@
+/** @file\r
+TI ADC108S102 ADC.\r
+\r
+Copyright (c) 2013-2015 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution.  The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+Device(ADC2)\r
+{\r
+    Name(_HID, "INT3495") // GalileoGen2 Low-Speed ADC.\r
+    Name(_CID, "INT3495")\r
+    Name(RBUF, ResourceTemplate()\r
+    {\r
+        SPISerialBus(0x0000, PolarityLow, ThreeWireMode, 0x10, ControllerInitiated, 0x1E8480, ClockPolarityLow, ClockPhaseFirst, "\\_SB.PCI0.SPI0", 0x00, ResourceConsumer, ,)\r
+    })\r
+    Method(_CRS, 0x0, NotSerialized)\r
+    {\r
+        Return(RBUF)\r
+    }\r
+    Method(_STA, 0x0, NotSerialized)\r
+    {\r
+        //\r
+        // Only Platform Type / Id 8 has this device.\r
+        //\r
+        If(LNotEqual(PTYP, 8))\r
+        {\r
+          return (0)\r
+        }\r
+        Return(0xf)\r
+    }\r
+}\r
diff --git a/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/CAT24C08.asi b/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/CAT24C08.asi
new file mode 100644 (file)
index 0000000..c8763ce
--- /dev/null
@@ -0,0 +1,40 @@
+/** @file\r
+ONSEMI CAT24C08 I2C 8KB EEPROM.\r
+\r
+Copyright (c) 2013-2015 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution.  The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+Device(EEP2)\r
+{\r
+    Name(_HID, "INT3499") // ONSEMI CAT24C08 I2C 8KB EEPROM.\r
+    Name(_CID, "INT3499")\r
+\r
+    Name(RBUF, ResourceTemplate()\r
+    {\r
+        I2CSerialBus(0x54, ControllerInitiated, 400000, AddressingMode7Bit, "\\_SB.PCI0.GIP0.I2C_", 0, ResourceConsumer, , )\r
+    })\r
+    Method(_CRS, 0x0, NotSerialized)\r
+    {\r
+        Return(RBUF)\r
+    }\r
+    Method(_STA, 0x0, NotSerialized)\r
+    {\r
+        //\r
+        // Only Platform Type / Id 8 has this device.\r
+        //\r
+        If(LNotEqual(PTYP, 8))\r
+        {\r
+          return (0)\r
+        }\r
+        Return(0xf)\r
+    }\r
+}\r
diff --git a/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/CY8C9540A.asi b/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/CY8C9540A.asi
new file mode 100644 (file)
index 0000000..f9c88f2
--- /dev/null
@@ -0,0 +1,53 @@
+/** @file\r
+\r
+Copyright (c) 2013-2015 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution.  The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+CY8C9540A 40 Bit I/O Expander with EEPROM.\r
+\r
+**/\r
+\r
+Device(CY8C)\r
+{\r
+    Name(_HID, "INT3490") // Cypress CY8C9540A Io Expander Function.\r
+    Name(_CID, "INT3490")\r
+\r
+    Name(RBUF, ResourceTemplate()\r
+    {\r
+        I2CSerialBus(0x20, ControllerInitiated, 100000, AddressingMode7Bit, "\\_SB.PCI0.GIP0.I2C_", 0, ResourceConsumer, , )\r
+        GpioInt (Level, ActiveLow, Exclusive, PullDefault, , "\\_SB.PCI0.GIP0.GPO", 0, ResourceConsumer, , ) {QUARK_GPIO5_MAPPING} /* GPIO<5> is INT_S0 */\r
+    })\r
+    Method(_CRS, 0x0, NotSerialized)\r
+    {\r
+        CreateByteField(RBUF, 16, OB1)\r
+        if (LEqual (ALTS, 0))\r
+        {\r
+            Store(0x20, OB1)\r
+        }\r
+        Else\r
+        {\r
+            Store(0x21, OB1)\r
+        }\r
+        Return(RBUF)\r
+    }\r
+    Method(_STA, 0x0, NotSerialized)\r
+    {\r
+        //\r
+        // Only Galileo platform has this device.\r
+        // EFI_PLATFORM_TYPE enum value Galileo = 6.\r
+        //\r
+        If(LNotEqual(PTYP, 6))\r
+        {\r
+          return (0)\r
+        }\r
+        Return(0xf)\r
+    }\r
+}\r
+\r
diff --git a/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/GpioClient.asi b/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/GpioClient.asi
new file mode 100644 (file)
index 0000000..c0ec122
--- /dev/null
@@ -0,0 +1,95 @@
+/** @file\r
+Expose GPIO resources to usermode through client driver.\r
+\r
+Copyright (c) 2013-2015 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution.  The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+Device(GPOT)\r
+{\r
+    Name(_HID, "INT349A")\r
+    Name(_CID, "INT349A")\r
+    Method(_CRS, 0x0, NotSerialized)\r
+    {\r
+        Name(RBUF, ResourceTemplate()\r
+        {\r
+            GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.PCI0.GIP0.GPO_", 0, ResourceConsumer, , ) {0}\r
+            GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.PCI0.GIP0.GPO_", 0, ResourceConsumer, , ) {0x1}\r
+            GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.PCI0.GIP0.GPO_", 0, ResourceConsumer, , ) {0x2}\r
+            GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.PCI0.GIP0.GPO_", 0, ResourceConsumer, , ) {0x3}\r
+            GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.PCI0.GIP0.GPO_", 0, ResourceConsumer, , ) {0x4}\r
+            GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.PCI0.GIP0.GPO_", 0, ResourceConsumer, , ) {0x5}\r
+            GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.PCI0.GIP0.GPO_", 0, ResourceConsumer, , ) {0x6}\r
+            GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.PCI0.GIP0.GPO_", 0, ResourceConsumer, , ) {0x7}\r
+            GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.PCI0.GIP0.GPO_", 0, ResourceConsumer, , ) {0x8}\r
+            GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.PCI0.GIP0.GPO_", 0, ResourceConsumer, , ) {0x9}\r
+            GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.PCI0.GIP0.GPO_", 0, ResourceConsumer, , ) {0xa}\r
+            GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.PCI0.GIP0.GPO_", 0, ResourceConsumer, , ) {0xb}\r
+            GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.PCI0.GIP0.GPO_", 0, ResourceConsumer, , ) {0xc}\r
+            GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.PCI0.GIP0.GPO_", 0, ResourceConsumer, , ) {0xd}\r
+            GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.PCI0.GIP0.GPO_", 0, ResourceConsumer, , ) {0xe}\r
+            GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.PCI0.GIP0.GPO_", 0, ResourceConsumer, , ) {0xf}\r
+            GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0}\r
+            GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0x1}\r
+            GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0x2}\r
+            GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0x3}\r
+            GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0x4}\r
+            GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0x5}\r
+            GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0x6}\r
+            GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0x7}\r
+            GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0x8}\r
+            GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0x9}\r
+            GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0xa}\r
+            GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0xb}\r
+            GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0xc}\r
+            GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0xd}\r
+            GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0xe}\r
+            GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0xf}\r
+            GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0x10}\r
+            GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0x11}\r
+            GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0x12}\r
+            GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0x13}\r
+            GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0x14}\r
+            GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0x15}\r
+            GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0x16}\r
+            GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0x17}\r
+            GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0x18}\r
+            GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0x19}\r
+            GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0x1a}\r
+            GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0x1b}\r
+            GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0x1c}\r
+            GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0x1d}\r
+            GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0x1e}\r
+            GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0x1f}\r
+            GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0x20}\r
+            GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0x21}\r
+            GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0x22}\r
+            GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0x23}\r
+            GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0x24}\r
+            GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0x25}\r
+            GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0x26}\r
+            GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0x27}\r
+        })\r
+        Return(RBUF)\r
+    }\r
+    Method(_STA, 0x0, NotSerialized)\r
+    {\r
+        //\r
+        // Only Galileo platform has this device.\r
+        // EFI_PLATFORM_TYPE enum value Galileo = 6.\r
+        //\r
+        If(LNotEqual(PTYP, 6))\r
+        {\r
+          return (0)\r
+        }\r
+        Return(0xf)\r
+    }\r
+}\r
diff --git a/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/LpcDev.asi b/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/LpcDev.asi
new file mode 100644 (file)
index 0000000..f24a982
--- /dev/null
@@ -0,0 +1,254 @@
+/** @file\r
+Legacy resource template\r
+\r
+Copyright (c) 2013-2015 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution.  The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#ifndef LPC_DEV_ASI\r
+#define LPC_DEV_ASI\r
+\r
+Device(RTC)\r
+{\r
+    Name(_HID,EISAID("PNP0B00"))\r
+    Name(BUF0,ResourceTemplate() {\r
+        IO(Decode16,0x70,0x70,0x01,0x04)\r
+        IO(Decode16,0x74,0x74,0x01,0x04)\r
+    })\r
+    Name(BUF1,ResourceTemplate() {\r
+        IO(Decode16,0x70,0x70,0x01,0x04)\r
+        IO(Decode16,0x74,0x74,0x01,0x04)\r
+        IRQNoFlags(){8}\r
+    })\r
+    Method(_CRS,0,Serialized)\r
+    {\r
+        If (HPEA)\r
+        {\r
+            return (BUF0)\r
+        }\r
+        Else\r
+        {\r
+            return (BUF1)\r
+        }\r
+    }\r
+}\r
+\r
+Device(PIC)\r
+{\r
+    Name(_HID,EISAID("PNP0000"))\r
+\r
+    Name(_CRS,ResourceTemplate() {\r
+        IO(Decode16,0x20,0x20,0x01,0x1E)        // length of 1Eh includes all aliases\r
+        IO(Decode16,0xA0,0xA0,0x01,0x1E)\r
+        IO(Decode16,0x4D0,0x4D0,0x01,0x02)\r
+    })\r
+}\r
+\r
+Device(TMR)\r
+{\r
+    Name(_HID,EISAID("PNP0100"))\r
+\r
+    Name(BUF0,ResourceTemplate() {\r
+        IO(Decode16,0x40,0x40,0x01,0x04)\r
+        IO(Decode16,0x50,0x50,0x01,0x04)        // alias\r
+    })\r
+    Name(BUF1,ResourceTemplate() {\r
+        IO(Decode16,0x40,0x40,0x01,0x04)\r
+        IO(Decode16,0x50,0x50,0x01,0x04)        // alias\r
+        IRQNoFlags(){0}\r
+    })\r
+    Method(_CRS,0,Serialized)\r
+    {\r
+        If (HPEA)\r
+        {\r
+            return (BUF0)\r
+        }\r
+        Else\r
+        {\r
+            return (BUF1)\r
+        }\r
+    }\r
+}\r
+\r
+Device(SPKR)\r
+{\r
+    Name(_HID,EISAID("PNP0800"))\r
+\r
+    Name(_CRS,ResourceTemplate() {\r
+        IO(Decode16,0x61,0x61,0x01,0x01)\r
+    })\r
+}\r
+\r
+Device(XTRA)    // all "PNP0C02" devices- pieces that don't fit anywhere else\r
+{\r
+    Name(_HID,EISAID("PNP0C02"))        // Generic motherboard devices\r
+\r
+    Name(CRS,\r
+        ResourceTemplate()\r
+        {\r
+            IO(Decode16,0x2E,0x2E,0x01,0x02)\r
+            IO(Decode16,0x4E,0x2E,0x01,0x02)\r
+            IO(Decode16,0x63,0x61,0x01,0x01)\r
+            IO(Decode16,0x65,0x61,0x01,0x01)\r
+            IO(Decode16,0x67,0x61,0x01,0x01)\r
+            IO(Decode16,0x80,0x80,0x01,0x01)\r
+            IO(Decode16,0x84,0x84,0x01,0x04)\r
+            IO(Decode16,0x88,0x88,0x01,0x01)\r
+            IO(Decode16,0x8c,0x8c,0x01,0x03)\r
+            IO(Decode16,0x92,0x92,0x01,0x01)\r
+\r
+            IO(\r
+              Decode16,\r
+              0,\r
+              0,\r
+              0x01,\r
+              0x10,\r
+              FIX1\r
+              )\r
+\r
+            IO(\r
+              Decode16,\r
+              0,\r
+              0,\r
+              0x01,\r
+              0x10,\r
+              FIX2\r
+              )\r
+\r
+            IO(\r
+              Decode16,\r
+              0,\r
+              0,\r
+              0x01,\r
+              0x40,\r
+              FIX3\r
+              )\r
+\r
+           IO(\r
+              Decode16,\r
+              0,\r
+              0,\r
+              0x01,\r
+              0x40,\r
+              FIX5\r
+              )\r
+\r
+            IO(\r
+              Decode16,\r
+              0,\r
+              0,\r
+              0x01,\r
+              0x40,\r
+              FIX6\r
+              )\r
+\r
+        }\r
+    )\r
+\r
+    Method (_CRS, 0, NotSerialized) {\r
+      CreateWordField (CRS, ^FIX1._MIN, MBR0)\r
+      Store(\P1BB, MBR0)\r
+      CreateWordField (CRS, ^FIX1._MAX, MBR1)\r
+      Store(\P1BB, MBR1)\r
+      CreateWordField (CRS, ^FIX2._MIN, MBR2)\r
+      Store(\PBAB, MBR2)\r
+      CreateWordField (CRS, ^FIX2._MAX, MBR3)\r
+      Store(\PBAB, MBR3)\r
+      CreateWordField (CRS, ^FIX3._MIN, MBR4)\r
+      Store(\GP0B, MBR4)\r
+      CreateWordField (CRS, ^FIX3._MAX, MBR5)\r
+      Store(\GP0B, MBR5)\r
+      CreateWordField (CRS, ^FIX5._MIN, MBR8)\r
+      Store(\SMBB, MBR8)\r
+      CreateWordField (CRS, ^FIX5._MAX, MBR9)\r
+      Store(\SMBB, MBR9)\r
+      CreateWordField (CRS, ^FIX6._MIN, MBRA)\r
+      Store(\WDTB, MBRA)\r
+      CreateWordField (CRS, ^FIX6._MAX, MBRB)\r
+      Store(\WDTB, MBRB)\r
+      return (CRS)\r
+    }\r
+}\r
+\r
+Device(LGIO)  // Legacy GPIO.\r
+{\r
+    Name(_HID, "INT3488")\r
+    Name(_CID, "INT3488")\r
+\r
+    Name(CRS,\r
+        ResourceTemplate()\r
+        {\r
+            IO(\r
+              Decode16,\r
+              0,\r
+              0,\r
+              0x01,\r
+              0x48,\r
+              FIX4\r
+              )\r
+        }\r
+    )\r
+\r
+    Method (_CRS, 0, NotSerialized) {\r
+      CreateWordField (CRS, ^FIX4._MIN, MBR6)\r
+      Store(\GPAB, MBR6)\r
+      CreateWordField (CRS, ^FIX4._MAX, MBR7)\r
+      Store(\GPAB, MBR7)\r
+      return (CRS)\r
+    }\r
+}\r
+\r
+Device(HPET)  // High Performance Event Timer\r
+{\r
+  Name(_HID,EISAID("PNP0103"))\r
+\r
+  Name(BUF0,ResourceTemplate()\r
+  {\r
+    IRQNoFlags() {0}\r
+    IRQNoFlags() {8}\r
+    Memory32Fixed(ReadOnly, 0, 0, FIX1)\r
+  })\r
+\r
+  Method(_STA,0)\r
+  {\r
+    // Show this Device only if the OS is WINXP or beyond.\r
+\r
+    If(LGreaterEqual(OSTP,WINDOWS_XP))\r
+    {\r
+      If(HPEA)\r
+      {\r
+        Return(0x000F)  // Enabled, do Display.\r
+      }\r
+    }\r
+    Else\r
+    {\r
+      // OS = WIN98, WINME, or WIN2000.\r
+\r
+      If(HPEA)\r
+      {\r
+        Return(0x000B)  // Enabled, don't Display.\r
+      }\r
+    }\r
+\r
+    Return(0x0000)      // Return Nothing.\r
+  }\r
+\r
+  Method(_CRS,0,Serialized)\r
+  {\r
+    CreateDWordField (BUF0, ^FIX1._BAS, MBR0)\r
+    Store(\HPTB, MBR0)\r
+    CreateDWordField (BUF0, ^FIX1._LEN, MBR1)\r
+    Store(\HPTS, MBR1)\r
+    Return(BUF0)\r
+  }\r
+}\r
+\r
+#endif\r
diff --git a/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/PCA9685.asi b/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/PCA9685.asi
new file mode 100644 (file)
index 0000000..4d3d550
--- /dev/null
@@ -0,0 +1,40 @@
+/** @file\r
+NXP PCA9685 i2c-accessible PWM/LED controller.\r
+\r
+Copyright (c) 2013-2015 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution.  The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+Device(PWM1)\r
+{\r
+    Name(_HID, "INT3492") // NXP PCA9685 i2c-accessible PWM/LED controller.\r
+    Name(_CID, "INT3492")\r
+\r
+    Name(RBUF, ResourceTemplate()\r
+    {\r
+        I2CSerialBus(0x47, ControllerInitiated, 400000, AddressingMode7Bit, "\\_SB.PCI0.GIP0.I2C_", 0, ResourceConsumer, , )\r
+    })\r
+    Method(_CRS, 0x0, NotSerialized)\r
+    {\r
+        Return(RBUF)\r
+    }\r
+    Method(_STA, 0x0, NotSerialized)\r
+    {\r
+        //\r
+        // Only Platform Type / Id 8 has this device.\r
+        //\r
+        If(LNotEqual(PTYP, 8))\r
+        {\r
+          return (0)\r
+        }\r
+        Return(0xf)\r
+    }\r
+}\r
diff --git a/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/PCAL9555A.asi b/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/PCAL9555A.asi
new file mode 100644 (file)
index 0000000..62c6718
--- /dev/null
@@ -0,0 +1,96 @@
+/** @file\r
+NXP PCAL9555A i2c-accessible I/O expander.\r
+\r
+Copyright (c) 2013-2015 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution.  The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+Device(NIO1)\r
+{\r
+    Name(_HID, "INT3491") // NXP PCAL9555A i2c-accessible I/O expander.\r
+    Name(_CID, "INT3491")\r
+    Name(_UID, 1)\r
+\r
+    Name(RBUF, ResourceTemplate()\r
+    {\r
+        I2CSerialBus(0x25, ControllerInitiated, 400000, AddressingMode7Bit, "\\_SB.PCI0.GIP0.I2C_", 0, ResourceConsumer, , )\r
+    })\r
+    Method(_CRS, 0x0, NotSerialized)\r
+    {\r
+        Return(RBUF)\r
+    }\r
+    Method(_STA, 0x0, NotSerialized)\r
+    {\r
+        //\r
+        // Only Platform Type / Id 8 has this device.\r
+        //\r
+        If(LNotEqual(PTYP, 8))\r
+        {\r
+          return (0)\r
+        }\r
+        Return(0xf)\r
+    }\r
+}\r
+\r
+Device(NIO2)\r
+{\r
+    Name(_HID, "INT3491") // NXP PCAL9555A i2c-accessible I/O expander.\r
+    Name(_CID, "INT3491")\r
+    Name(_UID, 2)\r
+\r
+    Name(RBUF, ResourceTemplate()\r
+    {\r
+        I2CSerialBus(0x26, ControllerInitiated, 400000, AddressingMode7Bit, "\\_SB.PCI0.GIP0.I2C_", 0, ResourceConsumer, , )\r
+    })\r
+    Method(_CRS, 0x0, NotSerialized)\r
+    {\r
+        Return(RBUF)\r
+    }\r
+    Method(_STA, 0x0, NotSerialized)\r
+    {\r
+        //\r
+        // Only Platform Type / Id 8 has this device.\r
+        //\r
+        If(LNotEqual(PTYP, 8))\r
+        {\r
+          return (0)\r
+        }\r
+        Return(0xf)\r
+    }\r
+}\r
+\r
+Device(NIO3)\r
+{\r
+    Name(_HID, "INT3491") // NXP PCAL9555A i2c-accessible I/O expander.\r
+    Name(_CID, "INT3491")\r
+    Name(_UID, 3)\r
+\r
+    Name(RBUF, ResourceTemplate()\r
+    {\r
+        I2CSerialBus(0x27, ControllerInitiated, 400000, AddressingMode7Bit, "\\_SB.PCI0.GIP0.I2C_", 0, ResourceConsumer, , )\r
+        GpioInt (Level, ActiveLow, Exclusive, PullDefault, , "\\_SB.PCI0.GIP0.GPO", 0, ResourceConsumer, , ) {QUARK_GPIO1_MAPPING} /* GPIO<1> is EXP2_INT */\r
+    })\r
+    Method(_CRS, 0x0, NotSerialized)\r
+    {\r
+        Return(RBUF)\r
+    }\r
+    Method(_STA, 0x0, NotSerialized)\r
+    {\r
+        //\r
+        // Only Platform Type / Id 8 has this device.\r
+        //\r
+        If(LNotEqual(PTYP, 8))\r
+        {\r
+          return (0)\r
+        }\r
+        Return(0xf)\r
+    }\r
+}\r
diff --git a/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/PciHostBridge.asi b/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/PciHostBridge.asi
new file mode 100644 (file)
index 0000000..2ed4776
--- /dev/null
@@ -0,0 +1,201 @@
+/** @file\r
+PCI Host Bridge Definitions\r
+\r
+Copyright (c) 2013-2015 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution.  The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+\r
+Name(PBRS, ResourceTemplate() {\r
+   WORDBusNumber(            //Bus number resource (0); the bridge produces bus numbers for its subsequent buses\r
+      ResourceProducer,      // bit 0 of general flags is 1\r
+      MinFixed,              // Range is fixed\r
+      MaxFixed,              // Range is fixed\r
+      PosDecode,             // PosDecode\r
+      0x0000,                // Granularity\r
+      0x0000,                // Min\r
+      0x001f,                // Max\r
+      0x0000,                // Translation\r
+      0x0020                 // Range Length = Max-Min+1\r
+   )\r
+\r
+   WORDIO(                   //Consumed-and-produced resource (all I/O below CF8)\r
+      ResourceProducer,      // bit 0 of general flags is 0\r
+      MinFixed,              // Range is fixed\r
+      MaxFixed,              // Range is fixed\r
+      PosDecode,\r
+      EntireRange,\r
+      0x0000,                // Granularity\r
+      0x0000,                // Min\r
+      0x0cf7,                // Max\r
+      0x0000,                // Translation\r
+      0x0cf8                 // Range Length\r
+   )\r
+\r
+   IO(                       //Consumed resource (CF8-CFF)\r
+      Decode16,\r
+      0x0cf8,\r
+      0xcf8,\r
+      1,\r
+      8\r
+   )\r
+\r
+   WORDIO(                   //Consumed-and-produced resource (all I/O above CFF)\r
+      ResourceProducer,      // bit 0 of general flags is 0\r
+      MinFixed,              // Range is fixed\r
+      MaxFixed,              // Range is fixed\r
+      PosDecode,\r
+      EntireRange,\r
+      0x0000,                // Granularity\r
+      0x0d00,                // Min\r
+      0xffff,                // Max\r
+      0x0000,                // Translation\r
+      0xf300                 // Range Length\r
+   )\r
+\r
+   DWORDMEMORY(              // descriptor for dos area(0->0xa0000)\r
+      ResourceProducer,      // bit 0 of general flags is 0\r
+      PosDecode,\r
+      MinFixed,              // Range is fixed\r
+      MaxFixed,              // Range is Fixed\r
+      Cacheable,\r
+      ReadWrite,\r
+      0x00000000,            // Granularity\r
+      0x000a0000,            // Min\r
+      0x000bffff,            // Max\r
+      0x00000000,            // Translation\r
+      0x00020000             // Range Length\r
+   )\r
+\r
+   DWORDMemory(              // Consumed-and-produced resource for pci memory mapped memory\r
+      ResourceProducer,      // bit 0 of general flags is 0\r
+      PosDecode,             // positive Decode\r
+      MinFixed,              // Range is fixed\r
+      MaxFixed,              // Range is fixed\r
+      Cacheable,\r
+      ReadWrite,\r
+      0x00000000,            // Granularity\r
+      0x00000000,            // Min (calculated dynamically)\r
+\r
+      0xfebfffff,            // Max = IO Apic base address - 1\r
+      0x00000000,            // Translation\r
+      0xfec00000,            // Range Length (calculated dynamically)\r
+      ,                      // Optional field left blank\r
+      ,                      // Optional field left blank\r
+      MEM1                   // Name declaration for this descriptor\r
+   )\r
+\r
+})          // end of CRES Buffer\r
+\r
+\r
+Method(_CRS, 0x0, NotSerialized)\r
+{\r
+    CreateDWordField(PBRS, \_SB.PCI0.MEM1._MIN, MMIN)\r
+    CreateDWordField(PBRS, \_SB.PCI0.MEM1._MAX, MMAX)\r
+    CreateDWordField(PBRS, \_SB.PCI0.MEM1._LEN, MLEN)\r
+\r
+    // HMBOUND is PCI memory base\r
+    And(MNRD(0x03, 0x08), 0xFFFFF000, MMIN)\r
+    Add(Subtract(MMAX, MMIN), 1, MLEN)\r
+\r
+    Return(PBRS)\r
+}\r
+\r
+// Message Nework Registers\r
+OperationRegion(MNR, PCI_Config, 0xD0, 0x10)\r
+Field(MNR, DWordAcc, NoLock, Preserve)\r
+{\r
+    MCR, 32,           // Message Control Register\r
+    MDR, 32            // Message Data Register\r
+}\r
+\r
+// Message Nework Read Method\r
+// Arg0 = Port\r
+// Arg1 = RegAddress\r
+// return 32 bit register value\r
+Method(MNRD, 2, Serialized)\r
+{\r
+    Or(ShiftLeft(Arg0, 16), ShiftLeft(Arg1, 8), Local0)\r
+    Or(Local0, 0x100000F0, Local0)\r
+    Store(Local0, MCR)\r
+    Return(MDR)\r
+}\r
+\r
+// Message Nework Write Method\r
+// Arg0 = Port\r
+// Arg1 = RegAddress\r
+// Arg2 = 32 bit write value\r
+Method(MNWR, 3, Serialized)\r
+{\r
+    Store(Arg2, MDR)\r
+    Or(ShiftLeft(Arg0, 16), ShiftLeft(Arg1, 8), Local0)\r
+    Or(Local0, 0x110000F0, Local0)\r
+    Store(Local0, MCR)\r
+}\r
+\r
+Method(_PRT, 0, NotSerialized)\r
+{\r
+  If (LEqual(\GPIC, Zero)) // 8259 Interrupt Routing\r
+  {\r
+    Return (\r
+      Package()\r
+      {\r
+        // Bus 0, Device 20 - IOSFAHB Bridge\r
+        Package() {0x0014ffff, 0, \_SB.PCI0.LPC.LNKA, 0}, // INTA\r
+        Package() {0x0014ffff, 1, \_SB.PCI0.LPC.LNKB, 0}, // INTB\r
+        Package() {0x0014ffff, 2, \_SB.PCI0.LPC.LNKC, 0}, // INTC\r
+        Package() {0x0014ffff, 3, \_SB.PCI0.LPC.LNKD, 0}, // INTD\r
+\r
+        // Bus 0, Device 21 - IOSFAHB Bridge\r
+        Package() {0x0015ffff, 0, \_SB.PCI0.LPC.LNKA, 0}, // INTA\r
+        Package() {0x0015ffff, 1, \_SB.PCI0.LPC.LNKB, 0}, // INTB\r
+        Package() {0x0015ffff, 2, \_SB.PCI0.LPC.LNKC, 0}, // INTC\r
+        Package() {0x0015ffff, 3, \_SB.PCI0.LPC.LNKD, 0}, // INTD\r
+\r
+        // Bus 0, Device 23 - PCIe port 0\r
+        Package() {0x0017ffff, 0, \_SB.PCI0.LPC.LNKE, 0}, // INTA\r
+        Package() {0x0017ffff, 1, \_SB.PCI0.LPC.LNKF, 0}, // INTB\r
+        Package() {0x0017ffff, 2, \_SB.PCI0.LPC.LNKG, 0}, // INTC\r
+        Package() {0x0017ffff, 3, \_SB.PCI0.LPC.LNKH, 0}, // INTD\r
+\r
+        // Bus 0, Device 31\r
+        Package() {0x001fffff, 0, \_SB.PCI0.LPC.LNKA, 0}, // LPC Bridge\r
+      }\r
+    )\r
+  }\r
+  else {\r
+    Return (\r
+      Package()\r
+      {\r
+        // Bus 0, Device 20 - IOSFAHB Bridge\r
+        Package() {0x0014ffff, 0, 0, 16}, // INTA\r
+        Package() {0x0014ffff, 1, 0, 17}, // INTB\r
+        Package() {0x0014ffff, 2, 0, 18}, // INTC\r
+        Package() {0x0014ffff, 3, 0, 19}, // INTD\r
+\r
+        // Bus 0, Device 21 - IOSFAHB Bridge\r
+        Package() {0x0015ffff, 0, 0, 16}, // INTA\r
+        Package() {0x0015ffff, 1, 0, 17}, // INTB\r
+        Package() {0x0015ffff, 2, 0, 18}, // INTC\r
+        Package() {0x0015ffff, 3, 0, 19}, // INTD\r
+\r
+        // Bus 0, Device 23 - PCIe port 0\r
+        Package() {0x0017ffff, 0, 0, 20}, // INTA\r
+        Package() {0x0017ffff, 1, 0, 21}, // INTB\r
+        Package() {0x0017ffff, 2, 0, 22}, // INTC\r
+        Package() {0x0017ffff, 3, 0, 23}, // INTD\r
+\r
+        // Bus 0, Device 31\r
+        Package() {0x001fffff, 0, 0, 16}, // LPC Bridge\r
+      }\r
+    )\r
+  }\r
+}\r
diff --git a/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/PciIrq.asi b/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/PciIrq.asi
new file mode 100644 (file)
index 0000000..cb9b4d6
--- /dev/null
@@ -0,0 +1,558 @@
+/** @file\r
+\r
+Copyright (c) 2013-2015 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution.  The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+\r
+// Interrupts can be DEB8=all except 13,8,6,2,1,0\r
+\r
+#ifndef PCIIRQ_ASI\r
+#define PCIIRQ_ASI\r
+\r
+OperationRegion(PRR0, PCI_Config, 0x60, 0x08)\r
+Field(PRR0, ANYACC, NOLOCK, PRESERVE)\r
+{\r
+    PIRA, 8,\r
+    PIRB, 8,\r
+    PIRC, 8,\r
+    PIRD, 8,\r
+    PIRE, 8,\r
+    PIRF, 8,\r
+    PIRG, 8,\r
+    PIRH, 8\r
+}\r
+\r
+Device(LNKA)            // PCI IRQ link A\r
+{\r
+    Name(_HID,EISAID("PNP0C0F"))\r
+\r
+    Name(_UID, 1)\r
+\r
+    Method(_STA,0,NotSerialized)\r
+    {\r
+        If(And(PIRA, 0x80))\r
+        {\r
+          Return(0x9)\r
+        }\r
+        Else\r
+        {\r
+          Return(0xB)\r
+        }    // Don't display\r
+    }\r
+\r
+    Method(_DIS,0,NotSerialized)\r
+    {\r
+        Or(PIRA, 0x80, PIRA)\r
+    }\r
+\r
+    Method(_CRS,0,Serialized)\r
+    {\r
+        Name(BUF0,\r
+            ResourceTemplate()\r
+            {IRQ(Level,ActiveLow,Shared){0}})\r
+\r
+                                // Define references to buffer elements\r
+        CreateWordField (BUF0, 0x01, IRQW)  // IRQ low\r
+                                // Write current settings into IRQ descriptor\r
+        If (And(PIRA, 0x80))\r
+        {\r
+            Store(Zero, Local0)\r
+        }\r
+        Else\r
+        {\r
+            Store(One,Local0)\r
+        }\r
+                                                    // Shift 1 by value in register 70\r
+        ShiftLeft(Local0,And(PIRA,0x0F),IRQW)       // Save in buffer\r
+        Return(BUF0)                                // Return Buf0\r
+    }                                               // End of _CRS method\r
+\r
+    Name(_PRS,\r
+        ResourceTemplate()\r
+        {IRQ(Level,ActiveLow,Shared){12,11,10,9,7,5,4,3}})\r
+\r
+    Method(_SRS,1,NotSerialized)\r
+    {\r
+        CreateWordField (ARG0, 0x01, IRQW)  // IRQ low\r
+\r
+        FindSetRightBit(IRQW,Local0)          // Set IRQ\r
+        If (LNotEqual(IRQW,Zero))\r
+        {\r
+            And(Local0, 0x7F,Local0)\r
+            Decrement(Local0)\r
+        }\r
+        Else\r
+        {\r
+            Or(Local0, 0x80,Local0)\r
+        }\r
+        store(Local0, PIRA)\r
+    }                                                  // End of _SRS Method\r
+}\r
+\r
+Device(LNKB)            // PCI IRQ link B\r
+{\r
+    Name(_HID,EISAID("PNP0C0F"))\r
+\r
+    Name(_UID, 2)\r
+\r
+    Method(_STA,0,NotSerialized)\r
+    {\r
+        If(And(PIRB, 0x80))\r
+        {\r
+          Return(0x9)\r
+        }\r
+        Else\r
+        {\r
+          Return(0xB)\r
+        }    // Don't display\r
+    }\r
+\r
+    Method(_DIS,0,NotSerialized)\r
+    {\r
+        Or(PIRB, 0x80,PIRB)\r
+    }\r
+\r
+    Method(_CRS,0,Serialized)\r
+    {\r
+        Name(BUF0,\r
+            ResourceTemplate()\r
+            {IRQ(Level,ActiveLow,Shared){0}})\r
+                                            // Define references to buffer elements\r
+        CreateWordField (BUF0, 0x01, IRQW)  // IRQ low\r
+                                            // Write current settings into IRQ descriptor\r
+        If (And(PIRB, 0x80))\r
+        {\r
+            Store(Zero, Local0)\r
+        }\r
+        Else\r
+        {\r
+                Store(One,Local0)\r
+        }\r
+                                               // Shift 1 by value in register 70\r
+        ShiftLeft(Local0,And(PIRB,0x0F),IRQW)  // Save in buffer\r
+        Return(BUF0)                           // Return Buf0\r
+    }                                          // End of _CRS method\r
+\r
+    Name(_PRS,\r
+        ResourceTemplate()\r
+        {IRQ(Level,ActiveLow,Shared){12,11,10,9,7,5,4,3}})\r
+\r
+    Method(_SRS,1,NotSerialized)\r
+    {\r
+        CreateWordField (ARG0, 0x01, IRQW)      // IRQ low\r
+\r
+        FindSetRightBit(IRQW,Local0)            // Set IRQ\r
+        If (LNotEqual(IRQW,Zero))\r
+        {\r
+            And(Local0, 0x7F,Local0)\r
+            Decrement(Local0)\r
+        }\r
+        Else\r
+        {\r
+            Or(Local0, 0x80,Local0)\r
+        }\r
+        Store(Local0, PIRB)\r
+    }                                           // End of _SRS Method\r
+}\r
+\r
+Device(LNKC)                                    // PCI IRQ link C\r
+{\r
+    Name(_HID,EISAID("PNP0C0F"))\r
+\r
+    Name(_UID, 3)\r
+\r
+    Method(_STA,0,NotSerialized)\r
+    {\r
+        If(And(PIRC, 0x80))\r
+        {\r
+          Return(0x9)\r
+        }\r
+        Else\r
+        {\r
+          Return(0xB)\r
+        }    // Don't display\r
+    }\r
+\r
+    Method(_DIS,0,NotSerialized)\r
+    {\r
+        Or(PIRC, 0x80,PIRC)\r
+    }\r
+\r
+    Method(_CRS,0,Serialized)\r
+    {\r
+        Name(BUF0,\r
+            ResourceTemplate()\r
+            {IRQ(Level,ActiveLow,Shared){0}})\r
+                                            // Define references to buffer elements\r
+        CreateWordField (BUF0, 0x01, IRQW)  // IRQ low\r
+                                            // Write current settings into IRQ descriptor\r
+        If (And(PIRC, 0x80))\r
+        {\r
+            Store(Zero, Local0)\r
+        }\r
+        Else\r
+        {\r
+            Store(One,Local0)\r
+        }                                      // Shift 1 by value in register 70\r
+        ShiftLeft(Local0,And(PIRC,0x0F),IRQW)  // Save in buffer\r
+        Return(BUF0)                           // Return Buf0\r
+    }                                          // End of _CRS method\r
+\r
+    Name(_PRS,\r
+        ResourceTemplate()\r
+        {IRQ(Level,ActiveLow,Shared){12,11,10,9,7,5,4,3}})\r
+\r
+    Method(_SRS,1,NotSerialized)\r
+    {\r
+        CreateWordField (ARG0, 0x01, IRQW)  // IRQ low\r
+\r
+        FindSetRightBit(IRQW,Local0)        // Set IRQ\r
+        If (LNotEqual(IRQW,Zero))\r
+        {\r
+            And(Local0, 0x7F,Local0)\r
+            Decrement(Local0)\r
+        }\r
+        Else {\r
+            Or(Local0, 0x80,Local0)\r
+        }\r
+        Store(Local0, PIRC)\r
+    }                                               // End of _SRS Method\r
+}\r
+\r
+Device(LNKD)                                        // PCI IRQ link D\r
+{\r
+    Name(_HID,EISAID("PNP0C0F"))\r
+\r
+    Name(_UID, 4)\r
+\r
+    Method(_STA,0,NotSerialized)\r
+    {\r
+        If(And(PIRD, 0x80))\r
+        {\r
+          Return(0x9)\r
+        }\r
+        Else\r
+        {\r
+          Return(0xB)\r
+        }    // Don't display\r
+    }\r
+\r
+    Method(_DIS,0,NotSerialized)\r
+    {\r
+        Or(PIRD, 0x80,PIRD)\r
+    }\r
+\r
+    Method(_CRS,0,Serialized)\r
+    {\r
+        Name(BUF0,\r
+            ResourceTemplate()\r
+            {IRQ(Level,ActiveLow,Shared){0}})\r
+        // Define references to buffer elements\r
+        CreateWordField (BUF0, 0x01, IRQW)  // IRQ low\r
+        // Write current settings into IRQ descriptor\r
+        If (And(PIRD, 0x80))\r
+        {\r
+            Store(Zero, Local0)\r
+        }\r
+        Else\r
+        {\r
+            Store(One,Local0)\r
+        }  // Shift 1 by value in register 70\r
+        ShiftLeft(Local0,And(PIRD,0x0F),IRQW)  // Save in buffer\r
+        Return(BUF0)        // Return Buf0\r
+    }                  // End of _CRS method\r
+\r
+    Name(_PRS,\r
+        ResourceTemplate()\r
+        {IRQ(Level,ActiveLow,Shared){12,11,10,9,7,5,4,3}})\r
+\r
+    Method(_SRS,1,NotSerialized)\r
+    {\r
+        CreateWordField (ARG0, 0x01, IRQW)  // IRQ low\r
+\r
+        FindSetRightBit(IRQW,Local0)// Set IRQ\r
+        If (LNotEqual(IRQW,Zero))\r
+        {\r
+            And(Local0, 0x7F,Local0)\r
+            Decrement(Local0)\r
+        }\r
+        Else\r
+        {\r
+            Or(Local0, 0x80,Local0)\r
+        }\r
+        Store(Local0, PIRD)\r
+    }                  // End of _SRS Method\r
+}\r
+\r
+Device(LNKE)           // PCI IRQ link E\r
+{\r
+    Name(_HID,EISAID("PNP0C0F"))\r
+\r
+    Name(_UID, 5)\r
+\r
+    Method(_STA,0,NotSerialized)\r
+    {\r
+        If(And(PIRE, 0x80))\r
+        {\r
+          Return(0x9)\r
+        }\r
+        Else\r
+        {\r
+          Return(0xB)\r
+        }    // Don't display\r
+    }\r
+\r
+    Method(_DIS,0,NotSerialized)\r
+    {\r
+        Or(PIRE, 0x80, PIRE)\r
+    }\r
+\r
+    Method(_CRS,0,Serialized)\r
+    {\r
+        Name(BUF0,\r
+            ResourceTemplate()\r
+            {IRQ(Level,ActiveLow,Shared){0}})\r
+\r
+                                // Define references to buffer elements\r
+        CreateWordField (BUF0, 0x01, IRQW)  // IRQ low\r
+                                // Write current settings into IRQ descriptor\r
+        If (And(PIRE, 0x80))\r
+        {\r
+            Store(Zero, Local0)\r
+        }\r
+        Else\r
+        {\r
+            Store(One,Local0)\r
+        }\r
+                                                    // Shift 1 by value in register 70\r
+        ShiftLeft(Local0,And(PIRE,0x0F),IRQW)       // Save in buffer\r
+        Return(BUF0)                                // Return Buf0\r
+    }                                               // End of _CRS method\r
+\r
+    Name(_PRS,\r
+        ResourceTemplate()\r
+        {IRQ(Level,ActiveLow,Shared){12,11,10,9,7,5,4,3}})\r
+\r
+    Method(_SRS,1,NotSerialized)\r
+    {\r
+        CreateWordField (ARG0, 0x01, IRQW)  // IRQ low\r
+\r
+        FindSetRightBit(IRQW,Local0)          // Set IRQ\r
+        If (LNotEqual(IRQW,Zero))\r
+        {\r
+            And(Local0, 0x7F,Local0)\r
+            Decrement(Local0)\r
+        }\r
+        Else\r
+        {\r
+            Or(Local0, 0x80,Local0)\r
+        }\r
+        store(Local0, PIRE)\r
+    }                                                  // End of _SRS Method\r
+}\r
+\r
+Device(LNKF)            // PCI IRQ link F\r
+{\r
+    Name(_HID,EISAID("PNP0C0F"))\r
+\r
+    Name(_UID, 6)\r
+\r
+    Method(_STA,0,NotSerialized)\r
+    {\r
+        If(And(PIRF, 0x80))\r
+        {\r
+          Return(0x9)\r
+        }\r
+        Else\r
+        {\r
+          Return(0xB)\r
+        }    // Don't display\r
+    }\r
+\r
+    Method(_DIS,0,NotSerialized)\r
+    {\r
+        Or(PIRB, 0x80,PIRF)\r
+    }\r
+\r
+    Method(_CRS,0,Serialized)\r
+    {\r
+        Name(BUF0,\r
+            ResourceTemplate()\r
+            {IRQ(Level,ActiveLow,Shared){0}})\r
+                                            // Define references to buffer elements\r
+        CreateWordField (BUF0, 0x01, IRQW)  // IRQ low\r
+                                            // Write current settings into IRQ descriptor\r
+        If (And(PIRF, 0x80))\r
+        {\r
+            Store(Zero, Local0)\r
+        }\r
+        Else\r
+        {\r
+                Store(One,Local0)\r
+        }\r
+                                               // Shift 1 by value in register 70\r
+        ShiftLeft(Local0,And(PIRF,0x0F),IRQW)  // Save in buffer\r
+        Return(BUF0)                           // Return Buf0\r
+    }                                          // End of _CRS method\r
+\r
+    Name(_PRS,\r
+        ResourceTemplate()\r
+        {IRQ(Level,ActiveLow,Shared){12,11,10,9,7,5,4,3}})\r
+\r
+    Method(_SRS,1,NotSerialized)\r
+    {\r
+        CreateWordField (ARG0, 0x01, IRQW)      // IRQ low\r
+\r
+        FindSetRightBit(IRQW,Local0)            // Set IRQ\r
+        If (LNotEqual(IRQW,Zero))\r
+        {\r
+            And(Local0, 0x7F,Local0)\r
+            Decrement(Local0)\r
+        }\r
+        Else\r
+        {\r
+            Or(Local0, 0x80,Local0)\r
+        }\r
+        Store(Local0, PIRF)\r
+    }                                                   // End of _SRS Method\r
+}\r
+\r
+Device(LNKG)                                            // PCI IRQ link G\r
+{\r
+    Name(_HID,EISAID("PNP0C0F"))\r
+\r
+    Name(_UID, 7)\r
+\r
+    Method(_STA,0,NotSerialized)\r
+    {\r
+        If(And(PIRG, 0x80))\r
+        {\r
+          Return(0x9)\r
+        }\r
+        Else\r
+        {\r
+          Return(0xB)\r
+        }    // Don't display\r
+    }\r
+\r
+    Method(_DIS,0,NotSerialized)\r
+    {\r
+        Or(PIRG, 0x80,PIRG)\r
+    }\r
+\r
+    Method(_CRS,0,Serialized)\r
+    {\r
+        Name(BUF0,\r
+            ResourceTemplate()\r
+            {IRQ(Level,ActiveLow,Shared){0}})\r
+                                            // Define references to buffer elements\r
+        CreateWordField (BUF0, 0x01, IRQW)  // IRQ low\r
+                                            // Write current settings into IRQ descriptor\r
+        If (And(PIRG, 0x80))\r
+        {\r
+            Store(Zero, Local0)\r
+        }\r
+        Else\r
+        {\r
+            Store(One,Local0)\r
+        }                                      // Shift 1 by value in register 70\r
+        ShiftLeft(Local0,And(PIRG,0x0F),IRQW)  // Save in buffer\r
+        Return(BUF0)                           // Return Buf0\r
+    }                                          // End of _CRS method\r
+\r
+    Name(_PRS,\r
+        ResourceTemplate()\r
+        {IRQ(Level,ActiveLow,Shared){12,11,10,9,7,5,4,3}})\r
+\r
+    Method(_SRS,1,NotSerialized)\r
+    {\r
+        CreateWordField (ARG0, 0x01, IRQW)  // IRQ low\r
+\r
+        FindSetRightBit(IRQW,Local0)          // Set IRQ\r
+        If (LNotEqual(IRQW,Zero))\r
+        {\r
+            And(Local0, 0x7F,Local0)\r
+            Decrement(Local0)\r
+        }\r
+        Else {\r
+            Or(Local0, 0x80,Local0)\r
+        }\r
+        Store(Local0, PIRG)\r
+    }                                               // End of _SRS Method\r
+}\r
+\r
+Device(LNKH)                                        // PCI IRQ link H\r
+{\r
+    Name(_HID,EISAID("PNP0C0F"))\r
+\r
+    Name(_UID, 8)\r
+\r
+    Method(_STA,0,NotSerialized)\r
+    {\r
+        If(And(PIRH, 0x80))\r
+        {\r
+          Return(0x9)\r
+        }\r
+        Else\r
+        {\r
+          Return(0xB)\r
+        }    // Don't display\r
+    }\r
+\r
+    Method(_DIS,0,NotSerialized)\r
+    {\r
+        Or(PIRH, 0x80,PIRH)\r
+    }\r
+\r
+    Method(_CRS,0,Serialized)\r
+    {\r
+        Name(BUF0,\r
+            ResourceTemplate()\r
+            {IRQ(Level,ActiveLow,Shared){0}})\r
+        // Define references to buffer elements\r
+        CreateWordField (BUF0, 0x01, IRQW)  // IRQ low\r
+        // Write current settings into IRQ descriptor\r
+        If (And(PIRH, 0x80))\r
+        {\r
+            Store(Zero, Local0)\r
+        }\r
+        Else\r
+        {\r
+            Store(One,Local0)\r
+        }  // Shift 1 by value in register 70\r
+        ShiftLeft(Local0,And(PIRH,0x0F),IRQW)  // Save in buffer\r
+        Return(BUF0)   // Return Buf0\r
+    }                  // End of _CRS method\r
+\r
+    Name(_PRS,\r
+        ResourceTemplate()\r
+        {IRQ(Level,ActiveLow,Shared){12,11,10,9,7,5,4,3}})\r
+\r
+    Method(_SRS,1,NotSerialized)\r
+    {\r
+        CreateWordField (ARG0, 0x01, IRQW)  // IRQ low\r
+\r
+        FindSetRightBit(IRQW,Local0)// Set IRQ\r
+        If (LNotEqual(IRQW,Zero))\r
+        {\r
+            And(Local0, 0x7F,Local0)\r
+            Decrement(Local0)\r
+        }\r
+        Else\r
+        {\r
+            Or(Local0, 0x80,Local0)\r
+        }\r
+        Store(Local0, PIRH)\r
+    }                  // End of _SRS Method\r
+}\r
+\r
+#endif\r
diff --git a/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/PcieExpansionPrt.asi b/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/PcieExpansionPrt.asi
new file mode 100644 (file)
index 0000000..6ccbec2
--- /dev/null
@@ -0,0 +1,133 @@
+/** @file\r
+PCI express expansion ports\r
+\r
+Copyright (c) 2013-2015 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution.  The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#ifndef PcieExpansionPrt_asi\r
+#define PcieExpansionPrt_asi\r
+\r
+Device (PEX0)    // PCI express bus bridged from [Bus 0, Device 23, Function 0]\r
+{\r
+    Name(_ADR,0x00170000)            // Device (HI WORD)=23, Func (LO WORD)=0\r
+    Name(_PRW,Package(){0x11,0x03})  // GPE pin 0x11, Wake from S3 -- PCI PME#\r
+\r
+    OperationRegion (PES0,PCI_Config,0x40,0xA0)\r
+    Field (PES0, AnyAcc, NoLock, Preserve)\r
+    {\r
+    Offset(0x1A),              // SLSTS - Slot Status Register\r
+    ABP0,  1,                  // Bit 0, Attention Button Pressed\r
+    ,  2,\r
+    PDC0,  1,                  // Bit 3, Presence Detect Changed\r
+    ,  2,\r
+    PDS0,  1,                  // Bit 6, Presence Detect State\r
+    , 1,\r
+    LSC0,  1,                  // Bit 8, Link Active State Changed\r
+    offset (0x20),\r
+    , 16,\r
+    PMS0, 1,                   // Bit 16, PME Status\r
+    offset (0x98),\r
+    , 30,\r
+    HPE0, 1,                   // Bit 30, Hot Plug SCI Enable\r
+    PCE0, 1,                   // Bit 31, Power Management SCI Enable.\r
+    , 30,\r
+    HPS0, 1,                   // Bit 30, Hot Plug SCI Status\r
+    PCS0, 1,                   // Bit 31, Power Management SCI Status.\r
+    }\r
+\r
+    Method(_PRT,0,NotSerialized) {\r
+        If (LEqual(\GPIC, Zero)) // 8259 Interrupt Routing\r
+        {\r
+            Return (\r
+                Package()\r
+                {\r
+                    // Port 0: INTA->PIRQE,INTB->PIRQF,INTC->PIRQG,INTD->PIRQH\r
+                    Package() {0x0000ffff, 0, \_SB_.PCI0.LPC.LNKE, 0}, // PCI Slot 1\r
+                    Package() {0x0000ffff, 1, \_SB_.PCI0.LPC.LNKF, 0},\r
+                    Package() {0x0000ffff, 2, \_SB_.PCI0.LPC.LNKG, 0},\r
+                    Package() {0x0000ffff, 3, \_SB_.PCI0.LPC.LNKH, 0},\r
+                }\r
+            )\r
+        }\r
+        else    // IOAPIC Routing\r
+        {\r
+            Return (\r
+                Package()\r
+                {\r
+                    // Port 0: INTA->PIRQE,INTB->PIRQF,INTC->PIRQG,INTD->PIRQH\r
+                    Package() {0x0000ffff, 0, 0, 20}, // PCI Slot 1\r
+                    Package() {0x0000ffff, 1, 0, 21},\r
+                    Package() {0x0000ffff, 2, 0, 22},\r
+                    Package() {0x0000ffff, 3, 0, 23},\r
+                }\r
+            )\r
+        }\r
+    }\r
+}\r
+\r
+Device (PEX1)    // PCI express bus bridged from [Bus 0, Device 23, Function 1]\r
+{\r
+    Name(_ADR,0x00170001)            // Device (HI WORD)=23, Func (LO WORD)=1\r
+    Name(_PRW,Package(){0x11,0x03})  // GPE pin 0x11, Wake from S3 -- PCI PME#\r
+    OperationRegion (PES1,PCI_Config,0x40,0xA0)\r
+    Field (PES1, AnyAcc, NoLock, Preserve)\r
+    {\r
+    Offset(0x1A),              // SLSTS - Slot Status Register\r
+    ABP1,  1,                  // Bit 0, Attention Button Pressed\r
+    ,  2,\r
+    PDC1,  1,                  // Bit 3, Presence Detect Changed\r
+    ,  2,\r
+    PDS1,  1,                  // Bit 6, Presence Detect State\r
+    , 1,\r
+    LSC1,  1,                  // Bit 8, Link Active State Changed\r
+    offset (0x20),\r
+    , 16,\r
+    PMS1, 1,                   // Bit 16, PME Status\r
+    offset (0x98),\r
+    , 30,\r
+    HPE1, 1,                   // Bit 30, Hot Plug SCI Enable\r
+    PCE1, 1,                   // Bit 31, Power Management SCI Enable.\r
+    , 30,\r
+    HPS1, 1,                   // Bit 30, Hot Plug SCI Status\r
+    PCS1, 1,                   // Bit 31, Power Management SCI Status.\r
+    }\r
+    Method(_PRT,0,NotSerialized) {\r
+        If (LEqual(\GPIC, Zero)) // 8259 Interrupt Routing\r
+        {\r
+            Return (\r
+                Package()\r
+                {\r
+                    // Port 1: INTA->PIRQF,INTB->PIRQG,INTC->PIRQH,INTD->PIRQE\r
+                    Package() {0x0000ffff, 0, \_SB_.PCI0.LPC.LNKF, 0},\r
+                    Package() {0x0000ffff, 1, \_SB_.PCI0.LPC.LNKG, 0},\r
+                    Package() {0x0000ffff, 2, \_SB_.PCI0.LPC.LNKH, 0},\r
+                    Package() {0x0000ffff, 3, \_SB_.PCI0.LPC.LNKE, 0},\r
+                }\r
+            )\r
+        }\r
+        else    // IOAPIC Routing\r
+        {\r
+            Return (\r
+                Package()\r
+                {\r
+                    // Port 1: INTA->PIRQF,INTB->PIRQG,INTC->PIRQH,INTD->PIRQE\r
+                    Package() {0x0000ffff, 0, 0, 21},\r
+                    Package() {0x0000ffff, 1, 0, 22},\r
+                    Package() {0x0000ffff, 2, 0, 23},\r
+                    Package() {0x0000ffff, 3, 0, 20},\r
+                }\r
+            )\r
+        }\r
+    }\r
+}\r
+\r
+#endif\r
diff --git a/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/Platform.asl b/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/Platform.asl
new file mode 100644 (file)
index 0000000..bf0acc2
--- /dev/null
@@ -0,0 +1,353 @@
+/** @file\r
+Contains root level name space objects for the platform\r
+\r
+Copyright (c) 2013-2015 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution.  The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+//\r
+// OS TYPE DEFINITION\r
+//\r
+#define WINDOWS_XP          0x01\r
+#define WINDOWS_XP_SP1      0x02\r
+#define WINDOWS_XP_SP2      0x04\r
+#define WINDOWS_2003        0x08\r
+#define WINDOWS_Vista       0x10\r
+#define WINDOWS_WIN7        0x11\r
+#define WINDOWS_WIN8        0x12\r
+#define WINDOWS_WIN8_1      0x13\r
+#define LINUX               0xF0\r
+\r
+//\r
+// GPIO Interrupt Connection Resource Descriptor (GpioInt) usage.\r
+// GpioInt() descriptors maybe used in this file and included .asi files.\r
+//\r
+// The mapping below was provided by the first OS user that requested\r
+// GpioInt() support.\r
+// Other OS users that need GpioInt() support must use the following mapping.\r
+//\r
+#define QUARK_GPIO8_MAPPING         0x00\r
+#define QUARK_GPIO9_MAPPING         0x01\r
+#define QUARK_GPIO_SUS0_MAPPING     0x02\r
+#define QUARK_GPIO_SUS1_MAPPING     0x03\r
+#define QUARK_GPIO_SUS2_MAPPING     0x04\r
+#define QUARK_GPIO_SUS3_MAPPING     0x05\r
+#define QUARK_GPIO_SUS4_MAPPING     0x06\r
+#define QUARK_GPIO_SUS5_MAPPING     0x07\r
+#define QUARK_GPIO0_MAPPING         0x08\r
+#define QUARK_GPIO1_MAPPING         0x09\r
+#define QUARK_GPIO2_MAPPING         0x0A\r
+#define QUARK_GPIO3_MAPPING         0x0B\r
+#define QUARK_GPIO4_MAPPING         0x0C\r
+#define QUARK_GPIO5_MAPPING         0x0D\r
+#define QUARK_GPIO6_MAPPING         0x0E\r
+#define QUARK_GPIO7_MAPPING         0x0F\r
+\r
+DefinitionBlock (\r
+  "Platform.aml",\r
+  "DSDT",\r
+  1,\r
+  "INTEL ",\r
+  "QuarkNcSocId",\r
+  3)\r
+{\r
+    //\r
+    // Global Variables\r
+    //\r
+    Name(\GPIC, 0x0)\r
+\r
+    //\r
+    // Port 80\r
+    //\r
+    OperationRegion (DBG0, SystemIO, 0x80, 1)\r
+    Field (DBG0, ByteAcc, NoLock, Preserve)\r
+    { IO80,8 }\r
+\r
+    //\r
+    // Access CMOS range\r
+    //\r
+    OperationRegion (ACMS, SystemIO, 0x72, 2)\r
+    Field (ACMS, ByteAcc, NoLock, Preserve)\r
+    { INDX, 8, DATA, 8 }\r
+\r
+    //\r
+    // Global NVS Memory Block\r
+    //\r
+    OperationRegion (MNVS, SystemMemory, 0xFFFF0000, 512)\r
+    Field (MNVS, ByteAcc, NoLock, Preserve)\r
+    {\r
+      OSTP, 32,\r
+      CFGD, 32,\r
+      HPEA, 32,  // HPET Enabled ?\r
+\r
+      P1BB, 32,  // Pm1blkIoBaseAddress;\r
+      PBAB, 32,  // PmbaIoBaseAddress;\r
+      GP0B, 32,  // Gpe0blkIoBaseAddress;\r
+      GPAB, 32,  // GbaIoBaseAddress;\r
+\r
+      SMBB, 32,  // SmbaIoBaseAddress;\r
+      NRV1, 32,  // GNVS reserved field 1.\r
+      WDTB, 32,  // WdtbaIoBaseAddress;\r
+\r
+      HPTB, 32,  // HpetBaseAddress;\r
+      HPTS, 32,  // HpetSize;\r
+      PEXB, 32,  // PciExpressBaseAddress;\r
+      PEXS, 32,  // PciExpressSize;\r
+\r
+      RCBB, 32,  // RcbaMmioBaseAddress;\r
+      RCBS, 32,  // RcbaMmioSize;\r
+      APCB, 32,  // IoApicBaseAddress;\r
+      APCS, 32,  // IoApicSize;\r
+\r
+      TPMP, 32,  // TpmPresent ?\r
+      DBGP, 32,  // DBG2 Present?\r
+      PTYP, 32,  // Set to one of EFI_PLATFORM_TYPE enums.\r
+      ALTS, 32,  // Use alternate I2c SLA addresses.\r
+    }\r
+\r
+    OperationRegion (GPEB, SystemIO, 0x1100, 0x40)  //GPE Block\r
+    Field (GPEB, AnyAcc, NoLock, Preserve)\r
+    {\r
+      Offset(0x10),\r
+      SMIE, 32,                 // SMI Enable\r
+      SMIS, 32,                 // SMI Status\r
+    }\r
+\r
+    //\r
+    //  Processor Objects\r
+    //\r
+    Scope(\_PR) {\r
+        //\r
+        // IO base will be updated at runtime with search key "PRIO"\r
+        //\r
+        Processor (CPU0, 0x01, 0x4F495250, 0x06) {}\r
+    }\r
+\r
+    //\r
+    // System Sleep States\r
+    //\r
+    Name (\_S0,Package (){0,0,0,0})\r
+    Name (\_S3,Package (){5,0,0,0})\r
+    Name (\_S4,Package (){6,0,0,0})\r
+    Name (\_S5,Package (){7,0,0,0})\r
+\r
+    //\r
+    //  General Purpose Event\r
+    //\r
+    Scope(\_GPE)\r
+    {\r
+        //\r
+        // EGPE generated GPE\r
+        //\r
+        Method(_L0D, 0x0, NotSerialized)\r
+        {\r
+            //\r
+            // Check EGPE for this wake event\r
+            //\r
+            Notify (\_SB.SLPB, 0x02)\r
+\r
+        }\r
+\r
+        //\r
+        // GPIO generated GPE\r
+        //\r
+        Method(_L0E, 0x0, NotSerialized)\r
+        {\r
+            //\r
+            // Check GPIO for this wake event\r
+            //\r
+            Notify (\_SB.PWRB, 0x02)\r
+\r
+        }\r
+\r
+        //\r
+        // SCLT generated GPE\r
+        //\r
+        Method(_L0F, 0x0, NotSerialized)\r
+        {\r
+            //\r
+            // Check SCLT for this wake event\r
+            //\r
+            Notify (\_SB.PCI0.SDIO, 0x02)\r
+            Notify (\_SB.PCI0.URT0, 0x02)\r
+            Notify (\_SB.PCI0.USBD, 0x02)\r
+            Notify (\_SB.PCI0.EHCI, 0x02)\r
+            Notify (\_SB.PCI0.OHCI, 0x02)\r
+            Notify (\_SB.PCI0.URT1, 0x02)\r
+            Notify (\_SB.PCI0.ENT0, 0x02)\r
+            Notify (\_SB.PCI0.ENT1, 0x02)\r
+            Notify (\_SB.PCI0.SPI0, 0x02)\r
+            Notify (\_SB.PCI0.SPI1, 0x02)\r
+            Notify (\_SB.PCI0.GIP0, 0x02)\r
+\r
+        }\r
+\r
+        //\r
+        // Remote Management Unit generated GPE\r
+        //\r
+        Method(_L10, 0x0, NotSerialized)\r
+        {\r
+            //\r
+            // Check Remote Management Unit for this wake event.\r
+            //\r
+        }\r
+\r
+        //\r
+        // PCIE generated GPE\r
+        //\r
+        Method(_L11, 0x0, NotSerialized)\r
+        {\r
+            //\r
+            // Check PCIE for this wake event\r
+            //\r
+            Notify (\_SB.PCI0.PEX0, 0x02)\r
+            Notify (\_SB.PCI0.PEX1, 0x02)\r
+        }\r
+    }\r
+\r
+    //\r
+    // define Sleeping button as mentioned in ACPI spec 2.0\r
+    //\r
+    Device (\_SB.SLPB)\r
+    {\r
+        Name (_HID, EISAID ("PNP0C0E"))\r
+        Method (_PRW, 0, NotSerialized)\r
+        {\r
+            Return (Package (0x02) {0x0D,0x04})\r
+        }\r
+    }\r
+\r
+    //\r
+    // define Power Button\r
+    //\r
+     Device (\_SB.PWRB)\r
+    {\r
+        Name (_HID, EISAID ("PNP0C0C"))\r
+        Method (_PRW, 0, NotSerialized)\r
+        {\r
+            Return (Package (0x02) {0x0E,0x04})\r
+        }\r
+    }\r
+    //\r
+    // System Wake up\r
+    //\r
+    Method(_WAK, 1, Serialized)\r
+    {\r
+       // Do nothing here\r
+       Return (0)\r
+    }\r
+\r
+    //\r
+    // System sleep down\r
+    //\r
+    Method (_PTS, 1, NotSerialized)\r
+    {\r
+        // Get ready for S3 sleep\r
+        if (Lequal(Arg0,3))\r
+        {\r
+                Store(0xffffffff,SMIS)     // clear SMI status\r
+                Store(SMIE, Local0)        // SMI Enable\r
+                Or(Local0,0x4,SMIE)        // Generate SMI on sleep\r
+        }\r
+    }\r
+\r
+    //\r
+    // Determing PIC mode\r
+    //\r
+    Method(\_PIC, 1, NotSerialized)\r
+    {\r
+        Store(Arg0,\GPIC)\r
+    }\r
+\r
+    //\r
+    //  System Bus\r
+    //\r
+    Scope(\_SB)\r
+    {\r
+        Device(PCI0)\r
+        {\r
+            Name(_HID,EISAID ("PNP0A08"))          // PCI Express Root Bridge\r
+            Name(_CID,EISAID ("PNP0A03"))          // Compatible PCI Root Bridge\r
+\r
+            Name(_ADR,0x00000000)                  // Device (HI WORD)=0, Func (LO WORD)=0\r
+            Method (_INI)\r
+            {\r
+                Store(LINUX, OSTP)                 // Set the default os is Linux\r
+                If (CondRefOf (_OSI, local0))\r
+                {\r
+                    //\r
+                    //_OSI is supported, so it is WinXp or Win2003Server\r
+                    //\r
+                    If (\_OSI("Windows 2001"))\r
+                    {\r
+                        Store (WINDOWS_XP, OSTP)\r
+                    }\r
+                    If (\_OSI("Windows 2001 SP1"))\r
+                    {\r
+                        Store (WINDOWS_XP_SP1, OSTP)\r
+                    }\r
+                    If (\_OSI("Windows 2001 SP2"))\r
+                    {\r
+                        Store (WINDOWS_XP_SP2, OSTP)\r
+                    }\r
+                    If (\_OSI("Windows 2001.1"))\r
+                    {\r
+                        Store (WINDOWS_2003, OSTP)\r
+                    }\r
+                    If (\_OSI("Windows 2006"))\r
+                    {\r
+                        Store (WINDOWS_Vista, OSTP)\r
+                    }\r
+                    If (\_OSI("Windows 2009"))\r
+                    {\r
+                        Store (WINDOWS_WIN7, OSTP)\r
+                    }\r
+                    If (\_OSI("Windows 2012"))\r
+                    {\r
+                        Store (WINDOWS_WIN8, OSTP)\r
+                    }\r
+                    If (\_OSI("Windows 2013"))\r
+                    {\r
+                        Store (WINDOWS_WIN8_1, OSTP)\r
+                    }\r
+                    If (\_OSI("Linux"))\r
+                    {\r
+                      Store (LINUX, OSTP)\r
+                    }\r
+                }\r
+            }\r
+\r
+            Include ("PciHostBridge.asi")     // PCI0 Host bridge\r
+            Include ("QNC.asi")               // QNC miscellaneous\r
+            Include ("PcieExpansionPrt.asi")  // PCIe expansion bridges/devices\r
+            Include ("QuarkSouthCluster.asi") // Quark South Cluster devices\r
+            Include ("QNCLpc.asi")            // LPC bridge device\r
+            Include ("QNCApic.asi")           // QNC I/O Apic device\r
+\r
+        }\r
+\r
+        //\r
+        // Include asi files for I2C and SPI onboard devices.\r
+        // Devices placed here instead of below relevant controllers.\r
+        // Hardware topology information is maintained by the\r
+        // ResourceSource arg to the I2CSerialBus/SPISerialBus macros\r
+        // within the device asi files.\r
+        //\r
+        Include ("Tpm.asi")          // TPM device.\r
+        Include ("CY8C9540A.asi")    // CY8C9540A 40Bit I/O Expander & EEPROM\r
+        Include ("PCAL9555A.asi")    // NXP PCAL9555A I/O expander.\r
+        Include ("PCA9685.asi")      // NXP PCA9685 PWM/LED controller.\r
+        Include ("CAT24C08.asi")     // ONSEMI CAT24C08 I2C 8KB EEPROM.\r
+        Include ("AD7298.asi")       // Analog devices AD7298 ADC.\r
+        Include ("ADC108S102.asi")   // TI ADC108S102 ADC.\r
+        Include ("GpioClient.asi")   // Software device to expose GPIO\r
+    }\r
+}\r
diff --git a/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/QNC.asi b/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/QNC.asi
new file mode 100644 (file)
index 0000000..5de9ea3
--- /dev/null
@@ -0,0 +1,55 @@
+/** @file\r
+QNC devices\r
+\r
+Copyright (c) 2013-2015 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution.  The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#ifndef QNC_ASI\r
+#define QNC_ASI\r
+\r
+Device(IOCM) // I/O controller miscellaneous\r
+{\r
+    Name(_HID,EISAID("PNP0C02"))   // System board resources device node ID\r
+\r
+    Name(CRS, ResourceTemplate()\r
+        {\r
+\r
+            // PCIEXBAR memory range\r
+            Memory32Fixed(ReadOnly, 0, 0, FIX1)\r
+\r
+            // RCRB memory range\r
+            Memory32Fixed(ReadOnly, 0, 0, FIX2)\r
+\r
+            // Option ROM shadow memory range\r
+            Memory32Fixed(ReadOnly, 0x000C0000, 0x20000)\r
+\r
+            // BIOS ROM shadow memory range\r
+            Memory32Fixed(ReadOnly, 0x000E0000, 0x20000)\r
+\r
+            // BIOS Firmware just below 4GByte of memory 8MBytes\r
+            Memory32Fixed(ReadOnly, 0xFF800000, 0x800000)\r
+        }\r
+    )\r
+\r
+    Method (_CRS, 0, NotSerialized) {\r
+        CreateDWordField (CRS, ^FIX1._BAS, MBR0)\r
+        Store(\PEXB, MBR0)\r
+        CreateDWordField (CRS, ^FIX1._LEN, MBR1)\r
+        Store(\PEXS, MBR1)\r
+        CreateDWordField (CRS, ^FIX2._BAS, MBR2)\r
+        Store(\RCBB, MBR2)\r
+        CreateDWordField (CRS, ^FIX2._LEN, MBR3)\r
+        Store(\RCBS, MBR3)\r
+        Return (CRS)\r
+    }\r
+}\r
+#endif\r
diff --git a/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/QNCApic.asi b/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/QNCApic.asi
new file mode 100644 (file)
index 0000000..cac45e6
--- /dev/null
@@ -0,0 +1,38 @@
+/** @file\r
+QNC I/O Apic devices\r
+\r
+Copyright (c) 2013-2015 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution.  The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#ifndef QNC_APIC_ASI\r
+#define QNC_APIC_ASI\r
+\r
+Device(APIC)\r
+{\r
+    Name(_HID,EISAID("PNP0003"))        // APIC resources\r
+\r
+    Name(CRS, ResourceTemplate()\r
+        {\r
+            Memory32Fixed(ReadOnly, 0, 0, FIX1) // IO APIC\r
+        }\r
+    )\r
+\r
+    Method (_CRS, 0, NotSerialized) {\r
+        CreateDWordField (CRS, ^FIX1._BAS, MBR0)\r
+        Store(\APCB, MBR0)\r
+        CreateDWordField (CRS, ^FIX1._LEN, MBR1)\r
+        Store(\APCS, MBR1)\r
+        Return (CRS)\r
+    }\r
+}\r
+\r
+#endif\r
diff --git a/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/QNCLpc.asi b/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/QNCLpc.asi
new file mode 100644 (file)
index 0000000..7a19b3c
--- /dev/null
@@ -0,0 +1,29 @@
+/** @file\r
+Lpc devices and control methods\r
+\r
+Copyright (c) 2013-2015 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution.  The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+\r
+#ifndef QNC_LPC_ASI\r
+#define QNC_LPC_ASI\r
+\r
+Device(LPC)\r
+{\r
+    Name(_ADR,0x001f0000)        // Device (HI WORD)=31, Func (LO WORD)=0\r
+\r
+    Include ("PciIrq.asi")       // PCI routing control methods\r
+    Include ("LpcDev.asi")       // Static Lpc device resource declaration\r
+}\r
+\r
+\r
+#endif\r
diff --git a/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/QuarkSouthCluster.asi b/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/QuarkSouthCluster.asi
new file mode 100644 (file)
index 0000000..2c539f7
--- /dev/null
@@ -0,0 +1,116 @@
+/** @file\r
+Quark South Cluster Devices.\r
+\r
+Copyright (c) 2013-2015 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution.  The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#ifndef QuarkSouthCluster_asi\r
+#define QuarkSouthCluster_asi\r
+\r
+Device (SDIO)    // SDIO [Bus 0, Device 20, Function 0]\r
+{\r
+    Name(_ADR,0x00140000)            // Device (HI WORD)=20, Func (LO WORD)=0\r
+    Name(_STA,0xF)                   // Enabled, do Display\r
+    Name(_PRW,Package(){0x0F,0x03})  // GPE pin 0x0F, Wake from S3 -- PCI PME#\r
+}\r
+\r
+Device (URT0)    // UART0 [Bus 0, Device 20, Function 1]\r
+{\r
+    Name(_ADR,0x00140001)            // Device (HI WORD)=20, Func (LO WORD)=1\r
+    Name(_STA,0xF)                   // Enabled, do Display\r
+    Name(_PRW,Package(){0x0F,0x03})  // GPE pin 0x0F, Wake from S3 -- PCI PME#\r
+}\r
+\r
+Device (USBD)    // USB Device [Bus 0, Device 20, Function 2]\r
+{\r
+    Name(_ADR,0x00140002)            // Device (HI WORD)=20, Func (LO WORD)=2\r
+    Name(_STA,0xF)                   // Enabled, do Display\r
+    Name(_PRW,Package(){0x0F,0x03})  // GPE pin 0x0F, Wake from S3 -- PCI PME#\r
+}\r
+\r
+Device (EHCI)    // EHCI [Bus 0, Device 20, Function 3]\r
+{\r
+    Name(_ADR,0x00140003)            // Device (HI WORD)=20, Func (LO WORD)=3\r
+    Name(_STA,0xF)                   // Enabled, do Display\r
+    Name(_PRW,Package(){0x0F,0x03})  // GPE pin 0x0F, Wake from S3 -- PCI PME#\r
+}\r
+\r
+Device (OHCI)    // OHCI [Bus 0, Device 20, Function 4]\r
+{\r
+    Name(_ADR,0x00140004)            // Device (HI WORD)=20, Func (LO WORD)=4\r
+    Name(_STA,0xF)                   // Enabled, do Display\r
+    Name(_PRW,Package(){0x0F,0x03})  // GPE pin 0x0F, Wake from S3 -- PCI PME#\r
+}\r
+\r
+Device (URT1)    // UART1 [Bus 0, Device 20, Function 5]\r
+{\r
+    Name(_ADR,0x00140005)            // Device (HI WORD)=20, Func (LO WORD)=5\r
+    Name(_STA,0xF)                   // Enabled, do Display\r
+    Name(_PRW,Package(){0x0F,0x03})  // GPE pin 0x0F, Wake from S3 -- PCI PME#\r
+}\r
+\r
+Device (ENT0)    // Ethernet0 [Bus 0, Device 20, Function 6]\r
+{\r
+    Name(_ADR,0x00140006)            // Device (HI WORD)=20, Func (LO WORD)=6\r
+    Name(_STA,0xF)                   // Enabled, do Display\r
+    Name(_PRW,Package(){0x0F,0x03})  // GPE pin 0x0F, Wake from S3 -- PCI PME#\r
+}\r
+\r
+Device (ENT1)    // Ethernet1 [Bus 0, Device 20, Function 7]\r
+{\r
+    Name(_ADR,0x00140007)            // Device (HI WORD)=20, Func (LO WORD)=7\r
+    Name(_STA,0xF)                   // Enabled, do Display\r
+    Name(_PRW,Package(){0x0F,0x03})  // GPE pin 0x0F, Wake from S3 -- PCI PME#\r
+}\r
+\r
+Device (SPI0)    // SPI0 [Bus 0, Device 21, Function 0]\r
+{\r
+    Name(_ADR,0x00150000)            // Device (HI WORD)=21, Func (LO WORD)=0\r
+    Name(_STA,0xF)                   // Enabled, do Display\r
+    Name(_PRW,Package(){0x0F,0x03})  // GPE pin 0x0F, Wake from S3 -- PCI PME#\r
+}\r
+\r
+Device (SPI1)    // SPI1 [Bus 0, Device 21, Function 1]\r
+{\r
+    Name(_ADR,0x00150001)            // Device (HI WORD)=21, Func (LO WORD)=1\r
+    Name(_STA,0xF)                   // Enabled, do Display\r
+    Name(_PRW,Package(){0x0F,0x03})  // GPE pin 0x0F, Wake from S3 -- PCI PME#\r
+}\r
+\r
+Device (GIP0)    // I2C/GPIO [Bus 0, Device 21, Function 2]\r
+{\r
+    Name(_ADR,0x00150002)            // Device (HI WORD)=21, Func (LO WORD)=2\r
+    Name(_STA,0xF)                   // Enabled, do Display\r
+    Name(_PRW,Package(){0x0F,0x03})  // GPE pin 0x0F, Wake from S3 -- PCI PME#\r
+\r
+    Device(GPO_)  // GPIO Virtual Child Device- for BAR0 resources\r
+    {\r
+        Name(_ADR, 0)\r
+        Name(_STA, 0xf)\r
+        Name(_PRW, Package(0x2)\r
+        {\r
+            0xf,\r
+            0x3\r
+        })\r
+    }\r
+    Device(I2C_)  // I2C Controller Virtual Child Device- for BAR1 resources\r
+    {\r
+        Name(_ADR, 1)\r
+        Name(_STA, 0xf)\r
+        Name(_PRW, Package(0x2)\r
+        {\r
+            0xf,\r
+            0x3\r
+        })\r
+    }\r
+}\r
+#endif\r
diff --git a/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/Tpm.asi b/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/Tpm.asi
new file mode 100644 (file)
index 0000000..f497973
--- /dev/null
@@ -0,0 +1,51 @@
+/** @file\r
+\r
+The Infineon SLB9645 TPM ACPI definition block.\r
+Provides TPM device info. and TPM presence check only.\r
+\r
+Copyright (c) 2013-2015 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution.  The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+Device (TPM)\r
+{\r
+  //\r
+  // Define _HID as Infineon TPM Device, _CID as "PNP0C31" (defined in\r
+  // "Secure Startup-FVE and TPM Admin BIOS and Platform Requirements").\r
+  //\r
+  Name(_HID ,EISAID("INT3493"))\r
+  Name(_CID, EISAID("PNP0C31"))\r
+\r
+  //\r
+  // Readable name of this device.\r
+  //\r
+  Name (_STR, Unicode ("Infineon TPM 1.2 Device (SLB9645TT1.2)"))\r
+\r
+  //\r
+  // Return the resource consumed by TPM device.\r
+  //\r
+  Name (_CRS, ResourceTemplate () {\r
+    I2cSerialBus (0x20, ControllerInitiated, 0x00061A80, AddressingMode7Bit, "\\_SB.PCI0.GIP0.I2C_", 0, ResourceConsumer,,)\r
+  })\r
+\r
+  //\r
+  // Check if TPM present.\r
+  //\r
+  Method (_STA, 0)\r
+  {\r
+    if (LEqual (TPMP, 0))\r
+    {\r
+      return (0)\r
+    }\r
+    Return (0x0f)\r
+  }\r
+\r
+}\r
diff --git a/QuarkPlatformPkg/Acpi/AcpiTables/Facs/Facs.aslc b/QuarkPlatformPkg/Acpi/AcpiTables/Facs/Facs.aslc
new file mode 100644 (file)
index 0000000..d34f116
--- /dev/null
@@ -0,0 +1,80 @@
+/** @file\r
+This file contains the FACS structure definition.\r
+\r
+Copyright (c) 2013-2015 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution.  The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+//\r
+// Statements that include other files\r
+//\r
+#include "Facs.h"\r
+\r
+EFI_ACPI_2_0_FIRMWARE_ACPI_CONTROL_STRUCTURE FACS = {\r
+  EFI_ACPI_2_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_SIGNATURE,\r
+  sizeof (EFI_ACPI_2_0_FIRMWARE_ACPI_CONTROL_STRUCTURE),\r
+\r
+  //\r
+  // Hardware Signature will be updated at runtime\r
+  //\r
+  0x00000000,\r
+  EFI_ACPI_FIRMWARE_WAKING_VECTOR,\r
+  EFI_ACPI_GLOBAL_LOCK,\r
+  EFI_ACPI_FIRMWARE_CONTROL_STRUCTURE_FLAGS,\r
+  EFI_ACPI_X_FIRMWARE_WAKING_VECTOR,\r
+  EFI_ACPI_2_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_VERSION,\r
+  {\r
+    EFI_ACPI_RESERVED_BYTE,\r
+    EFI_ACPI_RESERVED_BYTE,\r
+    EFI_ACPI_RESERVED_BYTE,\r
+    EFI_ACPI_RESERVED_BYTE,\r
+    EFI_ACPI_RESERVED_BYTE,\r
+    EFI_ACPI_RESERVED_BYTE,\r
+    EFI_ACPI_RESERVED_BYTE,\r
+    EFI_ACPI_RESERVED_BYTE,\r
+    EFI_ACPI_RESERVED_BYTE,\r
+    EFI_ACPI_RESERVED_BYTE,\r
+    EFI_ACPI_RESERVED_BYTE,\r
+    EFI_ACPI_RESERVED_BYTE,\r
+    EFI_ACPI_RESERVED_BYTE,\r
+    EFI_ACPI_RESERVED_BYTE,\r
+    EFI_ACPI_RESERVED_BYTE,\r
+    EFI_ACPI_RESERVED_BYTE,\r
+    EFI_ACPI_RESERVED_BYTE,\r
+    EFI_ACPI_RESERVED_BYTE,\r
+    EFI_ACPI_RESERVED_BYTE,\r
+    EFI_ACPI_RESERVED_BYTE,\r
+    EFI_ACPI_RESERVED_BYTE,\r
+    EFI_ACPI_RESERVED_BYTE,\r
+    EFI_ACPI_RESERVED_BYTE,\r
+    EFI_ACPI_RESERVED_BYTE,\r
+    EFI_ACPI_RESERVED_BYTE,\r
+    EFI_ACPI_RESERVED_BYTE,\r
+    EFI_ACPI_RESERVED_BYTE,\r
+    EFI_ACPI_RESERVED_BYTE,\r
+    EFI_ACPI_RESERVED_BYTE,\r
+    EFI_ACPI_RESERVED_BYTE,\r
+    EFI_ACPI_RESERVED_BYTE\r
+  }\r
+};\r
+\r
+VOID*\r
+ReferenceAcpiTable (\r
+  VOID\r
+  )\r
+\r
+{\r
+  //\r
+  // Reference the table being generated to prevent the optimizer from removing the\r
+  // data structure from the exeutable\r
+  //\r
+  return (VOID*)&FACS;\r
+}\r
diff --git a/QuarkPlatformPkg/Acpi/AcpiTables/Facs/Facs.h b/QuarkPlatformPkg/Acpi/AcpiTables/Facs/Facs.h
new file mode 100644 (file)
index 0000000..7997c19
--- /dev/null
@@ -0,0 +1,35 @@
+/** @file\r
+This file describes the contents of the ACPI Firmware ACPI Control Structure (FACS)\r
+.  Some additional ACPI values are defined in Acpi10.h, Acpi20.h, and Acpi30.h\r
+All changes to the FACS contents should be done in this file.\r
+\r
+Copyright (c) 2013-2015 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution.  The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#ifndef _FACS_H_\r
+#define _FACS_H_\r
+\r
+//\r
+// Statements that include other files\r
+//\r
+#include <IndustryStandard/Acpi.h>\r
+\r
+//\r
+// FACS Definitions\r
+//\r
+#define EFI_ACPI_FIRMWARE_WAKING_VECTOR 0x00000000\r
+#define EFI_ACPI_GLOBAL_LOCK 0x00000000\r
+\r
+#define EFI_ACPI_FIRMWARE_CONTROL_STRUCTURE_FLAGS 0x00000000\r
+#define EFI_ACPI_X_FIRMWARE_WAKING_VECTOR 0x0000000000000000\r
+\r
+#endif\r
diff --git a/QuarkPlatformPkg/Acpi/AcpiTables/Fadt/Fadt.h b/QuarkPlatformPkg/Acpi/AcpiTables/Fadt/Fadt.h
new file mode 100644 (file)
index 0000000..263fb3e
--- /dev/null
@@ -0,0 +1,108 @@
+/** @file\r
+This file describes the contents of the ACPI Fixed ACPI Description Table (FADT)\r
+.  Some additional ACPI values are defined in Acpi10.h, Acpi20.h, and Acpi30.h\r
+All changes to the FADT contents should be done in this file.\r
+\r
+Copyright (c) 2013-2015 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution.  The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#ifndef _FADT_H_\r
+#define _FADT_H_\r
+\r
+//\r
+// Statements that include other files\r
+//\r
+#include <IndustryStandard/Acpi.h>\r
+\r
+//\r
+// ACPI table information used to initialize tables.\r
+//\r
+#define EFI_ACPI_OEM_ID           'I','N','T','E','L',' '   // OEMID 6 bytes long\r
+#define EFI_ACPI_OEM_TABLE_ID     SIGNATURE_64('T','I','A','N','O',' ',' ',' ') // OEM table id 8 bytes long\r
+#define EFI_ACPI_OEM_REVISION     0x00000004\r
+#define EFI_ACPI_CREATOR_ID       SIGNATURE_32('I','N','T','L')\r
+#define EFI_ACPI_CREATOR_REVISION 0x0100000D\r
+\r
+//\r
+// FADT Definitions\r
+//\r
+#define PM_PROFILE      0x01\r
+#define INT_MODEL       0x01\r
+#define SCI_INT_VECTOR  0x0009\r
+#define ACPI_ENABLE     0x0a0\r
+#define ACPI_DISABLE    0x0a1\r
+#define S4BIOS_REQ      0x00\r
+#define PM1_EVT_LEN     0x04\r
+#define PM1_CNT_LEN     0x02\r
+#define PM2_CNT_LEN     0x00\r
+#define PM_TM_LEN       0x04\r
+#define GPE0_BLK_LEN    0x08\r
+#define GPE1_BLK_LEN    0x00\r
+#define GPE1_BASE       0x00\r
+#define RESERVED        0x00\r
+#define P_LVL2_LAT      0x0065\r
+#define P_LVL3_LAT      0x03e9\r
+#define FLUSH_SIZE      0x0400\r
+#define FLUSH_STRIDE    0x0010\r
+#define DUTY_OFFSET     0x01\r
+#define DUTY_WIDTH      0x03\r
+#define DAY_ALRM        0x00\r
+#define MON_ALRM        0x00\r
+#define CENTURY         0x00\r
+#define IAPC_BOOT_ARCH  EFI_ACPI_2_0_LEGACY_DEVICES\r
+#define FLAG            (EFI_ACPI_1_0_WBINVD | EFI_ACPI_1_0_PROC_C1 | EFI_ACPI_1_0_SLP_BUTTON | EFI_ACPI_1_0_RTC_S4)\r
+#define FLAG2           (EFI_ACPI_2_0_WBINVD | EFI_ACPI_2_0_PROC_C1 | EFI_ACPI_2_0_PWR_BUTTON | EFI_ACPI_2_0_SLP_BUTTON | EFI_ACPI_2_0_RTC_S4 | EFI_ACPI_2_0_RESET_REG_SUP | EFI_ACPI_3_0_USE_PLATFORM_CLOCK)\r
+\r
+#define RESET_REG_ADDRESS_SPACE_ID     EFI_ACPI_2_0_SYSTEM_IO\r
+#define RESET_REG_BIT_WIDTH            0x08\r
+#define RESET_REG_BIT_OFFSET           0x00\r
+#define RESET_REG_ADDRESS              0x0000000000000CF9\r
+#define RESET_VALUE                    0x02\r
+\r
+#define ACPI_RUNTIME_UPDATE            0x00\r
+\r
+#define PM1a_EVT_BLK_ADDRESS_SPACE_ID  EFI_ACPI_2_0_SYSTEM_IO\r
+#define PM1a_EVT_BLK_BIT_WIDTH         0x20\r
+#define PM1a_EVT_BLK_BIT_OFFSET        0x00\r
+\r
+#define PM1b_EVT_BLK_ADDRESS_SPACE_ID  EFI_ACPI_2_0_SYSTEM_IO\r
+#define PM1b_EVT_BLK_BIT_WIDTH         0x00\r
+#define PM1b_EVT_BLK_BIT_OFFSET        0x00\r
+#define PM1b_EVT_BLK_ADDRESS           0x0000000000000000\r
+\r
+#define PM1a_CNT_BLK_ADDRESS_SPACE_ID  EFI_ACPI_2_0_SYSTEM_IO\r
+#define PM1a_CNT_BLK_BIT_WIDTH         0x10\r
+#define PM1a_CNT_BLK_BIT_OFFSET        0x00\r
+\r
+#define PM1b_CNT_BLK_ADDRESS_SPACE_ID  EFI_ACPI_2_0_SYSTEM_IO\r
+#define PM1b_CNT_BLK_BIT_WIDTH         0x00\r
+#define PM1b_CNT_BLK_BIT_OFFSET        0x00\r
+#define PM1b_CNT_BLK_ADDRESS           0x0000000000000000\r
+\r
+#define PM2_CNT_BLK_ADDRESS_SPACE_ID   EFI_ACPI_2_0_SYSTEM_IO\r
+#define PM2_CNT_BLK_BIT_WIDTH          0x00\r
+#define PM2_CNT_BLK_BIT_OFFSET         0x00\r
+#define PM2_CNT_BLK_ADDRESS            0x0000000000000000\r
+\r
+#define PM_TMR_BLK_ADDRESS_SPACE_ID    EFI_ACPI_2_0_SYSTEM_IO\r
+#define PM_TMR_BLK_BIT_WIDTH           0x20\r
+#define PM_TMR_BLK_BIT_OFFSET          0x00\r
+\r
+#define GPE0_BLK_ADDRESS_SPACE_ID      EFI_ACPI_2_0_SYSTEM_IO\r
+#define GPE0_BLK_BIT_WIDTH             0x40\r
+#define GPE0_BLK_BIT_OFFSET            0x00\r
+\r
+#define GPE1_BLK_ADDRESS_SPACE_ID      EFI_ACPI_2_0_SYSTEM_IO\r
+#define GPE1_BLK_BIT_WIDTH             0x00\r
+#define GPE1_BLK_BIT_OFFSET            0x00\r
+#define GPE1_BLK_ADDRESS               0x0000000000000000\r
+#endif\r
diff --git a/QuarkPlatformPkg/Acpi/AcpiTables/Fadt/Fadt1.0.aslc b/QuarkPlatformPkg/Acpi/AcpiTables/Fadt/Fadt1.0.aslc
new file mode 100644 (file)
index 0000000..6ab0c40
--- /dev/null
@@ -0,0 +1,82 @@
+/** @file\r
+This file describes the contents of the ACPI Fixed ACPI Description Table\r
+(FADT).  Some additional ACPI values are defined in Acpi1_0.h and Acpi2_0.h.\r
+All changes to the FADT contents should be done in this file.\r
+\r
+Copyright (c) 2013-2015 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution.  The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#include "Fadt.h"\r
+\r
+EFI_ACPI_1_0_FIXED_ACPI_DESCRIPTION_TABLE FADT = {\r
+  EFI_ACPI_1_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE,\r
+  sizeof (EFI_ACPI_1_0_FIXED_ACPI_DESCRIPTION_TABLE),\r
+  EFI_ACPI_1_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION,\r
+  0,                          // to make sum of entire table == 0\r
+  EFI_ACPI_OEM_ID,            // OEMID is a 6 bytes long field\r
+  EFI_ACPI_OEM_TABLE_ID,      // OEM table identification(8 bytes long)\r
+  EFI_ACPI_OEM_REVISION,      // OEM revision number\r
+  EFI_ACPI_CREATOR_ID,        // ASL compiler vendor ID\r
+  EFI_ACPI_CREATOR_REVISION,  // ASL compiler revision number\r
+  0,                     // Physical addesss of FACS\r
+  0,                     // Physical address of DSDT\r
+  INT_MODEL,             // System Interrupt Model\r
+  RESERVED,              // reserved\r
+  SCI_INT_VECTOR,        // System vector of SCI interrupt\r
+  SMI_CMD_IO_PORT,       // Port address of SMI command port\r
+  ACPI_ENABLE,           // value to write to port smi_cmd to enable ACPI\r
+  ACPI_DISABLE,          // value to write to port smi_cmd to disable ACPI\r
+  S4BIOS_REQ,            // Value to write to SMI CMD port to enter the S4BIOS state\r
+  RESERVED,              // reserved - must be zero\r
+  PM1a_EVT_BLK_ADDRESS,  // Port address of Power Mgt 1a Event Reg Blk\r
+  PM1b_EVT_BLK_ADDRESS,  // Port address of Power Mgt 1b Event Reg Blk\r
+  PM1a_CNT_BLK_ADDRESS,  // Port address of Power Mgt 1a Ctrl Reg Blk\r
+  PM1b_CNT_BLK_ADDRESS,  // Port address of Power Mgt 1b Ctrl Reg Blk\r
+  PM2_CNT_BLK_ADDRESS,   // Port address of Power Mgt 2  Ctrl Reg Blk\r
+  PM_TMR_BLK_ADDRESS,    // Port address of Power Mgt Timer Ctrl Reg Blk\r
+  GPE0_BLK_ADDRESS,      // Port addr of General Purpose Event 0 Reg Blk\r
+  GPE1_BLK_ADDRESS,      // Port addr of General Purpose Event 1 Reg Blk\r
+  PM1_EVT_LEN,           // Byte Length of ports at pm1X_evt_blk\r
+  PM1_CNT_LEN,           // Byte Length of ports at pm1X_cnt_blk\r
+  PM2_CNT_LEN,           // Byte Length of ports at pm2_cnt_blk\r
+  PM_TM_LEN,             // Byte Length of ports at pm_tm_blk\r
+  GPE0_BLK_LEN,          // Byte Length of ports at gpe0_blk\r
+  GPE1_BLK_LEN,          // Byte Length of ports at gpe1_blk\r
+  GPE1_BASE,             // offset in gpe model where gpe1 events start\r
+  RESERVED,              // reserved\r
+  P_LVL2_LAT,            // worst case HW latency to enter/exit C2 state\r
+  P_LVL3_LAT,            // worst case HW latency to enter/exit C3 state\r
+  FLUSH_SIZE,            // Size of area read to flush caches\r
+  FLUSH_STRIDE,          // Stride used in flushing caches\r
+  DUTY_OFFSET,           // bit location of duty cycle field in p_cnt reg\r
+  DUTY_WIDTH,            // bit width of duty cycle field in p_cnt reg\r
+  DAY_ALRM,              // index to day-of-month alarm in RTC CMOS RAM\r
+  MON_ALRM,              // index to month-of-year alarm in RTC CMOS RAM\r
+  CENTURY,               // index to century in RTC CMOS RAM\r
+  RESERVED,              // reserved\r
+  RESERVED,              // reserved\r
+  RESERVED,              // reserved\r
+  FLAG\r
+};\r
+\r
+VOID*\r
+ReferenceAcpiTable (\r
+  VOID\r
+  )\r
+\r
+{\r
+  //\r
+  // Reference the table being generated to prevent the optimizer from removing the\r
+  // data structure from the exeutable\r
+  //\r
+  return (VOID*)&FADT;\r
+}\r
diff --git a/QuarkPlatformPkg/Acpi/AcpiTables/Fadt/Fadt2.0.aslc b/QuarkPlatformPkg/Acpi/AcpiTables/Fadt/Fadt2.0.aslc
new file mode 100644 (file)
index 0000000..0dbace1
--- /dev/null
@@ -0,0 +1,163 @@
+/** @file\r
+This file describes the contents of the ACPI Fixed ACPI Description Table\r
+(FADT).  Some additional ACPI values are defined in Acpi1_0.h and Acpi2_0.h.\r
+All changes to the FADT contents should be done in this file.\r
+\r
+Copyright (c) 2013-2015 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution.  The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#include "Fadt.h"\r
+\r
+EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE FADT = {\r
+  {\r
+    EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE,\r
+    sizeof (EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE),\r
+    EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION,\r
+    0,                    // to make sum of entire table == 0\r
+    {EFI_ACPI_OEM_ID},    // OEMID is a 6 bytes long field\r
+    EFI_ACPI_OEM_TABLE_ID,// OEM table identification(8 bytes long)\r
+    EFI_ACPI_OEM_REVISION,// OEM revision number\r
+    EFI_ACPI_CREATOR_ID,  // ASL compiler vendor ID\r
+    EFI_ACPI_CREATOR_REVISION  // ASL compiler revision number\r
+  },\r
+  0,                    // Physical addesss of FACS\r
+  0,                    // Physical address of DSDT\r
+  RESERVED,             // reserved\r
+  PM_PROFILE,           // Preferred powermanagement profile\r
+  SCI_INT_VECTOR,       // System vector of SCI interrupt\r
+  ACPI_RUNTIME_UPDATE,  // Port address of SMI command port\r
+  ACPI_ENABLE,          // value to write to port smi_cmd to enable ACPI\r
+  ACPI_DISABLE,         // value to write to port smi_cmd to disable ACPI\r
+  S4BIOS_REQ,           // Value to write to SMI CMD port to enter the S4BIOS state\r
+  RESERVED,             // reserved - must be zero\r
+  ACPI_RUNTIME_UPDATE,  // Port address of Power Mgt 1a Event Reg Blk\r
+  PM1b_EVT_BLK_ADDRESS, // Port address of Power Mgt 1b Event Reg Blk\r
+  ACPI_RUNTIME_UPDATE,  // Port address of Power Mgt 1a Ctrl Reg Blk\r
+  PM1b_CNT_BLK_ADDRESS, // Port address of Power Mgt 1b Ctrl Reg Blk\r
+  ACPI_RUNTIME_UPDATE,  // Port address of Power Mgt 2  Ctrl Reg Blk\r
+  ACPI_RUNTIME_UPDATE,  // Port address of Power Mgt Timer Ctrl Reg Blk\r
+  ACPI_RUNTIME_UPDATE,  // Port addr of General Purpose Event 0 Reg Blk\r
+  GPE1_BLK_ADDRESS,     // Port addr of General Purpose Event 1 Reg Blk\r
+  PM1_EVT_LEN,          // Byte Length of ports at pm1X_evt_blk\r
+  PM1_CNT_LEN,          // Byte Length of ports at pm1X_cnt_blk\r
+  PM2_CNT_LEN,          // Byte Length of ports at pm2_cnt_blk\r
+  PM_TM_LEN,            // Byte Length of ports at pm_tm_blk\r
+  GPE0_BLK_LEN,         // Byte Length of ports at gpe0_blk\r
+  GPE1_BLK_LEN,         // Byte Length of ports at gpe1_blk\r
+  GPE1_BASE,            // offset in gpe model where gpe1 events start\r
+  RESERVED,             // reserved\r
+  P_LVL2_LAT,           // worst case HW latency to enter/exit C2 state\r
+  P_LVL3_LAT,           // worst case HW latency to enter/exit C3 state\r
+  FLUSH_SIZE,           // Size of area read to flush caches\r
+  FLUSH_STRIDE,         // Stride used in flushing caches\r
+  DUTY_OFFSET,          // bit location of duty cycle field in p_cnt reg\r
+  DUTY_WIDTH,           // bit width of duty cycle field in p_cnt reg\r
+  DAY_ALRM,             // index to day-of-month alarm in RTC CMOS RAM\r
+  MON_ALRM,             // index to month-of-year alarm in RTC CMOS RAM\r
+  CENTURY,              // index to century in RTC CMOS RAM\r
+  IAPC_BOOT_ARCH,       // IA-PC Boot Architecture Flags\r
+  RESERVED,             // reserved\r
+  FLAG2,                // Fixed feature flags\r
+\r
+  {\r
+    RESET_REG_ADDRESS_SPACE_ID,  // Address of the reset register\r
+    RESET_REG_BIT_WIDTH,\r
+    RESET_REG_BIT_OFFSET,\r
+    RESERVED,\r
+    RESET_REG_ADDRESS\r
+  },\r
+  RESET_VALUE,          // Value to write to the RESET_REG port\r
+  {\r
+    RESERVED,\r
+    RESERVED,\r
+    RESERVED\r
+  },\r
+  0,                // 64Bit physical addesss of FACS\r
+  0,                // 64Bit physical address of DSDT\r
+\r
+  {\r
+    PM1a_EVT_BLK_ADDRESS_SPACE_ID, // Extended Port address of Power Mgt 1a Event Reg Blk\r
+    PM1a_EVT_BLK_BIT_WIDTH,\r
+    PM1a_EVT_BLK_BIT_OFFSET,\r
+    RESERVED,\r
+    ACPI_RUNTIME_UPDATE\r
+  },\r
+\r
+  {\r
+    PM1b_EVT_BLK_ADDRESS_SPACE_ID, // Extended Port address of Power Mgt 1b Event Reg Blk\r
+    PM1b_EVT_BLK_BIT_WIDTH,\r
+    PM1b_EVT_BLK_BIT_OFFSET,\r
+    RESERVED,\r
+    PM1b_EVT_BLK_ADDRESS\r
+  },\r
+\r
+  {\r
+    PM1a_CNT_BLK_ADDRESS_SPACE_ID, // Extended Port address of Power Mgt 1a Ctrl Reg Blk\r
+    PM1a_CNT_BLK_BIT_WIDTH,\r
+    PM1a_CNT_BLK_BIT_OFFSET,\r
+    RESERVED,\r
+    ACPI_RUNTIME_UPDATE\r
+  },\r
+\r
+  {\r
+    PM1b_CNT_BLK_ADDRESS_SPACE_ID, // Extended Port address of Power Mgt 1b Ctrl Reg Blk\r
+    PM1b_CNT_BLK_BIT_WIDTH,\r
+    PM1b_CNT_BLK_BIT_OFFSET,\r
+    RESERVED,\r
+    PM1b_CNT_BLK_ADDRESS\r
+  },\r
+\r
+  {\r
+    PM2_CNT_BLK_ADDRESS_SPACE_ID,  // Extended Port address of Power Mgt 2  Ctrl Reg Blk\r
+    PM2_CNT_BLK_BIT_WIDTH,\r
+    PM2_CNT_BLK_BIT_OFFSET,\r
+    RESERVED,\r
+    ACPI_RUNTIME_UPDATE\r
+  },\r
+\r
+  {\r
+    PM_TMR_BLK_ADDRESS_SPACE_ID,   // Extended Port address of Power Mgt Timer Ctrl Reg Blk\r
+    PM_TMR_BLK_BIT_WIDTH,\r
+    PM_TMR_BLK_BIT_OFFSET,\r
+    RESERVED,\r
+    ACPI_RUNTIME_UPDATE\r
+  },\r
+\r
+  {\r
+    GPE0_BLK_ADDRESS_SPACE_ID,   // Extended Port address of General Purpose Event 0 Reg Blk\r
+    GPE0_BLK_BIT_WIDTH,\r
+    GPE0_BLK_BIT_OFFSET,\r
+    RESERVED,\r
+    ACPI_RUNTIME_UPDATE\r
+  },\r
+\r
+  {\r
+    GPE1_BLK_ADDRESS_SPACE_ID,   // Extended Port address of General Purpose Event 1 Reg Blk\r
+    GPE1_BLK_BIT_WIDTH,\r
+    GPE1_BLK_BIT_OFFSET,\r
+    RESERVED,\r
+    GPE1_BLK_ADDRESS\r
+  }\r
+};\r
+\r
+VOID*\r
+ReferenceAcpiTable (\r
+  VOID\r
+  )\r
+\r
+{\r
+  //\r
+  // Reference the table being generated to prevent the optimizer from removing the\r
+  // data structure from the exeutable\r
+  //\r
+  return (VOID*)&FADT;\r
+}\r
diff --git a/QuarkPlatformPkg/Acpi/AcpiTables/Hpet/Hpet.aslc b/QuarkPlatformPkg/Acpi/AcpiTables/Hpet/Hpet.aslc
new file mode 100644 (file)
index 0000000..19497ef
--- /dev/null
@@ -0,0 +1,74 @@
+/** @file\r
+This file contains a structure definition for the ACPI 1.0 High Precision Event Timer\r
+Description Table (HPET).  The contents of this file should only be modified\r
+for bug fixes, no porting is required.  The table layout is defined in\r
+HighPrecisionEventTimerTable.h and the table contents are defined in Acpi1.0.h and Hpet.h.\r
+\r
+Copyright (c) 2013-2015 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution.  The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+//\r
+// Statements that include other files\r
+//\r
+\r
+#include "Hpet.h"\r
+\r
+//\r
+// High Precision Event Timer Table\r
+// Please modify all values in Hpet.h only.\r
+//\r
+\r
+EFI_ACPI_HIGH_PRECISION_EVENT_TIMER_TABLE_HEADER Hpet = {\r
+  {\r
+    EFI_ACPI_3_0_HIGH_PRECISION_EVENT_TIMER_TABLE_SIGNATURE,\r
+    sizeof (EFI_ACPI_HIGH_PRECISION_EVENT_TIMER_TABLE_HEADER),\r
+    EFI_ACPI_HIGH_PRECISION_EVENT_TIMER_TABLE_REVISION,\r
+\r
+    //\r
+    // Checksum will be updated at runtime\r
+    //\r
+    0x00,\r
+\r
+    //\r
+    // It is expected that these values will be updated at runtime\r
+    //\r
+    {' ', ' ', ' ', ' ', ' ', ' '},\r
+\r
+    0,\r
+    EFI_ACPI_OEM_HPET_REVISION,\r
+    0,\r
+    0\r
+  },\r
+  EFI_ACPI_EVENT_TIMER_BLOCK_ID,\r
+  {\r
+    EFI_ACPI_EVENT_TIMER_BLOCK_ADDRESS_SPACE_ID,\r
+    EFI_ACPI_EVENT_TIMER_BLOCK_BIT_WIDTH,\r
+    EFI_ACPI_EVENT_TIMER_BLOCK_BIT_OFFSET,\r
+    EFI_ACPI_EVENT_TIMER_ACCESS_SIZE,\r
+    ACPI_RUNTIME_UPDATE\r
+  },\r
+  EFI_ACPI_HPET_NUMBER,\r
+  EFI_ACPI_MIN_CLOCK_TICK,\r
+  EFI_ACPI_HPET_ATTRIBUTES\r
+};\r
+\r
+VOID*\r
+ReferenceAcpiTable (\r
+  VOID\r
+  )\r
+{\r
+  //\r
+  // Reference the table being generated to prevent the optimizer from removing the\r
+  // data structure from the exeutable\r
+  //\r
+  return (VOID*)&Hpet;\r
+}\r
diff --git a/QuarkPlatformPkg/Acpi/AcpiTables/Hpet/Hpet.h b/QuarkPlatformPkg/Acpi/AcpiTables/Hpet/Hpet.h
new file mode 100644 (file)
index 0000000..351550c
--- /dev/null
@@ -0,0 +1,51 @@
+/** @file\r
+This file describes the contents of the ACPI High Precision Event Timer Description Table\r
+(HPET).  Some additional ACPI values are defined in Acpi10.h, Acpi20.h, and Acpi30.h\r
+All changes to the HPET contents should be done in this file.\r
+\r
+Copyright (c) 2013-2015 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution.  The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#ifndef _HPET_H_\r
+#define _HPET_H_\r
+\r
+//\r
+// Statements that include other files\r
+//\r
+#include <IndustryStandard/Acpi.h>\r
+#include <IndustryStandard/HighPrecisionEventTimerTable.h>\r
+\r
+//\r
+// HPET Definitions\r
+//\r
+\r
+#define EFI_ACPI_OEM_HPET_REVISION                      0x00000001\r
+\r
+#define EFI_ACPI_EVENT_TIMER_BLOCK_ID                   0x8086A201\r
+\r
+#define ACPI_RUNTIME_UPDATE                             0x00\r
+\r
+//\r
+// Event Timer Block Base Address Information\r
+//\r
+#define EFI_ACPI_EVENT_TIMER_BLOCK_ADDRESS_SPACE_ID     EFI_ACPI_3_0_SYSTEM_MEMORY\r
+#define EFI_ACPI_EVENT_TIMER_BLOCK_BIT_WIDTH            0x00\r
+#define EFI_ACPI_EVENT_TIMER_BLOCK_BIT_OFFSET           0x00\r
+#define EFI_ACPI_EVENT_TIMER_ACCESS_SIZE                0x00\r
+\r
+#define EFI_ACPI_HPET_NUMBER                            0x00\r
+\r
+#define EFI_ACPI_MIN_CLOCK_TICK                         0x0080\r
+\r
+#define EFI_ACPI_HPET_ATTRIBUTES                        0x00\r
+\r
+#endif\r
diff --git a/QuarkPlatformPkg/Acpi/AcpiTables/Mcfg/Mcfg.aslc b/QuarkPlatformPkg/Acpi/AcpiTables/Mcfg/Mcfg.aslc
new file mode 100644 (file)
index 0000000..829d6b5
--- /dev/null
@@ -0,0 +1,81 @@
+/** @file\r
+This file contains a structure definition for the ACPI Memory Mapped Configuration\r
+Address Space table (MCFG).  Any changes to the number of entries in the table require\r
+updating the structure count in Mcfg.h and then adding the structure to the\r
+MCFG defined in this file.  The table layout is defined in Mcfg.h and the\r
+table contents are defined in the MemoryMappedConfigurationSpaceAccessTable.h.\r
+\r
+Copyright (c) 2013-2015 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution.  The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+//\r
+// Statements that include other files\r
+//\r
+\r
+#include "Mcfg.h"\r
+\r
+//\r
+// Multiple APIC Description Table\r
+//\r
+\r
+EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_DESCRIPTION_TABLE Mcfg = {\r
+  {\r
+    EFI_ACPI_3_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE,\r
+    sizeof (EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_DESCRIPTION_TABLE),\r
+    EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_TABLE_REVISION,\r
+\r
+    //\r
+    // Checksum will be updated at runtime\r
+    //\r
+    0x00,\r
+\r
+    //\r
+    // It is expected that these values will be programmed at runtime\r
+    //\r
+    {' ', ' ', ' ', ' ', ' ', ' '},\r
+\r
+    0,\r
+    EFI_ACPI_OEM_MCFG_REVISION,\r
+    0,\r
+    0\r
+  },\r
+  //\r
+  // Reserved\r
+  //\r
+  0x0000000000000000,\r
+\r
+  //\r
+  // MCFG specific fields\r
+  //\r
+\r
+  {\r
+    {\r
+      0x00000000,                                                   // BaseAddress (will be updated at runtime)\r
+      0x0000,                                                       // PciSegmentGroupNumber\r
+      0x00,                                                         // StartBusNumber\r
+      0x1F,                                                         // EndBusNumber\r
+      0x00000000                                                    // Reserved\r
+    }\r
+  }\r
+};\r
+\r
+VOID*\r
+ReferenceAcpiTable (\r
+  VOID\r
+  )\r
+{\r
+  //\r
+  // Reference the table being generated to prevent the optimizer from removing the\r
+  // data structure from the exeutable\r
+  //\r
+  return (VOID*)&Mcfg;\r
+}\r
diff --git a/QuarkPlatformPkg/Acpi/AcpiTables/Mcfg/Mcfg.h b/QuarkPlatformPkg/Acpi/AcpiTables/Mcfg/Mcfg.h
new file mode 100644 (file)
index 0000000..0d688f2
--- /dev/null
@@ -0,0 +1,62 @@
+/** @file\r
+This file describes the contents of the ACPI Memory Mapped Configuration\r
+Space Access Table (MCFG).  Some additional ACPI values are defined in Acpi10.h,\r
+Acpi20.h, and Acpi30.h.\r
+\r
+Copyright (c) 2013-2015 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution.  The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#ifndef _MCFG_H_\r
+#define _MCFG_H_\r
+\r
+//\r
+// Statements that include other files\r
+//\r
+\r
+#include <IndustryStandard/Acpi.h>\r
+#include <IndustryStandard/MemoryMappedConfigurationSpaceAccessTable.h>\r
+\r
+//\r
+// MCFG Definitions\r
+//\r
+\r
+#define EFI_ACPI_OEM_MCFG_REVISION 0x00000001\r
+\r
+//\r
+// Define the number of allocation structures so that we can build the table structure.\r
+//\r
+\r
+#define EFI_ACPI_ALLOCATION_STRUCTURE_COUNT           1\r
+\r
+//\r
+// MCFG structure\r
+//\r
+\r
+//\r
+// Ensure proper structure formats\r
+//\r
+#pragma pack (1)\r
+\r
+//\r
+// MCFG Table structure\r
+//\r
+typedef struct {\r
+  EFI_ACPI_DESCRIPTION_HEADER                                                            Header;\r
+  UINT64                                                                                 Reserved;\r
+#if EFI_ACPI_ALLOCATION_STRUCTURE_COUNT > 0\r
+  EFI_ACPI_MEMORY_MAPPED_ENHANCED_CONFIGURATION_SPACE_BASE_ADDRESS_ALLOCATION_STRUCTURE  AllocationStructure[EFI_ACPI_ALLOCATION_STRUCTURE_COUNT];\r
+#endif\r
+} EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_DESCRIPTION_TABLE;\r
+\r
+#pragma pack ()\r
+\r
+#endif\r
diff --git a/QuarkPlatformPkg/Acpi/Dxe/AcpiPlatform/AcpiPciUpdate.c b/QuarkPlatformPkg/Acpi/Dxe/AcpiPlatform/AcpiPciUpdate.c
new file mode 100644 (file)
index 0000000..b0f0b44
--- /dev/null
@@ -0,0 +1,1410 @@
+/** @file\r
+Update the _PRT and _PRW method for pci devices\r
+\r
+Copyright (c) 2013-2015 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution.  The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+**/\r
+#include "AcpiPlatform.h"\r
+\r
+PCI_DEVICE_INFO *mQNCPciInfo = NULL;\r
+\r
+/**\r
+  Init Pci Device Structure\r
+  @param mConfigData    - Pointer of Pci Device information Structure\r
+\r
+**/\r
+VOID\r
+InitPciDeviceInfoStructure (\r
+  PCI_DEVICE_SETTING            *mConfigData\r
+  )\r
+{\r
+  //\r
+  // Return 0 given that function unsupported.\r
+  // Would need to parse ACPI tables and build mQNCPciInfo above\r
+  // with found _PRT & _PRW methods for PCI devices.\r
+  //\r
+  mConfigData->PciDeviceInfoNumber = 0;\r
+}\r
+\r
+/**\r
+  return Integer value.\r
+\r
+  @param Data    - AML data buffer\r
+  @param Integer - integer value.\r
+\r
+  @return Data size processed.\r
+**/\r
+UINTN\r
+SdtGetInteger (\r
+  IN  UINT8  *Data,\r
+  OUT UINT64 *Integer\r
+  )\r
+{\r
+  *Integer = 0;\r
+  switch (*Data) {\r
+  case AML_ZERO_OP:\r
+    return 1;\r
+  case AML_ONE_OP:\r
+    *Integer = 1;\r
+    return 1;\r
+  case AML_ONES_OP:\r
+    *Integer = (UINTN)-1;\r
+    return 1;\r
+  case AML_BYTE_PREFIX:\r
+    CopyMem (Integer, Data + 1, sizeof(UINT8));\r
+    return 1 + sizeof(UINT8);\r
+  case AML_WORD_PREFIX:\r
+    CopyMem (Integer, Data + 1, sizeof(UINT16));\r
+    return 1 + sizeof(UINT16);\r
+  case AML_DWORD_PREFIX:\r
+    CopyMem (Integer, Data + 1, sizeof(UINT32));\r
+    return 1 + sizeof(UINT32);\r
+  case AML_QWORD_PREFIX:\r
+    CopyMem (Integer, Data + 1, sizeof(UINT64));\r
+    return 1 + sizeof(UINT64);\r
+  default:\r
+    // Something wrong\r
+    ASSERT (FALSE);\r
+    return 1;\r
+  }\r
+}\r
+\r
+\r
+/**\r
+  Check if this handle has expected opcode.\r
+\r
+  @param AcpiSdt    Pointer to Acpi SDT protocol\r
+  @param Handle     ACPI handle\r
+  @param OpCode     Expected OpCode\r
+  @param SubOpCode  Expected SubOpCode\r
+\r
+  @retval TURE  This handle has expected opcode\r
+  @retval FALSE This handle does not have expected opcode\r
+**/\r
+BOOLEAN\r
+SdtIsThisTypeObject (\r
+  IN EFI_ACPI_SDT_PROTOCOL *AcpiSdt,\r
+  IN EFI_ACPI_HANDLE Handle,\r
+  IN UINT8           OpCode,\r
+  IN UINT8           SubOpCode\r
+  )\r
+{\r
+  EFI_STATUS         Status;\r
+  EFI_ACPI_DATA_TYPE DataType;\r
+  UINT8              *Data;\r
+  UINTN              DataSize;\r
+\r
+  Status = AcpiSdt->GetOption (Handle, 0, &DataType, (CONST VOID **)&Data, &DataSize);\r
+  ASSERT_EFI_ERROR (Status);\r
+  ASSERT (DataType == EFI_ACPI_DATA_TYPE_OPCODE);\r
+\r
+  if (OpCode == AML_EXT_OP) {\r
+    if (Data[1] == SubOpCode) {\r
+      return TRUE;\r
+    }\r
+  } else {\r
+    if (Data[0] == OpCode) {\r
+      return TRUE;\r
+    }\r
+  }\r
+  return FALSE;\r
+}\r
+\r
+/**\r
+  Check if this handle has expected name and name value.\r
+\r
+  @param AcpiSdt    Pointer to Acpi SDT protocol\r
+  @param Handle     ACPI handle\r
+  @param Name       Expected name\r
+  @param Value      Expected name value\r
+\r
+  @retval TURE  This handle has expected name and name value.\r
+  @retval FALSE This handle does not have expected name and name value.\r
+**/\r
+BOOLEAN\r
+SdtIsNameIntegerValueEqual (\r
+  IN EFI_ACPI_SDT_PROTOCOL *AcpiSdt,\r
+  IN EFI_ACPI_HANDLE Handle,\r
+  IN CHAR8           *Name,\r
+  IN UINT64          Value\r
+  )\r
+{\r
+  EFI_STATUS         Status;\r
+  EFI_ACPI_DATA_TYPE DataType;\r
+  UINT8              *Data;\r
+  UINTN              DataSize;\r
+  UINT64             Integer;\r
+\r
+  Status = AcpiSdt->GetOption (Handle, 1, &DataType, (CONST VOID **)&Data, &DataSize);\r
+  ASSERT_EFI_ERROR (Status);\r
+  ASSERT (DataType == EFI_ACPI_DATA_TYPE_NAME_STRING);\r
+\r
+  if (CompareMem (Data, Name, 4) != 0) {\r
+    return FALSE;\r
+  }\r
+\r
+  //\r
+  // Name match check object\r
+  //\r
+  Status = AcpiSdt->GetOption (Handle, 2, &DataType, (CONST VOID **)&Data, &DataSize);\r
+  ASSERT_EFI_ERROR (Status);\r
+\r
+  Integer = 0;\r
+  SdtGetInteger (Data, &Integer);\r
+  if (Integer != Value) {\r
+    return FALSE;\r
+  }\r
+\r
+  // All match\r
+  return TRUE;\r
+}\r
+\r
+/**\r
+  Check if this handle's children has expected name and name value.\r
+\r
+  @param AcpiSdt          Pointer to Acpi SDT protocol\r
+  @param ParentHandle     ACPI parent handle\r
+  @param Name             Expected name\r
+  @param Value            Expected name value\r
+\r
+  @retval TURE  This handle's children has expected name and name value.\r
+  @retval FALSE This handle's children does not have expected name and name value.\r
+**/\r
+BOOLEAN\r
+SdtCheckNameIntegerValue (\r
+  IN EFI_ACPI_SDT_PROTOCOL *AcpiSdt,\r
+  IN EFI_ACPI_HANDLE ParentHandle,\r
+  IN CHAR8           *Name,\r
+  IN UINT64          Value\r
+  )\r
+{\r
+  EFI_ACPI_HANDLE PreviousHandle;\r
+  EFI_ACPI_HANDLE Handle;\r
+  EFI_STATUS      Status;\r
+\r
+  Handle = NULL;\r
+  while (TRUE) {\r
+    PreviousHandle = Handle;\r
+    Status = AcpiSdt->GetChild (ParentHandle, &Handle);\r
+    ASSERT_EFI_ERROR (Status);\r
+\r
+    if (PreviousHandle != NULL) {\r
+      Status = AcpiSdt->Close (PreviousHandle);\r
+      ASSERT_EFI_ERROR (Status);\r
+    }\r
+\r
+    //\r
+    // Done\r
+    //\r
+    if (Handle == NULL) {\r
+      return FALSE;\r
+    }\r
+\r
+    //\r
+    // Check this name\r
+    //\r
+    if (SdtIsThisTypeObject (AcpiSdt, Handle, AML_NAME_OP, 0)) {\r
+      if (SdtIsNameIntegerValueEqual (AcpiSdt, Handle, Name, Value)) {\r
+        return TRUE;\r
+      }\r
+    }\r
+  }\r
+\r
+  //\r
+  // Should not run here\r
+  //\r
+}\r
+\r
+/**\r
+  Convert the pci address from VPD (bus,dev,fun) into the address that acpi table\r
+  can recognize.\r
+\r
+  @param PciAddress    Pci address from VPD\r
+\r
+  @retval return the address that acpi table can recognize\r
+**/\r
+UINT32\r
+SdtConvertToAcpiPciAdress (\r
+  IN UINT32 PciAddress\r
+  )\r
+{\r
+  UINT32 ReturnAddress;\r
+\r
+  ReturnAddress = ((PciAddress & 0x0000FF00) << 8) | (PciAddress & 0x000000FF);\r
+\r
+  if ((PciAddress & 0x000000FF) == 0x000000FF)\r
+    ReturnAddress |= 0x0000FFFF;\r
+\r
+  return ReturnAddress;\r
+}\r
+\r
+/**\r
+  return AML NameString size.\r
+\r
+  @param Buffer - AML name string\r
+\r
+  @return AML name string size\r
+**/\r
+UINTN\r
+SdtGetNameStringSize (\r
+  IN UINT8              *Buffer\r
+  )\r
+{\r
+  UINTN                 SegCount;\r
+  UINTN                 Length;\r
+  UINT8                 *Name;\r
+\r
+  Name = Buffer;\r
+  Length = 0;\r
+\r
+  //\r
+  // Parse root or prefix\r
+  //\r
+  if (*Buffer == AML_ROOT_CHAR) {\r
+    //\r
+    // RootChar\r
+    //\r
+    Buffer ++;\r
+    Length ++;\r
+  } else if (*Buffer == AML_PARENT_PREFIX_CHAR) {\r
+    //\r
+    // ParentPrefixChar\r
+    //\r
+    Buffer ++;\r
+    Length ++;\r
+    while (*Buffer == AML_PARENT_PREFIX_CHAR) {\r
+      Buffer ++;\r
+      Length ++;\r
+    }\r
+  }\r
+\r
+  //\r
+  // Parse name segment\r
+  //\r
+  if (*Buffer == AML_DUAL_NAME_PREFIX) {\r
+    //\r
+    // DualName\r
+    //\r
+    Buffer ++;\r
+    Length ++;\r
+    SegCount = 2;\r
+  } else if (*Buffer == AML_MULTI_NAME_PREFIX) {\r
+    //\r
+    // MultiName\r
+    //\r
+    Buffer ++;\r
+    Length ++;\r
+    SegCount = *Buffer;\r
+    Buffer ++;\r
+    Length ++;\r
+  } else if (*Buffer == 0) {\r
+    //\r
+    // NULL Name\r
+    //\r
+    SegCount = 0;\r
+    Length ++;\r
+  } else {\r
+    //\r
+    // NameSeg\r
+    //\r
+    SegCount = 1;\r
+  }\r
+\r
+  Buffer += 4 * SegCount;\r
+  Length += 4 * SegCount;\r
+\r
+  return Length;\r
+}\r
+\r
+/**\r
+  The routine to check if this device is PCI root bridge.\r
+\r
+  @param AcpiSdt       Pointer to Acpi SDT protocol\r
+  @param DeviceHandle  ACPI device handle\r
+  @param Context       Context info - not used here\r
+\r
+  @retval TRUE  This is PCI root bridge\r
+  @retval FALSE This is not PCI root bridge\r
+**/\r
+BOOLEAN\r
+SdtFindRootBridgeHandle (\r
+  IN EFI_ACPI_SDT_PROTOCOL  *AcpiSdt,\r
+  IN EFI_ACPI_HANDLE        CheckHandle,\r
+  IN VOID                   *Context\r
+  )\r
+{\r
+  BOOLEAN            Result;\r
+  EFI_ACPI_DATA_TYPE DataType;\r
+  UINT8              *Data;\r
+  UINTN              DataSize;\r
+  EFI_STATUS         Status;\r
+\r
+  if (!SdtIsThisTypeObject (AcpiSdt, CheckHandle, AML_EXT_OP, AML_EXT_DEVICE_OP))\r
+    return FALSE;\r
+\r
+  Result = SdtCheckNameIntegerValue (AcpiSdt,CheckHandle, "_HID", (UINT64)0x080AD041); // PNP0A08\r
+  if (!Result) {\r
+    Result = SdtCheckNameIntegerValue (AcpiSdt, CheckHandle, "_CID", (UINT64)0x030AD041); // PNP0A03\r
+    if (!Result) {\r
+      return Result;\r
+    }\r
+  }\r
+\r
+  //\r
+  // Found\r
+  //\r
+  Status = AcpiSdt->GetOption (CheckHandle, 1, &DataType, (CONST VOID **)&Data, &DataSize);\r
+  ASSERT_EFI_ERROR (Status);\r
+  ASSERT (DataType == EFI_ACPI_DATA_TYPE_NAME_STRING);\r
+\r
+  return Result;\r
+}\r
+\r
+\r
+/**\r
+  The routine to check if this device is wanted.\r
+\r
+  @param AcpiSdt       Pointer to Acpi SDT protocol\r
+  @param DeviceHandle  ACPI device handle\r
+  @param Context       Context info - not used here\r
+\r
+  @retval TRUE  This is PCI device wanted\r
+  @retval FALSE This is not PCI device wanted\r
+**/\r
+BOOLEAN\r
+SdtFindPciDeviceHandle (\r
+  IN EFI_ACPI_SDT_PROTOCOL  *AcpiSdt,\r
+  IN EFI_ACPI_HANDLE        CheckHandle,\r
+  IN VOID                   *Context\r
+  )\r
+{\r
+  BOOLEAN            Result;\r
+  EFI_ACPI_DATA_TYPE DataType;\r
+  UINT8              *Data;\r
+  UINTN              DataSize;\r
+  EFI_STATUS         Status;\r
+\r
+  if (!SdtIsThisTypeObject (AcpiSdt, CheckHandle, AML_EXT_OP, AML_EXT_DEVICE_OP))\r
+    return FALSE;\r
+\r
+  Result = SdtCheckNameIntegerValue (AcpiSdt,CheckHandle, "_ADR", (UINT64)*(UINT32 *)Context);\r
+  if (!Result) {\r
+    return Result;\r
+  }\r
+\r
+  //\r
+  // Found\r
+  //\r
+  Status = AcpiSdt->GetOption (CheckHandle, 1, &DataType, (CONST VOID **)&Data, &DataSize);\r
+  ASSERT_EFI_ERROR (Status);\r
+  ASSERT (DataType == EFI_ACPI_DATA_TYPE_NAME_STRING);\r
+\r
+  return Result;\r
+}\r
+\r
+/**\r
+  Go through the parent handle and find the handle which pass CheckHandleInfo.\r
+\r
+  @param AcpiSdt          Pointer to Acpi SDT protocol\r
+  @param ParentHandle     ACPI parent handle\r
+  @param CheckHandleInfo  The callback routine to check if this handle meet the requirement\r
+  @param Context          The context of CheckHandleInfo\r
+\r
+  @return the handle which is first one can pass CheckHandleInfo.\r
+**/\r
+EFI_ACPI_HANDLE\r
+SdtGetHandleByScanAllChilds (\r
+  IN EFI_ACPI_SDT_PROTOCOL  *AcpiSdt,\r
+  IN EFI_ACPI_HANDLE        ParentHandle,\r
+  IN CHECK_HANDLE_INFO      CheckHandleInfo,\r
+  IN VOID                   *Context\r
+  )\r
+{\r
+  EFI_ACPI_HANDLE    PreviousHandle;\r
+  EFI_ACPI_HANDLE    Handle;\r
+  EFI_STATUS         Status;\r
+  EFI_ACPI_HANDLE    ReturnHandle;\r
+\r
+  //\r
+  // Use deep first algo to enumerate all ACPI object\r
+  //\r
+  Handle = NULL;\r
+  while (TRUE) {\r
+    PreviousHandle = Handle;\r
+    Status = AcpiSdt->GetChild (ParentHandle, &Handle);\r
+    ASSERT_EFI_ERROR (Status);\r
+\r
+    if (PreviousHandle != NULL) {\r
+      Status = AcpiSdt->Close (PreviousHandle);\r
+      ASSERT_EFI_ERROR (Status);\r
+    }\r
+\r
+    //\r
+    // Done\r
+    //\r
+    if (Handle == NULL) {\r
+      return NULL;\r
+    }\r
+\r
+    //\r
+    // Check this handle\r
+    //\r
+    if (CheckHandleInfo (AcpiSdt, Handle, Context)) {\r
+      return Handle;\r
+    }\r
+\r
+    //\r
+    // Enumerate\r
+    //\r
+    ReturnHandle = SdtGetHandleByScanAllChilds (AcpiSdt, Handle, CheckHandleInfo, Context);\r
+    if (ReturnHandle != NULL) {\r
+      return ReturnHandle;\r
+    }\r
+  }\r
+\r
+  //\r
+  // Should not run here\r
+  //\r
+}\r
+\r
+\r
+/**\r
+  Check whether the INTx package is matched\r
+\r
+  @param AcpiSdt          Pointer to Acpi SDT protocol\r
+  @param INTxPkgHandle    ACPI INTx package handle\r
+  @param PciAddress       Acpi pci address\r
+  @param INTx             Index of INTx pin\r
+  @param IsAPIC           Tell whether the returned INTx package is for APIC or not\r
+\r
+  @retval       TRUE      the INTx package is matched\r
+  @retval       FALSE     the INTx package is not matched\r
+\r
+**/\r
+BOOLEAN\r
+SdtCheckINTxPkgIsMatch (\r
+  IN EFI_ACPI_SDT_PROTOCOL  *AcpiSdt,\r
+  IN EFI_ACPI_HANDLE        INTxPkgHandle,\r
+  IN UINT32                 PciAddress,\r
+  IN UINT8                  INTx,\r
+  IN BOOLEAN                *IsAPIC\r
+  )\r
+{\r
+  EFI_ACPI_HANDLE    PreviousHandle;\r
+  EFI_STATUS         Status;\r
+  EFI_ACPI_HANDLE    MemberHandle;\r
+  EFI_ACPI_DATA_TYPE DataType;\r
+  UINT8              *Data;\r
+  UINTN              DataSize;\r
+  UINT64             CurrentPciAddress;\r
+  UINT64             CurrentINTx;\r
+  UINTN              ChildSize;\r
+\r
+\r
+  //\r
+  // Check the pci address\r
+  //\r
+  MemberHandle = NULL;\r
+  Status = AcpiSdt->GetChild (INTxPkgHandle, &MemberHandle);\r
+  ASSERT_EFI_ERROR (Status);\r
+  ASSERT (MemberHandle != NULL);\r
+\r
+  Status = AcpiSdt->GetOption (MemberHandle, 0, &DataType, (CONST VOID **)&Data, &DataSize);\r
+  ASSERT_EFI_ERROR (Status);\r
+  ASSERT (DataType == EFI_ACPI_DATA_TYPE_OPCODE);\r
+\r
+  CurrentPciAddress = 0;\r
+  SdtGetInteger (Data, &CurrentPciAddress);\r
+\r
+  if (CurrentPciAddress != PciAddress) {\r
+\r
+    Status = AcpiSdt->Close (MemberHandle);\r
+    ASSERT_EFI_ERROR (Status);\r
+    return FALSE;\r
+  }\r
+\r
+  //\r
+  // Check the pci interrupt pin\r
+  //\r
+  PreviousHandle = MemberHandle;\r
+  Status = AcpiSdt->GetChild (INTxPkgHandle, &MemberHandle);\r
+  ASSERT_EFI_ERROR (Status);\r
+  ASSERT (MemberHandle != NULL);\r
+\r
+  if (PreviousHandle != NULL) {\r
+    Status = AcpiSdt->Close (PreviousHandle);\r
+    ASSERT_EFI_ERROR (Status);\r
+  }\r
+\r
+  Status = AcpiSdt->GetOption (MemberHandle, 0, &DataType, (CONST VOID **)&Data, &DataSize);\r
+  ASSERT_EFI_ERROR (Status);\r
+  ASSERT (DataType == EFI_ACPI_DATA_TYPE_OPCODE);\r
+\r
+  CurrentINTx = 0;\r
+  ChildSize = SdtGetInteger (Data, &CurrentINTx);\r
+\r
+  Status = AcpiSdt->Close (MemberHandle);\r
+  ASSERT_EFI_ERROR (Status);\r
+\r
+  if (CurrentINTx != INTx)\r
+    return FALSE;\r
+\r
+  Data += ChildSize;\r
+\r
+  if (*Data == AML_BYTE_PREFIX)\r
+    Data += 1;\r
+\r
+  //\r
+  // Check the pci interrupt source\r
+  //\r
+  if (*Data  != 0)\r
+    *IsAPIC = FALSE;\r
+  else\r
+    *IsAPIC = TRUE;\r
+\r
+  return TRUE;\r
+}\r
+\r
+\r
+\r
+\r
+/**\r
+  Get the wanted INTx package inside the parent package\r
+\r
+  @param AcpiSdt          Pointer to Acpi SDT protocol\r
+  @param ParentPkgHandle  ACPI parent package handle\r
+  @param PciAddress       Acpi pci address\r
+  @param INTx             Index of INTx pin\r
+  @param INTxPkgHandle    ACPI INTx package handle\r
+  @param IsAPIC           Tell whether the returned INTx package is for APIC or not\r
+\r
+**/\r
+VOID\r
+SdtGetINTxPkgHandle (\r
+  IN EFI_ACPI_SDT_PROTOCOL  *AcpiSdt,\r
+  IN EFI_ACPI_HANDLE        ParentPkgHandle,\r
+  IN UINT32                 PciAddress,\r
+  IN UINT8                  INTx,\r
+  IN EFI_ACPI_HANDLE        *INTxPkgHandle,\r
+  IN BOOLEAN                *IsAPIC\r
+  )\r
+{\r
+  EFI_ACPI_HANDLE    PreviousHandle;\r
+  EFI_STATUS         Status;\r
+  EFI_ACPI_HANDLE    ChildPkgHandle;\r
+\r
+  ChildPkgHandle = NULL;\r
+  while (TRUE) {\r
+    PreviousHandle = ChildPkgHandle;\r
+    Status = AcpiSdt->GetChild (ParentPkgHandle, &ChildPkgHandle);\r
+    ASSERT_EFI_ERROR (Status);\r
+\r
+    if (PreviousHandle != NULL) {\r
+      Status = AcpiSdt->Close (PreviousHandle);\r
+      ASSERT_EFI_ERROR (Status);\r
+    }\r
+\r
+    if (ChildPkgHandle == NULL) {\r
+      break;\r
+    }\r
+\r
+    if (SdtCheckINTxPkgIsMatch(AcpiSdt, ChildPkgHandle, PciAddress, INTx, IsAPIC)) {\r
+      *INTxPkgHandle = ChildPkgHandle;\r
+      return;\r
+    }\r
+  }\r
+\r
+  return;\r
+}\r
+\r
+/**\r
+  Update the INTx package with the correct pirq value\r
+\r
+  @param AcpiSdt          Pointer to Acpi SDT protocol\r
+  @param INTxPkgHandle    ACPI INTx package handle\r
+  @param PirqValue        Correct pirq value\r
+  @param IsAPIC           Tell whether the INTx package is for APIC or not\r
+\r
+**/\r
+VOID\r
+SdtUpdateINTxPkg (\r
+  IN EFI_ACPI_SDT_PROTOCOL  *AcpiSdt,\r
+  IN EFI_ACPI_HANDLE        INTxPkgHandle,\r
+  IN UINT8                  PirqValue,\r
+  IN BOOLEAN                IsAPIC\r
+  )\r
+{\r
+  EFI_ACPI_HANDLE    PreviousHandle;\r
+  EFI_STATUS         Status;\r
+  EFI_ACPI_HANDLE    MemberHandle;\r
+  EFI_ACPI_DATA_TYPE DataType;\r
+  UINT8              *Data;\r
+  UINTN              DataSize;\r
+  UINT64             TempValue;\r
+  UINTN              ChildSize;\r
+\r
+\r
+  //\r
+  // Check the pci address\r
+  //\r
+  MemberHandle = NULL;\r
+  Status = AcpiSdt->GetChild (INTxPkgHandle, &MemberHandle);\r
+  ASSERT_EFI_ERROR (Status);\r
+  ASSERT (MemberHandle != NULL);\r
+\r
+  //\r
+  // Check the pci interrupt pin\r
+  //\r
+  PreviousHandle = MemberHandle;\r
+  Status = AcpiSdt->GetChild (INTxPkgHandle, &MemberHandle);\r
+  ASSERT_EFI_ERROR (Status);\r
+  ASSERT (MemberHandle != NULL);\r
+\r
+  if (PreviousHandle != NULL) {\r
+    Status = AcpiSdt->Close (PreviousHandle);\r
+    ASSERT_EFI_ERROR (Status);\r
+  }\r
+\r
+  Status = AcpiSdt->GetOption (MemberHandle, 0, &DataType, (CONST VOID **)&Data, &DataSize);\r
+  ASSERT_EFI_ERROR (Status);\r
+  ASSERT (DataType == EFI_ACPI_DATA_TYPE_OPCODE);\r
+\r
+  ChildSize = SdtGetInteger (Data, &TempValue);\r
+\r
+  Status = AcpiSdt->Close (MemberHandle);\r
+  ASSERT_EFI_ERROR (Status);\r
+\r
+  Data += ChildSize;\r
+\r
+  //\r
+  // update the pci interrupt source or source index\r
+  //\r
+  if (!IsAPIC) {\r
+    ChildSize = SdtGetNameStringSize (Data);\r
+    Data += (ChildSize - 1);\r
+\r
+    PirqValue += 0x40;   // change to ascii char\r
+    if (*Data != PirqValue)\r
+      *Data = PirqValue;\r
+  } else {\r
+\r
+    ChildSize = SdtGetInteger (Data, &TempValue);\r
+    Data += ChildSize;\r
+\r
+    Data += 1;\r
+\r
+    if (*Data != PirqValue)\r
+      *Data = PirqValue;\r
+  }\r
+}\r
+\r
+/**\r
+  Check every child package inside this interested parent package for update PRT\r
+\r
+  @param AcpiSdt          Pointer to Acpi SDT protocol\r
+  @param ParentPkgHandle  ACPI parent package handle\r
+  @param PciDeviceInfo    Pointer to PCI_DEVICE_INFO\r
+\r
+**/\r
+VOID\r
+SdtCheckParentPackage (\r
+  IN EFI_ACPI_SDT_PROTOCOL  *AcpiSdt,\r
+  IN EFI_ACPI_HANDLE        ParentPkgHandle,\r
+  IN PCI_DEVICE_INFO        *PciDeviceInfo\r
+  )\r
+{\r
+  EFI_ACPI_HANDLE    INTAPkgHandle;\r
+  EFI_ACPI_HANDLE    INTBPkgHandle;\r
+  EFI_ACPI_HANDLE    INTCPkgHandle;\r
+  EFI_ACPI_HANDLE    INTDPkgHandle;\r
+  UINT32             PciAddress = 0;\r
+  BOOLEAN            IsAllFunctions = FALSE;\r
+  UINT8              IsAPIC = 0;\r
+  EFI_STATUS         Status;\r
+\r
+  INTAPkgHandle = INTBPkgHandle = INTCPkgHandle = INTDPkgHandle = NULL;\r
+\r
+  PciAddress   = SdtConvertToAcpiPciAdress(PciDeviceInfo->DeviceAddress);\r
+\r
+  if ((PciAddress & 0xFFFF) == 0xFFFF) {\r
+    IsAllFunctions = TRUE;\r
+  } else {\r
+    IsAllFunctions = FALSE;\r
+    PciAddress = (PciAddress | 0xFFFF);\r
+  }\r
+\r
+  SdtGetINTxPkgHandle (AcpiSdt, ParentPkgHandle, PciAddress, 0, &INTAPkgHandle, (BOOLEAN *)&IsAPIC);\r
+  SdtGetINTxPkgHandle (AcpiSdt, ParentPkgHandle, PciAddress, 1, &INTBPkgHandle, (BOOLEAN *)&IsAPIC);\r
+  SdtGetINTxPkgHandle (AcpiSdt, ParentPkgHandle, PciAddress, 2, &INTCPkgHandle, (BOOLEAN *)&IsAPIC);\r
+  SdtGetINTxPkgHandle (AcpiSdt, ParentPkgHandle, PciAddress, 3, &INTDPkgHandle, (BOOLEAN *)&IsAPIC);\r
+\r
+  //\r
+  // Check INTA\r
+  //\r
+  if ((PciDeviceInfo->INTA[IsAPIC] != 0xFF) && (INTAPkgHandle != NULL)) {\r
+    //\r
+    // Find INTA package and there is valid INTA update item, update it\r
+    //\r
+    SdtUpdateINTxPkg (AcpiSdt, INTAPkgHandle, (PciDeviceInfo->INTA[IsAPIC]), IsAPIC);\r
+  } else if ((PciDeviceInfo->INTA[IsAPIC] != 0xFF) && (INTAPkgHandle == NULL)) {\r
+    //\r
+    // There is valid INTA update item, but no INA package exist, should add it\r
+    //\r
+    DEBUG ((EFI_D_ERROR, "\n\nShould add INTA item for this device(0x%x)\n\n", PciAddress));\r
+\r
+  } else if ((PciDeviceInfo->INTA[IsAPIC] == 0xFF) && (INTAPkgHandle != NULL) && IsAllFunctions) {\r
+    //\r
+    // For all functions senario, if there is invalid INTA update item, but INTA package does exist, should delete it\r
+    //\r
+    DEBUG ((EFI_D_ERROR, "\n\nShould remove INTA item for this device(0x%x)\n\n", PciAddress));\r
+\r
+  }\r
+\r
+  //\r
+  // Check INTB\r
+  //\r
+  if ((PciDeviceInfo->INTB[IsAPIC] != 0xFF) && (INTBPkgHandle != NULL)) {\r
+    //\r
+    // Find INTB package and there is valid INTB update item, update it\r
+    //\r
+    SdtUpdateINTxPkg (AcpiSdt, INTBPkgHandle, (PciDeviceInfo->INTB[IsAPIC]), IsAPIC);\r
+  } else if ((PciDeviceInfo->INTB[IsAPIC] != 0xFF) && (INTBPkgHandle == NULL)) {\r
+    //\r
+    // There is valid INTB update item, but no INTB package exist, should add it\r
+    //\r
+    DEBUG ((EFI_D_ERROR, "\n\nShould add INTB item for this device(0x%x)\n\n", PciAddress));\r
+\r
+  } else if ((PciDeviceInfo->INTB[IsAPIC] == 0xFF) && (INTBPkgHandle != NULL) && IsAllFunctions) {\r
+    //\r
+    // For all functions senario, if there is invalid INTB update item, but INTB package does exist, should delete it\r
+    //\r
+    DEBUG ((EFI_D_ERROR, "\n\nShould remove INTB item for this device(0x%x)\n\n", PciAddress));\r
+\r
+  }\r
+\r
+  //\r
+  // Check INTC\r
+  //\r
+  if ((PciDeviceInfo->INTC[IsAPIC] != 0xFF) && (INTCPkgHandle != NULL)) {\r
+    //\r
+    // Find INTC package and there is valid INTC update item, update it\r
+    //\r
+    SdtUpdateINTxPkg (AcpiSdt, INTCPkgHandle, (PciDeviceInfo->INTC[IsAPIC]), IsAPIC);\r
+  } else if ((PciDeviceInfo->INTC[IsAPIC] != 0xFF) && (INTCPkgHandle == NULL)) {\r
+    //\r
+    // There is valid INTC update item, but no INTC package exist, should add it\r
+    //\r
+    DEBUG ((EFI_D_ERROR, "\n\nShould add INTC item for this device(0x%x)\n\n", PciAddress));\r
+\r
+  } else if ((PciDeviceInfo->INTC[IsAPIC] == 0xFF) && (INTCPkgHandle != NULL) && IsAllFunctions) {\r
+    //\r
+    // For all functions senario, if there is invalid INTC update item, but INTC package does exist, should delete it\r
+    //\r
+    DEBUG ((EFI_D_ERROR, "\n\nShould remove INTC item for this device(0x%x)\n\n", PciAddress));\r
+  }\r
+\r
+  //\r
+  // Check INTD\r
+  //\r
+  if ((PciDeviceInfo->INTD[IsAPIC] != 0xFF) && (INTDPkgHandle != NULL)) {\r
+    //\r
+    // Find INTD package and there is valid INTD update item, update it\r
+    //\r
+    SdtUpdateINTxPkg (AcpiSdt, INTDPkgHandle, (PciDeviceInfo->INTD[IsAPIC]), IsAPIC);\r
+  } else if ((PciDeviceInfo->INTD[IsAPIC] != 0xFF) && (INTDPkgHandle == NULL)) {\r
+    //\r
+    // There is valid INTD update item, but no INTD package exist, should add it\r
+    //\r
+    DEBUG ((EFI_D_ERROR, "\n\nShould add INTD item for this device(0x%x)\n\n", PciAddress));\r
+\r
+  }  else if ((PciDeviceInfo->INTD[IsAPIC] == 0xFF) && (INTDPkgHandle != NULL) && IsAllFunctions) {\r
+    //\r
+    // For all functions senario, if there is invalid INTD update item, but INTD package does exist, should delete it\r
+    //\r
+    DEBUG ((EFI_D_ERROR, "\n\nShould remove INTD item for this device(0x%x)\n\n", PciAddress));\r
+  }\r
+\r
+\r
+  if (INTAPkgHandle != NULL) {\r
+    Status = AcpiSdt->Close (INTAPkgHandle);\r
+    ASSERT_EFI_ERROR (Status);\r
+  }\r
+\r
+  if (INTBPkgHandle != NULL) {\r
+    Status = AcpiSdt->Close (INTBPkgHandle);\r
+    ASSERT_EFI_ERROR (Status);\r
+  }\r
+\r
+  if (INTCPkgHandle != NULL) {\r
+    Status = AcpiSdt->Close (INTCPkgHandle);\r
+    ASSERT_EFI_ERROR (Status);\r
+  }\r
+\r
+  if (INTDPkgHandle != NULL) {\r
+    Status = AcpiSdt->Close (INTDPkgHandle);\r
+    ASSERT_EFI_ERROR (Status);\r
+  }\r
+\r
+  return;\r
+}\r
+\r
+/**\r
+  Check every return package for update PRT\r
+\r
+  @param AcpiSdt          Pointer to Acpi SDT protocol\r
+  @param ParentHandle     ACPI pci device handle\r
+  @param PciDeviceInfo    Pointer to PCI_DEVICE_INFO\r
+\r
+**/\r
+VOID\r
+SdtCheckReturnPackage (\r
+  IN EFI_ACPI_SDT_PROTOCOL  *AcpiSdt,\r
+  IN EFI_ACPI_HANDLE        MethodHandle,\r
+  IN PCI_DEVICE_INFO        *PciDeviceInfo\r
+  )\r
+{\r
+  EFI_ACPI_HANDLE    PreviousHandle;\r
+  EFI_ACPI_HANDLE    ReturnHandle;\r
+  EFI_ACPI_HANDLE    PackageHandle;\r
+  EFI_ACPI_HANDLE    NamePkgHandle;\r
+  EFI_STATUS         Status;\r
+  EFI_ACPI_DATA_TYPE DataType;\r
+  UINT8              *Data;\r
+  UINTN              DataSize;\r
+  CHAR8              NameStr[128];\r
+\r
+  ReturnHandle = NULL;\r
+  while (TRUE) {\r
+    PreviousHandle = ReturnHandle;\r
+    Status = AcpiSdt->GetChild (MethodHandle, &ReturnHandle);\r
+    ASSERT_EFI_ERROR (Status);\r
+\r
+    if (PreviousHandle != NULL) {\r
+      Status = AcpiSdt->Close (PreviousHandle);\r
+      ASSERT_EFI_ERROR (Status);\r
+    }\r
+\r
+    if (ReturnHandle == NULL) {\r
+      break;\r
+    }\r
+\r
+    Status = AcpiSdt->GetOption (ReturnHandle, 0, &DataType, (CONST VOID **)&Data, &DataSize);\r
+    ASSERT_EFI_ERROR (Status);\r
+    ASSERT (DataType == EFI_ACPI_DATA_TYPE_OPCODE);\r
+\r
+    if (*Data == AML_RETURN_OP) {\r
+      //\r
+      // Find the return method handle, then look for the returned package data\r
+      //\r
+      Status = AcpiSdt->GetOption (ReturnHandle, 1, &DataType, (CONST VOID **)&Data, &DataSize);\r
+      ASSERT_EFI_ERROR (Status);\r
+\r
+\r
+      if (DataType == EFI_ACPI_DATA_TYPE_NAME_STRING) {\r
+        ZeroMem (NameStr, 128);\r
+        AsciiStrCpy (NameStr, "\\_SB.");\r
+        DataSize = SdtGetNameStringSize (Data);\r
+        AsciiStrnCat (NameStr, (CHAR8 *)Data, DataSize);\r
+\r
+        NamePkgHandle = NULL;\r
+        Status = AcpiSdt->FindPath (mDsdtHandle, NameStr, &NamePkgHandle);\r
+        ASSERT_EFI_ERROR (Status);\r
+        ASSERT (NamePkgHandle != NULL);\r
+\r
+        Status = AcpiSdt->GetOption (NamePkgHandle, 0, &DataType, (CONST VOID **)&Data, &DataSize);\r
+        ASSERT_EFI_ERROR (Status);\r
+        ASSERT (DataType == EFI_ACPI_DATA_TYPE_OPCODE);\r
+        ASSERT (*Data == AML_NAME_OP);\r
+\r
+        Status = AcpiSdt->GetOption (NamePkgHandle, 2, &DataType, (CONST VOID **)&Data, &DataSize);\r
+        ASSERT_EFI_ERROR (Status);\r
+        ASSERT (DataType == EFI_ACPI_DATA_TYPE_CHILD);\r
+      }\r
+\r
+      ASSERT (DataType == EFI_ACPI_DATA_TYPE_CHILD);\r
+\r
+      //\r
+      // Get the parent package handle\r
+      //\r
+      PackageHandle = NULL;\r
+      Status = AcpiSdt->Open (Data, &PackageHandle);\r
+      ASSERT_EFI_ERROR (Status);\r
+\r
+      //\r
+      // Check the parent package for update pci routing\r
+      //\r
+      SdtCheckParentPackage (AcpiSdt, PackageHandle, PciDeviceInfo);\r
+\r
+      Status = AcpiSdt->Close (PackageHandle);\r
+      ASSERT_EFI_ERROR (Status);\r
+\r
+      Status = AcpiSdt->Close (ReturnHandle);\r
+      ASSERT_EFI_ERROR (Status);\r
+\r
+      break;\r
+    }\r
+\r
+    //\r
+    // Not ReturnOp, search it as parent\r
+    //\r
+    SdtCheckReturnPackage (AcpiSdt, ReturnHandle, PciDeviceInfo);\r
+  }\r
+\r
+  //\r
+  // Done\r
+  //\r
+  return;\r
+\r
+}\r
+\r
+/**\r
+  update interrupt info inside the PRT method for the given pci device handle\r
+\r
+  @param AcpiSdt       Pointer to Acpi SDT protocol\r
+  @param PciHandle     ACPI pci device handle\r
+  @param PciDeviceInfo Pointer to PCI_DEVICE_INFO\r
+\r
+**/\r
+EFI_STATUS\r
+SdtUpdatePrtMethod (\r
+  IN EFI_ACPI_SDT_PROTOCOL  *AcpiSdt,\r
+  IN EFI_ACPI_HANDLE        PciHandle,\r
+  IN PCI_DEVICE_INFO        *PciDeviceInfo\r
+  )\r
+{\r
+  EFI_STATUS         Status;\r
+  EFI_ACPI_HANDLE    PrtMethodHandle;\r
+\r
+  //\r
+  // Find the PRT method under this pci device\r
+  //\r
+  PrtMethodHandle = NULL;\r
+  Status = AcpiSdt->FindPath (PciHandle, "_PRT", &PrtMethodHandle);\r
+\r
+  if (EFI_ERROR (Status)) {\r
+    return EFI_INVALID_PARAMETER;\r
+  }\r
+\r
+  if (PrtMethodHandle == NULL) {\r
+    return EFI_INVALID_PARAMETER;\r
+  }\r
+\r
+  SdtCheckReturnPackage(AcpiSdt, PrtMethodHandle, PciDeviceInfo);\r
+\r
+  Status = AcpiSdt->Close (PrtMethodHandle);\r
+  ASSERT_EFI_ERROR (Status);\r
+\r
+  return Status;\r
+}\r
+\r
+\r
+/**\r
+  Update the package inside name op with correct wakeup resources\r
+\r
+  @param AcpiSdt          Pointer to Acpi SDT protocol\r
+  @param InPkgHandle      ACPI inside package handle\r
+  @param GPEPin           Correct gpe pin\r
+  @param SxNum            Correct system state the device can wake up from\r
+\r
+**/\r
+VOID\r
+SdtUpdatePackageInName (\r
+  IN EFI_ACPI_SDT_PROTOCOL  *AcpiSdt,\r
+  IN EFI_ACPI_HANDLE        INTxPkgHandle,\r
+  IN UINT8                  GPEPin,\r
+  IN UINT8                  SxNum\r
+  )\r
+{\r
+  EFI_ACPI_HANDLE    PreviousHandle;\r
+  EFI_STATUS         Status;\r
+  EFI_ACPI_HANDLE    MemberHandle;\r
+  EFI_ACPI_DATA_TYPE DataType;\r
+  UINT8              *Data;\r
+  UINTN              DataSize;\r
+\r
+  //\r
+  // Check the gpe pin\r
+  //\r
+  MemberHandle = NULL;\r
+  Status = AcpiSdt->GetChild (INTxPkgHandle, &MemberHandle);\r
+  ASSERT_EFI_ERROR (Status);\r
+  ASSERT (MemberHandle != NULL);\r
+\r
+  Status = AcpiSdt->GetOption (MemberHandle, 0, &DataType, (CONST VOID **)&Data, &DataSize);\r
+  ASSERT_EFI_ERROR (Status);\r
+  ASSERT (DataType == EFI_ACPI_DATA_TYPE_OPCODE);\r
+\r
+  //\r
+  // Skip byte prefix\r
+  //\r
+  Data += 1;\r
+\r
+  if (*Data != GPEPin) {\r
+\r
+    *Data = GPEPin;\r
+  }\r
+\r
+  //\r
+  // Check the sx number\r
+  //\r
+  PreviousHandle = MemberHandle;\r
+  Status = AcpiSdt->GetChild (INTxPkgHandle, &MemberHandle);\r
+  ASSERT_EFI_ERROR (Status);\r
+  ASSERT (MemberHandle != NULL);\r
+\r
+  if (PreviousHandle != NULL) {\r
+    Status = AcpiSdt->Close (PreviousHandle);\r
+    ASSERT_EFI_ERROR (Status);\r
+  }\r
+\r
+  Status = AcpiSdt->GetOption (MemberHandle, 0, &DataType, (CONST VOID **)&Data, &DataSize);\r
+  ASSERT_EFI_ERROR (Status);\r
+  ASSERT (DataType == EFI_ACPI_DATA_TYPE_OPCODE);\r
+\r
+  //\r
+  // Skip byte prefix\r
+  //\r
+  Data += 1;\r
+\r
+  if (*Data != SxNum) {\r
+\r
+    *Data = SxNum;\r
+  }\r
+\r
+  Status = AcpiSdt->Close (MemberHandle);\r
+  ASSERT_EFI_ERROR (Status);\r
+\r
+}\r
+\r
+/**\r
+  Check the name package belonged to PRW\r
+\r
+  @param AcpiSdt          Pointer to Acpi SDT protocol\r
+  @param PrwPkgHandle     ACPI PRW package handle\r
+  @param PciDeviceInfo    Pointer to PCI_DEVICE_INFO\r
+\r
+**/\r
+VOID\r
+SdtCheckNamePackage (\r
+  IN EFI_ACPI_SDT_PROTOCOL  *AcpiSdt,\r
+  IN EFI_ACPI_HANDLE        PrwPkgHandle,\r
+  IN PCI_DEVICE_INFO        *PciDeviceInfo\r
+  )\r
+{\r
+  EFI_ACPI_HANDLE    InPkgHandle;\r
+  EFI_STATUS         Status;\r
+  EFI_ACPI_DATA_TYPE DataType;\r
+  UINT8              *Data;\r
+  UINTN              DataSize;\r
+\r
+  Status = AcpiSdt->GetOption (PrwPkgHandle, 0, &DataType, (CONST VOID **)&Data, &DataSize);\r
+  ASSERT_EFI_ERROR (Status);\r
+  ASSERT (DataType == EFI_ACPI_DATA_TYPE_OPCODE);\r
+  ASSERT (*Data == AML_NAME_OP);\r
+\r
+  Status = AcpiSdt->GetOption (PrwPkgHandle, 2, &DataType, (CONST VOID **)&Data, &DataSize);\r
+  ASSERT_EFI_ERROR (Status);\r
+  ASSERT (DataType == EFI_ACPI_DATA_TYPE_CHILD);\r
+\r
+  //\r
+  // Get the inside package handle\r
+  //\r
+  InPkgHandle = NULL;\r
+  Status = AcpiSdt->Open (Data, &InPkgHandle);\r
+  ASSERT_EFI_ERROR (Status);\r
+\r
+  //\r
+  // update the package in name op for wakeup info\r
+  //\r
+  if ((PciDeviceInfo->GPEPin != 0xFF) && (PciDeviceInfo->SxNum != 0xFF))\r
+    SdtUpdatePackageInName (AcpiSdt, InPkgHandle, PciDeviceInfo->GPEPin, PciDeviceInfo->SxNum);\r
+\r
+  Status = AcpiSdt->Close (InPkgHandle);\r
+  ASSERT_EFI_ERROR (Status);\r
+\r
+  return;\r
+\r
+}\r
+\r
+/**\r
+  update wakeup info inside the PRW method for the given pci device handle\r
+\r
+  @param AcpiSdt       Pointer to Acpi SDT protocol\r
+  @param PciHandle     ACPI pci device handle\r
+  @param PciDeviceInfo Pointer to PCI_DEVICE_INFO\r
+\r
+**/\r
+EFI_STATUS\r
+SdtUpdatePrwPackage (\r
+  IN EFI_ACPI_SDT_PROTOCOL  *AcpiSdt,\r
+  IN EFI_ACPI_HANDLE        PciHandle,\r
+  IN PCI_DEVICE_INFO        *PciDeviceInfo\r
+  )\r
+{\r
+  EFI_STATUS         Status;\r
+  EFI_ACPI_HANDLE    PrwPkgHandle;\r
+\r
+  //\r
+  // Find the PRT method under this pci device\r
+  //\r
+  PrwPkgHandle = NULL;\r
+  Status = AcpiSdt->FindPath (PciHandle, "_PRW", &PrwPkgHandle);\r
+\r
+  if (EFI_ERROR (Status)) {\r
+    return EFI_INVALID_PARAMETER;\r
+  }\r
+\r
+  if (PrwPkgHandle == NULL) {\r
+    return EFI_INVALID_PARAMETER;\r
+  }\r
+\r
+  SdtCheckNamePackage(AcpiSdt, PrwPkgHandle, PciDeviceInfo);\r
+\r
+  Status = AcpiSdt->Close (PrwPkgHandle);\r
+  ASSERT_EFI_ERROR (Status);\r
+\r
+  return Status;\r
+}\r
+\r
+/**\r
+  update pci routing information in acpi table based on pcd settings\r
+\r
+  @param AcpiSdt          Pointer to Acpi SDT protocol\r
+  @param PciRootHandle       ACPI root bridge handle\r
+  @param PciDeviceInfo    Pointer to PCI_DEVICE_INFO\r
+\r
+**/\r
+EFI_STATUS\r
+SdtUpdatePciRouting (\r
+  IN EFI_ACPI_SDT_PROTOCOL  *AcpiSdt,\r
+  IN EFI_ACPI_HANDLE        PciRootHandle,\r
+  IN PCI_DEVICE_INFO        *PciDeviceInfo\r
+  )\r
+{\r
+  EFI_STATUS         Status;\r
+  EFI_ACPI_HANDLE    PciBridgeHandle;\r
+  UINT32             PciAddress;\r
+\r
+\r
+  PciBridgeHandle = NULL;\r
+  if (PciDeviceInfo->BridgeAddress == 0x00000000) {\r
+    //\r
+    // Its bridge is the host root bridge\r
+    //\r
+    PciBridgeHandle = PciRootHandle;\r
+\r
+  } else {\r
+\r
+    //\r
+    // Its bridge is just a pci device under the host bridge\r
+    //\r
+\r
+    //\r
+    // Conver the bridge address into one that acpi table can recognize\r
+    //\r
+    PciAddress = SdtConvertToAcpiPciAdress (PciDeviceInfo->BridgeAddress);\r
+\r
+    //\r
+    // Scan the whole table to find the pci device\r
+    //\r
+    PciBridgeHandle = SdtGetHandleByScanAllChilds(AcpiSdt, PciRootHandle, SdtFindPciDeviceHandle, &PciAddress);\r
+    if (PciBridgeHandle == NULL) {\r
+\r
+      return EFI_INVALID_PARAMETER;\r
+    }\r
+  }\r
+\r
+  Status = SdtUpdatePrtMethod(AcpiSdt, PciBridgeHandle, PciDeviceInfo);\r
+\r
+  if (PciDeviceInfo->BridgeAddress != 0x00000000) {\r
+    Status = AcpiSdt->Close (PciBridgeHandle);\r
+    ASSERT_EFI_ERROR (Status);\r
+  }\r
+\r
+  return Status;\r
+}\r
+\r
+\r
+/**\r
+  update power resource wake up information in acpi table based on pcd settings\r
+\r
+  @param AcpiSdt          Pointer to Acpi SDT protocol\r
+  @param PciRootHandle    ACPI root bridge handle\r
+  @param PciDeviceInfo    Pointer to PCI_DEVICE_INFO\r
+\r
+**/\r
+EFI_STATUS\r
+SdtUpdatePowerWake (\r
+  IN EFI_ACPI_SDT_PROTOCOL  *AcpiSdt,\r
+  IN EFI_ACPI_HANDLE        PciRootHandle,\r
+  IN PCI_DEVICE_INFO        *PciDeviceInfo\r
+  )\r
+{\r
+  EFI_STATUS         Status;\r
+  EFI_ACPI_HANDLE    PciBridgeHandle;\r
+  EFI_ACPI_HANDLE    PciDeviceHandle;\r
+  UINT32             PciAddress;\r
+\r
+  PciBridgeHandle = NULL;\r
+  if (PciDeviceInfo->BridgeAddress == 0x00000000) {\r
+    //\r
+    // Its bridge is the host root bridge\r
+    //\r
+    PciBridgeHandle = PciRootHandle;\r
+\r
+  } else {\r
+\r
+    //\r
+    // Its bridge is just a pci device under the host bridge\r
+    //\r
+\r
+    //\r
+    // Conver the bridge address into one that acpi table can recognize\r
+    //\r
+    PciAddress = SdtConvertToAcpiPciAdress (PciDeviceInfo->BridgeAddress);\r
+\r
+    //\r
+    // Scan the whole table to find the pci device\r
+    //\r
+    PciBridgeHandle = SdtGetHandleByScanAllChilds(AcpiSdt, PciRootHandle, SdtFindPciDeviceHandle, &PciAddress);\r
+\r
+    if (PciBridgeHandle == NULL) {\r
+\r
+      Status = AcpiSdt->Close (PciRootHandle);\r
+      ASSERT_EFI_ERROR (Status);\r
+\r
+      return EFI_INVALID_PARAMETER;\r
+    }\r
+  }\r
+\r
+  PciDeviceHandle = NULL;\r
+\r
+  //\r
+  // Conver the device address into one that acpi table can recognize\r
+  //\r
+  PciAddress = SdtConvertToAcpiPciAdress (PciDeviceInfo->DeviceAddress);\r
+\r
+  //\r
+  // Scan the whole table to find the pci device\r
+  //\r
+  PciDeviceHandle = SdtGetHandleByScanAllChilds(AcpiSdt, PciBridgeHandle, SdtFindPciDeviceHandle, &PciAddress);\r
+\r
+  if (PciDeviceHandle == NULL) {\r
+    if (PciDeviceInfo->BridgeAddress != 0x00000000) {\r
+      Status = AcpiSdt->Close (PciBridgeHandle);\r
+      ASSERT_EFI_ERROR (Status);\r
+    }\r
+\r
+    return EFI_INVALID_PARAMETER;\r
+  }\r
+\r
+  Status = SdtUpdatePrwPackage(AcpiSdt, PciDeviceHandle, PciDeviceInfo);\r
+\r
+  Status = AcpiSdt->Close (PciDeviceHandle);\r
+  ASSERT_EFI_ERROR (Status);\r
+\r
+  if (PciDeviceInfo->BridgeAddress != 0x00000000) {\r
+    Status = AcpiSdt->Close (PciBridgeHandle);\r
+    ASSERT_EFI_ERROR (Status);\r
+  }\r
+\r
+  return Status;\r
+}\r
+\r
+\r
+/**\r
+  Get the root bridge handle by scanning the acpi table\r
+\r
+  @param AcpiSdt          Pointer to Acpi SDT protocol\r
+  @param DsdtHandle       ACPI root handle\r
+\r
+  @retval EFI_ACPI_HANDLE the handle of the root bridge\r
+**/\r
+EFI_ACPI_HANDLE\r
+SdtGetRootBridgeHandle (\r
+  IN EFI_ACPI_SDT_PROTOCOL  *AcpiSdt,\r
+  IN EFI_ACPI_HANDLE        DsdtHandle\r
+  )\r
+{\r
+  EFI_ACPI_HANDLE    PciRootHandle;\r
+\r
+  //\r
+  // Scan the whole table to find the root bridge\r
+  //\r
+  PciRootHandle = NULL;\r
+  PciRootHandle = SdtGetHandleByScanAllChilds(AcpiSdt, DsdtHandle, SdtFindRootBridgeHandle, NULL);\r
+  ASSERT (PciRootHandle != NULL);\r
+\r
+  return PciRootHandle;\r
+}\r
+\r
+\r
+/**\r
+  Check input Pci device info is changed from the default values\r
+  @param PciDeviceInfo    Pointer to PCI_DEVICE_INFO\r
+  @param UpdatePRT        Pointer to BOOLEAN\r
+  @param UpdatePRW        Pointer to BOOLEAN\r
+\r
+**/\r
+VOID\r
+SdtCheckPciDeviceInfoChanged (\r
+  IN PCI_DEVICE_INFO        *PciDeviceInfo,\r
+  IN BOOLEAN                *UpdatePRT,\r
+  IN BOOLEAN                *UpdatePRW\r
+  )\r
+{\r
+  UINTN Index = 0;\r
+\r
+  if (mQNCPciInfo == NULL) {\r
+    *UpdatePRT = FALSE;\r
+    *UpdatePRW = FALSE;\r
+    return;\r
+  }\r
+\r
+  *UpdatePRT = TRUE;\r
+  *UpdatePRW = TRUE;\r
+\r
+  for (Index = 0;Index < CURRENT_PCI_DEVICE_NUM; Index++) {\r
+    if ((mQNCPciInfo[Index].BridgeAddress == PciDeviceInfo->BridgeAddress)\r
+      && (mQNCPciInfo[Index].DeviceAddress == PciDeviceInfo->DeviceAddress)) {\r
+      //\r
+      // Find one matched entry\r
+      //\r
+      if (CompareMem (&(mQNCPciInfo[Index].INTA[0]), &PciDeviceInfo->INTA[0], 10) == 0) {\r
+        *UpdatePRT = FALSE;\r
+        *UpdatePRW = FALSE;\r
+        //DEBUG ((EFI_D_ERROR, "Find one matched entry[%d] and no change\n", Index));\r
+      } else {\r
+        if (CompareMem (&(mQNCPciInfo[Index].INTA[0]), &PciDeviceInfo->INTA[0], 8) == 0)\r
+          *UpdatePRT = FALSE;\r
+\r
+        if (CompareMem (&(mQNCPciInfo[Index].GPEPin), &PciDeviceInfo->GPEPin, 2) == 0)\r
+          *UpdatePRW = FALSE;\r
+\r
+        if (*(UINT64 *)(&PciDeviceInfo->INTA[0]) == 0xFFFFFFFFFFFFFFFFULL)\r
+          *UpdatePRT = FALSE;\r
+\r
+        if (*(UINT16 *)(&PciDeviceInfo->GPEPin) == 0xFFFF)\r
+          *UpdatePRW = FALSE;\r
+\r
+        //DEBUG ((EFI_D_ERROR, "Find one matched entry[%d] and but need update PRT:0x%x PRW:0x%x\n", Index, *UpdatePRT, *UpdatePRW));\r
+      }\r
+      break;\r
+    }\r
+  }\r
+\r
+  //if (Index == 42) {\r
+  //  DEBUG ((EFI_D_ERROR, "Find No matched entry\n"));\r
+  //}\r
+\r
+  return;\r
+}\r
diff --git a/QuarkPlatformPkg/Acpi/Dxe/AcpiPlatform/AcpiPciUpdate.h b/QuarkPlatformPkg/Acpi/Dxe/AcpiPlatform/AcpiPciUpdate.h
new file mode 100644 (file)
index 0000000..0e4caff
--- /dev/null
@@ -0,0 +1,322 @@
+/** @file\r
+Update the _PRT and _PRW method for pci devices\r
+\r
+Copyright (c) 2013-2015 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution.  The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+**/\r
+#ifndef _ACPI_PCI_UPDATE_H_\r
+#define _ACPI_PCI_UPDATE_H_\r
+\r
+\r
+//\r
+// Primary OpCode\r
+//\r
+#define AML_ZERO_OP                  0x00\r
+#define AML_ONE_OP                   0x01\r
+#define AML_ALIAS_OP                 0x06\r
+#define AML_NAME_OP                  0x08\r
+#define AML_BYTE_PREFIX              0x0a\r
+#define AML_WORD_PREFIX              0x0b\r
+#define AML_DWORD_PREFIX             0x0c\r
+#define AML_STRING_PREFIX            0x0d\r
+#define AML_QWORD_PREFIX             0x0e\r
+#define AML_SCOPE_OP                 0x10\r
+#define AML_BUFFER_OP                0x11\r
+#define AML_PACKAGE_OP               0x12\r
+#define AML_VAR_PACKAGE_OP           0x13\r
+#define AML_METHOD_OP                0x14\r
+#define AML_DUAL_NAME_PREFIX         0x2e\r
+#define AML_MULTI_NAME_PREFIX        0x2f\r
+#define AML_NAME_CHAR_A              0x41\r
+#define AML_NAME_CHAR_B              0x42\r
+#define AML_NAME_CHAR_C              0x43\r
+#define AML_NAME_CHAR_D              0x44\r
+#define AML_NAME_CHAR_E              0x45\r
+#define AML_NAME_CHAR_F              0x46\r
+#define AML_NAME_CHAR_G              0x47\r
+#define AML_NAME_CHAR_H              0x48\r
+#define AML_NAME_CHAR_I              0x49\r
+#define AML_NAME_CHAR_J              0x4a\r
+#define AML_NAME_CHAR_K              0x4b\r
+#define AML_NAME_CHAR_L              0x4c\r
+#define AML_NAME_CHAR_M              0x4d\r
+#define AML_NAME_CHAR_N              0x4e\r
+#define AML_NAME_CHAR_O              0x4f\r
+#define AML_NAME_CHAR_P              0x50\r
+#define AML_NAME_CHAR_Q              0x51\r
+#define AML_NAME_CHAR_R              0x52\r
+#define AML_NAME_CHAR_S              0x53\r
+#define AML_NAME_CHAR_T              0x54\r
+#define AML_NAME_CHAR_U              0x55\r
+#define AML_NAME_CHAR_V              0x56\r
+#define AML_NAME_CHAR_W              0x57\r
+#define AML_NAME_CHAR_X              0x58\r
+#define AML_NAME_CHAR_Y              0x59\r
+#define AML_NAME_CHAR_Z              0x5a\r
+#define AML_ROOT_CHAR                0x5c\r
+#define AML_PARENT_PREFIX_CHAR       0x5e\r
+#define AML_NAME_CHAR__              0x5f\r
+#define AML_LOCAL0                   0x60\r
+#define AML_LOCAL1                   0x61\r
+#define AML_LOCAL2                   0x62\r
+#define AML_LOCAL3                   0x63\r
+#define AML_LOCAL4                   0x64\r
+#define AML_LOCAL5                   0x65\r
+#define AML_LOCAL6                   0x66\r
+#define AML_LOCAL7                   0x67\r
+#define AML_ARG0                     0x68\r
+#define AML_ARG1                     0x69\r
+#define AML_ARG2                     0x6a\r
+#define AML_ARG3                     0x6b\r
+#define AML_ARG4                     0x6c\r
+#define AML_ARG5                     0x6d\r
+#define AML_ARG6                     0x6e\r
+#define AML_STORE_OP                 0x70\r
+#define AML_REF_OF_OP                0x71\r
+#define AML_ADD_OP                   0x72\r
+#define AML_CONCAT_OP                0x73\r
+#define AML_SUBTRACT_OP              0x74\r
+#define AML_INCREMENT_OP             0x75\r
+#define AML_DECREMENT_OP             0x76\r
+#define AML_MULTIPLY_OP              0x77\r
+#define AML_DIVIDE_OP                0x78\r
+#define AML_SHIFT_LEFT_OP            0x79\r
+#define AML_SHIFT_RIGHT_OP           0x7a\r
+#define AML_AND_OP                   0x7b\r
+#define AML_NAND_OP                  0x7c\r
+#define AML_OR_OP                    0x7d\r
+#define AML_NOR_OP                   0x7e\r
+#define AML_XOR_OP                   0x7f\r
+#define AML_NOT_OP                   0x80\r
+#define AML_FIND_SET_LEFT_BIT_OP     0x81\r
+#define AML_FIND_SET_RIGHT_BIT_OP    0x82\r
+#define AML_DEREF_OF_OP              0x83\r
+#define AML_CONCAT_RES_OP            0x84\r
+#define AML_MOD_OP                   0x85\r
+#define AML_NOTIFY_OP                0x86\r
+#define AML_SIZE_OF_OP               0x87\r
+#define AML_INDEX_OP                 0x88\r
+#define AML_MATCH_OP                 0x89\r
+#define AML_CREATE_DWORD_FIELD_OP    0x8a\r
+#define AML_CREATE_WORD_FIELD_OP     0x8b\r
+#define AML_CREATE_BYTE_FIELD_OP     0x8c\r
+#define AML_CREATE_BIT_FIELD_OP      0x8d\r
+#define AML_OBJECT_TYPE_OP           0x8e\r
+#define AML_CREATE_QWORD_FIELD_OP    0x8f\r
+#define AML_LAND_OP                  0x90\r
+#define AML_LOR_OP                   0x91\r
+#define AML_LNOT_OP                  0x92\r
+#define AML_LEQUAL_OP                0x93\r
+#define AML_LGREATER_OP              0x94\r
+#define AML_LLESS_OP                 0x95\r
+#define AML_TO_BUFFER_OP             0x96\r
+#define AML_TO_DEC_STRING_OP         0x97\r
+#define AML_TO_HEX_STRING_OP         0x98\r
+#define AML_TO_INTEGER_OP            0x99\r
+#define AML_TO_STRING_OP             0x9c\r
+#define AML_COPY_OBJECT_OP           0x9d\r
+#define AML_MID_OP                   0x9e\r
+#define AML_CONTINUE_OP              0x9f\r
+#define AML_IF_OP                    0xa0\r
+#define AML_ELSE_OP                  0xa1\r
+#define AML_WHILE_OP                 0xa2\r
+#define AML_NOOP_OP                  0xa3\r
+#define AML_RETURN_OP                0xa4\r
+#define AML_BREAK_OP                 0xa5\r
+#define AML_BREAK_POINT_OP           0xcc\r
+#define AML_ONES_OP                  0xff\r
+\r
+//\r
+// Extended OpCode\r
+//\r
+#define AML_EXT_OP                   0x5b\r
+\r
+#define AML_EXT_MUTEX_OP             0x01\r
+#define AML_EXT_EVENT_OP             0x02\r
+#define AML_EXT_COND_REF_OF_OP       0x12\r
+#define AML_EXT_CREATE_FIELD_OP      0x13\r
+#define AML_EXT_LOAD_TABLE_OP        0x1f\r
+#define AML_EXT_LOAD_OP              0x20\r
+#define AML_EXT_STALL_OP             0x21\r
+#define AML_EXT_SLEEP_OP             0x22\r
+#define AML_EXT_ACQUIRE_OP           0x23\r
+#define AML_EXT_SIGNAL_OP            0x24\r
+#define AML_EXT_WAIT_OP              0x25\r
+#define AML_EXT_RESET_OP             0x26\r
+#define AML_EXT_RELEASE_OP           0x27\r
+#define AML_EXT_FROM_BCD_OP          0x28\r
+#define AML_EXT_TO_BCD_OP            0x29\r
+#define AML_EXT_UNLOAD_OP            0x2a\r
+#define AML_EXT_REVISION_OP          0x30\r
+#define AML_EXT_DEBUG_OP             0x31\r
+#define AML_EXT_FATAL_OP             0x32\r
+#define AML_EXT_TIMER_OP             0x33\r
+#define AML_EXT_REGION_OP            0x80\r
+#define AML_EXT_FIELD_OP             0x81\r
+#define AML_EXT_DEVICE_OP            0x82\r
+#define AML_EXT_PROCESSOR_OP         0x83\r
+#define AML_EXT_POWER_RES_OP         0x84\r
+#define AML_EXT_THERMAL_ZONE_OP      0x85\r
+#define AML_EXT_INDEX_FIELD_OP       0x86\r
+#define AML_EXT_BANK_FIELD_OP        0x87\r
+#define AML_EXT_DATA_REGION_OP       0x88\r
+\r
+#pragma pack(1)\r
+\r
+typedef struct {\r
+  UINT32    BridgeAddress;\r
+  UINT32    DeviceAddress;\r
+  UINT8     INTA[2];    // the first member record the 8259 link, the second member record the io apic irq number\r
+  UINT8     INTB[2];\r
+  UINT8     INTC[2];\r
+  UINT8     INTD[2];\r
+\r
+  UINT8     GPEPin;\r
+  UINT8     SxNum;\r
+} PCI_DEVICE_INFO;\r
+\r
+#pragma pack()\r
+\r
+#define PCI_DEVICE_INFO_MAX_NUM  50\r
+#define CURRENT_PCI_DEVICE_NUM   13\r
+\r
+#define  PIRQ_LINKA       1\r
+#define  PIRQ_LINKB       2\r
+#define  PIRQ_LINKC       3\r
+#define  PIRQ_LINKD       4\r
+#define  PIRQ_LINKE       5\r
+#define  PIRQ_LINKF       6\r
+#define  PIRQ_LINKG       7\r
+#define  PIRQ_LINKH       8\r
+#define  PIRQ_INVALID  0xFF\r
+\r
+typedef struct _PCI_DEVICE_SETTING{\r
+  UINT8    PciDeviceInfoNumber;\r
+  PCI_DEVICE_INFO PciDeviceInfo[PCI_DEVICE_INFO_MAX_NUM];\r
+}PCI_DEVICE_SETTING;\r
+\r
+typedef struct _AML_BYTE_ENCODING AML_BYTE_ENCODING;\r
+\r
+//\r
+// AML Handle Entry definition.\r
+//\r
+//  Signature must be set to EFI_AML_HANDLE_SIGNATURE or EFI_AML_ROOT_HANDLE_SIGNATURE\r
+//  Buffer is the ACPI node buffer pointer, the first/second bytes are opcode.\r
+//         This buffer should not be freed.\r
+//  Size is the total size of this ACPI node buffer.\r
+//\r
+typedef struct {\r
+  UINT32                  Signature;\r
+  UINT8                   *Buffer;\r
+  UINTN                   Size;\r
+  AML_BYTE_ENCODING       *AmlByteEncoding;\r
+  BOOLEAN                 Modified;\r
+} EFI_AML_HANDLE;\r
+\r
+typedef UINT32 AML_OP_PARSE_INDEX;\r
+\r
+typedef UINT32 AML_OP_PARSE_FORMAT;\r
+\r
+typedef UINT32 AML_OP_ATTRIBUTE;\r
+\r
+struct _AML_BYTE_ENCODING {\r
+  UINT8                      OpCode;\r
+  UINT8                      SubOpCode;\r
+  AML_OP_PARSE_INDEX         MaxIndex;\r
+  AML_OP_PARSE_FORMAT        Format[6];\r
+  AML_OP_ATTRIBUTE           Attribute;\r
+};\r
+\r
+\r
+//\r
+// Check device info fucntion prototype\r
+//\r
+typedef\r
+BOOLEAN\r
+(* CHECK_HANDLE_INFO) (\r
+  IN EFI_ACPI_SDT_PROTOCOL  *AcpiSdt,\r
+  IN EFI_ACPI_HANDLE        CheckHandle,\r
+  IN VOID                   *Context\r
+  );\r
+\r
+extern EFI_ACPI_HANDLE mDsdtHandle;\r
+extern EFI_ACPI_SDT_PROTOCOL *mAcpiSdt;\r
+\r
+/**\r
+  Init Pci Device Structure\r
+\r
+  @param mConfigData    - Pointer of Pci Device information Structure\r
+\r
+**/\r
+VOID\r
+InitPciDeviceInfoStructure (\r
+  PCI_DEVICE_SETTING            *mConfigData\r
+  );\r
+/**\r
+  update pci routing information in acpi table based on pcd settings\r
+\r
+  @param AcpiSdt          Pointer to Acpi SDT protocol\r
+  @param DsdtHandle       ACPI root handle\r
+  @param PciDeviceInfo    Pointer to PCI_DEVICE_INFO\r
+\r
+**/\r
+EFI_STATUS\r
+SdtUpdatePciRouting (\r
+  IN EFI_ACPI_SDT_PROTOCOL  *AcpiSdt,\r
+  IN EFI_ACPI_HANDLE        DsdtHandle,\r
+  IN PCI_DEVICE_INFO        *PciDeviceInfo\r
+  );\r
+\r
+\r
+/**\r
+  update power resource wake up information in acpi table based on pcd settings\r
+\r
+  @param AcpiSdt          Pointer to Acpi SDT protocol\r
+  @param DsdtHandle       ACPI root handle\r
+  @param PciDeviceInfo    Pointer to PCI_DEVICE_INFO\r
+\r
+**/\r
+EFI_STATUS\r
+SdtUpdatePowerWake (\r
+  IN EFI_ACPI_SDT_PROTOCOL  *AcpiSdt,\r
+  IN EFI_ACPI_HANDLE        DsdtHandle,\r
+  IN PCI_DEVICE_INFO        *PciDeviceInfo\r
+  );\r
+\r
+/**\r
+  Get the root bridge handle by scanning the acpi table\r
+\r
+  @param AcpiSdt          Pointer to Acpi SDT protocol\r
+  @param DsdtHandle       ACPI root handle\r
+\r
+  @retval EFI_ACPI_HANDLE the handle of the root bridge\r
+**/\r
+EFI_ACPI_HANDLE\r
+SdtGetRootBridgeHandle (\r
+  IN EFI_ACPI_SDT_PROTOCOL  *AcpiSdt,\r
+  IN EFI_ACPI_HANDLE        DsdtHandle\r
+  );\r
+\r
+/**\r
+  Check input Pci device info is changed from the default values\r
+  @param PciDeviceInfo    Pointer to PCI_DEVICE_INFO\r
+  @param UpdatePRT        Pointer to BOOLEAN\r
+  @param UpdatePRW        Pointer to BOOLEAN\r
+\r
+**/\r
+VOID\r
+SdtCheckPciDeviceInfoChanged (\r
+  IN PCI_DEVICE_INFO        *PciDeviceInfo,\r
+  IN BOOLEAN                *UpdatePRT,\r
+  IN BOOLEAN                *UpdatePRW\r
+  );\r
+#endif\r
diff --git a/QuarkPlatformPkg/Acpi/Dxe/AcpiPlatform/AcpiPlatform.c b/QuarkPlatformPkg/Acpi/Dxe/AcpiPlatform/AcpiPlatform.c
new file mode 100644 (file)
index 0000000..aa18cae
--- /dev/null
@@ -0,0 +1,815 @@
+/** @file\r
+ACPI Platform Driver\r
+\r
+Copyright (c) 2013-2015 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution.  The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#include <Protocol/AcpiTable.h>\r
+#include <IndustryStandard/Pci22.h>\r
+#include "AcpiPlatform.h"\r
+\r
+//\r
+// Global Variable\r
+//\r
+EFI_GLOBAL_NVS_AREA_PROTOCOL  mGlobalNvsArea;\r
+EFI_ACPI_SDT_PROTOCOL         *mAcpiSdt;\r
+\r
+EFI_ACPI_HANDLE mDsdtHandle = NULL;\r
+\r
+\r
+EFI_STATUS\r
+LocateSupportProtocol (\r
+  IN  EFI_GUID                       *Protocol,\r
+  OUT VOID                           **Instance,\r
+  IN  UINT32                         Type\r
+  )\r
+/*++\r
+\r
+Routine Description:\r
+\r
+  Locate the first instance of a protocol.  If the protocol requested is an\r
+  FV protocol, then it will return the first FV that contains the ACPI table\r
+  storage file.\r
+\r
+Arguments:\r
+\r
+  Protocol      The protocol to find.\r
+  Instance      Return pointer to the first instance of the protocol\r
+\r
+Returns:\r
+\r
+  EFI_SUCCESS           The function completed successfully.\r
+  EFI_NOT_FOUND         The protocol could not be located.\r
+  EFI_OUT_OF_RESOURCES  There are not enough resources to find the protocol.\r
+\r
+--*/\r
+{\r
+  EFI_STATUS              Status;\r
+  EFI_HANDLE              *HandleBuffer;\r
+  UINTN                   NumberOfHandles;\r
+  EFI_FV_FILETYPE         FileType;\r
+  UINT32                  FvStatus;\r
+  EFI_FV_FILE_ATTRIBUTES  Attributes;\r
+  UINTN                   Size;\r
+  UINTN                   i;\r
+\r
+  FvStatus = 0;\r
+\r
+  //\r
+  // Locate protocol.\r
+  //\r
+  Status = gBS->LocateHandleBuffer (\r
+                   ByProtocol,\r
+                   Protocol,\r
+                   NULL,\r
+                   &NumberOfHandles,\r
+                   &HandleBuffer\r
+                   );\r
+  if (EFI_ERROR (Status)) {\r
+\r
+    //\r
+    // Defined errors at this time are not found and out of resources.\r
+    //\r
+    return Status;\r
+  }\r
+\r
+\r
+\r
+  //\r
+  // Looking for FV with ACPI storage file\r
+  //\r
+\r
+  for (i = 0; i < NumberOfHandles; i++) {\r
+    //\r
+    // Get the protocol on this handle\r
+    // This should not fail because of LocateHandleBuffer\r
+    //\r
+    Status = gBS->HandleProtocol (\r
+                     HandleBuffer[i],\r
+                     Protocol,\r
+                     Instance\r
+                     );\r
+    ASSERT_EFI_ERROR (Status);\r
+\r
+    if (!Type) {\r
+      //\r
+      // Not looking for the FV protocol, so find the first instance of the\r
+      // protocol.  There should not be any errors because our handle buffer\r
+      // should always contain at least one or LocateHandleBuffer would have\r
+      // returned not found.\r
+      //\r
+      break;\r
+    }\r
+\r
+    //\r
+    // See if it has the ACPI storage file\r
+    //\r
+\r
+    Status = ((EFI_FIRMWARE_VOLUME2_PROTOCOL*) (*Instance))->ReadFile (*Instance,\r
+                                                              (EFI_GUID*)PcdGetPtr (PcdAcpiTableStorageFile),\r
+                                                              NULL,\r
+                                                              &Size,\r
+                                                              &FileType,\r
+                                                              &Attributes,\r
+                                                              &FvStatus\r
+                                                              );\r
+\r
+    //\r
+    // If we found it, then we are done\r
+    //\r
+    if (Status == EFI_SUCCESS) {\r
+      break;\r
+    }\r
+  }\r
+\r
+  //\r
+  // Our exit status is determined by the success of the previous operations\r
+  // If the protocol was found, Instance already points to it.\r
+  //\r
+\r
+  //\r
+  // Free any allocated buffers\r
+  //\r
+  gBS->FreePool (HandleBuffer);\r
+\r
+  return Status;\r
+}\r
+\r
+\r
+VOID\r
+DsdtTableUpdate (\r
+  IN OUT   EFI_ACPI_DESCRIPTION_HEADER  *TableHeader,\r
+  IN OUT   EFI_ACPI_TABLE_VERSION       *Version\r
+  )\r
+/*++\r
+\r
+  Routine Description:\r
+\r
+    Update the DSDT table\r
+\r
+  Arguments:\r
+\r
+    Table   - The table to be set\r
+    Version - Version to publish\r
+\r
+  Returns:\r
+\r
+    None\r
+\r
+--*/\r
+{\r
+\r
+  UINT8      *CurrPtr;\r
+  UINT8      *DsdtPointer;\r
+  UINT32     *Signature;\r
+  UINT8      *Operation;\r
+  UINT32     *Address;\r
+  UINT16     *Size;\r
+  //\r
+  // Loop through the ASL looking for values that we must fix up.\r
+  //\r
+  CurrPtr = (UINT8 *) TableHeader;\r
+  for (DsdtPointer = CurrPtr;\r
+       DsdtPointer <= (CurrPtr + ((EFI_ACPI_COMMON_HEADER *) CurrPtr)->Length);\r
+       DsdtPointer++\r
+      )\r
+  {\r
+    Signature = (UINT32 *) DsdtPointer;\r
+    switch (*Signature) {\r
+    //\r
+    // MNVS operation region\r
+    //\r
+    case (SIGNATURE_32 ('M', 'N', 'V', 'S')):\r
+      //\r
+      // Conditional match.  For Region Objects, the Operator will always be the\r
+      // byte immediately before the specific name.  Therefore, subtract 1 to check\r
+      // the Operator.\r
+      //\r
+      Operation = DsdtPointer - 1;\r
+      if (*Operation == AML_OPREGION_OP) {\r
+        Address   = (UINT32 *) (DsdtPointer + 6);\r
+        *Address  = (UINT32) (UINTN) mGlobalNvsArea.Area;\r
+        Size      = (UINT16 *) (DsdtPointer + 11);\r
+        *Size     = sizeof (EFI_GLOBAL_NVS_AREA);\r
+      }\r
+      break;\r
+\r
+    //\r
+    // Update processor PBLK register I/O base address\r
+    //\r
+    case (SIGNATURE_32 ('P', 'R', 'I', 'O')):\r
+      //\r
+      // Conditional match. Update the following ASL code:\r
+      // Processor (CPU0, 0x01, 0x4F495250, 0x06) {}\r
+      // The 3rd parameter will be updated to the actual PBLK I/O base address.\r
+      // the Operator.\r
+      //\r
+      Operation = DsdtPointer - 8;\r
+      if ((*Operation == AML_EXT_OP) && (*(Operation + 1) == AML_EXT_PROCESSOR_OP)) {\r
+        *(UINT32 *)DsdtPointer = PcdGet16(PcdPmbaIoBaseAddress);\r
+      }\r
+      break;\r
+    default:\r
+      break;\r
+    }\r
+  }\r
+}\r
+\r
+\r
+VOID\r
+ApicTableUpdate (\r
+  IN OUT   EFI_ACPI_DESCRIPTION_HEADER  *TableHeader,\r
+  IN OUT   EFI_ACPI_TABLE_VERSION       *Version\r
+  )\r
+/*++\r
+\r
+  Routine Description:\r
+\r
+    Update the processors information in the APIC table\r
+\r
+  Arguments:\r
+\r
+    Table   - The table to be set\r
+    Version - Version to publish\r
+\r
+  Returns:\r
+\r
+    None\r
+\r
+--*/\r
+{\r
+  EFI_STATUS                 Status;\r
+  EFI_MP_SERVICES_PROTOCOL   *MpService;\r
+  UINT8                      *CurrPtr;\r
+  UINT8                      *EndPtr;\r
+  UINT8                      CurrIoApic;\r
+  UINT8                      CurrProcessor;\r
+  UINTN                      NumberOfCPUs;\r
+  UINTN                      NumberOfEnabledCPUs;\r
+  UINTN                      BufferSize;\r
+  EFI_PROCESSOR_INFORMATION  MpContext;\r
+  ACPI_APIC_STRUCTURE_PTR    *ApicPtr;\r
+\r
+  CurrIoApic    = 0;\r
+  CurrProcessor = 0;\r
+  //\r
+  // Find the MP Protocol. This is an MP platform, so MP protocol must be\r
+  // there.\r
+  //\r
+  Status = gBS->LocateProtocol (\r
+                   &gEfiMpServiceProtocolGuid,\r
+                   NULL,\r
+                  (VOID**)&MpService\r
+                   );\r
+  if (EFI_ERROR (Status)) {\r
+    //\r
+    // Failed to get MP information, doesn't publish the invalid table\r
+    //\r
+    *Version = EFI_ACPI_TABLE_VERSION_NONE;\r
+    return;\r
+  }\r
+\r
+  //\r
+  // Determine the number of processors\r
+  //\r
+  MpService->GetNumberOfProcessors (\r
+              MpService,\r
+              &NumberOfCPUs,\r
+              &NumberOfEnabledCPUs\r
+              );\r
+\r
+  CurrPtr = (UINT8*) &(TableHeader[1]);\r
+  CurrPtr = CurrPtr + 8; // Size of Local APIC Address & Flag\r
+  EndPtr  = (UINT8*) TableHeader;\r
+  EndPtr  = EndPtr + TableHeader->Length;\r
+\r
+  while (CurrPtr < EndPtr) {\r
+\r
+    ApicPtr = (ACPI_APIC_STRUCTURE_PTR*) CurrPtr;\r
+    switch (ApicPtr->AcpiApicCommon.Type) {\r
+\r
+      case EFI_ACPI_1_0_PROCESSOR_LOCAL_APIC:\r
+        BufferSize = sizeof (EFI_PROCESSOR_INFORMATION);\r
+        ApicPtr->AcpiLocalApic.Flags = 0;\r
+        ApicPtr->AcpiLocalApic.ApicId = 0;\r
+        Status = MpService->GetProcessorInfo (\r
+                              MpService,\r
+                              CurrProcessor,\r
+                              &MpContext\r
+                              );\r
+\r
+        if (!EFI_ERROR (Status)) {\r
+          if (MpContext.StatusFlag & PROCESSOR_ENABLED_BIT) {\r
+            ApicPtr->AcpiLocalApic.Flags = EFI_ACPI_3_0_LOCAL_APIC_ENABLED;\r
+          }\r
+          ApicPtr->AcpiLocalApic.ApicId = (UINT8)MpContext.ProcessorId;\r
+        }\r
+        CurrProcessor++;\r
+        break;\r
+\r
+      case EFI_ACPI_1_0_IO_APIC:\r
+        //\r
+        // IO APIC entries can be patched here\r
+        //\r
+        if (CurrIoApic == 0) {\r
+          //\r
+          // Update SOC internel IOAPIC base\r
+          //\r
+          ApicPtr->AcpiIoApic.IoApicId      =  PcdGet8 (PcdIoApicSettingIoApicId);\r
+          ApicPtr->AcpiIoApic.IoApicAddress =  (UINT32)PcdGet64(PcdIoApicBaseAddress);\r
+          ApicPtr->AcpiIoApic.GlobalSystemInterruptBase = 0;\r
+        } else {\r
+          //\r
+          // Porting is required to update other IOAPIC entries if available\r
+          //\r
+          ASSERT (0);\r
+        }\r
+        CurrIoApic++;\r
+        break;\r
+\r
+      default:\r
+        break;\r
+      };\r
+    CurrPtr = CurrPtr + ApicPtr->AcpiApicCommon.Length;\r
+  }\r
+}\r
+\r
+VOID\r
+AcpiUpdateTable (\r
+  IN OUT   EFI_ACPI_DESCRIPTION_HEADER  *TableHeader,\r
+  IN OUT   EFI_ACPI_TABLE_VERSION       *Version\r
+  )\r
+/*++\r
+\r
+  Routine Description:\r
+\r
+    Set the correct table revision upon the setup value\r
+\r
+  Arguments:\r
+\r
+    Table   - The table to be set\r
+    Version - Version to publish\r
+\r
+  Returns:\r
+\r
+    None\r
+\r
+--*/\r
+\r
+{\r
+  EFI_ACPI_1_0_FIXED_ACPI_DESCRIPTION_TABLE *FadtHeader1;\r
+  EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE *FadtHeader2;\r
+  EFI_ACPI_3_0_FIXED_ACPI_DESCRIPTION_TABLE *FadtHeader3;\r
+  EFI_ACPI_MEMORY_MAPPED_ENHANCED_CONFIGURATION_SPACE_BASE_ADDRESS_ALLOCATION_STRUCTURE *AllocationStructurePtr;\r
+\r
+  if (TableHeader != NULL && Version != NULL) {\r
+\r
+    *Version = EFI_ACPI_TABLE_VERSION_1_0B | EFI_ACPI_TABLE_VERSION_2_0 | EFI_ACPI_TABLE_VERSION_3_0;\r
+    //\r
+    // Here we use all 3.0 signature because all version use same signature if they supported\r
+    //\r
+    switch (TableHeader->Signature) {\r
+    //\r
+    // "APIC" Multiple APIC Description Table\r
+    //\r
+    case EFI_ACPI_3_0_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE:\r
+      ApicTableUpdate (TableHeader, Version);\r
+      break;\r
+    //\r
+    // "DSDT" Differentiated System Description Table\r
+    //\r
+    case EFI_ACPI_3_0_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE:\r
+      DsdtTableUpdate (TableHeader, Version);\r
+      break;\r
+\r
+    //\r
+    // "FACP" Fixed ACPI Description Table (FADT)\r
+    //\r
+    case EFI_ACPI_3_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE:\r
+      *Version = EFI_ACPI_TABLE_VERSION_NONE;\r
+      if (TableHeader->Revision == EFI_ACPI_1_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION) {\r
+        *Version = EFI_ACPI_TABLE_VERSION_1_0B;\r
+        FadtHeader1 = (EFI_ACPI_1_0_FIXED_ACPI_DESCRIPTION_TABLE *) TableHeader;\r
+        FadtHeader1->SmiCmd     = PcdGet16(PcdSmmActivationPort);\r
+        FadtHeader1->Pm1aEvtBlk = PcdGet16(PcdPm1blkIoBaseAddress);\r
+        FadtHeader1->Pm1aCntBlk = PcdGet16(PcdPm1blkIoBaseAddress) + R_QNC_PM1BLK_PM1C;\r
+        FadtHeader1->PmTmrBlk   = PcdGet16(PcdPm1blkIoBaseAddress) + R_QNC_PM1BLK_PM1T;\r
+        FadtHeader1->Gpe0Blk    = PcdGet16(PcdGpe0blkIoBaseAddress);\r
+      } else if (TableHeader->Revision == EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION) {\r
+        *Version = EFI_ACPI_TABLE_VERSION_2_0;\r
+        FadtHeader2 = (EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE *) TableHeader;\r
+        FadtHeader2->SmiCmd     = PcdGet16(PcdSmmActivationPort);\r
+        FadtHeader2->Pm1aEvtBlk = PcdGet16(PcdPm1blkIoBaseAddress);\r
+        FadtHeader2->Pm1aCntBlk = PcdGet16(PcdPm1blkIoBaseAddress) + R_QNC_PM1BLK_PM1C;\r
+        FadtHeader2->PmTmrBlk   = PcdGet16(PcdPm1blkIoBaseAddress) + R_QNC_PM1BLK_PM1T;\r
+        FadtHeader2->Gpe0Blk    = PcdGet16(PcdGpe0blkIoBaseAddress);\r
+        FadtHeader2->XPm1aEvtBlk.Address = FadtHeader2->Pm1aEvtBlk;\r
+        FadtHeader2->XPm1aCntBlk.Address = FadtHeader2->Pm1aCntBlk;\r
+        FadtHeader2->XPmTmrBlk.Address   = FadtHeader2->PmTmrBlk;\r
+        FadtHeader2->XGpe0Blk.Address    = FadtHeader2->Gpe0Blk;\r
+      } else if (TableHeader->Revision == EFI_ACPI_3_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION) {\r
+        *Version = EFI_ACPI_TABLE_VERSION_3_0;\r
+        FadtHeader3 = (EFI_ACPI_3_0_FIXED_ACPI_DESCRIPTION_TABLE *) TableHeader;\r
+        FadtHeader3->SmiCmd     = PcdGet16(PcdSmmActivationPort);\r
+        FadtHeader3->Pm1aEvtBlk = PcdGet16(PcdPm1blkIoBaseAddress);\r
+        FadtHeader3->Pm1aCntBlk = PcdGet16(PcdPm1blkIoBaseAddress) + R_QNC_PM1BLK_PM1C;\r
+        FadtHeader3->PmTmrBlk   = PcdGet16(PcdPm1blkIoBaseAddress) + R_QNC_PM1BLK_PM1T;\r
+        FadtHeader3->Gpe0Blk    = PcdGet16(PcdGpe0blkIoBaseAddress);\r
+        FadtHeader3->XPm1aEvtBlk.Address = FadtHeader3->Pm1aEvtBlk;\r
+        FadtHeader3->XPm1aCntBlk.Address = FadtHeader3->Pm1aCntBlk;\r
+        FadtHeader3->XPmTmrBlk.Address   = FadtHeader3->PmTmrBlk;\r
+        FadtHeader3->XGpe0Blk.Address    = FadtHeader3->Gpe0Blk;\r
+      }\r
+      break;\r
+    //\r
+    // "FACS" Firmware ACPI Control Structure\r
+    //\r
+    case EFI_ACPI_3_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_SIGNATURE:\r
+      break;\r
+    //\r
+    // "SSDT" Secondary System Description Table\r
+    //\r
+    case EFI_ACPI_3_0_SECONDARY_SYSTEM_DESCRIPTION_TABLE_SIGNATURE:\r
+    break;\r
+    //\r
+    // "HPET" IA-PC High Precision Event Timer Table\r
+    //\r
+    case EFI_ACPI_3_0_HIGH_PRECISION_EVENT_TIMER_TABLE_SIGNATURE:\r
+      //\r
+      // If HPET is disabled in setup, don't publish the table.\r
+      //\r
+      if (mGlobalNvsArea.Area->HpetEnable == 0) {\r
+        *Version = EFI_ACPI_TABLE_VERSION_NONE;\r
+      }\r
+      ((EFI_ACPI_HIGH_PRECISION_EVENT_TIMER_TABLE_HEADER *) TableHeader)->BaseAddressLower32Bit.Address\r
+        = PcdGet64 (PcdHpetBaseAddress);\r
+      break;\r
+    //\r
+    // "SPCR" Serial Port Concole Redirection Table\r
+    //\r
+    case EFI_ACPI_3_0_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE:\r
+      break;\r
+    //\r
+    // "MCFG" PCI Express Memory Mapped Configuration Space Base Address Description Table\r
+    //\r
+    case EFI_ACPI_3_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE:\r
+      AllocationStructurePtr = (EFI_ACPI_MEMORY_MAPPED_ENHANCED_CONFIGURATION_SPACE_BASE_ADDRESS_ALLOCATION_STRUCTURE *)\r
+        ((UINT8 *)TableHeader + sizeof(EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE_HEADER));\r
+      AllocationStructurePtr->BaseAddress = PcdGet64(PcdPciExpressBaseAddress);\r
+      break;\r
+    // Lakeport platform doesn't support the following table\r
+    /*\r
+      //\r
+    // "ECDT" Embedded Controller Boot Resources Table\r
+        //\r
+    case EFI_ACPI_3_0_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE_SIGNATURE:\r
+      break;\r
+        //\r
+    // "PSDT" Persistent System Description Table\r
+          //\r
+    case EFI_ACPI_3_0_PERSISTENT_SYSTEM_DESCRIPTION_TABLE_SIGNATURE:\r
+      break;\r
+          //\r
+    // "SBST" Smart Battery Specification Table\r
+    //\r
+    case EFI_ACPI_3_0_SMART_BATTERY_SPECIFICATION_TABLE_SIGNATURE:\r
+          break;\r
+    //\r
+    // "SLIT" System Locality Information Table\r
+    //\r
+    case EFI_ACPI_3_0_SYSTEM_LOCALITY_INFORMATION_TABLE_SIGNATURE:\r
+          break;\r
+    //\r
+    // "SRAT" Static Resource Affinity Table\r
+    //\r
+    case EFI_ACPI_3_0_STATIC_RESOURCE_AFFINITY_TABLE_SIGNATURE:\r
+    break;\r
+  //\r
+    // "XSDT" Extended System Description Table\r
+  //\r
+    case EFI_ACPI_3_0_EXTENDED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE:\r
+      break;\r
+  //\r
+    // "BOOT" MS Simple Boot Spec\r
+  //\r
+    case EFI_ACPI_3_0_SIMPLE_BOOT_FLAG_TABLE_SIGNATURE:\r
+      break;\r
+  //\r
+    // "CPEP" Corrected Platform Error Polling Table\r
+  //\r
+    case EFI_ACPI_3_0_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_SIGNATURE:\r
+      break;\r
+  //\r
+    // "DBGP" MS Debug Port Spec\r
+  //\r
+    case EFI_ACPI_3_0_DEBUG_PORT_TABLE_SIGNATURE:\r
+      break;\r
+    //\r
+    // "ETDT" Event Timer Description Table\r
+    //\r
+    case EFI_ACPI_3_0_EVENT_TIMER_DESCRIPTION_TABLE_SIGNATURE:\r
+      break;\r
+    //\r
+    // "SPMI" Server Platform Management Interface Table\r
+    //\r
+    case EFI_ACPI_3_0_SERVER_PLATFORM_MANAGEMENT_INTERFACE_TABLE_SIGNATURE:\r
+      break;\r
+    //\r
+    // "TCPA" Trusted Computing Platform Alliance Capabilities Table\r
+    //\r
+    case EFI_ACPI_3_0_TRUSTED_COMPUTING_PLATFORM_ALLIANCE_CAPABILITIES_TABLE_SIGNATURE:\r
+      break;\r
+    */\r
+    default:\r
+      break;\r
+    }\r
+  }\r
+}\r
+\r
+//\r
+// Description:\r
+//    Entrypoint of Acpi Platform driver\r
+// In:\r
+//    ImageHandle\r
+//    SystemTable\r
+// Out:\r
+//    EFI_SUCCESS\r
+//    EFI_LOAD_ERROR\r
+//    EFI_OUT_OF_RESOURCES\r
+//\r
+\r
+EFI_STATUS\r
+AcpiPlatformEntryPoint (\r
+  IN EFI_HANDLE     ImageHandle,\r
+  IN EFI_SYSTEM_TABLE   *SystemTable\r
+  )\r
+{\r
+  EFI_STATUS                    Status;\r
+  EFI_ACPI_TABLE_PROTOCOL       *AcpiTable;\r
+  EFI_FIRMWARE_VOLUME2_PROTOCOL *FwVol;\r
+  INTN                          Instance;\r
+  EFI_ACPI_COMMON_HEADER        *CurrentTable;\r
+  UINTN                         TableHandle;\r
+  UINT32                        FvStatus;\r
+  UINTN                         Size;\r
+  EFI_ACPI_TABLE_VERSION        Version;\r
+  QNC_DEVICE_ENABLES            QNCDeviceEnables;\r
+  EFI_HANDLE                    Handle;\r
+  UINTN                         Index;\r
+  PCI_DEVICE_INFO               *PciDeviceInfo;\r
+  EFI_ACPI_HANDLE               PciRootHandle;\r
+  BOOLEAN                       UpdatePRT;\r
+  BOOLEAN                       UpdatePRW;\r
+  PCI_DEVICE_SETTING            *mConfigData;\r
+\r
+  DEBUG((DEBUG_INFO, "ACPI Platform start...\n"));\r
+\r
+  Instance = 0;\r
+  TableHandle = 0;\r
+  CurrentTable = NULL;\r
+  mConfigData  = NULL;\r
+  QNCDeviceEnables.Uint32 = PcdGet32 (PcdDeviceEnables);\r
+\r
+  //\r
+  // Initialize the EFI Driver Library\r
+  //\r
+\r
+  ASSERT (sizeof (EFI_GLOBAL_NVS_AREA) == 512);\r
+\r
+  Status = gBS->AllocatePool (\r
+                   EfiACPIMemoryNVS,\r
+                   sizeof (EFI_GLOBAL_NVS_AREA),\r
+                   (VOID**)&mGlobalNvsArea.Area\r
+                   );\r
+\r
+  Handle = NULL;\r
+  Status = gBS->InstallProtocolInterface (\r
+                  &Handle,\r
+                  &gEfiGlobalNvsAreaProtocolGuid,\r
+                  EFI_NATIVE_INTERFACE,\r
+                  &mGlobalNvsArea\r
+                  );\r
+\r
+  ASSERT_EFI_ERROR (Status);\r
+  if (!EFI_ERROR (Status)) {\r
+    SetMem (\r
+      mGlobalNvsArea.Area,\r
+      sizeof (EFI_GLOBAL_NVS_AREA),\r
+      0\r
+      );\r
+  }\r
+\r
+  //\r
+  // Initialize the data.  Eventually, this will be controlled by setup options.\r
+  //\r
+  mGlobalNvsArea.Area->HpetEnable           =  PcdGetBool (PcdHpetEnable);\r
+  mGlobalNvsArea.Area->Pm1blkIoBaseAddress  =  PcdGet16(PcdPm1blkIoBaseAddress);\r
+  mGlobalNvsArea.Area->PmbaIoBaseAddress    =  PcdGet16(PcdPmbaIoBaseAddress);\r
+  mGlobalNvsArea.Area->Gpe0blkIoBaseAddress =  PcdGet16(PcdGpe0blkIoBaseAddress);\r
+  mGlobalNvsArea.Area->GbaIoBaseAddress     =  PcdGet16(PcdGbaIoBaseAddress);\r
+  mGlobalNvsArea.Area->SmbaIoBaseAddress    =  PcdGet16(PcdSmbaIoBaseAddress);\r
+  mGlobalNvsArea.Area->WdtbaIoBaseAddress   =  PcdGet16(PcdWdtbaIoBaseAddress);\r
+  mGlobalNvsArea.Area->HpetBaseAddress      =  (UINT32)PcdGet64(PcdHpetBaseAddress);\r
+  mGlobalNvsArea.Area->HpetSize             =  (UINT32)PcdGet64(PcdHpetSize);\r
+  mGlobalNvsArea.Area->PciExpressBaseAddress=  (UINT32)PcdGet64(PcdPciExpressBaseAddress);\r
+  mGlobalNvsArea.Area->PciExpressSize       =  (UINT32)PcdGet64(PcdPciExpressSize);\r
+  mGlobalNvsArea.Area->RcbaMmioBaseAddress  =  (UINT32)PcdGet64(PcdRcbaMmioBaseAddress);\r
+  mGlobalNvsArea.Area->RcbaMmioSize         =  (UINT32)PcdGet64(PcdRcbaMmioSize);\r
+  mGlobalNvsArea.Area->IoApicBaseAddress    =  (UINT32)PcdGet64(PcdIoApicBaseAddress);\r
+  mGlobalNvsArea.Area->IoApicSize           =  (UINT32)PcdGet64(PcdIoApicSize);\r
+  mGlobalNvsArea.Area->TpmPresent           =  (UINT32)(FALSE);\r
+  mGlobalNvsArea.Area->DBG2Present          =  (UINT32)(FALSE);\r
+  mGlobalNvsArea.Area->PlatformType         =  (UINT32)PcdGet16 (PcdPlatformType);\r
+\r
+  //\r
+  // Configure platform IO expander I2C Slave Address.\r
+  //\r
+  if (mGlobalNvsArea.Area->PlatformType == Galileo) {\r
+    if (PlatformLegacyGpioGetLevel (R_QNC_GPIO_RGLVL_RESUME_WELL, GALILEO_DETERMINE_IOEXP_SLA_RESUMEWELL_GPIO)) {\r
+      mGlobalNvsArea.Area->AlternateSla = FALSE;\r
+    } else {\r
+      mGlobalNvsArea.Area->AlternateSla = TRUE;\r
+    }\r
+  }\r
+\r
+  //\r
+  // Find the AcpiTable protocol\r
+  //\r
+  Status = gBS->LocateProtocol (&gEfiAcpiTableProtocolGuid, NULL, (VOID**)&AcpiTable);\r
+  if (EFI_ERROR (Status)) {\r
+    return EFI_ABORTED;\r
+  }\r
+\r
+  //\r
+  // Initialize MADT table\r
+  //\r
+  Status = MadtTableInitialize (&CurrentTable, &Size);\r
+  ASSERT_EFI_ERROR (Status);\r
+  //\r
+  // Perform any table specific updates.\r
+  //\r
+  AcpiUpdateTable ((EFI_ACPI_DESCRIPTION_HEADER *) CurrentTable, &Version);\r
+\r
+  //\r
+  // Update the check sum\r
+  // It needs to be zeroed before the checksum calculation\r
+  //\r
+  ((EFI_ACPI_SDT_HEADER *)CurrentTable)->Checksum = 0;\r
+  ((EFI_ACPI_SDT_HEADER *)CurrentTable)->Checksum =\r
+    CalculateCheckSum8 ((VOID *)CurrentTable, CurrentTable->Length);\r
+\r
+  //\r
+  // Add the table\r
+  //\r
+  TableHandle = 0;\r
+  Status = AcpiTable->InstallAcpiTable (\r
+                            AcpiTable,\r
+                            CurrentTable,\r
+                            CurrentTable->Length,\r
+                          &TableHandle\r
+                          );\r
+  ASSERT_EFI_ERROR (Status);\r
+  CurrentTable = NULL;\r
+\r
+  //\r
+  // Init Pci Device PRT PRW information structure from PCD\r
+  //\r
+  mConfigData = (PCI_DEVICE_SETTING *)AllocateZeroPool (sizeof (PCI_DEVICE_SETTING));\r
+  ASSERT_EFI_ERROR (mConfigData);\r
+  InitPciDeviceInfoStructure (mConfigData);\r
+  //\r
+  // Get the Acpi SDT protocol for manipulation on acpi table\r
+  //\r
+  Status = gBS->LocateProtocol (&gEfiAcpiSdtProtocolGuid, NULL, (VOID **)&mAcpiSdt);\r
+  ASSERT_EFI_ERROR (Status);\r
+  //\r
+  // Locate the firmware volume protocol\r
+  //\r
+  Status = LocateSupportProtocol (&gEfiFirmwareVolume2ProtocolGuid, (VOID**)&FwVol, 1);\r
+  if (EFI_ERROR (Status)) {\r
+    return EFI_ABORTED;\r
+  }\r
+  //\r
+  // Read tables from the storage file.\r
+  //\r
+\r
+  while (Status == EFI_SUCCESS) {\r
+\r
+    Status = FwVol->ReadSection (\r
+                      FwVol,\r
+                      (EFI_GUID*)PcdGetPtr (PcdAcpiTableStorageFile),\r
+                      EFI_SECTION_RAW,\r
+                      Instance,\r
+                      (VOID**)&CurrentTable,\r
+                      &Size,\r
+                      &FvStatus\r
+                      );\r
+\r
+    if (!EFI_ERROR(Status)) {\r
+      //\r
+      // Perform any table specific updates.\r
+      //\r
+      AcpiUpdateTable ((EFI_ACPI_DESCRIPTION_HEADER *) CurrentTable, &Version);\r
+\r
+      //\r
+      // Update the check sum\r
+      // It needs to be zeroed before the checksum calculation\r
+      //\r
+      ((EFI_ACPI_SDT_HEADER *)CurrentTable)->Checksum = 0;\r
+      ((EFI_ACPI_SDT_HEADER *)CurrentTable)->Checksum =\r
+        CalculateCheckSum8 ((VOID *)CurrentTable, CurrentTable->Length);\r
+\r
+      //\r
+      // Add the table\r
+      //\r
+      TableHandle = 0;\r
+      Status = AcpiTable->InstallAcpiTable (\r
+                            AcpiTable,\r
+                              CurrentTable,\r
+                            ((EFI_ACPI_DESCRIPTION_HEADER *) CurrentTable)->Length,\r
+                              &TableHandle\r
+                              );\r
+      if (EFI_ERROR(Status)) {\r
+        return EFI_ABORTED;\r
+      }\r
+      //\r
+      // If this table is the DSDT table, then update the _PRT and _PRW based on\r
+      // the settings from pcds\r
+      //\r
+      if (CurrentTable->Signature == EFI_ACPI_2_0_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE) {\r
+        //\r
+        // Create the root handle for DSDT table\r
+        //\r
+        Status = mAcpiSdt->OpenSdt (TableHandle, &mDsdtHandle);\r
+        ASSERT_EFI_ERROR (Status);\r
+\r
+        PciRootHandle = NULL;\r
+        PciRootHandle = SdtGetRootBridgeHandle (mAcpiSdt, mDsdtHandle);\r
+        ASSERT (PciRootHandle != NULL);\r
+\r
+        PciDeviceInfo = NULL;\r
+        for (Index = 0; Index < mConfigData->PciDeviceInfoNumber; Index++) {\r
+          PciDeviceInfo = &(mConfigData->PciDeviceInfo[Index]);\r
+\r
+          //\r
+          // Check whether this is a valid item\r
+          //\r
+          if ((PciDeviceInfo->BridgeAddress != 0xFFFFFFFF) && (PciDeviceInfo->DeviceAddress != 0xFFFFFFFF)) {\r
+\r
+            //DEBUG ((EFI_D_ERROR, "Valid pci info structure: bridge address:0x%x, device address:0x%x\n", PciDeviceInfo->BridgeAddress, PciDeviceInfo->DeviceAddress));\r
+\r
+            UpdatePRT = FALSE;\r
+            UpdatePRW = FALSE;\r
+\r
+            SdtCheckPciDeviceInfoChanged (PciDeviceInfo, &UpdatePRT, &UpdatePRW);\r
+            //\r
+            // Check whether there is any valid pci routing item\r
+            //\r
+            if (UpdatePRT) {\r
+              //\r
+              // Update the pci routing information\r
+              //\r
+              //DEBUG ((EFI_D_ERROR, "Update _PRT\n"));\r
+              SdtUpdatePciRouting (mAcpiSdt, PciRootHandle, PciDeviceInfo);\r
+            }\r
+            //\r
+            // Check whether there is any valid pci routing item\r
+            //\r
+            if (UpdatePRW) {\r
+              //\r
+              // Update the pci wakeup information\r
+              //\r
+              //DEBUG ((EFI_D_ERROR, "Update _PRW\n"));\r
+              SdtUpdatePowerWake (mAcpiSdt, PciRootHandle, PciDeviceInfo);\r
+            }\r
+          }\r
+        }\r
+        Status = mAcpiSdt->Close (PciRootHandle);\r
+        ASSERT_EFI_ERROR (Status);\r
+        //\r
+        // Mark the root handle as modified , let SDT protocol recaculate the checksum\r
+        //\r
+        ((EFI_AML_HANDLE *)mDsdtHandle)->Modified = TRUE;\r
+        Status = mAcpiSdt->Close (mDsdtHandle);\r
+        ASSERT_EFI_ERROR (Status);\r
+      }\r
+      //\r
+      // Increment the instance\r
+      //\r
+      Instance++;\r
+      CurrentTable = NULL;\r
+    }\r
+  }\r
+\r
+  gBS->FreePool (mConfigData);\r
+  return EFI_SUCCESS;\r
+}\r
diff --git a/QuarkPlatformPkg/Acpi/Dxe/AcpiPlatform/AcpiPlatform.h b/QuarkPlatformPkg/Acpi/Dxe/AcpiPlatform/AcpiPlatform.h
new file mode 100644 (file)
index 0000000..d77fef8
--- /dev/null
@@ -0,0 +1,126 @@
+/** @file\r
+This is an implementation of the ACPI platform driver.  Requirements for\r
+this driver are defined in the Tiano ACPI External Product Specification,\r
+revision 0.3.6.\r
+\r
+Copyright (c) 2013-2015 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution.  The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+**/\r
+\r
+#ifndef _ACPI_PLATFORM_H_\r
+#define _ACPI_PLATFORM_H_\r
+\r
+//\r
+// Statements that include other header files\r
+//\r
+\r
+#include <PiDxe.h>\r
+#include <IntelQNCDxe.h>\r
+#include <Platform.h>\r
+#include <PlatformBoards.h>\r
+#include <Ioh.h>\r
+#include <QNCCommonDefinitions.h>\r
+\r
+#include <Protocol/GlobalNvsArea.h>\r
+#include <Protocol/MpService.h>\r
+#include <Protocol/AcpiSystemDescriptionTable.h>\r
+#include <Protocol/FirmwareVolume2.h>\r
+\r
+#include <Library/UefiDriverEntryPoint.h>\r
+#include <Library/UefiBootServicesTableLib.h>\r
+#include <Library/UefiRuntimeServicesTableLib.h>\r
+#include <Library/DebugLib.h>\r
+#include <Library/BaseMemoryLib.h>\r
+#include <Library/IoLib.h>\r
+#include <Library/PcdLib.h>\r
+#include <Library/UefiLib.h>\r
+#include <Library/DxeServicesLib.h>\r
+#include <Library/DevicePathLib.h>\r
+#include <Library/MemoryAllocationLib.h>\r
+#include <Library/QNCAccessLib.h>\r
+#include <Library/PlatformHelperLib.h>\r
+\r
+#include <IndustryStandard/Acpi.h>\r
+#include <IndustryStandard/HighPrecisionEventTimerTable.h>\r
+#include <IndustryStandard/MemoryMappedConfigurationSpaceAccessTable.h>\r
+\r
+#include "Madt.h"\r
+#include "AcpiPciUpdate.h"\r
+\r
+#pragma pack(1)\r
+typedef struct {\r
+  UINT8   StartByte;\r
+  UINT32  NameStr;\r
+  UINT8   OpCode;\r
+  UINT16  Size;                // Hardcode to 16bit width because the table we use is fixed size\r
+  UINT8   NumEntries;\r
+} EFI_ACPI_NAME_COMMAND;\r
+\r
+typedef struct {\r
+  UINT8   PackageOp;\r
+  UINT8   PkgLeadByte;\r
+  UINT8   NumEntries;\r
+  UINT8   DwordPrefix0;\r
+  UINT32  CoreFreq;\r
+  UINT8   DwordPrefix1;\r
+  UINT32  Power;\r
+  UINT8   DwordPrefix2;\r
+  UINT32  TransLatency;\r
+  UINT8   DwordPrefix3;\r
+  UINT32  BMLatency;\r
+  UINT8   DwordPrefix4;\r
+  UINT32  Control;\r
+  UINT8   DwordPrefix5;\r
+  UINT32  Status;\r
+} EFI_PSS_PACKAGE;\r
+#pragma pack()\r
+\r
+\r
+#define AML_NAME_OP               0x08\r
+#define AML_METHOD_OP             0x14\r
+#define AML_OPREGION_OP           0x80\r
+#define AML_PACKAGE_OP            0x12    // Package operator.\r
+\r
+//\r
+// ACPI table information used to initialize tables.\r
+//\r
+#define EFI_ACPI_OEM_ID           "INTEL "\r
+#define EFI_ACPI_OEM_TABLE_ID     0x2020204F4E414954ULL  // "TIANO   "\r
+#define EFI_ACPI_OEM_REVISION     0x00000002\r
+#define EFI_ACPI_CREATOR_ID       0x5446534D          // "MSFT"\r
+#define EFI_ACPI_CREATOR_REVISION 0x01000013\r
+\r
+#define ACPI_COMPATIBLE_1_0       0\r
+#define ACPI_COMPATIBLE_2_0       1\r
+#define ACPI_COMPATIBLE_3_0       2\r
+\r
+\r
+\r
+\r
+//\r
+// Private Driver Data\r
+//\r
+\r
+//\r
+// Define Union of IO APIC & Local APIC structure;\r
+//\r
+\r
+typedef union {\r
+  EFI_ACPI_2_0_PROCESSOR_LOCAL_APIC_STRUCTURE     AcpiLocalApic;\r
+  EFI_ACPI_2_0_IO_APIC_STRUCTURE                  AcpiIoApic;\r
+  struct {\r
+    UINT8                                         Type;\r
+    UINT8                                         Length;\r
+  } AcpiApicCommon;\r
+} ACPI_APIC_STRUCTURE_PTR;\r
+\r
+#endif\r
diff --git a/QuarkPlatformPkg/Acpi/Dxe/AcpiPlatform/AcpiPlatform.inf b/QuarkPlatformPkg/Acpi/Dxe/AcpiPlatform/AcpiPlatform.inf
new file mode 100644 (file)
index 0000000..dcf2b4a
--- /dev/null
@@ -0,0 +1,202 @@
+## @file\r
+# Component description file for AcpiPlatform module.\r
+#\r
+# This is an implementation of the ACPI platform driver,\r
+# whose requirements are from ACPI External Product Specification.\r
+# Copyright (c) 2013-2015 Intel Corporation.\r
+#\r
+# This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution.  The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php\r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+##\r
+\r
+[Defines]\r
+  INF_VERSION                    = 0x00010005\r
+  BASE_NAME                      = AcpiPlatform\r
+  FILE_GUID                      = 368B3649-F204-4cd0-89A8-091077C070FA\r
+  MODULE_TYPE                    = DXE_DRIVER\r
+  VERSION_STRING                 = 1.0\r
+  ENTRY_POINT                    = AcpiPlatformEntryPoint\r
+\r
+#\r
+# The following information is for reference only and not required by the build tools.\r
+#\r
+#  VALID_ARCHITECTURES           = IA32 X64 IPF EBC\r
+#\r
+\r
+[Sources]\r
+  AcpiPlatform.c\r
+  AcpiPlatform.h\r
+  MadtPlatform.c\r
+  Madt.h\r
+  AcpiPciUpdate.c\r
+  AcpiPciUpdate.h\r
+\r
+[Packages]\r
+  MdePkg/MdePkg.dec\r
+  MdeModulePkg/MdeModulePkg.dec\r
+  UefiCpuPkg/UefiCpuPkg.dec\r
+  QuarkSocPkg/QuarkSocPkg.dec\r
+  QuarkPlatformPkg/QuarkPlatformPkg.dec\r
+\r
+[LibraryClasses]\r
+  UefiLib\r
+  DxeServicesLib\r
+  PcdLib\r
+  IoLib\r
+  BaseMemoryLib\r
+  DebugLib\r
+  UefiRuntimeServicesTableLib\r
+  UefiBootServicesTableLib\r
+  UefiDriverEntryPoint\r
+  DevicePathLib\r
+  PlatformHelperLib\r
+\r
+[Protocols]\r
+  gEfiGlobalNvsAreaProtocolGuid                 # PROTOCOL ALWAYS_CONSUMED\r
+  gEfiMpServiceProtocolGuid                     # PROTOCOL SOMETIMES_CONSUMED\r
+  gEfiAcpiSdtProtocolGuid                       # PROTOCOL ALWAYS_CONSUMED\r
+  gEfiAcpiTableProtocolGuid                     # PROTOCOL ALWAYS_CONSUMED\r
+\r
+[Pcd]\r
+  gQuarkPlatformTokenSpaceGuid.PcdPlatformType\r
+\r
+  gUefiCpuPkgTokenSpaceGuid.PcdCpuLocalApicBaseAddress\r
+\r
+  gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable0Enable\r
+  gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable0SourceIrq\r
+  gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable0Polarity\r
+  gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable0TrigerMode\r
+  gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable0GlobalIrq\r
+\r
+  gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable1Enable\r
+  gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable1SourceIrq\r
+  gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable1Polarity\r
+  gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable1TrigerMode\r
+  gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable1GlobalIrq\r
+\r
+  gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable2Enable\r
+  gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable2SourceIrq\r
+  gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable2Polarity\r
+  gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable2TrigerMode\r
+  gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable2GlobalIrq\r
+\r
+  gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable3Enable\r
+  gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable3SourceIrq\r
+  gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable3Polarity\r
+  gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable3TrigerMode\r
+  gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable3GlobalIrq\r
+\r
+  gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable4Enable\r
+  gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable4SourceIrq\r
+  gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable4Polarity\r
+  gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable4TrigerMode\r
+  gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable4GlobalIrq\r
+\r
+  gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable5Enable\r
+  gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable5SourceIrq\r
+  gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable5Polarity\r
+  gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable5TrigerMode\r
+  gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable5GlobalIrq\r
+\r
+  gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable6Enable\r
+  gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable6SourceIrq\r
+  gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable6Polarity\r
+  gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable6TrigerMode\r
+  gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable6GlobalIrq\r
+\r
+  gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable7Enable\r
+  gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable7SourceIrq\r
+  gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable7Polarity\r
+  gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable7TrigerMode\r
+  gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable7GlobalIrq\r
+\r
+  gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable8Enable\r
+  gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable8SourceIrq\r
+  gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable8Polarity\r
+  gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable8TrigerMode\r
+  gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable8GlobalIrq\r
+\r
+  gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable9Enable\r
+  gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable9SourceIrq\r
+  gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable9Polarity\r
+  gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable9TrigerMode\r
+  gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable9GlobalIrq\r
+\r
+  gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable10Enable\r
+  gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable10SourceIrq\r
+  gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable10Polarity\r
+  gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable10TrigerMode\r
+  gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable10GlobalIrq\r
+\r
+  gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable11Enable\r
+  gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable11SourceIrq\r
+  gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable11Polarity\r
+  gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable11TrigerMode\r
+  gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable11GlobalIrq\r
+\r
+  gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable12Enable\r
+  gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable12SourceIrq\r
+  gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable12Polarity\r
+  gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable12TrigerMode\r
+  gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable12GlobalIrq\r
+\r
+  gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable13Enable\r
+  gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable13SourceIrq\r
+  gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable13Polarity\r
+  gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable13TrigerMode\r
+  gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable13GlobalIrq\r
+\r
+  gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable14Enable\r
+  gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable14SourceIrq\r
+  gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable14Polarity\r
+  gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable14TrigerMode\r
+  gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable14GlobalIrq\r
+\r
+  gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable15Enable\r
+  gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable15SourceIrq\r
+  gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable15Polarity\r
+  gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable15TrigerMode\r
+  gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable15GlobalIrq\r
+\r
+  gEfiQuarkNcSocIdTokenSpaceGuid.PcdIoApicBaseAddress\r
+  gQuarkPlatformTokenSpaceGuid.PcdIoApicSettingIoApicAddress\r
+  gQuarkPlatformTokenSpaceGuid.PcdIoApicSettingGlobalInterruptBase\r
+  gQuarkPlatformTokenSpaceGuid.PcdIoApicSettingIoApicId\r
+  gQuarkPlatformTokenSpaceGuid.PcdIoApicSettingNmiEnable\r
+  gQuarkPlatformTokenSpaceGuid.PcdIoApicSettingNmiSource\r
+  gQuarkPlatformTokenSpaceGuid.PcdIoApicSettingPolarity\r
+  gQuarkPlatformTokenSpaceGuid.PcdIoApicSettingTrigerMode\r
+  gQuarkPlatformTokenSpaceGuid.PcdLocalApicSettingNmiEnabelApicIdMask\r
+  gQuarkPlatformTokenSpaceGuid.PcdLocalApicSettingAddressOverrideEnable\r
+  gQuarkPlatformTokenSpaceGuid.PcdLocalApicSettingPolarity\r
+  gQuarkPlatformTokenSpaceGuid.PcdLocalApicSettingTrigerMode\r
+  gQuarkPlatformTokenSpace