--- /dev/null
+## @file\r
+# Component description file for PlatformAcpiTable module.\r
+#\r
+# Build acpi table data required by system boot.\r
+# All .asi files tagged with "ToolCode="DUMMY"" in following\r
+# file list are device description and are included by top\r
+# level ASL file which will be dealed with by asl.exe application.\r
+#\r
+# Copyright (c) 2013-2015 Intel Corporation.\r
+#\r
+# This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution. The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php\r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+##\r
+\r
+[Defines]\r
+ INF_VERSION = 0x00010005\r
+ BASE_NAME = AcpiTables\r
+ FILE_GUID = 7E374E25-8E01-4FEE-87F2-390C23C606CD\r
+ MODULE_TYPE = USER_DEFINED\r
+ VERSION_STRING = 1.0\r
+\r
+#\r
+# The following information is for reference only and not required by the build tools.\r
+#\r
+# VALID_ARCHITECTURES = IA32 X64 IPF EBC\r
+#\r
+\r
+[Sources]\r
+ Facs/Facs.aslc\r
+ Fadt/Fadt2.0.aslc\r
+ Hpet/Hpet.aslc\r
+ Mcfg/Mcfg.aslc\r
+ Dsdt/Platform.asl\r
+ CpuPm/CpuPm.asl\r
+ Cpu0Cst/Cpu0Cst.asl\r
+ Cpu0Ist/Cpu0Ist.asl\r
+ Cpu0Tst/Cpu0Tst.asl\r
+\r
+[Packages]\r
+ MdePkg/MdePkg.dec\r
+ QuarkPlatformPkg/QuarkPlatformPkg.dec\r
+ QuarkSocPkg/QuarkSocPkg.dec\r
--- /dev/null
+/** @file\r
+CPU C State control methods\r
+\r
+Copyright (c) 2013-2015 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+DefinitionBlock (\r
+ "Cpu0Cst.aml",\r
+ "SSDT",\r
+ 0x01,\r
+ "SsgPmm",\r
+ "Cpu0Cst",\r
+ 0x0011\r
+ )\r
+{\r
+ External(\_PR.CPU0, DeviceObj)\r
+ External (PDC0, IntObj)\r
+ External (CFGD, FieldUnitObj)\r
+\r
+ Scope(\_PR.CPU0)\r
+ {\r
+ Method (_CST, 0)\r
+ {\r
+ // If CMP is supported, and OSPM is not capable of independent C1, P, T state\r
+ // support for each processor for multi-processor configuration, we will just report\r
+ // C1 halt\r
+ //\r
+ // PDCx[4] = Indicates whether OSPM is not capable of independent C1, P, T state\r
+ // support for each processor for multi-processor configuration.\r
+ //\r
+ If(LAnd(And(CFGD,0x01000000), LNot(And(PDC0,0x10))))\r
+ {\r
+ Return(Package() {\r
+ 1,\r
+ Package()\r
+ { // C1 halt\r
+ ResourceTemplate(){Register(FFixedHW, 0, 0, 0)},\r
+ 1,\r
+ 157,\r
+ 1000\r
+ }\r
+ })\r
+ }\r
+\r
+ //\r
+ // If MWAIT extensions is supported and OSPM is capable of performing\r
+ // native C state instructions for the C2/C3 in multi-processor configuration,\r
+ // we report every c state with MWAIT extensions.\r
+ //\r
+ // PDCx[9] = Indicates whether OSPM is capable of performing native C state instructions\r
+ // for the C2/C3 in multi-processor configuration\r
+ //\r
+ If(LAnd(And(CFGD, 0x200000), And(PDC0,0x200)))\r
+ {\r
+ //\r
+ // If C6 is supported, we report MWAIT C1,C2,C4,C6\r
+ //\r
+ If(And(CFGD,0x200))\r
+ {\r
+ Return( Package()\r
+ {\r
+ 4,\r
+ Package()\r
+ { // MWAIT C1, hardware coordinated with no bus master avoidance\r
+ ResourceTemplate(){Register(FFixedHW, 1, 2, 0x00, 1)},\r
+ 1,\r
+ 1,\r
+ 1000\r
+ },\r
+ Package()\r
+ { // MWAIT C2, hardware coordinated with no bus master avoidance\r
+ ResourceTemplate(){Register(FFixedHW, 1, 2, 0x10, 1)},\r
+ 2,\r
+ 20,\r
+ 500\r
+ },\r
+ Package()\r
+ { // MWAIT C4, hardware coordinated with bus master avoidance enabled\r
+ ResourceTemplate(){Register(FFixedHW, 1, 2, 0x30, 3)},\r
+ 3,\r
+ 100,\r
+ 100\r
+ },\r
+ Package()\r
+ { // MWAIT C6, hardware coordinated with bus master avoidance enabled\r
+ ResourceTemplate(){Register(FFixedHW, 1, 2, 0x50, 3)},\r
+ 3,\r
+ 140,\r
+ 10\r
+ }\r
+ })\r
+ }\r
+ //\r
+ // If C4 is supported, we report MWAIT C1,C2,C4\r
+ //\r
+ If(And(CFGD,0x080))\r
+ {\r
+ Return( Package()\r
+ {\r
+ 3,\r
+ Package()\r
+ { // MWAIT C1, hardware coordinated with no bus master avoidance\r
+ ResourceTemplate(){Register(FFixedHW, 1, 2, 0x00, 1)},\r
+ 1,\r
+ 1,\r
+ 1000\r
+ },\r
+ Package()\r
+ { // MWAIT C2, hardware coordinated with no bus master avoidance\r
+ ResourceTemplate(){Register(FFixedHW, 1, 2, 0x10, 1)},\r
+ 2,\r
+ 20,\r
+ 500\r
+ },\r
+ Package()\r
+ { // MWAIT C4, hardware coordinated with bus master avoidance enabled\r
+ ResourceTemplate(){Register(FFixedHW, 1, 2, 0x30, 3)},\r
+ 3,\r
+ 100,\r
+ 100\r
+ }\r
+ })\r
+ }\r
+ //\r
+ // If C2 is supported, we report MWAIT C1,C2\r
+ //\r
+ If(And(CFGD,0x020))\r
+ {\r
+ Return( Package()\r
+ {\r
+ 2,\r
+ Package()\r
+ { // MWAIT C1, hardware coordinated with no bus master avoidance\r
+ ResourceTemplate(){Register(FFixedHW, 1, 2, 0x00, 1)},\r
+ 1,\r
+ 1,\r
+ 1000\r
+ },\r
+ Package()\r
+ { // MWAIT C2, hardware coordinated with no bus master avoidance\r
+ ResourceTemplate(){Register(FFixedHW, 1, 2, 0x10, 1)},\r
+ 2,\r
+ 20,\r
+ 500\r
+ }\r
+ })\r
+ }\r
+ //\r
+ // Else we only report MWAIT C1.\r
+ //\r
+ Return(Package()\r
+ {\r
+ 1,\r
+ Package()\r
+ { // MWAIT C1, hardware coordinated with no bus master avoidance\r
+ ResourceTemplate () {Register(FFixedHW, 1, 2, 0x00, 1)},\r
+ 1,\r
+ 1,\r
+ 1000\r
+ }\r
+ })\r
+ }\r
+\r
+ // If OSPM is only capable of performing native C state instructions for\r
+ // the C1 in multi-processor configuration, we report C1 with MWAIT, other\r
+ // C states with IO method.\r
+ //\r
+ // PDCx[8] = Indicates whether OSPM is capable of performing native C state instructions\r
+ // for the C1 in multi-processor configuration\r
+ //\r
+ If(LAnd(And(CFGD, 0x200000), And(PDC0,0x100)))\r
+ {\r
+ //\r
+ // If C6 is supported, we report MWAIT C1, IO C2,C4,C6\r
+ //\r
+ If(And(CFGD,0x200))\r
+ {\r
+ Return( Package()\r
+ {\r
+ 4,\r
+ Package()\r
+ { // MWAIT C1, hardware coordinated with no bus master avoidance\r
+ ResourceTemplate () {Register(FFixedHW, 1, 2, 0x00, 1)},\r
+ 1,\r
+ 1,\r
+ 1000\r
+ },\r
+ Package()\r
+ { // IO C2 ("PMBALVL2" will be updated at runtime)\r
+ ResourceTemplate () {Register(SystemIO, 8, 0, 0x324C564C41424D50)},\r
+ 2,\r
+ 20,\r
+ 500\r
+ },\r
+ Package()\r
+ { // IO C4 ("PMBALVL4" will be updated at runtime)\r
+ ResourceTemplate () {Register(SystemIO, 8, 0, 0x344C564C41424D50)},\r
+ 3,\r
+ 100,\r
+ 100\r
+ },\r
+ Package()\r
+ { // IO C6 ("PMBALVL6" will be updated at runtime)\r
+ ResourceTemplate () {Register(SystemIO, 8, 0, 0x364C564C41424D50)},\r
+ 3,\r
+ 140,\r
+ 10\r
+ }\r
+ })\r
+ }\r
+ //\r
+ // If C4 is supported, we report MWAIT C1, IO C2,C4\r
+ //\r
+ If(And(CFGD,0x080))\r
+ {\r
+ Return( Package()\r
+ {\r
+ 3,\r
+ Package()\r
+ { // MWAIT C1, hardware coordinated with no bus master avoidance\r
+ ResourceTemplate () {Register(FFixedHW, 1, 2, 0x00, 1)},\r
+ 1,\r
+ 1,\r
+ 1000\r
+ },\r
+ Package()\r
+ { // IO C2 ("PMBALVL2" will be updated at runtime)\r
+ ResourceTemplate () {Register(SystemIO, 8, 0, 0x324C564C41424D50)},\r
+ 2,\r
+ 20,\r
+ 500\r
+ },\r
+ Package()\r
+ { // IO C4 ("PMBALVL4" will be updated at runtime)\r
+ ResourceTemplate () {Register(SystemIO, 8, 0, 0x344C564C41424D50)},\r
+ 3,\r
+ 100,\r
+ 100\r
+ }\r
+ })\r
+ }\r
+ //\r
+ // If C2 is supported, we report MWAIT C1, IO C2\r
+ //\r
+ If(And(CFGD,0x020))\r
+ {\r
+ Return( Package()\r
+ {\r
+ 2,\r
+ Package()\r
+ { // MWAIT C1, hardware coordinated with no bus master avoidance\r
+ ResourceTemplate () {Register(FFixedHW, 1, 2, 0x00, 1)},\r
+ 1,\r
+ 1,\r
+ 1000\r
+ },\r
+ Package()\r
+ { // IO C2 ("PMBALVL2" will be updated at runtime)\r
+ ResourceTemplate () {Register(SystemIO, 8, 0, 0x324C564C41424D50)},\r
+ 2,\r
+ 20,\r
+ 500\r
+ }\r
+ })\r
+ }\r
+ //\r
+ // Else we only report MWAIT C1.\r
+ //\r
+ Return(Package()\r
+ {\r
+ 1,\r
+ Package()\r
+ { // MWAIT C1, hardware coordinated with no bus master avoidance\r
+ ResourceTemplate () {Register(FFixedHW, 1, 2, 0x00, 1)},\r
+ 1,\r
+ 1,\r
+ 1000\r
+ }\r
+ })\r
+ }\r
+\r
+ //\r
+ // If MWAIT is not supported, we report all the c states with IO method\r
+ //\r
+\r
+ //\r
+ // If C6 is supported, we report C1 halt, IO C2,C4,C6\r
+ //\r
+ If(And(CFGD,0x200))\r
+ {\r
+ Return(Package()\r
+ {\r
+ 4,\r
+ Package()\r
+ { // C1 Halt\r
+ ResourceTemplate () {Register(FFixedHW, 0, 0, 0)},\r
+ 1,\r
+ 1,\r
+ 1000\r
+ },\r
+ Package()\r
+ { // IO C2 ("PMBALVL2" will be updated at runtime)\r
+ ResourceTemplate () {Register(SystemIO, 8, 0, 0x324C564C41424D50)},\r
+ 2,\r
+ 20,\r
+ 500\r
+ },\r
+ Package()\r
+ { // IO C4 ("PMBALVL4" will be updated at runtime)\r
+ ResourceTemplate () {Register(SystemIO, 8, 0, 0x344C564C41424D50)},\r
+ 3,\r
+ 100,\r
+ 100\r
+ },\r
+ Package()\r
+ { // IO C6 ("PMBALVL6" will be updated at runtime)\r
+ ResourceTemplate () {Register(SystemIO, 8, 0, 0x364C564C41424D50)},\r
+ 3,\r
+ 140,\r
+ 10\r
+ }\r
+ })\r
+ }\r
+ //\r
+ // If C4 is supported, we report C1 halt, IO C2,C4\r
+ //\r
+ If(And(CFGD,0x080))\r
+ {\r
+ Return(Package()\r
+ {\r
+ 3,\r
+ Package()\r
+ { // C1 halt\r
+ ResourceTemplate () {Register(FFixedHW, 0, 0, 0)},\r
+ 1,\r
+ 1,\r
+ 1000\r
+ },\r
+ Package()\r
+ { // IO C2 ("PMBALVL2" will be updated at runtime)\r
+ ResourceTemplate () {Register(SystemIO, 8, 0, 0x324C564C41424D50)},\r
+ 2,\r
+ 20,\r
+ 500\r
+ },\r
+ Package()\r
+ { // IO C4 ("PMBALVL4" will be updated at runtime)\r
+ ResourceTemplate () {Register(SystemIO, 8, 0, 0x344C564C41424D50)},\r
+ 3,\r
+ 100,\r
+ 100\r
+ }\r
+ })\r
+ }\r
+\r
+ //\r
+ // If C2 is supported, we report C1 halt, IO C2\r
+ //\r
+ If(And(CFGD,0x020))\r
+ {\r
+ Return(Package()\r
+ {\r
+ 2,\r
+ Package()\r
+ { // C1 halt\r
+ ResourceTemplate () {Register(FFixedHW, 0, 0, 0)},\r
+ 1,\r
+ 1,\r
+ 1000\r
+ },\r
+ Package()\r
+ { // IO C2 ("PMBALVL2" will be updated at runtime)\r
+ ResourceTemplate () {Register(SystemIO, 8, 0, 0x324C564C41424D50)},\r
+ 2,\r
+ 20,\r
+ 500\r
+ }\r
+ })\r
+ }\r
+ //\r
+ // Else we only report C1 halt.\r
+ //\r
+ Return(Package()\r
+ {\r
+ 1,\r
+ Package()\r
+ { // C1 halt\r
+ ResourceTemplate () {Register(FFixedHW, 0, 0, 0)},\r
+ 1,\r
+ 1,\r
+ 1000\r
+ }\r
+ })\r
+ }\r
+ }\r
+}\r
--- /dev/null
+/** @file\r
+CPU EIST control methods\r
+\r
+Copyright (c) 2013-2015 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+DefinitionBlock (\r
+ "CPU0IST.aml",\r
+ "SSDT",\r
+ 0x01,\r
+ "SsgPmm",\r
+ "Cpu0Ist",\r
+ 0x0012\r
+ )\r
+{\r
+ External (PDC0, IntObj)\r
+ External (CFGD, FieldUnitObj)\r
+ External(\_PR.CPU0, DeviceObj)\r
+\r
+ Scope(\_PR.CPU0)\r
+ {\r
+ Method(_PPC,0)\r
+ {\r
+ Return(ZERO) // Return All States Available.\r
+ }\r
+\r
+ Method(_PCT,0)\r
+ {\r
+ //\r
+ // If GV3 is supported and OSPM is capable of direct access to\r
+ // performance state MSR, we use MSR method\r
+ //\r
+ //\r
+ // PDCx[0] = Indicates whether OSPM is capable of direct access to\r
+ // performance state MSR.\r
+ //\r
+ If(LAnd(And(CFGD,0x0001), And(PDC0,0x0001)))\r
+ {\r
+ Return(Package() // MSR Method\r
+ {\r
+ ResourceTemplate(){Register(FFixedHW, 0, 0, 0)},\r
+ ResourceTemplate(){Register(FFixedHW, 0, 0, 0)}\r
+ })\r
+\r
+ }\r
+\r
+ //\r
+ // Otherwise, we use smi method\r
+ //\r
+ Return(Package() // SMI Method\r
+ {\r
+ ResourceTemplate(){Register(SystemIO,16,0,0xB2)},\r
+ ResourceTemplate(){Register(SystemIO, 8,0,0xB3)}\r
+ })\r
+ }\r
+\r
+ Method(_PSS,0)\r
+ {\r
+ //\r
+ // If OSPM is capable of direct access to performance state MSR,\r
+ // we report NPSS, otherwise, we report SPSS.\r
+ If (And(PDC0,0x0001))\r
+ {\r
+ Return(NPSS)\r
+ }\r
+\r
+ Return(SPSS)\r
+ }\r
+\r
+ Name(SPSS,Package()\r
+ {\r
+ Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r
+ Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r
+ Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r
+ Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r
+ Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r
+ Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r
+ Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r
+ Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r
+ Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r
+ Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r
+ Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r
+ Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000}\r
+ })\r
+\r
+ Name(NPSS,Package()\r
+ {\r
+ Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r
+ Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r
+ Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r
+ Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r
+ Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r
+ Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r
+ Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r
+ Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r
+ Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r
+ Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r
+ Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r
+ Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000}\r
+ })\r
+\r
+ Method(_PSD,0)\r
+ {\r
+ //\r
+ // If CMP is suppored, we report the dependency with two processors\r
+ //\r
+ If(And(CFGD,0x1000000))\r
+ {\r
+ //\r
+ // If OSPM is capable of hardware coordination of P-states, we report\r
+ // the dependency with hardware coordination.\r
+ //\r
+ // PDCx[11] = Indicates whether OSPM is capable of hardware coordination of P-states\r
+ //\r
+ If(And(PDC0,0x0800))\r
+ {\r
+ Return(Package(){\r
+ Package(){\r
+ 5, // # entries.\r
+ 0, // Revision.\r
+ 0, // Domain #.\r
+ 0xFE, // Coord Type- HW_ALL.\r
+ 2 // # processors.\r
+ }\r
+ })\r
+ }\r
+\r
+ //\r
+ // Otherwise, the dependency with OSPM coordination\r
+ //\r
+ Return(Package(){\r
+ Package(){\r
+ 5, // # entries.\r
+ 0, // Revision.\r
+ 0, // Domain #.\r
+ 0xFC, // Coord Type- SW_ALL.\r
+ 2 // # processors.\r
+ }\r
+ })\r
+ }\r
+\r
+ //\r
+ // Otherwise, we report the dependency with one processor\r
+ //\r
+ Return(Package(){\r
+ Package(){\r
+ 5, // # entries.\r
+ 0, // Revision.\r
+ 0, // Domain #.\r
+ 0xFC, // Coord Type- SW_ALL.\r
+ 1 // # processors.\r
+ }\r
+ })\r
+ }\r
+ }\r
+}\r
--- /dev/null
+/** @file\r
+CPU T-state control methods\r
+\r
+Copyright (c) 2013-2015 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+DefinitionBlock (\r
+ "CPU0TST.aml",\r
+ "SSDT",\r
+ 0x01,\r
+ "SsgPmm",\r
+ "Cpu0Tst",\r
+ 0x0013\r
+ )\r
+{\r
+ External (PDC0, IntObj)\r
+ External (CFGD, FieldUnitObj)\r
+ External(\_PR.CPU0, DeviceObj)\r
+ External(_PSS)\r
+\r
+ Scope(\_PR.CPU0)\r
+ {\r
+ Method(_TPC,0)\r
+ {\r
+ Return(ZERO) // Return All States Available.\r
+ }\r
+\r
+ Name(TPTC, ResourceTemplate()\r
+ {\r
+ Memory32Fixed(ReadOnly, 0, 0, FIX1) // IO APIC\r
+ })\r
+\r
+ //\r
+ // If OSPM is capable of direct access to on demand throttling MSR,\r
+ // we use MSR method;otherwise we use IO method.\r
+ //\r
+ //\r
+ // PDCx[2] = Indicates whether OSPM is capable of direct access to\r
+ // on demand throttling MSR.\r
+ //\r
+ Method(_PTC, 0)\r
+ {\r
+ If(And(PDC0, 0x0004))\r
+ {\r
+ Return(Package() // MSR Method\r
+ {\r
+ ResourceTemplate(){Register(FFixedHW, 0, 0, 0)},\r
+ ResourceTemplate(){Register(FFixedHW, 0, 0, 0)}\r
+ }\r
+ )\r
+ }\r
+ Return(Package() // IO Method\r
+ {\r
+ //\r
+ // PM IO base ("PMBALVL0" will be updated at runtime)\r
+ //\r
+ ResourceTemplate(){Register(SystemIO, 4, 1, 0x304C564C41424D50)},\r
+ ResourceTemplate(){Register(SystemIO, 4, 1, 0x304C564C41424D50)}\r
+ }\r
+ )\r
+ }\r
+\r
+ //\r
+ // _TSS returned package for IO Method\r
+ //\r
+ Name(TSSI, Package()\r
+ {\r
+ Package(){100, 1000, 0, 0x00, 0}\r
+ }\r
+ )\r
+ //\r
+ // _TSS returned package for MSR Method\r
+ //\r
+ Name(TSSM, Package()\r
+ {\r
+ Package(){100, 1000, 0, 0x00, 0}\r
+ }\r
+ )\r
+\r
+ Method(_TSS, 0)\r
+ {\r
+ //\r
+ // If OSPM is capable of direct access to on demand throttling MSR,\r
+ // we report TSSM;otherwise report TSSI.\r
+ //\r
+ If(And(PDC0, 0x0004))\r
+ {\r
+ Return(TSSM)\r
+ }\r
+ Return(TSSI)\r
+ }\r
+\r
+ Method(_TSD, 0)\r
+ {\r
+ //\r
+ // If CMP is suppored, we report the dependency with two processors\r
+ //\r
+ If(LAnd(And(CFGD, 0x1000000), LNot(And(PDC0, 4))))\r
+ {\r
+ Return(Package()\r
+ {\r
+ Package()\r
+ {\r
+ 5, // # entries.\r
+ 0, // Revision.\r
+ 0, // Domain #.\r
+ 0xFD, // Coord Type- SW_ANY\r
+ 2 // # processors.\r
+ }\r
+ }\r
+ )\r
+ }\r
+ //\r
+ // Otherwise, we report the dependency with one processor\r
+ //\r
+ Return(Package()\r
+ {\r
+ Package()\r
+ {\r
+ 5, // # entries.\r
+ 0, // Revision.\r
+ 0, // Domain #.\r
+ 0xFC, // Coord Type- SW_ALL\r
+ 1 // # processors.\r
+ }\r
+ }\r
+ )\r
+ }\r
+ }\r
+}\r
--- /dev/null
+/** @file\r
+CPU power management control methods\r
+\r
+Copyright (c) 2013-2015 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+DefinitionBlock (\r
+ "CPUPM.aml",\r
+ "SSDT",\r
+ 0x01,\r
+ "SsgPmm",\r
+ "CpuPm",\r
+ 0x0010\r
+ )\r
+{\r
+ External(\_PR.CPU0, DeviceObj)\r
+ External(CFGD, FieldUnitObj)\r
+\r
+ Scope(\)\r
+ {\r
+ // Config DWord, modified during POST\r
+ // Bit definitions are the same as PPMFlags:\r
+ // CFGD[0] = PPM_GV3 = GV3\r
+ // CFGD[1] = PPM_TURBO = Turbo Mode\r
+ // CFGD[2] = PPM_SUPER_LFM = N/2 Ratio\r
+ // CFGD[4] = PPM_C1 = C1 Capable, Enabled\r
+ // CFGD[5] = PPM_C2 = C2 Capable, Enabled\r
+ // CFGD[6] = PPM_C3 = C3 Capable, Enabled\r
+ // CFGD[7] = PPM_C4 = C4 Capable, Enabled\r
+ // CFGD[8] = PPM_C5 = C5/Deep C4 Capable, Enabled\r
+ // CFGD[9] = PPM_C6 = C6 Capable, Enabled\r
+ // CFGD[10] = PPM_C1E = C1E Enabled\r
+ // CFGD[11] = PPM_C2E = C2E Enabled\r
+ // CFGD[12] = PPM_C3E = C3E Enabled\r
+ // CFGD[13] = PPM_C4E = C4E Enabled\r
+ // CFGD[14] = PPM_HARD_C4E = Hard C4E Capable, Enabled\r
+ // CFGD[16] = PPM_TM1 = Thermal Monitor 1\r
+ // CFGD[17] = PPM_TM2 = Thermal Monitor 2\r
+ // CFGD[19] = PPM_PHOT = Bi-directional ProcHot\r
+ // CFGD[21] = PPM_MWAIT_EXT = MWAIT extensions supported\r
+ // CFGD[24] = PPM_CMP = CMP supported, Enabled\r
+ // CFGD[28] = PPM_TSTATE = CPU T states supported\r
+ //\r
+ // Name(CFGD, 0x80000000)\r
+ // External Defined in GNVS\r
+\r
+ Name(PDC0,0x80000000) // CPU0 _PDC Flags.\r
+\r
+ // We load it in AcpiPlatform\r
+ //Name(SSDT,Package()\r
+ //{\r
+ // "CPU0IST ", 0x80000000, 0x80000000,\r
+ // "CPU1IST ", 0x80000000, 0x80000000,\r
+ // "CPU0CST ", 0x80000000, 0x80000000,\r
+ // "CPU1CST ", 0x80000000, 0x80000000,\r
+ //})\r
+ }\r
+ Scope(\_PR.CPU0)\r
+ {\r
+ Method(_PDC, 1)\r
+ {\r
+ //\r
+ // Store result of PDC.\r
+ //\r
+ CreateDWordField(Arg0,8,CAP0) // Point to 3rd DWORD.\r
+ Store(CAP0,PDC0) // Store It in PDC0.\r
+ }\r
+ }\r
+\r
+}\r
--- /dev/null
+/** @file\r
+Analog devices AD7298 ADC.\r
+\r
+Copyright (c) 2013-2015 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+Device(ADC1)\r
+{\r
+ Name(_HID, "INT3494") // Galileo Version 1 Low-Speed ADC.\r
+ Name(_CID, "INT3494")\r
+ Name(RBUF, ResourceTemplate()\r
+ {\r
+ // SPI0: mode 2, 4Mhz, 16-bit data length\r
+ SpiSerialBus (0x0000, PolarityLow, FourWireMode, 16, ControllerInitiated, 4000000, ClockPolarityHigh, ClockPhaseFirst, "\\_SB_.PCI0.SPI0",0x00, ResourceConsumer, ,)\r
+\r
+ // GPIO<0> is SPI0_CS_N\r
+ GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.PCI0.GIP0.GPO_", 0, ResourceConsumer, , ) {QUARK_GPIO0_MAPPING}\r
+ })\r
+ Method(_CRS, 0x0, NotSerialized)\r
+ {\r
+ Return(RBUF)\r
+ }\r
+ Method(_STA, 0x0, NotSerialized)\r
+ {\r
+ //\r
+ // Only Galileo platform has this device.\r
+ // EFI_PLATFORM_TYPE enum value Galileo = 6.\r
+ //\r
+ If(LNotEqual(PTYP, 6))\r
+ {\r
+ return (0)\r
+ }\r
+ Return(0xf)\r
+ }\r
+}\r
--- /dev/null
+/** @file\r
+TI ADC108S102 ADC.\r
+\r
+Copyright (c) 2013-2015 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+Device(ADC2)\r
+{\r
+ Name(_HID, "INT3495") // GalileoGen2 Low-Speed ADC.\r
+ Name(_CID, "INT3495")\r
+ Name(RBUF, ResourceTemplate()\r
+ {\r
+ SPISerialBus(0x0000, PolarityLow, ThreeWireMode, 0x10, ControllerInitiated, 0x1E8480, ClockPolarityLow, ClockPhaseFirst, "\\_SB.PCI0.SPI0", 0x00, ResourceConsumer, ,)\r
+ })\r
+ Method(_CRS, 0x0, NotSerialized)\r
+ {\r
+ Return(RBUF)\r
+ }\r
+ Method(_STA, 0x0, NotSerialized)\r
+ {\r
+ //\r
+ // Only Platform Type / Id 8 has this device.\r
+ //\r
+ If(LNotEqual(PTYP, 8))\r
+ {\r
+ return (0)\r
+ }\r
+ Return(0xf)\r
+ }\r
+}\r
--- /dev/null
+/** @file\r
+ONSEMI CAT24C08 I2C 8KB EEPROM.\r
+\r
+Copyright (c) 2013-2015 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+Device(EEP2)\r
+{\r
+ Name(_HID, "INT3499") // ONSEMI CAT24C08 I2C 8KB EEPROM.\r
+ Name(_CID, "INT3499")\r
+\r
+ Name(RBUF, ResourceTemplate()\r
+ {\r
+ I2CSerialBus(0x54, ControllerInitiated, 400000, AddressingMode7Bit, "\\_SB.PCI0.GIP0.I2C_", 0, ResourceConsumer, , )\r
+ })\r
+ Method(_CRS, 0x0, NotSerialized)\r
+ {\r
+ Return(RBUF)\r
+ }\r
+ Method(_STA, 0x0, NotSerialized)\r
+ {\r
+ //\r
+ // Only Platform Type / Id 8 has this device.\r
+ //\r
+ If(LNotEqual(PTYP, 8))\r
+ {\r
+ return (0)\r
+ }\r
+ Return(0xf)\r
+ }\r
+}\r
--- /dev/null
+/** @file\r
+\r
+Copyright (c) 2013-2015 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+CY8C9540A 40 Bit I/O Expander with EEPROM.\r
+\r
+**/\r
+\r
+Device(CY8C)\r
+{\r
+ Name(_HID, "INT3490") // Cypress CY8C9540A Io Expander Function.\r
+ Name(_CID, "INT3490")\r
+\r
+ Name(RBUF, ResourceTemplate()\r
+ {\r
+ I2CSerialBus(0x20, ControllerInitiated, 100000, AddressingMode7Bit, "\\_SB.PCI0.GIP0.I2C_", 0, ResourceConsumer, , )\r
+ GpioInt (Level, ActiveLow, Exclusive, PullDefault, , "\\_SB.PCI0.GIP0.GPO", 0, ResourceConsumer, , ) {QUARK_GPIO5_MAPPING} /* GPIO<5> is INT_S0 */\r
+ })\r
+ Method(_CRS, 0x0, NotSerialized)\r
+ {\r
+ CreateByteField(RBUF, 16, OB1)\r
+ if (LEqual (ALTS, 0))\r
+ {\r
+ Store(0x20, OB1)\r
+ }\r
+ Else\r
+ {\r
+ Store(0x21, OB1)\r
+ }\r
+ Return(RBUF)\r
+ }\r
+ Method(_STA, 0x0, NotSerialized)\r
+ {\r
+ //\r
+ // Only Galileo platform has this device.\r
+ // EFI_PLATFORM_TYPE enum value Galileo = 6.\r
+ //\r
+ If(LNotEqual(PTYP, 6))\r
+ {\r
+ return (0)\r
+ }\r
+ Return(0xf)\r
+ }\r
+}\r
+\r
--- /dev/null
+/** @file\r
+Expose GPIO resources to usermode through client driver.\r
+\r
+Copyright (c) 2013-2015 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+Device(GPOT)\r
+{\r
+ Name(_HID, "INT349A")\r
+ Name(_CID, "INT349A")\r
+ Method(_CRS, 0x0, NotSerialized)\r
+ {\r
+ Name(RBUF, ResourceTemplate()\r
+ {\r
+ GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.PCI0.GIP0.GPO_", 0, ResourceConsumer, , ) {0}\r
+ GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.PCI0.GIP0.GPO_", 0, ResourceConsumer, , ) {0x1}\r
+ GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.PCI0.GIP0.GPO_", 0, ResourceConsumer, , ) {0x2}\r
+ GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.PCI0.GIP0.GPO_", 0, ResourceConsumer, , ) {0x3}\r
+ GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.PCI0.GIP0.GPO_", 0, ResourceConsumer, , ) {0x4}\r
+ GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.PCI0.GIP0.GPO_", 0, ResourceConsumer, , ) {0x5}\r
+ GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.PCI0.GIP0.GPO_", 0, ResourceConsumer, , ) {0x6}\r
+ GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.PCI0.GIP0.GPO_", 0, ResourceConsumer, , ) {0x7}\r
+ GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.PCI0.GIP0.GPO_", 0, ResourceConsumer, , ) {0x8}\r
+ GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.PCI0.GIP0.GPO_", 0, ResourceConsumer, , ) {0x9}\r
+ GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.PCI0.GIP0.GPO_", 0, ResourceConsumer, , ) {0xa}\r
+ GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.PCI0.GIP0.GPO_", 0, ResourceConsumer, , ) {0xb}\r
+ GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.PCI0.GIP0.GPO_", 0, ResourceConsumer, , ) {0xc}\r
+ GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.PCI0.GIP0.GPO_", 0, ResourceConsumer, , ) {0xd}\r
+ GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.PCI0.GIP0.GPO_", 0, ResourceConsumer, , ) {0xe}\r
+ GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.PCI0.GIP0.GPO_", 0, ResourceConsumer, , ) {0xf}\r
+ GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0}\r
+ GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0x1}\r
+ GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0x2}\r
+ GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0x3}\r
+ GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0x4}\r
+ GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0x5}\r
+ GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0x6}\r
+ GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0x7}\r
+ GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0x8}\r
+ GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0x9}\r
+ GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0xa}\r
+ GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0xb}\r
+ GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0xc}\r
+ GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0xd}\r
+ GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0xe}\r
+ GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0xf}\r
+ GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0x10}\r
+ GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0x11}\r
+ GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0x12}\r
+ GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0x13}\r
+ GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0x14}\r
+ GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0x15}\r
+ GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0x16}\r
+ GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0x17}\r
+ GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0x18}\r
+ GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0x19}\r
+ GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0x1a}\r
+ GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0x1b}\r
+ GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0x1c}\r
+ GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0x1d}\r
+ GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0x1e}\r
+ GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0x1f}\r
+ GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0x20}\r
+ GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0x21}\r
+ GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0x22}\r
+ GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0x23}\r
+ GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0x24}\r
+ GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0x25}\r
+ GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0x26}\r
+ GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0x27}\r
+ })\r
+ Return(RBUF)\r
+ }\r
+ Method(_STA, 0x0, NotSerialized)\r
+ {\r
+ //\r
+ // Only Galileo platform has this device.\r
+ // EFI_PLATFORM_TYPE enum value Galileo = 6.\r
+ //\r
+ If(LNotEqual(PTYP, 6))\r
+ {\r
+ return (0)\r
+ }\r
+ Return(0xf)\r
+ }\r
+}\r
--- /dev/null
+/** @file\r
+Legacy resource template\r
+\r
+Copyright (c) 2013-2015 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#ifndef LPC_DEV_ASI\r
+#define LPC_DEV_ASI\r
+\r
+Device(RTC)\r
+{\r
+ Name(_HID,EISAID("PNP0B00"))\r
+ Name(BUF0,ResourceTemplate() {\r
+ IO(Decode16,0x70,0x70,0x01,0x04)\r
+ IO(Decode16,0x74,0x74,0x01,0x04)\r
+ })\r
+ Name(BUF1,ResourceTemplate() {\r
+ IO(Decode16,0x70,0x70,0x01,0x04)\r
+ IO(Decode16,0x74,0x74,0x01,0x04)\r
+ IRQNoFlags(){8}\r
+ })\r
+ Method(_CRS,0,Serialized)\r
+ {\r
+ If (HPEA)\r
+ {\r
+ return (BUF0)\r
+ }\r
+ Else\r
+ {\r
+ return (BUF1)\r
+ }\r
+ }\r
+}\r
+\r
+Device(PIC)\r
+{\r
+ Name(_HID,EISAID("PNP0000"))\r
+\r
+ Name(_CRS,ResourceTemplate() {\r
+ IO(Decode16,0x20,0x20,0x01,0x1E) // length of 1Eh includes all aliases\r
+ IO(Decode16,0xA0,0xA0,0x01,0x1E)\r
+ IO(Decode16,0x4D0,0x4D0,0x01,0x02)\r
+ })\r
+}\r
+\r
+Device(TMR)\r
+{\r
+ Name(_HID,EISAID("PNP0100"))\r
+\r
+ Name(BUF0,ResourceTemplate() {\r
+ IO(Decode16,0x40,0x40,0x01,0x04)\r
+ IO(Decode16,0x50,0x50,0x01,0x04) // alias\r
+ })\r
+ Name(BUF1,ResourceTemplate() {\r
+ IO(Decode16,0x40,0x40,0x01,0x04)\r
+ IO(Decode16,0x50,0x50,0x01,0x04) // alias\r
+ IRQNoFlags(){0}\r
+ })\r
+ Method(_CRS,0,Serialized)\r
+ {\r
+ If (HPEA)\r
+ {\r
+ return (BUF0)\r
+ }\r
+ Else\r
+ {\r
+ return (BUF1)\r
+ }\r
+ }\r
+}\r
+\r
+Device(SPKR)\r
+{\r
+ Name(_HID,EISAID("PNP0800"))\r
+\r
+ Name(_CRS,ResourceTemplate() {\r
+ IO(Decode16,0x61,0x61,0x01,0x01)\r
+ })\r
+}\r
+\r
+Device(XTRA) // all "PNP0C02" devices- pieces that don't fit anywhere else\r
+{\r
+ Name(_HID,EISAID("PNP0C02")) // Generic motherboard devices\r
+\r
+ Name(CRS,\r
+ ResourceTemplate()\r
+ {\r
+ IO(Decode16,0x2E,0x2E,0x01,0x02)\r
+ IO(Decode16,0x4E,0x2E,0x01,0x02)\r
+ IO(Decode16,0x63,0x61,0x01,0x01)\r
+ IO(Decode16,0x65,0x61,0x01,0x01)\r
+ IO(Decode16,0x67,0x61,0x01,0x01)\r
+ IO(Decode16,0x80,0x80,0x01,0x01)\r
+ IO(Decode16,0x84,0x84,0x01,0x04)\r
+ IO(Decode16,0x88,0x88,0x01,0x01)\r
+ IO(Decode16,0x8c,0x8c,0x01,0x03)\r
+ IO(Decode16,0x92,0x92,0x01,0x01)\r
+\r
+ IO(\r
+ Decode16,\r
+ 0,\r
+ 0,\r
+ 0x01,\r
+ 0x10,\r
+ FIX1\r
+ )\r
+\r
+ IO(\r
+ Decode16,\r
+ 0,\r
+ 0,\r
+ 0x01,\r
+ 0x10,\r
+ FIX2\r
+ )\r
+\r
+ IO(\r
+ Decode16,\r
+ 0,\r
+ 0,\r
+ 0x01,\r
+ 0x40,\r
+ FIX3\r
+ )\r
+\r
+ IO(\r
+ Decode16,\r
+ 0,\r
+ 0,\r
+ 0x01,\r
+ 0x40,\r
+ FIX5\r
+ )\r
+\r
+ IO(\r
+ Decode16,\r
+ 0,\r
+ 0,\r
+ 0x01,\r
+ 0x40,\r
+ FIX6\r
+ )\r
+\r
+ }\r
+ )\r
+\r
+ Method (_CRS, 0, NotSerialized) {\r
+ CreateWordField (CRS, ^FIX1._MIN, MBR0)\r
+ Store(\P1BB, MBR0)\r
+ CreateWordField (CRS, ^FIX1._MAX, MBR1)\r
+ Store(\P1BB, MBR1)\r
+ CreateWordField (CRS, ^FIX2._MIN, MBR2)\r
+ Store(\PBAB, MBR2)\r
+ CreateWordField (CRS, ^FIX2._MAX, MBR3)\r
+ Store(\PBAB, MBR3)\r
+ CreateWordField (CRS, ^FIX3._MIN, MBR4)\r
+ Store(\GP0B, MBR4)\r
+ CreateWordField (CRS, ^FIX3._MAX, MBR5)\r
+ Store(\GP0B, MBR5)\r
+ CreateWordField (CRS, ^FIX5._MIN, MBR8)\r
+ Store(\SMBB, MBR8)\r
+ CreateWordField (CRS, ^FIX5._MAX, MBR9)\r
+ Store(\SMBB, MBR9)\r
+ CreateWordField (CRS, ^FIX6._MIN, MBRA)\r
+ Store(\WDTB, MBRA)\r
+ CreateWordField (CRS, ^FIX6._MAX, MBRB)\r
+ Store(\WDTB, MBRB)\r
+ return (CRS)\r
+ }\r
+}\r
+\r
+Device(LGIO) // Legacy GPIO.\r
+{\r
+ Name(_HID, "INT3488")\r
+ Name(_CID, "INT3488")\r
+\r
+ Name(CRS,\r
+ ResourceTemplate()\r
+ {\r
+ IO(\r
+ Decode16,\r
+ 0,\r
+ 0,\r
+ 0x01,\r
+ 0x48,\r
+ FIX4\r
+ )\r
+ }\r
+ )\r
+\r
+ Method (_CRS, 0, NotSerialized) {\r
+ CreateWordField (CRS, ^FIX4._MIN, MBR6)\r
+ Store(\GPAB, MBR6)\r
+ CreateWordField (CRS, ^FIX4._MAX, MBR7)\r
+ Store(\GPAB, MBR7)\r
+ return (CRS)\r
+ }\r
+}\r
+\r
+Device(HPET) // High Performance Event Timer\r
+{\r
+ Name(_HID,EISAID("PNP0103"))\r
+\r
+ Name(BUF0,ResourceTemplate()\r
+ {\r
+ IRQNoFlags() {0}\r
+ IRQNoFlags() {8}\r
+ Memory32Fixed(ReadOnly, 0, 0, FIX1)\r
+ })\r
+\r
+ Method(_STA,0)\r
+ {\r
+ // Show this Device only if the OS is WINXP or beyond.\r
+\r
+ If(LGreaterEqual(OSTP,WINDOWS_XP))\r
+ {\r
+ If(HPEA)\r
+ {\r
+ Return(0x000F) // Enabled, do Display.\r
+ }\r
+ }\r
+ Else\r
+ {\r
+ // OS = WIN98, WINME, or WIN2000.\r
+\r
+ If(HPEA)\r
+ {\r
+ Return(0x000B) // Enabled, don't Display.\r
+ }\r
+ }\r
+\r
+ Return(0x0000) // Return Nothing.\r
+ }\r
+\r
+ Method(_CRS,0,Serialized)\r
+ {\r
+ CreateDWordField (BUF0, ^FIX1._BAS, MBR0)\r
+ Store(\HPTB, MBR0)\r
+ CreateDWordField (BUF0, ^FIX1._LEN, MBR1)\r
+ Store(\HPTS, MBR1)\r
+ Return(BUF0)\r
+ }\r
+}\r
+\r
+#endif\r
--- /dev/null
+/** @file\r
+NXP PCA9685 i2c-accessible PWM/LED controller.\r
+\r
+Copyright (c) 2013-2015 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+Device(PWM1)\r
+{\r
+ Name(_HID, "INT3492") // NXP PCA9685 i2c-accessible PWM/LED controller.\r
+ Name(_CID, "INT3492")\r
+\r
+ Name(RBUF, ResourceTemplate()\r
+ {\r
+ I2CSerialBus(0x47, ControllerInitiated, 400000, AddressingMode7Bit, "\\_SB.PCI0.GIP0.I2C_", 0, ResourceConsumer, , )\r
+ })\r
+ Method(_CRS, 0x0, NotSerialized)\r
+ {\r
+ Return(RBUF)\r
+ }\r
+ Method(_STA, 0x0, NotSerialized)\r
+ {\r
+ //\r
+ // Only Platform Type / Id 8 has this device.\r
+ //\r
+ If(LNotEqual(PTYP, 8))\r
+ {\r
+ return (0)\r
+ }\r
+ Return(0xf)\r
+ }\r
+}\r
--- /dev/null
+/** @file\r
+NXP PCAL9555A i2c-accessible I/O expander.\r
+\r
+Copyright (c) 2013-2015 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+Device(NIO1)\r
+{\r
+ Name(_HID, "INT3491") // NXP PCAL9555A i2c-accessible I/O expander.\r
+ Name(_CID, "INT3491")\r
+ Name(_UID, 1)\r
+\r
+ Name(RBUF, ResourceTemplate()\r
+ {\r
+ I2CSerialBus(0x25, ControllerInitiated, 400000, AddressingMode7Bit, "\\_SB.PCI0.GIP0.I2C_", 0, ResourceConsumer, , )\r
+ })\r
+ Method(_CRS, 0x0, NotSerialized)\r
+ {\r
+ Return(RBUF)\r
+ }\r
+ Method(_STA, 0x0, NotSerialized)\r
+ {\r
+ //\r
+ // Only Platform Type / Id 8 has this device.\r
+ //\r
+ If(LNotEqual(PTYP, 8))\r
+ {\r
+ return (0)\r
+ }\r
+ Return(0xf)\r
+ }\r
+}\r
+\r
+Device(NIO2)\r
+{\r
+ Name(_HID, "INT3491") // NXP PCAL9555A i2c-accessible I/O expander.\r
+ Name(_CID, "INT3491")\r
+ Name(_UID, 2)\r
+\r
+ Name(RBUF, ResourceTemplate()\r
+ {\r
+ I2CSerialBus(0x26, ControllerInitiated, 400000, AddressingMode7Bit, "\\_SB.PCI0.GIP0.I2C_", 0, ResourceConsumer, , )\r
+ })\r
+ Method(_CRS, 0x0, NotSerialized)\r
+ {\r
+ Return(RBUF)\r
+ }\r
+ Method(_STA, 0x0, NotSerialized)\r
+ {\r
+ //\r
+ // Only Platform Type / Id 8 has this device.\r
+ //\r
+ If(LNotEqual(PTYP, 8))\r
+ {\r
+ return (0)\r
+ }\r
+ Return(0xf)\r
+ }\r
+}\r
+\r
+Device(NIO3)\r
+{\r
+ Name(_HID, "INT3491") // NXP PCAL9555A i2c-accessible I/O expander.\r
+ Name(_CID, "INT3491")\r
+ Name(_UID, 3)\r
+\r
+ Name(RBUF, ResourceTemplate()\r
+ {\r
+ I2CSerialBus(0x27, ControllerInitiated, 400000, AddressingMode7Bit, "\\_SB.PCI0.GIP0.I2C_", 0, ResourceConsumer, , )\r
+ GpioInt (Level, ActiveLow, Exclusive, PullDefault, , "\\_SB.PCI0.GIP0.GPO", 0, ResourceConsumer, , ) {QUARK_GPIO1_MAPPING} /* GPIO<1> is EXP2_INT */\r
+ })\r
+ Method(_CRS, 0x0, NotSerialized)\r
+ {\r
+ Return(RBUF)\r
+ }\r
+ Method(_STA, 0x0, NotSerialized)\r
+ {\r
+ //\r
+ // Only Platform Type / Id 8 has this device.\r
+ //\r
+ If(LNotEqual(PTYP, 8))\r
+ {\r
+ return (0)\r
+ }\r
+ Return(0xf)\r
+ }\r
+}\r
--- /dev/null
+/** @file\r
+PCI Host Bridge Definitions\r
+\r
+Copyright (c) 2013-2015 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+\r
+Name(PBRS, ResourceTemplate() {\r
+ WORDBusNumber( //Bus number resource (0); the bridge produces bus numbers for its subsequent buses\r
+ ResourceProducer, // bit 0 of general flags is 1\r
+ MinFixed, // Range is fixed\r
+ MaxFixed, // Range is fixed\r
+ PosDecode, // PosDecode\r
+ 0x0000, // Granularity\r
+ 0x0000, // Min\r
+ 0x001f, // Max\r
+ 0x0000, // Translation\r
+ 0x0020 // Range Length = Max-Min+1\r
+ )\r
+\r
+ WORDIO( //Consumed-and-produced resource (all I/O below CF8)\r
+ ResourceProducer, // bit 0 of general flags is 0\r
+ MinFixed, // Range is fixed\r
+ MaxFixed, // Range is fixed\r
+ PosDecode,\r
+ EntireRange,\r
+ 0x0000, // Granularity\r
+ 0x0000, // Min\r
+ 0x0cf7, // Max\r
+ 0x0000, // Translation\r
+ 0x0cf8 // Range Length\r
+ )\r
+\r
+ IO( //Consumed resource (CF8-CFF)\r
+ Decode16,\r
+ 0x0cf8,\r
+ 0xcf8,\r
+ 1,\r
+ 8\r
+ )\r
+\r
+ WORDIO( //Consumed-and-produced resource (all I/O above CFF)\r
+ ResourceProducer, // bit 0 of general flags is 0\r
+ MinFixed, // Range is fixed\r
+ MaxFixed, // Range is fixed\r
+ PosDecode,\r
+ EntireRange,\r
+ 0x0000, // Granularity\r
+ 0x0d00, // Min\r
+ 0xffff, // Max\r
+ 0x0000, // Translation\r
+ 0xf300 // Range Length\r
+ )\r
+\r
+ DWORDMEMORY( // descriptor for dos area(0->0xa0000)\r
+ ResourceProducer, // bit 0 of general flags is 0\r
+ PosDecode,\r
+ MinFixed, // Range is fixed\r
+ MaxFixed, // Range is Fixed\r
+ Cacheable,\r
+ ReadWrite,\r
+ 0x00000000, // Granularity\r
+ 0x000a0000, // Min\r
+ 0x000bffff, // Max\r
+ 0x00000000, // Translation\r
+ 0x00020000 // Range Length\r
+ )\r
+\r
+ DWORDMemory( // Consumed-and-produced resource for pci memory mapped memory\r
+ ResourceProducer, // bit 0 of general flags is 0\r
+ PosDecode, // positive Decode\r
+ MinFixed, // Range is fixed\r
+ MaxFixed, // Range is fixed\r
+ Cacheable,\r
+ ReadWrite,\r
+ 0x00000000, // Granularity\r
+ 0x00000000, // Min (calculated dynamically)\r
+\r
+ 0xfebfffff, // Max = IO Apic base address - 1\r
+ 0x00000000, // Translation\r
+ 0xfec00000, // Range Length (calculated dynamically)\r
+ , // Optional field left blank\r
+ , // Optional field left blank\r
+ MEM1 // Name declaration for this descriptor\r
+ )\r
+\r
+}) // end of CRES Buffer\r
+\r
+\r
+Method(_CRS, 0x0, NotSerialized)\r
+{\r
+ CreateDWordField(PBRS, \_SB.PCI0.MEM1._MIN, MMIN)\r
+ CreateDWordField(PBRS, \_SB.PCI0.MEM1._MAX, MMAX)\r
+ CreateDWordField(PBRS, \_SB.PCI0.MEM1._LEN, MLEN)\r
+\r
+ // HMBOUND is PCI memory base\r
+ And(MNRD(0x03, 0x08), 0xFFFFF000, MMIN)\r
+ Add(Subtract(MMAX, MMIN), 1, MLEN)\r
+\r
+ Return(PBRS)\r
+}\r
+\r
+// Message Nework Registers\r
+OperationRegion(MNR, PCI_Config, 0xD0, 0x10)\r
+Field(MNR, DWordAcc, NoLock, Preserve)\r
+{\r
+ MCR, 32, // Message Control Register\r
+ MDR, 32 // Message Data Register\r
+}\r
+\r
+// Message Nework Read Method\r
+// Arg0 = Port\r
+// Arg1 = RegAddress\r
+// return 32 bit register value\r
+Method(MNRD, 2, Serialized)\r
+{\r
+ Or(ShiftLeft(Arg0, 16), ShiftLeft(Arg1, 8), Local0)\r
+ Or(Local0, 0x100000F0, Local0)\r
+ Store(Local0, MCR)\r
+ Return(MDR)\r
+}\r
+\r
+// Message Nework Write Method\r
+// Arg0 = Port\r
+// Arg1 = RegAddress\r
+// Arg2 = 32 bit write value\r
+Method(MNWR, 3, Serialized)\r
+{\r
+ Store(Arg2, MDR)\r
+ Or(ShiftLeft(Arg0, 16), ShiftLeft(Arg1, 8), Local0)\r
+ Or(Local0, 0x110000F0, Local0)\r
+ Store(Local0, MCR)\r
+}\r
+\r
+Method(_PRT, 0, NotSerialized)\r
+{\r
+ If (LEqual(\GPIC, Zero)) // 8259 Interrupt Routing\r
+ {\r
+ Return (\r
+ Package()\r
+ {\r
+ // Bus 0, Device 20 - IOSFAHB Bridge\r
+ Package() {0x0014ffff, 0, \_SB.PCI0.LPC.LNKA, 0}, // INTA\r
+ Package() {0x0014ffff, 1, \_SB.PCI0.LPC.LNKB, 0}, // INTB\r
+ Package() {0x0014ffff, 2, \_SB.PCI0.LPC.LNKC, 0}, // INTC\r
+ Package() {0x0014ffff, 3, \_SB.PCI0.LPC.LNKD, 0}, // INTD\r
+\r
+ // Bus 0, Device 21 - IOSFAHB Bridge\r
+ Package() {0x0015ffff, 0, \_SB.PCI0.LPC.LNKA, 0}, // INTA\r
+ Package() {0x0015ffff, 1, \_SB.PCI0.LPC.LNKB, 0}, // INTB\r
+ Package() {0x0015ffff, 2, \_SB.PCI0.LPC.LNKC, 0}, // INTC\r
+ Package() {0x0015ffff, 3, \_SB.PCI0.LPC.LNKD, 0}, // INTD\r
+\r
+ // Bus 0, Device 23 - PCIe port 0\r
+ Package() {0x0017ffff, 0, \_SB.PCI0.LPC.LNKE, 0}, // INTA\r
+ Package() {0x0017ffff, 1, \_SB.PCI0.LPC.LNKF, 0}, // INTB\r
+ Package() {0x0017ffff, 2, \_SB.PCI0.LPC.LNKG, 0}, // INTC\r
+ Package() {0x0017ffff, 3, \_SB.PCI0.LPC.LNKH, 0}, // INTD\r
+\r
+ // Bus 0, Device 31\r
+ Package() {0x001fffff, 0, \_SB.PCI0.LPC.LNKA, 0}, // LPC Bridge\r
+ }\r
+ )\r
+ }\r
+ else {\r
+ Return (\r
+ Package()\r
+ {\r
+ // Bus 0, Device 20 - IOSFAHB Bridge\r
+ Package() {0x0014ffff, 0, 0, 16}, // INTA\r
+ Package() {0x0014ffff, 1, 0, 17}, // INTB\r
+ Package() {0x0014ffff, 2, 0, 18}, // INTC\r
+ Package() {0x0014ffff, 3, 0, 19}, // INTD\r
+\r
+ // Bus 0, Device 21 - IOSFAHB Bridge\r
+ Package() {0x0015ffff, 0, 0, 16}, // INTA\r
+ Package() {0x0015ffff, 1, 0, 17}, // INTB\r
+ Package() {0x0015ffff, 2, 0, 18}, // INTC\r
+ Package() {0x0015ffff, 3, 0, 19}, // INTD\r
+\r
+ // Bus 0, Device 23 - PCIe port 0\r
+ Package() {0x0017ffff, 0, 0, 20}, // INTA\r
+ Package() {0x0017ffff, 1, 0, 21}, // INTB\r
+ Package() {0x0017ffff, 2, 0, 22}, // INTC\r
+ Package() {0x0017ffff, 3, 0, 23}, // INTD\r
+\r
+ // Bus 0, Device 31\r
+ Package() {0x001fffff, 0, 0, 16}, // LPC Bridge\r
+ }\r
+ )\r
+ }\r
+}\r
--- /dev/null
+/** @file\r
+\r
+Copyright (c) 2013-2015 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+\r
+// Interrupts can be DEB8=all except 13,8,6,2,1,0\r
+\r
+#ifndef PCIIRQ_ASI\r
+#define PCIIRQ_ASI\r
+\r
+OperationRegion(PRR0, PCI_Config, 0x60, 0x08)\r
+Field(PRR0, ANYACC, NOLOCK, PRESERVE)\r
+{\r
+ PIRA, 8,\r
+ PIRB, 8,\r
+ PIRC, 8,\r
+ PIRD, 8,\r
+ PIRE, 8,\r
+ PIRF, 8,\r
+ PIRG, 8,\r
+ PIRH, 8\r
+}\r
+\r
+Device(LNKA) // PCI IRQ link A\r
+{\r
+ Name(_HID,EISAID("PNP0C0F"))\r
+\r
+ Name(_UID, 1)\r
+\r
+ Method(_STA,0,NotSerialized)\r
+ {\r
+ If(And(PIRA, 0x80))\r
+ {\r
+ Return(0x9)\r
+ }\r
+ Else\r
+ {\r
+ Return(0xB)\r
+ } // Don't display\r
+ }\r
+\r
+ Method(_DIS,0,NotSerialized)\r
+ {\r
+ Or(PIRA, 0x80, PIRA)\r
+ }\r
+\r
+ Method(_CRS,0,Serialized)\r
+ {\r
+ Name(BUF0,\r
+ ResourceTemplate()\r
+ {IRQ(Level,ActiveLow,Shared){0}})\r
+\r
+ // Define references to buffer elements\r
+ CreateWordField (BUF0, 0x01, IRQW) // IRQ low\r
+ // Write current settings into IRQ descriptor\r
+ If (And(PIRA, 0x80))\r
+ {\r
+ Store(Zero, Local0)\r
+ }\r
+ Else\r
+ {\r
+ Store(One,Local0)\r
+ }\r
+ // Shift 1 by value in register 70\r
+ ShiftLeft(Local0,And(PIRA,0x0F),IRQW) // Save in buffer\r
+ Return(BUF0) // Return Buf0\r
+ } // End of _CRS method\r
+\r
+ Name(_PRS,\r
+ ResourceTemplate()\r
+ {IRQ(Level,ActiveLow,Shared){12,11,10,9,7,5,4,3}})\r
+\r
+ Method(_SRS,1,NotSerialized)\r
+ {\r
+ CreateWordField (ARG0, 0x01, IRQW) // IRQ low\r
+\r
+ FindSetRightBit(IRQW,Local0) // Set IRQ\r
+ If (LNotEqual(IRQW,Zero))\r
+ {\r
+ And(Local0, 0x7F,Local0)\r
+ Decrement(Local0)\r
+ }\r
+ Else\r
+ {\r
+ Or(Local0, 0x80,Local0)\r
+ }\r
+ store(Local0, PIRA)\r
+ } // End of _SRS Method\r
+}\r
+\r
+Device(LNKB) // PCI IRQ link B\r
+{\r
+ Name(_HID,EISAID("PNP0C0F"))\r
+\r
+ Name(_UID, 2)\r
+\r
+ Method(_STA,0,NotSerialized)\r
+ {\r
+ If(And(PIRB, 0x80))\r
+ {\r
+ Return(0x9)\r
+ }\r
+ Else\r
+ {\r
+ Return(0xB)\r
+ } // Don't display\r
+ }\r
+\r
+ Method(_DIS,0,NotSerialized)\r
+ {\r
+ Or(PIRB, 0x80,PIRB)\r
+ }\r
+\r
+ Method(_CRS,0,Serialized)\r
+ {\r
+ Name(BUF0,\r
+ ResourceTemplate()\r
+ {IRQ(Level,ActiveLow,Shared){0}})\r
+ // Define references to buffer elements\r
+ CreateWordField (BUF0, 0x01, IRQW) // IRQ low\r
+ // Write current settings into IRQ descriptor\r
+ If (And(PIRB, 0x80))\r
+ {\r
+ Store(Zero, Local0)\r
+ }\r
+ Else\r
+ {\r
+ Store(One,Local0)\r
+ }\r
+ // Shift 1 by value in register 70\r
+ ShiftLeft(Local0,And(PIRB,0x0F),IRQW) // Save in buffer\r
+ Return(BUF0) // Return Buf0\r
+ } // End of _CRS method\r
+\r
+ Name(_PRS,\r
+ ResourceTemplate()\r
+ {IRQ(Level,ActiveLow,Shared){12,11,10,9,7,5,4,3}})\r
+\r
+ Method(_SRS,1,NotSerialized)\r
+ {\r
+ CreateWordField (ARG0, 0x01, IRQW) // IRQ low\r
+\r
+ FindSetRightBit(IRQW,Local0) // Set IRQ\r
+ If (LNotEqual(IRQW,Zero))\r
+ {\r
+ And(Local0, 0x7F,Local0)\r
+ Decrement(Local0)\r
+ }\r
+ Else\r
+ {\r
+ Or(Local0, 0x80,Local0)\r
+ }\r
+ Store(Local0, PIRB)\r
+ } // End of _SRS Method\r
+}\r
+\r
+Device(LNKC) // PCI IRQ link C\r
+{\r
+ Name(_HID,EISAID("PNP0C0F"))\r
+\r
+ Name(_UID, 3)\r
+\r
+ Method(_STA,0,NotSerialized)\r
+ {\r
+ If(And(PIRC, 0x80))\r
+ {\r
+ Return(0x9)\r
+ }\r
+ Else\r
+ {\r
+ Return(0xB)\r
+ } // Don't display\r
+ }\r
+\r
+ Method(_DIS,0,NotSerialized)\r
+ {\r
+ Or(PIRC, 0x80,PIRC)\r
+ }\r
+\r
+ Method(_CRS,0,Serialized)\r
+ {\r
+ Name(BUF0,\r
+ ResourceTemplate()\r
+ {IRQ(Level,ActiveLow,Shared){0}})\r
+ // Define references to buffer elements\r
+ CreateWordField (BUF0, 0x01, IRQW) // IRQ low\r
+ // Write current settings into IRQ descriptor\r
+ If (And(PIRC, 0x80))\r
+ {\r
+ Store(Zero, Local0)\r
+ }\r
+ Else\r
+ {\r
+ Store(One,Local0)\r
+ } // Shift 1 by value in register 70\r
+ ShiftLeft(Local0,And(PIRC,0x0F),IRQW) // Save in buffer\r
+ Return(BUF0) // Return Buf0\r
+ } // End of _CRS method\r
+\r
+ Name(_PRS,\r
+ ResourceTemplate()\r
+ {IRQ(Level,ActiveLow,Shared){12,11,10,9,7,5,4,3}})\r
+\r
+ Method(_SRS,1,NotSerialized)\r
+ {\r
+ CreateWordField (ARG0, 0x01, IRQW) // IRQ low\r
+\r
+ FindSetRightBit(IRQW,Local0) // Set IRQ\r
+ If (LNotEqual(IRQW,Zero))\r
+ {\r
+ And(Local0, 0x7F,Local0)\r
+ Decrement(Local0)\r
+ }\r
+ Else {\r
+ Or(Local0, 0x80,Local0)\r
+ }\r
+ Store(Local0, PIRC)\r
+ } // End of _SRS Method\r
+}\r
+\r
+Device(LNKD) // PCI IRQ link D\r
+{\r
+ Name(_HID,EISAID("PNP0C0F"))\r
+\r
+ Name(_UID, 4)\r
+\r
+ Method(_STA,0,NotSerialized)\r
+ {\r
+ If(And(PIRD, 0x80))\r
+ {\r
+ Return(0x9)\r
+ }\r
+ Else\r
+ {\r
+ Return(0xB)\r
+ } // Don't display\r
+ }\r
+\r
+ Method(_DIS,0,NotSerialized)\r
+ {\r
+ Or(PIRD, 0x80,PIRD)\r
+ }\r
+\r
+ Method(_CRS,0,Serialized)\r
+ {\r
+ Name(BUF0,\r
+ ResourceTemplate()\r
+ {IRQ(Level,ActiveLow,Shared){0}})\r
+ // Define references to buffer elements\r
+ CreateWordField (BUF0, 0x01, IRQW) // IRQ low\r
+ // Write current settings into IRQ descriptor\r
+ If (And(PIRD, 0x80))\r
+ {\r
+ Store(Zero, Local0)\r
+ }\r
+ Else\r
+ {\r
+ Store(One,Local0)\r
+ } // Shift 1 by value in register 70\r
+ ShiftLeft(Local0,And(PIRD,0x0F),IRQW) // Save in buffer\r
+ Return(BUF0) // Return Buf0\r
+ } // End of _CRS method\r
+\r
+ Name(_PRS,\r
+ ResourceTemplate()\r
+ {IRQ(Level,ActiveLow,Shared){12,11,10,9,7,5,4,3}})\r
+\r
+ Method(_SRS,1,NotSerialized)\r
+ {\r
+ CreateWordField (ARG0, 0x01, IRQW) // IRQ low\r
+\r
+ FindSetRightBit(IRQW,Local0)// Set IRQ\r
+ If (LNotEqual(IRQW,Zero))\r
+ {\r
+ And(Local0, 0x7F,Local0)\r
+ Decrement(Local0)\r
+ }\r
+ Else\r
+ {\r
+ Or(Local0, 0x80,Local0)\r
+ }\r
+ Store(Local0, PIRD)\r
+ } // End of _SRS Method\r
+}\r
+\r
+Device(LNKE) // PCI IRQ link E\r
+{\r
+ Name(_HID,EISAID("PNP0C0F"))\r
+\r
+ Name(_UID, 5)\r
+\r
+ Method(_STA,0,NotSerialized)\r
+ {\r
+ If(And(PIRE, 0x80))\r
+ {\r
+ Return(0x9)\r
+ }\r
+ Else\r
+ {\r
+ Return(0xB)\r
+ } // Don't display\r
+ }\r
+\r
+ Method(_DIS,0,NotSerialized)\r
+ {\r
+ Or(PIRE, 0x80, PIRE)\r
+ }\r
+\r
+ Method(_CRS,0,Serialized)\r
+ {\r
+ Name(BUF0,\r
+ ResourceTemplate()\r
+ {IRQ(Level,ActiveLow,Shared){0}})\r
+\r
+ // Define references to buffer elements\r
+ CreateWordField (BUF0, 0x01, IRQW) // IRQ low\r
+ // Write current settings into IRQ descriptor\r
+ If (And(PIRE, 0x80))\r
+ {\r
+ Store(Zero, Local0)\r
+ }\r
+ Else\r
+ {\r
+ Store(One,Local0)\r
+ }\r
+ // Shift 1 by value in register 70\r
+ ShiftLeft(Local0,And(PIRE,0x0F),IRQW) // Save in buffer\r
+ Return(BUF0) // Return Buf0\r
+ } // End of _CRS method\r
+\r
+ Name(_PRS,\r
+ ResourceTemplate()\r
+ {IRQ(Level,ActiveLow,Shared){12,11,10,9,7,5,4,3}})\r
+\r
+ Method(_SRS,1,NotSerialized)\r
+ {\r
+ CreateWordField (ARG0, 0x01, IRQW) // IRQ low\r
+\r
+ FindSetRightBit(IRQW,Local0) // Set IRQ\r
+ If (LNotEqual(IRQW,Zero))\r
+ {\r
+ And(Local0, 0x7F,Local0)\r
+ Decrement(Local0)\r
+ }\r
+ Else\r
+ {\r
+ Or(Local0, 0x80,Local0)\r
+ }\r
+ store(Local0, PIRE)\r
+ } // End of _SRS Method\r
+}\r
+\r
+Device(LNKF) // PCI IRQ link F\r
+{\r
+ Name(_HID,EISAID("PNP0C0F"))\r
+\r
+ Name(_UID, 6)\r
+\r
+ Method(_STA,0,NotSerialized)\r
+ {\r
+ If(And(PIRF, 0x80))\r
+ {\r
+ Return(0x9)\r
+ }\r
+ Else\r
+ {\r
+ Return(0xB)\r
+ } // Don't display\r
+ }\r
+\r
+ Method(_DIS,0,NotSerialized)\r
+ {\r
+ Or(PIRB, 0x80,PIRF)\r
+ }\r
+\r
+ Method(_CRS,0,Serialized)\r
+ {\r
+ Name(BUF0,\r
+ ResourceTemplate()\r
+ {IRQ(Level,ActiveLow,Shared){0}})\r
+ // Define references to buffer elements\r
+ CreateWordField (BUF0, 0x01, IRQW) // IRQ low\r
+ // Write current settings into IRQ descriptor\r
+ If (And(PIRF, 0x80))\r
+ {\r
+ Store(Zero, Local0)\r
+ }\r
+ Else\r
+ {\r
+ Store(One,Local0)\r
+ }\r
+ // Shift 1 by value in register 70\r
+ ShiftLeft(Local0,And(PIRF,0x0F),IRQW) // Save in buffer\r
+ Return(BUF0) // Return Buf0\r
+ } // End of _CRS method\r
+\r
+ Name(_PRS,\r
+ ResourceTemplate()\r
+ {IRQ(Level,ActiveLow,Shared){12,11,10,9,7,5,4,3}})\r
+\r
+ Method(_SRS,1,NotSerialized)\r
+ {\r
+ CreateWordField (ARG0, 0x01, IRQW) // IRQ low\r
+\r
+ FindSetRightBit(IRQW,Local0) // Set IRQ\r
+ If (LNotEqual(IRQW,Zero))\r
+ {\r
+ And(Local0, 0x7F,Local0)\r
+ Decrement(Local0)\r
+ }\r
+ Else\r
+ {\r
+ Or(Local0, 0x80,Local0)\r
+ }\r
+ Store(Local0, PIRF)\r
+ } // End of _SRS Method\r
+}\r
+\r
+Device(LNKG) // PCI IRQ link G\r
+{\r
+ Name(_HID,EISAID("PNP0C0F"))\r
+\r
+ Name(_UID, 7)\r
+\r
+ Method(_STA,0,NotSerialized)\r
+ {\r
+ If(And(PIRG, 0x80))\r
+ {\r
+ Return(0x9)\r
+ }\r
+ Else\r
+ {\r
+ Return(0xB)\r
+ } // Don't display\r
+ }\r
+\r
+ Method(_DIS,0,NotSerialized)\r
+ {\r
+ Or(PIRG, 0x80,PIRG)\r
+ }\r
+\r
+ Method(_CRS,0,Serialized)\r
+ {\r
+ Name(BUF0,\r
+ ResourceTemplate()\r
+ {IRQ(Level,ActiveLow,Shared){0}})\r
+ // Define references to buffer elements\r
+ CreateWordField (BUF0, 0x01, IRQW) // IRQ low\r
+ // Write current settings into IRQ descriptor\r
+ If (And(PIRG, 0x80))\r
+ {\r
+ Store(Zero, Local0)\r
+ }\r
+ Else\r
+ {\r
+ Store(One,Local0)\r
+ } // Shift 1 by value in register 70\r
+ ShiftLeft(Local0,And(PIRG,0x0F),IRQW) // Save in buffer\r
+ Return(BUF0) // Return Buf0\r
+ } // End of _CRS method\r
+\r
+ Name(_PRS,\r
+ ResourceTemplate()\r
+ {IRQ(Level,ActiveLow,Shared){12,11,10,9,7,5,4,3}})\r
+\r
+ Method(_SRS,1,NotSerialized)\r
+ {\r
+ CreateWordField (ARG0, 0x01, IRQW) // IRQ low\r
+\r
+ FindSetRightBit(IRQW,Local0) // Set IRQ\r
+ If (LNotEqual(IRQW,Zero))\r
+ {\r
+ And(Local0, 0x7F,Local0)\r
+ Decrement(Local0)\r
+ }\r
+ Else {\r
+ Or(Local0, 0x80,Local0)\r
+ }\r
+ Store(Local0, PIRG)\r
+ } // End of _SRS Method\r
+}\r
+\r
+Device(LNKH) // PCI IRQ link H\r
+{\r
+ Name(_HID,EISAID("PNP0C0F"))\r
+\r
+ Name(_UID, 8)\r
+\r
+ Method(_STA,0,NotSerialized)\r
+ {\r
+ If(And(PIRH, 0x80))\r
+ {\r
+ Return(0x9)\r
+ }\r
+ Else\r
+ {\r
+ Return(0xB)\r
+ } // Don't display\r
+ }\r
+\r
+ Method(_DIS,0,NotSerialized)\r
+ {\r
+ Or(PIRH, 0x80,PIRH)\r
+ }\r
+\r
+ Method(_CRS,0,Serialized)\r
+ {\r
+ Name(BUF0,\r
+ ResourceTemplate()\r
+ {IRQ(Level,ActiveLow,Shared){0}})\r
+ // Define references to buffer elements\r
+ CreateWordField (BUF0, 0x01, IRQW) // IRQ low\r
+ // Write current settings into IRQ descriptor\r
+ If (And(PIRH, 0x80))\r
+ {\r
+ Store(Zero, Local0)\r
+ }\r
+ Else\r
+ {\r
+ Store(One,Local0)\r
+ } // Shift 1 by value in register 70\r
+ ShiftLeft(Local0,And(PIRH,0x0F),IRQW) // Save in buffer\r
+ Return(BUF0) // Return Buf0\r
+ } // End of _CRS method\r
+\r
+ Name(_PRS,\r
+ ResourceTemplate()\r
+ {IRQ(Level,ActiveLow,Shared){12,11,10,9,7,5,4,3}})\r
+\r
+ Method(_SRS,1,NotSerialized)\r
+ {\r
+ CreateWordField (ARG0, 0x01, IRQW) // IRQ low\r
+\r
+ FindSetRightBit(IRQW,Local0)// Set IRQ\r
+ If (LNotEqual(IRQW,Zero))\r
+ {\r
+ And(Local0, 0x7F,Local0)\r
+ Decrement(Local0)\r
+ }\r
+ Else\r
+ {\r
+ Or(Local0, 0x80,Local0)\r
+ }\r
+ Store(Local0, PIRH)\r
+ } // End of _SRS Method\r
+}\r
+\r
+#endif\r
--- /dev/null
+/** @file\r
+PCI express expansion ports\r
+\r
+Copyright (c) 2013-2015 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#ifndef PcieExpansionPrt_asi\r
+#define PcieExpansionPrt_asi\r
+\r
+Device (PEX0) // PCI express bus bridged from [Bus 0, Device 23, Function 0]\r
+{\r
+ Name(_ADR,0x00170000) // Device (HI WORD)=23, Func (LO WORD)=0\r
+ Name(_PRW,Package(){0x11,0x03}) // GPE pin 0x11, Wake from S3 -- PCI PME#\r
+\r
+ OperationRegion (PES0,PCI_Config,0x40,0xA0)\r
+ Field (PES0, AnyAcc, NoLock, Preserve)\r
+ {\r
+ Offset(0x1A), // SLSTS - Slot Status Register\r
+ ABP0, 1, // Bit 0, Attention Button Pressed\r
+ , 2,\r
+ PDC0, 1, // Bit 3, Presence Detect Changed\r
+ , 2,\r
+ PDS0, 1, // Bit 6, Presence Detect State\r
+ , 1,\r
+ LSC0, 1, // Bit 8, Link Active State Changed\r
+ offset (0x20),\r
+ , 16,\r
+ PMS0, 1, // Bit 16, PME Status\r
+ offset (0x98),\r
+ , 30,\r
+ HPE0, 1, // Bit 30, Hot Plug SCI Enable\r
+ PCE0, 1, // Bit 31, Power Management SCI Enable.\r
+ , 30,\r
+ HPS0, 1, // Bit 30, Hot Plug SCI Status\r
+ PCS0, 1, // Bit 31, Power Management SCI Status.\r
+ }\r
+\r
+ Method(_PRT,0,NotSerialized) {\r
+ If (LEqual(\GPIC, Zero)) // 8259 Interrupt Routing\r
+ {\r
+ Return (\r
+ Package()\r
+ {\r
+ // Port 0: INTA->PIRQE,INTB->PIRQF,INTC->PIRQG,INTD->PIRQH\r
+ Package() {0x0000ffff, 0, \_SB_.PCI0.LPC.LNKE, 0}, // PCI Slot 1\r
+ Package() {0x0000ffff, 1, \_SB_.PCI0.LPC.LNKF, 0},\r
+ Package() {0x0000ffff, 2, \_SB_.PCI0.LPC.LNKG, 0},\r
+ Package() {0x0000ffff, 3, \_SB_.PCI0.LPC.LNKH, 0},\r
+ }\r
+ )\r
+ }\r
+ else // IOAPIC Routing\r
+ {\r
+ Return (\r
+ Package()\r
+ {\r
+ // Port 0: INTA->PIRQE,INTB->PIRQF,INTC->PIRQG,INTD->PIRQH\r
+ Package() {0x0000ffff, 0, 0, 20}, // PCI Slot 1\r
+ Package() {0x0000ffff, 1, 0, 21},\r
+ Package() {0x0000ffff, 2, 0, 22},\r
+ Package() {0x0000ffff, 3, 0, 23},\r
+ }\r
+ )\r
+ }\r
+ }\r
+}\r
+\r
+Device (PEX1) // PCI express bus bridged from [Bus 0, Device 23, Function 1]\r
+{\r
+ Name(_ADR,0x00170001) // Device (HI WORD)=23, Func (LO WORD)=1\r
+ Name(_PRW,Package(){0x11,0x03}) // GPE pin 0x11, Wake from S3 -- PCI PME#\r
+ OperationRegion (PES1,PCI_Config,0x40,0xA0)\r
+ Field (PES1, AnyAcc, NoLock, Preserve)\r
+ {\r
+ Offset(0x1A), // SLSTS - Slot Status Register\r
+ ABP1, 1, // Bit 0, Attention Button Pressed\r
+ , 2,\r
+ PDC1, 1, // Bit 3, Presence Detect Changed\r
+ , 2,\r
+ PDS1, 1, // Bit 6, Presence Detect State\r
+ , 1,\r
+ LSC1, 1, // Bit 8, Link Active State Changed\r
+ offset (0x20),\r
+ , 16,\r
+ PMS1, 1, // Bit 16, PME Status\r
+ offset (0x98),\r
+ , 30,\r
+ HPE1, 1, // Bit 30, Hot Plug SCI Enable\r
+ PCE1, 1, // Bit 31, Power Management SCI Enable.\r
+ , 30,\r
+ HPS1, 1, // Bit 30, Hot Plug SCI Status\r
+ PCS1, 1, // Bit 31, Power Management SCI Status.\r
+ }\r
+ Method(_PRT,0,NotSerialized) {\r
+ If (LEqual(\GPIC, Zero)) // 8259 Interrupt Routing\r
+ {\r
+ Return (\r
+ Package()\r
+ {\r
+ // Port 1: INTA->PIRQF,INTB->PIRQG,INTC->PIRQH,INTD->PIRQE\r
+ Package() {0x0000ffff, 0, \_SB_.PCI0.LPC.LNKF, 0},\r
+ Package() {0x0000ffff, 1, \_SB_.PCI0.LPC.LNKG, 0},\r
+ Package() {0x0000ffff, 2, \_SB_.PCI0.LPC.LNKH, 0},\r
+ Package() {0x0000ffff, 3, \_SB_.PCI0.LPC.LNKE, 0},\r
+ }\r
+ )\r
+ }\r
+ else // IOAPIC Routing\r
+ {\r
+ Return (\r
+ Package()\r
+ {\r
+ // Port 1: INTA->PIRQF,INTB->PIRQG,INTC->PIRQH,INTD->PIRQE\r
+ Package() {0x0000ffff, 0, 0, 21},\r
+ Package() {0x0000ffff, 1, 0, 22},\r
+ Package() {0x0000ffff, 2, 0, 23},\r
+ Package() {0x0000ffff, 3, 0, 20},\r
+ }\r
+ )\r
+ }\r
+ }\r
+}\r
+\r
+#endif\r
--- /dev/null
+/** @file\r
+Contains root level name space objects for the platform\r
+\r
+Copyright (c) 2013-2015 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+//\r
+// OS TYPE DEFINITION\r
+//\r
+#define WINDOWS_XP 0x01\r
+#define WINDOWS_XP_SP1 0x02\r
+#define WINDOWS_XP_SP2 0x04\r
+#define WINDOWS_2003 0x08\r
+#define WINDOWS_Vista 0x10\r
+#define WINDOWS_WIN7 0x11\r
+#define WINDOWS_WIN8 0x12\r
+#define WINDOWS_WIN8_1 0x13\r
+#define LINUX 0xF0\r
+\r
+//\r
+// GPIO Interrupt Connection Resource Descriptor (GpioInt) usage.\r
+// GpioInt() descriptors maybe used in this file and included .asi files.\r
+//\r
+// The mapping below was provided by the first OS user that requested\r
+// GpioInt() support.\r
+// Other OS users that need GpioInt() support must use the following mapping.\r
+//\r
+#define QUARK_GPIO8_MAPPING 0x00\r
+#define QUARK_GPIO9_MAPPING 0x01\r
+#define QUARK_GPIO_SUS0_MAPPING 0x02\r
+#define QUARK_GPIO_SUS1_MAPPING 0x03\r
+#define QUARK_GPIO_SUS2_MAPPING 0x04\r
+#define QUARK_GPIO_SUS3_MAPPING 0x05\r
+#define QUARK_GPIO_SUS4_MAPPING 0x06\r
+#define QUARK_GPIO_SUS5_MAPPING 0x07\r
+#define QUARK_GPIO0_MAPPING 0x08\r
+#define QUARK_GPIO1_MAPPING 0x09\r
+#define QUARK_GPIO2_MAPPING 0x0A\r
+#define QUARK_GPIO3_MAPPING 0x0B\r
+#define QUARK_GPIO4_MAPPING 0x0C\r
+#define QUARK_GPIO5_MAPPING 0x0D\r
+#define QUARK_GPIO6_MAPPING 0x0E\r
+#define QUARK_GPIO7_MAPPING 0x0F\r
+\r
+DefinitionBlock (\r
+ "Platform.aml",\r
+ "DSDT",\r
+ 1,\r
+ "INTEL ",\r
+ "QuarkNcSocId",\r
+ 3)\r
+{\r
+ //\r
+ // Global Variables\r
+ //\r
+ Name(\GPIC, 0x0)\r
+\r
+ //\r
+ // Port 80\r
+ //\r
+ OperationRegion (DBG0, SystemIO, 0x80, 1)\r
+ Field (DBG0, ByteAcc, NoLock, Preserve)\r
+ { IO80,8 }\r
+\r
+ //\r
+ // Access CMOS range\r
+ //\r
+ OperationRegion (ACMS, SystemIO, 0x72, 2)\r
+ Field (ACMS, ByteAcc, NoLock, Preserve)\r
+ { INDX, 8, DATA, 8 }\r
+\r
+ //\r
+ // Global NVS Memory Block\r
+ //\r
+ OperationRegion (MNVS, SystemMemory, 0xFFFF0000, 512)\r
+ Field (MNVS, ByteAcc, NoLock, Preserve)\r
+ {\r
+ OSTP, 32,\r
+ CFGD, 32,\r
+ HPEA, 32, // HPET Enabled ?\r
+\r
+ P1BB, 32, // Pm1blkIoBaseAddress;\r
+ PBAB, 32, // PmbaIoBaseAddress;\r
+ GP0B, 32, // Gpe0blkIoBaseAddress;\r
+ GPAB, 32, // GbaIoBaseAddress;\r
+\r
+ SMBB, 32, // SmbaIoBaseAddress;\r
+ NRV1, 32, // GNVS reserved field 1.\r
+ WDTB, 32, // WdtbaIoBaseAddress;\r
+\r
+ HPTB, 32, // HpetBaseAddress;\r
+ HPTS, 32, // HpetSize;\r
+ PEXB, 32, // PciExpressBaseAddress;\r
+ PEXS, 32, // PciExpressSize;\r
+\r
+ RCBB, 32, // RcbaMmioBaseAddress;\r
+ RCBS, 32, // RcbaMmioSize;\r
+ APCB, 32, // IoApicBaseAddress;\r
+ APCS, 32, // IoApicSize;\r
+\r
+ TPMP, 32, // TpmPresent ?\r
+ DBGP, 32, // DBG2 Present?\r
+ PTYP, 32, // Set to one of EFI_PLATFORM_TYPE enums.\r
+ ALTS, 32, // Use alternate I2c SLA addresses.\r
+ }\r
+\r
+ OperationRegion (GPEB, SystemIO, 0x1100, 0x40) //GPE Block\r
+ Field (GPEB, AnyAcc, NoLock, Preserve)\r
+ {\r
+ Offset(0x10),\r
+ SMIE, 32, // SMI Enable\r
+ SMIS, 32, // SMI Status\r
+ }\r
+\r
+ //\r
+ // Processor Objects\r
+ //\r
+ Scope(\_PR) {\r
+ //\r
+ // IO base will be updated at runtime with search key "PRIO"\r
+ //\r
+ Processor (CPU0, 0x01, 0x4F495250, 0x06) {}\r
+ }\r
+\r
+ //\r
+ // System Sleep States\r
+ //\r
+ Name (\_S0,Package (){0,0,0,0})\r
+ Name (\_S3,Package (){5,0,0,0})\r
+ Name (\_S4,Package (){6,0,0,0})\r
+ Name (\_S5,Package (){7,0,0,0})\r
+\r
+ //\r
+ // General Purpose Event\r
+ //\r
+ Scope(\_GPE)\r
+ {\r
+ //\r
+ // EGPE generated GPE\r
+ //\r
+ Method(_L0D, 0x0, NotSerialized)\r
+ {\r
+ //\r
+ // Check EGPE for this wake event\r
+ //\r
+ Notify (\_SB.SLPB, 0x02)\r
+\r
+ }\r
+\r
+ //\r
+ // GPIO generated GPE\r
+ //\r
+ Method(_L0E, 0x0, NotSerialized)\r
+ {\r
+ //\r
+ // Check GPIO for this wake event\r
+ //\r
+ Notify (\_SB.PWRB, 0x02)\r
+\r
+ }\r
+\r
+ //\r
+ // SCLT generated GPE\r
+ //\r
+ Method(_L0F, 0x0, NotSerialized)\r
+ {\r
+ //\r
+ // Check SCLT for this wake event\r
+ //\r
+ Notify (\_SB.PCI0.SDIO, 0x02)\r
+ Notify (\_SB.PCI0.URT0, 0x02)\r
+ Notify (\_SB.PCI0.USBD, 0x02)\r
+ Notify (\_SB.PCI0.EHCI, 0x02)\r
+ Notify (\_SB.PCI0.OHCI, 0x02)\r
+ Notify (\_SB.PCI0.URT1, 0x02)\r
+ Notify (\_SB.PCI0.ENT0, 0x02)\r
+ Notify (\_SB.PCI0.ENT1, 0x02)\r
+ Notify (\_SB.PCI0.SPI0, 0x02)\r
+ Notify (\_SB.PCI0.SPI1, 0x02)\r
+ Notify (\_SB.PCI0.GIP0, 0x02)\r
+\r
+ }\r
+\r
+ //\r
+ // Remote Management Unit generated GPE\r
+ //\r
+ Method(_L10, 0x0, NotSerialized)\r
+ {\r
+ //\r
+ // Check Remote Management Unit for this wake event.\r
+ //\r
+ }\r
+\r
+ //\r
+ // PCIE generated GPE\r
+ //\r
+ Method(_L11, 0x0, NotSerialized)\r
+ {\r
+ //\r
+ // Check PCIE for this wake event\r
+ //\r
+ Notify (\_SB.PCI0.PEX0, 0x02)\r
+ Notify (\_SB.PCI0.PEX1, 0x02)\r
+ }\r
+ }\r
+\r
+ //\r
+ // define Sleeping button as mentioned in ACPI spec 2.0\r
+ //\r
+ Device (\_SB.SLPB)\r
+ {\r
+ Name (_HID, EISAID ("PNP0C0E"))\r
+ Method (_PRW, 0, NotSerialized)\r
+ {\r
+ Return (Package (0x02) {0x0D,0x04})\r
+ }\r
+ }\r
+\r
+ //\r
+ // define Power Button\r
+ //\r
+ Device (\_SB.PWRB)\r
+ {\r
+ Name (_HID, EISAID ("PNP0C0C"))\r
+ Method (_PRW, 0, NotSerialized)\r
+ {\r
+ Return (Package (0x02) {0x0E,0x04})\r
+ }\r
+ }\r
+ //\r
+ // System Wake up\r
+ //\r
+ Method(_WAK, 1, Serialized)\r
+ {\r
+ // Do nothing here\r
+ Return (0)\r
+ }\r
+\r
+ //\r
+ // System sleep down\r
+ //\r
+ Method (_PTS, 1, NotSerialized)\r
+ {\r
+ // Get ready for S3 sleep\r
+ if (Lequal(Arg0,3))\r
+ {\r
+ Store(0xffffffff,SMIS) // clear SMI status\r
+ Store(SMIE, Local0) // SMI Enable\r
+ Or(Local0,0x4,SMIE) // Generate SMI on sleep\r
+ }\r
+ }\r
+\r
+ //\r
+ // Determing PIC mode\r
+ //\r
+ Method(\_PIC, 1, NotSerialized)\r
+ {\r
+ Store(Arg0,\GPIC)\r
+ }\r
+\r
+ //\r
+ // System Bus\r
+ //\r
+ Scope(\_SB)\r
+ {\r
+ Device(PCI0)\r
+ {\r
+ Name(_HID,EISAID ("PNP0A08")) // PCI Express Root Bridge\r
+ Name(_CID,EISAID ("PNP0A03")) // Compatible PCI Root Bridge\r
+\r
+ Name(_ADR,0x00000000) // Device (HI WORD)=0, Func (LO WORD)=0\r
+ Method (_INI)\r
+ {\r
+ Store(LINUX, OSTP) // Set the default os is Linux\r
+ If (CondRefOf (_OSI, local0))\r
+ {\r
+ //\r
+ //_OSI is supported, so it is WinXp or Win2003Server\r
+ //\r
+ If (\_OSI("Windows 2001"))\r
+ {\r
+ Store (WINDOWS_XP, OSTP)\r
+ }\r
+ If (\_OSI("Windows 2001 SP1"))\r
+ {\r
+ Store (WINDOWS_XP_SP1, OSTP)\r
+ }\r
+ If (\_OSI("Windows 2001 SP2"))\r
+ {\r
+ Store (WINDOWS_XP_SP2, OSTP)\r
+ }\r
+ If (\_OSI("Windows 2001.1"))\r
+ {\r
+ Store (WINDOWS_2003, OSTP)\r
+ }\r
+ If (\_OSI("Windows 2006"))\r
+ {\r
+ Store (WINDOWS_Vista, OSTP)\r
+ }\r
+ If (\_OSI("Windows 2009"))\r
+ {\r
+ Store (WINDOWS_WIN7, OSTP)\r
+ }\r
+ If (\_OSI("Windows 2012"))\r
+ {\r
+ Store (WINDOWS_WIN8, OSTP)\r
+ }\r
+ If (\_OSI("Windows 2013"))\r
+ {\r
+ Store (WINDOWS_WIN8_1, OSTP)\r
+ }\r
+ If (\_OSI("Linux"))\r
+ {\r
+ Store (LINUX, OSTP)\r
+ }\r
+ }\r
+ }\r
+\r
+ Include ("PciHostBridge.asi") // PCI0 Host bridge\r
+ Include ("QNC.asi") // QNC miscellaneous\r
+ Include ("PcieExpansionPrt.asi") // PCIe expansion bridges/devices\r
+ Include ("QuarkSouthCluster.asi") // Quark South Cluster devices\r
+ Include ("QNCLpc.asi") // LPC bridge device\r
+ Include ("QNCApic.asi") // QNC I/O Apic device\r
+\r
+ }\r
+\r
+ //\r
+ // Include asi files for I2C and SPI onboard devices.\r
+ // Devices placed here instead of below relevant controllers.\r
+ // Hardware topology information is maintained by the\r
+ // ResourceSource arg to the I2CSerialBus/SPISerialBus macros\r
+ // within the device asi files.\r
+ //\r
+ Include ("Tpm.asi") // TPM device.\r
+ Include ("CY8C9540A.asi") // CY8C9540A 40Bit I/O Expander & EEPROM\r
+ Include ("PCAL9555A.asi") // NXP PCAL9555A I/O expander.\r
+ Include ("PCA9685.asi") // NXP PCA9685 PWM/LED controller.\r
+ Include ("CAT24C08.asi") // ONSEMI CAT24C08 I2C 8KB EEPROM.\r
+ Include ("AD7298.asi") // Analog devices AD7298 ADC.\r
+ Include ("ADC108S102.asi") // TI ADC108S102 ADC.\r
+ Include ("GpioClient.asi") // Software device to expose GPIO\r
+ }\r
+}\r
--- /dev/null
+/** @file\r
+QNC devices\r
+\r
+Copyright (c) 2013-2015 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#ifndef QNC_ASI\r
+#define QNC_ASI\r
+\r
+Device(IOCM) // I/O controller miscellaneous\r
+{\r
+ Name(_HID,EISAID("PNP0C02")) // System board resources device node ID\r
+\r
+ Name(CRS, ResourceTemplate()\r
+ {\r
+\r
+ // PCIEXBAR memory range\r
+ Memory32Fixed(ReadOnly, 0, 0, FIX1)\r
+\r
+ // RCRB memory range\r
+ Memory32Fixed(ReadOnly, 0, 0, FIX2)\r
+\r
+ // Option ROM shadow memory range\r
+ Memory32Fixed(ReadOnly, 0x000C0000, 0x20000)\r
+\r
+ // BIOS ROM shadow memory range\r
+ Memory32Fixed(ReadOnly, 0x000E0000, 0x20000)\r
+\r
+ // BIOS Firmware just below 4GByte of memory 8MBytes\r
+ Memory32Fixed(ReadOnly, 0xFF800000, 0x800000)\r
+ }\r
+ )\r
+\r
+ Method (_CRS, 0, NotSerialized) {\r
+ CreateDWordField (CRS, ^FIX1._BAS, MBR0)\r
+ Store(\PEXB, MBR0)\r
+ CreateDWordField (CRS, ^FIX1._LEN, MBR1)\r
+ Store(\PEXS, MBR1)\r
+ CreateDWordField (CRS, ^FIX2._BAS, MBR2)\r
+ Store(\RCBB, MBR2)\r
+ CreateDWordField (CRS, ^FIX2._LEN, MBR3)\r
+ Store(\RCBS, MBR3)\r
+ Return (CRS)\r
+ }\r
+}\r
+#endif\r
--- /dev/null
+/** @file\r
+QNC I/O Apic devices\r
+\r
+Copyright (c) 2013-2015 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#ifndef QNC_APIC_ASI\r
+#define QNC_APIC_ASI\r
+\r
+Device(APIC)\r
+{\r
+ Name(_HID,EISAID("PNP0003")) // APIC resources\r
+\r
+ Name(CRS, ResourceTemplate()\r
+ {\r
+ Memory32Fixed(ReadOnly, 0, 0, FIX1) // IO APIC\r
+ }\r
+ )\r
+\r
+ Method (_CRS, 0, NotSerialized) {\r
+ CreateDWordField (CRS, ^FIX1._BAS, MBR0)\r
+ Store(\APCB, MBR0)\r
+ CreateDWordField (CRS, ^FIX1._LEN, MBR1)\r
+ Store(\APCS, MBR1)\r
+ Return (CRS)\r
+ }\r
+}\r
+\r
+#endif\r
--- /dev/null
+/** @file\r
+Lpc devices and control methods\r
+\r
+Copyright (c) 2013-2015 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+\r
+#ifndef QNC_LPC_ASI\r
+#define QNC_LPC_ASI\r
+\r
+Device(LPC)\r
+{\r
+ Name(_ADR,0x001f0000) // Device (HI WORD)=31, Func (LO WORD)=0\r
+\r
+ Include ("PciIrq.asi") // PCI routing control methods\r
+ Include ("LpcDev.asi") // Static Lpc device resource declaration\r
+}\r
+\r
+\r
+#endif\r
--- /dev/null
+/** @file\r
+Quark South Cluster Devices.\r
+\r
+Copyright (c) 2013-2015 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#ifndef QuarkSouthCluster_asi\r
+#define QuarkSouthCluster_asi\r
+\r
+Device (SDIO) // SDIO [Bus 0, Device 20, Function 0]\r
+{\r
+ Name(_ADR,0x00140000) // Device (HI WORD)=20, Func (LO WORD)=0\r
+ Name(_STA,0xF) // Enabled, do Display\r
+ Name(_PRW,Package(){0x0F,0x03}) // GPE pin 0x0F, Wake from S3 -- PCI PME#\r
+}\r
+\r
+Device (URT0) // UART0 [Bus 0, Device 20, Function 1]\r
+{\r
+ Name(_ADR,0x00140001) // Device (HI WORD)=20, Func (LO WORD)=1\r
+ Name(_STA,0xF) // Enabled, do Display\r
+ Name(_PRW,Package(){0x0F,0x03}) // GPE pin 0x0F, Wake from S3 -- PCI PME#\r
+}\r
+\r
+Device (USBD) // USB Device [Bus 0, Device 20, Function 2]\r
+{\r
+ Name(_ADR,0x00140002) // Device (HI WORD)=20, Func (LO WORD)=2\r
+ Name(_STA,0xF) // Enabled, do Display\r
+ Name(_PRW,Package(){0x0F,0x03}) // GPE pin 0x0F, Wake from S3 -- PCI PME#\r
+}\r
+\r
+Device (EHCI) // EHCI [Bus 0, Device 20, Function 3]\r
+{\r
+ Name(_ADR,0x00140003) // Device (HI WORD)=20, Func (LO WORD)=3\r
+ Name(_STA,0xF) // Enabled, do Display\r
+ Name(_PRW,Package(){0x0F,0x03}) // GPE pin 0x0F, Wake from S3 -- PCI PME#\r
+}\r
+\r
+Device (OHCI) // OHCI [Bus 0, Device 20, Function 4]\r
+{\r
+ Name(_ADR,0x00140004) // Device (HI WORD)=20, Func (LO WORD)=4\r
+ Name(_STA,0xF) // Enabled, do Display\r
+ Name(_PRW,Package(){0x0F,0x03}) // GPE pin 0x0F, Wake from S3 -- PCI PME#\r
+}\r
+\r
+Device (URT1) // UART1 [Bus 0, Device 20, Function 5]\r
+{\r
+ Name(_ADR,0x00140005) // Device (HI WORD)=20, Func (LO WORD)=5\r
+ Name(_STA,0xF) // Enabled, do Display\r
+ Name(_PRW,Package(){0x0F,0x03}) // GPE pin 0x0F, Wake from S3 -- PCI PME#\r
+}\r
+\r
+Device (ENT0) // Ethernet0 [Bus 0, Device 20, Function 6]\r
+{\r
+ Name(_ADR,0x00140006) // Device (HI WORD)=20, Func (LO WORD)=6\r
+ Name(_STA,0xF) // Enabled, do Display\r
+ Name(_PRW,Package(){0x0F,0x03}) // GPE pin 0x0F, Wake from S3 -- PCI PME#\r
+}\r
+\r
+Device (ENT1) // Ethernet1 [Bus 0, Device 20, Function 7]\r
+{\r
+ Name(_ADR,0x00140007) // Device (HI WORD)=20, Func (LO WORD)=7\r
+ Name(_STA,0xF) // Enabled, do Display\r
+ Name(_PRW,Package(){0x0F,0x03}) // GPE pin 0x0F, Wake from S3 -- PCI PME#\r
+}\r
+\r
+Device (SPI0) // SPI0 [Bus 0, Device 21, Function 0]\r
+{\r
+ Name(_ADR,0x00150000) // Device (HI WORD)=21, Func (LO WORD)=0\r
+ Name(_STA,0xF) // Enabled, do Display\r
+ Name(_PRW,Package(){0x0F,0x03}) // GPE pin 0x0F, Wake from S3 -- PCI PME#\r
+}\r
+\r
+Device (SPI1) // SPI1 [Bus 0, Device 21, Function 1]\r
+{\r
+ Name(_ADR,0x00150001) // Device (HI WORD)=21, Func (LO WORD)=1\r
+ Name(_STA,0xF) // Enabled, do Display\r
+ Name(_PRW,Package(){0x0F,0x03}) // GPE pin 0x0F, Wake from S3 -- PCI PME#\r
+}\r
+\r
+Device (GIP0) // I2C/GPIO [Bus 0, Device 21, Function 2]\r
+{\r
+ Name(_ADR,0x00150002) // Device (HI WORD)=21, Func (LO WORD)=2\r
+ Name(_STA,0xF) // Enabled, do Display\r
+ Name(_PRW,Package(){0x0F,0x03}) // GPE pin 0x0F, Wake from S3 -- PCI PME#\r
+\r
+ Device(GPO_) // GPIO Virtual Child Device- for BAR0 resources\r
+ {\r
+ Name(_ADR, 0)\r
+ Name(_STA, 0xf)\r
+ Name(_PRW, Package(0x2)\r
+ {\r
+ 0xf,\r
+ 0x3\r
+ })\r
+ }\r
+ Device(I2C_) // I2C Controller Virtual Child Device- for BAR1 resources\r
+ {\r
+ Name(_ADR, 1)\r
+ Name(_STA, 0xf)\r
+ Name(_PRW, Package(0x2)\r
+ {\r
+ 0xf,\r
+ 0x3\r
+ })\r
+ }\r
+}\r
+#endif\r
--- /dev/null
+/** @file\r
+\r
+The Infineon SLB9645 TPM ACPI definition block.\r
+Provides TPM device info. and TPM presence check only.\r
+\r
+Copyright (c) 2013-2015 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+Device (TPM)\r
+{\r
+ //\r
+ // Define _HID as Infineon TPM Device, _CID as "PNP0C31" (defined in\r
+ // "Secure Startup-FVE and TPM Admin BIOS and Platform Requirements").\r
+ //\r
+ Name(_HID ,EISAID("INT3493"))\r
+ Name(_CID, EISAID("PNP0C31"))\r
+\r
+ //\r
+ // Readable name of this device.\r
+ //\r
+ Name (_STR, Unicode ("Infineon TPM 1.2 Device (SLB9645TT1.2)"))\r
+\r
+ //\r
+ // Return the resource consumed by TPM device.\r
+ //\r
+ Name (_CRS, ResourceTemplate () {\r
+ I2cSerialBus (0x20, ControllerInitiated, 0x00061A80, AddressingMode7Bit, "\\_SB.PCI0.GIP0.I2C_", 0, ResourceConsumer,,)\r
+ })\r
+\r
+ //\r
+ // Check if TPM present.\r
+ //\r
+ Method (_STA, 0)\r
+ {\r
+ if (LEqual (TPMP, 0))\r
+ {\r
+ return (0)\r
+ }\r
+ Return (0x0f)\r
+ }\r
+\r
+}\r
--- /dev/null
+/** @file\r
+This file contains the FACS structure definition.\r
+\r
+Copyright (c) 2013-2015 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+//\r
+// Statements that include other files\r
+//\r
+#include "Facs.h"\r
+\r
+EFI_ACPI_2_0_FIRMWARE_ACPI_CONTROL_STRUCTURE FACS = {\r
+ EFI_ACPI_2_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_SIGNATURE,\r
+ sizeof (EFI_ACPI_2_0_FIRMWARE_ACPI_CONTROL_STRUCTURE),\r
+\r
+ //\r
+ // Hardware Signature will be updated at runtime\r
+ //\r
+ 0x00000000,\r
+ EFI_ACPI_FIRMWARE_WAKING_VECTOR,\r
+ EFI_ACPI_GLOBAL_LOCK,\r
+ EFI_ACPI_FIRMWARE_CONTROL_STRUCTURE_FLAGS,\r
+ EFI_ACPI_X_FIRMWARE_WAKING_VECTOR,\r
+ EFI_ACPI_2_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_VERSION,\r
+ {\r
+ EFI_ACPI_RESERVED_BYTE,\r
+ EFI_ACPI_RESERVED_BYTE,\r
+ EFI_ACPI_RESERVED_BYTE,\r
+ EFI_ACPI_RESERVED_BYTE,\r
+ EFI_ACPI_RESERVED_BYTE,\r
+ EFI_ACPI_RESERVED_BYTE,\r
+ EFI_ACPI_RESERVED_BYTE,\r
+ EFI_ACPI_RESERVED_BYTE,\r
+ EFI_ACPI_RESERVED_BYTE,\r
+ EFI_ACPI_RESERVED_BYTE,\r
+ EFI_ACPI_RESERVED_BYTE,\r
+ EFI_ACPI_RESERVED_BYTE,\r
+ EFI_ACPI_RESERVED_BYTE,\r
+ EFI_ACPI_RESERVED_BYTE,\r
+ EFI_ACPI_RESERVED_BYTE,\r
+ EFI_ACPI_RESERVED_BYTE,\r
+ EFI_ACPI_RESERVED_BYTE,\r
+ EFI_ACPI_RESERVED_BYTE,\r
+ EFI_ACPI_RESERVED_BYTE,\r
+ EFI_ACPI_RESERVED_BYTE,\r
+ EFI_ACPI_RESERVED_BYTE,\r
+ EFI_ACPI_RESERVED_BYTE,\r
+ EFI_ACPI_RESERVED_BYTE,\r
+ EFI_ACPI_RESERVED_BYTE,\r
+ EFI_ACPI_RESERVED_BYTE,\r
+ EFI_ACPI_RESERVED_BYTE,\r
+ EFI_ACPI_RESERVED_BYTE,\r
+ EFI_ACPI_RESERVED_BYTE,\r
+ EFI_ACPI_RESERVED_BYTE,\r
+ EFI_ACPI_RESERVED_BYTE,\r
+ EFI_ACPI_RESERVED_BYTE\r
+ }\r
+};\r
+\r
+VOID*\r
+ReferenceAcpiTable (\r
+ VOID\r
+ )\r
+\r
+{\r
+ //\r
+ // Reference the table being generated to prevent the optimizer from removing the\r
+ // data structure from the exeutable\r
+ //\r
+ return (VOID*)&FACS;\r
+}\r
--- /dev/null
+/** @file\r
+This file describes the contents of the ACPI Firmware ACPI Control Structure (FACS)\r
+. Some additional ACPI values are defined in Acpi10.h, Acpi20.h, and Acpi30.h\r
+All changes to the FACS contents should be done in this file.\r
+\r
+Copyright (c) 2013-2015 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#ifndef _FACS_H_\r
+#define _FACS_H_\r
+\r
+//\r
+// Statements that include other files\r
+//\r
+#include <IndustryStandard/Acpi.h>\r
+\r
+//\r
+// FACS Definitions\r
+//\r
+#define EFI_ACPI_FIRMWARE_WAKING_VECTOR 0x00000000\r
+#define EFI_ACPI_GLOBAL_LOCK 0x00000000\r
+\r
+#define EFI_ACPI_FIRMWARE_CONTROL_STRUCTURE_FLAGS 0x00000000\r
+#define EFI_ACPI_X_FIRMWARE_WAKING_VECTOR 0x0000000000000000\r
+\r
+#endif\r
--- /dev/null
+/** @file\r
+This file describes the contents of the ACPI Fixed ACPI Description Table (FADT)\r
+. Some additional ACPI values are defined in Acpi10.h, Acpi20.h, and Acpi30.h\r
+All changes to the FADT contents should be done in this file.\r
+\r
+Copyright (c) 2013-2015 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#ifndef _FADT_H_\r
+#define _FADT_H_\r
+\r
+//\r
+// Statements that include other files\r
+//\r
+#include <IndustryStandard/Acpi.h>\r
+\r
+//\r
+// ACPI table information used to initialize tables.\r
+//\r
+#define EFI_ACPI_OEM_ID 'I','N','T','E','L',' ' // OEMID 6 bytes long\r
+#define EFI_ACPI_OEM_TABLE_ID SIGNATURE_64('T','I','A','N','O',' ',' ',' ') // OEM table id 8 bytes long\r
+#define EFI_ACPI_OEM_REVISION 0x00000004\r
+#define EFI_ACPI_CREATOR_ID SIGNATURE_32('I','N','T','L')\r
+#define EFI_ACPI_CREATOR_REVISION 0x0100000D\r
+\r
+//\r
+// FADT Definitions\r
+//\r
+#define PM_PROFILE 0x01\r
+#define INT_MODEL 0x01\r
+#define SCI_INT_VECTOR 0x0009\r
+#define ACPI_ENABLE 0x0a0\r
+#define ACPI_DISABLE 0x0a1\r
+#define S4BIOS_REQ 0x00\r
+#define PM1_EVT_LEN 0x04\r
+#define PM1_CNT_LEN 0x02\r
+#define PM2_CNT_LEN 0x00\r
+#define PM_TM_LEN 0x04\r
+#define GPE0_BLK_LEN 0x08\r
+#define GPE1_BLK_LEN 0x00\r
+#define GPE1_BASE 0x00\r
+#define RESERVED 0x00\r
+#define P_LVL2_LAT 0x0065\r
+#define P_LVL3_LAT 0x03e9\r
+#define FLUSH_SIZE 0x0400\r
+#define FLUSH_STRIDE 0x0010\r
+#define DUTY_OFFSET 0x01\r
+#define DUTY_WIDTH 0x03\r
+#define DAY_ALRM 0x00\r
+#define MON_ALRM 0x00\r
+#define CENTURY 0x00\r
+#define IAPC_BOOT_ARCH EFI_ACPI_2_0_LEGACY_DEVICES\r
+#define FLAG (EFI_ACPI_1_0_WBINVD | EFI_ACPI_1_0_PROC_C1 | EFI_ACPI_1_0_SLP_BUTTON | EFI_ACPI_1_0_RTC_S4)\r
+#define FLAG2 (EFI_ACPI_2_0_WBINVD | EFI_ACPI_2_0_PROC_C1 | EFI_ACPI_2_0_PWR_BUTTON | EFI_ACPI_2_0_SLP_BUTTON | EFI_ACPI_2_0_RTC_S4 | EFI_ACPI_2_0_RESET_REG_SUP | EFI_ACPI_3_0_USE_PLATFORM_CLOCK)\r
+\r
+#define RESET_REG_ADDRESS_SPACE_ID EFI_ACPI_2_0_SYSTEM_IO\r
+#define RESET_REG_BIT_WIDTH 0x08\r
+#define RESET_REG_BIT_OFFSET 0x00\r
+#define RESET_REG_ADDRESS 0x0000000000000CF9\r
+#define RESET_VALUE 0x02\r
+\r
+#define ACPI_RUNTIME_UPDATE 0x00\r
+\r
+#define PM1a_EVT_BLK_ADDRESS_SPACE_ID EFI_ACPI_2_0_SYSTEM_IO\r
+#define PM1a_EVT_BLK_BIT_WIDTH 0x20\r
+#define PM1a_EVT_BLK_BIT_OFFSET 0x00\r
+\r
+#define PM1b_EVT_BLK_ADDRESS_SPACE_ID EFI_ACPI_2_0_SYSTEM_IO\r
+#define PM1b_EVT_BLK_BIT_WIDTH 0x00\r
+#define PM1b_EVT_BLK_BIT_OFFSET 0x00\r
+#define PM1b_EVT_BLK_ADDRESS 0x0000000000000000\r
+\r
+#define PM1a_CNT_BLK_ADDRESS_SPACE_ID EFI_ACPI_2_0_SYSTEM_IO\r
+#define PM1a_CNT_BLK_BIT_WIDTH 0x10\r
+#define PM1a_CNT_BLK_BIT_OFFSET 0x00\r
+\r
+#define PM1b_CNT_BLK_ADDRESS_SPACE_ID EFI_ACPI_2_0_SYSTEM_IO\r
+#define PM1b_CNT_BLK_BIT_WIDTH 0x00\r
+#define PM1b_CNT_BLK_BIT_OFFSET 0x00\r
+#define PM1b_CNT_BLK_ADDRESS 0x0000000000000000\r
+\r
+#define PM2_CNT_BLK_ADDRESS_SPACE_ID EFI_ACPI_2_0_SYSTEM_IO\r
+#define PM2_CNT_BLK_BIT_WIDTH 0x00\r
+#define PM2_CNT_BLK_BIT_OFFSET 0x00\r
+#define PM2_CNT_BLK_ADDRESS 0x0000000000000000\r
+\r
+#define PM_TMR_BLK_ADDRESS_SPACE_ID EFI_ACPI_2_0_SYSTEM_IO\r
+#define PM_TMR_BLK_BIT_WIDTH 0x20\r
+#define PM_TMR_BLK_BIT_OFFSET 0x00\r
+\r
+#define GPE0_BLK_ADDRESS_SPACE_ID EFI_ACPI_2_0_SYSTEM_IO\r
+#define GPE0_BLK_BIT_WIDTH 0x40\r
+#define GPE0_BLK_BIT_OFFSET 0x00\r
+\r
+#define GPE1_BLK_ADDRESS_SPACE_ID EFI_ACPI_2_0_SYSTEM_IO\r
+#define GPE1_BLK_BIT_WIDTH 0x00\r
+#define GPE1_BLK_BIT_OFFSET 0x00\r
+#define GPE1_BLK_ADDRESS 0x0000000000000000\r
+#endif\r
--- /dev/null
+/** @file\r
+This file describes the contents of the ACPI Fixed ACPI Description Table\r
+(FADT). Some additional ACPI values are defined in Acpi1_0.h and Acpi2_0.h.\r
+All changes to the FADT contents should be done in this file.\r
+\r
+Copyright (c) 2013-2015 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#include "Fadt.h"\r
+\r
+EFI_ACPI_1_0_FIXED_ACPI_DESCRIPTION_TABLE FADT = {\r
+ EFI_ACPI_1_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE,\r
+ sizeof (EFI_ACPI_1_0_FIXED_ACPI_DESCRIPTION_TABLE),\r
+ EFI_ACPI_1_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION,\r
+ 0, // to make sum of entire table == 0\r
+ EFI_ACPI_OEM_ID, // OEMID is a 6 bytes long field\r
+ EFI_ACPI_OEM_TABLE_ID, // OEM table identification(8 bytes long)\r
+ EFI_ACPI_OEM_REVISION, // OEM revision number\r
+ EFI_ACPI_CREATOR_ID, // ASL compiler vendor ID\r
+ EFI_ACPI_CREATOR_REVISION, // ASL compiler revision number\r
+ 0, // Physical addesss of FACS\r
+ 0, // Physical address of DSDT\r
+ INT_MODEL, // System Interrupt Model\r
+ RESERVED, // reserved\r
+ SCI_INT_VECTOR, // System vector of SCI interrupt\r
+ SMI_CMD_IO_PORT, // Port address of SMI command port\r
+ ACPI_ENABLE, // value to write to port smi_cmd to enable ACPI\r
+ ACPI_DISABLE, // value to write to port smi_cmd to disable ACPI\r
+ S4BIOS_REQ, // Value to write to SMI CMD port to enter the S4BIOS state\r
+ RESERVED, // reserved - must be zero\r
+ PM1a_EVT_BLK_ADDRESS, // Port address of Power Mgt 1a Event Reg Blk\r
+ PM1b_EVT_BLK_ADDRESS, // Port address of Power Mgt 1b Event Reg Blk\r
+ PM1a_CNT_BLK_ADDRESS, // Port address of Power Mgt 1a Ctrl Reg Blk\r
+ PM1b_CNT_BLK_ADDRESS, // Port address of Power Mgt 1b Ctrl Reg Blk\r
+ PM2_CNT_BLK_ADDRESS, // Port address of Power Mgt 2 Ctrl Reg Blk\r
+ PM_TMR_BLK_ADDRESS, // Port address of Power Mgt Timer Ctrl Reg Blk\r
+ GPE0_BLK_ADDRESS, // Port addr of General Purpose Event 0 Reg Blk\r
+ GPE1_BLK_ADDRESS, // Port addr of General Purpose Event 1 Reg Blk\r
+ PM1_EVT_LEN, // Byte Length of ports at pm1X_evt_blk\r
+ PM1_CNT_LEN, // Byte Length of ports at pm1X_cnt_blk\r
+ PM2_CNT_LEN, // Byte Length of ports at pm2_cnt_blk\r
+ PM_TM_LEN, // Byte Length of ports at pm_tm_blk\r
+ GPE0_BLK_LEN, // Byte Length of ports at gpe0_blk\r
+ GPE1_BLK_LEN, // Byte Length of ports at gpe1_blk\r
+ GPE1_BASE, // offset in gpe model where gpe1 events start\r
+ RESERVED, // reserved\r
+ P_LVL2_LAT, // worst case HW latency to enter/exit C2 state\r
+ P_LVL3_LAT, // worst case HW latency to enter/exit C3 state\r
+ FLUSH_SIZE, // Size of area read to flush caches\r
+ FLUSH_STRIDE, // Stride used in flushing caches\r
+ DUTY_OFFSET, // bit location of duty cycle field in p_cnt reg\r
+ DUTY_WIDTH, // bit width of duty cycle field in p_cnt reg\r
+ DAY_ALRM, // index to day-of-month alarm in RTC CMOS RAM\r
+ MON_ALRM, // index to month-of-year alarm in RTC CMOS RAM\r
+ CENTURY, // index to century in RTC CMOS RAM\r
+ RESERVED, // reserved\r
+ RESERVED, // reserved\r
+ RESERVED, // reserved\r
+ FLAG\r
+};\r
+\r
+VOID*\r
+ReferenceAcpiTable (\r
+ VOID\r
+ )\r
+\r
+{\r
+ //\r
+ // Reference the table being generated to prevent the optimizer from removing the\r
+ // data structure from the exeutable\r
+ //\r
+ return (VOID*)&FADT;\r
+}\r
--- /dev/null
+/** @file\r
+This file describes the contents of the ACPI Fixed ACPI Description Table\r
+(FADT). Some additional ACPI values are defined in Acpi1_0.h and Acpi2_0.h.\r
+All changes to the FADT contents should be done in this file.\r
+\r
+Copyright (c) 2013-2015 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#include "Fadt.h"\r
+\r
+EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE FADT = {\r
+ {\r
+ EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE,\r
+ sizeof (EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE),\r
+ EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION,\r
+ 0, // to make sum of entire table == 0\r
+ {EFI_ACPI_OEM_ID}, // OEMID is a 6 bytes long field\r
+ EFI_ACPI_OEM_TABLE_ID,// OEM table identification(8 bytes long)\r
+ EFI_ACPI_OEM_REVISION,// OEM revision number\r
+ EFI_ACPI_CREATOR_ID, // ASL compiler vendor ID\r
+ EFI_ACPI_CREATOR_REVISION // ASL compiler revision number\r
+ },\r
+ 0, // Physical addesss of FACS\r
+ 0, // Physical address of DSDT\r
+ RESERVED, // reserved\r
+ PM_PROFILE, // Preferred powermanagement profile\r
+ SCI_INT_VECTOR, // System vector of SCI interrupt\r
+ ACPI_RUNTIME_UPDATE, // Port address of SMI command port\r
+ ACPI_ENABLE, // value to write to port smi_cmd to enable ACPI\r
+ ACPI_DISABLE, // value to write to port smi_cmd to disable ACPI\r
+ S4BIOS_REQ, // Value to write to SMI CMD port to enter the S4BIOS state\r
+ RESERVED, // reserved - must be zero\r
+ ACPI_RUNTIME_UPDATE, // Port address of Power Mgt 1a Event Reg Blk\r
+ PM1b_EVT_BLK_ADDRESS, // Port address of Power Mgt 1b Event Reg Blk\r
+ ACPI_RUNTIME_UPDATE, // Port address of Power Mgt 1a Ctrl Reg Blk\r
+ PM1b_CNT_BLK_ADDRESS, // Port address of Power Mgt 1b Ctrl Reg Blk\r
+ ACPI_RUNTIME_UPDATE, // Port address of Power Mgt 2 Ctrl Reg Blk\r
+ ACPI_RUNTIME_UPDATE, // Port address of Power Mgt Timer Ctrl Reg Blk\r
+ ACPI_RUNTIME_UPDATE, // Port addr of General Purpose Event 0 Reg Blk\r
+ GPE1_BLK_ADDRESS, // Port addr of General Purpose Event 1 Reg Blk\r
+ PM1_EVT_LEN, // Byte Length of ports at pm1X_evt_blk\r
+ PM1_CNT_LEN, // Byte Length of ports at pm1X_cnt_blk\r
+ PM2_CNT_LEN, // Byte Length of ports at pm2_cnt_blk\r
+ PM_TM_LEN, // Byte Length of ports at pm_tm_blk\r
+ GPE0_BLK_LEN, // Byte Length of ports at gpe0_blk\r
+ GPE1_BLK_LEN, // Byte Length of ports at gpe1_blk\r
+ GPE1_BASE, // offset in gpe model where gpe1 events start\r
+ RESERVED, // reserved\r
+ P_LVL2_LAT, // worst case HW latency to enter/exit C2 state\r
+ P_LVL3_LAT, // worst case HW latency to enter/exit C3 state\r
+ FLUSH_SIZE, // Size of area read to flush caches\r
+ FLUSH_STRIDE, // Stride used in flushing caches\r
+ DUTY_OFFSET, // bit location of duty cycle field in p_cnt reg\r
+ DUTY_WIDTH, // bit width of duty cycle field in p_cnt reg\r
+ DAY_ALRM, // index to day-of-month alarm in RTC CMOS RAM\r
+ MON_ALRM, // index to month-of-year alarm in RTC CMOS RAM\r
+ CENTURY, // index to century in RTC CMOS RAM\r
+ IAPC_BOOT_ARCH, // IA-PC Boot Architecture Flags\r
+ RESERVED, // reserved\r
+ FLAG2, // Fixed feature flags\r
+\r
+ {\r
+ RESET_REG_ADDRESS_SPACE_ID, // Address of the reset register\r
+ RESET_REG_BIT_WIDTH,\r
+ RESET_REG_BIT_OFFSET,\r
+ RESERVED,\r
+ RESET_REG_ADDRESS\r
+ },\r
+ RESET_VALUE, // Value to write to the RESET_REG port\r
+ {\r
+ RESERVED,\r
+ RESERVED,\r
+ RESERVED\r
+ },\r
+ 0, // 64Bit physical addesss of FACS\r
+ 0, // 64Bit physical address of DSDT\r
+\r
+ {\r
+ PM1a_EVT_BLK_ADDRESS_SPACE_ID, // Extended Port address of Power Mgt 1a Event Reg Blk\r
+ PM1a_EVT_BLK_BIT_WIDTH,\r
+ PM1a_EVT_BLK_BIT_OFFSET,\r
+ RESERVED,\r
+ ACPI_RUNTIME_UPDATE\r
+ },\r
+\r
+ {\r
+ PM1b_EVT_BLK_ADDRESS_SPACE_ID, // Extended Port address of Power Mgt 1b Event Reg Blk\r
+ PM1b_EVT_BLK_BIT_WIDTH,\r
+ PM1b_EVT_BLK_BIT_OFFSET,\r
+ RESERVED,\r
+ PM1b_EVT_BLK_ADDRESS\r
+ },\r
+\r
+ {\r
+ PM1a_CNT_BLK_ADDRESS_SPACE_ID, // Extended Port address of Power Mgt 1a Ctrl Reg Blk\r
+ PM1a_CNT_BLK_BIT_WIDTH,\r
+ PM1a_CNT_BLK_BIT_OFFSET,\r
+ RESERVED,\r
+ ACPI_RUNTIME_UPDATE\r
+ },\r
+\r
+ {\r
+ PM1b_CNT_BLK_ADDRESS_SPACE_ID, // Extended Port address of Power Mgt 1b Ctrl Reg Blk\r
+ PM1b_CNT_BLK_BIT_WIDTH,\r
+ PM1b_CNT_BLK_BIT_OFFSET,\r
+ RESERVED,\r
+ PM1b_CNT_BLK_ADDRESS\r
+ },\r
+\r
+ {\r
+ PM2_CNT_BLK_ADDRESS_SPACE_ID, // Extended Port address of Power Mgt 2 Ctrl Reg Blk\r
+ PM2_CNT_BLK_BIT_WIDTH,\r
+ PM2_CNT_BLK_BIT_OFFSET,\r
+ RESERVED,\r
+ ACPI_RUNTIME_UPDATE\r
+ },\r
+\r
+ {\r
+ PM_TMR_BLK_ADDRESS_SPACE_ID, // Extended Port address of Power Mgt Timer Ctrl Reg Blk\r
+ PM_TMR_BLK_BIT_WIDTH,\r
+ PM_TMR_BLK_BIT_OFFSET,\r
+ RESERVED,\r
+ ACPI_RUNTIME_UPDATE\r
+ },\r
+\r
+ {\r
+ GPE0_BLK_ADDRESS_SPACE_ID, // Extended Port address of General Purpose Event 0 Reg Blk\r
+ GPE0_BLK_BIT_WIDTH,\r
+ GPE0_BLK_BIT_OFFSET,\r
+ RESERVED,\r
+ ACPI_RUNTIME_UPDATE\r
+ },\r
+\r
+ {\r
+ GPE1_BLK_ADDRESS_SPACE_ID, // Extended Port address of General Purpose Event 1 Reg Blk\r
+ GPE1_BLK_BIT_WIDTH,\r
+ GPE1_BLK_BIT_OFFSET,\r
+ RESERVED,\r
+ GPE1_BLK_ADDRESS\r
+ }\r
+};\r
+\r
+VOID*\r
+ReferenceAcpiTable (\r
+ VOID\r
+ )\r
+\r
+{\r
+ //\r
+ // Reference the table being generated to prevent the optimizer from removing the\r
+ // data structure from the exeutable\r
+ //\r
+ return (VOID*)&FADT;\r
+}\r
--- /dev/null
+/** @file\r
+This file contains a structure definition for the ACPI 1.0 High Precision Event Timer\r
+Description Table (HPET). The contents of this file should only be modified\r
+for bug fixes, no porting is required. The table layout is defined in\r
+HighPrecisionEventTimerTable.h and the table contents are defined in Acpi1.0.h and Hpet.h.\r
+\r
+Copyright (c) 2013-2015 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+//\r
+// Statements that include other files\r
+//\r
+\r
+#include "Hpet.h"\r
+\r
+//\r
+// High Precision Event Timer Table\r
+// Please modify all values in Hpet.h only.\r
+//\r
+\r
+EFI_ACPI_HIGH_PRECISION_EVENT_TIMER_TABLE_HEADER Hpet = {\r
+ {\r
+ EFI_ACPI_3_0_HIGH_PRECISION_EVENT_TIMER_TABLE_SIGNATURE,\r
+ sizeof (EFI_ACPI_HIGH_PRECISION_EVENT_TIMER_TABLE_HEADER),\r
+ EFI_ACPI_HIGH_PRECISION_EVENT_TIMER_TABLE_REVISION,\r
+\r
+ //\r
+ // Checksum will be updated at runtime\r
+ //\r
+ 0x00,\r
+\r
+ //\r
+ // It is expected that these values will be updated at runtime\r
+ //\r
+ {' ', ' ', ' ', ' ', ' ', ' '},\r
+\r
+ 0,\r
+ EFI_ACPI_OEM_HPET_REVISION,\r
+ 0,\r
+ 0\r
+ },\r
+ EFI_ACPI_EVENT_TIMER_BLOCK_ID,\r
+ {\r
+ EFI_ACPI_EVENT_TIMER_BLOCK_ADDRESS_SPACE_ID,\r
+ EFI_ACPI_EVENT_TIMER_BLOCK_BIT_WIDTH,\r
+ EFI_ACPI_EVENT_TIMER_BLOCK_BIT_OFFSET,\r
+ EFI_ACPI_EVENT_TIMER_ACCESS_SIZE,\r
+ ACPI_RUNTIME_UPDATE\r
+ },\r
+ EFI_ACPI_HPET_NUMBER,\r
+ EFI_ACPI_MIN_CLOCK_TICK,\r
+ EFI_ACPI_HPET_ATTRIBUTES\r
+};\r
+\r
+VOID*\r
+ReferenceAcpiTable (\r
+ VOID\r
+ )\r
+{\r
+ //\r
+ // Reference the table being generated to prevent the optimizer from removing the\r
+ // data structure from the exeutable\r
+ //\r
+ return (VOID*)&Hpet;\r
+}\r
--- /dev/null
+/** @file\r
+This file describes the contents of the ACPI High Precision Event Timer Description Table\r
+(HPET). Some additional ACPI values are defined in Acpi10.h, Acpi20.h, and Acpi30.h\r
+All changes to the HPET contents should be done in this file.\r
+\r
+Copyright (c) 2013-2015 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#ifndef _HPET_H_\r
+#define _HPET_H_\r
+\r
+//\r
+// Statements that include other files\r
+//\r
+#include <IndustryStandard/Acpi.h>\r
+#include <IndustryStandard/HighPrecisionEventTimerTable.h>\r
+\r
+//\r
+// HPET Definitions\r
+//\r
+\r
+#define EFI_ACPI_OEM_HPET_REVISION 0x00000001\r
+\r
+#define EFI_ACPI_EVENT_TIMER_BLOCK_ID 0x8086A201\r
+\r
+#define ACPI_RUNTIME_UPDATE 0x00\r
+\r
+//\r
+// Event Timer Block Base Address Information\r
+//\r
+#define EFI_ACPI_EVENT_TIMER_BLOCK_ADDRESS_SPACE_ID EFI_ACPI_3_0_SYSTEM_MEMORY\r
+#define EFI_ACPI_EVENT_TIMER_BLOCK_BIT_WIDTH 0x00\r
+#define EFI_ACPI_EVENT_TIMER_BLOCK_BIT_OFFSET 0x00\r
+#define EFI_ACPI_EVENT_TIMER_ACCESS_SIZE 0x00\r
+\r
+#define EFI_ACPI_HPET_NUMBER 0x00\r
+\r
+#define EFI_ACPI_MIN_CLOCK_TICK 0x0080\r
+\r
+#define EFI_ACPI_HPET_ATTRIBUTES 0x00\r
+\r
+#endif\r
--- /dev/null
+/** @file\r
+This file contains a structure definition for the ACPI Memory Mapped Configuration\r
+Address Space table (MCFG). Any changes to the number of entries in the table require\r
+updating the structure count in Mcfg.h and then adding the structure to the\r
+MCFG defined in this file. The table layout is defined in Mcfg.h and the\r
+table contents are defined in the MemoryMappedConfigurationSpaceAccessTable.h.\r
+\r
+Copyright (c) 2013-2015 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+//\r
+// Statements that include other files\r
+//\r
+\r
+#include "Mcfg.h"\r
+\r
+//\r
+// Multiple APIC Description Table\r
+//\r
+\r
+EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_DESCRIPTION_TABLE Mcfg = {\r
+ {\r
+ EFI_ACPI_3_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE,\r
+ sizeof (EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_DESCRIPTION_TABLE),\r
+ EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_TABLE_REVISION,\r
+\r
+ //\r
+ // Checksum will be updated at runtime\r
+ //\r
+ 0x00,\r
+\r
+ //\r
+ // It is expected that these values will be programmed at runtime\r
+ //\r
+ {' ', ' ', ' ', ' ', ' ', ' '},\r
+\r
+ 0,\r
+ EFI_ACPI_OEM_MCFG_REVISION,\r
+ 0,\r
+ 0\r
+ },\r
+ //\r
+ // Reserved\r
+ //\r
+ 0x0000000000000000,\r
+\r
+ //\r
+ // MCFG specific fields\r
+ //\r
+\r
+ {\r
+ {\r
+ 0x00000000, // BaseAddress (will be updated at runtime)\r
+ 0x0000, // PciSegmentGroupNumber\r
+ 0x00, // StartBusNumber\r
+ 0x1F, // EndBusNumber\r
+ 0x00000000 // Reserved\r
+ }\r
+ }\r
+};\r
+\r
+VOID*\r
+ReferenceAcpiTable (\r
+ VOID\r
+ )\r
+{\r
+ //\r
+ // Reference the table being generated to prevent the optimizer from removing the\r
+ // data structure from the exeutable\r
+ //\r
+ return (VOID*)&Mcfg;\r
+}\r
--- /dev/null
+/** @file\r
+This file describes the contents of the ACPI Memory Mapped Configuration\r
+Space Access Table (MCFG). Some additional ACPI values are defined in Acpi10.h,\r
+Acpi20.h, and Acpi30.h.\r
+\r
+Copyright (c) 2013-2015 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#ifndef _MCFG_H_\r
+#define _MCFG_H_\r
+\r
+//\r
+// Statements that include other files\r
+//\r
+\r
+#include <IndustryStandard/Acpi.h>\r
+#include <IndustryStandard/MemoryMappedConfigurationSpaceAccessTable.h>\r
+\r
+//\r
+// MCFG Definitions\r
+//\r
+\r
+#define EFI_ACPI_OEM_MCFG_REVISION 0x00000001\r
+\r
+//\r
+// Define the number of allocation structures so that we can build the table structure.\r
+//\r
+\r
+#define EFI_ACPI_ALLOCATION_STRUCTURE_COUNT 1\r
+\r
+//\r
+// MCFG structure\r
+//\r
+\r
+//\r
+// Ensure proper structure formats\r
+//\r
+#pragma pack (1)\r
+\r
+//\r
+// MCFG Table structure\r
+//\r
+typedef struct {\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ UINT64 Reserved;\r
+#if EFI_ACPI_ALLOCATION_STRUCTURE_COUNT > 0\r
+ EFI_ACPI_MEMORY_MAPPED_ENHANCED_CONFIGURATION_SPACE_BASE_ADDRESS_ALLOCATION_STRUCTURE AllocationStructure[EFI_ACPI_ALLOCATION_STRUCTURE_COUNT];\r
+#endif\r
+} EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_DESCRIPTION_TABLE;\r
+\r
+#pragma pack ()\r
+\r
+#endif\r
--- /dev/null
+/** @file\r
+Update the _PRT and _PRW method for pci devices\r
+\r
+Copyright (c) 2013-2015 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+**/\r
+#include "AcpiPlatform.h"\r
+\r
+PCI_DEVICE_INFO *mQNCPciInfo = NULL;\r
+\r
+/**\r
+ Init Pci Device Structure\r
+ @param mConfigData - Pointer of Pci Device information Structure\r
+\r
+**/\r
+VOID\r
+InitPciDeviceInfoStructure (\r
+ PCI_DEVICE_SETTING *mConfigData\r
+ )\r
+{\r
+ //\r
+ // Return 0 given that function unsupported.\r
+ // Would need to parse ACPI tables and build mQNCPciInfo above\r
+ // with found _PRT & _PRW methods for PCI devices.\r
+ //\r
+ mConfigData->PciDeviceInfoNumber = 0;\r
+}\r
+\r
+/**\r
+ return Integer value.\r
+\r
+ @param Data - AML data buffer\r
+ @param Integer - integer value.\r
+\r
+ @return Data size processed.\r
+**/\r
+UINTN\r
+SdtGetInteger (\r
+ IN UINT8 *Data,\r
+ OUT UINT64 *Integer\r
+ )\r
+{\r
+ *Integer = 0;\r
+ switch (*Data) {\r
+ case AML_ZERO_OP:\r
+ return 1;\r
+ case AML_ONE_OP:\r
+ *Integer = 1;\r
+ return 1;\r
+ case AML_ONES_OP:\r
+ *Integer = (UINTN)-1;\r
+ return 1;\r
+ case AML_BYTE_PREFIX:\r
+ CopyMem (Integer, Data + 1, sizeof(UINT8));\r
+ return 1 + sizeof(UINT8);\r
+ case AML_WORD_PREFIX:\r
+ CopyMem (Integer, Data + 1, sizeof(UINT16));\r
+ return 1 + sizeof(UINT16);\r
+ case AML_DWORD_PREFIX:\r
+ CopyMem (Integer, Data + 1, sizeof(UINT32));\r
+ return 1 + sizeof(UINT32);\r
+ case AML_QWORD_PREFIX:\r
+ CopyMem (Integer, Data + 1, sizeof(UINT64));\r
+ return 1 + sizeof(UINT64);\r
+ default:\r
+ // Something wrong\r
+ ASSERT (FALSE);\r
+ return 1;\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ Check if this handle has expected opcode.\r
+\r
+ @param AcpiSdt Pointer to Acpi SDT protocol\r
+ @param Handle ACPI handle\r
+ @param OpCode Expected OpCode\r
+ @param SubOpCode Expected SubOpCode\r
+\r
+ @retval TURE This handle has expected opcode\r
+ @retval FALSE This handle does not have expected opcode\r
+**/\r
+BOOLEAN\r
+SdtIsThisTypeObject (\r
+ IN EFI_ACPI_SDT_PROTOCOL *AcpiSdt,\r
+ IN EFI_ACPI_HANDLE Handle,\r
+ IN UINT8 OpCode,\r
+ IN UINT8 SubOpCode\r
+ )\r
+{\r
+ EFI_STATUS Status;\r
+ EFI_ACPI_DATA_TYPE DataType;\r
+ UINT8 *Data;\r
+ UINTN DataSize;\r
+\r
+ Status = AcpiSdt->GetOption (Handle, 0, &DataType, (CONST VOID **)&Data, &DataSize);\r
+ ASSERT_EFI_ERROR (Status);\r
+ ASSERT (DataType == EFI_ACPI_DATA_TYPE_OPCODE);\r
+\r
+ if (OpCode == AML_EXT_OP) {\r
+ if (Data[1] == SubOpCode) {\r
+ return TRUE;\r
+ }\r
+ } else {\r
+ if (Data[0] == OpCode) {\r
+ return TRUE;\r
+ }\r
+ }\r
+ return FALSE;\r
+}\r
+\r
+/**\r
+ Check if this handle has expected name and name value.\r
+\r
+ @param AcpiSdt Pointer to Acpi SDT protocol\r
+ @param Handle ACPI handle\r
+ @param Name Expected name\r
+ @param Value Expected name value\r
+\r
+ @retval TURE This handle has expected name and name value.\r
+ @retval FALSE This handle does not have expected name and name value.\r
+**/\r
+BOOLEAN\r
+SdtIsNameIntegerValueEqual (\r
+ IN EFI_ACPI_SDT_PROTOCOL *AcpiSdt,\r
+ IN EFI_ACPI_HANDLE Handle,\r
+ IN CHAR8 *Name,\r
+ IN UINT64 Value\r
+ )\r
+{\r
+ EFI_STATUS Status;\r
+ EFI_ACPI_DATA_TYPE DataType;\r
+ UINT8 *Data;\r
+ UINTN DataSize;\r
+ UINT64 Integer;\r
+\r
+ Status = AcpiSdt->GetOption (Handle, 1, &DataType, (CONST VOID **)&Data, &DataSize);\r
+ ASSERT_EFI_ERROR (Status);\r
+ ASSERT (DataType == EFI_ACPI_DATA_TYPE_NAME_STRING);\r
+\r
+ if (CompareMem (Data, Name, 4) != 0) {\r
+ return FALSE;\r
+ }\r
+\r
+ //\r
+ // Name match check object\r
+ //\r
+ Status = AcpiSdt->GetOption (Handle, 2, &DataType, (CONST VOID **)&Data, &DataSize);\r
+ ASSERT_EFI_ERROR (Status);\r
+\r
+ Integer = 0;\r
+ SdtGetInteger (Data, &Integer);\r
+ if (Integer != Value) {\r
+ return FALSE;\r
+ }\r
+\r
+ // All match\r
+ return TRUE;\r
+}\r
+\r
+/**\r
+ Check if this handle's children has expected name and name value.\r
+\r
+ @param AcpiSdt Pointer to Acpi SDT protocol\r
+ @param ParentHandle ACPI parent handle\r
+ @param Name Expected name\r
+ @param Value Expected name value\r
+\r
+ @retval TURE This handle's children has expected name and name value.\r
+ @retval FALSE This handle's children does not have expected name and name value.\r
+**/\r
+BOOLEAN\r
+SdtCheckNameIntegerValue (\r
+ IN EFI_ACPI_SDT_PROTOCOL *AcpiSdt,\r
+ IN EFI_ACPI_HANDLE ParentHandle,\r
+ IN CHAR8 *Name,\r
+ IN UINT64 Value\r
+ )\r
+{\r
+ EFI_ACPI_HANDLE PreviousHandle;\r
+ EFI_ACPI_HANDLE Handle;\r
+ EFI_STATUS Status;\r
+\r
+ Handle = NULL;\r
+ while (TRUE) {\r
+ PreviousHandle = Handle;\r
+ Status = AcpiSdt->GetChild (ParentHandle, &Handle);\r
+ ASSERT_EFI_ERROR (Status);\r
+\r
+ if (PreviousHandle != NULL) {\r
+ Status = AcpiSdt->Close (PreviousHandle);\r
+ ASSERT_EFI_ERROR (Status);\r
+ }\r
+\r
+ //\r
+ // Done\r
+ //\r
+ if (Handle == NULL) {\r
+ return FALSE;\r
+ }\r
+\r
+ //\r
+ // Check this name\r
+ //\r
+ if (SdtIsThisTypeObject (AcpiSdt, Handle, AML_NAME_OP, 0)) {\r
+ if (SdtIsNameIntegerValueEqual (AcpiSdt, Handle, Name, Value)) {\r
+ return TRUE;\r
+ }\r
+ }\r
+ }\r
+\r
+ //\r
+ // Should not run here\r
+ //\r
+}\r
+\r
+/**\r
+ Convert the pci address from VPD (bus,dev,fun) into the address that acpi table\r
+ can recognize.\r
+\r
+ @param PciAddress Pci address from VPD\r
+\r
+ @retval return the address that acpi table can recognize\r
+**/\r
+UINT32\r
+SdtConvertToAcpiPciAdress (\r
+ IN UINT32 PciAddress\r
+ )\r
+{\r
+ UINT32 ReturnAddress;\r
+\r
+ ReturnAddress = ((PciAddress & 0x0000FF00) << 8) | (PciAddress & 0x000000FF);\r
+\r
+ if ((PciAddress & 0x000000FF) == 0x000000FF)\r
+ ReturnAddress |= 0x0000FFFF;\r
+\r
+ return ReturnAddress;\r
+}\r
+\r
+/**\r
+ return AML NameString size.\r
+\r
+ @param Buffer - AML name string\r
+\r
+ @return AML name string size\r
+**/\r
+UINTN\r
+SdtGetNameStringSize (\r
+ IN UINT8 *Buffer\r
+ )\r
+{\r
+ UINTN SegCount;\r
+ UINTN Length;\r
+ UINT8 *Name;\r
+\r
+ Name = Buffer;\r
+ Length = 0;\r
+\r
+ //\r
+ // Parse root or prefix\r
+ //\r
+ if (*Buffer == AML_ROOT_CHAR) {\r
+ //\r
+ // RootChar\r
+ //\r
+ Buffer ++;\r
+ Length ++;\r
+ } else if (*Buffer == AML_PARENT_PREFIX_CHAR) {\r
+ //\r
+ // ParentPrefixChar\r
+ //\r
+ Buffer ++;\r
+ Length ++;\r
+ while (*Buffer == AML_PARENT_PREFIX_CHAR) {\r
+ Buffer ++;\r
+ Length ++;\r
+ }\r
+ }\r
+\r
+ //\r
+ // Parse name segment\r
+ //\r
+ if (*Buffer == AML_DUAL_NAME_PREFIX) {\r
+ //\r
+ // DualName\r
+ //\r
+ Buffer ++;\r
+ Length ++;\r
+ SegCount = 2;\r
+ } else if (*Buffer == AML_MULTI_NAME_PREFIX) {\r
+ //\r
+ // MultiName\r
+ //\r
+ Buffer ++;\r
+ Length ++;\r
+ SegCount = *Buffer;\r
+ Buffer ++;\r
+ Length ++;\r
+ } else if (*Buffer == 0) {\r
+ //\r
+ // NULL Name\r
+ //\r
+ SegCount = 0;\r
+ Length ++;\r
+ } else {\r
+ //\r
+ // NameSeg\r
+ //\r
+ SegCount = 1;\r
+ }\r
+\r
+ Buffer += 4 * SegCount;\r
+ Length += 4 * SegCount;\r
+\r
+ return Length;\r
+}\r
+\r
+/**\r
+ The routine to check if this device is PCI root bridge.\r
+\r
+ @param AcpiSdt Pointer to Acpi SDT protocol\r
+ @param DeviceHandle ACPI device handle\r
+ @param Context Context info - not used here\r
+\r
+ @retval TRUE This is PCI root bridge\r
+ @retval FALSE This is not PCI root bridge\r
+**/\r
+BOOLEAN\r
+SdtFindRootBridgeHandle (\r
+ IN EFI_ACPI_SDT_PROTOCOL *AcpiSdt,\r
+ IN EFI_ACPI_HANDLE CheckHandle,\r
+ IN VOID *Context\r
+ )\r
+{\r
+ BOOLEAN Result;\r
+ EFI_ACPI_DATA_TYPE DataType;\r
+ UINT8 *Data;\r
+ UINTN DataSize;\r
+ EFI_STATUS Status;\r
+\r
+ if (!SdtIsThisTypeObject (AcpiSdt, CheckHandle, AML_EXT_OP, AML_EXT_DEVICE_OP))\r
+ return FALSE;\r
+\r
+ Result = SdtCheckNameIntegerValue (AcpiSdt,CheckHandle, "_HID", (UINT64)0x080AD041); // PNP0A08\r
+ if (!Result) {\r
+ Result = SdtCheckNameIntegerValue (AcpiSdt, CheckHandle, "_CID", (UINT64)0x030AD041); // PNP0A03\r
+ if (!Result) {\r
+ return Result;\r
+ }\r
+ }\r
+\r
+ //\r
+ // Found\r
+ //\r
+ Status = AcpiSdt->GetOption (CheckHandle, 1, &DataType, (CONST VOID **)&Data, &DataSize);\r
+ ASSERT_EFI_ERROR (Status);\r
+ ASSERT (DataType == EFI_ACPI_DATA_TYPE_NAME_STRING);\r
+\r
+ return Result;\r
+}\r
+\r
+\r
+/**\r
+ The routine to check if this device is wanted.\r
+\r
+ @param AcpiSdt Pointer to Acpi SDT protocol\r
+ @param DeviceHandle ACPI device handle\r
+ @param Context Context info - not used here\r
+\r
+ @retval TRUE This is PCI device wanted\r
+ @retval FALSE This is not PCI device wanted\r
+**/\r
+BOOLEAN\r
+SdtFindPciDeviceHandle (\r
+ IN EFI_ACPI_SDT_PROTOCOL *AcpiSdt,\r
+ IN EFI_ACPI_HANDLE CheckHandle,\r
+ IN VOID *Context\r
+ )\r
+{\r
+ BOOLEAN Result;\r
+ EFI_ACPI_DATA_TYPE DataType;\r
+ UINT8 *Data;\r
+ UINTN DataSize;\r
+ EFI_STATUS Status;\r
+\r
+ if (!SdtIsThisTypeObject (AcpiSdt, CheckHandle, AML_EXT_OP, AML_EXT_DEVICE_OP))\r
+ return FALSE;\r
+\r
+ Result = SdtCheckNameIntegerValue (AcpiSdt,CheckHandle, "_ADR", (UINT64)*(UINT32 *)Context);\r
+ if (!Result) {\r
+ return Result;\r
+ }\r
+\r
+ //\r
+ // Found\r
+ //\r
+ Status = AcpiSdt->GetOption (CheckHandle, 1, &DataType, (CONST VOID **)&Data, &DataSize);\r
+ ASSERT_EFI_ERROR (Status);\r
+ ASSERT (DataType == EFI_ACPI_DATA_TYPE_NAME_STRING);\r
+\r
+ return Result;\r
+}\r
+\r
+/**\r
+ Go through the parent handle and find the handle which pass CheckHandleInfo.\r
+\r
+ @param AcpiSdt Pointer to Acpi SDT protocol\r
+ @param ParentHandle ACPI parent handle\r
+ @param CheckHandleInfo The callback routine to check if this handle meet the requirement\r
+ @param Context The context of CheckHandleInfo\r
+\r
+ @return the handle which is first one can pass CheckHandleInfo.\r
+**/\r
+EFI_ACPI_HANDLE\r
+SdtGetHandleByScanAllChilds (\r
+ IN EFI_ACPI_SDT_PROTOCOL *AcpiSdt,\r
+ IN EFI_ACPI_HANDLE ParentHandle,\r
+ IN CHECK_HANDLE_INFO CheckHandleInfo,\r
+ IN VOID *Context\r
+ )\r
+{\r
+ EFI_ACPI_HANDLE PreviousHandle;\r
+ EFI_ACPI_HANDLE Handle;\r
+ EFI_STATUS Status;\r
+ EFI_ACPI_HANDLE ReturnHandle;\r
+\r
+ //\r
+ // Use deep first algo to enumerate all ACPI object\r
+ //\r
+ Handle = NULL;\r
+ while (TRUE) {\r
+ PreviousHandle = Handle;\r
+ Status = AcpiSdt->GetChild (ParentHandle, &Handle);\r
+ ASSERT_EFI_ERROR (Status);\r
+\r
+ if (PreviousHandle != NULL) {\r
+ Status = AcpiSdt->Close (PreviousHandle);\r
+ ASSERT_EFI_ERROR (Status);\r
+ }\r
+\r
+ //\r
+ // Done\r
+ //\r
+ if (Handle == NULL) {\r
+ return NULL;\r
+ }\r
+\r
+ //\r
+ // Check this handle\r
+ //\r
+ if (CheckHandleInfo (AcpiSdt, Handle, Context)) {\r
+ return Handle;\r
+ }\r
+\r
+ //\r
+ // Enumerate\r
+ //\r
+ ReturnHandle = SdtGetHandleByScanAllChilds (AcpiSdt, Handle, CheckHandleInfo, Context);\r
+ if (ReturnHandle != NULL) {\r
+ return ReturnHandle;\r
+ }\r
+ }\r
+\r
+ //\r
+ // Should not run here\r
+ //\r
+}\r
+\r
+\r
+/**\r
+ Check whether the INTx package is matched\r
+\r
+ @param AcpiSdt Pointer to Acpi SDT protocol\r
+ @param INTxPkgHandle ACPI INTx package handle\r
+ @param PciAddress Acpi pci address\r
+ @param INTx Index of INTx pin\r
+ @param IsAPIC Tell whether the returned INTx package is for APIC or not\r
+\r
+ @retval TRUE the INTx package is matched\r
+ @retval FALSE the INTx package is not matched\r
+\r
+**/\r
+BOOLEAN\r
+SdtCheckINTxPkgIsMatch (\r
+ IN EFI_ACPI_SDT_PROTOCOL *AcpiSdt,\r
+ IN EFI_ACPI_HANDLE INTxPkgHandle,\r
+ IN UINT32 PciAddress,\r
+ IN UINT8 INTx,\r
+ IN BOOLEAN *IsAPIC\r
+ )\r
+{\r
+ EFI_ACPI_HANDLE PreviousHandle;\r
+ EFI_STATUS Status;\r
+ EFI_ACPI_HANDLE MemberHandle;\r
+ EFI_ACPI_DATA_TYPE DataType;\r
+ UINT8 *Data;\r
+ UINTN DataSize;\r
+ UINT64 CurrentPciAddress;\r
+ UINT64 CurrentINTx;\r
+ UINTN ChildSize;\r
+\r
+\r
+ //\r
+ // Check the pci address\r
+ //\r
+ MemberHandle = NULL;\r
+ Status = AcpiSdt->GetChild (INTxPkgHandle, &MemberHandle);\r
+ ASSERT_EFI_ERROR (Status);\r
+ ASSERT (MemberHandle != NULL);\r
+\r
+ Status = AcpiSdt->GetOption (MemberHandle, 0, &DataType, (CONST VOID **)&Data, &DataSize);\r
+ ASSERT_EFI_ERROR (Status);\r
+ ASSERT (DataType == EFI_ACPI_DATA_TYPE_OPCODE);\r
+\r
+ CurrentPciAddress = 0;\r
+ SdtGetInteger (Data, &CurrentPciAddress);\r
+\r
+ if (CurrentPciAddress != PciAddress) {\r
+\r
+ Status = AcpiSdt->Close (MemberHandle);\r
+ ASSERT_EFI_ERROR (Status);\r
+ return FALSE;\r
+ }\r
+\r
+ //\r
+ // Check the pci interrupt pin\r
+ //\r
+ PreviousHandle = MemberHandle;\r
+ Status = AcpiSdt->GetChild (INTxPkgHandle, &MemberHandle);\r
+ ASSERT_EFI_ERROR (Status);\r
+ ASSERT (MemberHandle != NULL);\r
+\r
+ if (PreviousHandle != NULL) {\r
+ Status = AcpiSdt->Close (PreviousHandle);\r
+ ASSERT_EFI_ERROR (Status);\r
+ }\r
+\r
+ Status = AcpiSdt->GetOption (MemberHandle, 0, &DataType, (CONST VOID **)&Data, &DataSize);\r
+ ASSERT_EFI_ERROR (Status);\r
+ ASSERT (DataType == EFI_ACPI_DATA_TYPE_OPCODE);\r
+\r
+ CurrentINTx = 0;\r
+ ChildSize = SdtGetInteger (Data, &CurrentINTx);\r
+\r
+ Status = AcpiSdt->Close (MemberHandle);\r
+ ASSERT_EFI_ERROR (Status);\r
+\r
+ if (CurrentINTx != INTx)\r
+ return FALSE;\r
+\r
+ Data += ChildSize;\r
+\r
+ if (*Data == AML_BYTE_PREFIX)\r
+ Data += 1;\r
+\r
+ //\r
+ // Check the pci interrupt source\r
+ //\r
+ if (*Data != 0)\r
+ *IsAPIC = FALSE;\r
+ else\r
+ *IsAPIC = TRUE;\r
+\r
+ return TRUE;\r
+}\r
+\r
+\r
+\r
+\r
+/**\r
+ Get the wanted INTx package inside the parent package\r
+\r
+ @param AcpiSdt Pointer to Acpi SDT protocol\r
+ @param ParentPkgHandle ACPI parent package handle\r
+ @param PciAddress Acpi pci address\r
+ @param INTx Index of INTx pin\r
+ @param INTxPkgHandle ACPI INTx package handle\r
+ @param IsAPIC Tell whether the returned INTx package is for APIC or not\r
+\r
+**/\r
+VOID\r
+SdtGetINTxPkgHandle (\r
+ IN EFI_ACPI_SDT_PROTOCOL *AcpiSdt,\r
+ IN EFI_ACPI_HANDLE ParentPkgHandle,\r
+ IN UINT32 PciAddress,\r
+ IN UINT8 INTx,\r
+ IN EFI_ACPI_HANDLE *INTxPkgHandle,\r
+ IN BOOLEAN *IsAPIC\r
+ )\r
+{\r
+ EFI_ACPI_HANDLE PreviousHandle;\r
+ EFI_STATUS Status;\r
+ EFI_ACPI_HANDLE ChildPkgHandle;\r
+\r
+ ChildPkgHandle = NULL;\r
+ while (TRUE) {\r
+ PreviousHandle = ChildPkgHandle;\r
+ Status = AcpiSdt->GetChild (ParentPkgHandle, &ChildPkgHandle);\r
+ ASSERT_EFI_ERROR (Status);\r
+\r
+ if (PreviousHandle != NULL) {\r
+ Status = AcpiSdt->Close (PreviousHandle);\r
+ ASSERT_EFI_ERROR (Status);\r
+ }\r
+\r
+ if (ChildPkgHandle == NULL) {\r
+ break;\r
+ }\r
+\r
+ if (SdtCheckINTxPkgIsMatch(AcpiSdt, ChildPkgHandle, PciAddress, INTx, IsAPIC)) {\r
+ *INTxPkgHandle = ChildPkgHandle;\r
+ return;\r
+ }\r
+ }\r
+\r
+ return;\r
+}\r
+\r
+/**\r
+ Update the INTx package with the correct pirq value\r
+\r
+ @param AcpiSdt Pointer to Acpi SDT protocol\r
+ @param INTxPkgHandle ACPI INTx package handle\r
+ @param PirqValue Correct pirq value\r
+ @param IsAPIC Tell whether the INTx package is for APIC or not\r
+\r
+**/\r
+VOID\r
+SdtUpdateINTxPkg (\r
+ IN EFI_ACPI_SDT_PROTOCOL *AcpiSdt,\r
+ IN EFI_ACPI_HANDLE INTxPkgHandle,\r
+ IN UINT8 PirqValue,\r
+ IN BOOLEAN IsAPIC\r
+ )\r
+{\r
+ EFI_ACPI_HANDLE PreviousHandle;\r
+ EFI_STATUS Status;\r
+ EFI_ACPI_HANDLE MemberHandle;\r
+ EFI_ACPI_DATA_TYPE DataType;\r
+ UINT8 *Data;\r
+ UINTN DataSize;\r
+ UINT64 TempValue;\r
+ UINTN ChildSize;\r
+\r
+\r
+ //\r
+ // Check the pci address\r
+ //\r
+ MemberHandle = NULL;\r
+ Status = AcpiSdt->GetChild (INTxPkgHandle, &MemberHandle);\r
+ ASSERT_EFI_ERROR (Status);\r
+ ASSERT (MemberHandle != NULL);\r
+\r
+ //\r
+ // Check the pci interrupt pin\r
+ //\r
+ PreviousHandle = MemberHandle;\r
+ Status = AcpiSdt->GetChild (INTxPkgHandle, &MemberHandle);\r
+ ASSERT_EFI_ERROR (Status);\r
+ ASSERT (MemberHandle != NULL);\r
+\r
+ if (PreviousHandle != NULL) {\r
+ Status = AcpiSdt->Close (PreviousHandle);\r
+ ASSERT_EFI_ERROR (Status);\r
+ }\r
+\r
+ Status = AcpiSdt->GetOption (MemberHandle, 0, &DataType, (CONST VOID **)&Data, &DataSize);\r
+ ASSERT_EFI_ERROR (Status);\r
+ ASSERT (DataType == EFI_ACPI_DATA_TYPE_OPCODE);\r
+\r
+ ChildSize = SdtGetInteger (Data, &TempValue);\r
+\r
+ Status = AcpiSdt->Close (MemberHandle);\r
+ ASSERT_EFI_ERROR (Status);\r
+\r
+ Data += ChildSize;\r
+\r
+ //\r
+ // update the pci interrupt source or source index\r
+ //\r
+ if (!IsAPIC) {\r
+ ChildSize = SdtGetNameStringSize (Data);\r
+ Data += (ChildSize - 1);\r
+\r
+ PirqValue += 0x40; // change to ascii char\r
+ if (*Data != PirqValue)\r
+ *Data = PirqValue;\r
+ } else {\r
+\r
+ ChildSize = SdtGetInteger (Data, &TempValue);\r
+ Data += ChildSize;\r
+\r
+ Data += 1;\r
+\r
+ if (*Data != PirqValue)\r
+ *Data = PirqValue;\r
+ }\r
+}\r
+\r
+/**\r
+ Check every child package inside this interested parent package for update PRT\r
+\r
+ @param AcpiSdt Pointer to Acpi SDT protocol\r
+ @param ParentPkgHandle ACPI parent package handle\r
+ @param PciDeviceInfo Pointer to PCI_DEVICE_INFO\r
+\r
+**/\r
+VOID\r
+SdtCheckParentPackage (\r
+ IN EFI_ACPI_SDT_PROTOCOL *AcpiSdt,\r
+ IN EFI_ACPI_HANDLE ParentPkgHandle,\r
+ IN PCI_DEVICE_INFO *PciDeviceInfo\r
+ )\r
+{\r
+ EFI_ACPI_HANDLE INTAPkgHandle;\r
+ EFI_ACPI_HANDLE INTBPkgHandle;\r
+ EFI_ACPI_HANDLE INTCPkgHandle;\r
+ EFI_ACPI_HANDLE INTDPkgHandle;\r
+ UINT32 PciAddress = 0;\r
+ BOOLEAN IsAllFunctions = FALSE;\r
+ UINT8 IsAPIC = 0;\r
+ EFI_STATUS Status;\r
+\r
+ INTAPkgHandle = INTBPkgHandle = INTCPkgHandle = INTDPkgHandle = NULL;\r
+\r
+ PciAddress = SdtConvertToAcpiPciAdress(PciDeviceInfo->DeviceAddress);\r
+\r
+ if ((PciAddress & 0xFFFF) == 0xFFFF) {\r
+ IsAllFunctions = TRUE;\r
+ } else {\r
+ IsAllFunctions = FALSE;\r
+ PciAddress = (PciAddress | 0xFFFF);\r
+ }\r
+\r
+ SdtGetINTxPkgHandle (AcpiSdt, ParentPkgHandle, PciAddress, 0, &INTAPkgHandle, (BOOLEAN *)&IsAPIC);\r
+ SdtGetINTxPkgHandle (AcpiSdt, ParentPkgHandle, PciAddress, 1, &INTBPkgHandle, (BOOLEAN *)&IsAPIC);\r
+ SdtGetINTxPkgHandle (AcpiSdt, ParentPkgHandle, PciAddress, 2, &INTCPkgHandle, (BOOLEAN *)&IsAPIC);\r
+ SdtGetINTxPkgHandle (AcpiSdt, ParentPkgHandle, PciAddress, 3, &INTDPkgHandle, (BOOLEAN *)&IsAPIC);\r
+\r
+ //\r
+ // Check INTA\r
+ //\r
+ if ((PciDeviceInfo->INTA[IsAPIC] != 0xFF) && (INTAPkgHandle != NULL)) {\r
+ //\r
+ // Find INTA package and there is valid INTA update item, update it\r
+ //\r
+ SdtUpdateINTxPkg (AcpiSdt, INTAPkgHandle, (PciDeviceInfo->INTA[IsAPIC]), IsAPIC);\r
+ } else if ((PciDeviceInfo->INTA[IsAPIC] != 0xFF) && (INTAPkgHandle == NULL)) {\r
+ //\r
+ // There is valid INTA update item, but no INA package exist, should add it\r
+ //\r
+ DEBUG ((EFI_D_ERROR, "\n\nShould add INTA item for this device(0x%x)\n\n", PciAddress));\r
+\r
+ } else if ((PciDeviceInfo->INTA[IsAPIC] == 0xFF) && (INTAPkgHandle != NULL) && IsAllFunctions) {\r
+ //\r
+ // For all functions senario, if there is invalid INTA update item, but INTA package does exist, should delete it\r
+ //\r
+ DEBUG ((EFI_D_ERROR, "\n\nShould remove INTA item for this device(0x%x)\n\n", PciAddress));\r
+\r
+ }\r
+\r
+ //\r
+ // Check INTB\r
+ //\r
+ if ((PciDeviceInfo->INTB[IsAPIC] != 0xFF) && (INTBPkgHandle != NULL)) {\r
+ //\r
+ // Find INTB package and there is valid INTB update item, update it\r
+ //\r
+ SdtUpdateINTxPkg (AcpiSdt, INTBPkgHandle, (PciDeviceInfo->INTB[IsAPIC]), IsAPIC);\r
+ } else if ((PciDeviceInfo->INTB[IsAPIC] != 0xFF) && (INTBPkgHandle == NULL)) {\r
+ //\r
+ // There is valid INTB update item, but no INTB package exist, should add it\r
+ //\r
+ DEBUG ((EFI_D_ERROR, "\n\nShould add INTB item for this device(0x%x)\n\n", PciAddress));\r
+\r
+ } else if ((PciDeviceInfo->INTB[IsAPIC] == 0xFF) && (INTBPkgHandle != NULL) && IsAllFunctions) {\r
+ //\r
+ // For all functions senario, if there is invalid INTB update item, but INTB package does exist, should delete it\r
+ //\r
+ DEBUG ((EFI_D_ERROR, "\n\nShould remove INTB item for this device(0x%x)\n\n", PciAddress));\r
+\r
+ }\r
+\r
+ //\r
+ // Check INTC\r
+ //\r
+ if ((PciDeviceInfo->INTC[IsAPIC] != 0xFF) && (INTCPkgHandle != NULL)) {\r
+ //\r
+ // Find INTC package and there is valid INTC update item, update it\r
+ //\r
+ SdtUpdateINTxPkg (AcpiSdt, INTCPkgHandle, (PciDeviceInfo->INTC[IsAPIC]), IsAPIC);\r
+ } else if ((PciDeviceInfo->INTC[IsAPIC] != 0xFF) && (INTCPkgHandle == NULL)) {\r
+ //\r
+ // There is valid INTC update item, but no INTC package exist, should add it\r
+ //\r
+ DEBUG ((EFI_D_ERROR, "\n\nShould add INTC item for this device(0x%x)\n\n", PciAddress));\r
+\r
+ } else if ((PciDeviceInfo->INTC[IsAPIC] == 0xFF) && (INTCPkgHandle != NULL) && IsAllFunctions) {\r
+ //\r
+ // For all functions senario, if there is invalid INTC update item, but INTC package does exist, should delete it\r
+ //\r
+ DEBUG ((EFI_D_ERROR, "\n\nShould remove INTC item for this device(0x%x)\n\n", PciAddress));\r
+ }\r
+\r
+ //\r
+ // Check INTD\r
+ //\r
+ if ((PciDeviceInfo->INTD[IsAPIC] != 0xFF) && (INTDPkgHandle != NULL)) {\r
+ //\r
+ // Find INTD package and there is valid INTD update item, update it\r
+ //\r
+ SdtUpdateINTxPkg (AcpiSdt, INTDPkgHandle, (PciDeviceInfo->INTD[IsAPIC]), IsAPIC);\r
+ } else if ((PciDeviceInfo->INTD[IsAPIC] != 0xFF) && (INTDPkgHandle == NULL)) {\r
+ //\r
+ // There is valid INTD update item, but no INTD package exist, should add it\r
+ //\r
+ DEBUG ((EFI_D_ERROR, "\n\nShould add INTD item for this device(0x%x)\n\n", PciAddress));\r
+\r
+ } else if ((PciDeviceInfo->INTD[IsAPIC] == 0xFF) && (INTDPkgHandle != NULL) && IsAllFunctions) {\r
+ //\r
+ // For all functions senario, if there is invalid INTD update item, but INTD package does exist, should delete it\r
+ //\r
+ DEBUG ((EFI_D_ERROR, "\n\nShould remove INTD item for this device(0x%x)\n\n", PciAddress));\r
+ }\r
+\r
+\r
+ if (INTAPkgHandle != NULL) {\r
+ Status = AcpiSdt->Close (INTAPkgHandle);\r
+ ASSERT_EFI_ERROR (Status);\r
+ }\r
+\r
+ if (INTBPkgHandle != NULL) {\r
+ Status = AcpiSdt->Close (INTBPkgHandle);\r
+ ASSERT_EFI_ERROR (Status);\r
+ }\r
+\r
+ if (INTCPkgHandle != NULL) {\r
+ Status = AcpiSdt->Close (INTCPkgHandle);\r
+ ASSERT_EFI_ERROR (Status);\r
+ }\r
+\r
+ if (INTDPkgHandle != NULL) {\r
+ Status = AcpiSdt->Close (INTDPkgHandle);\r
+ ASSERT_EFI_ERROR (Status);\r
+ }\r
+\r
+ return;\r
+}\r
+\r
+/**\r
+ Check every return package for update PRT\r
+\r
+ @param AcpiSdt Pointer to Acpi SDT protocol\r
+ @param ParentHandle ACPI pci device handle\r
+ @param PciDeviceInfo Pointer to PCI_DEVICE_INFO\r
+\r
+**/\r
+VOID\r
+SdtCheckReturnPackage (\r
+ IN EFI_ACPI_SDT_PROTOCOL *AcpiSdt,\r
+ IN EFI_ACPI_HANDLE MethodHandle,\r
+ IN PCI_DEVICE_INFO *PciDeviceInfo\r
+ )\r
+{\r
+ EFI_ACPI_HANDLE PreviousHandle;\r
+ EFI_ACPI_HANDLE ReturnHandle;\r
+ EFI_ACPI_HANDLE PackageHandle;\r
+ EFI_ACPI_HANDLE NamePkgHandle;\r
+ EFI_STATUS Status;\r
+ EFI_ACPI_DATA_TYPE DataType;\r
+ UINT8 *Data;\r
+ UINTN DataSize;\r
+ CHAR8 NameStr[128];\r
+\r
+ ReturnHandle = NULL;\r
+ while (TRUE) {\r
+ PreviousHandle = ReturnHandle;\r
+ Status = AcpiSdt->GetChild (MethodHandle, &ReturnHandle);\r
+ ASSERT_EFI_ERROR (Status);\r
+\r
+ if (PreviousHandle != NULL) {\r
+ Status = AcpiSdt->Close (PreviousHandle);\r
+ ASSERT_EFI_ERROR (Status);\r
+ }\r
+\r
+ if (ReturnHandle == NULL) {\r
+ break;\r
+ }\r
+\r
+ Status = AcpiSdt->GetOption (ReturnHandle, 0, &DataType, (CONST VOID **)&Data, &DataSize);\r
+ ASSERT_EFI_ERROR (Status);\r
+ ASSERT (DataType == EFI_ACPI_DATA_TYPE_OPCODE);\r
+\r
+ if (*Data == AML_RETURN_OP) {\r
+ //\r
+ // Find the return method handle, then look for the returned package data\r
+ //\r
+ Status = AcpiSdt->GetOption (ReturnHandle, 1, &DataType, (CONST VOID **)&Data, &DataSize);\r
+ ASSERT_EFI_ERROR (Status);\r
+\r
+\r
+ if (DataType == EFI_ACPI_DATA_TYPE_NAME_STRING) {\r
+ ZeroMem (NameStr, 128);\r
+ AsciiStrCpy (NameStr, "\\_SB.");\r
+ DataSize = SdtGetNameStringSize (Data);\r
+ AsciiStrnCat (NameStr, (CHAR8 *)Data, DataSize);\r
+\r
+ NamePkgHandle = NULL;\r
+ Status = AcpiSdt->FindPath (mDsdtHandle, NameStr, &NamePkgHandle);\r
+ ASSERT_EFI_ERROR (Status);\r
+ ASSERT (NamePkgHandle != NULL);\r
+\r
+ Status = AcpiSdt->GetOption (NamePkgHandle, 0, &DataType, (CONST VOID **)&Data, &DataSize);\r
+ ASSERT_EFI_ERROR (Status);\r
+ ASSERT (DataType == EFI_ACPI_DATA_TYPE_OPCODE);\r
+ ASSERT (*Data == AML_NAME_OP);\r
+\r
+ Status = AcpiSdt->GetOption (NamePkgHandle, 2, &DataType, (CONST VOID **)&Data, &DataSize);\r
+ ASSERT_EFI_ERROR (Status);\r
+ ASSERT (DataType == EFI_ACPI_DATA_TYPE_CHILD);\r
+ }\r
+\r
+ ASSERT (DataType == EFI_ACPI_DATA_TYPE_CHILD);\r
+\r
+ //\r
+ // Get the parent package handle\r
+ //\r
+ PackageHandle = NULL;\r
+ Status = AcpiSdt->Open (Data, &PackageHandle);\r
+ ASSERT_EFI_ERROR (Status);\r
+\r
+ //\r
+ // Check the parent package for update pci routing\r
+ //\r
+ SdtCheckParentPackage (AcpiSdt, PackageHandle, PciDeviceInfo);\r
+\r
+ Status = AcpiSdt->Close (PackageHandle);\r
+ ASSERT_EFI_ERROR (Status);\r
+\r
+ Status = AcpiSdt->Close (ReturnHandle);\r
+ ASSERT_EFI_ERROR (Status);\r
+\r
+ break;\r
+ }\r
+\r
+ //\r
+ // Not ReturnOp, search it as parent\r
+ //\r
+ SdtCheckReturnPackage (AcpiSdt, ReturnHandle, PciDeviceInfo);\r
+ }\r
+\r
+ //\r
+ // Done\r
+ //\r
+ return;\r
+\r
+}\r
+\r
+/**\r
+ update interrupt info inside the PRT method for the given pci device handle\r
+\r
+ @param AcpiSdt Pointer to Acpi SDT protocol\r
+ @param PciHandle ACPI pci device handle\r
+ @param PciDeviceInfo Pointer to PCI_DEVICE_INFO\r
+\r
+**/\r
+EFI_STATUS\r
+SdtUpdatePrtMethod (\r
+ IN EFI_ACPI_SDT_PROTOCOL *AcpiSdt,\r
+ IN EFI_ACPI_HANDLE PciHandle,\r
+ IN PCI_DEVICE_INFO *PciDeviceInfo\r
+ )\r
+{\r
+ EFI_STATUS Status;\r
+ EFI_ACPI_HANDLE PrtMethodHandle;\r
+\r
+ //\r
+ // Find the PRT method under this pci device\r
+ //\r
+ PrtMethodHandle = NULL;\r
+ Status = AcpiSdt->FindPath (PciHandle, "_PRT", &PrtMethodHandle);\r
+\r
+ if (EFI_ERROR (Status)) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+\r
+ if (PrtMethodHandle == NULL) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+\r
+ SdtCheckReturnPackage(AcpiSdt, PrtMethodHandle, PciDeviceInfo);\r
+\r
+ Status = AcpiSdt->Close (PrtMethodHandle);\r
+ ASSERT_EFI_ERROR (Status);\r
+\r
+ return Status;\r
+}\r
+\r
+\r
+/**\r
+ Update the package inside name op with correct wakeup resources\r
+\r
+ @param AcpiSdt Pointer to Acpi SDT protocol\r
+ @param InPkgHandle ACPI inside package handle\r
+ @param GPEPin Correct gpe pin\r
+ @param SxNum Correct system state the device can wake up from\r
+\r
+**/\r
+VOID\r
+SdtUpdatePackageInName (\r
+ IN EFI_ACPI_SDT_PROTOCOL *AcpiSdt,\r
+ IN EFI_ACPI_HANDLE INTxPkgHandle,\r
+ IN UINT8 GPEPin,\r
+ IN UINT8 SxNum\r
+ )\r
+{\r
+ EFI_ACPI_HANDLE PreviousHandle;\r
+ EFI_STATUS Status;\r
+ EFI_ACPI_HANDLE MemberHandle;\r
+ EFI_ACPI_DATA_TYPE DataType;\r
+ UINT8 *Data;\r
+ UINTN DataSize;\r
+\r
+ //\r
+ // Check the gpe pin\r
+ //\r
+ MemberHandle = NULL;\r
+ Status = AcpiSdt->GetChild (INTxPkgHandle, &MemberHandle);\r
+ ASSERT_EFI_ERROR (Status);\r
+ ASSERT (MemberHandle != NULL);\r
+\r
+ Status = AcpiSdt->GetOption (MemberHandle, 0, &DataType, (CONST VOID **)&Data, &DataSize);\r
+ ASSERT_EFI_ERROR (Status);\r
+ ASSERT (DataType == EFI_ACPI_DATA_TYPE_OPCODE);\r
+\r
+ //\r
+ // Skip byte prefix\r
+ //\r
+ Data += 1;\r
+\r
+ if (*Data != GPEPin) {\r
+\r
+ *Data = GPEPin;\r
+ }\r
+\r
+ //\r
+ // Check the sx number\r
+ //\r
+ PreviousHandle = MemberHandle;\r
+ Status = AcpiSdt->GetChild (INTxPkgHandle, &MemberHandle);\r
+ ASSERT_EFI_ERROR (Status);\r
+ ASSERT (MemberHandle != NULL);\r
+\r
+ if (PreviousHandle != NULL) {\r
+ Status = AcpiSdt->Close (PreviousHandle);\r
+ ASSERT_EFI_ERROR (Status);\r
+ }\r
+\r
+ Status = AcpiSdt->GetOption (MemberHandle, 0, &DataType, (CONST VOID **)&Data, &DataSize);\r
+ ASSERT_EFI_ERROR (Status);\r
+ ASSERT (DataType == EFI_ACPI_DATA_TYPE_OPCODE);\r
+\r
+ //\r
+ // Skip byte prefix\r
+ //\r
+ Data += 1;\r
+\r
+ if (*Data != SxNum) {\r
+\r
+ *Data = SxNum;\r
+ }\r
+\r
+ Status = AcpiSdt->Close (MemberHandle);\r
+ ASSERT_EFI_ERROR (Status);\r
+\r
+}\r
+\r
+/**\r
+ Check the name package belonged to PRW\r
+\r
+ @param AcpiSdt Pointer to Acpi SDT protocol\r
+ @param PrwPkgHandle ACPI PRW package handle\r
+ @param PciDeviceInfo Pointer to PCI_DEVICE_INFO\r
+\r
+**/\r
+VOID\r
+SdtCheckNamePackage (\r
+ IN EFI_ACPI_SDT_PROTOCOL *AcpiSdt,\r
+ IN EFI_ACPI_HANDLE PrwPkgHandle,\r
+ IN PCI_DEVICE_INFO *PciDeviceInfo\r
+ )\r
+{\r
+ EFI_ACPI_HANDLE InPkgHandle;\r
+ EFI_STATUS Status;\r
+ EFI_ACPI_DATA_TYPE DataType;\r
+ UINT8 *Data;\r
+ UINTN DataSize;\r
+\r
+ Status = AcpiSdt->GetOption (PrwPkgHandle, 0, &DataType, (CONST VOID **)&Data, &DataSize);\r
+ ASSERT_EFI_ERROR (Status);\r
+ ASSERT (DataType == EFI_ACPI_DATA_TYPE_OPCODE);\r
+ ASSERT (*Data == AML_NAME_OP);\r
+\r
+ Status = AcpiSdt->GetOption (PrwPkgHandle, 2, &DataType, (CONST VOID **)&Data, &DataSize);\r
+ ASSERT_EFI_ERROR (Status);\r
+ ASSERT (DataType == EFI_ACPI_DATA_TYPE_CHILD);\r
+\r
+ //\r
+ // Get the inside package handle\r
+ //\r
+ InPkgHandle = NULL;\r
+ Status = AcpiSdt->Open (Data, &InPkgHandle);\r
+ ASSERT_EFI_ERROR (Status);\r
+\r
+ //\r
+ // update the package in name op for wakeup info\r
+ //\r
+ if ((PciDeviceInfo->GPEPin != 0xFF) && (PciDeviceInfo->SxNum != 0xFF))\r
+ SdtUpdatePackageInName (AcpiSdt, InPkgHandle, PciDeviceInfo->GPEPin, PciDeviceInfo->SxNum);\r
+\r
+ Status = AcpiSdt->Close (InPkgHandle);\r
+ ASSERT_EFI_ERROR (Status);\r
+\r
+ return;\r
+\r
+}\r
+\r
+/**\r
+ update wakeup info inside the PRW method for the given pci device handle\r
+\r
+ @param AcpiSdt Pointer to Acpi SDT protocol\r
+ @param PciHandle ACPI pci device handle\r
+ @param PciDeviceInfo Pointer to PCI_DEVICE_INFO\r
+\r
+**/\r
+EFI_STATUS\r
+SdtUpdatePrwPackage (\r
+ IN EFI_ACPI_SDT_PROTOCOL *AcpiSdt,\r
+ IN EFI_ACPI_HANDLE PciHandle,\r
+ IN PCI_DEVICE_INFO *PciDeviceInfo\r
+ )\r
+{\r
+ EFI_STATUS Status;\r
+ EFI_ACPI_HANDLE PrwPkgHandle;\r
+\r
+ //\r
+ // Find the PRT method under this pci device\r
+ //\r
+ PrwPkgHandle = NULL;\r
+ Status = AcpiSdt->FindPath (PciHandle, "_PRW", &PrwPkgHandle);\r
+\r
+ if (EFI_ERROR (Status)) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+\r
+ if (PrwPkgHandle == NULL) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+\r
+ SdtCheckNamePackage(AcpiSdt, PrwPkgHandle, PciDeviceInfo);\r
+\r
+ Status = AcpiSdt->Close (PrwPkgHandle);\r
+ ASSERT_EFI_ERROR (Status);\r
+\r
+ return Status;\r
+}\r
+\r
+/**\r
+ update pci routing information in acpi table based on pcd settings\r
+\r
+ @param AcpiSdt Pointer to Acpi SDT protocol\r
+ @param PciRootHandle ACPI root bridge handle\r
+ @param PciDeviceInfo Pointer to PCI_DEVICE_INFO\r
+\r
+**/\r
+EFI_STATUS\r
+SdtUpdatePciRouting (\r
+ IN EFI_ACPI_SDT_PROTOCOL *AcpiSdt,\r
+ IN EFI_ACPI_HANDLE PciRootHandle,\r
+ IN PCI_DEVICE_INFO *PciDeviceInfo\r
+ )\r
+{\r
+ EFI_STATUS Status;\r
+ EFI_ACPI_HANDLE PciBridgeHandle;\r
+ UINT32 PciAddress;\r
+\r
+\r
+ PciBridgeHandle = NULL;\r
+ if (PciDeviceInfo->BridgeAddress == 0x00000000) {\r
+ //\r
+ // Its bridge is the host root bridge\r
+ //\r
+ PciBridgeHandle = PciRootHandle;\r
+\r
+ } else {\r
+\r
+ //\r
+ // Its bridge is just a pci device under the host bridge\r
+ //\r
+\r
+ //\r
+ // Conver the bridge address into one that acpi table can recognize\r
+ //\r
+ PciAddress = SdtConvertToAcpiPciAdress (PciDeviceInfo->BridgeAddress);\r
+\r
+ //\r
+ // Scan the whole table to find the pci device\r
+ //\r
+ PciBridgeHandle = SdtGetHandleByScanAllChilds(AcpiSdt, PciRootHandle, SdtFindPciDeviceHandle, &PciAddress);\r
+ if (PciBridgeHandle == NULL) {\r
+\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+ }\r
+\r
+ Status = SdtUpdatePrtMethod(AcpiSdt, PciBridgeHandle, PciDeviceInfo);\r
+\r
+ if (PciDeviceInfo->BridgeAddress != 0x00000000) {\r
+ Status = AcpiSdt->Close (PciBridgeHandle);\r
+ ASSERT_EFI_ERROR (Status);\r
+ }\r
+\r
+ return Status;\r
+}\r
+\r
+\r
+/**\r
+ update power resource wake up information in acpi table based on pcd settings\r
+\r
+ @param AcpiSdt Pointer to Acpi SDT protocol\r
+ @param PciRootHandle ACPI root bridge handle\r
+ @param PciDeviceInfo Pointer to PCI_DEVICE_INFO\r
+\r
+**/\r
+EFI_STATUS\r
+SdtUpdatePowerWake (\r
+ IN EFI_ACPI_SDT_PROTOCOL *AcpiSdt,\r
+ IN EFI_ACPI_HANDLE PciRootHandle,\r
+ IN PCI_DEVICE_INFO *PciDeviceInfo\r
+ )\r
+{\r
+ EFI_STATUS Status;\r
+ EFI_ACPI_HANDLE PciBridgeHandle;\r
+ EFI_ACPI_HANDLE PciDeviceHandle;\r
+ UINT32 PciAddress;\r
+\r
+ PciBridgeHandle = NULL;\r
+ if (PciDeviceInfo->BridgeAddress == 0x00000000) {\r
+ //\r
+ // Its bridge is the host root bridge\r
+ //\r
+ PciBridgeHandle = PciRootHandle;\r
+\r
+ } else {\r
+\r
+ //\r
+ // Its bridge is just a pci device under the host bridge\r
+ //\r
+\r
+ //\r
+ // Conver the bridge address into one that acpi table can recognize\r
+ //\r
+ PciAddress = SdtConvertToAcpiPciAdress (PciDeviceInfo->BridgeAddress);\r
+\r
+ //\r
+ // Scan the whole table to find the pci device\r
+ //\r
+ PciBridgeHandle = SdtGetHandleByScanAllChilds(AcpiSdt, PciRootHandle, SdtFindPciDeviceHandle, &PciAddress);\r
+\r
+ if (PciBridgeHandle == NULL) {\r
+\r
+ Status = AcpiSdt->Close (PciRootHandle);\r
+ ASSERT_EFI_ERROR (Status);\r
+\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+ }\r
+\r
+ PciDeviceHandle = NULL;\r
+\r
+ //\r
+ // Conver the device address into one that acpi table can recognize\r
+ //\r
+ PciAddress = SdtConvertToAcpiPciAdress (PciDeviceInfo->DeviceAddress);\r
+\r
+ //\r
+ // Scan the whole table to find the pci device\r
+ //\r
+ PciDeviceHandle = SdtGetHandleByScanAllChilds(AcpiSdt, PciBridgeHandle, SdtFindPciDeviceHandle, &PciAddress);\r
+\r
+ if (PciDeviceHandle == NULL) {\r
+ if (PciDeviceInfo->BridgeAddress != 0x00000000) {\r
+ Status = AcpiSdt->Close (PciBridgeHandle);\r
+ ASSERT_EFI_ERROR (Status);\r
+ }\r
+\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+\r
+ Status = SdtUpdatePrwPackage(AcpiSdt, PciDeviceHandle, PciDeviceInfo);\r
+\r
+ Status = AcpiSdt->Close (PciDeviceHandle);\r
+ ASSERT_EFI_ERROR (Status);\r
+\r
+ if (PciDeviceInfo->BridgeAddress != 0x00000000) {\r
+ Status = AcpiSdt->Close (PciBridgeHandle);\r
+ ASSERT_EFI_ERROR (Status);\r
+ }\r
+\r
+ return Status;\r
+}\r
+\r
+\r
+/**\r
+ Get the root bridge handle by scanning the acpi table\r
+\r
+ @param AcpiSdt Pointer to Acpi SDT protocol\r
+ @param DsdtHandle ACPI root handle\r
+\r
+ @retval EFI_ACPI_HANDLE the handle of the root bridge\r
+**/\r
+EFI_ACPI_HANDLE\r
+SdtGetRootBridgeHandle (\r
+ IN EFI_ACPI_SDT_PROTOCOL *AcpiSdt,\r
+ IN EFI_ACPI_HANDLE DsdtHandle\r
+ )\r
+{\r
+ EFI_ACPI_HANDLE PciRootHandle;\r
+\r
+ //\r
+ // Scan the whole table to find the root bridge\r
+ //\r
+ PciRootHandle = NULL;\r
+ PciRootHandle = SdtGetHandleByScanAllChilds(AcpiSdt, DsdtHandle, SdtFindRootBridgeHandle, NULL);\r
+ ASSERT (PciRootHandle != NULL);\r
+\r
+ return PciRootHandle;\r
+}\r
+\r
+\r
+/**\r
+ Check input Pci device info is changed from the default values\r
+ @param PciDeviceInfo Pointer to PCI_DEVICE_INFO\r
+ @param UpdatePRT Pointer to BOOLEAN\r
+ @param UpdatePRW Pointer to BOOLEAN\r
+\r
+**/\r
+VOID\r
+SdtCheckPciDeviceInfoChanged (\r
+ IN PCI_DEVICE_INFO *PciDeviceInfo,\r
+ IN BOOLEAN *UpdatePRT,\r
+ IN BOOLEAN *UpdatePRW\r
+ )\r
+{\r
+ UINTN Index = 0;\r
+\r
+ if (mQNCPciInfo == NULL) {\r
+ *UpdatePRT = FALSE;\r
+ *UpdatePRW = FALSE;\r
+ return;\r
+ }\r
+\r
+ *UpdatePRT = TRUE;\r
+ *UpdatePRW = TRUE;\r
+\r
+ for (Index = 0;Index < CURRENT_PCI_DEVICE_NUM; Index++) {\r
+ if ((mQNCPciInfo[Index].BridgeAddress == PciDeviceInfo->BridgeAddress)\r
+ && (mQNCPciInfo[Index].DeviceAddress == PciDeviceInfo->DeviceAddress)) {\r
+ //\r
+ // Find one matched entry\r
+ //\r
+ if (CompareMem (&(mQNCPciInfo[Index].INTA[0]), &PciDeviceInfo->INTA[0], 10) == 0) {\r
+ *UpdatePRT = FALSE;\r
+ *UpdatePRW = FALSE;\r
+ //DEBUG ((EFI_D_ERROR, "Find one matched entry[%d] and no change\n", Index));\r
+ } else {\r
+ if (CompareMem (&(mQNCPciInfo[Index].INTA[0]), &PciDeviceInfo->INTA[0], 8) == 0)\r
+ *UpdatePRT = FALSE;\r
+\r
+ if (CompareMem (&(mQNCPciInfo[Index].GPEPin), &PciDeviceInfo->GPEPin, 2) == 0)\r
+ *UpdatePRW = FALSE;\r
+\r
+ if (*(UINT64 *)(&PciDeviceInfo->INTA[0]) == 0xFFFFFFFFFFFFFFFFULL)\r
+ *UpdatePRT = FALSE;\r
+\r
+ if (*(UINT16 *)(&PciDeviceInfo->GPEPin) == 0xFFFF)\r
+ *UpdatePRW = FALSE;\r
+\r
+ //DEBUG ((EFI_D_ERROR, "Find one matched entry[%d] and but need update PRT:0x%x PRW:0x%x\n", Index, *UpdatePRT, *UpdatePRW));\r
+ }\r
+ break;\r
+ }\r
+ }\r
+\r
+ //if (Index == 42) {\r
+ // DEBUG ((EFI_D_ERROR, "Find No matched entry\n"));\r
+ //}\r
+\r
+ return;\r
+}\r
--- /dev/null
+/** @file\r
+Update the _PRT and _PRW method for pci devices\r
+\r
+Copyright (c) 2013-2015 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+**/\r
+#ifndef _ACPI_PCI_UPDATE_H_\r
+#define _ACPI_PCI_UPDATE_H_\r
+\r
+\r
+//\r
+// Primary OpCode\r
+//\r
+#define AML_ZERO_OP 0x00\r
+#define AML_ONE_OP 0x01\r
+#define AML_ALIAS_OP 0x06\r
+#define AML_NAME_OP 0x08\r
+#define AML_BYTE_PREFIX 0x0a\r
+#define AML_WORD_PREFIX 0x0b\r
+#define AML_DWORD_PREFIX 0x0c\r
+#define AML_STRING_PREFIX 0x0d\r
+#define AML_QWORD_PREFIX 0x0e\r
+#define AML_SCOPE_OP 0x10\r
+#define AML_BUFFER_OP 0x11\r
+#define AML_PACKAGE_OP 0x12\r
+#define AML_VAR_PACKAGE_OP 0x13\r
+#define AML_METHOD_OP 0x14\r
+#define AML_DUAL_NAME_PREFIX 0x2e\r
+#define AML_MULTI_NAME_PREFIX 0x2f\r
+#define AML_NAME_CHAR_A 0x41\r
+#define AML_NAME_CHAR_B 0x42\r
+#define AML_NAME_CHAR_C 0x43\r
+#define AML_NAME_CHAR_D 0x44\r
+#define AML_NAME_CHAR_E 0x45\r
+#define AML_NAME_CHAR_F 0x46\r
+#define AML_NAME_CHAR_G 0x47\r
+#define AML_NAME_CHAR_H 0x48\r
+#define AML_NAME_CHAR_I 0x49\r
+#define AML_NAME_CHAR_J 0x4a\r
+#define AML_NAME_CHAR_K 0x4b\r
+#define AML_NAME_CHAR_L 0x4c\r
+#define AML_NAME_CHAR_M 0x4d\r
+#define AML_NAME_CHAR_N 0x4e\r
+#define AML_NAME_CHAR_O 0x4f\r
+#define AML_NAME_CHAR_P 0x50\r
+#define AML_NAME_CHAR_Q 0x51\r
+#define AML_NAME_CHAR_R 0x52\r
+#define AML_NAME_CHAR_S 0x53\r
+#define AML_NAME_CHAR_T 0x54\r
+#define AML_NAME_CHAR_U 0x55\r
+#define AML_NAME_CHAR_V 0x56\r
+#define AML_NAME_CHAR_W 0x57\r
+#define AML_NAME_CHAR_X 0x58\r
+#define AML_NAME_CHAR_Y 0x59\r
+#define AML_NAME_CHAR_Z 0x5a\r
+#define AML_ROOT_CHAR 0x5c\r
+#define AML_PARENT_PREFIX_CHAR 0x5e\r
+#define AML_NAME_CHAR__ 0x5f\r
+#define AML_LOCAL0 0x60\r
+#define AML_LOCAL1 0x61\r
+#define AML_LOCAL2 0x62\r
+#define AML_LOCAL3 0x63\r
+#define AML_LOCAL4 0x64\r
+#define AML_LOCAL5 0x65\r
+#define AML_LOCAL6 0x66\r
+#define AML_LOCAL7 0x67\r
+#define AML_ARG0 0x68\r
+#define AML_ARG1 0x69\r
+#define AML_ARG2 0x6a\r
+#define AML_ARG3 0x6b\r
+#define AML_ARG4 0x6c\r
+#define AML_ARG5 0x6d\r
+#define AML_ARG6 0x6e\r
+#define AML_STORE_OP 0x70\r
+#define AML_REF_OF_OP 0x71\r
+#define AML_ADD_OP 0x72\r
+#define AML_CONCAT_OP 0x73\r
+#define AML_SUBTRACT_OP 0x74\r
+#define AML_INCREMENT_OP 0x75\r
+#define AML_DECREMENT_OP 0x76\r
+#define AML_MULTIPLY_OP 0x77\r
+#define AML_DIVIDE_OP 0x78\r
+#define AML_SHIFT_LEFT_OP 0x79\r
+#define AML_SHIFT_RIGHT_OP 0x7a\r
+#define AML_AND_OP 0x7b\r
+#define AML_NAND_OP 0x7c\r
+#define AML_OR_OP 0x7d\r
+#define AML_NOR_OP 0x7e\r
+#define AML_XOR_OP 0x7f\r
+#define AML_NOT_OP 0x80\r
+#define AML_FIND_SET_LEFT_BIT_OP 0x81\r
+#define AML_FIND_SET_RIGHT_BIT_OP 0x82\r
+#define AML_DEREF_OF_OP 0x83\r
+#define AML_CONCAT_RES_OP 0x84\r
+#define AML_MOD_OP 0x85\r
+#define AML_NOTIFY_OP 0x86\r
+#define AML_SIZE_OF_OP 0x87\r
+#define AML_INDEX_OP 0x88\r
+#define AML_MATCH_OP 0x89\r
+#define AML_CREATE_DWORD_FIELD_OP 0x8a\r
+#define AML_CREATE_WORD_FIELD_OP 0x8b\r
+#define AML_CREATE_BYTE_FIELD_OP 0x8c\r
+#define AML_CREATE_BIT_FIELD_OP 0x8d\r
+#define AML_OBJECT_TYPE_OP 0x8e\r
+#define AML_CREATE_QWORD_FIELD_OP 0x8f\r
+#define AML_LAND_OP 0x90\r
+#define AML_LOR_OP 0x91\r
+#define AML_LNOT_OP 0x92\r
+#define AML_LEQUAL_OP 0x93\r
+#define AML_LGREATER_OP 0x94\r
+#define AML_LLESS_OP 0x95\r
+#define AML_TO_BUFFER_OP 0x96\r
+#define AML_TO_DEC_STRING_OP 0x97\r
+#define AML_TO_HEX_STRING_OP 0x98\r
+#define AML_TO_INTEGER_OP 0x99\r
+#define AML_TO_STRING_OP 0x9c\r
+#define AML_COPY_OBJECT_OP 0x9d\r
+#define AML_MID_OP 0x9e\r
+#define AML_CONTINUE_OP 0x9f\r
+#define AML_IF_OP 0xa0\r
+#define AML_ELSE_OP 0xa1\r
+#define AML_WHILE_OP 0xa2\r
+#define AML_NOOP_OP 0xa3\r
+#define AML_RETURN_OP 0xa4\r
+#define AML_BREAK_OP 0xa5\r
+#define AML_BREAK_POINT_OP 0xcc\r
+#define AML_ONES_OP 0xff\r
+\r
+//\r
+// Extended OpCode\r
+//\r
+#define AML_EXT_OP 0x5b\r
+\r
+#define AML_EXT_MUTEX_OP 0x01\r
+#define AML_EXT_EVENT_OP 0x02\r
+#define AML_EXT_COND_REF_OF_OP 0x12\r
+#define AML_EXT_CREATE_FIELD_OP 0x13\r
+#define AML_EXT_LOAD_TABLE_OP 0x1f\r
+#define AML_EXT_LOAD_OP 0x20\r
+#define AML_EXT_STALL_OP 0x21\r
+#define AML_EXT_SLEEP_OP 0x22\r
+#define AML_EXT_ACQUIRE_OP 0x23\r
+#define AML_EXT_SIGNAL_OP 0x24\r
+#define AML_EXT_WAIT_OP 0x25\r
+#define AML_EXT_RESET_OP 0x26\r
+#define AML_EXT_RELEASE_OP 0x27\r
+#define AML_EXT_FROM_BCD_OP 0x28\r
+#define AML_EXT_TO_BCD_OP 0x29\r
+#define AML_EXT_UNLOAD_OP 0x2a\r
+#define AML_EXT_REVISION_OP 0x30\r
+#define AML_EXT_DEBUG_OP 0x31\r
+#define AML_EXT_FATAL_OP 0x32\r
+#define AML_EXT_TIMER_OP 0x33\r
+#define AML_EXT_REGION_OP 0x80\r
+#define AML_EXT_FIELD_OP 0x81\r
+#define AML_EXT_DEVICE_OP 0x82\r
+#define AML_EXT_PROCESSOR_OP 0x83\r
+#define AML_EXT_POWER_RES_OP 0x84\r
+#define AML_EXT_THERMAL_ZONE_OP 0x85\r
+#define AML_EXT_INDEX_FIELD_OP 0x86\r
+#define AML_EXT_BANK_FIELD_OP 0x87\r
+#define AML_EXT_DATA_REGION_OP 0x88\r
+\r
+#pragma pack(1)\r
+\r
+typedef struct {\r
+ UINT32 BridgeAddress;\r
+ UINT32 DeviceAddress;\r
+ UINT8 INTA[2]; // the first member record the 8259 link, the second member record the io apic irq number\r
+ UINT8 INTB[2];\r
+ UINT8 INTC[2];\r
+ UINT8 INTD[2];\r
+\r
+ UINT8 GPEPin;\r
+ UINT8 SxNum;\r
+} PCI_DEVICE_INFO;\r
+\r
+#pragma pack()\r
+\r
+#define PCI_DEVICE_INFO_MAX_NUM 50\r
+#define CURRENT_PCI_DEVICE_NUM 13\r
+\r
+#define PIRQ_LINKA 1\r
+#define PIRQ_LINKB 2\r
+#define PIRQ_LINKC 3\r
+#define PIRQ_LINKD 4\r
+#define PIRQ_LINKE 5\r
+#define PIRQ_LINKF 6\r
+#define PIRQ_LINKG 7\r
+#define PIRQ_LINKH 8\r
+#define PIRQ_INVALID 0xFF\r
+\r
+typedef struct _PCI_DEVICE_SETTING{\r
+ UINT8 PciDeviceInfoNumber;\r
+ PCI_DEVICE_INFO PciDeviceInfo[PCI_DEVICE_INFO_MAX_NUM];\r
+}PCI_DEVICE_SETTING;\r
+\r
+typedef struct _AML_BYTE_ENCODING AML_BYTE_ENCODING;\r
+\r
+//\r
+// AML Handle Entry definition.\r
+//\r
+// Signature must be set to EFI_AML_HANDLE_SIGNATURE or EFI_AML_ROOT_HANDLE_SIGNATURE\r
+// Buffer is the ACPI node buffer pointer, the first/second bytes are opcode.\r
+// This buffer should not be freed.\r
+// Size is the total size of this ACPI node buffer.\r
+//\r
+typedef struct {\r
+ UINT32 Signature;\r
+ UINT8 *Buffer;\r
+ UINTN Size;\r
+ AML_BYTE_ENCODING *AmlByteEncoding;\r
+ BOOLEAN Modified;\r
+} EFI_AML_HANDLE;\r
+\r
+typedef UINT32 AML_OP_PARSE_INDEX;\r
+\r
+typedef UINT32 AML_OP_PARSE_FORMAT;\r
+\r
+typedef UINT32 AML_OP_ATTRIBUTE;\r
+\r
+struct _AML_BYTE_ENCODING {\r
+ UINT8 OpCode;\r
+ UINT8 SubOpCode;\r
+ AML_OP_PARSE_INDEX MaxIndex;\r
+ AML_OP_PARSE_FORMAT Format[6];\r
+ AML_OP_ATTRIBUTE Attribute;\r
+};\r
+\r
+\r
+//\r
+// Check device info fucntion prototype\r
+//\r
+typedef\r
+BOOLEAN\r
+(* CHECK_HANDLE_INFO) (\r
+ IN EFI_ACPI_SDT_PROTOCOL *AcpiSdt,\r
+ IN EFI_ACPI_HANDLE CheckHandle,\r
+ IN VOID *Context\r
+ );\r
+\r
+extern EFI_ACPI_HANDLE mDsdtHandle;\r
+extern EFI_ACPI_SDT_PROTOCOL *mAcpiSdt;\r
+\r
+/**\r
+ Init Pci Device Structure\r
+\r
+ @param mConfigData - Pointer of Pci Device information Structure\r
+\r
+**/\r
+VOID\r
+InitPciDeviceInfoStructure (\r
+ PCI_DEVICE_SETTING *mConfigData\r
+ );\r
+/**\r
+ update pci routing information in acpi table based on pcd settings\r
+\r
+ @param AcpiSdt Pointer to Acpi SDT protocol\r
+ @param DsdtHandle ACPI root handle\r
+ @param PciDeviceInfo Pointer to PCI_DEVICE_INFO\r
+\r
+**/\r
+EFI_STATUS\r
+SdtUpdatePciRouting (\r
+ IN EFI_ACPI_SDT_PROTOCOL *AcpiSdt,\r
+ IN EFI_ACPI_HANDLE DsdtHandle,\r
+ IN PCI_DEVICE_INFO *PciDeviceInfo\r
+ );\r
+\r
+\r
+/**\r
+ update power resource wake up information in acpi table based on pcd settings\r
+\r
+ @param AcpiSdt Pointer to Acpi SDT protocol\r
+ @param DsdtHandle ACPI root handle\r
+ @param PciDeviceInfo Pointer to PCI_DEVICE_INFO\r
+\r
+**/\r
+EFI_STATUS\r
+SdtUpdatePowerWake (\r
+ IN EFI_ACPI_SDT_PROTOCOL *AcpiSdt,\r
+ IN EFI_ACPI_HANDLE DsdtHandle,\r
+ IN PCI_DEVICE_INFO *PciDeviceInfo\r
+ );\r
+\r
+/**\r
+ Get the root bridge handle by scanning the acpi table\r
+\r
+ @param AcpiSdt Pointer to Acpi SDT protocol\r
+ @param DsdtHandle ACPI root handle\r
+\r
+ @retval EFI_ACPI_HANDLE the handle of the root bridge\r
+**/\r
+EFI_ACPI_HANDLE\r
+SdtGetRootBridgeHandle (\r
+ IN EFI_ACPI_SDT_PROTOCOL *AcpiSdt,\r
+ IN EFI_ACPI_HANDLE DsdtHandle\r
+ );\r
+\r
+/**\r
+ Check input Pci device info is changed from the default values\r
+ @param PciDeviceInfo Pointer to PCI_DEVICE_INFO\r
+ @param UpdatePRT Pointer to BOOLEAN\r
+ @param UpdatePRW Pointer to BOOLEAN\r
+\r
+**/\r
+VOID\r
+SdtCheckPciDeviceInfoChanged (\r
+ IN PCI_DEVICE_INFO *PciDeviceInfo,\r
+ IN BOOLEAN *UpdatePRT,\r
+ IN BOOLEAN *UpdatePRW\r
+ );\r
+#endif\r
--- /dev/null
+/** @file\r
+ACPI Platform Driver\r
+\r
+Copyright (c) 2013-2015 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#include <Protocol/AcpiTable.h>\r
+#include <IndustryStandard/Pci22.h>\r
+#include "AcpiPlatform.h"\r
+\r
+//\r
+// Global Variable\r
+//\r
+EFI_GLOBAL_NVS_AREA_PROTOCOL mGlobalNvsArea;\r
+EFI_ACPI_SDT_PROTOCOL *mAcpiSdt;\r
+\r
+EFI_ACPI_HANDLE mDsdtHandle = NULL;\r
+\r
+\r
+EFI_STATUS\r
+LocateSupportProtocol (\r
+ IN EFI_GUID *Protocol,\r
+ OUT VOID **Instance,\r
+ IN UINT32 Type\r
+ )\r
+/*++\r
+\r
+Routine Description:\r
+\r
+ Locate the first instance of a protocol. If the protocol requested is an\r
+ FV protocol, then it will return the first FV that contains the ACPI table\r
+ storage file.\r
+\r
+Arguments:\r
+\r
+ Protocol The protocol to find.\r
+ Instance Return pointer to the first instance of the protocol\r
+\r
+Returns:\r
+\r
+ EFI_SUCCESS The function completed successfully.\r
+ EFI_NOT_FOUND The protocol could not be located.\r
+ EFI_OUT_OF_RESOURCES There are not enough resources to find the protocol.\r
+\r
+--*/\r
+{\r
+ EFI_STATUS Status;\r
+ EFI_HANDLE *HandleBuffer;\r
+ UINTN NumberOfHandles;\r
+ EFI_FV_FILETYPE FileType;\r
+ UINT32 FvStatus;\r
+ EFI_FV_FILE_ATTRIBUTES Attributes;\r
+ UINTN Size;\r
+ UINTN i;\r
+\r
+ FvStatus = 0;\r
+\r
+ //\r
+ // Locate protocol.\r
+ //\r
+ Status = gBS->LocateHandleBuffer (\r
+ ByProtocol,\r
+ Protocol,\r
+ NULL,\r
+ &NumberOfHandles,\r
+ &HandleBuffer\r
+ );\r
+ if (EFI_ERROR (Status)) {\r
+\r
+ //\r
+ // Defined errors at this time are not found and out of resources.\r
+ //\r
+ return Status;\r
+ }\r
+\r
+\r
+\r
+ //\r
+ // Looking for FV with ACPI storage file\r
+ //\r
+\r
+ for (i = 0; i < NumberOfHandles; i++) {\r
+ //\r
+ // Get the protocol on this handle\r
+ // This should not fail because of LocateHandleBuffer\r
+ //\r
+ Status = gBS->HandleProtocol (\r
+ HandleBuffer[i],\r
+ Protocol,\r
+ Instance\r
+ );\r
+ ASSERT_EFI_ERROR (Status);\r
+\r
+ if (!Type) {\r
+ //\r
+ // Not looking for the FV protocol, so find the first instance of the\r
+ // protocol. There should not be any errors because our handle buffer\r
+ // should always contain at least one or LocateHandleBuffer would have\r
+ // returned not found.\r
+ //\r
+ break;\r
+ }\r
+\r
+ //\r
+ // See if it has the ACPI storage file\r
+ //\r
+\r
+ Status = ((EFI_FIRMWARE_VOLUME2_PROTOCOL*) (*Instance))->ReadFile (*Instance,\r
+ (EFI_GUID*)PcdGetPtr (PcdAcpiTableStorageFile),\r
+ NULL,\r
+ &Size,\r
+ &FileType,\r
+ &Attributes,\r
+ &FvStatus\r
+ );\r
+\r
+ //\r
+ // If we found it, then we are done\r
+ //\r
+ if (Status == EFI_SUCCESS) {\r
+ break;\r
+ }\r
+ }\r
+\r
+ //\r
+ // Our exit status is determined by the success of the previous operations\r
+ // If the protocol was found, Instance already points to it.\r
+ //\r
+\r
+ //\r
+ // Free any allocated buffers\r
+ //\r
+ gBS->FreePool (HandleBuffer);\r
+\r
+ return Status;\r
+}\r
+\r
+\r
+VOID\r
+DsdtTableUpdate (\r
+ IN OUT EFI_ACPI_DESCRIPTION_HEADER *TableHeader,\r
+ IN OUT EFI_ACPI_TABLE_VERSION *Version\r
+ )\r
+/*++\r
+\r
+ Routine Description:\r
+\r
+ Update the DSDT table\r
+\r
+ Arguments:\r
+\r
+ Table - The table to be set\r
+ Version - Version to publish\r
+\r
+ Returns:\r
+\r
+ None\r
+\r
+--*/\r
+{\r
+\r
+ UINT8 *CurrPtr;\r
+ UINT8 *DsdtPointer;\r
+ UINT32 *Signature;\r
+ UINT8 *Operation;\r
+ UINT32 *Address;\r
+ UINT16 *Size;\r
+ //\r
+ // Loop through the ASL looking for values that we must fix up.\r
+ //\r
+ CurrPtr = (UINT8 *) TableHeader;\r
+ for (DsdtPointer = CurrPtr;\r
+ DsdtPointer <= (CurrPtr + ((EFI_ACPI_COMMON_HEADER *) CurrPtr)->Length);\r
+ DsdtPointer++\r
+ )\r
+ {\r
+ Signature = (UINT32 *) DsdtPointer;\r
+ switch (*Signature) {\r
+ //\r
+ // MNVS operation region\r
+ //\r
+ case (SIGNATURE_32 ('M', 'N', 'V', 'S')):\r
+ //\r
+ // Conditional match. For Region Objects, the Operator will always be the\r
+ // byte immediately before the specific name. Therefore, subtract 1 to check\r
+ // the Operator.\r
+ //\r
+ Operation = DsdtPointer - 1;\r
+ if (*Operation == AML_OPREGION_OP) {\r
+ Address = (UINT32 *) (DsdtPointer + 6);\r
+ *Address = (UINT32) (UINTN) mGlobalNvsArea.Area;\r
+ Size = (UINT16 *) (DsdtPointer + 11);\r
+ *Size = sizeof (EFI_GLOBAL_NVS_AREA);\r
+ }\r
+ break;\r
+\r
+ //\r
+ // Update processor PBLK register I/O base address\r
+ //\r
+ case (SIGNATURE_32 ('P', 'R', 'I', 'O')):\r
+ //\r
+ // Conditional match. Update the following ASL code:\r
+ // Processor (CPU0, 0x01, 0x4F495250, 0x06) {}\r
+ // The 3rd parameter will be updated to the actual PBLK I/O base address.\r
+ // the Operator.\r
+ //\r
+ Operation = DsdtPointer - 8;\r
+ if ((*Operation == AML_EXT_OP) && (*(Operation + 1) == AML_EXT_PROCESSOR_OP)) {\r
+ *(UINT32 *)DsdtPointer = PcdGet16(PcdPmbaIoBaseAddress);\r
+ }\r
+ break;\r
+ default:\r
+ break;\r
+ }\r
+ }\r
+}\r
+\r
+\r
+VOID\r
+ApicTableUpdate (\r
+ IN OUT EFI_ACPI_DESCRIPTION_HEADER *TableHeader,\r
+ IN OUT EFI_ACPI_TABLE_VERSION *Version\r
+ )\r
+/*++\r
+\r
+ Routine Description:\r
+\r
+ Update the processors information in the APIC table\r
+\r
+ Arguments:\r
+\r
+ Table - The table to be set\r
+ Version - Version to publish\r
+\r
+ Returns:\r
+\r
+ None\r
+\r
+--*/\r
+{\r
+ EFI_STATUS Status;\r
+ EFI_MP_SERVICES_PROTOCOL *MpService;\r
+ UINT8 *CurrPtr;\r
+ UINT8 *EndPtr;\r
+ UINT8 CurrIoApic;\r
+ UINT8 CurrProcessor;\r
+ UINTN NumberOfCPUs;\r
+ UINTN NumberOfEnabledCPUs;\r
+ UINTN BufferSize;\r
+ EFI_PROCESSOR_INFORMATION MpContext;\r
+ ACPI_APIC_STRUCTURE_PTR *ApicPtr;\r
+\r
+ CurrIoApic = 0;\r
+ CurrProcessor = 0;\r
+ //\r
+ // Find the MP Protocol. This is an MP platform, so MP protocol must be\r
+ // there.\r
+ //\r
+ Status = gBS->LocateProtocol (\r
+ &gEfiMpServiceProtocolGuid,\r
+ NULL,\r
+ (VOID**)&MpService\r
+ );\r
+ if (EFI_ERROR (Status)) {\r
+ //\r
+ // Failed to get MP information, doesn't publish the invalid table\r
+ //\r
+ *Version = EFI_ACPI_TABLE_VERSION_NONE;\r
+ return;\r
+ }\r
+\r
+ //\r
+ // Determine the number of processors\r
+ //\r
+ MpService->GetNumberOfProcessors (\r
+ MpService,\r
+ &NumberOfCPUs,\r
+ &NumberOfEnabledCPUs\r
+ );\r
+\r
+ CurrPtr = (UINT8*) &(TableHeader[1]);\r
+ CurrPtr = CurrPtr + 8; // Size of Local APIC Address & Flag\r
+ EndPtr = (UINT8*) TableHeader;\r
+ EndPtr = EndPtr + TableHeader->Length;\r
+\r
+ while (CurrPtr < EndPtr) {\r
+\r
+ ApicPtr = (ACPI_APIC_STRUCTURE_PTR*) CurrPtr;\r
+ switch (ApicPtr->AcpiApicCommon.Type) {\r
+\r
+ case EFI_ACPI_1_0_PROCESSOR_LOCAL_APIC:\r
+ BufferSize = sizeof (EFI_PROCESSOR_INFORMATION);\r
+ ApicPtr->AcpiLocalApic.Flags = 0;\r
+ ApicPtr->AcpiLocalApic.ApicId = 0;\r
+ Status = MpService->GetProcessorInfo (\r
+ MpService,\r
+ CurrProcessor,\r
+ &MpContext\r
+ );\r
+\r
+ if (!EFI_ERROR (Status)) {\r
+ if (MpContext.StatusFlag & PROCESSOR_ENABLED_BIT) {\r
+ ApicPtr->AcpiLocalApic.Flags = EFI_ACPI_3_0_LOCAL_APIC_ENABLED;\r
+ }\r
+ ApicPtr->AcpiLocalApic.ApicId = (UINT8)MpContext.ProcessorId;\r
+ }\r
+ CurrProcessor++;\r
+ break;\r
+\r
+ case EFI_ACPI_1_0_IO_APIC:\r
+ //\r
+ // IO APIC entries can be patched here\r
+ //\r
+ if (CurrIoApic == 0) {\r
+ //\r
+ // Update SOC internel IOAPIC base\r
+ //\r
+ ApicPtr->AcpiIoApic.IoApicId = PcdGet8 (PcdIoApicSettingIoApicId);\r
+ ApicPtr->AcpiIoApic.IoApicAddress = (UINT32)PcdGet64(PcdIoApicBaseAddress);\r
+ ApicPtr->AcpiIoApic.GlobalSystemInterruptBase = 0;\r
+ } else {\r
+ //\r
+ // Porting is required to update other IOAPIC entries if available\r
+ //\r
+ ASSERT (0);\r
+ }\r
+ CurrIoApic++;\r
+ break;\r
+\r
+ default:\r
+ break;\r
+ };\r
+ CurrPtr = CurrPtr + ApicPtr->AcpiApicCommon.Length;\r
+ }\r
+}\r
+\r
+VOID\r
+AcpiUpdateTable (\r
+ IN OUT EFI_ACPI_DESCRIPTION_HEADER *TableHeader,\r
+ IN OUT EFI_ACPI_TABLE_VERSION *Version\r
+ )\r
+/*++\r
+\r
+ Routine Description:\r
+\r
+ Set the correct table revision upon the setup value\r
+\r
+ Arguments:\r
+\r
+ Table - The table to be set\r
+ Version - Version to publish\r
+\r
+ Returns:\r
+\r
+ None\r
+\r
+--*/\r
+\r
+{\r
+ EFI_ACPI_1_0_FIXED_ACPI_DESCRIPTION_TABLE *FadtHeader1;\r
+ EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE *FadtHeader2;\r
+ EFI_ACPI_3_0_FIXED_ACPI_DESCRIPTION_TABLE *FadtHeader3;\r
+ EFI_ACPI_MEMORY_MAPPED_ENHANCED_CONFIGURATION_SPACE_BASE_ADDRESS_ALLOCATION_STRUCTURE *AllocationStructurePtr;\r
+\r
+ if (TableHeader != NULL && Version != NULL) {\r
+\r
+ *Version = EFI_ACPI_TABLE_VERSION_1_0B | EFI_ACPI_TABLE_VERSION_2_0 | EFI_ACPI_TABLE_VERSION_3_0;\r
+ //\r
+ // Here we use all 3.0 signature because all version use same signature if they supported\r
+ //\r
+ switch (TableHeader->Signature) {\r
+ //\r
+ // "APIC" Multiple APIC Description Table\r
+ //\r
+ case EFI_ACPI_3_0_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE:\r
+ ApicTableUpdate (TableHeader, Version);\r
+ break;\r
+ //\r
+ // "DSDT" Differentiated System Description Table\r
+ //\r
+ case EFI_ACPI_3_0_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE:\r
+ DsdtTableUpdate (TableHeader, Version);\r
+ break;\r
+\r
+ //\r
+ // "FACP" Fixed ACPI Description Table (FADT)\r
+ //\r
+ case EFI_ACPI_3_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE:\r
+ *Version = EFI_ACPI_TABLE_VERSION_NONE;\r
+ if (TableHeader->Revision == EFI_ACPI_1_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION) {\r
+ *Version = EFI_ACPI_TABLE_VERSION_1_0B;\r
+ FadtHeader1 = (EFI_ACPI_1_0_FIXED_ACPI_DESCRIPTION_TABLE *) TableHeader;\r
+ FadtHeader1->SmiCmd = PcdGet16(PcdSmmActivationPort);\r
+ FadtHeader1->Pm1aEvtBlk = PcdGet16(PcdPm1blkIoBaseAddress);\r
+ FadtHeader1->Pm1aCntBlk = PcdGet16(PcdPm1blkIoBaseAddress) + R_QNC_PM1BLK_PM1C;\r
+ FadtHeader1->PmTmrBlk = PcdGet16(PcdPm1blkIoBaseAddress) + R_QNC_PM1BLK_PM1T;\r
+ FadtHeader1->Gpe0Blk = PcdGet16(PcdGpe0blkIoBaseAddress);\r
+ } else if (TableHeader->Revision == EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION) {\r
+ *Version = EFI_ACPI_TABLE_VERSION_2_0;\r
+ FadtHeader2 = (EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE *) TableHeader;\r
+ FadtHeader2->SmiCmd = PcdGet16(PcdSmmActivationPort);\r
+ FadtHeader2->Pm1aEvtBlk = PcdGet16(PcdPm1blkIoBaseAddress);\r
+ FadtHeader2->Pm1aCntBlk = PcdGet16(PcdPm1blkIoBaseAddress) + R_QNC_PM1BLK_PM1C;\r
+ FadtHeader2->PmTmrBlk = PcdGet16(PcdPm1blkIoBaseAddress) + R_QNC_PM1BLK_PM1T;\r
+ FadtHeader2->Gpe0Blk = PcdGet16(PcdGpe0blkIoBaseAddress);\r
+ FadtHeader2->XPm1aEvtBlk.Address = FadtHeader2->Pm1aEvtBlk;\r
+ FadtHeader2->XPm1aCntBlk.Address = FadtHeader2->Pm1aCntBlk;\r
+ FadtHeader2->XPmTmrBlk.Address = FadtHeader2->PmTmrBlk;\r
+ FadtHeader2->XGpe0Blk.Address = FadtHeader2->Gpe0Blk;\r
+ } else if (TableHeader->Revision == EFI_ACPI_3_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION) {\r
+ *Version = EFI_ACPI_TABLE_VERSION_3_0;\r
+ FadtHeader3 = (EFI_ACPI_3_0_FIXED_ACPI_DESCRIPTION_TABLE *) TableHeader;\r
+ FadtHeader3->SmiCmd = PcdGet16(PcdSmmActivationPort);\r
+ FadtHeader3->Pm1aEvtBlk = PcdGet16(PcdPm1blkIoBaseAddress);\r
+ FadtHeader3->Pm1aCntBlk = PcdGet16(PcdPm1blkIoBaseAddress) + R_QNC_PM1BLK_PM1C;\r
+ FadtHeader3->PmTmrBlk = PcdGet16(PcdPm1blkIoBaseAddress) + R_QNC_PM1BLK_PM1T;\r
+ FadtHeader3->Gpe0Blk = PcdGet16(PcdGpe0blkIoBaseAddress);\r
+ FadtHeader3->XPm1aEvtBlk.Address = FadtHeader3->Pm1aEvtBlk;\r
+ FadtHeader3->XPm1aCntBlk.Address = FadtHeader3->Pm1aCntBlk;\r
+ FadtHeader3->XPmTmrBlk.Address = FadtHeader3->PmTmrBlk;\r
+ FadtHeader3->XGpe0Blk.Address = FadtHeader3->Gpe0Blk;\r
+ }\r
+ break;\r
+ //\r
+ // "FACS" Firmware ACPI Control Structure\r
+ //\r
+ case EFI_ACPI_3_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_SIGNATURE:\r
+ break;\r
+ //\r
+ // "SSDT" Secondary System Description Table\r
+ //\r
+ case EFI_ACPI_3_0_SECONDARY_SYSTEM_DESCRIPTION_TABLE_SIGNATURE:\r
+ break;\r
+ //\r
+ // "HPET" IA-PC High Precision Event Timer Table\r
+ //\r
+ case EFI_ACPI_3_0_HIGH_PRECISION_EVENT_TIMER_TABLE_SIGNATURE:\r
+ //\r
+ // If HPET is disabled in setup, don't publish the table.\r
+ //\r
+ if (mGlobalNvsArea.Area->HpetEnable == 0) {\r
+ *Version = EFI_ACPI_TABLE_VERSION_NONE;\r
+ }\r
+ ((EFI_ACPI_HIGH_PRECISION_EVENT_TIMER_TABLE_HEADER *) TableHeader)->BaseAddressLower32Bit.Address\r
+ = PcdGet64 (PcdHpetBaseAddress);\r
+ break;\r
+ //\r
+ // "SPCR" Serial Port Concole Redirection Table\r
+ //\r
+ case EFI_ACPI_3_0_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE:\r
+ break;\r
+ //\r
+ // "MCFG" PCI Express Memory Mapped Configuration Space Base Address Description Table\r
+ //\r
+ case EFI_ACPI_3_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE:\r
+ AllocationStructurePtr = (EFI_ACPI_MEMORY_MAPPED_ENHANCED_CONFIGURATION_SPACE_BASE_ADDRESS_ALLOCATION_STRUCTURE *)\r
+ ((UINT8 *)TableHeader + sizeof(EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE_HEADER));\r
+ AllocationStructurePtr->BaseAddress = PcdGet64(PcdPciExpressBaseAddress);\r
+ break;\r
+ // Lakeport platform doesn't support the following table\r
+ /*\r
+ //\r
+ // "ECDT" Embedded Controller Boot Resources Table\r
+ //\r
+ case EFI_ACPI_3_0_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE_SIGNATURE:\r
+ break;\r
+ //\r
+ // "PSDT" Persistent System Description Table\r
+ //\r
+ case EFI_ACPI_3_0_PERSISTENT_SYSTEM_DESCRIPTION_TABLE_SIGNATURE:\r
+ break;\r
+ //\r
+ // "SBST" Smart Battery Specification Table\r
+ //\r
+ case EFI_ACPI_3_0_SMART_BATTERY_SPECIFICATION_TABLE_SIGNATURE:\r
+ break;\r
+ //\r
+ // "SLIT" System Locality Information Table\r
+ //\r
+ case EFI_ACPI_3_0_SYSTEM_LOCALITY_INFORMATION_TABLE_SIGNATURE:\r
+ break;\r
+ //\r
+ // "SRAT" Static Resource Affinity Table\r
+ //\r
+ case EFI_ACPI_3_0_STATIC_RESOURCE_AFFINITY_TABLE_SIGNATURE:\r
+ break;\r
+ //\r
+ // "XSDT" Extended System Description Table\r
+ //\r
+ case EFI_ACPI_3_0_EXTENDED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE:\r
+ break;\r
+ //\r
+ // "BOOT" MS Simple Boot Spec\r
+ //\r
+ case EFI_ACPI_3_0_SIMPLE_BOOT_FLAG_TABLE_SIGNATURE:\r
+ break;\r
+ //\r
+ // "CPEP" Corrected Platform Error Polling Table\r
+ //\r
+ case EFI_ACPI_3_0_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_SIGNATURE:\r
+ break;\r
+ //\r
+ // "DBGP" MS Debug Port Spec\r
+ //\r
+ case EFI_ACPI_3_0_DEBUG_PORT_TABLE_SIGNATURE:\r
+ break;\r
+ //\r
+ // "ETDT" Event Timer Description Table\r
+ //\r
+ case EFI_ACPI_3_0_EVENT_TIMER_DESCRIPTION_TABLE_SIGNATURE:\r
+ break;\r
+ //\r
+ // "SPMI" Server Platform Management Interface Table\r
+ //\r
+ case EFI_ACPI_3_0_SERVER_PLATFORM_MANAGEMENT_INTERFACE_TABLE_SIGNATURE:\r
+ break;\r
+ //\r
+ // "TCPA" Trusted Computing Platform Alliance Capabilities Table\r
+ //\r
+ case EFI_ACPI_3_0_TRUSTED_COMPUTING_PLATFORM_ALLIANCE_CAPABILITIES_TABLE_SIGNATURE:\r
+ break;\r
+ */\r
+ default:\r
+ break;\r
+ }\r
+ }\r
+}\r
+\r
+//\r
+// Description:\r
+// Entrypoint of Acpi Platform driver\r
+// In:\r
+// ImageHandle\r
+// SystemTable\r
+// Out:\r
+// EFI_SUCCESS\r
+// EFI_LOAD_ERROR\r
+// EFI_OUT_OF_RESOURCES\r
+//\r
+\r
+EFI_STATUS\r
+AcpiPlatformEntryPoint (\r
+ IN EFI_HANDLE ImageHandle,\r
+ IN EFI_SYSTEM_TABLE *SystemTable\r
+ )\r
+{\r
+ EFI_STATUS Status;\r
+ EFI_ACPI_TABLE_PROTOCOL *AcpiTable;\r
+ EFI_FIRMWARE_VOLUME2_PROTOCOL *FwVol;\r
+ INTN Instance;\r
+ EFI_ACPI_COMMON_HEADER *CurrentTable;\r
+ UINTN TableHandle;\r
+ UINT32 FvStatus;\r
+ UINTN Size;\r
+ EFI_ACPI_TABLE_VERSION Version;\r
+ QNC_DEVICE_ENABLES QNCDeviceEnables;\r
+ EFI_HANDLE Handle;\r
+ UINTN Index;\r
+ PCI_DEVICE_INFO *PciDeviceInfo;\r
+ EFI_ACPI_HANDLE PciRootHandle;\r
+ BOOLEAN UpdatePRT;\r
+ BOOLEAN UpdatePRW;\r
+ PCI_DEVICE_SETTING *mConfigData;\r
+\r
+ DEBUG((DEBUG_INFO, "ACPI Platform start...\n"));\r
+\r
+ Instance = 0;\r
+ TableHandle = 0;\r
+ CurrentTable = NULL;\r
+ mConfigData = NULL;\r
+ QNCDeviceEnables.Uint32 = PcdGet32 (PcdDeviceEnables);\r
+\r
+ //\r
+ // Initialize the EFI Driver Library\r
+ //\r
+\r
+ ASSERT (sizeof (EFI_GLOBAL_NVS_AREA) == 512);\r
+\r
+ Status = gBS->AllocatePool (\r
+ EfiACPIMemoryNVS,\r
+ sizeof (EFI_GLOBAL_NVS_AREA),\r
+ (VOID**)&mGlobalNvsArea.Area\r
+ );\r
+\r
+ Handle = NULL;\r
+ Status = gBS->InstallProtocolInterface (\r
+ &Handle,\r
+ &gEfiGlobalNvsAreaProtocolGuid,\r
+ EFI_NATIVE_INTERFACE,\r
+ &mGlobalNvsArea\r
+ );\r
+\r
+ ASSERT_EFI_ERROR (Status);\r
+ if (!EFI_ERROR (Status)) {\r
+ SetMem (\r
+ mGlobalNvsArea.Area,\r
+ sizeof (EFI_GLOBAL_NVS_AREA),\r
+ 0\r
+ );\r
+ }\r
+\r
+ //\r
+ // Initialize the data. Eventually, this will be controlled by setup options.\r
+ //\r
+ mGlobalNvsArea.Area->HpetEnable = PcdGetBool (PcdHpetEnable);\r
+ mGlobalNvsArea.Area->Pm1blkIoBaseAddress = PcdGet16(PcdPm1blkIoBaseAddress);\r
+ mGlobalNvsArea.Area->PmbaIoBaseAddress = PcdGet16(PcdPmbaIoBaseAddress);\r
+ mGlobalNvsArea.Area->Gpe0blkIoBaseAddress = PcdGet16(PcdGpe0blkIoBaseAddress);\r
+ mGlobalNvsArea.Area->GbaIoBaseAddress = PcdGet16(PcdGbaIoBaseAddress);\r
+ mGlobalNvsArea.Area->SmbaIoBaseAddress = PcdGet16(PcdSmbaIoBaseAddress);\r
+ mGlobalNvsArea.Area->WdtbaIoBaseAddress = PcdGet16(PcdWdtbaIoBaseAddress);\r
+ mGlobalNvsArea.Area->HpetBaseAddress = (UINT32)PcdGet64(PcdHpetBaseAddress);\r
+ mGlobalNvsArea.Area->HpetSize = (UINT32)PcdGet64(PcdHpetSize);\r
+ mGlobalNvsArea.Area->PciExpressBaseAddress= (UINT32)PcdGet64(PcdPciExpressBaseAddress);\r
+ mGlobalNvsArea.Area->PciExpressSize = (UINT32)PcdGet64(PcdPciExpressSize);\r
+ mGlobalNvsArea.Area->RcbaMmioBaseAddress = (UINT32)PcdGet64(PcdRcbaMmioBaseAddress);\r
+ mGlobalNvsArea.Area->RcbaMmioSize = (UINT32)PcdGet64(PcdRcbaMmioSize);\r
+ mGlobalNvsArea.Area->IoApicBaseAddress = (UINT32)PcdGet64(PcdIoApicBaseAddress);\r
+ mGlobalNvsArea.Area->IoApicSize = (UINT32)PcdGet64(PcdIoApicSize);\r
+ mGlobalNvsArea.Area->TpmPresent = (UINT32)(FALSE);\r
+ mGlobalNvsArea.Area->DBG2Present = (UINT32)(FALSE);\r
+ mGlobalNvsArea.Area->PlatformType = (UINT32)PcdGet16 (PcdPlatformType);\r
+\r
+ //\r
+ // Configure platform IO expander I2C Slave Address.\r
+ //\r
+ if (mGlobalNvsArea.Area->PlatformType == Galileo) {\r
+ if (PlatformLegacyGpioGetLevel (R_QNC_GPIO_RGLVL_RESUME_WELL, GALILEO_DETERMINE_IOEXP_SLA_RESUMEWELL_GPIO)) {\r
+ mGlobalNvsArea.Area->AlternateSla = FALSE;\r
+ } else {\r
+ mGlobalNvsArea.Area->AlternateSla = TRUE;\r
+ }\r
+ }\r
+\r
+ //\r
+ // Find the AcpiTable protocol\r
+ //\r
+ Status = gBS->LocateProtocol (&gEfiAcpiTableProtocolGuid, NULL, (VOID**)&AcpiTable);\r
+ if (EFI_ERROR (Status)) {\r
+ return EFI_ABORTED;\r
+ }\r
+\r
+ //\r
+ // Initialize MADT table\r
+ //\r
+ Status = MadtTableInitialize (&CurrentTable, &Size);\r
+ ASSERT_EFI_ERROR (Status);\r
+ //\r
+ // Perform any table specific updates.\r
+ //\r
+ AcpiUpdateTable ((EFI_ACPI_DESCRIPTION_HEADER *) CurrentTable, &Version);\r
+\r
+ //\r
+ // Update the check sum\r
+ // It needs to be zeroed before the checksum calculation\r
+ //\r
+ ((EFI_ACPI_SDT_HEADER *)CurrentTable)->Checksum = 0;\r
+ ((EFI_ACPI_SDT_HEADER *)CurrentTable)->Checksum =\r
+ CalculateCheckSum8 ((VOID *)CurrentTable, CurrentTable->Length);\r
+\r
+ //\r
+ // Add the table\r
+ //\r
+ TableHandle = 0;\r
+ Status = AcpiTable->InstallAcpiTable (\r
+ AcpiTable,\r
+ CurrentTable,\r
+ CurrentTable->Length,\r
+ &TableHandle\r
+ );\r
+ ASSERT_EFI_ERROR (Status);\r
+ CurrentTable = NULL;\r
+\r
+ //\r
+ // Init Pci Device PRT PRW information structure from PCD\r
+ //\r
+ mConfigData = (PCI_DEVICE_SETTING *)AllocateZeroPool (sizeof (PCI_DEVICE_SETTING));\r
+ ASSERT_EFI_ERROR (mConfigData);\r
+ InitPciDeviceInfoStructure (mConfigData);\r
+ //\r
+ // Get the Acpi SDT protocol for manipulation on acpi table\r
+ //\r
+ Status = gBS->LocateProtocol (&gEfiAcpiSdtProtocolGuid, NULL, (VOID **)&mAcpiSdt);\r
+ ASSERT_EFI_ERROR (Status);\r
+ //\r
+ // Locate the firmware volume protocol\r
+ //\r
+ Status = LocateSupportProtocol (&gEfiFirmwareVolume2ProtocolGuid, (VOID**)&FwVol, 1);\r
+ if (EFI_ERROR (Status)) {\r
+ return EFI_ABORTED;\r
+ }\r
+ //\r
+ // Read tables from the storage file.\r
+ //\r
+\r
+ while (Status == EFI_SUCCESS) {\r
+\r
+ Status = FwVol->ReadSection (\r
+ FwVol,\r
+ (EFI_GUID*)PcdGetPtr (PcdAcpiTableStorageFile),\r
+ EFI_SECTION_RAW,\r
+ Instance,\r
+ (VOID**)&CurrentTable,\r
+ &Size,\r
+ &FvStatus\r
+ );\r
+\r
+ if (!EFI_ERROR(Status)) {\r
+ //\r
+ // Perform any table specific updates.\r
+ //\r
+ AcpiUpdateTable ((EFI_ACPI_DESCRIPTION_HEADER *) CurrentTable, &Version);\r
+\r
+ //\r
+ // Update the check sum\r
+ // It needs to be zeroed before the checksum calculation\r
+ //\r
+ ((EFI_ACPI_SDT_HEADER *)CurrentTable)->Checksum = 0;\r
+ ((EFI_ACPI_SDT_HEADER *)CurrentTable)->Checksum =\r
+ CalculateCheckSum8 ((VOID *)CurrentTable, CurrentTable->Length);\r
+\r
+ //\r
+ // Add the table\r
+ //\r
+ TableHandle = 0;\r
+ Status = AcpiTable->InstallAcpiTable (\r
+ AcpiTable,\r
+ CurrentTable,\r
+ ((EFI_ACPI_DESCRIPTION_HEADER *) CurrentTable)->Length,\r
+ &TableHandle\r
+ );\r
+ if (EFI_ERROR(Status)) {\r
+ return EFI_ABORTED;\r
+ }\r
+ //\r
+ // If this table is the DSDT table, then update the _PRT and _PRW based on\r
+ // the settings from pcds\r
+ //\r
+ if (CurrentTable->Signature == EFI_ACPI_2_0_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE) {\r
+ //\r
+ // Create the root handle for DSDT table\r
+ //\r
+ Status = mAcpiSdt->OpenSdt (TableHandle, &mDsdtHandle);\r
+ ASSERT_EFI_ERROR (Status);\r
+\r
+ PciRootHandle = NULL;\r
+ PciRootHandle = SdtGetRootBridgeHandle (mAcpiSdt, mDsdtHandle);\r
+ ASSERT (PciRootHandle != NULL);\r
+\r
+ PciDeviceInfo = NULL;\r
+ for (Index = 0; Index < mConfigData->PciDeviceInfoNumber; Index++) {\r
+ PciDeviceInfo = &(mConfigData->PciDeviceInfo[Index]);\r
+\r
+ //\r
+ // Check whether this is a valid item\r
+ //\r
+ if ((PciDeviceInfo->BridgeAddress != 0xFFFFFFFF) && (PciDeviceInfo->DeviceAddress != 0xFFFFFFFF)) {\r
+\r
+ //DEBUG ((EFI_D_ERROR, "Valid pci info structure: bridge address:0x%x, device address:0x%x\n", PciDeviceInfo->BridgeAddress, PciDeviceInfo->DeviceAddress));\r
+\r
+ UpdatePRT = FALSE;\r
+ UpdatePRW = FALSE;\r
+\r
+ SdtCheckPciDeviceInfoChanged (PciDeviceInfo, &UpdatePRT, &UpdatePRW);\r
+ //\r
+ // Check whether there is any valid pci routing item\r
+ //\r
+ if (UpdatePRT) {\r
+ //\r
+ // Update the pci routing information\r
+ //\r
+ //DEBUG ((EFI_D_ERROR, "Update _PRT\n"));\r
+ SdtUpdatePciRouting (mAcpiSdt, PciRootHandle, PciDeviceInfo);\r
+ }\r
+ //\r
+ // Check whether there is any valid pci routing item\r
+ //\r
+ if (UpdatePRW) {\r
+ //\r
+ // Update the pci wakeup information\r
+ //\r
+ //DEBUG ((EFI_D_ERROR, "Update _PRW\n"));\r
+ SdtUpdatePowerWake (mAcpiSdt, PciRootHandle, PciDeviceInfo);\r
+ }\r
+ }\r
+ }\r
+ Status = mAcpiSdt->Close (PciRootHandle);\r
+ ASSERT_EFI_ERROR (Status);\r
+ //\r
+ // Mark the root handle as modified , let SDT protocol recaculate the checksum\r
+ //\r
+ ((EFI_AML_HANDLE *)mDsdtHandle)->Modified = TRUE;\r
+ Status = mAcpiSdt->Close (mDsdtHandle);\r
+ ASSERT_EFI_ERROR (Status);\r
+ }\r
+ //\r
+ // Increment the instance\r
+ //\r
+ Instance++;\r
+ CurrentTable = NULL;\r
+ }\r
+ }\r
+\r
+ gBS->FreePool (mConfigData);\r
+ return EFI_SUCCESS;\r
+}\r
--- /dev/null
+/** @file\r
+This is an implementation of the ACPI platform driver. Requirements for\r
+this driver are defined in the Tiano ACPI External Product Specification,\r
+revision 0.3.6.\r
+\r
+Copyright (c) 2013-2015 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+**/\r
+\r
+#ifndef _ACPI_PLATFORM_H_\r
+#define _ACPI_PLATFORM_H_\r
+\r
+//\r
+// Statements that include other header files\r
+//\r
+\r
+#include <PiDxe.h>\r
+#include <IntelQNCDxe.h>\r
+#include <Platform.h>\r
+#include <PlatformBoards.h>\r
+#include <Ioh.h>\r
+#include <QNCCommonDefinitions.h>\r
+\r
+#include <Protocol/GlobalNvsArea.h>\r
+#include <Protocol/MpService.h>\r
+#include <Protocol/AcpiSystemDescriptionTable.h>\r
+#include <Protocol/FirmwareVolume2.h>\r
+\r
+#include <Library/UefiDriverEntryPoint.h>\r
+#include <Library/UefiBootServicesTableLib.h>\r
+#include <Library/UefiRuntimeServicesTableLib.h>\r
+#include <Library/DebugLib.h>\r
+#include <Library/BaseMemoryLib.h>\r
+#include <Library/IoLib.h>\r
+#include <Library/PcdLib.h>\r
+#include <Library/UefiLib.h>\r
+#include <Library/DxeServicesLib.h>\r
+#include <Library/DevicePathLib.h>\r
+#include <Library/MemoryAllocationLib.h>\r
+#include <Library/QNCAccessLib.h>\r
+#include <Library/PlatformHelperLib.h>\r
+\r
+#include <IndustryStandard/Acpi.h>\r
+#include <IndustryStandard/HighPrecisionEventTimerTable.h>\r
+#include <IndustryStandard/MemoryMappedConfigurationSpaceAccessTable.h>\r
+\r
+#include "Madt.h"\r
+#include "AcpiPciUpdate.h"\r
+\r
+#pragma pack(1)\r
+typedef struct {\r
+ UINT8 StartByte;\r
+ UINT32 NameStr;\r
+ UINT8 OpCode;\r
+ UINT16 Size; // Hardcode to 16bit width because the table we use is fixed size\r
+ UINT8 NumEntries;\r
+} EFI_ACPI_NAME_COMMAND;\r
+\r
+typedef struct {\r
+ UINT8 PackageOp;\r
+ UINT8 PkgLeadByte;\r
+ UINT8 NumEntries;\r
+ UINT8 DwordPrefix0;\r
+ UINT32 CoreFreq;\r
+ UINT8 DwordPrefix1;\r
+ UINT32 Power;\r
+ UINT8 DwordPrefix2;\r
+ UINT32 TransLatency;\r
+ UINT8 DwordPrefix3;\r
+ UINT32 BMLatency;\r
+ UINT8 DwordPrefix4;\r
+ UINT32 Control;\r
+ UINT8 DwordPrefix5;\r
+ UINT32 Status;\r
+} EFI_PSS_PACKAGE;\r
+#pragma pack()\r
+\r
+\r
+#define AML_NAME_OP 0x08\r
+#define AML_METHOD_OP 0x14\r
+#define AML_OPREGION_OP 0x80\r
+#define AML_PACKAGE_OP 0x12 // Package operator.\r
+\r
+//\r
+// ACPI table information used to initialize tables.\r
+//\r
+#define EFI_ACPI_OEM_ID "INTEL "\r
+#define EFI_ACPI_OEM_TABLE_ID 0x2020204F4E414954ULL // "TIANO "\r
+#define EFI_ACPI_OEM_REVISION 0x00000002\r
+#define EFI_ACPI_CREATOR_ID 0x5446534D // "MSFT"\r
+#define EFI_ACPI_CREATOR_REVISION 0x01000013\r
+\r
+#define ACPI_COMPATIBLE_1_0 0\r
+#define ACPI_COMPATIBLE_2_0 1\r
+#define ACPI_COMPATIBLE_3_0 2\r
+\r
+\r
+\r
+\r
+//\r
+// Private Driver Data\r
+//\r
+\r
+//\r
+// Define Union of IO APIC & Local APIC structure;\r
+//\r
+\r
+typedef union {\r
+ EFI_ACPI_2_0_PROCESSOR_LOCAL_APIC_STRUCTURE AcpiLocalApic;\r
+ EFI_ACPI_2_0_IO_APIC_STRUCTURE AcpiIoApic;\r
+ struct {\r
+ UINT8 Type;\r
+ UINT8 Length;\r
+ } AcpiApicCommon;\r
+} ACPI_APIC_STRUCTURE_PTR;\r
+\r
+#endif\r
--- /dev/null
+## @file\r
+# Component description file for AcpiPlatform module.\r
+#\r
+# This is an implementation of the ACPI platform driver,\r
+# whose requirements are from ACPI External Product Specification.\r
+# Copyright (c) 2013-2015 Intel Corporation.\r
+#\r
+# This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution. The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php\r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+##\r
+\r
+[Defines]\r
+ INF_VERSION = 0x00010005\r
+ BASE_NAME = AcpiPlatform\r
+ FILE_GUID = 368B3649-F204-4cd0-89A8-091077C070FA\r
+ MODULE_TYPE = DXE_DRIVER\r
+ VERSION_STRING = 1.0\r
+ ENTRY_POINT = AcpiPlatformEntryPoint\r
+\r
+#\r
+# The following information is for reference only and not required by the build tools.\r
+#\r
+# VALID_ARCHITECTURES = IA32 X64 IPF EBC\r
+#\r
+\r
+[Sources]\r
+ AcpiPlatform.c\r
+ AcpiPlatform.h\r
+ MadtPlatform.c\r
+ Madt.h\r
+ AcpiPciUpdate.c\r
+ AcpiPciUpdate.h\r
+\r
+[Packages]\r
+ MdePkg/MdePkg.dec\r
+ MdeModulePkg/MdeModulePkg.dec\r
+ UefiCpuPkg/UefiCpuPkg.dec\r
+ QuarkSocPkg/QuarkSocPkg.dec\r
+ QuarkPlatformPkg/QuarkPlatformPkg.dec\r
+\r
+[LibraryClasses]\r
+ UefiLib\r
+ DxeServicesLib\r
+ PcdLib\r
+ IoLib\r
+ BaseMemoryLib\r
+ DebugLib\r
+ UefiRuntimeServicesTableLib\r
+ UefiBootServicesTableLib\r
+ UefiDriverEntryPoint\r
+ DevicePathLib\r
+ PlatformHelperLib\r
+\r
+[Protocols]\r
+ gEfiGlobalNvsAreaProtocolGuid # PROTOCOL ALWAYS_CONSUMED\r
+ gEfiMpServiceProtocolGuid # PROTOCOL SOMETIMES_CONSUMED\r
+ gEfiAcpiSdtProtocolGuid # PROTOCOL ALWAYS_CONSUMED\r
+ gEfiAcpiTableProtocolGuid # PROTOCOL ALWAYS_CONSUMED\r
+\r
+[Pcd]\r
+ gQuarkPlatformTokenSpaceGuid.PcdPlatformType\r
+\r
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuLocalApicBaseAddress\r
+\r
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable0Enable\r
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable0SourceIrq\r
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable0Polarity\r
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable0TrigerMode\r
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable0GlobalIrq\r
+\r
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable1Enable\r
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable1SourceIrq\r
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable1Polarity\r
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable1TrigerMode\r
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable1GlobalIrq\r
+\r
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable2Enable\r
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable2SourceIrq\r
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable2Polarity\r
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable2TrigerMode\r
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable2GlobalIrq\r
+\r
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable3Enable\r
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable3SourceIrq\r
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable3Polarity\r
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable3TrigerMode\r
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable3GlobalIrq\r
+\r
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable4Enable\r
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable4SourceIrq\r
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable4Polarity\r
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable4TrigerMode\r
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable4GlobalIrq\r
+\r
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable5Enable\r
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable5SourceIrq\r
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable5Polarity\r
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable5TrigerMode\r
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable5GlobalIrq\r
+\r
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable6Enable\r
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable6SourceIrq\r
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable6Polarity\r
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable6TrigerMode\r
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable6GlobalIrq\r
+\r
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable7Enable\r
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable7SourceIrq\r
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable7Polarity\r
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable7TrigerMode\r
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable7GlobalIrq\r
+\r
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable8Enable\r
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable8SourceIrq\r
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable8Polarity\r
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable8TrigerMode\r
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable8GlobalIrq\r
+\r
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable9Enable\r
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable9SourceIrq\r
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable9Polarity\r
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable9TrigerMode\r
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable9GlobalIrq\r
+\r
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable10Enable\r
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable10SourceIrq\r
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable10Polarity\r
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable10TrigerMode\r
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable10GlobalIrq\r
+\r
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable11Enable\r
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable11SourceIrq\r
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable11Polarity\r
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable11TrigerMode\r
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable11GlobalIrq\r
+\r
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable12Enable\r
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable12SourceIrq\r
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable12Polarity\r
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable12TrigerMode\r
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable12GlobalIrq\r
+\r
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable13Enable\r
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable13SourceIrq\r
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable13Polarity\r
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable13TrigerMode\r
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable13GlobalIrq\r
+\r
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable14Enable\r
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable14SourceIrq\r
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable14Polarity\r
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable14TrigerMode\r
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable14GlobalIrq\r
+\r
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable15Enable\r
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable15SourceIrq\r
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable15Polarity\r
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable15TrigerMode\r
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable15GlobalIrq\r
+\r
+ gEfiQuarkNcSocIdTokenSpaceGuid.PcdIoApicBaseAddress\r
+ gQuarkPlatformTokenSpaceGuid.PcdIoApicSettingIoApicAddress\r
+ gQuarkPlatformTokenSpaceGuid.PcdIoApicSettingGlobalInterruptBase\r
+ gQuarkPlatformTokenSpaceGuid.PcdIoApicSettingIoApicId\r
+ gQuarkPlatformTokenSpaceGuid.PcdIoApicSettingNmiEnable\r
+ gQuarkPlatformTokenSpaceGuid.PcdIoApicSettingNmiSource\r
+ gQuarkPlatformTokenSpaceGuid.PcdIoApicSettingPolarity\r
+ gQuarkPlatformTokenSpaceGuid.PcdIoApicSettingTrigerMode\r
+ gQuarkPlatformTokenSpaceGuid.PcdLocalApicSettingNmiEnabelApicIdMask\r
+ gQuarkPlatformTokenSpaceGuid.PcdLocalApicSettingAddressOverrideEnable\r
+ gQuarkPlatformTokenSpaceGuid.PcdLocalApicSettingPolarity\r
+ gQuarkPlatformTokenSpaceGuid.PcdLocalApicSettingTrigerMode\r
+ gQuarkPlatformTokenSpaceGuid.PcdLocalApicSettingLocalApicLint\r
+ gQuarkPlatformTokenSpaceGuid.PcdLocalApicAddressOverride\r
+\r
+ gEfiQuarkNcSocIdTokenSpaceGuid.PcdSmmActivationPort\r
+ gEfiQuarkNcSocIdTokenSpaceGuid.PcdPm1blkIoBaseAddress\r
+ gEfiQuarkNcSocIdTokenSpaceGuid.PcdGpe0blkIoBaseAddress\r
+ gEfiQuarkNcSocIdTokenSpaceGuid.PcdPmbaIoBaseAddress\r
+ gEfiQuarkNcSocIdTokenSpaceGuid.PcdGbaIoBaseAddress\r
+ gEfiQuarkNcSocIdTokenSpaceGuid.PcdSmbaIoBaseAddress\r
+ gEfiQuarkNcSocIdTokenSpaceGuid.PcdHpetBaseAddress\r
+ gEfiQuarkNcSocIdTokenSpaceGuid.PcdHpetSize\r
+ gEfiQuarkNcSocIdTokenSpaceGuid.PcdIoApicBaseAddress\r
+ gEfiQuarkNcSocIdTokenSpaceGuid.PcdIoApicSize\r
+ gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress\r
+ gEfiQuarkNcSocIdTokenSpaceGuid.PcdPciExpressSize\r
+ gEfiQuarkNcSocIdTokenSpaceGuid.PcdRcbaMmioBaseAddress\r
+ gEfiQuarkNcSocIdTokenSpaceGuid.PcdRcbaMmioSize\r
+ gEfiQuarkNcSocIdTokenSpaceGuid.PcdWdtbaIoBaseAddress\r
+ gQuarkPlatformTokenSpaceGuid.PcdHpetEnable\r
+ gEfiQuarkNcSocIdTokenSpaceGuid.PcdDeviceEnables\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiTableStorageFile\r
+\r
+[Depex]\r
+ gEfiMpServiceProtocolGuid AND gEfiAcpiTableProtocolGuid\r
--- /dev/null
+/** @file\r
+This file describes the contents of the ACPI Multiple APIC Description\r
+Table (MADT). Some additional ACPI values are defined in Acpi10.h and\r
+Acpi20.h.\r
+To make changes to the MADT, it is necessary to update the count for the\r
+APIC structure being updated, and to modify table found in Madt.c.\r
+\r
+Copyright (c) 2013-2015 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+**/\r
+\r
+#ifndef _MADT_H\r
+#define _MADT_H\r
+\r
+\r
+//\r
+// Statements that include other files\r
+//\r
+\r
+#include <IndustryStandard/Acpi.h>\r
+#include <Library/PcdLib.h>\r
+\r
+//\r
+// MADT Definitions\r
+//\r
+\r
+#define EFI_ACPI_OEM_MADT_REVISION 0x00000001\r
+\r
+//\r
+// Local APIC address\r
+//\r
+\r
+#define EFI_ACPI_LOCAL_APIC_ADDRESS 0xFEE00000\r
+\r
+//\r
+// Multiple APIC Flags are defined in AcpiX.0.h\r
+//\r
+#define EFI_ACPI_1_0_MULTIPLE_APIC_FLAGS (EFI_ACPI_1_0_PCAT_COMPAT)\r
+#define EFI_ACPI_2_0_MULTIPLE_APIC_FLAGS (EFI_ACPI_2_0_PCAT_COMPAT)\r
+\r
+//\r
+// Define the number of each table type.\r
+// This is where the table layout is modified.\r
+//\r
+\r
+#define EFI_ACPI_PROCESSOR_LOCAL_APIC_COUNT 2\r
+#define EFI_ACPI_IO_APIC_COUNT 1\r
+#define EFI_ACPI_INTERRUPT_SOURCE_OVERRIDE_COUNT 2\r
+#define EFI_ACPI_NON_MASKABLE_INTERRUPT_SOURCE_COUNT 0\r
+#define EFI_ACPI_LOCAL_APIC_NMI_COUNT 2\r
+#define EFI_ACPI_LOCAL_APIC_ADDRESS_OVERRIDE_COUNT 0\r
+#define EFI_ACPI_IO_SAPIC_COUNT 0\r
+#define EFI_ACPI_PROCESSOR_LOCAL_SAPIC_COUNT 0\r
+#define EFI_ACPI_PLATFORM_INTERRUPT_SOURCES_COUNT 0\r
+\r
+#define EFI_ACPI_INTERRUPT_SOURCE_OVERRIDE_COUNT_MAX 16\r
+\r
+//\r
+// MADT structure\r
+//\r
+\r
+//\r
+// Ensure proper structure formats\r
+//\r
+#pragma pack (1)\r
+\r
+//\r
+// ACPI 1.0 Table structure\r
+//\r
+typedef struct {\r
+ EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header;\r
+\r
+#if EFI_ACPI_PROCESSOR_LOCAL_APIC_COUNT > 0\r
+ EFI_ACPI_1_0_PROCESSOR_LOCAL_APIC_STRUCTURE LocalApic[EFI_ACPI_PROCESSOR_LOCAL_APIC_COUNT];\r
+#endif\r
+\r
+#if EFI_ACPI_IO_APIC_COUNT > 0\r
+ EFI_ACPI_1_0_IO_APIC_STRUCTURE IoApic[EFI_ACPI_IO_APIC_COUNT];\r
+#endif\r
+\r
+#if EFI_ACPI_INTERRUPT_SOURCE_OVERRIDE_COUNT > 0\r
+ EFI_ACPI_1_0_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE Iso[EFI_ACPI_INTERRUPT_SOURCE_OVERRIDE_COUNT];\r
+#endif\r
+\r
+#if EFI_ACPI_NON_MASKABLE_INTERRUPT_SOURCE_COUNT > 0\r
+ EFI_ACPI_1_0_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE NmiSource[EFI_ACPI_NON_MASKABLE_INTERRUPT_SOURCE_COUNT];\r
+#endif\r
+\r
+#if EFI_ACPI_LOCAL_APIC_NMI_COUNT > 0\r
+ EFI_ACPI_1_0_LOCAL_APIC_NMI_STRUCTURE LocalApicNmi[EFI_ACPI_LOCAL_APIC_NMI_COUNT];\r
+#endif\r
+\r
+#if EFI_ACPI_LOCAL_APIC_ADDRESS_OVERRIDE_COUNT > 0\r
+ EFI_ACPI_1_0_LOCAL_APIC_ADDRESS_OVERRIDE_STRUCTURE LocalApicOverride[EFI_ACPI_LOCAL_APIC_OVERRIDE_COUNT];\r
+#endif\r
+\r
+} EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE;\r
+\r
+//\r
+// ACPI 2.0 Table structure\r
+//\r
+typedef struct {\r
+ EFI_ACPI_2_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header;\r
+\r
+#if EFI_ACPI_PROCESSOR_LOCAL_APIC_COUNT > 0\r
+ EFI_ACPI_2_0_PROCESSOR_LOCAL_APIC_STRUCTURE LocalApic[EFI_ACPI_PROCESSOR_LOCAL_APIC_COUNT];\r
+#endif\r
+\r
+#if EFI_ACPI_IO_APIC_COUNT > 0\r
+ EFI_ACPI_2_0_IO_APIC_STRUCTURE IoApic[EFI_ACPI_IO_APIC_COUNT];\r
+#endif\r
+\r
+#if EFI_ACPI_INTERRUPT_SOURCE_OVERRIDE_COUNT > 0\r
+ EFI_ACPI_2_0_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE Iso[EFI_ACPI_INTERRUPT_SOURCE_OVERRIDE_COUNT];\r
+#endif\r
+\r
+#if EFI_ACPI_NON_MASKABLE_INTERRUPT_SOURCE_COUNT > 0\r
+ EFI_ACPI_2_0_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE NmiSource[EFI_ACPI_NON_MASKABLE_INTERRUPT_SOURCE_COUNT];\r
+#endif\r
+\r
+#if EFI_ACPI_LOCAL_APIC_NMI_COUNT > 0\r
+ EFI_ACPI_2_0_LOCAL_APIC_NMI_STRUCTURE LocalApicNmi[EFI_ACPI_LOCAL_APIC_NMI_COUNT];\r
+#endif\r
+\r
+#if EFI_ACPI_LOCAL_APIC_ADDRESS_OVERRIDE_COUNT > 0\r
+ EFI_ACPI_2_0_LOCAL_APIC_ADDRESS_OVERRIDE_STRUCTURE LocalApicOverride[EFI_ACPI_LOCAL_APIC_ADDRESS_OVERRIDE_COUNT];\r
+#endif\r
+\r
+#if EFI_ACPI_IO_SAPIC_COUNT > 0\r
+ EFI_ACPI_2_0_IO_SAPIC_STRUCTURE IoSapic[EFI_ACPI_IO_SAPIC_COUNT];\r
+#endif\r
+\r
+#if EFI_ACPI_PROCESSOR_LOCAL_SAPIC_COUNT > 0\r
+ EFI_ACPI_2_0_PROCESSOR_LOCAL_SAPIC_STRUCTURE LocalSapic[EFI_ACPI_PROCESSOR_LOCAL_SAPIC_COUNT];\r
+#endif\r
+\r
+#if EFI_ACPI_PLATFORM_INTERRUPT_SOURCES_COUNT > 0\r
+ EFI_ACPI_2_0_PLATFORM_INTERRUPT_SOURCES_STRUCTURE PlatformInterruptSources[EFI_ACPI_PLATFORM_INTERRUPT_SOURCES_COUNT];\r
+#endif\r
+\r
+} EFI_ACPI_2_0_MULTIPLE_APIC_DESCRIPTION_TABLE;\r
+\r
+#define _PcdIntSettingTblEnable(x) PcdGet8 (PcdInterruptOverrideSettingTable##x##Enable)\r
+#define PcdIntSettingTblEnable(x) _PcdIntSettingTblEnable(x)\r
+\r
+#define _PcdIntSettingTblSourceIrq(x) PcdGet8 (PcdInterruptOverrideSettingTable##x##Enable)\r
+#define PcdIntSettingTblSourceIrq(x) _PcdIntSettingTblSourceIrq(x)\r
+\r
+#define _PcdIntSettingTblPolarity(x) PcdGet8 (PcdInterruptOverrideSettingTable##x##Polarity)\r
+#define PcdIntSettingTblPolarity(x) _PcdIntSettingTblPolarity(x)\r
+\r
+#define _PcdIntSettingTableTrigerMode(x) PcdGet8 (PcdInterruptOverrideSettingTable##x##TrigerMode)\r
+#define PcdIntSettingTableTrigerMode(x) _PcdIntSettingTableTrigerMode(x)\r
+\r
+#define _PcdIntSettingTableGlobalIrq(x) PcdGet32 (PcdInterruptOverrideSettingTable##x##GlobalIrq)\r
+#define PcdIntSettingTableGlobalIrq(x) _PcdIntSettingTableGlobalIrq(x)\r
+\r
+typedef struct {\r
+ UINT8 Enable;\r
+ UINT8 SourceIrq;\r
+ UINT8 Polarity;\r
+ UINT8 TrigerMode;\r
+ UINT32 GlobalIrq;\r
+} INTERRUPT_OVERRIDE_SETTING;\r
+\r
+\r
+typedef struct {\r
+ UINT32 IoApicAddress;\r
+ UINT32 GlobalInterruptBase;\r
+ UINT8 IoApicId;\r
+ UINT8 NmiEnable;\r
+ UINT8 NmiSource;\r
+ UINT8 Polarity;\r
+ UINT8 TrigerMode;\r
+} IO_APIC_SETTING;\r
+\r
+typedef struct {\r
+ UINT8 NmiEnabelApicIdMask;\r
+ UINT8 AddressOverrideEnable;\r
+ UINT8 Polarity;\r
+ UINT8 TrigerMode;\r
+ UINT8 LocalApicLint;\r
+ UINT8 Reserve[3];\r
+ UINT32 LocalApicAddress;\r
+ UINT64 LocalApicAddressOverride;\r
+} LOCAL_APIC_SETTING;\r
+\r
+typedef struct _MADT_CONFIG_DATA {\r
+ INTERRUPT_OVERRIDE_SETTING MadtInterruptSetting[EFI_ACPI_INTERRUPT_SOURCE_OVERRIDE_COUNT_MAX];\r
+ IO_APIC_SETTING MadtIoApicSetting;\r
+ LOCAL_APIC_SETTING MadtLocalApicSetting;\r
+}MADT_CONFIG_DATA;\r
+\r
+#pragma pack ()\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+MadtTableInitialize (\r
+ OUT EFI_ACPI_COMMON_HEADER **MadtTable,\r
+ OUT UINTN *Size\r
+ );\r
+\r
+\r
+#endif\r
--- /dev/null
+/** @file\r
+This file contains Madt Talbe initialized work.\r
+\r
+Copyright (c) 2013-2015 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+**/\r
+\r
+//\r
+// Statements that include other files\r
+//\r
+\r
+#include "AcpiPlatform.h"\r
+\r
+VOID\r
+InitMadtConfigData (MADT_CONFIG_DATA *mConfigData)\r
+{\r
+ mConfigData->MadtInterruptSetting[0].Enable = PcdGet8 (PcdInterruptOverrideSettingTable0Enable);\r
+ mConfigData->MadtInterruptSetting[0].SourceIrq = PcdGet8 (PcdInterruptOverrideSettingTable0SourceIrq);\r
+ mConfigData->MadtInterruptSetting[0].Polarity = PcdGet8 (PcdInterruptOverrideSettingTable0Polarity);\r
+ mConfigData->MadtInterruptSetting[0].TrigerMode = PcdGet8 (PcdInterruptOverrideSettingTable0TrigerMode);\r
+ mConfigData->MadtInterruptSetting[0].GlobalIrq = PcdGet32 (PcdInterruptOverrideSettingTable0GlobalIrq);\r
+\r
+ mConfigData->MadtInterruptSetting[1].Enable = PcdGet8 (PcdInterruptOverrideSettingTable1Enable);\r
+ mConfigData->MadtInterruptSetting[1].SourceIrq = PcdGet8 (PcdInterruptOverrideSettingTable1SourceIrq);\r
+ mConfigData->MadtInterruptSetting[1].Polarity = PcdGet8 (PcdInterruptOverrideSettingTable1Polarity);\r
+ mConfigData->MadtInterruptSetting[1].TrigerMode = PcdGet8 (PcdInterruptOverrideSettingTable1TrigerMode);\r
+ mConfigData->MadtInterruptSetting[1].GlobalIrq = PcdGet32 (PcdInterruptOverrideSettingTable1GlobalIrq);\r
+\r
+ mConfigData->MadtInterruptSetting[2].Enable = PcdGet8 (PcdInterruptOverrideSettingTable2Enable);\r
+ mConfigData->MadtInterruptSetting[2].SourceIrq = PcdGet8 (PcdInterruptOverrideSettingTable2SourceIrq);\r
+ mConfigData->MadtInterruptSetting[2].Polarity = PcdGet8 (PcdInterruptOverrideSettingTable2Polarity);\r
+ mConfigData->MadtInterruptSetting[2].TrigerMode = PcdGet8 (PcdInterruptOverrideSettingTable2TrigerMode);\r
+ mConfigData->MadtInterruptSetting[2].GlobalIrq = PcdGet32 (PcdInterruptOverrideSettingTable2GlobalIrq);\r
+\r
+ mConfigData->MadtInterruptSetting[3].Enable = PcdGet8 (PcdInterruptOverrideSettingTable3Enable);\r
+ mConfigData->MadtInterruptSetting[3].SourceIrq = PcdGet8 (PcdInterruptOverrideSettingTable3SourceIrq);\r
+ mConfigData->MadtInterruptSetting[3].Polarity = PcdGet8 (PcdInterruptOverrideSettingTable3Polarity);\r
+ mConfigData->MadtInterruptSetting[3].TrigerMode = PcdGet8 (PcdInterruptOverrideSettingTable3TrigerMode);\r
+ mConfigData->MadtInterruptSetting[3].GlobalIrq = PcdGet32 (PcdInterruptOverrideSettingTable3GlobalIrq);\r
+\r
+ mConfigData->MadtInterruptSetting[4].Enable = PcdGet8 (PcdInterruptOverrideSettingTable4Enable);\r
+ mConfigData->MadtInterruptSetting[4].SourceIrq = PcdGet8 (PcdInterruptOverrideSettingTable4SourceIrq);\r
+ mConfigData->MadtInterruptSetting[4].Polarity = PcdGet8 (PcdInterruptOverrideSettingTable4Polarity);\r
+ mConfigData->MadtInterruptSetting[4].TrigerMode = PcdGet8 (PcdInterruptOverrideSettingTable4TrigerMode);\r
+ mConfigData->MadtInterruptSetting[4].GlobalIrq = PcdGet32 (PcdInterruptOverrideSettingTable4GlobalIrq);\r
+\r
+ mConfigData->MadtInterruptSetting[5].Enable = PcdGet8 (PcdInterruptOverrideSettingTable5Enable);\r
+ mConfigData->MadtInterruptSetting[5].SourceIrq = PcdGet8 (PcdInterruptOverrideSettingTable5SourceIrq);\r
+ mConfigData->MadtInterruptSetting[5].Polarity = PcdGet8 (PcdInterruptOverrideSettingTable5Polarity);\r
+ mConfigData->MadtInterruptSetting[5].TrigerMode = PcdGet8 (PcdInterruptOverrideSettingTable5TrigerMode);\r
+ mConfigData->MadtInterruptSetting[5].GlobalIrq = PcdGet32 (PcdInterruptOverrideSettingTable5GlobalIrq);\r
+\r
+ mConfigData->MadtInterruptSetting[6].Enable = PcdGet8 (PcdInterruptOverrideSettingTable6Enable);\r
+ mConfigData->MadtInterruptSetting[6].SourceIrq = PcdGet8 (PcdInterruptOverrideSettingTable6SourceIrq);\r
+ mConfigData->MadtInterruptSetting[6].Polarity = PcdGet8 (PcdInterruptOverrideSettingTable6Polarity);\r
+ mConfigData->MadtInterruptSetting[6].TrigerMode = PcdGet8 (PcdInterruptOverrideSettingTable6TrigerMode);\r
+ mConfigData->MadtInterruptSetting[6].GlobalIrq = PcdGet32 (PcdInterruptOverrideSettingTable6GlobalIrq);\r
+\r
+ mConfigData->MadtInterruptSetting[7].Enable = PcdGet8 (PcdInterruptOverrideSettingTable7Enable);\r
+ mConfigData->MadtInterruptSetting[7].SourceIrq = PcdGet8 (PcdInterruptOverrideSettingTable7SourceIrq);\r
+ mConfigData->MadtInterruptSetting[7].Polarity = PcdGet8 (PcdInterruptOverrideSettingTable7Polarity);\r
+ mConfigData->MadtInterruptSetting[7].TrigerMode = PcdGet8 (PcdInterruptOverrideSettingTable7TrigerMode);\r
+ mConfigData->MadtInterruptSetting[7].GlobalIrq = PcdGet32 (PcdInterruptOverrideSettingTable7GlobalIrq);\r
+\r
+ mConfigData->MadtInterruptSetting[8].Enable = PcdGet8 (PcdInterruptOverrideSettingTable8Enable);\r
+ mConfigData->MadtInterruptSetting[8].SourceIrq = PcdGet8 (PcdInterruptOverrideSettingTable8SourceIrq);\r
+ mConfigData->MadtInterruptSetting[8].Polarity = PcdGet8 (PcdInterruptOverrideSettingTable8Polarity);\r
+ mConfigData->MadtInterruptSetting[8].TrigerMode = PcdGet8 (PcdInterruptOverrideSettingTable8TrigerMode);\r
+ mConfigData->MadtInterruptSetting[8].GlobalIrq = PcdGet32 (PcdInterruptOverrideSettingTable8GlobalIrq);\r
+\r
+ mConfigData->MadtInterruptSetting[9].Enable = PcdGet8 (PcdInterruptOverrideSettingTable9Enable);\r
+ mConfigData->MadtInterruptSetting[9].SourceIrq = PcdGet8 (PcdInterruptOverrideSettingTable9SourceIrq);\r
+ mConfigData->MadtInterruptSetting[9].Polarity = PcdGet8 (PcdInterruptOverrideSettingTable9Polarity);\r
+ mConfigData->MadtInterruptSetting[9].TrigerMode = PcdGet8 (PcdInterruptOverrideSettingTable9TrigerMode);\r
+ mConfigData->MadtInterruptSetting[9].GlobalIrq = PcdGet32 (PcdInterruptOverrideSettingTable9GlobalIrq);\r
+\r
+ mConfigData->MadtInterruptSetting[10].Enable = PcdGet8 (PcdInterruptOverrideSettingTable10Enable);\r
+ mConfigData->MadtInterruptSetting[10].SourceIrq = PcdGet8 (PcdInterruptOverrideSettingTable10SourceIrq);\r
+ mConfigData->MadtInterruptSetting[10].Polarity = PcdGet8 (PcdInterruptOverrideSettingTable10Polarity);\r
+ mConfigData->MadtInterruptSetting[10].TrigerMode = PcdGet8 (PcdInterruptOverrideSettingTable10TrigerMode);\r
+ mConfigData->MadtInterruptSetting[10].GlobalIrq = PcdGet32 (PcdInterruptOverrideSettingTable10GlobalIrq);\r
+\r
+ mConfigData->MadtInterruptSetting[11].Enable = PcdGet8 (PcdInterruptOverrideSettingTable11Enable);\r
+ mConfigData->MadtInterruptSetting[11].SourceIrq = PcdGet8 (PcdInterruptOverrideSettingTable11SourceIrq);\r
+ mConfigData->MadtInterruptSetting[11].Polarity = PcdGet8 (PcdInterruptOverrideSettingTable11Polarity);\r
+ mConfigData->MadtInterruptSetting[11].TrigerMode = PcdGet8 (PcdInterruptOverrideSettingTable11TrigerMode);\r
+ mConfigData->MadtInterruptSetting[11].GlobalIrq = PcdGet32 (PcdInterruptOverrideSettingTable11GlobalIrq);\r
+\r
+ mConfigData->MadtInterruptSetting[12].Enable = PcdGet8 (PcdInterruptOverrideSettingTable12Enable);\r
+ mConfigData->MadtInterruptSetting[12].SourceIrq = PcdGet8 (PcdInterruptOverrideSettingTable12SourceIrq);\r
+ mConfigData->MadtInterruptSetting[12].Polarity = PcdGet8 (PcdInterruptOverrideSettingTable12Polarity);\r
+ mConfigData->MadtInterruptSetting[12].TrigerMode = PcdGet8 (PcdInterruptOverrideSettingTable12TrigerMode);\r
+ mConfigData->MadtInterruptSetting[12].GlobalIrq = PcdGet32 (PcdInterruptOverrideSettingTable12GlobalIrq);\r
+\r
+ mConfigData->MadtInterruptSetting[13].Enable = PcdGet8 (PcdInterruptOverrideSettingTable13Enable);\r
+ mConfigData->MadtInterruptSetting[13].SourceIrq = PcdGet8 (PcdInterruptOverrideSettingTable13SourceIrq);\r
+ mConfigData->MadtInterruptSetting[13].Polarity = PcdGet8 (PcdInterruptOverrideSettingTable13Polarity);\r
+ mConfigData->MadtInterruptSetting[13].TrigerMode = PcdGet8 (PcdInterruptOverrideSettingTable13TrigerMode);\r
+ mConfigData->MadtInterruptSetting[13].GlobalIrq = PcdGet32 (PcdInterruptOverrideSettingTable13GlobalIrq);\r
+\r
+ mConfigData->MadtInterruptSetting[14].Enable = PcdGet8 (PcdInterruptOverrideSettingTable14Enable);\r
+ mConfigData->MadtInterruptSetting[14].SourceIrq = PcdGet8 (PcdInterruptOverrideSettingTable14SourceIrq);\r
+ mConfigData->MadtInterruptSetting[14].Polarity = PcdGet8 (PcdInterruptOverrideSettingTable14Polarity);\r
+ mConfigData->MadtInterruptSetting[14].TrigerMode = PcdGet8 (PcdInterruptOverrideSettingTable14TrigerMode);\r
+ mConfigData->MadtInterruptSetting[14].GlobalIrq = PcdGet32 (PcdInterruptOverrideSettingTable14GlobalIrq);\r
+\r
+ mConfigData->MadtInterruptSetting[15].Enable = PcdGet8 (PcdInterruptOverrideSettingTable15Enable);\r
+ mConfigData->MadtInterruptSetting[15].SourceIrq = PcdGet8 (PcdInterruptOverrideSettingTable15SourceIrq);\r
+ mConfigData->MadtInterruptSetting[15].Polarity = PcdGet8 (PcdInterruptOverrideSettingTable15Polarity);\r
+ mConfigData->MadtInterruptSetting[15].TrigerMode = PcdGet8 (PcdInterruptOverrideSettingTable15TrigerMode);\r
+ mConfigData->MadtInterruptSetting[15].GlobalIrq = PcdGet32 (PcdInterruptOverrideSettingTable15GlobalIrq);\r
+\r
+ mConfigData->MadtIoApicSetting.IoApicAddress = (UINT32)PcdGet64(PcdIoApicBaseAddress);\r
+ mConfigData->MadtIoApicSetting.GlobalInterruptBase = PcdGet32 (PcdIoApicSettingGlobalInterruptBase);\r
+ mConfigData->MadtIoApicSetting.IoApicId = PcdGet8 (PcdIoApicSettingIoApicId);\r
+ mConfigData->MadtIoApicSetting.NmiEnable = PcdGet8 (PcdIoApicSettingNmiEnable);\r
+ mConfigData->MadtIoApicSetting.NmiSource = PcdGet8 (PcdIoApicSettingNmiSource);\r
+ mConfigData->MadtIoApicSetting.Polarity = PcdGet8 (PcdIoApicSettingPolarity);\r
+ mConfigData->MadtIoApicSetting.TrigerMode = PcdGet8 (PcdIoApicSettingTrigerMode);\r
+\r
+ mConfigData->MadtLocalApicSetting.NmiEnabelApicIdMask = PcdGet8 (PcdLocalApicSettingNmiEnabelApicIdMask);\r
+ mConfigData->MadtLocalApicSetting.AddressOverrideEnable = PcdGet8 (PcdLocalApicSettingAddressOverrideEnable);\r
+ mConfigData->MadtLocalApicSetting.Polarity = PcdGet8 (PcdLocalApicSettingPolarity);\r
+ mConfigData->MadtLocalApicSetting.TrigerMode = PcdGet8 (PcdLocalApicSettingTrigerMode);\r
+ mConfigData->MadtLocalApicSetting.LocalApicLint = PcdGet8 (PcdLocalApicSettingLocalApicLint);\r
+ mConfigData->MadtLocalApicSetting.LocalApicAddressOverride = PcdGet64 (PcdLocalApicAddressOverride);\r
+ mConfigData->MadtLocalApicSetting.LocalApicAddress = PcdGet32 (PcdCpuLocalApicBaseAddress);\r
+}\r
+UINT32\r
+GetAcutalMadtTableSize (\r
+ IN MADT_CONFIG_DATA * MadtConfigData,\r
+ IN INTN NumberOfCPUs\r
+ )\r
+{\r
+ UINT32 MadtSize;\r
+ UINT8 Index;\r
+ MadtSize = (UINT32)(sizeof (EFI_ACPI_2_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER) +\r
+ sizeof (EFI_ACPI_2_0_PROCESSOR_LOCAL_APIC_STRUCTURE) * NumberOfCPUs +\r
+ sizeof (EFI_ACPI_2_0_IO_APIC_STRUCTURE) +\r
+ sizeof (EFI_ACPI_2_0_LOCAL_APIC_ADDRESS_OVERRIDE_STRUCTURE) * (MadtConfigData->MadtLocalApicSetting.AddressOverrideEnable != 0?1:0)\r
+ );\r
+ for (Index = 0; Index < EFI_ACPI_INTERRUPT_SOURCE_OVERRIDE_COUNT_MAX; Index ++ ) {\r
+ if (MadtConfigData->MadtInterruptSetting[Index].Enable != 0) {\r
+ MadtSize += sizeof (EFI_ACPI_2_0_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE);\r
+ }\r
+ }\r
+ for (Index = 0; Index < NumberOfCPUs; Index ++ ) {\r
+ if (0 != (MadtConfigData->MadtLocalApicSetting.NmiEnabelApicIdMask & (1 << Index))) {\r
+ MadtSize += sizeof (EFI_ACPI_2_0_LOCAL_APIC_NMI_STRUCTURE);\r
+ }\r
+ }\r
+ if (0 != MadtConfigData->MadtIoApicSetting.NmiEnable) {\r
+ MadtSize += sizeof (EFI_ACPI_2_0_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE);\r
+ }\r
+ return MadtSize;\r
+}\r
+\r
+//\r
+// Init Multiple APIC Description Table\r
+//\r
+EFI_STATUS\r
+MadtTableInitialize (\r
+ OUT EFI_ACPI_COMMON_HEADER **MadtTable,\r
+ OUT UINTN *Size\r
+ )\r
+{\r
+ EFI_ACPI_2_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER *Madt;\r
+ EFI_ACPI_2_0_PROCESSOR_LOCAL_APIC_STRUCTURE *ProcLocalApic;\r
+ EFI_ACPI_2_0_IO_APIC_STRUCTURE *IoApic;\r
+ EFI_ACPI_2_0_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE *InterruptSourceOverride;\r
+ EFI_ACPI_2_0_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE *IoApicNmiSource;\r
+ EFI_ACPI_2_0_LOCAL_APIC_NMI_STRUCTURE *LocalApicNmiSource;\r
+ EFI_ACPI_2_0_LOCAL_APIC_ADDRESS_OVERRIDE_STRUCTURE *LocalApicAddressOverride;\r
+\r
+ EFI_MP_SERVICES_PROTOCOL *MpService;\r
+ UINTN NumberOfCPUs;\r
+ UINTN NumberOfEnabledCPUs;\r
+ MADT_CONFIG_DATA MadtConfigData;\r
+\r
+ UINT32 MadtSize;\r
+ UINTN Index;\r
+ EFI_STATUS Status;\r
+\r
+\r
+ ASSERT (NULL != MadtTable);\r
+ ASSERT (NULL != Size);\r
+ //\r
+ // Init Madt table data\r
+ //\r
+ InitMadtConfigData (&MadtConfigData);\r
+ //\r
+ // Find the MP Protocol. This is an MP platform, so MP protocol must be\r
+ // there.\r
+ //\r
+ Status = gBS->LocateProtocol (\r
+ &gEfiMpServiceProtocolGuid,\r
+ NULL,\r
+ (VOID **)&MpService\r
+ );\r
+ ASSERT_EFI_ERROR (Status);\r
+ //\r
+ // Determine the number of processors\r
+ //\r
+ MpService->GetNumberOfProcessors (\r
+ MpService,\r
+ &NumberOfCPUs,\r
+ &NumberOfEnabledCPUs\r
+ );\r
+ //ASSERT (NumberOfCPUs <= 2 && NumberOfCPUs > 0);\r
+ MadtSize = GetAcutalMadtTableSize (&MadtConfigData, NumberOfCPUs);\r
+ Madt = (EFI_ACPI_2_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER *)AllocateZeroPool (MadtSize);\r
+ ASSERT_EFI_ERROR (Madt);\r
+ //\r
+ // Initialize MADT Header information\r
+ //\r
+ Madt->Header.Signature = EFI_ACPI_2_0_MULTIPLE_SAPIC_DESCRIPTION_TABLE_SIGNATURE;\r
+ Madt->Header.Length = MadtSize;\r
+ Madt->Header.Revision = EFI_ACPI_2_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION;\r
+ Madt->Header.OemTableId = EFI_ACPI_OEM_TABLE_ID;\r
+ Madt->Header.OemRevision = EFI_ACPI_OEM_MADT_REVISION;\r
+ Madt->Header.CreatorId = EFI_ACPI_CREATOR_ID;\r
+ Madt->LocalApicAddress = MadtConfigData.MadtLocalApicSetting.LocalApicAddress;\r
+ Madt->Flags = EFI_ACPI_2_0_MULTIPLE_APIC_FLAGS;\r
+ CopyMem (Madt->Header.OemId, EFI_ACPI_OEM_ID, 6);\r
+\r
+ ProcLocalApic = (EFI_ACPI_2_0_PROCESSOR_LOCAL_APIC_STRUCTURE *) (Madt + 1);\r
+ //\r
+ // Initialization of Processor's local APICs\r
+ //\r
+ for (Index = 0;Index < NumberOfCPUs; Index++) {\r
+ ProcLocalApic[Index].Type = EFI_ACPI_2_0_PROCESSOR_LOCAL_APIC;\r
+ ProcLocalApic[Index].Length = sizeof (EFI_ACPI_2_0_PROCESSOR_LOCAL_APIC_STRUCTURE);\r
+ ProcLocalApic[Index].AcpiProcessorId = (UINT8)(Index + 1);\r
+ ProcLocalApic[Index].ApicId = 0xff;\r
+ ProcLocalApic[Index].Flags = 0;\r
+ }\r
+ //\r
+ // Initialization of IO APIC.\r
+ // Note: Here assumes that there must be one and only one IO APIC in platform.\r
+ //\r
+ IoApic = (EFI_ACPI_2_0_IO_APIC_STRUCTURE *) (&ProcLocalApic[Index]);\r
+ IoApic->Type = EFI_ACPI_2_0_IO_APIC;\r
+ IoApic->Length = sizeof (EFI_ACPI_2_0_IO_APIC_STRUCTURE);\r
+ IoApic->IoApicId = MadtConfigData.MadtIoApicSetting.IoApicId;\r
+ IoApic->IoApicAddress = MadtConfigData.MadtIoApicSetting.IoApicAddress;\r
+ IoApic->GlobalSystemInterruptBase = MadtConfigData.MadtIoApicSetting.GlobalInterruptBase;\r
+\r
+ InterruptSourceOverride = (EFI_ACPI_2_0_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE *) (IoApic + 1);\r
+ for (Index = 0;Index < EFI_ACPI_INTERRUPT_SOURCE_OVERRIDE_COUNT_MAX; Index++ ){\r
+ if (MadtConfigData.MadtInterruptSetting[Index].Enable) {\r
+ InterruptSourceOverride->Type = EFI_ACPI_2_0_INTERRUPT_SOURCE_OVERRIDE;\r
+ InterruptSourceOverride->Length = sizeof (EFI_ACPI_2_0_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE);\r
+ InterruptSourceOverride->Bus = 0;\r
+ InterruptSourceOverride->Source = MadtConfigData.MadtInterruptSetting[Index].SourceIrq;\r
+ InterruptSourceOverride->Flags = ((MadtConfigData.MadtInterruptSetting[Index].TrigerMode & 0x03) << 2) | (MadtConfigData.MadtInterruptSetting[Index].Polarity & 0x03);\r
+ InterruptSourceOverride->GlobalSystemInterrupt = MadtConfigData.MadtInterruptSetting[Index].GlobalIrq;\r
+ InterruptSourceOverride++;\r
+ }\r
+ }\r
+ //\r
+ // support NMI source configuration.\r
+ //\r
+ IoApicNmiSource = (EFI_ACPI_2_0_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE *) InterruptSourceOverride;\r
+ if ((BOOLEAN) MadtConfigData.MadtIoApicSetting.NmiEnable) {\r
+ IoApicNmiSource->Type = EFI_ACPI_2_0_NON_MASKABLE_INTERRUPT_SOURCE;\r
+ IoApicNmiSource->Length = sizeof (EFI_ACPI_2_0_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE);\r
+ IoApicNmiSource->Flags = ((MadtConfigData.MadtIoApicSetting.TrigerMode & 0x03) << 2) | (MadtConfigData.MadtIoApicSetting.Polarity & 0x03);\r
+ IoApicNmiSource->GlobalSystemInterrupt = MadtConfigData.MadtIoApicSetting.NmiSource;\r
+ IoApicNmiSource ++;\r
+ }\r
+ //\r
+ // Assume each processor has same NMI interrupt source.\r
+ //\r
+ LocalApicNmiSource = (EFI_ACPI_2_0_LOCAL_APIC_NMI_STRUCTURE *) IoApicNmiSource;\r
+ for (Index = 0;Index < NumberOfCPUs; Index++) {\r
+ if (0 != (MadtConfigData.MadtLocalApicSetting.NmiEnabelApicIdMask & (1 << Index))){\r
+ LocalApicNmiSource->Type = EFI_ACPI_2_0_LOCAL_APIC_NMI;\r
+ LocalApicNmiSource->Length = sizeof (EFI_ACPI_2_0_LOCAL_APIC_NMI_STRUCTURE);\r
+ LocalApicNmiSource->LocalApicLint = MadtConfigData.MadtLocalApicSetting.LocalApicLint;\r
+ LocalApicNmiSource->Flags = ((MadtConfigData.MadtLocalApicSetting.TrigerMode & 0x03) << 2) | (MadtConfigData.MadtLocalApicSetting.Polarity & 0x03);\r
+ LocalApicNmiSource->AcpiProcessorId = (UINT8)(Index + 1);\r
+ LocalApicNmiSource++;\r
+ }\r
+ }\r
+\r
+ LocalApicAddressOverride = (EFI_ACPI_2_0_LOCAL_APIC_ADDRESS_OVERRIDE_STRUCTURE *) LocalApicNmiSource;\r
+ if ((BOOLEAN) MadtConfigData.MadtLocalApicSetting.AddressOverrideEnable) {\r
+ LocalApicAddressOverride->Type = EFI_ACPI_2_0_LOCAL_APIC_ADDRESS_OVERRIDE;\r
+ LocalApicAddressOverride->Length = sizeof (EFI_ACPI_2_0_LOCAL_APIC_ADDRESS_OVERRIDE_STRUCTURE);\r
+ LocalApicAddressOverride->LocalApicAddress = MadtConfigData.MadtLocalApicSetting.LocalApicAddressOverride;\r
+ LocalApicAddressOverride++;\r
+ }\r
+ *Size = MadtSize;\r
+ *MadtTable = (EFI_ACPI_COMMON_HEADER *) Madt;\r
+\r
+ return EFI_SUCCESS;\r
+}\r
--- /dev/null
+## @file\r
+# Boot Script Executor Module\r
+#\r
+# This is a standalone Boot Script Executor. Standalone means it does not\r
+# depends on any PEI or DXE service.\r
+#\r
+# Copyright (c) 2013-2015 Intel Corporation.\r
+#\r
+# This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution. The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php\r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+##\r
+\r
+[Defines]\r
+ INF_VERSION = 0x00010005\r
+ BASE_NAME = BootScriptExecutorDxe\r
+ FILE_GUID = FA20568B-548B-4b2b-81EF-1BA08D4A3CEC\r
+ MODULE_TYPE = DXE_DRIVER\r
+ VERSION_STRING = 1.0\r
+\r
+ ENTRY_POINT = BootScriptExecutorEntryPoint\r
+\r
+#\r
+# The following information is for reference only and not required by the build tools.\r
+#\r
+# VALID_ARCHITECTURES = IA32 X64\r
+#\r
+\r
+[Sources]\r
+ ScriptExecute.h\r
+ ScriptExecute.c\r
+\r
+[Sources.Ia32]\r
+ IA32/SetIdtEntry.c\r
+ IA32/S3Asm.asm\r
+ IA32/S3Asm.S\r
+\r
+[Packages]\r
+ MdePkg/MdePkg.dec\r
+ MdeModulePkg/MdeModulePkg.dec\r
+ QuarkPlatformPkg/QuarkPlatformPkg.dec\r
+ QuarkSocPkg/QuarkSocPkg.dec\r
+\r
+[LibraryClasses]\r
+ TimerLib\r
+ PcdLib\r
+ BaseMemoryLib\r
+ SmbusLib\r
+ UefiDriverEntryPoint\r
+ BaseLib\r
+ PciLib\r
+ IoLib\r
+ S3BootScriptLib\r
+ PeCoffLib\r
+ DxeServicesLib\r
+ UefiBootServicesTableLib\r
+ UefiRuntimeServicesTableLib\r
+ CacheMaintenanceLib\r
+ UefiLib\r
+ DebugAgentLib\r
+ LockBoxLib\r
+ IntelQNCLib\r
+ QNCAccessLib\r
+\r
+[Guids]\r
+ gEfiBootScriptExecutorVariableGuid\r
+ gEfiBootScriptExecutorContextGuid\r
+ gPerformanceProtocolGuid\r
+ gEfiEventExitBootServicesGuid\r
+\r
+[FeaturePcd]\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdDxeIplSwitchToLongMode\r
+\r
+[Pcd]\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdUse1GPageTable\r
+\r
+[Depex]\r
+ gEfiLockBoxProtocolGuid\r
--- /dev/null
+## @file\r
+#\r
+# Copyright (c) 2013-2015 Intel Corporation.\r
+#\r
+# This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution. The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php\r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+#-----------------------------------------\r
+#VOID\r
+#AsmTransferControl (\r
+# IN UINT32 S3WakingVector,\r
+# IN UINT32 AcpiLowMemoryBase\r
+# );\r
+#-----------------------------------------\r
+\r
+ASM_GLOBAL ASM_PFX(AsmTransferControl)\r
+ASM_PFX(AsmTransferControl):\r
+ # S3WakingVector :DWORD\r
+ # AcpiLowMemoryBase :DWORD\r
+ pushl %ebp\r
+ movl %esp,%ebp\r
+ leal LABLE, %eax\r
+ pushl $0x28 # CS\r
+ pushl %eax\r
+ movl 8(%ebp),%ecx\r
+ shrdl $20,%ecx,%ebx\r
+ andl $0xf,%ecx\r
+ movw %cx,%bx\r
+ movl %ebx, jmp_addr\r
+ lret\r
+LABLE:\r
+ .byte 0xb8,0x30,0 # mov ax, 30h as selector\r
+ movw %ax,%ds\r
+ movw %ax,%es\r
+ movw %ax,%fs\r
+ movw %ax,%gs\r
+ movw %ax,%ss\r
+ movl %cr0, %eax # Get control register 0\r
+ .byte 0x66\r
+ .byte 0x83,0xe0,0xfe # and eax, 0fffffffeh ; Clear PE bit (bit #0)\r
+ .byte 0xf,0x22,0xc0 # mov cr0, eax ; Activate real mode\r
+ .byte 0xea # jmp far @jmp_addr\r
+jmp_addr:\r
+ .long 0\r
+\r
--- /dev/null
+;; @file\r
+; This is the assembly code for transferring to control to OS S3 waking vector\r
+; for IA32 platform\r
+;\r
+; Copyright (c) 2013-2015 Intel Corporation.\r
+;\r
+; This program and the accompanying materials\r
+; are licensed and made available under the terms and conditions of the BSD License\r
+; which accompanies this distribution. The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+ .586P\r
+ .model flat,C\r
+ .code\r
+\r
+;-----------------------------------------\r
+;VOID\r
+;AsmTransferControl (\r
+; IN UINT32 S3WakingVector,\r
+; IN UINT32 AcpiLowMemoryBase\r
+; );\r
+;-----------------------------------------\r
+\r
+AsmTransferControl PROC\r
+ ; S3WakingVector :DWORD\r
+ ; AcpiLowMemoryBase :DWORD\r
+ push ebp\r
+ mov ebp, esp\r
+ lea eax, @F\r
+ push 28h ; CS\r
+ push eax\r
+ mov ecx, [ebp + 8]\r
+ shrd ebx, ecx, 20\r
+ and ecx, 0fh\r
+ mov bx, cx\r
+ mov @jmp_addr, ebx\r
+ retf\r
+@@:\r
+ DB 0b8h, 30h, 0 ; mov ax, 30h as selector\r
+ mov ds, ax\r
+ mov es, ax\r
+ mov fs, ax\r
+ mov gs, ax\r
+ mov ss, ax\r
+ mov eax, cr0 ; Get control register 0\r
+ DB 66h\r
+ DB 83h, 0e0h, 0feh ; and eax, 0fffffffeh ; Clear PE bit (bit #0)\r
+ DB 0fh, 22h, 0c0h ; mov cr0, eax ; Activate real mode\r
+ DB 0eah ; jmp far @jmp_addr\r
+@jmp_addr DD ?\r
+\r
+AsmTransferControl ENDP\r
+\r
+ END\r
--- /dev/null
+/** @file\r
+Set a IDT entry for debug purpose\r
+\r
+Set a IDT entry for interrupt vector 3 for debug purpose for IA32 platform\r
+\r
+Copyright (c) 2013-2015 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+#include "ScriptExecute.h"\r
+//\r
+// INTERRUPT_GATE_DESCRIPTOR and SetIdtEntry () are used to setup IDT to do debug\r
+//\r
+\r
+#pragma pack(1)\r
+\r
+typedef struct {\r
+ UINT16 OffsetLow;\r
+ UINT16 SegmentSelector;\r
+ UINT16 Attributes;\r
+ UINT16 OffsetHigh;\r
+} INTERRUPT_GATE_DESCRIPTOR;\r
+\r
+#define INTERRUPT_GATE_ATTRIBUTE 0x8e00\r
+\r
+#pragma pack()\r
+/**\r
+ Set a IDT entry for interrupt vector 3 for debug purpose.\r
+\r
+ @param AcpiS3Context a pointer to a structure of ACPI_S3_CONTEXT\r
+\r
+**/\r
+VOID\r
+SetIdtEntry (\r
+ IN ACPI_S3_CONTEXT *AcpiS3Context\r
+ )\r
+{\r
+ INTERRUPT_GATE_DESCRIPTOR *IdtEntry;\r
+ IA32_DESCRIPTOR *IdtDescriptor;\r
+ UINTN S3DebugBuffer;\r
+\r
+ //\r
+ // Restore IDT for debug\r
+ //\r
+ IdtDescriptor = (IA32_DESCRIPTOR *) (UINTN) (AcpiS3Context->IdtrProfile);\r
+ IdtEntry = (INTERRUPT_GATE_DESCRIPTOR *)(IdtDescriptor->Base + (3 * sizeof (INTERRUPT_GATE_DESCRIPTOR)));\r
+ S3DebugBuffer = (UINTN) (AcpiS3Context->S3DebugBufferAddress);\r
+\r
+ IdtEntry->OffsetLow = (UINT16)S3DebugBuffer;\r
+ IdtEntry->SegmentSelector = (UINT16)AsmReadCs ();\r
+ IdtEntry->Attributes = (UINT16)INTERRUPT_GATE_ATTRIBUTE;\r
+ IdtEntry->OffsetHigh = (UINT16)(S3DebugBuffer >> 16);\r
+\r
+ AsmWriteIdtr (IdtDescriptor);\r
+}\r
+\r
--- /dev/null
+/** @file\r
+This is the code for Boot Script Executer module.\r
+\r
+This driver is dispatched by Dxe core and the driver will reload itself to ACPI NVS memory\r
+in the entry point. The functionality is to interpret and restore the S3 boot script\r
+\r
+Copyright (c) 2013-2015 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#include "ScriptExecute.h"\r
+\r
+#pragma pack(1)\r
+typedef union {\r
+ struct {\r
+ UINT32 LimitLow : 16;\r
+ UINT32 BaseLow : 16;\r
+ UINT32 BaseMid : 8;\r
+ UINT32 Type : 4;\r
+ UINT32 System : 1;\r
+ UINT32 Dpl : 2;\r
+ UINT32 Present : 1;\r
+ UINT32 LimitHigh : 4;\r
+ UINT32 Software : 1;\r
+ UINT32 Reserved : 1;\r
+ UINT32 DefaultSize : 1;\r
+ UINT32 Granularity : 1;\r
+ UINT32 BaseHigh : 8;\r
+ } Bits;\r
+ UINT64 Uint64;\r
+} IA32_GDT;\r
+\r
+#pragma pack()\r
+\r
+EFI_GUID mBootScriptExecutorImageGuid = {\r
+ 0x9a8d3433, 0x9fe8, 0x42b6, {0x87, 0xb, 0x1e, 0x31, 0xc8, 0x4e, 0xbe, 0x3b}\r
+};\r
+\r
+//\r
+// Global Descriptor Table (GDT)\r
+//\r
+GLOBAL_REMOVE_IF_UNREFERENCED IA32_GDT mGdtEntries[] = {\r
+/* selector { Global Segment Descriptor } */\r
+/* 0x00 */ {{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}},\r
+/* 0x08 */ {{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}},\r
+/* 0x10 */ {{0xFFFF, 0, 0, 0xB, 1, 0, 1, 0xF, 0, 0, 1, 1, 0}},\r
+/* 0x18 */ {{0xFFFF, 0, 0, 0x3, 1, 0, 1, 0xF, 0, 0, 1, 1, 0}},\r
+/* 0x20 */ {{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}},\r
+/* 0x28 */ {{0xFFFF, 0, 0, 0xB, 1, 0, 1, 0xF, 0, 0, 0, 1, 0}},\r
+/* 0x30 */ {{0xFFFF, 0, 0, 0x3, 1, 0, 1, 0xF, 0, 0, 0, 1, 0}},\r
+/* 0x38 */ {{0xFFFF, 0, 0, 0xB, 1, 0, 1, 0xF, 0, 1, 0, 1, 0}},\r
+/* 0x40 */ {{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}},\r
+};\r
+\r
+//\r
+// IA32 Gdt register\r
+//\r
+GLOBAL_REMOVE_IF_UNREFERENCED CONST IA32_DESCRIPTOR mGdt = {\r
+ sizeof (mGdtEntries) - 1,\r
+ (UINTN) mGdtEntries\r
+ };\r
+\r
+/**\r
+ Entry function of Boot script exector. This function will be executed in\r
+ S3 boot path.\r
+ This function should not return, because it is invoked by switch stack.\r
+\r
+ @param AcpiS3Context a pointer to a structure of ACPI_S3_CONTEXT\r
+ @param PeiS3ResumeState a pointer to a structure of PEI_S3_RESUME_STATE\r
+\r
+ @retval EFI_INVALID_PARAMETER - OS waking vector not found\r
+ @retval EFI_UNSUPPORTED - something wrong when we resume to OS\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+S3BootScriptExecutorEntryFunction (\r
+ IN ACPI_S3_CONTEXT *AcpiS3Context,\r
+ IN PEI_S3_RESUME_STATE *PeiS3ResumeState\r
+ )\r
+{\r
+ EFI_STATUS Status;\r
+\r
+ //\r
+ // Disable interrupt of Debug timer, since new IDT table cannot handle it.\r
+ //\r
+ SaveAndSetDebugTimerInterrupt (FALSE);\r
+\r
+ //\r
+ // Restore IDT for debug\r
+ //\r
+ SetIdtEntry (AcpiS3Context);\r
+\r
+ //\r
+ // Initialize Debug Agent to support source level debug in S3 path.\r
+ //\r
+ InitializeDebugAgent (DEBUG_AGENT_INIT_S3, NULL, NULL);\r
+\r
+ //\r
+ // Because not install BootScriptExecute PPI(used just in this module), So just pass NULL\r
+ // for that parameter.\r
+ //\r
+ Status = S3BootScriptExecute ();\r
+\r
+ AsmWbinvd ();\r
+\r
+ //\r
+ // We need turn back to S3Resume - install boot script done ppi and report status code on S3resume.\r
+ //\r
+ if (PeiS3ResumeState != 0) {\r
+ //\r
+ // Need report status back to S3ResumePeim.\r
+ // If boot script execution is failed, S3ResumePeim wil report the error status code.\r
+ //\r
+ PeiS3ResumeState->ReturnStatus = (UINT64)(UINTN)Status;\r
+ //\r
+ // IA32 S3 Resume\r
+ //\r
+ DEBUG ((EFI_D_INFO, "Call SwitchStack() to return to S3 Resume in PEI Phase\n"));\r
+ PeiS3ResumeState->AsmTransferControl = (EFI_PHYSICAL_ADDRESS)(UINTN)PlatformTransferControl16;\r
+\r
+ SwitchStack (\r
+ (SWITCH_STACK_ENTRY_POINT)(UINTN)PeiS3ResumeState->ReturnEntryPoint,\r
+ (VOID *)(UINTN)AcpiS3Context,\r
+ (VOID *)(UINTN)PeiS3ResumeState,\r
+ (VOID *)(UINTN)PeiS3ResumeState->ReturnStackPointer\r
+ );\r
+\r
+ //\r
+ // Never run to here\r
+ //\r
+ CpuDeadLoop();\r
+ return EFI_UNSUPPORTED;\r
+ }\r
+\r
+ //\r
+ // Never run to here\r
+ //\r
+ CpuDeadLoop();\r
+ return EFI_UNSUPPORTED;\r
+}\r
+/**\r
+ Entrypoint of Boot script exector driver, this function will be executed in\r
+ normal boot phase and invoked by DXE dispatch.\r
+\r
+ @param[in] ImageHandle The firmware allocated handle for the EFI image.\r
+ @param[in] SystemTable A pointer to the EFI System Table.\r
+\r
+ @retval EFI_SUCCESS The entry point is executed successfully.\r
+ @retval other Some error occurs when executing this entry point.\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+BootScriptExecutorEntryPoint (\r
+ IN EFI_HANDLE ImageHandle,\r
+ IN EFI_SYSTEM_TABLE *SystemTable\r
+ )\r
+{\r
+ UINT8 *Buffer;\r
+ UINTN BufferSize;\r
+ UINTN Pages;\r
+ EFI_PHYSICAL_ADDRESS FfsBuffer;\r
+ PE_COFF_LOADER_IMAGE_CONTEXT ImageContext;\r
+ BOOT_SCRIPT_EXECUTOR_VARIABLE *EfiBootScriptExecutorVariable;\r
+ EFI_PHYSICAL_ADDRESS BootScriptExecutorBuffer;\r
+ EFI_STATUS Status;\r
+ VOID *DevicePath;\r
+ EFI_HANDLE NewImageHandle;\r
+\r
+ //\r
+ // Test if the gEfiCallerIdGuid of this image is already installed. if not, the entry\r
+ // point is loaded by DXE code which is the first time loaded. or else, it is already\r
+ // be reloaded be itself.This is a work-around\r
+ //\r
+ Status = gBS->LocateProtocol (&gEfiCallerIdGuid, NULL, &DevicePath);\r
+ if (EFI_ERROR (Status)) {\r
+\r
+ //\r
+ // This is the first-time loaded by DXE core. reload itself to NVS mem\r
+ //\r
+ //\r
+ // A workarouond: Here we install a dummy handle\r
+ //\r
+ NewImageHandle = NULL;\r
+ Status = gBS->InstallProtocolInterface (\r
+ &NewImageHandle,\r
+ &gEfiCallerIdGuid,\r
+ EFI_NATIVE_INTERFACE,\r
+ NULL\r
+ );\r
+\r
+ Status = GetSectionFromAnyFv (\r
+ &gEfiCallerIdGuid,\r
+ EFI_SECTION_PE32,\r
+ 0,\r
+ (VOID **) &Buffer,\r
+ &BufferSize\r
+ );\r
+ ImageContext.Handle = Buffer;\r
+ ImageContext.ImageRead = PeCoffLoaderImageReadFromMemory;\r
+ //\r
+ // Get information about the image being loaded\r
+ //\r
+ Status = PeCoffLoaderGetImageInfo (&ImageContext);\r
+ if (EFI_ERROR (Status)) {\r
+ return Status;\r
+ }\r
+ Pages = EFI_SIZE_TO_PAGES(BufferSize + ImageContext.SectionAlignment);\r
+ FfsBuffer = 0xFFFFFFFF;\r
+ Status = gBS->AllocatePages (\r
+ AllocateMaxAddress,\r
+ EfiACPIMemoryNVS,\r
+ Pages,\r
+ &FfsBuffer\r
+ );\r
+ if (EFI_ERROR (Status)) {\r
+ return EFI_OUT_OF_RESOURCES;\r
+ }\r
+ ImageContext.ImageAddress = (PHYSICAL_ADDRESS)(UINTN)FfsBuffer;\r
+ //\r
+ // Align buffer on section boundry\r
+ //\r
+ ImageContext.ImageAddress += ImageContext.SectionAlignment - 1;\r
+ ImageContext.ImageAddress &= ~(ImageContext.SectionAlignment - 1);\r
+ //\r
+ // Load the image to our new buffer\r
+ //\r
+ Status = PeCoffLoaderLoadImage (&ImageContext);\r
+ if (EFI_ERROR (Status)) {\r
+ gBS->FreePages (FfsBuffer, Pages);\r
+ return Status;\r
+ }\r
+\r
+ //\r
+ // Relocate the image in our new buffer\r
+ //\r
+ Status = PeCoffLoaderRelocateImage (&ImageContext);\r
+\r
+ if (EFI_ERROR (Status)) {\r
+ PeCoffLoaderUnloadImage (&ImageContext);\r
+ gBS->FreePages (FfsBuffer, Pages);\r
+ return Status;\r
+ }\r
+ //\r
+ // Flush the instruction cache so the image data is written before we execute it\r
+ //\r
+ InvalidateInstructionCacheRange ((VOID *)(UINTN)ImageContext.ImageAddress, (UINTN)ImageContext.ImageSize);\r
+ Status = ((EFI_IMAGE_ENTRY_POINT)(UINTN)(ImageContext.EntryPoint)) (NewImageHandle, SystemTable);\r
+ if (EFI_ERROR (Status)) {\r
+ gBS->FreePages (FfsBuffer, Pages);\r
+ return Status;\r
+ }\r
+ //\r
+ // Additional step for BootScript integrity\r
+ // Save BootScriptExecutor image\r
+ //\r
+ Status = SaveLockBox (\r
+ &mBootScriptExecutorImageGuid,\r
+ (VOID *)(UINTN)ImageContext.ImageAddress,\r
+ (UINTN)ImageContext.ImageSize\r
+ );\r
+ ASSERT_EFI_ERROR (Status);\r
+\r
+ Status = SetLockBoxAttributes (&mBootScriptExecutorImageGuid, LOCK_BOX_ATTRIBUTE_RESTORE_IN_PLACE);\r
+ ASSERT_EFI_ERROR (Status);\r
+\r
+ } else {\r
+ //\r
+ // the entry point is invoked after reloading. following code only run in ACPI NVS\r
+ //\r
+ BufferSize = sizeof (BOOT_SCRIPT_EXECUTOR_VARIABLE);\r
+\r
+ BootScriptExecutorBuffer = 0xFFFFFFFF;\r
+ Pages = EFI_SIZE_TO_PAGES(BufferSize);\r
+ Status = gBS->AllocatePages (\r
+ AllocateMaxAddress,\r
+ EfiACPIMemoryNVS,\r
+ Pages,\r
+ &BootScriptExecutorBuffer\r
+ );\r
+ if (EFI_ERROR (Status)) {\r
+ return EFI_OUT_OF_RESOURCES;\r
+ }\r
+\r
+ EfiBootScriptExecutorVariable = (BOOT_SCRIPT_EXECUTOR_VARIABLE *)(UINTN)BootScriptExecutorBuffer;\r
+ EfiBootScriptExecutorVariable->BootScriptExecutorEntrypoint = (UINTN) S3BootScriptExecutorEntryFunction ;\r
+\r
+ Status = SaveLockBox (\r
+ &gEfiBootScriptExecutorVariableGuid,\r
+ &BootScriptExecutorBuffer,\r
+ sizeof(BootScriptExecutorBuffer)\r
+ );\r
+ ASSERT_EFI_ERROR (Status);\r
+\r
+ //\r
+ // Additional step for BootScript integrity\r
+ // Save BootScriptExecutor context\r
+ //\r
+ Status = SaveLockBox (\r
+ &gEfiBootScriptExecutorContextGuid,\r
+ EfiBootScriptExecutorVariable,\r
+ sizeof(*EfiBootScriptExecutorVariable)\r
+ );\r
+ ASSERT_EFI_ERROR (Status);\r
+\r
+ Status = SetLockBoxAttributes (&gEfiBootScriptExecutorContextGuid, LOCK_BOX_ATTRIBUTE_RESTORE_IN_PLACE);\r
+ ASSERT_EFI_ERROR (Status);\r
+\r
+ }\r
+\r
+ return EFI_SUCCESS;\r
+}\r
+\r
+/**\r
+ Platform specific mechanism to transfer control to 16bit OS waking vector\r
+\r
+ @param[in] AcpiWakingVector The 16bit OS waking vector\r
+ @param[in] AcpiLowMemoryBase A buffer under 1M which could be used during the transfer\r
+\r
+**/\r
+VOID\r
+PlatformTransferControl16 (\r
+ IN UINT32 AcpiWakingVector,\r
+ IN UINT32 AcpiLowMemoryBase\r
+ )\r
+{\r
+ UINT32 NewValue;\r
+ UINT64 BaseAddress;\r
+ UINT64 SmramLength;\r
+ UINTN Index;\r
+\r
+ DEBUG (( EFI_D_INFO, "PlatformTransferControl - Entry\r\n"));\r
+\r
+ //\r
+ // Need to make sure the GDT is loaded with values that support long mode and real mode.\r
+ //\r
+ AsmWriteGdtr (&mGdt);\r
+\r
+ //\r
+ // Disable eSram block (this will also clear/zero eSRAM)\r
+ // We only use eSRAM in the PEI phase. Disable now that we are resuming the OS\r
+ //\r
+ NewValue = QNCPortRead (QUARK_NC_MEMORY_MANAGER_SB_PORT_ID, QUARK_NC_MEMORY_MANAGER_ESRAMPGCTRL_BLOCK);\r
+ NewValue |= BLOCK_DISABLE_PG;\r
+ QNCPortWrite (QUARK_NC_MEMORY_MANAGER_SB_PORT_ID, QUARK_NC_MEMORY_MANAGER_ESRAMPGCTRL_BLOCK, NewValue);\r
+\r
+ //\r
+ // Update HMBOUND to top of DDR3 memory and LOCK\r
+ // We disabled eSRAM so now we move HMBOUND down to top of DDR3\r
+ //\r
+ QNCGetTSEGMemoryRange (&BaseAddress, &SmramLength);\r
+ NewValue = (UINT32)(BaseAddress + SmramLength);\r
+ DEBUG ((EFI_D_INFO,"Locking HMBOUND at: = 0x%8x\n",NewValue));\r
+ QNCPortWrite (QUARK_NC_HOST_BRIDGE_SB_PORT_ID, QUARK_NC_HOST_BRIDGE_HMBOUND_REG, (NewValue | HMBOUND_LOCK));\r
+\r
+ //\r
+ // Lock all IMR regions now that HMBOUND is locked\r
+ //\r
+ for (Index = (QUARK_NC_MEMORY_MANAGER_IMR0+QUARK_NC_MEMORY_MANAGER_IMRXL); Index <= (QUARK_NC_MEMORY_MANAGER_IMR7+QUARK_NC_MEMORY_MANAGER_IMRXL); Index += 4) {\r
+ NewValue = QNCPortRead (QUARK_NC_MEMORY_MANAGER_SB_PORT_ID, Index);\r
+ NewValue |= IMR_LOCK;\r
+ QNCPortWrite (QUARK_NC_MEMORY_MANAGER_SB_PORT_ID, Index, NewValue);\r
+ }\r
+\r
+ //\r
+ // Call ASM routine to switch to real mode and jump to 16bit OS waking vector\r
+ //\r
+ AsmTransferControl(AcpiWakingVector, 0);\r
+\r
+ //\r
+ // Never run to here\r
+ //\r
+ CpuDeadLoop();\r
+}\r
+\r
+\r
+\r
+\r
--- /dev/null
+/** @file\r
+The header file for Boot Script Executer module.\r
+\r
+This driver is dispatched by Dxe core and the driver will reload itself to ACPI NVS memory\r
+in the entry point. The functionality is to interpret and restore the S3 boot script\r
+\r
+Copyright (c) 2013-2015 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+#ifndef _SCRIPT_EXECUTE_H_\r
+#define _SCRIPT_EXECUTE_H_\r
+\r
+#include <PiDxe.h>\r
+\r
+#include <Library/BaseLib.h>\r
+#include <Library/UefiDriverEntryPoint.h>\r
+#include <Library/BaseMemoryLib.h>\r
+#include <Library/DebugLib.h>\r
+#include <Library/S3BootScriptLib.h>\r
+#include <Library/PeCoffLib.h>\r
+#include <Library/DxeServicesLib.h>\r
+#include <Library/UefiBootServicesTableLib.h>\r
+#include <Library/UefiRuntimeServicesTableLib.h>\r
+#include <Library/PcdLib.h>\r
+#include <Library/CacheMaintenanceLib.h>\r
+#include <Library/TimerLib.h>\r
+#include <Library/UefiLib.h>\r
+#include <Library/DebugAgentLib.h>\r
+#include <Library/LockBoxLib.h>\r
+#include <Library/IntelQNCLib.h>\r
+#include <Library/QNCAccessLib.h>\r
+\r
+#include <Guid/AcpiS3Context.h>\r
+#include <Guid/BootScriptExecutorVariable.h>\r
+#include <Guid/EventGroup.h>\r
+#include <IndustryStandard/Acpi.h>\r
+\r
+/**\r
+ a ASM function to transfer control to OS.\r
+\r
+ @param S3WakingVector The S3 waking up vector saved in ACPI Facs table\r
+ @param AcpiLowMemoryBase a buffer under 1M which could be used during the transfer\r
+**/\r
+VOID\r
+AsmTransferControl (\r
+ IN UINT32 S3WakingVector,\r
+ IN UINT32 AcpiLowMemoryBase\r
+ );\r
+\r
+VOID\r
+SetIdtEntry (\r
+ IN ACPI_S3_CONTEXT *AcpiS3Context\r
+ );\r
+\r
+/**\r
+ Platform specific mechanism to transfer control to 16bit OS waking vector\r
+\r
+ @param[in] AcpiWakingVector The 16bit OS waking vector\r
+ @param[in] AcpiLowMemoryBase A buffer under 1M which could be used during the transfer\r
+\r
+**/\r
+VOID\r
+PlatformTransferControl16 (\r
+ IN UINT32 AcpiWakingVector,\r
+ IN UINT32 AcpiLowMemoryBase\r
+ );\r
+\r
+#endif //_SCRIPT_EXECUTE_H_\r
--- /dev/null
+/** @file\r
+ACPISMM Driver implementation file.\r
+\r
+This is QNC Smm platform driver\r
+\r
+Copyright (c) 2013-2015 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+**/\r
+\r
+#include <AcpiSmmPlatform.h>\r
+\r
+#define PCILIB_TO_COMMON_ADDRESS(Address) \\r
+ ((UINT64) ((((UINTN) ((Address>>20) & 0xff)) << 24) + (((UINTN) ((Address>>15) & 0x1f)) << 16) + (((UINTN) ((Address>>12) & 0x07)) << 8) + ((UINTN) (Address & 0xfff ))))\r
+\r
+//\r
+// Modular variables needed by this driver\r
+//\r
+EFI_ACPI_SMM_DEV mAcpiSmm;\r
+\r
+UINT8 mPciCfgRegTable[] = {\r
+ //\r
+ // Logic to decode the table masks to arrive at the registers saved\r
+ // Dword Registers are saved. For a given mask, the Base+offset register\r
+ // will be saved as in the table below.\r
+ // (example) To save register 0x24, 0x28 the mask at the Base 0x20 will be 0x06\r
+ // Base 0x00 0x20 0x40 0x60 0x80 0xA0 0xC0 0xE0\r
+ // Mask offset\r
+ // 0x01 0x00\r
+ // 0x02 0x04\r
+ // 0x04 0x08\r
+ // 0x08 0x0C\r
+ // 0x10 0x10\r
+ // 0x20 0x14\r
+ // 0x40 0x18\r
+ // 0x80 0x1C\r
+ //\r
+\r
+ //\r
+ // Bus, Dev, Func,\r
+ // 00-1F, 20-3F, 40-5F, 60-7F, 80-9F, A0-BF, C0-DF, E0-FF\r
+ // Only Bus 0 device is supported now\r
+ //\r
+\r
+ //\r
+ // Quark South Cluster devices\r
+ //\r
+ PCI_DEVICE (0, 20, 0),\r
+ PCI_REG_MASK (0x18, 0x98, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),\r
+\r
+ PCI_DEVICE (0, 20, 1),\r
+ PCI_REG_MASK (0x38, 0x98, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),\r
+\r
+ PCI_DEVICE (0, 20, 2),\r
+ PCI_REG_MASK (0x18, 0x98, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),\r
+\r
+ PCI_DEVICE (0, 20, 3),\r
+ PCI_REG_MASK (0x18, 0x98, 0x00, 0x01, 0x00, 0x00, 0x03, 0x00),\r
+\r
+ PCI_DEVICE (0, 20, 4),\r
+ PCI_REG_MASK (0x18, 0x98, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),\r
+\r
+ PCI_DEVICE (0, 20, 5),\r
+ PCI_REG_MASK (0x38, 0x98, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),\r
+\r
+ PCI_DEVICE (0, 20, 6),\r
+ PCI_REG_MASK (0x18, 0x98, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),\r
+\r
+ PCI_DEVICE (0, 20, 7),\r
+ PCI_REG_MASK (0x18, 0x98, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),\r
+\r
+ PCI_DEVICE (0, 21, 0),\r
+ PCI_REG_MASK (0x18, 0x98, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),\r
+\r
+ PCI_DEVICE (0, 21, 1),\r
+ PCI_REG_MASK (0x18, 0x98, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),\r
+\r
+ PCI_DEVICE (0, 21, 2),\r
+ PCI_REG_MASK (0x38, 0x98, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),\r
+\r
+ //\r
+ // Quark North Cluster devices\r
+ //\r
+ PCI_DEVICE (0, 0, 0),\r
+ PCI_REG_MASK (0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),\r
+\r
+ PCI_DEVICE (0, 23, 0),\r
+ PCI_REG_MASK (0xC0, 0x8F, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00),\r
+\r
+ PCI_DEVICE (0, 23, 1),\r
+ PCI_REG_MASK (0xC0, 0x8F, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00),\r
+\r
+ PCI_DEVICE (0, 31, 0),\r
+ PCI_REG_MASK (0x00, 0x08, 0x4E, 0x03, 0x02, 0x00, 0x60, 0x10),\r
+\r
+ PCI_DEVICE_END\r
+};\r
+\r
+EFI_PLATFORM_TYPE mPlatformType;\r
+\r
+ // These registers have to set in byte order\r
+const UINT8 QNCS3SaveExtReg[] = {\r
+ QUARK_NC_HOST_BRIDGE_SB_PORT_ID, QNC_MSG_FSBIC_REG_HSMMC, // SMRAM settings\r
+\r
+ QUARK_NC_MEMORY_MANAGER_SB_PORT_ID, QUARK_NC_MEMORY_MANAGER_IMR0+QUARK_NC_MEMORY_MANAGER_IMRXL,\r
+ QUARK_NC_MEMORY_MANAGER_SB_PORT_ID, QUARK_NC_MEMORY_MANAGER_IMR0+QUARK_NC_MEMORY_MANAGER_IMRXH,\r
+ QUARK_NC_MEMORY_MANAGER_SB_PORT_ID, QUARK_NC_MEMORY_MANAGER_IMR0+QUARK_NC_MEMORY_MANAGER_IMRXRM,\r
+ QUARK_NC_MEMORY_MANAGER_SB_PORT_ID, QUARK_NC_MEMORY_MANAGER_IMR0+QUARK_NC_MEMORY_MANAGER_IMRXWM,\r
+\r
+ QUARK_NC_MEMORY_MANAGER_SB_PORT_ID, QUARK_NC_MEMORY_MANAGER_IMR1+QUARK_NC_MEMORY_MANAGER_IMRXL,\r
+ QUARK_NC_MEMORY_MANAGER_SB_PORT_ID, QUARK_NC_MEMORY_MANAGER_IMR1+QUARK_NC_MEMORY_MANAGER_IMRXH,\r
+ QUARK_NC_MEMORY_MANAGER_SB_PORT_ID, QUARK_NC_MEMORY_MANAGER_IMR1+QUARK_NC_MEMORY_MANAGER_IMRXRM,\r
+ QUARK_NC_MEMORY_MANAGER_SB_PORT_ID, QUARK_NC_MEMORY_MANAGER_IMR1+QUARK_NC_MEMORY_MANAGER_IMRXWM,\r
+\r
+ QUARK_NC_MEMORY_MANAGER_SB_PORT_ID, QUARK_NC_MEMORY_MANAGER_IMR2+QUARK_NC_MEMORY_MANAGER_IMRXL,\r
+ QUARK_NC_MEMORY_MANAGER_SB_PORT_ID, QUARK_NC_MEMORY_MANAGER_IMR2+QUARK_NC_MEMORY_MANAGER_IMRXH,\r
+ QUARK_NC_MEMORY_MANAGER_SB_PORT_ID, QUARK_NC_MEMORY_MANAGER_IMR2+QUARK_NC_MEMORY_MANAGER_IMRXRM,\r
+ QUARK_NC_MEMORY_MANAGER_SB_PORT_ID, QUARK_NC_MEMORY_MANAGER_IMR2+QUARK_NC_MEMORY_MANAGER_IMRXWM,\r
+\r
+ QUARK_NC_MEMORY_MANAGER_SB_PORT_ID, QUARK_NC_MEMORY_MANAGER_IMR3+QUARK_NC_MEMORY_MANAGER_IMRXL,\r
+ QUARK_NC_MEMORY_MANAGER_SB_PORT_ID, QUARK_NC_MEMORY_MANAGER_IMR3+QUARK_NC_MEMORY_MANAGER_IMRXH,\r
+ QUARK_NC_MEMORY_MANAGER_SB_PORT_ID, QUARK_NC_MEMORY_MANAGER_IMR3+QUARK_NC_MEMORY_MANAGER_IMRXRM,\r
+ QUARK_NC_MEMORY_MANAGER_SB_PORT_ID, QUARK_NC_MEMORY_MANAGER_IMR3+QUARK_NC_MEMORY_MANAGER_IMRXWM,\r
+\r
+ QUARK_NC_MEMORY_MANAGER_SB_PORT_ID, QUARK_NC_MEMORY_MANAGER_IMR4+QUARK_NC_MEMORY_MANAGER_IMRXL,\r
+ QUARK_NC_MEMORY_MANAGER_SB_PORT_ID, QUARK_NC_MEMORY_MANAGER_IMR4+QUARK_NC_MEMORY_MANAGER_IMRXH,\r
+ QUARK_NC_MEMORY_MANAGER_SB_PORT_ID, QUARK_NC_MEMORY_MANAGER_IMR4+QUARK_NC_MEMORY_MANAGER_IMRXRM,\r
+ QUARK_NC_MEMORY_MANAGER_SB_PORT_ID, QUARK_NC_MEMORY_MANAGER_IMR4+QUARK_NC_MEMORY_MANAGER_IMRXWM,\r
+\r
+ QUARK_NC_MEMORY_MANAGER_SB_PORT_ID, QUARK_NC_MEMORY_MANAGER_IMR5+QUARK_NC_MEMORY_MANAGER_IMRXL,\r
+ QUARK_NC_MEMORY_MANAGER_SB_PORT_ID, QUARK_NC_MEMORY_MANAGER_IMR5+QUARK_NC_MEMORY_MANAGER_IMRXH,\r
+ QUARK_NC_MEMORY_MANAGER_SB_PORT_ID, QUARK_NC_MEMORY_MANAGER_IMR5+QUARK_NC_MEMORY_MANAGER_IMRXRM,\r
+ QUARK_NC_MEMORY_MANAGER_SB_PORT_ID, QUARK_NC_MEMORY_MANAGER_IMR5+QUARK_NC_MEMORY_MANAGER_IMRXWM,\r
+\r
+ QUARK_NC_MEMORY_MANAGER_SB_PORT_ID, QUARK_NC_MEMORY_MANAGER_IMR6+QUARK_NC_MEMORY_MANAGER_IMRXL,\r
+ QUARK_NC_MEMORY_MANAGER_SB_PORT_ID, QUARK_NC_MEMORY_MANAGER_IMR6+QUARK_NC_MEMORY_MANAGER_IMRXH,\r
+ QUARK_NC_MEMORY_MANAGER_SB_PORT_ID, QUARK_NC_MEMORY_MANAGER_IMR6+QUARK_NC_MEMORY_MANAGER_IMRXRM,\r
+ QUARK_NC_MEMORY_MANAGER_SB_PORT_ID, QUARK_NC_MEMORY_MANAGER_IMR6+QUARK_NC_MEMORY_MANAGER_IMRXWM,\r
+\r
+ QUARK_NC_MEMORY_MANAGER_SB_PORT_ID, QUARK_NC_MEMORY_MANAGER_IMR7+QUARK_NC_MEMORY_MANAGER_IMRXL,\r
+ QUARK_NC_MEMORY_MANAGER_SB_PORT_ID, QUARK_NC_MEMORY_MANAGER_IMR7+QUARK_NC_MEMORY_MANAGER_IMRXH,\r
+ QUARK_NC_MEMORY_MANAGER_SB_PORT_ID, QUARK_NC_MEMORY_MANAGER_IMR7+QUARK_NC_MEMORY_MANAGER_IMRXRM,\r
+ QUARK_NC_MEMORY_MANAGER_SB_PORT_ID, QUARK_NC_MEMORY_MANAGER_IMR7+QUARK_NC_MEMORY_MANAGER_IMRXWM,\r
+\r
+ QUARK_NC_RMU_SB_PORT_ID, QUARK_NC_ECC_SCRUB_END_MEM_REG, // ECC Scrub settings\r
+ QUARK_NC_RMU_SB_PORT_ID, QUARK_NC_ECC_SCRUB_START_MEM_REG,\r
+ QUARK_NC_RMU_SB_PORT_ID, QUARK_NC_ECC_SCRUB_NEXT_READ_REG,\r
+ QUARK_NC_RMU_SB_PORT_ID, QUARK_NC_ECC_SCRUB_CONFIG_REG,\r
+\r
+ 0xFF\r
+ };\r
+\r
+/**\r
+ Allocate EfiACPIMemoryNVS below 4G memory address.\r
+\r
+ This function allocates EfiACPIMemoryNVS below 4G memory address.\r
+\r
+ @param Size Size of memory to allocate.\r
+\r
+ @return Allocated address for output.\r
+\r
+**/\r
+VOID*\r
+AllocateAcpiNvsMemoryBelow4G (\r
+ IN UINTN Size\r
+ )\r
+{\r
+ UINTN Pages;\r
+ EFI_PHYSICAL_ADDRESS Address;\r
+ EFI_STATUS Status;\r
+ VOID* Buffer;\r
+\r
+ Pages = EFI_SIZE_TO_PAGES (Size);\r
+ Address = 0xffffffff;\r
+\r
+ Status = gBS->AllocatePages (\r
+ AllocateMaxAddress,\r
+ EfiACPIMemoryNVS,\r
+ Pages,\r
+ &Address\r
+ );\r
+ if (EFI_ERROR (Status)) {\r
+ return NULL;\r
+ }\r
+\r
+ Buffer = (VOID *) (UINTN) Address;\r
+ ZeroMem (Buffer, Size);\r
+\r
+ return Buffer;\r
+}\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+ReservedS3Memory (\r
+ UINTN SystemMemoryLength\r
+\r
+ )\r
+/*++\r
+\r
+Routine Description:\r
+\r
+ Reserved S3 memory for InstallS3Memory\r
+\r
+Arguments:\r
+\r
+\r
+Returns:\r
+\r
+ EFI_OUT_OF_RESOURCES - Insufficient resources to complete function.\r
+ EFI_SUCCESS - Function has completed successfully.\r
+\r
+--*/\r
+{\r
+\r
+ VOID *GuidHob;\r
+ EFI_SMRAM_HOB_DESCRIPTOR_BLOCK *DescriptorBlock;\r
+ VOID *AcpiReservedBase;\r
+\r
+ UINTN TsegIndex;\r
+ UINTN TsegSize;\r
+ UINTN TsegBase;\r
+ RESERVED_ACPI_S3_RANGE *AcpiS3Range;\r
+ //\r
+ // Get Hob list for SMRAM desc\r
+ //\r
+ GuidHob = GetFirstGuidHob (&gEfiSmmPeiSmramMemoryReserveGuid);\r
+ ASSERT (GuidHob);\r
+ DescriptorBlock = GET_GUID_HOB_DATA (GuidHob);\r
+ ASSERT (DescriptorBlock);\r
+\r
+ //\r
+ // Use the hob to get SMRAM capabilities\r
+ //\r
+ TsegIndex = DescriptorBlock->NumberOfSmmReservedRegions - 1;\r
+ ASSERT (TsegIndex <= (MAX_SMRAM_RANGES - 1));\r
+ TsegBase = (UINTN)DescriptorBlock->Descriptor[TsegIndex].PhysicalStart;\r
+ TsegSize = (UINTN)DescriptorBlock->Descriptor[TsegIndex].PhysicalSize;\r
+\r
+ DEBUG ((EFI_D_INFO, "SMM Base: %08X\n", TsegBase));\r
+ DEBUG ((EFI_D_INFO, "SMM Size: %08X\n", TsegSize));\r
+\r
+ //\r
+ // Now find the location of the data structure that is used to store the address\r
+ // of the S3 reserved memory.\r
+ //\r
+ AcpiS3Range = (RESERVED_ACPI_S3_RANGE*) (UINTN) (TsegBase + RESERVED_ACPI_S3_RANGE_OFFSET);\r
+\r
+ //\r
+ // Allocate reserved ACPI memory for S3 resume. Pointer to this region is\r
+ // stored in SMRAM in the first page of TSEG.\r
+ //\r
+ AcpiReservedBase = AllocateAcpiNvsMemoryBelow4G (PcdGet32 (PcdS3AcpiReservedMemorySize));\r
+ if (AcpiReservedBase != NULL) {\r
+ AcpiS3Range->AcpiReservedMemoryBase = (UINT32)(UINTN) AcpiReservedBase;\r
+ AcpiS3Range->AcpiReservedMemorySize = PcdGet32 (PcdS3AcpiReservedMemorySize);\r
+ }\r
+ AcpiS3Range->SystemMemoryLength = (UINT32)SystemMemoryLength;\r
+\r
+ DEBUG ((EFI_D_INFO, "S3 Memory Base: %08X\n", AcpiS3Range->AcpiReservedMemoryBase));\r
+ DEBUG ((EFI_D_INFO, "S3 Memory Size: %08X\n", AcpiS3Range->AcpiReservedMemorySize));\r
+ DEBUG ((EFI_D_INFO, "S3 SysMemoryLength: %08X\n", AcpiS3Range->SystemMemoryLength));\r
+\r
+ return EFI_SUCCESS;\r
+}\r
+\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+InitAcpiSmmPlatform (\r
+ IN EFI_HANDLE ImageHandle,\r
+ IN EFI_SYSTEM_TABLE *SystemTable\r
+ )\r
+/*++\r
+\r
+Routine Description:\r
+\r
+ Initializes the SMM S3 Handler Driver.\r
+\r
+Arguments:\r
+\r
+ ImageHandle - The image handle of Sleep State Wake driver.\r
+ SystemTable - The starndard EFI system table.\r
+\r
+Returns:\r
+\r
+ EFI_OUT_OF_RESOURCES - Insufficient resources to complete function.\r
+ EFI_SUCCESS - Function has completed successfully.\r
+ Other - Error occured during execution.\r
+\r
+--*/\r
+{\r
+ EFI_STATUS Status;\r
+ EFI_GLOBAL_NVS_AREA_PROTOCOL *AcpiNvsProtocol = NULL;\r
+ UINTN MemoryLength;\r
+ EFI_PEI_HOB_POINTERS Hob;\r
+\r
+ Status = gBS->LocateProtocol (\r
+ &gEfiGlobalNvsAreaProtocolGuid,\r
+ NULL,\r
+ (VOID **) &AcpiNvsProtocol\r
+ );\r
+ ASSERT_EFI_ERROR (Status);\r
+\r
+ mAcpiSmm.BootScriptSaved = 0;\r
+\r
+ mPlatformType = (EFI_PLATFORM_TYPE)PcdGet16 (PcdPlatformType);\r
+\r
+ //\r
+ // Calculate the system memory length by memory hobs\r
+ //\r
+ MemoryLength = 0x100000;\r
+ Hob.Raw = GetFirstHob (EFI_HOB_TYPE_RESOURCE_DESCRIPTOR);\r
+ ASSERT (Hob.Raw != NULL);\r
+ while ((Hob.Raw != NULL) && (!END_OF_HOB_LIST (Hob))) {\r
+ if (Hob.ResourceDescriptor->ResourceType == EFI_RESOURCE_SYSTEM_MEMORY) {\r
+ //\r
+ // Skip the memory region below 1MB\r
+ //\r
+ if (Hob.ResourceDescriptor->PhysicalStart >= 0x100000) {\r
+ MemoryLength += (UINTN)Hob.ResourceDescriptor->ResourceLength;\r
+ }\r
+ }\r
+ Hob.Raw = GET_NEXT_HOB (Hob);\r
+ Hob.Raw = GetNextHob (EFI_HOB_TYPE_RESOURCE_DESCRIPTOR, Hob.Raw);\r
+ }\r
+\r
+ ReservedS3Memory(MemoryLength);\r
+\r
+ //\r
+ // Locate and Register to Parent driver\r
+ //\r
+ Status = RegisterToDispatchDriver ();\r
+ ASSERT_EFI_ERROR (Status);\r
+\r
+ return EFI_SUCCESS;\r
+}\r
+\r
+EFI_STATUS\r
+RegisterToDispatchDriver (\r
+ VOID\r
+ )\r
+/*++\r
+\r
+Routine Description:\r
+\r
+ Register to dispatch driver.\r
+\r
+Arguments:\r
+\r
+ None.\r
+\r
+Returns:\r
+\r
+ EFI_SUCCESS - Successfully init the device.\r
+ Other - Error occured whening calling Dxe lib functions.\r
+\r
+--*/\r
+{\r
+ UINTN Length;\r
+ EFI_STATUS Status;\r
+ EFI_SMM_SX_DISPATCH2_PROTOCOL *SxDispatch;\r
+ EFI_SMM_SW_DISPATCH2_PROTOCOL *SwDispatch;\r
+ EFI_SMM_SX_REGISTER_CONTEXT *EntryDispatchContext;\r
+ EFI_SMM_SX_REGISTER_CONTEXT *EntryS1DispatchContext;\r
+ EFI_SMM_SX_REGISTER_CONTEXT *EntryS3DispatchContext;\r
+ EFI_SMM_SX_REGISTER_CONTEXT *EntryS4DispatchContext;\r
+ EFI_SMM_SX_REGISTER_CONTEXT *EntryS5DispatchContext;\r
+ EFI_SMM_SW_REGISTER_CONTEXT *SwContext;\r
+ EFI_SMM_SW_REGISTER_CONTEXT *AcpiDisableSwContext;\r
+ EFI_SMM_SW_REGISTER_CONTEXT *AcpiEnableSwContext;\r
+\r
+ Status = gSmst->SmmLocateProtocol (\r
+ &gEfiSmmSxDispatch2ProtocolGuid,\r
+ NULL,\r
+ (VOID **) &SxDispatch\r
+ );\r
+ if (EFI_ERROR (Status)) {\r
+ return Status;\r
+ }\r
+\r
+ Status = gSmst->SmmLocateProtocol (\r
+ &gEfiSmmSwDispatch2ProtocolGuid,\r
+ NULL,\r
+ (VOID **) &SwDispatch\r
+ );\r
+ if (EFI_ERROR (Status)) {\r
+ return Status;\r
+ }\r
+\r
+ Length = sizeof (EFI_SMM_SX_REGISTER_CONTEXT) * 4 + sizeof (EFI_SMM_SW_REGISTER_CONTEXT) * 2;\r
+ Status = gSmst->SmmAllocatePool (\r
+ EfiRuntimeServicesData,\r
+ Length,\r
+ (VOID **) &EntryDispatchContext\r
+ );\r
+ if (EFI_ERROR (Status)) {\r
+ return Status;\r
+ }\r
+\r
+ SetMem (EntryDispatchContext, Length, 0);\r
+\r
+ EntryS1DispatchContext = EntryDispatchContext++;\r
+ EntryS3DispatchContext = EntryDispatchContext++;\r
+ EntryS4DispatchContext = EntryDispatchContext++;\r
+ EntryS5DispatchContext = EntryDispatchContext++;\r
+\r
+ SwContext = (EFI_SMM_SW_REGISTER_CONTEXT *)EntryDispatchContext;\r
+ AcpiDisableSwContext = SwContext++;\r
+ AcpiEnableSwContext = SwContext++;\r
+\r
+ //\r
+ // Register the enable handler\r
+ //\r
+ AcpiEnableSwContext->SwSmiInputValue = EFI_ACPI_ACPI_ENABLE;\r
+ Status = SwDispatch->Register (\r
+ SwDispatch,\r
+ EnableAcpiCallback,\r
+ AcpiEnableSwContext,\r
+ &(mAcpiSmm.DisableAcpiHandle)\r
+ );\r
+\r
+ //\r
+ // Register the disable handler\r
+ //\r
+ AcpiDisableSwContext->SwSmiInputValue = EFI_ACPI_ACPI_DISABLE;\r
+ Status = SwDispatch->Register (\r
+ SwDispatch,\r
+ DisableAcpiCallback,\r
+ AcpiDisableSwContext,\r
+ &(mAcpiSmm.EnableAcpiHandle)\r
+ );\r
+\r
+\r
+ //\r
+ // Register entry phase call back function for S1\r
+ //\r
+ EntryS1DispatchContext->Type = SxS1;\r
+ EntryS1DispatchContext->Phase = SxEntry;\r
+ Status = SxDispatch->Register (\r
+ SxDispatch,\r
+ SxSleepEntryCallBack,\r
+ EntryS1DispatchContext,\r
+ &(mAcpiSmm.S1SleepEntryHandle)\r
+ );\r
+\r
+ //\r
+ // Register entry phase call back function\r
+ //\r
+ EntryS3DispatchContext->Type = SxS3;\r
+ EntryS3DispatchContext->Phase = SxEntry;\r
+ Status = SxDispatch->Register (\r
+ SxDispatch,\r
+ SxSleepEntryCallBack,\r
+ EntryS3DispatchContext,\r
+ &(mAcpiSmm.S3SleepEntryHandle)\r
+ );\r
+\r
+ //\r
+ // Register entry phase call back function for S4\r
+ //\r
+ EntryS4DispatchContext->Type = SxS4;\r
+ EntryS4DispatchContext->Phase = SxEntry;\r
+ Status = SxDispatch->Register (\r
+ SxDispatch,\r
+ SxSleepEntryCallBack,\r
+ EntryS4DispatchContext,\r
+ &(mAcpiSmm.S4SleepEntryHandle)\r
+ );\r
+\r
+ //\r
+ // Register callback for S5 in order to workaround the LAN shutdown issue\r
+ //\r
+ EntryS5DispatchContext->Type = SxS5;\r
+ EntryS5DispatchContext->Phase = SxEntry;\r
+ Status = SxDispatch->Register (\r
+ SxDispatch,\r
+ SxSleepEntryCallBack,\r
+ EntryS5DispatchContext,\r
+ &(mAcpiSmm.S5SoftOffEntryHandle)\r
+ );\r
+\r
+ return Status;\r
+}\r
+\r
+\r
+EFI_STATUS\r
+RestoreQncS3SwCallback (\r
+ IN EFI_HANDLE DispatchHandle,\r
+ IN CONST VOID *DispatchContext,\r
+ IN OUT VOID *CommBuffer,\r
+ IN OUT UINTN *CommBufferSize\r
+ )\r
+/*++\r
+\r
+Routine Description:\r
+ SMI handler to retore QncS3 code & context for S3 path\r
+ This will be only triggered when BootScript got executed during resume\r
+\r
+Arguments:\r
+ DispatchHandle - EFI Handle\r
+ DispatchContext - Pointer to the EFI_SMM_SW_DISPATCH_CONTEXT\r
+\r
+Returns:\r
+ Nothing\r
+\r
+--*/\r
+{\r
+ //\r
+ // Restore to original address by default\r
+ //\r
+ RestoreLockBox(&gQncS3CodeInLockBoxGuid, NULL, NULL);\r
+ RestoreLockBox(&gQncS3ContextInLockBoxGuid, NULL, NULL);\r
+ return EFI_SUCCESS;\r
+}\r
+\r
+EFI_STATUS\r
+DisableAcpiCallback (\r
+ IN EFI_HANDLE DispatchHandle,\r
+ IN CONST VOID *DispatchContext,\r
+ IN OUT VOID *CommBuffer,\r
+ IN OUT UINTN *CommBufferSize\r
+ )\r
+/*++\r
+\r
+Routine Description:\r
+ SMI handler to disable ACPI mode\r
+\r
+ Dispatched on reads from APM port with value 0xA1\r
+\r
+ ACPI events are disabled and ACPI event status is cleared.\r
+ SCI mode is then disabled.\r
+ Clear all ACPI event status and disable all ACPI events\r
+ Disable PM sources except power button\r
+ Clear status bits\r
+ Disable GPE0 sources\r
+ Clear status bits\r
+ Disable GPE1 sources\r
+ Clear status bits\r
+ Disable SCI\r
+\r
+Arguments:\r
+ DispatchHandle - EFI Handle\r
+ DispatchContext - Pointer to the EFI_SMM_SW_DISPATCH_CONTEXT\r
+\r
+Returns:\r
+ Nothing\r
+\r
+--*/\r
+{\r
+ EFI_STATUS Status;\r
+ UINT16 Pm1Cnt;\r
+\r
+ Status = GetAllQncPmBase (gSmst);\r
+ ASSERT_EFI_ERROR (Status);\r
+ Pm1Cnt = IoRead16 (mAcpiSmm.QncPmBase + R_QNC_PM1BLK_PM1C);\r
+\r
+ //\r
+ // Disable SCI\r
+ //\r
+ Pm1Cnt &= ~B_QNC_PM1BLK_PM1C_SCIEN;\r
+\r
+ IoWrite16 (mAcpiSmm.QncPmBase + R_QNC_PM1BLK_PM1C, Pm1Cnt);\r
+\r
+ return EFI_SUCCESS;\r
+}\r
+\r
+EFI_STATUS\r
+EnableAcpiCallback (\r
+ IN EFI_HANDLE DispatchHandle,\r
+ IN CONST VOID *DispatchContext,\r
+ IN OUT VOID *CommBuffer,\r
+ IN OUT UINTN *CommBufferSize\r
+ )\r
+/*++\r
+\r
+Routine Description:\r
+ SMI handler to enable ACPI mode\r
+\r
+ Dispatched on reads from APM port with value 0xA0\r
+\r
+ Disables the SW SMI Timer.\r
+ ACPI events are disabled and ACPI event status is cleared.\r
+ SCI mode is then enabled.\r
+\r
+ Disable SW SMI Timer\r
+\r
+ Clear all ACPI event status and disable all ACPI events\r
+ Disable PM sources except power button\r
+ Clear status bits\r
+\r
+ Disable GPE0 sources\r
+ Clear status bits\r
+\r
+ Disable GPE1 sources\r
+ Clear status bits\r
+\r
+ Guarantee day-of-month alarm is invalid (ACPI 1.0 section 4.7.2.4)\r
+\r
+ Enable SCI\r
+\r
+Arguments:\r
+ DispatchHandle - EFI Handle\r
+ DispatchContext - Pointer to the EFI_SMM_SW_DISPATCH_CONTEXT\r
+\r
+Returns:\r
+ Nothing\r
+\r
+--*/\r
+{\r
+ EFI_STATUS Status;\r
+ UINT32 SmiEn;\r
+ UINT16 Pm1Cnt;\r
+ UINT8 Data8;\r
+\r
+ Status = GetAllQncPmBase (gSmst);\r
+ ASSERT_EFI_ERROR (Status);\r
+\r
+ SmiEn = IoRead32 (mAcpiSmm.QncGpe0Base + R_QNC_GPE0BLK_SMIE);\r
+\r
+ //\r
+ // Disable SW SMI Timer\r
+ //\r
+ SmiEn &= ~(B_QNC_GPE0BLK_SMIE_SWT);\r
+ IoWrite32 (mAcpiSmm.QncGpe0Base + R_QNC_GPE0BLK_SMIE, SmiEn);\r
+\r
+ //\r
+ // Guarantee day-of-month alarm is invalid (ACPI 1.0 section 4.7.2.4)\r
+ //\r
+ Data8 = RTC_ADDRESS_REGISTER_D;\r
+ IoWrite8 (R_IOPORT_CMOS_STANDARD_INDEX, Data8);\r
+ Data8 = 0x0;\r
+ IoWrite8 (R_IOPORT_CMOS_STANDARD_DATA, Data8);\r
+\r
+ //\r
+ // Enable SCI\r
+ //\r
+ Pm1Cnt = IoRead16 (mAcpiSmm.QncPmBase + R_QNC_PM1BLK_PM1C);\r
+ Pm1Cnt |= B_QNC_PM1BLK_PM1C_SCIEN;\r
+ IoWrite16 (mAcpiSmm.QncPmBase + R_QNC_PM1BLK_PM1C, Pm1Cnt);\r
+\r
+ //\r
+ // Do platform specific stuff for ACPI enable SMI\r
+ //\r
+\r
+\r
+ return EFI_SUCCESS;\r
+}\r
+\r
+EFI_STATUS\r
+SxSleepEntryCallBack (\r
+ IN EFI_HANDLE DispatchHandle,\r
+ IN CONST VOID *DispatchContext,\r
+ IN OUT VOID *CommBuffer,\r
+ IN OUT UINTN *CommBufferSize\r
+ )\r
+/*++\r
+\r
+Routine Description:\r
+\r
+ Callback function entry for Sx sleep state.\r
+\r
+Arguments:\r
+\r
+ DispatchHandle - The handle of this callback, obtained when registering.\r
+ DispatchContext - The predefined context which contained sleep type and phase.\r
+\r
+Returns:\r
+\r
+ EFI_SUCCESS - Operation successfully performed.\r
+ EFI_INVALID_PARAMETER - Invalid parameter passed in.\r
+\r
+--*/\r
+{\r
+ EFI_STATUS Status;\r
+ UINT8 Data8;\r
+ UINT16 Data16;\r
+ UINT32 Data32;\r
+\r
+ REPORT_STATUS_CODE (EFI_PROGRESS_CODE, PcdGet32 (PcdProgressCodeS3SuspendStart));\r
+\r
+ //\r
+ // Reget QNC power mgmr regs base in case of OS changing it at runtime\r
+ //\r
+ Status = GetAllQncPmBase (gSmst);\r
+\r
+ //\r
+ // Clear RTC Alarm (if set)\r
+ //\r
+ Data8 = RTC_ADDRESS_REGISTER_C;\r
+ IoWrite8 (R_IOPORT_CMOS_STANDARD_INDEX, Data8);\r
+ Data8 = IoRead8 (R_IOPORT_CMOS_STANDARD_DATA);\r
+\r
+ //\r
+ // Clear all ACPI status bits\r
+ //\r
+ Data32 = B_QNC_GPE0BLK_GPE0S_ALL;\r
+ Status = gSmst->SmmIo.Io.Write( &gSmst->SmmIo, SMM_IO_UINT32, mAcpiSmm.QncGpe0Base + R_QNC_GPE0BLK_GPE0S, 1, &Data32 );\r
+ Data16 = B_QNC_PM1BLK_PM1S_ALL;\r
+ Status = gSmst->SmmIo.Io.Write( &gSmst->SmmIo, SMM_IO_UINT16, mAcpiSmm.QncPmBase + R_QNC_PM1BLK_PM1S, 1, &Data16 );\r
+\r
+ //\r
+ // Handling S1 - setting appropriate wake bits in GPE0_EN\r
+ //\r
+ if ((DispatchHandle == mAcpiSmm.S1SleepEntryHandle) && (((EFI_SMM_SX_REGISTER_CONTEXT *)DispatchContext)->Type == SxS1)) {\r
+ //\r
+ // Enable bit13 (EGPE), 14 (GPIO) ,17 (PCIE) in GPE0_EN\r
+ //\r
+ Status = gSmst->SmmIo.Io.Read( &gSmst->SmmIo, SMM_IO_UINT32, mAcpiSmm.QncGpe0Base + R_QNC_GPE0BLK_GPE0E, 1, &Data32 );\r
+ Data32 |= (B_QNC_GPE0BLK_GPE0E_EGPE | B_QNC_GPE0BLK_GPE0E_GPIO | B_QNC_GPE0BLK_GPE0E_PCIE);\r
+ Status = gSmst->SmmIo.Io.Write( &gSmst->SmmIo, SMM_IO_UINT32, mAcpiSmm.QncGpe0Base + R_QNC_GPE0BLK_GPE0E, 1, &Data32 );\r
+\r
+ //\r
+ // Enable bit10 (RTC) in PM1E\r
+ //\r
+ Status = gSmst->SmmIo.Io.Read( &gSmst->SmmIo, SMM_IO_UINT16, mAcpiSmm.QncPmBase + R_QNC_PM1BLK_PM1E, 1, &Data16 );\r
+ Data16 |= B_QNC_PM1BLK_PM1E_RTC;\r
+ Status = gSmst->SmmIo.Io.Write( &gSmst->SmmIo, SMM_IO_UINT16, mAcpiSmm.QncPmBase + R_QNC_PM1BLK_PM1E, 1, &Data16 );\r
+\r
+ return EFI_SUCCESS;\r
+ }\r
+\r
+ //\r
+ // Handling S4, S5 and WOL - setting appropriate wake bits in GPE0_EN\r
+ //\r
+ if (((DispatchHandle == mAcpiSmm.S4SleepEntryHandle) && (((EFI_SMM_SX_REGISTER_CONTEXT *)DispatchContext)->Type == SxS4)) ||\r
+ ((DispatchHandle == mAcpiSmm.S5SoftOffEntryHandle) && (((EFI_SMM_SX_REGISTER_CONTEXT *)DispatchContext)->Type == SxS5))\r
+ ) {\r
+ //\r
+ // Enable bit13 (EGPE), 14 (GPIO) ,17 (PCIE) in GPE0_EN\r
+ // Enable the WOL bits in GPE0_EN reg here for PME\r
+ //\r
+ Status = gSmst->SmmIo.Io.Read( &gSmst->SmmIo, SMM_IO_UINT32, mAcpiSmm.QncGpe0Base + R_QNC_GPE0BLK_GPE0E, 1, &Data32 );\r
+ Data32 |= (B_QNC_GPE0BLK_GPE0E_EGPE | B_QNC_GPE0BLK_GPE0E_GPIO | B_QNC_GPE0BLK_GPE0E_PCIE);\r
+ Status = gSmst->SmmIo.Io.Write( &gSmst->SmmIo, SMM_IO_UINT32, mAcpiSmm.QncGpe0Base + R_QNC_GPE0BLK_GPE0E, 1, &Data32 );\r
+\r
+ //\r
+ // Enable bit10 (RTC) in PM1E\r
+ //\r
+ Status = gSmst->SmmIo.Io.Read( &gSmst->SmmIo, SMM_IO_UINT16, mAcpiSmm.QncPmBase + R_QNC_PM1BLK_PM1E, 1, &Data16 );\r
+ Data16 |= B_QNC_PM1BLK_PM1E_RTC;\r
+ Status = gSmst->SmmIo.Io.Write( &gSmst->SmmIo, SMM_IO_UINT16, mAcpiSmm.QncPmBase + R_QNC_PM1BLK_PM1E, 1, &Data16 );\r
+\r
+ } else {\r
+\r
+ if ((DispatchHandle != mAcpiSmm.S3SleepEntryHandle) || (((EFI_SMM_SX_REGISTER_CONTEXT *)DispatchContext)->Type != SxS3)) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+\r
+ Status = SaveRuntimeScriptTable (gSmst);\r
+ if (EFI_ERROR (Status)) {\r
+ return Status;\r
+ }\r
+\r
+ //\r
+ // Enable bit13 (EGPE), 14 (GPIO), 17 (PCIE) in GPE0_EN\r
+ // Enable the WOL bits in GPE0_EN reg here for PME\r
+ //\r
+ Status = gSmst->SmmIo.Io.Read( &gSmst->SmmIo, SMM_IO_UINT32, mAcpiSmm.QncGpe0Base + R_QNC_GPE0BLK_GPE0E, 1, &Data32 );\r
+ Data32 |= (B_QNC_GPE0BLK_GPE0E_EGPE | B_QNC_GPE0BLK_GPE0E_GPIO | B_QNC_GPE0BLK_GPE0E_PCIE);\r
+ Status = gSmst->SmmIo.Io.Write( &gSmst->SmmIo, SMM_IO_UINT32, mAcpiSmm.QncGpe0Base + R_QNC_GPE0BLK_GPE0E, 1, &Data32 );\r
+\r
+ //\r
+ // Enable bit10 (RTC) in PM1E\r
+ //\r
+ Status = gSmst->SmmIo.Io.Read( &gSmst->SmmIo, SMM_IO_UINT16, mAcpiSmm.QncPmBase + R_QNC_PM1BLK_PM1E, 1, &Data16 );\r
+ Data16 |= B_QNC_PM1BLK_PM1E_RTC;\r
+ Status = gSmst->SmmIo.Io.Write( &gSmst->SmmIo, SMM_IO_UINT16, mAcpiSmm.QncPmBase + R_QNC_PM1BLK_PM1E, 1, &Data16 );\r
+ }\r
+\r
+ //\r
+ // When entering a power-managed state like S3,\r
+ // PERST# must be asserted in advance of power-off.\r
+ //\r
+ PlatformPERSTAssert (mPlatformType);\r
+\r
+ return EFI_SUCCESS;\r
+}\r
+\r
+EFI_STATUS\r
+GetAllQncPmBase (\r
+ IN EFI_SMM_SYSTEM_TABLE2 *Smst\r
+ )\r
+/*++\r
+\r
+Routine Description:\r
+\r
+ Get QNC chipset LPC Power Management I/O Base at runtime.\r
+\r
+Arguments:\r
+\r
+ Smst - The standard SMM system table.\r
+\r
+Returns:\r
+\r
+ EFI_SUCCESS - Successfully init the device.\r
+ Other - Error occured whening calling Dxe lib functions.\r
+\r
+--*/\r
+{\r
+ mAcpiSmm.QncPmBase = PciRead16 (PCI_LIB_ADDRESS(PCI_BUS_NUMBER_QNC, PCI_DEVICE_NUMBER_QNC_LPC, 0, R_QNC_LPC_PM1BLK)) & B_QNC_LPC_PM1BLK_MASK;\r
+ mAcpiSmm.QncGpe0Base = PciRead16 (PCI_LIB_ADDRESS(PCI_BUS_NUMBER_QNC, PCI_DEVICE_NUMBER_QNC_LPC, 0, R_QNC_LPC_GPE0BLK)) & B_QNC_LPC_GPE0BLK_MASK;\r
+\r
+ //\r
+ // Quark does not support Changing Primary SoC IOBARs from what was\r
+ // setup in SEC/PEI UEFI stages.\r
+ //\r
+ ASSERT (mAcpiSmm.QncPmBase == (UINT32) PcdGet16 (PcdPm1blkIoBaseAddress));\r
+ ASSERT (mAcpiSmm.QncGpe0Base == (UINT32) PcdGet16 (PcdGpe0blkIoBaseAddress));\r
+ return EFI_SUCCESS;\r
+}\r
+\r
+EFI_STATUS\r
+SaveRuntimeScriptTable (\r
+ IN EFI_SMM_SYSTEM_TABLE2 *Smst\r
+ )\r
+{\r
+ EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS PciAddress;\r
+ UINT32 Data32;\r
+ UINT16 Data16;\r
+ UINT8 Mask;\r
+ UINTN Index;\r
+ UINTN Offset;\r
+ UINT16 DeviceId;\r
+\r
+ //\r
+ // Check what Soc we are running on (read Host bridge DeviceId)\r
+ //\r
+ DeviceId = QncGetSocDeviceId();\r
+\r
+ //\r
+ // Save PCI-Host bridge settings (0, 0, 0). 0x90, 94 and 9c are changed by CSM\r
+ // and vital to S3 resume. That's why we put save code here\r
+ //\r
+ Index = 0;\r
+ while (mPciCfgRegTable[Index] != PCI_DEVICE_END) {\r
+\r
+ PciAddress.Bus = mPciCfgRegTable[Index++];\r
+ PciAddress.Device = mPciCfgRegTable[Index++];\r
+ PciAddress.Function = mPciCfgRegTable[Index++];\r
+ PciAddress.Register = 0;\r
+ PciAddress.ExtendedRegister = 0;\r
+\r
+ Data16 = PciRead16 (PCI_LIB_ADDRESS(PciAddress.Bus, PciAddress.Device, PciAddress.Function, PciAddress.Register));\r
+ if (Data16 == 0xFFFF) {\r
+ Index += 8;\r
+ continue;\r
+ }\r
+\r
+ for (Offset = 0, Mask = 0x01; Offset < 256; Offset += 4, Mask <<= 1) {\r
+\r
+ if (Mask == 0x00) {\r
+ Mask = 0x01;\r
+ }\r
+\r
+ if (mPciCfgRegTable[Index + Offset / 32] & Mask) {\r
+\r
+ PciAddress.Register = (UINT8) Offset;\r
+ Data32 = PciRead32 (PCI_LIB_ADDRESS(PciAddress.Bus, PciAddress.Device, PciAddress.Function, PciAddress.Register));\r
+\r
+\r
+ //\r
+ // Save latest settings to runtime script table\r
+ //\r
+ S3BootScriptSavePciCfgWrite (\r
+ S3BootScriptWidthUint32,\r
+ PCILIB_TO_COMMON_ADDRESS (PCI_LIB_ADDRESS(PciAddress.Bus, PciAddress.Device, PciAddress.Function, PciAddress.Register)),\r
+ 1,\r
+ &Data32\r
+ );\r
+ }\r
+ }\r
+\r
+ Index += 8;\r
+\r
+ }\r
+\r
+ //\r
+ // Save message bus registers\r
+ //\r
+ Index = 0;\r
+ while (QNCS3SaveExtReg[Index] != 0xFF) {\r
+ Data32 = QNCPortRead (QNCS3SaveExtReg[Index], QNCS3SaveExtReg[Index + 1]);\r
+\r
+ //\r
+ // Save IMR settings with IMR protection disabled initially\r
+ // HMBOUND and IMRs will be locked just before jumping to the OS waking vector\r
+ //\r
+ if (QNCS3SaveExtReg[Index] == QUARK_NC_MEMORY_MANAGER_SB_PORT_ID) {\r
+ if ((QNCS3SaveExtReg[Index + 1] >= (QUARK_NC_MEMORY_MANAGER_IMR0+QUARK_NC_MEMORY_MANAGER_IMRXL)) && (QNCS3SaveExtReg[Index + 1] <= (QUARK_NC_MEMORY_MANAGER_IMR7+QUARK_NC_MEMORY_MANAGER_IMRXWM)) && ((QNCS3SaveExtReg[Index + 1] & 0x03) == QUARK_NC_MEMORY_MANAGER_IMRXL)) {\r
+ Data32 &= ~IMR_LOCK;\r
+ if (DeviceId == QUARK2_MC_DEVICE_ID) {\r
+ Data32 &= ~IMR_EN;\r
+ }\r
+ }\r
+ if ((QNCS3SaveExtReg[Index + 1] >= (QUARK_NC_MEMORY_MANAGER_IMR0+QUARK_NC_MEMORY_MANAGER_IMRXRM)) && (QNCS3SaveExtReg[Index + 1] <= (QUARK_NC_MEMORY_MANAGER_IMR7+QUARK_NC_MEMORY_MANAGER_IMRXWM)) && ((QNCS3SaveExtReg[Index + 1] & 0x03) >= QUARK_NC_MEMORY_MANAGER_IMRXRM)) {\r
+ Data32 = (UINT32)IMRX_ALL_ACCESS;\r
+ }\r
+ }\r
+\r
+ //\r
+ // Save latest settings to runtime script table\r
+ //\r
+ S3BootScriptSavePciCfgWrite (\r
+ S3BootScriptWidthUint32,\r
+ PCILIB_TO_COMMON_ADDRESS (PCI_LIB_ADDRESS(0, 0, 0, QNC_ACCESS_PORT_MDR)),\r
+ 1,\r
+ &Data32\r
+ );\r
+\r
+ Data32 = MESSAGE_WRITE_DW (QNCS3SaveExtReg[Index], QNCS3SaveExtReg[Index + 1]);\r
+\r
+ S3BootScriptSavePciCfgWrite (\r
+ S3BootScriptWidthUint32,\r
+ PCILIB_TO_COMMON_ADDRESS (PCI_LIB_ADDRESS(0, 0, 0, QNC_ACCESS_PORT_MCR)),\r
+ 1,\r
+ &Data32\r
+ );\r
+ Index += 2;\r
+ }\r
+\r
+ Index = 0;\r
+ while (QNCS3SaveExtReg[Index] != 0xFF) {\r
+ //\r
+ // Save IMR settings with IMR protection enabled (above script was to handle restoring all settings first - now we want to enable)\r
+ //\r
+ if (QNCS3SaveExtReg[Index] == QUARK_NC_MEMORY_MANAGER_SB_PORT_ID) {\r
+ if (DeviceId == QUARK2_MC_DEVICE_ID) {\r
+ if ((QNCS3SaveExtReg[Index + 1] >= (QUARK_NC_MEMORY_MANAGER_IMR0+QUARK_NC_MEMORY_MANAGER_IMRXL)) && (QNCS3SaveExtReg[Index + 1] <= (QUARK_NC_MEMORY_MANAGER_IMR7+QUARK_NC_MEMORY_MANAGER_IMRXWM)) && ((QNCS3SaveExtReg[Index + 1] & 0x03) == QUARK_NC_MEMORY_MANAGER_IMRXL)) {\r
+ Data32 = QNCPortRead (QNCS3SaveExtReg[Index], QNCS3SaveExtReg[Index + 1]);\r
+ Data32 &= ~IMR_LOCK;\r
+\r
+ //\r
+ // Save latest settings to runtime script table\r
+ //\r
+ S3BootScriptSavePciCfgWrite (\r
+ S3BootScriptWidthUint32,\r
+ PCILIB_TO_COMMON_ADDRESS (PCI_LIB_ADDRESS(0, 0, 0, QNC_ACCESS_PORT_MDR)),\r
+ 1,\r
+ &Data32\r
+ );\r
+\r
+ Data32 = MESSAGE_WRITE_DW (QNCS3SaveExtReg[Index], QNCS3SaveExtReg[Index + 1]);\r
+\r
+ S3BootScriptSavePciCfgWrite (\r
+ S3BootScriptWidthUint32,\r
+ PCILIB_TO_COMMON_ADDRESS (PCI_LIB_ADDRESS(0, 0, 0, QNC_ACCESS_PORT_MCR)),\r
+ 1,\r
+ &Data32\r
+ );\r
+ }\r
+ } else {\r
+ if ((QNCS3SaveExtReg[Index + 1] >= (QUARK_NC_MEMORY_MANAGER_IMR0+QUARK_NC_MEMORY_MANAGER_IMRXRM)) && (QNCS3SaveExtReg[Index + 1] <= (QUARK_NC_MEMORY_MANAGER_IMR7+QUARK_NC_MEMORY_MANAGER_IMRXWM)) && ((QNCS3SaveExtReg[Index + 1] & 0x03) >= QUARK_NC_MEMORY_MANAGER_IMRXRM)) {\r
+ Data32 = QNCPortRead (QNCS3SaveExtReg[Index], QNCS3SaveExtReg[Index + 1]);\r
+\r
+ //\r
+ // Save latest settings to runtime script table\r
+ //\r
+ S3BootScriptSavePciCfgWrite (\r
+ S3BootScriptWidthUint32,\r
+ PCILIB_TO_COMMON_ADDRESS (PCI_LIB_ADDRESS(0, 0, 0, QNC_ACCESS_PORT_MDR)),\r
+ 1,\r
+ &Data32\r
+ );\r
+\r
+ Data32 = MESSAGE_WRITE_DW (QNCS3SaveExtReg[Index], QNCS3SaveExtReg[Index + 1]);\r
+\r
+ S3BootScriptSavePciCfgWrite (\r
+ S3BootScriptWidthUint32,\r
+ PCILIB_TO_COMMON_ADDRESS (PCI_LIB_ADDRESS(0, 0, 0, QNC_ACCESS_PORT_MCR)),\r
+ 1,\r
+ &Data32\r
+ );\r
+ }\r
+ }\r
+ }\r
+ Index += 2;\r
+ }\r
+\r
+ // Check if ECC scrub enabled and need re-enabling on resume\r
+ // All scrub related configuration registers are saved on suspend\r
+ // as part of QNCS3SaveExtReg configuration table script.\r
+ // The code below extends the S3 resume script with scrub reactivation\r
+ // message (if needed only)\r
+ Data32 = QNCPortRead (QUARK_NC_RMU_SB_PORT_ID, QUARK_NC_ECC_SCRUB_CONFIG_REG);\r
+ if( 0 != (Data32 & SCRUB_CFG_ACTIVE)) {\r
+\r
+ Data32 = SCRUB_RESUME_MSG();\r
+\r
+ S3BootScriptSavePciCfgWrite (\r
+ S3BootScriptWidthUint32,\r
+ PCILIB_TO_COMMON_ADDRESS (PCI_LIB_ADDRESS(0, 0, 0, QNC_ACCESS_PORT_MCR)),\r
+ 1,\r
+ &Data32\r
+ );\r
+ }\r
+\r
+ //\r
+ // Save I/O ports to S3 script table\r
+ //\r
+\r
+ //\r
+ // Important to trap Sx for SMM\r
+ //\r
+ Data32 = IoRead32 (mAcpiSmm.QncGpe0Base + R_QNC_GPE0BLK_SMIE);\r
+ S3BootScriptSaveIoWrite(S3BootScriptWidthUint32, (mAcpiSmm.QncGpe0Base + R_QNC_GPE0BLK_SMIE), 1, &Data32);\r
+\r
+ return EFI_SUCCESS;\r
+}\r
+\r
--- /dev/null
+/** @file\r
+Header file for SMM S3 Handler Driver.\r
+\r
+Copyright (c) 2013-2015 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+**/\r
+\r
+#ifndef _ACPI_SMM_DRIVER_H\r
+#define _ACPI_SMM_DRIVER_H\r
+//\r
+// Include files\r
+//\r
+//\r
+// Driver Consumed Protocol Prototypes\r
+//\r
+#include <Protocol/SmmSxDispatch2.h>\r
+#include <Protocol/SmmSwDispatch2.h>\r
+#include <Protocol/FirmwareVolume.h>\r
+#include <Protocol/GlobalNvsArea.h>\r
+#include <Protocol/PciRootBridgeIo.h>\r
+#include <Library/UefiDriverEntryPoint.h>\r
+#include <Protocol/Spi.h>\r
+#include <Library/IoLib.h>\r
+#include <Library/PciLib.h>\r
+#include <Library/PcdLib.h>\r
+#include <Library/LockBoxLib.h>\r
+#include <Library/DebugLib.h>\r
+#include <Library/BaseMemoryLib.h>\r
+#include <Library/UefiBootServicesTableLib.h>\r
+#include <Library/BaseLib.h>\r
+#include <Library/UefiRuntimeServicesTableLib.h>\r
+#include <Library/S3IoLib.h>\r
+#include <Library/S3BootScriptLib.h>\r
+#include <Guid/Acpi.h>\r
+#include <Guid/GlobalVariable.h>\r
+#include <Library/SmmServicesTableLib.h>\r
+#include <Guid/SmramMemoryReserve.h>\r
+#include <Library/ReportStatusCodeLib.h>\r
+#include <Library/HobLib.h>\r
+#include <QNCAccess.h>\r
+#include <Library/QNCAccessLib.h>\r
+#include <Library/IntelQNCLib.h>\r
+#include <Library/PlatformHelperLib.h>\r
+#include <Library/PlatformPcieHelperLib.h>\r
+#include "Platform.h"\r
+#include <IndustryStandard/Pci22.h>\r
+\r
+#define EFI_ACPI_ACPI_ENABLE 0xA0\r
+#define EFI_ACPI_ACPI_DISABLE 0xA1\r
+\r
+#define R_IOPORT_CMOS_STANDARD_INDEX 0x70\r
+#define R_IOPORT_CMOS_STANDARD_DATA 0x71\r
+#define RTC_ADDRESS_REGISTER_C 12\r
+#define RTC_ADDRESS_REGISTER_D 13\r
+\r
+#define PCI_DEVICE(Bus, Dev, Func) \\r
+ Bus, Dev, Func\r
+\r
+#define PCI_REG_MASK(Byte0, Byte1, Byte2, Byte3, Byte4, Byte5, Byte6, Byte7) \\r
+ Byte0, Byte1, Byte2, Byte3, Byte4, Byte5, Byte6, Byte7\r
+\r
+#define PCI_DEVICE_END 0xFF\r
+\r
+//\r
+// Related data structures definition\r
+//\r
+typedef struct _EFI_ACPI_SMM_DEV {\r
+\r
+ //\r
+ // Parent dispatch driver returned sleep handle\r
+ //\r
+ EFI_HANDLE S3SleepEntryHandle;\r
+\r
+ EFI_HANDLE S4SleepEntryHandle;\r
+\r
+ EFI_HANDLE S1SleepEntryHandle;\r
+\r
+ EFI_HANDLE S5SoftOffEntryHandle;\r
+\r
+ EFI_HANDLE EnableAcpiHandle;\r
+\r
+ EFI_HANDLE DisableAcpiHandle;\r
+\r
+ EFI_HANDLE PpCallbackHandle;\r
+\r
+ EFI_HANDLE MorCallbackHandle;\r
+\r
+ //\r
+ // QNC Power Management I/O register base\r
+ //\r
+ UINT32 QncPmBase;\r
+\r
+ //\r
+ // QNC General Purpose Event0 register base\r
+ //\r
+ UINT32 QncGpe0Base;\r
+\r
+ UINT32 BootScriptSaved;\r
+\r
+} EFI_ACPI_SMM_DEV;\r
+\r
+//\r
+// Prototypes\r
+//\r
+EFI_STATUS\r
+InitPlatformAcpiSmm (\r
+ IN EFI_HANDLE ImageHandle,\r
+ IN EFI_SYSTEM_TABLE *SystemTable,\r
+ IN OUT VOID *CommBuffer,\r
+ IN OUT UINTN *CommBufferSize\r
+ );\r
+\r
+EFI_STATUS\r
+SxSleepEntryCallBack (\r
+ IN EFI_HANDLE DispatchHandle,\r
+ IN CONST VOID *DispatchContext,\r
+\r
+ IN OUT VOID *CommBuffer,\r
+ IN OUT UINTN *CommBufferSize\r
+ );\r
+\r
+EFI_STATUS\r
+DisableAcpiCallback (\r
+ IN EFI_HANDLE DispatchHandle,\r
+ IN CONST VOID *DispatchContext,\r
+ IN OUT VOID *CommBuffer,\r
+ IN OUT UINTN *CommBufferSize\r
+ );\r
+\r
+EFI_STATUS\r
+EnableAcpiCallback (\r
+ IN EFI_HANDLE DispatchHandle,\r
+ IN CONST VOID *DispatchContext,\r
+ IN OUT VOID *CommBuffer,\r
+ IN OUT UINTN *CommBufferSize\r
+ );\r
+\r
+EFI_STATUS\r
+RegisterToDispatchDriver (\r
+ VOID\r
+ );\r
+\r
+EFI_STATUS\r
+GetAllQncPmBase (\r
+ IN EFI_SMM_SYSTEM_TABLE2 *Smst\r
+ );\r
+\r
+EFI_STATUS\r
+SaveRuntimeScriptTable (\r
+ IN EFI_SMM_SYSTEM_TABLE2 *Smst\r
+ );\r
+\r
+EFI_STATUS\r
+RestoreQncS3SwCallback (\r
+ IN EFI_HANDLE DispatchHandle,\r
+ IN CONST VOID *DispatchContext,\r
+ IN OUT VOID *CommBuffer,\r
+ IN OUT UINTN *CommBufferSize\r
+ );\r
+\r
+extern EFI_GUID gQncS3CodeInLockBoxGuid;\r
+extern EFI_GUID gQncS3ContextInLockBoxGuid;\r
+\r
+#endif\r
--- /dev/null
+## @file\r
+# Component description file for ACPI SMM Platform handler module\r
+#\r
+# This is QNC Smm platform driver .\r
+# Copyright (c) 2013-2015 Intel Corporation.\r
+#\r
+# This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution. The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php\r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+##\r
+\r
+\r
+[Defines]\r
+ INF_VERSION = 0x00010005\r
+ BASE_NAME = AcpiSmmPlatform\r
+ FILE_GUID = F5AC7057-5650-466e-B692-76A47223EFB0\r
+ MODULE_TYPE = DXE_SMM_DRIVER\r
+ VERSION_STRING = 1.0\r
+ PI_SPECIFICATION_VERSION = 0x0001000A\r
+ ENTRY_POINT = InitAcpiSmmPlatform\r
+\r
+[Sources]\r
+ AcpiSmmPlatform.c\r
+ AcpiSmmPlatform.h\r
+\r
+[Packages]\r
+ MdePkg/MdePkg.dec\r
+ MdeModulePkg/MdeModulePkg.dec\r
+ IntelFrameworkPkg/IntelFrameworkPkg.dec\r
+ IntelFrameworkModulePkg/IntelFrameworkModulePkg.dec\r
+ QuarkSocPkg/QuarkSocPkg.dec\r
+ QuarkPlatformPkg/QuarkPlatformPkg.dec\r
+\r
+[LibraryClasses]\r
+ UefiBootServicesTableLib\r
+ UefiRuntimeServicesTableLib\r
+ ReportStatusCodeLib\r
+ UefiDriverEntryPoint\r
+ DebugLib\r
+ IoLib\r
+ PciLib\r
+ BaseMemoryLib\r
+ BaseLib\r
+ SmmServicesTableLib\r
+ PcdLib\r
+ HobLib\r
+ S3BootScriptLib\r
+ LockBoxLib\r
+ PlatformHelperLib\r
+ IntelQNCLib\r
+ PlatformPcieHelperLib\r
+\r
+[Protocols]\r
+ gEfiSmmSxDispatch2ProtocolGuid\r
+ gEfiPciRootBridgeIoProtocolGuid\r
+ gEfiVariableArchProtocolGuid\r
+ gEfiVariableWriteArchProtocolGuid\r
+ gEfiGlobalNvsAreaProtocolGuid\r
+ gEfiSmmSwDispatch2ProtocolGuid\r
+\r
+[Guids]\r
+ gEfiSmmPeiSmramMemoryReserveGuid\r
+ gQncS3CodeInLockBoxGuid\r
+ gQncS3ContextInLockBoxGuid\r
+\r
+[Pcd]\r
+ gQuarkPlatformTokenSpaceGuid.PcdPlatformType\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdProgressCodeS3SuspendStart\r
+ gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdS3AcpiReservedMemorySize\r
+ gEfiQuarkNcSocIdTokenSpaceGuid.PcdGpe0blkIoBaseAddress\r
+ gEfiQuarkNcSocIdTokenSpaceGuid.PcdPm1blkIoBaseAddress\r
+\r
+[Depex]\r
+ gEfiSmmSxDispatch2ProtocolGuid AND\r
+ gEfiPciRootBridgeIoProtocolGuid AND\r
+ gEfiVariableArchProtocolGuid AND\r
+ gEfiVariableWriteArchProtocolGuid AND\r
+ gEfiGlobalNvsAreaProtocolGuid AND\r
+ gEfiQncS3SupportProtocolGuid\r
--- /dev/null
+/** @file\r
+\r
+Processor power management initialization code.\r
+\r
+Copyright (c) 2013-2015 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+**/\r
+\r
+#include "SmmPowerManagement.h"\r
+\r
+//\r
+// Global variables\r
+//\r
+extern EFI_ACPI_SDT_PROTOCOL *mAcpiSdt;\r
+extern EFI_ACPI_TABLE_PROTOCOL *mAcpiTable;\r
+\r
+extern EFI_GUID gPowerManagementAcpiTableStorageGuid;\r
+\r
+/**\r
+ This function is the entry of processor power management initialization code.\r
+ It initializes the processor's power management features based on the user\r
+ configurations and hardware capabilities.\r
+**/\r
+VOID\r
+PpmInit (\r
+ VOID\r
+ )\r
+{\r
+ //\r
+ // Processor Power Management Flags\r
+ //\r
+ mGlobalNvsAreaPtr->Cfgd = PcdGet32(PcdPpmFlags);\r
+\r
+ //\r
+ // Patch and publish power management related acpi tables\r
+ //\r
+ PpmPatchAndPublishAcpiTables();\r
+}\r
+\r
+/**\r
+ This function is to patch and publish power management related acpi tables.\r
+**/\r
+VOID\r
+PpmPatchAndPublishAcpiTables (\r
+ VOID\r
+ )\r
+{\r
+ //\r
+ // Patch FADT table to enable C2,C3\r
+ //\r
+ PpmPatchFadtTable();\r
+\r
+ //\r
+ // Load all the power management acpi tables and patch IST table\r
+ //\r
+ PpmLoadAndPatchPMTables();\r
+}\r
+\r
+/**\r
+ This function is to patch PLvl2Lat and PLvl3Lat to enable C2, C3 support in OS.\r
+**/\r
+VOID\r
+PpmPatchFadtTable (\r
+ VOID\r
+ )\r
+{\r
+ EFI_STATUS Status;\r
+ EFI_ACPI_DESCRIPTION_HEADER *Table;\r
+ EFI_ACPI_SDT_HEADER *CurrentTable;\r
+ EFI_ACPI_TABLE_VERSION Version;\r
+ UINTN Index;\r
+ UINTN Handle;\r
+ EFI_ACPI_3_0_FIXED_ACPI_DESCRIPTION_TABLE *FadtPointer;\r
+\r
+ //\r
+ // Scan all the acpi tables to find FADT 2.0\r
+ //\r
+ Index = 0;\r
+ do {\r
+ Status = mAcpiSdt->GetAcpiTable (\r
+ Index,\r
+ &CurrentTable,\r
+ &Version,\r
+ &Handle\r
+ );\r
+ if (Status == EFI_NOT_FOUND) {\r
+ break;\r
+ }\r
+ ASSERT_EFI_ERROR (Status);\r
+ Index++;\r
+ } while (CurrentTable->Signature != EFI_ACPI_3_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE || CurrentTable->Revision != 0x03);\r
+\r
+ ASSERT (CurrentTable->Signature == EFI_ACPI_3_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE);\r
+\r
+ Table = NULL;\r
+ Status = gBS->AllocatePool (EfiBootServicesData, CurrentTable->Length, (VOID **) &Table);\r
+ ASSERT (Table != NULL);\r
+ CopyMem (Table, CurrentTable, CurrentTable->Length);\r
+\r
+ FadtPointer = (EFI_ACPI_3_0_FIXED_ACPI_DESCRIPTION_TABLE*) Table;\r
+\r
+ //\r
+ // Update the ACPI table and recalculate checksum\r
+ //\r
+ Status = mAcpiTable->UninstallAcpiTable (mAcpiTable, Handle);\r
+ if (EFI_ERROR (Status)) {\r
+ //\r
+ // Should not get an error here ever, but abort if we do.\r
+ //\r
+ return ;\r
+ }\r
+\r
+ //\r
+ // Update the check sum\r
+ // It needs to be zeroed before the checksum calculation\r
+ //\r
+ ((EFI_ACPI_SDT_HEADER *)Table)->Checksum = 0;\r
+ ((EFI_ACPI_SDT_HEADER *)Table)->Checksum =\r
+ CalculateCheckSum8 ((VOID *)Table, Table->Length);\r
+\r
+ //\r
+ // Add the table\r
+ //\r
+ Status = mAcpiTable->InstallAcpiTable (\r
+ mAcpiTable,\r
+ Table,\r
+ Table->Length,\r
+ &Handle\r
+ );\r
+ ASSERT_EFI_ERROR (Status);\r
+ gBS->FreePool (Table);\r
+}\r
+\r
+VOID\r
+SsdtTableUpdate (\r
+ IN OUT EFI_ACPI_DESCRIPTION_HEADER *TableHeader\r
+ )\r
+/*++\r
+\r
+ Routine Description:\r
+\r
+ Update the SSDT table\r
+\r
+ Arguments:\r
+\r
+ Table - The SSDT table to be patched\r
+\r
+ Returns:\r
+\r
+ None\r
+\r
+--*/\r
+{\r
+ UINT8 *CurrPtr;\r
+ UINT8 *SsdtPointer;\r
+ UINT32 *Signature;\r
+\r
+ //\r
+ // Loop through the ASL looking for values that we must fix up.\r
+ //\r
+ CurrPtr = (UINT8 *) TableHeader;\r
+ for (SsdtPointer = CurrPtr;\r
+ SsdtPointer <= (CurrPtr + ((EFI_ACPI_COMMON_HEADER *) CurrPtr)->Length);\r
+ SsdtPointer++\r
+ )\r
+ {\r
+ Signature = (UINT32 *) SsdtPointer;\r
+ if ((*Signature) == SIGNATURE_32 ('P', 'M', 'B', 'A')) {\r
+ switch (*(Signature+1)) {\r
+ case (SIGNATURE_32 ('L', 'V', 'L', '0')):\r
+ Signature[0] = PcdGet16(PcdPmbaIoBaseAddress);\r
+ Signature[1] = 0;\r
+ break;\r
+ case (SIGNATURE_32 ('L', 'V', 'L', '2')):\r
+ Signature[0] = PcdGet16(PcdPmbaIoLVL2);\r
+ Signature[1] = 0;\r
+ break;\r
+ }\r
+ }\r
+ }\r
+}\r
+\r
+EFI_STATUS\r
+LocateSupportProtocol (\r
+ IN EFI_GUID *Protocol,\r
+ OUT VOID **Instance,\r
+ IN UINT32 Type\r
+ )\r
+/*++\r
+\r
+Routine Description:\r
+\r
+ Locate the first instance of a protocol. If the protocol requested is an\r
+ FV protocol, then it will return the first FV that contains the ACPI table\r
+ storage file.\r
+\r
+Arguments:\r
+\r
+ Protocol The protocol to find.\r
+ Instance Return pointer to the first instance of the protocol\r
+\r
+Returns:\r
+\r
+ EFI_SUCCESS The function completed successfully.\r
+ EFI_NOT_FOUND The protocol could not be located.\r
+ EFI_OUT_OF_RESOURCES There are not enough resources to find the protocol.\r
+\r
+--*/\r
+{\r
+ EFI_STATUS Status;\r
+ EFI_HANDLE *HandleBuffer;\r
+ UINTN NumberOfHandles;\r
+ EFI_FV_FILETYPE FileType;\r
+ UINT32 FvStatus;\r
+ EFI_FV_FILE_ATTRIBUTES Attributes;\r
+ UINTN Size;\r
+ UINTN i;\r
+\r
+ FvStatus = 0;\r
+\r
+ //\r
+ // Locate protocol.\r
+ //\r
+ Status = gBS->LocateHandleBuffer (\r
+ ByProtocol,\r
+ Protocol,\r
+ NULL,\r
+ &NumberOfHandles,\r
+ &HandleBuffer\r
+ );\r
+ if (EFI_ERROR (Status)) {\r
+\r
+ //\r
+ // Defined errors at this time are not found and out of resources.\r
+ //\r
+ return Status;\r
+ }\r
+\r
+\r
+\r
+ //\r
+ // Looking for FV with ACPI storage file\r
+ //\r
+\r
+ for (i = 0; i < NumberOfHandles; i++) {\r
+ //\r
+ // Get the protocol on this handle\r
+ // This should not fail because of LocateHandleBuffer\r
+ //\r
+ Status = gBS->HandleProtocol (\r
+ HandleBuffer[i],\r
+ Protocol,\r
+ Instance\r
+ );\r
+ ASSERT_EFI_ERROR (Status);\r
+\r
+ if (!Type) {\r
+ //\r
+ // Not looking for the FV protocol, so find the first instance of the\r
+ // protocol. There should not be any errors because our handle buffer\r
+ // should always contain at least one or LocateHandleBuffer would have\r
+ // returned not found.\r
+ //\r
+ break;\r
+ }\r
+\r
+ //\r
+ // See if it has the ACPI storage file\r
+ //\r
+\r
+ Status = ((EFI_FIRMWARE_VOLUME2_PROTOCOL*) (*Instance))->ReadFile (*Instance,\r
+ &gPowerManagementAcpiTableStorageGuid,\r
+ NULL,\r
+ &Size,\r
+ &FileType,\r
+ &Attributes,\r
+ &FvStatus\r
+ );\r
+\r
+ //\r
+ // If we found it, then we are done\r
+ //\r
+ if (Status == EFI_SUCCESS) {\r
+ break;\r
+ }\r
+ }\r
+\r
+ //\r
+ // Our exit status is determined by the success of the previous operations\r
+ // If the protocol was found, Instance already points to it.\r
+ //\r
+\r
+ //\r
+ // Free any allocated buffers\r
+ //\r
+ gBS->FreePool (HandleBuffer);\r
+\r
+ return Status;\r
+}\r
+\r
+/**\r
+ This function is to load all the power management acpi tables and patch IST table.\r
+**/\r
+VOID\r
+PpmLoadAndPatchPMTables (\r
+ VOID\r
+ )\r
+{\r
+ EFI_FIRMWARE_VOLUME2_PROTOCOL *FwVol;\r
+ EFI_STATUS Status;\r
+ INTN Instance;\r
+ EFI_ACPI_COMMON_HEADER *CurrentTable;\r
+ UINTN TableHandle;\r
+ UINT32 FvStatus;\r
+ UINTN Size;\r
+ EFI_ACPI_TABLE_VERSION Version;\r
+\r
+ Status = LocateSupportProtocol (&gEfiFirmwareVolume2ProtocolGuid, (VOID**)&FwVol, 1);\r
+ if (EFI_ERROR (Status)) {\r
+ return;\r
+ }\r
+\r
+ //\r
+ // Read tables from the storage file.\r
+ //\r
+ Instance = 0;\r
+ CurrentTable = NULL;\r
+\r
+ while (Status == EFI_SUCCESS) {\r
+\r
+ Status = FwVol->ReadSection (\r
+ FwVol,\r
+ &gPowerManagementAcpiTableStorageGuid,\r
+ EFI_SECTION_RAW,\r
+ Instance,\r
+ (VOID**)&CurrentTable,\r
+ &Size,\r
+ &FvStatus\r
+ );\r
+\r
+ if (!EFI_ERROR(Status)) {\r
+ Version = EFI_ACPI_TABLE_VERSION_1_0B | EFI_ACPI_TABLE_VERSION_2_0 | EFI_ACPI_TABLE_VERSION_3_0;\r
+\r
+ if(((EFI_ACPI_DESCRIPTION_HEADER*) CurrentTable)->OemTableId == SIGNATURE_64 ('C', 'p', 'u', '0', 'I', 's', 't', 0)) {\r
+ Version = EFI_ACPI_TABLE_VERSION_NONE;\r
+ } else if(((EFI_ACPI_DESCRIPTION_HEADER*) CurrentTable)->OemTableId == SIGNATURE_64 ('C', 'p', 'u', '1', 'I', 's', 't', 0)) {\r
+ Version = EFI_ACPI_TABLE_VERSION_NONE;\r
+ }\r
+\r
+ SsdtTableUpdate ((EFI_ACPI_DESCRIPTION_HEADER *) CurrentTable);\r
+\r
+ //\r
+ // Update the check sum\r
+ // It needs to be zeroed before the checksum calculation\r
+ //\r
+ ((EFI_ACPI_SDT_HEADER *)CurrentTable)->Checksum = 0;\r
+ ((EFI_ACPI_SDT_HEADER *)CurrentTable)->Checksum = (UINT8)\r
+ CalculateCheckSum8 ((VOID *)CurrentTable, CurrentTable->Length);\r
+\r
+ //\r
+ // Add the table\r
+ //\r
+ TableHandle = 0;\r
+ Status = mAcpiTable->InstallAcpiTable (\r
+ mAcpiTable,\r
+ CurrentTable,\r
+ CurrentTable->Length,\r
+ &TableHandle\r
+ );\r
+\r
+ ASSERT_EFI_ERROR (Status);\r
+\r
+ //\r
+ // Increment the instance\r
+ //\r
+ Instance++;\r
+ CurrentTable = NULL;\r
+ }\r
+ }\r
+\r
+}\r
--- /dev/null
+/** @file\r
+\r
+Processor power management initialization code.\r
+\r
+Copyright (c) 2013-2015 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+**/\r
+\r
+#ifndef _PPM_H\r
+#define _PPM_H\r
+\r
+//\r
+// Bit definitions of PPMFlags\r
+//\r
+#define PPM_GV3 (1 << 0) // Geyserville 3\r
+#define PPM_TURBO (1 << 1) // Turbo Mode\r
+#define PPM_SUPER_LFM (1 << 2) // N/2 Ratio\r
+#define PPM_C1 (1 << 4) // C1 Capable, Enabled\r
+#define PPM_C2 (1 << 5) // C2 Capable, Enabled\r
+#define PPM_C3 (1 << 6) // C3 Capable, Enabled\r
+#define PPM_C4 (1 << 7) // C4 Capable, Enabled\r
+#define PPM_C5 (1 << 8) // C5/Deep C4 Capable, Enabled\r
+#define PPM_C6 (1 << 9) // C6 Capable, Enabled\r
+#define PPM_C1E (1 << 10) // C1E Enabled\r
+#define PPM_C2E (1 << 11) // C2E Enabled\r
+#define PPM_C3E (1 << 12) // C3E Enabled\r
+#define PPM_C4E (1 << 13) // C4E Enabled\r
+#define PPM_HARD_C4E (1 << 14) // Hard C4E Capable, Enabled\r
+#define PPM_TM1 (1 << 16) // Thermal Monitor 1\r
+#define PPM_TM2 (1 << 17) // Thermal Monitor 2\r
+#define PPM_PHOT (1 << 19) // Bi-directional ProcHot\r
+#define PPM_MWAIT_EXT (1 << 21) // MWAIT extensions supported\r
+#define PPM_CMP (1 << 24) // CMP supported, Enabled\r
+#define PPM_TSTATE (1 << 28) // CPU T states supported\r
+\r
+#define PPM_C_STATES (PPM_C1 + PPM_C2 + PPM_C3 + PPM_C4 + PPM_C5 + PPM_C6)\r
+#define PPM_CE_STATES (PPM_C1E + PPM_C2E + PPM_C3E + PPM_C4E + PPM_HARD_C4E)\r
+\r
+\r
+#define MAX_P_STATES_NUM 12\r
+\r
+#define AML_NAME_OP 0x08\r
+#define AML_SCOPE_OP 0x10\r
+#define AML_PACKAGE_OP 0x12\r
+#define AML_METHOD_OP 0x14\r
+\r
+#define S3_CPU_REGISTER_TABLE_GUID \\r
+ { \\r
+ 0xc4ef988d, 0xe5e, 0x4403, { 0xbe, 0xeb, 0xf1, 0xbb, 0x6, 0x79, 0x6e, 0xdf } \\r
+ }\r
+\r
+#pragma pack(1)\r
+typedef struct {\r
+ UINT8 StartByte;\r
+ UINT32 NameStr;\r
+ UINT8 OpCode;\r
+ UINT16 Size; // Hardcode to 16bit width because the table we use is fixed size\r
+ UINT8 NumEntries;\r
+} EFI_ACPI_NAME_COMMAND;\r
+\r
+typedef struct {\r
+ UINT8 PackageOp;\r
+ UINT8 PkgLeadByte;\r
+ UINT8 NumEntries;\r
+ UINT8 DwordPrefix0;\r
+ UINT32 CoreFreq;\r
+ UINT8 DwordPrefix1;\r
+ UINT32 Power;\r
+ UINT8 DwordPrefix2;\r
+ UINT32 TransLatency;\r
+ UINT8 DwordPrefix3;\r
+ UINT32 BMLatency;\r
+ UINT8 DwordPrefix4;\r
+ UINT32 Control;\r
+ UINT8 DwordPrefix5;\r
+ UINT32 Status;\r
+} EFI_PSS_PACKAGE;\r
+#pragma pack()\r
+\r
+typedef struct {\r
+ UINT32 Index;\r
+ UINT64 Value;\r
+} S3_CPU_REGISTER;\r
+\r
+//\r
+// Function prototypes\r
+//\r
+\r
+/**\r
+ This function is the entry of processor power management initialization code.\r
+ It initializes the processor's power management features based on the user\r
+ configurations and hardware capablities.\r
+**/\r
+VOID\r
+PpmInit (\r
+ VOID\r
+ );\r
+\r
+/**\r
+ This function is to determine the Processor Power Management Flags\r
+ based on the hardware capability.\r
+**/\r
+VOID\r
+PpmDetectCapability (\r
+ VOID\r
+ );\r
+\r
+/**\r
+ This function is to determine the user configuration mask\r
+**/\r
+VOID\r
+PpmGetUserConfigurationMask (\r
+ VOID\r
+ );\r
+\r
+/**\r
+ This function is to patch and publish power management related acpi tables.\r
+**/\r
+VOID\r
+PpmPatchAndPublishAcpiTables (\r
+ VOID\r
+ );\r
+\r
+/**\r
+ This function is to patch PLvl2Lat and PLvl3Lat to enable C2, C3 support in OS.\r
+**/\r
+VOID\r
+PpmPatchFadtTable (\r
+ VOID\r
+ );\r
+\r
+/**\r
+ This function is to load all the power management acpi tables and patch IST table.\r
+**/\r
+VOID\r
+PpmLoadAndPatchPMTables (\r
+ VOID\r
+ );\r
+\r
+/**\r
+ This function is to save cpu registers for s3 resume.\r
+**/\r
+VOID\r
+PpmS3SaveRegisters (\r
+ VOID\r
+ );\r
+#endif\r
--- /dev/null
+/** @file\r
+\r
+This is QNC Smm Power Management driver\r
+\r
+Copyright (c) 2013-2015 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+**/\r
+\r
+#include "SmmPowerManagement.h"\r
+\r
+//\r
+// Global variables\r
+//\r
+EFI_SMM_CPU_PROTOCOL *mSmmCpu = NULL;\r
+EFI_GLOBAL_NVS_AREA *mGlobalNvsAreaPtr = NULL;\r
+EFI_MP_SERVICES_PROTOCOL *mMpService = NULL;\r
+EFI_ACPI_SDT_PROTOCOL *mAcpiSdt = NULL;\r
+EFI_ACPI_TABLE_PROTOCOL *mAcpiTable = NULL;\r
+\r
+EFI_GUID mS3CpuRegisterTableGuid = S3_CPU_REGISTER_TABLE_GUID;\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+InitializePowerManagement (\r
+ IN EFI_HANDLE ImageHandle,\r
+ IN EFI_SYSTEM_TABLE *SystemTable\r
+ )\r
+/*++\r
+\r
+Routine Description:\r
+\r
+ Initializes the SMM Handler Driver\r
+\r
+Arguments:\r
+\r
+ ImageHandle -\r
+\r
+ SystemTable -\r
+\r
+Returns:\r
+\r
+ None\r
+\r
+--*/\r
+{\r
+ EFI_STATUS Status;\r
+ EFI_SMM_SW_DISPATCH2_PROTOCOL *SwDispatch;\r
+ EFI_GLOBAL_NVS_AREA_PROTOCOL *GlobalNvsAreaProtocol;\r
+\r
+ //\r
+ // Get SMM CPU protocol\r
+ //\r
+ Status = gSmst->SmmLocateProtocol (\r
+ &gEfiSmmCpuProtocolGuid,\r
+ NULL,\r
+ (VOID **)&mSmmCpu\r
+ );\r
+ ASSERT_EFI_ERROR (Status);\r
+\r
+ //\r
+ // Get the Sw dispatch protocol\r
+ //\r
+ Status = gSmst->SmmLocateProtocol (\r
+ &gEfiSmmSwDispatch2ProtocolGuid,\r
+ NULL,\r
+ (VOID**)&SwDispatch\r
+ );\r
+ ASSERT_EFI_ERROR (Status);\r
+\r
+ //\r
+ // Get Global NVS Area Protocol\r
+ //\r
+ Status = gBS->LocateProtocol (&gEfiGlobalNvsAreaProtocolGuid, NULL, (VOID **)&GlobalNvsAreaProtocol);\r
+ ASSERT_EFI_ERROR (Status);\r
+ mGlobalNvsAreaPtr = GlobalNvsAreaProtocol->Area;\r
+\r
+ //\r
+ // Locate and cache PI AcpiSdt Protocol.\r
+ //\r
+ Status = gBS->LocateProtocol (\r
+ &gEfiAcpiSdtProtocolGuid,\r
+ NULL,\r
+ (VOID **) &mAcpiSdt\r
+ );\r
+ ASSERT_EFI_ERROR (Status);\r
+\r
+\r
+ //\r
+ // Locate and cache PI AcpiSdt Protocol.\r
+ //\r
+ Status = gBS->LocateProtocol (\r
+ &gEfiAcpiTableProtocolGuid,\r
+ NULL,\r
+ (VOID **) &mAcpiTable\r
+ );\r
+ ASSERT_EFI_ERROR (Status);\r
+\r
+\r
+ //\r
+ // Get MpService protocol\r
+ //\r
+ Status = gBS->LocateProtocol (&gEfiMpServiceProtocolGuid, NULL, (VOID **)&mMpService);\r
+ ASSERT_EFI_ERROR (Status);\r
+ //\r
+ // Initialize power management features on processors\r
+ //\r
+ PpmInit();\r
+\r
+ return Status;\r
+}\r
--- /dev/null
+/** @file\r
+Header file for QNC Smm Power Management driver\r
+\r
+Copyright (c) 2013-2015 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#ifndef _SMM_POWER_MANAGEMENT_H_\r
+#define _SMM_POWER_MANAGEMENT_H_\r
+\r
+#include <PiSmm.h>\r
+#include <IntelQNCDxe.h>\r
+\r
+#include <Protocol/AcpiTable.h>\r
+#include <Protocol/SmmCpu.h>\r
+#include <Protocol/SmmSwDispatch2.h>\r
+#include <Protocol/GlobalNvsArea.h>\r
+#include <Protocol/AcpiSystemDescriptionTable.h>\r
+#include <Protocol/FirmwareVolume2.h>\r
+#include <Protocol/MpService.h>\r
+\r
+#include <Library/DebugLib.h>\r
+#include <Library/PcdLib.h>\r
+#include <Library/IoLib.h>\r
+#include <Library/PciLib.h>\r
+#include <Library/BaseLib.h>\r
+#include <Library/BaseMemoryLib.h>\r
+#include <Library/SmmServicesTableLib.h>\r
+#include <Library/UefiBootServicesTableLib.h>\r
+#include <Library/S3BootScriptLib.h>\r
+#include <Library/MemoryAllocationLib.h>\r
+\r
+#include <IndustryStandard/Acpi.h>\r
+\r
+#include <AcpiCpuData.h>\r
+\r
+#include "Ppm.h"\r
+\r
+//\r
+// Module global variable\r
+//\r
+extern EFI_SMM_CPU_PROTOCOL *mSmmCpu;\r
+extern EFI_GLOBAL_NVS_AREA *mGlobalNvsAreaPtr;\r
+extern EFI_MP_SERVICES_PROTOCOL *mMpService;\r
+\r
+//\r
+// Function prototypes\r
+//\r
+\r
+#endif\r
--- /dev/null
+## @file\r
+# Component description file for SMM Power Management module\r
+#\r
+# This is QNC Smm Power Management driver .\r
+# Copyright (c) 2013-2015 Intel Corporation.\r
+#\r
+# This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution. The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php\r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+##\r
+\r
+[Defines]\r
+ INF_VERSION = 0x00010005\r
+ BASE_NAME = SmmPowerManagement\r
+ FILE_GUID = 271F1343-20D6-4e14-9B62-3C0297F56F07\r
+ MODULE_TYPE = DXE_SMM_DRIVER\r
+ VERSION_STRING = 1.0\r
+ PI_SPECIFICATION_VERSION = 0x0001000A\r
+ ENTRY_POINT = InitializePowerManagement\r
+\r
+#\r
+# The following information is for reference only and not required by the build tools.\r
+#\r
+# VALID_ARCHITECTURES = IA32 X64 IPF EBC\r
+#\r
+\r
+[Sources]\r
+ SmmPowerManagement.c\r
+ SmmPowerManagement.h\r
+ Ppm.c\r
+ Ppm.h\r
+\r
+[Packages]\r
+ MdePkg/MdePkg.dec\r
+ MdeModulePkg/MdeModulePkg.dec\r
+ UefiCpuPkg/UefiCpuPkg.dec\r
+ QuarkSocPkg/QuarkSocPkg.dec\r
+ QuarkPlatformPkg/QuarkPlatformPkg.dec\r
+\r
+[LibraryClasses]\r
+ UefiDriverEntryPoint\r
+ DebugLib\r
+ PcdLib\r
+ IoLib\r
+ PciLib\r
+ BaseLib\r
+ BaseMemoryLib\r
+ SmmServicesTableLib\r
+ UefiBootServicesTableLib\r
+ S3BootScriptLib\r
+ MemoryAllocationLib\r
+\r
+[Protocols]\r
+ gEfiSmmCpuProtocolGuid # PROTOCOL ALWAYS_CONSUMED\r
+ gEfiSmmSwDispatch2ProtocolGuid # PROTOCOL ALWAYS_CONSUMED\r
+ gEfiGlobalNvsAreaProtocolGuid # PROTOCOL ALWAYS_CONSUMED\r
+ gEfiFirmwareVolume2ProtocolGuid # PROTOCOL ALWAYS_CONSUMED\r
+ gEfiMpServiceProtocolGuid # PROTOCOL ALWAYS_CONSUMED\r
+ gEfiAcpiSdtProtocolGuid # PROTOCOL ALWAYS_CONSUMED\r
+ gEfiAcpiTableProtocolGuid # PROTOCOL ALWAYS_CONSUMED\r
+\r
+[Guids]\r
+ gPowerManagementAcpiTableStorageGuid\r
+\r
+[Pcd]\r
+ gEfiQuarkNcSocIdTokenSpaceGuid.PcdPmbaIoBaseAddress\r
+ gEfiQuarkNcSocIdTokenSpaceGuid.PcdPmbaIoLVL2\r
+ gQuarkPlatformTokenSpaceGuid.PcdPpmFlags\r
+\r
+[Depex]\r
+ gEfiSmmCpuProtocolGuid AND\r
+ gEfiSmmSwDispatch2ProtocolGuid AND\r
+ gEfiGlobalNvsAreaProtocolGuid AND\r
+ gEfiAcpiTableProtocolGuid AND\r
+ gEfiMpServiceProtocolGuid\r
--- /dev/null
+\r
+======================\r
+= Code Contributions =\r
+======================\r
+\r
+To make a contribution to a TianoCore project, follow these steps.\r
+1. Create a change description in the format specified below to\r
+ use in the source control commit log.\r
+2. Your commit message must include your "Signed-off-by" signature,\r
+ and "Contributed-under" message.\r
+3. Your "Contributed-under" message explicitly states that the\r
+ contribution is made under the terms of the specified\r
+ contribution agreement. Your "Contributed-under" message\r
+ must include the name of contribution agreement and version.\r
+ For example: Contributed-under: TianoCore Contribution Agreement 1.0\r
+ The "TianoCore Contribution Agreement" is included below in\r
+ this document.\r
+4. Submit your code to the TianoCore project using the process\r
+ that the project documents on its web page. If the process is\r
+ not documented, then submit the code on development email list\r
+ for the project.\r
+5. It is preferred that contributions are submitted using the same\r
+ copyright license as the base project. When that is not possible,\r
+ then contributions using the following licenses can be accepted:\r
+ * BSD (2-clause): http://opensource.org/licenses/BSD-2-Clause\r
+ * BSD (3-clause): http://opensource.org/licenses/BSD-3-Clause\r
+ * MIT: http://opensource.org/licenses/MIT\r
+ * Python-2.0: http://opensource.org/licenses/Python-2.0\r
+ * Zlib: http://opensource.org/licenses/Zlib\r
+\r
+ Contributions of code put into the public domain can also be\r
+ accepted.\r
+\r
+ Contributions using other licenses might be accepted, but further\r
+ review will be required.\r
+\r
+=====================================================\r
+= Change Description / Commit Message / Patch Email =\r
+=====================================================\r
+\r
+Your change description should use the standard format for a\r
+commit message, and must include your "Signed-off-by" signature\r
+and the "Contributed-under" message.\r
+\r
+== Sample Change Description / Commit Message =\r
+\r
+=== Start of sample patch email message ===\r
+\r
+From: Contributor Name <contributor@example.com>\r
+Subject: [PATCH] CodeModule: Brief-single-line-summary\r
+\r
+Full-commit-message\r
+\r
+Contributed-under: TianoCore Contribution Agreement 1.0\r
+Signed-off-by: Contributor Name <contributor@example.com>\r
+---\r
+\r
+An extra message for the patch email which will not be considered part\r
+of the commit message can be added here.\r
+\r
+Patch content inline or attached\r
+\r
+=== End of sample patch email message ===\r
+\r
+=== Notes for sample patch email ===\r
+\r
+* The first line of commit message is taken from the email's subject\r
+ line following [PATCH]. The remaining portion of the commit message\r
+ is the email's content until the '---' line.\r
+* git format-patch is one way to create this format\r
+\r
+=== Definitions for sample patch email ===\r
+\r
+* "CodeModule" is a short idenfier for the affected code. For\r
+ example MdePkg, or MdeModulePkg UsbBusDxe.\r
+* "Brief-single-line-summary" is a short summary of the change.\r
+* The entire first line should be less than ~70 characters.\r
+* "Full-commit-message" a verbose multiple line comment describing\r
+ the change. Each line should be less than ~70 characters.\r
+* "Contributed-under" explicitely states that the contribution is\r
+ made under the terms of the contribtion agreement. This\r
+ agreement is included below in this document.\r
+* "Signed-off-by" is the contributor's signature identifying them\r
+ by their real/legal name and their email address.\r
+\r
+========================================\r
+= TianoCore Contribution Agreement 1.0 =\r
+========================================\r
+\r
+INTEL CORPORATION ("INTEL") MAKES AVAILABLE SOFTWARE, DOCUMENTATION,\r
+INFORMATION AND/OR OTHER MATERIALS FOR USE IN THE TIANOCORE OPEN SOURCE\r
+PROJECT (COLLECTIVELY "CONTENT"). USE OF THE CONTENT IS GOVERNED BY THE\r
+TERMS AND CONDITIONS OF THIS AGREEMENT BETWEEN YOU AND INTEL AND/OR THE\r
+TERMS AND CONDITIONS OF LICENSE AGREEMENTS OR NOTICES INDICATED OR\r
+REFERENCED BELOW. BY USING THE CONTENT, YOU AGREE THAT YOUR USE OF THE\r
+CONTENT IS GOVERNED BY THIS AGREEMENT AND/OR THE TERMS AND CONDITIONS\r
+OF ANY APPLICABLE LICENSE AGREEMENTS OR NOTICES INDICATED OR REFERENCED\r
+BELOW. IF YOU DO NOT AGREE TO THE TERMS AND CONDITIONS OF THIS\r
+AGREEMENT AND THE TERMS AND CONDITIONS OF ANY APPLICABLE LICENSE\r
+AGREEMENTS OR NOTICES INDICATED OR REFERENCED BELOW, THEN YOU MAY NOT\r
+USE THE CONTENT.\r
+\r
+Unless otherwise indicated, all Content made available on the TianoCore\r
+site is provided to you under the terms and conditions of the BSD\r
+License ("BSD"). A copy of the BSD License is available at\r
+http://opensource.org/licenses/bsd-license.php\r
+or when applicable, in the associated License.txt file.\r
+\r
+Certain other content may be made available under other licenses as\r
+indicated in or with such Content. (For example, in a License.txt file.)\r
+\r
+You accept and agree to the following terms and conditions for Your\r
+present and future Contributions submitted to TianoCore site. Except\r
+for the license granted to Intel hereunder, You reserve all right,\r
+title, and interest in and to Your Contributions.\r
+\r
+== SECTION 1: Definitions ==\r
+* "You" or "Contributor" shall mean the copyright owner or legal\r
+ entity authorized by the copyright owner that is making a\r
+ Contribution hereunder. All other entities that control, are\r
+ controlled by, or are under common control with that entity are\r
+ considered to be a single Contributor. For the purposes of this\r
+ definition, "control" means (i) the power, direct or indirect, to\r
+ cause the direction or management of such entity, whether by\r
+ contract or otherwise, or (ii) ownership of fifty percent (50%)\r
+ or more of the outstanding shares, or (iii) beneficial ownership\r
+ of such entity.\r
+* "Contribution" shall mean any original work of authorship,\r
+ including any modifications or additions to an existing work,\r
+ that is intentionally submitted by You to the TinaoCore site for\r
+ inclusion in, or documentation of, any of the Content. For the\r
+ purposes of this definition, "submitted" means any form of\r
+ electronic, verbal, or written communication sent to the\r
+ TianoCore site or its representatives, including but not limited\r
+ to communication on electronic mailing lists, source code\r
+ control systems, and issue tracking systems that are managed by,\r
+ or on behalf of, the TianoCore site for the purpose of\r
+ discussing and improving the Content, but excluding\r
+ communication that is conspicuously marked or otherwise\r
+ designated in writing by You as "Not a Contribution."\r
+\r
+== SECTION 2: License for Contributions ==\r
+* Contributor hereby agrees that redistribution and use of the\r
+ Contribution in source and binary forms, with or without\r
+ modification, are permitted provided that the following\r
+ conditions are met:\r
+** Redistributions of source code must retain the Contributor's\r
+ copyright notice, this list of conditions and the following\r
+ disclaimer.\r
+** Redistributions in binary form must reproduce the Contributor's\r
+ copyright notice, this list of conditions and the following\r
+ disclaimer in the documentation and/or other materials provided\r
+ with the distribution.\r
+* Disclaimer. None of the names of Contributor, Intel, or the names\r
+ of their respective contributors may be used to endorse or\r
+ promote products derived from this software without specific\r
+ prior written permission.\r
+* Contributor grants a license (with the right to sublicense) under\r
+ claims of Contributor's patents that Contributor can license that\r
+ are infringed by the Contribution (as delivered by Contributor) to\r
+ make, use, distribute, sell, offer for sale, and import the\r
+ Contribution and derivative works thereof solely to the minimum\r
+ extent necessary for licensee to exercise the granted copyright\r
+ license; this patent license applies solely to those portions of\r
+ the Contribution that are unmodified. No hardware per se is\r
+ licensed.\r
+* EXCEPT AS EXPRESSLY SET FORTH IN SECTION 3 BELOW, THE\r
+ CONTRIBUTION IS PROVIDED BY THE CONTRIBUTOR "AS IS" AND ANY\r
+ EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,\r
+ THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A\r
+ PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE\r
+ CONTRIBUTOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\r
+ SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT\r
+ NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\r
+ LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\r
+ HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\r
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR\r
+ OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THE\r
+ CONTRIBUTION, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH\r
+ DAMAGE.\r
+\r
+== SECTION 3: Representations ==\r
+* You represent that You are legally entitled to grant the above\r
+ license. If your employer(s) has rights to intellectual property\r
+ that You create that includes Your Contributions, You represent\r
+ that You have received permission to make Contributions on behalf\r
+ of that employer, that Your employer has waived such rights for\r
+ Your Contributions.\r
+* You represent that each of Your Contributions is Your original\r
+ creation (see Section 4 for submissions on behalf of others).\r
+ You represent that Your Contribution submissions include complete\r
+ details of any third-party license or other restriction\r
+ (including, but not limited to, related patents and trademarks)\r
+ of which You are personally aware and which are associated with\r
+ any part of Your Contributions.\r
+\r
+== SECTION 4: Third Party Contributions ==\r
+* Should You wish to submit work that is not Your original creation,\r
+ You may submit it to TianoCore site separately from any\r
+ Contribution, identifying the complete details of its source\r
+ and of any license or other restriction (including, but not\r
+ limited to, related patents, trademarks, and license agreements)\r
+ of which You are personally aware, and conspicuously marking the\r
+ work as "Submitted on behalf of a third-party: [named here]".\r
+\r
+== SECTION 5: Miscellaneous ==\r
+* Applicable Laws. Any claims arising under or relating to this\r
+ Agreement shall be governed by the internal substantive laws of\r
+ the State of Delaware or federal courts located in Delaware,\r
+ without regard to principles of conflict of laws.\r
+* Language. This Agreement is in the English language only, which\r
+ language shall be controlling in all respects, and all versions\r
+ of this Agreement in any other language shall be for accommodation\r
+ only and shall not be binding. All communications and notices made\r
+ or given pursuant to this Agreement, and all documentation and\r
+ support to be provided, unless otherwise noted, shall be in the\r
+ English language.\r
+\r
--- /dev/null
+/** @file\r
+Capsule on Data CD GUID.\r
+\r
+Copyright (c) 2013-2015 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+This is the contract between the recovery module and device recovery module\r
+in order to convey the name of a given recovery module type\r
+\r
+**/\r
+\r
+#ifndef _CAPSULE_ON_DATA_CD_H\r
+#define _CAPSULE_ON_DATA_CD_H\r
+\r
+#define PEI_CAPSULE_ON_DATA_CD_GUID \\r
+ { \\r
+ 0x5cac0099, 0x0dc9, 0x48e5, {0x80, 0x68, 0xbb, 0x95, 0xf5, 0x40, 0x0a, 0x9f } \\r
+ };\r
+\r
+extern EFI_GUID gPeiCapsuleOnDataCDGuid;\r
+\r
+#endif\r
--- /dev/null
+/** @file\r
+Capsule on Fat Floppy Disk GUID.\r
+\r
+Copyright (c) 2013-2015 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+This is the contract between the recovery module and device recovery module\r
+in order to convey the name of a given recovery module type\r
+\r
+**/\r
+\r
+#ifndef _CAPSULE_ON_FAT_FLOPPY_DISK_H\r
+#define _CAPSULE_ON_FAT_FLOPPY_DISK_H\r
+\r
+#define PEI_CAPSULE_ON_FAT_FLOPPY_DISK_GUID \\r
+ { \\r
+ 0x2e3d2e75, 0x9b2e, 0x412d, {0xb4, 0xb1, 0x70, 0x41, 0x6b, 0x87, 0x0, 0xff }\\r
+ };\r
+\r
+extern EFI_GUID gPeiCapsuleOnFatFloppyDiskGuid;\r
+\r
+#endif\r
--- /dev/null
+/** @file\r
+Capsule on Fat Ide Disk GUID.\r
+\r
+Copyright (c) 2013-2015 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+This is the contract between the recovery module and device recovery module\r
+in order to convey the name of a given recovery module type\r
+\r
+**/\r
+\r
+#ifndef _CAPSULE_ON_FAT_IDE_DISK_H\r
+#define _CAPSULE_ON_FAT_IDE_DISK_H\r
+\r
+#define PEI_CAPSULE_ON_FAT_IDE_DISK_GUID \\r
+ { \\r
+ 0xb38573b6, 0x6200, 0x4ac5, {0xb5, 0x1d, 0x82, 0xe6, 0x59, 0x38, 0xd7, 0x83 }\\r
+ };\r
+\r
+extern EFI_GUID gPeiCapsuleOnFatIdeDiskGuid;\r
+\r
+#endif\r
--- /dev/null
+/** @file\r
+Capsule on Fat Usb Disk GUID.\r
+\r
+Copyright (c) 2013-2015 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+This is the contract between the recovery module and device recovery module\r
+in order to convey the name of a given recovery module type\r
+\r
+**/\r
+\r
+#ifndef _PEI_CAPSULE_ON_FAT_USB_DISK_H\r
+#define _PEI_CAPSULE_ON_FAT_USB_DISK_H\r
+\r
+#define PEI_CAPSULE_ON_FAT_USB_DISK_GUID \\r
+ { \\r
+ 0x0ffbce19, 0x324c, 0x4690, {0xa0, 0x09, 0x98, 0xc6, 0xae, 0x2e, 0xb1, 0x86 } \\r
+ };\r
+\r
+extern EFI_GUID gPeiCapsuleOnFatUsbDiskGuid;\r
+\r
+#endif\r
--- /dev/null
+/** @file\r
+Define a GUID name for GUID HOB which is used to pass Memory\r
+Configuration Data information to different modules.\r
+\r
+Copyright (c) 2013-2015 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#ifndef _MEMORY_CONFIG_DATA_H_\r
+#define _MEMORY_CONFIG_DATA_H_\r
+\r
+#define EFI_MEMORY_CONFIG_DATA_GUID \\r
+ { \\r
+ 0x80dbd530, 0xb74c, 0x4f11, {0x8c, 0x03, 0x41, 0x86, 0x65, 0x53, 0x28, 0x31 } \\r
+ }\r
+\r
+#define EFI_MEMORY_CONFIG_DATA_NAME L"MemoryConfig"\r
+\r
+extern EFI_GUID gEfiMemoryConfigDataGuid;\r
+\r
+#endif\r
--- /dev/null
+/** @file\r
+\r
+Capsule format guid for Quark capsule image.\r
+\r
+Copyright (c) 2013-2015 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#ifndef _QUARK_CAPSULE_GUID_H_\r
+#define _QUARK_CAPSULE_GUID_H_\r
+\r
+#define QUARK_CAPSULE_GUID \\r
+ { 0xd400d1e4, 0xa314, 0x442b, { 0x89, 0xed, 0xa9, 0x2e, 0x4c, 0x81, 0x97, 0xcb } }\r
+\r
+#define SMI_INPUT_UPDATE_CAP 0x27\r
+#define SMI_INPUT_GET_CAP 0x28\r
+\r
+#define SMI_CAP_FUNCTION 0xEF\r
+\r
+#pragma pack(1)\r
+typedef struct {\r
+ UINT64 Address;\r
+ UINT32 BufferOffset;\r
+ UINT32 Size;\r
+ UINT32 Flags;\r
+ UINT32 Reserved;\r
+} CAPSULE_FRAGMENT;\r
+\r
+typedef struct {\r
+ UINTN CapsuleLocation; // Top of the capsule that point to structure CAPSULE_FRAGMENT\r
+ UINTN CapsuleSize; // Size of the capsule\r
+ EFI_STATUS Status; // Returned status\r
+} CAPSULE_INFO_PACKET;\r
+\r
+typedef struct {\r
+ UINTN BlocksCompleted; // # of blocks processed\r
+ UINTN TotalBlocks; // Total # of blocks to be processed\r
+ EFI_STATUS Status; // returned status\r
+} UPDATE_STATUS_PACKET;\r
+#pragma pack()\r
+\r
+extern EFI_GUID gEfiQuarkCapsuleGuid;\r
+\r
+#endif\r
--- /dev/null
+/** @file\r
+\r
+Guid and variable name used to trigger quark lock of specific UEFI variables.\r
+\r
+Copyright (c) 2013 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#ifndef _QUARK_VARIABLE_LOCK_GUID_H_\r
+#define _QUARK_VARIABLE_LOCK_GUID_H_\r
+\r
+#define QUARK_VARIABLE_LOCK_GUID \\r
+ { \\r
+ 0xeef749c2, 0xc047, 0x4d6e, { 0xb1, 0xbc, 0xd3, 0x6e, 0xb3, 0xa5, 0x55, 0x9c } \\r
+ }\r
+\r
+#define QUARK_VARIABLE_LOCK_NAME L"QuarkVariableLock"\r
+\r
+extern EFI_GUID gQuarkVariableLockGuid;\r
+\r
+#endif\r
--- /dev/null
+/** @file\r
+GUIDs used for System Non Volatile HOB entries in the in the HOB list and FV Guids carrying\r
+the System specific information.\r
+\r
+Copyright (c) 2013-2015 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#ifndef _SYSTEM_NV_DATA_HOB_GUID_H_\r
+#define _SYSTEM_NV_DATA_HOB_GUID_H_\r
+\r
+#define EFI_SYSTEM_NV_DATA_HOB_GUID \\r
+ {0xd6e5092d, 0xc7b2, 0x4872, {0xaf, 0x66, 0xfd, 0xc0, 0xe6, 0xf9, 0x5e, 0x78}}\r
+\r
+typedef struct {\r
+ EFI_GUID SystemNvDataHobGuid;\r
+ EFI_GUID SystemNvDataFvGuid;\r
+ EFI_LBA StartLba;\r
+ UINTN StartLbaOffset;\r
+ EFI_LBA EndLba;\r
+ UINTN EndLbaOffset;\r
+ UINT32 DataTypeSignature;\r
+} NV_SYSTEM_DATA_GUID_TYPE;\r
+\r
+extern EFI_GUID gEfiSystemNvDataHobGuid;\r
+\r
+#endif\r
--- /dev/null
+/** @file\r
+PlatformHelperLib function prototype definitions.\r
+\r
+Copyright (c) 2013 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#ifndef __PLATFORM_HELPER_LIB_H__\r
+#define __PLATFORM_HELPER_LIB_H__\r
+\r
+#include "Platform.h"\r
+\r
+//\r
+// Function prototypes for routines exported by this library.\r
+//\r
+\r
+/**\r
+ Find pointer to RAW data in Firmware volume file.\r
+\r
+ @param FvNameGuid Firmware volume to search. If == NULL search all.\r
+ @param FileNameGuid Firmware volume file to search for.\r
+ @param SectionData Pointer to RAW data section of found file.\r
+ @param SectionDataSize Pointer to UNITN to get size of RAW data.\r
+\r
+ @retval EFI_SUCCESS Raw Data found.\r
+ @retval EFI_INVALID_PARAMETER FileNameGuid == NULL.\r
+ @retval EFI_NOT_FOUND Firmware volume file not found.\r
+ @retval EFI_UNSUPPORTED Unsupported in current enviroment (PEI or DXE).\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+PlatformFindFvFileRawDataSection (\r
+ IN CONST EFI_GUID *FvNameGuid OPTIONAL,\r
+ IN CONST EFI_GUID *FileNameGuid,\r
+ OUT VOID **SectionData,\r
+ OUT UINTN *SectionDataSize\r
+ );\r
+\r
+/**\r
+ Read 8bit character from debug stream.\r
+\r
+ Block until character is read.\r
+\r
+ @return 8bit character read from debug stream.\r
+\r
+**/\r
+CHAR8\r
+EFIAPI\r
+PlatformDebugPortGetChar8 (\r
+ VOID\r
+ );\r
+\r
+/**\r
+ Find free spi protect register and write to it to protect a flash region.\r
+\r
+ @param DirectValue Value to directly write to register.\r
+ if DirectValue == 0 the use Base & Length below.\r
+ @param BaseAddress Base address of region in Flash Memory Map.\r
+ @param Length Length of region to protect.\r
+\r
+ @retval EFI_SUCCESS Free spi protect register found & written.\r
+ @retval EFI_NOT_FOUND Free Spi protect register not found.\r
+ @retval EFI_DEVICE_ERROR Unable to write to spi protect register.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+PlatformWriteFirstFreeSpiProtect (\r
+ IN CONST UINT32 DirectValue,\r
+ IN CONST UINT32 BaseAddress,\r
+ IN CONST UINT32 Length\r
+ );\r
+\r
+/**\r
+ Lock legacy SPI static configuration information.\r
+\r
+ Function will assert if unable to lock config.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+PlatformFlashLockConfig (\r
+ VOID\r
+ );\r
+\r
+/**\r
+ Lock regions and config of SPI flash given the policy for this platform.\r
+\r
+ Function will assert if unable to lock regions or config.\r
+\r
+ @param PreBootPolicy If TRUE do Pre Boot Flash Lock Policy.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+PlatformFlashLockPolicy (\r
+ IN CONST BOOLEAN PreBootPolicy\r
+ );\r
+\r
+/**\r
+ Erase and Write to platform flash.\r
+\r
+ Routine accesses one flash block at a time, each access consists\r
+ of an erase followed by a write of FLASH_BLOCK_SIZE. One or both\r
+ of DoErase & DoWrite params must be TRUE.\r
+\r
+ Limitations:-\r
+ CpuWriteAddress must be aligned to FLASH_BLOCK_SIZE.\r
+ DataSize must be a multiple of FLASH_BLOCK_SIZE.\r
+\r
+ @param Smst If != NULL then InSmm and use to locate\r
+ SpiProtocol.\r
+ @param CpuWriteAddress Address in CPU memory map of flash region.\r
+ @param Data The buffer containing the data to be written.\r
+ @param DataSize Amount of data to write.\r
+ @param DoErase Earse each block.\r
+ @param DoWrite Write to each block.\r
+\r
+ @retval EFI_SUCCESS Operation successful.\r
+ @retval EFI_NOT_READY Required resources not setup.\r
+ @retval EFI_INVALID_PARAMETER Invalid parameter.\r
+ @retval Others Unexpected error happened.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+PlatformFlashEraseWrite (\r
+ IN VOID *Smst,\r
+ IN UINTN CpuWriteAddress,\r
+ IN UINT8 *Data,\r
+ IN UINTN DataSize,\r
+ IN BOOLEAN DoErase,\r
+ IN BOOLEAN DoWrite\r
+ );\r
+\r
+/** Check if System booted with recovery Boot Stage1 image.\r
+\r
+ @retval TRUE If system booted with recovery Boot Stage1 image.\r
+ @retval FALSE If system booted with normal stage1 image.\r
+\r
+**/\r
+BOOLEAN\r
+EFIAPI\r
+PlatformIsBootWithRecoveryStage1 (\r
+ VOID\r
+ );\r
+\r
+/**\r
+ Clear SPI Protect registers.\r
+\r
+ @retval EFI_SUCESS SPI protect registers cleared.\r
+ @retval EFI_ACCESS_DENIED Unable to clear SPI protect registers.\r
+**/\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+PlatformClearSpiProtect (\r
+ VOID\r
+ );\r
+\r
+/**\r
+ Determine if an SPI address range is protected.\r
+\r
+ @param SpiBaseAddress Base of SPI range.\r
+ @param Length Length of SPI range.\r
+\r
+ @retval TRUE Range is protected.\r
+ @retval FALSE Range is not protected.\r
+**/\r
+BOOLEAN\r
+EFIAPI\r
+PlatformIsSpiRangeProtected (\r
+ IN CONST UINT32 SpiBaseAddress,\r
+ IN CONST UINT32 Length\r
+ );\r
+\r
+/**\r
+ Set Legacy GPIO Level\r
+\r
+ @param LevelRegOffset GPIO level register Offset from GPIO Base Address.\r
+ @param GpioNum GPIO bit to change.\r
+ @param HighLevel If TRUE set GPIO High else Set GPIO low.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+PlatformLegacyGpioSetLevel (\r
+ IN CONST UINT32 LevelRegOffset,\r
+ IN CONST UINT32 GpioNum,\r
+ IN CONST BOOLEAN HighLevel\r
+ );\r
+\r
+/**\r
+ Get Legacy GPIO Level\r
+\r
+ @param LevelRegOffset GPIO level register Offset from GPIO Base Address.\r
+ @param GpioNum GPIO bit to check.\r
+\r
+ @retval TRUE If bit is SET.\r
+ @retval FALSE If bit is CLEAR.\r
+\r
+**/\r
+BOOLEAN\r
+EFIAPI\r
+PlatformLegacyGpioGetLevel (\r
+ IN CONST UINT32 LevelRegOffset,\r
+ IN CONST UINT32 GpioNum\r
+ );\r
+\r
+/**\r
+ Set the direction of Pcal9555 IO Expander GPIO pin.\r
+\r
+ @param Pcal9555SlaveAddr I2c Slave address of Pcal9555 Io Expander.\r
+ @param GpioNum Gpio direction to configure - values 0-7 for Port0\r
+ and 8-15 for Port1.\r
+ @param CfgAsInput If TRUE set pin direction as input else set as output.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+PlatformPcal9555GpioSetDir (\r
+ IN CONST UINT32 Pcal9555SlaveAddr,\r
+ IN CONST UINT32 GpioNum,\r
+ IN CONST BOOLEAN CfgAsInput\r
+ );\r
+\r
+/**\r
+ Set the level of Pcal9555 IO Expander GPIO high or low.\r
+\r
+ @param Pcal9555SlaveAddr I2c Slave address of Pcal9555 Io Expander.\r
+ @param GpioNum Gpio to change values 0-7 for Port0 and 8-15\r
+ for Port1.\r
+ @param HighLevel If TRUE set pin high else set pin low.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+PlatformPcal9555GpioSetLevel (\r
+ IN CONST UINT32 Pcal9555SlaveAddr,\r
+ IN CONST UINT32 GpioNum,\r
+ IN CONST BOOLEAN HighLevel\r
+ );\r
+\r
+/**\r
+\r
+ Enable pull-up/pull-down resistors of Pcal9555 GPIOs.\r
+\r
+ @param Pcal9555SlaveAddr I2c Slave address of Pcal9555 Io Expander.\r
+ @param GpioNum Gpio to change values 0-7 for Port0 and 8-15\r
+ for Port1.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+PlatformPcal9555GpioEnablePull (\r
+ IN CONST UINT32 Pcal9555SlaveAddr,\r
+ IN CONST UINT32 GpioNum\r
+ );\r
+\r
+/**\r
+\r
+ Disable pull-up/pull-down resistors of Pcal9555 GPIOs.\r
+\r
+ @param Pcal9555SlaveAddr I2c Slave address of Pcal9555 Io Expander.\r
+ @param GpioNum Gpio to change values 0-7 for Port0 and 8-15\r
+ for Port1.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+PlatformPcal9555GpioDisablePull (\r
+ IN CONST UINT32 Pcal9555SlaveAddr,\r
+ IN CONST UINT32 GpioNum\r
+ );\r
+\r
+BOOLEAN\r
+EFIAPI\r
+PlatformPcal9555GpioGetState (\r
+ IN CONST UINT32 Pcal9555SlaveAddr,\r
+ IN CONST UINT32 GpioNum\r
+ );\r
+\r
+/**\r
+ Init platform LEDs into known state.\r
+\r
+ @param PlatformType Executing platform type.\r
+\r
+ @retval EFI_SUCCESS Operation success.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+PlatformLedInit (\r
+ IN CONST EFI_PLATFORM_TYPE Type\r
+ );\r
+\r
+/**\r
+ Turn on or off platform flash update LED.\r
+\r
+ @param PlatformType Executing platform type.\r
+ @param TurnOn If TRUE turn on else turn off.\r
+\r
+ @retval EFI_SUCCESS Operation success.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+PlatformFlashUpdateLed (\r
+ IN CONST EFI_PLATFORM_TYPE Type,\r
+ IN CONST BOOLEAN TurnOn\r
+ );\r
+\r
+#endif // #ifndef __PLATFORM_HELPER_LIB_H__\r
--- /dev/null
+/** @file\r
+PlatformPcieHelperLib function prototype definitions.\r
+\r
+Copyright (c) 2013-2015 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#ifndef __PLATFORM_PCIE_HELPER_LIB_H__\r
+#define __PLATFORM_PCIE_HELPER_LIB_H__\r
+\r
+#include "Platform.h"\r
+\r
+//\r
+// Function prototypes for routines exported by this library.\r
+//\r
+\r
+/**\r
+ Platform assert PCI express PERST# signal.\r
+\r
+ @param PlatformType See EFI_PLATFORM_TYPE enum definitions.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+PlatformPERSTAssert (\r
+ IN CONST EFI_PLATFORM_TYPE PlatformType\r
+ );\r
+\r
+/**\r
+ Platform de assert PCI express PERST# signal.\r
+\r
+ @param PlatformType See EFI_PLATFORM_TYPE enum definitions.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+PlatformPERSTDeAssert (\r
+ IN CONST EFI_PLATFORM_TYPE PlatformType\r
+ );\r
+\r
+/** Early initialisation of the PCIe controller.\r
+\r
+ @param PlatformType See EFI_PLATFORM_TYPE enum definitions.\r
+\r
+ @retval EFI_SUCCESS Operation success.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+PlatformPciExpressEarlyInit (\r
+ IN CONST EFI_PLATFORM_TYPE PlatformType\r
+ );\r
+\r
+#endif // #ifndef __PLATFORM_PCIE_HELPER_LIB_H__\r
--- /dev/null
+/** @file\r
+This library includes the recovery function that can be customized by OEM,\r
+including how to select the recovery capsule if more than one capsule found,\r
+and security check.\r
+\r
+Copyright (c) 2013-2015 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#ifndef __RECOVERY_OEM_HOOK_LIB_H__\r
+#define __RECOVERY_OEM_HOOK_LIB_H__\r
+\r
+/**\r
+ This function allows the user to force a system recovery\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+OemInitiateRecovery (\r
+ VOID\r
+ );\r
+\r
+/**\r
+ This function allows the user to force a system recovery and deadloop.\r
+\r
+ Deadloop required since system should not execute beyond this point.\r
+ Deadloop should never happen since OemInitiateRecovery () called within\r
+ this routine should never return since it executes a Warm Reset.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+OemInitiateRecoveryAndWait (\r
+ VOID\r
+ );\r
+\r
+#endif\r
--- /dev/null
+/** @file\r
+Definition for Pcal9555 I2c IO Expander.\r
+\r
+Copyright (c) 2013-2015 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+**/\r
+\r
+#ifndef __PCAL9555_H__\r
+#define __PCAL9555_H__\r
+\r
+#define PCAL9555_REG_IN_PORT0 0x00\r
+#define PCAL9555_REG_IN_PORT1 0x01\r
+#define PCAL9555_REG_OUT_PORT0 0x02\r
+#define PCAL9555_REG_OUT_PORT1 0x03\r
+#define PCAL9555_REG_CFG_PORT0 0x06\r
+#define PCAL9555_REG_CFG_PORT1 0x07\r
+\r
+#define PCAL9555_REG_PULL_EN_PORT0 0x46\r
+#define PCAL9555_REG_PULL_EN_PORT1 0x47\r
+\r
+#endif\r
--- /dev/null
+/** @file\r
+Quark platform specific information.\r
+\r
+Copyright (c) 2013 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+**/\r
+#include "Uefi.h"\r
+\r
+#ifndef __PLATFORM_H__\r
+#define __PLATFORM_H__\r
+\r
+//\r
+// Constant definition\r
+//\r
+#define MAX_SMRAM_RANGES 4\r
+#define MAX_NODE 1\r
+\r
+#define QUARK_STAGE1_IMAGE_TYPE_MASK 0xF0\r
+#define QUARK_STAGE1_BOOT_IMAGE_TYPE 0x00 // Stage1 Boot images 0x00 -> 0x0F.\r
+#define QUARK_STAGE1_RECOVERY_IMAGE_TYPE 0x10 // Stage1 Recovery images 0x10 -> 0x1F.\r
+\r
+#define QUARK_BOOTROM_BASE_ADDRESS 0xFFFE0000 // Base address of Quark ROM in memory map.\r
+#define QUARK_BOOTROM_SIZE_BYTES 0x20000 // Quark ROM is 128KB.\r
+#define SMM_DEFAULT_SMBASE 0x30000 // Default SMBASE address.\r
+#define SMM_DEFAULT_SMBASE_SIZE_BYTES 0x10000 // Size in bytes of default SMRAM.\r
+\r
+//\r
+// Gpio to be used to assert / deassert PCI express PERST# signal.\r
+//\r
+#define PCIEXP_PERST_RESUMEWELL_GPIO 3\r
+\r
+//\r
+// Minimum time in microseconds for assertion of PERST# signal.\r
+//\r
+#define PCIEXP_PERST_MIN_ASSERT_US 100\r
+\r
+//\r
+// Microsecond delay post issueing common lane reset.\r
+//\r
+#define PCIEXP_DELAY_US_POST_CMNRESET_RESET 1\r
+\r
+//\r
+// Microsecond delay to wait for PLL to lock.\r
+//\r
+#define PCIEXP_DELAY_US_WAIT_PLL_LOCK 80\r
+\r
+//\r
+// Microsecond delay post issueing sideband interface reset.\r
+//\r
+#define PCIEXP_DELAY_US_POST_SBI_RESET 20\r
+\r
+//\r
+// Microsecond delay post deasserting PERST#.\r
+//\r
+#define PCIEXP_DELAY_US_POST_PERST_DEASSERT 10\r
+\r
+//\r
+// Catastrophic Trip point in degrees Celsius for this platform.\r
+//\r
+#define PLATFORM_CATASTROPHIC_TRIP_CELSIUS 105\r
+\r
+//\r
+// Platform flash update LED common definitions.\r
+//\r
+#define PLATFORM_FLASH_UPDATE_LED_TOGGLE_COUNT 7\r
+#define PLATFORM_FLASH_UPDATE_LED_TOGGLE_DELTA (1000 * 1000) // In Microseconds for EFI_STALL.\r
+\r
+//\r
+// This structure stores the base and size of the ACPI reserved memory used when\r
+// resuming from S3. This region must be allocated by the platform code.\r
+//\r
+typedef struct {\r
+ UINT32 AcpiReservedMemoryBase;\r
+ UINT32 AcpiReservedMemorySize;\r
+ UINT32 SystemMemoryLength;\r
+} RESERVED_ACPI_S3_RANGE;\r
+\r
+#define RESERVED_ACPI_S3_RANGE_OFFSET (EFI_PAGE_SIZE - sizeof (RESERVED_ACPI_S3_RANGE))\r
+\r
+//\r
+// Define valid platform types.\r
+// First add value before TypePlatformMax in EFI_PLATFORM_TYPE definition\r
+// and then add string description to end of EFI_PLATFORM_TYPE_NAME_TABLE_DEFINITION.\r
+// Value shown for supported platforms to help sanity checking with build tools\r
+// and ACPI method usage.\r
+//\r
+typedef enum {\r
+ TypeUnknown = 0, // !!! SHOULD BE THE FIRST ENTRY !!!\r
+ QuarkEmulation = 1,\r
+ ClantonPeakSVP = 2,\r
+ KipsBay = 3,\r
+ CrossHill = 4,\r
+ ClantonHill = 5,\r
+ Galileo = 6,\r
+ TypePlatformRsv7 = 7,\r
+ GalileoGen2 = 8,\r
+ TypePlatformMax // !!! SHOULD BE THE LAST ENTRY !!!\r
+} EFI_PLATFORM_TYPE;\r
+\r
+#define EFI_PLATFORM_TYPE_NAME_TABLE_DEFINITION \\r
+ L"TypeUnknown",\\r
+ L"QuarkEmulation",\\r
+ L"ClantonPeakSVP",\\r
+ L"KipsBay",\\r
+ L"CrossHill",\\r
+ L"ClantonHill",\\r
+ L"Galileo",\\r
+ L"TypePlatformRsv7",\\r
+ L"GalileoGen2",\\r
+\r
+typedef struct {\r
+ UINT32 EntryOffset;\r
+ UINT8 ImageIndex;\r
+} QUARK_EDKII_STAGE1_HEADER;\r
+\r
+#endif\r
--- /dev/null
+/** @file\r
+Board config definitions for each of the boards supported by this platform\r
+package.\r
+\r
+Copyright (c) 2013 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+**/\r
+#include "Platform.h"\r
+\r
+#ifndef __PLATFORM_BOARDS_H__\r
+#define __PLATFORM_BOARDS_H__\r
+\r
+//\r
+// Constant definition\r
+//\r
+\r
+//\r
+// Default resume well TPM reset.\r
+//\r
+#define PLATFORM_RESUMEWELL_TPM_RST_GPIO 5\r
+\r
+//\r
+// Basic Configs for GPIO table definitions.\r
+//\r
+#define NULL_LEGACY_GPIO_INITIALIZER {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00}\r
+#define ALL_INPUT_LEGACY_GPIO_INITIALIZER {0x03,0x03,0x00,0x00,0x00,0x00,0x00,0x03,0x00,0x3f,0x3f,0x00,0x00,0x00,0x00,0x00,0x3f,0x00}\r
+#define QUARK_EMULATION_LEGACY_GPIO_INITIALIZER ALL_INPUT_LEGACY_GPIO_INITIALIZER\r
+#define CLANTON_PEAK_SVP_LEGACY_GPIO_INITIALIZER {0x03,0x03,0x00,0x00,0x00,0x00,0x00,0x03,0x00,0x3f,0x3f,0x00,0x00,0x3f,0x3f,0x00,0x3f,0x00}\r
+#define KIPS_BAY_LEGACY_GPIO_INITIALIZER {0x03,0x03,0x00,0x00,0x00,0x00,0x00,0x03,0x00,0x3f,0x25,0x10,0x00,0x00,0x00,0x00,0x3f,0x00}\r
+#define CROSS_HILL_LEGACY_GPIO_INITIALIZER {0x03,0x03,0x00,0x00,0x00,0x00,0x00,0x03,0x00,0x3f,0x03,0x10,0x00,0x03,0x03,0x00,0x3f,0x00}\r
+#define CLANTON_HILL_LEGACY_GPIO_INITIALIZER {0x03,0x03,0x00,0x00,0x00,0x00,0x00,0x03,0x00,0x3f,0x06,0x10,0x00,0x04,0x04,0x00,0x3f,0x00}\r
+#define GALILEO_LEGACY_GPIO_INITIALIZER {0x03,0x00,0x00,0x00,0x00,0x00,0x00,0x03,0x00,0x3f,0x21,0x14,0x00,0x00,0x00,0x00,0x3f,0x00}\r
+#define GALILEO_GEN2_LEGACY_GPIO_INITIALIZER {0x03,0x03,0x00,0x00,0x00,0x00,0x00,0x03,0x00,0x3f,0x1c,0x02,0x00,0x00,0x00,0x00,0x3f,0x00}\r
+\r
+#define NULL_GPIO_CONTROLLER_INITIALIZER {0,0,0,0,0,0,0,0}\r
+#define ALL_INPUT_GPIO_CONTROLLER_INITIALIZER NULL_GPIO_CONTROLLER_INITIALIZER\r
+#define QUARK_EMULATION_GPIO_CONTROLLER_INITIALIZER NULL_GPIO_CONTROLLER_INITIALIZER\r
+#define CLANTON_PEAK_SVP_GPIO_CONTROLLER_INITIALIZER NULL_GPIO_CONTROLLER_INITIALIZER\r
+#define KIPS_BAY_GPIO_CONTROLLER_INITIALIZER {0x05,0x05,0,0,0,0,0,0}\r
+#define CROSS_HILL_GPIO_CONTROLLER_INITIALIZER {0x0D,0x2D,0,0,0,0,0,0}\r
+#define CLANTON_HILL_GPIO_CONTROLLER_INITIALIZER {0x01,0x39,0,0,0,0,0,0}\r
+#define GALILEO_GPIO_CONTROLLER_INITIALIZER {0x05,0x15,0,0,0,0,0,0}\r
+#define GALILEO_GEN2_GPIO_CONTROLLER_INITIALIZER {0x05,0x05,0,0,0,0,0,0}\r
+\r
+//\r
+// Legacy Gpio to be used to assert / deassert PCI express PERST# signal\r
+// on Galileo Gen 2 platform.\r
+//\r
+#define GALILEO_GEN2_PCIEXP_PERST_RESUMEWELL_GPIO 0\r
+\r
+//\r
+// Io expander slave address.\r
+//\r
+\r
+//\r
+// On Galileo value of Jumper J2 determines slave address of io expander.\r
+//\r
+#define GALILEO_DETERMINE_IOEXP_SLA_RESUMEWELL_GPIO 5\r
+#define GALILEO_IOEXP_J2HI_7BIT_SLAVE_ADDR 0x20\r
+#define GALILEO_IOEXP_J2LO_7BIT_SLAVE_ADDR 0x21\r
+\r
+//\r
+// Three IO Expmanders at fixed addresses on Galileo Gen2.\r
+//\r
+#define GALILEO_GEN2_IOEXP0_7BIT_SLAVE_ADDR 0x25\r
+#define GALILEO_GEN2_IOEXP1_7BIT_SLAVE_ADDR 0x26\r
+#define GALILEO_GEN2_IOEXP2_7BIT_SLAVE_ADDR 0x27\r
+\r
+//\r
+// Led GPIOs for flash update / recovery.\r
+//\r
+#define GALILEO_FLASH_UPDATE_LED_RESUMEWELL_GPIO 1\r
+#define GALILEO_GEN2_FLASH_UPDATE_LED_RESUMEWELL_GPIO 5\r
+\r
+//\r
+// Legacy GPIO config struct for each element in PLATFORM_LEGACY_GPIO_TABLE_DEFINITION.\r
+//\r
+typedef struct {\r
+ UINT32 CoreWellEnable; ///< Value for QNC NC Reg R_QNC_GPIO_CGEN_CORE_WELL.\r
+ UINT32 CoreWellIoSelect; ///< Value for QNC NC Reg R_QNC_GPIO_CGIO_CORE_WELL.\r
+ UINT32 CoreWellLvlForInputOrOutput; ///< Value for QNC NC Reg R_QNC_GPIO_CGLVL_CORE_WELL.\r
+ UINT32 CoreWellTriggerPositiveEdge; ///< Value for QNC NC Reg R_QNC_GPIO_CGTPE_CORE_WELL.\r
+ UINT32 CoreWellTriggerNegativeEdge; ///< Value for QNC NC Reg R_QNC_GPIO_CGTNE_CORE_WELL.\r
+ UINT32 CoreWellGPEEnable; ///< Value for QNC NC Reg R_QNC_GPIO_CGGPE_CORE_WELL.\r
+ UINT32 CoreWellSMIEnable; ///< Value for QNC NC Reg R_QNC_GPIO_CGSMI_CORE_WELL.\r
+ UINT32 CoreWellTriggerStatus; ///< Value for QNC NC Reg R_QNC_GPIO_CGTS_CORE_WELL.\r
+ UINT32 CoreWellNMIEnable; ///< Value for QNC NC Reg R_QNC_GPIO_CGNMIEN_CORE_WELL.\r
+ UINT32 ResumeWellEnable; ///< Value for QNC NC Reg R_QNC_GPIO_RGEN_RESUME_WELL.\r
+ UINT32 ResumeWellIoSelect; ///< Value for QNC NC Reg R_QNC_GPIO_RGIO_RESUME_WELL.\r
+ UINT32 ResumeWellLvlForInputOrOutput;///< Value for QNC NC Reg R_QNC_GPIO_RGLVL_RESUME_WELL.\r
+ UINT32 ResumeWellTriggerPositiveEdge;///< Value for QNC NC Reg R_QNC_GPIO_RGTPE_RESUME_WELL.\r
+ UINT32 ResumeWellTriggerNegativeEdge;///< Value for QNC NC Reg R_QNC_GPIO_RGTNE_RESUME_WELL.\r
+ UINT32 ResumeWellGPEEnable; ///< Value for QNC NC Reg R_QNC_GPIO_RGGPE_RESUME_WELL.\r
+ UINT32 ResumeWellSMIEnable; ///< Value for QNC NC Reg R_QNC_GPIO_RGSMI_RESUME_WELL.\r
+ UINT32 ResumeWellTriggerStatus; ///< Value for QNC NC Reg R_QNC_GPIO_RGTS_RESUME_WELL.\r
+ UINT32 ResumeWellNMIEnable; ///< Value for QNC NC Reg R_QNC_GPIO_RGNMIEN_RESUME_WELL.\r
+} BOARD_LEGACY_GPIO_CONFIG;\r
+\r
+//\r
+// GPIO controller config struct for each element in PLATFORM_GPIO_CONTROLLER_CONFIG_DEFINITION.\r
+//\r
+typedef struct {\r
+ UINT32 PortADR; ///< Value for IOH REG GPIO_SWPORTA_DR.\r
+ UINT32 PortADir; ///< Value for IOH REG GPIO_SWPORTA_DDR.\r
+ UINT32 IntEn; ///< Value for IOH REG GPIO_INTEN.\r
+ UINT32 IntMask; ///< Value for IOH REG GPIO_INTMASK.\r
+ UINT32 IntType; ///< Value for IOH REG GPIO_INTTYPE_LEVEL.\r
+ UINT32 IntPolarity; ///< Value for IOH REG GPIO_INT_POLARITY.\r
+ UINT32 Debounce; ///< Value for IOH REG GPIO_DEBOUNCE.\r
+ UINT32 LsSync; ///< Value for IOH REG GPIO_LS_SYNC.\r
+} BOARD_GPIO_CONTROLLER_CONFIG;\r
+\r
+///\r
+/// Table of BOARD_LEGACY_GPIO_CONFIG structures for each board supported\r
+/// by this platform package.\r
+/// Table indexed with EFI_PLATFORM_TYPE enum value.\r
+///\r
+#define PLATFORM_LEGACY_GPIO_TABLE_DEFINITION \\r
+ /* EFI_PLATFORM_TYPE - TypeUnknown*/\\r
+ NULL_LEGACY_GPIO_INITIALIZER,\\r
+ /* EFI_PLATFORM_TYPE - QuarkEmulation*/\\r
+ QUARK_EMULATION_LEGACY_GPIO_INITIALIZER,\\r
+ /* EFI_PLATFORM_TYPE - ClantonPeakSVP*/\\r
+ CLANTON_PEAK_SVP_LEGACY_GPIO_INITIALIZER,\\r
+ /* EFI_PLATFORM_TYPE - KipsBay*/\\r
+ KIPS_BAY_LEGACY_GPIO_INITIALIZER,\\r
+ /* EFI_PLATFORM_TYPE - CrossHill*/\\r
+ CROSS_HILL_LEGACY_GPIO_INITIALIZER,\\r
+ /* EFI_PLATFORM_TYPE - ClantonHill*/\\r
+ CLANTON_HILL_LEGACY_GPIO_INITIALIZER,\\r
+ /* EFI_PLATFORM_TYPE - Galileo*/\\r
+ GALILEO_LEGACY_GPIO_INITIALIZER,\\r
+ /* EFI_PLATFORM_TYPE - TypePlatformRsv7*/\\r
+ NULL_LEGACY_GPIO_INITIALIZER,\\r
+ /* EFI_PLATFORM_TYPE - GalileoGen2*/\\r
+ GALILEO_GEN2_LEGACY_GPIO_INITIALIZER,\\r
+\r
+///\r
+/// Table of BOARD_GPIO_CONTROLLER_CONFIG structures for each board\r
+/// supported by this platform package.\r
+/// Table indexed with EFI_PLATFORM_TYPE enum value.\r
+///\r
+#define PLATFORM_GPIO_CONTROLLER_CONFIG_DEFINITION \\r
+ /* EFI_PLATFORM_TYPE - TypeUnknown*/\\r
+ NULL_GPIO_CONTROLLER_INITIALIZER,\\r
+ /* EFI_PLATFORM_TYPE - QuarkEmulation*/\\r
+ QUARK_EMULATION_GPIO_CONTROLLER_INITIALIZER,\\r
+ /* EFI_PLATFORM_TYPE - ClantonPeakSVP*/\\r
+ CLANTON_PEAK_SVP_GPIO_CONTROLLER_INITIALIZER,\\r
+ /* EFI_PLATFORM_TYPE - KipsBay*/\\r
+ KIPS_BAY_GPIO_CONTROLLER_INITIALIZER,\\r
+ /* EFI_PLATFORM_TYPE - CrossHill*/\\r
+ CROSS_HILL_GPIO_CONTROLLER_INITIALIZER,\\r
+ /* EFI_PLATFORM_TYPE - ClantonHill*/\\r
+ CLANTON_HILL_GPIO_CONTROLLER_INITIALIZER,\\r
+ /* EFI_PLATFORM_TYPE - Galileo*/\\r
+ GALILEO_GPIO_CONTROLLER_INITIALIZER,\\r
+ /* EFI_PLATFORM_TYPE - TypePlatformRsv7 */\\r
+ NULL_GPIO_CONTROLLER_INITIALIZER,\\r
+ /* EFI_PLATFORM_TYPE - GalileoGen2*/\\r
+ GALILEO_GEN2_GPIO_CONTROLLER_INITIALIZER,\\r
+\r
+#endif\r
--- /dev/null
+/** @file\r
+Definition of the global NVS area protocol. This protocol\r
+publishes the address and format of a global ACPI NVS buffer\r
+used as a communications buffer between SMM code and ASL code.\r
+The format is derived from the ACPI reference code, version 0.95.\r
+Note: Data structures defined in this protocol are not naturally aligned.\r
+\r
+Copyright (c) 2013-2015 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#ifndef _GLOBAL_NVS_AREA_H_\r
+#define _GLOBAL_NVS_AREA_H_\r
+\r
+//\r
+// Forward reference for pure ANSI compatability\r
+//\r
+\r
+typedef struct _EFI_GLOBAL_NVS_AREA_PROTOCOL EFI_GLOBAL_NVS_AREA_PROTOCOL;\r
+\r
+//\r
+// Global NVS Area Protocol GUID\r
+//\r
+#define EFI_GLOBAL_NVS_AREA_PROTOCOL_GUID \\r
+{ 0x74e1e48, 0x8132, 0x47a1, {0x8c, 0x2c, 0x3f, 0x14, 0xad, 0x9a, 0x66, 0xdc} }\r
+\r
+\r
+//\r
+// Global NVS Area definition\r
+//\r
+#pragma pack (1)\r
+typedef struct {\r
+ //\r
+ // Miscellaneous Dynamic Values\r
+ //\r
+ UINT32 OperatingSystemType; // Os type indicator\r
+ UINT32 Cfgd; // System configuration description\r
+ UINT32 HpetEnable;\r
+\r
+ UINT32 Pm1blkIoBaseAddress;\r
+ UINT32 PmbaIoBaseAddress;\r
+ UINT32 Gpe0blkIoBaseAddress;\r
+ UINT32 GbaIoBaseAddress;\r
+\r
+ UINT32 SmbaIoBaseAddress;\r
+ UINT32 Reserved1;\r
+ UINT32 WdtbaIoBaseAddress;\r
+\r
+ UINT32 HpetBaseAddress;\r
+ UINT32 HpetSize;\r
+ UINT32 PciExpressBaseAddress;\r
+ UINT32 PciExpressSize;\r
+\r
+ UINT32 RcbaMmioBaseAddress;\r
+ UINT32 RcbaMmioSize;\r
+ UINT32 IoApicBaseAddress;\r
+ UINT32 IoApicSize;\r
+\r
+ UINT32 TpmPresent;\r
+ UINT32 DBG2Present;\r
+ UINT32 PlatformType; // Set to one of EFI_PLATFORM_TYPE enums.\r
+ UINT32 AlternateSla; // If TRUE use alternate I2C Slave addresses.\r
+\r
+ UINT8 Reserved[512 - 4 * 22]; // Total 512 Bytes\r
+} EFI_GLOBAL_NVS_AREA;\r
+#pragma pack ()\r
+\r
+//\r
+// Global NVS Area Protocol\r
+//\r
+struct _EFI_GLOBAL_NVS_AREA_PROTOCOL {\r
+ EFI_GLOBAL_NVS_AREA *Area;\r
+};\r
+\r
+//\r
+// Extern the GUID for protocol users.\r
+//\r
+extern EFI_GUID gEfiGlobalNvsAreaProtocolGuid;\r
+\r
+#endif\r
--- /dev/null
+/** @file\r
+This protocol indicates that the platform SPI interface is ready for use.\r
+\r
+Copyright (c) 2013-2015 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+**/\r
+\r
+#ifndef _PLATFORM_SPI_READY_H_\r
+#define _PLATFORM_SPI_READY_H_\r
+\r
+// {7A5DBC75-5B2B-4e67-BDE1-D48EEE761562}\r
+#define EFI_SMM_SPI_READY_PROTOCOL_GUID \\r
+ { 0x7a5dbc75, 0x5b2b, 0x4e67, 0xbd, 0xe1, 0xd4, 0x8e, 0xee, 0x76, 0x15, 0x62 }\r
+\r
+//\r
+// Extern the GUID for protocol users.\r
+//\r
+extern EFI_GUID gEfiSmmSpiReadyProtocolGuid;\r
+\r
+#endif\r
--- /dev/null
+/** @file\r
+This file include all platform action which can be customized\r
+by IBV/OEM.\r
+\r
+Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#include "PlatformBootManager.h"\r
+\r
+EFI_GUID mUefiShellFileGuid = {0x7C04A583, 0x9E3E, 0x4f1c, {0xAD, 0x65, 0xE0, 0x52, 0x68, 0xD0, 0xB4, 0xD1 }};\r
+\r
+/**\r
+ Return the index of the load option in the load option array.\r
+\r
+ The function consider two load options are equal when the\r
+ OptionType, Attributes, Description, FilePath and OptionalData are equal.\r
+\r
+ @param Key Pointer to the load option to be found.\r
+ @param Array Pointer to the array of load options to be found.\r
+ @param Count Number of entries in the Array.\r
+\r
+ @retval -1 Key wasn't found in the Array.\r
+ @retval 0 ~ Count-1 The index of the Key in the Array.\r
+**/\r
+INTN\r
+PlatformFindLoadOption (\r
+ IN CONST EFI_BOOT_MANAGER_LOAD_OPTION *Key,\r
+ IN CONST EFI_BOOT_MANAGER_LOAD_OPTION *Array,\r
+ IN UINTN Count\r
+ )\r
+{\r
+ UINTN Index;\r
+\r
+ for (Index = 0; Index < Count; Index++) {\r
+ if ((Key->OptionType == Array[Index].OptionType) &&\r
+ (Key->Attributes == Array[Index].Attributes) &&\r
+ (StrCmp (Key->Description, Array[Index].Description) == 0) &&\r
+ (CompareMem (Key->FilePath, Array[Index].FilePath, GetDevicePathSize (Key->FilePath)) == 0) &&\r
+ (Key->OptionalDataSize == Array[Index].OptionalDataSize) &&\r
+ (CompareMem (Key->OptionalData, Array[Index].OptionalData, Key->OptionalDataSize) == 0)) {\r
+ return (INTN) Index;\r
+ }\r
+ }\r
+\r
+ return -1;\r
+}\r
+\r
+VOID\r
+PlatformRegisterFvBootOption (\r
+ EFI_GUID *FileGuid,\r
+ CHAR16 *Description,\r
+ UINT32 Attributes\r
+ )\r
+{\r
+ EFI_STATUS Status;\r
+ EFI_HANDLE *HandleBuffer;\r
+ UINTN HandleCount;\r
+ UINTN IndexFv;\r
+ EFI_FIRMWARE_VOLUME2_PROTOCOL *Fv;\r
+ CHAR16 *UiSection;\r
+ UINTN UiSectionLength;\r
+ UINT32 AuthenticationStatus;\r
+ EFI_HANDLE FvHandle;\r
+ MEDIA_FW_VOL_FILEPATH_DEVICE_PATH FileNode;\r
+ EFI_DEVICE_PATH_PROTOCOL *DevicePath;\r
+ EFI_BOOT_MANAGER_LOAD_OPTION *BootOptions;\r
+ UINTN BootOptionCount;\r
+ UINTN OptionIndex;\r
+ EFI_BOOT_MANAGER_LOAD_OPTION NewOption;\r
+\r
+ //\r
+ // Locate all available FVs.\r
+ //\r
+ HandleBuffer = NULL;\r
+ Status = gBS->LocateHandleBuffer (\r
+ ByProtocol,\r
+ &gEfiFirmwareVolume2ProtocolGuid,\r
+ NULL,\r
+ &HandleCount,\r
+ &HandleBuffer\r
+ );\r
+ if (EFI_ERROR (Status)) {\r
+ return;\r
+ }\r
+\r
+ //\r
+ // Go through FVs one by one to find the required FFS file\r
+ //\r
+ for (IndexFv = 0, FvHandle = NULL; IndexFv < HandleCount && FvHandle == NULL; IndexFv++) {\r
+ Status = gBS->HandleProtocol (\r
+ HandleBuffer[IndexFv],\r
+ &gEfiFirmwareVolume2ProtocolGuid,\r
+ (VOID **)&Fv\r
+ );\r
+ if (EFI_ERROR (Status)) {\r
+ continue;\r
+ }\r
+\r
+ //\r
+ // Attempt to read a EFI_SECTION_USER_INTERFACE section from the required FFS file\r
+ //\r
+ UiSection = NULL;\r
+ Status = Fv->ReadSection (\r
+ Fv,\r
+ FileGuid,\r
+ EFI_SECTION_USER_INTERFACE,\r
+ 0,\r
+ (VOID **) &UiSection,\r
+ &UiSectionLength,\r
+ &AuthenticationStatus\r
+ );\r
+ if (EFI_ERROR (Status)) {\r
+ continue;\r
+ }\r
+ FreePool (UiSection);\r
+\r
+ //\r
+ // Save the handle of the FV where the FFS file was found\r
+ //\r
+ FvHandle = HandleBuffer[IndexFv];\r
+ }\r
+\r
+ //\r
+ // Free the buffer of FV handles\r
+ //\r
+ FreePool (HandleBuffer);\r
+\r
+ //\r
+ // If the FFS file was not found, then return\r
+ //\r
+ if (FvHandle == NULL) {\r
+ return;\r
+ }\r
+\r
+ //\r
+ // Create a device path for the FFS file that was found\r
+ //\r
+ EfiInitializeFwVolDevicepathNode (&FileNode, FileGuid);\r
+ DevicePath = AppendDevicePathNode (\r
+ DevicePathFromHandle (FvHandle),\r
+ (EFI_DEVICE_PATH_PROTOCOL *) &FileNode\r
+ );\r
+\r
+ //\r
+ // Create and add a new load option for the FFS file that was found\r
+ //\r
+ Status = EfiBootManagerInitializeLoadOption (\r
+ &NewOption,\r
+ LoadOptionNumberUnassigned,\r
+ LoadOptionTypeBoot,\r
+ Attributes,\r
+ Description,\r
+ DevicePath,\r
+ NULL,\r
+ 0\r
+ );\r
+ if (!EFI_ERROR (Status)) {\r
+ BootOptions = EfiBootManagerGetLoadOptions (&BootOptionCount, LoadOptionTypeBoot);\r
+\r
+ OptionIndex = PlatformFindLoadOption (&NewOption, BootOptions, BootOptionCount);\r
+\r
+ if (OptionIndex == -1) {\r
+ Status = EfiBootManagerAddLoadOptionVariable (&NewOption, (UINTN) -1);\r
+ ASSERT_EFI_ERROR (Status);\r
+ }\r
+ EfiBootManagerFreeLoadOption (&NewOption);\r
+ EfiBootManagerFreeLoadOptions (BootOptions, BootOptionCount);\r
+ }\r
+}\r
+\r
+VOID\r
+EFIAPI\r
+InternalBdsEmptyCallbackFuntion (\r
+ IN EFI_EVENT Event,\r
+ IN VOID *Context\r
+ )\r
+{\r
+ return;\r
+}\r
+\r
+/**\r
+ Do the platform specific action before the console is connected.\r
+\r
+ Such as:\r
+ Update console variable;\r
+ Register new Driver#### or Boot####;\r
+ Signal ReadyToLock event.\r
+**/\r
+VOID\r
+EFIAPI\r
+PlatformBootManagerBeforeConsole (\r
+ VOID\r
+ )\r
+{\r
+ EFI_STATUS Status;\r
+ UINTN Index;\r
+ EFI_INPUT_KEY Enter;\r
+ EFI_INPUT_KEY F2;\r
+ EFI_BOOT_MANAGER_LOAD_OPTION BootOption;\r
+ EFI_ACPI_S3_SAVE_PROTOCOL *AcpiS3Save;\r
+ EFI_HANDLE Handle;\r
+ EFI_EVENT EndOfDxeEvent;\r
+\r
+ //\r
+ // Update the console variables.\r
+ //\r
+ for (Index = 0; gPlatformConsole[Index].DevicePath != NULL; Index++) {\r
+ if ((gPlatformConsole[Index].ConnectType & CONSOLE_IN) == CONSOLE_IN) {\r
+ EfiBootManagerUpdateConsoleVariable (ConIn, gPlatformConsole[Index].DevicePath, NULL);\r
+ }\r
+\r
+ if ((gPlatformConsole[Index].ConnectType & CONSOLE_OUT) == CONSOLE_OUT) {\r
+ EfiBootManagerUpdateConsoleVariable (ConOut, gPlatformConsole[Index].DevicePath, NULL);\r
+ }\r
+\r
+ if ((gPlatformConsole[Index].ConnectType & STD_ERROR) == STD_ERROR) {\r
+ EfiBootManagerUpdateConsoleVariable (ErrOut, gPlatformConsole[Index].DevicePath, NULL);\r
+ }\r
+ }\r
+\r
+ //\r
+ // Register ENTER as CONTINUE key\r
+ //\r
+ Enter.ScanCode = SCAN_NULL;\r
+ Enter.UnicodeChar = CHAR_CARRIAGE_RETURN;\r
+ EfiBootManagerRegisterContinueKeyOption (0, &Enter, NULL);\r
+\r
+ //\r
+ // Map F2 to Boot Manager Menu\r
+ //\r
+ F2.ScanCode = SCAN_F2;\r
+ F2.UnicodeChar = CHAR_NULL;\r
+ EfiBootManagerGetBootManagerMenu (&BootOption);\r
+ EfiBootManagerAddKeyOptionVariable (NULL, (UINT16) BootOption.OptionNumber, 0, &F2, NULL);\r
+\r
+ //\r
+ // Register UEFI Shell\r
+ //\r
+ PlatformRegisterFvBootOption (&mUefiShellFileGuid, L"UEFI Shell", LOAD_OPTION_ACTIVE);\r
+\r
+ //\r
+ // Prepare for S3\r
+ //\r
+ Status = gBS->LocateProtocol (&gEfiAcpiS3SaveProtocolGuid, NULL, (VOID **)&AcpiS3Save);\r
+ if (!EFI_ERROR (Status)) {\r
+ AcpiS3Save->S3Save (AcpiS3Save, NULL);\r
+ }\r
+\r
+ //\r
+ // Inform PI SMM drivers that BDS may run 3rd party code\r
+ // Create and signal End of DXE event group\r
+ //\r
+ Status = gBS->CreateEventEx (\r
+ EVT_NOTIFY_SIGNAL,\r
+ TPL_CALLBACK,\r
+ InternalBdsEmptyCallbackFuntion,\r
+ NULL,\r
+ &gEfiEndOfDxeEventGroupGuid,\r
+ &EndOfDxeEvent\r
+ );\r
+ ASSERT_EFI_ERROR (Status);\r
+ gBS->SignalEvent (EndOfDxeEvent);\r
+ gBS->CloseEvent (EndOfDxeEvent);\r
+\r
+ DEBUG((EFI_D_INFO,"All EndOfDxe callbacks have returned successfully\n"));\r
+\r
+ //\r
+ // Install SMM Ready To Lock protocol so all resources can be locked down\r
+ // before BDS runs 3rd party code. This action must be done last so all\r
+ // other SMM driver signals are processed before this final lock down action.\r
+ //\r
+ Handle = NULL;\r
+ Status = gBS->InstallProtocolInterface (\r
+ &Handle,\r
+ &gEfiDxeSmmReadyToLockProtocolGuid,\r
+ EFI_NATIVE_INTERFACE,\r
+ NULL\r
+ );\r
+ ASSERT_EFI_ERROR (Status);\r
+}\r
+\r
+/**\r
+ Do the platform specific action after the console is connected.\r
+\r
+ Such as:\r
+ Dynamically switch output mode;\r
+ Signal console ready platform customized event;\r
+ Run diagnostics like memory testing;\r
+ Connect certain devices;\r
+ Dispatch additional option ROMs\r
+**/\r
+VOID\r
+EFIAPI\r
+PlatformBootManagerAfterConsole (\r
+ VOID\r
+ )\r
+{\r
+ EFI_STATUS Status;\r
+\r
+ Print (\r
+ L"\n"\r
+ L"F2 to enter Boot Manager Menu.\n"\r
+ L"ENTER to boot directly.\n"\r
+ L"\n"\r
+ );\r
+\r
+ //\r
+ // Use a DynamicHii type pcd to save the boot status, which is used to\r
+ // control configuration mode, such as FULL/MINIMAL/NO_CHANGES configuration.\r
+ //\r
+ if (PcdGetBool(PcdBootState)) {\r
+ Status = PcdSetBoolS (PcdBootState, FALSE);\r
+ ASSERT_EFI_ERROR (Status);\r
+ }\r
+}\r
+\r
+/**\r
+ This function is called each second during the boot manager waits the timeout.\r
+\r
+ @param TimeoutRemain The remaining timeout.\r
+**/\r
+VOID\r
+EFIAPI\r
+PlatformBootManagerWaitCallback (\r
+ UINT16 TimeoutRemain\r
+ )\r
+{\r
+ Print (L"\r%-2d seconds remained...", TimeoutRemain);\r
+}\r
--- /dev/null
+/** @file\r
+Head file for BDS Platform specific code\r
+\r
+Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+**/\r
+\r
+#ifndef _PLATFORM_BOOT_MANAGER_H\r
+#define _PLATFORM_BOOT_MANAGER_H\r
+\r
+#include <PiDxe.h>\r
+\r
+#include <Library/PlatformBootManagerLib.h>\r
+\r
+#include <Protocol/FirmwareVolume2.h>\r
+#include <Protocol/AcpiS3Save.h>\r
+#include <Protocol/DxeSmmReadyToLock.h>\r
+#include <Guid/DebugAgentGuid.h>\r
+#include <Guid/EventGroup.h>\r
+#include <Guid/PcAnsi.h>\r
+#include <Guid/TtyTerm.h>\r
+#include <Library/BaseLib.h>\r
+#include <Library/BaseMemoryLib.h>\r
+#include <Library/PcdLib.h>\r
+#include <Library/DebugLib.h>\r
+#include <Library/DevicePathLib.h>\r
+#include <Library/MemoryAllocationLib.h>\r
+#include <Library/UefiBootServicesTableLib.h>\r
+#include <Library/UefiLib.h>\r
+#include <Library/UefiBootManagerLib.h>\r
+\r
+\r
+typedef struct {\r
+ EFI_DEVICE_PATH_PROTOCOL *DevicePath;\r
+ UINTN ConnectType;\r
+} PLATFORM_CONSOLE_CONNECT_ENTRY;\r
+\r
+extern PLATFORM_CONSOLE_CONNECT_ENTRY gPlatformConsole[];\r
+\r
+#define CONSOLE_OUT BIT0\r
+#define CONSOLE_IN BIT1\r
+#define STD_ERROR BIT2\r
+\r
+#endif // _PLATFORM_BOOT_MANAGER_H\r
--- /dev/null
+## @file\r
+# Include all platform action which can be customized by IBV/OEM.\r
+#\r
+# Copyright (c) 2012 - 2015, Intel Corporation. All rights reserved.<BR>\r
+# This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution. The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php\r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+##\r
+\r
+[Defines]\r
+ INF_VERSION = 0x00010005\r
+ BASE_NAME = PlatformBootManagerLib\r
+ FILE_GUID = EC67889B-9E62-4c81-8CA0-86E6A6EEE61A\r
+ MODULE_TYPE = DXE_DRIVER\r
+ VERSION_STRING = 1.0\r
+ LIBRARY_CLASS = PlatformBootManagerLib|DXE_DRIVER\r
+ CONSTRUCTOR = InitializePlatformBootManagerLib\r
+\r
+#\r
+# The following information is for reference only and not required by the build tools.\r
+#\r
+# VALID_ARCHITECTURES = IA32 X64 EBC\r
+#\r
+\r
+[Sources]\r
+ PlatformData.c\r
+ PlatformBootManager.c\r
+ PlatformBootManager.h\r
+\r
+[Packages]\r
+ MdePkg/MdePkg.dec\r
+ MdeModulePkg/MdeModulePkg.dec\r
+ IntelFrameworkPkg/IntelFrameworkPkg.dec\r
+ IntelFrameworkModulePkg/IntelFrameworkModulePkg.dec\r
+ SourceLevelDebugPkg/SourceLevelDebugPkg.dec\r
+\r
+[LibraryClasses]\r
+ BaseLib\r
+ BaseMemoryLib\r
+ PcdLib\r
+ DebugLib\r
+ DevicePathLib\r
+ MemoryAllocationLib\r
+ UefiBootServicesTableLib\r
+ UefiLib\r
+ UefiBootManagerLib\r
+\r
+[Protocols]\r
+ gEfiFirmwareVolume2ProtocolGuid\r
+ gEfiAcpiS3SaveProtocolGuid\r
+ gEfiDxeSmmReadyToLockProtocolGuid\r
+\r
+[Guids]\r
+ gEfiPcAnsiGuid\r
+ gEfiVT100Guid\r
+ gEfiVT100PlusGuid\r
+ gEfiVTUTF8Guid\r
+ gEfiTtyTermGuid\r
+ gEfiEndOfDxeEventGroupGuid\r
+\r
+[Pcd]\r
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate\r
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits\r
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity\r
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits\r
+ gEfiMdePkgTokenSpaceGuid.PcdDefaultTerminalType\r
+ gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdBootState\r
--- /dev/null
+/** @file\r
+Defined the platform specific device path which will be filled to\r
+ConIn/ConOut variables.\r
+\r
+Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#include "PlatformBootManager.h"\r
+\r
+///\r
+/// the short form device path for Usb keyboard\r
+///\r
+#define CLASS_HID 3\r
+#define SUBCLASS_BOOT 1\r
+#define PROTOCOL_KEYBOARD 1\r
+\r
+///\r
+/// PcdDefaultTerminalType values\r
+///\r
+#define PCANSITYPE 0\r
+#define VT100TYPE 1\r
+#define VT100PLUSTYPE 2\r
+#define VTUTF8TYPE 3\r
+#define TTYTERMTYPE 4\r
+\r
+//\r
+// Below is the platform console device path\r
+//\r
+typedef struct {\r
+ ACPI_HID_DEVICE_PATH PciRootBridge;\r
+ PCI_DEVICE_PATH PciUart;\r
+ UART_DEVICE_PATH Uart;\r
+ VENDOR_DEVICE_PATH TerminalType;\r
+ EFI_DEVICE_PATH_PROTOCOL End;\r
+} PCI_UART_DEVICE_PATH;\r
+\r
+typedef struct {\r
+ VENDOR_DEVICE_PATH VendorHardware;\r
+ UART_DEVICE_PATH Uart;\r
+ VENDOR_DEVICE_PATH TerminalType;\r
+ EFI_DEVICE_PATH_PROTOCOL End;\r
+} VENDOR_UART_DEVICE_PATH;\r
+\r
+typedef struct {\r
+ USB_CLASS_DEVICE_PATH UsbClass;\r
+ EFI_DEVICE_PATH_PROTOCOL End;\r
+} USB_CLASS_FORMAT_DEVICE_PATH;\r
+\r
+#define PNPID_DEVICE_PATH_NODE(PnpId) \\r
+ { \\r
+ { \\r
+ ACPI_DEVICE_PATH, \\r
+ ACPI_DP, \\r
+ { \\r
+ (UINT8) (sizeof (ACPI_HID_DEVICE_PATH)), \\r
+ (UINT8) ((sizeof (ACPI_HID_DEVICE_PATH)) >> 8) \\r
+ } \\r
+ }, \\r
+ EISA_PNP_ID((PnpId)), \\r
+ 0 \\r
+ }\r
+\r
+#define PCI_DEVICE_PATH_NODE(Func, Dev) \\r
+ { \\r
+ { \\r
+ HARDWARE_DEVICE_PATH, \\r
+ HW_PCI_DP, \\r
+ { \\r
+ (UINT8) (sizeof (PCI_DEVICE_PATH)), \\r
+ (UINT8) ((sizeof (PCI_DEVICE_PATH)) >> 8) \\r
+ }, \\r
+ }, \\r
+ (Func), \\r
+ (Dev) \\r
+ }\r
+\r
+#define gEndEntire \\r
+ { \\r
+ END_DEVICE_PATH_TYPE, \\r
+ END_ENTIRE_DEVICE_PATH_SUBTYPE, \\r
+ { \\r
+ END_DEVICE_PATH_LENGTH, \\r
+ 0 \\r
+ } \\r
+ }\r
+\r
+//\r
+// Platform specific serial device path\r
+//\r
+PCI_UART_DEVICE_PATH gPciUartDevicePath0 = {\r
+ PNPID_DEVICE_PATH_NODE(0x0A03),\r
+ PCI_DEVICE_PATH_NODE(1, 20),\r
+ {\r
+ {\r
+ MESSAGING_DEVICE_PATH,\r
+ MSG_UART_DP,\r
+ {\r
+ (UINT8)(sizeof (UART_DEVICE_PATH)),\r
+ (UINT8)((sizeof (UART_DEVICE_PATH)) >> 8)\r
+ }\r
+ },\r
+ 0, // Reserved\r
+ 921600, // BaudRate\r
+ 8, // DataBits\r
+ 1, // Parity\r
+ 1 // StopBits\r
+ },\r
+ {\r
+ {\r
+ MESSAGING_DEVICE_PATH,\r
+ MSG_VENDOR_DP,\r
+ {\r
+ (UINT8)(sizeof (VENDOR_DEVICE_PATH)),\r
+ (UINT8)((sizeof (VENDOR_DEVICE_PATH)) >> 8)\r
+ },\r
+ },\r
+ DEVICE_PATH_MESSAGING_PC_ANSI\r
+ },\r
+ gEndEntire\r
+};\r
+\r
+PCI_UART_DEVICE_PATH gPciUartDevicePath1 = {\r
+ PNPID_DEVICE_PATH_NODE(0x0A03),\r
+ PCI_DEVICE_PATH_NODE(5, 20),\r
+ {\r
+ {\r
+ MESSAGING_DEVICE_PATH,\r
+ MSG_UART_DP,\r
+ {\r
+ (UINT8)(sizeof (UART_DEVICE_PATH)),\r
+ (UINT8)((sizeof (UART_DEVICE_PATH)) >> 8)\r
+ }\r
+ },\r
+ 0, // Reserved\r
+ 921600, // BaudRate\r
+ 8, // DataBits\r
+ 1, // Parity\r
+ 1 // StopBits\r
+ },\r
+ {\r
+ {\r
+ MESSAGING_DEVICE_PATH,\r
+ MSG_VENDOR_DP,\r
+ {\r
+ (UINT8)(sizeof (VENDOR_DEVICE_PATH)),\r
+ (UINT8)((sizeof (VENDOR_DEVICE_PATH)) >> 8)\r
+ }\r
+ },\r
+ DEVICE_PATH_MESSAGING_PC_ANSI\r
+ },\r
+ gEndEntire\r
+};\r
+\r
+VENDOR_UART_DEVICE_PATH gDebugAgentUartDevicePath = {\r
+ {\r
+ {\r
+ HARDWARE_DEVICE_PATH,\r
+ HW_VENDOR_DP,\r
+ {\r
+ (UINT8) (sizeof (VENDOR_DEVICE_PATH)),\r
+ (UINT8) ((sizeof (VENDOR_DEVICE_PATH)) >> 8)\r
+ }\r
+ },\r
+ EFI_DEBUG_AGENT_GUID,\r
+ },\r
+ {\r
+ {\r
+ MESSAGING_DEVICE_PATH,\r
+ MSG_UART_DP,\r
+ {\r
+ (UINT8) (sizeof (UART_DEVICE_PATH)),\r
+ (UINT8) ((sizeof (UART_DEVICE_PATH)) >> 8)\r
+ }\r
+ },\r
+ 0, // Reserved\r
+ 0, // BaudRate - Default\r
+ 0, // DataBits - Default\r
+ 0, // Parity - Default\r
+ 0, // StopBits - Default\r
+ },\r
+ {\r
+ {\r
+ MESSAGING_DEVICE_PATH,\r
+ MSG_VENDOR_DP,\r
+ {\r
+ (UINT8)(sizeof (VENDOR_DEVICE_PATH)),\r
+ (UINT8)((sizeof (VENDOR_DEVICE_PATH)) >> 8)\r
+ }\r
+ },\r
+ DEVICE_PATH_MESSAGING_PC_ANSI\r
+ },\r
+ gEndEntire\r
+};\r
+\r
+USB_CLASS_FORMAT_DEVICE_PATH gUsbClassKeyboardDevicePath = {\r
+ {\r
+ {\r
+ MESSAGING_DEVICE_PATH,\r
+ MSG_USB_CLASS_DP,\r
+ {\r
+ (UINT8)(sizeof (USB_CLASS_DEVICE_PATH)),\r
+ (UINT8)((sizeof (USB_CLASS_DEVICE_PATH)) >> 8)\r
+ }\r
+ },\r
+ 0xffff, // VendorId - Match any vendor\r
+ 0xffff, // ProductId - Match any product\r
+ CLASS_HID, // DeviceClass\r
+ SUBCLASS_BOOT, // DeviceSubClass\r
+ PROTOCOL_KEYBOARD // DeviceProtocol\r
+ },\r
+ gEndEntire\r
+};\r
+\r
+//\r
+// Predefined platform default console device path\r
+//\r
+PLATFORM_CONSOLE_CONNECT_ENTRY gPlatformConsole[] = {\r
+ { (EFI_DEVICE_PATH_PROTOCOL *) &gPciUartDevicePath0, (CONSOLE_OUT | CONSOLE_IN) },\r
+ { (EFI_DEVICE_PATH_PROTOCOL *) &gPciUartDevicePath1, (CONSOLE_OUT | CONSOLE_IN) },\r
+ { (EFI_DEVICE_PATH_PROTOCOL *) &gDebugAgentUartDevicePath, (CONSOLE_OUT | CONSOLE_IN) },\r
+ { (EFI_DEVICE_PATH_PROTOCOL *) &gUsbClassKeyboardDevicePath, (CONSOLE_IN) },\r
+ { NULL, 0 }\r
+};\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+InitializePlatformBootManagerLib (\r
+ IN EFI_HANDLE ImageHandle,\r
+ IN EFI_SYSTEM_TABLE *SystemTable\r
+ )\r
+{\r
+ EFI_GUID *TerminalTypeGuid;\r
+\r
+ //\r
+ // Update UART device path nodes based on UART PCD settings\r
+ //\r
+ gPciUartDevicePath0.Uart.BaudRate = PcdGet64 (PcdUartDefaultBaudRate);\r
+ gPciUartDevicePath0.Uart.DataBits = PcdGet8 (PcdUartDefaultDataBits);\r
+ gPciUartDevicePath0.Uart.Parity = PcdGet8 (PcdUartDefaultParity);\r
+ gPciUartDevicePath0.Uart.StopBits = PcdGet8 (PcdUartDefaultStopBits);\r
+ gPciUartDevicePath1.Uart.BaudRate = PcdGet64 (PcdUartDefaultBaudRate);\r
+ gPciUartDevicePath1.Uart.DataBits = PcdGet8 (PcdUartDefaultDataBits);\r
+ gPciUartDevicePath1.Uart.Parity = PcdGet8 (PcdUartDefaultParity);\r
+ gPciUartDevicePath1.Uart.StopBits = PcdGet8 (PcdUartDefaultStopBits);\r
+\r
+ //\r
+ // Update Vendor device path nodes based on terminal type PCD settings\r
+ //\r
+ switch (PcdGet8 (PcdDefaultTerminalType)) {\r
+ case PCANSITYPE:\r
+ TerminalTypeGuid = &gEfiPcAnsiGuid;\r
+ break;\r
+ case VT100TYPE:\r
+ TerminalTypeGuid = &gEfiVT100Guid;\r
+ break;\r
+ case VT100PLUSTYPE:\r
+ TerminalTypeGuid = &gEfiVT100PlusGuid;\r
+ break;\r
+ case VTUTF8TYPE:\r
+ TerminalTypeGuid = &gEfiVTUTF8Guid;\r
+ break;\r
+ case TTYTERMTYPE:\r
+ TerminalTypeGuid = &gEfiTtyTermGuid;\r
+ break;\r
+ default:\r
+ TerminalTypeGuid = &gEfiPcAnsiGuid;\r
+ break;\r
+ }\r
+ CopyGuid (&gPciUartDevicePath0.TerminalType.Guid, TerminalTypeGuid);\r
+ CopyGuid (&gPciUartDevicePath1.TerminalType.Guid, TerminalTypeGuid);\r
+\r
+ return EFI_SUCCESS;\r
+}\r
--- /dev/null
+/** @file\r
+Common header file shared by all source files in this component.\r
+\r
+Copyright (c) 2013-2015 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+**/\r
+\r
+#ifndef __COMMON_HEADER_H_\r
+#define __COMMON_HEADER_H_\r
+\r
+#include <Uefi.h>\r
+#include <Library/DebugLib.h>\r
+#include <Library/BaseLib.h>\r
+#include <Library/SerialPortLib.h>\r
+#include <Library/IoLib.h>\r
+#include <Library/HobLib.h>\r
+#include <Library/BaseMemoryLib.h>\r
+#include <Library/CapsuleLib.h>\r
+#include <Library/IntelQNCLib.h>\r
+#include <Platform.h>\r
+#include <PlatformBoards.h>\r
+#include <Pcal9555.h>\r
+#include <QNCAccess.h>\r
+#include <Library/QNCAccessLib.h>\r
+#include <IohAccess.h>\r
+\r
+#include <Library/PlatformHelperLib.h>\r
+\r
+//\r
+// Routines shared between souce modules in this component.\r
+//\r
+\r
+EFI_STATUS\r
+WriteFirstFreeSpiProtect (\r
+ IN CONST UINT32 PchRootComplexBar,\r
+ IN CONST UINT32 DirectValue,\r
+ IN CONST UINT32 BaseAddress,\r
+ IN CONST UINT32 Length,\r
+ OUT UINT32 *OffsetPtr\r
+ );\r
+\r
+VOID\r
+Pcal9555SetPortRegBit (\r
+ IN CONST UINT32 Pcal9555SlaveAddr,\r
+ IN CONST UINT32 GpioNum,\r
+ IN CONST UINT8 RegBase,\r
+ IN CONST BOOLEAN LogicOne\r
+ );\r
+\r
+#endif\r
--- /dev/null
+## @file\r
+# Library producing helper routines for this platform.\r
+#\r
+# Copyright (c) 2013 Intel Corporation.\r
+#\r
+# This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution. The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php\r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+##\r
+\r
+[Defines]\r
+ INF_VERSION = 0x00010005\r
+ BASE_NAME = DxePlatformHelperLib\r
+ FILE_GUID = 02805010-2591-4ed3-827B-A218F34AE0D7\r
+ MODULE_TYPE = DXE_DRIVER\r
+ VERSION_STRING = 1.0\r
+ LIBRARY_CLASS = PlatformHelperLib|DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SAL_DRIVER SMM_CORE DXE_SMM_DRIVER UEFI_APPLICATION UEFI_DRIVER\r
+\r
+#\r
+# The following information is for reference only and not required by the build tools.\r
+#\r
+# VALID_ARCHITECTURES = IA32\r
+#\r
+\r
+[Sources]\r
+ PlatformHelperLib.c\r
+ PlatformHelperDxe.c\r
+ PlatformLeds.c\r
+\r
+[Packages]\r
+ MdePkg/MdePkg.dec\r
+ MdeModulePkg/MdeModulePkg.dec\r
+ QuarkSocPkg/QuarkSocPkg.dec\r
+ QuarkPlatformPkg/QuarkPlatformPkg.dec\r
+\r
+[LibraryClasses]\r
+ BaseLib\r
+ PcdLib\r
+ BaseMemoryLib\r
+ SerialPortLib\r
+ S3BootScriptLib\r
+ UefiBootServicesTableLib\r
+ UefiRuntimeServicesTableLib\r
+ DxeServicesLib\r
+ HobLib\r
+ IntelQNCLib\r
+ I2cLib\r
+\r
+[Protocols]\r
+ gEfiSpiProtocolGuid\r
+ gEfiSmmSpiProtocolGuid\r
+ gEfiSmmBase2ProtocolGuid\r
+ gEdkiiVariableLockProtocolGuid ## CONSUMES\r
+\r
+[Guids]\r
+ gEfiGlobalVariableGuid\r
+ gEfiImageSecurityDatabaseGuid\r
+ gEfiQuarkCapsuleGuid\r
+ gQuarkVariableLockGuid ## CONSUMES\r
+ gEfiMemoryConfigDataGuid ## CONSUMES\r
+\r
+[Pcd]\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize\r
+ gQuarkPlatformTokenSpaceGuid.PcdFlashAreaBaseAddress\r
+ gQuarkPlatformTokenSpaceGuid.PcdFlashFvRecoveryBase\r
+ gQuarkPlatformTokenSpaceGuid.PcdFlashFvRecoverySize\r
+ gQuarkPlatformTokenSpaceGuid.PcdPkX509File\r
+ gQuarkPlatformTokenSpaceGuid.PcdKekX509File\r
+ gQuarkPlatformTokenSpaceGuid.PcdKekRsa2048File\r
+ gQuarkPlatformTokenSpaceGuid.PcdSpiFlashDeviceSize\r
--- /dev/null
+## @file\r
+# Library producing helper routines for this platform.\r
+#\r
+# Copyright (c) 2013-2015 Intel Corporation.\r
+#\r
+# This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution. The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php\r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+##\r
+\r
+[Defines]\r
+ INF_VERSION = 0x00010005\r
+ BASE_NAME = PeiPlatformHelperLib\r
+ FILE_GUID = 024D3127-7B60-48f4-A6FE-726E19CD4CEB\r
+ MODULE_TYPE = PEIM\r
+ VERSION_STRING = 1.0\r
+ LIBRARY_CLASS = PlatformHelperLib|PEIM PEI_CORE SEC\r
+\r
+#\r
+# The following information is for reference only and not required by the build tools.\r
+#\r
+# VALID_ARCHITECTURES = IA32\r
+#\r
+\r
+[Sources]\r
+ PlatformHelperLib.c\r
+ PlatformHelperPei.c\r
+\r
+[Packages]\r
+ MdePkg/MdePkg.dec\r
+ MdeModulePkg/MdeModulePkg.dec\r
+ QuarkSocPkg/QuarkSocPkg.dec\r
+ QuarkPlatformPkg/QuarkPlatformPkg.dec\r
+\r
+[LibraryClasses]\r
+ BaseLib\r
+ PcdLib\r
+ BaseMemoryLib\r
+ PeiServicesTablePointerLib\r
+ PeiServicesLib\r
+ SerialPortLib\r
+ QNCAccessLib\r
+ I2cLib\r
+\r
+[Pcd]\r
+ gQuarkPlatformTokenSpaceGuid.PcdEsramStage1Base\r
--- /dev/null
+/** @file\r
+Implementation of helper routines for DXE environment.\r
+\r
+Copyright (c) 2013 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#include <PiDxe.h>\r
+\r
+#include <Library/UefiBootServicesTableLib.h>\r
+#include <Library/S3BootScriptLib.h>\r
+#include <Library/DxeServicesLib.h>\r
+#include <Library/UefiRuntimeServicesTableLib.h>\r
+#include <Library/I2cLib.h>\r
+#include <Protocol/SmmBase2.h>\r
+#include <Protocol/Spi.h>\r
+#include <Protocol/VariableLock.h>\r
+\r
+#include <Guid/MemoryConfigData.h>\r
+#include <Guid/QuarkVariableLock.h>\r
+\r
+#include "CommonHeader.h"\r
+\r
+#define FLASH_BLOCK_SIZE SIZE_4KB\r
+\r
+//\r
+// Global variables.\r
+//\r
+EFI_SPI_PROTOCOL *mPlatHelpSpiProtocolRef = NULL;\r
+\r
+//\r
+// Routines defined in other source modules of this component.\r
+//\r
+\r
+//\r
+// Routines local to this component.\r
+//\r
+\r
+//\r
+// Routines shared with other souce modules in this component.\r
+//\r
+\r
+BOOLEAN\r
+Pcal9555GetPortRegBit (\r
+ IN CONST UINT32 Pcal9555SlaveAddr,\r
+ IN CONST UINT32 GpioNum,\r
+ IN CONST UINT8 RegBase\r
+ )\r
+{\r
+ EFI_STATUS Status;\r
+ UINTN ReadLength;\r
+ UINTN WriteLength;\r
+ UINT8 Data[2];\r
+ EFI_I2C_DEVICE_ADDRESS I2cDeviceAddr;\r
+ EFI_I2C_ADDR_MODE I2cAddrMode;\r
+ UINT8 *RegValuePtr;\r
+ UINT8 GpioNumMask;\r
+ UINT8 SubAddr;\r
+\r
+ I2cDeviceAddr.I2CDeviceAddress = (UINTN) Pcal9555SlaveAddr;\r
+ I2cAddrMode = EfiI2CSevenBitAddrMode;\r
+\r
+ if (GpioNum < 8) {\r
+ SubAddr = RegBase;\r
+ GpioNumMask = (UINT8) (1 << GpioNum);\r
+ } else {\r
+ SubAddr = RegBase + 1;\r
+ GpioNumMask = (UINT8) (1 << (GpioNum - 8));\r
+ }\r
+\r
+ //\r
+ // Output port value always at 2nd byte in Data variable.\r
+ //\r
+ RegValuePtr = &Data[1];\r
+\r
+ //\r
+ // On read entry sub address at 2nd byte, on read exit output\r
+ // port value in 2nd byte.\r
+ //\r
+ Data[1] = SubAddr;\r
+ WriteLength = 1;\r
+ ReadLength = 1;\r
+ Status = I2cReadMultipleByte (\r
+ I2cDeviceAddr,\r
+ I2cAddrMode,\r
+ &WriteLength,\r
+ &ReadLength,\r
+ &Data[1]\r
+ );\r
+ ASSERT_EFI_ERROR (Status);\r
+\r
+ //\r
+ // Adjust output port bit given callers request.\r
+ //\r
+ return ((*RegValuePtr & GpioNumMask) != 0);\r
+}\r
+\r
+VOID\r
+Pcal9555SetPortRegBit (\r
+ IN CONST UINT32 Pcal9555SlaveAddr,\r
+ IN CONST UINT32 GpioNum,\r
+ IN CONST UINT8 RegBase,\r
+ IN CONST BOOLEAN LogicOne\r
+ )\r
+{\r
+ EFI_STATUS Status;\r
+ UINTN ReadLength;\r
+ UINTN WriteLength;\r
+ UINT8 Data[2];\r
+ EFI_I2C_DEVICE_ADDRESS I2cDeviceAddr;\r
+ EFI_I2C_ADDR_MODE I2cAddrMode;\r
+ UINT8 *RegValuePtr;\r
+ UINT8 GpioNumMask;\r
+ UINT8 SubAddr;\r
+\r
+ I2cDeviceAddr.I2CDeviceAddress = (UINTN) Pcal9555SlaveAddr;\r
+ I2cAddrMode = EfiI2CSevenBitAddrMode;\r
+\r
+ if (GpioNum < 8) {\r
+ SubAddr = RegBase;\r
+ GpioNumMask = (UINT8) (1 << GpioNum);\r
+ } else {\r
+ SubAddr = RegBase + 1;\r
+ GpioNumMask = (UINT8) (1 << (GpioNum - 8));\r
+ }\r
+\r
+ //\r
+ // Output port value always at 2nd byte in Data variable.\r
+ //\r
+ RegValuePtr = &Data[1];\r
+\r
+ //\r
+ // On read entry sub address at 2nd byte, on read exit output\r
+ // port value in 2nd byte.\r
+ //\r
+ Data[1] = SubAddr;\r
+ WriteLength = 1;\r
+ ReadLength = 1;\r
+ Status = I2cReadMultipleByte (\r
+ I2cDeviceAddr,\r
+ I2cAddrMode,\r
+ &WriteLength,\r
+ &ReadLength,\r
+ &Data[1]\r
+ );\r
+ ASSERT_EFI_ERROR (Status);\r
+\r
+ //\r
+ // Adjust output port bit given callers request.\r
+ //\r
+ if (LogicOne) {\r
+ *RegValuePtr = *RegValuePtr | GpioNumMask;\r
+ } else {\r
+ *RegValuePtr = *RegValuePtr & ~(GpioNumMask);\r
+ }\r
+\r
+ //\r
+ // Update register. Sub address at 1st byte, value at 2nd byte.\r
+ //\r
+ WriteLength = 2;\r
+ Data[0] = SubAddr;\r
+ Status = I2cWriteMultipleByte (\r
+ I2cDeviceAddr,\r
+ I2cAddrMode,\r
+ &WriteLength,\r
+ Data\r
+ );\r
+ ASSERT_EFI_ERROR (Status);\r
+}\r
+\r
+\r
+EFI_SPI_PROTOCOL *\r
+LocateSpiProtocol (\r
+ IN EFI_SMM_SYSTEM_TABLE2 *Smst\r
+ )\r
+{\r
+ if (mPlatHelpSpiProtocolRef == NULL) {\r
+ if (Smst != NULL) {\r
+ Smst->SmmLocateProtocol (\r
+ &gEfiSmmSpiProtocolGuid,\r
+ NULL,\r
+ (VOID **) &mPlatHelpSpiProtocolRef\r
+ );\r
+ } else {\r
+ gBS->LocateProtocol (\r
+ &gEfiSpiProtocolGuid,\r
+ NULL,\r
+ (VOID **) &mPlatHelpSpiProtocolRef\r
+ );\r
+ }\r
+ ASSERT (mPlatHelpSpiProtocolRef != NULL);\r
+ }\r
+ return mPlatHelpSpiProtocolRef;\r
+}\r
+\r
+//\r
+// Routines exported by this source module.\r
+//\r
+\r
+/**\r
+ Find pointer to RAW data in Firmware volume file.\r
+\r
+ @param FvNameGuid Firmware volume to search. If == NULL search all.\r
+ @param FileNameGuid Firmware volume file to search for.\r
+ @param SectionData Pointer to RAW data section of found file.\r
+ @param SectionDataSize Pointer to UNITN to get size of RAW data.\r
+\r
+ @retval EFI_SUCCESS Raw Data found.\r
+ @retval EFI_INVALID_PARAMETER FileNameGuid == NULL.\r
+ @retval EFI_NOT_FOUND Firmware volume file not found.\r
+ @retval EFI_UNSUPPORTED Unsupported in current enviroment (PEI or DXE).\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+PlatformFindFvFileRawDataSection (\r
+ IN CONST EFI_GUID *FvNameGuid OPTIONAL,\r
+ IN CONST EFI_GUID *FileNameGuid,\r
+ OUT VOID **SectionData,\r
+ OUT UINTN *SectionDataSize\r
+ )\r
+{\r
+ if (FileNameGuid == NULL || SectionData == NULL || SectionDataSize == NULL) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+ if (FvNameGuid != NULL) {\r
+ return EFI_UNSUPPORTED; // Searching in specific FV unsupported in DXE.\r
+ }\r
+\r
+ return GetSectionFromAnyFv (FileNameGuid, EFI_SECTION_RAW, 0, SectionData, SectionDataSize);\r
+}\r
+\r
+/**\r
+ Find free spi protect register and write to it to protect a flash region.\r
+\r
+ @param DirectValue Value to directly write to register.\r
+ if DirectValue == 0 the use Base & Length below.\r
+ @param BaseAddress Base address of region in Flash Memory Map.\r
+ @param Length Length of region to protect.\r
+\r
+ @retval EFI_SUCCESS Free spi protect register found & written.\r
+ @retval EFI_NOT_FOUND Free Spi protect register not found.\r
+ @retval EFI_DEVICE_ERROR Unable to write to spi protect register.\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+PlatformWriteFirstFreeSpiProtect (\r
+ IN CONST UINT32 DirectValue,\r
+ IN CONST UINT32 BaseAddress,\r
+ IN CONST UINT32 Length\r
+ )\r
+{\r
+ UINT32 FreeOffset;\r
+ UINT32 PchRootComplexBar;\r
+ EFI_STATUS Status;\r
+\r
+ PchRootComplexBar = QNC_RCRB_BASE;\r
+\r
+ Status = WriteFirstFreeSpiProtect (\r
+ PchRootComplexBar,\r
+ DirectValue,\r
+ BaseAddress,\r
+ Length,\r
+ &FreeOffset\r
+ );\r
+\r
+ if (!EFI_ERROR (Status)) {\r
+ S3BootScriptSaveMemWrite (\r
+ S3BootScriptWidthUint32,\r
+ (UINTN) (PchRootComplexBar + FreeOffset),\r
+ 1,\r
+ (VOID *) (UINTN) (PchRootComplexBar + FreeOffset)\r
+ );\r
+ }\r
+\r
+ return Status;\r
+}\r
+\r
+/**\r
+ Lock legacy SPI static configuration information.\r
+\r
+ Function will assert if unable to lock config.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+PlatformFlashLockConfig (\r
+ VOID\r
+ )\r
+{\r
+ EFI_STATUS Status;\r
+ EFI_SPI_PROTOCOL *SpiProtocol;\r
+\r
+ //\r
+ // Enable lock of legacy SPI static configuration information.\r
+ //\r
+\r
+ SpiProtocol = LocateSpiProtocol (NULL); // This routine will not be called in SMM.\r
+ ASSERT_EFI_ERROR (SpiProtocol != NULL);\r
+ if (SpiProtocol != NULL) {\r
+ Status = SpiProtocol->Lock (SpiProtocol);\r
+\r
+ if (!EFI_ERROR (Status)) {\r
+ DEBUG ((EFI_D_INFO, "Platform: Spi Config Locked Down\n"));\r
+ } else if (Status == EFI_ACCESS_DENIED) {\r
+ DEBUG ((EFI_D_INFO, "Platform: Spi Config already locked down\n"));\r
+ } else {\r
+ ASSERT_EFI_ERROR (Status);\r
+ }\r
+ }\r
+}\r
+\r
+/**\r
+ Platform Variable Lock.\r
+\r
+ @retval EFI_SUCCESS Platform Variable Lock successful.\r
+ @retval EFI_NOT_FOUND No protocol instances were found that match Protocol and\r
+ Registration.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+PlatformVariableLock (\r
+ )\r
+{\r
+ EFI_STATUS Status;\r
+ EDKII_VARIABLE_LOCK_PROTOCOL *VariableLockProtocol;\r
+\r
+ Status = gBS->LocateProtocol (&gEdkiiVariableLockProtocolGuid, NULL, (VOID **)&VariableLockProtocol);\r
+ ASSERT_EFI_ERROR (Status);\r
+\r
+ Status = VariableLockProtocol->RequestToLock (\r
+ VariableLockProtocol,\r
+ QUARK_VARIABLE_LOCK_NAME,\r
+ &gQuarkVariableLockGuid\r
+ );\r
+ ASSERT_EFI_ERROR (Status);\r
+\r
+ // Memory Config Data shouldn't be writable when Quark Variable Lock is enabled.\r
+ Status = VariableLockProtocol->RequestToLock (\r
+ VariableLockProtocol,\r
+ EFI_MEMORY_CONFIG_DATA_NAME,\r
+ &gEfiMemoryConfigDataGuid\r
+ );\r
+ ASSERT_EFI_ERROR (Status);\r
+}\r
+\r
+/**\r
+ Lock regions and config of SPI flash given the policy for this platform.\r
+\r
+ Function will assert if unable to lock regions or config.\r
+\r
+ @param PreBootPolicy If TRUE do Pre Boot Flash Lock Policy.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+PlatformFlashLockPolicy (\r
+ IN CONST BOOLEAN PreBootPolicy\r
+ )\r
+{\r
+ EFI_STATUS Status;\r
+ UINT64 CpuAddressNvStorage;\r
+ UINT64 CpuAddressFlashDevice;\r
+ UINT64 SpiAddress;\r
+ EFI_BOOT_MODE BootMode;\r
+ UINTN SpiFlashDeviceSize;\r
+\r
+ BootMode = GetBootModeHob ();\r
+\r
+ SpiFlashDeviceSize = (UINTN) PcdGet32 (PcdSpiFlashDeviceSize);\r
+ CpuAddressFlashDevice = SIZE_4GB - SpiFlashDeviceSize;\r
+ DEBUG (\r
+ (EFI_D_INFO,\r
+ "Platform:FlashDeviceSize = 0x%08x Bytes\n",\r
+ SpiFlashDeviceSize)\r
+ );\r
+\r
+ //\r
+ // If not in update or recovery mode, lock stuff down\r
+ //\r
+ if ((BootMode != BOOT_IN_RECOVERY_MODE) && (BootMode != BOOT_ON_FLASH_UPDATE)) {\r
+\r
+ //\r
+ // Lock regions\r
+ //\r
+ CpuAddressNvStorage = (UINT64) PcdGet32 (PcdFlashNvStorageVariableBase);\r
+\r
+ //\r
+ // Lock from start of flash device up to Smi writable flash storage areas.\r
+ //\r
+ SpiAddress = 0;\r
+ if (!PlatformIsSpiRangeProtected ((UINT32) SpiAddress, (UINT32) (CpuAddressNvStorage - CpuAddressFlashDevice))) {\r
+ DEBUG (\r
+ (EFI_D_INFO,\r
+ "Platform: Protect Region Base:Len 0x%08x:0x%08x\n",\r
+ (UINTN) SpiAddress, (UINTN)(CpuAddressNvStorage - CpuAddressFlashDevice))\r
+ );\r
+ Status = PlatformWriteFirstFreeSpiProtect (\r
+ 0,\r
+ (UINT32) SpiAddress,\r
+ (UINT32) (CpuAddressNvStorage - CpuAddressFlashDevice)\r
+ );\r
+\r
+ ASSERT_EFI_ERROR (Status);\r
+ }\r
+ //\r
+ // Move Spi Address to after Smi writable flash storage areas.\r
+ //\r
+ SpiAddress = CpuAddressNvStorage - CpuAddressFlashDevice;\r
+ SpiAddress += ((UINT64) PcdGet32 (PcdFlashNvStorageVariableSize));\r
+\r
+ //\r
+ // Lock from end of OEM area to end of flash part.\r
+ //\r
+ if (!PlatformIsSpiRangeProtected ((UINT32) SpiAddress, SpiFlashDeviceSize - ((UINT32) SpiAddress))) {\r
+ DEBUG (\r
+ (EFI_D_INFO,\r
+ "Platform: Protect Region Base:Len 0x%08x:0x%08x\n",\r
+ (UINTN) SpiAddress,\r
+ (UINTN) (SpiFlashDeviceSize - ((UINT32) SpiAddress)))\r
+ );\r
+ ASSERT (SpiAddress < ((UINT64) SpiFlashDeviceSize));\r
+ Status = PlatformWriteFirstFreeSpiProtect (\r
+ 0,\r
+ (UINT32) SpiAddress,\r
+ SpiFlashDeviceSize - ((UINT32) SpiAddress)\r
+ );\r
+\r
+ ASSERT_EFI_ERROR (Status);\r
+ }\r
+ }\r
+\r
+ //\r
+ // Always Lock flash config registers if about to boot a boot option\r
+ // else lock depending on boot mode.\r
+ //\r
+ if (PreBootPolicy || (BootMode != BOOT_ON_FLASH_UPDATE)) {\r
+ PlatformFlashLockConfig ();\r
+ }\r
+\r
+ //\r
+ // Enable Quark Variable lock if PreBootPolicy.\r
+ //\r
+ if (PreBootPolicy) {\r
+ PlatformVariableLock ();\r
+ }\r
+}\r
+\r
+/**\r
+ Erase and Write to platform flash.\r
+\r
+ Routine accesses one flash block at a time, each access consists\r
+ of an erase followed by a write of FLASH_BLOCK_SIZE. One or both\r
+ of DoErase & DoWrite params must be TRUE.\r
+\r
+ Limitations:-\r
+ CpuWriteAddress must be aligned to FLASH_BLOCK_SIZE.\r
+ DataSize must be a multiple of FLASH_BLOCK_SIZE.\r
+\r
+ @param Smst If != NULL then InSmm and use to locate\r
+ SpiProtocol.\r
+ @param CpuWriteAddress Address in CPU memory map of flash region.\r
+ @param Data The buffer containing the data to be written.\r
+ @param DataSize Amount of data to write.\r
+ @param DoErase Earse each block.\r
+ @param DoWrite Write to each block.\r
+\r
+ @retval EFI_SUCCESS Operation successful.\r
+ @retval EFI_NOT_READY Required resources not setup.\r
+ @retval EFI_INVALID_PARAMETER Invalid parameter.\r
+ @retval Others Unexpected error happened.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+PlatformFlashEraseWrite (\r
+ IN VOID *Smst,\r
+ IN UINTN CpuWriteAddress,\r
+ IN UINT8 *Data,\r
+ IN UINTN DataSize,\r
+ IN BOOLEAN DoErase,\r
+ IN BOOLEAN DoWrite\r
+ )\r
+{\r
+ EFI_STATUS Status;\r
+ UINT64 CpuBaseAddress;\r
+ SPI_INIT_INFO *SpiInfo;\r
+ UINT8 *WriteBuf;\r
+ UINTN Index;\r
+ UINTN SpiWriteAddress;\r
+ EFI_SPI_PROTOCOL *SpiProtocol;\r
+\r
+ if (!DoErase && !DoWrite) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+ if (DoWrite && Data == NULL) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+ if ((CpuWriteAddress % FLASH_BLOCK_SIZE) != 0) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+ if ((DataSize % FLASH_BLOCK_SIZE) != 0) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+ SpiProtocol = LocateSpiProtocol ((EFI_SMM_SYSTEM_TABLE2 *)Smst);\r
+ if (SpiProtocol == NULL) {\r
+ return EFI_NOT_READY;\r
+ }\r
+\r
+ //\r
+ // Find info to allow usage of SpiProtocol->Execute.\r
+ //\r
+ Status = SpiProtocol->Info (\r
+ SpiProtocol,\r
+ &SpiInfo\r
+ );\r
+ if (EFI_ERROR(Status)) {\r
+ return Status;\r
+ }\r
+ ASSERT (SpiInfo->InitTable != NULL);\r
+ ASSERT (SpiInfo->EraseOpcodeIndex < SPI_NUM_OPCODE);\r
+ ASSERT (SpiInfo->ProgramOpcodeIndex < SPI_NUM_OPCODE);\r
+\r
+ CpuBaseAddress = PcdGet32 (PcdFlashAreaBaseAddress) - (UINT32)SpiInfo->InitTable->BiosStartOffset;\r
+ ASSERT(CpuBaseAddress >= (SIZE_4GB - SIZE_8MB));\r
+ if (CpuWriteAddress < CpuBaseAddress) {\r
+ return (EFI_INVALID_PARAMETER);\r
+ }\r
+\r
+ SpiWriteAddress = CpuWriteAddress - ((UINTN) CpuBaseAddress);\r
+ WriteBuf = Data;\r
+ DEBUG (\r
+ (EFI_D_INFO, "PlatformFlashWrite:SpiWriteAddress=%08x EraseIndex=%d WriteIndex=%d\n",\r
+ SpiWriteAddress,\r
+ (UINTN) SpiInfo->EraseOpcodeIndex,\r
+ (UINTN) SpiInfo->ProgramOpcodeIndex\r
+ ));\r
+ for (Index =0; Index < DataSize / FLASH_BLOCK_SIZE; Index++) {\r
+ if (DoErase) {\r
+ DEBUG (\r
+ (EFI_D_INFO, "PlatformFlashWrite:Erase[%04x] SpiWriteAddress=%08x\n",\r
+ Index,\r
+ SpiWriteAddress\r
+ ));\r
+ Status = SpiProtocol->Execute (\r
+ SpiProtocol,\r
+ SpiInfo->EraseOpcodeIndex,// OpcodeIndex\r
+ 0, // PrefixOpcodeIndex\r
+ FALSE, // DataCycle\r
+ TRUE, // Atomic\r
+ FALSE, // ShiftOut\r
+ SpiWriteAddress, // Address\r
+ 0, // Data Number\r
+ NULL,\r
+ EnumSpiRegionAll // SPI_REGION_TYPE\r
+ );\r
+ if (EFI_ERROR(Status)) {\r
+ return Status;\r
+ }\r
+ }\r
+\r
+ if (DoWrite) {\r
+ DEBUG (\r
+ (EFI_D_INFO, "PlatformFlashWrite:Write[%04x] SpiWriteAddress=%08x\n",\r
+ Index,\r
+ SpiWriteAddress\r
+ ));\r
+ Status = SpiProtocol->Execute (\r
+ SpiProtocol,\r
+ SpiInfo->ProgramOpcodeIndex, // OpcodeIndex\r
+ 0, // PrefixOpcodeIndex\r
+ TRUE, // DataCycle\r
+ TRUE, // Atomic\r
+ TRUE, // ShiftOut\r
+ SpiWriteAddress, // Address\r
+ FLASH_BLOCK_SIZE, // Data Number\r
+ WriteBuf,\r
+ EnumSpiRegionAll\r
+ );\r
+ if (EFI_ERROR(Status)) {\r
+ return Status;\r
+ }\r
+ WriteBuf+=FLASH_BLOCK_SIZE;\r
+ }\r
+ SpiWriteAddress+=FLASH_BLOCK_SIZE;\r
+ }\r
+ return EFI_SUCCESS;\r
+}\r
+\r
+/** Check if System booted with recovery Boot Stage1 image.\r
+\r
+ @retval TRUE If system booted with recovery Boot Stage1 image.\r
+ @retval FALSE If system booted with normal stage1 image.\r
+\r
+**/\r
+BOOLEAN\r
+EFIAPI\r
+PlatformIsBootWithRecoveryStage1 (\r
+ VOID\r
+ )\r
+{\r
+ ASSERT_EFI_ERROR (EFI_UNSUPPORTED);\r
+ return FALSE;\r
+}\r
+\r
+/**\r
+ Set the direction of Pcal9555 IO Expander GPIO pin.\r
+\r
+ @param Pcal9555SlaveAddr I2c Slave address of Pcal9555 Io Expander.\r
+ @param GpioNum Gpio direction to configure - values 0-7 for Port0\r
+ and 8-15 for Port1.\r
+ @param CfgAsInput If TRUE set pin direction as input else set as output.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+PlatformPcal9555GpioSetDir (\r
+ IN CONST UINT32 Pcal9555SlaveAddr,\r
+ IN CONST UINT32 GpioNum,\r
+ IN CONST BOOLEAN CfgAsInput\r
+ )\r
+{\r
+ Pcal9555SetPortRegBit (\r
+ Pcal9555SlaveAddr,\r
+ GpioNum,\r
+ PCAL9555_REG_CFG_PORT0,\r
+ CfgAsInput\r
+ );\r
+}\r
+\r
+/**\r
+ Set the level of Pcal9555 IO Expander GPIO high or low.\r
+\r
+ @param Pcal9555SlaveAddr I2c Slave address of Pcal9555 Io Expander.\r
+ @param GpioNum Gpio to change values 0-7 for Port0 and 8-15\r
+ for Port1.\r
+ @param HighLevel If TRUE set pin high else set pin low.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+PlatformPcal9555GpioSetLevel (\r
+ IN CONST UINT32 Pcal9555SlaveAddr,\r
+ IN CONST UINT32 GpioNum,\r
+ IN CONST BOOLEAN HighLevel\r
+ )\r
+{\r
+ Pcal9555SetPortRegBit (\r
+ Pcal9555SlaveAddr,\r
+ GpioNum,\r
+ PCAL9555_REG_OUT_PORT0,\r
+ HighLevel\r
+ );\r
+}\r
+\r
+/**\r
+\r
+ Enable pull-up/pull-down resistors of Pcal9555 GPIOs.\r
+\r
+ @param Pcal9555SlaveAddr I2c Slave address of Pcal9555 Io Expander.\r
+ @param GpioNum Gpio to change values 0-7 for Port0 and 8-15\r
+ for Port1.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+PlatformPcal9555GpioEnablePull (\r
+ IN CONST UINT32 Pcal9555SlaveAddr,\r
+ IN CONST UINT32 GpioNum\r
+ )\r
+{\r
+ Pcal9555SetPortRegBit (\r
+ Pcal9555SlaveAddr,\r
+ GpioNum,\r
+ PCAL9555_REG_PULL_EN_PORT0,\r
+ TRUE\r
+ );\r
+}\r
+\r
+/**\r
+\r
+ Disable pull-up/pull-down resistors of Pcal9555 GPIOs.\r
+\r
+ @param Pcal9555SlaveAddr I2c Slave address of Pcal9555 Io Expander.\r
+ @param GpioNum Gpio to change values 0-7 for Port0 and 8-15\r
+ for Port1.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+PlatformPcal9555GpioDisablePull (\r
+ IN CONST UINT32 Pcal9555SlaveAddr,\r
+ IN CONST UINT32 GpioNum\r
+ )\r
+{\r
+ Pcal9555SetPortRegBit (\r
+ Pcal9555SlaveAddr,\r
+ GpioNum,\r
+ PCAL9555_REG_PULL_EN_PORT0,\r
+ FALSE\r
+ );\r
+}\r
+\r
+/**\r
+\r
+ Get state of Pcal9555 GPIOs.\r
+\r
+ @param Pcal9555SlaveAddr I2c Slave address of Pcal9555 Io Expander.\r
+ @param GpioNum Gpio to change values 0-7 for Port0 and 8-15\r
+ for Port1.\r
+\r
+ @retval TRUE GPIO pin is high\r
+ @retval FALSE GPIO pin is low\r
+**/\r
+BOOLEAN\r
+EFIAPI\r
+PlatformPcal9555GpioGetState (\r
+ IN CONST UINT32 Pcal9555SlaveAddr,\r
+ IN CONST UINT32 GpioNum\r
+ )\r
+{\r
+ return Pcal9555GetPortRegBit (Pcal9555SlaveAddr, GpioNum, PCAL9555_REG_IN_PORT0);\r
+}\r
--- /dev/null
+/** @file\r
+Helper routines with common PEI / DXE implementation.\r
+\r
+Copyright (c) 2013-2015 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#include "CommonHeader.h"\r
+\r
+CHAR16 *mPlatTypeNameTable[] = { EFI_PLATFORM_TYPE_NAME_TABLE_DEFINITION };\r
+UINTN mPlatTypeNameTableLen = ((sizeof(mPlatTypeNameTable)) / sizeof (CHAR16 *));\r
+\r
+//\r
+// Routines defined in other source modules of this component.\r
+//\r
+\r
+//\r
+// Routines local to this source module.\r
+//\r
+\r
+//\r
+// Routines shared with other souce modules in this component.\r
+//\r
+\r
+EFI_STATUS\r
+WriteFirstFreeSpiProtect (\r
+ IN CONST UINT32 PchRootComplexBar,\r
+ IN CONST UINT32 DirectValue,\r
+ IN CONST UINT32 BaseAddress,\r
+ IN CONST UINT32 Length,\r
+ OUT UINT32 *OffsetPtr\r
+ )\r
+{\r
+ UINT32 RegVal;\r
+ UINT32 Offset;\r
+ UINT32 StepLen;\r
+\r
+ ASSERT (PchRootComplexBar > 0);\r
+\r
+ Offset = 0;\r
+ if (OffsetPtr != NULL) {\r
+ *OffsetPtr = Offset;\r
+ }\r
+ if (MmioRead32 (PchRootComplexBar + R_QNC_RCRB_SPIPBR0) == 0) {\r
+ Offset = R_QNC_RCRB_SPIPBR0;\r
+ } else {\r
+ if (MmioRead32 (PchRootComplexBar + R_QNC_RCRB_SPIPBR1) == 0) {\r
+ Offset = R_QNC_RCRB_SPIPBR1;\r
+ } else {\r
+ if (MmioRead32 (PchRootComplexBar + R_QNC_RCRB_SPIPBR2) == 0) {\r
+ Offset = R_QNC_RCRB_SPIPBR2;\r
+ }\r
+ }\r
+ }\r
+ if (Offset != 0) {\r
+ if (DirectValue == 0) {\r
+ StepLen = ALIGN_VALUE (Length,SIZE_4KB); // Bring up to 4K boundary.\r
+ RegVal = BaseAddress + StepLen - 1;\r
+ RegVal &= 0x00FFF000; // Set EDS Protected Range Limit (PRL).\r
+ RegVal |= ((BaseAddress >> 12) & 0xfff); // or in EDS Protected Range Base (PRB).\r
+ } else {\r
+ RegVal = DirectValue;\r
+ }\r
+ //\r
+ // Enable protection.\r
+ //\r
+ RegVal |= B_QNC_RCRB_SPIPBRn_WPE;\r
+ MmioWrite32 (PchRootComplexBar + Offset, RegVal);\r
+ if (RegVal == MmioRead32 (PchRootComplexBar + Offset)) {\r
+ if (OffsetPtr != NULL) {\r
+ *OffsetPtr = Offset;\r
+ }\r
+ return EFI_SUCCESS;\r
+ }\r
+ return EFI_DEVICE_ERROR;\r
+ }\r
+ return EFI_NOT_FOUND;\r
+}\r
+\r
+//\r
+// Routines exported by this component.\r
+//\r
+\r
+/**\r
+ Read 8bit character from debug stream.\r
+\r
+ Block until character is read.\r
+\r
+ @return 8bit character read from debug stream.\r
+\r
+**/\r
+CHAR8\r
+EFIAPI\r
+PlatformDebugPortGetChar8 (\r
+ VOID\r
+ )\r
+{\r
+ CHAR8 Got;\r
+\r
+ do {\r
+ if (SerialPortPoll ()) {\r
+ if (SerialPortRead ((UINT8 *) &Got, 1) == 1) {\r
+ break;\r
+ }\r
+ }\r
+ } while (TRUE);\r
+\r
+ return Got;\r
+}\r
+\r
+/**\r
+ Clear SPI Protect registers.\r
+\r
+ @retval EFI_SUCCESS SPI protect registers cleared.\r
+ @retval EFI_ACCESS_DENIED Unable to clear SPI protect registers.\r
+**/\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+PlatformClearSpiProtect (\r
+ VOID\r
+ )\r
+{\r
+ UINT32 PchRootComplexBar;\r
+\r
+ PchRootComplexBar = QNC_RCRB_BASE;\r
+ //\r
+ // Check if the SPI interface has been locked-down.\r
+ //\r
+ if ((MmioRead16 (PchRootComplexBar + R_QNC_RCRB_SPIS) & B_QNC_RCRB_SPIS_SCL) != 0) {\r
+ return EFI_ACCESS_DENIED;\r
+ }\r
+ MmioWrite32 (PchRootComplexBar + R_QNC_RCRB_SPIPBR0, 0);\r
+ if (MmioRead32 (PchRootComplexBar + R_QNC_RCRB_SPIPBR0) != 0) {\r
+ return EFI_ACCESS_DENIED;\r
+ }\r
+ MmioWrite32 (PchRootComplexBar + R_QNC_RCRB_SPIPBR1, 0);\r
+ if (MmioRead32 (PchRootComplexBar + R_QNC_RCRB_SPIPBR0) != 0) {\r
+ return EFI_ACCESS_DENIED;\r
+ }\r
+ MmioWrite32 (PchRootComplexBar + R_QNC_RCRB_SPIPBR2, 0);\r
+ if (MmioRead32 (PchRootComplexBar + R_QNC_RCRB_SPIPBR0) != 0) {\r
+ return EFI_ACCESS_DENIED;\r
+ }\r
+ return EFI_SUCCESS;\r
+}\r
+\r
+/**\r
+ Determine if an SPI address range is protected.\r
+\r
+ @param SpiBaseAddress Base of SPI range.\r
+ @param Length Length of SPI range.\r
+\r
+ @retval TRUE Range is protected.\r
+ @retval FALSE Range is not protected.\r
+**/\r
+BOOLEAN\r
+EFIAPI\r
+PlatformIsSpiRangeProtected (\r
+ IN CONST UINT32 SpiBaseAddress,\r
+ IN CONST UINT32 Length\r
+ )\r
+{\r
+ UINT32 RegVal;\r
+ UINT32 Offset;\r
+ UINT32 Limit;\r
+ UINT32 ProtectedBase;\r
+ UINT32 ProtectedLimit;\r
+ UINT32 PchRootComplexBar;\r
+\r
+ PchRootComplexBar = QNC_RCRB_BASE;\r
+\r
+ if (Length > 0) {\r
+ Offset = R_QNC_RCRB_SPIPBR0;\r
+ Limit = SpiBaseAddress + (Length - 1);\r
+ do {\r
+ RegVal = MmioRead32 (PchRootComplexBar + Offset);\r
+ if ((RegVal & B_QNC_RCRB_SPIPBRn_WPE) != 0) {\r
+ ProtectedBase = (RegVal & 0xfff) << 12;\r
+ ProtectedLimit = (RegVal & 0x00fff000) + 0xfff;\r
+ if (SpiBaseAddress >= ProtectedBase && Limit <= ProtectedLimit) {\r
+ return TRUE;\r
+ }\r
+ }\r
+ if (Offset == R_QNC_RCRB_SPIPBR0) {\r
+ Offset = R_QNC_RCRB_SPIPBR1;\r
+ } else if (Offset == R_QNC_RCRB_SPIPBR1) {\r
+ Offset = R_QNC_RCRB_SPIPBR2;\r
+ } else {\r
+ break;\r
+ }\r
+ } while (TRUE);\r
+ }\r
+ return FALSE;\r
+}\r
+\r
+/**\r
+ Set Legacy GPIO Level\r
+\r
+ @param LevelRegOffset GPIO level register Offset from GPIO Base Address.\r
+ @param GpioNum GPIO bit to change.\r
+ @param HighLevel If TRUE set GPIO High else Set GPIO low.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+PlatformLegacyGpioSetLevel (\r
+ IN CONST UINT32 LevelRegOffset,\r
+ IN CONST UINT32 GpioNum,\r
+ IN CONST BOOLEAN HighLevel\r
+ )\r
+{\r
+ UINT32 RegValue;\r
+ UINT32 GpioBaseAddress;\r
+ UINT32 GpioNumMask;\r
+\r
+ GpioBaseAddress = LpcPciCfg32 (R_QNC_LPC_GBA_BASE) & B_QNC_LPC_GPA_BASE_MASK;\r
+ ASSERT (GpioBaseAddress > 0);\r
+\r
+ RegValue = IoRead32 (GpioBaseAddress + LevelRegOffset);\r
+ GpioNumMask = (1 << GpioNum);\r
+ if (HighLevel) {\r
+ RegValue |= (GpioNumMask);\r
+ } else {\r
+ RegValue &= ~(GpioNumMask);\r
+ }\r
+ IoWrite32 (GpioBaseAddress + LevelRegOffset, RegValue);\r
+}\r
+\r
+/**\r
+ Get Legacy GPIO Level\r
+\r
+ @param LevelRegOffset GPIO level register Offset from GPIO Base Address.\r
+ @param GpioNum GPIO bit to check.\r
+\r
+ @retval TRUE If bit is SET.\r
+ @retval FALSE If bit is CLEAR.\r
+\r
+**/\r
+BOOLEAN\r
+EFIAPI\r
+PlatformLegacyGpioGetLevel (\r
+ IN CONST UINT32 LevelRegOffset,\r
+ IN CONST UINT32 GpioNum\r
+ )\r
+{\r
+ UINT32 RegValue;\r
+ UINT32 GpioBaseAddress;\r
+ UINT32 GpioNumMask;\r
+\r
+ GpioBaseAddress = LpcPciCfg32 (R_QNC_LPC_GBA_BASE) & B_QNC_LPC_GPA_BASE_MASK;\r
+ RegValue = IoRead32 (GpioBaseAddress + LevelRegOffset);\r
+ GpioNumMask = (1 << GpioNum);\r
+ return ((RegValue & GpioNumMask) != 0);\r
+}\r
--- /dev/null
+/** @file\r
+Implementation of Helper routines for PEI enviroment.\r
+\r
+Copyright (c) 2013-2015 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#include <PiPei.h>\r
+\r
+#include <Library/PeiServicesTablePointerLib.h>\r
+#include <Library/PeiServicesLib.h>\r
+#include <Library/I2cLib.h>\r
+\r
+#include "CommonHeader.h"\r
+\r
+//\r
+// Routines defined in other source modules of this component.\r
+//\r
+\r
+//\r
+// Routines local to this source module.\r
+//\r
+\r
+//\r
+// Routines exported by this source module.\r
+//\r
+\r
+/**\r
+ Find pointer to RAW data in Firmware volume file.\r
+\r
+ @param FvNameGuid Firmware volume to search. If == NULL search all.\r
+ @param FileNameGuid Firmware volume file to search for.\r
+ @param SectionData Pointer to RAW data section of found file.\r
+ @param SectionDataSize Pointer to UNITN to get size of RAW data.\r
+\r
+ @retval EFI_SUCCESS Raw Data found.\r
+ @retval EFI_INVALID_PARAMETER FileNameGuid == NULL.\r
+ @retval EFI_NOT_FOUND Firmware volume file not found.\r
+ @retval EFI_UNSUPPORTED Unsupported in current enviroment (PEI or DXE).\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+PlatformFindFvFileRawDataSection (\r
+ IN CONST EFI_GUID *FvNameGuid OPTIONAL,\r
+ IN CONST EFI_GUID *FileNameGuid,\r
+ OUT VOID **SectionData,\r
+ OUT UINTN *SectionDataSize\r
+ )\r
+{\r
+ EFI_STATUS Status;\r
+ UINTN Instance;\r
+ EFI_PEI_FV_HANDLE VolumeHandle;\r
+ EFI_PEI_FILE_HANDLE FileHandle;\r
+ EFI_SECTION_TYPE SearchType;\r
+ EFI_FV_INFO VolumeInfo;\r
+ EFI_FV_FILE_INFO FileInfo;\r
+ CONST EFI_PEI_SERVICES **PeiServices;\r
+\r
+ if (FileNameGuid == NULL || SectionData == NULL || SectionDataSize == NULL) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+ *SectionData = NULL;\r
+ *SectionDataSize = 0;\r
+\r
+ PeiServices = GetPeiServicesTablePointer ();\r
+ SearchType = EFI_SECTION_RAW;\r
+ for (Instance = 0; !EFI_ERROR((PeiServicesFfsFindNextVolume (Instance, &VolumeHandle))); Instance++) {\r
+ if (FvNameGuid != NULL) {\r
+ Status = PeiServicesFfsGetVolumeInfo (VolumeHandle, &VolumeInfo);\r
+ if (EFI_ERROR (Status)) {\r
+ continue;\r
+ }\r
+ if (!CompareGuid (FvNameGuid, &VolumeInfo.FvName)) {\r
+ continue;\r
+ }\r
+ }\r
+ Status = PeiServicesFfsFindFileByName (FileNameGuid, VolumeHandle, &FileHandle);\r
+ if (!EFI_ERROR (Status)) {\r
+ Status = PeiServicesFfsGetFileInfo (FileHandle, &FileInfo);\r
+ if (EFI_ERROR (Status)) {\r
+ continue;\r
+ }\r
+ if (IS_SECTION2(FileInfo.Buffer)) {\r
+ *SectionDataSize = SECTION2_SIZE(FileInfo.Buffer) - sizeof(EFI_COMMON_SECTION_HEADER2);\r
+ } else {\r
+ *SectionDataSize = SECTION_SIZE(FileInfo.Buffer) - sizeof(EFI_COMMON_SECTION_HEADER);\r
+ }\r
+ Status = PeiServicesFfsFindSectionData (SearchType, FileHandle, SectionData);\r
+ if (!EFI_ERROR (Status)) {\r
+ return Status;\r
+ }\r
+ }\r
+ }\r
+ return EFI_NOT_FOUND;\r
+}\r
+\r
+/**\r
+ Find free spi protect register and write to it to protect a flash region.\r
+\r
+ @param DirectValue Value to directly write to register.\r
+ if DirectValue == 0 the use Base & Length below.\r
+ @param BaseAddress Base address of region in Flash Memory Map.\r
+ @param Length Length of region to protect.\r
+\r
+ @retval EFI_SUCCESS Free spi protect register found & written.\r
+ @retval EFI_NOT_FOUND Free Spi protect register not found.\r
+ @retval EFI_DEVICE_ERROR Unable to write to spi protect register.\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+PlatformWriteFirstFreeSpiProtect (\r
+ IN CONST UINT32 DirectValue,\r
+ IN CONST UINT32 BaseAddress,\r
+ IN CONST UINT32 Length\r
+ )\r
+{\r
+ return WriteFirstFreeSpiProtect (\r
+ QNC_RCRB_BASE,\r
+ DirectValue,\r
+ BaseAddress,\r
+ Length,\r
+ NULL\r
+ );\r
+}\r
+\r
+/** Check if System booted with recovery Boot Stage1 image.\r
+\r
+ @retval TRUE If system booted with recovery Boot Stage1 image.\r
+ @retval FALSE If system booted with normal stage1 image.\r
+\r
+**/\r
+BOOLEAN\r
+EFIAPI\r
+PlatformIsBootWithRecoveryStage1 (\r
+ VOID\r
+ )\r
+{\r
+ BOOLEAN IsRecoveryBoot;\r
+ QUARK_EDKII_STAGE1_HEADER *Edk2ImageHeader;\r
+\r
+ Edk2ImageHeader = (QUARK_EDKII_STAGE1_HEADER *) PcdGet32 (PcdEsramStage1Base);\r
+ switch ((UINT8)Edk2ImageHeader->ImageIndex & QUARK_STAGE1_IMAGE_TYPE_MASK) {\r
+ case QUARK_STAGE1_RECOVERY_IMAGE_TYPE:\r
+ //\r
+ // Recovery Boot\r
+ //\r
+ IsRecoveryBoot = TRUE;\r
+ break;\r
+ default:\r
+ //\r
+ // Normal Boot\r
+ //\r
+ IsRecoveryBoot = FALSE;\r
+ break;\r
+ }\r
+\r
+ return IsRecoveryBoot;\r
+}\r
--- /dev/null
+/** @file\r
+Platform helper LED routines.\r
+\r
+Copyright (c) 2013-2015 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#include <PiDxe.h>\r
+\r
+#include "CommonHeader.h"\r
+\r
+//\r
+// Routines defined in other source modules of this component.\r
+//\r
+\r
+//\r
+// Routines local to this source module.\r
+//\r
+\r
+VOID\r
+GalileoGen2RouteOutFlashUpdateLed (\r
+ VOID\r
+ )\r
+{\r
+ //\r
+ // For GpioNums below values 0 to 7 are for Port0 ie P0-0 - P0-7 and\r
+ // values 8 to 15 are for Port1 ie P1-0 - P1-7.\r
+ //\r
+\r
+ //\r
+ // Disable Pull-ups / pull downs on EXP0 pin for LVL_B_PU7 signal.\r
+ //\r
+ PlatformPcal9555GpioDisablePull (\r
+ GALILEO_GEN2_IOEXP0_7BIT_SLAVE_ADDR, // IO Expander 0.\r
+ 15 // P1-7.\r
+ );\r
+\r
+ //\r
+ // Make LVL_B_OE7_N an output pin.\r
+ //\r
+ PlatformPcal9555GpioSetDir (\r
+ GALILEO_GEN2_IOEXP0_7BIT_SLAVE_ADDR, // IO Expander 0.\r
+ 14, // P1-6.\r
+ FALSE\r
+ );\r
+\r
+ //\r
+ // Set level of LVL_B_OE7_N to low.\r
+ //\r
+ PlatformPcal9555GpioSetLevel (\r
+ GALILEO_GEN2_IOEXP0_7BIT_SLAVE_ADDR,\r
+ 14,\r
+ FALSE\r
+ );\r
+\r
+ //\r
+ // Make MUX8_SEL an output pin.\r
+ //\r
+ PlatformPcal9555GpioSetDir (\r
+ GALILEO_GEN2_IOEXP1_7BIT_SLAVE_ADDR, // IO Expander 1.\r
+ 14, // P1-6.\r
+ FALSE\r
+ );\r
+\r
+ //\r
+ // Set level of MUX8_SEL to low to route GPIO_SUS<5> to LED.\r
+ //\r
+ PlatformPcal9555GpioSetLevel (\r
+ GALILEO_GEN2_IOEXP1_7BIT_SLAVE_ADDR, // IO Expander 1.\r
+ 14, // P1-6.\r
+ FALSE\r
+ );\r
+}\r
+\r
+//\r
+// Routines exported by this source module.\r
+//\r
+\r
+/**\r
+ Init platform LEDs into known state.\r
+\r
+ @param PlatformType Executing platform type.\r
+ @param I2cBus Pointer to I2c Host controller protocol.\r
+\r
+ @retval EFI_SUCCESS Operation success.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+PlatformLedInit (\r
+ IN CONST EFI_PLATFORM_TYPE Type\r
+ )\r
+{\r
+ EFI_BOOT_MODE BootMode;\r
+\r
+ BootMode = GetBootModeHob ();\r
+\r
+ //\r
+ // Init Flash update / recovery LED in OFF state.\r
+ //\r
+ if (BootMode == BOOT_ON_FLASH_UPDATE || BootMode == BOOT_IN_RECOVERY_MODE) {\r
+ if (Type == GalileoGen2) {\r
+ PlatformLegacyGpioSetLevel (R_QNC_GPIO_RGLVL_RESUME_WELL, GALILEO_GEN2_FLASH_UPDATE_LED_RESUMEWELL_GPIO, FALSE);\r
+ GalileoGen2RouteOutFlashUpdateLed ();\r
+ } else if (Type == Galileo) {\r
+ PlatformLegacyGpioSetLevel (R_QNC_GPIO_RGLVL_RESUME_WELL, GALILEO_FLASH_UPDATE_LED_RESUMEWELL_GPIO, FALSE);\r
+ } else {\r
+ //\r
+ // These platforms have no flash update LED.\r
+ //\r
+ }\r
+ }\r
+\r
+ return EFI_SUCCESS;\r
+}\r
+\r
+/**\r
+ Turn on or off platform flash update LED.\r
+\r
+ @param PlatformType Executing platform type.\r
+ @param TurnOn If TRUE turn on else turn off.\r
+\r
+ @retval EFI_SUCCESS Operation success.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+PlatformFlashUpdateLed (\r
+ IN CONST EFI_PLATFORM_TYPE Type,\r
+ IN CONST BOOLEAN TurnOn\r
+ )\r
+{\r
+ if (Type == GalileoGen2) {\r
+ PlatformLegacyGpioSetLevel (R_QNC_GPIO_RGLVL_RESUME_WELL, GALILEO_GEN2_FLASH_UPDATE_LED_RESUMEWELL_GPIO, TurnOn);\r
+ } else if (Type == Galileo) {\r
+ PlatformLegacyGpioSetLevel (R_QNC_GPIO_RGLVL_RESUME_WELL, GALILEO_FLASH_UPDATE_LED_RESUMEWELL_GPIO, TurnOn);\r
+ } else {\r
+ //\r
+ // These platforms have no flash update LED.\r
+ //\r
+ }\r
+\r
+ return EFI_SUCCESS;\r
+}\r
--- /dev/null
+/** @file\r
+Common header file shared by all source files in this component.\r
+\r
+Copyright (c) 2013-2015 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+**/\r
+\r
+#ifndef __COMMON_HEADER_H_\r
+#define __COMMON_HEADER_H_\r
+\r
+#include <Uefi.h>\r
+#include <Library/BaseLib.h>\r
+#include <Library/DebugLib.h>\r
+#include <Library/IoLib.h>\r
+#include <Library/TimerLib.h>\r
+#include <Library/QNCAccessLib.h>\r
+#include <Library/IntelQNCLib.h>\r
+#include <IntelQNCRegs.h>\r
+#include <IntelQNCConfig.h>\r
+#include <Pcal9555.h>\r
+#include <Platform.h>\r
+#include <PlatformBoards.h>\r
+\r
+#include <Library/PlatformPcieHelperLib.h>\r
+\r
+//\r
+// Routines shared between souce modules in this component.\r
+//\r
+\r
+VOID\r
+EFIAPI\r
+PlatformPcieErratas (\r
+ VOID\r
+ );\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+SocUnitEarlyInitialisation (\r
+ VOID\r
+ );\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+SocUnitReleasePcieControllerPreWaitPllLock (\r
+ IN CONST EFI_PLATFORM_TYPE PlatformType\r
+ );\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+SocUnitReleasePcieControllerPostPllLock (\r
+ IN CONST EFI_PLATFORM_TYPE PlatformType\r
+ );\r
+\r
+#endif\r
--- /dev/null
+/** @file\r
+Platform Pcie Helper Lib.\r
+\r
+Copyright (c) 2013 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#include "CommonHeader.h"\r
+\r
+//\r
+// Routines local to this source module.\r
+//\r
+VOID\r
+LegacyGpioSetLevel (\r
+ IN CONST UINT32 LevelRegOffset,\r
+ IN CONST UINT32 GpioNum,\r
+ IN CONST BOOLEAN HighLevel\r
+ )\r
+{\r
+ UINT32 RegValue;\r
+ UINT32 GpioBaseAddress;\r
+ UINT32 GpioNumMask;\r
+\r
+ GpioBaseAddress = LpcPciCfg32 (R_QNC_LPC_GBA_BASE) & B_QNC_LPC_GPA_BASE_MASK;\r
+ ASSERT (GpioBaseAddress > 0);\r
+\r
+ RegValue = IoRead32 (GpioBaseAddress + LevelRegOffset);\r
+ GpioNumMask = (1 << GpioNum);\r
+ if (HighLevel) {\r
+ RegValue |= (GpioNumMask);\r
+ } else {\r
+ RegValue &= ~(GpioNumMask);\r
+ }\r
+ IoWrite32 (GpioBaseAddress + R_QNC_GPIO_RGLVL_RESUME_WELL, RegValue);\r
+}\r
+\r
+//\r
+// Routines exported by this component.\r
+//\r
+\r
+/**\r
+ Platform assert PCI express PERST# signal.\r
+\r
+ @param PlatformType See EFI_PLATFORM_TYPE enum definitions.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+PlatformPERSTAssert (\r
+ IN CONST EFI_PLATFORM_TYPE PlatformType\r
+ )\r
+{\r
+ if (PlatformType == GalileoGen2) {\r
+ LegacyGpioSetLevel (R_QNC_GPIO_RGLVL_RESUME_WELL, GALILEO_GEN2_PCIEXP_PERST_RESUMEWELL_GPIO, FALSE);\r
+ } else {\r
+ LegacyGpioSetLevel (R_QNC_GPIO_RGLVL_RESUME_WELL, PCIEXP_PERST_RESUMEWELL_GPIO, FALSE);\r
+ }\r
+}\r
+\r
+/**\r
+ Platform de assert PCI express PERST# signal.\r
+\r
+ @param PlatformType See EFI_PLATFORM_TYPE enum definitions.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+PlatformPERSTDeAssert (\r
+ IN CONST EFI_PLATFORM_TYPE PlatformType\r
+ )\r
+{\r
+ if (PlatformType == GalileoGen2) {\r
+ LegacyGpioSetLevel (R_QNC_GPIO_RGLVL_RESUME_WELL, GALILEO_GEN2_PCIEXP_PERST_RESUMEWELL_GPIO, TRUE);\r
+ } else {\r
+ LegacyGpioSetLevel (R_QNC_GPIO_RGLVL_RESUME_WELL, PCIEXP_PERST_RESUMEWELL_GPIO, TRUE);\r
+ }\r
+}\r
+\r
+/** Early initialisation of the PCIe controller.\r
+\r
+ @param PlatformType See EFI_PLATFORM_TYPE enum definitions.\r
+\r
+ @retval EFI_SUCCESS Operation success.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+PlatformPciExpressEarlyInit (\r
+ IN CONST EFI_PLATFORM_TYPE PlatformType\r
+ )\r
+{\r
+\r
+ //\r
+ // Release and wait for PCI controller to come out of reset.\r
+ //\r
+ SocUnitReleasePcieControllerPreWaitPllLock (PlatformType);\r
+ MicroSecondDelay (PCIEXP_DELAY_US_WAIT_PLL_LOCK);\r
+ SocUnitReleasePcieControllerPostPllLock (PlatformType);\r
+\r
+ //\r
+ // Early PCIe initialisation\r
+ //\r
+ SocUnitEarlyInitialisation ();\r
+\r
+ //\r
+ // Do North cluster early PCIe init.\r
+ //\r
+ PciExpressEarlyInit ();\r
+\r
+ return EFI_SUCCESS;\r
+}\r
+\r
--- /dev/null
+/** @file\r
+System On Chip Unit (SOCUnit) routines.\r
+\r
+Copyright (c) 2013-2015 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#include "CommonHeader.h"\r
+\r
+/** Early initialisation of the SOC Unit\r
+\r
+ @retval EFI_SUCCESS Operation success.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+SocUnitEarlyInitialisation (\r
+ VOID\r
+ )\r
+{\r
+ UINT32 NewValue;\r
+\r
+ //\r
+ // Set the mixer load resistance\r
+ //\r
+ NewValue = QNCPortIORead (QUARK_SC_PCIE_AFE_SB_PORT_ID, QUARK_PCIE_AFE_PCIE_RXPICTRL0_L0);\r
+ NewValue &= OCFGPIMIXLOAD_1_0_MASK;\r
+ QNCPortIOWrite (QUARK_SC_PCIE_AFE_SB_PORT_ID, QUARK_PCIE_AFE_PCIE_RXPICTRL0_L0, NewValue);\r
+\r
+ NewValue = QNCPortIORead (QUARK_SC_PCIE_AFE_SB_PORT_ID, QUARK_PCIE_AFE_PCIE_RXPICTRL0_L1);\r
+ NewValue &= OCFGPIMIXLOAD_1_0_MASK;\r
+ QNCPortIOWrite (QUARK_SC_PCIE_AFE_SB_PORT_ID, QUARK_PCIE_AFE_PCIE_RXPICTRL0_L1, NewValue);\r
+\r
+ return EFI_SUCCESS;\r
+}\r
+\r
+/** Tasks to release PCI controller from reset pre wait for PLL Lock.\r
+\r
+ @retval EFI_SUCCESS Operation success.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+SocUnitReleasePcieControllerPreWaitPllLock (\r
+ IN CONST EFI_PLATFORM_TYPE PlatformType\r
+ )\r
+{\r
+ UINT32 NewValue;\r
+\r
+ //\r
+ // Assert PERST# and validate time assertion time.\r
+ //\r
+ PlatformPERSTAssert (PlatformType);\r
+ ASSERT (PCIEXP_PERST_MIN_ASSERT_US <= (PCIEXP_DELAY_US_POST_CMNRESET_RESET + PCIEXP_DELAY_US_WAIT_PLL_LOCK + PCIEXP_DELAY_US_POST_SBI_RESET));\r
+\r
+ //\r
+ // PHY Common lane reset.\r
+ //\r
+ NewValue = QNCAltPortRead (QUARK_SCSS_SOC_UNIT_SB_PORT_ID, QUARK_SCSS_SOC_UNIT_SOCCLKEN_CONFIG);\r
+ NewValue |= SOCCLKEN_CONFIG_PHY_I_CMNRESET_L;\r
+ QNCAltPortWrite (QUARK_SCSS_SOC_UNIT_SB_PORT_ID, QUARK_SCSS_SOC_UNIT_SOCCLKEN_CONFIG, NewValue);\r
+\r
+ //\r
+ // Wait post common lane reset.\r
+ //\r
+ MicroSecondDelay (PCIEXP_DELAY_US_POST_CMNRESET_RESET);\r
+\r
+ //\r
+ // PHY Sideband interface reset.\r
+ // Controller main reset\r
+ //\r
+ NewValue = QNCAltPortRead (QUARK_SCSS_SOC_UNIT_SB_PORT_ID, QUARK_SCSS_SOC_UNIT_SOCCLKEN_CONFIG);\r
+ NewValue |= (SOCCLKEN_CONFIG_SBI_RST_100_CORE_B | SOCCLKEN_CONFIG_PHY_I_SIDE_RST_L);\r
+ QNCAltPortWrite (QUARK_SCSS_SOC_UNIT_SB_PORT_ID, QUARK_SCSS_SOC_UNIT_SOCCLKEN_CONFIG, NewValue);\r
+\r
+ return EFI_SUCCESS;\r
+}\r
+\r
+/** Tasks to release PCI controller from reset after PLL has locked\r
+\r
+ @retval EFI_SUCCESS Operation success.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+SocUnitReleasePcieControllerPostPllLock (\r
+ IN CONST EFI_PLATFORM_TYPE PlatformType\r
+ )\r
+{\r
+ UINT32 NewValue;\r
+\r
+ //\r
+ // Controller sideband interface reset.\r
+ //\r
+ NewValue = QNCAltPortRead (QUARK_SCSS_SOC_UNIT_SB_PORT_ID, QUARK_SCSS_SOC_UNIT_SOCCLKEN_CONFIG);\r
+ NewValue |= SOCCLKEN_CONFIG_SBI_BB_RST_B;\r
+ QNCAltPortWrite (QUARK_SCSS_SOC_UNIT_SB_PORT_ID, QUARK_SCSS_SOC_UNIT_SOCCLKEN_CONFIG, NewValue);\r
+\r
+ //\r
+ // Wait post sideband interface reset.\r
+ //\r
+ MicroSecondDelay (PCIEXP_DELAY_US_POST_SBI_RESET);\r
+\r
+ //\r
+ // Deassert PERST#.\r
+ //\r
+ PlatformPERSTDeAssert (PlatformType);\r
+\r
+ //\r
+ // Wait post de assert PERST#.\r
+ //\r
+ MicroSecondDelay (PCIEXP_DELAY_US_POST_PERST_DEASSERT);\r
+\r
+ //\r
+ // Controller primary interface reset.\r
+ //\r
+ NewValue = QNCAltPortRead (QUARK_SCSS_SOC_UNIT_SB_PORT_ID, QUARK_SCSS_SOC_UNIT_SOCCLKEN_CONFIG);\r
+ NewValue |= SOCCLKEN_CONFIG_BB_RST_B;\r
+ QNCAltPortWrite (QUARK_SCSS_SOC_UNIT_SB_PORT_ID, QUARK_SCSS_SOC_UNIT_SOCCLKEN_CONFIG, NewValue);\r
+\r
+ return EFI_SUCCESS;\r
+}\r
+\r
--- /dev/null
+#------------------------------------------------------------------------------\r
+#\r
+# Copyright (c) 2013 Intel Corporation.\r
+#\r
+# This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution. The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php\r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+# Module Name:\r
+#\r
+# Flat32.S\r
+#\r
+# Abstract:\r
+#\r
+# This is the code that goes from real-mode to protected mode.\r
+# It consumes the reset vector, configures the stack.\r
+#\r
+#\r
+#------------------------------------------------------------------------------\r
+\r
+.macro RET32\r
+ jmp *%esp\r
+.endm\r
+\r
+#\r
+# ROM/SPI/MEMORY Definitions\r
+#\r
+.equ QUARK_DDR3_MEM_BASE_ADDRESS, (0x000000000) # Memory Base Address = 0\r
+.equ QUARK_MAX_DDR3_MEM_SIZE_BYTES, (0x80000000) # DDR3 Memory Size = 2GB\r
+.equ QUARK_ESRAM_MEM_SIZE_BYTES, (0x00080000) # eSRAM Memory Size = 512K\r
+.equ QUARK_STACK_SIZE_BYTES, (0x008000) # Quark stack size = 32K\r
+\r
+#\r
+# RTC/CMOS definitions\r
+#\r
+.equ RTC_INDEX, (0x70)\r
+.equ NMI_DISABLE, (0x80) # Bit7=1 disables NMI\r
+.equ NMI_ENABLE, (0x00) # Bit7=0 disables NMI\r
+.equ RTC_DATA, (0x71)\r
+\r
+#\r
+# PCI Configuration definitions\r
+#\r
+.equ PCI_CFG, (0x80000000) # PCI configuration access mechanism\r
+.equ PCI_ADDRESS_PORT, (0xCF8)\r
+.equ PCI_DATA_PORT, (0xCFC)\r
+\r
+#\r
+# Quark PCI devices\r
+#\r
+.equ HOST_BRIDGE_PFA, (0x0000) # B0:D0:F0 (Host Bridge)\r
+.equ ILB_PFA, (0x00F8) # B0:D31:F0 (Legacy Block)\r
+\r
+#\r
+# ILB PCI Config Registers\r
+#\r
+.equ BDE, (0x0D4) # BIOS Decode Enable register\r
+.equ DECODE_ALL_REGIONS_ENABLE, (0xFF000000) # Decode all BIOS decode ranges\r
+\r
+#\r
+# iLB Reset Register\r
+#\r
+.equ ILB_RESET_REG, (0x0CF9)\r
+.equ CF9_WARM_RESET, (0x02)\r
+.equ CF9_COLD_RESET, (0x08)\r
+\r
+#\r
+# Host Bridge PCI Config Registers\r
+#\r
+.equ MESSAGE_BUS_CONTROL_REG, (0xD0) # Message Bus Control Register\r
+.equ SB_OPCODE_FIELD, (0x18) # Bit location of Opcode field\r
+.equ OPCODE_SIDEBAND_REG_READ, (0x10) # Read opcode\r
+.equ OPCODE_SIDEBAND_REG_WRITE, (0x11) # Write opcode\r
+.equ OPCODE_SIDEBAND_ALT_REG_READ, (0x06) # Alternate Read opcode\r
+.equ OPCODE_SIDEBAND_ALT_REG_WRITE, (0x07) # Alternate Write opcode\r
+.equ OPCODE_WARM_RESET_REQUEST, (0xF4) # Reset Warm\r
+.equ OPCODE_COLD_RESET_REQUEST, (0xF5) # Reset Cold\r
+.equ SB_PORT_FIELD, (0x10) # Bit location of Port ID field\r
+.equ MEMORY_ARBITER_PORT_ID, (0x00)\r
+.equ HOST_BRIDGE_PORT_ID, (0x03)\r
+.equ RMU_PORT_ID, (0x04)\r
+.equ MEMORY_MANAGER_PORT_ID, (0x05)\r
+.equ SOC_UNIT_PORT_ID, (0x31)\r
+.equ SB_ADDR_FIELD, (0x08) # Bit location of Register field\r
+.equ SB_BE_FIELD, (0x04) # Bit location of Byte Enables field\r
+.equ ALL_BYTE_EN, (0x0F) # All Byte Enables\r
+.equ MESSAGE_DATA_REG, (0xD4) # Message Data Register\r
+\r
+#\r
+# Memory Arbiter Config Registers\r
+#\r
+.equ AEC_CTRL_OFFSET, (0x00)\r
+\r
+#\r
+# Host Bridge Config Registers\r
+#\r
+.equ HMISC2_OFFSET, (0x03) # PCI configuration access mechanism\r
+.equ OR_PM_FIELD, (0x10)\r
+.equ SMI_EN, (0x00080000)\r
+\r
+.equ HMBOUND_OFFSET, (0x08)\r
+.equ HMBOUND_ADDRESS, (QUARK_DDR3_MEM_BASE_ADDRESS + QUARK_MAX_DDR3_MEM_SIZE_BYTES + QUARK_ESRAM_MEM_SIZE_BYTES)\r
+.equ HMBOUND_LOCK, (0x01)\r
+.equ HECREG_OFFSET, (0x09)\r
+.equ EC_BASE, (0xE0000000)\r
+.equ EC_ENABLE, (0x01)\r
+.equ HLEGACY_OFFSET, (0x0A)\r
+.equ NMI, (0x00004000)\r
+.equ SMI, (0x00001000)\r
+.equ INTR, (0x00000400)\r
+\r
+#\r
+# Memory Manager Config Registers\r
+#\r
+.equ ESRAMPGCTRL_BLOCK_OFFSET, (0x82)\r
+.equ BLOCK_ENABLE_PG, (0x10000000)\r
+.equ BIMRVCTL_OFFSET, (0x19)\r
+.equ ENABLE_IMR_INTERRUPT, (0x80000000)\r
+\r
+#\r
+# SOC UNIT Debug Registers\r
+#\r
+.equ CFGSTICKY_W1_OFFSET, (0x50)\r
+.equ FORCE_COLD_RESET, (0x00000001)\r
+.equ CFGSTICKY_RW_OFFSET, (0x51)\r
+.equ RESET_FOR_ESRAM_LOCK, (0x00000020)\r
+.equ RESET_FOR_HMBOUND_LOCK, (0x00000040)\r
+.equ CFGNONSTICKY_W1_OFFSET, (0x52)\r
+.equ FORCE_WARM_RESET, (0x00000001)\r
+\r
+#\r
+# CR0 cache control bit definition\r
+#\r
+.equ CR0_CACHE_DISABLE, 0x040000000\r
+.equ CR0_NO_WRITE, 0x020000000\r
+\r
+ASM_GLOBAL ASM_PFX(PcdGet32(PcdEsramStage1Base))\r
+\r
+\r
+#\r
+# Contrary to the name, this file contains 16 bit code as well.\r
+#\r
+.text\r
+#----------------------------------------------------------------------------\r
+#\r
+# Procedure: _ModuleEntryPoint\r
+#\r
+# Input: None\r
+#\r
+# Output: None\r
+#\r
+# Destroys: Assume all registers\r
+#\r
+# Description:\r
+#\r
+# Transition to non-paged flat-model protected mode from a\r
+# hard-coded GDT that provides exactly two descriptors.\r
+# This is a bare bones transition to protected mode only\r
+# used for a while in PEI and possibly DXE.\r
+#\r
+# After enabling protected mode, a far jump is executed to\r
+# transfer to PEI using the newly loaded GDT.\r
+#\r
+# Return: None\r
+#\r
+#----------------------------------------------------------------------------\r
+ASM_GLOBAL ASM_PFX(_ModuleEntryPoint)\r
+ASM_PFX(_ModuleEntryPoint):\r
+\r
+ #\r
+ # Warm Reset (INIT#) check.\r
+ #\r
+ .byte 0xbe,0x00,0xf0 #movw $0xF000, %si\r
+ .byte 0x8e,0xde #movw %si, %ds\r
+ .byte 0xbe,0xf0,0xff #movw $0xFFF0, %si\r
+ .byte 0x80,0x3c,0xea #cmpb $0xEA, (%si) # Is it warm reset ?\r
+ jne NotWarmReset # Jump if not.\r
+ .byte 0xb0,0x08 #movb $0x08, %al\r
+ .byte 0xba,0xf9,0x0c #movw $0xcf9, %dx\r
+ .byte 0xee #outb %al, %dx\r
+ .byte 0xb0,0x55 #movb $0x55, %al\r
+ .byte 0xe6,0x80 #outb %al, $0x80\r
+ jmp .\r
+NotWarmReset:\r
+ .byte 0x66,0x8b,0xe8 #movl %eax, %ebp\r
+\r
+ #\r
+ # Load the GDT table in GdtDesc\r
+ #\r
+ .byte 0x66,0xbe #movl $GdtDesc, %esi\r
+ .long GdtDesc\r
+\r
+ .byte 0x66,0x2e,0x0f,0x01,0x14 #lgdt %cs:(%si)\r
+\r
+ #\r
+ # Transition to 16 bit protected mode\r
+ #\r
+ .byte 0x0f,0x20,0xc0 #movl %cr0, %eax # Get control register 0\r
+ .byte 0x66,0x83,0xc8,0x03 #orl $0x0000003, %eax # Set PE bit (bit #0) & MP bit (bit #1)\r
+ .byte 0x0f,0x22,0xc0 #movl %eax, %cr0 # Activate protected mode\r
+\r
+ #\r
+ # Now we're in 16 bit protected mode\r
+ # Set up the selectors for 32 bit protected mode entry\r
+ #\r
+ .byte 0xb8 #movw SYS_DATA_SEL, %ax\r
+ .word SYS_DATA_SEL\r
+\r
+ .byte 0x8e,0xd8 #movw %ax, %ds\r
+ .byte 0x8e,0xc0 #movw %ax, %es\r
+ .byte 0x8e,0xe0 #movw %ax, %fs\r
+ .byte 0x8e,0xe8 #movw %ax, %gs\r
+ .byte 0x8e,0xd0 #movw %ax, %ss\r
+\r
+ #\r
+ # Transition to Flat 32 bit protected mode\r
+ # The jump to a far pointer causes the transition to 32 bit mode\r
+ #\r
+ .byte 0x66,0xbe #movl ProtectedModeEntryLinearAddress, %esi\r
+ .long ProtectedModeEntryLinearAddress\r
+ .byte 0x66,0x2e,0xff,0x2c #jmp %cs:(%esi)\r
+\r
+#\r
+# Protected mode portion initializes stack, configures cache, and calls C entry point\r
+#\r
+\r
+#----------------------------------------------------------------------------\r
+#\r
+# Procedure: ProtectedModeEntryPoint\r
+#\r
+# Input: Executing in 32 Bit Protected (flat) mode\r
+# cs: 0-4GB\r
+# ds: 0-4GB\r
+# es: 0-4GB\r
+# fs: 0-4GB\r
+# gs: 0-4GB\r
+# ss: 0-4GB\r
+#\r
+# Output: This function never returns\r
+#\r
+# Destroys:\r
+# ecx\r
+# edi\r
+# esi\r
+# esp\r
+#\r
+# Description:\r
+# Perform any essential early platform initilaisation\r
+# Setup a stack\r
+# Transfer control to EDKII code in eSRAM\r
+#\r
+#----------------------------------------------------------------------------\r
+ProtectedModeEntryPoint:\r
+ leal L0, %esp\r
+ jmp stackless_EarlyPlatformInit\r
+L0:\r
+\r
+ #\r
+ # Set up stack pointer\r
+ #\r
+ movl ASM_PFX(PcdGet32(PcdEsramStage1Base)), %esp\r
+ movl $QUARK_STACK_SIZE_BYTES, %esi\r
+ addl %esi, %esp # ESP = top of stack (stack grows downwards).\r
+\r
+ #\r
+ # Store the the BIST value in EBP\r
+ #\r
+ movl $0, %ebp # No processor BIST on Quark\r
+\r
+ #\r
+ # Push processor count to stack first, then BIST status (AP then BSP)\r
+ #\r
+ movl $1, %eax\r
+ cpuid\r
+ shrl $16, %ebx\r
+ andl $0x000000FF, %ebx\r
+ cmpb $1, %bl\r
+ jae PushProcessorCount\r
+\r
+ #\r
+ # Some processors report 0 logical processors. Effectively 0 = 1.\r
+ # So we fix up the processor count\r
+ #\r
+ incl %ebx\r
+\r
+PushProcessorCount:\r
+ pushl %ebx\r
+\r
+ #\r
+ # We need to implement a long-term solution for BIST capture. For now, we just copy BSP BIST\r
+ # for all processor threads\r
+ #\r
+ xorl %ecx, %ecx\r
+ movb %bl, %cl\r
+\r
+PushBist:\r
+ pushl %ebp\r
+ loop PushBist\r
+\r
+ #\r
+ # Pass entry point of the PEI core\r
+ #\r
+ movl $0xFFFFFFE0, %edi\r
+ pushl %ds:(%edi)\r
+\r
+ #\r
+ # Pass BFV into the PEI Core\r
+ #\r
+ movl $0xFFFFFFFC, %edi\r
+ pushl %ds:(%edi)\r
+\r
+ #\r
+ # Pass Temp Ram Base into the PEI Core\r
+ #\r
+ movl ASM_PFX(PcdGet32(PcdEsramStage1Base)), %eax\r
+ addl $(QUARK_ESRAM_MEM_SIZE_BYTES - QUARK_STACK_SIZE_BYTES), %eax\r
+ pushl %eax\r
+\r
+\r
+ #\r
+ # Pass stack size into the PEI Core\r
+ #\r
+ pushl $QUARK_STACK_SIZE_BYTES\r
+\r
+ #\r
+ # Pass Control into the PEI Core\r
+ #\r
+ call SecStartup\r
+\r
+ #\r
+ # PEI Core should never return to here, this is just to capture an invalid return.\r
+ #\r
+ jmp .\r
+\r
+#----------------------------------------------------------------------------\r
+#\r
+# Procedure: stackless_EarlyPlatformInit\r
+#\r
+# Input: esp - Return address\r
+#\r
+# Output: None\r
+#\r
+# Destroys: Assume all registers\r
+#\r
+# Description:\r
+# Any early platform initialisation required\r
+#\r
+# Return:\r
+# None\r
+#\r
+#----------------------------------------------------------------------------\r
+stackless_EarlyPlatformInit:\r
+\r
+ #\r
+ # Save return address\r
+ #\r
+ movl %esp, %ebp\r
+\r
+ #\r
+ # Ensure cache is disabled.\r
+ #\r
+ movl %cr0, %eax\r
+ orl $(CR0_CACHE_DISABLE + CR0_NO_WRITE), %eax\r
+ invd\r
+ movl %eax, %cr0\r
+\r
+ #\r
+ # Disable NMI operation\r
+ # Good convention suggests you should read back RTC data port after\r
+ # accessing the RTC index port.\r
+ #\r
+ movb $(NMI_DISABLE), %al\r
+ movw $(RTC_INDEX), %dx\r
+ outb %al, %dx\r
+ movw $(RTC_DATA), %dx\r
+ inb %dx, %al\r
+\r
+ #\r
+ # Disable SMI (Disables SMI wire, not SMI messages)\r
+ #\r
+ movl $((OPCODE_SIDEBAND_REG_READ << SB_OPCODE_FIELD) | (HOST_BRIDGE_PORT_ID << SB_PORT_FIELD) | (HMISC2_OFFSET << SB_ADDR_FIELD)), %ecx\r
+ leal L1, %esp\r
+ jmp stackless_SideBand_Read\r
+L1:\r
+ andl $(~SMI_EN), %eax\r
+ movl $((OPCODE_SIDEBAND_REG_WRITE << SB_OPCODE_FIELD) | (HOST_BRIDGE_PORT_ID << SB_PORT_FIELD) | (HMISC2_OFFSET << SB_ADDR_FIELD)), %ecx\r
+ leal L2, %esp\r
+ jmp stackless_SideBand_Write\r
+L2:\r
+\r
+ #\r
+ # Before we get going, check SOC Unit Registers to see if we are required to issue a warm/cold reset\r
+ #\r
+ movl $((OPCODE_SIDEBAND_ALT_REG_READ << SB_OPCODE_FIELD) | (SOC_UNIT_PORT_ID << SB_PORT_FIELD) | (CFGNONSTICKY_W1_OFFSET << SB_ADDR_FIELD)), %ecx\r
+ leal L3, %esp\r
+ jmp stackless_SideBand_Read\r
+L3:\r
+ andl $(FORCE_WARM_RESET), %eax\r
+ jz TestForceColdReset # Zero means bit clear, we're not requested to warm reset so continue as normal\r
+ jmp IssueWarmReset\r
+\r
+TestForceColdReset:\r
+ movl $((OPCODE_SIDEBAND_ALT_REG_READ << SB_OPCODE_FIELD) | (SOC_UNIT_PORT_ID << SB_PORT_FIELD) | (CFGNONSTICKY_W1_OFFSET << SB_ADDR_FIELD)), %ecx\r
+ leal L4, %esp\r
+ jmp stackless_SideBand_Read\r
+L4:\r
+ andl $(FORCE_COLD_RESET), %eax\r
+ jz TestHmboundLock # Zero means bit clear, we're not requested to cold reset so continue as normal\r
+ jmp IssueColdReset\r
+\r
+ #\r
+ # Before setting HMBOUND, check it's not locked\r
+ #\r
+TestHmboundLock:\r
+ movl $((OPCODE_SIDEBAND_REG_READ << SB_OPCODE_FIELD) | (HOST_BRIDGE_PORT_ID << SB_PORT_FIELD) | (HMBOUND_OFFSET << SB_ADDR_FIELD)), %ecx\r
+ leal L5, %esp\r
+ jmp stackless_SideBand_Read\r
+L5:\r
+ andl $(HMBOUND_LOCK), %eax\r
+ jz ConfigHmbound # Zero means bit clear, we have the config we want so continue as normal\r
+ #\r
+ # Failed to config - store sticky bit debug\r
+ #\r
+ movl $((OPCODE_SIDEBAND_ALT_REG_READ << SB_OPCODE_FIELD) | (SOC_UNIT_PORT_ID << SB_PORT_FIELD) | (CFGSTICKY_RW_OFFSET << SB_ADDR_FIELD)), %ecx\r
+ leal L6, %esp\r
+ jmp stackless_SideBand_Read\r
+L6:\r
+ orl $(RESET_FOR_HMBOUND_LOCK), %eax\r
+ movl $((OPCODE_SIDEBAND_ALT_REG_WRITE << SB_OPCODE_FIELD) | (SOC_UNIT_PORT_ID << SB_PORT_FIELD) | (CFGSTICKY_RW_OFFSET << SB_ADDR_FIELD)), %ecx\r
+ leal L7, %esp\r
+ jmp stackless_SideBand_Write\r
+L7:\r
+ jmp IssueWarmReset\r
+\r
+ #\r
+ # Set up the HMBOUND register\r
+ #\r
+ConfigHmbound:\r
+ movl $(HMBOUND_ADDRESS), %eax # Data (Set HMBOUND location)\r
+ movl $((OPCODE_SIDEBAND_REG_WRITE << SB_OPCODE_FIELD) | (HOST_BRIDGE_PORT_ID << SB_PORT_FIELD) | (HMBOUND_OFFSET << SB_ADDR_FIELD)), %ecx\r
+ leal L8, %esp\r
+ jmp stackless_SideBand_Write\r
+L8:\r
+\r
+ #\r
+ # Enable interrupts to Remote Management Unit when a IMR/SMM/HMBOUND violation occurs.\r
+ #\r
+ movl $(ENABLE_IMR_INTERRUPT), %eax # Data (Set interrupt enable mask)\r
+ movl $((OPCODE_SIDEBAND_REG_WRITE << SB_OPCODE_FIELD) | (MEMORY_MANAGER_PORT_ID << SB_PORT_FIELD) | (BIMRVCTL_OFFSET << SB_ADDR_FIELD)), %ecx\r
+ leal L9, %esp\r
+ jmp stackless_SideBand_Write\r
+L9:\r
+\r
+ #\r
+ # Set eSRAM address\r
+ #\r
+ movl ASM_PFX(PcdGet32(PcdEsramStage1Base)), %eax # Data (Set eSRAM location)\r
+ shr $(0x18), %eax\r
+ addl $(BLOCK_ENABLE_PG), %eax\r
+ movl $((OPCODE_SIDEBAND_REG_WRITE << SB_OPCODE_FIELD) | (MEMORY_MANAGER_PORT_ID << SB_PORT_FIELD) | (ESRAMPGCTRL_BLOCK_OFFSET << SB_ADDR_FIELD)), %ecx\r
+ leal L10, %esp\r
+ jmp stackless_SideBand_Write\r
+L10:\r
+\r
+ #\r
+ # Check that we're not blocked from setting the config that we want.\r
+ #\r
+ movl $((OPCODE_SIDEBAND_REG_READ << SB_OPCODE_FIELD) | (MEMORY_MANAGER_PORT_ID << SB_PORT_FIELD) | (ESRAMPGCTRL_BLOCK_OFFSET << SB_ADDR_FIELD)), %ecx\r
+ leal L11, %esp\r
+ jmp stackless_SideBand_Read\r
+L11:\r
+ andl $(BLOCK_ENABLE_PG), %eax\r
+ jnz ConfigPci # Non-zero means bit set, we have the config we want so continue as normal\r
+ #\r
+ # Failed to config - store sticky bit debug\r
+ #\r
+ movl $((OPCODE_SIDEBAND_ALT_REG_READ << SB_OPCODE_FIELD) | (SOC_UNIT_PORT_ID << SB_PORT_FIELD) | (CFGSTICKY_RW_OFFSET << SB_ADDR_FIELD)), %ecx\r
+ leal L12, %esp\r
+ jmp stackless_SideBand_Read\r
+L12:\r
+ orl $(RESET_FOR_ESRAM_LOCK), %eax # Set the bit we're interested in\r
+ movl $((OPCODE_SIDEBAND_ALT_REG_WRITE << SB_OPCODE_FIELD) | (SOC_UNIT_PORT_ID << SB_PORT_FIELD) | (CFGSTICKY_RW_OFFSET << SB_ADDR_FIELD)), %ecx\r
+ leal L13, %esp\r
+ jmp stackless_SideBand_Write\r
+L13:\r
+ jmp IssueWarmReset\r
+\r
+ #\r
+ # Enable PCIEXBAR\r
+ #\r
+ConfigPci:\r
+ movl $(EC_BASE + EC_ENABLE), %eax # Data\r
+ movl $((OPCODE_SIDEBAND_REG_WRITE << SB_OPCODE_FIELD) | (MEMORY_ARBITER_PORT_ID << SB_PORT_FIELD) | (AEC_CTRL_OFFSET << SB_ADDR_FIELD)), %ecx\r
+ leal L14, %esp\r
+ jmp stackless_SideBand_Write\r
+L14:\r
+\r
+ movl $(EC_BASE + EC_ENABLE), %eax # Data\r
+ movl $((OPCODE_SIDEBAND_REG_WRITE << SB_OPCODE_FIELD) | (HOST_BRIDGE_PORT_ID << SB_PORT_FIELD) | (HECREG_OFFSET << SB_ADDR_FIELD)), %ecx\r
+ leal L15, %esp\r
+ jmp stackless_SideBand_Write\r
+L15:\r
+\r
+ #\r
+ # Open up full 8MB SPI decode\r
+ #\r
+ movl $(PCI_CFG | (ILB_PFA << 8) | BDE), %ebx # PCI Configuration address\r
+ movl $(DECODE_ALL_REGIONS_ENABLE), %eax\r
+ leal L16, %esp\r
+ jmp stackless_PCIConfig_Write\r
+L16:\r
+\r
+ #\r
+ # Enable NMI operation\r
+ # Good convention suggests you should read back RTC data port after\r
+ # accessing the RTC index port.\r
+ #\r
+ movb $(NMI_ENABLE), %al\r
+ movw $(RTC_INDEX), %dx\r
+ outb %al, %dx\r
+ movw $(RTC_DATA), %dx\r
+ inb %dx, %al\r
+\r
+ #\r
+ # Clear Host Bridge SMI, NMI, INTR fields\r
+ #\r
+ movl $((OPCODE_SIDEBAND_REG_READ << SB_OPCODE_FIELD) | (HOST_BRIDGE_PORT_ID << SB_PORT_FIELD) | (HLEGACY_OFFSET << SB_ADDR_FIELD)), %ecx\r
+ leal L21, %esp\r
+ jmp stackless_SideBand_Read\r
+L21:\r
+ andl $~(NMI + SMI + INTR), %eax # Clear NMI, SMI, INTR fields\r
+ movl $((OPCODE_SIDEBAND_REG_WRITE << SB_OPCODE_FIELD) | (HOST_BRIDGE_PORT_ID << SB_PORT_FIELD) | (HLEGACY_OFFSET << SB_ADDR_FIELD)), %ecx\r
+ leal L22, %esp\r
+ jmp stackless_SideBand_Write\r
+L22:\r
+\r
+ #\r
+ # Restore return address\r
+ #\r
+ movl %ebp, %esp\r
+ RET32\r
+\r
+IssueWarmReset:\r
+ #\r
+ # Issue Warm Reset request to Remote Management Unit via iLB\r
+ #\r
+ movw $(CF9_WARM_RESET), %ax\r
+ movw $(ILB_RESET_REG), %dx\r
+ outw %ax, %dx\r
+ jmp . # Stay here until we are reset.\r
+\r
+IssueColdReset:\r
+ #\r
+ # Issue Cold Reset request to Remote Management Unit via iLB\r
+ #\r
+ movw $(CF9_COLD_RESET), %ax\r
+ movw $(ILB_RESET_REG), %dx\r
+ outw %ax, %dx\r
+ jmp . # Stay here until we are reset.\r
+\r
+#----------------------------------------------------------------------------\r
+#\r
+# Procedure: stackless_SideBand_Read\r
+#\r
+# Input: esp - return address\r
+# ecx[15:8] - Register offset\r
+# ecx[23:16] - Port ID\r
+# ecx[31:24] - Opcode\r
+#\r
+# Output: eax - Data read\r
+#\r
+# Destroys:\r
+# eax\r
+# ebx\r
+# cl\r
+# esi\r
+#\r
+# Description:\r
+# Perform requested sideband read\r
+#\r
+#----------------------------------------------------------------------------\r
+stackless_SideBand_Read:\r
+\r
+ movl %esp, %esi # Save the return address\r
+\r
+ #\r
+ # Load the SideBand Packet Register to generate the transaction\r
+ #\r
+ movl $((PCI_CFG) | (HOST_BRIDGE_PFA << 8) | (MESSAGE_BUS_CONTROL_REG)), %ebx # PCI Configuration address\r
+ movb $(ALL_BYTE_EN << SB_BE_FIELD), %cl # Set all Byte Enable bits\r
+ xchgl %ecx, %eax\r
+ leal L17, %esp\r
+ jmp stackless_PCIConfig_Write\r
+L17:\r
+ xchgl %ecx, %eax\r
+\r
+ #\r
+ # Read the SideBand Data Register\r
+ #\r
+ movl $((PCI_CFG) | (HOST_BRIDGE_PFA << 8) | (MESSAGE_DATA_REG)), %ebx # PCI Configuration address\r
+ leal L18, %esp\r
+ jmp stackless_PCIConfig_Read\r
+L18:\r
+\r
+ movl %esi, %esp # Restore the return address\r
+ RET32\r
+\r
+\r
+#----------------------------------------------------------------------------\r
+#\r
+# Procedure: stackless_SideBand_Write\r
+#\r
+# Input: esp - return address\r
+# eax - Data\r
+# ecx[15:8] - Register offset\r
+# ecx[23:16] - Port ID\r
+# ecx[31:24] - Opcode\r
+#\r
+# Output: None\r
+#\r
+# Destroys:\r
+# ebx\r
+# cl\r
+# esi\r
+#\r
+# Description:\r
+# Perform requested sideband write\r
+#\r
+#\r
+#----------------------------------------------------------------------------\r
+stackless_SideBand_Write:\r
+\r
+ movl %esp, %esi # Save the return address\r
+\r
+ #\r
+ # Load the SideBand Data Register with the data\r
+ #\r
+ movl $((PCI_CFG) | (HOST_BRIDGE_PFA << 8) | (MESSAGE_DATA_REG)), %ebx # PCI Configuration address\r
+ leal L19, %esp\r
+ jmp stackless_PCIConfig_Write\r
+L19:\r
+\r
+ #\r
+ # Load the SideBand Packet Register to generate the transaction\r
+ #\r
+ movl $((PCI_CFG) | (HOST_BRIDGE_PFA << 8) | (MESSAGE_BUS_CONTROL_REG)), %ebx # PCI Configuration address\r
+ movb $(ALL_BYTE_EN << SB_BE_FIELD), %cl # Set all Byte Enable bits\r
+ xchgl %ecx, %eax\r
+ leal L20, %esp\r
+ jmp stackless_PCIConfig_Write\r
+L20:\r
+ xchgl %ecx, %eax\r
+\r
+ movl %esi, %esp # Restore the return address\r
+ RET32\r
+\r
+\r
+#----------------------------------------------------------------------------\r
+#\r
+# Procedure: stackless_PCIConfig_Write\r
+#\r
+# Input: esp - return address\r
+# eax - Data to write\r
+# ebx - PCI Config Address\r
+#\r
+# Output: None\r
+#\r
+# Destroys:\r
+# dx\r
+#\r
+# Description:\r
+# Perform a DWORD PCI Configuration write\r
+#\r
+#----------------------------------------------------------------------------\r
+stackless_PCIConfig_Write:\r
+\r
+ #\r
+ # Write the PCI Config Address to the address port\r
+ #\r
+ xchgl %ebx, %eax\r
+ movw $(PCI_ADDRESS_PORT), %dx\r
+ outl %eax, %dx\r
+ xchgl %ebx, %eax\r
+\r
+ #\r
+ # Write the PCI DWORD Data to the data port\r
+ #\r
+ movw $(PCI_DATA_PORT), %dx\r
+ outl %eax, %dx\r
+\r
+ RET32\r
+\r
+\r
+#----------------------------------------------------------------------------\r
+#\r
+# Procedure: stackless_PCIConfig_Read\r
+#\r
+# Input: esp - return address\r
+# ebx - PCI Config Address\r
+#\r
+# Output: eax - Data read\r
+#\r
+# Destroys:\r
+# eax\r
+# dx\r
+#\r
+# Description:\r
+# Perform a DWORD PCI Configuration read\r
+#\r
+#----------------------------------------------------------------------------\r
+stackless_PCIConfig_Read:\r
+\r
+ #\r
+ # Write the PCI Config Address to the address port\r
+ #\r
+ xchgl %ebx, %eax\r
+ movw $(PCI_ADDRESS_PORT), %dx\r
+ outl %eax, %dx\r
+ xchgl %ebx, %eax\r
+\r
+ #\r
+ # Read the PCI DWORD Data from the data port\r
+ #\r
+ movw $(PCI_DATA_PORT), %dx\r
+ inl %dx, %eax\r
+\r
+ RET32\r
+\r
+\r
+#\r
+# ROM-based Global-Descriptor Table for the Tiano PEI Phase\r
+#\r
+.align 16\r
+#\r
+# GDT[0]: 000h: Null entry, never used.\r
+#\r
+\r
+GDT_BASE:\r
+BootGdtTable:\r
+# null descriptor\r
+.equ NULL_SEL, . - GDT_BASE # Selector [0]\r
+ .word 0 # limit 15:0\r
+ .word 0 # base 15:0\r
+ .byte 0 # base 23:16\r
+ .byte 0 # type\r
+ .byte 0 # limit 19:16, flags\r
+ .byte 0 # base 31:24\r
+\r
+# linear data segment descriptor\r
+.equ LINEAR_SEL, . - GDT_BASE # Selector [0x8]\r
+ .word 0xFFFF # limit 0xFFFFF\r
+ .word 0 # base 0\r
+ .byte 0\r
+ .byte 0x92 # present, ring 0, data, expand-up, writable\r
+ .byte 0xCF # page-granular, 32-bit\r
+ .byte 0\r
+\r
+# linear code segment descriptor\r
+.equ LINEAR_CODE_SEL, . - GDT_BASE # Selector [0x10]\r
+ .word 0xFFFF # limit 0xFFFFF\r
+ .word 0 # base 0\r
+ .byte 0\r
+ .byte 0x9A # present, ring 0, data, expand-up, writable\r
+ .byte 0xCF # page-granular, 32-bit\r
+ .byte 0\r
+\r
+# system data segment descriptor\r
+.equ SYS_DATA_SEL, . - GDT_BASE # Selector [0x18]\r
+ .word 0xFFFF # limit 0xFFFFF\r
+ .word 0 # base 0\r
+ .byte 0\r
+ .byte 0x92 # present, ring 0, data, expand-up, writable\r
+ .byte 0xCF # page-granular, 32-bit\r
+ .byte 0\r
+\r
+# system code segment descriptor\r
+.equ SYS_CODE_SEL, . - GDT_BASE\r
+ .word 0xFFFF # limit 0xFFFFF\r
+ .word 0 # base 0\r
+ .byte 0\r
+ .byte 0x9A # present, ring 0, data, expand-up, writable\r
+ .byte 0xCF # page-granular, 32-bit\r
+ .byte 0\r
+\r
+# spare segment descriptor\r
+.equ SYS16_CODE_SEL, . - GDT_BASE\r
+ .word 0xffff # limit 0xFFFFF\r
+ .word 0 # base 0\r
+ .byte 0x0f\r
+ .byte 0x9b # present, ring 0, data, expand-up, writable\r
+ .byte 0 # page-granular, 32-bit\r
+ .byte 0\r
+\r
+# spare segment descriptor\r
+.equ SYS16_DATA_SEL, . - GDT_BASE\r
+ .word 0xffff # limit 0xFFFFF\r
+ .word 0 # base 0\r
+ .byte 0\r
+ .byte 0x93 # present, ring 0, data, expand-up, not-writable\r
+ .byte 0 # page-granular, 32-bit\r
+ .byte 0\r
+\r
+# spare segment descriptor\r
+.equ SPARE5_SEL, . - GDT_BASE\r
+ .word 0 # limit 0xFFFFF\r
+ .word 0 # base 0\r
+ .byte 0\r
+ .byte 0 # present, ring 0, data, expand-up, writable\r
+ .byte 0 # page-granular, 32-bit\r
+ .byte 0\r
+.equ GDT_SIZE, . - GDT_BASE\r
+\r
+#\r
+# GDT Descriptor\r
+#\r
+GdtDesc: # GDT descriptor\r
+ .word GDT_SIZE - 1\r
+ .long BootGdtTable\r
+\r
+ProtectedModeEntryLinearAddress:\r
+ProtectedModeEntryLinearOffset:\r
+ .long ProtectedModeEntryPoint\r
+ .word LINEAR_CODE_SEL\r
--- /dev/null
+;------------------------------------------------------------------------------\r
+;\r
+; Copyright (c) 2013-2015 Intel Corporation.\r
+;\r
+; This program and the accompanying materials\r
+; are licensed and made available under the terms and conditions of the BSD License\r
+; which accompanies this distribution. The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+; Module Name:\r
+;\r
+; Flat32.asm\r
+;\r
+; Abstract:\r
+;\r
+; This is the code that goes from real-mode to protected mode.\r
+; It consumes the reset vector, configures the stack.\r
+;\r
+;\r
+;------------------------------------------------------------------------------\r
+\r
+\r
+;\r
+; Define assembler characteristics\r
+;\r
+.586p\r
+.model flat, c\r
+\r
+;\r
+; Include processor definitions\r
+;\r
+\r
+INCLUDE Platform.inc\r
+\r
+\r
+;\r
+; CR0 cache control bit definition\r
+;\r
+CR0_CACHE_DISABLE EQU 040000000h\r
+CR0_NO_WRITE EQU 020000000h\r
+\r
+;\r
+; External and public declarations\r
+; TopOfStack is used by C code\r
+; SecStartup is the entry point to the C code\r
+; Neither of these names can be modified without\r
+; updating the C code.\r
+;\r
+EXTRN PlatformSecLibStartup: NEAR\r
+EXTERNDEF C PcdGet32 (PcdEsramStage1Base):DWORD\r
+\r
+;\r
+; Contrary to the name, this file contains 16 bit code as well.\r
+;\r
+_TEXT_REALMODE SEGMENT PARA PUBLIC USE16 'CODE'\r
+ ASSUME CS:_TEXT_REALMODE, DS:_TEXT_REALMODE\r
+\r
+;----------------------------------------------------------------------------\r
+;\r
+; Procedure: _ModuleEntryPoint\r
+;\r
+; Input: None\r
+;\r
+; Output: None\r
+;\r
+; Destroys: Assume all registers\r
+;\r
+; Description:\r
+;\r
+; Transition to non-paged flat-model protected mode from a\r
+; hard-coded GDT that provides exactly two descriptors.\r
+; This is a bare bones transition to protected mode only\r
+; used for a while in PEI and possibly DXE.\r
+;\r
+; After enabling protected mode, a far jump is executed to\r
+; transfer to PEI using the newly loaded GDT.\r
+;\r
+; Return: None\r
+;\r
+;----------------------------------------------------------------------------\r
+align 16\r
+_ModuleEntryPoint PROC C PUBLIC\r
+\r
+ ;\r
+ ; Warm Reset (INIT#) check.\r
+ ;\r
+ mov si, 0F000h\r
+ mov ds, si\r
+ mov si, 0FFF0h\r
+ cmp BYTE PTR [si], 0EAh ; Is it warm reset ?\r
+ jne NotWarmReset ; JIf not.\r
+\r
+ mov al, 08\r
+ mov dx, 0cf9h\r
+ out dx, al\r
+ mov al, 055h\r
+ out 080h, al;\r
+ jmp $\r
+NotWarmReset:\r
+\r
+ ;\r
+ ; Load the GDT table in GdtDesc\r
+ ;\r
+ mov esi, OFFSET GdtDesc\r
+ db 66h\r
+ lgdt fword ptr cs:[si]\r
+\r
+ ;\r
+ ; Transition to 16 bit protected mode\r
+ ;\r
+ mov eax, cr0 ; Get control register 0\r
+ or eax, 00000003h ; Set PE bit (bit #0) & MP bit (bit #1)\r
+ mov cr0, eax ; Activate protected mode\r
+\r
+ ;\r
+ ; Now we're in 16 bit protected mode\r
+ ; Set up the selectors for 32 bit protected mode entry\r
+ ;\r
+ mov ax, SYS_DATA_SEL\r
+ mov ds, ax\r
+ mov es, ax\r
+ mov fs, ax\r
+ mov gs, ax\r
+ mov ss, ax\r
+\r
+ ;\r
+ ; Transition to Flat 32 bit protected mode\r
+ ; The jump to a far pointer causes the transition to 32 bit mode\r
+ ;\r
+ mov esi, offset ProtectedModeEntryLinearAddress\r
+ jmp fword ptr cs:[si]\r
+\r
+_ModuleEntryPoint ENDP\r
+\r
+_TEXT_REALMODE ENDS\r
+\r
+.code\r
+;\r
+; Protected mode portion initializes stack, configures cache, and calls C entry point\r
+;\r
+\r
+;----------------------------------------------------------------------------\r
+;\r
+; Procedure: ProtectedModeEntryPoint\r
+;\r
+; Input: Executing in 32 Bit Protected (flat) mode\r
+; cs: 0-4GB\r
+; ds: 0-4GB\r
+; es: 0-4GB\r
+; fs: 0-4GB\r
+; gs: 0-4GB\r
+; ss: 0-4GB\r
+;\r
+; Output: This function never returns\r
+;\r
+; Destroys:\r
+; ecx\r
+; edi\r
+; esi\r
+; esp\r
+;\r
+; Description:\r
+; Perform any essential early platform initilaisation\r
+; Setup a stack\r
+; Call the main EDKII Sec C code\r
+;\r
+;----------------------------------------------------------------------------\r
+\r
+ProtectedModeEntryPoint PROC NEAR C PUBLIC\r
+\r
+ JMP32 stackless_EarlyPlatformInit\r
+\r
+ ;\r
+ ; Set up stack pointer\r
+ ;\r
+ mov esp, PcdGet32(PcdEsramStage1Base)\r
+ mov esi, QUARK_ESRAM_MEM_SIZE_BYTES\r
+ add esp, esi ; ESP = top of stack (stack grows downwards).\r
+\r
+ ;\r
+ ; Store the the BIST value in EBP\r
+ ;\r
+ mov ebp, 00h ; No processor BIST on Quark\r
+\r
+ ;\r
+ ; Push processor count to stack first, then BIST status (AP then BSP)\r
+ ;\r
+ mov eax, 1\r
+ cpuid\r
+ shr ebx, 16\r
+ and ebx, 0000000FFh\r
+ cmp bl, 1\r
+ jae PushProcessorCount\r
+\r
+ ;\r
+ ; Some processors report 0 logical processors. Effectively 0 = 1.\r
+ ; So we fix up the processor count\r
+ ;\r
+ inc ebx\r
+\r
+PushProcessorCount:\r
+ push ebx\r
+\r
+ ;\r
+ ; We need to implement a long-term solution for BIST capture. For now, we just copy BSP BIST\r
+ ; for all processor threads\r
+ ;\r
+ xor ecx, ecx\r
+ mov cl, bl\r
+PushBist:\r
+ push ebp\r
+ loop PushBist\r
+\r
+ ;\r
+ ; Pass Control into the PEI Core\r
+ ;\r
+ call PlatformSecLibStartup\r
+\r
+ ;\r
+ ; PEI Core should never return to here, this is just to capture an invalid return.\r
+ ;\r
+ jmp $\r
+\r
+ProtectedModeEntryPoint ENDP\r
+\r
+;----------------------------------------------------------------------------\r
+;\r
+; Procedure: stackless_EarlyPlatformInit\r
+;\r
+; Input: esp - Return address\r
+;\r
+; Output: None\r
+;\r
+; Destroys:\r
+; eax\r
+; ecx\r
+; dx\r
+; ebp\r
+;\r
+; Description:\r
+; Any essential early platform initialisation required:\r
+; (1) Disable Cache\r
+; (2) Disable NMI's/SMI's\r
+; (3) Setup HMBOUND (defines what memory accesses go to MMIO/RAM)\r
+; (4) Setup eSRAM (provide early memory to the system)\r
+; (5) Setup PCIEXBAR access mechanism\r
+; (6) Open up full SPI flash decode\r
+;\r
+;----------------------------------------------------------------------------\r
+stackless_EarlyPlatformInit PROC NEAR C PUBLIC\r
+\r
+ ;\r
+ ; Save return address\r
+ ;\r
+ mov ebp, esp\r
+\r
+ ;\r
+ ; Ensure cache is disabled.\r
+ ;\r
+ mov eax, cr0\r
+ or eax, CR0_CACHE_DISABLE + CR0_NO_WRITE\r
+ invd\r
+ mov cr0, eax\r
+\r
+ ;\r
+ ; Disable NMI\r
+ ; Good convention suggests you should read back RTC data port after\r
+ ; accessing the RTC index port.\r
+ ;\r
+ mov al, NMI_DISABLE\r
+ mov dx, RTC_INDEX\r
+ out dx, al\r
+ mov dx, RTC_DATA\r
+ in al, dx\r
+\r
+ ;\r
+ ; Disable SMI (Disables SMI wire, not SMI messages)\r
+ ;\r
+ mov ecx, (OPCODE_SIDEBAND_REG_READ SHL SB_OPCODE_FIELD) OR (HOST_BRIDGE_PORT_ID SHL SB_PORT_FIELD) OR (HMISC2_OFFSET SHL SB_ADDR_FIELD)\r
+ JMP32 stackless_SideBand_Read\r
+ and eax, NOT (SMI_EN)\r
+ mov ecx, (OPCODE_SIDEBAND_REG_WRITE SHL SB_OPCODE_FIELD) OR (HOST_BRIDGE_PORT_ID SHL SB_PORT_FIELD) OR (HMISC2_OFFSET SHL SB_ADDR_FIELD)\r
+ JMP32 stackless_SideBand_Write\r
+\r
+ ;\r
+ ; Before we get going, check SOC Unit Registers to see if we are required to issue a warm/cold reset\r
+ ;\r
+ mov ecx, (OPCODE_SIDEBAND_ALT_REG_READ SHL SB_OPCODE_FIELD) OR (SOC_UNIT_PORT_ID SHL SB_PORT_FIELD) OR (CFGNONSTICKY_W1_OFFSET SHL SB_ADDR_FIELD)\r
+ JMP32 stackless_SideBand_Read\r
+ and eax, FORCE_WARM_RESET\r
+ jz TestForceColdReset ; Zero means bit clear, we're not requested to warm reset so continue as normal\r
+ jmp IssueWarmReset\r
+\r
+TestForceColdReset:\r
+ mov ecx, (OPCODE_SIDEBAND_ALT_REG_READ SHL SB_OPCODE_FIELD) OR (SOC_UNIT_PORT_ID SHL SB_PORT_FIELD) OR (CFGSTICKY_W1_OFFSET SHL SB_ADDR_FIELD)\r
+ JMP32 stackless_SideBand_Read\r
+ and eax, FORCE_COLD_RESET\r
+ jz TestHmboundLock ; Zero means bit clear, we're not requested to cold reset so continue as normal\r
+ jmp IssueColdReset\r
+\r
+ ;\r
+ ; Before setting HMBOUND, check it's not locked\r
+ ;\r
+TestHmboundLock:\r
+ mov ecx, (OPCODE_SIDEBAND_REG_READ SHL SB_OPCODE_FIELD) OR (HOST_BRIDGE_PORT_ID SHL SB_PORT_FIELD) OR (HMBOUND_OFFSET SHL SB_ADDR_FIELD)\r
+ JMP32 stackless_SideBand_Read\r
+ and eax, HMBOUND_LOCK\r
+ jz ConfigHmbound ; Zero means bit clear, we have the config we want so continue as normal\r
+ ;\r
+ ; Failed to config - store sticky bit debug\r
+ ;\r
+ mov ecx, (OPCODE_SIDEBAND_ALT_REG_READ SHL SB_OPCODE_FIELD) OR (SOC_UNIT_PORT_ID SHL SB_PORT_FIELD) OR (CFGSTICKY_RW_OFFSET SHL SB_ADDR_FIELD)\r
+ JMP32 stackless_SideBand_Read\r
+ or eax, RESET_FOR_HMBOUND_LOCK ; Set the bit we're interested in\r
+ mov ecx, (OPCODE_SIDEBAND_ALT_REG_WRITE SHL SB_OPCODE_FIELD) OR (SOC_UNIT_PORT_ID SHL SB_PORT_FIELD) OR (CFGSTICKY_RW_OFFSET SHL SB_ADDR_FIELD)\r
+ JMP32 stackless_SideBand_Write\r
+ jmp IssueWarmReset\r
+\r
+ ;\r
+ ; Set up the HMBOUND register\r
+ ;\r
+ConfigHmbound:\r
+ mov eax, HMBOUND_ADDRESS ; Data (Set HMBOUND location)\r
+ mov ecx, (OPCODE_SIDEBAND_REG_WRITE SHL SB_OPCODE_FIELD) OR (HOST_BRIDGE_PORT_ID SHL SB_PORT_FIELD) OR (HMBOUND_OFFSET SHL SB_ADDR_FIELD)\r
+ JMP32 stackless_SideBand_Write\r
+\r
+ ;\r
+ ; Enable interrupts to Remote Management Unit when a IMR/SMM/HMBOUND violation occurs.\r
+ ;\r
+ mov eax, ENABLE_IMR_INTERRUPT ; Data (Set interrupt enable mask)\r
+ mov ecx, (OPCODE_SIDEBAND_REG_WRITE SHL SB_OPCODE_FIELD) OR (MEMORY_MANAGER_PORT_ID SHL SB_PORT_FIELD) OR (BIMRVCTL_OFFSET SHL SB_ADDR_FIELD)\r
+ JMP32 stackless_SideBand_Write\r
+\r
+ ;\r
+ ; Set eSRAM address\r
+ ;\r
+ mov eax, PcdGet32 (PcdEsramStage1Base) ; Data (Set eSRAM location)\r
+ shr eax, 18h ; Data (Set eSRAM location)\r
+ add eax, BLOCK_ENABLE_PG\r
+ mov ecx, (OPCODE_SIDEBAND_REG_WRITE SHL SB_OPCODE_FIELD) OR (MEMORY_MANAGER_PORT_ID SHL SB_PORT_FIELD) OR (ESRAMPGCTRL_BLOCK_OFFSET SHL SB_ADDR_FIELD)\r
+ JMP32 stackless_SideBand_Write\r
+ ;\r
+ ; Check that we're not blocked from setting the config that we want.\r
+ ;\r
+ mov ecx, (OPCODE_SIDEBAND_REG_READ SHL SB_OPCODE_FIELD) OR (MEMORY_MANAGER_PORT_ID SHL SB_PORT_FIELD) OR (ESRAMPGCTRL_BLOCK_OFFSET SHL SB_ADDR_FIELD)\r
+ JMP32 stackless_SideBand_Read\r
+ and eax, BLOCK_ENABLE_PG\r
+ jnz ConfigPci ; Non-zero means bit set, we have the config we want so continue as normal\r
+ ;\r
+ ; Failed to config - store sticky bit debug\r
+ ;\r
+ mov ecx, (OPCODE_SIDEBAND_ALT_REG_READ SHL SB_OPCODE_FIELD) OR (SOC_UNIT_PORT_ID SHL SB_PORT_FIELD) OR (CFGSTICKY_RW_OFFSET SHL SB_ADDR_FIELD)\r
+ JMP32 stackless_SideBand_Read\r
+ or eax, RESET_FOR_ESRAM_LOCK ; Set the bit we're interested in\r
+ mov ecx, (OPCODE_SIDEBAND_ALT_REG_WRITE SHL SB_OPCODE_FIELD) OR (SOC_UNIT_PORT_ID SHL SB_PORT_FIELD) OR (CFGSTICKY_RW_OFFSET SHL SB_ADDR_FIELD)\r
+ JMP32 stackless_SideBand_Write\r
+ jmp IssueWarmReset\r
+\r
+ ;\r
+ ; Enable PCIEXBAR\r
+ ;\r
+ConfigPci:\r
+ mov eax, (EC_BASE + EC_ENABLE) ; Data\r
+ mov ecx, (OPCODE_SIDEBAND_REG_WRITE SHL SB_OPCODE_FIELD) OR (MEMORY_ARBITER_PORT_ID SHL SB_PORT_FIELD) OR (AEC_CTRL_OFFSET SHL SB_ADDR_FIELD)\r
+ JMP32 stackless_SideBand_Write\r
+\r
+ mov eax, (EC_BASE + EC_ENABLE) ; Data\r
+ mov ecx, (OPCODE_SIDEBAND_REG_WRITE SHL SB_OPCODE_FIELD) OR (HOST_BRIDGE_PORT_ID SHL SB_PORT_FIELD) OR (HECREG_OFFSET SHL SB_ADDR_FIELD)\r
+ JMP32 stackless_SideBand_Write\r
+\r
+ ;\r
+ ; Open up full 8MB SPI decode\r
+ ;\r
+ mov ebx, PCI_CFG OR (ILB_PFA SHL 8) OR BDE ; PCI Configuration address\r
+ mov eax, DECODE_ALL_REGIONS_ENABLE\r
+ JMP32 stackless_PCIConfig_Write\r
+\r
+ ;\r
+ ; Enable NMI operation\r
+ ; Good convention suggests you should read back RTC data port after\r
+ ; accessing the RTC index port.\r
+ ;\r
+ mov al, NMI_ENABLE\r
+ mov dx, RTC_INDEX\r
+ out dx, al\r
+ mov dx, RTC_DATA\r
+ in al, dx\r
+\r
+ ;\r
+ ; Clear Host Bridge SMI, NMI, INTR fields\r
+ ;\r
+ mov ecx, (OPCODE_SIDEBAND_REG_READ SHL SB_OPCODE_FIELD) OR (HOST_BRIDGE_PORT_ID SHL SB_PORT_FIELD) OR (HLEGACY_OFFSET SHL SB_ADDR_FIELD)\r
+ JMP32 stackless_SideBand_Read\r
+ and eax, NOT(NMI + SMI + INTR) ; Clear NMI, SMI, INTR fields\r
+ mov ecx, (OPCODE_SIDEBAND_REG_WRITE SHL SB_OPCODE_FIELD) OR (HOST_BRIDGE_PORT_ID SHL SB_PORT_FIELD) OR (HLEGACY_OFFSET SHL SB_ADDR_FIELD)\r
+ JMP32 stackless_SideBand_Write\r
+\r
+ ;\r
+ ; Restore return address\r
+ ;\r
+ mov esp, ebp\r
+ RET32\r
+\r
+IssueWarmReset:\r
+ ;\r
+ ; Issue Warm Reset request to Remote Management Unit via iLB\r
+ ;\r
+ mov ax, CF9_WARM_RESET\r
+ mov dx, ILB_RESET_REG\r
+ out dx, ax\r
+ jmp $ ; Stay here until we are reset.\r
+\r
+IssueColdReset:\r
+ ;\r
+ ; Issue Cold Reset request to Remote Management Unit via iLB\r
+ ;\r
+ mov ax, CF9_COLD_RESET\r
+ mov dx, ILB_RESET_REG\r
+ out dx, ax\r
+ jmp $ ; Stay here until we are reset.\r
+\r
+stackless_EarlyPlatformInit ENDP\r
+\r
+;----------------------------------------------------------------------------\r
+;\r
+; Procedure: stackless_SideBand_Read\r
+;\r
+; Input: esp - return address\r
+; ecx[15:8] - Register offset\r
+; ecx[23:16] - Port ID\r
+; ecx[31:24] - Opcode\r
+;\r
+; Output: eax - Data read\r
+;\r
+; Destroys:\r
+; eax\r
+; ebx\r
+; cl\r
+; esi\r
+;\r
+; Description:\r
+; Perform requested sideband read\r
+;\r
+;----------------------------------------------------------------------------\r
+stackless_SideBand_Read PROC NEAR C PUBLIC\r
+\r
+ mov esi, esp ; Save the return address\r
+\r
+ ;\r
+ ; Load the SideBand Packet Register to generate the transaction\r
+ ;\r
+ mov ebx, PCI_CFG OR (HOST_BRIDGE_PFA SHL 8) OR MESSAGE_BUS_CONTROL_REG ; PCI Configuration address\r
+ mov cl, (ALL_BYTE_EN SHL SB_BE_FIELD) ; Set all Byte Enable bits\r
+ xchg eax, ecx\r
+ JMP32 stackless_PCIConfig_Write\r
+ xchg eax, ecx\r
+\r
+ ;\r
+ ; Read the SideBand Data Register\r
+ ;\r
+ mov ebx, PCI_CFG OR (HOST_BRIDGE_PFA SHL 8) OR MESSAGE_DATA_REG ; PCI Configuration address\r
+ JMP32 stackless_PCIConfig_Read\r
+\r
+ mov esp, esi ; Restore the return address\r
+ RET32\r
+\r
+stackless_SideBand_Read ENDP\r
+\r
+;----------------------------------------------------------------------------\r
+;\r
+; Procedure: stackless_SideBand_Write\r
+;\r
+; Input: esp - return address\r
+; eax - Data\r
+; ecx[15:8] - Register offset\r
+; ecx[23:16] - Port ID\r
+; ecx[31:24] - Opcode\r
+;\r
+; Output: None\r
+;\r
+; Destroys:\r
+; ebx\r
+; cl\r
+; esi\r
+;\r
+; Description:\r
+; Perform requested sideband write\r
+;\r
+;\r
+;----------------------------------------------------------------------------\r
+stackless_SideBand_Write PROC NEAR C PUBLIC\r
+\r
+ mov esi, esp ; Save the return address\r
+\r
+ ;\r
+ ; Load the SideBand Data Register with the data\r
+ ;\r
+ mov ebx, PCI_CFG OR (HOST_BRIDGE_PFA SHL 8) OR MESSAGE_DATA_REG ; PCI Configuration address\r
+ JMP32 stackless_PCIConfig_Write\r
+\r
+ ;\r
+ ; Load the SideBand Packet Register to generate the transaction\r
+ ;\r
+ mov ebx, PCI_CFG OR (HOST_BRIDGE_PFA SHL 8) OR MESSAGE_BUS_CONTROL_REG ; PCI Configuration address\r
+ mov cl, (ALL_BYTE_EN SHL SB_BE_FIELD) ; Set all Byte Enable bits\r
+ xchg eax, ecx\r
+ JMP32 stackless_PCIConfig_Write\r
+ xchg eax, ecx\r
+\r
+ mov esp, esi ; Restore the return address\r
+ RET32\r
+\r
+stackless_SideBand_Write ENDP\r
+\r
+;----------------------------------------------------------------------------\r
+;\r
+; Procedure: stackless_PCIConfig_Write\r
+;\r
+; Input: esp - return address\r
+; eax - Data to write\r
+; ebx - PCI Config Address\r
+;\r
+; Output: None\r
+;\r
+; Destroys:\r
+; dx\r
+;\r
+; Description:\r
+; Perform a DWORD PCI Configuration write\r
+;\r
+;----------------------------------------------------------------------------\r
+stackless_PCIConfig_Write PROC NEAR C PUBLIC\r
+\r
+ ;\r
+ ; Write the PCI Config Address to the address port\r
+ ;\r
+ xchg eax, ebx\r
+ mov dx, PCI_ADDRESS_PORT\r
+ out dx, eax\r
+ xchg eax, ebx\r
+\r
+ ;\r
+ ; Write the PCI DWORD Data to the data port\r
+ ;\r
+ mov dx, PCI_DATA_PORT\r
+ out dx, eax\r
+\r
+ RET32\r
+\r
+stackless_PCIConfig_Write ENDP\r
+\r
+;----------------------------------------------------------------------------\r
+;\r
+; Procedure: stackless_PCIConfig_Read\r
+;\r
+; Input: esp - return address\r
+; ebx - PCI Config Address\r
+;\r
+; Output: eax - Data read\r
+;\r
+; Destroys:\r
+; eax\r
+; dx\r
+;\r
+; Description:\r
+; Perform a DWORD PCI Configuration read\r
+;\r
+;----------------------------------------------------------------------------\r
+stackless_PCIConfig_Read PROC NEAR C PUBLIC\r
+\r
+ ;\r
+ ; Write the PCI Config Address to the address port\r
+ ;\r
+ xchg eax, ebx\r
+ mov dx, PCI_ADDRESS_PORT\r
+ out dx, eax\r
+ xchg eax, ebx\r
+\r
+ ;\r
+ ; Read the PCI DWORD Data from the data port\r
+ ;\r
+ mov dx, PCI_DATA_PORT\r
+ in eax, dx\r
+\r
+ RET32\r
+\r
+stackless_PCIConfig_Read ENDP\r
+\r
+;\r
+; ROM-based Global-Descriptor Table for the Tiano PEI Phase\r
+;\r
+align 16\r
+PUBLIC BootGdtTable\r
+\r
+;\r
+; GDT[0]: 0x00: Null entry, never used.\r
+;\r
+NULL_SEL equ $ - GDT_BASE ; Selector [0]\r
+GDT_BASE:\r
+BootGdtTable DD 0\r
+ DD 0\r
+;\r
+; Linear data segment descriptor\r
+;\r
+LINEAR_SEL equ $ - GDT_BASE ; Selector [0x8]\r
+ DW 0FFFFh ; limit 0xFFFF\r
+ DW 0 ; base 0\r
+ DB 0\r
+ DB 092h ; present, ring 0, data, expand-up, writable\r
+ DB 0CFh ; page-granular, 32-bit\r
+ DB 0\r
+;\r
+; Linear code segment descriptor\r
+;\r
+LINEAR_CODE_SEL equ $ - GDT_BASE ; Selector [0x10]\r
+ DW 0FFFFh ; limit 0xFFFF\r
+ DW 0 ; base 0\r
+ DB 0\r
+ DB 09Bh ; present, ring 0, data, expand-up, not-writable\r
+ DB 0CFh ; page-granular, 32-bit\r
+ DB 0\r
+;\r
+; System data segment descriptor\r
+;\r
+SYS_DATA_SEL equ $ - GDT_BASE ; Selector [0x18]\r
+ DW 0FFFFh ; limit 0xFFFF\r
+ DW 0 ; base 0\r
+ DB 0\r
+ DB 093h ; present, ring 0, data, expand-up, not-writable\r
+ DB 0CFh ; page-granular, 32-bit\r
+ DB 0\r
+\r
+;\r
+; System code segment descriptor\r
+;\r
+SYS_CODE_SEL equ $ - GDT_BASE ; Selector [0x20]\r
+ DW 0FFFFh ; limit 0xFFFF\r
+ DW 0 ; base 0\r
+ DB 0\r
+ DB 09Ah ; present, ring 0, data, expand-up, writable\r
+ DB 0CFh ; page-granular, 32-bit\r
+ DB 0\r
+;\r
+; Spare segment descriptor\r
+;\r
+SYS16_CODE_SEL equ $ - GDT_BASE ; Selector [0x28]\r
+ DW 0FFFFh ; limit 0xFFFF\r
+ DW 0 ; base 0\r
+ DB 0Fh\r
+ DB 09Bh ; present, ring 0, code, expand-up, writable\r
+ DB 00h ; byte-granular, 16-bit\r
+ DB 0\r
+;\r
+; Spare segment descriptor\r
+;\r
+SYS16_DATA_SEL equ $ - GDT_BASE ; Selector [0x30]\r
+ DW 0FFFFh ; limit 0xFFFF\r
+ DW 0 ; base 0\r
+ DB 0\r
+ DB 093h ; present, ring 0, data, expand-up, not-writable\r
+ DB 00h ; byte-granular, 16-bit\r
+ DB 0\r
+\r
+;\r
+; Spare segment descriptor\r
+;\r
+SPARE5_SEL equ $ - GDT_BASE ; Selector [0x38]\r
+ DW 0 ; limit 0xFFFF\r
+ DW 0 ; base 0\r
+ DB 0\r
+ DB 0 ; present, ring 0, data, expand-up, writable\r
+ DB 0 ; page-granular, 32-bit\r
+ DB 0\r
+GDT_SIZE EQU $ - BootGDTtable ; Size, in bytes\r
+\r
+;\r
+; GDT Descriptor\r
+;\r
+GdtDesc: ; GDT descriptor\r
+ DW GDT_SIZE - 1 ; GDT limit\r
+ DD OFFSET BootGdtTable ; GDT base address\r
+\r
+ProtectedModeEntryLinearAddress LABEL FWORD\r
+ProtectedModeEntryLinearOffset LABEL DWORD\r
+ DD OFFSET ProtectedModeEntryPoint ; Offset of our 32 bit code\r
+ DW LINEAR_CODE_SEL\r
+\r
+END\r
--- /dev/null
+;\r
+; Copyright (c) 2013-2015 Intel Corporation.\r
+;\r
+; This program and the accompanying materials\r
+; are licensed and made available under the terms and conditions of the BSD License\r
+; which accompanies this distribution. The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+;------------------------------------------------------------------------------\r
+;\r
+; Module Name:\r
+;\r
+; Platform.inc\r
+;\r
+; Abstract:\r
+;\r
+; Quark A0 Platform Specific Definitions\r
+;\r
+;------------------------------------------------------------------------------\r
+\r
+JMP32 MACRO FunctionName\r
+ lea esp, @F\r
+ jmp FunctionName\r
+@@:\r
+ENDM\r
+\r
+RET32 MACRO\r
+ jmp esp\r
+ENDM\r
+\r
+;\r
+; ROM/SPI/MEMORY Definitions\r
+;\r
+QUARK_DDR3_MEM_BASE_ADDRESS EQU 000000000h ; Memory Base Address = 0\r
+QUARK_MAX_DDR3_MEM_SIZE_BYTES EQU 080000000h ; DDR3 Memory Size = 2GB\r
+QUARK_ESRAM_MEM_SIZE_BYTES EQU 000080000h ; eSRAM Memory Size = 512K\r
+QUARK_STACK_SIZE_BYTES EQU 008000h ; Quark stack size = 32K\r
+\r
+;\r
+; RTC/CMOS definitions\r
+;\r
+RTC_INDEX EQU 070h\r
+ NMI_DISABLE EQU 080h ; Bit7=1 disables NMI\r
+ NMI_ENABLE EQU 000h ; Bit7=0 disables NMI\r
+RTC_DATA EQU 071h\r
+\r
+;\r
+; PCI Configuration definitions\r
+;\r
+PCI_CFG EQU 1 SHL 01Fh ; PCI configuration access mechanism\r
+PCI_ADDRESS_PORT EQU 0CF8h\r
+PCI_DATA_PORT EQU 0CFCh\r
+\r
+;\r
+; Quark PCI devices\r
+;\r
+HOST_BRIDGE_PFA EQU 0000h ; B0:D0:F0 (Host Bridge)\r
+ILB_PFA EQU 00F8h ; B0:D31:F0 (Legacy Block)\r
+\r
+;\r
+; ILB PCI Config Registers\r
+;\r
+BDE EQU 0D4h ; BIOS Decode Enable register\r
+ DECODE_ALL_REGIONS_ENABLE EQU 0FF000000h ; Decode all BIOS decode ranges\r
+\r
+\r
+;\r
+; iLB Reset Register\r
+;\r
+ILB_RESET_REG EQU 0CF9h\r
+ CF9_WARM_RESET EQU 02h\r
+ CF9_COLD_RESET EQU 08h\r
+\r
+;\r
+; Host Bridge PCI Config Registers\r
+;\r
+MESSAGE_BUS_CONTROL_REG EQU 0D0h ; Message Bus Control Register\r
+ SB_OPCODE_FIELD EQU 018h ; Bit location of Opcode field\r
+ OPCODE_SIDEBAND_REG_READ EQU 010h ; Read opcode\r
+ OPCODE_SIDEBAND_REG_WRITE EQU 011h ; Write opcode\r
+ OPCODE_SIDEBAND_ALT_REG_READ EQU 06h ; Alternate Read opcode\r
+ OPCODE_SIDEBAND_ALT_REG_WRITE EQU 07h ; Alternate Write opcode\r
+ OPCODE_WARM_RESET_REQUEST EQU 0F4h ; Reset Warm\r
+ OPCODE_COLD_RESET_REQUEST EQU 0F5h ; Reset Cold\r
+ SB_PORT_FIELD EQU 010h ; Bit location of Port ID field\r
+ MEMORY_ARBITER_PORT_ID EQU 00h\r
+ HOST_BRIDGE_PORT_ID EQU 03h\r
+ RMU_PORT_ID EQU 04h\r
+ MEMORY_MANAGER_PORT_ID EQU 05h\r
+ SOC_UNIT_PORT_ID EQU 031h\r
+ SB_ADDR_FIELD EQU 008h ; Bit location of Register field\r
+ SB_BE_FIELD EQU 004h ; Bit location of Byte Enables field\r
+ ALL_BYTE_EN EQU 00Fh ; All Byte Enables\r
+MESSAGE_DATA_REG EQU 0D4h ; Message Data Register\r
+\r
+;\r
+; Memory Arbiter Config Registers\r
+;\r
+AEC_CTRL_OFFSET EQU 00h\r
+\r
+;\r
+; Host Bridge Config Registers\r
+;\r
+HMISC2_OFFSET EQU 03h\r
+ OR_PM_FIELD EQU 010h\r
+ SMI_EN EQU 1 SHL 13h\r
+\r
+HMBOUND_OFFSET EQU 08h\r
+ HMBOUND_ADDRESS EQU (QUARK_DDR3_MEM_BASE_ADDRESS + QUARK_MAX_DDR3_MEM_SIZE_BYTES + QUARK_ESRAM_MEM_SIZE_BYTES)\r
+ HMBOUND_LOCK EQU 00000001h\r
+HECREG_OFFSET EQU 09h\r
+ EC_BASE EQU 0E0000000h\r
+ EC_ENABLE EQU 01h\r
+HLEGACY_OFFSET EQU 0Ah\r
+ NMI EQU 1 SHL 0Eh ; Pin 14\r
+ SMI EQU 1 SHL 0Ch ; Pin 12\r
+ INTR EQU 1 SHL 0Ah ; Pin 10\r
+\r
+\r
+;\r
+; Memory Manager Config Registers\r
+;\r
+ESRAMPGCTRL_BLOCK_OFFSET EQU 082h\r
+ BLOCK_ENABLE_PG EQU 010000000h\r
+BIMRVCTL_OFFSET EQU 019h\r
+ ENABLE_IMR_INTERRUPT EQU 080000000h\r
+\r
+;\r
+; SOC UNIT Debug Registers\r
+;\r
+CFGSTICKY_W1_OFFSET EQU 050h\r
+ FORCE_COLD_RESET EQU 00000001h\r
+CFGSTICKY_RW_OFFSET EQU 051h\r
+ RESET_FOR_ESRAM_LOCK EQU 00000020h\r
+ RESET_FOR_HMBOUND_LOCK EQU 00000040h\r
+CFGNONSTICKY_W1_OFFSET EQU 052h\r
+ FORCE_WARM_RESET EQU 00000001h\r
--- /dev/null
+/** @file\r
+Platform SEC Library for Quark.\r
+\r
+Copyright (c) 2013-2015 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+**/\r
+\r
+#include <PiPei.h>\r
+\r
+#include <Ppi/SecPlatformInformation.h>\r
+#include <Ppi/TemporaryRamSupport.h>\r
+#include <Library/PcdLib.h>\r
+#include <Library/BaseLib.h>\r
+#include <Library/DebugLib.h>\r
+#include <Library/BaseMemoryLib.h>\r
+#include <Library/HobLib.h>\r
+#include <Library/MtrrLib.h>\r
+\r
+/**\r
+\r
+ Entry point to the C language phase of SEC. After the SEC assembly\r
+ code has initialized some temporary memory and set up the stack,\r
+ the control is transferred to this function.\r
+\r
+ @param SizeOfRam Size of the temporary memory available for use.\r
+ @param TempRamBase Base address of temporary ram\r
+ @param BootFirmwareVolume Base address of the Boot Firmware Volume.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+SecStartup (\r
+ IN UINT32 SizeOfRam,\r
+ IN UINT32 TempRamBase,\r
+ IN VOID *BootFirmwareVolume\r
+ );\r
+\r
+/**\r
+ Auto-generated function that calls the library constructors for all of the module's\r
+ dependent libraries. This function must be called by the SEC Core once a stack has\r
+ been established.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+ProcessLibraryConstructorList (\r
+ VOID\r
+ );\r
+\r
+/**\r
+\r
+ Entry point to the C language phase of PlatformSecLib. After the SEC assembly\r
+ code has initialized some temporary memory and set up the stack, control is\r
+ transferred to this function.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+PlatformSecLibStartup (\r
+ VOID\r
+ )\r
+{\r
+ //\r
+ // Process all library constructor functions linked to SecCore.\r
+ // This function must be called before any library functions are called\r
+ //\r
+ ProcessLibraryConstructorList ();\r
+\r
+ //\r
+ // Set write back cache attribute for SPI FLASH\r
+ //\r
+ MtrrSetMemoryAttribute (\r
+ PcdGet32 (PcdFlashAreaBaseAddress),\r
+ PcdGet32 (PcdFlashAreaSize),\r
+ CacheWriteBack\r
+ );\r
+\r
+ //\r
+ // Set write back cache attribute for 512KB Embedded SRAM\r
+ //\r
+ MtrrSetMemoryAttribute (\r
+ PcdGet32 (PcdEsramStage1Base),\r
+ SIZE_512KB,\r
+ CacheWriteBack\r
+ );\r
+\r
+ //\r
+ // Pass control to SecCore module passing in the size of the temporary RAM in\r
+ // Embedded SRAM, the base address of the temporary RAM in Embedded SRAM, and\r
+ // the base address of the boot firmware volume. The top 32KB of the 512 KB\r
+ // embedded SRAM are used as temporary RAM.\r
+ //\r
+ SecStartup (\r
+ SIZE_32KB,\r
+ PcdGet32 (PcdEsramStage1Base) + SIZE_512KB - SIZE_32KB,\r
+ (VOID *)(UINTN)PcdGet32 (PcdFlashFvRecoveryBase)\r
+ );\r
+}\r
+\r
+/**\r
+ A developer supplied function to perform platform specific operations.\r
+\r
+ It's a developer supplied function to perform any operations appropriate to a\r
+ given platform. It's invoked just before passing control to PEI core by SEC\r
+ core. Platform developer may modify the SecCoreData and PPI list that is\r
+ passed to PEI Core.\r
+\r
+ @param SecCoreData The same parameter as passing to PEI core. It\r
+ could be overridden by this function.\r
+ @param PpiList The default PPI list passed from generic SEC\r
+ part.\r
+\r
+ @return The final PPI list that platform wishes to passed to PEI core.\r
+\r
+**/\r
+EFI_PEI_PPI_DESCRIPTOR *\r
+EFIAPI\r
+SecPlatformMain (\r
+ IN OUT EFI_SEC_PEI_HAND_OFF *SecCoreData,\r
+ IN EFI_PEI_PPI_DESCRIPTOR *PpiList\r
+ )\r
+{\r
+ return NULL;\r
+}\r
+\r
+/**\r
+ This interface conveys state information out of the Security (SEC) phase into PEI.\r
+\r
+ @param PeiServices Pointer to the PEI Services Table.\r
+ @param StructureSize Pointer to the variable describing size of the input buffer.\r
+ @param PlatformInformationRecord Pointer to the EFI_SEC_PLATFORM_INFORMATION_RECORD.\r
+\r
+ @retval EFI_SUCCESS The data was successfully returned.\r
+ @retval EFI_BUFFER_TOO_SMALL The buffer was too small.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+SecPlatformInformation (\r
+ IN CONST EFI_PEI_SERVICES **PeiServices,\r
+ IN OUT UINT64 *StructureSize,\r
+ OUT EFI_SEC_PLATFORM_INFORMATION_RECORD *PlatformInformationRecord\r
+ )\r
+{\r
+ UINT32 *BIST;\r
+ UINT32 Size;\r
+ UINT32 Count;\r
+ EFI_HOB_GUID_TYPE *GuidHob;\r
+ UINT32 *TopOfStack;\r
+\r
+ //\r
+ // Top of the stack is the top of the 512KB Embedded SRAM region\r
+ //\r
+ TopOfStack = (UINT32 *)(UINTN)(PcdGet32 (PcdEsramStage1Base) + SIZE_512KB);\r
+\r
+ GuidHob = GetFirstGuidHob (&gEfiSecPlatformInformationPpiGuid);\r
+ if (GuidHob != NULL) {\r
+ Size = GET_GUID_HOB_DATA_SIZE (GuidHob);\r
+ BIST = GET_GUID_HOB_DATA (GuidHob);\r
+ } else {\r
+ //\r
+ // The entries of BIST information, together with the number of them,\r
+ // reside in the bottom of stack, left untouched by normal stack operation.\r
+ // This routine copies the BIST information to the buffer pointed by\r
+ // PlatformInformationRecord for output.\r
+ //\r
+ Count = *(TopOfStack - 1);\r
+ Size = Count * sizeof (IA32_HANDOFF_STATUS);\r
+ BIST = (UINT32 *) ((UINT32) TopOfStack - sizeof (UINT32) - Size);\r
+\r
+ //\r
+ // Copy Data from Stack to Hob to avoid data is lost after memory is ready.\r
+ //\r
+ BuildGuidDataHob (\r
+ &gEfiSecPlatformInformationPpiGuid,\r
+ BIST,\r
+ (UINTN)Size\r
+ );\r
+ GuidHob = GetFirstGuidHob (&gEfiSecPlatformInformationPpiGuid);\r
+ Size = GET_GUID_HOB_DATA_SIZE (GuidHob);\r
+ BIST = GET_GUID_HOB_DATA (GuidHob);\r
+ }\r
+\r
+ if ((*StructureSize) < (UINT64) Size) {\r
+ *StructureSize = Size;\r
+ return EFI_BUFFER_TOO_SMALL;\r
+ }\r
+\r
+ *StructureSize = Size;\r
+ CopyMem (PlatformInformationRecord, BIST, Size);\r
+\r
+ return EFI_SUCCESS;\r
+}\r
+\r
+/**\r
+ This interface disables temporary memory in SEC Phase.\r
+**/\r
+VOID\r
+EFIAPI\r
+SecPlatformDisableTemporaryMemory (\r
+ VOID\r
+ )\r
+{\r
+}\r
--- /dev/null
+#/** @file\r
+# Platform SEC Library for Quark.\r
+#\r
+# Copyright (c) 2013-2015 Intel Corporation.\r
+#\r
+# This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution. The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php\r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+#**/\r
+\r
+[Defines]\r
+ INF_VERSION = 0x00010005\r
+ BASE_NAME = PlatformSecLib\r
+ FILE_GUID = 8DE4221F-A9CC-4c78-85B9-D863681F0C01\r
+ MODULE_TYPE = SEC\r
+ VERSION_STRING = 1.0\r
+ LIBRARY_CLASS = PlatformSecLib\r
+ MODULE_UNI_FILE = PlatformSecLibModStrs.uni\r
+\r
+#\r
+# The following information is for reference only and not required by the build tools.\r
+#\r
+# VALID_ARCHITECTURES = IA32\r
+#\r
+\r
+[Sources]\r
+ PlatformSecLib.c\r
+\r
+[Sources.IA32]\r
+ Ia32/Flat32.asm | MSFT\r
+ Ia32/Flat32.asm | INTEL\r
+ Ia32/Flat32.S | GCC\r
+\r
+[Packages]\r
+ MdePkg/MdePkg.dec\r
+ UefiCpuPkg/UefiCpuPkg.dec\r
+ QuarkPlatformPkg/QuarkPlatformPkg.dec\r
+\r
+[LibraryClasses]\r
+ DebugLib\r
+ BaseLib\r
+ BaseMemoryLib\r
+ PciLib\r
+ PcdLib\r
+ HobLib\r
+ MtrrLib\r
+\r
+[Pcd]\r
+ gQuarkPlatformTokenSpaceGuid.PcdEsramStage1Base ## CONSUMES\r
+ gQuarkPlatformTokenSpaceGuid.PcdFlashFvRecoveryBase ## CONSUMES\r
+ gQuarkPlatformTokenSpaceGuid.PcdFlashAreaBaseAddress ## CONSUMES\r
+ gQuarkPlatformTokenSpaceGuid.PcdFlashAreaSize ## CONSUMES\r
+\r
+[Ppis]\r
+ gEfiSecPlatformInformationPpiGuid ## UNDEFINED # it is used as GUIDED HOB\r
--- /dev/null
+// /** @file\r
+// PlatformSecLib Localized Abstract and Description Content\r
+//\r
+// Copyright (c) 2012 - 2013, Intel Corporation. All rights reserved.<BR>\r
+//\r
+// This program and the accompanying materials\r
+// are licensed and made available under the terms and conditions of the BSD License\r
+// which accompanies this distribution. The full text of the license may be found at\r
+// http://opensource.org/licenses/bsd-license.php\r
+//\r
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+//\r
+// **/\r
+\r
+#string STR_MODULE_ABSTRACT\r
+#language en-US\r
+"SEC Platform Library "\r
+\r
+#string STR_MODULE_DESCRIPTION\r
+#language en-US\r
+"Provides a platform-specific function to be used during the SEC stage of POST. "\r
+\r
+\r
--- /dev/null
+/** @file\r
+Provides a secure platform-specific method to detect physically present user.\r
+\r
+Copyright (c) 2013 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#include <PiDxe.h>\r
+#include <Library/PlatformHelperLib.h>\r
+#include <Library/DebugLib.h>\r
+#include <Library/UefiBootServicesTableLib.h>\r
+#include <Library/I2cLib.h>\r
+\r
+#include <PlatformBoards.h>\r
+#include <Pcal9555.h>\r
+#include <QNCAccess.h>\r
+\r
+//\r
+// Global variable to cache pointer to I2C protocol.\r
+//\r
+EFI_PLATFORM_TYPE mPlatformType = TypeUnknown;\r
+\r
+BOOLEAN\r
+CheckResetButtonState (\r
+ VOID\r
+ )\r
+{\r
+ EFI_STATUS Status;\r
+ EFI_I2C_DEVICE_ADDRESS I2CSlaveAddress;\r
+ UINTN Length;\r
+ UINTN ReadLength;\r
+ UINT8 Buffer[2];\r
+\r
+ DEBUG ((EFI_D_ERROR, "CheckResetButtonState(): mPlatformType == %d\n", mPlatformType));\r
+ if (mPlatformType == GalileoGen2) {\r
+ //\r
+ // Reset Button - EXP2.P1_7 should be configured as an input.\r
+ //\r
+ PlatformPcal9555GpioSetDir (\r
+ GALILEO_GEN2_IOEXP2_7BIT_SLAVE_ADDR, // IO Expander 2.\r
+ 15, // P1-7.\r
+ FALSE\r
+ );\r
+\r
+ //\r
+ // Reset Button - EXP2.P1_7 pullup should be disabled.\r
+ //\r
+ PlatformPcal9555GpioDisablePull (\r
+ GALILEO_GEN2_IOEXP2_7BIT_SLAVE_ADDR, // IO Expander 2.\r
+ 15 // P1-7.\r
+ );\r
+\r
+ //\r
+ // Read state of Reset Button - EXP2.P1_7\r
+ // This GPIO is pulled high when the button is not pressed\r
+ // This GPIO reads low when button is pressed\r
+ //\r
+ return PlatformPcal9555GpioGetState (\r
+ GALILEO_GEN2_IOEXP2_7BIT_SLAVE_ADDR, // IO Expander 2.\r
+ 15 // P1-7.\r
+ );\r
+ }\r
+ if (mPlatformType == Galileo) {\r
+ //\r
+ // Detect the I2C Slave Address of the GPIO Expander\r
+ //\r
+ if (PlatformLegacyGpioGetLevel (R_QNC_GPIO_RGLVL_RESUME_WELL, GALILEO_DETERMINE_IOEXP_SLA_RESUMEWELL_GPIO)) {\r
+ I2CSlaveAddress.I2CDeviceAddress = GALILEO_IOEXP_J2HI_7BIT_SLAVE_ADDR;\r
+ } else {\r
+ I2CSlaveAddress.I2CDeviceAddress = GALILEO_IOEXP_J2LO_7BIT_SLAVE_ADDR;\r
+ }\r
+\r
+ //\r
+ // Select Port 5\r
+ //\r
+ Length = 2;\r
+ Buffer[0] = 0x18;\r
+ Buffer[1] = 0x05;\r
+ Status = I2cWriteMultipleByte (\r
+ I2CSlaveAddress,\r
+ EfiI2CSevenBitAddrMode,\r
+ &Length,\r
+ &Buffer\r
+ );\r
+ ASSERT_EFI_ERROR (Status);\r
+\r
+ //\r
+ // Read "Pin Direction" of Port 5\r
+ //\r
+ Length = 1;\r
+ ReadLength = 1;\r
+ Buffer[1] = 0x1C;\r
+ Status = I2cReadMultipleByte (\r
+ I2CSlaveAddress,\r
+ EfiI2CSevenBitAddrMode,\r
+ &Length,\r
+ &ReadLength,\r
+ &Buffer[1]\r
+ );\r
+ ASSERT_EFI_ERROR (Status);\r
+\r
+ //\r
+ // Set "Pin Direction" of Port 5, Bit 0 as input\r
+ //\r
+ Length = 2;\r
+ Buffer[0] = 0x1C;\r
+ Buffer[1] = Buffer[1] | BIT0;\r
+\r
+ Status = I2cWriteMultipleByte (\r
+ I2CSlaveAddress,\r
+ EfiI2CSevenBitAddrMode,\r
+ &Length,\r
+ &Buffer\r
+ );\r
+ ASSERT_EFI_ERROR (Status);\r
+\r
+ //\r
+ // Read Port 5\r
+ //\r
+ Buffer[1] = 5;\r
+ Length = 1;\r
+ ReadLength = 1;\r
+\r
+ Status = I2cReadMultipleByte (\r
+ I2CSlaveAddress,\r
+ EfiI2CSevenBitAddrMode,\r
+ &Length,\r
+ &ReadLength,\r
+ &Buffer[1]\r
+ );\r
+ ASSERT_EFI_ERROR (Status);\r
+\r
+ //\r
+ // Return the state of Port 5, Bit 0\r
+ //\r
+ return ((Buffer[1] & BIT0) != 0);\r
+ }\r
+ return TRUE;\r
+}\r
+\r
+/**\r
+\r
+ This function provides a platform-specific method to detect whether the platform\r
+ is operating by a physically present user.\r
+\r
+ Programmatic changing of platform security policy (such as disable Secure Boot,\r
+ or switch between Standard/Custom Secure Boot mode) MUST NOT be possible during\r
+ Boot Services or after exiting EFI Boot Services. Only a physically present user\r
+ is allowed to perform these operations.\r
+\r
+ NOTE THAT: This function cannot depend on any EFI Variable Service since they are\r
+ not available when this function is called in AuthenticateVariable driver.\r
+\r
+ @retval TRUE The platform is operated by a physically present user.\r
+ @retval FALSE The platform is NOT operated by a physically present user.\r
+\r
+**/\r
+BOOLEAN\r
+EFIAPI\r
+UserPhysicalPresent (\r
+ VOID\r
+ )\r
+{\r
+ EFI_STATUS Status;\r
+\r
+ //\r
+ // If user has already been detected as present, then return TRUE\r
+ //\r
+ if (PcdGetBool (PcdUserIsPhysicallyPresent)) {\r
+ return TRUE;\r
+ }\r
+\r
+ //\r
+ // Check to see if user is present now\r
+ //\r
+ if (CheckResetButtonState ()) {\r
+ //\r
+ // User is still not present, then return FALSE\r
+ //\r
+ return FALSE;\r
+ }\r
+\r
+ //\r
+ // User has gone from not present to present state, so set\r
+ // PcdUserIsPhysicallyPresent to TRUE\r
+ //\r
+ Status = PcdSetBoolS (PcdUserIsPhysicallyPresent, TRUE);\r
+ ASSERT_EFI_ERROR (Status);\r
+\r
+ return TRUE;\r
+}\r
+\r
+/**\r
+ Determines if a user is physically present by reading the reset button state.\r
+\r
+ @param ImageHandle The image handle of this driver.\r
+ @param SystemTable A pointer to the EFI System Table.\r
+\r
+ @retval EFI_SUCCESS Install the Secure Boot Helper Protocol successfully.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+PlatformSecureLibInitialize (\r
+ IN EFI_HANDLE ImageHandle,\r
+ IN EFI_SYSTEM_TABLE *SystemTable\r
+ )\r
+{\r
+ EFI_STATUS Status;\r
+\r
+ //\r
+ // Get the platform type\r
+ //\r
+ mPlatformType = (EFI_PLATFORM_TYPE)PcdGet16 (PcdPlatformType);\r
+\r
+ //\r
+ // Read the state of the reset button when the library is initialized\r
+ //\r
+ Status = PcdSetBoolS (PcdUserIsPhysicallyPresent, !CheckResetButtonState ());\r
+ ASSERT_EFI_ERROR (Status);\r
+\r
+ return EFI_SUCCESS;\r
+}\r
--- /dev/null
+## @file\r
+# Provides a secure platform-specific method to detect physically present user.\r
+#\r
+# Copyright (c) 2013 Intel Corporation.\r
+#\r
+# This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution. The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php\r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+##\r
+\r
+[Defines]\r
+ INF_VERSION = 0x00010005\r
+ BASE_NAME = PlatformSecureLib\r
+ FILE_GUID = 38BB5221-F685-469f-846E-F1C508FC5F4A\r
+ MODULE_TYPE = DXE_DRIVER\r
+ VERSION_STRING = 1.0\r
+ LIBRARY_CLASS = PlatformSecureLib|DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_DRIVER\r
+ CONSTRUCTOR = PlatformSecureLibInitialize\r
+\r
+#\r
+# The following information is for reference only and not required by the build tools.\r
+#\r
+# VALID_ARCHITECTURES = IA32\r
+#\r
+\r
+[Sources]\r
+ PlatformSecureLib.c\r
+\r
+[Packages]\r
+ MdePkg/MdePkg.dec\r
+ QuarkSocPkg/QuarkSocPkg.dec\r
+ QuarkPlatformPkg/QuarkPlatformPkg.dec\r
+\r
+[LibraryClasses]\r
+ DebugLib\r
+ PlatformHelperLib\r
+ UefiBootServicesTableLib\r
+ I2cLib\r
+\r
+[Pcd]\r
+ gQuarkPlatformTokenSpaceGuid.PcdPlatformType\r
+ gQuarkPlatformTokenSpaceGuid.PcdUserIsPhysicallyPresent\r
--- /dev/null
+/** @file\r
+Common header file shared by all source files.\r
+\r
+This file includes package header files, library classes and protocol, PPI & GUID definitions.\r
+\r
+Copyright (c) 2013-2015 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+**/\r
+\r
+#ifndef __COMMON_HEADER_H_\r
+#define __COMMON_HEADER_H_\r
+\r
+\r
+\r
+#include <PiPei.h>\r
+\r
+#include <Ppi/DeviceRecoveryModule.h>\r
+\r
+#include <Library/RecoveryOemHookLib.h>\r
+#include <Library/QNCAccessLib.h>\r
+#include <Library/ResetSystemLib.h>\r
+\r
+#endif\r
--- /dev/null
+/** @file\r
+This file includes the function that can be customized by OEM.\r
+\r
+Copyright (c) 2013-2015 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#include "CommonHeader.h"\r
+\r
+/**\r
+ This function allows the user to force a system recovery\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+OemInitiateRecovery (\r
+ VOID\r
+ )\r
+{\r
+ UINT32 Data32;\r
+\r
+ //\r
+ // Set 'B_CFG_STICKY_RW_FORCE_RECOVERY' sticky bit so we know we need to do a recovery following warm reset\r
+ //\r
+ Data32 = QNCAltPortRead (QUARK_SCSS_SOC_UNIT_SB_PORT_ID, QUARK_SCSS_SOC_UNIT_CFG_STICKY_RW);\r
+ Data32 |= B_CFG_STICKY_RW_FORCE_RECOVERY;\r
+ QNCAltPortWrite (QUARK_SCSS_SOC_UNIT_SB_PORT_ID, QUARK_SCSS_SOC_UNIT_CFG_STICKY_RW, Data32);\r
+\r
+ //\r
+ // Initialte the warm reset\r
+ //\r
+ ResetWarm ();\r
+}\r
+\r
+/**\r
+ This function allows the user to force a system recovery and deadloop.\r
+\r
+ Deadloop required since system should not execute beyond this point.\r
+ Deadloop should never happen since OemInitiateRecovery () called within\r
+ this routine should never return since it executes a Warm Reset.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+OemInitiateRecoveryAndWait (\r
+ VOID\r
+ )\r
+{\r
+ volatile UINTN Index;\r
+\r
+ OemInitiateRecovery ();\r
+ for (Index = 0; Index == 0;);\r
+}\r
--- /dev/null
+## @file\r
+# Library Hook Point functions for Intel QNC.\r
+#\r
+# This library provides hook points for OEM w.r.t recovery\r
+#\r
+# Copyright (c) 2013-2015 Intel Corporation.\r
+#\r
+# This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution. The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php\r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+##\r
+\r
+[Defines]\r
+ INF_VERSION = 0x00010005\r
+ BASE_NAME = RecoveryOemHookLib\r
+ FILE_GUID = DE6D4FB9-12DB-4dbb-ACF1-92514388355F\r
+ MODULE_TYPE = BASE\r
+ VERSION_STRING = 1.0\r
+ LIBRARY_CLASS = RecoveryOemHookLib\r
+\r
+#\r
+# The following information is for reference only and not required by the build tools.\r
+#\r
+# VALID_ARCHITECTURES = IA32\r
+#\r
+\r
+[Sources]\r
+ RecoveryOemHookLib.c\r
+ CommonHeader.h\r
+\r
+\r
+[Packages]\r
+ MdePkg/MdePkg.dec\r
+ MdeModulePkg/MdeModulePkg.dec\r
+ QuarkPlatformPkg/QuarkPlatformPkg.dec\r
+ QuarkSocPkg/QuarkSocPkg.dec\r
+\r
+[LibraryClasses]\r
+ QNCAccessLib\r
+ ResetSystemLib\r
+\r
+[Ppis]\r
+ gEfiPeiDeviceRecoveryModulePpiGuid # PPI SOMETIMES_CONSUMED\r
+\r
--- /dev/null
+Copyright (c) 2012, Intel Corporation. All rights reserved.\r
+\r
+Redistribution and use in source and binary forms, with or without\r
+modification, are permitted provided that the following conditions\r
+are met:\r
+\r
+* Redistributions of source code must retain the above copyright\r
+ notice, this list of conditions and the following disclaimer.\r
+* Redistributions in binary form must reproduce the above copyright\r
+ notice, this list of conditions and the following disclaimer in\r
+ the documentation and/or other materials provided with the\r
+ distribution.\r
+\r
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
+"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
+LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\r
+FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE\r
+COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\r
+INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\r
+BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\r
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r
+CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\r
+LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\r
+ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+POSSIBILITY OF SUCH DAMAGE.\r
--- /dev/null
+/** @file\r
+Pci Host Bridge driver for a simple IIO. There is only one PCI Root Bridge in the system.\r
+Provides the basic interfaces to abstract a PCI Host Bridge Resource Allocation.\r
+\r
+Copyright (c) 2013-2015 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+**/\r
+\r
+#include "PciHostBridge.h"\r
+#include <IntelQNCRegs.h>\r
+\r
+//\r
+// We can hardcode the following for a Simple IIO -\r
+// Root Bridge Count within the host bridge\r
+// Root Bridge's device path\r
+// Root Bridge's resource appeture\r
+//\r
+EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciRootBridgeDevicePath[ROOT_BRIDGE_COUNT] = {\r
+ {\r
+ {\r
+ {\r
+ ACPI_DEVICE_PATH,\r
+ ACPI_DP,\r
+ {\r
+ (UINT8) (sizeof (ACPI_HID_DEVICE_PATH)),\r
+ (UINT8) ((sizeof (ACPI_HID_DEVICE_PATH)) >> 8)\r
+ }\r
+ },\r
+ EISA_PNP_ID (0x0A03),\r
+ 0\r
+ },\r
+ {\r
+ END_DEVICE_PATH_TYPE,\r
+ END_ENTIRE_DEVICE_PATH_SUBTYPE,\r
+ {\r
+ END_DEVICE_PATH_LENGTH,\r
+ 0\r
+ }\r
+ }\r
+ }\r
+};\r
+\r
+EFI_HANDLE mDriverImageHandle;\r
+PCI_ROOT_BRIDGE_RESOURCE_APERTURE *mResAperture;\r
+\r
+//\r
+// Implementation\r
+//\r
+EFI_STATUS\r
+EFIAPI\r
+InitializePciHostBridge (\r
+ IN EFI_HANDLE ImageHandle,\r
+ IN EFI_SYSTEM_TABLE *SystemTable\r
+ )\r
+/*++\r
+\r
+Routine Description:\r
+\r
+ Entry point of this driver.\r
+\r
+Arguments:\r
+\r
+ ImageHandle - Image handle of this driver.\r
+ SystemTable - Pointer to standard EFI system table.\r
+\r
+Returns:\r
+\r
+ EFI_SUCCESS - Succeed.\r
+ EFI_DEVICE_ERROR - Fail to install PCI_ROOT_BRIDGE_IO protocol.\r
+\r
+--*/\r
+{\r
+ EFI_STATUS Status;\r
+ UINTN TotalRootBridgeFound;\r
+ PCI_HOST_BRIDGE_INSTANCE *HostBridge;\r
+ PCI_ROOT_BRIDGE_INSTANCE *PrivateData;\r
+ UINT64 AllocAttributes;\r
+ EFI_PHYSICAL_ADDRESS BaseAddress;\r
+\r
+ PrivateData = NULL;\r
+\r
+ mDriverImageHandle = ImageHandle;\r
+\r
+ //\r
+ // Most systems in the world including complex servers\r
+ // have only one Host Bridge. Create Host Bridge Device Handle\r
+ //\r
+ Status = gBS->AllocatePool(EfiBootServicesData, sizeof(PCI_HOST_BRIDGE_INSTANCE), (VOID **) &HostBridge);\r
+ ASSERT_EFI_ERROR (Status);\r
+ ZeroMem (HostBridge, sizeof (PCI_HOST_BRIDGE_INSTANCE));\r
+\r
+ HostBridge->Signature = PCI_HOST_BRIDGE_SIGNATURE;\r
+ HostBridge->RootBridgeCount = 1;\r
+ HostBridge->ResourceSubmited = FALSE;\r
+ HostBridge->CanRestarted = TRUE;\r
+ //\r
+ // InitializeListHead (&HostBridge->Head);\r
+ //\r
+ HostBridge->ResAlloc.NotifyPhase = NotifyPhase;\r
+ HostBridge->ResAlloc.GetNextRootBridge = GetNextRootBridge;\r
+ HostBridge->ResAlloc.GetAllocAttributes = GetAttributes;\r
+ HostBridge->ResAlloc.StartBusEnumeration = StartBusEnumeration;\r
+ HostBridge->ResAlloc.SetBusNumbers = SetBusNumbers;\r
+ HostBridge->ResAlloc.SubmitResources = SubmitResources;\r
+ HostBridge->ResAlloc.GetProposedResources = GetProposedResources;\r
+ HostBridge->ResAlloc.PreprocessController = PreprocessController;\r
+\r
+ Status = gBS->InstallProtocolInterface (\r
+ &HostBridge->HostBridgeHandle,\r
+ &gEfiPciHostBridgeResourceAllocationProtocolGuid,\r
+ EFI_NATIVE_INTERFACE,\r
+ &HostBridge->ResAlloc\r
+ );\r
+ if (EFI_ERROR (Status)) {\r
+ gBS->FreePool (HostBridge);\r
+ return EFI_DEVICE_ERROR;\r
+ }\r
+\r
+ Status = gBS->AllocatePool (EfiBootServicesData,\r
+ HostBridge->RootBridgeCount * sizeof(PCI_ROOT_BRIDGE_RESOURCE_APERTURE),\r
+ (VOID **) &mResAperture);\r
+ ASSERT_EFI_ERROR (Status);\r
+ ZeroMem (mResAperture, HostBridge->RootBridgeCount * sizeof(PCI_ROOT_BRIDGE_RESOURCE_APERTURE));\r
+\r
+ DEBUG ((EFI_D_INFO, "Address of resource Aperture: %x\n", mResAperture));\r
+\r
+ //\r
+ // Create Root Bridge Device Handle in this Host Bridge\r
+ //\r
+ InitializeListHead (&HostBridge->Head);\r
+\r
+ TotalRootBridgeFound = 0;\r
+\r
+ Status = gBS->AllocatePool ( EfiBootServicesData,sizeof (PCI_ROOT_BRIDGE_INSTANCE), (VOID **) &PrivateData);\r
+ ASSERT_EFI_ERROR (Status);\r
+ ZeroMem (PrivateData, sizeof (PCI_ROOT_BRIDGE_INSTANCE));\r
+\r
+ PrivateData->Signature = PCI_ROOT_BRIDGE_SIGNATURE;\r
+ PrivateData->DevicePath = (EFI_DEVICE_PATH_PROTOCOL *) &mEfiPciRootBridgeDevicePath[TotalRootBridgeFound];\r
+ AllocAttributes = GetAllocAttributes (TotalRootBridgeFound);\r
+\r
+ SimpleIioRootBridgeConstructor (\r
+ &PrivateData->Io,\r
+ HostBridge->HostBridgeHandle,\r
+ &(mResAperture[TotalRootBridgeFound]),\r
+ AllocAttributes\r
+ );\r
+ //\r
+ // Update Root Bridge with UDS resource information\r
+ //\r
+ PrivateData->Aperture.BusBase = QNC_PCI_HOST_BRIDGE_RESOURCE_APPETURE_BUSBASE;\r
+ PrivateData->Aperture.BusLimit = QNC_PCI_HOST_BRIDGE_RESOURCE_APPETURE_BUSLIMIT;\r
+ PrivateData->Aperture.Mem32Base = PcdGet32 (PcdPciHostBridgeMemory32Base);\r
+ PrivateData->Aperture.Mem32Limit = PcdGet32 (PcdPciHostBridgeMemory32Base) + (PcdGet32 (PcdPciHostBridgeMemory32Size) - 1);\r
+ PrivateData->Aperture.IoBase = PcdGet16 (PcdPciHostBridgeIoBase);\r
+ PrivateData->Aperture.IoLimit = PcdGet16 (PcdPciHostBridgeIoBase) + (PcdGet16 (PcdPciHostBridgeIoSize) - 1);\r
+\r
+ DEBUG ((EFI_D_INFO, "PCI Host Bridge BusBase: %x\n", QNC_PCI_HOST_BRIDGE_RESOURCE_APPETURE_BUSBASE));\r
+ DEBUG ((EFI_D_INFO, "PCI Host Bridge BusLimit: %x\n", QNC_PCI_HOST_BRIDGE_RESOURCE_APPETURE_BUSLIMIT));\r
+ DEBUG ((EFI_D_INFO, "PCI Host Bridge PciResourceMem32Base: %x\n", PcdGet32 (PcdPciHostBridgeMemory32Base)));\r
+ DEBUG ((EFI_D_INFO, "PCI Host Bridge PciResourceMem32Limit: %x\n", PcdGet32 (PcdPciHostBridgeMemory32Base) + (PcdGet32 (PcdPciHostBridgeMemory32Size) - 1)));\r
+ DEBUG ((EFI_D_INFO, "PCI Host Bridge PciResourceMem64Base: %lX\n", PcdGet64 (PcdPciHostBridgeMemory64Base)));\r
+ DEBUG ((EFI_D_INFO, "PCI Host Bridge PciResourceMem64Limit: %lX\n", PcdGet64 (PcdPciHostBridgeMemory64Base) + (PcdGet64 (PcdPciHostBridgeMemory64Size) - 1)));\r
+ DEBUG ((EFI_D_INFO, "PCI Host Bridge PciResourceIoBase: %x\n", PcdGet16 (PcdPciHostBridgeIoBase)));\r
+ DEBUG ((EFI_D_INFO, "PCI Host Bridge PciResourceIoLimit: %x\n", PcdGet16 (PcdPciHostBridgeIoBase) + (PcdGet16 (PcdPciHostBridgeIoSize) - 1)));\r
+\r
+ PrivateData->Handle = NULL;\r
+ Status = gBS->InstallMultipleProtocolInterfaces (\r
+ &PrivateData->Handle,\r
+ &gEfiDevicePathProtocolGuid,\r
+ PrivateData->DevicePath,\r
+ &gEfiPciRootBridgeIoProtocolGuid,\r
+ &PrivateData->Io,\r
+ NULL\r
+ );\r
+ ASSERT_EFI_ERROR (Status);\r
+\r
+ InsertTailList (&HostBridge->Head, &PrivateData->Link);\r
+ TotalRootBridgeFound++; // This is a valid rootbridge so imcrement total root bridges found\r
+\r
+ //\r
+ // Add PCIE base into Runtime memory so that it can be reported in E820 table\r
+ //\r
+ Status = gDS->AddMemorySpace (\r
+ EfiGcdMemoryTypeMemoryMappedIo,\r
+ PcdGet64 (PcdPciExpressBaseAddress),\r
+ PcdGet64 (PcdPciExpressSize),\r
+ EFI_MEMORY_RUNTIME | EFI_MEMORY_UC\r
+ );\r
+ ASSERT_EFI_ERROR(Status);\r
+\r
+ BaseAddress = PcdGet64 (PcdPciExpressBaseAddress);\r
+\r
+ Status = gDS->AllocateMemorySpace (\r
+ EfiGcdAllocateAddress,\r
+ EfiGcdMemoryTypeMemoryMappedIo,\r
+ 0,\r
+ PcdGet64 (PcdPciExpressSize),\r
+ &BaseAddress,\r
+ ImageHandle,\r
+ NULL\r
+ );\r
+ ASSERT_EFI_ERROR(Status);\r
+\r
+ Status = gDS->SetMemorySpaceAttributes (\r
+ PcdGet64 (PcdPciExpressBaseAddress),\r
+ PcdGet64 (PcdPciExpressSize),\r
+ EFI_MEMORY_RUNTIME\r
+ );\r
+ ASSERT_EFI_ERROR (Status);\r
+\r
+ if (PcdGet16 (PcdPciHostBridgeIoSize) > 0) {\r
+ //\r
+ // At present, we use up the first 4k for fixed ranges like\r
+ // ICH GPIO, ACPI and ISA devices. The first 4k is not\r
+ // tracked through GCD. It should be.\r
+ //\r
+ Status = gDS->AddIoSpace (\r
+ EfiGcdIoTypeIo,\r
+ PcdGet16(PcdPciHostBridgeIoBase),\r
+ PcdGet16(PcdPciHostBridgeIoSize)\r
+ );\r
+ ASSERT_EFI_ERROR (Status);\r
+ }\r
+\r
+ if (PcdGet32(PcdPciHostBridgeMemory32Size) > 0) {\r
+ //\r
+ // Shouldn't the capabilities be UC?\r
+ //\r
+ Status = gDS->AddMemorySpace (\r
+ EfiGcdMemoryTypeMemoryMappedIo,\r
+ PcdGet32(PcdPciHostBridgeMemory32Base),\r
+ PcdGet32(PcdPciHostBridgeMemory32Size),\r
+ 0\r
+ );\r
+ ASSERT_EFI_ERROR (Status);\r
+ }\r
+\r
+ return Status;\r
+}\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+NotifyPhase (\r
+ IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r
+ IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PHASE Phase\r
+ )\r
+/*++\r
+\r
+Routine Description:\r
+\r
+ Enter a certain phase of the PCI enumeration process.\r
+\r
+Arguments:\r
+\r
+ This - The EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL instance.\r
+ Phase - The phase during enumeration.\r
+\r
+Returns:\r
+\r
+ EFI_SUCCESS - Succeed.\r
+ EFI_INVALID_PARAMETER - Wrong phase parameter passed in.\r
+ EFI_NOT_READY - Resources have not been submitted yet.\r
+\r
+--*/\r
+{\r
+ PCI_HOST_BRIDGE_INSTANCE *HostBridgeInstance;\r
+ PCI_ROOT_BRIDGE_INSTANCE *RootBridgeInstance;\r
+ PCI_RESOURCE_TYPE Index;\r
+ EFI_LIST_ENTRY *List;\r
+ EFI_PHYSICAL_ADDRESS BaseAddress;\r
+ UINT64 AddrLen;\r
+ UINTN BitsOfAlignment;\r
+ UINT64 Alignment;\r
+ EFI_STATUS Status;\r
+ EFI_STATUS ReturnStatus;\r
+ PCI_RESOURCE_TYPE Index1;\r
+ PCI_RESOURCE_TYPE Index2;\r
+ BOOLEAN ResNodeHandled[TypeMax];\r
+ UINT64 MaxAlignment;\r
+\r
+ HostBridgeInstance = INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This);\r
+\r
+ switch (Phase) {\r
+ case EfiPciHostBridgeBeginEnumeration:\r
+ if (HostBridgeInstance->CanRestarted) {\r
+ //\r
+ // Reset Root Bridge\r
+ //\r
+ List = HostBridgeInstance->Head.ForwardLink;\r
+\r
+ while (List != &HostBridgeInstance->Head) {\r
+ RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);\r
+ for (Index = TypeIo; Index < TypeMax; Index++) {\r
+ RootBridgeInstance->ResAllocNode[Index].Type = Index;\r
+ RootBridgeInstance->ResAllocNode[Index].Base = 0;\r
+ RootBridgeInstance->ResAllocNode[Index].Length = 0;\r
+ RootBridgeInstance->ResAllocNode[Index].Status = ResNone;\r
+ } // for\r
+\r
+ List = List->ForwardLink;\r
+ } // while\r
+\r
+ HostBridgeInstance->ResourceSubmited = FALSE;\r
+ HostBridgeInstance->CanRestarted = TRUE;\r
+ } else {\r
+ //\r
+ // Can not restart\r
+ //\r
+ return EFI_NOT_READY;\r
+ } // if\r
+ break;\r
+\r
+ case EfiPciHostBridgeEndEnumeration:\r
+ return EFI_SUCCESS;\r
+ break;\r
+\r
+ case EfiPciHostBridgeBeginBusAllocation:\r
+ //\r
+ // No specific action is required here, can perform any chipset specific programing\r
+ //\r
+ HostBridgeInstance->CanRestarted = FALSE;\r
+ return EFI_SUCCESS;\r
+ break;\r
+\r
+ case EfiPciHostBridgeEndBusAllocation:\r
+ //\r
+ // No specific action is required here, can perform any chipset specific programing\r
+ //\r
+ // HostBridgeInstance->CanRestarted = FALSE;\r
+ //\r
+ return EFI_SUCCESS;\r
+ break;\r
+\r
+ case EfiPciHostBridgeBeginResourceAllocation:\r
+ //\r
+ // No specific action is required here, can perform any chipset specific programing\r
+ //\r
+ // HostBridgeInstance->CanRestarted = FALSE;\r
+ //\r
+ return EFI_SUCCESS;\r
+ break;\r
+\r
+ case EfiPciHostBridgeAllocateResources:\r
+ ReturnStatus = EFI_SUCCESS;\r
+ if (HostBridgeInstance->ResourceSubmited) {\r
+ List = HostBridgeInstance->Head.ForwardLink;\r
+ while (List != &HostBridgeInstance->Head) {\r
+ for (Index1 = TypeIo; Index1 < TypeBus; Index1++) {\r
+ ResNodeHandled[Index1] = FALSE;\r
+ }\r
+\r
+ RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);\r
+ DEBUG ((EFI_D_INFO, "Address of RootBridgeInstance: %x)\n", RootBridgeInstance));\r
+ DEBUG ((EFI_D_INFO, " Signature: %x\n", RootBridgeInstance->Signature));\r
+ DEBUG ((EFI_D_INFO, " Bus Number Assigned: %x\n", RootBridgeInstance->BusNumberAssigned));\r
+ DEBUG ((EFI_D_INFO, " Bus Scan Count: %x\n", RootBridgeInstance->BusScanCount));\r
+\r
+ for (Index1 = TypeIo; Index1 < TypeBus; Index1++) {\r
+ if (RootBridgeInstance->ResAllocNode[Index1].Status == ResNone) {\r
+ ResNodeHandled[Index1] = TRUE;\r
+ } else {\r
+ //\r
+ // Allocate the resource node with max alignment at first\r
+ //\r
+ MaxAlignment = 0;\r
+ Index = TypeMax;\r
+ for (Index2 = TypeIo; Index2 < TypeBus; Index2++) {\r
+ if (ResNodeHandled[Index2]) {\r
+ continue;\r
+ }\r
+ if (MaxAlignment <= RootBridgeInstance->ResAllocNode[Index2].Alignment) {\r
+ MaxAlignment = RootBridgeInstance->ResAllocNode[Index2].Alignment;\r
+ Index = Index2;\r
+ }\r
+ } // for\r
+\r
+ if (Index < TypeMax) {\r
+ ResNodeHandled[Index] = TRUE;\r
+ } else {\r
+ ASSERT (FALSE);\r
+ }\r
+\r
+ Alignment = RootBridgeInstance->ResAllocNode[Index].Alignment;\r
+\r
+ //\r
+ // Get the number of '1' in Alignment.\r
+ //\r
+ for (BitsOfAlignment = 0; Alignment != 0; BitsOfAlignment++) {\r
+ Alignment = RShiftU64 (Alignment, 1);\r
+ }\r
+\r
+ AddrLen = RootBridgeInstance->ResAllocNode[Index].Length;\r
+ Alignment = RootBridgeInstance->ResAllocNode[Index].Alignment;\r
+\r
+ DEBUG ((EFI_D_INFO, "\n\nResource Type to assign : %x\n", Index));\r
+ DEBUG ((EFI_D_INFO, " Length to allocate: %x\n", RootBridgeInstance->ResAllocNode[Index].Length));\r
+ DEBUG ((EFI_D_INFO, " Aligment: %x\n", Alignment));\r
+\r
+ switch (Index) {\r
+ case TypeIo:\r
+ if (RootBridgeInstance->Aperture.IoBase < RootBridgeInstance->Aperture.IoLimit) {\r
+ //\r
+ // It is impossible for 0xFFFF Alignment for IO16\r
+ //\r
+ if (BitsOfAlignment >= 16)\r
+ Alignment = 0;\r
+\r
+ BaseAddress = RootBridgeInstance->Aperture.IoBase;\r
+\r
+ //\r
+ // Have to make sure Aligment is handled seeing we are doing direct address allocation\r
+ //\r
+ if ((BaseAddress & ~(Alignment)) != BaseAddress)\r
+ BaseAddress = ((BaseAddress + Alignment) & ~(Alignment));\r
+\r
+ while((BaseAddress + AddrLen) <= RootBridgeInstance->Aperture.IoLimit + 1) {\r
+\r
+ Status = gDS->AllocateIoSpace ( EfiGcdAllocateAddress, EfiGcdIoTypeIo, BitsOfAlignment,\r
+ AddrLen, &BaseAddress, mDriverImageHandle, NULL );\r
+\r
+ if (!EFI_ERROR (Status)) {\r
+ RootBridgeInstance->ResAllocNode[Index].Base = (UINT64) BaseAddress;\r
+ RootBridgeInstance->ResAllocNode[Index].Status = ResAllocated;\r
+ goto TypeIoFound;\r
+ }\r
+\r
+ BaseAddress += (Alignment + 1);\r
+ } // while\r
+\r
+ } // if\r
+\r
+ TypeIoFound:\r
+ if (RootBridgeInstance->ResAllocNode[Index].Status != ResAllocated) {\r
+ //\r
+ // No Room at the Inn for this resources request\r
+ //\r
+ ReturnStatus = EFI_OUT_OF_RESOURCES;\r
+ } // if\r
+\r
+ break;\r
+\r
+ case TypeMem32:\r
+ if (RootBridgeInstance->Aperture.Mem32Base < RootBridgeInstance->Aperture.Mem32Limit) {\r
+\r
+ BaseAddress = RootBridgeInstance->Aperture.Mem32Base;\r
+ //\r
+ // Have to make sure Aligment is handled seeing we are doing direct address allocation\r
+ //\r
+ if ((BaseAddress & ~(Alignment)) != BaseAddress)\r
+ BaseAddress = ((BaseAddress + Alignment) & ~(Alignment));\r
+\r
+ while((BaseAddress + AddrLen) <= RootBridgeInstance->Aperture.Mem32Limit + 1) {\r
+\r
+ Status = gDS->AllocateMemorySpace ( EfiGcdAllocateAddress, EfiGcdMemoryTypeMemoryMappedIo,\r
+ BitsOfAlignment, AddrLen, &BaseAddress, mDriverImageHandle, NULL);\r
+\r
+ if (!EFI_ERROR (Status)) {\r
+ RootBridgeInstance->ResAllocNode[Index].Base = (UINT64) BaseAddress;\r
+ RootBridgeInstance->ResAllocNode[Index].Status = ResAllocated;\r
+ goto TypeMem32Found;\r
+ } // if\r
+\r
+ BaseAddress += (Alignment + 1);\r
+ } // while\r
+ } // if\r
+\r
+ TypeMem32Found:\r
+ if (RootBridgeInstance->ResAllocNode[Index].Status != ResAllocated) {\r
+ //\r
+ // No Room at the Inn for this resources request\r
+ //\r
+ ReturnStatus = EFI_OUT_OF_RESOURCES;\r
+ }\r
+\r
+ break;\r
+\r
+ case TypePMem32:\r
+ StartTypePMem32:\r
+ if (RootBridgeInstance->Aperture.Mem32Base < RootBridgeInstance->Aperture.Mem32Limit) {\r
+\r
+ BaseAddress = RootBridgeInstance->Aperture.Mem32Limit + 1;\r
+ BaseAddress -= AddrLen;\r
+\r
+ //\r
+ // Have to make sure Aligment is handled seeing we are doing direct address allocation\r
+ //\r
+ if ((BaseAddress & ~(Alignment)) != BaseAddress)\r
+ BaseAddress = ((BaseAddress) & ~(Alignment));\r
+\r
+ while(RootBridgeInstance->Aperture.Mem32Base <= BaseAddress) {\r
+\r
+ DEBUG ((EFI_D_INFO, " Attempting %x allocation at 0x%lx .....", Index, BaseAddress));\r
+ Status = gDS->AllocateMemorySpace ( EfiGcdAllocateAddress, EfiGcdMemoryTypeMemoryMappedIo,\r
+ BitsOfAlignment, AddrLen, &BaseAddress, mDriverImageHandle, NULL);\r
+\r
+ if (!EFI_ERROR (Status)) {\r
+ RootBridgeInstance->ResAllocNode[Index].Base = (UINT64) BaseAddress;\r
+ RootBridgeInstance->ResAllocNode[Index].Status = ResAllocated;\r
+ DEBUG ((EFI_D_INFO, "... Passed!!\n"));\r
+ goto TypePMem32Found;\r
+ }\r
+ DEBUG ((EFI_D_INFO, "... Failed!!\n"));\r
+ BaseAddress -= (Alignment + 1);\r
+ } // while\r
+ } // if\r
+\r
+ TypePMem32Found:\r
+ if (RootBridgeInstance->ResAllocNode[Index].Status != ResAllocated) {\r
+ //\r
+ // No Room at the Inn for this resources request\r
+ //\r
+ ReturnStatus = EFI_OUT_OF_RESOURCES;\r
+ }\r
+\r
+ break;\r
+\r
+ case TypeMem64:\r
+ case TypePMem64:\r
+ if (RootBridgeInstance->ResAllocNode[Index].Status != ResAllocated) {\r
+ //\r
+ // If 64-bit resourcing is not available, then try as PMem32\r
+ //\r
+ goto StartTypePMem32;\r
+ }\r
+\r
+ break;\r
+\r
+ default:\r
+ break;\r
+ } // End switch (Index)\r
+\r
+ DEBUG ((EFI_D_INFO, "Resource Type Assigned: %x\n", Index));\r
+ if (RootBridgeInstance->ResAllocNode[Index].Status == ResAllocated) {\r
+ DEBUG ((EFI_D_INFO, " Base Address Assigned: %x\n", RootBridgeInstance->ResAllocNode[Index].Base));\r
+ DEBUG ((EFI_D_INFO, " Length Assigned: %x\n", RootBridgeInstance->ResAllocNode[Index].Length));\r
+ } else {\r
+ DEBUG ((DEBUG_ERROR, " Resource Allocation failed! There was no room at the inn\n"));\r
+ }\r
+\r
+ }\r
+ }\r
+\r
+ List = List->ForwardLink;\r
+ }\r
+\r
+ if (ReturnStatus == EFI_OUT_OF_RESOURCES) {\r
+ DEBUG ((DEBUG_ERROR, "Resource allocation Failed. Continue booting the system.\n"));\r
+ }\r
+\r
+ //\r
+ // Set resource to zero for nodes where allocation fails\r
+ //\r
+ List = HostBridgeInstance->Head.ForwardLink;\r
+ while (List != &HostBridgeInstance->Head) {\r
+ RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);\r
+ for (Index = TypeIo; Index < TypeBus; Index++) {\r
+ if (RootBridgeInstance->ResAllocNode[Index].Status != ResAllocated) {\r
+ RootBridgeInstance->ResAllocNode[Index].Length = 0;\r
+ }\r
+ }\r
+ List = List->ForwardLink;\r
+ }\r
+ return ReturnStatus;\r
+ } else {\r
+ return EFI_NOT_READY;\r
+ }\r
+ //\r
+ // HostBridgeInstance->CanRestarted = FALSE;\r
+ //\r
+ break;\r
+\r
+ case EfiPciHostBridgeSetResources:\r
+ //\r
+ // HostBridgeInstance->CanRestarted = FALSE;\r
+ //\r
+ break;\r
+\r
+ case EfiPciHostBridgeFreeResources:\r
+ //\r
+ // HostBridgeInstance->CanRestarted = FALSE;\r
+ //\r
+ ReturnStatus = EFI_SUCCESS;\r
+ List = HostBridgeInstance->Head.ForwardLink;\r
+ while (List != &HostBridgeInstance->Head) {\r
+ RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);\r
+ for (Index = TypeIo; Index < TypeBus; Index++) {\r
+ if (RootBridgeInstance->ResAllocNode[Index].Status == ResAllocated) {\r
+ AddrLen = RootBridgeInstance->ResAllocNode[Index].Length;\r
+ BaseAddress = (EFI_PHYSICAL_ADDRESS) RootBridgeInstance->ResAllocNode[Index].Base;\r
+ switch (Index) {\r
+ case TypeIo:\r
+ Status = gDS->FreeIoSpace (BaseAddress, AddrLen);\r
+ if (EFI_ERROR (Status)) {\r
+ ReturnStatus = Status;\r
+ }\r
+ break;\r
+\r
+ case TypeMem32:\r
+ Status = gDS->FreeMemorySpace (BaseAddress, AddrLen);\r
+ if (EFI_ERROR (Status)) {\r
+ ReturnStatus = Status;\r
+ }\r
+ break;\r
+\r
+ case TypePMem32:\r
+ break;\r
+\r
+ case TypeMem64:\r
+ break;\r
+\r
+ case TypePMem64:\r
+ Status = gDS->FreeMemorySpace (BaseAddress, AddrLen);\r
+ if (EFI_ERROR (Status)) {\r
+ ReturnStatus = Status;\r
+ }\r
+ break;\r
+\r
+ default:\r
+ break;\r
+ } // end switch (Index)\r
+\r
+ RootBridgeInstance->ResAllocNode[Index].Type = Index;\r
+ RootBridgeInstance->ResAllocNode[Index].Base = 0;\r
+ RootBridgeInstance->ResAllocNode[Index].Length = 0;\r
+ RootBridgeInstance->ResAllocNode[Index].Status = ResNone;\r
+ }\r
+ }\r
+\r
+ List = List->ForwardLink;\r
+ }\r
+\r
+ HostBridgeInstance->ResourceSubmited = FALSE;\r
+ HostBridgeInstance->CanRestarted = TRUE;\r
+ return ReturnStatus;\r
+ break;\r
+\r
+ case EfiPciHostBridgeEndResourceAllocation:\r
+ //\r
+ // Resource enumeration is done. Perform any activities that\r
+ // must wait until that time.\r
+ //\r
+ break;\r
+\r
+ default:\r
+ return EFI_INVALID_PARAMETER;\r
+ } // End switch (Phase)\r
+\r
+ return EFI_SUCCESS;\r
+}\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+GetNextRootBridge (\r
+ IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r
+ IN OUT EFI_HANDLE *RootBridgeHandle\r
+ )\r
+/*++\r
+\r
+Routine Description:\r
+ Return the device handle of the next PCI root bridge that is associated with\r
+ this Host Bridge.\r
+\r
+Arguments:\r
+\r
+ This - The EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_ PROTOCOL instance.\r
+ RootBridgeHandle - Returns the device handle of the next PCI Root Bridge.\r
+ On input, it holds the RootBridgeHandle returned by the most\r
+ recent call to GetNextRootBridge().The handle for the first\r
+ PCI Root Bridge is returned if RootBridgeHandle is NULL on input.\r
+\r
+Returns:\r
+\r
+ EFI_SUCCESS - Succeed.\r
+ EFI_NOT_FOUND - Next PCI root bridge not found.\r
+ EFI_INVALID_PARAMETER - Wrong parameter passed in.\r
+\r
+--*/\r
+{\r
+ BOOLEAN NoRootBridge;\r
+ EFI_LIST_ENTRY *List;\r
+ PCI_HOST_BRIDGE_INSTANCE *HostBridgeInstance;\r
+ PCI_ROOT_BRIDGE_INSTANCE *RootBridgeInstance;\r
+\r
+ NoRootBridge = TRUE;\r
+ HostBridgeInstance = INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This);\r
+ List = HostBridgeInstance->Head.ForwardLink;\r
+\r
+ while (List != &HostBridgeInstance->Head) {\r
+ NoRootBridge = FALSE;\r
+ RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);\r
+ if (*RootBridgeHandle == NULL) {\r
+ //\r
+ // Return the first Root Bridge Handle of the Host Bridge\r
+ //\r
+ *RootBridgeHandle = RootBridgeInstance->Handle;\r
+ return EFI_SUCCESS;\r
+ } else {\r
+ if (*RootBridgeHandle == RootBridgeInstance->Handle) {\r
+ //\r
+ // Get next if have\r
+ //\r
+ List = List->ForwardLink;\r
+ if (List != &HostBridgeInstance->Head) {\r
+ RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);\r
+ *RootBridgeHandle = RootBridgeInstance->Handle;\r
+ return EFI_SUCCESS;\r
+ } else {\r
+ return EFI_NOT_FOUND;\r
+ }\r
+ }\r
+ }\r
+\r
+ List = List->ForwardLink;\r
+ //\r
+ // end while\r
+ //\r
+ }\r
+\r
+ if (NoRootBridge) {\r
+ return EFI_NOT_FOUND;\r
+ } else {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+}\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+GetAttributes (\r
+ IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r
+ IN EFI_HANDLE RootBridgeHandle,\r
+ OUT UINT64 *Attributes\r
+ )\r
+/*++\r
+\r
+Routine Description:\r
+ Returns the attributes of a PCI Root Bridge.\r
+\r
+Arguments:\r
+\r
+ This - The EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_ PROTOCOL instance.\r
+ RootBridgeHandle - The device handle of the PCI Root Bridge\r
+ that the caller is interested in.\r
+ Attributes - The pointer to attributes of the PCI Root Bridge.\r
+\r
+Returns:\r
+\r
+ EFI_SUCCESS - Succeed.\r
+ EFI_INVALID_PARAMETER - Attributes parameter passed in is NULL or\r
+ RootBridgeHandle is not an EFI_HANDLE\r
+ that was returned on a previous call to\r
+ GetNextRootBridge().\r
+\r
+--*/\r
+{\r
+ EFI_LIST_ENTRY *List;\r
+ PCI_HOST_BRIDGE_INSTANCE *HostBridgeInstance;\r
+ PCI_ROOT_BRIDGE_INSTANCE *RootBridgeInstance;\r
+\r
+ if (Attributes == NULL) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+\r
+ HostBridgeInstance = INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This);\r
+ List = HostBridgeInstance->Head.ForwardLink;\r
+\r
+ while (List != &HostBridgeInstance->Head) {\r
+ RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);\r
+ if (RootBridgeHandle == RootBridgeInstance->Handle) {\r
+ *Attributes = RootBridgeInstance->RootBridgeAllocAttrib;\r
+ return EFI_SUCCESS;\r
+ }\r
+\r
+ List = List->ForwardLink;\r
+ }\r
+ //\r
+ // RootBridgeHandle is not an EFI_HANDLE\r
+ // that was returned on a previous call to GetNextRootBridge()\r
+ //\r
+ return EFI_INVALID_PARAMETER;\r
+}\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+StartBusEnumeration (\r
+ IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r
+ IN EFI_HANDLE RootBridgeHandle,\r
+ OUT VOID **Configuration\r
+ )\r
+/*++\r
+\r
+Routine Description:\r
+ This is the request from the PCI enumerator to set up\r
+ the specified PCI Root Bridge for bus enumeration process.\r
+\r
+Arguments:\r
+\r
+ This - The EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_ PROTOCOL instance.\r
+ RootBridgeHandle - The PCI Root Bridge to be set up.\r
+ Configuration - Pointer to the pointer to the PCI bus resource descriptor.\r
+\r
+Returns:\r
+\r
+ EFI_SUCCESS - Succeed.\r
+ EFI_OUT_OF_RESOURCES - Not enough pool to be allocated.\r
+ EFI_INVALID_PARAMETER - RootBridgeHandle is not a valid handle.\r
+\r
+--*/\r
+{\r
+ EFI_LIST_ENTRY *List;\r
+ PCI_HOST_BRIDGE_INSTANCE *HostBridgeInstance;\r
+ PCI_ROOT_BRIDGE_INSTANCE *RootBridgeInstance;\r
+ VOID *Buffer;\r
+ UINT8 *Temp;\r
+ EFI_STATUS Status;\r
+ UINTN BusStart;\r
+ UINTN BusEnd;\r
+ UINT64 BusReserve;\r
+\r
+ HostBridgeInstance = INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This);\r
+ List = HostBridgeInstance->Head.ForwardLink;\r
+\r
+ while (List != &HostBridgeInstance->Head) {\r
+ RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);\r
+ if (RootBridgeHandle == RootBridgeInstance->Handle) {\r
+ //\r
+ // Set up the Root Bridge for Bus Enumeration\r
+ //\r
+ BusStart = RootBridgeInstance->Aperture.BusBase;\r
+ BusEnd = RootBridgeInstance->Aperture.BusLimit;\r
+ BusReserve = RootBridgeInstance->Aperture.BusReserve;\r
+ //\r
+ // Program the Hardware(if needed) if error return EFI_DEVICE_ERROR\r
+ //\r
+ Status = gBS->AllocatePool (\r
+ EfiBootServicesData,\r
+ sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR),\r
+ &Buffer\r
+ );\r
+ if (EFI_ERROR (Status)) {\r
+ return EFI_OUT_OF_RESOURCES;\r
+ }\r
+\r
+ Temp = (UINT8 *) Buffer;\r
+\r
+ ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Temp)->Desc = ACPI_ADDRESS_SPACE_DESCRIPTOR;\r
+ ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Temp)->Len = 0x2B;\r
+ ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Temp)->ResType = ACPI_ADDRESS_SPACE_TYPE_BUS;\r
+ ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Temp)->GenFlag = 0;\r
+ ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Temp)->SpecificFlag = 0;\r
+ ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Temp)->AddrSpaceGranularity = 0;\r
+ ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Temp)->AddrRangeMin = BusStart;\r
+ ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Temp)->AddrRangeMax = BusReserve;\r
+ ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Temp)->AddrTranslationOffset = 0;\r
+ ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Temp)->AddrLen = BusEnd - BusStart + 1;\r
+\r
+ Temp = Temp + sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR);\r
+ ((EFI_ACPI_END_TAG_DESCRIPTOR *) Temp)->Desc = ACPI_END_TAG_DESCRIPTOR;\r
+ ((EFI_ACPI_END_TAG_DESCRIPTOR *) Temp)->Checksum = 0x0;\r
+\r
+ *Configuration = Buffer;\r
+ return EFI_SUCCESS;\r
+ }\r
+\r
+ List = List->ForwardLink;\r
+ }\r
+\r
+ return EFI_INVALID_PARAMETER;\r
+}\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+SetBusNumbers (\r
+ IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r
+ IN EFI_HANDLE RootBridgeHandle,\r
+ IN VOID *Configuration\r
+ )\r
+/*++\r
+\r
+Routine Description:\r
+ This function programs the PCI Root Bridge hardware so that\r
+ it decodes the specified PCI bus range.\r
+\r
+Arguments:\r
+\r
+ This - The EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_ PROTOCOL instance.\r
+ RootBridgeHandle - The PCI Root Bridge whose bus range is to be programmed.\r
+ Configuration - The pointer to the PCI bus resource descriptor.\r
+\r
+Returns:\r
+\r
+ EFI_SUCCESS - Succeed.\r
+ EFI_INVALID_PARAMETER - Wrong parameters passed in.\r
+\r
+--*/\r
+{\r
+ EFI_LIST_ENTRY *List;\r
+ PCI_HOST_BRIDGE_INSTANCE *HostBridgeInstance;\r
+ PCI_ROOT_BRIDGE_INSTANCE *RootBridgeInstance;\r
+ UINT8 *Ptr;\r
+ UINTN BusStart;\r
+ UINTN BusEnd;\r
+ UINTN BusLen;\r
+\r
+ if (Configuration == NULL) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+\r
+ Ptr = Configuration;\r
+\r
+ //\r
+ // Check the Configuration is valid\r
+ //\r
+ if (*Ptr != ACPI_ADDRESS_SPACE_DESCRIPTOR) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+\r
+ if (((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Ptr)->ResType != ACPI_ADDRESS_SPACE_TYPE_BUS) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+\r
+ Ptr += sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR);\r
+ if (*Ptr != ACPI_END_TAG_DESCRIPTOR) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+\r
+ HostBridgeInstance = INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This);\r
+ List = HostBridgeInstance->Head.ForwardLink;\r
+\r
+ Ptr = Configuration;\r
+\r
+ while (List != &HostBridgeInstance->Head) {\r
+ RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);\r
+ if (RootBridgeHandle == RootBridgeInstance->Handle) {\r
+ BusStart = (UINTN) ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Ptr)->AddrRangeMin;\r
+ BusLen = (UINTN) ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Ptr)->AddrLen;\r
+ BusEnd = BusStart + BusLen - 1;\r
+\r
+ if (BusStart > BusEnd) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+\r
+ if ((BusStart < RootBridgeInstance->Aperture.BusBase) || (BusEnd > RootBridgeInstance->Aperture.BusLimit)) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+ //\r
+ // Update the Bus Range\r
+ //\r
+ RootBridgeInstance->ResAllocNode[TypeBus].Base = BusStart;\r
+ RootBridgeInstance->ResAllocNode[TypeBus].Length = BusLen;\r
+ RootBridgeInstance->ResAllocNode[TypeBus].Status = ResAllocated;\r
+ RootBridgeInstance->BusScanCount++;\r
+ if (RootBridgeInstance->BusScanCount > 0) {\r
+ //\r
+ // Only care about the 2nd PCI bus scanning\r
+ //\r
+ RootBridgeInstance->BusNumberAssigned = TRUE;\r
+ }\r
+\r
+ return EFI_SUCCESS;\r
+ }\r
+\r
+ List = List->ForwardLink;\r
+ }\r
+\r
+ return EFI_INVALID_PARAMETER;\r
+}\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+SubmitResources (\r
+ IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r
+ IN EFI_HANDLE RootBridgeHandle,\r
+ IN VOID *Configuration\r
+ )\r
+/*++\r
+\r
+Routine Description:\r
+\r
+ Submits the I/O and memory resource requirements for the specified PCI Root Bridge.\r
+\r
+Arguments:\r
+ This - The EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_ PROTOCOL instance.\r
+ RootBridgeHandle - The PCI Root Bridge whose I/O and memory resource requirements.\r
+ are being submitted.\r
+ Configuration - The pointer to the PCI I/O and PCI memory resource descriptor.\r
+\r
+Returns:\r
+\r
+ EFI_SUCCESS - Succeed.\r
+ EFI_INVALID_PARAMETER - Wrong parameters passed in.\r
+\r
+--*/\r
+{\r
+ EFI_LIST_ENTRY *List;\r
+ PCI_HOST_BRIDGE_INSTANCE *HostBridgeInstance;\r
+ PCI_ROOT_BRIDGE_INSTANCE *RootBridgeInstance;\r
+ UINT8 *Temp;\r
+ EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *ptr;\r
+ UINT64 AddrLen;\r
+ UINT64 Alignment;\r
+ UINT64 Value;\r
+\r
+ //\r
+ // Check the input parameter: Configuration\r
+ //\r
+ if (Configuration == NULL) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+\r
+ HostBridgeInstance = INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This);\r
+ List = HostBridgeInstance->Head.ForwardLink;\r
+\r
+ Temp = (UINT8 *) Configuration;\r
+ while (List != &HostBridgeInstance->Head) {\r
+ RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);\r
+ if (RootBridgeHandle == RootBridgeInstance->Handle) {\r
+ //\r
+ // Check the resource descriptors.\r
+ // If the Configuration includes one or more invalid resource descriptors, all the resource\r
+ // descriptors are ignored and the function returns EFI_INVALID_PARAMETER.\r
+ //\r
+ while (*Temp == ACPI_ADDRESS_SPACE_DESCRIPTOR) {\r
+ ptr = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Temp;\r
+ DEBUG ((EFI_D_INFO, " ptr->ResType:%x \n",ptr->ResType));\r
+ DEBUG ((EFI_D_INFO, " ptr->AddrLen:0x%lx AddrRangeMin:0x%lx AddrRangeMax:0x%lx\n\n",ptr->AddrLen,ptr->AddrRangeMin,ptr->AddrRangeMax));\r
+\r
+ switch (ptr->ResType) {\r
+ case ACPI_ADDRESS_SPACE_TYPE_MEM:\r
+ if (ptr->AddrSpaceGranularity != 32 && ptr->AddrSpaceGranularity != 64) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+ if (ptr->AddrSpaceGranularity == 32 && ptr->AddrLen > 0xffffffff) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+ //\r
+ // If the PCI root bridge does not support separate windows for nonprefetchable and\r
+ // prefetchable memory, then the PCI bus driver needs to include requests for\r
+ // prefetchable memory in the nonprefetchable memory pool.\r
+ //\r
+ if ((RootBridgeInstance->RootBridgeAllocAttrib & EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM) != 0 &&\r
+ ((ptr->SpecificFlag & (BIT2 | BIT1)) != 0)) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+ case ACPI_ADDRESS_SPACE_TYPE_IO:\r
+ //\r
+ // Check aligment, it should be of the form 2^n-1\r
+ //\r
+ Value = Power2MaxMemory (ptr->AddrRangeMax + 1);\r
+ if (Value != (ptr->AddrRangeMax + 1)) {\r
+ CpuDeadLoop();\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+ break;\r
+ case ACPI_ADDRESS_SPACE_TYPE_BUS:\r
+ default:\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+ Temp += sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) ;\r
+ }\r
+ if (*Temp != ACPI_END_TAG_DESCRIPTOR) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+\r
+ Temp = (UINT8 *) Configuration;\r
+ while (*Temp == ACPI_ADDRESS_SPACE_DESCRIPTOR) {\r
+ ptr = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Temp;\r
+\r
+ switch (ptr->ResType) {\r
+ case ACPI_ADDRESS_SPACE_TYPE_MEM:\r
+ AddrLen = (UINT64) ptr->AddrLen;\r
+ Alignment = (UINT64) ptr->AddrRangeMax;\r
+ if (ptr->AddrSpaceGranularity == 32) {\r
+ if (ptr->SpecificFlag == 0x06) {\r
+ //\r
+ // Apply from GCD\r
+ //\r
+ RootBridgeInstance->ResAllocNode[TypePMem32].Status = ResSubmitted;\r
+ } else {\r
+ RootBridgeInstance->ResAllocNode[TypeMem32].Length = AddrLen;\r
+ RootBridgeInstance->ResAllocNode[TypeMem32].Alignment = Alignment;\r
+ RootBridgeInstance->ResAllocNode[TypeMem32].Status = ResRequested;\r
+ HostBridgeInstance->ResourceSubmited = TRUE;\r
+ }\r
+ }\r
+\r
+ if (ptr->AddrSpaceGranularity == 64) {\r
+ if (ptr->SpecificFlag == 0x06) {\r
+ RootBridgeInstance->ResAllocNode[TypePMem64].Status = ResSubmitted;\r
+ } else {\r
+ RootBridgeInstance->ResAllocNode[TypeMem64].Length = AddrLen;\r
+ RootBridgeInstance->ResAllocNode[TypeMem64].Alignment = Alignment;\r
+ RootBridgeInstance->ResAllocNode[TypeMem64].Status = ResSubmitted;\r
+ HostBridgeInstance->ResourceSubmited = TRUE;\r
+ }\r
+ }\r
+ break;\r
+\r
+ case ACPI_ADDRESS_SPACE_TYPE_IO:\r
+ AddrLen = (UINT64) ptr->AddrLen;\r
+ Alignment = (UINT64) ptr->AddrRangeMax;\r
+ RootBridgeInstance->ResAllocNode[TypeIo].Length = AddrLen;\r
+ RootBridgeInstance->ResAllocNode[TypeIo].Alignment = Alignment;\r
+ RootBridgeInstance->ResAllocNode[TypeIo].Status = ResRequested;\r
+ HostBridgeInstance->ResourceSubmited = TRUE;\r
+ break;\r
+\r
+ default:\r
+ break;\r
+ }\r
+\r
+ Temp += sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR);\r
+ }\r
+\r
+ return EFI_SUCCESS;\r
+ }\r
+\r
+ List = List->ForwardLink;\r
+ }\r
+\r
+ return EFI_INVALID_PARAMETER;\r
+}\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+GetProposedResources (\r
+ IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r
+ IN EFI_HANDLE RootBridgeHandle,\r
+ OUT VOID **Configuration\r
+ )\r
+/*++\r
+\r
+Routine Description:\r
+ This function returns the proposed resource settings for the specified\r
+ PCI Root Bridge.\r
+\r
+Arguments:\r
+\r
+ This - The EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_ PROTOCOL instance.\r
+ RootBridgeHandle - The PCI Root Bridge handle.\r
+ Configuration - The pointer to the pointer to the PCI I/O\r
+ and memory resource descriptor.\r
+\r
+Returns:\r
+\r
+ EFI_SUCCESS - Succeed.\r
+ EFI_OUT_OF_RESOURCES - Not enough pool to be allocated.\r
+ EFI_INVALID_PARAMETER - RootBridgeHandle is not a valid handle.\r
+\r
+--*/\r
+{\r
+ EFI_LIST_ENTRY *List;\r
+ PCI_HOST_BRIDGE_INSTANCE *HostBridgeInstance;\r
+ PCI_ROOT_BRIDGE_INSTANCE *RootBridgeInstance;\r
+ UINTN Index;\r
+ UINTN Number;\r
+ VOID *Buffer;\r
+ UINT8 *Temp;\r
+ EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *ptr;\r
+ EFI_STATUS Status;\r
+ UINT64 ResStatus;\r
+\r
+ Buffer = NULL;\r
+ Number = 0;\r
+ //\r
+ // Get the Host Bridge Instance from the resource allocation protocol\r
+ //\r
+ HostBridgeInstance = INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This);\r
+ List = HostBridgeInstance->Head.ForwardLink;\r
+\r
+ //\r
+ // Enumerate the root bridges in this host bridge\r
+ //\r
+ while (List != &HostBridgeInstance->Head) {\r
+ RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);\r
+ if (RootBridgeHandle == RootBridgeInstance->Handle) {\r
+ for (Index = 0; Index < TypeBus; Index++) {\r
+ if (RootBridgeInstance->ResAllocNode[Index].Status != ResNone) {\r
+ Number++;\r
+ }\r
+ }\r
+\r
+ if (Number > 0) {\r
+ Status = gBS->AllocatePool (\r
+ EfiBootServicesData,\r
+ Number * sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR),\r
+ &Buffer\r
+ );\r
+\r
+ if (EFI_ERROR (Status)) {\r
+ return EFI_OUT_OF_RESOURCES;\r
+ }\r
+\r
+ ZeroMem (Buffer, sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) * Number + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR));\r
+ }\r
+\r
+ ASSERT (Buffer != NULL);\r
+ Temp = Buffer;\r
+ for (Index = 0; Index < TypeBus; Index++) {\r
+ if (RootBridgeInstance->ResAllocNode[Index].Status != ResNone) {\r
+ ptr = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Temp;\r
+ ResStatus = RootBridgeInstance->ResAllocNode[Index].Status;\r
+\r
+ switch (Index) {\r
+\r
+ case TypeIo:\r
+ //\r
+ // Io\r
+ //\r
+ ptr->Desc = 0x8A;\r
+ ptr->Len = 0x2B;\r
+ ptr->ResType = 1;\r
+ ptr->GenFlag = 0;\r
+ ptr->SpecificFlag = 0;\r
+ ptr->AddrRangeMin = RootBridgeInstance->ResAllocNode[Index].Base;\r
+ ptr->AddrRangeMax = 0;\r
+ ptr->AddrTranslationOffset = (ResStatus == ResAllocated) ? EFI_RESOURCE_SATISFIED : EFI_RESOURCE_LESS;\r
+ ptr->AddrLen = RootBridgeInstance->ResAllocNode[Index].Length;\r
+ break;\r
+\r
+ case TypeMem32:\r
+ //\r
+ // Memory 32\r
+ //\r
+ ptr->Desc = 0x8A;\r
+ ptr->Len = 0x2B;\r
+ ptr->ResType = 0;\r
+ ptr->GenFlag = 0;\r
+ ptr->SpecificFlag = 0;\r
+ ptr->AddrSpaceGranularity = 32;\r
+ ptr->AddrRangeMin = RootBridgeInstance->ResAllocNode[Index].Base;\r
+ ptr->AddrRangeMax = 0;\r
+ ptr->AddrTranslationOffset = (ResStatus == ResAllocated) ? EFI_RESOURCE_SATISFIED : EFI_RESOURCE_LESS;\r
+ ptr->AddrLen = RootBridgeInstance->ResAllocNode[Index].Length;\r
+ break;\r
+\r
+ case TypePMem32:\r
+ //\r
+ // Prefetch memory 32\r
+ //\r
+ ptr->Desc = 0x8A;\r
+ ptr->Len = 0x2B;\r
+ ptr->ResType = 0;\r
+ ptr->GenFlag = 0;\r
+ ptr->SpecificFlag = 6;\r
+ ptr->AddrSpaceGranularity = 32;\r
+ ptr->AddrRangeMin = 0;\r
+ ptr->AddrRangeMax = 0;\r
+ ptr->AddrTranslationOffset = EFI_RESOURCE_NONEXISTENT;\r
+ ptr->AddrLen = 0;\r
+ break;\r
+\r
+ case TypeMem64:\r
+ //\r
+ // Memory 64\r
+ //\r
+ ptr->Desc = 0x8A;\r
+ ptr->Len = 0x2B;\r
+ ptr->ResType = 0;\r
+ ptr->GenFlag = 0;\r
+ ptr->SpecificFlag = 0;\r
+ ptr->AddrSpaceGranularity = 64;\r
+ ptr->AddrRangeMin = RootBridgeInstance->ResAllocNode[Index].Base;\r
+ ptr->AddrRangeMax = 0;\r
+ ptr->AddrTranslationOffset = (ResStatus == ResAllocated) ? EFI_RESOURCE_SATISFIED : EFI_RESOURCE_LESS;\r
+ ptr->AddrLen = RootBridgeInstance->ResAllocNode[Index].Length;\r
+ break;\r
+\r
+ case TypePMem64:\r
+ //\r
+ // Prefetch memory 64\r
+ //\r
+ ptr->Desc = 0x8A;\r
+ ptr->Len = 0x2B;\r
+ ptr->ResType = 0;\r
+ ptr->GenFlag = 0;\r
+ ptr->SpecificFlag = 6;\r
+ ptr->AddrSpaceGranularity = 64;\r
+ ptr->AddrRangeMin = 0;\r
+ ptr->AddrRangeMax = 0;\r
+ ptr->AddrTranslationOffset = EFI_RESOURCE_NONEXISTENT;\r
+ ptr->AddrLen = 0;\r
+ break;\r
+ }\r
+\r
+ Temp += sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR);\r
+ }\r
+ }\r
+\r
+ ((EFI_ACPI_END_TAG_DESCRIPTOR *) Temp)->Desc = 0x79;\r
+ ((EFI_ACPI_END_TAG_DESCRIPTOR *) Temp)->Checksum = 0x0;\r
+\r
+ *Configuration = Buffer;\r
+\r
+ return EFI_SUCCESS;\r
+ }\r
+\r
+ List = List->ForwardLink;\r
+ }\r
+\r
+ return EFI_INVALID_PARAMETER;\r
+}\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+PreprocessController (\r
+ IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r
+ IN EFI_HANDLE RootBridgeHandle,\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS PciAddress,\r
+ IN EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE Phase\r
+ )\r
+/*++\r
+\r
+Routine Description:\r
+ This function is called for all the PCI controllers that the PCI\r
+ bus driver finds. Can be used to Preprogram the controller.\r
+\r
+Arguments:\r
+\r
+ This - The EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_ PROTOCOL instance.\r
+ RootBridgeHandle - The PCI Root Bridge handle.\r
+ PciAddress - Address of the controller on the PCI bus.\r
+ Phase - The Phase during resource allocation.\r
+\r
+Returns:\r
+\r
+ EFI_SUCCESS - Succeed.\r
+ EFI_INVALID_PARAMETER - RootBridgeHandle is not a valid handle.\r
+\r
+--*/\r
+{\r
+ BOOLEAN RootBridgeFound;\r
+ EFI_LIST_ENTRY *List;\r
+ PCI_HOST_BRIDGE_INSTANCE *HostBridgeInstance;\r
+ PCI_ROOT_BRIDGE_INSTANCE *RootBridgeInstance;\r
+\r
+ if (RootBridgeHandle == NULL) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+\r
+ RootBridgeFound = FALSE;\r
+ HostBridgeInstance = INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This);\r
+ List = HostBridgeInstance->Head.ForwardLink;\r
+\r
+ while (List != &HostBridgeInstance->Head) {\r
+ RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);\r
+\r
+ if (RootBridgeHandle == RootBridgeInstance->Handle) {\r
+ RootBridgeFound = TRUE;\r
+ break;\r
+ }\r
+ //\r
+ // Get next if have\r
+ //\r
+ List = List->ForwardLink;\r
+ }\r
+\r
+ if (RootBridgeFound == FALSE) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+\r
+ return EFI_SUCCESS;\r
+}\r
+\r
+UINT64\r
+Power2MaxMemory (\r
+ IN UINT64 MemoryLength\r
+ )\r
+/*++\r
+\r
+Routine Description:\r
+\r
+ Calculate maximum memory length that can be fit to a mtrr.\r
+\r
+Arguments:\r
+\r
+ MemoryLength - Input memory length.\r
+\r
+Returns:\r
+\r
+ Returned Maximum length.\r
+\r
+--*/\r
+{\r
+ UINT64 Result;\r
+\r
+ if (RShiftU64 (MemoryLength, 32)) {\r
+ Result = LShiftU64 ((UINT64) GetPowerOfTwo64 ((UINT32) RShiftU64 (MemoryLength, 32)), 32);\r
+ } else {\r
+ Result = (UINT64) GetPowerOfTwo64 ((UINT32) MemoryLength);\r
+ }\r
+\r
+ return Result;\r
+}\r
--- /dev/null
+/** @file\r
+The Header file of the Pci Host Bridge Driver.\r
+\r
+Copyright (c) 2013-2015 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+**/\r
+\r
+#ifndef _PCI_HOST_BRIDGE_H_\r
+#define _PCI_HOST_BRIDGE_H_\r
+\r
+\r
+#include <PiDxe.h>\r
+#include <IndustryStandard/Acpi.h>\r
+#include <IndustryStandard/Pci.h>\r
+#include <PciRootBridge.h>\r
+#include <Library/UefiDriverEntryPoint.h>\r
+#include <IndustryStandard/Pci22.h>\r
+#include <Library/UefiLib.h>\r
+#include <Guid/HobList.h>\r
+#include <Library/UefiRuntimeServicesTableLib.h>\r
+#include <Protocol/PciHostBridgeResourceAllocation.h>\r
+\r
+#define PCI_HOST_BRIDGE_SIGNATURE SIGNATURE_32 ('e', 'h', 's', 't')\r
+typedef struct {\r
+ UINTN Signature;\r
+ EFI_HANDLE HostBridgeHandle;\r
+ UINTN RootBridgeCount;\r
+ EFI_LIST_ENTRY Head;\r
+ BOOLEAN ResourceSubmited;\r
+ BOOLEAN CanRestarted;\r
+ EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL ResAlloc;\r
+} PCI_HOST_BRIDGE_INSTANCE;\r
+\r
+#define INSTANCE_FROM_RESOURCE_ALLOCATION_THIS(a) CR (a, PCI_HOST_BRIDGE_INSTANCE, ResAlloc, PCI_HOST_BRIDGE_SIGNATURE)\r
+\r
+typedef enum {\r
+ SocketResourceRatioChanged,\r
+ SocketResourceRatioNotChanged,\r
+ SocketResourceAdjustMax\r
+} SOCKET_RESOURCE_ADJUSTMENT_RESULT;\r
+\r
+//\r
+// Driver Entry Point\r
+//\r
+EFI_STATUS\r
+EFIAPI\r
+InitializePciHostBridge (\r
+ IN EFI_HANDLE ImageHandle,\r
+ IN EFI_SYSTEM_TABLE *SystemTable\r
+ )\r
+/*++\r
+\r
+Routine Description:\r
+\r
+ Entry point of this driver.\r
+\r
+Arguments:\r
+\r
+ ImageHandle - Image handle of this driver.\r
+ SystemTable - Pointer to standard EFI system table.\r
+\r
+Returns:\r
+\r
+ EFI_SUCCESS - Succeed.\r
+ EFI_DEVICE_ERROR - Fail to install PCI_ROOT_BRIDGE_IO protocol.\r
+\r
+--*/\r
+;\r
+\r
+//\r
+// HostBridge Resource Allocation interface\r
+//\r
+EFI_STATUS\r
+EFIAPI\r
+NotifyPhase (\r
+ IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r
+ IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PHASE Phase\r
+ )\r
+/*++\r
+\r
+Routine Description:\r
+\r
+ Enter a certain phase of the PCI enumeration process.\r
+\r
+Arguments:\r
+\r
+ This - The EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL instance.\r
+ Phase - The phase during enumeration.\r
+\r
+Returns:\r
+\r
+ EFI_SUCCESS - Succeed.\r
+ EFI_INVALID_PARAMETER - Wrong phase parameter passed in.\r
+ EFI_NOT_READY - Resources have not been submitted yet.\r
+\r
+--*/\r
+;\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+GetNextRootBridge (\r
+ IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r
+ IN OUT EFI_HANDLE *RootBridgeHandle\r
+ )\r
+/*++\r
+\r
+Routine Description:\r
+\r
+ Return the device handle of the next PCI root bridge that is associated with\r
+ this Host Bridge.\r
+\r
+Arguments:\r
+\r
+ This - The EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_ PROTOCOL instance.\r
+ RootBridgeHandle - Returns the device handle of the next PCI Root Bridge.\r
+ On input, it holds the RootBridgeHandle returned by the most\r
+ recent call to GetNextRootBridge().The handle for the first\r
+ PCI Root Bridge is returned if RootBridgeHandle is NULL on input.\r
+\r
+Returns:\r
+\r
+ EFI_SUCCESS - Succeed.\r
+ EFI_NOT_FOUND - Next PCI root bridge not found.\r
+ EFI_INVALID_PARAMETER - Wrong parameter passed in.\r
+\r
+--*/\r
+;\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+GetAttributes (\r
+ IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r
+ IN EFI_HANDLE RootBridgeHandle,\r
+ OUT UINT64 *Attributes\r
+ )\r
+/*++\r
+\r
+Routine Description:\r
+\r
+ Returns the attributes of a PCI Root Bridge.\r
+\r
+Arguments:\r
+\r
+ This - The EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_ PROTOCOL instance\r
+ RootBridgeHandle - The device handle of the PCI Root Bridge\r
+ that the caller is interested in\r
+ Attributes - The pointer to attributes of the PCI Root Bridge\r
+\r
+Returns:\r
+\r
+ EFI_SUCCESS - Succeed.\r
+ EFI_INVALID_PARAMETER - Attributes parameter passed in is NULL or\r
+ RootBridgeHandle is not an EFI_HANDLE\r
+ that was returned on a previous call to\r
+ GetNextRootBridge().\r
+\r
+--*/\r
+;\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+StartBusEnumeration (\r
+ IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r
+ IN EFI_HANDLE RootBridgeHandle,\r
+ OUT VOID **Configuration\r
+ )\r
+/*++\r
+\r
+Routine Description:\r
+\r
+ This is the request from the PCI enumerator to set up\r
+ the specified PCI Root Bridge for bus enumeration process.\r
+\r
+Arguments:\r
+\r
+ This - The EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_ PROTOCOL instance.\r
+ RootBridgeHandle - The PCI Root Bridge to be set up.\r
+ Configuration - Pointer to the pointer to the PCI bus resource descriptor.\r
+\r
+Returns:\r
+\r
+ EFI_SUCCESS - Succeed.\r
+ EFI_OUT_OF_RESOURCES - Not enough pool to be allocated.\r
+ EFI_INVALID_PARAMETER - RootBridgeHandle is not a valid handle.\r
+\r
+--*/\r
+;\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+SetBusNumbers (\r
+ IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r
+ IN EFI_HANDLE RootBridgeHandle,\r
+ IN VOID *Configuration\r
+ )\r
+/*++\r
+\r
+Routine Description:\r
+\r
+ This function programs the PCI Root Bridge hardware so that\r
+ it decodes the specified PCI bus range.\r
+\r
+Arguments:\r
+\r
+ This - The EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_ PROTOCOL instance.\r
+ RootBridgeHandle - The PCI Root Bridge whose bus range is to be programmed.\r
+ Configuration - The pointer to the PCI bus resource descriptor.\r
+\r
+Returns:\r
+\r
+ EFI_SUCCESS - Succeed.\r
+ EFI_INVALID_PARAMETER - Wrong parameters passed in.\r
+\r
+--*/\r
+;\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+SubmitResources (\r
+ IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r
+ IN EFI_HANDLE RootBridgeHandle,\r
+ IN VOID *Configuration\r
+ )\r
+/*++\r
+\r
+Routine Description:\r
+\r
+ Submits the I/O and memory resource requirements for the specified PCI Root Bridge.\r
+\r
+Arguments:\r
+\r
+ This - The EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_ PROTOCOL instance\r
+ RootBridgeHandle - The PCI Root Bridge whose I/O and memory resource requirements\r
+ are being submitted\r
+ Configuration - The pointer to the PCI I/O and PCI memory resource descriptor\r
+\r
+Returns:\r
+\r
+ EFI_SUCCESS - Succeed.\r
+ EFI_INVALID_PARAMETER - Wrong parameters passed in.\r
+\r
+--*/\r
+;\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+GetProposedResources (\r
+ IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r
+ IN EFI_HANDLE RootBridgeHandle,\r
+ OUT VOID **Configuration\r
+ )\r
+/*++\r
+\r
+Routine Description:\r
+\r
+ This function returns the proposed resource settings for the specified\r
+ PCI Root Bridge.\r
+\r
+Arguments:\r
+\r
+ This - The EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_ PROTOCOL instance.\r
+ RootBridgeHandle - The PCI Root Bridge handle.\r
+ Configuration - The pointer to the pointer to the PCI I/O\r
+ and memory resource descriptor.\r
+\r
+Returns:\r
+\r
+ EFI_SUCCESS - Succeed.\r
+ EFI_OUT_OF_RESOURCES - Not enough pool to be allocated.\r
+ EFI_INVALID_PARAMETER - RootBridgeHandle is not a valid handle.\r
+\r
+--*/\r
+;\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+PreprocessController (\r
+ IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r
+ IN EFI_HANDLE RootBridgeHandle,\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS PciAddress,\r
+ IN EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE Phase\r
+ )\r
+/*++\r
+\r
+Routine Description:\r
+\r
+ This function is called for all the PCI controllers that the PCI\r
+ bus driver finds. Can be used to Preprogram the controller.\r
+\r
+Arguments:\r
+\r
+ This - The EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_ PROTOCOL instance.\r
+ RootBridgeHandle - The PCI Root Bridge handle.\r
+ PciAddress - Address of the controller on the PCI bus.\r
+ Phase - The Phase during resource allocation.\r
+\r
+Returns:\r
+\r
+ EFI_SUCCESS - Succeed.\r
+ EFI_INVALID_PARAMETER - RootBridgeHandle is not a valid handle.\r
+\r
+--*/\r
+;\r
+\r
+//\r
+// Host Bridge Silicon specific hooks\r
+//\r
+UINT64\r
+GetAllocAttributes (\r
+ IN UINTN RootBridgeIndex\r
+ )\r
+/*++\r
+\r
+Routine Description:\r
+\r
+ Returns the Allocation attributes for the BNB Root Bridge.\r
+\r
+Arguments:\r
+\r
+ RootBridgeIndex - The root bridge number. 0 based.\r
+\r
+Returns:\r
+\r
+ EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM | EFI_PCI_HOST_BRIDGE_MEM64_DECODE\r
+\r
+--*/\r
+;\r
+\r
+EFI_STATUS\r
+GetHostBridgeMemApertures (\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo,\r
+ OUT UINT32 *Mem32Base,\r
+ OUT UINT32 *Mem32Limit,\r
+ OUT UINT64 *Mem64Base,\r
+ OUT UINT64 *Mem64Limit\r
+ )\r
+/*++\r
+\r
+Routine Description:\r
+\r
+ Returns memory apertures for the BNB Root Bridge.\r
+\r
+Arguments:\r
+\r
+ PciRootBridgeIo - Pointer to Efi Pci root bridge Io protocol interface instance.\r
+ Mem32Base - Pointer to 32 bit memory base. This is the lowest 32 bit memory address\r
+ that is decoded by the Host Bridge.\r
+ Mem32Limit - Pointer to 32 bit memory limit.This is the highest 32 bit memory address\r
+ that is decoded by the Host Bridge. The size of the 32 bit window is\r
+ (Mem32Limit - Mem32base + 1).\r
+ Mem64Base - Pointer to 64 bit memory base. This is the lowest 64 bit memory address\r
+ that is decoded by the Host Bridge.\r
+ Mem64Limit - Pointer to 64 bit memory limit.This is the highest 64 bit memory address\r
+ that is decoded by the Host Bridge. The size of the 64 bit window is\r
+ (Mem64Limit - Mem64base + 1). Set Mem64Limit < Mem64Base if the host bridge\r
+ does not support 64 bit memory addresses.\r
+\r
+Returns:\r
+\r
+ EFI_SUCCESS - Success.\r
+\r
+--*/\r
+;\r
+\r
+UINT64\r
+Power2MaxMemory (\r
+ IN UINT64 MemoryLength\r
+ )\r
+/*++\r
+\r
+Routine Description:\r
+\r
+ Calculate maximum memory length that can be fit to a mtrr.\r
+\r
+Arguments:\r
+\r
+ MemoryLength - Input memory length.\r
+\r
+Returns:\r
+\r
+ Returned Maximum length.\r
+\r
+--*/\r
+;\r
+\r
+#endif\r
--- /dev/null
+## @file\r
+# Component description file for PciHostBridge module\r
+#\r
+# Copyright (c) 2013-2015 Intel Corporation.\r
+#\r
+# This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution. The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php\r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+##\r
+\r
+\r
+[Defines]\r
+ INF_VERSION = 0x00010005\r
+ BASE_NAME = PciHostBridge\r
+ FILE_GUID = D58EBCE1-AF26-488d-BE66-C164417F8C13\r
+ MODULE_TYPE = DXE_DRIVER\r
+ VERSION_STRING = 1.0\r
+ ENTRY_POINT = InitializePciHostBridge\r
+\r
+[Sources]\r
+ PciHostBridge.h\r
+ PciRootBridge.h\r
+ PciHostBridge.c\r
+ PciRootBridgeIo.c\r
+ PciHostBridgeSupport.c\r
+ PciHostResource.h\r
+\r
+[Packages]\r
+ MdePkg/MdePkg.dec\r
+ QuarkSocPkg/QuarkSocPkg.dec\r
+ QuarkPlatformPkg/QuarkPlatformPkg.dec\r
+\r
+[LibraryClasses]\r
+ UefiDriverEntryPoint\r
+ UefiBootServicesTableLib\r
+ DebugLib\r
+ UefiLib\r
+ DxeServicesTableLib\r
+ UefiRuntimeServicesTableLib\r
+ DevicePathLib\r
+ BaseMemoryLib\r
+ BaseLib\r
+\r
+[Protocols]\r
+ gEfiMetronomeArchProtocolGuid\r
+ gEfiCpuIo2ProtocolGuid\r
+ gEfiDevicePathProtocolGuid\r
+ gEfiPciRootBridgeIoProtocolGuid\r
+ gEfiPciHostBridgeResourceAllocationProtocolGuid\r
+\r
+[Pcd]\r
+ gEfiQuarkNcSocIdTokenSpaceGuid.PcdPciHostBridgeIoBase\r
+ gEfiQuarkNcSocIdTokenSpaceGuid.PcdPciHostBridgeIoSize\r
+ gEfiQuarkNcSocIdTokenSpaceGuid.PcdPciHostBridgeMemory32Base\r
+ gEfiQuarkNcSocIdTokenSpaceGuid.PcdPciHostBridgeMemory32Size\r
+ gEfiQuarkNcSocIdTokenSpaceGuid.PcdPciHostBridgeMemory64Base\r
+ gEfiQuarkNcSocIdTokenSpaceGuid.PcdPciHostBridgeMemory64Size\r
+ gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress\r
+ gEfiQuarkNcSocIdTokenSpaceGuid.PcdPciExpressSize\r
+\r
+[Depex]\r
+ gEfiCpuIo2ProtocolGuid AND gEfiMetronomeArchProtocolGuid\r
--- /dev/null
+/** @file\r
+Do platform initialization for PCI bridge.\r
+\r
+Copyright (c) 2013-2015 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+**/\r
+\r
+#include "PciHostBridge.h"\r
+\r
+EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *mPciRootBridgeIo;\r
+\r
+EFI_STATUS\r
+ChipsetPreprocessController (\r
+ IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r
+ IN EFI_HANDLE RootBridgeHandle,\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS PciAddress,\r
+ IN EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE Phase\r
+ )\r
+/*++\r
+\r
+Routine Description:\r
+ This function is called for all the PCI controllers that the PCI\r
+ bus driver finds. Can be used to Preprogram the controller.\r
+\r
+Arguments:\r
+ This -- The EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_ PROTOCOL instance\r
+ RootBridgeHandle -- The PCI Root Bridge handle\r
+ PciBusAddress -- Address of the controller on the PCI bus\r
+ Phase -- The Phase during resource allocation\r
+\r
+Returns:\r
+ EFI_SUCCESS\r
+\r
+--*/\r
+\r
+// GC_TODO: PciAddress - add argument and description to function comment\r
+//\r
+// GC_TODO: PciAddress - add argument and description to function comment\r
+//\r
+// GC_TODO: PciAddress - add argument and description to function comment\r
+//\r
+// GC_TODO: PciAddress - add argument and description to function comment\r
+//\r
+{\r
+\r
+ EFI_STATUS Status;\r
+ UINT8 Latency;\r
+ UINT8 CacheLineSize;\r
+\r
+ if (mPciRootBridgeIo == NULL) {\r
+ //\r
+ // Get root bridge in the system.\r
+ //\r
+ Status = gBS->HandleProtocol (RootBridgeHandle, &gEfiPciRootBridgeIoProtocolGuid, (VOID **) &mPciRootBridgeIo);\r
+ ASSERT_EFI_ERROR (Status);\r
+ }\r
+\r
+ if (Phase == EfiPciBeforeResourceCollection) {\r
+ //\r
+ // Program the latency register, CLS register\r
+ //\r
+ PciAddress.Register = PCI_LATENCY_TIMER_OFFSET;\r
+ mPciRootBridgeIo->Pci.Read (\r
+ mPciRootBridgeIo,\r
+ EfiPciWidthUint8,\r
+ *((UINT64 *) &PciAddress),\r
+ 1,\r
+ &Latency\r
+ );\r
+\r
+ //\r
+ // PCI-x cards come up with a default latency of 0x40. Don't touch them.\r
+ //\r
+ if (Latency == 0) {\r
+ Latency = DEFAULT_PCI_LATENCY;\r
+ mPciRootBridgeIo->Pci.Write (\r
+ mPciRootBridgeIo,\r
+ EfiPciWidthUint8,\r
+ *((UINT64 *) &PciAddress),\r
+ 1,\r
+ &Latency\r
+ );\r
+ }\r
+ //\r
+ // Program Cache Line Size as 64bytes\r
+ // 16 of DWORDs = 64bytes (0x10)\r
+ //\r
+ PciAddress.Register = PCI_CACHELINE_SIZE_OFFSET;\r
+ CacheLineSize = 0x10;\r
+ mPciRootBridgeIo->Pci.Write (\r
+ mPciRootBridgeIo,\r
+ EfiPciWidthUint8,\r
+ *((UINT64 *) &PciAddress),\r
+ 1,\r
+ &CacheLineSize\r
+ );\r
+\r
+ }\r
+\r
+ return EFI_SUCCESS;\r
+}\r
+\r
+UINT64\r
+GetAllocAttributes (\r
+ IN UINTN RootBridgeIndex\r
+ )\r
+/*++\r
+\r
+Routine Description:\r
+\r
+ Returns the Allocation attributes for the BNB Root Bridge.\r
+\r
+Arguments:\r
+\r
+ RootBridgeIndex - The root bridge number. 0 based.\r
+\r
+Returns:\r
+\r
+ EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM | EFI_PCI_HOST_BRIDGE_MEM64_DECODE\r
+\r
+--*/\r
+{\r
+ //\r
+ // Cannot have more than one Root bridge\r
+ //\r
+ //ASSERT (RootBridgeIndex == 0);\r
+\r
+ //\r
+ // PCI Root Bridge does not support separate windows for Non-prefetchable\r
+ // and Prefetchable memory. A PCI bus driver needs to include requests for\r
+ // Prefetchable memory in the Non-prefetchable memory pool.\r
+ // Further TNB does not support 64 bit memory apertures for PCI. BNB\r
+ // can only have system memory above 4 GB,\r
+ //\r
+\r
+ return EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM | EFI_PCI_HOST_BRIDGE_MEM64_DECODE;\r
+}\r
--- /dev/null
+/** @file\r
+The Header file of the Pci Host Bridge Driver.\r
+\r
+Copyright (c) 2013-2015 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+**/\r
+\r
+#ifndef _PCI_HOST_RESOURCE_H_\r
+#define _PCI_HOST_RESOURCE_H_\r
+\r
+#include <PiDxe.h>\r
+\r
+#define EFI_RESOURCE_NONEXISTENT 0xFFFFFFFFFFFFFFFFULL\r
+#define EFI_RESOURCE_LESS 0xFFFFFFFFFFFFFFFEULL\r
+\r
+typedef struct {\r
+ UINTN BusBase;\r
+ UINTN BusLimit;\r
+ UINTN BusReserve;\r
+\r
+ UINT32 Mem32Base;\r
+ UINT32 Mem32Limit;\r
+\r
+ UINT64 Mem64Base;\r
+ UINT64 Mem64Limit;\r
+\r
+ UINTN IoBase;\r
+ UINTN IoLimit;\r
+} PCI_ROOT_BRIDGE_RESOURCE_APERTURE;\r
+\r
+typedef enum {\r
+ TypeIo = 0,\r
+ TypeMem32,\r
+ TypePMem32,\r
+ TypeMem64,\r
+ TypePMem64,\r
+ TypeBus,\r
+ TypeMax\r
+} PCI_RESOURCE_TYPE;\r
+\r
+typedef enum {\r
+ ResNone = 0,\r
+ ResSubmitted,\r
+ ResRequested,\r
+ ResAllocated,\r
+ ResStatusMax\r
+} RES_STATUS;\r
+\r
+typedef struct {\r
+ PCI_RESOURCE_TYPE Type;\r
+ UINT64 Base;\r
+ UINT64 Length;\r
+ UINT64 Alignment;\r
+ RES_STATUS Status;\r
+} PCI_RES_NODE;\r
+\r
+#endif\r
--- /dev/null
+/** @file\r
+The PCI Root Bridge header file.\r
+\r
+Copyright (c) 2013-2015 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+**/\r
+\r
+#ifndef _PCI_ROOT_BRIDGE_H_\r
+#define _PCI_ROOT_BRIDGE_H_\r
+\r
+#include <PiDxe.h>\r
+#include <IndustryStandard/Acpi.h>\r
+#include <IndustryStandard/Pci.h>\r
+#include <PciHostResource.h>\r
+\r
+//\r
+// Driver Consumed Protocol Prototypes\r
+//\r
+#include <Protocol/Metronome.h>\r
+#include <Protocol/CpuIo2.h>\r
+#include <Protocol/DevicePath.h>\r
+#include <Protocol/Runtime.h>\r
+#include <Protocol/PciRootBridgeIo.h>\r
+#include <Library/UefiLib.h>\r
+#include <Library/DebugLib.h>\r
+#include <Library/DevicePathLib.h>\r
+#include <Library/BaseMemoryLib.h>\r
+#include <Library/DxeServicesTableLib.h>\r
+#include <Library/UefiBootServicesTableLib.h>\r
+#include <Library/BaseLib.h>\r
+\r
+\r
+//\r
+// Define the region of memory used for DMA memory\r
+//\r
+#define DMA_MEMORY_TOP 0x0000000001FFFFFFULL\r
+\r
+//\r
+// The number of PCI root bridges\r
+//\r
+#define ROOT_BRIDGE_COUNT 1\r
+\r
+//\r
+// The default latency for controllers\r
+//\r
+#define DEFAULT_PCI_LATENCY 0x20\r
+\r
+//\r
+// Define resource status constant\r
+//\r
+typedef struct {\r
+ EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION Operation;\r
+ UINTN NumberOfBytes;\r
+ UINTN NumberOfPages;\r
+ EFI_PHYSICAL_ADDRESS HostAddress;\r
+ EFI_PHYSICAL_ADDRESS MappedHostAddress;\r
+} MAP_INFO;\r
+\r
+typedef struct {\r
+ ACPI_HID_DEVICE_PATH AcpiDevicePath;\r
+ EFI_DEVICE_PATH_PROTOCOL EndDevicePath;\r
+} EFI_PCI_ROOT_BRIDGE_DEVICE_PATH;\r
+\r
+#define PCI_ROOT_BRIDGE_SIGNATURE SIGNATURE_32 ('e', '2', 'p', 'b')\r
+\r
+typedef struct {\r
+ UINT32 Signature;\r
+ EFI_LIST_ENTRY Link;\r
+ EFI_HANDLE Handle;\r
+ UINT64 RootBridgeAllocAttrib;\r
+ UINT64 Attributes;\r
+ UINT64 Supports;\r
+ PCI_RES_NODE ResAllocNode[6];\r
+ PCI_ROOT_BRIDGE_RESOURCE_APERTURE Aperture;\r
+ EFI_LOCK PciLock;\r
+ UINTN PciAddress;\r
+ UINTN PciData;\r
+ UINT32 HecBase;\r
+ UINT32 HecLen;\r
+ UINTN BusScanCount;\r
+ BOOLEAN BusNumberAssigned;\r
+ VOID *ConfigBuffer;\r
+ EFI_DEVICE_PATH_PROTOCOL *DevicePath;\r
+ EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL Io;\r
+} PCI_ROOT_BRIDGE_INSTANCE;\r
+\r
+//\r
+// Driver Instance Data Macros\r
+//\r
+#define DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS(a) CR (a, PCI_ROOT_BRIDGE_INSTANCE, Io, PCI_ROOT_BRIDGE_SIGNATURE)\r
+\r
+#define DRIVER_INSTANCE_FROM_LIST_ENTRY(a) CR (a, PCI_ROOT_BRIDGE_INSTANCE, Link, PCI_ROOT_BRIDGE_SIGNATURE)\r
+\r
+EFI_STATUS\r
+SimpleIioRootBridgeConstructor (\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *Protocol,\r
+ IN EFI_HANDLE HostBridgeHandle,\r
+ IN PCI_ROOT_BRIDGE_RESOURCE_APERTURE *ResAppeture,\r
+ IN UINT64 AllocAttributes\r
+ )\r
+/*++\r
+\r
+Routine Description:\r
+\r
+ Construct the Pci Root Bridge Io protocol.\r
+\r
+Arguments:\r
+\r
+ Protocol - Protocol to initialize.\r
+ HostBridgeHandle - Handle to the HostBridge.\r
+ ResAppeture - Resource apperture of the root bridge.\r
+ AllocAttributes - Attribute of resouce allocated.\r
+\r
+Returns:\r
+\r
+ EFI_SUCCESS - Success.\r
+ Others - Fail.\r
+\r
+--*/\r
+;\r
+\r
+//\r
+// Protocol Member Function Prototypes\r
+//\r
+EFI_STATUS\r
+EFIAPI\r
+RootBridgeIoPollMem (\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
+ IN UINT64 Address,\r
+ IN UINT64 Mask,\r
+ IN UINT64 Value,\r
+ IN UINT64 Delay,\r
+ OUT UINT64 *Result\r
+ )\r
+/*++\r
+\r
+Routine Description:\r
+\r
+ Poll an address in memory mapped space until an exit condition is met\r
+ or a timeout occurs.\r
+\r
+Arguments:\r
+\r
+ This - Pointer to EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL instance.\r
+ Width - Width of the memory operation.\r
+ Address - The base address of the memory operation.\r
+ Mask - Mask used for polling criteria.\r
+ Value - Comparison value used for polling exit criteria.\r
+ Delay - Number of 100ns units to poll.\r
+ Result - Pointer to the last value read from memory location.\r
+\r
+Returns:\r
+\r
+ EFI_SUCCESS - Success.\r
+ EFI_INVALID_PARAMETER - Invalid parameter found.\r
+ EFI_TIMEOUT - Delay expired before a match occurred.\r
+ EFI_OUT_OF_RESOURCES - Fail due to lack of resources.\r
+\r
+--*/\r
+;\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+RootBridgeIoPollIo (\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
+ IN UINT64 Address,\r
+ IN UINT64 Mask,\r
+ IN UINT64 Value,\r
+ IN UINT64 Delay,\r
+ OUT UINT64 *Result\r
+ )\r
+/*++\r
+\r
+Routine Description:\r
+\r
+ Poll an address in I/O space until an exit condition is met\r
+ or a timeout occurs.\r
+\r
+Arguments:\r
+\r
+ This - Pointer to EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL instance.\r
+ Width - Width of I/O operation.\r
+ Address - The base address of the I/O operation.\r
+ Mask - Mask used for polling criteria.\r
+ Value - Comparison value used for polling exit criteria.\r
+ Delay - Number of 100ns units to poll.\r
+ Result - Pointer to the last value read from memory location.\r
+\r
+Returns:\r
+\r
+ EFI_SUCCESS - Success.\r
+ EFI_INVALID_PARAMETER - Invalid parameter found.\r
+ EFI_TIMEOUT - Delay expired before a match occurred.\r
+ EFI_OUT_OF_RESOURCES - Fail due to lack of resources.\r
+\r
+--*/\r
+;\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+RootBridgeIoMemRead (\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
+ IN UINT64 Address,\r
+ IN UINTN Count,\r
+ IN OUT VOID *Buffer\r
+ )\r
+/*++\r
+\r
+Routine Description:\r
+\r
+ Allow read from memory mapped I/O space.\r
+\r
+Arguments:\r
+\r
+ This - Pointer to EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL instance.\r
+ Width - The width of memory operation.\r
+ Address - Base address of the memory operation.\r
+ Count - Number of memory opeartion to perform.\r
+ Buffer - The destination buffer to store data.\r
+\r
+Returns:\r
+\r
+ EFI_SUCCESS - Success.\r
+ EFI_INVALID_PARAMETER - Invalid parameter found.\r
+ EFI_OUT_OF_RESOURCES - Fail due to lack of resources.\r
+\r
+--*/\r
+;\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+RootBridgeIoMemWrite (\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
+ IN UINT64 Address,\r
+ IN UINTN Count,\r
+ IN OUT VOID *Buffer\r
+ )\r
+/*++\r
+\r
+Routine Description:\r
+\r
+ Allow write to memory mapped I/O space.\r
+\r
+Arguments:\r
+\r
+ This - Pointer to EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL instance.\r
+ Width - The width of memory operation.\r
+ Address - Base address of the memory operation.\r
+ Count - Number of memory opeartion to perform.\r
+ Buffer - The source buffer to write data from.\r
+\r
+Returns:\r
+\r
+ EFI_SUCCESS - Success.\r
+ EFI_INVALID_PARAMETER - Invalid parameter found.\r
+ EFI_OUT_OF_RESOURCES - Fail due to lack of resources.\r
+\r
+--*/\r
+;\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+RootBridgeIoIoRead (\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
+ IN UINT64 UserAddress,\r
+ IN UINTN Count,\r
+ IN OUT VOID *UserBuffer\r
+ )\r
+/*++\r
+\r
+Routine Description:\r
+\r
+ Enable a PCI driver to read PCI controller registers in the\r
+ PCI root bridge I/O space.\r
+\r
+Arguments:\r
+\r
+ This - A pointer to EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL\r
+ Width - Signifies the width of the memory operation.\r
+ UserAddress - The base address of the I/O operation.\r
+ Count - The number of I/O operations to perform.\r
+ UserBuffer - The destination buffer to store the results.\r
+\r
+Returns:\r
+\r
+ EFI_SUCCESS - The data was read from the PCI root bridge.\r
+ EFI_INVALID_PARAMETER - Invalid parameters found.\r
+ EFI_OUT_OF_RESOURCES - The request could not be completed due to a lack of\r
+ resources.\r
+--*/\r
+;\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+RootBridgeIoIoWrite (\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
+ IN UINT64 UserAddress,\r
+ IN UINTN Count,\r
+ IN OUT VOID *UserBuffer\r
+ )\r
+/*++\r
+\r
+Routine Description:\r
+\r
+ Enable a PCI driver to write to PCI controller registers in the\r
+ PCI root bridge I/O space.\r
+\r
+Arguments:\r
+\r
+ This - A pointer to EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL\r
+ Width - Signifies the width of the memory operation.\r
+ UserAddress - The base address of the I/O operation.\r
+ Count - The number of I/O operations to perform.\r
+ UserBuffer - The source buffer to write data from.\r
+\r
+Returns:\r
+\r
+ EFI_SUCCESS - The data was written to the PCI root bridge.\r
+ EFI_INVALID_PARAMETER - Invalid parameters found.\r
+ EFI_OUT_OF_RESOURCES - The request could not be completed due to a lack of\r
+ resources.\r
+--*/\r
+;\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+RootBridgeIoCopyMem (\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
+ IN UINT64 DestAddress,\r
+ IN UINT64 SrcAddress,\r
+ IN UINTN Count\r
+ )\r
+/*++\r
+\r
+Routine Description:\r
+\r
+ Copy one region of PCI root bridge memory space to be copied to\r
+ another region of PCI root bridge memory space.\r
+\r
+Arguments:\r
+\r
+ This - A pointer to EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL instance.\r
+ Width - Signifies the width of the memory operation.\r
+ DestAddress - Destination address of the memory operation.\r
+ SrcAddress - Source address of the memory operation.\r
+ Count - Number of memory operations to perform.\r
+\r
+Returns:\r
+\r
+ EFI_SUCCESS - The data was copied successfully.\r
+ EFI_INVALID_PARAMETER - Invalid parameters found.\r
+ EFI_OUT_OF_RESOURCES - The request could not be completed due to a lack of\r
+ resources.\r
+--*/\r
+;\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+RootBridgeIoPciRead (\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
+ IN UINT64 Address,\r
+ IN UINTN Count,\r
+ IN OUT VOID *Buffer\r
+ )\r
+/*++\r
+\r
+Routine Description:\r
+\r
+ Allows read from PCI configuration space.\r
+\r
+Arguments:\r
+\r
+ This - A pointer to EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL\r
+ Width - Signifies the width of the memory operation.\r
+ Address - The address within the PCI configuration space\r
+ for the PCI controller.\r
+ Count - The number of PCI configuration operations\r
+ to perform.\r
+ Buffer - The destination buffer to store the results.\r
+\r
+Returns:\r
+\r
+ EFI_SUCCESS - The data was read from the PCI root bridge.\r
+ EFI_INVALID_PARAMETER - Invalid parameters found.\r
+ EFI_OUT_OF_RESOURCES - The request could not be completed due to a lack of\r
+ resources.\r
+--*/\r
+;\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+RootBridgeIoPciWrite (\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
+ IN UINT64 Address,\r
+ IN UINTN Count,\r
+ IN OUT VOID *Buffer\r
+ )\r
+/*++\r
+\r
+Routine Description:\r
+\r
+ Allows write to PCI configuration space.\r
+\r
+Arguments:\r
+\r
+ This - A pointer to EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL\r
+ Width - Signifies the width of the memory operation.\r
+ Address - The address within the PCI configuration space\r
+ for the PCI controller.\r
+ Count - The number of PCI configuration operations\r
+ to perform.\r
+ Buffer - The source buffer to get the results.\r
+\r
+Returns:\r
+\r
+ EFI_SUCCESS - The data was written to the PCI root bridge.\r
+ EFI_INVALID_PARAMETER - Invalid parameters found.\r
+ EFI_OUT_OF_RESOURCES - The request could not be completed due to a lack of\r
+ resources.\r
+--*/\r
+;\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+RootBridgeIoMap (\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION Operation,\r
+ IN VOID *HostAddress,\r
+ IN OUT UINTN *NumberOfBytes,\r
+ OUT EFI_PHYSICAL_ADDRESS *DeviceAddress,\r
+ OUT VOID **Mapping\r
+ )\r
+/*++\r
+\r
+Routine Description:\r
+\r
+ Provides the PCI controller-specific address needed to access\r
+ system memory for DMA.\r
+\r
+Arguments:\r
+\r
+ This - A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
+ Operation - Indicate if the bus master is going to read or write\r
+ to system memory.\r
+ HostAddress - The system memory address to map on the PCI controller.\r
+ NumberOfBytes - On input the number of bytes to map.\r
+ On output the number of bytes that were mapped.\r
+ DeviceAddress - The resulting map address for the bus master PCI\r
+ controller to use to access the system memory's HostAddress.\r
+ Mapping - The value to pass to Unmap() when the bus master DMA\r
+ operation is complete.\r
+\r
+Returns:\r
+\r
+ EFI_SUCCESS - Success.\r
+ EFI_INVALID_PARAMETER - Invalid parameters found.\r
+ EFI_UNSUPPORTED - The HostAddress cannot be mapped as a common\r
+ buffer.\r
+ EFI_DEVICE_ERROR - The System hardware could not map the requested\r
+ address.\r
+ EFI_OUT_OF_RESOURCES - The request could not be completed due to\r
+ lack of resources.\r
+\r
+--*/\r
+;\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+RootBridgeIoUnmap (\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
+ IN VOID *Mapping\r
+ )\r
+/*++\r
+\r
+Routine Description:\r
+\r
+ Completes the Map() operation and releases any corresponding resources.\r
+\r
+Arguments:\r
+\r
+ This - Pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL instance.\r
+ Mapping - The value returned from Map() operation.\r
+\r
+Returns:\r
+\r
+ EFI_SUCCESS - The range was unmapped successfully.\r
+ EFI_INVALID_PARAMETER - Mapping is not a value that was returned\r
+ by Map operation.\r
+ EFI_DEVICE_ERROR - The data was not committed to the target\r
+ system memory.\r
+\r
+--*/\r
+;\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+RootBridgeIoAllocateBuffer (\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
+ IN EFI_ALLOCATE_TYPE Type,\r
+ IN EFI_MEMORY_TYPE MemoryType,\r
+ IN UINTN Pages,\r
+ OUT VOID **HostAddress,\r
+ IN UINT64 Attributes\r
+ )\r
+/*++\r
+\r
+Routine Description:\r
+\r
+ Allocates pages that are suitable for a common buffer mapping.\r
+\r
+Arguments:\r
+\r
+ This - Pointer to EFI_ROOT_BRIDGE_IO_PROTOCOL instance.\r
+ Type - Not used and can be ignored.\r
+ MemoryType - Type of memory to allocate.\r
+ Pages - Number of pages to allocate.\r
+ HostAddress - Pointer to store the base system memory address\r
+ of the allocated range.\r
+ Attributes - Requested bit mask of attributes of the allocated\r
+ range.\r
+\r
+Returns:\r
+\r
+ EFI_SUCCESS - The requested memory range were allocated.\r
+ EFI_INVALID_PARAMETER - Invalid parameter found.\r
+ EFI_UNSUPPORTED - Attributes is unsupported.\r
+\r
+--*/\r
+;\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+RootBridgeIoFreeBuffer (\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
+ IN UINTN Pages,\r
+ OUT VOID *HostAddress\r
+ )\r
+/*++\r
+\r
+Routine Description:\r
+\r
+ Free memory allocated in AllocateBuffer.\r
+\r
+Arguments:\r
+\r
+ This - Pointer to EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL\r
+ instance.\r
+ Pages - Number of pages to free.\r
+ HostAddress - The base system memory address of the\r
+ allocated range.\r
+\r
+Returns:\r
+\r
+ EFI_SUCCESS - Requested memory pages were freed.\r
+ EFI_INVALID_PARAMETER - Invalid parameter found.\r
+\r
+--*/\r
+;\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+RootBridgeIoFlush (\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This\r
+ )\r
+/*++\r
+\r
+Routine Description:\r
+\r
+ Flushes all PCI posted write transactions from a PCI host\r
+ bridge to system memory.\r
+\r
+Arguments:\r
+\r
+ This - Pointer to EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL instance.\r
+\r
+Returns:\r
+\r
+ EFI_SUCCESS - PCI posted write transactions were flushed\r
+ from PCI host bridge to system memory.\r
+ EFI_DEVICE_ERROR - Fail due to hardware error.\r
+\r
+--*/\r
+;\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+RootBridgeIoGetAttributes (\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
+ OUT UINT64 *Supported,\r
+ OUT UINT64 *Attributes\r
+ )\r
+/*++\r
+\r
+Routine Description:\r
+\r
+ Get the attributes that a PCI root bridge supports and\r
+ the attributes the PCI root bridge is currently using.\r
+\r
+Arguments:\r
+\r
+ This - Pointer to EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL\r
+ instance.\r
+ Supports - A pointer to the mask of attributes that\r
+ this PCI root bridge supports.\r
+ Attributes - A pointer to the mask of attributes that\r
+ this PCI root bridge is currently using.\r
+Returns:\r
+\r
+ EFI_SUCCESS - Success.\r
+ EFI_INVALID_PARAMETER - Invalid parameter found.\r
+\r
+--*/\r
+\r
+// GC_TODO: Supported - add argument and description to function comment\r
+//\r
+// GC_TODO: Supported - add argument and description to function comment\r
+//\r
+// GC_TODO: Supported - add argument and description to function comment\r
+//\r
+;\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+RootBridgeIoSetAttributes (\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
+ IN UINT64 Attributes,\r
+ IN OUT UINT64 *ResourceBase,\r
+ IN OUT UINT64 *ResourceLength\r
+ )\r
+/*++\r
+\r
+Routine Description:\r
+\r
+ Sets the attributes for a resource range on a PCI root bridge.\r
+\r
+Arguments:\r
+\r
+ This - Pointer to EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL instance.\r
+ Attributes - The mask of attributes to set.\r
+ ResourceBase - Pointer to the base address of the resource range\r
+ to be modified by the attributes specified by Attributes.\r
+ ResourceLength - Pointer to the length of the resource range to be modified.\r
+\r
+Returns:\r
+ EFI_SUCCESS - Success.\r
+ EFI_INVALID_PARAMETER - Invalid parameter found.\r
+ EFI_OUT_OF_RESOURCES - Not enough resources to set the attributes upon.\r
+\r
+--*/\r
+;\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+RootBridgeIoConfiguration (\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
+ OUT VOID **Resources\r
+ )\r
+/*++\r
+\r
+Routine Description:\r
+\r
+ Retrieves the current resource settings of this PCI root bridge\r
+ in the form of a set of ACPI 2.0 resource descriptor.\r
+\r
+Arguments:\r
+\r
+ This - Pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL instance.\r
+ Resources - Pointer to the ACPI 2.0 resource descriptor that\r
+ describe the current configuration of this PCI root\r
+ bridge.\r
+\r
+Returns:\r
+\r
+ EFI_SUCCESS - Success.\r
+ EFI_UNSUPPORTED - Current configuration of the PCI root bridge\r
+ could not be retrieved.\r
+\r
+--*/\r
+;\r
+\r
+#endif\r
--- /dev/null
+/** @file\r
+IIO PCI Root Bridge Io Protocol code. Generic enough to work for all IIOs.\r
+Does not support configuration accesses to the extended PCI Express registers yet.\r
+\r
+Copyright (c) 2013-2015 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+**/\r
+\r
+#include "PciRootBridge.h"\r
+\r
+//\r
+// Define PCI express offse\r
+//\r
+#define PCIE_OFF(Bus, Device, Function, Register) \\r
+ ((UINT64) ((UINTN) (Bus << 20) + (UINTN) (Device << 15) + (UINTN) (Function << 12) + (UINTN) (Register)))\r
+\r
+//\r
+// Pci Root Bridge Io Module Variables\r
+//\r
+EFI_METRONOME_ARCH_PROTOCOL *mMetronome;\r
+EFI_CPU_IO2_PROTOCOL *mCpuIo;\r
+\r
+EFI_STATUS\r
+SimpleIioRootBridgeConstructor (\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *Protocol,\r
+ IN EFI_HANDLE HostBridgeHandle,\r
+ IN PCI_ROOT_BRIDGE_RESOURCE_APERTURE *ResAperture,\r
+ UINT64 AllocAttributes\r
+ )\r
+/*++\r
+\r
+Routine Description:\r
+\r
+ Construct the Pci Root Bridge Io protocol.\r
+\r
+Arguments:\r
+\r
+ Protocol - Protocol to initialize.\r
+ HostBridgeHandle - Handle to the HostBridge.\r
+ ResAperture - Resource apperture of the root bridge.\r
+ AllocAttributes - Attribute of resouce allocated.\r
+\r
+Returns:\r
+\r
+ EFI_SUCCESS - Success.\r
+ Others - Fail.\r
+\r
+--*/\r
+{\r
+ EFI_STATUS Status;\r
+ PCI_ROOT_BRIDGE_INSTANCE *PrivateData;\r
+ PCI_RESOURCE_TYPE Index;\r
+ UINT32 HecBase;\r
+ UINT32 HecSize;\r
+\r
+ PrivateData = DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS (Protocol);\r
+\r
+ //\r
+ // Initialize the apertures with default values\r
+ //\r
+ CopyMem (\r
+ &PrivateData->Aperture,\r
+ ResAperture,\r
+ sizeof (PCI_ROOT_BRIDGE_RESOURCE_APERTURE)\r
+ );\r
+\r
+ for (Index = TypeIo; Index < TypeMax; Index++) {\r
+ PrivateData->ResAllocNode[Index].Type = Index;\r
+ PrivateData->ResAllocNode[Index].Base = 0;\r
+ PrivateData->ResAllocNode[Index].Length = 0;\r
+ PrivateData->ResAllocNode[Index].Status = ResNone;\r
+ }\r
+\r
+ EfiInitializeLock (&PrivateData->PciLock, TPL_HIGH_LEVEL);\r
+ PrivateData->PciAddress = 0xCF8;\r
+ PrivateData->PciData = 0xCFC;\r
+\r
+ PrivateData->RootBridgeAllocAttrib = AllocAttributes;\r
+ PrivateData->Attributes = 0;\r
+ PrivateData->Supports = EFI_PCI_ATTRIBUTE_IDE_PRIMARY_IO |\r
+ EFI_PCI_ATTRIBUTE_IDE_SECONDARY_IO |\r
+ EFI_PCI_ATTRIBUTE_ISA_IO_16 |\r
+ EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16 |\r
+ EFI_PCI_ATTRIBUTE_VGA_MEMORY |\r
+ EFI_PCI_ATTRIBUTE_VGA_IO_16;\r
+\r
+ //\r
+ // Don't support BASE above 4GB currently\r
+ // Position to bit 39:28\r
+ //\r
+ HecBase = (UINT32) PcdGet64 (PcdPciExpressBaseAddress);\r
+ HecSize = (UINT32) PcdGet64 (PcdPciExpressSize);\r
+\r
+ ASSERT ((HecBase & (HecSize - 1)) == 0);\r
+ ASSERT (HecBase != 0);\r
+\r
+ PrivateData->HecBase = HecBase;\r
+ PrivateData->HecLen = HecSize;\r
+\r
+ PrivateData->BusNumberAssigned = FALSE;\r
+ PrivateData->BusScanCount = 0;\r
+\r
+ Protocol->ParentHandle = HostBridgeHandle;\r
+\r
+ Protocol->PollMem = RootBridgeIoPollMem;\r
+ Protocol->PollIo = RootBridgeIoPollIo;\r
+\r
+ Protocol->Mem.Read = RootBridgeIoMemRead;\r
+ Protocol->Mem.Write = RootBridgeIoMemWrite;\r
+\r
+ Protocol->Io.Read = RootBridgeIoIoRead;\r
+ Protocol->Io.Write = RootBridgeIoIoWrite;\r
+\r
+ Protocol->CopyMem = RootBridgeIoCopyMem;\r
+\r
+ Protocol->Pci.Read = RootBridgeIoPciRead;\r
+ Protocol->Pci.Write = RootBridgeIoPciWrite;\r
+\r
+ Protocol->Map = RootBridgeIoMap;\r
+ Protocol->Unmap = RootBridgeIoUnmap;\r
+\r
+ Protocol->AllocateBuffer = RootBridgeIoAllocateBuffer;\r
+ Protocol->FreeBuffer = RootBridgeIoFreeBuffer;\r
+\r
+ Protocol->Flush = RootBridgeIoFlush;\r
+\r
+ Protocol->GetAttributes = RootBridgeIoGetAttributes;\r
+ Protocol->SetAttributes = RootBridgeIoSetAttributes;\r
+\r
+ Protocol->Configuration = RootBridgeIoConfiguration;\r
+\r
+ Protocol->SegmentNumber = 0;\r
+\r
+ Status = gBS->LocateProtocol (&gEfiMetronomeArchProtocolGuid, NULL, (VOID **) &mMetronome);\r
+ ASSERT_EFI_ERROR (Status);\r
+\r
+ Status = gBS->LocateProtocol (\r
+ &gEfiCpuIo2ProtocolGuid,\r
+ NULL,\r
+ (VOID **) &mCpuIo\r
+ );\r
+ ASSERT_EFI_ERROR (Status);\r
+\r
+ return EFI_SUCCESS;\r
+}\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+RootBridgeIoPollMem (\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
+ IN UINT64 Address,\r
+ IN UINT64 Mask,\r
+ IN UINT64 Value,\r
+ IN UINT64 Delay,\r
+ OUT UINT64 *Result\r
+ )\r
+/*++\r
+\r
+Routine Description:\r
+\r
+ Poll an address in memory mapped space until an exit condition is met\r
+ or a timeout occurs.\r
+\r
+Arguments:\r
+\r
+ This - Pointer to EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL instance.\r
+ Width - Width of the memory operation.\r
+ Address - The base address of the memory operation.\r
+ Mask - Mask used for polling criteria.\r
+ Value - Comparison value used for polling exit criteria.\r
+ Delay - Number of 100ns units to poll.\r
+ Result - Pointer to the last value read from memory location.\r
+\r
+Returns:\r
+\r
+ EFI_SUCCESS - Success.\r
+ EFI_INVALID_PARAMETER - Invalid parameter found.\r
+ EFI_TIMEOUT - Delay expired before a match occurred.\r
+ EFI_OUT_OF_RESOURCES - Fail due to lack of resources.\r
+\r
+--*/\r
+{\r
+ EFI_STATUS Status;\r
+ UINT64 NumberOfTicks;\r
+ UINT32 Remainder;\r
+\r
+ if (Result == NULL) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+\r
+ if (Width < 0 || Width > EfiPciWidthUint64) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+ //\r
+ // No matter what, always do a single poll.\r
+ //\r
+ Status = This->Mem.Read (\r
+ This,\r
+ Width,\r
+ Address,\r
+ 1,\r
+ Result\r
+ );\r
+ if (EFI_ERROR (Status)) {\r
+ return Status;\r
+ }\r
+\r
+ if ((*Result & Mask) == Value) {\r
+ return EFI_SUCCESS;\r
+ }\r
+\r
+ if (Delay != 0) {\r
+ //\r
+ // Determine the proper # of metronome ticks to wait for polling the\r
+ // location. The nuber of ticks is Roundup (Delay / mMetronome->TickPeriod)+1\r
+ // The "+1" to account for the possibility of the first tick being short\r
+ // because we started in the middle of a tick.\r
+ //\r
+ // BugBug: overriding mMetronome->TickPeriod with UINT32 until Metronome\r
+ // protocol definition is updated.\r
+ //\r
+ NumberOfTicks = DivU64x32Remainder (\r
+ Delay,\r
+ (UINT32) mMetronome->TickPeriod,\r
+ &Remainder\r
+ );\r
+ if (Remainder != 0) {\r
+ NumberOfTicks += 1;\r
+ }\r
+\r
+ NumberOfTicks += 1;\r
+\r
+ while (NumberOfTicks) {\r
+\r
+ mMetronome->WaitForTick (mMetronome, 1);\r
+\r
+ Status = This->Mem.Read (\r
+ This,\r
+ Width,\r
+ Address,\r
+ 1,\r
+ Result\r
+ );\r
+ if (EFI_ERROR (Status)) {\r
+ return Status;\r
+ }\r
+\r
+ if ((*Result & Mask) == Value) {\r
+ return EFI_SUCCESS;\r
+ }\r
+\r
+ NumberOfTicks -= 1;\r
+ }\r
+ }\r
+\r
+ return EFI_TIMEOUT;\r
+}\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+RootBridgeIoPollIo (\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
+ IN UINT64 Address,\r
+ IN UINT64 Mask,\r
+ IN UINT64 Value,\r
+ IN UINT64 Delay,\r
+ OUT UINT64 *Result\r
+ )\r
+/*++\r
+\r
+Routine Description:\r
+\r
+ Poll an address in I/O space until an exit condition is met\r
+ or a timeout occurs.\r
+\r
+Arguments:\r
+\r
+ This - Pointer to EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL instance.\r
+ Width - Width of I/O operation.\r
+ Address - The base address of the I/O operation.\r
+ Mask - Mask used for polling criteria.\r
+ Value - Comparison value used for polling exit criteria.\r
+ Delay - Number of 100ns units to poll.\r
+ Result - Pointer to the last value read from memory location.\r
+\r
+Returns:\r
+\r
+ EFI_SUCCESS - Success.\r
+ EFI_INVALID_PARAMETER - Invalid parameter found.\r
+ EFI_TIMEOUT - Delay expired before a match occurred.\r
+ EFI_OUT_OF_RESOURCES - Fail due to lack of resources.\r
+\r
+--*/\r
+{\r
+ EFI_STATUS Status;\r
+ UINT64 NumberOfTicks;\r
+ UINT32 Remainder;\r
+\r
+ //\r
+ // No matter what, always do a single poll.\r
+ //\r
+ if (Result == NULL) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+\r
+ if (Width < 0 || Width > EfiPciWidthUint64) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+\r
+ Status = This->Io.Read (\r
+ This,\r
+ Width,\r
+ Address,\r
+ 1,\r
+ Result\r
+ );\r
+ if (EFI_ERROR (Status)) {\r
+ return Status;\r
+ }\r
+\r
+ if ((*Result & Mask) == Value) {\r
+ return EFI_SUCCESS;\r
+ }\r
+\r
+ if (Delay != 0) {\r
+ //\r
+ // Determine the proper # of metronome ticks to wait for polling the\r
+ // location. The number of ticks is Roundup (Delay / mMetronome->TickPeriod)+1\r
+ // The "+1" to account for the possibility of the first tick being short\r
+ // because we started in the middle of a tick.\r
+ //\r
+ NumberOfTicks = DivU64x32Remainder (\r
+ Delay,\r
+ (UINT32) mMetronome->TickPeriod,\r
+ &Remainder\r
+ );\r
+ if (Remainder != 0) {\r
+ NumberOfTicks += 1;\r
+ }\r
+\r
+ NumberOfTicks += 1;\r
+\r
+ while (NumberOfTicks) {\r
+\r
+ mMetronome->WaitForTick (mMetronome, 1);\r
+\r
+ Status = This->Io.Read (\r
+ This,\r
+ Width,\r
+ Address,\r
+ 1,\r
+ Result\r
+ );\r
+ if (EFI_ERROR (Status)) {\r
+ return Status;\r
+ }\r
+\r
+ if ((*Result & Mask) == Value) {\r
+ return EFI_SUCCESS;\r
+ }\r
+\r
+ NumberOfTicks -= 1;\r
+ }\r
+ }\r
+\r
+ return EFI_TIMEOUT;\r
+}\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+RootBridgeIoMemRead (\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
+ IN UINT64 Address,\r
+ IN UINTN Count,\r
+ IN OUT VOID *Buffer\r
+ )\r
+/*++\r
+\r
+Routine Description:\r
+\r
+ Allow read from memory mapped I/O space.\r
+\r
+Arguments:\r
+\r
+ This - Pointer to EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL instance.\r
+ Width - The width of memory operation.\r
+ Address - Base address of the memory operation.\r
+ Count - Number of memory opeartion to perform.\r
+ Buffer - The destination buffer to store data.\r
+\r
+Returns:\r
+\r
+ EFI_SUCCESS - Success.\r
+ EFI_INVALID_PARAMETER - Invalid parameter found.\r
+ EFI_OUT_OF_RESOURCES - Fail due to lack of resources.\r
+\r
+--*/\r
+{\r
+ PCI_ROOT_BRIDGE_INSTANCE *PrivateData;\r
+ if (Buffer == NULL) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+\r
+ if (Width < 0 ||\r
+ Width == EfiPciWidthUint64 ||\r
+ Width == EfiPciWidthFifoUint64 ||\r
+ Width == EfiPciWidthFillUint64 ||\r
+ Width >= EfiPciWidthMaximum\r
+ ) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+\r
+ PrivateData = DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS (This);\r
+ //\r
+ // Check memory access limit\r
+ //\r
+ if (PrivateData->Aperture.Mem64Limit > PrivateData->Aperture.Mem64Base) {\r
+ if (Address > PrivateData->Aperture.Mem64Limit) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+ } else {\r
+ if (Address > PrivateData->Aperture.Mem32Limit) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+ }\r
+\r
+ return mCpuIo->Mem.Read (\r
+ mCpuIo,\r
+ (EFI_CPU_IO_PROTOCOL_WIDTH) Width,\r
+ Address,\r
+ Count,\r
+ Buffer\r
+ );\r
+}\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+RootBridgeIoMemWrite (\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
+ IN UINT64 Address,\r
+ IN UINTN Count,\r
+ IN OUT VOID *Buffer\r
+ )\r
+/*++\r
+\r
+Routine Description:\r
+\r
+ Allow write to memory mapped I/O space.\r
+\r
+Arguments:\r
+\r
+ This - Pointer to EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL instance.\r
+ Width - The width of memory operation.\r
+ Address - Base address of the memory operation.\r
+ Count - Number of memory opeartion to perform.\r
+ Buffer - The source buffer to write data from.\r
+\r
+Returns:\r
+\r
+ EFI_SUCCESS - Success.\r
+ EFI_INVALID_PARAMETER - Invalid parameter found.\r
+ EFI_OUT_OF_RESOURCES - Fail due to lack of resources.\r
+\r
+--*/\r
+{\r
+ PCI_ROOT_BRIDGE_INSTANCE *PrivateData;\r
+\r
+ if (Buffer == NULL) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+\r
+ if (Width < 0 ||\r
+ Width == EfiPciWidthUint64 ||\r
+ Width == EfiPciWidthFifoUint64 ||\r
+ Width == EfiPciWidthFillUint64 ||\r
+ Width >= EfiPciWidthMaximum\r
+ ) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+\r
+ PrivateData = DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS (This);\r
+\r
+ //\r
+ // Check memory access limit\r
+ //\r
+ if (PrivateData->Aperture.Mem64Limit > PrivateData->Aperture.Mem64Base) {\r
+ if (Address > PrivateData->Aperture.Mem64Limit) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+ } else {\r
+ if (Address > PrivateData->Aperture.Mem32Limit) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+ }\r
+\r
+ return mCpuIo->Mem.Write (\r
+ mCpuIo,\r
+ (EFI_CPU_IO_PROTOCOL_WIDTH) Width,\r
+ Address,\r
+ Count,\r
+ Buffer\r
+ );\r
+}\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+RootBridgeIoIoRead (\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
+ IN UINT64 Address,\r
+ IN UINTN Count,\r
+ IN OUT VOID *Buffer\r
+ )\r
+/*++\r
+\r
+Routine Description:\r
+\r
+ Enable a PCI driver to read PCI controller registers in the\r
+ PCI root bridge I/O space.\r
+\r
+Arguments:\r
+\r
+ This - A pointer to EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL\r
+ Width - Signifies the width of the memory operation.\r
+ Address - The base address of the I/O operation.\r
+ Count - The number of I/O operations to perform.\r
+ Buffer - The destination buffer to store the results.\r
+\r
+Returns:\r
+\r
+ EFI_SUCCESS - The data was read from the PCI root bridge.\r
+ EFI_INVALID_PARAMETER - Invalid parameters found.\r
+ EFI_OUT_OF_RESOURCES - The request could not be completed due to a lack of\r
+ resources.\r
+--*/\r
+{\r
+\r
+ UINTN AlignMask;\r
+ PCI_ROOT_BRIDGE_INSTANCE *PrivateData;\r
+\r
+ if (Buffer == NULL) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+\r
+ if (Width < 0 ||\r
+ Width == EfiPciWidthUint64 ||\r
+ Width == EfiPciWidthFifoUint64 ||\r
+ Width == EfiPciWidthFillUint64 ||\r
+ Width >= EfiPciWidthMaximum\r
+ ) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+\r
+ PrivateData = DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS (This);\r
+\r
+ //\r
+ // AlignMask = (1 << Width) - 1;\r
+ //\r
+ AlignMask = (1 << (Width & 0x03)) - 1;\r
+\r
+ //\r
+ // check Io access limit\r
+ //\r
+ if (Address > PrivateData->Aperture.IoLimit) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+\r
+ if (Address & AlignMask) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+\r
+ return mCpuIo->Io.Read (\r
+ mCpuIo,\r
+ (EFI_CPU_IO_PROTOCOL_WIDTH) Width,\r
+ Address,\r
+ Count,\r
+ Buffer\r
+ );\r
+\r
+}\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+RootBridgeIoIoWrite (\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
+ IN UINT64 Address,\r
+ IN UINTN Count,\r
+ IN OUT VOID *Buffer\r
+ )\r
+/*++\r
+\r
+Routine Description:\r
+\r
+ Enable a PCI driver to write to PCI controller registers in the\r
+ PCI root bridge I/O space.\r
+\r
+Arguments:\r
+\r
+ This - A pointer to EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL\r
+ Width - Signifies the width of the memory operation.\r
+ Address - The base address of the I/O operation.\r
+ Count - The number of I/O operations to perform.\r
+ Buffer - The source buffer to write data from.\r
+\r
+Returns:\r
+\r
+ EFI_SUCCESS - The data was written to the PCI root bridge.\r
+ EFI_INVALID_PARAMETER - Invalid parameters found.\r
+ EFI_OUT_OF_RESOURCES - The request could not be completed due to a lack of\r
+ resources.\r
+--*/\r
+{\r
+ UINTN AlignMask;\r
+ PCI_ROOT_BRIDGE_INSTANCE *PrivateData;\r
+\r
+ if (Buffer == NULL) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+\r
+ if (Width < 0 ||\r
+ Width == EfiPciWidthUint64 ||\r
+ Width == EfiPciWidthFifoUint64 ||\r
+ Width == EfiPciWidthFillUint64 ||\r
+ Width >= EfiPciWidthMaximum\r
+ ) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+\r
+ PrivateData = DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS (This);\r
+\r
+ //\r
+ // AlignMask = (1 << Width) - 1;\r
+ //\r
+ AlignMask = (1 << (Width & 0x03)) - 1;\r
+\r
+ //\r
+ // Check Io access limit\r
+ //\r
+ if (Address > PrivateData->Aperture.IoLimit) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+\r
+ if (Address & AlignMask) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+\r
+ return mCpuIo->Io.Write (\r
+ mCpuIo,\r
+ (EFI_CPU_IO_PROTOCOL_WIDTH) Width,\r
+ Address,\r
+ Count,\r
+ Buffer\r
+ );\r
+\r
+}\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+RootBridgeIoCopyMem (\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
+ IN UINT64 DestAddress,\r
+ IN UINT64 SrcAddress,\r
+ IN UINTN Count\r
+ )\r
+/*++\r
+\r
+Routine Description:\r
+\r
+ Copy one region of PCI root bridge memory space to be copied to\r
+ another region of PCI root bridge memory space.\r
+\r
+Arguments:\r
+\r
+ This - A pointer to EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL instance.\r
+ Width - Signifies the width of the memory operation.\r
+ DestAddress - Destination address of the memory operation.\r
+ SrcAddress - Source address of the memory operation.\r
+ Count - Number of memory operations to perform.\r
+\r
+Returns:\r
+\r
+ EFI_SUCCESS - The data was copied successfully.\r
+ EFI_INVALID_PARAMETER - Invalid parameters found.\r
+ EFI_OUT_OF_RESOURCES - The request could not be completed due to a lack of\r
+ resources.\r
+--*/\r
+{\r
+ EFI_STATUS Status;\r
+ BOOLEAN Direction;\r
+ UINTN Stride;\r
+ UINTN Index;\r
+ UINT64 Result;\r
+\r
+ if (Width < 0 || Width > EfiPciWidthUint64) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+\r
+ if (DestAddress == SrcAddress) {\r
+ return EFI_SUCCESS;\r
+ }\r
+\r
+ Stride = (UINTN)1 << Width;\r
+\r
+ Direction = TRUE;\r
+ if ((DestAddress > SrcAddress) && (DestAddress < (SrcAddress + Count * Stride))) {\r
+ Direction = FALSE;\r
+ SrcAddress = SrcAddress + (Count - 1) * Stride;\r
+ DestAddress = DestAddress + (Count - 1) * Stride;\r
+ }\r
+\r
+ for (Index = 0; Index < Count; Index++) {\r
+ Status = RootBridgeIoMemRead (\r
+ This,\r
+ Width,\r
+ SrcAddress,\r
+ 1,\r
+ &Result\r
+ );\r
+ if (EFI_ERROR (Status)) {\r
+ return Status;\r
+ }\r
+\r
+ Status = RootBridgeIoMemWrite (\r
+ This,\r
+ Width,\r
+ DestAddress,\r
+ 1,\r
+ &Result\r
+ );\r
+ if (EFI_ERROR (Status)) {\r
+ return Status;\r
+ }\r
+\r
+ if (Direction) {\r
+ SrcAddress += Stride;\r
+ DestAddress += Stride;\r
+ } else {\r
+ SrcAddress -= Stride;\r
+ DestAddress -= Stride;\r
+ }\r
+ }\r
+\r
+ return EFI_SUCCESS;\r
+}\r
+\r
+EFI_STATUS\r
+RootBridgeIoPciRW (\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
+ IN BOOLEAN Write,\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
+ IN UINT64 UserAddress,\r
+ IN UINTN Count,\r
+ IN OUT VOID *UserBuffer\r
+ )\r
+/*++\r
+\r
+Routine Description:\r
+\r
+Arguments:\r
+\r
+Returns:\r
+\r
+--*/\r
+{\r
+ PCI_CONFIG_ACCESS_CF8 Pci;\r
+ PCI_CONFIG_ACCESS_CF8 PciAligned;\r
+ UINT32 Stride;\r
+ UINTN PciData;\r
+ UINTN PciDataStride;\r
+ PCI_ROOT_BRIDGE_INSTANCE *PrivateData;\r
+\r
+ if (Width >= EfiPciWidthMaximum) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+\r
+ PrivateData = DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS(This);\r
+\r
+ ASSERT (((EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS*)&UserAddress)->ExtendedRegister == 0x00);\r
+\r
+ Stride = 1 << Width;\r
+\r
+ Pci.Bits.Reg = ((EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS*) &UserAddress)->Register;\r
+ Pci.Bits.Func = ((EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS*) &UserAddress)->Function;\r
+ Pci.Bits.Dev = ((EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS*) &UserAddress)->Device;\r
+ Pci.Bits.Bus = ((EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS*) &UserAddress)->Bus;\r
+ Pci.Bits.Reserved = 0;\r
+ Pci.Bits.Enable = 1;\r
+\r
+ //\r
+ // PCI Configure access are all 32-bit aligned, but by accessing the\r
+ // CONFIG_DATA_REGISTER (0xcfc) with different widths more cycle types\r
+ // are possible on PCI.\r
+ //\r
+ // To read a byte of PCI configuration space you load 0xcf8 and\r
+ // read 0xcfc, 0xcfd, 0xcfe, 0xcff\r
+ //\r
+ PciDataStride = ((EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS*) &UserAddress)->Register & 0x03;\r
+\r
+ while (Count) {\r
+ PciAligned = Pci;\r
+ PciAligned.Bits.Reg &= 0xfc;\r
+ PciData = PrivateData->PciData + PciDataStride;\r
+ EfiAcquireLock(&PrivateData->PciLock);\r
+ This->Io.Write (This, EfiPciWidthUint32, \\r
+ PrivateData->PciAddress, 1, &PciAligned);\r
+ if (Write) {\r
+ This->Io.Write (This, Width, PciData, 1, UserBuffer);\r
+ } else {\r
+ This->Io.Read (This, Width, PciData, 1, UserBuffer);\r
+ }\r
+ EfiReleaseLock(&PrivateData->PciLock);\r
+ UserBuffer = ((UINT8 *)UserBuffer) + Stride;\r
+ PciDataStride = (PciDataStride + Stride) % 4;\r
+ Count -= 1;\r
+\r
+ //\r
+ // Only increment the PCI address if Width is not a FIFO.\r
+ //\r
+ if (Width >= EfiPciWidthUint8 && Width <= EfiPciWidthUint64) {\r
+ Pci.Bits.Reg += Stride;\r
+ }\r
+ }\r
+ return EFI_SUCCESS;\r
+}\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+RootBridgeIoPciRead (\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
+ IN UINT64 Address,\r
+ IN UINTN Count,\r
+ IN OUT VOID *Buffer\r
+ )\r
+/*++\r
+\r
+Routine Description:\r
+\r
+ Allows read from PCI configuration space.\r
+\r
+Arguments:\r
+\r
+ This - A pointer to EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL\r
+ Width - Signifies the width of the memory operation.\r
+ Address - The address within the PCI configuration space\r
+ for the PCI controller.\r
+ Count - The number of PCI configuration operations\r
+ to perform.\r
+ Buffer - The destination buffer to store the results.\r
+\r
+Returns:\r
+\r
+ EFI_SUCCESS - The data was read from the PCI root bridge.\r
+ EFI_INVALID_PARAMETER - Invalid parameters found.\r
+ EFI_OUT_OF_RESOURCES - The request could not be completed due to a lack of\r
+ resources.\r
+--*/\r
+{\r
+ PCI_ROOT_BRIDGE_INSTANCE *PrivateData;\r
+ UINT32 PciBus;\r
+ UINT32 PciDev;\r
+ UINT32 PciFn;\r
+ UINT32 PciExtReg;\r
+ UINT64 ExtConfigAdd;\r
+\r
+ if (Buffer == NULL) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+\r
+ if (Width < 0 ||\r
+ Width == EfiPciWidthUint64 ||\r
+ Width == EfiPciWidthFifoUint64 ||\r
+ Width == EfiPciWidthFillUint64 ||\r
+ Width >= EfiPciWidthMaximum\r
+ ) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+\r
+ //\r
+ // Read Pci configuration space\r
+ //\r
+ PrivateData = DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS (This);\r
+\r
+ if (PrivateData->HecBase == 0) {\r
+ return RootBridgeIoPciRW (This, FALSE, Width, Address, Count, Buffer);\r
+ }\r
+\r
+ if (!((EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS *) &Address)->ExtendedRegister) {\r
+ PciExtReg = ((EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS *) &Address)->Register;\r
+ } else {\r
+ PciExtReg = ((EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS *) &Address)->ExtendedRegister & 0x0FFF;\r
+ }\r
+\r
+ PciBus = ((EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS *) &Address)->Bus;\r
+ PciDev = ((EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS *) &Address)->Device;\r
+ PciFn = ((EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS *) &Address)->Function;\r
+\r
+ ExtConfigAdd = (UINT64) PrivateData->HecBase + PCIE_OFF (PciBus, PciDev, PciFn, PciExtReg);\r
+\r
+ return mCpuIo->Mem.Read (\r
+ mCpuIo,\r
+ (EFI_CPU_IO_PROTOCOL_WIDTH) Width,\r
+ ExtConfigAdd,\r
+ Count,\r
+ Buffer\r
+ );\r
+}\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+RootBridgeIoPciWrite (\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
+ IN UINT64 Address,\r
+ IN UINTN Count,\r
+ IN OUT VOID *Buffer\r
+ )\r
+/*++\r
+\r
+Routine Description:\r
+\r
+ Allows write to PCI configuration space.\r
+\r
+Arguments:\r
+\r
+ This - A pointer to EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL\r
+ Width - Signifies the width of the memory operation.\r
+ Address - The address within the PCI configuration space\r
+ for the PCI controller.\r
+ Count - The number of PCI configuration operations\r
+ to perform.\r
+ Buffer - The source buffer to get the results.\r
+\r
+Returns:\r
+\r
+ EFI_SUCCESS - The data was written to the PCI root bridge.\r
+ EFI_INVALID_PARAMETER - Invalid parameters found.\r
+ EFI_OUT_OF_RESOURCES - The request could not be completed due to a lack of\r
+ resources.\r
+--*/\r
+{\r
+ PCI_ROOT_BRIDGE_INSTANCE *PrivateData;\r
+ UINT32 PciBus;\r
+ UINT32 PciDev;\r
+ UINT32 PciFn;\r
+ UINT32 PciExtReg;\r
+ UINT64 ExtConfigAdd;\r
+\r
+ if (Buffer == NULL) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+\r
+ if (Width < 0 || Width >= EfiPciWidthMaximum) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+\r
+ //\r
+ // Write Pci configuration space\r
+ //\r
+ PrivateData = DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS (This);\r
+\r
+ if (PrivateData->HecBase == 0) {\r
+ return RootBridgeIoPciRW (This, TRUE, Width, Address, Count, Buffer);\r
+ }\r
+\r
+ if (!((EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS *) &Address)->ExtendedRegister) {\r
+ PciExtReg = ((EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS *) &Address)->Register;\r
+ } else {\r
+ PciExtReg = ((EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS *) &Address)->ExtendedRegister & 0x0FFF;\r
+ }\r
+\r
+ PciBus = ((EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS *) &Address)->Bus;\r
+ PciDev = ((EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS *) &Address)->Device;\r
+ PciFn = ((EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS *) &Address)->Function;\r
+\r
+ ExtConfigAdd = (UINT64) PrivateData->HecBase + PCIE_OFF (PciBus, PciDev, PciFn, PciExtReg);\r
+\r
+ return mCpuIo->Mem.Write (\r
+ mCpuIo,\r
+ (EFI_CPU_IO_PROTOCOL_WIDTH) Width,\r
+ ExtConfigAdd,\r
+ Count,\r
+ Buffer\r
+ );\r
+}\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+RootBridgeIoMap (\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION Operation,\r
+ IN VOID *HostAddress,\r
+ IN OUT UINTN *NumberOfBytes,\r
+ OUT EFI_PHYSICAL_ADDRESS *DeviceAddress,\r
+ OUT VOID **Mapping\r
+ )\r
+/*++\r
+\r
+Routine Description:\r
+\r
+ Provides the PCI controller-specific address needed to access\r
+ system memory for DMA.\r
+\r
+Arguments:\r
+\r
+ This - A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
+ Operation - Indicate if the bus master is going to read or write\r
+ to system memory.\r
+ HostAddress - The system memory address to map on the PCI controller.\r
+ NumberOfBytes - On input the number of bytes to map.\r
+ On output the number of bytes that were mapped.\r
+ DeviceAddress - The resulting map address for the bus master PCI\r
+ controller to use to access the system memory's HostAddress.\r
+ Mapping - The value to pass to Unmap() when the bus master DMA\r
+ operation is complete.\r
+\r
+Returns:\r
+\r
+ EFI_SUCCESS - Success.\r
+ EFI_INVALID_PARAMETER - Invalid parameters found.\r
+ EFI_UNSUPPORTED - The HostAddress cannot be mapped as a common\r
+ buffer.\r
+ EFI_DEVICE_ERROR - The System hardware could not map the requested\r
+ address.\r
+ EFI_OUT_OF_RESOURCES - The request could not be completed due to\r
+ lack of resources.\r
+\r
+--*/\r
+{\r
+ EFI_STATUS Status;\r
+ EFI_PHYSICAL_ADDRESS PhysicalAddress;\r
+ MAP_INFO *MapInfo;\r
+\r
+ if (NumberOfBytes == NULL || Mapping == NULL || DeviceAddress == NULL || HostAddress == NULL) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+ //\r
+ // Initialize the return values to their defaults\r
+ //\r
+ *Mapping = NULL;\r
+\r
+ //\r
+ // Make sure that Operation is valid\r
+ //\r
+ if ((Operation < 0) || (Operation > EfiPciOperationBusMasterCommonBuffer64)) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+ //\r
+ // Most PCAT like chipsets can not handle performing DMA above 4GB.\r
+ // If any part of the DMA transfer being mapped is above 4GB, then\r
+ // map the DMA transfer to a buffer below 4GB.\r
+ //\r
+ PhysicalAddress = (EFI_PHYSICAL_ADDRESS) (UINTN) HostAddress;\r
+ if ((PhysicalAddress +*NumberOfBytes) > 0x100000000ULL) {\r
+ //\r
+ // Common Buffer operations can not be remapped. If the common buffer\r
+ // if above 4GB, then it is not possible to generate a mapping, so return\r
+ // an error.\r
+ //\r
+ if (Operation == EfiPciOperationBusMasterCommonBuffer || Operation == EfiPciOperationBusMasterCommonBuffer64) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+ }\r
+\r
+ if ((PhysicalAddress + *NumberOfBytes) > (DMA_MEMORY_TOP+1)) {\r
+\r
+ //\r
+ // Common Buffer operations can not be remapped.\r
+ //\r
+ if (Operation == EfiPciOperationBusMasterCommonBuffer || Operation == EfiPciOperationBusMasterCommonBuffer64) {\r
+ *DeviceAddress = PhysicalAddress;\r
+ return EFI_SUCCESS;\r
+ }\r
+ //\r
+ // Allocate a MAP_INFO structure to remember the mapping when Unmap() is\r
+ // called later.\r
+ //\r
+ Status = gBS->AllocatePool (\r
+ EfiBootServicesData,\r
+ sizeof (MAP_INFO),\r
+ (VOID **) &MapInfo\r
+ );\r
+ if (EFI_ERROR (Status)) {\r
+ *NumberOfBytes = 0;\r
+ return Status;\r
+ }\r
+ //\r
+ // Return a pointer to the MAP_INFO structure in Mapping\r
+ //\r
+ *Mapping = MapInfo;\r
+\r
+ //\r
+ // Initialize the MAP_INFO structure\r
+ //\r
+ MapInfo->Operation = Operation;\r
+ MapInfo->NumberOfBytes = *NumberOfBytes;\r
+ MapInfo->NumberOfPages = EFI_SIZE_TO_PAGES (*NumberOfBytes);\r
+ MapInfo->HostAddress = PhysicalAddress;\r
+ MapInfo->MappedHostAddress = DMA_MEMORY_TOP;\r
+\r
+ //\r
+ // Allocate a buffer below DMA_MEMORY_TOP to map the transfer to.\r
+ //\r
+ Status = gBS->AllocatePages (\r
+ AllocateMaxAddress,\r
+ EfiBootServicesData,\r
+ MapInfo->NumberOfPages,\r
+ &MapInfo->MappedHostAddress\r
+ );\r
+ if (EFI_ERROR (Status)) {\r
+ gBS->FreePool (MapInfo);\r
+ *NumberOfBytes = 0;\r
+ return Status;\r
+ }\r
+ //\r
+ // If this is a read operation from the Bus Master's point of view,\r
+ // then copy the contents of the real buffer into the mapped buffer\r
+ // so the Bus Master can read the contents of the real buffer.\r
+ //\r
+ if (Operation == EfiPciOperationBusMasterRead || Operation == EfiPciOperationBusMasterRead64) {\r
+ CopyMem (\r
+ (VOID *) (UINTN) MapInfo->MappedHostAddress,\r
+ (VOID *) (UINTN) MapInfo->HostAddress,\r
+ MapInfo->NumberOfBytes\r
+ );\r
+ }\r
+ //\r
+ // The DeviceAddress is the address of the maped buffer below DMA_MEMORY_TOP\r
+ //\r
+ *DeviceAddress = MapInfo->MappedHostAddress;\r
+ } else {\r
+ //\r
+ // The transfer is below DMA_MEMORY_TOP, so the DeviceAddress is simply the HostAddress\r
+ //\r
+ *DeviceAddress = PhysicalAddress;\r
+ }\r
+\r
+ return EFI_SUCCESS;\r
+}\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+RootBridgeIoUnmap (\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
+ IN VOID *Mapping\r
+ )\r
+/*++\r
+\r
+Routine Description:\r
+\r
+ Completes the Map() operation and releases any corresponding resources.\r
+\r
+Arguments:\r
+\r
+ This - Pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL instance.\r
+ Mapping - The value returned from Map() operation.\r
+\r
+Returns:\r
+\r
+ EFI_SUCCESS - The range was unmapped successfully.\r
+ EFI_INVALID_PARAMETER - Mapping is not a value that was returned\r
+ by Map operation.\r
+ EFI_DEVICE_ERROR - The data was not committed to the target\r
+ system memory.\r
+\r
+--*/\r
+{\r
+ MAP_INFO *MapInfo;\r
+\r
+ //\r
+ // See if the Map() operation associated with this Unmap() required a mapping buffer.\r
+ // If a mapping buffer was not required, then this function simply returns EFI_SUCCESS.\r
+ //\r
+ if (Mapping != NULL) {\r
+ //\r
+ // Get the MAP_INFO structure from Mapping\r
+ //\r
+ MapInfo = (MAP_INFO *) Mapping;\r
+\r
+ //\r
+ // If this is a write operation from the Bus Master's point of view,\r
+ // then copy the contents of the mapped buffer into the real buffer\r
+ // so the processor can read the contents of the real buffer.\r
+ //\r
+ if ((MapInfo->Operation == EfiPciOperationBusMasterWrite) ||\r
+ (MapInfo->Operation == EfiPciOperationBusMasterWrite64)\r
+ ) {\r
+ CopyMem (\r
+ (VOID *) (UINTN) MapInfo->HostAddress,\r
+ (VOID *) (UINTN) MapInfo->MappedHostAddress,\r
+ MapInfo->NumberOfBytes\r
+ );\r
+ }\r
+ //\r
+ // Free the mapped buffer and the MAP_INFO structure.\r
+ //\r
+ gBS->FreePages (MapInfo->MappedHostAddress, MapInfo->NumberOfPages);\r
+ gBS->FreePool (Mapping);\r
+ }\r
+\r
+ return EFI_SUCCESS;\r
+}\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+RootBridgeIoAllocateBuffer (\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
+ IN EFI_ALLOCATE_TYPE Type,\r
+ IN EFI_MEMORY_TYPE MemoryType,\r
+ IN UINTN Pages,\r
+ OUT VOID **HostAddress,\r
+ IN UINT64 Attributes\r
+ )\r
+/*++\r
+\r
+Routine Description:\r
+\r
+ Allocates pages that are suitable for a common buffer mapping.\r
+\r
+Arguments:\r
+\r
+ This - Pointer to EFI_ROOT_BRIDGE_IO_PROTOCOL instance.\r
+ Type - Not used and can be ignored.\r
+ MemoryType - Type of memory to allocate.\r
+ Pages - Number of pages to allocate.\r
+ HostAddress - Pointer to store the base system memory address\r
+ of the allocated range.\r
+ Attributes - Requested bit mask of attributes of the allocated\r
+ range.\r
+\r
+Returns:\r
+\r
+ EFI_SUCCESS - The requested memory range were allocated.\r
+ EFI_INVALID_PARAMETER - Invalid parameter found.\r
+ EFI_UNSUPPORTED - Attributes is unsupported.\r
+\r
+--*/\r
+{\r
+ EFI_STATUS Status;\r
+ EFI_PHYSICAL_ADDRESS PhysicalAddress;\r
+\r
+ //\r
+ // Validate Attributes\r
+ //\r
+ if ((Attributes & EFI_PCI_ATTRIBUTE_INVALID_FOR_ALLOCATE_BUFFER) != 0) {\r
+ return EFI_UNSUPPORTED;\r
+ }\r
+ //\r
+ // Check for invalid inputs\r
+ //\r
+ if (HostAddress == NULL) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+ //\r
+ // The only valid memory types are EfiBootServicesData and EfiRuntimeServicesData\r
+ //\r
+ if ((MemoryType != EfiBootServicesData) && (MemoryType != EfiRuntimeServicesData)) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+ //\r
+ // Limit allocations to memory below DMA_MEMORY_TOP\r
+ //\r
+ PhysicalAddress = DMA_MEMORY_TOP;\r
+\r
+ Status = gBS->AllocatePages (\r
+ AllocateMaxAddress,\r
+ MemoryType,\r
+ Pages,\r
+ &PhysicalAddress\r
+ );\r
+ if (EFI_ERROR (Status)) {\r
+ return Status;\r
+ }\r
+\r
+ *HostAddress = (VOID *) (UINTN) PhysicalAddress;\r
+\r
+ return EFI_SUCCESS;\r
+}\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+RootBridgeIoFreeBuffer (\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
+ IN UINTN Pages,\r
+ OUT VOID *HostAddress\r
+ )\r
+/*++\r
+\r
+Routine Description:\r
+\r
+ Free memory allocated in AllocateBuffer.\r
+\r
+Arguments:\r
+\r
+ This - Pointer to EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL\r
+ instance.\r
+ Pages - Number of pages to free.\r
+ HostAddress - The base system memory address of the\r
+ allocated range.\r
+\r
+Returns:\r
+\r
+ EFI_SUCCESS - Requested memory pages were freed.\r
+ EFI_INVALID_PARAMETER - Invalid parameter found.\r
+\r
+--*/\r
+{\r
+ return gBS->FreePages ((EFI_PHYSICAL_ADDRESS) (UINTN) HostAddress, Pages);\r
+}\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+RootBridgeIoFlush (\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This\r
+ )\r
+/*++\r
+\r
+Routine Description:\r
+\r
+ Flushes all PCI posted write transactions from a PCI host\r
+ bridge to system memory.\r
+\r
+Arguments:\r
+\r
+ This - Pointer to EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL instance.\r
+\r
+Returns:\r
+\r
+ EFI_SUCCESS - PCI posted write transactions were flushed\r
+ from PCI host bridge to system memory.\r
+ EFI_DEVICE_ERROR - Fail due to hardware error.\r
+\r
+--*/\r
+{\r
+ //\r
+ // not supported yet\r
+ //\r
+ return EFI_SUCCESS;\r
+}\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+RootBridgeIoGetAttributes (\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
+ OUT UINT64 *Supported,\r
+ OUT UINT64 *Attributes\r
+ )\r
+/*++\r
+\r
+Routine Description:\r
+\r
+ Get the attributes that a PCI root bridge supports and\r
+ the attributes the PCI root bridge is currently using.\r
+\r
+Arguments:\r
+\r
+ This - Pointer to EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL\r
+ instance.\r
+ Supports - A pointer to the mask of attributes that\r
+ this PCI root bridge supports.\r
+ Attributes - A pointer to the mask of attributes that\r
+ this PCI root bridge is currently using.\r
+Returns:\r
+\r
+ EFI_SUCCESS - Success.\r
+ EFI_INVALID_PARAMETER - Invalid parameter found.\r
+\r
+--*/\r
+\r
+// GC_TODO: Supported - add argument and description to function comment\r
+//\r
+// GC_TODO: Supported - add argument and description to function comment\r
+//\r
+// GC_TODO: Supported - add argument and description to function comment\r
+//\r
+{\r
+ PCI_ROOT_BRIDGE_INSTANCE *PrivateData;\r
+\r
+ PrivateData = DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS (This);\r
+\r
+ if (Attributes == NULL && Supported == NULL) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+ //\r
+ // Set the return value for Supported and Attributes\r
+ //\r
+ if (Supported) {\r
+ *Supported = PrivateData->Supports;\r
+ }\r
+\r
+ if (Attributes) {\r
+ *Attributes = PrivateData->Attributes;\r
+ }\r
+\r
+ return EFI_SUCCESS;\r
+}\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+RootBridgeIoSetAttributes (\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
+ IN UINT64 Attributes,\r
+ IN OUT UINT64 *ResourceBase,\r
+ IN OUT UINT64 *ResourceLength\r
+ )\r
+/*++\r
+\r
+Routine Description:\r
+\r
+ Sets the attributes for a resource range on a PCI root bridge.\r
+\r
+Arguments:\r
+\r
+ This - Pointer to EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL instance.\r
+ Attributes - The mask of attributes to set.\r
+ ResourceBase - Pointer to the base address of the resource range\r
+ to be modified by the attributes specified by Attributes.\r
+ ResourceLength - Pointer to the length of the resource range to be modified.\r
+\r
+Returns:\r
+ EFI_SUCCESS - Success.\r
+ EFI_INVALID_PARAMETER - Invalid parameter found.\r
+ EFI_OUT_OF_RESOURCES - Not enough resources to set the attributes upon.\r
+\r
+--*/\r
+\r
+//\r
+// GC_TODO: EFI_UNSUPPORTED - add return value to function comment\r
+//\r
+{\r
+ PCI_ROOT_BRIDGE_INSTANCE *PrivateData;\r
+\r
+ PrivateData = DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS (This);\r
+\r
+ if (Attributes != 0) {\r
+ Attributes &= (PrivateData->Supports);\r
+ if (Attributes == 0) {\r
+ return EFI_UNSUPPORTED;\r
+ }\r
+ }\r
+\r
+ if (Attributes == PrivateData->Attributes) {\r
+ return EFI_SUCCESS;\r
+ }\r
+ //\r
+ // It is just a trick for some attribute can only be enabled or disabled\r
+ // otherwise it can impact on other devices\r
+ //\r
+ PrivateData->Attributes = Attributes;\r
+\r
+ return EFI_SUCCESS;\r
+}\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+RootBridgeIoConfiguration (\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
+ OUT VOID **Resources\r
+ )\r
+/*++\r
+\r
+Routine Description:\r
+\r
+ Retrieves the current resource settings of this PCI root bridge\r
+ in the form of a set of ACPI 2.0 resource descriptor.\r
+\r
+Arguments:\r
+\r
+ This - Pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL instance.\r
+ Resources - Pointer to the ACPI 2.0 resource descriptor that\r
+ describe the current configuration of this PCI root\r
+ bridge.\r
+\r
+Returns:\r
+\r
+ EFI_SUCCESS - Success.\r
+ EFI_UNSUPPORTED - Current configuration of the PCI root bridge\r
+ could not be retrieved.\r
+\r
+--*/\r
+\r
+//\r
+// GC_TODO: EFI_OUT_OF_RESOURCES - add return value to function comment\r
+//\r
+{\r
+ EFI_STATUS Status;\r
+ UINTN Idx;\r
+\r
+ PCI_ROOT_BRIDGE_INSTANCE *RbPrivateData;\r
+ PCI_RES_NODE *ResAllocNode;\r
+ EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Config;\r
+\r
+ //\r
+ // Get this instance of the Root Bridge.\r
+ //\r
+ RbPrivateData = DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS (This);\r
+\r
+ //\r
+ // If the pointer is not NULL, it points to a buffer already allocated.\r
+ //\r
+ if (RbPrivateData->ConfigBuffer == NULL) {\r
+ Status = gBS->AllocatePool (\r
+ EfiBootServicesData,\r
+ TypeMax * sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR),\r
+ &RbPrivateData->ConfigBuffer\r
+ );\r
+ if (EFI_ERROR (Status)) {\r
+ return EFI_OUT_OF_RESOURCES;\r
+ }\r
+ }\r
+\r
+ Config = RbPrivateData->ConfigBuffer;\r
+\r
+ ZeroMem (Config, TypeMax * sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR));\r
+\r
+ for (Idx = 0; Idx < TypeMax; Idx++) {\r
+\r
+ ResAllocNode = &RbPrivateData->ResAllocNode[Idx];\r
+\r
+ if (ResAllocNode->Status != ResAllocated) {\r
+ continue;\r
+ }\r
+\r
+ switch (ResAllocNode->Type) {\r
+\r
+ case TypeIo:\r
+ Config->Desc = ACPI_ADDRESS_SPACE_DESCRIPTOR;\r
+ Config->Len = sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) - 3;\r
+ Config->ResType = ACPI_ADDRESS_SPACE_TYPE_IO;\r
+ Config->AddrRangeMin = ResAllocNode->Base;\r
+ Config->AddrRangeMax = ResAllocNode->Base + ResAllocNode->Length - 1;\r
+ Config->AddrLen = ResAllocNode->Length;\r
+ break;\r
+\r
+ case TypeMem32:\r
+ Config->Desc = ACPI_ADDRESS_SPACE_DESCRIPTOR;\r
+ Config->Len = sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) - 3;\r
+ Config->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;\r
+ Config->AddrSpaceGranularity = 32;\r
+ Config->AddrRangeMin = ResAllocNode->Base;\r
+ Config->AddrRangeMax = ResAllocNode->Base + ResAllocNode->Length - 1;\r
+ Config->AddrLen = ResAllocNode->Length;\r
+ break;\r
+\r
+ case TypePMem32:\r
+ Config->Desc = ACPI_ADDRESS_SPACE_DESCRIPTOR;\r
+ Config->Len = sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) - 3;\r
+ Config->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;\r
+ Config->SpecificFlag = 6;\r
+ Config->AddrSpaceGranularity = 32;\r
+ Config->AddrRangeMin = ResAllocNode->Base;\r
+ Config->AddrRangeMax = ResAllocNode->Base + ResAllocNode->Length - 1;\r
+ Config->AddrLen = ResAllocNode->Length;\r
+ break;\r
+\r
+ case TypeMem64:\r
+ Config->Desc = ACPI_ADDRESS_SPACE_DESCRIPTOR;\r
+ Config->Len = sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) - 3;\r
+ Config->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;\r
+ Config->SpecificFlag = 6;\r
+ Config->AddrSpaceGranularity = 64;\r
+ Config->AddrRangeMin = ResAllocNode->Base;\r
+ Config->AddrRangeMax = ResAllocNode->Base + ResAllocNode->Length - 1;\r
+ Config->AddrLen = ResAllocNode->Length;\r
+ break;\r
+\r
+ case TypePMem64:\r
+ Config->Desc = ACPI_ADDRESS_SPACE_DESCRIPTOR;\r
+ Config->Len = sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) - 3;\r
+ Config->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;\r
+ Config->SpecificFlag = 6;\r
+ Config->AddrSpaceGranularity = 64;\r
+ Config->AddrRangeMin = ResAllocNode->Base;\r
+ Config->AddrRangeMax = ResAllocNode->Base + ResAllocNode->Length - 1;\r
+ Config->AddrLen = ResAllocNode->Length;\r
+ break;\r
+\r
+ case TypeBus:\r
+ Config->Desc = ACPI_ADDRESS_SPACE_DESCRIPTOR;\r
+ Config->Len = sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) - 3;\r
+ Config->ResType = ACPI_ADDRESS_SPACE_TYPE_BUS;\r
+ Config->AddrRangeMin = ResAllocNode->Base;\r
+ Config->AddrRangeMax = ResAllocNode->Base + ResAllocNode->Length - 1;\r
+ Config->AddrLen = ResAllocNode->Length;\r
+ break;\r
+\r
+ default:\r
+ break;\r
+ }\r
+\r
+ Config++;\r
+ }\r
+ //\r
+ // Terminate the entries.\r
+ //\r
+ ((EFI_ACPI_END_TAG_DESCRIPTOR *) Config)->Desc = ACPI_END_TAG_DESCRIPTOR;\r
+ ((EFI_ACPI_END_TAG_DESCRIPTOR *) Config)->Checksum = 0x0;\r
+\r
+ *Resources = RbPrivateData->ConfigBuffer;\r
+ return EFI_SUCCESS;\r
+}\r
--- /dev/null
+/** @file\r
+Common header file shared by all source files.\r
+\r
+This file includes package header files, library classes and protocol, PPI & GUID definitions.\r
+\r
+Copyright (c) 2013-2015 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+**/\r
+\r
+#ifndef __COMMON_HEADER_H_\r
+#define __COMMON_HEADER_H_\r
+\r
+\r
+\r
+#include <PiDxe.h>\r
+#include <IntelQNCDxe.h>\r
+\r
+#include <Protocol/PciPlatform.h>\r
+#include <Protocol/PciIo.h>\r
+\r
+#include <Library/DxeServicesLib.h>\r
+#include <Library/UefiDriverEntryPoint.h>\r
+#include <Library/UefiBootServicesTableLib.h>\r
+#include <Library/UefiRuntimeServicesTableLib.h>\r
+#include <Library/DebugLib.h>\r
+#include <Library/IoLib.h>\r
+#include <Library/PciLib.h>\r
+#include <Library/IohLib.h>\r
+\r
+#endif\r
--- /dev/null
+/** @file\r
+Registers onboard PCI ROMs with PCI.IO\r
+\r
+Copyright (c) 2013-2015 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+**/\r
+\r
+#include "CommonHeader.h"\r
+\r
+#include "PciPlatform.h"\r
+\r
+\r
+PCI_OPTION_ROM_TABLE mPciOptionRomTable[] = {\r
+ { NULL_ROM_FILE_GUID, 0, 0, 0, 0, 0xffff, 0xffff }\r
+};\r
+EFI_PCI_PLATFORM_PROTOCOL mPciPlatform = {\r
+ PhaseNotify,\r
+ PlatformPrepController,\r
+ GetPlatformPolicy,\r
+ GetPciRom\r
+};\r
+\r
+EFI_HANDLE mPciPlatformHandle = NULL;\r
+EFI_HANDLE mImageHandle = NULL;\r
+\r
+\r
+EFI_STATUS\r
+PhaseNotify (\r
+ IN EFI_PCI_PLATFORM_PROTOCOL *This,\r
+ IN EFI_HANDLE HostBridge,\r
+ IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PHASE Phase,\r
+ IN EFI_PCI_CHIPSET_EXECUTION_PHASE ChipsetPhase\r
+ )\r
+{\r
+ UINT8 UsbHostBusNumber = IOH_BUS;\r
+ if (Phase == EfiPciHostBridgeEndResourceAllocation) {\r
+ // Required for QuarkSouthCluster.\r
+ // Enable USB controller memory, io and bus master before Ehci driver.\r
+ EnableUsbMemIoBusMaster (UsbHostBusNumber);\r
+ return EFI_SUCCESS;\r
+ }\r
+ return EFI_UNSUPPORTED;\r
+}\r
+\r
+\r
+EFI_STATUS\r
+PlatformPrepController (\r
+ IN EFI_PCI_PLATFORM_PROTOCOL *This,\r
+ IN EFI_HANDLE HostBridge,\r
+ IN EFI_HANDLE RootBridge,\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS PciAddress,\r
+ IN EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE Phase,\r
+ IN EFI_PCI_CHIPSET_EXECUTION_PHASE ChipsetPhase\r
+ )\r
+{\r
+ return EFI_UNSUPPORTED;\r
+}\r
+\r
+EFI_STATUS\r
+GetPlatformPolicy (\r
+ IN CONST EFI_PCI_PLATFORM_PROTOCOL *This,\r
+ OUT EFI_PCI_PLATFORM_POLICY *PciPolicy\r
+ )\r
+{\r
+ if (PciPolicy == NULL) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+\r
+ return EFI_UNSUPPORTED;\r
+}\r
+\r
+EFI_STATUS\r
+GetPciRom (\r
+ IN CONST EFI_PCI_PLATFORM_PROTOCOL *This,\r
+ IN EFI_HANDLE PciHandle,\r
+ OUT VOID **RomImage,\r
+ OUT UINTN *RomSize\r
+ )\r
+/*++\r
+\r
+ Routine Description:\r
+ Return a PCI ROM image for the onboard device represented by PciHandle\r
+\r
+ Arguments:\r
+ This - Protocol instance pointer.\r
+ PciHandle - PCI device to return the ROM image for.\r
+ RomImage - PCI Rom Image for onboard device\r
+ RomSize - Size of RomImage in bytes\r
+\r
+ Returns:\r
+ EFI_SUCCESS - RomImage is valid\r
+ EFI_NOT_FOUND - No RomImage\r
+\r
+--*/\r
+{\r
+ EFI_STATUS Status;\r
+ EFI_PCI_IO_PROTOCOL *PciIo;\r
+ UINTN Segment;\r
+ UINTN Bus;\r
+ UINTN Device;\r
+ UINTN Function;\r
+ UINT16 VendorId;\r
+ UINT16 DeviceId;\r
+ UINT16 DeviceClass;\r
+ UINTN TableIndex;\r
+\r
+ Status = gBS->HandleProtocol (\r
+ PciHandle,\r
+ &gEfiPciIoProtocolGuid,\r
+ (VOID **) &PciIo\r
+ );\r
+ if (EFI_ERROR (Status)) {\r
+ return EFI_NOT_FOUND;\r
+ }\r
+\r
+ PciIo->GetLocation (PciIo, &Segment, &Bus, &Device, &Function);\r
+\r
+ PciIo->Pci.Read (PciIo, EfiPciIoWidthUint16, 0x0A, 1, &DeviceClass);\r
+\r
+ PciIo->Pci.Read (PciIo, EfiPciIoWidthUint16, 0, 1, &VendorId);\r
+\r
+ PciIo->Pci.Read (PciIo, EfiPciIoWidthUint16, 2, 1, &DeviceId);\r
+\r
+ //\r
+ // Loop through table of video option rom descriptions\r
+ //\r
+ for (TableIndex = 0; mPciOptionRomTable[TableIndex].VendorId != 0xffff; TableIndex++) {\r
+\r
+ //\r
+ // See if the PCI device specified by PciHandle matches at device in mPciOptionRomTable\r
+ //\r
+ if (VendorId != mPciOptionRomTable[TableIndex].VendorId ||\r
+ DeviceId != mPciOptionRomTable[TableIndex].DeviceId ||\r
+ Segment != mPciOptionRomTable[TableIndex].Segment ||\r
+ Bus != mPciOptionRomTable[TableIndex].Bus ||\r
+ Device != mPciOptionRomTable[TableIndex].Device ||\r
+ Function != mPciOptionRomTable[TableIndex].Function) {\r
+ continue;\r
+ }\r
+\r
+ Status = GetSectionFromFv (\r
+ &mPciOptionRomTable[TableIndex].FileName,\r
+ EFI_SECTION_RAW,\r
+ 0,\r
+ RomImage,\r
+ RomSize\r
+ );\r
+\r
+ if (EFI_ERROR (Status)) {\r
+ continue;\r
+ }\r
+\r
+ return EFI_SUCCESS;\r
+ }\r
+\r
+ return EFI_NOT_FOUND;\r
+}\r
+\r
+EFI_STATUS\r
+PciPlatformDriverEntry (\r
+ IN EFI_HANDLE ImageHandle,\r
+ IN EFI_SYSTEM_TABLE *SystemTable\r
+ )\r
+/*++\r
+\r
+Routine Description:\r
+\r
+Arguments:\r
+ (Standard EFI Image entry - EFI_IMAGE_ENTRY_POINT)\r
+\r
+Returns:\r
+ EFI_STATUS\r
+\r
+--*/\r
+{\r
+ EFI_STATUS Status;\r
+\r
+ mImageHandle = ImageHandle;\r
+\r
+ //\r
+ // Install on a new handle\r
+ //\r
+ Status = gBS->InstallProtocolInterface (\r
+ &mPciPlatformHandle,\r
+ &gEfiPciPlatformProtocolGuid,\r
+ EFI_NATIVE_INTERFACE,\r
+ &mPciPlatform\r
+ );\r
+\r
+ return Status;\r
+}\r
--- /dev/null
+/** @file\r
+This code supports a the private implementation\r
+of the Legacy BIOS Platform protocol\r
+\r
+Copyright (c) 2013-2015 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+**/\r
+\r
+#ifndef PCI_PLATFORM_H_\r
+#define PCI_PLATFORM_H_\r
+\r
+#include <IndustryStandard/Pci.h>\r
+#include <Library/PcdLib.h>\r
+//\r
+// Global variables for Option ROMs\r
+//\r
+#define NULL_ROM_FILE_GUID \\r
+{ 0x00000000, 0x0000, 0x0000, {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }}\r
+\r
+#define ONBOARD_VIDEO_OPTION_ROM_FILE_GUID \\r
+{ 0x8dfae5d4, 0xb50e, 0x4c10, {0x96, 0xe6, 0xf2, 0xc2, 0x66, 0xca, 0xcb, 0xb6 }}\r
+\r
+#define IDE_RAID_OPTION_ROM_FILE_GUID \\r
+{ 0x3392A8E1, 0x1881, 0x4398, {0x83, 0xa6, 0x53, 0xd3, 0x87, 0xdb, 0x20, 0x20 }}\r
+\r
+#define TANX_UNDI_OPTION_ROM_FILE_GUID \\r
+{ 0x84c24ab0, 0x124e, 0x4aed, {0x8e, 0xfe, 0xf9, 0x1b, 0xb9, 0x73, 0x69, 0xf4 }}\r
+\r
+#define PXE_UNDI_OPTION_ROM_FILE_GUID \\r
+{ 0xea34cd48, 0x5fdf, 0x46f0, {0xb5, 0xfa, 0xeb, 0xe0, 0x76, 0xa4, 0xf1, 0x2c }}\r
+\r
+\r
+typedef struct {\r
+ EFI_GUID FileName;\r
+ UINTN Segment;\r
+ UINTN Bus;\r
+ UINTN Device;\r
+ UINTN Function;\r
+ UINT16 VendorId;\r
+ UINT16 DeviceId;\r
+} PCI_OPTION_ROM_TABLE;\r
+\r
+\r
+EFI_STATUS\r
+PhaseNotify (\r
+ IN EFI_PCI_PLATFORM_PROTOCOL *This,\r
+ IN EFI_HANDLE HostBridge,\r
+ IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PHASE Phase,\r
+ IN EFI_PCI_CHIPSET_EXECUTION_PHASE ChipsetPhase\r
+ );\r
+\r
+\r
+EFI_STATUS\r
+PlatformPrepController (\r
+ IN EFI_PCI_PLATFORM_PROTOCOL *This,\r
+ IN EFI_HANDLE HostBridge,\r
+ IN EFI_HANDLE RootBridge,\r
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS PciAddress,\r
+ IN EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE Phase,\r
+ IN EFI_PCI_CHIPSET_EXECUTION_PHASE ChipsetPhase\r
+ );\r
+\r
+EFI_STATUS\r
+GetPlatformPolicy (\r
+ IN CONST EFI_PCI_PLATFORM_PROTOCOL *This,\r
+ OUT EFI_PCI_PLATFORM_POLICY *PciPolicy\r
+ );\r
+\r
+EFI_STATUS\r
+GetPciRom (\r
+ IN CONST EFI_PCI_PLATFORM_PROTOCOL *This,\r
+ IN EFI_HANDLE PciHandle,\r
+ OUT VOID **RomImage,\r
+ OUT UINTN *RomSize\r
+ );\r
+\r
+#endif\r
+\r
+\r
--- /dev/null
+## @file\r
+# Component description file for PciPlatform module.\r
+#\r
+# This driver installs pciplatform protocol to provide access interfaces to the onboard pci roms.\r
+# Copyright (c) 2013-2015 Intel Corporation.\r
+#\r
+# This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution. The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php\r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+##\r
+\r
+[Defines]\r
+ INF_VERSION = 0x00010005\r
+ BASE_NAME = PciPlatform\r
+ FILE_GUID = 2E8CD01A-BDB7-40b4-8376-E7C26EAC21FF\r
+ MODULE_TYPE = DXE_DRIVER\r
+ VERSION_STRING = 1.0\r
+ ENTRY_POINT = PciPlatformDriverEntry\r
+\r
+#\r
+# The following information is for reference only and not required by the build tools.\r
+#\r
+# VALID_ARCHITECTURES = IA32 X64 IPF EBC\r
+#\r
+\r
+[Sources]\r
+ PciPlatform.c\r
+ PciPlatform.h\r
+ CommonHeader.h\r
+\r
+[Packages]\r
+ MdePkg/MdePkg.dec\r
+ QuarkPlatformPkg/QuarkPlatformPkg.dec\r
+ QuarkSocPkg/QuarkSocPkg.dec\r
+\r
+[LibraryClasses]\r
+ PciLib\r
+ PcdLib\r
+ IohLib\r
+ DebugLib\r
+ UefiRuntimeServicesTableLib\r
+ UefiBootServicesTableLib\r
+ UefiDriverEntryPoint\r
+ DxeServicesLib\r
+\r
+[Guids]\r
+\r
+[Protocols]\r
+ gEfiPciIoProtocolGuid # PROTOCOL ALWAYS_CONSUMED\r
+ gEfiPciPlatformProtocolGuid # PROTOCOL ALWAYS_PRODUCED\r
+\r
+[Pcd]\r
+\r
+[Depex]\r
+ TRUE\r
--- /dev/null
+/** @file\r
+This is the driver that locates the MemoryConfigurationData Variable, if it\r
+exists, and reports the data to the DataHub.\r
+\r
+Copyright (c) 2013-2015 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#include "MemorySubClass.h"\r
+\r
+extern UINT8 MemorySubClassStrings[];\r
+\r
+EFI_GUID gEfiMemorySubClassDriverGuid = EFI_MEMORY_SUBCLASS_DRIVER_GUID;\r
+\r
+EFI_STATUS\r
+MemorySubClassEntryPoint (\r
+ IN EFI_HANDLE ImageHandle,\r
+ IN EFI_SYSTEM_TABLE *SystemTable\r
+ )\r
+/*++\r
+\r
+ Routine Description:\r
+ This is the standard EFI driver point that detects whether there is a\r
+ MemoryConfigurationData Variable and, if so, reports memory configuration info\r
+ to the DataHub.\r
+\r
+ Arguments:\r
+ ImageHandle - Handle for the image of this driver\r
+ SystemTable - Pointer to the EFI System Table\r
+\r
+ Returns:\r
+ EFI_SUCCESS if the data is successfully reported\r
+ EFI_NOT_FOUND if the HOB list could not be located.\r
+\r
+--*/\r
+{\r
+// UINT8 Index;\r
+ UINTN DataSize;\r
+ UINT8 Dimm;\r
+ UINTN StringBufferSize;\r
+ UINT8 NumSlots;\r
+ UINTN DevLocStrLen;\r
+ UINTN BankLocStrLen;\r
+ UINTN ManuStrLen;\r
+ UINTN SerialNumStrLen;\r
+ UINTN AssertTagStrLen;\r
+ UINTN PartNumStrLen;\r
+ UINTN MemoryDeviceSize;\r
+ CHAR8* OptionalStrStart;\r
+ UINT16 ArrayInstance;\r
+ UINT64 DimmMemorySize;\r
+ UINT64 TotalMemorySize;\r
+ UINT32 Data;\r
+ UINT32 MemoryCapacity;\r
+ BOOLEAN MemoryDeviceSizeUnitMega;\r
+ EFI_STATUS Status;\r
+ EFI_STRING StringBuffer;\r
+ EFI_STRING DevLocStr;\r
+ EFI_STRING BankLocStr;\r
+ EFI_STRING ManuStr;\r
+ EFI_STRING SerialNumStr;\r
+ EFI_STRING AssertTagStr;\r
+ EFI_STRING PartNumStr;\r
+ EFI_HII_HANDLE HiiHandle;\r
+ EFI_SMBIOS_HANDLE MemArraySmbiosHandle;\r
+ EFI_SMBIOS_HANDLE MemArrayMappedAddrSmbiosHandle;\r
+ EFI_SMBIOS_HANDLE MemDevSmbiosHandle;\r
+ EFI_SMBIOS_HANDLE MemDevMappedAddrSmbiosHandle;\r
+ EFI_SMBIOS_HANDLE MemModuleInfoSmbiosHandle;\r
+ SMBIOS_TABLE_TYPE6 *Type6Record;\r
+ SMBIOS_TABLE_TYPE16 *Type16Record;\r
+ SMBIOS_TABLE_TYPE17 *Type17Record;\r
+ SMBIOS_TABLE_TYPE19 *Type19Record;\r
+ SMBIOS_TABLE_TYPE20 *Type20Record;\r
+ EFI_SMBIOS_PROTOCOL *Smbios;\r
+ EFI_MEMORY_ARRAY_LINK_DATA ArrayLink;\r
+ EFI_MEMORY_ARRAY_LOCATION_DATA ArrayLocationData;\r
+ EFI_MEMORY_DEVICE_START_ADDRESS_DATA DeviceStartAddress;\r
+\r
+\r
+ DataSize = 0;\r
+ Dimm = 0;\r
+\r
+\r
+ //\r
+ // Allocate Buffers\r
+ //\r
+ StringBufferSize = (sizeof (CHAR16)) * 100;\r
+ StringBuffer = AllocateZeroPool (StringBufferSize);\r
+ ASSERT (StringBuffer != NULL);\r
+\r
+ //\r
+ // Locate dependent protocols\r
+ //\r
+ Status = gBS->LocateProtocol (&gEfiSmbiosProtocolGuid, NULL, (VOID**)&Smbios);\r
+ ASSERT_EFI_ERROR (Status);\r
+\r
+\r
+ //\r
+ // Add our default strings to the HII database. They will be modified later.\r
+ //\r
+ HiiHandle = HiiAddPackages (\r
+ &gEfiMemorySubClassDriverGuid,\r
+ NULL,\r
+ MemorySubClassStrings,\r
+ NULL\r
+ );\r
+ ASSERT (HiiHandle != NULL);\r
+\r
+ //\r
+ // Create physical array and associated data for all mainboard memory\r
+ // This will translate into a Type 16 SMBIOS Record\r
+ //\r
+ ArrayInstance = 1;\r
+\r
+ McD0PciCfg32 (QNC_ACCESS_PORT_MCR) = MESSAGE_READ_DW (0x3, 0x8);\r
+ TotalMemorySize = McD0PciCfg32 (QNC_ACCESS_PORT_MDR);\r
+\r
+ ArrayLocationData.MemoryArrayLocation = EfiMemoryArrayLocationSystemBoard;\r
+ ArrayLocationData.MemoryArrayUse = EfiMemoryArrayUseSystemMemory;\r
+\r
+ ArrayLocationData.MemoryErrorCorrection = EfiMemoryErrorCorrectionNone;\r
+\r
+ Data = 0x40000000;//(UINT32) RShiftU64(MemConfigData->RowInfo.MaxMemory, 10);\r
+\r
+ ArrayLocationData.MaximumMemoryCapacity.Exponent = (UINT16) LowBitSet32 (Data);\r
+ ArrayLocationData.MaximumMemoryCapacity.Value = (UINT16) (Data >> ArrayLocationData.MaximumMemoryCapacity.Exponent);\r
+\r
+ NumSlots = 2;// (UINT8)(MemConfigData->RowInfo.MaxRows >> 1);\r
+ ArrayLocationData.NumberMemoryDevices = (UINT16)(NumSlots);\r
+\r
+ //\r
+ // Report top level physical array to Type 16 SMBIOS Record\r
+ //\r
+ Type16Record = AllocatePool(sizeof(SMBIOS_TABLE_TYPE16) + 1 + 1);\r
+ ZeroMem(Type16Record, sizeof(SMBIOS_TABLE_TYPE16) + 1 + 1);\r
+\r
+ Type16Record->Hdr.Type = EFI_SMBIOS_TYPE_PHYSICAL_MEMORY_ARRAY;\r
+ Type16Record->Hdr.Length = sizeof(SMBIOS_TABLE_TYPE16);\r
+ Type16Record->Hdr.Handle = 0;\r
+\r
+ Type16Record->Location = (UINT8)ArrayLocationData.MemoryArrayLocation;\r
+\r
+ Type16Record->Use = (UINT8)ArrayLocationData.MemoryArrayUse;\r
+\r
+ Type16Record->MemoryErrorCorrection = (UINT8)ArrayLocationData.MemoryErrorCorrection;\r
+\r
+ MemoryCapacity = (UINT32) ArrayLocationData.MaximumMemoryCapacity.Value * (1 << ((UINT32) ArrayLocationData.MaximumMemoryCapacity.Exponent - 10));\r
+ Type16Record->MaximumCapacity = MemoryCapacity;\r
+\r
+ Type16Record->MemoryErrorInformationHandle = 0xfffe;\r
+\r
+ Type16Record->NumberOfMemoryDevices = ArrayLocationData.NumberMemoryDevices;\r
+ //\r
+ // Don't change it. This handle will be referenced by type 17 records\r
+ //\r
+ MemArraySmbiosHandle = SMBIOS_HANDLE_PI_RESERVED;\r
+ Status = Smbios->Add (Smbios, NULL, &MemArraySmbiosHandle, (EFI_SMBIOS_TABLE_HEADER*) Type16Record);\r
+ FreePool(Type16Record);\r
+ ASSERT_EFI_ERROR (Status);\r
+\r
+ // Do associated data for each DIMM\r
+ //RowConfArray = &MemConfigData->RowConfArray;\r
+\r
+ //\r
+ // Get total memory size for the construction of smbios record type 19\r
+ //\r
+ //TotalMemorySize = 0;// MSG_BUS_READ(0x0208);\r
+\r
+ //\r
+ // Generate Memory Array Mapped Address info\r
+ //\r
+ Type19Record = AllocatePool(sizeof (SMBIOS_TABLE_TYPE19));\r
+ ZeroMem(Type19Record, sizeof(SMBIOS_TABLE_TYPE19));\r
+ Type19Record->Hdr.Type = EFI_SMBIOS_TYPE_MEMORY_ARRAY_MAPPED_ADDRESS;\r
+ Type19Record->Hdr.Length = sizeof(SMBIOS_TABLE_TYPE19);\r
+ Type19Record->Hdr.Handle = 0;\r
+ Type19Record->StartingAddress = 0;\r
+ Type19Record->EndingAddress = (UINT32)RShiftU64(TotalMemorySize, 10) - 1;\r
+ Type19Record->MemoryArrayHandle = MemArraySmbiosHandle;\r
+ Type19Record->PartitionWidth = (UINT8)(NumSlots);\r
+\r
+ //\r
+ // Generate Memory Array Mapped Address info (TYPE 19)\r
+ //\r
+ MemArrayMappedAddrSmbiosHandle = SMBIOS_HANDLE_PI_RESERVED;\r
+ Status = Smbios->Add (Smbios, NULL, &MemArrayMappedAddrSmbiosHandle, (EFI_SMBIOS_TABLE_HEADER*) Type19Record);\r
+ FreePool(Type19Record);\r
+ ASSERT_EFI_ERROR (Status);\r
+\r
+\r
+ // Use SPD data to generate Device Type info\r
+ ZeroMem (&ArrayLink, sizeof (EFI_MEMORY_ARRAY_LINK_DATA));\r
+ ArrayLink.MemoryDeviceLocator = STRING_TOKEN(STR_MEMORY_SUBCLASS_DEVICE_LOCATOR_0);\r
+ ArrayLink.MemoryBankLocator = STRING_TOKEN(STR_MEMORY_SUBCLASS_DEVICE_LOCATOR_0);\r
+ ArrayLink.MemoryAssetTag = STRING_TOKEN(STR_MEMORY_SUBCLASS_UNKNOWN);\r
+ ArrayLink.MemoryArrayLink.ProducerName = gEfiMemorySubClassDriverGuid;\r
+ ArrayLink.MemoryArrayLink.Instance = ArrayInstance;\r
+ ArrayLink.MemoryArrayLink.SubInstance = EFI_SUBCLASS_INSTANCE_NON_APPLICABLE;\r
+ ArrayLink.MemorySubArrayLink.ProducerName = gEfiMemorySubClassDriverGuid;\r
+ ArrayLink.MemorySubArrayLink.SubInstance = EFI_SUBCLASS_INSTANCE_NON_APPLICABLE;\r
+ ArrayLink.MemoryFormFactor = EfiMemoryFormFactorChip;\r
+ ArrayLink.MemoryType = EfiMemoryTypeDdr2;\r
+\r
+\r
+ StrCpy (StringBuffer, L"NO DIMM,MEMROY DOWN");\r
+ ArrayLink.MemoryManufacturer = HiiSetString (\r
+ HiiHandle,\r
+ 0,\r
+ StringBuffer,\r
+ NULL\r
+ );\r
+ ArrayLink.MemorySerialNumber = HiiSetString (\r
+ HiiHandle,\r
+ 0,\r
+ StringBuffer,\r
+ NULL\r
+ );\r
+\r
+ ArrayLink.MemoryPartNumber = HiiSetString (\r
+ HiiHandle,\r
+ 0,\r
+ StringBuffer,\r
+ NULL\r
+ );\r
+\r
+ //\r
+ // Hardcode value. Need to revise for different configuration.\r
+ //\r
+ ArrayLink.MemoryTotalWidth = 64;\r
+ ArrayLink.MemoryDataWidth = 64;\r
+\r
+ DimmMemorySize = TotalMemorySize;// MSG_BUS_READ(0x0208);\r
+\r
+ ArrayLink.MemoryDeviceSize.Exponent = (UINT16) LowBitSet64 (DimmMemorySize);\r
+ ArrayLink.MemoryDeviceSize.Value = (UINT16) RShiftU64(DimmMemorySize, ArrayLink.MemoryDeviceSize.Exponent);\r
+ ArrayLink.MemoryTypeDetail.Synchronous = 1;\r
+ Data = 800;\r
+ ArrayLink.MemorySpeed = *((EFI_EXP_BASE10_DATA *) &Data);\r
+\r
+\r
+\r
+ DevLocStr = HiiGetPackageString(&gEfiMemorySubClassDriverGuid, ArrayLink.MemoryDeviceLocator, NULL);\r
+ DevLocStrLen = StrLen(DevLocStr);\r
+ ASSERT(DevLocStrLen <= SMBIOS_STRING_MAX_LENGTH);\r
+\r
+ BankLocStr = HiiGetPackageString(&gEfiMemorySubClassDriverGuid, ArrayLink.MemoryBankLocator, NULL);\r
+ BankLocStrLen = StrLen(BankLocStr);\r
+ ASSERT(BankLocStrLen <= SMBIOS_STRING_MAX_LENGTH);\r
+\r
+ ManuStr = HiiGetPackageString(&gEfiMemorySubClassDriverGuid, ArrayLink.MemoryManufacturer, NULL);\r
+ ManuStrLen = StrLen(ManuStr);\r
+ ASSERT(ManuStrLen <= SMBIOS_STRING_MAX_LENGTH);\r
+\r
+ SerialNumStr = HiiGetPackageString(&gEfiMemorySubClassDriverGuid, ArrayLink.MemorySerialNumber, NULL);\r
+ SerialNumStrLen = StrLen(SerialNumStr);\r
+ ASSERT(SerialNumStrLen <= SMBIOS_STRING_MAX_LENGTH);\r
+\r
+ AssertTagStr = HiiGetPackageString(&gEfiMemorySubClassDriverGuid, ArrayLink.MemoryAssetTag, NULL);\r
+ AssertTagStrLen = StrLen(AssertTagStr);\r
+ ASSERT(AssertTagStrLen <= SMBIOS_STRING_MAX_LENGTH);\r
+\r
+ PartNumStr = HiiGetPackageString(&gEfiMemorySubClassDriverGuid, ArrayLink.MemoryPartNumber, NULL);\r
+ PartNumStrLen = StrLen(PartNumStr);\r
+ ASSERT(PartNumStrLen <= SMBIOS_STRING_MAX_LENGTH);\r
+\r
+ //\r
+ // Report DIMM level memory module information to smbios (Type 6)\r
+ //\r
+ DataSize = sizeof(SMBIOS_TABLE_TYPE6) + DevLocStrLen + 1 + 1;\r
+ Type6Record = AllocatePool(DataSize);\r
+ ZeroMem(Type6Record, DataSize);\r
+ Type6Record->Hdr.Type = EFI_SMBIOS_TYPE_MEMORY_MODULE_INFORMATON;\r
+ Type6Record->Hdr.Length = sizeof (SMBIOS_TABLE_TYPE6);\r
+ Type6Record->Hdr.Handle = 0;\r
+ Type6Record->SocketDesignation = 1;\r
+ if (ArrayLink.MemorySpeed.Value == 0) {\r
+ Type6Record->CurrentSpeed = 0;\r
+ } else {\r
+ //\r
+ // Memory speed is in ns unit\r
+ //\r
+ Type6Record->CurrentSpeed = (UINT8)(1000 / (ArrayLink.MemorySpeed.Value));\r
+ }\r
+ //\r
+ // Device Size\r
+ //\r
+ MemoryDeviceSize = (UINTN)(ArrayLink.MemoryDeviceSize.Value) * (UINTN)(1 << ArrayLink.MemoryDeviceSize.Exponent);\r
+ if (MemoryDeviceSize == 0) {\r
+ *(UINT8*)&(Type6Record->InstalledSize) = 0x7F;\r
+ *(UINT8*)&(Type6Record->EnabledSize) = 0x7F;\r
+ } else {\r
+ MemoryDeviceSize = (UINTN) RShiftU64 ((UINT64) MemoryDeviceSize, 21);\r
+ while (MemoryDeviceSize != 0) {\r
+ (*(UINT8*)&(Type6Record->InstalledSize))++;\r
+ (*(UINT8*)&(Type6Record->EnabledSize))++;\r
+ MemoryDeviceSize = (UINTN) RShiftU64 ((UINT64) MemoryDeviceSize,1);\r
+ }\r
+ }\r
+\r
+ if (ArrayLink.MemoryFormFactor == EfiMemoryFormFactorDimm ||\r
+ ArrayLink.MemoryFormFactor == EfiMemoryFormFactorFbDimm) {\r
+ *(UINT16*)&Type6Record->CurrentMemoryType |= 1<<8;\r
+ }\r
+ if (ArrayLink.MemoryFormFactor == EfiMemoryFormFactorSimm) {\r
+ *(UINT16*)&Type6Record->CurrentMemoryType |= 1<<7;\r
+ }\r
+ if (ArrayLink.MemoryType == EfiMemoryTypeSdram) {\r
+ *(UINT16*)&Type6Record->CurrentMemoryType |= 1<<10;\r
+ }\r
+ if (ArrayLink.MemoryTypeDetail.Edo == 1) {\r
+ *(UINT16*)&Type6Record->CurrentMemoryType |= 1<<4;\r
+ }\r
+ if (ArrayLink.MemoryTypeDetail.FastPaged == 1) {\r
+ *(UINT16*)&Type6Record->CurrentMemoryType |= 1<<3;\r
+ }\r
+ OptionalStrStart = (CHAR8 *)(Type6Record + 1);\r
+ UnicodeStrToAsciiStr(DevLocStr, OptionalStrStart);\r
+ MemModuleInfoSmbiosHandle = SMBIOS_HANDLE_PI_RESERVED;\r
+ Status = Smbios->Add (Smbios, NULL, &MemModuleInfoSmbiosHandle, (EFI_SMBIOS_TABLE_HEADER*) Type6Record);\r
+ FreePool(Type6Record);\r
+ ASSERT_EFI_ERROR (Status);\r
+ //\r
+ // Report DIMM level Device Type to smbios (Type 17)\r
+ //\r
+ DataSize = sizeof (SMBIOS_TABLE_TYPE17) + DevLocStrLen + 1 + BankLocStrLen + 1 + ManuStrLen + 1 + SerialNumStrLen + 1 + AssertTagStrLen + 1 + PartNumStrLen + 1 + 1;\r
+ Type17Record = AllocatePool(DataSize);\r
+ ZeroMem(Type17Record, DataSize);\r
+ Type17Record->Hdr.Type = EFI_SMBIOS_TYPE_MEMORY_DEVICE;\r
+ Type17Record->Hdr.Length = sizeof (SMBIOS_TABLE_TYPE17);\r
+ Type17Record->Hdr.Handle = 0;\r
+\r
+ Type17Record->MemoryArrayHandle = MemArraySmbiosHandle;\r
+ Type17Record->MemoryErrorInformationHandle = 0xfffe;\r
+ Type17Record->TotalWidth = ArrayLink.MemoryTotalWidth;\r
+ Type17Record->DataWidth = ArrayLink.MemoryDataWidth;\r
+ //\r
+ // Device Size\r
+ //\r
+ MemoryDeviceSize = ((UINTN) ArrayLink.MemoryDeviceSize.Value) << (ArrayLink.MemoryDeviceSize.Exponent - 10);\r
+ MemoryDeviceSizeUnitMega = FALSE;\r
+ //\r
+ // kilo as unit\r
+ //\r
+ if (MemoryDeviceSize > 0xffff) {\r
+ MemoryDeviceSize = MemoryDeviceSize >> 10;\r
+ //\r
+ // Mega as unit\r
+ //\r
+ MemoryDeviceSizeUnitMega = TRUE;\r
+ }\r
+\r
+ MemoryDeviceSize = MemoryDeviceSize & 0x7fff;\r
+ if (MemoryDeviceSize != 0 && MemoryDeviceSizeUnitMega == FALSE) {\r
+ MemoryDeviceSize |= 0x8000;\r
+ }\r
+ Type17Record->Size = (UINT16)MemoryDeviceSize;\r
+\r
+ Type17Record->FormFactor = (UINT8)ArrayLink.MemoryFormFactor;\r
+ Type17Record->DeviceLocator = 1;\r
+ Type17Record->BankLocator = 2;\r
+ Type17Record->MemoryType = (UINT8)ArrayLink.MemoryType;\r
+ CopyMem (\r
+ (UINT8 *) &Type17Record->TypeDetail,\r
+ &ArrayLink.MemoryTypeDetail,\r
+ 2\r
+ );\r
+\r
+ Type17Record->Speed = ArrayLink.MemorySpeed.Value;\r
+ Type17Record->Manufacturer = 3;\r
+ Type17Record->SerialNumber = 4;\r
+ Type17Record->AssetTag = 5;\r
+ Type17Record->PartNumber = 6;\r
+ //\r
+ // temporary solution for save device label information.\r
+ //\r
+ Type17Record->Attributes = (UINT8)(Dimm + 1);\r
+\r
+ OptionalStrStart = (CHAR8 *)(Type17Record + 1);\r
+ UnicodeStrToAsciiStr(DevLocStr, OptionalStrStart);\r
+ UnicodeStrToAsciiStr(BankLocStr, OptionalStrStart + DevLocStrLen + 1);\r
+ UnicodeStrToAsciiStr(ManuStr, OptionalStrStart + DevLocStrLen + 1 + BankLocStrLen + 1);\r
+ UnicodeStrToAsciiStr(SerialNumStr, OptionalStrStart + DevLocStrLen + 1 + BankLocStrLen + 1 + ManuStrLen + 1);\r
+ UnicodeStrToAsciiStr(AssertTagStr, OptionalStrStart + DevLocStrLen + 1 + BankLocStrLen + 1 + ManuStrLen + 1 + SerialNumStrLen + 1);\r
+ UnicodeStrToAsciiStr(PartNumStr, OptionalStrStart + DevLocStrLen + 1 + BankLocStrLen + 1 + ManuStrLen + 1 + SerialNumStrLen + 1 + AssertTagStrLen + 1);\r
+ MemDevSmbiosHandle = SMBIOS_HANDLE_PI_RESERVED;\r
+ Status = Smbios->Add (Smbios, NULL, &MemDevSmbiosHandle, (EFI_SMBIOS_TABLE_HEADER*) Type17Record);\r
+ FreePool(Type17Record);\r
+ ASSERT_EFI_ERROR (Status);\r
+\r
+ //\r
+ // Generate Memory Device Mapped Address info\r
+ //\r
+ ZeroMem(&DeviceStartAddress, sizeof(EFI_MEMORY_DEVICE_START_ADDRESS_DATA));\r
+ DeviceStartAddress.MemoryDeviceStartAddress = 0;\r
+ DeviceStartAddress.MemoryDeviceEndAddress = DeviceStartAddress.MemoryDeviceStartAddress + DimmMemorySize-1;\r
+ DeviceStartAddress.PhysicalMemoryDeviceLink.ProducerName = gEfiMemorySubClassDriverGuid;\r
+ DeviceStartAddress.PhysicalMemoryDeviceLink.Instance = ArrayInstance;\r
+ DeviceStartAddress.PhysicalMemoryDeviceLink.SubInstance = (UINT16)(Dimm + 1);\r
+ DeviceStartAddress.PhysicalMemoryArrayLink.ProducerName = gEfiMemorySubClassDriverGuid;\r
+ DeviceStartAddress.PhysicalMemoryArrayLink.Instance = ArrayInstance;\r
+ DeviceStartAddress.PhysicalMemoryArrayLink.SubInstance = EFI_SUBCLASS_INSTANCE_NON_APPLICABLE;\r
+\r
+ //\r
+ // Single channel mode\r
+ //\r
+ DeviceStartAddress.MemoryDevicePartitionRowPosition = 0x01;\r
+ DeviceStartAddress.MemoryDeviceInterleavePosition = 0x00;\r
+ DeviceStartAddress.MemoryDeviceInterleaveDataDepth = 0x00;\r
+\r
+ //\r
+ // Generate Memory Device Mapped Address info (TYPE 20)\r
+ //\r
+ Type20Record = AllocatePool(sizeof (SMBIOS_TABLE_TYPE20));\r
+ ZeroMem(Type20Record, sizeof (SMBIOS_TABLE_TYPE20));\r
+ Type20Record->Hdr.Type = EFI_SMBIOS_TYPE_MEMORY_DEVICE_MAPPED_ADDRESS;\r
+ Type20Record->Hdr.Length = sizeof(SMBIOS_TABLE_TYPE20);\r
+ Type20Record->Hdr.Handle = 0;\r
+\r
+ Type20Record->StartingAddress = (UINT32)RShiftU64 (DeviceStartAddress.MemoryDeviceStartAddress, 10);\r
+ Type20Record->EndingAddress = (UINT32)RShiftU64 (DeviceStartAddress.MemoryDeviceEndAddress, 10);\r
+ Type20Record->MemoryDeviceHandle = MemDevSmbiosHandle;\r
+ Type20Record->MemoryArrayMappedAddressHandle = MemArrayMappedAddrSmbiosHandle;\r
+ Type20Record->PartitionRowPosition = DeviceStartAddress.MemoryDevicePartitionRowPosition;\r
+ Type20Record->InterleavePosition = DeviceStartAddress.MemoryDeviceInterleavePosition;\r
+ Type20Record->InterleavedDataDepth = DeviceStartAddress.MemoryDeviceInterleaveDataDepth;\r
+ MemDevMappedAddrSmbiosHandle = SMBIOS_HANDLE_PI_RESERVED;\r
+ Status = Smbios->Add (Smbios, NULL, &MemDevMappedAddrSmbiosHandle, (EFI_SMBIOS_TABLE_HEADER*) Type20Record);\r
+ FreePool(Type20Record);\r
+ ASSERT_EFI_ERROR (Status);\r
+\r
+ return Status;\r
+}\r
--- /dev/null
+/** @file\r
+Header file for MemorySubClass Driver.\r
+\r
+Copyright (c) 2013-2015 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#ifndef _MEMORY_SUB_CLASS_H\r
+#define _MEMORY_SUB_CLASS_H\r
+\r
+//\r
+// The package level header files this module uses\r
+//\r
+#include <FrameworkDxe.h>\r
+//\r
+// The protocols, PPI and GUID definitions for this module\r
+//\r
+#include <IndustryStandard/SmBios.h>\r
+#include <Protocol/Smbios.h>\r
+#include <Protocol/PciRootBridgeIo.h>\r
+#include <Protocol/SmbusHc.h>\r
+#include <Guid/DataHubRecords.h>\r
+#include <Guid/MemoryConfigData.h>\r
+#include <Protocol/HiiDatabase.h>\r
+#include <Guid/MdeModuleHii.h>\r
+\r
+//\r
+// The Library classes this module consumes\r
+//\r
+#include <Library/BaseLib.h>\r
+#include <Library/HobLib.h>\r
+#include <Library/UefiDriverEntryPoint.h>\r
+#include <Library/UefiBootServicesTableLib.h>\r
+#include <Library/UefiRuntimeServicesTableLib.h>\r
+#include <Library/DebugLib.h>\r
+#include <Library/BaseMemoryLib.h>\r
+#include <Library/PrintLib.h>\r
+#include <Library/HiiLib.h>\r
+#include <Library/MemoryAllocationLib.h>\r
+#include <Library/PciLib.h>\r
+#include <Library/QNCAccessLib.h>\r
+\r
+#include "QNCAccess.h"\r
+\r
+\r
+\r
+//\r
+// This is the generated header file which includes whatever needs to be exported (strings + IFR)\r
+//\r
+\r
+#define EFI_MEMORY_SUBCLASS_DRIVER_GUID \\r
+ { 0xef17cee7, 0x267d, 0x4bfd, { 0xa2, 0x57, 0x4a, 0x6a, 0xb3, 0xee, 0x85, 0x91 }}\r
+\r
+//\r
+// Prototypes\r
+//\r
+EFI_STATUS\r
+MemorySubClassEntryPoint (\r
+ IN EFI_HANDLE ImageHandle,\r
+ IN EFI_SYSTEM_TABLE *SystemTable\r
+ );\r
+\r
+#endif\r
--- /dev/null
+## @file\r
+# Component description file for MemorySubClass module.\r
+#\r
+# This is the driver that locates the MemoryConfigurationData Variable, if it\r
+# exists, and reports the data to the DataHub.\r
+# Copyright (c) 2013-2015 Intel Corporation.\r
+#\r
+# This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution. The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php\r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+##\r
+\r
+[Defines]\r
+ INF_VERSION = 0x00010005\r
+ BASE_NAME = MemorySubClass\r
+ FILE_GUID = EF17CEE7-267D-4BFD-A257-4A6AB3EE8591\r
+ MODULE_TYPE = DXE_DRIVER\r
+ VERSION_STRING = 1.0\r
+ ENTRY_POINT = MemorySubClassEntryPoint\r
+\r
+#\r
+# The following information is for reference only and not required by the build tools.\r
+#\r
+# VALID_ARCHITECTURES = IA32 X64 IPF EBC\r
+#\r
+\r
+[Sources]\r
+ MemorySubClass.c\r
+ MemorySubClass.h\r
+ MemorySubClassStrings.uni\r
+\r
+[Packages]\r
+ MdePkg/MdePkg.dec\r
+ MdeModulePkg/MdeModulePkg.dec\r
+ IntelFrameworkPkg/IntelFrameworkPkg.dec\r
+ QuarkSocPkg/QuarkSocPkg.dec\r
+ QuarkPlatformPkg/QuarkPlatformPkg.dec\r
+\r
+[LibraryClasses]\r
+ MemoryAllocationLib\r
+ HiiLib\r
+ PrintLib\r
+ BaseMemoryLib\r
+ DebugLib\r
+ UefiRuntimeServicesTableLib\r
+ UefiBootServicesTableLib\r
+ UefiDriverEntryPoint\r
+ BaseLib\r
+ HobLib\r
+ PciLib\r
+ QNCAccessLib\r
+\r
+[Guids]\r
+ gEfiMemoryConfigDataGuid # ALWAYS_CONSUMED\r
+\r
+[Protocols]\r
+ gEfiSmbiosProtocolGuid # PROTOCOL ALWAYS_CONSUMED\r
+ gEfiSmbusHcProtocolGuid # PROTOCOL ALWAYS_CONSUMED\r
+\r
+[Depex]\r
+ gEfiVariableArchProtocolGuid AND gEfiVariableWriteArchProtocolGuid AND gEfiSmbiosProtocolGuid AND gEfiSmbusHcProtocolGuid\r
--- /dev/null
+// /** @file\r
+// String definitions for Smbios Memory SubClass data.\r
+//\r
+// Copyright (c) 2013-2015 Intel Corporation.\r
+//\r
+// This program and the accompanying materials\r
+// are licensed and made available under the terms and conditions of the BSD License\r
+// which accompanies this distribution. The full text of the license may be found at\r
+// http://opensource.org/licenses/bsd-license.php\r
+//\r
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+//\r
+//\r
+// **/\r
+\r
+\r
+/=#\r
+\r
+#langdef en-US "English"\r
+\r
+//\r
+// Begin English Language Strings\r
+//\r
+#string STR_MEMORY_SUBCLASS_UNKNOWN #language en-US "Unknown"\r
+#string STR_MEMORY_SUBCLASS_DEVICE_LOCATOR_0 #language en-US "SOLDER DOWN"\r
+#string STR_MEMORY_SUBCLASS_MANUFACTURER #language en-US "Manufacturer: "\r
+#string STR_MEMORY_SUBCLASS_SERIAL_NUMBER #language en-US "Serial Number: "\r
+#string STR_MEMORY_SUBCLASS_ASSET_TAG #language en-US "Asset Tag: "\r
+#string STR_MEMORY_SUBCLASS_PART_NUMBER #language en-US "PartNumber: "\r
+//\r
+// End English Language Strings\r
+//\r
+\r
+\r
--- /dev/null
+/** @file\r
+Essential platform configuration.\r
+\r
+Copyright (c) 2013 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+**/\r
+\r
+#include "PlatformInitDxe.h"\r
+\r
+//\r
+// The protocols, PPI and GUID defintions for this module\r
+//\r
+\r
+//\r
+// The Library classes this module consumes\r
+//\r
+\r
+//\r
+// RTC:28208 - System hang/crash when entering probe mode(ITP) when relocating SMBASE\r
+// Workaround to make default SMRAM UnCachable\r
+//\r
+#define SMM_DEFAULT_SMBASE 0x30000 // Default SMBASE address\r
+#define SMM_DEFAULT_SMBASE_SIZE_BYTES 0x10000 // Size in bytes of default SMRAM\r
+\r
+BOOLEAN mMemCfgDone = FALSE;\r
+UINT8 ChipsetDefaultMac [6] = {0xff,0xff,0xff,0xff,0xff,0xff};\r
+\r
+VOID\r
+EFIAPI\r
+PlatformInitializeUart0MuxGalileo (\r
+ VOID\r
+ )\r
+/*++\r
+\r
+\r
+Routine Description:\r
+\r
+ This is the routine to initialize UART0 for DBG2 support. The hardware used in this process is a\r
+ Legacy Bridge (Legacy GPIO), I2C controller, a bi-directional MUX and a Cypress CY8C9540A chip.\r
+\r
+Arguments:\r
+\r
+ None.\r
+\r
+Returns:\r
+\r
+ None.\r
+\r
+--*/\r
+{\r
+ EFI_STATUS Status;\r
+ EFI_I2C_DEVICE_ADDRESS I2CSlaveAddress;\r
+ UINTN Length;\r
+ UINT8 Buffer[2];\r
+\r
+ if (PlatformLegacyGpioGetLevel (R_QNC_GPIO_RGLVL_RESUME_WELL, GALILEO_DETERMINE_IOEXP_SLA_RESUMEWELL_GPIO)) {\r
+ I2CSlaveAddress.I2CDeviceAddress = GALILEO_IOEXP_J2HI_7BIT_SLAVE_ADDR;\r
+ } else {\r
+ I2CSlaveAddress.I2CDeviceAddress = GALILEO_IOEXP_J2LO_7BIT_SLAVE_ADDR;\r
+ }\r
+\r
+ //\r
+ // Set GPIO_SUS<2> as an output, raise voltage to Vdd.\r
+ //\r
+ PlatformLegacyGpioSetLevel (R_QNC_GPIO_RGLVL_RESUME_WELL, 2, TRUE);\r
+\r
+ //\r
+ // Select Port 3\r
+ //\r
+ Length = 2;\r
+ Buffer[0] = 0x18; //sub-address\r
+ Buffer[1] = 0x03; //data\r
+\r
+ Status = I2cWriteMultipleByte (\r
+ I2CSlaveAddress,\r
+ EfiI2CSevenBitAddrMode,\r
+ &Length,\r
+ &Buffer\r
+ );\r
+ ASSERT_EFI_ERROR (Status);\r
+\r
+ //\r
+ // Set "Pin Direction" bit4 and bit5 as outputs\r
+ //\r
+ Length = 2;\r
+ Buffer[0] = 0x1C; //sub-address\r
+ Buffer[1] = 0xCF; //data\r
+\r
+ Status = I2cWriteMultipleByte (\r
+ I2CSlaveAddress,\r
+ EfiI2CSevenBitAddrMode,\r
+ &Length,\r
+ &Buffer\r
+ );\r
+ ASSERT_EFI_ERROR (Status);\r
+\r
+ //\r
+ // Lower GPORT3 bit4 and bit5 to Vss\r
+ //\r
+ Length = 2;\r
+ Buffer[0] = 0x0B; //sub-address\r
+ Buffer[1] = 0xCF; //data\r
+\r
+ Status = I2cWriteMultipleByte (\r
+ I2CSlaveAddress,\r
+ EfiI2CSevenBitAddrMode,\r
+ &Length,\r
+ &Buffer\r
+ );\r
+ ASSERT_EFI_ERROR (Status);\r
+}\r
+\r
+VOID\r
+EFIAPI\r
+PlatformInitializeUart0MuxGalileoGen2 (\r
+ VOID\r
+ )\r
+/*++\r
+\r
+\r
+Routine Description:\r
+\r
+ This is the routine to initialize UART0 on GalileoGen2. The hardware used in this process is\r
+ I2C controller and the configuring the following IO Expander signal.\r
+\r
+ EXP1.P1_5 should be configured as an output & driven high.\r
+ EXP1.P0_0 should be configured as an output & driven high.\r
+ EXP0.P1_4 should be configured as an output, driven low.\r
+ EXP1.P0_1 pullup should be disabled.\r
+ EXP0.P1_5 Pullup should be disabled.\r
+\r
+Arguments:\r
+\r
+ None.\r
+\r
+Returns:\r
+\r
+ None.\r
+\r
+--*/\r
+\r
+{\r
+ //\r
+ // EXP1.P1_5 should be configured as an output & driven high.\r
+ //\r
+ PlatformPcal9555GpioSetDir (\r
+ GALILEO_GEN2_IOEXP1_7BIT_SLAVE_ADDR, // IO Expander 1.\r
+ 13, // P1-5.\r
+ TRUE\r
+ );\r
+ PlatformPcal9555GpioSetLevel (\r
+ GALILEO_GEN2_IOEXP1_7BIT_SLAVE_ADDR, // IO Expander 1.\r
+ 13, // P1-5.\r
+ TRUE\r
+ );\r
+\r
+ //\r
+ // EXP1.P0_0 should be configured as an output & driven high.\r
+ //\r
+ PlatformPcal9555GpioSetDir (\r
+ GALILEO_GEN2_IOEXP0_7BIT_SLAVE_ADDR, // IO Expander 0.\r
+ 0, // P0_0.\r
+ TRUE\r
+ );\r
+ PlatformPcal9555GpioSetLevel (\r
+ GALILEO_GEN2_IOEXP0_7BIT_SLAVE_ADDR, // IO Expander 0.\r
+ 0, // P0_0.\r
+ TRUE\r
+ );\r
+\r
+ //\r
+ // EXP0.P1_4 should be configured as an output, driven low.\r
+ //\r
+ PlatformPcal9555GpioSetDir (\r
+ GALILEO_GEN2_IOEXP0_7BIT_SLAVE_ADDR, // IO Expander 0.\r
+ 12, // P1-4.\r
+ FALSE\r
+ );\r
+ PlatformPcal9555GpioSetLevel ( // IO Expander 0.\r
+ GALILEO_GEN2_IOEXP0_7BIT_SLAVE_ADDR, // P1-4\r
+ 12,\r
+ FALSE\r
+ );\r
+\r
+ //\r
+ // EXP1.P0_1 pullup should be disabled.\r
+ //\r
+ PlatformPcal9555GpioDisablePull (\r
+ GALILEO_GEN2_IOEXP1_7BIT_SLAVE_ADDR, // IO Expander 1.\r
+ 1 // P0-1.\r
+ );\r
+\r
+ //\r
+ // EXP0.P1_5 Pullup should be disabled.\r
+ //\r
+ PlatformPcal9555GpioDisablePull (\r
+ GALILEO_GEN2_IOEXP0_7BIT_SLAVE_ADDR, // IO Expander 0.\r
+ 13 // P1-5.\r
+ );\r
+}\r
+\r
+VOID\r
+EFIAPI\r
+PlatformConfigOnSmmConfigurationProtocol (\r
+ IN EFI_EVENT Event,\r
+ IN VOID *Context\r
+ )\r
+/*++\r
+\r
+Routine Description:\r
+\r
+ Function runs in PI-DXE to perform platform specific config when\r
+ SmmConfigurationProtocol is installed.\r
+\r
+Arguments:\r
+ Event - The event that occured.\r
+ Context - For EFI compatiblity. Not used.\r
+\r
+Returns:\r
+ None.\r
+--*/\r
+\r
+{\r
+ EFI_STATUS Status;\r
+ UINT32 NewValue;\r
+ UINT64 BaseAddress;\r
+ UINT64 SmramLength;\r
+ VOID *SmmCfgProt;\r
+\r
+ Status = gBS->LocateProtocol (&gEfiSmmConfigurationProtocolGuid, NULL, &SmmCfgProt);\r
+ if (Status != EFI_SUCCESS){\r
+ DEBUG ((DEBUG_INFO, "gEfiSmmConfigurationProtocolGuid triggered but not valid.\n"));\r
+ return;\r
+ }\r
+ if (mMemCfgDone) {\r
+ DEBUG ((DEBUG_INFO, "Platform DXE Mem config already done.\n"));\r
+ return;\r
+ }\r
+\r
+ //\r
+ // Disable eSram block (this will also clear/zero eSRAM)\r
+ // We only use eSRAM in the PEI phase. Disable now that we are in the DXE phase\r
+ //\r
+ NewValue = QNCPortRead (QUARK_NC_MEMORY_MANAGER_SB_PORT_ID, QUARK_NC_MEMORY_MANAGER_ESRAMPGCTRL_BLOCK);\r
+ NewValue |= BLOCK_DISABLE_PG;\r
+ QNCPortWrite (QUARK_NC_MEMORY_MANAGER_SB_PORT_ID, QUARK_NC_MEMORY_MANAGER_ESRAMPGCTRL_BLOCK, NewValue);\r
+\r
+ //\r
+ // Update HMBOUND to top of DDR3 memory and LOCK\r
+ // We disabled eSRAM so now we move HMBOUND down to top of DDR3\r
+ //\r
+ QNCGetTSEGMemoryRange (&BaseAddress, &SmramLength);\r
+ NewValue = (UINT32)(BaseAddress + SmramLength);\r
+ DEBUG ((EFI_D_INFO,"Locking HMBOUND at: = 0x%8x\n",NewValue));\r
+ QNCPortWrite (QUARK_NC_HOST_BRIDGE_SB_PORT_ID, QUARK_NC_HOST_BRIDGE_HMBOUND_REG, (NewValue | HMBOUND_LOCK));\r
+\r
+ //\r
+ // Lock IMR5 now that HMBOUND is locked (legacy S3 region)\r
+ //\r
+ NewValue = QNCPortRead (QUARK_NC_MEMORY_MANAGER_SB_PORT_ID, QUARK_NC_MEMORY_MANAGER_IMR5+QUARK_NC_MEMORY_MANAGER_IMRXL);\r
+ NewValue |= IMR_LOCK;\r
+ QNCPortWrite (QUARK_NC_MEMORY_MANAGER_SB_PORT_ID, QUARK_NC_MEMORY_MANAGER_IMR5+QUARK_NC_MEMORY_MANAGER_IMRXL, NewValue);\r
+\r
+ //\r
+ // Lock IMR6 now that HMBOUND is locked (ACPI Reclaim/ACPI/Runtime services/Reserved)\r
+ //\r
+ NewValue = QNCPortRead (QUARK_NC_MEMORY_MANAGER_SB_PORT_ID, QUARK_NC_MEMORY_MANAGER_IMR6+QUARK_NC_MEMORY_MANAGER_IMRXL);\r
+ NewValue |= IMR_LOCK;\r
+ QNCPortWrite (QUARK_NC_MEMORY_MANAGER_SB_PORT_ID, QUARK_NC_MEMORY_MANAGER_IMR6+QUARK_NC_MEMORY_MANAGER_IMRXL, NewValue);\r
+\r
+ //\r
+ // Disable IMR2 memory protection (RMU Main Binary)\r
+ //\r
+ QncImrWrite (\r
+ QUARK_NC_MEMORY_MANAGER_IMR2,\r
+ (UINT32)(IMRL_RESET & ~IMR_EN),\r
+ (UINT32)IMRH_RESET,\r
+ (UINT32)IMRX_ALL_ACCESS,\r
+ (UINT32)IMRX_ALL_ACCESS\r
+ );\r
+\r
+ //\r
+ // Disable IMR3 memory protection (Default SMRAM)\r
+ //\r
+ QncImrWrite (\r
+ QUARK_NC_MEMORY_MANAGER_IMR3,\r
+ (UINT32)(IMRL_RESET & ~IMR_EN),\r
+ (UINT32)IMRH_RESET,\r
+ (UINT32)IMRX_ALL_ACCESS,\r
+ (UINT32)IMRX_ALL_ACCESS\r
+ );\r
+\r
+ //\r
+ // Disable IMR4 memory protection (eSRAM).\r
+ //\r
+ QncImrWrite (\r
+ QUARK_NC_MEMORY_MANAGER_IMR4,\r
+ (UINT32)(IMRL_RESET & ~IMR_EN),\r
+ (UINT32)IMRH_RESET,\r
+ (UINT32)IMRX_ALL_ACCESS,\r
+ (UINT32)IMRX_ALL_ACCESS\r
+ );\r
+\r
+ //\r
+ // RTC:28208 - System hang/crash when entering probe mode(ITP) when relocating SMBASE\r
+ // Workaround to make default SMRAM UnCachable\r
+ //\r
+ Status = gDS->SetMemorySpaceAttributes (\r
+ (EFI_PHYSICAL_ADDRESS) SMM_DEFAULT_SMBASE,\r
+ SMM_DEFAULT_SMBASE_SIZE_BYTES,\r
+ EFI_MEMORY_WB\r
+ );\r
+ ASSERT_EFI_ERROR (Status);\r
+\r
+ mMemCfgDone = TRUE;\r
+}\r
+\r
+VOID\r
+EFIAPI\r
+PlatformConfigOnSpiReady (\r
+ IN EFI_EVENT Event,\r
+ IN VOID *Context\r
+ )\r
+/*++\r
+\r
+Routine Description:\r
+\r
+ Function runs in PI-DXE to perform platform specific config when SPI\r
+ interface is ready.\r
+\r
+Arguments:\r
+ Event - The event that occured.\r
+ Context - For EFI compatiblity. Not used.\r
+\r
+Returns:\r
+ None.\r
+\r
+--*/\r
+{\r
+ EFI_STATUS Status;\r
+ VOID *SpiReadyProt = NULL;\r
+ EFI_PLATFORM_TYPE Type;\r
+ EFI_BOOT_MODE BootMode;\r
+\r
+ BootMode = GetBootModeHob ();\r
+\r
+ Status = gBS->LocateProtocol (&gEfiSmmSpiReadyProtocolGuid, NULL, &SpiReadyProt);\r
+ if (Status != EFI_SUCCESS){\r
+ DEBUG ((DEBUG_INFO, "gEfiSmmSpiReadyProtocolGuid triggered but not valid.\n"));\r
+ return;\r
+ }\r
+\r
+ //\r
+ // Lock regions SPI flash.\r
+ //\r
+ PlatformFlashLockPolicy (FALSE);\r
+\r
+ //\r
+ // Configurations and checks to be done when DXE tracing available.\r
+ //\r
+\r
+ //\r
+ // Platform specific Signal routing.\r
+ //\r
+\r
+ //\r
+ // Skip any signal not needed for recovery and flash update.\r
+ //\r
+ if (BootMode != BOOT_ON_FLASH_UPDATE && BootMode != BOOT_IN_RECOVERY_MODE) {\r
+\r
+ //\r
+ // Galileo Platform UART0 support.\r
+ //\r
+ Type = (EFI_PLATFORM_TYPE)PcdGet16 (PcdPlatformType);\r
+ if (Type == Galileo) {\r
+ //\r
+ // Use MUX to connect out UART0 pins.\r
+ //\r
+ PlatformInitializeUart0MuxGalileo ();\r
+ }\r
+\r
+ //\r
+ // GalileoGen2 Platform UART0 support.\r
+ //\r
+ if (Type == GalileoGen2) {\r
+ //\r
+ // Use route out UART0 pins.\r
+ //\r
+ PlatformInitializeUart0MuxGalileoGen2 ();\r
+ }\r
+ }\r
+}\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+CreateConfigEvents (\r
+ VOID\r
+ )\r
+/*++\r
+\r
+Routine Description:\r
+\r
+Arguments:\r
+ None\r
+\r
+Returns:\r
+ EFI_STATUS\r
+\r
+--*/\r
+{\r
+ EFI_EVENT EventSmmCfg;\r
+ EFI_EVENT EventSpiReady;\r
+ VOID *RegistrationSmmCfg;\r
+ VOID *RegistrationSpiReady;\r
+\r
+ //\r
+ // Schedule callback for when SmmConfigurationProtocol installed.\r
+ //\r
+ EventSmmCfg = EfiCreateProtocolNotifyEvent (\r
+ &gEfiSmmConfigurationProtocolGuid,\r
+ TPL_CALLBACK,\r
+ PlatformConfigOnSmmConfigurationProtocol,\r
+ NULL,\r
+ &RegistrationSmmCfg\r
+ );\r
+ ASSERT (EventSmmCfg != NULL);\r
+\r
+ //\r
+ // Schedule callback to setup SPI Flash Policy when SPI interface ready.\r
+ //\r
+ EventSpiReady = EfiCreateProtocolNotifyEvent (\r
+ &gEfiSmmSpiReadyProtocolGuid,\r
+ TPL_CALLBACK,\r
+ PlatformConfigOnSpiReady,\r
+ NULL,\r
+ &RegistrationSpiReady\r
+ );\r
+ ASSERT (EventSpiReady != NULL);\r
+ return EFI_SUCCESS;\r
+}\r
--- /dev/null
+/** @file\r
+Platform init DXE driver for this platform.\r
+\r
+Copyright (c) 2013 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+//\r
+// Statements that include other files\r
+//\r
+#include "PlatformInitDxe.h"\r
+#include <Library/PciLib.h>\r
+#include <IndustryStandard/Pci.h>\r
+\r
+VOID\r
+GetQncName (\r
+ VOID\r
+ )\r
+{\r
+ DEBUG ((EFI_D_INFO, "QNC Name: "));\r
+ switch (PciRead16 (PCI_LIB_ADDRESS (MC_BUS, MC_DEV, MC_FUN, PCI_DEVICE_ID_OFFSET))) {\r
+ case QUARK_MC_DEVICE_ID:\r
+ DEBUG ((EFI_D_INFO, "Quark"));\r
+ break;\r
+ case QUARK2_MC_DEVICE_ID:\r
+ DEBUG ((EFI_D_INFO, "Quark2"));\r
+ break;\r
+ default:\r
+ DEBUG ((EFI_D_INFO, "Unknown"));\r
+ }\r
+\r
+ //\r
+ // Revision\r
+ //\r
+ switch (PciRead8 (PCI_LIB_ADDRESS (MC_BUS, MC_DEV, MC_FUN, PCI_REVISION_ID_OFFSET))) {\r
+ case QNC_MC_REV_ID_A0:\r
+ DEBUG ((EFI_D_INFO, " - A0 stepping\n"));\r
+ break;\r
+ default:\r
+ DEBUG ((EFI_D_INFO, " - xx\n"));\r
+ }\r
+\r
+ return;\r
+}\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+PlatformInit (\r
+ IN EFI_HANDLE ImageHandle,\r
+ IN EFI_SYSTEM_TABLE *SystemTable\r
+ )\r
+/*++\r
+\r
+Routine Description:\r
+ Entry point for the driver.\r
+\r
+Arguments:\r
+\r
+ ImageHandle - Image Handle.\r
+ SystemTable - EFI System Table.\r
+\r
+Returns:\r
+\r
+ EFI_SUCCESS - Function has completed successfully.\r
+\r
+--*/\r
+{\r
+ EFI_STATUS Status;\r
+\r
+ GetQncName();\r
+\r
+ //\r
+ // Create events for configuration callbacks.\r
+ //\r
+ CreateConfigEvents ();\r
+\r
+ //\r
+ // Init Platform LEDs.\r
+ //\r
+ Status = PlatformLedInit ((EFI_PLATFORM_TYPE)PcdGet16 (PcdPlatformType));\r
+ ASSERT_EFI_ERROR (Status);\r
+\r
+ return EFI_SUCCESS;\r
+}\r
+\r
--- /dev/null
+/** @file\r
+Platform init DXE driver header file.\r
+\r
+Copyright (c) 2013 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#ifndef _PLATFORM_TYPES_H_\r
+#define _PLATFORM_TYPES_H_\r
+\r
+#include <PiDxe.h>\r
+#include <Library/DebugLib.h>\r
+#include <Library/BaseLib.h>\r
+#include <Library/BaseMemoryLib.h>\r
+#include <Library/UefiLib.h>\r
+#include <Library/UefiBootServicesTableLib.h>\r
+#include <Library/HobLib.h>\r
+#include <Library/UefiRuntimeServicesTableLib.h>\r
+#include <Library/PlatformHelperLib.h>\r
+#include <Library/PlatformPcieHelperLib.h>\r
+#include <Library/IntelQNCLib.h>\r
+#include <Library/QNCAccessLib.h>\r
+#include <Library/DxeServicesTableLib.h>\r
+#include <Library/I2cLib.h>\r
+#include <Protocol/Variable.h>\r
+#include <Protocol/Cpu.h>\r
+#include <Protocol/PciEnumerationComplete.h>\r
+#include <Protocol/Spi.h>\r
+#include <Protocol/PlatformSmmSpiReady.h>\r
+#include <Protocol/SmmConfiguration.h>\r
+#include <Guid/HobList.h>\r
+#include <IntelQNCRegs.h>\r
+#include <Platform.h>\r
+#include <Pcal9555.h>\r
+#include <PlatformBoards.h>\r
+#include <IohAccess.h>\r
+\r
+#define BLOCK_SIZE_32KB 0x8000\r
+#define BLOCK_SIZE_64KB 0x10000\r
+\r
+//\r
+// Function prototypes for routines private to this driver.\r
+//\r
+EFI_STATUS\r
+EFIAPI\r
+CreateConfigEvents (\r
+ VOID\r
+ );\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+PlatformPcal9555Config (\r
+ IN CONST EFI_PLATFORM_TYPE PlatformType\r
+ );\r
+\r
+#endif\r
--- /dev/null
+## @file\r
+# Component description file for Quark Platform Init DXE module.\r
+#\r
+# Copyright (c) 2013 Intel Corporation.\r
+#\r
+# This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution. The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php\r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+##\r
+\r
+\r
+[Defines]\r
+ INF_VERSION = 0x00010005\r
+ BASE_NAME = PlatformInitDxe\r
+ FILE_GUID = 2E6A521C-F697-402d-9774-98B2B7E140F3\r
+ MODULE_TYPE = DXE_DRIVER\r
+ VERSION_STRING = 1.0\r
+ ENTRY_POINT = PlatformInit\r
+\r
+[Sources]\r
+ PlatformInitDxe.h\r
+ PlatformInitDxe.c\r
+ PlatformConfig.c\r
+\r
+[Packages]\r
+ MdePkg/MdePkg.dec\r
+ QuarkSocPkg/QuarkSocPkg.dec\r
+ QuarkPlatformPkg/QuarkPlatformPkg.dec\r
+\r
+[LibraryClasses]\r
+ BaseLib\r
+ HobLib\r
+ DebugLib\r
+ UefiDriverEntryPoint\r
+ UefiBootServicesTableLib\r
+ UefiRuntimeServicesTableLib\r
+ DxeServicesTableLib\r
+ PlatformHelperLib\r
+ PlatformPcieHelperLib\r
+ DxeServicesLib\r
+ IntelQNCLib\r
+ QNCAccessLib\r
+ BaseMemoryLib\r
+ I2cLib\r
+\r
+[Protocols]\r
+ gEfiFirmwareVolumeBlockProtocolGuid\r
+ gEfiCpuArchProtocolGuid\r
+ gEfiSmmConfigurationProtocolGuid\r
+ gEfiSmmSpiReadyProtocolGuid\r
+\r
+[Pcd]\r
+ gQuarkPlatformTokenSpaceGuid.PcdPlatformType\r
+\r
+[Depex]\r
+ TRUE\r
+\r
--- /dev/null
+/** @file\r
+This is the driver that locates the MemoryConfigurationData HOB, if it\r
+exists, and saves the data to nvRAM.\r
+\r
+Copyright (c) 2013-2015 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#include <Library/DebugLib.h>\r
+#include <Library/HobLib.h>\r
+#include <Library/MemoryAllocationLib.h>\r
+#include <Library/UefiBootServicesTableLib.h>\r
+#include <Library/UefiRuntimeServicesTableLib.h>\r
+#include <Library/BaseMemoryLib.h>\r
+#include <Library/UefiDriverEntryPoint.h>\r
+\r
+#include <Guid/MemoryConfigData.h>\r
+#include <Guid/DebugMask.h>\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+SaveMemoryConfigEntryPoint (\r
+ IN EFI_HANDLE ImageHandle,\r
+ IN EFI_SYSTEM_TABLE *SystemTable\r
+ )\r
+/*++\r
+\r
+ Routine Description:\r
+ This is the standard EFI driver point that detects whether there is a\r
+ MemoryConfigurationData HOB and, if so, saves its data to nvRAM.\r
+\r
+ Arguments:\r
+ ImageHandle - Handle for the image of this driver\r
+ SystemTable - Pointer to the EFI System Table\r
+\r
+ Returns:\r
+ EFI_SUCCESS - if the data is successfully saved or there was no data\r
+ EFI_NOT_FOUND - if the HOB list could not be located.\r
+ EFI_UNLOAD_IMAGE - It is not success\r
+\r
+--*/\r
+{\r
+ EFI_STATUS Status;\r
+ VOID *HobList;\r
+ EFI_HOB_GUID_TYPE *GuidHob;\r
+ VOID *HobData;\r
+ VOID *VariableData;\r
+ UINTN DataSize;\r
+ UINTN BufferSize;\r
+\r
+ DataSize = 0;\r
+ VariableData = NULL;\r
+ GuidHob = NULL;\r
+ HobList = NULL;\r
+ HobData = NULL;\r
+ Status = EFI_UNSUPPORTED;\r
+\r
+ //\r
+ // Get the HOB list. If it is not present, then ASSERT.\r
+ //\r
+ HobList = GetHobList ();\r
+ ASSERT (HobList != NULL);\r
+\r
+ //\r
+ // Search for the Memory Configuration GUID HOB. If it is not present, then\r
+ // there's nothing we can do. It may not exist on the update path.\r
+ //\r
+ GuidHob = GetNextGuidHob (&gEfiMemoryConfigDataGuid, HobList);\r
+ if (GuidHob != NULL) {\r
+ HobData = GET_GUID_HOB_DATA (GuidHob);\r
+ DataSize = GET_GUID_HOB_DATA_SIZE (GuidHob);\r
+ //\r
+ // Use the HOB to save Memory Configuration Data\r
+ //\r
+ BufferSize = DataSize;\r
+ VariableData = AllocatePool (BufferSize);\r
+ ASSERT (VariableData != NULL);\r
+ Status = gRT->GetVariable (\r
+ EFI_MEMORY_CONFIG_DATA_NAME,\r
+ &gEfiMemoryConfigDataGuid,\r
+ NULL,\r
+ &BufferSize,\r
+ VariableData\r
+ );\r
+ if (Status == EFI_BUFFER_TOO_SMALL) {\r
+ gBS->FreePool (VariableData);\r
+ VariableData = AllocatePool (BufferSize);\r
+ ASSERT (VariableData != NULL);\r
+ Status = gRT->GetVariable (\r
+ EFI_MEMORY_CONFIG_DATA_NAME,\r
+ &gEfiMemoryConfigDataGuid,\r
+ NULL,\r
+ &BufferSize,\r
+ VariableData\r
+ );\r
+ }\r
+\r
+ if (EFI_ERROR(Status) || BufferSize != DataSize || CompareMem (HobData, VariableData, DataSize) != 0) {\r
+ Status = gRT->SetVariable (\r
+ EFI_MEMORY_CONFIG_DATA_NAME,\r
+ &gEfiMemoryConfigDataGuid,\r
+ (EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS),\r
+ DataSize,\r
+ HobData\r
+ );\r
+ ASSERT((Status == EFI_SUCCESS) || (Status == EFI_OUT_OF_RESOURCES));\r
+ }\r
+\r
+ gBS->FreePool (VariableData);\r
+ }\r
+\r
+ //\r
+ // This driver does not produce any protocol services, so always unload it.\r
+ //\r
+ return Status;\r
+}\r
--- /dev/null
+## @file\r
+# Component description file for SaveMemoryConfig module\r
+#\r
+# Copyright (c) 2013-2015 Intel Corporation.\r
+#\r
+# This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution. The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php\r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+##\r
+\r
+[Defines]\r
+ INF_VERSION = 0x00010005\r
+ BASE_NAME = SaveMemoryConfig\r
+ FILE_GUID = 0F99E33C-CA0C-4aa2-887D-B57EC9050278\r
+ MODULE_TYPE = DXE_DRIVER\r
+ VERSION_STRING = 1.0\r
+ ENTRY_POINT = SaveMemoryConfigEntryPoint\r
+\r
+[sources]\r
+ SaveMemoryConfig.c\r
+\r
+[Packages]\r
+ MdePkg/MdePkg.dec\r
+ MdeModulePkg/MdeModulePkg.dec\r
+ QuarkPlatformPkg/QuarkPlatformPkg.dec\r
+\r
+[LibraryClasses]\r
+ DebugLib\r
+ MemoryAllocationLib\r
+ BaseMemoryLib\r
+ UefiRuntimeServicesTableLib\r
+ UefiBootServicesTableLib\r
+ UefiDriverEntryPoint\r
+ HobLib\r
+\r
+[Protocols]\r
+\r
+[Guids]\r
+ gEfiGenericVariableGuid\r
+ gEfiMemoryConfigDataGuid\r
+\r
+[Depex]\r
+ gEdkiiVariableLockProtocolGuid AND\r
+ gEfiVariableArchProtocolGuid AND\r
+ gEfiVariableWriteArchProtocolGuid\r
--- /dev/null
+/** @file\r
+Common header file shared by all source files.\r
+\r
+This file includes package header files, library classes and protocol, PPI & GUID definitions.\r
+\r
+Copyright (c) 2013-2015 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+**/\r
+\r
+#ifndef __COMMON_HEADER_H_\r
+#define __COMMON_HEADER_H_\r
+\r
+\r
+\r
+#include <PiDxe.h>\r
+#include <IntelQNCDxe.h>\r
+#include <IndustryStandard/Pci22.h>\r
+\r
+#include <Guid/MdeModuleHii.h>\r
+#include <Protocol/Smbios.h>\r
+#include <Protocol/DevicePath.h>\r
+#include <Protocol/DiskInfo.h>\r
+#include <Protocol/PlatformPolicy.h>\r
+#include <Protocol/MpService.h>\r
+\r
+#include <Protocol/HiiString.h>\r
+#include <Protocol/HiiDatabase.h>\r
+#include <Protocol/HiiConfigRouting.h>\r
+#include <Protocol/HiiConfigAccess.h>\r
+\r
+#include <Protocol/IdeControllerInit.h>\r
+#include <Protocol/PciIo.h>\r
+\r
+#include <Library/BaseLib.h>\r
+#include <Library/UefiLib.h>\r
+#include <Library/UefiDriverEntryPoint.h>\r
+#include <Library/UefiBootServicesTableLib.h>\r
+#include <Library/UefiRuntimeServicesTableLib.h>\r
+#include <Library/DebugLib.h>\r
+#include <Library/S3BootScriptLib.h>\r
+#include <Library/BaseMemoryLib.h>\r
+#include <Library/HiiLib.h>\r
+#include <Library/DevicePathLib.h>\r
+#include <Library/MemoryAllocationLib.h>\r
+#include <Library/PrintLib.h>\r
+#include <Library/PcdLib.h>\r
+#include <Library/IntelQNCLib.h>\r
+#include <Library/IoLib.h>\r
+#include <Library/PciLib.h>\r
+#include <Library/S3IoLib.h>\r
+#include <Library/S3PciLib.h>\r
+#include <Library/DevicePathLib.h>\r
+\r
+#endif\r
--- /dev/null
+## @file\r
+# Component description file for DxePlatform module.\r
+#\r
+# This driver initializes platform configuration setting and installs several platform policy potocols.\r
+# Copyright (c) 2013-2015 Intel Corporation.\r
+#\r
+# This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution. The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php\r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+##\r
+\r
+[Defines]\r
+ INF_VERSION = 0x00010005\r
+ BASE_NAME = DxePlatform\r
+ FILE_GUID = DAA55048-BC3F-4dd9-999B-F58ABF2BBFCC\r
+ MODULE_TYPE = DXE_DRIVER\r
+ VERSION_STRING = 1.0\r
+ ENTRY_POINT = DxePlatformDriverEntry\r
+\r
+#\r
+# The following information is for reference only and not required by the build tools.\r
+#\r
+# VALID_ARCHITECTURES = IA32 X64 IPF EBC\r
+#\r
+\r
+[Sources]\r
+ KeyboardLayout.c\r
+ QNCRegTable.c\r
+ processor.c\r
+ SetupPlatform.c\r
+ SetupPlatform.h\r
+ Strings.uni\r
+\r
+[Packages]\r
+ MdePkg/MdePkg.dec\r
+ MdeModulePkg/MdeModulePkg.dec\r
+ QuarkPlatformPkg/QuarkPlatformPkg.dec\r
+ QuarkSocPkg/QuarkSocPkg.dec\r
+\r
+[LibraryClasses]\r
+ IoLib\r
+ IntelQNCLib\r
+ PcdLib\r
+ PrintLib\r
+ MemoryAllocationLib\r
+ BaseMemoryLib\r
+ S3BootScriptLib\r
+ DebugLib\r
+ UefiRuntimeServicesTableLib\r
+ UefiBootServicesTableLib\r
+ UefiDriverEntryPoint\r
+ BaseLib\r
+ S3IoLib\r
+ S3PciLib\r
+ HiiLib\r
+ HobLib\r
+ PciLib\r
+ UefiLib\r
+\r
+[Guids]\r
+\r
+[Protocols]\r
+ gEfiPlatformPolicyProtocolGuid # PROTOCOL ALWAYS_PRODUCED\r
+ gEfiHiiDatabaseProtocolGuid # PROTOCOL ALWAYS_CONSUMED\r
+ gEfiHiiConfigAccessProtocolGuid # PROTOCOL ALWAYS_CONSUMED\r
+ gEfiHiiConfigRoutingProtocolGuid # PROTOCOL ALWAYS_CONSUMED\r
+\r
+[Pcd]\r
+ gEfiQuarkNcSocIdTokenSpaceGuid.PcdRcbaMmioBaseAddress\r
+ gEfiQuarkNcSocIdTokenSpaceGuid.PcdQuarkAgent0IR\r
+ gEfiQuarkNcSocIdTokenSpaceGuid.PcdQuarkAgent1IR\r
+ gEfiQuarkNcSocIdTokenSpaceGuid.PcdQuarkAgent2IR\r
+ gEfiQuarkNcSocIdTokenSpaceGuid.PcdQuarkAgent3IR\r
+\r
+[Depex]\r
+ # AND EFI_SDRAM_MEMORY_SETUP_PROTOCOL_GUID AND\r
+ gEfiVariableArchProtocolGuid AND gEfiVariableWriteArchProtocolGuid AND gEfiHiiDatabaseProtocolGuid AND gPcdProtocolGuid\r
--- /dev/null
+/** @file\r
+Example code to register customized keyboard layout to HII database.\r
+\r
+Copyright (c) 2013-2015 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#include "CommonHeader.h"\r
+\r
+//\r
+// Define "`" as Non-spacing key to switch "a","u","i","o","e"\r
+//\r
+#define ENABLE_NS_KEY 1\r
+\r
+#ifdef ENABLE_NS_KEY\r
+#define KEYBOARD_KEY_COUNT (104 + 5)\r
+#else\r
+#define KEYBOARD_KEY_COUNT 104\r
+#endif\r
+\r
+#pragma pack (1)\r
+typedef struct {\r
+ //\r
+ // This 4-bytes total array length is required by PreparePackageList()\r
+ //\r
+ UINT32 Length;\r
+\r
+ //\r
+ // Keyboard Layout package definition\r
+ //\r
+ EFI_HII_PACKAGE_HEADER PackageHeader;\r
+ UINT16 LayoutCount;\r
+\r
+ //\r
+ // EFI_HII_KEYBOARD_LAYOUT\r
+ //\r
+ UINT16 LayoutLength;\r
+ EFI_GUID Guid;\r
+ UINT32 LayoutDescriptorStringOffset;\r
+ UINT8 DescriptorCount;\r
+ EFI_KEY_DESCRIPTOR KeyDescriptor[KEYBOARD_KEY_COUNT];\r
+ UINT16 DescriptionCount; // EFI_DESCRIPTION_STRING_BUNDLE\r
+ CHAR16 Language[5]; // RFC4646 Language Code: "en-US"\r
+ CHAR16 Space;\r
+ CHAR16 DescriptionString[17]; // Description: "English Keyboard"\r
+} KEYBOARD_LAYOUT_PACK_BIN;\r
+#pragma pack()\r
+\r
+#define KEYBOARD_LAYOUT_PACKAGE_GUID \\r
+ { \\r
+ 0xd66f7b7a, 0x5e06, 0x49f3, { 0xa1, 0xcf, 0x12, 0x8d, 0x4, 0x86, 0xc2, 0x7c } \\r
+ }\r
+\r
+#define KEYBOARD_LAYOUT_KEY_GUID \\r
+ { \\r
+ 0xd9db96f4, 0xff47, 0x4eb6, { 0x8a, 0x4, 0x79, 0x5b, 0x56, 0x87, 0xb, 0x4e } \\r
+ }\r
+\r
+EFI_GUID mKeyboardLayoutPackageGuid = KEYBOARD_LAYOUT_PACKAGE_GUID;\r
+EFI_GUID mKeyboardLayoutKeyGuid = KEYBOARD_LAYOUT_KEY_GUID;\r
+\r
+KEYBOARD_LAYOUT_PACK_BIN mKeyboardLayoutBin = {\r
+ sizeof (KEYBOARD_LAYOUT_PACK_BIN), // Binary size\r
+\r
+ //\r
+ // EFI_HII_PACKAGE_HEADER\r
+ //\r
+ {\r
+ sizeof (KEYBOARD_LAYOUT_PACK_BIN) - sizeof (UINT32),\r
+ EFI_HII_PACKAGE_KEYBOARD_LAYOUT\r
+ },\r
+ 1, // LayoutCount\r
+ sizeof (KEYBOARD_LAYOUT_PACK_BIN) - sizeof (UINT32) - sizeof (EFI_HII_PACKAGE_HEADER) - sizeof (UINT16), // LayoutLength\r
+ KEYBOARD_LAYOUT_KEY_GUID, // KeyGuid\r
+ sizeof (UINT16) + sizeof (EFI_GUID) + sizeof (UINT32) + sizeof (UINT8) + (KEYBOARD_KEY_COUNT * sizeof (EFI_KEY_DESCRIPTOR)), // LayoutDescriptorStringOffset\r
+ KEYBOARD_KEY_COUNT, // DescriptorCount\r
+ {\r
+ //\r
+ // EFI_KEY_DESCRIPTOR\r
+ //\r
+ {EfiKeyC1, 'a', 'A', 0, 0, EFI_NULL_MODIFIER, EFI_AFFECTED_BY_STANDARD_SHIFT | EFI_AFFECTED_BY_CAPS_LOCK},\r
+ {EfiKeyB5, 'b', 'B', 0, 0, EFI_NULL_MODIFIER, EFI_AFFECTED_BY_STANDARD_SHIFT | EFI_AFFECTED_BY_CAPS_LOCK},\r
+ {EfiKeyB3, 'c', 'C', 0, 0, EFI_NULL_MODIFIER, EFI_AFFECTED_BY_STANDARD_SHIFT | EFI_AFFECTED_BY_CAPS_LOCK},\r
+ {EfiKeyC3, 'd', 'D', 0, 0, EFI_NULL_MODIFIER, EFI_AFFECTED_BY_STANDARD_SHIFT | EFI_AFFECTED_BY_CAPS_LOCK},\r
+ {EfiKeyD3, 'e', 'E', 0, 0, EFI_NULL_MODIFIER, EFI_AFFECTED_BY_STANDARD_SHIFT | EFI_AFFECTED_BY_CAPS_LOCK},\r
+ {EfiKeyC4, 'f', 'F', 0, 0, EFI_NULL_MODIFIER, EFI_AFFECTED_BY_STANDARD_SHIFT | EFI_AFFECTED_BY_CAPS_LOCK},\r
+ {EfiKeyC5, 'g', 'G', 0, 0, EFI_NULL_MODIFIER, EFI_AFFECTED_BY_STANDARD_SHIFT | EFI_AFFECTED_BY_CAPS_LOCK},\r
+ {EfiKeyC6, 'h', 'H', 0, 0, EFI_NULL_MODIFIER, EFI_AFFECTED_BY_STANDARD_SHIFT | EFI_AFFECTED_BY_CAPS_LOCK},\r
+ {EfiKeyD8, 'i', 'I', 0, 0, EFI_NULL_MODIFIER, EFI_AFFECTED_BY_STANDARD_SHIFT | EFI_AFFECTED_BY_CAPS_LOCK},\r
+ {EfiKeyC7, 'j', 'J', 0, 0, EFI_NULL_MODIFIER, EFI_AFFECTED_BY_STANDARD_SHIFT | EFI_AFFECTED_BY_CAPS_LOCK},\r
+ {EfiKeyC8, 'k', 'K', 0, 0, EFI_NULL_MODIFIER, EFI_AFFECTED_BY_STANDARD_SHIFT | EFI_AFFECTED_BY_CAPS_LOCK},\r
+ {EfiKeyC9, 'l', 'L', 0, 0, EFI_NULL_MODIFIER, EFI_AFFECTED_BY_STANDARD_SHIFT | EFI_AFFECTED_BY_CAPS_LOCK},\r
+ {EfiKeyB7, 'm', 'M', 0, 0, EFI_NULL_MODIFIER, EFI_AFFECTED_BY_STANDARD_SHIFT | EFI_AFFECTED_BY_CAPS_LOCK},\r
+ {EfiKeyB6, 'n', 'N', 0, 0, EFI_NULL_MODIFIER, EFI_AFFECTED_BY_STANDARD_SHIFT | EFI_AFFECTED_BY_CAPS_LOCK},\r
+ {EfiKeyD9, 'o', 'O', 0, 0, EFI_NULL_MODIFIER, EFI_AFFECTED_BY_STANDARD_SHIFT | EFI_AFFECTED_BY_CAPS_LOCK},\r
+ {EfiKeyD10, 'p', 'P', 0, 0, EFI_NULL_MODIFIER, EFI_AFFECTED_BY_STANDARD_SHIFT | EFI_AFFECTED_BY_CAPS_LOCK},\r
+ {EfiKeyD1, 'q', 'Q', 0, 0, EFI_NULL_MODIFIER, EFI_AFFECTED_BY_STANDARD_SHIFT | EFI_AFFECTED_BY_CAPS_LOCK},\r
+ {EfiKeyD4, 'r', 'R', 0, 0, EFI_NULL_MODIFIER, EFI_AFFECTED_BY_STANDARD_SHIFT | EFI_AFFECTED_BY_CAPS_LOCK},\r
+ {EfiKeyC2, 's', 'S', 0, 0, EFI_NULL_MODIFIER, EFI_AFFECTED_BY_STANDARD_SHIFT | EFI_AFFECTED_BY_CAPS_LOCK},\r
+ {EfiKeyD5, 't', 'T', 0, 0, EFI_NULL_MODIFIER, EFI_AFFECTED_BY_STANDARD_SHIFT | EFI_AFFECTED_BY_CAPS_LOCK},\r
+ {EfiKeyD7, 'u', 'U', 0, 0, EFI_NULL_MODIFIER, EFI_AFFECTED_BY_STANDARD_SHIFT | EFI_AFFECTED_BY_CAPS_LOCK},\r
+ {EfiKeyB4, 'v', 'V', 0, 0, EFI_NULL_MODIFIER, EFI_AFFECTED_BY_STANDARD_SHIFT | EFI_AFFECTED_BY_CAPS_LOCK},\r
+ {EfiKeyD2, 'w', 'W', 0, 0, EFI_NULL_MODIFIER, EFI_AFFECTED_BY_STANDARD_SHIFT | EFI_AFFECTED_BY_CAPS_LOCK},\r
+ {EfiKeyB2, 'x', 'X', 0, 0, EFI_NULL_MODIFIER, EFI_AFFECTED_BY_STANDARD_SHIFT | EFI_AFFECTED_BY_CAPS_LOCK},\r
+ {EfiKeyD6, 'y', 'Y', 0, 0, EFI_NULL_MODIFIER, EFI_AFFECTED_BY_STANDARD_SHIFT | EFI_AFFECTED_BY_CAPS_LOCK},\r
+ {EfiKeyB1, 'z', 'Z', 0, 0, EFI_NULL_MODIFIER, EFI_AFFECTED_BY_STANDARD_SHIFT | EFI_AFFECTED_BY_CAPS_LOCK},\r
+ {EfiKeyE1, '1', '!', 0, 0, EFI_NULL_MODIFIER, EFI_AFFECTED_BY_STANDARD_SHIFT},\r
+ {EfiKeyE2, '2', '@', 0, 0, EFI_NULL_MODIFIER, EFI_AFFECTED_BY_STANDARD_SHIFT},\r
+ {EfiKeyE3, '3', '#', 0, 0, EFI_NULL_MODIFIER, EFI_AFFECTED_BY_STANDARD_SHIFT},\r
+ {EfiKeyE4, '4', '$', 0, 0, EFI_NULL_MODIFIER, EFI_AFFECTED_BY_STANDARD_SHIFT},\r
+ {EfiKeyE5, '5', '%', 0, 0, EFI_NULL_MODIFIER, EFI_AFFECTED_BY_STANDARD_SHIFT},\r
+ {EfiKeyE6, '6', '^', 0, 0, EFI_NULL_MODIFIER, EFI_AFFECTED_BY_STANDARD_SHIFT},\r
+ {EfiKeyE7, '7', '&', 0, 0, EFI_NULL_MODIFIER, EFI_AFFECTED_BY_STANDARD_SHIFT},\r
+ {EfiKeyE8, '8', '*', 0, 0, EFI_NULL_MODIFIER, EFI_AFFECTED_BY_STANDARD_SHIFT},\r
+ {EfiKeyE9, '9', '(', 0, 0, EFI_NULL_MODIFIER, EFI_AFFECTED_BY_STANDARD_SHIFT},\r
+ {EfiKeyE10, '0', ')', 0, 0, EFI_NULL_MODIFIER, EFI_AFFECTED_BY_STANDARD_SHIFT},\r
+ {EfiKeyEnter, 0x0d, 0x0d, 0, 0, EFI_NULL_MODIFIER, 0},\r
+ {EfiKeyEsc, 0x1b, 0x1b, 0, 0, EFI_NULL_MODIFIER, 0},\r
+ {EfiKeyBackSpace, 0x08, 0x08, 0, 0, EFI_NULL_MODIFIER, 0},\r
+ {EfiKeyTab, 0x09, 0x09, 0, 0, EFI_NULL_MODIFIER, 0},\r
+ {EfiKeySpaceBar, ' ', ' ', 0, 0, EFI_NULL_MODIFIER, 0},\r
+ {EfiKeyE11, '-', '_', 0, 0, EFI_NULL_MODIFIER, EFI_AFFECTED_BY_STANDARD_SHIFT},\r
+ {EfiKeyE12, '=', '+', 0, 0, EFI_NULL_MODIFIER, EFI_AFFECTED_BY_STANDARD_SHIFT},\r
+ {EfiKeyD11, '[', '{', 0, 0, EFI_NULL_MODIFIER, EFI_AFFECTED_BY_STANDARD_SHIFT},\r
+ {EfiKeyD12, ']', '}', 0, 0, EFI_NULL_MODIFIER, EFI_AFFECTED_BY_STANDARD_SHIFT},\r
+ {EfiKeyD13, '\\', '|', 0, 0, EFI_NULL_MODIFIER, EFI_AFFECTED_BY_STANDARD_SHIFT},\r
+ {EfiKeyC10, ';', ':', 0, 0, EFI_NULL_MODIFIER, EFI_AFFECTED_BY_STANDARD_SHIFT},\r
+ {EfiKeyC11, '\'', '"', 0, 0, EFI_NULL_MODIFIER, EFI_AFFECTED_BY_STANDARD_SHIFT},\r
+\r
+#ifdef ENABLE_NS_KEY\r
+ //\r
+ // Non-Spacing key example\r
+ //\r
+ {EfiKeyE0, 0, 0, 0, 0, EFI_NS_KEY_MODIFIER, 0},\r
+ {EfiKeyC1, 0x00E2, 0x00C2, 0, 0, EFI_NS_KEY_DEPENDENCY_MODIFIER, EFI_AFFECTED_BY_STANDARD_SHIFT | EFI_AFFECTED_BY_CAPS_LOCK},\r
+ {EfiKeyD3, 0x00EA, 0x00CA, 0, 0, EFI_NS_KEY_DEPENDENCY_MODIFIER, EFI_AFFECTED_BY_STANDARD_SHIFT | EFI_AFFECTED_BY_CAPS_LOCK},\r
+ {EfiKeyD8, 0x00EC, 0x00CC, 0, 0, EFI_NS_KEY_DEPENDENCY_MODIFIER, EFI_AFFECTED_BY_STANDARD_SHIFT | EFI_AFFECTED_BY_CAPS_LOCK},\r
+ {EfiKeyD9, 0x00F4, 0x00D4, 0, 0, EFI_NS_KEY_DEPENDENCY_MODIFIER, EFI_AFFECTED_BY_STANDARD_SHIFT | EFI_AFFECTED_BY_CAPS_LOCK},\r
+ {EfiKeyD7, 0x00FB, 0x00CB, 0, 0, EFI_NS_KEY_DEPENDENCY_MODIFIER, EFI_AFFECTED_BY_STANDARD_SHIFT | EFI_AFFECTED_BY_CAPS_LOCK},\r
+#else\r
+ {EfiKeyE0, '`', '~', 0, 0, EFI_NULL_MODIFIER, EFI_AFFECTED_BY_STANDARD_SHIFT},\r
+#endif\r
+\r
+ {EfiKeyB8, ',', '<', 0, 0, EFI_NULL_MODIFIER, EFI_AFFECTED_BY_STANDARD_SHIFT},\r
+ {EfiKeyB9, '.', '>', 0, 0, EFI_NULL_MODIFIER, EFI_AFFECTED_BY_STANDARD_SHIFT},\r
+ {EfiKeyB10, '/', '?', 0, 0, EFI_NULL_MODIFIER, EFI_AFFECTED_BY_STANDARD_SHIFT},\r
+ {EfiKeyCapsLock, 0x00, 0x00, 0, 0, EFI_CAPS_LOCK_MODIFIER, 0},\r
+ {EfiKeyF1, 0x00, 0x00, 0, 0, EFI_FUNCTION_KEY_ONE_MODIFIER, 0},\r
+ {EfiKeyF2, 0x00, 0x00, 0, 0, EFI_FUNCTION_KEY_TWO_MODIFIER, 0},\r
+ {EfiKeyF3, 0x00, 0x00, 0, 0, EFI_FUNCTION_KEY_THREE_MODIFIER, 0},\r
+ {EfiKeyF4, 0x00, 0x00, 0, 0, EFI_FUNCTION_KEY_FOUR_MODIFIER, 0},\r
+ {EfiKeyF5, 0x00, 0x00, 0, 0, EFI_FUNCTION_KEY_FIVE_MODIFIER, 0},\r
+ {EfiKeyF6, 0x00, 0x00, 0, 0, EFI_FUNCTION_KEY_SIX_MODIFIER, 0},\r
+ {EfiKeyF7, 0x00, 0x00, 0, 0, EFI_FUNCTION_KEY_SEVEN_MODIFIER, 0},\r
+ {EfiKeyF8, 0x00, 0x00, 0, 0, EFI_FUNCTION_KEY_EIGHT_MODIFIER, 0},\r
+ {EfiKeyF9, 0x00, 0x00, 0, 0, EFI_FUNCTION_KEY_NINE_MODIFIER, 0},\r
+ {EfiKeyF10, 0x00, 0x00, 0, 0, EFI_FUNCTION_KEY_TEN_MODIFIER, 0},\r
+ {EfiKeyF11, 0x00, 0x00, 0, 0, EFI_FUNCTION_KEY_ELEVEN_MODIFIER, 0},\r
+ {EfiKeyF12, 0x00, 0x00, 0, 0, EFI_FUNCTION_KEY_TWELVE_MODIFIER, 0},\r
+ {EfiKeyPrint, 0x00, 0x00, 0, 0, EFI_PRINT_MODIFIER, 0},\r
+ {EfiKeySLck, 0x00, 0x00, 0, 0, EFI_SCROLL_LOCK_MODIFIER, 0},\r
+ {EfiKeyPause, 0x00, 0x00, 0, 0, EFI_PAUSE_MODIFIER, 0},\r
+ {EfiKeyIns, 0x00, 0x00, 0, 0, EFI_INSERT_MODIFIER, 0},\r
+ {EfiKeyHome, 0x00, 0x00, 0, 0, EFI_HOME_MODIFIER, 0},\r
+ {EfiKeyPgUp, 0x00, 0x00, 0, 0, EFI_PAGE_UP_MODIFIER, 0},\r
+ {EfiKeyDel, 0x00, 0x00, 0, 0, EFI_DELETE_MODIFIER, 0},\r
+ {EfiKeyEnd, 0x00, 0x00, 0, 0, EFI_END_MODIFIER, 0},\r
+ {EfiKeyPgDn, 0x00, 0x00, 0, 0, EFI_PAGE_DOWN_MODIFIER, 0},\r
+ {EfiKeyRightArrow, 0x00, 0x00, 0, 0, EFI_RIGHT_ARROW_MODIFIER, 0},\r
+ {EfiKeyLeftArrow, 0x00, 0x00, 0, 0, EFI_LEFT_ARROW_MODIFIER, 0},\r
+ {EfiKeyDownArrow, 0x00, 0x00, 0, 0, EFI_DOWN_ARROW_MODIFIER, 0},\r
+ {EfiKeyUpArrow, 0x00, 0x00, 0, 0, EFI_UP_ARROW_MODIFIER, 0},\r
+ {EfiKeyNLck, 0x00, 0x00, 0, 0, EFI_NUM_LOCK_MODIFIER, 0},\r
+ {EfiKeySlash, '/', '/', 0, 0, EFI_NULL_MODIFIER, 0},\r
+ {EfiKeyAsterisk, '*', '*', 0, 0, EFI_NULL_MODIFIER, 0},\r
+ {EfiKeyMinus, '-', '-', 0, 0, EFI_NULL_MODIFIER, 0},\r
+ {EfiKeyPlus, '+', '+', 0, 0, EFI_NULL_MODIFIER, 0},\r
+ {EfiKeyEnter, 0x0d, 0x0d, 0, 0, EFI_NULL_MODIFIER, 0},\r
+ {EfiKeyOne, '1', '1', 0, 0, EFI_END_MODIFIER, EFI_AFFECTED_BY_STANDARD_SHIFT | EFI_AFFECTED_BY_NUM_LOCK},\r
+ {EfiKeyTwo, '2', '2', 0, 0, EFI_DOWN_ARROW_MODIFIER, EFI_AFFECTED_BY_STANDARD_SHIFT | EFI_AFFECTED_BY_NUM_LOCK},\r
+ {EfiKeyThree, '3', '3', 0, 0, EFI_PAGE_DOWN_MODIFIER, EFI_AFFECTED_BY_STANDARD_SHIFT | EFI_AFFECTED_BY_NUM_LOCK},\r
+ {EfiKeyFour, '4', '4', 0, 0, EFI_LEFT_ARROW_MODIFIER, EFI_AFFECTED_BY_STANDARD_SHIFT | EFI_AFFECTED_BY_NUM_LOCK},\r
+ {EfiKeyFive, '5', '5', 0, 0, EFI_NULL_MODIFIER, EFI_AFFECTED_BY_STANDARD_SHIFT | EFI_AFFECTED_BY_NUM_LOCK},\r
+ {EfiKeySix, '6', '6', 0, 0, EFI_RIGHT_ARROW_MODIFIER, EFI_AFFECTED_BY_STANDARD_SHIFT | EFI_AFFECTED_BY_NUM_LOCK},\r
+ {EfiKeySeven, '7', '7', 0, 0, EFI_HOME_MODIFIER, EFI_AFFECTED_BY_STANDARD_SHIFT | EFI_AFFECTED_BY_NUM_LOCK},\r
+ {EfiKeyEight, '8', '8', 0, 0, EFI_UP_ARROW_MODIFIER, EFI_AFFECTED_BY_STANDARD_SHIFT | EFI_AFFECTED_BY_NUM_LOCK},\r
+ {EfiKeyNine, '9', '9', 0, 0, EFI_PAGE_UP_MODIFIER, EFI_AFFECTED_BY_STANDARD_SHIFT | EFI_AFFECTED_BY_NUM_LOCK},\r
+ {EfiKeyZero, '0', '0', 0, 0, EFI_INSERT_MODIFIER, EFI_AFFECTED_BY_STANDARD_SHIFT | EFI_AFFECTED_BY_NUM_LOCK},\r
+ {EfiKeyPeriod, '.', '.', 0, 0, EFI_DELETE_MODIFIER, EFI_AFFECTED_BY_STANDARD_SHIFT | EFI_AFFECTED_BY_NUM_LOCK},\r
+ {EfiKeyA4, 0x00, 0x00, 0, 0, EFI_MENU_MODIFIER, 0},\r
+ {EfiKeyLCtrl, 0, 0, 0, 0, EFI_LEFT_CONTROL_MODIFIER, 0},\r
+ {EfiKeyLShift, 0, 0, 0, 0, EFI_LEFT_SHIFT_MODIFIER, 0},\r
+ {EfiKeyLAlt, 0, 0, 0, 0, EFI_LEFT_ALT_MODIFIER, 0},\r
+ {EfiKeyA0, 0, 0, 0, 0, EFI_LEFT_LOGO_MODIFIER, 0},\r
+ {EfiKeyRCtrl, 0, 0, 0, 0, EFI_RIGHT_CONTROL_MODIFIER, 0},\r
+ {EfiKeyRShift, 0, 0, 0, 0, EFI_RIGHT_SHIFT_MODIFIER, 0},\r
+ {EfiKeyA2, 0, 0, 0, 0, EFI_RIGHT_ALT_MODIFIER, 0},\r
+ {EfiKeyA3, 0, 0, 0, 0, EFI_RIGHT_LOGO_MODIFIER, 0},\r
+ },\r
+ 1, // DescriptionCount\r
+ {'e', 'n', '-', 'U', 'S'}, // RFC4646 language code\r
+ ' ', // Space\r
+ {'E', 'n', 'g', 'l', 'i', 's', 'h', ' ', 'K', 'e', 'y', 'b', 'o', 'a', 'r', 'd', '\0'}, // DescriptionString[17]\r
+};\r
+\r
+extern EFI_HANDLE mImageHandle;\r
+\r
+EFI_STATUS\r
+InitKeyboardLayout (\r
+ VOID\r
+ )\r
+/*++\r
+\r
+ Routine Description:\r
+ Install keyboard layout package and set current keyboard layout.\r
+\r
+ Arguments:\r
+ None.\r
+\r
+ Returns:\r
+ EFI_STATUS\r
+\r
+--*/\r
+{\r
+ EFI_STATUS Status;\r
+ EFI_HII_DATABASE_PROTOCOL *HiiDatabase;\r
+ EFI_HII_HANDLE HiiHandle;\r
+\r
+ //\r
+ // Locate Hii database protocol\r
+ //\r
+ Status = gBS->LocateProtocol (\r
+ &gEfiHiiDatabaseProtocolGuid,\r
+ NULL,\r
+ (VOID**)&HiiDatabase\r
+ );\r
+ if (EFI_ERROR (Status)) {\r
+ return Status;\r
+ }\r
+\r
+ //\r
+ // Install Keyboard Layout package to HII database\r
+ //\r
+ HiiHandle = HiiAddPackages (\r
+ &mKeyboardLayoutPackageGuid,\r
+ mImageHandle,\r
+ &mKeyboardLayoutBin,\r
+ NULL\r
+ );\r
+ if (HiiHandle == NULL) {\r
+ return EFI_OUT_OF_RESOURCES;\r
+ }\r
+\r
+ //\r
+ // Set current keyboard layout\r
+ //\r
+ Status = HiiDatabase->SetKeyboardLayout (HiiDatabase, &mKeyboardLayoutKeyGuid);\r
+\r
+ return Status;\r
+}\r
--- /dev/null
+/** @file\r
+Register initialization table for Ich.\r
+\r
+Copyright (c) 2013-2015 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+**/\r
+\r
+\r
+#include "CommonHeader.h"\r
+\r
+VOID\r
+PlatformInitQNCRegs (\r
+ VOID\r
+ )\r
+{\r
+ //\r
+ // All devices on bus 0.\r
+ // Device 0:\r
+ // FNC 0: Host Bridge\r
+ // Device 20:\r
+ // FNC 0: IOSF2AHB Bridge\r
+ // Device 21:\r
+ // FNC 0: IOSF2AHB Bridge\r
+ // Device 23:\r
+ // FNC 0: PCIe Port 0\r
+ // Device 24:\r
+ // FNC 0: PCIe Port 1\r
+\r
+ // Device 31:\r
+ // FNC 0: PCI-LPC Bridge\r
+ //\r
+ S3PciWrite32 (PCI_LIB_ADDRESS (PCI_BUS_NUMBER_QNC, PCI_DEVICE_NUMBER_QNC_LPC, PCI_FUNCTION_NUMBER_QNC_LPC, R_QNC_LPC_FWH_BIOS_DEC),\r
+ B_QNC_LPC_FWH_BIOS_DEC_F0 | B_QNC_LPC_FWH_BIOS_DEC_F8 |\r
+ B_QNC_LPC_FWH_BIOS_DEC_E0 | B_QNC_LPC_FWH_BIOS_DEC_E8 |\r
+ B_QNC_LPC_FWH_BIOS_DEC_D0 | B_QNC_LPC_FWH_BIOS_DEC_D8 |\r
+ B_QNC_LPC_FWH_BIOS_DEC_C0 | B_QNC_LPC_FWH_BIOS_DEC_C8\r
+ );\r
+\r
+ //\r
+ // Program SCI Interrupt for IRQ9\r
+ //\r
+ S3PciWrite8 (PCI_LIB_ADDRESS (PCI_BUS_NUMBER_QNC, PCI_DEVICE_NUMBER_QNC_LPC, PCI_FUNCTION_NUMBER_QNC_LPC, R_QNC_LPC_ACTL),\r
+ V_QNC_LPC_ACTL_SCIS_IRQ9\r
+ );\r
+\r
+ //\r
+ // Program Quark Interrupt Route Registers\r
+ //\r
+ S3MmioWrite16 ((UINTN)PcdGet64(PcdRcbaMmioBaseAddress) + R_QNC_RCRB_AGENT0IR,\r
+ PcdGet16(PcdQuarkAgent0IR)\r
+ );\r
+ S3MmioWrite16 ((UINTN)PcdGet64(PcdRcbaMmioBaseAddress) + R_QNC_RCRB_AGENT1IR,\r
+ PcdGet16(PcdQuarkAgent1IR)\r
+ );\r
+ S3MmioWrite16 ((UINTN)PcdGet64(PcdRcbaMmioBaseAddress) + R_QNC_RCRB_AGENT2IR,\r
+ PcdGet16(PcdQuarkAgent2IR)\r
+ );\r
+ S3MmioWrite16 ((UINTN)PcdGet64(PcdRcbaMmioBaseAddress) + R_QNC_RCRB_AGENT3IR,\r
+ PcdGet16(PcdQuarkAgent3IR)\r
+ );\r
+\r
+ //\r
+ // Program SVID and SID for QNC PCI devices. In order to boost performance, we\r
+ // combine two 16 bit PCI_WRITE into one 32 bit PCI_WRITE. The programmed LPC SVID\r
+ // will reflect on all internal devices's SVID registers\r
+ //\r
+ S3PciWrite32 (PCI_LIB_ADDRESS (PCI_BUS_NUMBER_QNC, PCI_DEVICE_NUMBER_QNC_LPC, PCI_FUNCTION_NUMBER_QNC_LPC, R_EFI_PCI_SVID),\r
+ (UINT32)(V_INTEL_VENDOR_ID + (QUARK_V_LPC_DEVICE_ID_0 << 16))\r
+ );\r
+\r
+ //\r
+ // Write once on Element Self Description Register before OS boot\r
+ //\r
+ QNCMmio32And (PcdGet64(PcdRcbaMmioBaseAddress), 0x04, 0xFF00FFFF);\r
+\r
+ return;\r
+}\r
--- /dev/null
+/** @file\r
+Platform Initialization Driver.\r
+\r
+Copyright (c) 2013-2015 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#include "CommonHeader.h"\r
+\r
+#include "SetupPlatform.h"\r
+#include <Library/HobLib.h>\r
+\r
+EFI_HANDLE mImageHandle = NULL;\r
+\r
+EFI_HII_DATABASE_PROTOCOL *mHiiDataBase = NULL;\r
+EFI_HII_CONFIG_ROUTING_PROTOCOL *mHiiConfigRouting = NULL;\r
+\r
+UINT8 mSmbusRsvdAddresses[PLATFORM_NUM_SMBUS_RSVD_ADDRESSES] = {\r
+ SMBUS_ADDR_CH_A_1,\r
+ SMBUS_ADDR_CK505,\r
+ SMBUS_ADDR_THERMAL_SENSOR1,\r
+ SMBUS_ADDR_THERMAL_SENSOR2\r
+};\r
+\r
+EFI_PLATFORM_POLICY_PROTOCOL mPlatformPolicyData = {\r
+ PLATFORM_NUM_SMBUS_RSVD_ADDRESSES,\r
+ mSmbusRsvdAddresses\r
+};\r
+\r
+EFI_STATUS\r
+DxePlatformDriverEntry (\r
+ IN EFI_HANDLE ImageHandle,\r
+ IN EFI_SYSTEM_TABLE *SystemTable\r
+ )\r
+/*++\r
+\r
+ Routine Description:\r
+ This is the standard EFI driver point for the D845GRgPlatform Driver. This\r
+ driver is responsible for setting up any platform specific policy or\r
+ initialization information.\r
+\r
+ Arguments:\r
+ ImageHandle - Handle for the image of this driver\r
+ SystemTable - Pointer to the EFI System Table\r
+\r
+ Returns:\r
+ EFI_SUCCESS - Policy decisions set\r
+\r
+--*/\r
+{\r
+ EFI_STATUS Status;\r
+ EFI_HANDLE Handle;\r
+\r
+ S3BootScriptSaveInformationAsciiString (\r
+ "SetupDxeEntryBegin"\r
+ );\r
+\r
+ mImageHandle = ImageHandle;\r
+\r
+ Status = gBS->LocateProtocol (&gEfiHiiDatabaseProtocolGuid, NULL, (VOID**)&mHiiDataBase);\r
+ ASSERT_EFI_ERROR (Status);\r
+\r
+ Status = gBS->LocateProtocol (&gEfiHiiConfigRoutingProtocolGuid, NULL, (VOID**)&mHiiConfigRouting);\r
+ ASSERT_EFI_ERROR (Status);\r
+\r
+ //\r
+ // Initialize keyboard layout\r
+ //\r
+ Status = InitKeyboardLayout ();\r
+\r
+ //\r
+ // Initialize ICH registers\r
+ //\r
+ PlatformInitQNCRegs();\r
+\r
+ ProducePlatformCpuData ();\r
+\r
+ //\r
+ // Install protocol to to allow access to this Policy.\r
+ //\r
+ Handle = NULL;\r
+ Status = gBS->InstallMultipleProtocolInterfaces (\r
+ &Handle,\r
+ &gEfiPlatformPolicyProtocolGuid, &mPlatformPolicyData,\r
+ NULL\r
+ );\r
+ ASSERT_EFI_ERROR(Status);\r
+\r
+ S3BootScriptSaveInformationAsciiString (\r
+ "SetupDxeEntryEnd"\r
+ );\r
+\r
+ return EFI_SUCCESS;\r
+}\r
+\r
--- /dev/null
+/** @file\r
+Header file for Platform Initialization Driver.\r
+\r
+Copyright (c) 2013-2015 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#ifndef _SETUP_PLATFORM_H\r
+#define _SETUP_PLATFORM_H\r
+\r
+//\r
+// Data\r
+//\r
+#define PLATFORM_NUM_SMBUS_RSVD_ADDRESSES 4\r
+#define VAR_OFFSET(Field) ((UINT16) ((UINTN) &(((SYSTEM_CONFIGURATION *) 0)->Field)))\r
+#define QUESTION_ID(Field) (VAR_OFFSET (Field) + 1)\r
+\r
+#define SMBUS_ADDR_CH_A_1 0xA0\r
+#define SMBUS_ADDR_CK505 0xD2\r
+#define SMBUS_ADDR_THERMAL_SENSOR1 0x4C\r
+#define SMBUS_ADDR_THERMAL_SENSOR2 0x4D\r
+\r
+///\r
+/// HII specific Vendor Device Path Node definition.\r
+///\r
+#pragma pack(1)\r
+\r
+typedef struct {\r
+ VENDOR_DEVICE_PATH VendorDevicePath;\r
+ UINT16 UniqueId;\r
+} HII_VENDOR_DEVICE_PATH_NODE;\r
+\r
+///\r
+/// HII specific Vendor Device Path definition.\r
+///\r
+typedef struct {\r
+ HII_VENDOR_DEVICE_PATH_NODE Node;\r
+ EFI_DEVICE_PATH_PROTOCOL End;\r
+} HII_VENDOR_DEVICE_PATH;\r
+\r
+#pragma pack()\r
+\r
+//\r
+// Prototypes\r
+//\r
+VOID\r
+ProducePlatformCpuData (\r
+ VOID\r
+ );\r
+\r
+VOID\r
+PlatformInitQNCRegs (\r
+ VOID\r
+ );\r
+\r
+EFI_STATUS\r
+InitKeyboardLayout (\r
+ VOID\r
+ );\r
+\r
+//\r
+// Global externs\r
+//\r
+extern UINT8 UefiSetupDxeStrings[];\r
+\r
+extern EFI_HII_DATABASE_PROTOCOL *mHiiDataBase;\r
+extern EFI_HII_CONFIG_ROUTING_PROTOCOL *mHiiConfigRouting;\r
+\r
+#endif\r
--- /dev/null
+// /** @file\r
+// String definitions for Sample Setup formset.\r
+//\r
+// Copyright (c) 2013-2015 Intel Corporation.\r
+//\r
+// This program and the accompanying materials\r
+// are licensed and made available under the terms and conditions of the BSD License\r
+// which accompanies this distribution. The full text of the license may be found at\r
+// http://opensource.org/licenses/bsd-license.php\r
+//\r
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+//\r
+//\r
+// **/\r
+\r
+/=#\r
+\r
+#langdef en-US "English"\r
+#langdef fr-FR "Français"\r
+#langdef es-ES "Español"\r
+\r
+#string STR_LGA775 #language en-US "L775"\r
+#string STR_LGA775 #language fr-FR "L775"\r
+#string STR_LGA775 #language es-ES "L775"\r
+\r
+\r
+// Enable or Disable\r
+#string STR_ENABLE #language en-US "Enable"\r
+#string STR_ENABLE #language fr-FR "Activé"\r
+#string STR_ENABLE #language es-ES "Activada"\r
+\r
+#string STR_DISABLE #language en-US "Disable"\r
+#string STR_DISABLE #language fr-FR "Désactivé"\r
+#string STR_DISABLE #language es-ES "Desactivada"\r
+\r
+#string STR_AUTO #language en-US "Auto"\r
+#string STR_AUTO #language fr-FR "Auto"\r
+#string STR_AUTO #language es-ES "Auto"\r
+\r
+// Unknown\r
+#string STR_UNKNOWN #language en-US "Unknown"\r
+#string STR_UNKNOWN #language fr-FR "Unknown"\r
+#string STR_UNKNOWN #language es-ES "Unknown"\r
+\r
+\r
+// NULL String\r
+#string STR_NULL_STRING #language en-US ""\r
+\r
+#string STR_VAR_TOTAL_MEMORY_SIZE #language en-US "54"\r
+\r
+#string VAR_EQ_CONFIG_MODE_NAME #language en-US "67"\r
+// End of file\r
--- /dev/null
+/** @file\r
+Platform CPU Data\r
+\r
+Copyright (c) 2013-2015 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+\r
+#include "CommonHeader.h"\r
+\r
+#include "SetupPlatform.h"\r
+\r
+\r
+#define NUMBER_OF_PACKAGES 1\r
+\r
+CHAR16 *SocketNames[NUMBER_OF_PACKAGES];\r
+CHAR16 *AssetTags[NUMBER_OF_PACKAGES];\r
+\r
+CHAR16 EmptyString[] = L" ";\r
+CHAR16 SocketString[] = L"LGA775";\r
+\r
+VOID\r
+ProducePlatformCpuData (\r
+ VOID\r
+ )\r
+{\r
+ UINTN Index;\r
+\r
+ for (Index = 0; Index < NUMBER_OF_PACKAGES; Index++) {\r
+\r
+ //\r
+ // The String Package of a module is registered together with all IFR packages.\r
+ // So we just arbitrarily pick a package GUID that is always installed to get the string.\r
+ //\r
+ AssetTags[Index] = EmptyString;\r
+ SocketNames[Index] = SocketString;\r
+ }\r
+}\r
--- /dev/null
+/** @file\r
+Common header file shared by all source files.\r
+\r
+This file includes package header files, library classes and protocol, PPI & GUID definitions.\r
+\r
+Copyright (c) 2013-2015 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+**/\r
+\r
+#ifndef __COMMON_HEADER_H_\r
+#define __COMMON_HEADER_H_\r
+\r
+\r
+\r
+#include <FrameworkDxe.h>\r
+#include <IndustryStandard/SmBios.h>\r
+#include <Protocol/Smbios.h>\r
+#include <Guid/MdeModuleHii.h>\r
+#include <Guid/DataHubRecords.h>\r
+\r
+#include <Library/UefiDriverEntryPoint.h>\r
+#include <Library/UefiBootServicesTableLib.h>\r
+#include <Library/DebugLib.h>\r
+#include <Library/BaseLib.h>\r
+#include <Library/BaseMemoryLib.h>\r
+#include <Library/DevicePathLib.h>\r
+#include <Library/MemoryAllocationLib.h>\r
+#include <Library/HiiLib.h>\r
+#include <Library/PcdLib.h>\r
+#include <Library/UefiLib.h>\r
+\r
+extern EFI_HII_HANDLE gHiiHandle;\r
+#endif\r
--- /dev/null
+// /** @file\r
+// System Manufacturer Information\r
+//\r
+// Copyright (c) 2013-2015 Intel Corporation.\r
+//\r
+// This program and the accompanying materials\r
+// are licensed and made available under the terms and conditions of the BSD License\r
+// which accompanies this distribution. The full text of the license may be found at\r
+// http://opensource.org/licenses/bsd-license.php\r
+//\r
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+//\r
+//\r
+// **/\r
+\r
+/=#\r
+\r
+#string STR_MISC_BASE_BOARD_MANUFACTURER #language en-US "Intel Corp."\r
+#string STR_MISC_BASE_BOARD_PRODUCT_NAME #language en-US "QUARK"\r
+#string STR_MISC_BASE_BOARD_VERSION #language en-US "FAB-D"\r
+#string STR_MISC_BASE_BOARD_SERIAL_NUMBER #language en-US "XXXXXXXXXXXX"\r
+#string STR_MISC_BASE_BOARD_ASSET_TAG #language en-US "Base Board Asset Tag"\r
+#string STR_MISC_BASE_BOARD_CHASSIS_LOCATION #language en-US "Part Component"\r
+\r
--- /dev/null
+/** @file\r
+Type 2: Base Board Information.\r
+\r
+Copyright (c) 2013-2015 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+\r
+#include "CommonHeader.h"\r
+#include "SmbiosMisc.h"\r
+\r
+//\r
+// Static (possibly build generated) Bios Vendor data.\r
+//\r
+MISC_SMBIOS_TABLE_DATA(EFI_MISC_BASE_BOARD_MANUFACTURER_DATA, MiscBaseBoardManufacturer)\r
+= {\r
+ STRING_TOKEN(STR_MISC_BASE_BOARD_MANUFACTURER),\r
+ STRING_TOKEN(STR_MISC_BASE_BOARD_PRODUCT_NAME),\r
+ STRING_TOKEN(STR_MISC_BASE_BOARD_VERSION),\r
+ STRING_TOKEN(STR_MISC_BASE_BOARD_SERIAL_NUMBER),\r
+ STRING_TOKEN(STR_MISC_BASE_BOARD_ASSET_TAG),\r
+ STRING_TOKEN(STR_MISC_BASE_BOARD_CHASSIS_LOCATION),\r
+ { // BaseBoardFeatureFlags\r
+ 1, // Motherboard\r
+ 0, // RequiresDaughterCard\r
+ 0, // Removable\r
+ 1, // Replaceable,\r
+ 0, // HotSwappable\r
+ 0, // Reserved\r
+ },\r
+ EfiBaseBoardTypeUnknown, // BaseBoardType\r
+ { // BaseBoardChassisLink\r
+ EFI_MISC_SUBCLASS_GUID, // ProducerName\r
+ 1, // Instance\r
+ 1, // SubInstance\r
+ },\r
+ 0, // BaseBoardNumberLinks\r
+ { // LinkN\r
+ EFI_MISC_SUBCLASS_GUID, // ProducerName\r
+ 1, // Instance\r
+ 1, // SubInstance\r
+ },\r
+};\r
--- /dev/null
+/** @file\r
+Base Board Information boot time changes.\r
+Misc. subclass type 4.\r
+SMBIOS type 2.\r
+\r
+Copyright (c) 2013-2015 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+\r
+#include "CommonHeader.h"\r
+#include "SmbiosMisc.h"\r
+\r
+/**\r
+ This function makes boot time changes to the contents of the\r
+ MiscBaseBoardManufacturer (Type 2).\r
+\r
+ @param RecordData Pointer to copy of RecordData from the Data Table.\r
+\r
+ @retval EFI_SUCCESS All parameters were valid.\r
+ @retval EFI_UNSUPPORTED Unexpected RecordType value.\r
+ @retval EFI_INVALID_PARAMETER Invalid parameter was found.\r
+\r
+**/\r
+MISC_SMBIOS_TABLE_FUNCTION(MiscBaseBoardManufacturer)\r
+{\r
+ CHAR8 *OptionalStrStart;\r
+ UINTN ManuStrLen;\r
+ UINTN ProductStrLen;\r
+ UINTN VerStrLen;\r
+ UINTN AssertTagStrLen;\r
+ UINTN SerialNumStrLen;\r
+ UINTN ChassisStrLen;\r
+ EFI_STATUS Status;\r
+ EFI_STRING Manufacturer;\r
+ EFI_STRING Product;\r
+ EFI_STRING Version;\r
+ EFI_STRING SerialNumber;\r
+ EFI_STRING AssertTag;\r
+ EFI_STRING Chassis;\r
+ STRING_REF TokenToGet;\r
+ STRING_REF TokenToUpdate;\r
+ EFI_SMBIOS_HANDLE SmbiosHandle;\r
+ SMBIOS_TABLE_TYPE2 *SmbiosRecord;\r
+ EFI_MISC_BASE_BOARD_MANUFACTURER *ForType2InputData;\r
+ UINTN TypeStringSize;\r
+ CHAR16 TypeString[SMBIOS_STRING_MAX_LENGTH];\r
+\r
+ ForType2InputData = (EFI_MISC_BASE_BOARD_MANUFACTURER *)RecordData;\r
+\r
+ //\r
+ // First check for invalid parameters.\r
+ //\r
+ if (RecordData == NULL) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+\r
+ TokenToGet = STRING_TOKEN (STR_MISC_BASE_BOARD_MANUFACTURER);\r
+ Manufacturer = HiiGetPackageString(&gEfiCallerIdGuid, TokenToGet, NULL);\r
+ ManuStrLen = StrLen(Manufacturer);\r
+ if (ManuStrLen > SMBIOS_STRING_MAX_LENGTH) {\r
+ return EFI_UNSUPPORTED;\r
+ }\r
+\r
+ StrCpy (TypeString, L"");\r
+ TypeStringSize = PcdGetSize (PcdPlatformTypeName);\r
+ if (TypeStringSize > 0 && TypeStringSize <= sizeof (TypeString)) {\r
+ CopyMem (TypeString, PcdGetPtr (PcdPlatformTypeName), TypeStringSize);\r
+ }\r
+ if (StrLen (TypeString) == 0) {\r
+ StrCpy (TypeString, L"Unknown");\r
+ }\r
+ TokenToUpdate = STRING_TOKEN (STR_MISC_BASE_BOARD_PRODUCT_NAME);\r
+ HiiSetString (mHiiHandle, TokenToUpdate, TypeString, NULL);\r
+\r
+ TokenToGet = STRING_TOKEN (STR_MISC_BASE_BOARD_PRODUCT_NAME);\r
+ Product = HiiGetPackageString(&gEfiCallerIdGuid, TokenToGet, NULL);\r
+ ProductStrLen = StrLen(TypeString);\r
+ if (ProductStrLen > SMBIOS_STRING_MAX_LENGTH) {\r
+ return EFI_UNSUPPORTED;\r
+ }\r
+\r
+ TokenToGet = STRING_TOKEN (STR_MISC_BASE_BOARD_VERSION);\r
+ Version = HiiGetPackageString(&gEfiCallerIdGuid, TokenToGet, NULL);\r
+ VerStrLen = StrLen(Version);\r
+ if (VerStrLen > SMBIOS_STRING_MAX_LENGTH) {\r
+ return EFI_UNSUPPORTED;\r
+ }\r
+\r
+ TokenToGet = STRING_TOKEN (STR_MISC_BASE_BOARD_SERIAL_NUMBER);\r
+ SerialNumber = HiiGetPackageString(&gEfiCallerIdGuid, TokenToGet, NULL);\r
+ SerialNumStrLen = StrLen(SerialNumber);\r
+ if (SerialNumStrLen > SMBIOS_STRING_MAX_LENGTH) {\r
+ return EFI_UNSUPPORTED;\r
+ }\r
+\r
+ TokenToGet = STRING_TOKEN (STR_MISC_BASE_BOARD_ASSET_TAG);\r
+ AssertTag = HiiGetPackageString(&gEfiCallerIdGuid, TokenToGet, NULL);\r
+ AssertTagStrLen = StrLen(AssertTag);\r
+ if (AssertTagStrLen > SMBIOS_STRING_MAX_LENGTH) {\r
+ return EFI_UNSUPPORTED;\r
+ }\r
+\r
+ TokenToGet = STRING_TOKEN (STR_MISC_BASE_BOARD_CHASSIS_LOCATION);\r
+ Chassis = HiiGetPackageString(&gEfiCallerIdGuid, TokenToGet, NULL);\r
+ ChassisStrLen = StrLen(Chassis);\r
+ if (ChassisStrLen > SMBIOS_STRING_MAX_LENGTH) {\r
+ return EFI_UNSUPPORTED;\r
+ }\r
+\r
+\r
+ //\r
+ // Two zeros following the last string.\r
+ //\r
+ SmbiosRecord = AllocatePool(sizeof (SMBIOS_TABLE_TYPE3) + ManuStrLen + 1 + ProductStrLen + 1 + VerStrLen + 1 + SerialNumStrLen + 1 + AssertTagStrLen + 1 + ChassisStrLen +1 + 1);\r
+ ZeroMem(SmbiosRecord, sizeof (SMBIOS_TABLE_TYPE3) + ManuStrLen + 1 + ProductStrLen + 1 + VerStrLen + 1 + SerialNumStrLen + 1 + AssertTagStrLen + 1 + ChassisStrLen +1 + 1);\r
+\r
+ SmbiosRecord->Hdr.Type = EFI_SMBIOS_TYPE_BASEBOARD_INFORMATION;\r
+ SmbiosRecord->Hdr.Length = sizeof (SMBIOS_TABLE_TYPE2);\r
+ //\r
+ // Make handle chosen by smbios protocol.add automatically.\r
+ //\r
+ SmbiosRecord->Hdr.Handle = 0;\r
+ //\r
+ // Manu will be the 1st optional string following the formatted structure.\r
+ //\r
+ SmbiosRecord->Manufacturer = 1;\r
+ //\r
+ // ProductName will be the 2st optional string following the formatted structure.\r
+ //\r
+ SmbiosRecord->ProductName = 2;\r
+ //\r
+ // Version will be the 3rd optional string following the formatted structure.\r
+ //\r
+ SmbiosRecord->Version = 3;\r
+ //\r
+ // SerialNumber will be the 4th optional string following the formatted structure.\r
+ //\r
+ SmbiosRecord->SerialNumber = 4;\r
+ //\r
+ // AssertTag will be the 5th optional string following the formatted structure.\r
+ //\r
+ SmbiosRecord->AssetTag = 5;\r
+\r
+ //\r
+ // LocationInChassis will be the 6th optional string following the formatted structure.\r
+ //\r
+ SmbiosRecord->LocationInChassis = 6;\r
+ SmbiosRecord->FeatureFlag = (*(BASE_BOARD_FEATURE_FLAGS*)&(ForType2InputData->BaseBoardFeatureFlags));\r
+ SmbiosRecord->ChassisHandle = 0;\r
+ SmbiosRecord->BoardType = (UINT8)ForType2InputData->BaseBoardType;\r
+ SmbiosRecord->NumberOfContainedObjectHandles = 0;\r
+\r
+ OptionalStrStart = (CHAR8 *)(SmbiosRecord + 1);\r
+ //\r
+ // Since we fill NumberOfContainedObjectHandles = 0 for simple, just after this filed to fill string\r
+ //\r
+ //OptionalStrStart -= 2;\r
+ UnicodeStrToAsciiStr(Manufacturer, OptionalStrStart);\r
+ UnicodeStrToAsciiStr(Product, OptionalStrStart + ManuStrLen + 1);\r
+ UnicodeStrToAsciiStr(Version, OptionalStrStart + ManuStrLen + 1 + ProductStrLen + 1);\r
+ UnicodeStrToAsciiStr(SerialNumber, OptionalStrStart + ManuStrLen + 1 + ProductStrLen + 1 + VerStrLen + 1);\r
+ UnicodeStrToAsciiStr(AssertTag, OptionalStrStart + ManuStrLen + 1 + ProductStrLen + 1 + VerStrLen + 1 + SerialNumStrLen + 1);\r
+ UnicodeStrToAsciiStr(Chassis, OptionalStrStart + ManuStrLen + 1 + ProductStrLen + 1 + VerStrLen + 1 + SerialNumStrLen + 1 + AssertTagStrLen + 1);\r
+\r
+ //\r
+ // Now we have got the full smbios record, call smbios protocol to add this record.\r
+ //\r
+ SmbiosHandle = SMBIOS_HANDLE_PI_RESERVED;\r
+ Status = Smbios-> Add(\r
+ Smbios,\r
+ NULL,\r
+ &SmbiosHandle,\r
+ (EFI_SMBIOS_TABLE_HEADER *) SmbiosRecord\r
+ );\r
+\r
+ FreePool(SmbiosRecord);\r
+ return Status;\r
+}\r
--- /dev/null
+// /** @file\r
+// BIOS vendor information.\r
+// Misc. subclass type 2.\r
+// SMBIOS type 0.\r
+//\r
+// Copyright (c) 2013-2015 Intel Corporation.\r
+//\r
+// This program and the accompanying materials\r
+// are licensed and made available under the terms and conditions of the BSD License\r
+// which accompanies this distribution. The full text of the license may be found at\r
+// http://opensource.org/licenses/bsd-license.php\r
+//\r
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+//\r
+//\r
+// **/\r
+\r
+\r
+/=#\r
+\r
+#string STR_MISC_BIOS_VENDOR #language en-US "Intel Corp."\r
+#string STR_MISC_BIOS_VERSION #language en-US "BIOS Version"\r
+#string STR_MISC_BIOS_RELEASE_DATE #language en-US "11/03/2015"\r
--- /dev/null
+/** @file\r
+BIOS vendor information static data.\r
+Misc. subclass type 2.\r
+SMBIOS type 0.\r
+\r
+Copyright (c) 2013-2015 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+**/\r
+\r
+\r
+#include "CommonHeader.h"\r
+\r
+#include "SmbiosMisc.h"\r
+\r
+\r
+//\r
+// Static (possibly build generated) Bios Vendor data.\r
+//\r
+MISC_SMBIOS_TABLE_DATA(EFI_MISC_BIOS_VENDOR, MiscBiosVendor) = {\r
+ STRING_TOKEN (STR_MISC_BIOS_VENDOR), // BiosVendor\r
+ STRING_TOKEN (STR_MISC_BIOS_VERSION), // BiosVersion\r
+ STRING_TOKEN (STR_MISC_BIOS_RELEASE_DATE), // BiosReleaseDate\r
+ 0xE0000, // BiosStartingAddress\r
+ { // BiosPhysicalDeviceSize\r
+ 2, // Value\r
+ 20, // Exponent\r
+ },\r
+ { // BiosCharacteristics1\r
+ 0, // Reserved1 :2\r
+ 0, // Unknown :1\r
+ 0, // BiosCharacteristicsNotSupported :1\r
+ 0, // IsaIsSupported :1\r
+ 0, // McaIsSupported :1\r
+\r
+ 0, // EisaIsSupported :1\r
+ 1, // PciIsSupported :1\r
+ 0, // PcmciaIsSupported :1\r
+ 0, // PlugAndPlayIsSupported :1\r
+ 0, // ApmIsSupported :1\r
+\r
+ 1, // BiosIsUpgradable :1\r
+ 1, // BiosShadowingAllowed :1\r
+ 0, // VlVesaIsSupported :1\r
+ 0, // EscdSupportIsAvailable :1\r
+ 1, // BootFromCdIsSupported :1\r
+\r
+ 1, // SelectableBootIsSupported :1\r
+ 0, // RomBiosIsSocketed :1\r
+ 0, // BootFromPcmciaIsSupported :1\r
+ 1, // EDDSpecificationIsSupported :1\r
+ 0, // JapaneseNecFloppyIsSupported :1\r
+\r
+ 0, // JapaneseToshibaFloppyIsSupported :1\r
+ 0, // Floppy525_360IsSupported :1\r
+ 0, // Floppy525_12IsSupported :1\r
+ 0, // Floppy35_720IsSupported :1\r
+ 0, // Floppy35_288IsSupported :1\r
+\r
+ 1, // PrintScreenIsSupported :1\r
+ 1, // Keyboard8042IsSupported :1\r
+ 1, // SerialIsSupported :1\r
+ 1, // PrinterIsSupported :1\r
+ 1, // CgaMonoIsSupported :1\r
+\r
+ 0, // NecPc98 :1\r
+ 1, // AcpiIsSupported :1\r
+ 1, // UsbLegacyIsSupported :1\r
+ 0, // AgpIsSupported :1\r
+ 0, // I20BootIsSupported :1\r
+\r
+ 0, // Ls120BootIsSupported :1\r
+ 0, // AtapiZipDriveBootIsSupported :1\r
+ 0, // Boot1394IsSupported :1\r
+ 0, // SmartBatteryIsSupported :1\r
+ 1, // BiosBootSpecIsSupported :1\r
+\r
+ 1, // FunctionKeyNetworkBootIsSupported :1\r
+ 0 // Reserved :22\r
+ },\r
+ { // BiosCharacteristics2\r
+ 0, // BiosReserved :16\r
+ 0, // SystemReserved :16\r
+ 0 // Reserved :32\r
+ },\r
+ 0x1, // System BIOS Major Release\r
+ 0x0, // System BIOS Minor Release\r
+ 0xFF, // Embedded controller firmware major Release\r
+ 0xFF, // Embedded controller firmware minor Release\r
+};\r
--- /dev/null
+/** @file\r
+BIOS vendor information boot time changes.\r
+Misc. subclass type 2.\r
+SMBIOS type 0.\r
+\r
+Copyright (c) 2013-2015 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+**/\r
+\r
+\r
+#include "CommonHeader.h"\r
+\r
+#include "SmbiosMisc.h"\r
+\r
+/**\r
+ This function returns the value & exponent to Base2 for a given\r
+ Hex value. This is used to calculate the BiosPhysicalDeviceSize.\r
+\r
+ @param Value The hex value which is to be converted into value-exponent form\r
+ @param Exponent The exponent out of the conversion\r
+\r
+ @retval EFI_SUCCESS All parameters were valid and *Value & *Exponent have been set.\r
+ @retval EFI_INVALID_PARAMETER Invalid parameter was found.\r
+\r
+**/\r
+EFI_STATUS\r
+GetValueExponentBase2(\r
+ IN OUT UINTN *Value,\r
+ OUT UINTN *Exponent\r
+ )\r
+{\r
+ if ((Value == NULL) || (Exponent == NULL)) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+\r
+ while ((*Value % 2) == 0) {\r
+ *Value=*Value/2;\r
+ (*Exponent)++;\r
+ }\r
+\r
+ return EFI_SUCCESS;\r
+}\r
+\r
+/**\r
+ Field Filling Function. Transform an EFI_EXP_BASE2_DATA to a byte, with '64k'\r
+ as the unit.\r
+\r
+ @param Base2Data Pointer to Base2_Data\r
+\r
+ @retval EFI_SUCCESS Transform successfully.\r
+ @retval EFI_INVALID_PARAMETER Invalid parameter was found.\r
+\r
+**/\r
+UINT16\r
+Base2ToByteWith64KUnit (\r
+ IN EFI_EXP_BASE2_DATA *Base2Data\r
+ )\r
+{\r
+ UINT16 Value;\r
+ UINT16 Exponent;\r
+\r
+ Value = Base2Data->Value;\r
+ Exponent = Base2Data->Exponent;\r
+ Exponent -= 16;\r
+ Value <<= Exponent;\r
+\r
+ return Value;\r
+}\r
+\r
+\r
+/**\r
+ This function makes boot time changes to the contents of the\r
+ MiscBiosVendor (Type 0).\r
+\r
+ @param RecordData Pointer to copy of RecordData from the Data Table.\r
+\r
+ @retval EFI_SUCCESS All parameters were valid.\r
+ @retval EFI_UNSUPPORTED Unexpected RecordType value.\r
+ @retval EFI_INVALID_PARAMETER Invalid parameter was found.\r
+\r
+**/\r
+MISC_SMBIOS_TABLE_FUNCTION(MiscBiosVendor)\r
+{\r
+ CHAR8 *OptionalStrStart;\r
+ UINTN VendorStrLen;\r
+ UINTN VerStrLen;\r
+ UINTN DateStrLen;\r
+ UINTN BiosPhysicalSizeHexValue;\r
+ UINTN BiosPhysicalSizeExponent;\r
+ CHAR16 Version[SMBIOS_STRING_MAX_LENGTH];\r
+ CHAR16 Vendor[SMBIOS_STRING_MAX_LENGTH];\r
+ CHAR16 ReleaseDate[SMBIOS_STRING_MAX_LENGTH];\r
+ EFI_STRING VersionPtr;\r
+ EFI_STRING VendorPtr;\r
+ EFI_STRING ReleaseDatePtr;\r
+ EFI_STATUS Status;\r
+ STRING_REF TokenToGet;\r
+ STRING_REF TokenToUpdate;\r
+ SMBIOS_TABLE_TYPE0 *SmbiosRecord;\r
+ EFI_SMBIOS_HANDLE SmbiosHandle;\r
+ EFI_MISC_BIOS_VENDOR *ForType0InputData;\r
+\r
+ BiosPhysicalSizeHexValue = 0x0;\r
+ BiosPhysicalSizeExponent = 0x0;\r
+ ForType0InputData = (EFI_MISC_BIOS_VENDOR *)RecordData;\r
+\r
+ //\r
+ // First check for invalid parameters.\r
+ //\r
+ if (RecordData == NULL) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+ //\r
+ // Now update the BiosPhysicalSize\r
+ //\r
+ BiosPhysicalSizeHexValue = PcdGet32 (PcdFlashAreaSize);\r
+ Status= GetValueExponentBase2 (\r
+ &BiosPhysicalSizeHexValue,\r
+ &BiosPhysicalSizeExponent\r
+ );\r
+ if(Status == EFI_SUCCESS){\r
+ ForType0InputData->BiosPhysicalDeviceSize.Value = (UINT16)BiosPhysicalSizeHexValue;\r
+ ForType0InputData->BiosPhysicalDeviceSize.Exponent = (UINT16)BiosPhysicalSizeExponent;\r
+ }\r
+ //\r
+ // Update strings from PCD\r
+ //\r
+ AsciiStrToUnicodeStr ((CHAR8 *) PcdGetPtr (PcdSMBIOSBiosVendor), Vendor);\r
+ if (StrLen (Vendor) > 0) {\r
+ TokenToUpdate = STRING_TOKEN (STR_MISC_BIOS_VENDOR);\r
+ HiiSetString (mHiiHandle, TokenToUpdate, Vendor, NULL);\r
+ }\r
+ TokenToGet = STRING_TOKEN (STR_MISC_BIOS_VENDOR);\r
+ VendorPtr = HiiGetPackageString(&gEfiCallerIdGuid, TokenToGet, NULL);\r
+ VendorStrLen = StrLen(VendorPtr);\r
+ if (VendorStrLen > SMBIOS_STRING_MAX_LENGTH) {\r
+ return EFI_UNSUPPORTED;\r
+ }\r
+\r
+ UnicodeSPrint (Version, sizeof (Version), L"0x%08x", PcdGet32 (PcdFirmwareRevision));\r
+ if (StrLen (Version) > 0) {\r
+ TokenToUpdate = STRING_TOKEN (STR_MISC_BIOS_VERSION);\r
+ HiiSetString (mHiiHandle, TokenToUpdate, Version, NULL);\r
+ }\r
+ TokenToGet = STRING_TOKEN (STR_MISC_BIOS_VERSION);\r
+ VersionPtr = HiiGetPackageString(&gEfiCallerIdGuid, TokenToGet, NULL);\r
+ VerStrLen = StrLen(VersionPtr);\r
+ if (VerStrLen > SMBIOS_STRING_MAX_LENGTH) {\r
+ return EFI_UNSUPPORTED;\r
+ }\r
+\r
+ AsciiStrToUnicodeStr ((CHAR8 *) PcdGetPtr (PcdSMBIOSBiosReleaseDate), ReleaseDate);\r
+ if (StrLen (ReleaseDate) > 0) {\r
+ TokenToUpdate = STRING_TOKEN (STR_MISC_BIOS_RELEASE_DATE);\r
+ HiiSetString (mHiiHandle, TokenToUpdate, ReleaseDate, NULL);\r
+ }\r
+ TokenToGet = STRING_TOKEN (STR_MISC_BIOS_RELEASE_DATE);\r
+ ReleaseDatePtr = HiiGetPackageString(&gEfiCallerIdGuid, TokenToGet, NULL);\r
+ DateStrLen = StrLen(ReleaseDatePtr);\r
+ if (DateStrLen > SMBIOS_STRING_MAX_LENGTH) {\r
+ return EFI_UNSUPPORTED;\r
+ }\r
+\r
+ //\r
+ // Two zeros following the last string.\r
+ //\r
+ SmbiosRecord = AllocatePool(sizeof (SMBIOS_TABLE_TYPE0) + VendorStrLen + 1 + VerStrLen + 1 + DateStrLen + 1 + 1);\r
+ ZeroMem(SmbiosRecord, sizeof (SMBIOS_TABLE_TYPE0) + VendorStrLen + 1 + VerStrLen + 1 + DateStrLen + 1 + 1);\r
+\r
+ SmbiosRecord->Hdr.Type = EFI_SMBIOS_TYPE_BIOS_INFORMATION;\r
+ SmbiosRecord->Hdr.Length = sizeof (SMBIOS_TABLE_TYPE0);\r
+ //\r
+ // Make handle chosen by smbios protocol.add automatically.\r
+ //\r
+ SmbiosRecord->Hdr.Handle = 0;\r
+ //\r
+ // Vendor will be the 1st optional string following the formatted structure.\r
+ //\r
+ SmbiosRecord->Vendor = 1;\r
+ //\r
+ // Version will be the 2nd optional string following the formatted structure.\r
+ //\r
+ SmbiosRecord->BiosVersion = 2;\r
+ SmbiosRecord->BiosSegment = PcdGet16 (PcdSMBIOSBiosStartAddress);\r
+ //\r
+ // ReleaseDate will be the 3rd optional string following the formatted structure.\r
+ //\r
+ SmbiosRecord->BiosReleaseDate = 3;\r
+ SmbiosRecord->BiosSize = (UINT8)(Base2ToByteWith64KUnit(&ForType0InputData->BiosPhysicalDeviceSize) - 1);\r
+ *(UINT64 *)&SmbiosRecord->BiosCharacteristics = PcdGet64 (PcdSMBIOSBiosChar);\r
+ //\r
+ // CharacterExtensionBytes also store in ForType0InputData->BiosCharacteristics1 later two bytes to save size.\r
+ //\r
+ SmbiosRecord->BIOSCharacteristicsExtensionBytes[0] = PcdGet8 (PcdSMBIOSBiosCharEx1);\r
+ SmbiosRecord->BIOSCharacteristicsExtensionBytes[1] = PcdGet8 (PcdSMBIOSBiosCharEx2);\r
+\r
+ SmbiosRecord->SystemBiosMajorRelease = ForType0InputData->BiosMajorRelease;\r
+ SmbiosRecord->SystemBiosMinorRelease = ForType0InputData->BiosMinorRelease;\r
+ SmbiosRecord->EmbeddedControllerFirmwareMajorRelease = ForType0InputData->BiosEmbeddedFirmwareMajorRelease;\r
+ SmbiosRecord->EmbeddedControllerFirmwareMinorRelease = ForType0InputData->BiosEmbeddedFirmwareMinorRelease;\r
+\r
+ OptionalStrStart = (CHAR8 *)(SmbiosRecord + 1);\r
+ UnicodeStrToAsciiStr(VendorPtr, OptionalStrStart);\r
+ UnicodeStrToAsciiStr(VersionPtr, OptionalStrStart + VendorStrLen + 1);\r
+ UnicodeStrToAsciiStr(ReleaseDatePtr, OptionalStrStart + VendorStrLen + 1 + VerStrLen + 1);\r
+ //\r
+ // Now we have got the full smbios record, call smbios protocol to add this record.\r
+ //\r
+ SmbiosHandle = SMBIOS_HANDLE_PI_RESERVED;\r
+ Status = Smbios-> Add(\r
+ Smbios,\r
+ NULL,\r
+ &SmbiosHandle,\r
+ (EFI_SMBIOS_TABLE_HEADER *) SmbiosRecord\r
+ );\r
+\r
+ FreePool(SmbiosRecord);\r
+ return Status;\r
+}\r
--- /dev/null
+/** @file\r
+This driver parses the mMiscSubclassDataTable structure and reports\r
+any generated data to the DataHub.\r
+\r
+Copyright (c) 2013-2015 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+**/\r
+\r
+\r
+#include "CommonHeader.h"\r
+\r
+#include "SmbiosMisc.h"\r
+\r
+\r
+//\r
+// Static (possibly build generated) Bios Vendor data. SMBIOS TYPE 32\r
+//\r
+MISC_SMBIOS_TABLE_DATA(EFI_MISC_BOOT_INFORMATION_STATUS, MiscBootInfoStatus) = {\r
+ EfiBootInformationStatusNoError, // BootInformationStatus\r
+ {0} // BootInformationData\r
+};\r
--- /dev/null
+/** @file\r
+boot information boot time changes.\r
+SMBIOS type 32.\r
+\r
+Copyright (c) 2013-2015 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+**/\r
+\r
+\r
+#include "CommonHeader.h"\r
+#include "SmbiosMisc.h"\r
+\r
+\r
+/**\r
+ This function makes boot time changes to the contents of the\r
+ MiscBootInformation (Type 32).\r
+\r
+ @param RecordData Pointer to copy of RecordData from the Data Table.\r
+\r
+ @retval EFI_SUCCESS All parameters were valid.\r
+ @retval EFI_UNSUPPORTED Unexpected RecordType value.\r
+ @retval EFI_INVALID_PARAMETER Invalid parameter was found.\r
+\r
+**/\r
+\r
+MISC_SMBIOS_TABLE_FUNCTION(MiscBootInfoStatus)\r
+{\r
+ EFI_STATUS Status;\r
+ EFI_SMBIOS_HANDLE SmbiosHandle;\r
+ SMBIOS_TABLE_TYPE32 *SmbiosRecord;\r
+ EFI_MISC_BOOT_INFORMATION_STATUS* ForType32InputData;\r
+\r
+ ForType32InputData = (EFI_MISC_BOOT_INFORMATION_STATUS *)RecordData;\r
+\r
+ //\r
+ // First check for invalid parameters.\r
+ //\r
+ if (RecordData == NULL) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+\r
+ //\r
+ // Two zeros following the last string.\r
+ //\r
+ SmbiosRecord = AllocatePool(sizeof (SMBIOS_TABLE_TYPE32) + 1 + 1);\r
+ ZeroMem(SmbiosRecord, sizeof (SMBIOS_TABLE_TYPE32) + 1 + 1);\r
+\r
+ SmbiosRecord->Hdr.Type = EFI_SMBIOS_TYPE_SYSTEM_BOOT_INFORMATION;\r
+ SmbiosRecord->Hdr.Length = sizeof (SMBIOS_TABLE_TYPE32);\r
+ //\r
+ // Make handle chosen by smbios protocol.add automatically.\r
+ //\r
+ SmbiosRecord->Hdr.Handle = 0;\r
+ SmbiosRecord->BootStatus = (UINT8)ForType32InputData->BootInformationStatus;\r
+\r
+ //\r
+ // Now we have got the full smbios record, call smbios protocol to add this record.\r
+ //\r
+ SmbiosHandle = SMBIOS_HANDLE_PI_RESERVED;\r
+ Status = Smbios-> Add(\r
+ Smbios,\r
+ NULL,\r
+ &SmbiosHandle,\r
+ (EFI_SMBIOS_TABLE_HEADER *) SmbiosRecord\r
+ );\r
+ FreePool(SmbiosRecord);\r
+ return Status;\r
+}\r
--- /dev/null
+// /** @file\r
+// Miscellaneous chassis manufacturer information\r
+//\r
+// Copyright (c) 2013-2015 Intel Corporation.\r
+//\r
+// This program and the accompanying materials\r
+// are licensed and made available under the terms and conditions of the BSD License\r
+// which accompanies this distribution. The full text of the license may be found at\r
+// http://opensource.org/licenses/bsd-license.php\r
+//\r
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+//\r
+//\r
+// **/\r
+\r
+\r
+/=#\r
+\r
+#string STR_MISC_CHASSIS_MANUFACTURER #language en-US "Chassis Manufacturer"\r
+#string STR_MISC_CHASSIS_VERSION #language en-US "Chassis Version"\r
+#string STR_MISC_CHASSIS_SERIAL_NUMBER #language en-US "Chassis Serial Number"\r
+#string STR_MISC_CHASSIS_ASSET_TAG #language en-US "Chassis Asset Tag"\r
--- /dev/null
+/** @file\r
+This driver parses the mMiscSubclassDataTable structure and reports\r
+any generated data to the DataHub.\r
+\r
+Copyright (c) 2013-2015 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+**/\r
+\r
+\r
+#include "CommonHeader.h"\r
+\r
+#include "SmbiosMisc.h"\r
+\r
+\r
+//\r
+// Static (possibly build generated) Chassis Manufacturer data.\r
+//\r
+MISC_SMBIOS_TABLE_DATA(EFI_MISC_CHASSIS_MANUFACTURER, MiscChassisManufacturer) = {\r
+ STRING_TOKEN(STR_MISC_CHASSIS_MANUFACTURER), // ChassisManufactrurer\r
+ STRING_TOKEN(STR_MISC_CHASSIS_VERSION), // ChassisVersion\r
+ STRING_TOKEN(STR_MISC_CHASSIS_SERIAL_NUMBER), // ChassisSerialNumber\r
+ STRING_TOKEN(STR_MISC_CHASSIS_ASSET_TAG), // ChassisAssetTag\r
+ { // ChassisTypeStatus\r
+ EfiMiscChassisTypeDeskTop, // ChassisType\r
+ 0, // ChassisLockPresent\r
+ 0 // Reserved\r
+ },\r
+ EfiChassisStateSafe, // ChassisBootupState\r
+ EfiChassisStateSafe, // ChassisPowerSupplyState\r
+ EfiChassisStateOther, // ChassisThermalState\r
+ EfiChassisSecurityStatusOther, // ChassisSecurityState\r
+ 0 // ChassisOemDefined\r
+};\r
--- /dev/null
+/** @file\r
+Chassis manufacturer information boot time changes.\r
+SMBIOS type 3.\r
+\r
+Copyright (c) 2013-2015 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+**/\r
+\r
+\r
+#include "CommonHeader.h"\r
+\r
+#include "SmbiosMisc.h"\r
+\r
+/**\r
+ This function makes boot time changes to the contents of the\r
+ MiscChassisManufacturer (Type 3).\r
+\r
+ @param RecordData Pointer to copy of RecordData from the Data Table.\r
+\r
+ @retval EFI_SUCCESS All parameters were valid.\r
+ @retval EFI_UNSUPPORTED Unexpected RecordType value.\r
+ @retval EFI_INVALID_PARAMETER Invalid parameter was found.\r
+\r
+**/\r
+MISC_SMBIOS_TABLE_FUNCTION(MiscChassisManufacturer)\r
+{\r
+ CHAR8 *OptionalStrStart;\r
+ UINTN ManuStrLen;\r
+ UINTN VerStrLen;\r
+ UINTN AssertTagStrLen;\r
+ UINTN SerialNumStrLen;\r
+ EFI_STATUS Status;\r
+ CHAR16 Manufacturer[SMBIOS_STRING_MAX_LENGTH];\r
+ CHAR16 Version[SMBIOS_STRING_MAX_LENGTH];\r
+ CHAR16 SerialNumber[SMBIOS_STRING_MAX_LENGTH];\r
+ CHAR16 AssertTag[SMBIOS_STRING_MAX_LENGTH];\r
+ EFI_STRING ManufacturerPtr;\r
+ EFI_STRING VersionPtr;\r
+ EFI_STRING SerialNumberPtr;\r
+ EFI_STRING AssertTagPtr;\r
+ STRING_REF TokenToGet;\r
+ STRING_REF TokenToUpdate;\r
+ EFI_SMBIOS_HANDLE SmbiosHandle;\r
+ SMBIOS_TABLE_TYPE3 *SmbiosRecord;\r
+ EFI_MISC_CHASSIS_MANUFACTURER *ForType3InputData;\r
+\r
+ ForType3InputData = (EFI_MISC_CHASSIS_MANUFACTURER *)RecordData;\r
+\r
+ //\r
+ // First check for invalid parameters.\r
+ //\r
+ if (RecordData == NULL) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+\r
+ //\r
+ // Update strings from PCD\r
+ //\r
+ AsciiStrToUnicodeStr ((CHAR8 *) PcdGetPtr(PcdSMBIOSChassisManufacturer), Manufacturer);\r
+ if (StrLen (Manufacturer) > 0) {\r
+ TokenToUpdate = STRING_TOKEN (STR_MISC_CHASSIS_MANUFACTURER);\r
+ HiiSetString (mHiiHandle, TokenToUpdate, Manufacturer, NULL);\r
+ }\r
+ TokenToGet = STRING_TOKEN (STR_MISC_CHASSIS_MANUFACTURER);\r
+ ManufacturerPtr = HiiGetPackageString(&gEfiCallerIdGuid, TokenToGet, NULL);\r
+ ManuStrLen = StrLen(ManufacturerPtr);\r
+ if (ManuStrLen > SMBIOS_STRING_MAX_LENGTH) {\r
+ return EFI_UNSUPPORTED;\r
+ }\r
+\r
+ AsciiStrToUnicodeStr ((CHAR8 *) PcdGetPtr(PcdSMBIOSChassisVersion), Version);\r
+ if (StrLen (Version) > 0) {\r
+ TokenToUpdate = STRING_TOKEN (STR_MISC_CHASSIS_VERSION);\r
+ HiiSetString (mHiiHandle, TokenToUpdate, Version, NULL);\r
+ }\r
+ TokenToGet = STRING_TOKEN (STR_MISC_CHASSIS_VERSION);\r
+ VersionPtr = HiiGetPackageString(&gEfiCallerIdGuid, TokenToGet, NULL);\r
+ VerStrLen = StrLen(VersionPtr);\r
+ if (VerStrLen > SMBIOS_STRING_MAX_LENGTH) {\r
+ return EFI_UNSUPPORTED;\r
+ }\r
+\r
+ AsciiStrToUnicodeStr ((CHAR8 *) PcdGetPtr(PcdSMBIOSChassisSerialNumber), SerialNumber);\r
+ if (StrLen (SerialNumber) > 0) {\r
+ TokenToUpdate = STRING_TOKEN (STR_MISC_CHASSIS_SERIAL_NUMBER);\r
+ HiiSetString (mHiiHandle, TokenToUpdate, SerialNumber, NULL);\r
+ }\r
+ TokenToGet = STRING_TOKEN (STR_MISC_CHASSIS_SERIAL_NUMBER);\r
+ SerialNumberPtr = HiiGetPackageString(&gEfiCallerIdGuid, TokenToGet, NULL);\r
+ SerialNumStrLen = StrLen(SerialNumberPtr);\r
+ if (SerialNumStrLen > SMBIOS_STRING_MAX_LENGTH) {\r
+ return EFI_UNSUPPORTED;\r
+ }\r
+\r
+ AsciiStrToUnicodeStr ((CHAR8 *) PcdGetPtr(PcdSMBIOSChassisAssetTag), AssertTag);\r
+ if (StrLen (AssertTag) > 0) {\r
+ TokenToUpdate = STRING_TOKEN (STR_MISC_CHASSIS_ASSET_TAG);\r
+ HiiSetString (mHiiHandle, TokenToUpdate, AssertTag, NULL);\r
+ }\r
+ TokenToGet = STRING_TOKEN (STR_MISC_CHASSIS_ASSET_TAG);\r
+ AssertTagPtr = HiiGetPackageString(&gEfiCallerIdGuid, TokenToGet, NULL);\r
+ AssertTagStrLen = StrLen(AssertTagPtr);\r
+ if (AssertTagStrLen > SMBIOS_STRING_MAX_LENGTH) {\r
+ return EFI_UNSUPPORTED;\r
+ }\r
+\r
+ //\r
+ // Two zeros following the last string.\r
+ //\r
+ SmbiosRecord = AllocatePool(sizeof (SMBIOS_TABLE_TYPE3) + ManuStrLen + 1 + VerStrLen + 1 + SerialNumStrLen + 1 + AssertTagStrLen + 1 + 1);\r
+ ZeroMem(SmbiosRecord, sizeof (SMBIOS_TABLE_TYPE3) + ManuStrLen + 1 + VerStrLen + 1 + SerialNumStrLen + 1 + AssertTagStrLen + 1 + 1);\r
+\r
+ SmbiosRecord->Hdr.Type = EFI_SMBIOS_TYPE_SYSTEM_ENCLOSURE;\r
+ SmbiosRecord->Hdr.Length = sizeof (SMBIOS_TABLE_TYPE3);\r
+ //\r
+ // Make handle chosen by smbios protocol.add automatically.\r
+ //\r
+ SmbiosRecord->Hdr.Handle = 0;\r
+ //\r
+ // Manu will be the 1st optional string following the formatted structure.\r
+ //\r
+ SmbiosRecord->Manufacturer = 1;\r
+ SmbiosRecord->Type = PcdGet8 (PcdSMBIOSChassisType);\r
+ //\r
+ // Version will be the 2nd optional string following the formatted structure.\r
+ //\r
+ SmbiosRecord->Version = 2;\r
+ //\r
+ // SerialNumber will be the 3rd optional string following the formatted structure.\r
+ //\r
+ SmbiosRecord->SerialNumber = 3;\r
+ //\r
+ // AssertTag will be the 4th optional string following the formatted structure.\r
+ //\r
+ SmbiosRecord->AssetTag = 4;\r
+ SmbiosRecord->BootupState = PcdGet8 (PcdSMBIOSChassisBootupState);\r
+ SmbiosRecord->PowerSupplyState = PcdGet8 (PcdSMBIOSChassisPowerSupplyState);\r
+ SmbiosRecord->ThermalState = (UINT8)ForType3InputData->ChassisThermalState;\r
+ SmbiosRecord->SecurityStatus = PcdGet8 (PcdSMBIOSChassisSecurityState);\r
+ *(UINT32 *)&SmbiosRecord->OemDefined = PcdGet32 (PcdSMBIOSChassisOemDefined);\r
+ SmbiosRecord->Height = PcdGet8 (PcdSMBIOSChassisHeight);\r
+ SmbiosRecord->NumberofPowerCords = PcdGet8 (PcdSMBIOSChassisNumberPowerCords);\r
+ SmbiosRecord->ContainedElementCount = PcdGet8 (PcdSMBIOSChassisElementCount);\r
+ SmbiosRecord->ContainedElementRecordLength = PcdGet8 (PcdSMBIOSChassisElementRecordLength);\r
+\r
+ OptionalStrStart = (CHAR8 *)(SmbiosRecord + 1);\r
+ UnicodeStrToAsciiStr(ManufacturerPtr, OptionalStrStart);\r
+ UnicodeStrToAsciiStr(VersionPtr, OptionalStrStart + ManuStrLen + 1);\r
+ UnicodeStrToAsciiStr(SerialNumberPtr, OptionalStrStart + ManuStrLen + 1 + VerStrLen + 1);\r
+ UnicodeStrToAsciiStr(AssertTagPtr, OptionalStrStart + ManuStrLen + 1 + VerStrLen + 1 + SerialNumStrLen + 1);\r
+\r
+ //\r
+ // Now we have got the full smbios record, call smbios protocol to add this record.\r
+ //\r
+ SmbiosHandle = SMBIOS_HANDLE_PI_RESERVED;\r
+ Status = Smbios-> Add(\r
+ Smbios,\r
+ NULL,\r
+ &SmbiosHandle,\r
+ (EFI_SMBIOS_TABLE_HEADER *) SmbiosRecord\r
+ );\r
+\r
+ FreePool(SmbiosRecord);\r
+ return Status;\r
+}\r
--- /dev/null
+/** @file\r
+Misc class required EFI Device Path definitions (Ports, slots &\r
+onboard devices)\r
+\r
+Copyright (c) 2013-2015 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+**/\r
+\r
+#ifndef _MISC_DEVICE_PATH_H\r
+#define _MISC_DEVICE_PATH_H\r
+\r
+#pragma pack(1)\r
+\r
+//USB\r
+/* For reference:\r
+#define USB1_1_STR "ACPI(PNP0A03,0)/PCI(1D,0)."\r
+#define USB1_2_STR "ACPI(PNP0A03,0)/PCI(1D,1)."\r
+#define USB1_3_STR "ACPI(PNP0A03,0)/PCI(1D,2)."\r
+#define USB2_1_STR "ACPI(PNP0A03,0)/PCI(1D,7)."\r
+*/\r
+\r
+#define DP_ACPI { ACPI_DEVICE_PATH,\\r
+ ACPI_DP, (UINT8) (sizeof (ACPI_HID_DEVICE_PATH)),\\r
+ (UINT8) ((sizeof (ACPI_HID_DEVICE_PATH)) >> 8), EISA_PNP_ID(0x0A03), 0 }\r
+#define DP_PCI( device,function) { HARDWARE_DEVICE_PATH,\\r
+ HW_PCI_DP, (UINT8) (sizeof (PCI_DEVICE_PATH)),\\r
+ (UINT8) ((sizeof (PCI_DEVICE_PATH)) >> 8), function, device }\r
+#define DP_END { END_DEVICE_PATH_TYPE, \\r
+ END_ENTIRE_DEVICE_PATH_SUBTYPE, {END_DEVICE_PATH_LENGTH, 0 }}\r
+\r
+#define DP_LPC(eisaid,function ){ ACPI_DEVICE_PATH, \\r
+ACPI_DP,(UINT8) (sizeof (ACPI_HID_DEVICE_PATH)),\\r
+(UINT8) ((sizeof (ACPI_HID_DEVICE_PATH)) >> 8),EISA_PNP_ID(eisaid), function }\r
+\r
+\r
+#pragma pack()\r
+\r
+\r
+#endif\r
--- /dev/null
+/** @file\r
+This driver parses the mSmbiosMiscDataTable structure and reports\r
+any generated data to SMBIOS.\r
+\r
+Copyright (c) 2013-2015 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+**/\r
+\r
+\r
+#include "CommonHeader.h"\r
+\r
+#include "SmbiosMisc.h"\r
+\r
+\r
+//\r
+// Static (possibly build generated) Bios Vendor data.\r
+//\r
+MISC_SMBIOS_TABLE_DATA(EFI_MISC_NUMBER_OF_INSTALLABLE_LANGUAGES, NumberOfInstallableLanguages) = {\r
+ 2, // NumberOfInstallableLanguages\r
+ { // LanguageFlags\r
+ 0, // AbbreviatedLanguageFormat\r
+ 0 // Reserved\r
+ },\r
+ 1, // CurrentLanguageNumber\r
+};\r
--- /dev/null
+/** @file\r
+This driver parses the mSmbiosMiscDataTable structure and reports\r
+any generated data.\r
+\r
+Copyright (c) 2013-2015 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+**/\r
+\r
+\r
+#include "CommonHeader.h"\r
+\r
+#include "SmbiosMisc.h"\r
+/*++\r
+ Check whether the language is supported for given HII handle\r
+\r
+ @param HiiHandle The HII package list handle.\r
+ @param Offset The offest of current lanague in the supported languages.\r
+ @param CurrentLang The language code.\r
+\r
+ @retval TRUE Supported.\r
+ @retval FALSE Not Supported.\r
+\r
+--*/\r
+BOOLEAN\r
+EFIAPI\r
+CurrentLanguageMatch (\r
+ IN EFI_HII_HANDLE HiiHandle,\r
+ OUT UINT16 *Offset,\r
+ OUT CHAR8 *CurrentLang\r
+ )\r
+{\r
+ CHAR8 *DefaultLang;\r
+ CHAR8 *BestLanguage;\r
+ CHAR8 *Languages;\r
+ CHAR8 *MatchLang;\r
+ CHAR8 *EndMatchLang;\r
+ UINTN CompareLength;\r
+ BOOLEAN LangMatch;\r
+\r
+ Languages = HiiGetSupportedLanguages (HiiHandle);\r
+ if (Languages == NULL) {\r
+ return FALSE;\r
+ }\r
+\r
+ LangMatch = FALSE;\r
+ CurrentLang = GetEfiGlobalVariable (L"PlatformLang");\r
+ DefaultLang = (CHAR8 *) PcdGetPtr (PcdUefiVariableDefaultPlatformLang);\r
+ BestLanguage = GetBestLanguage (\r
+ Languages,\r
+ FALSE,\r
+ (CurrentLang != NULL) ? CurrentLang : "",\r
+ DefaultLang,\r
+ NULL\r
+ );\r
+ if (BestLanguage != NULL) {\r
+ //\r
+ // Find the best matching RFC 4646 language, compute the offset.\r
+ //\r
+ LangMatch = TRUE;\r
+ CompareLength = AsciiStrLen (BestLanguage);\r
+ for (MatchLang = Languages, (*Offset) = 0; *MatchLang != '\0'; (*Offset)++) {\r
+ //\r
+ // Seek to the end of current match language.\r
+ //\r
+ for (EndMatchLang = MatchLang; *EndMatchLang != '\0' && *EndMatchLang != ';'; EndMatchLang++);\r
+\r
+ if ((EndMatchLang == MatchLang + CompareLength) && AsciiStrnCmp(MatchLang, BestLanguage, CompareLength) == 0) {\r
+ //\r
+ // Find the current best Language in the supported languages\r
+ //\r
+ break;\r
+ }\r
+ //\r
+ // best language match be in the supported language.\r
+ //\r
+ ASSERT (*EndMatchLang == ';');\r
+ MatchLang = EndMatchLang + 1;\r
+ }\r
+ FreePool (BestLanguage);\r
+ }\r
+\r
+ FreePool (Languages);\r
+ if (CurrentLang != NULL) {\r
+ FreePool (CurrentLang);\r
+ }\r
+ return LangMatch;\r
+}\r
+\r
+\r
+/**\r
+ Get next language from language code list (with separator ';').\r
+\r
+ @param LangCode Input: point to first language in the list. On\r
+ Otput: point to next language in the list, or\r
+ NULL if no more language in the list.\r
+ @param Lang The first language in the list.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+GetNextLanguage (\r
+ IN OUT CHAR8 **LangCode,\r
+ OUT CHAR8 *Lang\r
+ )\r
+{\r
+ UINTN Index;\r
+ CHAR8 *StringPtr;\r
+\r
+ ASSERT (LangCode != NULL);\r
+ ASSERT (*LangCode != NULL);\r
+ ASSERT (Lang != NULL);\r
+\r
+ Index = 0;\r
+ StringPtr = *LangCode;\r
+ while (StringPtr[Index] != 0 && StringPtr[Index] != ';') {\r
+ Index++;\r
+ }\r
+\r
+ CopyMem (Lang, StringPtr, Index);\r
+ Lang[Index] = 0;\r
+\r
+ if (StringPtr[Index] == ';') {\r
+ Index++;\r
+ }\r
+ *LangCode = StringPtr + Index;\r
+}\r
+\r
+/**\r
+ This function returns the number of supported languages on HiiHandle.\r
+\r
+ @param HiiHandle The HII package list handle.\r
+\r
+ @retval The number of supported languages.\r
+\r
+**/\r
+UINT16\r
+EFIAPI\r
+GetSupportedLanguageNumber (\r
+ IN EFI_HII_HANDLE HiiHandle\r
+ )\r
+{\r
+ CHAR8 *Lang;\r
+ CHAR8 *Languages;\r
+ CHAR8 *LanguageString;\r
+ UINT16 LangNumber;\r
+\r
+ Languages = HiiGetSupportedLanguages (HiiHandle);\r
+ if (Languages == NULL) {\r
+ return 0;\r
+ }\r
+\r
+ LangNumber = 0;\r
+ Lang = AllocatePool (AsciiStrSize (Languages));\r
+ if (Lang != NULL) {\r
+ LanguageString = Languages;\r
+ while (*LanguageString != 0) {\r
+ GetNextLanguage (&LanguageString, Lang);\r
+ LangNumber++;\r
+ }\r
+ FreePool (Lang);\r
+ }\r
+ FreePool (Languages);\r
+ return LangNumber;\r
+}\r
+\r
+\r
+/**\r
+ This function makes boot time changes to the contents of the\r
+ MiscNumberOfInstallableLanguages (Type 13).\r
+\r
+ @param RecordData Pointer to copy of RecordData from the Data Table.\r
+\r
+ @retval EFI_SUCCESS All parameters were valid.\r
+ @retval EFI_UNSUPPORTED Unexpected RecordType value.\r
+ @retval EFI_INVALID_PARAMETER Invalid parameter was found.\r
+\r
+**/\r
+MISC_SMBIOS_TABLE_FUNCTION(NumberOfInstallableLanguages)\r
+{\r
+ UINTN LangStrLen;\r
+ CHAR8 CurrentLang[SMBIOS_STRING_MAX_LENGTH + 1];\r
+ CHAR8 *OptionalStrStart;\r
+ UINT16 Offset;\r
+ BOOLEAN LangMatch;\r
+ EFI_STATUS Status;\r
+ EFI_SMBIOS_HANDLE SmbiosHandle;\r
+ SMBIOS_TABLE_TYPE13 *SmbiosRecord;\r
+ EFI_MISC_NUMBER_OF_INSTALLABLE_LANGUAGES *ForType13InputData;\r
+\r
+ ForType13InputData = (EFI_MISC_NUMBER_OF_INSTALLABLE_LANGUAGES *)RecordData;\r
+\r
+ //\r
+ // First check for invalid parameters.\r
+ //\r
+ if (RecordData == NULL) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+\r
+ ForType13InputData->NumberOfInstallableLanguages = GetSupportedLanguageNumber (mHiiHandle);\r
+\r
+ //\r
+ // Try to check if current langcode matches with the langcodes in installed languages\r
+ //\r
+ LangMatch = FALSE;\r
+ ZeroMem(CurrentLang, SMBIOS_STRING_MAX_LENGTH + 1);\r
+ LangMatch = CurrentLanguageMatch (mHiiHandle, &Offset, CurrentLang);\r
+ LangStrLen = AsciiStrLen(CurrentLang);\r
+\r
+ //\r
+ // Two zeros following the last string.\r
+ //\r
+ SmbiosRecord = AllocatePool(sizeof (SMBIOS_TABLE_TYPE13) + LangStrLen + 1 + 1);\r
+ ZeroMem(SmbiosRecord, sizeof (SMBIOS_TABLE_TYPE13) + LangStrLen + 1 + 1);\r
+\r
+ SmbiosRecord->Hdr.Type = EFI_SMBIOS_TYPE_BIOS_LANGUAGE_INFORMATION;\r
+ SmbiosRecord->Hdr.Length = sizeof (SMBIOS_TABLE_TYPE13);\r
+ //\r
+ // Make handle chosen by smbios protocol.add automatically.\r
+ //\r
+ SmbiosRecord->Hdr.Handle = 0;\r
+\r
+ SmbiosRecord->InstallableLanguages = (UINT8)ForType13InputData->NumberOfInstallableLanguages;\r
+ SmbiosRecord->Flags = (UINT8)ForType13InputData->LanguageFlags.AbbreviatedLanguageFormat;\r
+ SmbiosRecord->CurrentLanguages = 1;\r
+ OptionalStrStart = (CHAR8 *)(SmbiosRecord + 1);\r
+ AsciiStrCpy(OptionalStrStart, CurrentLang);\r
+ //\r
+ // Now we have got the full smbios record, call smbios protocol to add this record.\r
+ //\r
+ SmbiosHandle = SMBIOS_HANDLE_PI_RESERVED;\r
+ Status = Smbios-> Add(\r
+ Smbios,\r
+ NULL,\r
+ &SmbiosHandle,\r
+ (EFI_SMBIOS_TABLE_HEADER *) SmbiosRecord\r
+ );\r
+ FreePool(SmbiosRecord);\r
+ return Status;\r
+}\r
--- /dev/null
+// /** @file\r
+// Unicode string used for SMBIOS type 11 record (OEM string)\r
+//\r
+// Copyright (c) 2013-2015 Intel Corporation.\r
+//\r
+// This program and the accompanying materials\r
+// are licensed and made available under the terms and conditions of the BSD License\r
+// which accompanies this distribution. The full text of the license may be found at\r
+// http://opensource.org/licenses/bsd-license.php\r
+//\r
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+//\r
+// **/\r
+\r
+/=#\r
+\r
+#string STR_MISC_OEM_EN_US #language en-US "Intel SSG"\r
--- /dev/null
+/** @file\r
+This driver parses the mMiscSubclassDataTable structure and reports\r
+any generated data to smbios.\r
+\r
+Copyright (c) 2013-2015 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+\r
+#include "CommonHeader.h"\r
+\r
+#include "SmbiosMisc.h"\r
+\r
+//\r
+// Static (possibly build generated) OEM String data.\r
+//\r
+MISC_SMBIOS_TABLE_DATA(EFI_MISC_OEM_STRING, MiscOemString)\r
+= { {STRING_TOKEN(STR_MISC_OEM_EN_US) }};\r
--- /dev/null
+/** @file\r
+boot information boot time changes.\r
+SMBIOS type 11.\r
+\r
+Copyright (c) 2013-2015 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+\r
+#include "CommonHeader.h"\r
+#include "SmbiosMisc.h"\r
+\r
+/**\r
+ This function makes boot time changes to the contents of the\r
+ MiscOemString (Type 11).\r
+\r
+ @param RecordData Pointer to copy of RecordData from the Data Table.\r
+\r
+ @retval EFI_SUCCESS All parameters were valid.\r
+ @retval EFI_UNSUPPORTED Unexpected RecordType value.\r
+ @retval EFI_INVALID_PARAMETER Invalid parameter was found.\r
+\r
+**/\r
+MISC_SMBIOS_TABLE_FUNCTION(MiscOemString)\r
+{\r
+ UINTN OemStrLen;\r
+ CHAR8 *OptionalStrStart;\r
+ EFI_STATUS Status;\r
+ EFI_STRING OemStr;\r
+ STRING_REF TokenToGet;\r
+ EFI_SMBIOS_HANDLE SmbiosHandle;\r
+ SMBIOS_TABLE_TYPE11 *SmbiosRecord;\r
+ EFI_MISC_OEM_STRING *ForType11InputData;\r
+\r
+ ForType11InputData = (EFI_MISC_OEM_STRING *)RecordData;\r
+\r
+ //\r
+ // First check for invalid parameters.\r
+ //\r
+ if (RecordData == NULL) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+\r
+ TokenToGet = STRING_TOKEN (STR_MISC_OEM_EN_US);\r
+ OemStr = HiiGetPackageString(&gEfiCallerIdGuid, TokenToGet, NULL);\r
+ OemStrLen = StrLen(OemStr);\r
+ if (OemStrLen > SMBIOS_STRING_MAX_LENGTH) {\r
+ return EFI_UNSUPPORTED;\r
+ }\r
+\r
+ //\r
+ // Two zeros following the last string.\r
+ //\r
+ SmbiosRecord = AllocatePool(sizeof (SMBIOS_TABLE_TYPE11) + OemStrLen + 1 + 1);\r
+ ZeroMem(SmbiosRecord, sizeof (SMBIOS_TABLE_TYPE11) + OemStrLen + 1 + 1);\r
+\r
+ SmbiosRecord->Hdr.Type = EFI_SMBIOS_TYPE_OEM_STRINGS;\r
+ SmbiosRecord->Hdr.Length = sizeof (SMBIOS_TABLE_TYPE11);\r
+ //\r
+ // Make handle chosen by smbios protocol.add automatically.\r
+ //\r
+ SmbiosRecord->Hdr.Handle = 0;\r
+ SmbiosRecord->StringCount = 1;\r
+ OptionalStrStart = (CHAR8 *)(SmbiosRecord + 1);\r
+ UnicodeStrToAsciiStr(OemStr, OptionalStrStart);\r
+\r
+ //\r
+ // Now we have got the full smbios record, call smbios protocol to add this record.\r
+ //\r
+ SmbiosHandle = SMBIOS_HANDLE_PI_RESERVED;\r
+ Status = Smbios-> Add(\r
+ Smbios,\r
+ NULL,\r
+ &SmbiosHandle,\r
+ (EFI_SMBIOS_TABLE_HEADER *) SmbiosRecord\r
+ );\r
+ FreePool(SmbiosRecord);\r
+ return Status;\r
+}\r
--- /dev/null
+// /** @file\r
+// Miscellaneous Onboard Device\r
+//\r
+// Copyright (c) 2013-2015 Intel Corporation.\r
+//\r
+// This program and the accompanying materials\r
+// are licensed and made available under the terms and conditions of the BSD License\r
+// which accompanies this distribution. The full text of the license may be found at\r
+// http://opensource.org/licenses/bsd-license.php\r
+//\r
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+//\r
+//\r
+// MiscOnboardDevice.Vfr\r
+//\r
+// **/\r
+\r
+\r
+/=#\r
+\r
+#string STR_MISC_ONBOARD_DEVICE_VIDEO #language en-US "Intel(R) Extreme Graphics 3 Controller"\r
+#string STR_MISC_ONBOARD_DEVICE_NETWORK #language en-US "Gigabit Ethernet"\r
+#string STR_MISC_ONBOARD_DEVICE_AUDIO #language en-US "Intel(R) High Definition Audio Device"\r
--- /dev/null
+/** @file\r
+This driver parses the mMiscSubclassDataTable structure and reports\r
+any generated data to smbios.\r
+\r
+Copyright (c) 2013-2015 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+**/\r
+\r
+\r
+#include "CommonHeader.h"\r
+\r
+#include "SmbiosMisc.h"\r
+\r
+\r
+//\r
+// Static (possibly build generated) Bios Vendor data.\r
+//\r
+MISC_SMBIOS_TABLE_DATA(EFI_MISC_ONBOARD_DEVICE, MiscOnboardDeviceVideo) = {\r
+ STRING_TOKEN(STR_MISC_ONBOARD_DEVICE_VIDEO), // OnBoardDeviceDescription\r
+ { // OnBoardDeviceStatus\r
+ EfiOnBoardDeviceTypeVideo, // DeviceType\r
+ 1, // DeviceEnabled\r
+ 0 // Reserved\r
+ },\r
+ {0} // OnBoardDevicePath\r
+};\r
+\r
+MISC_SMBIOS_TABLE_DATA(EFI_MISC_ONBOARD_DEVICE, MiscOnboardDeviceNetwork) = {\r
+ STRING_TOKEN(STR_MISC_ONBOARD_DEVICE_NETWORK), // OnBoardDeviceDescription\r
+ { // OnBoardDeviceStatus\r
+ EfiOnBoardDeviceTypeEthernet, // DeviceType\r
+ 1, // DeviceEnabled\r
+ 0 // Reserved\r
+ },\r
+ {0} // OnBoardDevicePath\r
+};\r
+\r
+MISC_SMBIOS_TABLE_DATA(EFI_MISC_ONBOARD_DEVICE, MiscOnboardDeviceAudio) = {\r
+ STRING_TOKEN(STR_MISC_ONBOARD_DEVICE_AUDIO), // OnBoardDeviceDescription\r
+ { // OnBoardDeviceStatus\r
+ EfiOnBoardDeviceTypeSound, // DeviceType\r
+ 1, // DeviceEnabled\r
+ 0 // Reserved\r
+ },\r
+ DP_END // OnBoardDevicePath\r
+};\r
--- /dev/null
+/** @file\r
+Onboard device information boot time changes.\r
+SMBIOS type 10.\r
+\r
+Copyright (c) 2013-2015 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+**/\r
+\r
+\r
+#include "CommonHeader.h"\r
+\r
+#include "SmbiosMisc.h"\r
+\r
+\r
+/**\r
+ This function makes boot time changes to the contents of the\r
+ MiscOnboardDevice (Type 10).\r
+\r
+ @param RecordData Pointer to copy of RecordData from the Data Table.\r
+\r
+ @retval EFI_SUCCESS All parameters were valid.\r
+ @retval EFI_UNSUPPORTED Unexpected RecordType value.\r
+ @retval EFI_INVALID_PARAMETER Invalid parameter was found.\r
+\r
+**/\r
+MISC_SMBIOS_TABLE_FUNCTION(MiscOnboardDevice)\r
+{\r
+ CHAR8 *OptionalStrStart;\r
+ UINT8 StatusAndType;\r
+ UINTN DescriptionStrLen;\r
+ EFI_STRING DeviceDescription;\r
+ STRING_REF TokenToGet;\r
+ EFI_STATUS Status;\r
+ EFI_SMBIOS_HANDLE SmbiosHandle;\r
+ SMBIOS_TABLE_TYPE10 *SmbiosRecord;\r
+ EFI_MISC_ONBOARD_DEVICE *ForType10InputData;\r
+\r
+ ForType10InputData = (EFI_MISC_ONBOARD_DEVICE *)RecordData;\r
+ //\r
+ // First check for invalid parameters.\r
+ //\r
+ if (RecordData == NULL) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+\r
+ TokenToGet = 0;\r
+ switch (ForType10InputData->OnBoardDeviceDescription) {\r
+ case STR_MISC_ONBOARD_DEVICE_VIDEO:\r
+ TokenToGet = STRING_TOKEN (STR_MISC_ONBOARD_DEVICE_VIDEO);\r
+ break;\r
+ case STR_MISC_ONBOARD_DEVICE_AUDIO:\r
+ TokenToGet = STRING_TOKEN (STR_MISC_ONBOARD_DEVICE_AUDIO);\r
+ break;\r
+ }\r
+\r
+ DeviceDescription = HiiGetPackageString(&gEfiCallerIdGuid, TokenToGet, NULL);\r
+ DescriptionStrLen = StrLen(DeviceDescription);\r
+ if (DescriptionStrLen > SMBIOS_STRING_MAX_LENGTH) {\r
+ return EFI_UNSUPPORTED;\r
+ }\r
+\r
+ //\r
+ // Two zeros following the last string.\r
+ //\r
+ SmbiosRecord = AllocatePool(sizeof (SMBIOS_TABLE_TYPE10) + DescriptionStrLen + 1 + 1);\r
+ ZeroMem(SmbiosRecord, sizeof (SMBIOS_TABLE_TYPE10) + DescriptionStrLen + 1 + 1);\r
+\r
+ SmbiosRecord->Hdr.Type = EFI_SMBIOS_TYPE_ONBOARD_DEVICE_INFORMATION;\r
+ SmbiosRecord->Hdr.Length = sizeof (SMBIOS_TABLE_TYPE10);\r
+ //\r
+ // Make handle chosen by smbios protocol.add automatically.\r
+ //\r
+ SmbiosRecord->Hdr.Handle = 0;\r
+\r
+ //\r
+ // Status & Type: Bit 7 Devicen Status, Bits 6:0 Type of Device\r
+ //\r
+ StatusAndType = (UINT8) ForType10InputData->OnBoardDeviceStatus.DeviceType;\r
+ if (ForType10InputData->OnBoardDeviceStatus.DeviceEnabled != 0) {\r
+ StatusAndType |= 0x80;\r
+ } else {\r
+ StatusAndType &= 0x7F;\r
+ }\r
+\r
+ SmbiosRecord->Device[0].DeviceType = StatusAndType;\r
+ SmbiosRecord->Device[0].DescriptionString = 1;\r
+ OptionalStrStart = (CHAR8 *)(SmbiosRecord + 1);\r
+ UnicodeStrToAsciiStr(DeviceDescription, OptionalStrStart);\r
+\r
+ //\r
+ // Now we have got the full smbios record, call smbios protocol to add this record.\r
+ //\r
+ SmbiosHandle = SMBIOS_HANDLE_PI_RESERVED;\r
+ Status = Smbios-> Add(\r
+ Smbios,\r
+ NULL,\r
+ &SmbiosHandle,\r
+ (EFI_SMBIOS_TABLE_HEADER *) SmbiosRecord\r
+ );\r
+ FreePool(SmbiosRecord);\r
+ return Status;\r
+}\r
--- /dev/null
+// /** @file\r
+// Miscellaneous Port Internal Connector Information\r
+//\r
+// Copyright (c) 2013-2015 Intel Corporation.\r
+//\r
+// This program and the accompanying materials\r
+// are licensed and made available under the terms and conditions of the BSD License\r
+// which accompanies this distribution. The full text of the license may be found at\r
+// http://opensource.org/licenses/bsd-license.php\r
+//\r
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+//\r
+//\r
+// **/\r
+/=#\r
+\r
+#string STR_MISC_PORT1_INTERNAL_DESIGN #language en-US "P1ICD"\r
+#string STR_MISC_PORT1_EXTERNAL_DESIGN #language en-US "P1ECD"\r
+#string STR_MISC_PORT2_INTERNAL_DESIGN #language en-US "P2ICD"\r
+#string STR_MISC_PORT2_EXTERNAL_DESIGN #language en-US "P2ECD"\r
+#string STR_MISC_PORT3_INTERNAL_DESIGN #language en-US "P3ICD"\r
+#string STR_MISC_PORT3_EXTERNAL_DESIGN #language en-US "P3ECD"\r
+#string STR_MISC_PORT4_INTERNAL_DESIGN #language en-US "P4ICD"\r
+#string STR_MISC_PORT4_EXTERNAL_DESIGN #language en-US "P4ECD"\r
+#string STR_MISC_PORT5_INTERNAL_DESIGN #language en-US "P5ICD"\r
+#string STR_MISC_PORT5_EXTERNAL_DESIGN #language en-US "P5ECD"\r
+#string STR_MISC_PORT6_INTERNAL_DESIGN #language en-US "P6ICD"\r
+#string STR_MISC_PORT6_EXTERNAL_DESIGN #language en-US "P6ECD"\r
+#string STR_MISC_PORT7_INTERNAL_DESIGN #language en-US "P7ICD"\r
+#string STR_MISC_PORT7_EXTERNAL_DESIGN #language en-US "P7ECD"\r
+#string STR_MISC_PORT8_INTERNAL_DESIGN #language en-US "P8ICD"\r
+#string STR_MISC_PORT8_EXTERNAL_DESIGN #language en-US "P8ECD"\r
+#string STR_MISC_PORT9_INTERNAL_DESIGN #language en-US "P9ICD"\r
+#string STR_MISC_PORT9_EXTERNAL_DESIGN #language en-US "P9ECD"\r
+#string STR_MISC_PORT10_INTERNAL_DESIGN #language en-US "P10ICD"\r
+#string STR_MISC_PORT10_EXTERNAL_DESIGN #language en-US "P10ECD"\r
+#string STR_MISC_PORT11_INTERNAL_DESIGN #language en-US "P11ICD"\r
+#string STR_MISC_PORT11_EXTERNAL_DESIGN #language en-US "P11ECD"\r
+#string STR_MISC_PORT12_INTERNAL_DESIGN #language en-US "P12ICD"\r
+#string STR_MISC_PORT12_EXTERNAL_DESIGN #language en-US "P12ECD"\r
+#string STR_MISC_PORT13_INTERNAL_DESIGN #language en-US "P13ICD"\r
+#string STR_MISC_PORT13_EXTERNAL_DESIGN #language en-US "P13ECD"\r
+#string STR_MISC_PORT14_INTERNAL_DESIGN #language en-US "P14ICD"\r
+#string STR_MISC_PORT14_EXTERNAL_DESIGN #language en-US "P14ECD"\r
+#string STR_MISC_PORT15_INTERNAL_DESIGN #language en-US "P15ICD"\r
+#string STR_MISC_PORT15_EXTERNAL_DESIGN #language en-US "P15ECD"\r
+#string STR_MISC_PORT16_INTERNAL_DESIGN #language en-US "P16ICD"\r
+#string STR_MISC_PORT16_EXTERNAL_DESIGN #language en-US "P16ECD"\r
+#string STR_MISC_PORT17_INTERNAL_DESIGN #language en-US "P17ICD"\r
+#string STR_MISC_PORT17_EXTERNAL_DESIGN #language en-US "P17ECD"\r
+#string STR_MISC_PORT18_INTERNAL_DESIGN #language en-US "P18ICD"\r
+#string STR_MISC_PORT18_EXTERNAL_DESIGN #language en-US "P18ECD"\r
+#string STR_MISC_PORT19_INTERNAL_DESIGN #language en-US "P19ICD"\r
+#string STR_MISC_PORT19_EXTERNAL_DESIGN #language en-US "P19ECD"\r
+#string STR_MISC_PORT20_INTERNAL_DESIGN #language en-US "P20ICD"\r
+#string STR_MISC_PORT20_EXTERNAL_DESIGN #language en-US "P20ECD"\r
+#string STR_MISC_PORT21_INTERNAL_DESIGN #language en-US "P21ICD"\r
+#string STR_MISC_PORT21_EXTERNAL_DESIGN #language en-US "P21ECD"\r
--- /dev/null
+/** @file\r
+This driver parses the mSmbiosMiscDataTable structure and reports\r
+any generated data to the DataHub.\r
+\r
+Copyright (c) 2013-2015 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+**/\r
+\r
+\r
+#include "CommonHeader.h"\r
+\r
+#include "SmbiosMisc.h"\r
+\r
+//\r
+// Static (possibly build generated) Bios Vendor data.\r
+//\r
+MISC_SMBIOS_TABLE_DATA(EFI_MISC_PORT_INTERNAL_CONNECTOR_DESIGNATOR, MiscPortConnector1) = {\r
+ STRING_TOKEN (STR_MISC_PORT1_INTERNAL_DESIGN), // PortInternalConnectorDesignator\r
+ STRING_TOKEN (STR_MISC_PORT1_EXTERNAL_DESIGN), // PortExternalConnectorDesignator\r
+ EfiPortConnectorTypeNone, // PortInternalConnectorType\r
+ EfiPortConnectorTypePS2, // PortExternalConnectorType\r
+ EfiPortTypeKeyboard, // PortType\r
+ //mPs2KbyboardDevicePath // PortPath\r
+ {{{{0}}}}\r
+};\r
+\r
+MISC_SMBIOS_TABLE_DATA(EFI_MISC_PORT_INTERNAL_CONNECTOR_DESIGNATOR, MiscPortConnector2) = {\r
+ STRING_TOKEN (STR_MISC_PORT2_INTERNAL_DESIGN), // PortInternalConnectorDesignator\r
+ STRING_TOKEN (STR_MISC_PORT2_EXTERNAL_DESIGN), // PortExternalConnectorDesignator\r
+ EfiPortConnectorTypeNone, // PortInternalConnectorType\r
+ EfiPortConnectorTypePS2, // PortExternalConnectorType\r
+ EfiPortTypeMouse, // PortType\r
+ //mPs2MouseDevicePath // PortPath\r
+ {{{{0}}}}\r
+};\r
+\r
+MISC_SMBIOS_TABLE_DATA(EFI_MISC_PORT_INTERNAL_CONNECTOR_DESIGNATOR, MiscPortConnector3) = {\r
+ STRING_TOKEN (STR_MISC_PORT3_INTERNAL_DESIGN),\r
+ STRING_TOKEN (STR_MISC_PORT3_EXTERNAL_DESIGN),\r
+ EfiPortConnectorTypeOther,\r
+ EfiPortConnectorTypeNone,\r
+ EfiPortTypeSerial16550ACompatible,\r
+ //mCom1DevicePath\r
+ {{{{0}}}}\r
+};\r
+\r
+\r
+\r
+MISC_SMBIOS_TABLE_DATA(EFI_MISC_PORT_INTERNAL_CONNECTOR_DESIGNATOR, MiscPortConnector4) = {\r
+ STRING_TOKEN (STR_MISC_PORT4_INTERNAL_DESIGN),\r
+ STRING_TOKEN (STR_MISC_PORT4_EXTERNAL_DESIGN),\r
+ EfiPortConnectorTypeNone,\r
+ EfiPortConnectorTypeRJ45,\r
+ EfiPortTypeSerial16550ACompatible,\r
+ //mCom2DevicePath\r
+ {{{{0}}}}\r
+};\r
+\r
+MISC_SMBIOS_TABLE_DATA(EFI_MISC_PORT_INTERNAL_CONNECTOR_DESIGNATOR, MiscPortConnector5) = {\r
+ STRING_TOKEN (STR_MISC_PORT5_INTERNAL_DESIGN),\r
+ STRING_TOKEN (STR_MISC_PORT5_EXTERNAL_DESIGN),\r
+ EfiPortConnectorTypeOther,\r
+ EfiPortConnectorTypeNone,\r
+ EfiPortTypeSerial16550ACompatible,\r
+ //mCom3DevicePath\r
+ {{{{0}}}}\r
+};\r
+\r
+MISC_SMBIOS_TABLE_DATA(EFI_MISC_PORT_INTERNAL_CONNECTOR_DESIGNATOR, MiscPortConnector6) = {\r
+ STRING_TOKEN (STR_MISC_PORT6_INTERNAL_DESIGN),\r
+ STRING_TOKEN (STR_MISC_PORT6_EXTERNAL_DESIGN),\r
+ EfiPortConnectorTypeNone,\r
+ EfiPortConnectorTypeRJ45,\r
+ EfiPortTypeSerial16550ACompatible,\r
+ //mCom3DevicePath\r
+ {{{{0}}}}\r
+};\r
+\r
+MISC_SMBIOS_TABLE_DATA(EFI_MISC_PORT_INTERNAL_CONNECTOR_DESIGNATOR, MiscPortConnector7) = {\r
+ STRING_TOKEN (STR_MISC_PORT7_INTERNAL_DESIGN),\r
+ STRING_TOKEN (STR_MISC_PORT7_EXTERNAL_DESIGN),\r
+ EfiPortConnectorTypeNone,\r
+ EfiPortConnectorTypeDB25Male,\r
+ EfiPortTypeParallelPortEcpEpp,\r
+ //mLpt1DevicePath\r
+ {{{{0}}}}\r
+};\r
+\r
+\r
+MISC_SMBIOS_TABLE_DATA(EFI_MISC_PORT_INTERNAL_CONNECTOR_DESIGNATOR, MiscPortConnector8) = {\r
+ STRING_TOKEN (STR_MISC_PORT8_INTERNAL_DESIGN),\r
+ STRING_TOKEN (STR_MISC_PORT8_EXTERNAL_DESIGN),\r
+ EfiPortConnectorTypeNone,\r
+ EfiPortConnectorTypeUsb,\r
+ EfiPortTypeUsb,\r
+ //mUsb0DevicePath\r
+ {{{{0}}}}\r
+};\r
+\r
+MISC_SMBIOS_TABLE_DATA(EFI_MISC_PORT_INTERNAL_CONNECTOR_DESIGNATOR, MiscPortConnector9) = {\r
+ STRING_TOKEN (STR_MISC_PORT9_INTERNAL_DESIGN),\r
+ STRING_TOKEN (STR_MISC_PORT9_EXTERNAL_DESIGN),\r
+ EfiPortConnectorTypeNone,\r
+ EfiPortConnectorTypeUsb,\r
+ EfiPortTypeUsb,\r
+ //mUsb1DevicePath\r
+ {{{{0}}}}\r
+};\r
+\r
+MISC_SMBIOS_TABLE_DATA(EFI_MISC_PORT_INTERNAL_CONNECTOR_DESIGNATOR, MiscPortConnector10) = {\r
+ STRING_TOKEN (STR_MISC_PORT10_INTERNAL_DESIGN),\r
+ STRING_TOKEN (STR_MISC_PORT10_EXTERNAL_DESIGN),\r
+ EfiPortConnectorTypeNone,\r
+ EfiPortConnectorTypeUsb,\r
+ EfiPortTypeUsb,\r
+ //mUsb2DevicePath\r
+ {{{{0}}}}\r
+};\r
+\r
+MISC_SMBIOS_TABLE_DATA(EFI_MISC_PORT_INTERNAL_CONNECTOR_DESIGNATOR, MiscPortConnector11) = {\r
+ STRING_TOKEN (STR_MISC_PORT11_INTERNAL_DESIGN),\r
+ STRING_TOKEN (STR_MISC_PORT11_EXTERNAL_DESIGN),\r
+ EfiPortConnectorTypeNone,\r
+ EfiPortConnectorTypeUsb,\r
+ EfiPortTypeUsb,\r
+ //mUsb3DevicePath\r
+ {{{{0}}}}\r
+};\r
+\r
+\r
+MISC_SMBIOS_TABLE_DATA(EFI_MISC_PORT_INTERNAL_CONNECTOR_DESIGNATOR, MiscPortConnector12) = {\r
+ STRING_TOKEN (STR_MISC_PORT12_INTERNAL_DESIGN),\r
+ STRING_TOKEN (STR_MISC_PORT12_EXTERNAL_DESIGN),\r
+ EfiPortConnectorTypeNone,\r
+ EfiPortConnectorTypeRJ45,\r
+ EfiPortTypeNetworkPort,\r
+ //mGbNicDevicePath\r
+ {{{{0}}}}\r
+};\r
+\r
+\r
+MISC_SMBIOS_TABLE_DATA(EFI_MISC_PORT_INTERNAL_CONNECTOR_DESIGNATOR, MiscPortConnector13) = {\r
+ STRING_TOKEN (STR_MISC_PORT13_INTERNAL_DESIGN),\r
+ STRING_TOKEN (STR_MISC_PORT13_EXTERNAL_DESIGN),\r
+ EfiPortConnectorTypeOnboardFloppy,\r
+ EfiPortConnectorTypeNone,\r
+ EfiPortTypeOther,\r
+ //mFloopyADevicePath\r
+ {{{{0}}}}\r
+};\r
+\r
+MISC_SMBIOS_TABLE_DATA(EFI_MISC_PORT_INTERNAL_CONNECTOR_DESIGNATOR, MiscPortConnector14) = {\r
+ STRING_TOKEN (STR_MISC_PORT14_INTERNAL_DESIGN),\r
+ STRING_TOKEN (STR_MISC_PORT14_EXTERNAL_DESIGN),\r
+ EfiPortConnectorTypeOnboardIde,\r
+ EfiPortConnectorTypeNone,\r
+ EfiPortTypeOther,\r
+ //mIdeDevicePath\r
+ {{{{0}}}}\r
+};\r
+\r
+MISC_SMBIOS_TABLE_DATA(EFI_MISC_PORT_INTERNAL_CONNECTOR_DESIGNATOR, MiscPortConnector15) = {\r
+ STRING_TOKEN (STR_MISC_PORT15_INTERNAL_DESIGN),\r
+ STRING_TOKEN (STR_MISC_PORT15_EXTERNAL_DESIGN),\r
+ EfiPortConnectorTypeOnboardIde,\r
+ EfiPortConnectorTypeNone,\r
+ EfiPortTypeOther,\r
+ //mSataDevicePath\r
+ {{{{0}}}}\r
+};\r
+\r
+MISC_SMBIOS_TABLE_DATA(EFI_MISC_PORT_INTERNAL_CONNECTOR_DESIGNATOR, MiscPortConnector16) = {\r
+ STRING_TOKEN (STR_MISC_PORT16_INTERNAL_DESIGN),\r
+ STRING_TOKEN (STR_MISC_PORT16_EXTERNAL_DESIGN),\r
+ EfiPortConnectorTypeOnboardIde,\r
+ EfiPortConnectorTypeNone,\r
+ EfiPortTypeOther,\r
+ //mSataDevicePath\r
+ {{{{0}}}}\r
+};\r
+\r
--- /dev/null
+/** @file\r
+Port internal connector designator information boot time changes.\r
+SMBIOS type 8.\r
+\r
+Copyright (c) 2013-2015 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+**/\r
+\r
+\r
+#include "CommonHeader.h"\r
+\r
+#include "SmbiosMisc.h"\r
+\r
+//STATIC PS2_CONN_DEVICE_PATH mPs2KeyboardDevicePath = { DP_ACPI, DP_PCI( 0x1F,0x00 ),DP_LPC( 0x0303,0 ), DP_END };\r
+//STATIC PS2_CONN_DEVICE_PATH mPs2MouseDevicePath = { DP_ACPI, DP_PCI( 0x1F,0x00 ),DP_LPC( 0x0303,1 ), DP_END };\r
+//STATIC SERIAL_CONN_DEVICE_PATH mCom1DevicePath = { DP_ACPI, DP_PCI( 0x1F,0x00 ),DP_LPC( 0x0501,0 ), DP_END };\r
+//STATIC SERIAL_CONN_DEVICE_PATH mCom2DevicePath = { DP_ACPI, DP_PCI( 0x1F,0x00 ),DP_LPC( 0x0501,1 ), DP_END };\r
+//STATIC PARALLEL_CONN_DEVICE_PATH mLpt1DevicePath = { DP_ACPI, DP_PCI( 0x1F,0x00 ),DP_LPC( 0x0401,0 ), DP_END };\r
+//STATIC FLOOPY_CONN_DEVICE_PATH mFloopyADevicePath = { DP_ACPI, DP_PCI( 0x1F,0x00 ),DP_LPC( 0x0604,0 ), DP_END };\r
+//STATIC FLOOPY_CONN_DEVICE_PATH mFloopyBDevicePath = { DP_ACPI, DP_PCI( 0x1F,0x00 ),DP_LPC( 0x0604,1 ), DP_END };\r
+//STATIC USB_PORT_DEVICE_PATH mUsb0DevicePath = { DP_ACPI, DP_PCI( 0x1d,0x00 ), DP_END };\r
+//STATIC USB_PORT_DEVICE_PATH mUsb1DevicePath = { DP_ACPI, DP_PCI( 0x1d,0x01 ), DP_END };\r
+//STATIC USB_PORT_DEVICE_PATH mUsb2DevicePath = { DP_ACPI, DP_PCI( 0x1d,0x02 ), DP_END };\r
+//STATIC USB_PORT_DEVICE_PATH mUsb3DevicePath = { DP_ACPI, DP_PCI( 0x1d,0x03 ), DP_END };\r
+//STATIC IDE_DEVICE_PATH mIdeDevicePath = { DP_ACPI, DP_PCI( 0x1F,0x01 ), DP_END };\r
+//STATIC IDE_DEVICE_PATH mSata1DevicePath = { DP_ACPI, DP_PCI( 0x1F,0x02 ), DP_END };\r
+//STATIC GB_NIC_DEVICE_PATH mGbNicDevicePath = { DP_ACPI, DP_PCI( 0x03,0x00 ),DP_PCI( 0x1F,0x00 ),DP_PCI( 0x07,0x00 ), DP_END };\r
+EFI_DEVICE_PATH_PROTOCOL mEndDevicePath = DP_END;\r
+\r
+MISC_SMBIOS_DATA_TABLE_EXTERNS (EFI_MISC_PORT_INTERNAL_CONNECTOR_DESIGNATOR, MiscPortConnector1);\r
+MISC_SMBIOS_DATA_TABLE_EXTERNS (EFI_MISC_PORT_INTERNAL_CONNECTOR_DESIGNATOR, MiscPortConnector2);\r
+MISC_SMBIOS_DATA_TABLE_EXTERNS (EFI_MISC_PORT_INTERNAL_CONNECTOR_DESIGNATOR, MiscPortConnector3);\r
+MISC_SMBIOS_DATA_TABLE_EXTERNS (EFI_MISC_PORT_INTERNAL_CONNECTOR_DESIGNATOR, MiscPortConnector4);\r
+MISC_SMBIOS_DATA_TABLE_EXTERNS (EFI_MISC_PORT_INTERNAL_CONNECTOR_DESIGNATOR, MiscPortConnector5);\r
+MISC_SMBIOS_DATA_TABLE_EXTERNS (EFI_MISC_PORT_INTERNAL_CONNECTOR_DESIGNATOR, MiscPortConnector6);\r
+MISC_SMBIOS_DATA_TABLE_EXTERNS (EFI_MISC_PORT_INTERNAL_CONNECTOR_DESIGNATOR, MiscPortConnector7);\r
+MISC_SMBIOS_DATA_TABLE_EXTERNS (EFI_MISC_PORT_INTERNAL_CONNECTOR_DESIGNATOR, MiscPortConnector8);\r
+MISC_SMBIOS_DATA_TABLE_EXTERNS (EFI_MISC_PORT_INTERNAL_CONNECTOR_DESIGNATOR, MiscPortConnector9);\r
+MISC_SMBIOS_DATA_TABLE_EXTERNS (EFI_MISC_PORT_INTERNAL_CONNECTOR_DESIGNATOR, MiscPortConnector10);\r
+MISC_SMBIOS_DATA_TABLE_EXTERNS (EFI_MISC_PORT_INTERNAL_CONNECTOR_DESIGNATOR, MiscPortConnector11);\r
+MISC_SMBIOS_DATA_TABLE_EXTERNS (EFI_MISC_PORT_INTERNAL_CONNECTOR_DESIGNATOR, MiscPortConnector12);\r
+MISC_SMBIOS_DATA_TABLE_EXTERNS (EFI_MISC_PORT_INTERNAL_CONNECTOR_DESIGNATOR, MiscPortConnector13);\r
+MISC_SMBIOS_DATA_TABLE_EXTERNS (EFI_MISC_PORT_INTERNAL_CONNECTOR_DESIGNATOR, MiscPortConnector14);\r
+\r
+\r
+EFI_MISC_PORT_INTERNAL_CONNECTOR_DESIGNATOR *mMiscConnectorArray[SMBIOS_PORT_CONNECTOR_MAX_NUM] =\r
+{\r
+ MISC_SMBIOS_DATA_TABLE_POINTER(MiscPortConnector1),\r
+ MISC_SMBIOS_DATA_TABLE_POINTER(MiscPortConnector2),\r
+ MISC_SMBIOS_DATA_TABLE_POINTER(MiscPortConnector3),\r
+ MISC_SMBIOS_DATA_TABLE_POINTER(MiscPortConnector4),\r
+ MISC_SMBIOS_DATA_TABLE_POINTER(MiscPortConnector5),\r
+ MISC_SMBIOS_DATA_TABLE_POINTER(MiscPortConnector6),\r
+ MISC_SMBIOS_DATA_TABLE_POINTER(MiscPortConnector7),\r
+ MISC_SMBIOS_DATA_TABLE_POINTER(MiscPortConnector8),\r
+ MISC_SMBIOS_DATA_TABLE_POINTER(MiscPortConnector9),\r
+ MISC_SMBIOS_DATA_TABLE_POINTER(MiscPortConnector10),\r
+ MISC_SMBIOS_DATA_TABLE_POINTER(MiscPortConnector11),\r
+ MISC_SMBIOS_DATA_TABLE_POINTER(MiscPortConnector12),\r
+ MISC_SMBIOS_DATA_TABLE_POINTER(MiscPortConnector13),\r
+ MISC_SMBIOS_DATA_TABLE_POINTER(MiscPortConnector14),\r
+};\r
+\r
+BOOLEAN PcdMiscPortIsInit = FALSE;\r
+SMBIOS_PORT_CONNECTOR_DESIGNATOR_COFNIG SMBIOSPortConnector = {0};\r
+\r
+\r
+/**\r
+ Get Misc Port Configuration information from PCD\r
+ @param SMBIOSPortConnector Pointer to SMBIOSPortConnector table.\r
+\r
+**/\r
+\r
+VOID\r
+GetMiscPortConfigFromPcd ()\r
+{\r
+ //\r
+ // Type 8\r
+ //\r
+ SMBIOSPortConnector.SMBIOSConnectorNumber = PcdGet8 (PcdSMBIOSConnectorNumber);\r
+ AsciiStrToUnicodeStr ((CHAR8 *) PcdGetPtr(PcdSMBIOSPort1InternalConnectorDesignator), SMBIOSPortConnector.SMBIOSPortConnector[0].PortInternalConnectorDesignator);\r
+ AsciiStrToUnicodeStr ((CHAR8 *) PcdGetPtr(PcdSMBIOSPort1ExternalConnectorDesignator), SMBIOSPortConnector.SMBIOSPortConnector[0].PortExternalConnectorDesignator);\r
+ SMBIOSPortConnector.SMBIOSPortConnector[0].PortInternalConnectorType = PcdGet8 (PcdSMBIOSPort1InternalConnectorType);\r
+ SMBIOSPortConnector.SMBIOSPortConnector[0].PortExternalConnectorType = PcdGet8 (PcdSMBIOSPort1ExternalConnectorType);\r
+ SMBIOSPortConnector.SMBIOSPortConnector[0].PortType = PcdGet8 (PcdSMBIOSPort1Type);\r
+\r
+ AsciiStrToUnicodeStr ((CHAR8 *) PcdGetPtr(PcdSMBIOSPort2InternalConnectorDesignator), SMBIOSPortConnector.SMBIOSPortConnector[1].PortInternalConnectorDesignator);\r
+ AsciiStrToUnicodeStr ((CHAR8 *) PcdGetPtr(PcdSMBIOSPort2ExternalConnectorDesignator), SMBIOSPortConnector.SMBIOSPortConnector[1].PortExternalConnectorDesignator);\r
+ SMBIOSPortConnector.SMBIOSPortConnector[1].PortInternalConnectorType = PcdGet8 (PcdSMBIOSPort2InternalConnectorType);\r
+ SMBIOSPortConnector.SMBIOSPortConnector[1].PortExternalConnectorType = PcdGet8 (PcdSMBIOSPort2ExternalConnectorType);\r
+ SMBIOSPortConnector.SMBIOSPortConnector[1].PortType = PcdGet8 (PcdSMBIOSPort2Type);\r
+\r
+ AsciiStrToUnicodeStr ((CHAR8 *) PcdGetPtr(PcdSMBIOSPort3InternalConnectorDesignator), SMBIOSPortConnector.SMBIOSPortConnector[2].PortInternalConnectorDesignator);\r
+ AsciiStrToUnicodeStr ((CHAR8 *) PcdGetPtr(PcdSMBIOSPort3ExternalConnectorDesignator), SMBIOSPortConnector.SMBIOSPortConnector[2].PortExternalConnectorDesignator);\r
+ SMBIOSPortConnector.SMBIOSPortConnector[2].PortInternalConnectorType = PcdGet8 (PcdSMBIOSPort3InternalConnectorType);\r
+ SMBIOSPortConnector.SMBIOSPortConnector[2].PortExternalConnectorType = PcdGet8 (PcdSMBIOSPort3ExternalConnectorType);\r
+ SMBIOSPortConnector.SMBIOSPortConnector[2].PortType = PcdGet8 (PcdSMBIOSPort3Type);\r
+\r
+ AsciiStrToUnicodeStr ((CHAR8 *) PcdGetPtr(PcdSMBIOSPort4InternalConnectorDesignator), SMBIOSPortConnector.SMBIOSPortConnector[3].PortInternalConnectorDesignator);\r
+ AsciiStrToUnicodeStr ((CHAR8 *) PcdGetPtr(PcdSMBIOSPort4ExternalConnectorDesignator), SMBIOSPortConnector.SMBIOSPortConnector[3].PortExternalConnectorDesignator);\r
+ SMBIOSPortConnector.SMBIOSPortConnector[3].PortInternalConnectorType = PcdGet8 (PcdSMBIOSPort4InternalConnectorType);\r
+ SMBIOSPortConnector.SMBIOSPortConnector[3].PortExternalConnectorType = PcdGet8 (PcdSMBIOSPort4ExternalConnectorType);\r
+ SMBIOSPortConnector.SMBIOSPortConnector[3].PortType = PcdGet8 (PcdSMBIOSPort4Type);\r
+\r
+ AsciiStrToUnicodeStr ((CHAR8 *) PcdGetPtr(PcdSMBIOSPort5InternalConnectorDesignator), SMBIOSPortConnector.SMBIOSPortConnector[4].PortInternalConnectorDesignator);\r
+ AsciiStrToUnicodeStr ((CHAR8 *) PcdGetPtr(PcdSMBIOSPort5ExternalConnectorDesignator), SMBIOSPortConnector.SMBIOSPortConnector[4].PortExternalConnectorDesignator);\r
+ SMBIOSPortConnector.SMBIOSPortConnector[4].PortInternalConnectorType = PcdGet8 (PcdSMBIOSPort5InternalConnectorType);\r
+ SMBIOSPortConnector.SMBIOSPortConnector[4].PortExternalConnectorType = PcdGet8 (PcdSMBIOSPort5ExternalConnectorType);\r
+ SMBIOSPortConnector.SMBIOSPortConnector[4].PortType = PcdGet8 (PcdSMBIOSPort5Type);\r
+\r
+ AsciiStrToUnicodeStr ((CHAR8 *) PcdGetPtr(PcdSMBIOSPort6InternalConnectorDesignator), SMBIOSPortConnector.SMBIOSPortConnector[5].PortInternalConnectorDesignator);\r
+ AsciiStrToUnicodeStr ((CHAR8 *) PcdGetPtr(PcdSMBIOSPort6ExternalConnectorDesignator), SMBIOSPortConnector.SMBIOSPortConnector[5].PortExternalConnectorDesignator);\r
+ SMBIOSPortConnector.SMBIOSPortConnector[5].PortInternalConnectorType = PcdGet8 (PcdSMBIOSPort6InternalConnectorType);\r
+ SMBIOSPortConnector.SMBIOSPortConnector[5].PortExternalConnectorType = PcdGet8 (PcdSMBIOSPort6ExternalConnectorType);\r
+ SMBIOSPortConnector.SMBIOSPortConnector[5].PortType = PcdGet8 (PcdSMBIOSPort6Type);\r
+\r
+ AsciiStrToUnicodeStr ((CHAR8 *) PcdGetPtr(PcdSMBIOSPort7InternalConnectorDesignator), SMBIOSPortConnector.SMBIOSPortConnector[6].PortInternalConnectorDesignator);\r
+ AsciiStrToUnicodeStr ((CHAR8 *) PcdGetPtr(PcdSMBIOSPort7ExternalConnectorDesignator), SMBIOSPortConnector.SMBIOSPortConnector[6].PortExternalConnectorDesignator);\r
+ SMBIOSPortConnector.SMBIOSPortConnector[6].PortInternalConnectorType = PcdGet8 (PcdSMBIOSPort7InternalConnectorType);\r
+ SMBIOSPortConnector.SMBIOSPortConnector[6].PortExternalConnectorType = PcdGet8 (PcdSMBIOSPort7ExternalConnectorType);\r
+ SMBIOSPortConnector.SMBIOSPortConnector[6].PortType = PcdGet8 (PcdSMBIOSPort7Type);\r
+\r
+ AsciiStrToUnicodeStr ((CHAR8 *) PcdGetPtr(PcdSMBIOSPort8InternalConnectorDesignator), SMBIOSPortConnector.SMBIOSPortConnector[7].PortInternalConnectorDesignator);\r
+ AsciiStrToUnicodeStr ((CHAR8 *) PcdGetPtr(PcdSMBIOSPort8ExternalConnectorDesignator), SMBIOSPortConnector.SMBIOSPortConnector[7].PortExternalConnectorDesignator);\r
+ SMBIOSPortConnector.SMBIOSPortConnector[7].PortInternalConnectorType = PcdGet8 (PcdSMBIOSPort8InternalConnectorType);\r
+ SMBIOSPortConnector.SMBIOSPortConnector[7].PortExternalConnectorType = PcdGet8 (PcdSMBIOSPort8ExternalConnectorType);\r
+ SMBIOSPortConnector.SMBIOSPortConnector[7].PortType = PcdGet8 (PcdSMBIOSPort8Type);\r
+\r
+ AsciiStrToUnicodeStr ((CHAR8 *) PcdGetPtr(PcdSMBIOSPort9InternalConnectorDesignator), SMBIOSPortConnector.SMBIOSPortConnector[8].PortInternalConnectorDesignator);\r
+ AsciiStrToUnicodeStr ((CHAR8 *) PcdGetPtr(PcdSMBIOSPort9ExternalConnectorDesignator), SMBIOSPortConnector.SMBIOSPortConnector[8].PortExternalConnectorDesignator);\r
+ SMBIOSPortConnector.SMBIOSPortConnector[8].PortInternalConnectorType = PcdGet8 (PcdSMBIOSPort9InternalConnectorType);\r
+ SMBIOSPortConnector.SMBIOSPortConnector[8].PortExternalConnectorType = PcdGet8 (PcdSMBIOSPort9ExternalConnectorType);\r
+ SMBIOSPortConnector.SMBIOSPortConnector[8].PortType = PcdGet8 (PcdSMBIOSPort9Type);\r
+\r
+ AsciiStrToUnicodeStr ((CHAR8 *) PcdGetPtr(PcdSMBIOSPort10InternalConnectorDesignator), SMBIOSPortConnector.SMBIOSPortConnector[9].PortInternalConnectorDesignator);\r
+ AsciiStrToUnicodeStr ((CHAR8 *) PcdGetPtr(PcdSMBIOSPort10ExternalConnectorDesignator), SMBIOSPortConnector.SMBIOSPortConnector[9].PortExternalConnectorDesignator);\r
+ SMBIOSPortConnector.SMBIOSPortConnector[9].PortInternalConnectorType = PcdGet8 (PcdSMBIOSPort10InternalConnectorType);\r
+ SMBIOSPortConnector.SMBIOSPortConnector[9].PortExternalConnectorType = PcdGet8 (PcdSMBIOSPort10ExternalConnectorType);\r
+ SMBIOSPortConnector.SMBIOSPortConnector[9].PortType = PcdGet8 (PcdSMBIOSPort10Type);\r
+\r
+ AsciiStrToUnicodeStr ((CHAR8 *) PcdGetPtr(PcdSMBIOSPort11InternalConnectorDesignator), SMBIOSPortConnector.SMBIOSPortConnector[10].PortInternalConnectorDesignator);\r
+ AsciiStrToUnicodeStr ((CHAR8 *) PcdGetPtr(PcdSMBIOSPort11ExternalConnectorDesignator), SMBIOSPortConnector.SMBIOSPortConnector[10].PortExternalConnectorDesignator);\r
+ SMBIOSPortConnector.SMBIOSPortConnector[10].PortInternalConnectorType = PcdGet8 (PcdSMBIOSPort11InternalConnectorType);\r
+ SMBIOSPortConnector.SMBIOSPortConnector[10].PortExternalConnectorType = PcdGet8 (PcdSMBIOSPort11ExternalConnectorType);\r
+ SMBIOSPortConnector.SMBIOSPortConnector[10].PortType = PcdGet8 (PcdSMBIOSPort11Type);\r
+\r
+ AsciiStrToUnicodeStr ((CHAR8 *) PcdGetPtr(PcdSMBIOSPort12InternalConnectorDesignator), SMBIOSPortConnector.SMBIOSPortConnector[11].PortInternalConnectorDesignator);\r
+ AsciiStrToUnicodeStr ((CHAR8 *) PcdGetPtr(PcdSMBIOSPort12ExternalConnectorDesignator), SMBIOSPortConnector.SMBIOSPortConnector[11].PortExternalConnectorDesignator);\r
+ SMBIOSPortConnector.SMBIOSPortConnector[11].PortInternalConnectorType = PcdGet8 (PcdSMBIOSPort12InternalConnectorType);\r
+ SMBIOSPortConnector.SMBIOSPortConnector[11].PortExternalConnectorType = PcdGet8 (PcdSMBIOSPort12ExternalConnectorType);\r
+ SMBIOSPortConnector.SMBIOSPortConnector[11].PortType = PcdGet8 (PcdSMBIOSPort12Type);\r
+\r
+ AsciiStrToUnicodeStr ((CHAR8 *) PcdGetPtr(PcdSMBIOSPort13InternalConnectorDesignator), SMBIOSPortConnector.SMBIOSPortConnector[12].PortInternalConnectorDesignator);\r
+ AsciiStrToUnicodeStr ((CHAR8 *) PcdGetPtr(PcdSMBIOSPort13ExternalConnectorDesignator), SMBIOSPortConnector.SMBIOSPortConnector[12].PortExternalConnectorDesignator);\r
+ SMBIOSPortConnector.SMBIOSPortConnector[12].PortInternalConnectorType = PcdGet8 (PcdSMBIOSPort13InternalConnectorType);\r
+ SMBIOSPortConnector.SMBIOSPortConnector[12].PortExternalConnectorType = PcdGet8 (PcdSMBIOSPort13ExternalConnectorType);\r
+ SMBIOSPortConnector.SMBIOSPortConnector[12].PortType = PcdGet8 (PcdSMBIOSPort13Type);\r
+\r
+ AsciiStrToUnicodeStr ((CHAR8 *) PcdGetPtr(PcdSMBIOSPort14InternalConnectorDesignator), SMBIOSPortConnector.SMBIOSPortConnector[13].PortInternalConnectorDesignator);\r
+ AsciiStrToUnicodeStr ((CHAR8 *) PcdGetPtr(PcdSMBIOSPort14ExternalConnectorDesignator), SMBIOSPortConnector.SMBIOSPortConnector[13].PortExternalConnectorDesignator);\r
+ SMBIOSPortConnector.SMBIOSPortConnector[13].PortInternalConnectorType = PcdGet8 (PcdSMBIOSPort14InternalConnectorType);\r
+ SMBIOSPortConnector.SMBIOSPortConnector[13].PortExternalConnectorType = PcdGet8 (PcdSMBIOSPort14ExternalConnectorType);\r
+ SMBIOSPortConnector.SMBIOSPortConnector[13].PortType = PcdGet8 (PcdSMBIOSPort14Type);\r
+}\r
+/**\r
+ This function makes boot time changes to the contents of the\r
+ MiscPortConnectorInformation (Type 8).\r
+\r
+ @param RecordData Pointer to copy of RecordData from the Data Table.\r
+\r
+ @retval EFI_SUCCESS All parameters were valid.\r
+ @retval EFI_UNSUPPORTED Unexpected RecordType value.\r
+ @retval EFI_INVALID_PARAMETER Invalid parameter was found.\r
+\r
+**/\r
+MISC_SMBIOS_TABLE_FUNCTION(MiscPortInternalConnectorDesignator)\r
+{\r
+ CHAR8 *OptionalStrStart;\r
+ UINTN InternalRefStrLen;\r
+ UINTN ExternalRefStrLen;\r
+ EFI_STRING InternalRef;\r
+ EFI_STRING ExternalRef;\r
+ STRING_REF TokenForInternal;\r
+ STRING_REF TokenForExternal;\r
+ STRING_REF TokenToUpdate;\r
+ UINT8 InternalType;\r
+ UINT8 ExternalType;\r
+ UINT8 PortType;\r
+ EFI_STATUS Status;\r
+ SMBIOS_TABLE_TYPE8 *SmbiosRecord;\r
+ EFI_SMBIOS_HANDLE SmbiosHandle;\r
+ EFI_MISC_PORT_INTERNAL_CONNECTOR_DESIGNATOR *ForType8InputData;\r
+ UINT8 Index;\r
+\r
+ ForType8InputData = (EFI_MISC_PORT_INTERNAL_CONNECTOR_DESIGNATOR *)RecordData;\r
+ //\r
+ // First check for invalid parameters.\r
+ //\r
+ if (RecordData == NULL) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+\r
+ TokenForInternal = 0;\r
+ TokenForExternal = 0;\r
+ InternalType = 0;\r
+ ExternalType = 0;\r
+ PortType = 0;\r
+\r
+ if (!PcdMiscPortIsInit) {\r
+ GetMiscPortConfigFromPcd ();\r
+ PcdMiscPortIsInit = TRUE;\r
+ }\r
+\r
+ for (Index = 0; Index < SMBIOS_PORT_CONNECTOR_MAX_NUM; Index++) {\r
+ if (ForType8InputData->PortInternalConnectorDesignator == (mMiscConnectorArray[Index])->PortInternalConnectorDesignator) {\r
+ //DEBUG ((EFI_D_ERROR, "Found Port Connector Data %d : ", Index));\r
+ break;\r
+ }\r
+ }\r
+ if (Index >= SMBIOSPortConnector.SMBIOSConnectorNumber) {\r
+ return EFI_SUCCESS;\r
+ }\r
+\r
+ if (Index >= SMBIOS_PORT_CONNECTOR_MAX_NUM) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+\r
+ InternalRef = SMBIOSPortConnector.SMBIOSPortConnector[Index].PortInternalConnectorDesignator;\r
+ if (StrLen (InternalRef) > 0) {\r
+ TokenToUpdate = STRING_TOKEN ((mMiscConnectorArray[Index])->PortInternalConnectorDesignator);\r
+ HiiSetString (mHiiHandle, TokenToUpdate, InternalRef, NULL);\r
+ }\r
+ ExternalRef = SMBIOSPortConnector.SMBIOSPortConnector[Index].PortExternalConnectorDesignator;\r
+ if (StrLen (ExternalRef) > 0) {\r
+ TokenToUpdate = STRING_TOKEN ((mMiscConnectorArray[Index])->PortExternalConnectorDesignator);\r
+ HiiSetString (mHiiHandle, TokenToUpdate, ExternalRef, NULL);\r
+ }\r
+ TokenForInternal = STRING_TOKEN ((mMiscConnectorArray[Index])->PortInternalConnectorDesignator);\r
+ TokenForExternal = STRING_TOKEN ((mMiscConnectorArray[Index])->PortExternalConnectorDesignator);\r
+ InternalType = SMBIOSPortConnector.SMBIOSPortConnector[Index].PortInternalConnectorType;\r
+ ExternalType = SMBIOSPortConnector.SMBIOSPortConnector[Index].PortExternalConnectorType;\r
+ PortType = SMBIOSPortConnector.SMBIOSPortConnector[Index].PortType;\r
+\r
+ InternalRef = HiiGetPackageString(&gEfiCallerIdGuid, TokenForInternal, NULL);\r
+ InternalRefStrLen = StrLen(InternalRef);\r
+ if (InternalRefStrLen > SMBIOS_STRING_MAX_LENGTH) {\r
+ return EFI_UNSUPPORTED;\r
+ }\r
+\r
+ ExternalRef = HiiGetPackageString(&gEfiCallerIdGuid, TokenForExternal, NULL);\r
+ ExternalRefStrLen = StrLen(ExternalRef);\r
+ if (ExternalRefStrLen > SMBIOS_STRING_MAX_LENGTH) {\r
+ return EFI_UNSUPPORTED;\r
+ }\r
+ //\r
+ // Two zeros following the last string.\r
+ //\r
+ SmbiosRecord = AllocatePool(sizeof (SMBIOS_TABLE_TYPE8) + InternalRefStrLen + 1 + ExternalRefStrLen + 1 + 1);\r
+ ZeroMem(SmbiosRecord, sizeof (SMBIOS_TABLE_TYPE8) + InternalRefStrLen + 1 + ExternalRefStrLen + 1 + 1);\r
+\r
+ SmbiosRecord->Hdr.Type = EFI_SMBIOS_TYPE_PORT_CONNECTOR_INFORMATION;\r
+ SmbiosRecord->Hdr.Length = sizeof (SMBIOS_TABLE_TYPE8);\r
+ //\r
+ // Make handle chosen by smbios protocol.add automatically.\r
+ //\r
+ SmbiosRecord->Hdr.Handle = 0;\r
+ SmbiosRecord->InternalReferenceDesignator = 1;\r
+ SmbiosRecord->InternalConnectorType = InternalType;\r
+ SmbiosRecord->ExternalReferenceDesignator = 2;\r
+ SmbiosRecord->ExternalConnectorType = ExternalType;\r
+ SmbiosRecord->PortType = PortType;\r
+\r
+ OptionalStrStart = (CHAR8 *)(SmbiosRecord + 1);\r
+ UnicodeStrToAsciiStr(InternalRef, OptionalStrStart);\r
+ UnicodeStrToAsciiStr(ExternalRef, OptionalStrStart + InternalRefStrLen + 1);\r
+\r
+ //\r
+ // Now we have got the full smbios record, call smbios protocol to add this record.\r
+ //\r
+ SmbiosHandle = SMBIOS_HANDLE_PI_RESERVED;\r
+ Status = Smbios-> Add(\r
+ Smbios,\r
+ NULL,\r
+ &SmbiosHandle,\r
+ (EFI_SMBIOS_TABLE_HEADER *) SmbiosRecord\r
+ );\r
+ FreePool(SmbiosRecord);\r
+ return Status;\r
+}\r
--- /dev/null
+// /** @file\r
+// System Manufacturer Information\r
+//\r
+// Copyright (c) 2013-2015 Intel Corporation.\r
+//\r
+// This program and the accompanying materials\r
+// are licensed and made available under the terms and conditions of the BSD License\r
+// which accompanies this distribution. The full text of the license may be found at\r
+// http://opensource.org/licenses/bsd-license.php\r
+//\r
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+//\r
+//\r
+// **/\r
+\r
+\r
+/=#\r
+\r
+\r
+#string STR_MISC_SYSTEM_MANUFACTURER #language en-US "Intel Corp."\r
+#string STR_MISC_SYSTEM_PRODUCT_NAME #language en-US "QUARK"\r
+#string STR_MISC_SYSTEM_VERSION #language en-US "1.0"\r
+#string STR_MISC_SYSTEM_SERIAL_NUMBER #language en-US "Unknown"\r
+#string STR_MISC_SYSTEM_SKU_NUMBER #language en-US "System SKUNumber"\r
+#string STR_MISC_SYSTEM_FAMILY #language en-US "X1000"\r
--- /dev/null
+/** @file\r
+This driver parses the mMiscSubclassDataTable structure and reports\r
+any generated data using smbios protocol.\r
+\r
+Copyright (c) 2013-2015 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+**/\r
+\r
+\r
+#include "CommonHeader.h"\r
+\r
+#include "SmbiosMisc.h"\r
+\r
+\r
+//\r
+// Static (possibly build generated) System Manufacturer data.\r
+//\r
+MISC_SMBIOS_TABLE_DATA(EFI_MISC_SYSTEM_MANUFACTURER, MiscSystemManufacturer) = {\r
+ STRING_TOKEN(STR_MISC_SYSTEM_MANUFACTURER), // SystemManufactrurer\r
+ STRING_TOKEN(STR_MISC_SYSTEM_PRODUCT_NAME), // SystemProductName\r
+ STRING_TOKEN(STR_MISC_SYSTEM_VERSION), // SystemVersion\r
+ STRING_TOKEN(STR_MISC_SYSTEM_SERIAL_NUMBER), // SystemSerialNumber\r
+ { // SystemUuid\r
+ 0x13ffef23, 0x8654, 0x46da, {0xa4, 0x7, 0x39, 0xc9, 0x12, 0x2, 0xd3, 0x56}\r
+ },\r
+ EfiSystemWakeupTypePowerSwitch, // SystemWakeupType\r
+ STRING_TOKEN(STR_MISC_SYSTEM_SKU_NUMBER), // SystemSKUNumber\r
+ STRING_TOKEN(STR_MISC_SYSTEM_FAMILY), // SystemFamily\r
+};\r
--- /dev/null
+/** @file\r
+This driver parses the mMiscSubclassDataTable structure and reports\r
+any generated data to smbios.\r
+\r
+Copyright (c) 2013-2015 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+**/\r
+\r
+\r
+#include "CommonHeader.h"\r
+\r
+#include "SmbiosMisc.h"\r
+\r
+/**\r
+ This function makes boot time changes to the contents of the\r
+ MiscSystemManufacturer (Type 1).\r
+\r
+ @param RecordData Pointer to copy of RecordData from the Data Table.\r
+\r
+ @retval EFI_SUCCESS All parameters were valid.\r
+ @retval EFI_UNSUPPORTED Unexpected RecordType value.\r
+ @retval EFI_INVALID_PARAMETER Invalid parameter was found.\r
+\r
+**/\r
+MISC_SMBIOS_TABLE_FUNCTION(MiscSystemManufacturer)\r
+{\r
+ CHAR8 *OptionalStrStart;\r
+ UINTN ManuStrLen;\r
+ UINTN VerStrLen;\r
+ UINTN PdNameStrLen;\r
+ UINTN SerialNumStrLen;\r
+ UINTN SKUNumStrLen;\r
+ UINTN FamilyStrLen;\r
+ EFI_STATUS Status;\r
+ CHAR16 Manufacturer[SMBIOS_STRING_MAX_LENGTH];\r
+ CHAR16 ProductName[SMBIOS_STRING_MAX_LENGTH];\r
+ CHAR16 Version[SMBIOS_STRING_MAX_LENGTH];\r
+ CHAR16 SerialNumber[SMBIOS_STRING_MAX_LENGTH];\r
+ CHAR16 SKUNumber[SMBIOS_STRING_MAX_LENGTH];\r
+ CHAR16 Family[SMBIOS_STRING_MAX_LENGTH];\r
+ EFI_STRING ManufacturerPtr;\r
+ EFI_STRING ProductNamePtr;\r
+ EFI_STRING VersionPtr;\r
+ EFI_STRING SerialNumberPtr;\r
+ EFI_STRING SKUNumberPtr;\r
+ EFI_STRING FamilyPtr;\r
+ STRING_REF TokenToGet;\r
+ STRING_REF TokenToUpdate;\r
+ EFI_SMBIOS_HANDLE SmbiosHandle;\r
+ SMBIOS_TABLE_TYPE1 *SmbiosRecord;\r
+ EFI_MISC_SYSTEM_MANUFACTURER *ForType1InputData;\r
+\r
+ ForType1InputData = (EFI_MISC_SYSTEM_MANUFACTURER *)RecordData;\r
+\r
+ //\r
+ // First check for invalid parameters.\r
+ //\r
+ if (RecordData == NULL) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+\r
+ //\r
+ // Update strings from PCD\r
+ //\r
+ AsciiStrToUnicodeStr ((CHAR8 *) PcdGetPtr(PcdSMBIOSSystemManufacturer), Manufacturer);\r
+ if (StrLen (Manufacturer) > 0) {\r
+ TokenToUpdate = STRING_TOKEN (STR_MISC_SYSTEM_MANUFACTURER);\r
+ HiiSetString (mHiiHandle, TokenToUpdate, Manufacturer, NULL);\r
+ }\r
+ TokenToGet = STRING_TOKEN (STR_MISC_SYSTEM_MANUFACTURER);\r
+ ManufacturerPtr = HiiGetPackageString(&gEfiCallerIdGuid, TokenToGet, NULL);\r
+ ManuStrLen = StrLen(ManufacturerPtr);\r
+ if (ManuStrLen > SMBIOS_STRING_MAX_LENGTH) {\r
+ return EFI_UNSUPPORTED;\r
+ }\r
+\r
+ AsciiStrToUnicodeStr ((CHAR8 *) PcdGetPtr(PcdSMBIOSSystemProductName), ProductName);\r
+ if (StrLen (ProductName) > 0) {\r
+ TokenToUpdate = STRING_TOKEN (STR_MISC_SYSTEM_PRODUCT_NAME);\r
+ HiiSetString (mHiiHandle, TokenToUpdate, ProductName, NULL);\r
+ }\r
+ TokenToGet = STRING_TOKEN (STR_MISC_SYSTEM_PRODUCT_NAME);\r
+ ProductNamePtr = HiiGetPackageString(&gEfiCallerIdGuid, TokenToGet, NULL);\r
+ PdNameStrLen = StrLen(ProductNamePtr);\r
+ if (PdNameStrLen > SMBIOS_STRING_MAX_LENGTH) {\r
+ return EFI_UNSUPPORTED;\r
+ }\r
+\r
+ AsciiStrToUnicodeStr ((CHAR8 *) PcdGetPtr(PcdSMBIOSSystemVersion), Version);\r
+ if (StrLen (Version) > 0) {\r
+ TokenToUpdate = STRING_TOKEN (STR_MISC_SYSTEM_VERSION);\r
+ HiiSetString (mHiiHandle, TokenToUpdate, Version, NULL);\r
+ }\r
+ TokenToGet = STRING_TOKEN (STR_MISC_SYSTEM_VERSION);\r
+ VersionPtr = HiiGetPackageString(&gEfiCallerIdGuid, TokenToGet, NULL);\r
+ VerStrLen = StrLen(VersionPtr);\r
+ if (VerStrLen > SMBIOS_STRING_MAX_LENGTH) {\r
+ return EFI_UNSUPPORTED;\r
+ }\r
+\r
+ AsciiStrToUnicodeStr ((CHAR8 *) PcdGetPtr(PcdSMBIOSSystemSerialNumber), SerialNumber);\r
+ if (StrLen (SerialNumber) > 0) {\r
+ TokenToUpdate = STRING_TOKEN (STR_MISC_SYSTEM_SERIAL_NUMBER);\r
+ HiiSetString (mHiiHandle, TokenToUpdate, SerialNumber, NULL);\r
+ }\r
+ TokenToGet = STRING_TOKEN (STR_MISC_SYSTEM_SERIAL_NUMBER);\r
+ SerialNumberPtr = HiiGetPackageString(&gEfiCallerIdGuid, TokenToGet, NULL);\r
+ SerialNumStrLen = StrLen(SerialNumberPtr);\r
+ if (SerialNumStrLen > SMBIOS_STRING_MAX_LENGTH) {\r
+ return EFI_UNSUPPORTED;\r
+ }\r
+\r
+ AsciiStrToUnicodeStr ((CHAR8 *) PcdGetPtr(PcdSMBIOSSystemSKUNumber), SKUNumber);\r
+ if (StrLen (SKUNumber) > 0) {\r
+ TokenToUpdate = STRING_TOKEN (STR_MISC_SYSTEM_SKU_NUMBER);\r
+ HiiSetString (mHiiHandle, TokenToUpdate, SKUNumber, NULL);\r
+ }\r
+ TokenToGet = STRING_TOKEN (STR_MISC_SYSTEM_SKU_NUMBER);\r
+ SKUNumberPtr = HiiGetPackageString(&gEfiCallerIdGuid, TokenToGet, NULL);\r
+ SKUNumStrLen = StrLen(SKUNumberPtr);\r
+ if (SKUNumStrLen > SMBIOS_STRING_MAX_LENGTH) {\r
+ return EFI_UNSUPPORTED;\r
+ }\r
+\r
+ AsciiStrToUnicodeStr ((CHAR8 *) PcdGetPtr(PcdSMBIOSSystemFamily), Family);\r
+ if (StrLen (Family) > 0) {\r
+ TokenToUpdate = STRING_TOKEN (STR_MISC_SYSTEM_FAMILY);\r
+ HiiSetString (mHiiHandle, TokenToUpdate, Family, NULL);\r
+ }\r
+ TokenToGet = STRING_TOKEN (STR_MISC_SYSTEM_FAMILY);\r
+ FamilyPtr = HiiGetPackageString(&gEfiCallerIdGuid, TokenToGet, NULL);\r
+ FamilyStrLen = StrLen(FamilyPtr);\r
+ if (FamilyStrLen > SMBIOS_STRING_MAX_LENGTH) {\r
+ return EFI_UNSUPPORTED;\r
+ }\r
+ //\r
+ // Two zeros following the last string.\r
+ //\r
+ SmbiosRecord = AllocatePool(sizeof (SMBIOS_TABLE_TYPE1) + ManuStrLen + 1 + PdNameStrLen + 1 + VerStrLen + 1 + SerialNumStrLen + 1 + SKUNumStrLen + 1 + FamilyStrLen + 1 + 1);\r
+ ZeroMem(SmbiosRecord, sizeof (SMBIOS_TABLE_TYPE1) + ManuStrLen + 1 + PdNameStrLen + 1 + VerStrLen + 1 + SerialNumStrLen + 1 + SKUNumStrLen + 1 + FamilyStrLen + 1 + 1);\r
+\r
+ SmbiosRecord->Hdr.Type = EFI_SMBIOS_TYPE_SYSTEM_INFORMATION;\r
+ SmbiosRecord->Hdr.Length = sizeof (SMBIOS_TABLE_TYPE1);\r
+ //\r
+ // Make handle chosen by smbios protocol.add automatically.\r
+ //\r
+ SmbiosRecord->Hdr.Handle = 0;\r
+ //\r
+ // Manu will be the 1st optional string following the formatted structure.\r
+ //\r
+ SmbiosRecord->Manufacturer = 1;\r
+ //\r
+ // ProductName will be the 2nd optional string following the formatted structure.\r
+ //\r
+ SmbiosRecord->ProductName = 2;\r
+ //\r
+ // Version will be the 3rd optional string following the formatted structure.\r
+ //\r
+ SmbiosRecord->Version = 3;\r
+ //\r
+ // Serial number will be the 4th optional string following the formatted structure.\r
+ //\r
+ SmbiosRecord->SerialNumber = 4;\r
+ //\r
+ // SKU number will be the 5th optional string following the formatted structure.\r
+ //\r
+ SmbiosRecord->SKUNumber = 5;\r
+ //\r
+ // Family will be the 6th optional string following the formatted structure.\r
+ //\r
+ SmbiosRecord->Family = 6;\r
+ CopyMem ((UINT8 *) (&SmbiosRecord->Uuid), (UINT8 *)PcdGetPtr(PcdSMBIOSSystemUuid),16);\r
+ SmbiosRecord->WakeUpType = (UINT8)ForType1InputData->SystemWakeupType;\r
+\r
+ OptionalStrStart = (CHAR8 *)(SmbiosRecord + 1);\r
+ UnicodeStrToAsciiStr(ManufacturerPtr, OptionalStrStart);\r
+ UnicodeStrToAsciiStr(ProductNamePtr, OptionalStrStart + ManuStrLen + 1);\r
+ UnicodeStrToAsciiStr(VersionPtr, OptionalStrStart + ManuStrLen + 1 + PdNameStrLen + 1);\r
+ UnicodeStrToAsciiStr(SerialNumberPtr, OptionalStrStart + ManuStrLen + 1 + PdNameStrLen + 1 + VerStrLen + 1);\r
+ UnicodeStrToAsciiStr(SKUNumberPtr, OptionalStrStart + ManuStrLen + 1 + PdNameStrLen + 1 + VerStrLen + 1 + SerialNumStrLen+ 1);\r
+ UnicodeStrToAsciiStr(FamilyPtr, OptionalStrStart + ManuStrLen + 1 + PdNameStrLen + 1 + VerStrLen + 1 + SerialNumStrLen + 1 + SKUNumStrLen+ 1);\r
+\r
+ //\r
+ // Now we have got the full smbios record, call smbios protocol to add this record.\r
+ //\r
+ SmbiosHandle = SMBIOS_HANDLE_PI_RESERVED;\r
+ Status = Smbios-> Add(\r
+ Smbios,\r
+ NULL,\r
+ &SmbiosHandle,\r
+ (EFI_SMBIOS_TABLE_HEADER *) SmbiosRecord\r
+ );\r
+ FreePool(SmbiosRecord);\r
+ return Status;\r
+}\r
--- /dev/null
+// /** @file\r
+// Miscellaneous System Option Strings\r
+//\r
+// Copyright (c) 2013-2015 Intel Corporation.\r
+//\r
+// This program and the accompanying materials\r
+// are licensed and made available under the terms and conditions of the BSD License\r
+// which accompanies this distribution. The full text of the license may be found at\r
+// http://opensource.org/licenses/bsd-license.php\r
+//\r
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+//\r
+//\r
+// **/\r
+\r
+\r
+/=#\r
+\r
+#string STR_MISC_SYSTEM_OPTION_STRING #language en-US "J1D4:1-2,5-6,9-10Default;2-3CMOS clr,6-7Pswd clr,10-11Recovery"\r
--- /dev/null
+/** @file\r
+This driver parses the mSmbiosMiscDataTable structure and reports\r
+any generated data to smbios.\r
+\r
+Copyright (c) 2013-2015 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+**/\r
+\r
+\r
+#include "CommonHeader.h"\r
+\r
+#include "SmbiosMisc.h"\r
+\r
+\r
+//\r
+// Static (possibly build generated) Bios Vendor data.\r
+//\r
+MISC_SMBIOS_TABLE_DATA(EFI_MISC_SYSTEM_OPTION_STRING, SystemOptionString) = {\r
+ {STRING_TOKEN (STR_MISC_SYSTEM_OPTION_STRING)}\r
+};\r
--- /dev/null
+/** @file\r
+BIOS system option string boot time changes.\r
+SMBIOS type 12.\r
+\r
+Copyright (c) 2013-2015 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+**/\r
+\r
+\r
+#include "CommonHeader.h"\r
+#include "SmbiosMisc.h"\r
+\r
+\r
+/**\r
+ This function makes boot time changes to the contents of the\r
+ MiscSystemOptionString (Type 12).\r
+\r
+ @param RecordData Pointer to copy of RecordData from the Data Table.\r
+\r
+ @retval EFI_SUCCESS All parameters were valid.\r
+ @retval EFI_UNSUPPORTED Unexpected RecordType value.\r
+ @retval EFI_INVALID_PARAMETER Invalid parameter was found.\r
+\r
+**/\r
+MISC_SMBIOS_TABLE_FUNCTION(SystemOptionString)\r
+{\r
+ CHAR8 *OptionalStrStart;\r
+ UINTN OptStrLen;\r
+ EFI_STRING OptionString;\r
+ EFI_STATUS Status;\r
+ STRING_REF TokenToGet;\r
+ EFI_SMBIOS_HANDLE SmbiosHandle;\r
+ SMBIOS_TABLE_TYPE12 *SmbiosRecord;\r
+ EFI_MISC_SYSTEM_OPTION_STRING *ForType12InputData;\r
+\r
+ ForType12InputData = (EFI_MISC_SYSTEM_OPTION_STRING *)RecordData;\r
+\r
+ //\r
+ // First check for invalid parameters.\r
+ //\r
+ if (RecordData == NULL) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+\r
+ TokenToGet = STRING_TOKEN (STR_MISC_SYSTEM_OPTION_STRING);\r
+ OptionString = HiiGetPackageString(&gEfiCallerIdGuid, TokenToGet, NULL);\r
+ OptStrLen = StrLen(OptionString);\r
+ if (OptStrLen > SMBIOS_STRING_MAX_LENGTH) {\r
+ return EFI_UNSUPPORTED;\r
+ }\r
+\r
+ //\r
+ // Two zeros following the last string.\r
+ //\r
+ SmbiosRecord = AllocatePool(sizeof (SMBIOS_TABLE_TYPE12) + OptStrLen + 1 + 1);\r
+ ZeroMem(SmbiosRecord, sizeof (SMBIOS_TABLE_TYPE12) + OptStrLen + 1 + 1);\r
+\r
+ SmbiosRecord->Hdr.Type = EFI_SMBIOS_TYPE_SYSTEM_CONFIGURATION_OPTIONS;\r
+ SmbiosRecord->Hdr.Length = sizeof (SMBIOS_TABLE_TYPE12);\r
+ //\r
+ // Make handle chosen by smbios protocol.add automatically.\r
+ //\r
+ SmbiosRecord->Hdr.Handle = 0;\r
+\r
+ SmbiosRecord->StringCount = 1;\r
+ OptionalStrStart = (CHAR8*) (SmbiosRecord + 1);\r
+ UnicodeStrToAsciiStr(OptionString, OptionalStrStart);\r
+ //\r
+ // Now we have got the full smbios record, call smbios protocol to add this record.\r
+ //\r
+ SmbiosHandle = SMBIOS_HANDLE_PI_RESERVED;\r
+ Status = Smbios-> Add(\r
+ Smbios,\r
+ NULL,\r
+ &SmbiosHandle,\r
+ (EFI_SMBIOS_TABLE_HEADER *) SmbiosRecord\r
+ );\r
+\r
+ FreePool(SmbiosRecord);\r
+ return Status;\r
+}\r
--- /dev/null
+// /** @file\r
+// Miscellaneous Port Connector Information\r
+//\r
+// Copyright (c) 2013-2015 Intel Corporation.\r
+//\r
+// This program and the accompanying materials\r
+// are licensed and made available under the terms and conditions of the BSD License\r
+// which accompanies this distribution. The full text of the license may be found at\r
+// http://opensource.org/licenses/bsd-license.php\r
+//\r
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+//\r
+//\r
+// **/\r
+\r
+\r
+/=#\r
+\r
+#string STR_MISC_SYSTEM_SLOT1 #language en-US "SLOT1"\r
+#string STR_MISC_SYSTEM_SLOT2 #language en-US "SLOT2"\r
+#string STR_MISC_SYSTEM_SLOT3 #language en-US "SLOT3"\r
+#string STR_MISC_SYSTEM_SLOT4 #language en-US "SLOT4"\r
+#string STR_MISC_SYSTEM_SLOT5 #language en-US "SLOT5"\r
+#string STR_MISC_SYSTEM_SLOT6 #language en-US "SLOT6"\r
+#string STR_MISC_SYSTEM_SLOT7 #language en-US "SLOT7"\r
+#string STR_MISC_SYSTEM_SLOT8 #language en-US "SLOT8"\r
+#string STR_MISC_SYSTEM_SLOT9 #language en-US "SLOT9"\r
+#string STR_MISC_SYSTEM_SLOT10 #language en-US "SLOT10"\r
+#string STR_MISC_SYSTEM_SLOT11 #language en-US "SLOT11"\r
+#string STR_MISC_SYSTEM_SLOT12 #language en-US "SLOT12"\r
+#string STR_MISC_SYSTEM_SLOT13 #language en-US "SLOT13"\r
+#string STR_MISC_SYSTEM_SLOT14 #language en-US "SLOT14"\r
--- /dev/null
+/** @file\r
+This driver parses the mMiscSubclassDataTable structure and reports\r
+any generated data to the DataHub.\r
+\r
+Copyright (c) 2013-2015 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+**/\r
+\r
+\r
+#include "CommonHeader.h"\r
+\r
+#include "SmbiosMisc.h"\r
+\r
+\r
+//\r
+// Static (possibly build generated) Bios Vendor data.\r
+//\r
+MISC_SMBIOS_TABLE_DATA(EFI_MISC_SYSTEM_SLOT_DESIGNATION, MiscSystemSlot1) = {\r
+ STRING_TOKEN(STR_MISC_SYSTEM_SLOT1), // SlotDesignation\r
+ EfiSlotTypePci, // SlotType\r
+ EfiSlotDataBusWidth32Bit, // SlotDataBusWidth\r
+ EfiSlotUsageAvailable, // SlotUsage\r
+ EfiSlotLengthLong , // SlotLength\r
+ 1, // SlotId\r
+ { // SlotCharacteristics\r
+ 0, // CharacteristicsUnknown :1;\r
+ 0, // Provides50Volts :1;\r
+ 1, // Provides33Volts :1;\r
+ 0, // SharedSlot :1;\r
+ 0, // PcCard16Supported :1;\r
+ 0, // CardBusSupported :1;\r
+ 0, // ZoomVideoSupported :1;\r
+ 0, // ModemRingResumeSupported:1;\r
+ 1, // PmeSignalSupported :1;\r
+ 0, // HotPlugDevicesSupported :1;\r
+ 1, // SmbusSignalSupported :1;\r
+ 0 // Reserved :21;\r
+ },\r
+ {0} // SlotDevicePath\r
+};\r
+\r
+MISC_SMBIOS_TABLE_DATA(EFI_MISC_SYSTEM_SLOT_DESIGNATION, MiscSystemSlot2) = {\r
+ STRING_TOKEN(STR_MISC_SYSTEM_SLOT2), // SlotDesignation\r
+ EfiSlotTypePciExpress, // SlotType\r
+ EfiSlotDataBusWidth32Bit, // SlotDataBusWidth\r
+ EfiSlotUsageAvailable, // SlotUsage\r
+ EfiSlotLengthLong , // SlotLength\r
+ 1, // SlotId\r
+ { // SlotCharacteristics\r
+ 0, // CharacteristicsUnknown :1;\r
+ 0, // Provides50Volts :1;\r
+ 1, // Provides33Volts :1;\r
+ 0, // SharedSlot :1;\r
+ 0, // PcCard16Supported :1;\r
+ 0, // CardBusSupported :1;\r
+ 0, // ZoomVideoSupported :1;\r
+ 0, // ModemRingResumeSupported:1;\r
+ 1, // PmeSignalSupported :1;\r
+ 1, // HotPlugDevicesSupported :1;\r
+ 1, // SmbusSignalSupported :1;\r
+ 0 // Reserved :21;\r
+ },\r
+ {0} // SlotDevicePath\r
+};\r
+\r
+MISC_SMBIOS_TABLE_DATA(EFI_MISC_SYSTEM_SLOT_DESIGNATION, MiscSystemSlot3) = {\r
+ STRING_TOKEN(STR_MISC_SYSTEM_SLOT3), // SlotDesignation\r
+ EfiSlotTypePciExpress, // SlotType\r
+ EfiSlotDataBusWidth32Bit, // SlotDataBusWidth\r
+ EfiSlotUsageAvailable, // SlotUsage\r
+ EfiSlotLengthLong , // SlotLength\r
+ 2, // SlotId\r
+ { // SlotCharacteristics\r
+ 0, // CharacteristicsUnknown :1;\r
+ 0, // Provides50Volts :1;\r
+ 1, // Provides33Volts :1;\r
+ 0, // SharedSlot :1;\r
+ 0, // PcCard16Supported :1;\r
+ 0, // CardBusSupported :1;\r
+ 0, // ZoomVideoSupported :1;\r
+ 0, // ModemRingResumeSupported:1;\r
+ 1, // PmeSignalSupported :1;\r
+ 1, // HotPlugDevicesSupported :1;\r
+ 1, // SmbusSignalSupported :1;\r
+ 0 // Reserved :21;\r
+ },\r
+ {0} // SlotDevicePath\r
+};\r
+\r
+MISC_SMBIOS_TABLE_DATA(EFI_MISC_SYSTEM_SLOT_DESIGNATION, MiscSystemSlot4) = {\r
+ STRING_TOKEN(STR_MISC_SYSTEM_SLOT4), // SlotDesignation\r
+ EfiSlotTypePciExpress, // SlotType\r
+ EfiSlotDataBusWidth32Bit, // SlotDataBusWidth\r
+ EfiSlotUsageAvailable, // SlotUsage\r
+ EfiSlotLengthLong , // SlotLength\r
+ 2, // SlotId\r
+ { // SlotCharacteristics\r
+ 0, // CharacteristicsUnknown :1;\r
+ 0, // Provides50Volts :1;\r
+ 1, // Provides33Volts :1;\r
+ 0, // SharedSlot :1;\r
+ 0, // PcCard16Supported :1;\r
+ 0, // CardBusSupported :1;\r
+ 0, // ZoomVideoSupported :1;\r
+ 0, // ModemRingResumeSupported:1;\r
+ 1, // PmeSignalSupported :1;\r
+ 1, // HotPlugDevicesSupported :1;\r
+ 1, // SmbusSignalSupported :1;\r
+ 0 // Reserved :21;\r
+ },\r
+ {0} // SlotDevicePath\r
+};\r
+\r
+MISC_SMBIOS_TABLE_DATA(EFI_MISC_SYSTEM_SLOT_DESIGNATION, MiscSystemSlot5) = {\r
+ STRING_TOKEN(STR_MISC_SYSTEM_SLOT5), // SlotDesignation\r
+ EfiSlotTypePciExpress, // SlotType\r
+ EfiSlotDataBusWidth32Bit, // SlotDataBusWidth\r
+ EfiSlotUsageAvailable, // SlotUsage\r
+ EfiSlotLengthLong , // SlotLength\r
+ 3, // SlotId\r
+ { // SlotCharacteristics\r
+ 0, // CharacteristicsUnknown :1;\r
+ 0, // Provides50Volts :1;\r
+ 1, // Provides33Volts :1;\r
+ 0, // SharedSlot :1;\r
+ 0, // PcCard16Supported :1;\r
+ 0, // CardBusSupported :1;\r
+ 0, // ZoomVideoSupported :1;\r
+ 0, // ModemRingResumeSupported:1;\r
+ 1, // PmeSignalSupported :1;\r
+ 1, // HotPlugDevicesSupported :1;\r
+ 1, // SmbusSignalSupported :1;\r
+ 0 // Reserved :21;\r
+ },\r
+ {0} // SlotDevicePath\r
+};\r
+\r
+MISC_SMBIOS_TABLE_DATA(EFI_MISC_SYSTEM_SLOT_DESIGNATION, MiscSystemSlot6) = {\r
+ STRING_TOKEN(STR_MISC_SYSTEM_SLOT6), // SlotDesignation\r
+ EfiSlotTypePciExpress, // SlotType\r
+ EfiSlotDataBusWidth32Bit, // SlotDataBusWidth\r
+ EfiSlotUsageAvailable, // SlotUsage\r
+ EfiSlotLengthLong , // SlotLength\r
+ 3, // SlotId\r
+ { // SlotCharacteristics\r
+ 0, // CharacteristicsUnknown :1;\r
+ 0, // Provides50Volts :1;\r
+ 1, // Provides33Volts :1;\r
+ 0, // SharedSlot :1;\r
+ 0, // PcCard16Supported :1;\r
+ 0, // CardBusSupported :1;\r
+ 0, // ZoomVideoSupported :1;\r
+ 0, // ModemRingResumeSupported:1;\r
+ 1, // PmeSignalSupported :1;\r
+ 1, // HotPlugDevicesSupported :1;\r
+ 1, // SmbusSignalSupported :1;\r
+ 0 // Reserved :21;\r
+ },\r
+ {0} // SlotDevicePath\r
+};\r
+\r
+MISC_SMBIOS_TABLE_DATA(EFI_MISC_SYSTEM_SLOT_DESIGNATION, MiscSystemSlot7) = {\r
+ STRING_TOKEN(STR_MISC_SYSTEM_SLOT7), // SlotDesignation\r
+ EfiSlotTypePciExpress, // SlotType\r
+ EfiSlotDataBusWidth32Bit, // SlotDataBusWidth\r
+ EfiSlotUsageAvailable, // SlotUsage\r
+ EfiSlotLengthLong , // SlotLength\r
+ 3, // SlotId\r
+ { // SlotCharacteristics\r
+ 0, // CharacteristicsUnknown :1;\r
+ 0, // Provides50Volts :1;\r
+ 1, // Provides33Volts :1;\r
+ 0, // SharedSlot :1;\r
+ 0, // PcCard16Supported :1;\r
+ 0, // CardBusSupported :1;\r
+ 0, // ZoomVideoSupported :1;\r
+ 0, // ModemRingResumeSupported:1;\r
+ 1, // PmeSignalSupported :1;\r
+ 1, // HotPlugDevicesSupported :1;\r
+ 1, // SmbusSignalSupported :1;\r
+ 0 // Reserved :21;\r
+ },\r
+ {0} // SlotDevicePath\r
+};\r
+\r
+MISC_SMBIOS_TABLE_DATA(EFI_MISC_SYSTEM_SLOT_DESIGNATION, MiscSystemSlot8) = {\r
+ STRING_TOKEN(STR_MISC_SYSTEM_SLOT8), // SlotDesignation\r
+ EfiSlotTypePciExpress, // SlotType\r
+ EfiSlotDataBusWidth32Bit, // SlotDataBusWidth\r
+ EfiSlotUsageAvailable, // SlotUsage\r
+ EfiSlotLengthLong , // SlotLength\r
+ 3, // SlotId\r
+ { // SlotCharacteristics\r
+ 0, // CharacteristicsUnknown :1;\r
+ 0, // Provides50Volts :1;\r
+ 1, // Provides33Volts :1;\r
+ 0, // SharedSlot :1;\r
+ 0, // PcCard16Supported :1;\r
+ 0, // CardBusSupported :1;\r
+ 0, // ZoomVideoSupported :1;\r
+ 0, // ModemRingResumeSupported:1;\r
+ 1, // PmeSignalSupported :1;\r
+ 1, // HotPlugDevicesSupported :1;\r
+ 1, // SmbusSignalSupported :1;\r
+ 0 // Reserved :21;\r
+ },\r
+ {0} // SlotDevicePath\r
+};\r
+\r
+MISC_SMBIOS_TABLE_DATA(EFI_MISC_SYSTEM_SLOT_DESIGNATION, MiscSystemSlot9) = {\r
+ STRING_TOKEN(STR_MISC_SYSTEM_SLOT9), // SlotDesignation\r
+ EfiSlotTypeUnknown, // SlotType\r
+ EfiSlotDataBusWidthUnknown, // SlotDataBusWidth\r
+ EfiSlotUsageUnknown, // SlotUsage\r
+ EfiSlotLengthUnknown , // SlotLength\r
+ 0, // SlotId\r
+ { // SlotCharacteristics\r
+ 0, // CharacteristicsUnknown :1;\r
+ 0, // Provides50Volts :1;\r
+ 1, // Provides33Volts :1;\r
+ 0, // SharedSlot :1;\r
+ 0, // PcCard16Supported :1;\r
+ 0, // CardBusSupported :1;\r
+ 0, // ZoomVideoSupported :1;\r
+ 0, // ModemRingResumeSupported:1;\r
+ 1, // PmeSignalSupported :1;\r
+ 1, // HotPlugDevicesSupported :1;\r
+ 1, // SmbusSignalSupported :1;\r
+ 0 // Reserved :21;\r
+ },\r
+ {0} // SlotDevicePath\r
+};\r
+\r
+MISC_SMBIOS_TABLE_DATA(EFI_MISC_SYSTEM_SLOT_DESIGNATION, MiscSystemSlot10) = {\r
+ STRING_TOKEN(STR_MISC_SYSTEM_SLOT10), // SlotDesignation\r
+ EfiSlotTypeUnknown, // SlotType\r
+ EfiSlotDataBusWidthUnknown, // SlotDataBusWidth\r
+ EfiSlotUsageUnknown, // SlotUsage\r
+ EfiSlotLengthUnknown , // SlotLength\r
+ 0, // SlotId\r
+ { // SlotCharacteristics\r
+ 0, // CharacteristicsUnknown :1;\r
+ 0, // Provides50Volts :1;\r
+ 1, // Provides33Volts :1;\r
+ 0, // SharedSlot :1;\r
+ 0, // PcCard16Supported :1;\r
+ 0, // CardBusSupported :1;\r
+ 0, // ZoomVideoSupported :1;\r
+ 0, // ModemRingResumeSupported:1;\r
+ 1, // PmeSignalSupported :1;\r
+ 1, // HotPlugDevicesSupported :1;\r
+ 1, // SmbusSignalSupported :1;\r
+ 0 // Reserved :21;\r
+ },\r
+ {0} // SlotDevicePath\r
+};\r
+\r
+MISC_SMBIOS_TABLE_DATA(EFI_MISC_SYSTEM_SLOT_DESIGNATION, MiscSystemSlot11) = {\r
+ STRING_TOKEN(STR_MISC_SYSTEM_SLOT11), // SlotDesignation\r
+ EfiSlotTypeUnknown, // SlotType\r
+ EfiSlotDataBusWidthUnknown, // SlotDataBusWidth\r
+ EfiSlotUsageUnknown, // SlotUsage\r
+ EfiSlotLengthUnknown , // SlotLength\r
+ 0, // SlotId\r
+ { // SlotCharacteristics\r
+ 0, // CharacteristicsUnknown :1;\r
+ 0, // Provides50Volts :1;\r
+ 1, // Provides33Volts :1;\r
+ 0, // SharedSlot :1;\r
+ 0, // PcCard16Supported :1;\r
+ 0, // CardBusSupported :1;\r
+ 0, // ZoomVideoSupported :1;\r
+ 0, // ModemRingResumeSupported:1;\r
+ 1, // PmeSignalSupported :1;\r
+ 1, // HotPlugDevicesSupported :1;\r
+ 1, // SmbusSignalSupported :1;\r
+ 0 // Reserved :21;\r
+ },\r
+ {0} // SlotDevicePath\r
+};\r
+\r
+MISC_SMBIOS_TABLE_DATA(EFI_MISC_SYSTEM_SLOT_DESIGNATION, MiscSystemSlot12) = {\r
+ STRING_TOKEN(STR_MISC_SYSTEM_SLOT12), // SlotDesignation\r
+ EfiSlotTypeUnknown, // SlotType\r
+ EfiSlotDataBusWidthUnknown, // SlotDataBusWidth\r
+ EfiSlotUsageUnknown, // SlotUsage\r
+ EfiSlotLengthUnknown , // SlotLength\r
+ 0, // SlotId\r
+ { // SlotCharacteristics\r
+ 0, // CharacteristicsUnknown :1;\r
+ 0, // Provides50Volts :1;\r
+ 1, // Provides33Volts :1;\r
+ 0, // SharedSlot :1;\r
+ 0, // PcCard16Supported :1;\r
+ 0, // CardBusSupported :1;\r
+ 0, // ZoomVideoSupported :1;\r
+ 0, // ModemRingResumeSupported:1;\r
+ 1, // PmeSignalSupported :1;\r
+ 1, // HotPlugDevicesSupported :1;\r
+ 1, // SmbusSignalSupported :1;\r
+ 0 // Reserved :21;\r
+ },\r
+ {0} // SlotDevicePath\r
+};\r
+\r
+MISC_SMBIOS_TABLE_DATA(EFI_MISC_SYSTEM_SLOT_DESIGNATION, MiscSystemSlot13) = {\r
+ STRING_TOKEN(STR_MISC_SYSTEM_SLOT13), // SlotDesignation\r
+ EfiSlotTypeUnknown, // SlotType\r
+ EfiSlotDataBusWidthUnknown, // SlotDataBusWidth\r
+ EfiSlotUsageUnknown, // SlotUsage\r
+ EfiSlotLengthUnknown , // SlotLength\r
+ 0, // SlotId\r
+ { // SlotCharacteristics\r
+ 0, // CharacteristicsUnknown :1;\r
+ 0, // Provides50Volts :1;\r
+ 1, // Provides33Volts :1;\r
+ 0, // SharedSlot :1;\r
+ 0, // PcCard16Supported :1;\r
+ 0, // CardBusSupported :1;\r
+ 0, // ZoomVideoSupported :1;\r
+ 0, // ModemRingResumeSupported:1;\r
+ 1, // PmeSignalSupported :1;\r
+ 1, // HotPlugDevicesSupported :1;\r
+ 1, // SmbusSignalSupported :1;\r
+ 0 // Reserved :21;\r
+ },\r
+ {0} // SlotDevicePath\r
+};\r
+\r
+MISC_SMBIOS_TABLE_DATA(EFI_MISC_SYSTEM_SLOT_DESIGNATION, MiscSystemSlot14) = {\r
+ STRING_TOKEN(STR_MISC_SYSTEM_SLOT14), // SlotDesignation\r
+ EfiSlotTypeUnknown, // SlotType\r
+ EfiSlotDataBusWidthUnknown, // SlotDataBusWidth\r
+ EfiSlotUsageUnknown, // SlotUsage\r
+ EfiSlotLengthUnknown , // SlotLength\r
+ 0, // SlotId\r
+ { // SlotCharacteristics\r
+ 0, // CharacteristicsUnknown :1;\r
+ 0, // Provides50Volts :1;\r
+ 1, // Provides33Volts :1;\r
+ 0, // SharedSlot :1;\r
+ 0, // PcCard16Supported :1;\r
+ 0, // CardBusSupported :1;\r
+ 0, // ZoomVideoSupported :1;\r
+ 0, // ModemRingResumeSupported:1;\r
+ 1, // PmeSignalSupported :1;\r
+ 1, // HotPlugDevicesSupported :1;\r
+ 1, // SmbusSignalSupported :1;\r
+ 0 // Reserved :21;\r
+ },\r
+ {0} // SlotDevicePath\r
+};\r
+\r
+\r
--- /dev/null
+/** @file\r
+BIOS system slot designator information boot time changes.\r
+SMBIOS type 9.\r
+\r
+Copyright (c) 2013-2015 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+MiscSystemSlotDesignatorFunction.c\r
+\r
+**/\r
+\r
+\r
+#include "CommonHeader.h"\r
+\r
+#include "SmbiosMisc.h"\r
+\r
+//\r
+//\r
+//\r
+\r
+MISC_SMBIOS_DATA_TABLE_EXTERNS (EFI_MISC_SYSTEM_SLOT_DESIGNATION, MiscSystemSlot1);\r
+MISC_SMBIOS_DATA_TABLE_EXTERNS (EFI_MISC_SYSTEM_SLOT_DESIGNATION, MiscSystemSlot2);\r
+MISC_SMBIOS_DATA_TABLE_EXTERNS (EFI_MISC_SYSTEM_SLOT_DESIGNATION, MiscSystemSlot3);\r
+MISC_SMBIOS_DATA_TABLE_EXTERNS (EFI_MISC_SYSTEM_SLOT_DESIGNATION, MiscSystemSlot4);\r
+MISC_SMBIOS_DATA_TABLE_EXTERNS (EFI_MISC_SYSTEM_SLOT_DESIGNATION, MiscSystemSlot5);\r
+MISC_SMBIOS_DATA_TABLE_EXTERNS (EFI_MISC_SYSTEM_SLOT_DESIGNATION, MiscSystemSlot6);\r
+MISC_SMBIOS_DATA_TABLE_EXTERNS (EFI_MISC_SYSTEM_SLOT_DESIGNATION, MiscSystemSlot7);\r
+MISC_SMBIOS_DATA_TABLE_EXTERNS (EFI_MISC_SYSTEM_SLOT_DESIGNATION, MiscSystemSlot8);\r
+MISC_SMBIOS_DATA_TABLE_EXTERNS (EFI_MISC_SYSTEM_SLOT_DESIGNATION, MiscSystemSlot9);\r
+MISC_SMBIOS_DATA_TABLE_EXTERNS (EFI_MISC_SYSTEM_SLOT_DESIGNATION, MiscSystemSlot10);\r
+MISC_SMBIOS_DATA_TABLE_EXTERNS (EFI_MISC_SYSTEM_SLOT_DESIGNATION, MiscSystemSlot11);\r
+MISC_SMBIOS_DATA_TABLE_EXTERNS (EFI_MISC_SYSTEM_SLOT_DESIGNATION, MiscSystemSlot12);\r
+MISC_SMBIOS_DATA_TABLE_EXTERNS (EFI_MISC_SYSTEM_SLOT_DESIGNATION, MiscSystemSlot13);\r
+MISC_SMBIOS_DATA_TABLE_EXTERNS (EFI_MISC_SYSTEM_SLOT_DESIGNATION, MiscSystemSlot14);\r
+\r
+EFI_MISC_SYSTEM_SLOT_DESIGNATION *mMiscSlotArray[SMBIOS_SYSTEM_SLOT_MAX_NUM] =\r
+{\r
+ MISC_SMBIOS_DATA_TABLE_POINTER (MiscSystemSlot1),\r
+ MISC_SMBIOS_DATA_TABLE_POINTER (MiscSystemSlot2),\r
+ MISC_SMBIOS_DATA_TABLE_POINTER (MiscSystemSlot3),\r
+ MISC_SMBIOS_DATA_TABLE_POINTER (MiscSystemSlot4),\r
+ MISC_SMBIOS_DATA_TABLE_POINTER (MiscSystemSlot5),\r
+ MISC_SMBIOS_DATA_TABLE_POINTER (MiscSystemSlot6),\r
+ MISC_SMBIOS_DATA_TABLE_POINTER (MiscSystemSlot7),\r
+ MISC_SMBIOS_DATA_TABLE_POINTER (MiscSystemSlot8),\r
+ MISC_SMBIOS_DATA_TABLE_POINTER (MiscSystemSlot9),\r
+ MISC_SMBIOS_DATA_TABLE_POINTER (MiscSystemSlot10),\r
+ MISC_SMBIOS_DATA_TABLE_POINTER (MiscSystemSlot11),\r
+ MISC_SMBIOS_DATA_TABLE_POINTER (MiscSystemSlot12),\r
+ MISC_SMBIOS_DATA_TABLE_POINTER (MiscSystemSlot13),\r
+ MISC_SMBIOS_DATA_TABLE_POINTER (MiscSystemSlot14),\r
+};\r
+\r
+BOOLEAN PcdMiscSlotIsInit = FALSE;\r
+SMBIOS_SLOT_COFNIG SMBIOSlotConfig = {0};\r
+\r
+/**\r
+ Get Misc Slot Configuration information from PCD\r
+ @param SMBIOSPortConnector Pointer to SMBIOSPortConnector table.\r
+\r
+**/\r
+\r
+VOID\r
+GetMiscSLotConfigFromPcd ()\r
+{\r
+ //\r
+ // Type 9\r
+ //\r
+ SMBIOSlotConfig.SMBIOSSystemSlotNumber = PcdGet8 (PcdSMBIOSSystemSlotNumber);\r
+ AsciiStrToUnicodeStr ((CHAR8 *) PcdGetPtr(PcdSMBIOSSystemSlot1Designation), SMBIOSlotConfig.SMBIOSSystemSlot[0].SlotDesignation);\r
+ SMBIOSlotConfig.SMBIOSSystemSlot[0].SlotType = PcdGet8(PcdSMBIOSSystemSlot1Type);\r
+ SMBIOSlotConfig.SMBIOSSystemSlot[0].SlotDataBusWidth = PcdGet8(PcdSMBIOSSystemSlot1DataBusWidth);\r
+ SMBIOSlotConfig.SMBIOSSystemSlot[0].SlotUsage = PcdGet8(PcdSMBIOSSystemSlot1Usage);\r
+ SMBIOSlotConfig.SMBIOSSystemSlot[0].SlotLength = PcdGet8(PcdSMBIOSSystemSlot1Length);\r
+ SMBIOSlotConfig.SMBIOSSystemSlot[0].SlotId = PcdGet16(PcdSMBIOSSystemSlot1Id);\r
+ SMBIOSlotConfig.SMBIOSSystemSlot[0].SlotCharacteristics = PcdGet32(PcdSMBIOSSystemSlot1Characteristics);\r
+\r
+ AsciiStrToUnicodeStr ((CHAR8 *) PcdGetPtr(PcdSMBIOSSystemSlot2Designation), SMBIOSlotConfig.SMBIOSSystemSlot[1].SlotDesignation);\r
+ SMBIOSlotConfig.SMBIOSSystemSlot[1].SlotType = PcdGet8(PcdSMBIOSSystemSlot2Type);\r
+ SMBIOSlotConfig.SMBIOSSystemSlot[1].SlotDataBusWidth = PcdGet8(PcdSMBIOSSystemSlot2DataBusWidth);\r
+ SMBIOSlotConfig.SMBIOSSystemSlot[1].SlotUsage = PcdGet8(PcdSMBIOSSystemSlot2Usage);\r
+ SMBIOSlotConfig.SMBIOSSystemSlot[1].SlotLength = PcdGet8(PcdSMBIOSSystemSlot2Length);\r
+ SMBIOSlotConfig.SMBIOSSystemSlot[1].SlotId = PcdGet16(PcdSMBIOSSystemSlot2Id);\r
+ SMBIOSlotConfig.SMBIOSSystemSlot[1].SlotCharacteristics = PcdGet32(PcdSMBIOSSystemSlot2Characteristics);\r
+\r
+ AsciiStrToUnicodeStr ((CHAR8 *) PcdGetPtr(PcdSMBIOSSystemSlot3Designation), SMBIOSlotConfig.SMBIOSSystemSlot[2].SlotDesignation);\r
+ SMBIOSlotConfig.SMBIOSSystemSlot[2].SlotType = PcdGet8(PcdSMBIOSSystemSlot3Type);\r
+ SMBIOSlotConfig.SMBIOSSystemSlot[2].SlotDataBusWidth = PcdGet8(PcdSMBIOSSystemSlot3DataBusWidth);\r
+ SMBIOSlotConfig.SMBIOSSystemSlot[2].SlotUsage = PcdGet8(PcdSMBIOSSystemSlot3Usage);\r
+ SMBIOSlotConfig.SMBIOSSystemSlot[2].SlotLength = PcdGet8(PcdSMBIOSSystemSlot3Length);\r
+ SMBIOSlotConfig.SMBIOSSystemSlot[2].SlotId = PcdGet16(PcdSMBIOSSystemSlot3Id);\r
+ SMBIOSlotConfig.SMBIOSSystemSlot[2].SlotCharacteristics = PcdGet32(PcdSMBIOSSystemSlot3Characteristics);\r
+\r
+ AsciiStrToUnicodeStr ((CHAR8 *) PcdGetPtr(PcdSMBIOSSystemSlot4Designation), SMBIOSlotConfig.SMBIOSSystemSlot[3].SlotDesignation);\r
+ SMBIOSlotConfig.SMBIOSSystemSlot[3].SlotType = PcdGet8(PcdSMBIOSSystemSlot4Type);\r
+ SMBIOSlotConfig.SMBIOSSystemSlot[3].SlotDataBusWidth = PcdGet8(PcdSMBIOSSystemSlot4DataBusWidth);\r
+ SMBIOSlotConfig.SMBIOSSystemSlot[3].SlotUsage = PcdGet8(PcdSMBIOSSystemSlot4Usage);\r
+ SMBIOSlotConfig.SMBIOSSystemSlot[3].SlotLength = PcdGet8(PcdSMBIOSSystemSlot4Length);\r
+ SMBIOSlotConfig.SMBIOSSystemSlot[3].SlotId = PcdGet16(PcdSMBIOSSystemSlot4Id);\r
+ SMBIOSlotConfig.SMBIOSSystemSlot[3].SlotCharacteristics = PcdGet32(PcdSMBIOSSystemSlot4Characteristics);\r
+\r
+ AsciiStrToUnicodeStr ((CHAR8 *) PcdGetPtr(PcdSMBIOSSystemSlot5Designation), SMBIOSlotConfig.SMBIOSSystemSlot[4].SlotDesignation);\r
+ SMBIOSlotConfig.SMBIOSSystemSlot[4].SlotType = PcdGet8(PcdSMBIOSSystemSlot5Type);\r
+ SMBIOSlotConfig.SMBIOSSystemSlot[4].SlotDataBusWidth = PcdGet8(PcdSMBIOSSystemSlot5DataBusWidth);\r
+ SMBIOSlotConfig.SMBIOSSystemSlot[4].SlotUsage = PcdGet8(PcdSMBIOSSystemSlot5Usage);\r
+ SMBIOSlotConfig.SMBIOSSystemSlot[4].SlotLength = PcdGet8(PcdSMBIOSSystemSlot5Length);\r
+ SMBIOSlotConfig.SMBIOSSystemSlot[4].SlotId = PcdGet16(PcdSMBIOSSystemSlot5Id);\r
+ SMBIOSlotConfig.SMBIOSSystemSlot[4].SlotCharacteristics = PcdGet32(PcdSMBIOSSystemSlot5Characteristics);\r
+\r
+ AsciiStrToUnicodeStr ((CHAR8 *) PcdGetPtr(PcdSMBIOSSystemSlot6Designation), SMBIOSlotConfig.SMBIOSSystemSlot[5].SlotDesignation);\r
+ SMBIOSlotConfig.SMBIOSSystemSlot[5].SlotType = PcdGet8(PcdSMBIOSSystemSlot6Type);\r
+ SMBIOSlotConfig.SMBIOSSystemSlot[5].SlotDataBusWidth = PcdGet8(PcdSMBIOSSystemSlot6DataBusWidth);\r
+ SMBIOSlotConfig.SMBIOSSystemSlot[5].SlotUsage = PcdGet8(PcdSMBIOSSystemSlot6Usage);\r
+ SMBIOSlotConfig.SMBIOSSystemSlot[5].SlotLength = PcdGet8(PcdSMBIOSSystemSlot6Length);\r
+ SMBIOSlotConfig.SMBIOSSystemSlot[5].SlotId = PcdGet16(PcdSMBIOSSystemSlot6Id);\r
+ SMBIOSlotConfig.SMBIOSSystemSlot[5].SlotCharacteristics = PcdGet32(PcdSMBIOSSystemSlot6Characteristics);\r
+\r
+ AsciiStrToUnicodeStr ((CHAR8 *) PcdGetPtr(PcdSMBIOSSystemSlot7Designation), SMBIOSlotConfig.SMBIOSSystemSlot[6].SlotDesignation);\r
+ SMBIOSlotConfig.SMBIOSSystemSlot[6].SlotType = PcdGet8(PcdSMBIOSSystemSlot7Type);\r
+ SMBIOSlotConfig.SMBIOSSystemSlot[6].SlotDataBusWidth = PcdGet8(PcdSMBIOSSystemSlot7DataBusWidth);\r
+ SMBIOSlotConfig.SMBIOSSystemSlot[6].SlotUsage = PcdGet8(PcdSMBIOSSystemSlot7Usage);\r
+ SMBIOSlotConfig.SMBIOSSystemSlot[6].SlotLength = PcdGet8(PcdSMBIOSSystemSlot7Length);\r
+ SMBIOSlotConfig.SMBIOSSystemSlot[6].SlotId = PcdGet16(PcdSMBIOSSystemSlot7Id);\r
+ SMBIOSlotConfig.SMBIOSSystemSlot[6].SlotCharacteristics = PcdGet32(PcdSMBIOSSystemSlot7Characteristics);\r
+\r
+ AsciiStrToUnicodeStr ((CHAR8 *) PcdGetPtr(PcdSMBIOSSystemSlot8Designation), SMBIOSlotConfig.SMBIOSSystemSlot[7].SlotDesignation);\r
+ SMBIOSlotConfig.SMBIOSSystemSlot[7].SlotType = PcdGet8(PcdSMBIOSSystemSlot8Type);\r
+ SMBIOSlotConfig.SMBIOSSystemSlot[7].SlotDataBusWidth = PcdGet8(PcdSMBIOSSystemSlot8DataBusWidth);\r
+ SMBIOSlotConfig.SMBIOSSystemSlot[7].SlotUsage = PcdGet8(PcdSMBIOSSystemSlot8Usage);\r
+ SMBIOSlotConfig.SMBIOSSystemSlot[7].SlotLength = PcdGet8(PcdSMBIOSSystemSlot8Length);\r
+ SMBIOSlotConfig.SMBIOSSystemSlot[7].SlotId = PcdGet16(PcdSMBIOSSystemSlot8Id);\r
+ SMBIOSlotConfig.SMBIOSSystemSlot[7].SlotCharacteristics = PcdGet32(PcdSMBIOSSystemSlot8Characteristics);\r
+\r
+ AsciiStrToUnicodeStr ((CHAR8 *) PcdGetPtr(PcdSMBIOSSystemSlot9Designation), SMBIOSlotConfig.SMBIOSSystemSlot[8].SlotDesignation);\r
+ SMBIOSlotConfig.SMBIOSSystemSlot[8].SlotType = PcdGet8(PcdSMBIOSSystemSlot9Type);\r
+ SMBIOSlotConfig.SMBIOSSystemSlot[8].SlotDataBusWidth = PcdGet8(PcdSMBIOSSystemSlot9DataBusWidth);\r
+ SMBIOSlotConfig.SMBIOSSystemSlot[8].SlotUsage = PcdGet8(PcdSMBIOSSystemSlot9Usage);\r
+ SMBIOSlotConfig.SMBIOSSystemSlot[8].SlotLength = PcdGet8(PcdSMBIOSSystemSlot9Length);\r
+ SMBIOSlotConfig.SMBIOSSystemSlot[8].SlotId = PcdGet16(PcdSMBIOSSystemSlot9Id);\r
+ SMBIOSlotConfig.SMBIOSSystemSlot[8].SlotCharacteristics = PcdGet32(PcdSMBIOSSystemSlot9Characteristics);\r
+\r
+ AsciiStrToUnicodeStr ((CHAR8 *) PcdGetPtr(PcdSMBIOSSystemSlot10Designation), SMBIOSlotConfig.SMBIOSSystemSlot[9].SlotDesignation);\r
+ SMBIOSlotConfig.SMBIOSSystemSlot[9].SlotType = PcdGet8(PcdSMBIOSSystemSlot10Type);\r
+ SMBIOSlotConfig.SMBIOSSystemSlot[9].SlotDataBusWidth = PcdGet8(PcdSMBIOSSystemSlot10DataBusWidth);\r
+ SMBIOSlotConfig.SMBIOSSystemSlot[9].SlotUsage = PcdGet8(PcdSMBIOSSystemSlot10Usage);\r
+ SMBIOSlotConfig.SMBIOSSystemSlot[9].SlotLength = PcdGet8(PcdSMBIOSSystemSlot10Length);\r
+ SMBIOSlotConfig.SMBIOSSystemSlot[9].SlotId = PcdGet16(PcdSMBIOSSystemSlot10Id);\r
+ SMBIOSlotConfig.SMBIOSSystemSlot[9].SlotCharacteristics = PcdGet32(PcdSMBIOSSystemSlot10Characteristics);\r
+\r
+ AsciiStrToUnicodeStr ((CHAR8 *) PcdGetPtr(PcdSMBIOSSystemSlot11Designation), SMBIOSlotConfig.SMBIOSSystemSlot[10].SlotDesignation);\r
+ SMBIOSlotConfig.SMBIOSSystemSlot[10].SlotType = PcdGet8(PcdSMBIOSSystemSlot11Type);\r
+ SMBIOSlotConfig.SMBIOSSystemSlot[10].SlotDataBusWidth = PcdGet8(PcdSMBIOSSystemSlot11DataBusWidth);\r
+ SMBIOSlotConfig.SMBIOSSystemSlot[10].SlotUsage = PcdGet8(PcdSMBIOSSystemSlot11Usage);\r
+ SMBIOSlotConfig.SMBIOSSystemSlot[10].SlotLength = PcdGet8(PcdSMBIOSSystemSlot11Length);\r
+ SMBIOSlotConfig.SMBIOSSystemSlot[10].SlotId = PcdGet16(PcdSMBIOSSystemSlot11Id);\r
+ SMBIOSlotConfig.SMBIOSSystemSlot[10].SlotCharacteristics = PcdGet32(PcdSMBIOSSystemSlot11Characteristics);\r
+\r
+ AsciiStrToUnicodeStr ((CHAR8 *) PcdGetPtr(PcdSMBIOSSystemSlot12Designation), SMBIOSlotConfig.SMBIOSSystemSlot[11].SlotDesignation);\r
+ SMBIOSlotConfig.SMBIOSSystemSlot[11].SlotType = PcdGet8(PcdSMBIOSSystemSlot12Type);\r
+ SMBIOSlotConfig.SMBIOSSystemSlot[11].SlotDataBusWidth = PcdGet8(PcdSMBIOSSystemSlot12DataBusWidth);\r
+ SMBIOSlotConfig.SMBIOSSystemSlot[11].SlotUsage = PcdGet8(PcdSMBIOSSystemSlot12Usage);\r
+ SMBIOSlotConfig.SMBIOSSystemSlot[11].SlotLength = PcdGet8(PcdSMBIOSSystemSlot12Length);\r
+ SMBIOSlotConfig.SMBIOSSystemSlot[11].SlotId = PcdGet16(PcdSMBIOSSystemSlot12Id);\r
+ SMBIOSlotConfig.SMBIOSSystemSlot[11].SlotCharacteristics = PcdGet32(PcdSMBIOSSystemSlot12Characteristics);\r
+\r
+ AsciiStrToUnicodeStr ((CHAR8 *) PcdGetPtr(PcdSMBIOSSystemSlot13Designation), SMBIOSlotConfig.SMBIOSSystemSlot[12].SlotDesignation);\r
+ SMBIOSlotConfig.SMBIOSSystemSlot[12].SlotType = PcdGet8(PcdSMBIOSSystemSlot13Type);\r
+ SMBIOSlotConfig.SMBIOSSystemSlot[12].SlotDataBusWidth = PcdGet8(PcdSMBIOSSystemSlot13DataBusWidth);\r
+ SMBIOSlotConfig.SMBIOSSystemSlot[12].SlotUsage = PcdGet8(PcdSMBIOSSystemSlot13Usage);\r
+ SMBIOSlotConfig.SMBIOSSystemSlot[12].SlotLength = PcdGet8(PcdSMBIOSSystemSlot13Length);\r
+ SMBIOSlotConfig.SMBIOSSystemSlot[12].SlotId = PcdGet16(PcdSMBIOSSystemSlot13Id);\r
+ SMBIOSlotConfig.SMBIOSSystemSlot[12].SlotCharacteristics = PcdGet32(PcdSMBIOSSystemSlot13Characteristics);\r
+\r
+ AsciiStrToUnicodeStr ((CHAR8 *) PcdGetPtr(PcdSMBIOSSystemSlot14Designation), SMBIOSlotConfig.SMBIOSSystemSlot[13].SlotDesignation);\r
+ SMBIOSlotConfig.SMBIOSSystemSlot[13].SlotType = PcdGet8(PcdSMBIOSSystemSlot14Type);\r
+ SMBIOSlotConfig.SMBIOSSystemSlot[13].SlotDataBusWidth = PcdGet8(PcdSMBIOSSystemSlot14DataBusWidth);\r
+ SMBIOSlotConfig.SMBIOSSystemSlot[13].SlotUsage = PcdGet8(PcdSMBIOSSystemSlot14Usage);\r
+ SMBIOSlotConfig.SMBIOSSystemSlot[13].SlotLength = PcdGet8(PcdSMBIOSSystemSlot14Length);\r
+ SMBIOSlotConfig.SMBIOSSystemSlot[13].SlotId = PcdGet16(PcdSMBIOSSystemSlot14Id);\r
+ SMBIOSlotConfig.SMBIOSSystemSlot[13].SlotCharacteristics = PcdGet32(PcdSMBIOSSystemSlot14Characteristics);\r
+}\r
+/**\r
+ This function makes boot time changes to the contents of the\r
+ MiscSystemSlotDesignator structure (Type 9).\r
+\r
+ @param RecordData Pointer to copy of RecordData from the Data Table.\r
+\r
+ @retval EFI_SUCCESS All parameters were valid.\r
+ @retval EFI_UNSUPPORTED Unexpected RecordType value.\r
+ @retval EFI_INVALID_PARAMETER Invalid parameter was found.\r
+\r
+**/\r
+MISC_SMBIOS_TABLE_FUNCTION(MiscSystemSlotDesignator)\r
+{\r
+ CHAR8 *OptionalStrStart;\r
+ UINTN SlotDesignationStrLen;\r
+ EFI_STATUS Status;\r
+ EFI_STRING SlotDesignation;\r
+ STRING_REF TokenToUpdate;\r
+ STRING_REF TokenToGet;\r
+ SMBIOS_TABLE_TYPE9 *SmbiosRecord;\r
+ EFI_SMBIOS_HANDLE SmbiosHandle;\r
+ EFI_MISC_SYSTEM_SLOT_DESIGNATION* ForType9InputData;\r
+ UINT8 Index;\r
+\r
+ ForType9InputData = (EFI_MISC_SYSTEM_SLOT_DESIGNATION *)RecordData;\r
+\r
+ TokenToGet = 0;\r
+\r
+ //\r
+ // First check for invalid parameters.\r
+ //\r
+ if (RecordData == NULL) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+\r
+ if (!PcdMiscSlotIsInit) {\r
+ GetMiscSLotConfigFromPcd ();\r
+ PcdMiscSlotIsInit = TRUE;\r
+ }\r
+\r
+ for (Index = 0; Index < SMBIOS_SYSTEM_SLOT_MAX_NUM; Index++) {\r
+ if (ForType9InputData->SlotDesignation == (mMiscSlotArray[Index])->SlotDesignation) {\r
+ //DEBUG ((EFI_D_ERROR, "Found slot Data %d : ", Index));\r
+ break;\r
+ }\r
+ }\r
+ if (Index >= SMBIOSlotConfig.SMBIOSSystemSlotNumber) {\r
+ return EFI_SUCCESS;\r
+ }\r
+\r
+ if (Index >= SMBIOS_SYSTEM_SLOT_MAX_NUM) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+\r
+ SlotDesignation = SMBIOSlotConfig.SMBIOSSystemSlot[Index].SlotDesignation;\r
+ TokenToGet = STRING_TOKEN ((mMiscSlotArray[Index])->SlotDesignation);\r
+\r
+ if (StrLen (SlotDesignation) > 0) {\r
+ TokenToUpdate = STRING_TOKEN ((mMiscSlotArray[Index])->SlotDesignation);\r
+ HiiSetString (mHiiHandle, TokenToUpdate, SlotDesignation, NULL);\r
+ }\r
+\r
+ SlotDesignation = HiiGetPackageString(&gEfiCallerIdGuid, TokenToGet, NULL);\r
+ SlotDesignationStrLen = StrLen(SlotDesignation);\r
+ if (SlotDesignationStrLen > SMBIOS_STRING_MAX_LENGTH) {\r
+ return EFI_UNSUPPORTED;\r
+ }\r
+ //\r
+ // Two zeros following the last string.\r
+ //\r
+ SmbiosRecord = AllocatePool(sizeof (SMBIOS_TABLE_TYPE9) + SlotDesignationStrLen + 1 + 1);\r
+ ZeroMem(SmbiosRecord, sizeof (SMBIOS_TABLE_TYPE9) +SlotDesignationStrLen + 1 + 1);\r
+\r
+ SmbiosRecord->Hdr.Type = EFI_SMBIOS_TYPE_SYSTEM_SLOTS;\r
+ SmbiosRecord->Hdr.Length = sizeof (SMBIOS_TABLE_TYPE9);\r
+ SmbiosRecord->Hdr.Handle = 0;\r
+ SmbiosRecord->SlotDesignation = 1;\r
+ SmbiosRecord->SlotType = SMBIOSlotConfig.SMBIOSSystemSlot[Index].SlotType;\r
+ SmbiosRecord->SlotDataBusWidth = SMBIOSlotConfig.SMBIOSSystemSlot[Index].SlotDataBusWidth;\r
+ SmbiosRecord->CurrentUsage = SMBIOSlotConfig.SMBIOSSystemSlot[Index].SlotUsage;\r
+ SmbiosRecord->SlotLength = SMBIOSlotConfig.SMBIOSSystemSlot[Index].SlotLength;\r
+ SmbiosRecord->SlotID = SMBIOSlotConfig.SMBIOSSystemSlot[Index].SlotId;\r
+ *(UINT16 *)&SmbiosRecord->SlotCharacteristics1 = (UINT16)(SMBIOSlotConfig.SMBIOSSystemSlot[Index].SlotCharacteristics);\r
+\r
+ //\r
+ // Slot Characteristics\r
+ //\r
+ OptionalStrStart = (CHAR8 *)(SmbiosRecord + 1);\r
+ UnicodeStrToAsciiStr(SlotDesignation, OptionalStrStart);\r
+ //\r
+ // Now we have got the full smbios record, call smbios protocol to add this record.\r
+ //\r
+ SmbiosHandle = SMBIOS_HANDLE_PI_RESERVED;\r
+ Status = Smbios-> Add(\r
+ Smbios,\r
+ NULL,\r
+ &SmbiosHandle,\r
+ (EFI_SMBIOS_TABLE_HEADER *) SmbiosRecord\r
+ );\r
+ FreePool(SmbiosRecord);\r
+ return Status;\r
+}\r
--- /dev/null
+// /** @file\r
+// System Slot onboard devices\r
+//\r
+// Copyright (c) 2013-2015 Intel Corporation.\r
+//\r
+// This program and the accompanying materials\r
+// are licensed and made available under the terms and conditions of the BSD License\r
+// which accompanies this distribution. The full text of the license may be found at\r
+// http://opensource.org/licenses/bsd-license.php\r
+//\r
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+//\r
+//\r
+// **/\r
+/=#\r
+\r
+\r
+\r
+#string STR_MISC_SYSTEM_SLOT_P64_B1 #language en-US "P64B1"\r
+#string STR_MISC_SYSTEM_SLOT_P64_B2 #language en-US "P64B2"\r
+#string STR_MISC_SYSTEM_SLOT_P64_B3 #language en-US "P64B3"\r
+#string STR_MISC_SYSTEM_SLOT_P64_C1 #language en-US "P64C1"\r
+#string STR_MISC_SYSTEM_SLOT_P64_C2 #language en-US "P64C2"\r
+#string STR_MISC_SYSTEM_SLOT_P64_C3 #language en-US "P64C3"\r
+\r
+\r
+\r
+\r
--- /dev/null
+/** @file\r
+Header file for the SmbiosMisc Driver.\r
+\r
+Copyright (c) 2013-2015 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+**/\r
+\r
+#ifndef _SMBIOS_MISC_H\r
+#define _SMBIOS_MISC_H\r
+\r
+#include "MiscDevicePath.h"\r
+#include <Library/UefiBootServicesTableLib.h>\r
+#include <Library/PrintLib.h>\r
+\r
+///\r
+/// Reference SMBIOS 2.6, chapter 3.1.3.\r
+/// Each text string is limited to 64 significant characters due to system MIF limitations.\r
+///\r
+#define SMBIOS_STRING_MAX_LENGTH 64\r
+#define SMBIOS_PORT_CONNECTOR_MAX_NUM 14\r
+\r
+typedef struct {\r
+ CHAR16 PortInternalConnectorDesignator[SMBIOS_STRING_MAX_LENGTH];\r
+ CHAR16 PortExternalConnectorDesignator[SMBIOS_STRING_MAX_LENGTH];\r
+ UINT8 PortInternalConnectorType;\r
+ UINT8 PortExternalConnectorType;\r
+ UINT8 PortType;\r
+} SMBIOS_PORT_CONNECTOR_DESIGNATOR;\r
+\r
+typedef struct {\r
+ UINT8 SMBIOSConnectorNumber;\r
+ SMBIOS_PORT_CONNECTOR_DESIGNATOR SMBIOSPortConnector[SMBIOS_PORT_CONNECTOR_MAX_NUM];\r
+} SMBIOS_PORT_CONNECTOR_DESIGNATOR_COFNIG;\r
+\r
+#define SMBIOS_SYSTEM_SLOT_MAX_NUM 14\r
+\r
+typedef struct {\r
+ CHAR16 SlotDesignation[SMBIOS_STRING_MAX_LENGTH];\r
+ UINT8 SlotType;\r
+ UINT8 SlotDataBusWidth;\r
+ UINT8 SlotUsage;\r
+ UINT8 SlotLength;\r
+ UINT16 SlotId;\r
+ UINT32 SlotCharacteristics;\r
+} SMBIOS_SLOT_DESIGNATION;\r
+\r
+typedef struct {\r
+ UINT8 SMBIOSSystemSlotNumber;\r
+ SMBIOS_SLOT_DESIGNATION SMBIOSSystemSlot[SMBIOS_SYSTEM_SLOT_MAX_NUM];\r
+} SMBIOS_SLOT_COFNIG;\r
+\r
+//\r
+// Data table entry update function.\r
+//\r
+typedef EFI_STATUS (EFIAPI EFI_MISC_SMBIOS_DATA_FUNCTION) (\r
+ IN VOID *RecordData,\r
+ IN EFI_SMBIOS_PROTOCOL *Smbios\r
+ );\r
+\r
+\r
+//\r
+// Data table entry definition.\r
+//\r
+typedef struct {\r
+ //\r
+ // intermediat input data for SMBIOS record\r
+ //\r
+ VOID *RecordData;\r
+ EFI_MISC_SMBIOS_DATA_FUNCTION *Function;\r
+} EFI_MISC_SMBIOS_DATA_TABLE;\r
+\r
+//\r
+// Data Table extern definitions.\r
+//\r
+#define MISC_SMBIOS_DATA_TABLE_POINTER(NAME1) \\r
+ & NAME1 ## Data\r
+\r
+//\r
+// Data Table extern definitions.\r
+//\r
+#define MISC_SMBIOS_DATA_TABLE_EXTERNS(NAME1, NAME2) \\r
+extern NAME1 NAME2 ## Data\r
+\r
+//\r
+// Data and function Table extern definitions.\r
+//\r
+#define MISC_SMBIOS_TABLE_EXTERNS(NAME1, NAME2, NAME3) \\r
+extern NAME1 NAME2 ## Data; \\r
+extern EFI_MISC_SMBIOS_DATA_FUNCTION NAME3 ## Function\r
+\r
+\r
+//\r
+// Data Table entries\r
+//\r
+\r
+#define MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(NAME1, NAME2) \\r
+{ \\r
+ & NAME1 ## Data, \\r
+ & NAME2 ## Function \\r
+}\r
+\r
+\r
+//\r
+// Global definition macros.\r
+//\r
+#define MISC_SMBIOS_TABLE_DATA(NAME1, NAME2) \\r
+ NAME1 NAME2 ## Data\r
+\r
+#define MISC_SMBIOS_TABLE_FUNCTION(NAME2) \\r
+ EFI_STATUS EFIAPI NAME2 ## Function( \\r
+ IN VOID *RecordData, \\r
+ IN EFI_SMBIOS_PROTOCOL *Smbios \\r
+ )\r
+\r
+\r
+// Data Table Array\r
+//\r
+extern EFI_MISC_SMBIOS_DATA_TABLE mSmbiosMiscDataTable[];\r
+\r
+//\r
+// Data Table Array Entries\r
+//\r
+extern UINTN mSmbiosMiscDataTableEntries;\r
+extern EFI_HII_HANDLE mHiiHandle;\r
+//\r
+// Prototypes\r
+//\r
+EFI_STATUS\r
+PiSmbiosMiscEntryPoint (\r
+ IN EFI_HANDLE ImageHandle,\r
+ IN EFI_SYSTEM_TABLE *SystemTable\r
+ );\r
+\r
+#endif\r
--- /dev/null
+/** @file\r
+This driver parses the mSmbiosMiscDataTable structure and reports\r
+any generated data using SMBIOS protocol.\r
+\r
+Copyright (c) 2013-2015 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+**/\r
+\r
+\r
+#include "CommonHeader.h"\r
+\r
+#include "SmbiosMisc.h"\r
+\r
+\r
+//\r
+// External definitions referenced by Data Table entries.\r
+//\r
+\r
+MISC_SMBIOS_TABLE_EXTERNS(EFI_MISC_BIOS_VENDOR, MiscBiosVendor, MiscBiosVendor);\r
+MISC_SMBIOS_TABLE_EXTERNS(EFI_MISC_SYSTEM_MANUFACTURER, MiscSystemManufacturer, MiscSystemManufacturer);\r
+MISC_SMBIOS_TABLE_EXTERNS(EFI_MISC_SYSTEM_MANUFACTURER, MiscBaseBoardManufacturer, MiscBaseBoardManufacturer);\r
+MISC_SMBIOS_TABLE_EXTERNS(EFI_MISC_CHASSIS_MANUFACTURER, MiscChassisManufacturer, MiscChassisManufacturer);\r
+MISC_SMBIOS_TABLE_EXTERNS(EFI_MISC_BOOT_INFORMATION_STATUS, MiscBootInfoStatus, MiscBootInfoStatus);\r
+MISC_SMBIOS_TABLE_EXTERNS(EFI_MISC_NUMBER_OF_INSTALLABLE_LANGUAGES, NumberOfInstallableLanguages, NumberOfInstallableLanguages);\r
+MISC_SMBIOS_TABLE_EXTERNS (EFI_MISC_SYSTEM_OPTION_STRING, SystemOptionString, SystemOptionString);\r
+MISC_SMBIOS_TABLE_EXTERNS(EFI_MISC_ONBOARD_DEVICE, MiscOnboardDeviceVideo, MiscOnboardDevice);\r
+MISC_SMBIOS_TABLE_EXTERNS(EFI_MISC_OEM_STRING,MiscOemString, MiscOemString);\r
+\r
+MISC_SMBIOS_TABLE_EXTERNS(EFI_MISC_PORT_INTERNAL_CONNECTOR_DESIGNATOR, MiscPortConnector1, MiscPortInternalConnectorDesignator);\r
+MISC_SMBIOS_TABLE_EXTERNS(EFI_MISC_PORT_INTERNAL_CONNECTOR_DESIGNATOR, MiscPortConnector2, MiscPortInternalConnectorDesignator);\r
+MISC_SMBIOS_TABLE_EXTERNS(EFI_MISC_PORT_INTERNAL_CONNECTOR_DESIGNATOR, MiscPortConnector3, MiscPortInternalConnectorDesignator);\r
+MISC_SMBIOS_TABLE_EXTERNS(EFI_MISC_PORT_INTERNAL_CONNECTOR_DESIGNATOR, MiscPortConnector4, MiscPortInternalConnectorDesignator);\r
+MISC_SMBIOS_TABLE_EXTERNS(EFI_MISC_PORT_INTERNAL_CONNECTOR_DESIGNATOR, MiscPortConnector5, MiscPortInternalConnectorDesignator);\r
+MISC_SMBIOS_TABLE_EXTERNS(EFI_MISC_PORT_INTERNAL_CONNECTOR_DESIGNATOR, MiscPortConnector6, MiscPortInternalConnectorDesignator);\r
+MISC_SMBIOS_TABLE_EXTERNS(EFI_MISC_PORT_INTERNAL_CONNECTOR_DESIGNATOR, MiscPortConnector7, MiscPortInternalConnectorDesignator);\r
+MISC_SMBIOS_TABLE_EXTERNS(EFI_MISC_PORT_INTERNAL_CONNECTOR_DESIGNATOR, MiscPortConnector8, MiscPortInternalConnectorDesignator);\r
+MISC_SMBIOS_TABLE_EXTERNS(EFI_MISC_PORT_INTERNAL_CONNECTOR_DESIGNATOR, MiscPortConnector9, MiscPortInternalConnectorDesignator);\r
+MISC_SMBIOS_TABLE_EXTERNS(EFI_MISC_PORT_INTERNAL_CONNECTOR_DESIGNATOR, MiscPortConnector10, MiscPortInternalConnectorDesignator);\r
+MISC_SMBIOS_TABLE_EXTERNS(EFI_MISC_PORT_INTERNAL_CONNECTOR_DESIGNATOR, MiscPortConnector11, MiscPortInternalConnectorDesignator);\r
+MISC_SMBIOS_TABLE_EXTERNS(EFI_MISC_PORT_INTERNAL_CONNECTOR_DESIGNATOR, MiscPortConnector12, MiscPortInternalConnectorDesignator);\r
+MISC_SMBIOS_TABLE_EXTERNS(EFI_MISC_PORT_INTERNAL_CONNECTOR_DESIGNATOR, MiscPortConnector13, MiscPortInternalConnectorDesignator);\r
+MISC_SMBIOS_TABLE_EXTERNS(EFI_MISC_PORT_INTERNAL_CONNECTOR_DESIGNATOR, MiscPortConnector14, MiscPortInternalConnectorDesignator);\r
+MISC_SMBIOS_TABLE_EXTERNS(EFI_MISC_SYSTEM_SLOT_DESIGNATION, MiscSystemSlot1, MiscSystemSlotDesignator);\r
+MISC_SMBIOS_TABLE_EXTERNS(EFI_MISC_SYSTEM_SLOT_DESIGNATION, MiscSystemSlot2, MiscSystemSlotDesignator);\r
+MISC_SMBIOS_TABLE_EXTERNS(EFI_MISC_SYSTEM_SLOT_DESIGNATION, MiscSystemSlot3, MiscSystemSlotDesignator);\r
+MISC_SMBIOS_TABLE_EXTERNS(EFI_MISC_SYSTEM_SLOT_DESIGNATION, MiscSystemSlot4, MiscSystemSlotDesignator);\r
+MISC_SMBIOS_TABLE_EXTERNS(EFI_MISC_SYSTEM_SLOT_DESIGNATION, MiscSystemSlot5, MiscSystemSlotDesignator);\r
+MISC_SMBIOS_TABLE_EXTERNS(EFI_MISC_SYSTEM_SLOT_DESIGNATION, MiscSystemSlot6, MiscSystemSlotDesignator);\r
+MISC_SMBIOS_TABLE_EXTERNS(EFI_MISC_SYSTEM_SLOT_DESIGNATION, MiscSystemSlot7, MiscSystemSlotDesignator);\r
+MISC_SMBIOS_TABLE_EXTERNS(EFI_MISC_SYSTEM_SLOT_DESIGNATION, MiscSystemSlot8, MiscSystemSlotDesignator);\r
+MISC_SMBIOS_TABLE_EXTERNS(EFI_MISC_SYSTEM_SLOT_DESIGNATION, MiscSystemSlot9, MiscSystemSlotDesignator);\r
+MISC_SMBIOS_TABLE_EXTERNS(EFI_MISC_SYSTEM_SLOT_DESIGNATION, MiscSystemSlot10, MiscSystemSlotDesignator);\r
+MISC_SMBIOS_TABLE_EXTERNS(EFI_MISC_SYSTEM_SLOT_DESIGNATION, MiscSystemSlot11, MiscSystemSlotDesignator);\r
+MISC_SMBIOS_TABLE_EXTERNS(EFI_MISC_SYSTEM_SLOT_DESIGNATION, MiscSystemSlot12, MiscSystemSlotDesignator);\r
+MISC_SMBIOS_TABLE_EXTERNS(EFI_MISC_SYSTEM_SLOT_DESIGNATION, MiscSystemSlot13, MiscSystemSlotDesignator);\r
+MISC_SMBIOS_TABLE_EXTERNS(EFI_MISC_SYSTEM_SLOT_DESIGNATION, MiscSystemSlot14, MiscSystemSlotDesignator);\r
+\r
+\r
+//\r
+// Data Table\r
+//\r
+EFI_MISC_SMBIOS_DATA_TABLE mSmbiosMiscDataTable[] = {\r
+ MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscBiosVendor, MiscBiosVendor),\r
+ MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscSystemManufacturer, MiscSystemManufacturer),\r
+ MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscBaseBoardManufacturer, MiscBaseBoardManufacturer),\r
+ MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscChassisManufacturer, MiscChassisManufacturer),\r
+ MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscPortConnector1, MiscPortInternalConnectorDesignator),\r
+ MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscPortConnector2, MiscPortInternalConnectorDesignator),\r
+ MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscPortConnector3, MiscPortInternalConnectorDesignator),\r
+ MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscPortConnector4, MiscPortInternalConnectorDesignator),\r
+ MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscPortConnector5, MiscPortInternalConnectorDesignator),\r
+ MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscPortConnector6, MiscPortInternalConnectorDesignator),\r
+ MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscPortConnector7, MiscPortInternalConnectorDesignator),\r
+ MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscPortConnector8, MiscPortInternalConnectorDesignator),\r
+ MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscPortConnector9, MiscPortInternalConnectorDesignator),\r
+ MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscPortConnector10, MiscPortInternalConnectorDesignator),\r
+ MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscPortConnector11, MiscPortInternalConnectorDesignator),\r
+ MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscPortConnector12, MiscPortInternalConnectorDesignator),\r
+ MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscPortConnector13, MiscPortInternalConnectorDesignator),\r
+ MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscPortConnector14, MiscPortInternalConnectorDesignator),\r
+ MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscSystemSlot1, MiscSystemSlotDesignator),\r
+ MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscSystemSlot2, MiscSystemSlotDesignator),\r
+ MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscSystemSlot3, MiscSystemSlotDesignator),\r
+ MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscSystemSlot4, MiscSystemSlotDesignator),\r
+ MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscSystemSlot5, MiscSystemSlotDesignator),\r
+ MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscSystemSlot6, MiscSystemSlotDesignator),\r
+ MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscSystemSlot7, MiscSystemSlotDesignator),\r
+ MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscSystemSlot8, MiscSystemSlotDesignator),\r
+ MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscSystemSlot9, MiscSystemSlotDesignator),\r
+ MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscSystemSlot10, MiscSystemSlotDesignator),\r
+ MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscSystemSlot11, MiscSystemSlotDesignator),\r
+ MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscSystemSlot12, MiscSystemSlotDesignator),\r
+ MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscSystemSlot13, MiscSystemSlotDesignator),\r
+ MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscSystemSlot14, MiscSystemSlotDesignator),\r
+ MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscOnboardDeviceVideo, MiscOnboardDevice),\r
+ MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscOemString, MiscOemString),\r
+ MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(SystemOptionString, SystemOptionString),\r
+ MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(NumberOfInstallableLanguages, NumberOfInstallableLanguages),\r
+ MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscBootInfoStatus, MiscBootInfoStatus)\r
+};\r
+\r
+//\r
+// Number of Data Table entries.\r
+//\r
+UINTN mSmbiosMiscDataTableEntries =\r
+ (sizeof mSmbiosMiscDataTable) / sizeof(EFI_MISC_SMBIOS_DATA_TABLE);\r
--- /dev/null
+## @file\r
+# Component description file for Smbios Misc module.\r
+#\r
+# This driver parses the mSmbiosMiscDataTable structure\r
+# and reports any generated data using SMBIOS protocol.\r
+# SmBios To Misc.Subclass Map Table.\r
+# SMBIOS Type |SMBIOS Name |Misc Subclass Record |Misc Subclass Name\r
+# 0 | BIOS Information | 0x2 | BiosVendor\r
+# 3 | System/Chassis Enclosure | 0x5 | ChassisManufacturer\r
+# 8 | Port Connector Information | 0x6 | PortInternalConnectorDesignator\r
+# 9 | System Slot Information | 0x7 | SystemSlotDesignator\r
+# 10 | On Board Device Information | 0x8 | OnboardDevice\r
+# 12 | System Configuration Options| 0xA | SystemOptionString\r
+# 13 | BIOS Language Information | 0xB | NumberOfInstallableLanguages\r
+# 32 | Boot Information | 0x1A | BootInformationStatus\r
+# The uni files tagged with "ToolCode="DUMMY"" are included by SmbiosMiscStrings.uni file which is input\r
+# file for StrGather tool.\r
+# Copyright (c) 2013-2015 Intel Corporation.\r
+#\r
+# This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution. The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php\r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+##\r
+\r
+[Defines]\r
+ INF_VERSION = 0x00010005\r
+ BASE_NAME = SmbiosMisc\r
+ FILE_GUID = EF0C99B6-B1D3-4025-9405-BF6A560FE0E0\r
+ MODULE_TYPE = DXE_DRIVER\r
+ VERSION_STRING = 1.0\r
+ ENTRY_POINT = SmbiosMiscEntryPoint\r
+\r
+#\r
+# The following information is for reference only and not required by the build tools.\r
+#\r
+# VALID_ARCHITECTURES = IA32 X64 IPF EBC\r
+#\r
+\r
+[Sources]\r
+ MiscOemStringFunction.c\r
+ MiscOemStringData.c\r
+ SmbiosMiscEntryPoint.c\r
+ SmbiosMiscDataTable.c\r
+ MiscSystemManufacturerData.c\r
+ MiscSystemManufacturerFunction.c\r
+ MiscBaseBoardManufacturerData.c\r
+ MiscBaseBoardManufacturerFunction.c\r
+ MiscOnboardDeviceFunction.c\r
+ MiscOnboardDeviceData.c\r
+ MiscSystemSlotDesignationFunction.c\r
+ MiscSystemSlotDesignationData.c\r
+ MiscNumberOfInstallableLanguagesFunction.c\r
+ MiscNumberOfInstallableLanguagesData.c\r
+ MiscChassisManufacturerFunction.c\r
+ MiscChassisManufacturerData.c\r
+ MiscBootInformationFunction.c\r
+ MiscBootInformationData.c\r
+ MiscBiosVendorFunction.c\r
+ MiscBiosVendorData.c\r
+ MiscSystemOptionStringFunction.c\r
+ MiscSystemOptionStringData.c\r
+ MiscPortInternalConnectorDesignatorFunction.c\r
+ MiscPortInternalConnectorDesignatorData.c\r
+ SmbiosMisc.h\r
+ MiscDevicePath.h\r
+ SmbiosMiscStrings.uni\r
+ CommonHeader.h\r
+\r
+\r
+[Packages]\r
+ MdePkg/MdePkg.dec\r
+ MdeModulePkg/MdeModulePkg.dec\r
+ IntelFrameworkPkg/IntelFrameworkPkg.dec\r
+ QuarkPlatformPkg/QuarkPlatformPkg.dec\r
+\r
+[LibraryClasses]\r
+ PcdLib\r
+ HiiLib\r
+ MemoryAllocationLib\r
+ DevicePathLib\r
+ BaseMemoryLib\r
+ BaseLib\r
+ DebugLib\r
+ UefiBootServicesTableLib\r
+ UefiDriverEntryPoint\r
+ UefiLib\r
+\r
+[Protocols]\r
+ gEfiSmbiosProtocolGuid # PROTOCOL ALWAYS_CONSUMED\r
+\r
+[Pcd]\r
+ gEfiMdePkgTokenSpaceGuid.PcdUefiVariableDefaultPlatformLang\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareRevision\r
+ gQuarkPlatformTokenSpaceGuid.PcdPlatformTypeName\r
+ gQuarkPlatformTokenSpaceGuid.PcdFlashAreaSize\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSBiosVendor\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSBiosReleaseDate\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSBiosStartAddress\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSBiosChar\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSBiosCharEx1\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSBiosCharEx2\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemManufacturer\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemProductName\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemVersion\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSerialNumber\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemUuid\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSKUNumber\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemFamily\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSBoardManufacturer\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSBoardProductName\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSBoardVersion\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSBoardSerialNumber\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSChassisManufacturer\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSChassisVersion\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSChassisSerialNumber\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSChassisAssetTag\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSChassisType\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSChassisBootupState\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSChassisPowerSupplyState\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSChassisSecurityState\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSChassisOemDefined\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSChassisHeight\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSChassisNumberPowerCords\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSChassisElementCount\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSChassisElementRecordLength\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSConnectorNumber\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort1InternalConnectorDesignator\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort1ExternalConnectorDesignator\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort1InternalConnectorType\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort1ExternalConnectorType\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort1Type\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort2InternalConnectorDesignator\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort2ExternalConnectorDesignator\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort2InternalConnectorType\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort2ExternalConnectorType\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort2Type\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort3InternalConnectorDesignator\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort3ExternalConnectorDesignator\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort3InternalConnectorType\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort3ExternalConnectorType\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort3Type\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort4InternalConnectorDesignator\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort4ExternalConnectorDesignator\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort4InternalConnectorType\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort4ExternalConnectorType\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort4Type\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort5InternalConnectorDesignator\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort5ExternalConnectorDesignator\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort5InternalConnectorType\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort5ExternalConnectorType\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort5Type\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort6InternalConnectorDesignator\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort6ExternalConnectorDesignator\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort6InternalConnectorType\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort6ExternalConnectorType\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort6Type\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort7InternalConnectorDesignator\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort7ExternalConnectorDesignator\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort7InternalConnectorType\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort7ExternalConnectorType\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort7Type\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort8InternalConnectorDesignator\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort8ExternalConnectorDesignator\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort8InternalConnectorType\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort8ExternalConnectorType\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort8Type\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort9InternalConnectorDesignator\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort9ExternalConnectorDesignator\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort9InternalConnectorType\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort9ExternalConnectorType\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort9Type\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort10InternalConnectorDesignator\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort10ExternalConnectorDesignator\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort10InternalConnectorType\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort10ExternalConnectorType\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort10Type\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort11InternalConnectorDesignator\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort11ExternalConnectorDesignator\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort11InternalConnectorType\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort11ExternalConnectorType\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort11Type\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort12InternalConnectorDesignator\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort12ExternalConnectorDesignator\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort12InternalConnectorType\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort12ExternalConnectorType\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort12Type\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort13InternalConnectorDesignator\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort13ExternalConnectorDesignator\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort13InternalConnectorType\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort13ExternalConnectorType\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort13Type\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort14InternalConnectorDesignator\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort14ExternalConnectorDesignator\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort14InternalConnectorType\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort14ExternalConnectorType\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort14Type\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort15InternalConnectorDesignator\r
+\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort15InternalConnectorType\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort15ExternalConnectorType\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort15Type\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort16InternalConnectorDesignator\r
+\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort16InternalConnectorType\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort16ExternalConnectorType\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort16Type\r
+\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlotNumber\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot1Designation\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot1Type\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot1DataBusWidth\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot1Usage\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot1Length\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot1Id\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot1Characteristics\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot2Designation\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot2Type\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot2DataBusWidth\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot2Usage\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot2Length\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot2Id\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot2Characteristics\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot3Designation\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot3Type\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot3DataBusWidth\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot3Usage\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot3Length\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot3Id\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot3Characteristics\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot4Designation\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot4Type\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot4DataBusWidth\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot4Usage\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot4Length\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot4Id\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot4Characteristics\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot5Designation\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot5Type\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot5DataBusWidth\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot5Usage\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot5Length\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot5Id\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot5Characteristics\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot6Designation\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot6Type\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot6DataBusWidth\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot6Usage\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot6Length\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot6Id\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot6Characteristics\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot7Designation\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot7Type\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot7DataBusWidth\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot7Usage\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot7Length\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot7Id\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot7Characteristics\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot8Designation\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot8Type\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot8DataBusWidth\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot8Usage\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot8Length\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot8Id\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot8Characteristics\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot9Designation\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot9Type\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot9DataBusWidth\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot9Usage\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot9Length\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot9Id\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot9Characteristics\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot10Designation\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot10Type\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot10DataBusWidth\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot10Usage\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot10Length\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot10Id\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot10Characteristics\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot11Designation\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot11Type\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot11DataBusWidth\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot11Usage\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot11Length\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot11Id\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot11Characteristics\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot12Designation\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot12Type\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot12DataBusWidth\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot12Usage\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot12Length\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot12Id\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot12Characteristics\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot13Designation\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot13Type\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot13DataBusWidth\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot13Usage\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot13Length\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot13Id\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot13Characteristics\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot14Designation\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot14Type\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot14DataBusWidth\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot14Usage\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot14Length\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot14Id\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot14Characteristics\r
+\r
+[Depex]\r
+ gEfiSmbiosProtocolGuid\r
--- /dev/null
+/** @file\r
+This driver parses the mSmbiosMiscDataTable structure and reports\r
+any generated data using SMBIOS protocol.\r
+\r
+Copyright (c) 2013-2015 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+**/\r
+\r
+\r
+#include "CommonHeader.h"\r
+\r
+#include "SmbiosMisc.h"\r
+\r
+\r
+extern UINT8 SmbiosMiscStrings[];\r
+EFI_HANDLE mImageHandle;\r
+\r
+EFI_HII_HANDLE mHiiHandle;\r
+\r
+\r
+\r
+/**\r
+ Standard EFI driver point. This driver parses the mSmbiosMiscDataTable\r
+ structure and reports any generated data using SMBIOS protocol.\r
+\r
+ @param ImageHandle Handle for the image of this driver\r
+ @param SystemTable Pointer to the EFI System Table\r
+\r
+ @retval EFI_SUCCESS The data was successfully stored.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+SmbiosMiscEntryPoint(\r
+ IN EFI_HANDLE ImageHandle,\r
+ IN EFI_SYSTEM_TABLE *SystemTable\r
+ )\r
+{\r
+ UINTN Index;\r
+ EFI_STATUS EfiStatus;\r
+ EFI_SMBIOS_PROTOCOL *Smbios;\r
+\r
+\r
+ mImageHandle = ImageHandle;\r
+\r
+ EfiStatus = gBS->LocateProtocol(&gEfiSmbiosProtocolGuid, NULL, (VOID**)&Smbios);\r
+\r
+ if (EFI_ERROR(EfiStatus)) {\r
+ DEBUG((EFI_D_ERROR, "Could not locate SMBIOS protocol. %r\n", EfiStatus));\r
+ return EfiStatus;\r
+ }\r
+\r
+ mHiiHandle = HiiAddPackages (\r
+ &gEfiCallerIdGuid,\r
+ mImageHandle,\r
+ SmbiosMiscStrings,\r
+ NULL\r
+ );\r
+ ASSERT (mHiiHandle != NULL);\r
+\r
+ for (Index = 0; Index < mSmbiosMiscDataTableEntries; ++Index) {\r
+ //\r
+ // If the entry have a function pointer, just log the data.\r
+ //\r
+ if (mSmbiosMiscDataTable[Index].Function != NULL) {\r
+ EfiStatus = (*mSmbiosMiscDataTable[Index].Function)(\r
+ mSmbiosMiscDataTable[Index].RecordData,\r
+ Smbios\r
+ );\r
+\r
+ if (EFI_ERROR(EfiStatus)) {\r
+ DEBUG((EFI_D_ERROR, "Misc smbios store error. Index=%d, ReturnStatus=%r\n", Index, EfiStatus));\r
+ return EfiStatus;\r
+ }\r
+ }\r
+ }\r
+\r
+ return EfiStatus;\r
+}\r
--- /dev/null
+// /** @file\r
+// SmbiosMisc formset.\r
+//\r
+// Copyright (c) 2013-2015 Intel Corporation.\r
+//\r
+// This program and the accompanying materials\r
+// are licensed and made available under the terms and conditions of the BSD License\r
+// which accompanies this distribution. The full text of the license may be found at\r
+// http://opensource.org/licenses/bsd-license.php\r
+//\r
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+//\r
+//\r
+// **/\r
+\r
+/=#\r
+\r
+#langdef en-US "English"\r
+\r
+#string STR_MISC_SUBCLASS_DRIVER_TITLE #language en-US "SMBIOS Misc subclass driver"\r
+\r
+\r
+#include "MiscBiosVendor.uni"\r
+#include "MiscChassisManufacturer.uni"\r
+#include "MiscPortInternalConnectorDesignator.uni"\r
+#include "MiscSystemManufacturer.uni"\r
+#include "MiscBaseBoardManufacturer.uni"\r
+#include "MiscSystemOptionString.uni"\r
+#include "MiscSystemSlotDesignation.uni"\r
+#include "MiscOnboardDevice.uni"\r
+#include "MiscOemString.uni"\r
--- /dev/null
+/** @file\r
+Principle source module for Clanton Peak platform config PEIM driver.\r
+\r
+Copyright (c) 2013 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#include <PiPei.h>\r
+#include <Library/IntelQNCLib.h>\r
+#include <Library/PlatformHelperLib.h>\r
+#include <Library/QNCAccessLib.h>\r
+\r
+VOID\r
+EFIAPI\r
+LegacySpiProtect (\r
+ VOID\r
+ )\r
+{\r
+ UINT32 RegVal;\r
+\r
+ RegVal = PcdGet32 (PcdLegacyProtectedBIOSRange0Pei);\r
+ if (RegVal != 0) {\r
+ PlatformWriteFirstFreeSpiProtect (\r
+ RegVal,\r
+ 0,\r
+ 0\r
+ );\r
+ }\r
+ RegVal = PcdGet32 (PcdLegacyProtectedBIOSRange1Pei);\r
+ if (RegVal != 0) {\r
+ PlatformWriteFirstFreeSpiProtect (\r
+ RegVal,\r
+ 0,\r
+ 0\r
+ );\r
+ }\r
+ RegVal = PcdGet32 (PcdLegacyProtectedBIOSRange2Pei);\r
+ if (RegVal != 0) {\r
+ PlatformWriteFirstFreeSpiProtect (\r
+ RegVal,\r
+ 0,\r
+ 0\r
+ );\r
+ }\r
+\r
+ //\r
+ // Make legacy SPI READ/WRITE enabled if not a secure build\r
+ //\r
+ LpcPciCfg32And (R_QNC_LPC_BIOS_CNTL, ~B_QNC_LPC_BIOS_CNTL_BIOSWE);\r
+}\r
+\r
+/** PlatformConfigPei driver entry point.\r
+\r
+ Platform config in PEI stage.\r
+\r
+ @param[in] FfsHeader Pointer to Firmware File System file header.\r
+ @param[in] PeiServices General purpose services available to every PEIM.\r
+\r
+ @retval EFI_SUCCESS Platform config success.\r
+*/\r
+EFI_STATUS\r
+EFIAPI\r
+PlatformConfigPeiInit (\r
+ IN EFI_PEI_FILE_HANDLE FileHandle,\r
+ IN CONST EFI_PEI_SERVICES **PeiServices\r
+ )\r
+{\r
+ //\r
+ // Do SOC Init Pre memory init.\r
+ //\r
+ PeiQNCPreMemInit ();\r
+\r
+ //\r
+ // Protect areas specified by PCDs.\r
+ //\r
+ LegacySpiProtect ();\r
+\r
+ return EFI_SUCCESS;\r
+}\r
--- /dev/null
+## @file\r
+# Component description file for Clanton Peak platform config PEIM module.\r
+#\r
+# Copyright (c) 2013 Intel Corporation.\r
+#\r
+# This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution. The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php\r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+##\r
+\r
+[Defines]\r
+ INF_VERSION = 0x00010005\r
+ BASE_NAME = PlatformConfigPei\r
+ FILE_GUID = 55961E20-B0D9-4553-9948-E3ECF0BE0889\r
+ MODULE_TYPE = PEIM\r
+ VERSION_STRING = 1.0\r
+ ENTRY_POINT = PlatformConfigPeiInit\r
+\r
+#\r
+# The following information is for reference only and not required by the build tools.\r
+#\r
+# VALID_ARCHITECTURES = IA32\r
+#\r
+\r
+[Sources]\r
+ PlatformConfigPei.c\r
+\r
+[Packages]\r
+ MdePkg/MdePkg.dec\r
+ QuarkPlatformPkg/QuarkPlatformPkg.dec\r
+ QuarkSocPkg/QuarkSocPkg.dec\r
+\r
+[LibraryClasses]\r
+ PeimEntryPoint\r
+ PcdLib\r
+ IntelQNCLib\r
+ PlatformHelperLib\r
+ QNCAccessLib\r
+\r
+[Pcd]\r
+ gQuarkPlatformTokenSpaceGuid.PcdLegacyProtectedBIOSRange0Pei\r
+ gQuarkPlatformTokenSpaceGuid.PcdLegacyProtectedBIOSRange1Pei\r
+ gQuarkPlatformTokenSpaceGuid.PcdLegacyProtectedBIOSRange2Pei\r
+\r
+[Depex]\r
+ TRUE\r
--- /dev/null
+/** @file\r
+This file provide the function to detect boot mode\r
+\r
+Copyright (c) 2013 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+\r
+#include "CommonHeader.h"\r
+#include <Pi/PiFirmwareVolume.h>\r
+\r
+EFI_PEI_PPI_DESCRIPTOR mPpiListRecoveryBootMode = {\r
+ (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),\r
+ &gEfiPeiBootInRecoveryModePpiGuid,\r
+ NULL\r
+};\r
+\r
+/**\r
+ If the box was opened, it's boot with full config.\r
+ If the box is closed, then\r
+ 1. If it's first time to boot, it's boot with full config .\r
+ 2. If the ChassisIntrution is selected, force to be a boot with full config\r
+ 3. Otherwise it's boot with no change.\r
+\r
+ @param PeiServices General purpose services available to every PEIM.\r
+\r
+ @retval TRUE If it's boot with no change.\r
+\r
+ @retval FALSE If boot with no change.\r
+**/\r
+BOOLEAN\r
+IsBootWithNoChange (\r
+ IN EFI_PEI_SERVICES **PeiServices\r
+ )\r
+{\r
+ BOOLEAN IsFirstBoot = FALSE;\r
+\r
+ BOOLEAN EnableFastBoot = FALSE;\r
+ IsFirstBoot = PcdGetBool(PcdBootState);\r
+ EnableFastBoot = PcdGetBool (PcdEnableFastBoot);\r
+\r
+ DEBUG ((EFI_D_INFO, "IsFirstBoot = %x , EnableFastBoot= %x. \n", IsFirstBoot, EnableFastBoot));\r
+\r
+ if ((!IsFirstBoot) && EnableFastBoot) {\r
+ return TRUE;\r
+ } else {\r
+ return FALSE;\r
+ }\r
+}\r
+\r
+\r
+/**\r
+\r
+Routine Description:\r
+\r
+ This function is used to verify if the FV header is validate.\r
+\r
+ @param FwVolHeader - The FV header that to be verified.\r
+\r
+ @retval EFI_SUCCESS - The Fv header is valid.\r
+ @retval EFI_NOT_FOUND - The Fv header is invalid.\r
+\r
+**/\r
+EFI_STATUS\r
+ValidateFvHeader (\r
+ EFI_BOOT_MODE *BootMode\r
+ )\r
+{\r
+ UINT16 *Ptr;\r
+ UINT16 HeaderLength;\r
+ UINT16 Checksum;\r
+\r
+ EFI_FIRMWARE_VOLUME_HEADER *FwVolHeader;\r
+\r
+ if (BOOT_IN_RECOVERY_MODE == *BootMode) {\r
+ DEBUG ((EFI_D_INFO, "Boot mode recovery\n"));\r
+ return EFI_SUCCESS;\r
+ }\r
+ //\r
+ // Let's check whether FvMain header is valid, if not enter into recovery mode\r
+ //\r
+ //\r
+ // Verify the header revision, header signature, length\r
+ // Length of FvBlock cannot be 2**64-1\r
+ // HeaderLength cannot be an odd number\r
+ //\r
+ FwVolHeader = (EFI_FIRMWARE_VOLUME_HEADER *)(UINTN)PcdGet32(PcdFlashFvMainBase);\r
+ if ((FwVolHeader->Revision != EFI_FVH_REVISION)||\r
+ (FwVolHeader->Signature != EFI_FVH_SIGNATURE) ||\r
+ (FwVolHeader->FvLength == ((UINT64) -1)) ||\r
+ ((FwVolHeader->HeaderLength & 0x01) != 0)\r
+ ) {\r
+ return EFI_NOT_FOUND;\r
+ }\r
+ //\r
+ // Verify the header checksum\r
+ //\r
+ HeaderLength = (UINT16) (FwVolHeader->HeaderLength / 2);\r
+ Ptr = (UINT16 *) FwVolHeader;\r
+ Checksum = 0;\r
+ while (HeaderLength > 0) {\r
+ Checksum = Checksum +*Ptr;\r
+ Ptr++;\r
+ HeaderLength--;\r
+ }\r
+\r
+ if (Checksum != 0) {\r
+ return EFI_NOT_FOUND;\r
+ }\r
+\r
+ return EFI_SUCCESS;\r
+}\r
+\r
+/**\r
+\r
+ Check whether go to recovery path\r
+ @retval TRUE Go to recovery path\r
+ @retval FALSE Go to normal path\r
+\r
+**/\r
+BOOLEAN\r
+OemRecoveryBootMode ()\r
+{\r
+ return PlatformIsBootWithRecoveryStage1 ();\r
+}\r
+\r
+/**\r
+ Peform the boot mode determination logic\r
+ If the box is closed, then\r
+ 1. If it's first time to boot, it's boot with full config .\r
+ 2. If the ChassisIntrution is selected, force to be a boot with full config\r
+ 3. Otherwise it's boot with no change.\r
+\r
+ @param PeiServices General purpose services available to every PEIM.\r
+\r
+ @param BootMode The detected boot mode.\r
+\r
+ @retval EFI_SUCCESS if the boot mode could be set\r
+**/\r
+EFI_STATUS\r
+UpdateBootMode (\r
+ IN EFI_PEI_SERVICES **PeiServices,\r
+ OUT EFI_BOOT_MODE *BootMode\r
+ )\r
+{\r
+ EFI_STATUS Status;\r
+ EFI_BOOT_MODE NewBootMode;\r
+ PEI_CAPSULE_PPI *Capsule;\r
+ CHAR8 UserSelection;\r
+ UINT32 Straps32;\r
+\r
+ //\r
+ // Read Straps. Used later if recovery boot.\r
+ //\r
+ Straps32 = QNCAltPortRead (QUARK_SCSS_SOC_UNIT_SB_PORT_ID, QUARK_SCSS_SOC_UNIT_STPDDRCFG);\r
+\r
+ //\r
+ // Check if we need to boot in recovery mode\r
+ //\r
+ if ((ValidateFvHeader (BootMode) != EFI_SUCCESS)) {\r
+ DEBUG ((EFI_D_INFO, "Force Boot mode recovery\n"));\r
+ NewBootMode = BOOT_IN_RECOVERY_MODE;\r
+ Status = PeiServicesInstallPpi (&mPpiListRecoveryBootMode);\r
+ ASSERT_EFI_ERROR (Status);\r
+ if (OemRecoveryBootMode () == FALSE) {\r
+ DEBUG ((EFI_D_INFO, "Recovery stage1 not Active, reboot to activate recovery stage1 image\n"));\r
+ OemInitiateRecoveryAndWait ();\r
+ }\r
+ } else if (OemRecoveryBootMode ()) {\r
+ DEBUG ((EFI_D_INFO, "Boot mode recovery\n"));\r
+ NewBootMode = BOOT_IN_RECOVERY_MODE;\r
+ Status = PeiServicesInstallPpi (&mPpiListRecoveryBootMode);\r
+ ASSERT_EFI_ERROR (Status);\r
+ } else if (QNCCheckS3AndClearState ()) {\r
+ //\r
+ // Determine if we're in capsule update mode\r
+ //\r
+ Status = PeiServicesLocatePpi (\r
+ &gPeiCapsulePpiGuid,\r
+ 0,\r
+ NULL,\r
+ (VOID **)&Capsule\r
+ );\r
+ if (Status == EFI_SUCCESS) {\r
+ Status = Capsule->CheckCapsuleUpdate (PeiServices);\r
+ if (Status == EFI_SUCCESS) {\r
+ DEBUG ((EFI_D_INFO, "Boot mode Flash Update\n"));\r
+ NewBootMode = BOOT_ON_FLASH_UPDATE;\r
+ } else {\r
+ DEBUG ((EFI_D_INFO, "Boot mode S3 resume\n"));\r
+ NewBootMode = BOOT_ON_S3_RESUME;\r
+ }\r
+ } else {\r
+ DEBUG ((EFI_D_INFO, "Boot mode S3 resume\n"));\r
+ NewBootMode = BOOT_ON_S3_RESUME;\r
+ }\r
+ } else {\r
+ //\r
+ // Check if this is a power on reset\r
+ //\r
+ if (QNCCheckPowerOnResetAndClearState ()) {\r
+ DEBUG ((EFI_D_INFO, "Power On Reset\n"));\r
+ }\r
+ if (IsBootWithNoChange (PeiServices)) {\r
+ DEBUG ((EFI_D_INFO, "Boot with Minimum cfg\n"));\r
+ NewBootMode = BOOT_ASSUMING_NO_CONFIGURATION_CHANGES;\r
+ } else {\r
+ DEBUG ((EFI_D_INFO, "Boot with Full cfg\n"));\r
+ NewBootMode = BOOT_WITH_FULL_CONFIGURATION;\r
+ }\r
+ }\r
+ *BootMode = NewBootMode;\r
+ Status = PeiServicesSetBootMode (NewBootMode);\r
+ ASSERT_EFI_ERROR (Status);\r
+\r
+ //\r
+ // If Recovery Boot then prompt the user to insert a USB key with recovery nodule and\r
+ // continue with the recovery. Also give the user a chance to retry a normal boot.\r
+ //\r
+ if (NewBootMode == BOOT_IN_RECOVERY_MODE) {\r
+ if ((Straps32 & B_STPDDRCFG_FORCE_RECOVERY) == 0) {\r
+ DEBUG ((EFI_D_ERROR, "*****************************************************************\n"));\r
+ DEBUG ((EFI_D_ERROR, "***** Force Recovery Jumper Detected. *****\n"));\r
+ DEBUG ((EFI_D_ERROR, "***** Attempting auto recovery of system flash. *****\n"));\r
+ DEBUG ((EFI_D_ERROR, "***** Expecting USB key with recovery module connected. *****\n"));\r
+ DEBUG ((EFI_D_ERROR, "***** PLEASE REMOVE FORCE RECOVERY JUMPER. *****\n"));\r
+ DEBUG ((EFI_D_ERROR, "*****************************************************************\n"));\r
+ } else {\r
+ DEBUG ((EFI_D_ERROR, "*****************************************************************\n"));\r
+ DEBUG ((EFI_D_ERROR, "***** ERROR: System boot failure!!!!!!! *****\n"));\r
+ DEBUG ((EFI_D_ERROR, "***** - Press 'R' if you wish to force system recovery *****\n"));\r
+ DEBUG ((EFI_D_ERROR, "***** (connect USB key with recovery module first) *****\n"));\r
+ DEBUG ((EFI_D_ERROR, "***** - Press any other key to attempt another boot *****\n"));\r
+ DEBUG ((EFI_D_ERROR, "*****************************************************************\n"));\r
+\r
+ UserSelection = PlatformDebugPortGetChar8 ();\r
+ if ((UserSelection != 'R') && (UserSelection != 'r')) {\r
+ DEBUG ((EFI_D_ERROR, "New boot attempt selected........\n"));\r
+ //\r
+ // Initialte the cold reset\r
+ //\r
+ ResetCold ();\r
+ }\r
+ DEBUG ((EFI_D_ERROR, "Recovery boot selected..........\n"));\r
+ }\r
+ }\r
+\r
+ return EFI_SUCCESS;\r
+}\r
--- /dev/null
+/** @file\r
+Common header file shared by all source files.\r
+\r
+This file includes package header files, library classes and protocol, PPI & GUID definitions.\r
+\r
+Copyright (c) 2013 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+**/\r
+\r
+#ifndef __COMMON_HEADER_H_\r
+#define __COMMON_HEADER_H_\r
+\r
+\r
+\r
+#include <PiPei.h>\r
+#include <IntelQNCPeim.h>\r
+#include "Ioh.h"\r
+#include <Platform.h>\r
+#include <PlatformBoards.h>\r
+\r
+#include <IndustryStandard/SmBus.h>\r
+#include <IndustryStandard/Pci22.h>\r
+\r
+#include <Guid/AcpiS3Context.h>\r
+#include <Ppi/AtaController.h>\r
+#include <Guid/Capsule.h>\r
+#include <Ppi/MasterBootMode.h>\r
+#include <Guid/MemoryTypeInformation.h>\r
+#include <Guid/RecoveryDevice.h>\r
+#include <Guid/MemoryConfigData.h>\r
+#include <Guid/MemoryOverwriteControl.h>\r
+#include <Guid/CapsuleVendor.h>\r
+#include <Guid/QuarkCapsuleGuid.h>\r
+#include <Ppi/ReadOnlyVariable2.h>\r
+#include <Ppi/FvLoadFile.h>\r
+#include <Guid/SmramMemoryReserve.h>\r
+#include <Ppi/DeviceRecoveryModule.h>\r
+#include <Ppi/Capsule.h>\r
+#include <Ppi/Reset.h>\r
+#include <Ppi/Stall.h>\r
+#include <Ppi/BootInRecoveryMode.h>\r
+#include <Guid/FirmwareFileSystem2.h>\r
+#include <Ppi/MemoryDiscovered.h>\r
+#include <Ppi/RecoveryModule.h>\r
+#include <Ppi/Smbus2.h>\r
+#include <Ppi/FirmwareVolumeInfo.h>\r
+#include <Ppi/EndOfPeiPhase.h>\r
+\r
+#include <Library/DebugLib.h>\r
+#include <Library/PeimEntryPoint.h>\r
+#include <Library/BaseLib.h>\r
+#include <Library/PeiServicesTablePointerLib.h>\r
+#include <Library/PeiServicesLib.h>\r
+#include <Library/BaseMemoryLib.h>\r
+#include <Library/HobLib.h>\r
+#include <Library/PciCf8Lib.h>\r
+#include <Library/IoLib.h>\r
+#include <Library/PciLib.h>\r
+#include <Library/ReportStatusCodeLib.h>\r
+#include <Library/IntelQNCLib.h>\r
+#include <Library/PcdLib.h>\r
+#include <Library/SmbusLib.h>\r
+#include <Library/RecoveryOemHookLib.h>\r
+#include <Library/TimerLib.h>\r
+#include <Library/PrintLib.h>\r
+#include <Library/ResetSystemLib.h>\r
+#include <Library/MemoryAllocationLib.h>\r
+#include <Library/PerformanceLib.h>\r
+#include <Library/CacheMaintenanceLib.h>\r
+#include <Library/MtrrLib.h>\r
+#include <Library/QNCAccessLib.h>\r
+#include <Library/PlatformHelperLib.h>\r
+#include <Library/PlatformPcieHelperLib.h>\r
+\r
+#include <Register/Cpuid.h>\r
+\r
+#endif\r
--- /dev/null
+/** @file\r
+Install Platform EFI_PEI_RECOVERY_MODULE_PPI and Implementation of\r
+EFI_PEI_LOAD_RECOVERY_CAPSULE service.\r
+\r
+Copyright (c) 2013 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#include "CommonHeader.h"\r
+#include "PlatformEarlyInit.h"\r
+\r
+#include <Ppi/BlockIo.h>\r
+\r
+//\r
+// Capsule Types supported in this platform module\r
+//\r
+#include <Guid/CapsuleOnFatFloppyDisk.h>\r
+#include <Guid/CapsuleOnFatIdeDisk.h>\r
+#include <Guid/CapsuleOnFatUsbDisk.h>\r
+#include <Guid/CapsuleOnDataCD.h>\r
+#include <Guid/QuarkCapsuleGuid.h>\r
+\r
+#include <Ppi/RecoveryModule.h>\r
+#include <Ppi/DeviceRecoveryModule.h>\r
+\r
+#include <Library/PeiServicesLib.h>\r
+\r
+//\r
+// Required Service\r
+//\r
+EFI_STATUS\r
+EFIAPI\r
+PlatformRecoveryModule (\r
+ IN EFI_PEI_SERVICES **PeiServices,\r
+ IN EFI_PEI_RECOVERY_MODULE_PPI *This\r
+ );\r
+\r
+VOID\r
+AssertNoCapsulesError (\r
+ IN EFI_PEI_SERVICES **PeiServices\r
+ );\r
+\r
+VOID\r
+AssertMediaDeviceError (\r
+ IN EFI_PEI_SERVICES **PeiServices\r
+ );\r
+\r
+VOID\r
+ReportLoadCapsuleSuccess (\r
+ IN EFI_PEI_SERVICES **PeiServices\r
+ );\r
+\r
+VOID\r
+CheckIfMediaPresentOnBlockIoDevice (\r
+ IN EFI_PEI_SERVICES **PeiServices,\r
+ IN OUT BOOLEAN *MediaDeviceError,\r
+ IN OUT BOOLEAN *MediaPresent\r
+ );\r
+\r
+//\r
+// Module globals\r
+//\r
+EFI_PEI_RECOVERY_MODULE_PPI mRecoveryPpi = { PlatformRecoveryModule };\r
+\r
+EFI_PEI_PPI_DESCRIPTOR mRecoveryPpiList = {\r
+ (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),\r
+ &gEfiPeiRecoveryModulePpiGuid,\r
+ &mRecoveryPpi\r
+};\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+PeimInitializeRecovery (\r
+ IN EFI_PEI_SERVICES **PeiServices\r
+ )\r
+/*++\r
+\r
+Routine Description:\r
+\r
+ Provide the functionality of the Recovery Module.\r
+\r
+Arguments:\r
+\r
+ PeiServices - General purpose services available to every PEIM.\r
+\r
+Returns:\r
+\r
+ EFI_SUCCESS - If the interface could be successfully\r
+ installed.\r
+\r
+--*/\r
+{\r
+ EFI_STATUS Status;\r
+\r
+ Status = PeiServicesInstallPpi (&mRecoveryPpiList);\r
+\r
+ return Status;\r
+}\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+PlatformRecoveryModule (\r
+ IN EFI_PEI_SERVICES **PeiServices,\r
+ IN EFI_PEI_RECOVERY_MODULE_PPI *This\r
+ )\r
+/*++\r
+\r
+Routine Description:\r
+\r
+ Provide the functionality of the Platform Recovery Module.\r
+\r
+Arguments:\r
+\r
+ PeiServices - General purpose services available to every PEIM.\r
+ This - Pointer to EFI_PEI_RECOVERY_MODULE_PPI.\r
+\r
+Returns:\r
+\r
+ EFI_SUCCESS - If the interface could be successfully\r
+ installed.\r
+ EFI_UNSUPPORTED - Not supported.\r
+\r
+--*/\r
+{\r
+ EFI_STATUS Status;\r
+ EFI_PEI_DEVICE_RECOVERY_MODULE_PPI *DeviceRecoveryModule;\r
+ UINTN NumberOfImageProviders;\r
+ BOOLEAN ProviderAvailable;\r
+ UINTN NumberRecoveryCapsules;\r
+ UINTN RecoveryCapsuleSize;\r
+ EFI_GUID DeviceId;\r
+ BOOLEAN ImageFound;\r
+ EFI_PHYSICAL_ADDRESS Address;\r
+ VOID *Buffer;\r
+ EFI_CAPSULE_HEADER *CapsuleHeader;\r
+ EFI_PEI_HOB_POINTERS Hob;\r
+ EFI_PEI_HOB_POINTERS HobOld;\r
+ BOOLEAN HobUpdate;\r
+ EFI_FIRMWARE_VOLUME_HEADER *FvHeader;\r
+ UINTN Index;\r
+ EFI_STATUS AuthStatus;\r
+ EFI_GUID mEfiCapsuleHeaderGuid = QUARK_CAPSULE_GUID;\r
+\r
+ Index = 0;\r
+\r
+ Status = EFI_SUCCESS;\r
+ AuthStatus = EFI_SUCCESS;\r
+ HobUpdate = FALSE;\r
+\r
+ ProviderAvailable = TRUE;\r
+ ImageFound = FALSE;\r
+ NumberOfImageProviders = 0;\r
+\r
+ DeviceRecoveryModule = NULL;\r
+\r
+ DEBUG ((EFI_D_INFO | EFI_D_LOAD, "Recovery Entry\n"));\r
+\r
+ //\r
+ // Search the platform for some recovery capsule if the DXE IPL\r
+ // discovered a recovery condition and has requested a load.\r
+ //\r
+ while (ProviderAvailable) {\r
+\r
+ Status = PeiServicesLocatePpi (\r
+ &gEfiPeiDeviceRecoveryModulePpiGuid,\r
+ Index,\r
+ NULL,\r
+ (VOID **)&DeviceRecoveryModule\r
+ );\r
+\r
+ if (!EFI_ERROR (Status)) {\r
+ DEBUG ((EFI_D_INFO | EFI_D_LOAD, "Device Recovery PPI located\n"));\r
+ NumberOfImageProviders++;\r
+\r
+ Status = DeviceRecoveryModule->GetNumberRecoveryCapsules (\r
+ PeiServices,\r
+ DeviceRecoveryModule,\r
+ &NumberRecoveryCapsules\r
+ );\r
+\r
+ DEBUG ((EFI_D_INFO | EFI_D_LOAD, "Number Of Recovery Capsules: %d\n", NumberRecoveryCapsules));\r
+\r
+ if (NumberRecoveryCapsules == 0) {\r
+ Index++;\r
+ } else {\r
+ break;\r
+ }\r
+ } else {\r
+ ProviderAvailable = FALSE;\r
+ }\r
+ }\r
+ //\r
+ // The number of recovery capsules is 0.\r
+ //\r
+ if (!ProviderAvailable) {\r
+ AssertNoCapsulesError (PeiServices);\r
+ }\r
+ //\r
+ // If there is an image provider, get the capsule ID\r
+ //\r
+ if (ProviderAvailable) {\r
+ RecoveryCapsuleSize = 0;\r
+ if (FeaturePcdGet (PcdFrameworkCompatibilitySupport)) {\r
+ Status = DeviceRecoveryModule->GetRecoveryCapsuleInfo (\r
+ PeiServices,\r
+ DeviceRecoveryModule,\r
+ 0,\r
+ &RecoveryCapsuleSize,\r
+ &DeviceId\r
+ );\r
+ } else {\r
+ Status = DeviceRecoveryModule->GetRecoveryCapsuleInfo (\r
+ PeiServices,\r
+ DeviceRecoveryModule,\r
+ 1,\r
+ &RecoveryCapsuleSize,\r
+ &DeviceId\r
+ );\r
+\r
+\r
+ }\r
+\r
+ if (EFI_ERROR (Status)) {\r
+ return Status;\r
+ }\r
+\r
+ DEBUG ((EFI_D_INFO | EFI_D_LOAD, "Recovery Capsule Size: %d\n", RecoveryCapsuleSize));\r
+\r
+ //\r
+ // Only support the 2 capsule types known\r
+ // Future enhancement is to rank-order the selection\r
+ //\r
+ if ((!CompareGuid (&DeviceId, &gPeiCapsuleOnFatIdeDiskGuid)) &&\r
+ (!CompareGuid (&DeviceId, &gPeiCapsuleOnDataCDGuid)) &&\r
+ (!CompareGuid (&DeviceId, &gPeiCapsuleOnFatUsbDiskGuid))\r
+ ) {\r
+ return EFI_UNSUPPORTED;\r
+ }\r
+\r
+ Buffer = NULL;\r
+ Address = (UINTN) AllocatePages ((RecoveryCapsuleSize - 1) / 0x1000 + 1);\r
+ ASSERT (Address);\r
+\r
+ Buffer = (UINT8 *) (UINTN) Address;\r
+ if (FeaturePcdGet (PcdFrameworkCompatibilitySupport)) {\r
+ Status = DeviceRecoveryModule->LoadRecoveryCapsule (\r
+ PeiServices,\r
+ DeviceRecoveryModule,\r
+ 0,\r
+ Buffer\r
+ );\r
+ } else {\r
+ Status = DeviceRecoveryModule->LoadRecoveryCapsule (\r
+ PeiServices,\r
+ DeviceRecoveryModule,\r
+ 1,\r
+ Buffer\r
+ );\r
+\r
+ }\r
+\r
+ DEBUG ((EFI_D_INFO | EFI_D_LOAD, "LoadRecoveryCapsule Returns: %r\n", Status));\r
+\r
+ if (Status == EFI_DEVICE_ERROR) {\r
+ AssertMediaDeviceError (PeiServices);\r
+ }\r
+\r
+ if (EFI_ERROR (Status)) {\r
+ return Status;\r
+ } else {\r
+ ReportLoadCapsuleSuccess (PeiServices);\r
+ }\r
+\r
+ //\r
+ // Update FV Hob if found\r
+ //\r
+ Buffer = (VOID *)((UINT8 *) Buffer);\r
+ Status = PeiServicesGetHobList ((VOID **)&Hob.Raw);\r
+ HobOld.Raw = Hob.Raw;\r
+ while (!END_OF_HOB_LIST (Hob)) {\r
+ if (Hob.Header->HobType == EFI_HOB_TYPE_FV) {\r
+ DEBUG ((EFI_D_INFO | EFI_D_LOAD, "Hob FV Length: %x\n", Hob.FirmwareVolume->Length));\r
+\r
+ if (Hob.FirmwareVolume->BaseAddress == (UINTN) PcdGet32 (PcdFlashFvMainBase)) {\r
+ HobUpdate = TRUE;\r
+ //\r
+ // This looks like the Hob we are interested in\r
+ //\r
+ DEBUG ((EFI_D_INFO | EFI_D_LOAD, "Hob Updated\n"));\r
+ Hob.FirmwareVolume->BaseAddress = (UINTN) Buffer;\r
+ Hob.FirmwareVolume->Length = RecoveryCapsuleSize;\r
+ }\r
+ }\r
+\r
+ Hob.Raw = GET_NEXT_HOB (Hob);\r
+ }\r
+ //\r
+ // Check if the top of the file is a firmware volume header\r
+ //\r
+ FvHeader = (EFI_FIRMWARE_VOLUME_HEADER *) Buffer;\r
+ CapsuleHeader = (EFI_CAPSULE_HEADER *) Buffer;\r
+ if (FvHeader->Signature == EFI_FVH_SIGNATURE) {\r
+ //\r
+ // build FV Hob if it is not built before\r
+ //\r
+ if (!HobUpdate) {\r
+ DEBUG ((EFI_D_INFO | EFI_D_LOAD, "FV Hob is not found, Build FV Hob then..\n"));\r
+ BuildFvHob (\r
+ (UINTN) Buffer,\r
+ FvHeader->FvLength\r
+ );\r
+\r
+ DEBUG ((EFI_D_INFO | EFI_D_LOAD, "Install FV Info PPI..\n"));\r
+\r
+ PeiServicesInstallFvInfoPpi (\r
+ NULL,\r
+ Buffer,\r
+ (UINT32) FvHeader->FvLength,\r
+ NULL,\r
+ NULL\r
+ );\r
+ }\r
+ //\r
+ // Point to the location immediately after the FV.\r
+ //\r
+ CapsuleHeader = (EFI_CAPSULE_HEADER *) ((UINT8 *) Buffer + FvHeader->FvLength);\r
+ }\r
+\r
+ //\r
+ // Check if pointer is still within the buffer\r
+ //\r
+ if ((UINTN) CapsuleHeader < (UINTN) ((UINT8 *) Buffer + RecoveryCapsuleSize)) {\r
+\r
+ //\r
+ // Check if it is a capsule\r
+ //\r
+ if (CompareGuid ((EFI_GUID *) CapsuleHeader, &mEfiCapsuleHeaderGuid)) {\r
+\r
+ //\r
+ // Set bootmode to capsule update so the capsule hob gets the right bootmode in the hob header.\r
+ //\r
+ Status = PeiServicesSetBootMode (BOOT_ON_FLASH_UPDATE);\r
+ if (EFI_ERROR (Status)) {\r
+ return Status;\r
+ }\r
+\r
+ //\r
+ // Build capsule hob\r
+ //\r
+ BuildCvHob ((EFI_PHYSICAL_ADDRESS)(UINTN)CapsuleHeader, (UINT64)CapsuleHeader->CapsuleImageSize);\r
+ }\r
+ }\r
+ }\r
+\r
+ DEBUG ((EFI_D_INFO | EFI_D_LOAD, "Recovery Module Returning: %r\n", Status));\r
+ return Status;\r
+}\r
+\r
+/*\r
+ AssertNoCapsulesError:\r
+ There were no recovery capsules found.\r
+ Case 1: Report the error that no recovery block io device/media is readable and assert.\r
+ Case 2: Report the error that there is no media present on any recovery block io device and assert.\r
+ Case 3: There is media present on some recovery block io device,\r
+ but there is no recovery capsule on it. Report the error and assert.\r
+*/\r
+VOID\r
+AssertNoCapsulesError (\r
+ IN EFI_PEI_SERVICES **PeiServices\r
+ )\r
+{\r
+ BOOLEAN MediaDeviceError;\r
+ BOOLEAN MediaPresent;\r
+\r
+ MediaDeviceError = TRUE;\r
+ MediaPresent = FALSE;\r
+\r
+ CheckIfMediaPresentOnBlockIoDevice (PeiServices, &MediaDeviceError, &MediaPresent);\r
+/* if (MediaDeviceError) {\r
+ ReportStatusCode (\r
+ (EFI_ERROR_CODE | EFI_ERROR_UNRECOVERED),\r
+ (EFI_PERIPHERAL_RECOVERY_MEDIA | EFI_P_EC_MEDIA_DEVICE_ERROR)\r
+ );\r
+\r
+ } else if (!MediaPresent) {\r
+ ReportStatusCode (\r
+ (EFI_ERROR_CODE | EFI_ERROR_UNRECOVERED),\r
+ (EFI_PERIPHERAL_RECOVERY_MEDIA | EFI_P_EC_MEDIA_NOT_PRESENT)\r
+ );\r
+\r
+ } else {\r
+ ReportStatusCode (\r
+ (EFI_ERROR_CODE | EFI_ERROR_UNRECOVERED),\r
+ (EFI_SOFTWARE_PEI_MODULE | EFI_SW_PEIM_EC_NO_RECOVERY_CAPSULE)\r
+ );\r
+ }*/\r
+ //\r
+ // Hang.\r
+ //\r
+ CpuDeadLoop();\r
+}\r
+\r
+#define MAX_BLOCK_IO_PPI 32\r
+\r
+/*\r
+ CheckIfMediaPresentOnBlockIoDevice:\r
+ Checks to see whether there was a media device error or to see if there is media present.\r
+*/\r
+VOID\r
+CheckIfMediaPresentOnBlockIoDevice (\r
+ IN EFI_PEI_SERVICES **PeiServices,\r
+ IN OUT BOOLEAN *MediaDeviceError,\r
+ IN OUT BOOLEAN *MediaPresent\r
+ )\r
+{\r
+ EFI_STATUS Status;\r
+ UINTN BlockIoPpiInstance;\r
+ EFI_PEI_RECOVERY_BLOCK_IO_PPI *BlockIoPpi;\r
+ UINTN NumberBlockDevices;\r
+ EFI_PEI_BLOCK_IO_MEDIA Media;\r
+\r
+ *MediaDeviceError = TRUE;\r
+ *MediaPresent = FALSE;\r
+\r
+ for (BlockIoPpiInstance = 0; BlockIoPpiInstance < MAX_BLOCK_IO_PPI; BlockIoPpiInstance++) {\r
+ Status = PeiServicesLocatePpi (\r
+ &gEfiPeiVirtualBlockIoPpiGuid,\r
+ BlockIoPpiInstance,\r
+ NULL,\r
+ (VOID **)&BlockIoPpi\r
+ );\r
+ if (EFI_ERROR (Status)) {\r
+ //\r
+ // Done with all Block Io Ppis\r
+ //\r
+ break;\r
+ }\r
+\r
+ Status = BlockIoPpi->GetNumberOfBlockDevices (\r
+ PeiServices,\r
+ BlockIoPpi,\r
+ &NumberBlockDevices\r
+ );\r
+ if (EFI_ERROR (Status) || (NumberBlockDevices == 0)) {\r
+ continue;\r
+ }\r
+ //\r
+ // Just retrieve the first block\r
+ //\r
+ Status = BlockIoPpi->GetBlockDeviceMediaInfo (\r
+ PeiServices,\r
+ BlockIoPpi,\r
+ 0,\r
+ &Media\r
+ );\r
+ if (!EFI_ERROR (Status)) {\r
+ *MediaDeviceError = FALSE;\r
+ if (Media.MediaPresent) {\r
+ *MediaPresent = TRUE;\r
+ break;\r
+ }\r
+ }\r
+ }\r
+}\r
+\r
+VOID\r
+AssertMediaDeviceError (\r
+ IN EFI_PEI_SERVICES **PeiServices\r
+ )\r
+{\r
+/* ReportStatusCode (\r
+ (EFI_ERROR_CODE | EFI_ERROR_UNRECOVERED),\r
+ (EFI_PERIPHERAL_RECOVERY_MEDIA | EFI_P_EC_MEDIA_DEVICE_ERROR)\r
+ );\r
+*/\r
+ CpuDeadLoop ();\r
+}\r
+\r
+VOID\r
+ReportLoadCapsuleSuccess (\r
+ IN EFI_PEI_SERVICES **PeiServices\r
+ )\r
+{\r
+ //\r
+ // EFI_SW_PEI_PC_CAPSULE_START: (from the status code spec):\r
+ // Loaded the recovery capsule. About to hand off control to the capsule.\r
+ //\r
+/* ReportStatusCode (\r
+ EFI_PROGRESS_CODE,\r
+ (EFI_SOFTWARE_PEI_MODULE | EFI_SW_PEIM_PC_CAPSULE_LOAD_SUCCESS)\r
+ );*/\r
+}\r
+\r
--- /dev/null
+/** @file\r
+This file includes a memory call back function notified when MRC is done,\r
+following action is performed in this file,\r
+ 1. ICH initialization after MRC.\r
+ 2. SIO initialization.\r
+ 3. Install ResetSystem and FinvFv PPI.\r
+ 4. Set MTRR for PEI\r
+ 5. Create FV HOB and Flash HOB\r
+\r
+Copyright (c) 2013 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+\r
+#include "CommonHeader.h"\r
+\r
+#include "PlatformEarlyInit.h"\r
+\r
+extern EFI_PEI_PPI_DESCRIPTOR mPpiStall[];\r
+\r
+EFI_PEI_RESET_PPI mResetPpi = { ResetSystem };\r
+\r
+EFI_PEI_PPI_DESCRIPTOR mPpiList[1] = {\r
+ {\r
+ (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),\r
+ &gEfiPeiResetPpiGuid,\r
+ &mResetPpi\r
+ }\r
+};\r
+\r
+/**\r
+ This function reset the entire platform, including all processor and devices, and\r
+ reboots the system.\r
+\r
+ @param PeiServices General purpose services available to every PEIM.\r
+\r
+ @retval EFI_SUCCESS if it completed successfully.\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+ResetSystem (\r
+ IN CONST EFI_PEI_SERVICES **PeiServices\r
+ )\r
+{\r
+ ResetCold();\r
+ return EFI_SUCCESS;\r
+}\r
+\r
+/**\r
+ This function provides a blocking stall for reset at least the given number of microseconds\r
+ stipulated in the final argument.\r
+\r
+ @param PeiServices General purpose services available to every PEIM.\r
+\r
+ @param this Pointer to the local data for the interface.\r
+\r
+ @param Microseconds number of microseconds for which to stall.\r
+\r
+ @retval EFI_SUCCESS the function provided at least the required stall.\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+Stall (\r
+ IN CONST EFI_PEI_SERVICES **PeiServices,\r
+ IN CONST EFI_PEI_STALL_PPI *This,\r
+ IN UINTN Microseconds\r
+ )\r
+{\r
+ MicroSecondDelay (Microseconds);\r
+ return EFI_SUCCESS;\r
+}\r
+\r
+\r
+/**\r
+ This function will be called when MRC is done.\r
+\r
+ @param PeiServices General purpose services available to every PEIM.\r
+\r
+ @param NotifyDescriptor Information about the notify event..\r
+\r
+ @param Ppi The notify context.\r
+\r
+ @retval EFI_SUCCESS If the function completed successfully.\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+MemoryDiscoveredPpiNotifyCallback (\r
+ IN EFI_PEI_SERVICES **PeiServices,\r
+ IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,\r
+ IN VOID *Ppi\r
+ )\r
+{\r
+ EFI_STATUS Status;\r
+ EFI_BOOT_MODE BootMode;\r
+ UINT64 MemoryLength;\r
+ EFI_SMRAM_DESCRIPTOR *SmramDescriptor;\r
+ UINTN NumSmramRegions;\r
+ UINT32 RmuMainBaseAddress;\r
+ UINT32 RegData32;\r
+ UINT8 CpuAddressWidth;\r
+ UINT32 RegEax;\r
+ MTRR_SETTINGS MtrrSettings;\r
+\r
+ DEBUG ((EFI_D_INFO, "Platform PEIM Memory Callback\n"));\r
+\r
+ NumSmramRegions = 0;\r
+ SmramDescriptor = NULL;\r
+ RmuMainBaseAddress = 0;\r
+\r
+ PERF_START (NULL, "SetCache", NULL, 0);\r
+\r
+ InfoPostInstallMemory (&RmuMainBaseAddress, &SmramDescriptor, &NumSmramRegions);\r
+ ASSERT (SmramDescriptor != NULL);\r
+ ASSERT (RmuMainBaseAddress != 0);\r
+\r
+ MemoryLength = ((UINT64) RmuMainBaseAddress) + 0x10000;\r
+\r
+ Status = PeiServicesGetBootMode (&BootMode);\r
+ ASSERT_EFI_ERROR (Status);\r
+\r
+ //\r
+ // Get current MTRR settings\r
+ //\r
+ MtrrGetAllMtrrs (&MtrrSettings);\r
+\r
+ //\r
+ // Set all DRAM cachability to CacheWriteBack\r
+ //\r
+ Status = MtrrSetMemoryAttributeInMtrrSettings (&MtrrSettings, 0, MemoryLength, CacheWriteBack);\r
+ ASSERT_EFI_ERROR (Status);\r
+\r
+ //\r
+ // RTC:28208 - System hang/crash when entering probe mode(ITP) when relocating SMBASE\r
+ // Workaround to make default SMRAM UnCachable\r
+ //\r
+ Status = MtrrSetMemoryAttributeInMtrrSettings (&MtrrSettings, 0x30000, SIZE_64KB, CacheUncacheable);\r
+ ASSERT_EFI_ERROR (Status);\r
+\r
+ //\r
+ // Set new MTRR settings\r
+ //\r
+ MtrrSetAllMtrrs (&MtrrSettings);\r
+\r
+ PERF_END (NULL, "SetCache", NULL, 0);\r
+\r
+ //\r
+ // Install PeiReset for PeiResetSystem service\r
+ //\r
+ Status = PeiServicesInstallPpi (&mPpiList[0]);\r
+ ASSERT_EFI_ERROR (Status);\r
+\r
+ //\r
+ // Do QNC initialization after MRC\r
+ //\r
+ PeiQNCPostMemInit ();\r
+\r
+ Status = PeiServicesInstallPpi (&mPpiStall[0]);\r
+ ASSERT_EFI_ERROR (Status);\r
+\r
+ //\r
+ // Set E000/F000 Routing\r
+ //\r
+ RegData32 = QNCPortRead (QUARK_NC_HOST_BRIDGE_SB_PORT_ID, QNC_MSG_FSBIC_REG_HMISC);\r
+ RegData32 |= (BIT2|BIT1);\r
+ QNCPortWrite (QUARK_NC_HOST_BRIDGE_SB_PORT_ID, QNC_MSG_FSBIC_REG_HMISC, RegData32);\r
+\r
+ if (BootMode == BOOT_IN_RECOVERY_MODE) {\r
+ Status = PeimInitializeRecovery (PeiServices);\r
+ ASSERT_EFI_ERROR (Status);\r
+ } else if (BootMode == BOOT_ON_S3_RESUME) {\r
+ return EFI_SUCCESS;\r
+ } else {\r
+ PeiServicesInstallFvInfoPpi (\r
+ NULL,\r
+ (VOID *) (UINTN) PcdGet32 (PcdFlashFvMainBase),\r
+ PcdGet32 (PcdFlashFvMainSize),\r
+ NULL,\r
+ NULL\r
+ );\r
+\r
+ //\r
+ // Publish the FVMAIN FV so the DXE Phase can dispatch drivers from this FV\r
+ // and produce Load File Protocols for UEFI Applications in this FV.\r
+ //\r
+ BuildFvHob (\r
+ PcdGet32 (PcdFlashFvMainBase),\r
+ PcdGet32 (PcdFlashFvMainSize)\r
+ );\r
+\r
+ //\r
+ // Publish the Payload FV so the DXE Phase can dispatch drivers from this FV\r
+ // and produce Load File Protocols for UEFI Applications in this FV.\r
+ //\r
+ BuildFvHob (\r
+ PcdGet32 (PcdFlashFvPayloadBase),\r
+ PcdGet32 (PcdFlashFvPayloadSize)\r
+ );\r
+ }\r
+\r
+ //\r
+ // Build flash HOB, it's going to be used by GCD and E820 building\r
+ // Map full SPI flash decode range (regardless of smaller SPI flash parts installed)\r
+ //\r
+ BuildResourceDescriptorHob (\r
+ EFI_RESOURCE_FIRMWARE_DEVICE,\r
+ (EFI_RESOURCE_ATTRIBUTE_PRESENT |\r
+ EFI_RESOURCE_ATTRIBUTE_INITIALIZED |\r
+ EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE),\r
+ (SIZE_4GB - SIZE_8MB),\r
+ SIZE_8MB\r
+ );\r
+\r
+ //\r
+ // Create a CPU hand-off information\r
+ //\r
+ CpuAddressWidth = 32;\r
+ AsmCpuid (CPUID_EXTENDED_FUNCTION, &RegEax, NULL, NULL, NULL);\r
+ if (RegEax >= CPUID_VIR_PHY_ADDRESS_SIZE) {\r
+ AsmCpuid (CPUID_VIR_PHY_ADDRESS_SIZE, &RegEax, NULL, NULL, NULL);\r
+ CpuAddressWidth = (UINT8) (RegEax & 0xFF);\r
+ }\r
+ DEBUG ((EFI_D_INFO, "CpuAddressWidth: %d\n", CpuAddressWidth));\r
+\r
+ BuildCpuHob (CpuAddressWidth, 16);\r
+\r
+ ASSERT_EFI_ERROR (Status);\r
+\r
+ return Status;\r
+}\r
--- /dev/null
+/** @file\r
+Framework PEIM to initialize memory on a Quark Memory Controller.\r
+\r
+Copyright (c) 2013 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#include "CommonHeader.h"\r
+#include "MrcWrapper.h"\r
+#include <Ioh.h>\r
+#include "Platform.h"\r
+\r
+#include <Library/PlatformHelperLib.h>\r
+\r
+//\r
+// ------------------------ TSEG Base\r
+//\r
+// ------------------------ RESERVED_CPU_S3_SAVE_OFFSET\r
+// CPU S3 data\r
+// ------------------------ RESERVED_ACPI_S3_RANGE_OFFSET\r
+// S3 Memory base structure\r
+// ------------------------ TSEG + 1 page\r
+\r
+#define RESERVED_CPU_S3_SAVE_OFFSET (RESERVED_ACPI_S3_RANGE_OFFSET - sizeof (SMM_S3_RESUME_STATE))\r
+\r
+// Strap configuration register specifying DDR setup\r
+#define QUARK_SCSS_REG_STPDDRCFG 0x00\r
+\r
+// Macro counting array elements\r
+#define COUNT(a) (sizeof(a)/sizeof(*a))\r
+\r
+\r
+EFI_MEMORY_TYPE_INFORMATION mDefaultQncMemoryTypeInformation[] = {\r
+ { EfiReservedMemoryType, EDKII_RESERVED_SIZE_PAGES }, // BIOS Reserved\r
+ { EfiACPIMemoryNVS, ACPI_NVS_SIZE_PAGES }, // S3, SMM, etc\r
+ { EfiRuntimeServicesData, RUNTIME_SERVICES_DATA_SIZE_PAGES },\r
+ { EfiRuntimeServicesCode, RUNTIME_SERVICES_CODE_SIZE_PAGES },\r
+ { EfiACPIReclaimMemory, ACPI_RECLAIM_SIZE_PAGES }, // ACPI ASL\r
+ { EfiMaxMemoryType, 0 }\r
+};\r
+\r
+/**\r
+ Configure Uart mmio base for MRC serial log purpose\r
+\r
+ @param MrcData - MRC configuration data updated\r
+\r
+**/\r
+VOID\r
+MrcUartConfig(\r
+ MRC_PARAMS *MrcData\r
+ )\r
+{\r
+ UINT8 UartIdx;\r
+ UINT32 RegData32;\r
+ UINT8 IohUartBus;\r
+ UINT8 IohUartDev;\r
+\r
+ UartIdx = PcdGet8(PcdIohUartFunctionNumber);\r
+ IohUartBus = PcdGet8(PcdIohUartBusNumber);\r
+ IohUartDev = PcdGet8(PcdIohUartDevNumber);\r
+\r
+ RegData32 = PciRead32 (PCI_LIB_ADDRESS(IohUartBus, IohUartDev, UartIdx, PCI_BASE_ADDRESSREG_OFFSET));\r
+ MrcData->uart_mmio_base = RegData32 & 0xFFFFFFF0;\r
+}\r
+\r
+/**\r
+ Configure MRC from memory controller fuse settings.\r
+\r
+ @param MrcData - MRC configuration data to be updated.\r
+\r
+ @return EFI_SUCCESS MRC Config parameters updated from platform data.\r
+**/\r
+EFI_STATUS\r
+MrcConfigureFromMcFuses (\r
+ OUT MRC_PARAMS *MrcData\r
+ )\r
+{\r
+ UINT32 McFuseStat;\r
+\r
+ McFuseStat = QNCPortRead (\r
+ QUARK_NC_MEMORY_CONTROLLER_SB_PORT_ID,\r
+ QUARK_NC_MEMORY_CONTROLLER_REG_DFUSESTAT\r
+ );\r
+\r
+ DEBUG ((EFI_D_INFO, "MRC McFuseStat 0x%08x\n", McFuseStat));\r
+\r
+ if ((McFuseStat & B_DFUSESTAT_ECC_DIS) != 0) {\r
+ DEBUG ((EFI_D_INFO, "MRC Fuse : fus_dun_ecc_dis.\n"));\r
+ MrcData->ecc_enables = 0;\r
+ } else {\r
+ MrcData->ecc_enables = 1;\r
+ }\r
+ return EFI_SUCCESS;\r
+}\r
+\r
+/**\r
+ Configure MRC from platform info hob.\r
+\r
+ @param MrcData - MRC configuration data to be updated.\r
+\r
+ @return EFI_SUCCESS MRC Config parameters updated from hob.\r
+ @return EFI_NOT_FOUND Platform Info or MRC Config parameters not found.\r
+ @return EFI_INVALID_PARAMETER Wrong params in hob.\r
+**/\r
+EFI_STATUS\r
+MrcConfigureFromInfoHob (\r
+ OUT MRC_PARAMS *MrcData\r
+ )\r
+{\r
+ PDAT_MRC_ITEM *ItemData;\r
+\r
+ ItemData = (PDAT_MRC_ITEM *)PcdGetPtr (PcdMrcParameters);\r
+\r
+ MrcData->channel_enables = ItemData->ChanMask;\r
+ MrcData->channel_width = ItemData->ChanWidth;\r
+ MrcData->address_mode = ItemData->AddrMode;\r
+ // Enable scrambling if requested.\r
+ MrcData->scrambling_enables = (ItemData->Flags & PDAT_MRC_FLAG_SCRAMBLE_EN) != 0;\r
+ MrcData->ddr_type = ItemData->DramType;\r
+ MrcData->dram_width = ItemData->DramWidth;\r
+ MrcData->ddr_speed = ItemData->DramSpeed;\r
+ // Enable ECC if requested.\r
+ MrcData->rank_enables = ItemData->RankMask;\r
+ MrcData->params.DENSITY = ItemData->DramDensity;\r
+ MrcData->params.tCL = ItemData->tCL;\r
+ MrcData->params.tRAS = ItemData->tRAS;\r
+ MrcData->params.tWTR = ItemData->tWTR;\r
+ MrcData->params.tRRD = ItemData->tRRD;\r
+ MrcData->params.tFAW = ItemData->tFAW;\r
+\r
+ MrcData->refresh_rate = ItemData->SrInt;\r
+ MrcData->sr_temp_range = ItemData->SrTemp;\r
+ MrcData->ron_value = ItemData->DramRonVal;\r
+ MrcData->rtt_nom_value = ItemData->DramRttNomVal;\r
+ MrcData->rd_odt_value = ItemData->SocRdOdtVal;\r
+\r
+ DEBUG ((EFI_D_INFO, "MRC dram_width %d\n", MrcData->dram_width));\r
+ DEBUG ((EFI_D_INFO, "MRC rank_enables %d\n",MrcData->rank_enables));\r
+ DEBUG ((EFI_D_INFO, "MRC ddr_speed %d\n", MrcData->ddr_speed));\r
+ DEBUG ((EFI_D_INFO, "MRC flags: %s\n",\r
+ (MrcData->scrambling_enables) ? L"SCRAMBLE_EN" : L""\r
+ ));\r
+\r
+ DEBUG ((EFI_D_INFO, "MRC density=%d tCL=%d tRAS=%d tWTR=%d tRRD=%d tFAW=%d\n",\r
+ MrcData->params.DENSITY,\r
+ MrcData->params.tCL,\r
+ MrcData->params.tRAS,\r
+ MrcData->params.tWTR,\r
+ MrcData->params.tRRD,\r
+ MrcData->params.tFAW\r
+ ));\r
+\r
+ return EFI_SUCCESS;\r
+}\r
+\r
+/**\r
+\r
+ Configure ECC scrub\r
+\r
+ @param MrcData - MRC configuration\r
+\r
+**/\r
+VOID\r
+EccScrubSetup(\r
+ const MRC_PARAMS *MrcData\r
+ )\r
+{\r
+ UINT32 BgnAdr = 0;\r
+ UINT32 EndAdr = MrcData->mem_size;\r
+ UINT32 BlkSize = PcdGet8(PcdEccScrubBlkSize) & SCRUB_CFG_BLOCKSIZE_MASK;\r
+ UINT32 Interval = PcdGet8(PcdEccScrubInterval) & SCRUB_CFG_INTERVAL_MASK;\r
+\r
+ if( MrcData->ecc_enables == 0 || MrcData->boot_mode == bmS3 || Interval == 0) {\r
+ // No scrub configuration needed if ECC not enabled\r
+ // On S3 resume reconfiguration is done as part of resume\r
+ // script, see SNCS3Save.c ==> SaveRuntimeScriptTable()\r
+ // Also if PCD disables scrub, then we do nothing.\r
+ return;\r
+ }\r
+\r
+ QNCPortWrite (QUARK_NC_RMU_SB_PORT_ID, QUARK_NC_ECC_SCRUB_END_MEM_REG, EndAdr);\r
+ QNCPortWrite (QUARK_NC_RMU_SB_PORT_ID, QUARK_NC_ECC_SCRUB_START_MEM_REG, BgnAdr);\r
+ QNCPortWrite (QUARK_NC_RMU_SB_PORT_ID, QUARK_NC_ECC_SCRUB_NEXT_READ_REG, BgnAdr);\r
+ QNCPortWrite (QUARK_NC_RMU_SB_PORT_ID, QUARK_NC_ECC_SCRUB_CONFIG_REG,\r
+ Interval << SCRUB_CFG_INTERVAL_SHIFT |\r
+ BlkSize << SCRUB_CFG_BLOCKSIZE_SHIFT);\r
+\r
+ McD0PciCfg32 (QNC_ACCESS_PORT_MCR) = SCRUB_RESUME_MSG();\r
+}\r
+\r
+/** Post InstallS3Memory / InstallEfiMemory tasks given MrcData context.\r
+\r
+ @param[in] MrcData MRC configuration.\r
+ @param[in] IsS3 TRUE if after InstallS3Memory.\r
+\r
+**/\r
+VOID\r
+PostInstallMemory (\r
+ IN MRC_PARAMS *MrcData,\r
+ IN BOOLEAN IsS3\r
+ )\r
+{\r
+ UINT32 RmuMainDestBaseAddress;\r
+ UINT32 *RmuMainSrcBaseAddress;\r
+ UINTN RmuMainSize;\r
+ EFI_STATUS Status;\r
+\r
+ //\r
+ // Setup ECC policy (All boot modes).\r
+ //\r
+ QNCPolicyDblEccBitErr (V_WDT_CONTROL_DBL_ECC_BIT_ERR_WARM);\r
+\r
+ //\r
+ // Find the 64KB of memory for Rmu Main at the top of available memory.\r
+ //\r
+ InfoPostInstallMemory (&RmuMainDestBaseAddress, NULL, NULL);\r
+ DEBUG ((EFI_D_INFO, "RmuMain Base Address : 0x%x\n", RmuMainDestBaseAddress));\r
+\r
+ //\r
+ // Relocate RmuMain.\r
+ //\r
+ if (IsS3) {\r
+ QNCSendOpcodeDramReady (RmuMainDestBaseAddress);\r
+ } else {\r
+ Status = PlatformFindFvFileRawDataSection (NULL, PcdGetPtr(PcdQuarkMicrocodeFile), (VOID **) &RmuMainSrcBaseAddress, &RmuMainSize);\r
+ ASSERT_EFI_ERROR (Status);\r
+ if (!EFI_ERROR (Status)) {\r
+ DEBUG ((EFI_D_INFO, "Found Microcode ADDR:SIZE 0x%08x:0x%04x\n", (UINTN) RmuMainSrcBaseAddress, RmuMainSize));\r
+ }\r
+\r
+ RmuMainRelocation (RmuMainDestBaseAddress, (UINT32) RmuMainSrcBaseAddress, RmuMainSize);\r
+ QNCSendOpcodeDramReady (RmuMainDestBaseAddress);\r
+ EccScrubSetup (MrcData);\r
+ }\r
+}\r
+\r
+/**\r
+\r
+ Do memory initialisation for QNC DDR3 SDRAM Controller\r
+\r
+ @param FfsHeader Not used.\r
+ @param PeiServices General purpose services available to every PEIM.\r
+\r
+ @return EFI_SUCCESS Memory initialisation completed successfully.\r
+ All other error conditions encountered result in an ASSERT.\r
+\r
+**/\r
+EFI_STATUS\r
+MemoryInit (\r
+ IN EFI_PEI_SERVICES **PeiServices\r
+ )\r
+{\r
+ MRC_PARAMS MrcData;\r
+ EFI_BOOT_MODE BootMode;\r
+ EFI_STATUS Status;\r
+ EFI_PEI_READ_ONLY_VARIABLE2_PPI *VariableServices;\r
+ EFI_STATUS_CODE_VALUE ErrorCodeValue;\r
+ PEI_QNC_MEMORY_INIT_PPI *QncMemoryInitPpi;\r
+ UINT16 PmswAdr;\r
+\r
+ ErrorCodeValue = 0;\r
+\r
+ //\r
+ // It is critical that both of these data structures are initialized to 0.\r
+ // This PEIM knows the number of DIMMs in the system and works with that\r
+ // information. The MCH PEIM that consumes these data structures does not\r
+ // know the number of DIMMs so it expects the entire structure to be\r
+ // properly initialized. By initializing these to zero, all flags indicating\r
+ // that the SPD is present or the row should be configured are set to false.\r
+ //\r
+ ZeroMem (&MrcData, sizeof(MrcData));\r
+\r
+ //\r
+ // Get necessary PPI\r
+ //\r
+ Status = PeiServicesLocatePpi (\r
+ &gEfiPeiReadOnlyVariable2PpiGuid, // GUID\r
+ 0, // INSTANCE\r
+ NULL, // EFI_PEI_PPI_DESCRIPTOR\r
+ (VOID **)&VariableServices // PPI\r
+ );\r
+ ASSERT_EFI_ERROR (Status);\r
+\r
+ //\r
+ // Determine boot mode\r
+ //\r
+ Status = PeiServicesGetBootMode (&BootMode);\r
+ ASSERT_EFI_ERROR (Status);\r
+\r
+ //\r
+ // Initialize Error type for reporting status code\r
+ //\r
+ switch (BootMode) {\r
+ case BOOT_ON_FLASH_UPDATE:\r
+ ErrorCodeValue = EFI_COMPUTING_UNIT_MEMORY + EFI_CU_MEMORY_EC_UPDATE_FAIL;\r
+ break;\r
+ case BOOT_ON_S3_RESUME:\r
+ ErrorCodeValue = EFI_COMPUTING_UNIT_MEMORY + EFI_CU_MEMORY_EC_S3_RESUME_FAIL;\r
+ break;\r
+ default:\r
+ ErrorCodeValue = EFI_COMPUTING_UNIT_MEMORY;\r
+ break;\r
+ }\r
+\r
+ //\r
+ // Specify MRC boot mode\r
+ //\r
+ switch (BootMode) {\r
+ case BOOT_ON_S3_RESUME:\r
+ case BOOT_ON_FLASH_UPDATE:\r
+ MrcData.boot_mode = bmS3;\r
+ break;\r
+ case BOOT_ASSUMING_NO_CONFIGURATION_CHANGES:\r
+ MrcData.boot_mode = bmFast;\r
+ break;\r
+ default:\r
+ MrcData.boot_mode = bmCold;\r
+ break;\r
+ }\r
+\r
+ //\r
+ // Configure MRC input parameters.\r
+ //\r
+ Status = MrcConfigureFromMcFuses (&MrcData);\r
+ ASSERT_EFI_ERROR (Status);\r
+ Status = MrcConfigureFromInfoHob (&MrcData);\r
+ ASSERT_EFI_ERROR (Status);\r
+ MrcUartConfig(&MrcData);\r
+\r
+ if (BootMode == BOOT_IN_RECOVERY_MODE) {\r
+ //\r
+ // Always do bmCold on recovery.\r
+ //\r
+ DEBUG ((DEBUG_INFO, "MemoryInit:Force bmCold on Recovery\n"));\r
+ MrcData.boot_mode = bmCold;\r
+ } else {\r
+\r
+ //\r
+ // Load Memory configuration data saved in previous boot from variable\r
+ //\r
+ Status = LoadConfig (\r
+ PeiServices,\r
+ VariableServices,\r
+ &MrcData\r
+ );\r
+\r
+ if (EFI_ERROR (Status)) {\r
+\r
+ switch (BootMode) {\r
+ case BOOT_ON_S3_RESUME:\r
+ case BOOT_ON_FLASH_UPDATE:\r
+ REPORT_STATUS_CODE (\r
+ EFI_ERROR_CODE + EFI_ERROR_UNRECOVERED,\r
+ ErrorCodeValue\r
+ );\r
+ PeiServicesResetSystem ();\r
+ break;\r
+\r
+ default:\r
+ MrcData.boot_mode = bmCold;\r
+ break;\r
+ }\r
+ }\r
+ }\r
+\r
+ //\r
+ // Locate Memory Reference Code PPI\r
+ //\r
+ Status = PeiServicesLocatePpi (\r
+ &gQNCMemoryInitPpiGuid, // GUID\r
+ 0, // INSTANCE\r
+ NULL, // EFI_PEI_PPI_DESCRIPTOR\r
+ (VOID **)&QncMemoryInitPpi // PPI\r
+ );\r
+ ASSERT_EFI_ERROR (Status);\r
+\r
+ PmswAdr = (UINT16)(LpcPciCfg32 (R_QNC_LPC_GPE0BLK) & 0xFFFF) + R_QNC_GPE0BLK_PMSW;\r
+ if( IoRead32 (PmswAdr) & B_QNC_GPE0BLK_PMSW_DRAM_INIT) {\r
+ // MRC did not complete last execution, force cold boot path\r
+ MrcData.boot_mode = bmCold;\r
+ }\r
+\r
+ // Mark MRC pending\r
+ IoOr32 (PmswAdr, (UINT32)B_QNC_GPE0BLK_PMSW_DRAM_INIT);\r
+\r
+ //\r
+ // Call Memory Reference Code's Routines\r
+ //\r
+ QncMemoryInitPpi->MrcStart (&MrcData);\r
+\r
+ // Mark MRC completed\r
+ IoAnd32 (PmswAdr, ~(UINT32)B_QNC_GPE0BLK_PMSW_DRAM_INIT);\r
+\r
+\r
+ //\r
+ // Note emulation platform has to read actual memory size\r
+ // MrcData.mem_size from PcdGet32 (PcdMemorySize);\r
+\r
+ if (BootMode == BOOT_ON_S3_RESUME) {\r
+\r
+ DEBUG ((EFI_D_INFO, "Following BOOT_ON_S3_RESUME boot path.\n"));\r
+\r
+ Status = InstallS3Memory (PeiServices, VariableServices, MrcData.mem_size);\r
+ if (EFI_ERROR (Status)) {\r
+ REPORT_STATUS_CODE (\r
+ EFI_ERROR_CODE + EFI_ERROR_UNRECOVERED,\r
+ ErrorCodeValue\r
+ );\r
+ PeiServicesResetSystem ();\r
+ }\r
+ PostInstallMemory (&MrcData, TRUE);\r
+ return EFI_SUCCESS;\r
+ }\r
+\r
+ //\r
+ // Assign physical memory to PEI and DXE\r
+ //\r
+ DEBUG ((EFI_D_INFO, "InstallEfiMemory.\n"));\r
+\r
+ Status = InstallEfiMemory (\r
+ PeiServices,\r
+ VariableServices,\r
+ BootMode,\r
+ MrcData.mem_size\r
+ );\r
+ ASSERT_EFI_ERROR (Status);\r
+\r
+ PostInstallMemory (&MrcData, FALSE);\r
+\r
+ //\r
+ // Save current configuration into Hob and will save into Variable later in DXE\r
+ //\r
+ DEBUG ((EFI_D_INFO, "SaveConfig.\n"));\r
+ Status = SaveConfig (\r
+ &MrcData\r
+ );\r
+ ASSERT_EFI_ERROR (Status);\r
+\r
+ DEBUG ((EFI_D_INFO, "MemoryInit Complete.\n"));\r
+\r
+ return EFI_SUCCESS;\r
+}\r
+\r
+/**\r
+\r
+ This function saves a config to a HOB.\r
+\r
+ @param RowInfo The MCH row configuration information.\r
+ @param TimingData Timing data to be saved.\r
+ @param RowConfArray Row configuration information for each row in the system.\r
+ @param SpdData SPD info read for each DIMM slot in the system.\r
+\r
+ @return EFI_SUCCESS: The function completed successfully.\r
+\r
+**/\r
+EFI_STATUS\r
+SaveConfig (\r
+ IN MRC_PARAMS *MrcData\r
+ )\r
+{\r
+ //\r
+ // Build HOB data for Memory Config\r
+ // HOB data size (stored in variable) is required to be multiple of 8 bytes\r
+ //\r
+ BuildGuidDataHob (\r
+ &gEfiMemoryConfigDataGuid,\r
+ (VOID *) &MrcData->timings,\r
+ ((sizeof (MrcData->timings) + 0x7) & (~0x7))\r
+ );\r
+\r
+ DEBUG ((EFI_D_INFO, "IIO IoApicBase = %x IoApicLimit=%x\n", IOAPIC_BASE, (IOAPIC_BASE + IOAPIC_SIZE - 1)));\r
+ DEBUG ((EFI_D_INFO, "IIO RcbaAddress = %x\n", (UINT32)PcdGet64 (PcdRcbaMmioBaseAddress)));\r
+\r
+ return EFI_SUCCESS;\r
+}\r
+\r
+/**\r
+\r
+ Load a configuration stored in a variable.\r
+\r
+ @param TimingData Timing data to be loaded from NVRAM.\r
+ @param RowConfArray Row configuration information for each row in the system.\r
+\r
+ @return EFI_SUCCESS The function completed successfully.\r
+ Other Could not read variable.\r
+\r
+**/\r
+EFI_STATUS\r
+LoadConfig (\r
+ IN EFI_PEI_SERVICES **PeiServices,\r
+ IN EFI_PEI_READ_ONLY_VARIABLE2_PPI *VariableServices,\r
+ IN OUT MRC_PARAMS *MrcData\r
+ )\r
+{\r
+ EFI_STATUS Status;\r
+ UINTN BufferSize;\r
+ PLATFORM_VARIABLE_MEMORY_CONFIG_DATA VarData;\r
+\r
+ BufferSize = ((sizeof (VarData.timings) + 0x7) & (~0x7)); // HOB data size (stored in variable) is required to be multiple of 8bytes\r
+\r
+ Status = VariableServices->GetVariable (\r
+ VariableServices,\r
+ EFI_MEMORY_CONFIG_DATA_NAME,\r
+ &gEfiMemoryConfigDataGuid,\r
+ NULL,\r
+ &BufferSize,\r
+ &VarData.timings\r
+ );\r
+ if (!EFI_ERROR (Status)) {\r
+ CopyMem (&MrcData->timings, &VarData.timings, sizeof(MrcData->timings));\r
+ }\r
+ return Status;\r
+}\r
+\r
+/**\r
+\r
+ This function installs memory.\r
+\r
+ @param PeiServices PEI Services table.\r
+ @param BootMode The specific boot path that is being followed\r
+ @param Mch Pointer to the DualChannelDdrMemoryInit PPI\r
+ @param RowConfArray Row configuration information for each row in the system.\r
+\r
+ @return EFI_SUCCESS The function completed successfully.\r
+ EFI_INVALID_PARAMETER One of the input parameters was invalid.\r
+ EFI_ABORTED An error occurred.\r
+\r
+**/\r
+EFI_STATUS\r
+InstallEfiMemory (\r
+ IN EFI_PEI_SERVICES **PeiServices,\r
+ IN EFI_PEI_READ_ONLY_VARIABLE2_PPI *VariableServices,\r
+ IN EFI_BOOT_MODE BootMode,\r
+ IN UINT32 TotalMemorySize\r
+ )\r
+{\r
+ EFI_PHYSICAL_ADDRESS PeiMemoryBaseAddress;\r
+ EFI_SMRAM_HOB_DESCRIPTOR_BLOCK *SmramHobDescriptorBlock;\r
+ EFI_STATUS Status;\r
+ EFI_PEI_HOB_POINTERS Hob;\r
+ PEI_DUAL_CHANNEL_DDR_MEMORY_MAP_RANGE MemoryMap[MAX_RANGES];\r
+ UINT8 Index;\r
+ UINT8 NumRanges;\r
+ UINT8 SmramIndex;\r
+ UINT8 SmramRanges;\r
+ UINT64 PeiMemoryLength;\r
+ UINTN BufferSize;\r
+ UINTN PeiMemoryIndex;\r
+ UINTN RequiredMemSize;\r
+ EFI_RESOURCE_ATTRIBUTE_TYPE Attribute;\r
+ EFI_PHYSICAL_ADDRESS BadMemoryAddress;\r
+ EFI_SMRAM_DESCRIPTOR DescriptorAcpiVariable;\r
+ VOID *CapsuleBuffer;\r
+ UINTN CapsuleBufferLength;\r
+ PEI_CAPSULE_PPI *Capsule;\r
+ VOID *LargeMemRangeBuf;\r
+ UINTN LargeMemRangeBufLen;\r
+\r
+ //\r
+ // Test the memory from 1M->TOM\r
+ //\r
+ if (BootMode != BOOT_ON_FLASH_UPDATE) {\r
+ Status = BaseMemoryTest (\r
+ PeiServices,\r
+ 0x100000,\r
+ (TotalMemorySize - 0x100000),\r
+ Quick,\r
+ &BadMemoryAddress\r
+ );\r
+ ASSERT_EFI_ERROR (Status);\r
+ }\r
+\r
+\r
+ //\r
+ // Get the Memory Map\r
+ //\r
+ NumRanges = MAX_RANGES;\r
+\r
+ ZeroMem (MemoryMap, sizeof (PEI_DUAL_CHANNEL_DDR_MEMORY_MAP_RANGE) * NumRanges);\r
+\r
+ Status = GetMemoryMap (\r
+ PeiServices,\r
+ TotalMemorySize,\r
+ (PEI_DUAL_CHANNEL_DDR_MEMORY_MAP_RANGE *) MemoryMap,\r
+ &NumRanges\r
+ );\r
+ ASSERT_EFI_ERROR (Status);\r
+\r
+ //\r
+ // Find the highest memory range in processor native address space to give to\r
+ // PEI. Then take the top.\r
+ //\r
+ PeiMemoryBaseAddress = 0;\r
+\r
+ //\r
+ // Query the platform for the minimum memory size\r
+ //\r
+\r
+ Status = GetPlatformMemorySize (\r
+ PeiServices,\r
+ BootMode,\r
+ &PeiMemoryLength\r
+ );\r
+ ASSERT_EFI_ERROR (Status);\r
+\r
+ //\r
+ // Get required memory size for ACPI use. This helps to put ACPI memory on the topest\r
+ //\r
+ RequiredMemSize = 0;\r
+ RetriveRequiredMemorySize (PeiServices, &RequiredMemSize);\r
+\r
+ PeiMemoryIndex = 0;\r
+\r
+ for (Index = 0; Index < NumRanges; Index++)\r
+ {\r
+ DEBUG ((EFI_D_INFO, "Found 0x%x bytes at ", MemoryMap[Index].RangeLength));\r
+ DEBUG ((EFI_D_INFO, "0x%x.\n", MemoryMap[Index].PhysicalAddress));\r
+\r
+ if ((MemoryMap[Index].Type == DualChannelDdrMainMemory) &&\r
+ (MemoryMap[Index].PhysicalAddress + MemoryMap[Index].RangeLength < MAX_ADDRESS) &&\r
+ (MemoryMap[Index].PhysicalAddress >= PeiMemoryBaseAddress) &&\r
+ (MemoryMap[Index].RangeLength >= PeiMemoryLength)) {\r
+ PeiMemoryBaseAddress = MemoryMap[Index].PhysicalAddress +\r
+ MemoryMap[Index].RangeLength -\r
+ PeiMemoryLength;\r
+ PeiMemoryIndex = Index;\r
+ }\r
+ }\r
+\r
+ //\r
+ // Find the largest memory range excluding that given to PEI.\r
+ //\r
+ LargeMemRangeBuf = NULL;\r
+ LargeMemRangeBufLen = 0;\r
+ for (Index = 0; Index < NumRanges; Index++) {\r
+ if ((MemoryMap[Index].Type == DualChannelDdrMainMemory) &&\r
+ (MemoryMap[Index].PhysicalAddress + MemoryMap[Index].RangeLength < MAX_ADDRESS)) {\r
+ if (Index != PeiMemoryIndex) {\r
+ if (MemoryMap[Index].RangeLength > LargeMemRangeBufLen) {\r
+ LargeMemRangeBuf = (VOID *) ((UINTN) MemoryMap[Index].PhysicalAddress);\r
+ LargeMemRangeBufLen = (UINTN) MemoryMap[Index].RangeLength;\r
+ }\r
+ } else {\r
+ if ((MemoryMap[Index].RangeLength - PeiMemoryLength) >= LargeMemRangeBufLen) {\r
+ LargeMemRangeBuf = (VOID *) ((UINTN) MemoryMap[Index].PhysicalAddress);\r
+ LargeMemRangeBufLen = (UINTN) (MemoryMap[Index].RangeLength - PeiMemoryLength);\r
+ }\r
+ }\r
+ }\r
+ }\r
+\r
+ Capsule = NULL;\r
+ CapsuleBuffer = NULL;\r
+ CapsuleBufferLength = 0;\r
+ if (BootMode == BOOT_ON_FLASH_UPDATE) {\r
+ Status = PeiServicesLocatePpi (\r
+ &gPeiCapsulePpiGuid, // GUID\r
+ 0, // INSTANCE\r
+ NULL, // EFI_PEI_PPI_DESCRIPTOR\r
+ (VOID **)&Capsule // PPI\r
+ );\r
+ ASSERT_EFI_ERROR (Status);\r
+\r
+ if (Status == EFI_SUCCESS) {\r
+ CapsuleBuffer = LargeMemRangeBuf;\r
+ CapsuleBufferLength = LargeMemRangeBufLen;\r
+\r
+ //\r
+ // Call the Capsule PPI Coalesce function to coalesce the capsule data.\r
+ //\r
+ Status = Capsule->Coalesce (\r
+ PeiServices,\r
+ &CapsuleBuffer,\r
+ &CapsuleBufferLength\r
+ );\r
+ //\r
+ // If it failed, then NULL out our capsule PPI pointer so that the capsule\r
+ // HOB does not get created below.\r
+ //\r
+ if (Status != EFI_SUCCESS) {\r
+ Capsule = NULL;\r
+ }\r
+ }\r
+ }\r
+\r
+ //\r
+ // Set up the IMR policy required for this platform\r
+ //\r
+ Status = SetPlatformImrPolicy (\r
+ PeiMemoryBaseAddress,\r
+ PeiMemoryLength,\r
+ RequiredMemSize\r
+ );\r
+ ASSERT_EFI_ERROR (Status);\r
+\r
+ //\r
+ // Carve out the top memory reserved for ACPI\r
+ //\r
+ Status = PeiServicesInstallPeiMemory (PeiMemoryBaseAddress, (PeiMemoryLength - RequiredMemSize));\r
+ ASSERT_EFI_ERROR (Status);\r
+\r
+ BuildResourceDescriptorHob (\r
+ EFI_RESOURCE_SYSTEM_MEMORY, // MemoryType,\r
+ (\r
+ EFI_RESOURCE_ATTRIBUTE_PRESENT |\r
+ EFI_RESOURCE_ATTRIBUTE_INITIALIZED |\r
+ EFI_RESOURCE_ATTRIBUTE_TESTED |\r
+ EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |\r
+ EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |\r
+ EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |\r
+ EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE\r
+ ),\r
+ PeiMemoryBaseAddress, // MemoryBegin\r
+ PeiMemoryLength // MemoryLength\r
+ );\r
+\r
+ //\r
+ // Install physical memory descriptor hobs for each memory range.\r
+ //\r
+ SmramRanges = 0;\r
+ for (Index = 0; Index < NumRanges; Index++) {\r
+ Attribute = 0;\r
+ if (MemoryMap[Index].Type == DualChannelDdrMainMemory)\r
+ {\r
+ if (Index == PeiMemoryIndex) {\r
+ //\r
+ // This is a partially tested Main Memory range, give it to EFI\r
+ //\r
+ BuildResourceDescriptorHob (\r
+ EFI_RESOURCE_SYSTEM_MEMORY,\r
+ (\r
+ EFI_RESOURCE_ATTRIBUTE_PRESENT |\r
+ EFI_RESOURCE_ATTRIBUTE_INITIALIZED |\r
+ EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |\r
+ EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |\r
+ EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |\r
+ EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE\r
+ ),\r
+ MemoryMap[Index].PhysicalAddress,\r
+ MemoryMap[Index].RangeLength - PeiMemoryLength\r
+ );\r
+ } else {\r
+ //\r
+ // This is an untested Main Memory range, give it to EFI\r
+ //\r
+ BuildResourceDescriptorHob (\r
+ EFI_RESOURCE_SYSTEM_MEMORY, // MemoryType,\r
+ (\r
+ EFI_RESOURCE_ATTRIBUTE_PRESENT |\r
+ EFI_RESOURCE_ATTRIBUTE_INITIALIZED |\r
+ EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |\r
+ EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |\r
+ EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |\r
+ EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE\r
+ ),\r
+ MemoryMap[Index].PhysicalAddress, // MemoryBegin\r
+ MemoryMap[Index].RangeLength // MemoryLength\r
+ );\r
+ }\r
+ } else {\r
+ if ((MemoryMap[Index].Type == DualChannelDdrSmramCacheable) ||\r
+ (MemoryMap[Index].Type == DualChannelDdrSmramNonCacheable)) {\r
+ SmramRanges++;\r
+ }\r
+ if ((MemoryMap[Index].Type == DualChannelDdrSmramNonCacheable) ||\r
+ (MemoryMap[Index].Type == DualChannelDdrGraphicsMemoryNonCacheable)) {\r
+ Attribute |= EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE;\r
+ }\r
+ if ((MemoryMap[Index].Type == DualChannelDdrSmramCacheable) ||\r
+ (MemoryMap[Index].Type == DualChannelDdrGraphicsMemoryCacheable)) {\r
+ //\r
+ // TSEG and HSEG can be used with a write-back(WB) cache policy; however,\r
+ // the specification requires that the TSEG and HSEG space be cached only\r
+ // inside of the SMI handler. when using HSEG or TSEG an IA-32 processor\r
+ // does not automatically write back and invalidate its cache before entering\r
+ // SMM or before existing SMM therefore any MTRR defined for the active TSEG\r
+ // or HSEG must be set to un-cacheable(UC) outside of SMM.\r
+ //\r
+ Attribute |= EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE;\r
+ }\r
+ if (MemoryMap[Index].Type == DualChannelDdrReservedMemory) {\r
+ Attribute |= EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |\r
+ EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE;\r
+ }\r
+ //\r
+ // Make sure non-system memory is marked as reserved\r
+ //\r
+ BuildResourceDescriptorHob (\r
+ EFI_RESOURCE_MEMORY_RESERVED, // MemoryType,\r
+ Attribute, // MemoryAttribute\r
+ MemoryMap[Index].PhysicalAddress, // MemoryBegin\r
+ MemoryMap[Index].RangeLength // MemoryLength\r
+ );\r
+ }\r
+ }\r
+\r
+ //\r
+ // Allocate one extra EFI_SMRAM_DESCRIPTOR to describe a page of SMRAM memory that contains a pointer\r
+ // to the SMM Services Table that is required on the S3 resume path\r
+ //\r
+ ASSERT (SmramRanges > 0);\r
+ BufferSize = sizeof (EFI_SMRAM_HOB_DESCRIPTOR_BLOCK);\r
+ BufferSize += ((SmramRanges - 1) * sizeof (EFI_SMRAM_DESCRIPTOR));\r
+\r
+ Hob.Raw = BuildGuidHob (\r
+ &gEfiSmmPeiSmramMemoryReserveGuid,\r
+ BufferSize\r
+ );\r
+ ASSERT (Hob.Raw);\r
+\r
+ SmramHobDescriptorBlock = (EFI_SMRAM_HOB_DESCRIPTOR_BLOCK *) (Hob.Raw);\r
+ SmramHobDescriptorBlock->NumberOfSmmReservedRegions = SmramRanges;\r
+\r
+ SmramIndex = 0;\r
+ for (Index = 0; Index < NumRanges; Index++) {\r
+ if ((MemoryMap[Index].Type == DualChannelDdrSmramCacheable) ||\r
+ (MemoryMap[Index].Type == DualChannelDdrSmramNonCacheable)\r
+ ) {\r
+ //\r
+ // This is an SMRAM range, create an SMRAM descriptor\r
+ //\r
+ SmramHobDescriptorBlock->Descriptor[SmramIndex].PhysicalStart = MemoryMap[Index].PhysicalAddress;\r
+ SmramHobDescriptorBlock->Descriptor[SmramIndex].CpuStart = MemoryMap[Index].CpuAddress;\r
+ SmramHobDescriptorBlock->Descriptor[SmramIndex].PhysicalSize = MemoryMap[Index].RangeLength;\r
+ if (MemoryMap[Index].Type == DualChannelDdrSmramCacheable) {\r
+ SmramHobDescriptorBlock->Descriptor[SmramIndex].RegionState = EFI_SMRAM_CLOSED | EFI_CACHEABLE;\r
+ } else {\r
+ SmramHobDescriptorBlock->Descriptor[SmramIndex].RegionState = EFI_SMRAM_CLOSED;\r
+ }\r
+\r
+ SmramIndex++;\r
+ }\r
+ }\r
+\r
+ //\r
+ // Build a HOB with the location of the reserved memory range.\r
+ //\r
+ CopyMem(&DescriptorAcpiVariable, &SmramHobDescriptorBlock->Descriptor[SmramRanges-1], sizeof(EFI_SMRAM_DESCRIPTOR));\r
+ DescriptorAcpiVariable.CpuStart += RESERVED_CPU_S3_SAVE_OFFSET;\r
+ BuildGuidDataHob (\r
+ &gEfiAcpiVariableGuid,\r
+ &DescriptorAcpiVariable,\r
+ sizeof (EFI_SMRAM_DESCRIPTOR)\r
+ );\r
+\r
+ //\r
+ // If we found the capsule PPI (and we didn't have errors), then\r
+ // call the capsule PEIM to allocate memory for the capsule.\r
+ //\r
+ if (Capsule != NULL) {\r
+ Status = Capsule->CreateState (PeiServices, CapsuleBuffer, CapsuleBufferLength);\r
+ }\r
+\r
+ return EFI_SUCCESS;\r
+}\r
+\r
+/**\r
+\r
+ Find memory that is reserved so PEI has some to use.\r
+\r
+ @param PeiServices PEI Services table.\r
+ @param VariableSevices Variable PPI instance.\r
+\r
+ @return EFI_SUCCESS The function completed successfully.\r
+ Error value from LocatePpi()\r
+ Error Value from VariableServices->GetVariable()\r
+\r
+**/\r
+EFI_STATUS\r
+InstallS3Memory (\r
+ IN EFI_PEI_SERVICES **PeiServices,\r
+ IN EFI_PEI_READ_ONLY_VARIABLE2_PPI *VariableServices,\r
+ IN UINT32 TotalMemorySize\r
+ )\r
+{\r
+ EFI_STATUS Status;\r
+ UINTN S3MemoryBase;\r
+ UINTN S3MemorySize;\r
+ UINT8 SmramRanges;\r
+ UINT8 NumRanges;\r
+ UINT8 Index;\r
+ UINT8 SmramIndex;\r
+ UINTN BufferSize;\r
+ EFI_PEI_HOB_POINTERS Hob;\r
+ EFI_SMRAM_HOB_DESCRIPTOR_BLOCK *SmramHobDescriptorBlock;\r
+ PEI_DUAL_CHANNEL_DDR_MEMORY_MAP_RANGE MemoryMap[MAX_RANGES];\r
+ RESERVED_ACPI_S3_RANGE *S3MemoryRangeData;\r
+ EFI_SMRAM_DESCRIPTOR DescriptorAcpiVariable;\r
+\r
+ //\r
+ // Get the Memory Map\r
+ //\r
+ NumRanges = MAX_RANGES;\r
+\r
+ ZeroMem (MemoryMap, sizeof (PEI_DUAL_CHANNEL_DDR_MEMORY_MAP_RANGE) * NumRanges);\r
+\r
+ Status = GetMemoryMap (\r
+ PeiServices,\r
+ TotalMemorySize,\r
+ (PEI_DUAL_CHANNEL_DDR_MEMORY_MAP_RANGE *) MemoryMap,\r
+ &NumRanges\r
+ );\r
+ ASSERT_EFI_ERROR (Status);\r
+\r
+ //\r
+ // Install physical memory descriptor hobs for each memory range.\r
+ //\r
+ SmramRanges = 0;\r
+ for (Index = 0; Index < NumRanges; Index++) {\r
+ if ((MemoryMap[Index].Type == DualChannelDdrSmramCacheable) ||\r
+ (MemoryMap[Index].Type == DualChannelDdrSmramNonCacheable)) {\r
+ SmramRanges++;\r
+ }\r
+ }\r
+\r
+ ASSERT (SmramRanges > 0);\r
+\r
+ //\r
+ // Allocate one extra EFI_SMRAM_DESCRIPTOR to describe a page of SMRAM memory that contains a pointer\r
+ // to the SMM Services Table that is required on the S3 resume path\r
+ //\r
+ BufferSize = sizeof (EFI_SMRAM_HOB_DESCRIPTOR_BLOCK);\r
+ if (SmramRanges > 0) {\r
+ BufferSize += ((SmramRanges - 1) * sizeof (EFI_SMRAM_DESCRIPTOR));\r
+ }\r
+\r
+ Hob.Raw = BuildGuidHob (\r
+ &gEfiSmmPeiSmramMemoryReserveGuid,\r
+ BufferSize\r
+ );\r
+ ASSERT (Hob.Raw);\r
+\r
+ SmramHobDescriptorBlock = (EFI_SMRAM_HOB_DESCRIPTOR_BLOCK *) (Hob.Raw);\r
+ SmramHobDescriptorBlock->NumberOfSmmReservedRegions = SmramRanges;\r
+\r
+ SmramIndex = 0;\r
+ for (Index = 0; Index < NumRanges; Index++) {\r
+ if ((MemoryMap[Index].Type == DualChannelDdrSmramCacheable) ||\r
+ (MemoryMap[Index].Type == DualChannelDdrSmramNonCacheable)\r
+ ) {\r
+ //\r
+ // This is an SMRAM range, create an SMRAM descriptor\r
+ //\r
+ SmramHobDescriptorBlock->Descriptor[SmramIndex].PhysicalStart = MemoryMap[Index].PhysicalAddress;\r
+ SmramHobDescriptorBlock->Descriptor[SmramIndex].CpuStart = MemoryMap[Index].CpuAddress;\r
+ SmramHobDescriptorBlock->Descriptor[SmramIndex].PhysicalSize = MemoryMap[Index].RangeLength;\r
+ if (MemoryMap[Index].Type == DualChannelDdrSmramCacheable) {\r
+ SmramHobDescriptorBlock->Descriptor[SmramIndex].RegionState = EFI_SMRAM_CLOSED | EFI_CACHEABLE;\r
+ } else {\r
+ SmramHobDescriptorBlock->Descriptor[SmramIndex].RegionState = EFI_SMRAM_CLOSED;\r
+ }\r
+\r
+ SmramIndex++;\r
+ }\r
+ }\r
+\r
+ //\r
+ // Build a HOB with the location of the reserved memory range.\r
+ //\r
+ CopyMem(&DescriptorAcpiVariable, &SmramHobDescriptorBlock->Descriptor[SmramRanges-1], sizeof(EFI_SMRAM_DESCRIPTOR));\r
+ DescriptorAcpiVariable.CpuStart += RESERVED_CPU_S3_SAVE_OFFSET;\r
+ BuildGuidDataHob (\r
+ &gEfiAcpiVariableGuid,\r
+ &DescriptorAcpiVariable,\r
+ sizeof (EFI_SMRAM_DESCRIPTOR)\r
+ );\r
+\r
+ //\r
+ // Get the location and size of the S3 memory range in the reserved page and\r
+ // install it as PEI Memory.\r
+ //\r
+\r
+ DEBUG ((EFI_D_INFO, "TSEG Base = 0x%08x\n", SmramHobDescriptorBlock->Descriptor[SmramRanges-1].PhysicalStart));\r
+ S3MemoryRangeData = (RESERVED_ACPI_S3_RANGE*)(UINTN)\r
+ (SmramHobDescriptorBlock->Descriptor[SmramRanges-1].PhysicalStart + RESERVED_ACPI_S3_RANGE_OFFSET);\r
+\r
+ S3MemoryBase = (UINTN) (S3MemoryRangeData->AcpiReservedMemoryBase);\r
+ DEBUG ((EFI_D_INFO, "S3MemoryBase = 0x%08x\n", S3MemoryBase));\r
+ S3MemorySize = (UINTN) (S3MemoryRangeData->AcpiReservedMemorySize);\r
+ DEBUG ((EFI_D_INFO, "S3MemorySize = 0x%08x\n", S3MemorySize));\r
+\r
+ Status = PeiServicesInstallPeiMemory (S3MemoryBase, S3MemorySize);\r
+ ASSERT_EFI_ERROR (Status);\r
+\r
+ //\r
+ // Retrieve the system memory length and build memory hob for the system\r
+ // memory above 1MB. So Memory Callback can set cache for the system memory\r
+ // correctly on S3 boot path, just like it does on Normal boot path.\r
+ //\r
+ ASSERT_EFI_ERROR ((S3MemoryRangeData->SystemMemoryLength - 0x100000) > 0);\r
+ BuildResourceDescriptorHob (\r
+ EFI_RESOURCE_SYSTEM_MEMORY,\r
+ (\r
+ EFI_RESOURCE_ATTRIBUTE_PRESENT |\r
+ EFI_RESOURCE_ATTRIBUTE_INITIALIZED |\r
+ EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |\r
+ EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |\r
+ EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |\r
+ EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE\r
+ ),\r
+ 0x100000,\r
+ S3MemoryRangeData->SystemMemoryLength - 0x100000\r
+ );\r
+\r
+ for (Index = 0; Index < NumRanges; Index++) {\r
+ if ((MemoryMap[Index].Type == DualChannelDdrMainMemory) &&\r
+ (MemoryMap[Index].PhysicalAddress + MemoryMap[Index].RangeLength < 0x100000)) {\r
+ BuildResourceDescriptorHob (\r
+ EFI_RESOURCE_SYSTEM_MEMORY,\r
+ (\r
+ EFI_RESOURCE_ATTRIBUTE_PRESENT |\r
+ EFI_RESOURCE_ATTRIBUTE_INITIALIZED |\r
+ EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |\r
+ EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |\r
+ EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |\r
+ EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE\r
+ ),\r
+ MemoryMap[Index].PhysicalAddress,\r
+ MemoryMap[Index].RangeLength\r
+ );\r
+ DEBUG ((EFI_D_INFO, "Build resource HOB for Legacy Region on S3 patch :"));\r
+ DEBUG ((EFI_D_INFO, " Memory Base:0x%lX Length:0x%lX\n", MemoryMap[Index].PhysicalAddress, MemoryMap[Index].RangeLength));\r
+ }\r
+ }\r
+\r
+ return EFI_SUCCESS;\r
+}\r
+\r
+/**\r
+\r
+ This function returns the size, in bytes, required for the DXE phase.\r
+\r
+ @param PeiServices PEI Services table.\r
+ @param Size Pointer to the size, in bytes, required for the DXE phase.\r
+\r
+ @return None\r
+\r
+**/\r
+VOID\r
+RetriveRequiredMemorySize (\r
+ IN EFI_PEI_SERVICES **PeiServices,\r
+ OUT UINTN *Size\r
+ )\r
+{\r
+ EFI_STATUS Status;\r
+ EFI_PEI_HOB_POINTERS Hob;\r
+ EFI_MEMORY_TYPE_INFORMATION *MemoryData;\r
+ UINT8 Index;\r
+ UINTN TempPageNum;\r
+\r
+ MemoryData = NULL;\r
+ TempPageNum = 0;\r
+ Index = 0;\r
+\r
+ Status = PeiServicesGetHobList ((VOID **)&Hob.Raw);\r
+ while (!END_OF_HOB_LIST (Hob)) {\r
+ if (Hob.Header->HobType == EFI_HOB_TYPE_GUID_EXTENSION &&\r
+ CompareGuid (&Hob.Guid->Name, &gEfiMemoryTypeInformationGuid)\r
+ ) {\r
+ MemoryData = (EFI_MEMORY_TYPE_INFORMATION *) (Hob.Raw + sizeof (EFI_HOB_GENERIC_HEADER) + sizeof (EFI_GUID));\r
+ break;\r
+ }\r
+\r
+ Hob.Raw = GET_NEXT_HOB (Hob);\r
+ }\r
+ //\r
+ // Platform PEIM should supply such a information. Generic PEIM doesn't assume any default value\r
+ //\r
+ if (!MemoryData) {\r
+ return ;\r
+ }\r
+\r
+ while (MemoryData[Index].Type != EfiMaxMemoryType) {\r
+ //\r
+ // Accumulate default memory size requirements\r
+ //\r
+ TempPageNum += MemoryData[Index].NumberOfPages;\r
+ Index++;\r
+ }\r
+\r
+ if (TempPageNum == 0) {\r
+ return ;\r
+ }\r
+\r
+ //\r
+ // Add additional pages used by DXE memory manager\r
+ //\r
+ (*Size) = (TempPageNum + EDKII_DXE_MEM_SIZE_PAGES) * EFI_PAGE_SIZE;\r
+\r
+ return ;\r
+}\r
+\r
+/**\r
+\r
+ This function returns the memory ranges to be enabled, along with information\r
+ describing how the range should be used.\r
+\r
+ @param PeiServices PEI Services Table.\r
+ @param TimingData Detected DDR timing parameters for installed memory.\r
+ @param RowConfArray Pointer to an array of EFI_DUAL_CHANNEL_DDR_ROW_CONFIG structures. The number\r
+ of items in the array must match MaxRows returned by the McGetRowInfo() function.\r
+ @param MemoryMap Buffer to record details of the memory ranges tobe enabled.\r
+ @param NumRanges On input, this contains the maximum number of memory ranges that can be described\r
+ in the MemoryMap buffer.\r
+\r
+ @return MemoryMap The buffer will be filled in\r
+ NumRanges will contain the actual number of memory ranges that are to be anabled.\r
+ EFI_SUCCESS The function completed successfully.\r
+\r
+**/\r
+EFI_STATUS\r
+GetMemoryMap (\r
+ IN EFI_PEI_SERVICES **PeiServices,\r
+ IN UINT32 TotalMemorySize,\r
+ IN OUT PEI_DUAL_CHANNEL_DDR_MEMORY_MAP_RANGE *MemoryMap,\r
+ IN OUT UINT8 *NumRanges\r
+ )\r
+{\r
+ EFI_PHYSICAL_ADDRESS MemorySize;\r
+ EFI_PHYSICAL_ADDRESS RowLength;\r
+ EFI_STATUS Status;\r
+ PEI_MEMORY_RANGE_PCI_MEMORY PciMemoryMask;\r
+ PEI_MEMORY_RANGE_OPTION_ROM OptionRomMask;\r
+ PEI_MEMORY_RANGE_SMRAM SmramMask;\r
+ PEI_MEMORY_RANGE_SMRAM TsegMask;\r
+ UINT32 BlockNum;\r
+ UINT8 EsmramcRegister;\r
+ UINT8 ExtendedMemoryIndex;\r
+ UINT32 Register;\r
+\r
+ if ((*NumRanges) < MAX_RANGES) {\r
+ return EFI_BUFFER_TOO_SMALL;\r
+ }\r
+\r
+ *NumRanges = 0;\r
+\r
+ //\r
+ // Find out which memory ranges to reserve on this platform\r
+ //\r
+ Status = ChooseRanges (\r
+ &OptionRomMask,\r
+ &SmramMask,\r
+ &PciMemoryMask\r
+ );\r
+ ASSERT_EFI_ERROR (Status);\r
+\r
+ //\r
+ // Generate Memory ranges for the memory map.\r
+ //\r
+ EsmramcRegister = 0;\r
+ MemorySize = 0;\r
+\r
+ RowLength = TotalMemorySize;\r
+\r
+ //\r
+ // Add memory below 640KB to the memory map. Make sure memory between\r
+ // 640KB and 1MB are reserved, even if not used for SMRAM\r
+ //\r
+ MemoryMap[*NumRanges].PhysicalAddress = MemorySize;\r
+ MemoryMap[*NumRanges].CpuAddress = MemorySize;\r
+ MemoryMap[*NumRanges].RangeLength = 0xA0000;\r
+ MemoryMap[*NumRanges].Type = DualChannelDdrMainMemory;\r
+ (*NumRanges)++;\r
+\r
+ //\r
+ // Just mark this range reserved\r
+ //\r
+ MemoryMap[*NumRanges].PhysicalAddress = 0xA0000;\r
+ MemoryMap[*NumRanges].CpuAddress = 0xA0000;\r
+ MemoryMap[*NumRanges].RangeLength = 0x60000;\r
+ MemoryMap[*NumRanges].Type = DualChannelDdrReservedMemory;\r
+ (*NumRanges)++;\r
+\r
+ RowLength -= (0x100000 - MemorySize);\r
+ MemorySize = 0x100000;\r
+\r
+ //\r
+ // Add remaining memory to the memory map\r
+ //\r
+ MemoryMap[*NumRanges].PhysicalAddress = MemorySize;\r
+ MemoryMap[*NumRanges].CpuAddress = MemorySize;\r
+ MemoryMap[*NumRanges].RangeLength = RowLength;\r
+ MemoryMap[*NumRanges].Type = DualChannelDdrMainMemory;\r
+ (*NumRanges)++;\r
+ MemorySize += RowLength;\r
+\r
+ ExtendedMemoryIndex = (UINT8) (*NumRanges - 1);\r
+\r
+ // See if we need to trim TSEG out of the highest memory range\r
+ //\r
+ if (SmramMask & PEI_MR_SMRAM_TSEG_MASK) {//pcd\r
+ //\r
+ // Create the new range for TSEG and remove that range from the previous SdrDdrMainMemory range\r
+ //\r
+ TsegMask = (SmramMask & PEI_MR_SMRAM_SIZE_MASK);\r
+\r
+ BlockNum = 1;\r
+ while (TsegMask) {\r
+ TsegMask >>= 1;\r
+ BlockNum <<= 1;\r
+ }\r
+\r
+ BlockNum >>= 1;\r
+\r
+ if (BlockNum) {\r
+\r
+ MemoryMap[*NumRanges].RangeLength = (BlockNum * 128 * 1024);\r
+ Register = (UINT32)((MemorySize - 1) & SMM_END_MASK);\r
+ MemorySize -= MemoryMap[*NumRanges].RangeLength;\r
+ MemoryMap[*NumRanges].PhysicalAddress = MemorySize;\r
+ MemoryMap[*NumRanges].CpuAddress = MemorySize;\r
+ MemoryMap[ExtendedMemoryIndex].RangeLength -= MemoryMap[*NumRanges].RangeLength;\r
+\r
+ //\r
+ // Update QuarkNcSoc HSMMCTL register\r
+ //\r
+ Register |= (UINT32)(((RShiftU64(MemorySize, 16)) & SMM_START_MASK) + (SMM_WRITE_OPEN | SMM_READ_OPEN | SMM_CODE_RD_OPEN));\r
+ QncHsmmcWrite (Register);\r
+ }\r
+\r
+ //\r
+ // Chipset only supports cacheable SMRAM\r
+ //\r
+ MemoryMap[*NumRanges].Type = DualChannelDdrSmramCacheable;\r
+\r
+ (*NumRanges)++;\r
+ }\r
+\r
+ //\r
+ // trim 64K memory from highest memory range for Rmu Main binary shadow\r
+ //\r
+ MemoryMap[*NumRanges].RangeLength = 0x10000;\r
+ MemorySize -= MemoryMap[*NumRanges].RangeLength;\r
+ MemoryMap[*NumRanges].PhysicalAddress = MemorySize;\r
+ MemoryMap[*NumRanges].CpuAddress = MemorySize;\r
+ MemoryMap[ExtendedMemoryIndex].RangeLength -= MemoryMap[*NumRanges].RangeLength;\r
+ MemoryMap[*NumRanges].Type = DualChannelDdrReservedMemory;\r
+ (*NumRanges)++;\r
+\r
+ return EFI_SUCCESS;\r
+}\r
+\r
+/**\r
+\r
+Routine Description:\r
+\r
+ Fill in bit masks to specify reserved memory ranges on the Lakeport platform\r
+\r
+Arguments:\r
+\r
+Returns:\r
+\r
+ OptionRomMask - Bit mask specifying memory regions reserved for Legacy option\r
+ ROM use (if any)\r
+\r
+ SmramMask - Bit mask specifying memory regions reserved for SMM use (if any)\r
+\r
+**/\r
+EFI_STATUS\r
+ChooseRanges (\r
+ IN OUT PEI_MEMORY_RANGE_OPTION_ROM *OptionRomMask,\r
+ IN OUT PEI_MEMORY_RANGE_SMRAM *SmramMask,\r
+ IN OUT PEI_MEMORY_RANGE_PCI_MEMORY *PciMemoryMask\r
+ )\r
+{\r
+\r
+ //\r
+ // Choose regions to reserve for Option ROM use\r
+ //\r
+ *OptionRomMask = PEI_MR_OPTION_ROM_NONE;\r
+\r
+ //\r
+ // Choose regions to reserve for SMM use (AB/H SEG and TSEG). Size is in 128K blocks\r
+ //\r
+ *SmramMask = PEI_MR_SMRAM_CACHEABLE_MASK | PEI_MR_SMRAM_TSEG_MASK | ((PcdGet32(PcdTSegSize)) >> 17);\r
+\r
+ *PciMemoryMask = 0;\r
+\r
+ return EFI_SUCCESS;\r
+}\r
+\r
+EFI_STATUS\r
+GetPlatformMemorySize (\r
+ IN EFI_PEI_SERVICES **PeiServices,\r
+ IN EFI_BOOT_MODE BootMode,\r
+ IN OUT UINT64 *MemorySize\r
+ )\r
+{\r
+ EFI_STATUS Status;\r
+ EFI_PEI_READ_ONLY_VARIABLE2_PPI *Variable;\r
+ UINTN DataSize;\r
+ EFI_MEMORY_TYPE_INFORMATION MemoryData [EfiMaxMemoryType + 1];\r
+ UINTN Index;\r
+\r
+ DataSize = sizeof (MemoryData);\r
+\r
+ if (BootMode == BOOT_IN_RECOVERY_MODE) {\r
+\r
+ //\r
+ // // Treat recovery as if variable not found (eg 1st boot).\r
+ //\r
+ Status = EFI_NOT_FOUND;\r
+\r
+ } else {\r
+ Status = PeiServicesLocatePpi (\r
+ &gEfiPeiReadOnlyVariable2PpiGuid,\r
+ 0,\r
+ NULL,\r
+ (VOID **)&Variable\r
+ );\r
+\r
+ ASSERT_EFI_ERROR (Status);\r
+\r
+ DataSize = sizeof (MemoryData);\r
+ Status = Variable->GetVariable (\r
+ Variable,\r
+ EFI_MEMORY_TYPE_INFORMATION_VARIABLE_NAME,\r
+ &gEfiMemoryTypeInformationGuid,\r
+ NULL,\r
+ &DataSize,\r
+ &MemoryData\r
+ );\r
+ }\r
+\r
+ //\r
+ // Accumulate maximum amount of memory needed\r
+ //\r
+ if (EFI_ERROR (Status)) {\r
+ //\r
+ // Start with minimum memory\r
+ //\r
+ *MemorySize = PEI_MIN_MEMORY_SIZE;\r
+\r
+ for (Index = 0; Index < sizeof(mDefaultQncMemoryTypeInformation) / sizeof (EFI_MEMORY_TYPE_INFORMATION); Index++) {\r
+ *MemorySize += mDefaultQncMemoryTypeInformation[Index].NumberOfPages * EFI_PAGE_SIZE;\r
+ }\r
+\r
+ //\r
+ // Build the GUID'd HOB for DXE\r
+ //\r
+ BuildGuidDataHob (\r
+ &gEfiMemoryTypeInformationGuid,\r
+ mDefaultQncMemoryTypeInformation,\r
+ sizeof(mDefaultQncMemoryTypeInformation)\r
+ );\r
+ } else {\r
+ //\r
+ // Start with at least PEI_MIN_MEMORY_SIZE pages of memory for the DXE Core and the DXE Stack\r
+ //\r
+\r
+ *MemorySize = PEI_MIN_MEMORY_SIZE;\r
+ for (Index = 0; Index < DataSize / sizeof (EFI_MEMORY_TYPE_INFORMATION); Index++) {\r
+ DEBUG ((EFI_D_INFO, "Index %d, Page: %d\n", Index, MemoryData[Index].NumberOfPages));\r
+ *MemorySize += MemoryData[Index].NumberOfPages * EFI_PAGE_SIZE;\r
+ }\r
+\r
+ //\r
+ // Build the GUID'd HOB for DXE\r
+ //\r
+ BuildGuidDataHob (\r
+ &gEfiMemoryTypeInformationGuid,\r
+ MemoryData,\r
+ DataSize\r
+ );\r
+\r
+ }\r
+\r
+ return EFI_SUCCESS;\r
+}\r
+\r
+\r
+EFI_STATUS\r
+BaseMemoryTest (\r
+ IN EFI_PEI_SERVICES **PeiServices,\r
+ IN EFI_PHYSICAL_ADDRESS BeginAddress,\r
+ IN UINT64 MemoryLength,\r
+ IN PEI_MEMORY_TEST_OP Operation,\r
+ OUT EFI_PHYSICAL_ADDRESS *ErrorAddress\r
+ )\r
+{\r
+ UINT32 TestPattern;\r
+ EFI_PHYSICAL_ADDRESS TempAddress;\r
+ UINT32 SpanSize;\r
+\r
+ TestPattern = 0x5A5A5A5A;\r
+ SpanSize = 0;\r
+\r
+ //\r
+ // Make sure we don't try and test anything above the max physical address range\r
+ //\r
+ ASSERT (BeginAddress + MemoryLength < MAX_ADDRESS);\r
+\r
+ switch (Operation) {\r
+ case Extensive:\r
+ SpanSize = 0x4;\r
+ break;\r
+\r
+ case Sparse:\r
+ case Quick:\r
+ SpanSize = 0x40000;\r
+ break;\r
+\r
+ case Ignore:\r
+ goto Done;\r
+ break;\r
+ }\r
+ //\r
+ // Write the test pattern into memory range\r
+ //\r
+ TempAddress = BeginAddress;\r
+ while (TempAddress < BeginAddress + MemoryLength) {\r
+ (*(UINT32 *) (UINTN) TempAddress) = TestPattern;\r
+ TempAddress += SpanSize;\r
+ }\r
+ //\r
+ // Read pattern from memory and compare it\r
+ //\r
+ TempAddress = BeginAddress;\r
+ while (TempAddress < BeginAddress + MemoryLength) {\r
+ if ((*(UINT32 *) (UINTN) TempAddress) != TestPattern) {\r
+ *ErrorAddress = TempAddress;\r
+ DEBUG ((EFI_D_ERROR, "Memory test failed at 0x%x.\n", TempAddress));\r
+ return EFI_DEVICE_ERROR;\r
+ }\r
+\r
+ TempAddress += SpanSize;\r
+ }\r
+\r
+Done:\r
+ return EFI_SUCCESS;\r
+}\r
+\r
+/**\r
+\r
+ This function sets up the platform specific IMR protection for the various\r
+ memory regions.\r
+\r
+ @param PeiMemoryBaseAddress Base address of memory allocated for PEI.\r
+ @param PeiMemoryLength Length in bytes of the PEI memory (includes ACPI memory).\r
+ @param RequiredMemSize Size in bytes of the ACPI/Runtime memory\r
+\r
+ @return EFI_SUCCESS The function completed successfully.\r
+ EFI_ACCESS_DENIED Access to IMRs failed.\r
+\r
+**/\r
+EFI_STATUS\r
+SetPlatformImrPolicy (\r
+ IN EFI_PHYSICAL_ADDRESS PeiMemoryBaseAddress,\r
+ IN UINT64 PeiMemoryLength,\r
+ IN UINTN RequiredMemSize\r
+ )\r
+{\r
+ UINT8 Index;\r
+ UINT32 Register;\r
+ UINT16 DeviceId;\r
+\r
+ //\r
+ // Check what Soc we are running on (read Host bridge DeviceId)\r
+ //\r
+ DeviceId = QNCMmPci16(0, MC_BUS, MC_DEV, MC_FUN, PCI_DEVICE_ID_OFFSET);\r
+\r
+ //\r
+ // If any IMR register is locked then we cannot proceed\r
+ //\r
+ for (Index = (QUARK_NC_MEMORY_MANAGER_IMR0+QUARK_NC_MEMORY_MANAGER_IMRXL); Index <=(QUARK_NC_MEMORY_MANAGER_IMR7+QUARK_NC_MEMORY_MANAGER_IMRXL); Index=Index+4)\r
+ {\r
+ Register = QNCPortRead (QUARK_NC_MEMORY_MANAGER_SB_PORT_ID, Index);\r
+ if (Register & IMR_LOCK) {\r
+ return EFI_ACCESS_DENIED;\r
+ }\r
+ }\r
+\r
+ //\r
+ // Add IMR0 protection for the 'PeiMemory'\r
+ //\r
+ QncImrWrite (\r
+ QUARK_NC_MEMORY_MANAGER_IMR0,\r
+ (UINT32)(((RShiftU64(PeiMemoryBaseAddress, 8)) & IMRL_MASK) | IMR_EN),\r
+ (UINT32)((RShiftU64((PeiMemoryBaseAddress+PeiMemoryLength-RequiredMemSize + EFI_PAGES_TO_SIZE(EDKII_DXE_MEM_SIZE_PAGES-1) - 1), 8)) & IMRL_MASK),\r
+ (UINT32)(CPU_SNOOP + CPU0_NON_SMM),\r
+ (UINT32)(CPU_SNOOP + CPU0_NON_SMM)\r
+ );\r
+\r
+ //\r
+ // Add IMR2 protection for shadowed RMU binary.\r
+ //\r
+ QncImrWrite (\r
+ QUARK_NC_MEMORY_MANAGER_IMR2,\r
+ (UINT32)(((RShiftU64((PeiMemoryBaseAddress+PeiMemoryLength), 8)) & IMRH_MASK) | IMR_EN),\r
+ (UINT32)((RShiftU64((PeiMemoryBaseAddress+PeiMemoryLength+PcdGet32(PcdFlashQNCMicrocodeSize)-1), 8)) & IMRH_MASK),\r
+ (UINT32)(CPU_SNOOP + RMU + CPU0_NON_SMM),\r
+ (UINT32)(CPU_SNOOP + RMU + CPU0_NON_SMM)\r
+ );\r
+\r
+ //\r
+ // Add IMR3 protection for the default SMRAM.\r
+ //\r
+ QncImrWrite (\r
+ QUARK_NC_MEMORY_MANAGER_IMR3,\r
+ (UINT32)(((RShiftU64((SMM_DEFAULT_SMBASE), 8)) & IMRL_MASK) | IMR_EN),\r
+ (UINT32)((RShiftU64((SMM_DEFAULT_SMBASE+SMM_DEFAULT_SMBASE_SIZE_BYTES-1), 8)) & IMRH_MASK),\r
+ (UINT32)(CPU_SNOOP + CPU0_NON_SMM),\r
+ (UINT32)(CPU_SNOOP + CPU0_NON_SMM)\r
+ );\r
+\r
+ //\r
+ // Add IMR5 protection for the legacy S3 and AP Startup Vector region (below 1MB).\r
+ //\r
+ QncImrWrite (\r
+ QUARK_NC_MEMORY_MANAGER_IMR5,\r
+ (UINT32)(((RShiftU64(AP_STARTUP_VECTOR, 8)) & IMRL_MASK) | IMR_EN),\r
+ (UINT32)((RShiftU64((AP_STARTUP_VECTOR + EFI_PAGE_SIZE - 1), 8)) & IMRH_MASK),\r
+ (UINT32)(CPU_SNOOP + CPU0_NON_SMM),\r
+ (UINT32)(CPU_SNOOP + CPU0_NON_SMM)\r
+ );\r
+\r
+ //\r
+ // Add IMR6 protection for the ACPI Reclaim/ACPI/Runtime Services.\r
+ //\r
+ QncImrWrite (\r
+ QUARK_NC_MEMORY_MANAGER_IMR6,\r
+ (UINT32)(((RShiftU64((PeiMemoryBaseAddress+PeiMemoryLength-RequiredMemSize+EFI_PAGES_TO_SIZE(EDKII_DXE_MEM_SIZE_PAGES-1)), 8)) & IMRL_MASK) | IMR_EN),\r
+ (UINT32)((RShiftU64((PeiMemoryBaseAddress+PeiMemoryLength-EFI_PAGE_SIZE-1), 8)) & IMRH_MASK),\r
+ (UINT32)(CPU_SNOOP + CPU0_NON_SMM),\r
+ (UINT32)(CPU_SNOOP + CPU0_NON_SMM)\r
+ );\r
+\r
+ //\r
+ // Enable IMR4 protection of eSRAM.\r
+ //\r
+ QncImrWrite (\r
+ QUARK_NC_MEMORY_MANAGER_IMR4,\r
+ (UINT32)(((RShiftU64((UINTN)PcdGet32 (PcdEsramStage1Base), 8)) & IMRL_MASK) | IMR_EN),\r
+ (UINT32)((RShiftU64(((UINTN)PcdGet32 (PcdEsramStage1Base) + (UINTN)PcdGet32 (PcdESramMemorySize) - 1), 8)) & IMRH_MASK),\r
+ (UINT32)(CPU_SNOOP + CPU0_NON_SMM),\r
+ (UINT32)(CPU_SNOOP + CPU0_NON_SMM)\r
+ );\r
+\r
+ //\r
+ // Enable Interrupt on IMR/SMM Violation\r
+ //\r
+ QNCPortWrite (QUARK_NC_MEMORY_MANAGER_SB_PORT_ID, QUARK_NC_MEMORY_MANAGER_BIMRVCTL, (UINT32)(EnableIMRInt));\r
+ if (DeviceId == QUARK2_MC_DEVICE_ID) {\r
+ QNCPortWrite (QUARK_NC_MEMORY_MANAGER_SB_PORT_ID, QUARK_NC_MEMORY_MANAGER_BSMMVCTL, (UINT32)(EnableSMMInt));\r
+ }\r
+\r
+ //\r
+ // Disable IMR7 memory protection (eSRAM + DDR3 memory) since our policies\r
+ // are now setup.\r
+ //\r
+ QncImrWrite (\r
+ QUARK_NC_MEMORY_MANAGER_IMR7,\r
+ (UINT32)(IMRL_RESET & ~IMR_EN),\r
+ (UINT32)IMRH_RESET,\r
+ (UINT32)IMRX_ALL_ACCESS,\r
+ (UINT32)IMRX_ALL_ACCESS\r
+ );\r
+\r
+ return EFI_SUCCESS;\r
+}\r
+\r
+/** Return info derived from Installing Memory by MemoryInit.\r
+\r
+ @param[out] RmuMainBaseAddressPtr Return RmuMainBaseAddress to this location.\r
+ @param[out] SmramDescriptorPtr Return start of Smram descriptor list to this location.\r
+ @param[out] NumSmramRegionsPtr Return numbers of Smram regions to this location.\r
+\r
+ @return Address of RMU shadow region at the top of available memory.\r
+ @return List of Smram descriptors for each Smram region.\r
+ @return Numbers of Smram regions.\r
+**/\r
+VOID\r
+EFIAPI\r
+InfoPostInstallMemory (\r
+ OUT UINT32 *RmuMainBaseAddressPtr OPTIONAL,\r
+ OUT EFI_SMRAM_DESCRIPTOR **SmramDescriptorPtr OPTIONAL,\r
+ OUT UINTN *NumSmramRegionsPtr OPTIONAL\r
+ )\r
+{\r
+ EFI_STATUS Status;\r
+ EFI_PEI_HOB_POINTERS Hob;\r
+ UINT64 CalcLength;\r
+ EFI_SMRAM_HOB_DESCRIPTOR_BLOCK *SmramHobDescriptorBlock;\r
+\r
+ if ((RmuMainBaseAddressPtr == NULL) && (SmramDescriptorPtr == NULL) && (NumSmramRegionsPtr == NULL)) {\r
+ return;\r
+ }\r
+\r
+ SmramHobDescriptorBlock = NULL;\r
+ if (SmramDescriptorPtr != NULL) {\r
+ *SmramDescriptorPtr = NULL;\r
+ }\r
+ if (NumSmramRegionsPtr != NULL) {\r
+ *NumSmramRegionsPtr = 0;\r
+ }\r
+\r
+ //\r
+ // Calculate RMU shadow region base address.\r
+ // Set to 1 MB. Since 1MB cacheability will always be set\r
+ // until override by CSM.\r
+ //\r
+ CalcLength = 0x100000;\r
+\r
+ Status = PeiServicesGetHobList ((VOID **) &Hob.Raw);\r
+ ASSERT_EFI_ERROR (Status);\r
+ while (!END_OF_HOB_LIST (Hob)) {\r
+ if (Hob.Header->HobType == EFI_HOB_TYPE_RESOURCE_DESCRIPTOR) {\r
+ if (Hob.ResourceDescriptor->ResourceType == EFI_RESOURCE_SYSTEM_MEMORY) {\r
+ //\r
+ // Skip the memory region below 1MB\r
+ //\r
+ if (Hob.ResourceDescriptor->PhysicalStart >= 0x100000) {\r
+ CalcLength += (UINT64) (Hob.ResourceDescriptor->ResourceLength);\r
+ }\r
+ }\r
+ } else if (Hob.Header->HobType == EFI_HOB_TYPE_GUID_EXTENSION) {\r
+ if (CompareGuid (&(Hob.Guid->Name), &gEfiSmmPeiSmramMemoryReserveGuid)) {\r
+ SmramHobDescriptorBlock = (VOID*) (Hob.Raw + sizeof (EFI_HOB_GUID_TYPE));\r
+ if (SmramDescriptorPtr != NULL) {\r
+ *SmramDescriptorPtr = SmramHobDescriptorBlock->Descriptor;\r
+ }\r
+ if (NumSmramRegionsPtr != NULL) {\r
+ *NumSmramRegionsPtr = SmramHobDescriptorBlock->NumberOfSmmReservedRegions;\r
+ }\r
+ }\r
+ }\r
+ Hob.Raw = GET_NEXT_HOB (Hob);\r
+ }\r
+\r
+ if (RmuMainBaseAddressPtr != NULL) {\r
+ *RmuMainBaseAddressPtr = (UINT32) CalcLength;\r
+ }\r
+}\r
--- /dev/null
+/** @file\r
+Framework PEIM to initialize memory on an DDR2 SDRAM Memory Controller.\r
+\r
+Copyright (c) 2013 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#ifndef _MRC_WRAPPER_H\r
+#define _MRC_WRAPPER_H\r
+\r
+#include <Ppi/QNCMemoryInit.h>\r
+#include "PlatformEarlyInit.h"\r
+\r
+//\r
+// Define the default memory areas required\r
+//\r
+#define EDKII_RESERVED_SIZE_PAGES 0x40\r
+#define ACPI_NVS_SIZE_PAGES 0x40\r
+#define RUNTIME_SERVICES_DATA_SIZE_PAGES 0x20\r
+#define RUNTIME_SERVICES_CODE_SIZE_PAGES 0x60\r
+#define ACPI_RECLAIM_SIZE_PAGES 0x10\r
+#define EDKII_DXE_MEM_SIZE_PAGES 0x20\r
+\r
+#define AP_STARTUP_VECTOR 0x00097000\r
+\r
+//\r
+// Maximum number of "Socket Sets", where a "Socket Set is a set of matching\r
+// DIMM's from the various channels\r
+//\r
+#define MAX_SOCKET_SETS 2\r
+\r
+//\r
+// Maximum number of memory ranges supported by the memory controller\r
+//\r
+#define MAX_RANGES (MAX_ROWS + 5)\r
+\r
+//\r
+// Min. of 48MB PEI phase\r
+//\r
+#define PEI_MIN_MEMORY_SIZE (6 * 0x800000)\r
+#define PEI_RECOVERY_MIN_MEMORY_SIZE (6 * 0x800000)\r
+\r
+#define PEI_MEMORY_RANGE_OPTION_ROM UINT32\r
+#define PEI_MR_OPTION_ROM_NONE 0x00000000\r
+\r
+//\r
+// SMRAM Memory Range\r
+//\r
+#define PEI_MEMORY_RANGE_SMRAM UINT32\r
+#define PEI_MR_SMRAM_ALL 0xFFFFFFFF\r
+#define PEI_MR_SMRAM_NONE 0x00000000\r
+#define PEI_MR_SMRAM_CACHEABLE_MASK 0x80000000\r
+#define PEI_MR_SMRAM_SEGTYPE_MASK 0x00FF0000\r
+#define PEI_MR_SMRAM_ABSEG_MASK 0x00010000\r
+#define PEI_MR_SMRAM_HSEG_MASK 0x00020000\r
+#define PEI_MR_SMRAM_TSEG_MASK 0x00040000\r
+//\r
+// SMRAM Size is a multiple of 128KB.\r
+//\r
+#define PEI_MR_SMRAM_SIZE_MASK 0x0000FFFF\r
+\r
+//\r
+// Pci Memory Hole\r
+//\r
+#define PEI_MEMORY_RANGE_PCI_MEMORY UINT32\r
+\r
+typedef enum {\r
+ Ignore,\r
+ Quick,\r
+ Sparse,\r
+ Extensive\r
+} PEI_MEMORY_TEST_OP;\r
+\r
+//\r
+// MRC Params Variable structure.\r
+//\r
+\r
+typedef struct {\r
+ MrcTimings_t timings; // Actual MRC config values saved in variable store.\r
+ UINT8 VariableStorePad[8]; // Allow for data stored in variable is required to be multiple of 8bytes.\r
+} PLATFORM_VARIABLE_MEMORY_CONFIG_DATA;\r
+\r
+///\r
+/// MRC Params Platform Data Flags bits\r
+///\r
+#define PDAT_MRC_FLAG_ECC_EN BIT0\r
+#define PDAT_MRC_FLAG_SCRAMBLE_EN BIT1\r
+#define PDAT_MRC_FLAG_MEMTEST_EN BIT2\r
+#define PDAT_MRC_FLAG_TOP_TREE_EN BIT3 ///< 0b DDR "fly-by" topology else 1b DDR "tree" topology.\r
+#define PDAT_MRC_FLAG_WR_ODT_EN BIT4 ///< If set ODR signal is asserted to DRAM devices on writes.\r
+\r
+///\r
+/// MRC Params Platform Data.\r
+///\r
+typedef struct {\r
+ UINT32 Flags; ///< Bitmap of PDAT_MRC_FLAG_XXX defs above.\r
+ UINT8 DramWidth; ///< 0=x8, 1=x16, others=RESERVED.\r
+ UINT8 DramSpeed; ///< 0=DDRFREQ_800, 1=DDRFREQ_1066, others=RESERVED. Only 533MHz SKU support 1066 memory.\r
+ UINT8 DramType; ///< 0=DDR3,1=DDR3L, others=RESERVED.\r
+ UINT8 RankMask; ///< bit[0] RANK0_EN, bit[1] RANK1_EN, others=RESERVED.\r
+ UINT8 ChanMask; ///< bit[0] CHAN0_EN, others=RESERVED.\r
+ UINT8 ChanWidth; ///< 1=x16, others=RESERVED.\r
+ UINT8 AddrMode; ///< 0, 1, 2 (mode 2 forced if ecc enabled), others=RESERVED.\r
+ UINT8 SrInt; ///< 1=1.95us, 2=3.9us, 3=7.8us, others=RESERVED. REFRESH_RATE.\r
+ UINT8 SrTemp; ///< 0=normal, 1=extended, others=RESERVED.\r
+ UINT8 DramRonVal; ///< 0=34ohm, 1=40ohm, others=RESERVED. RON_VALUE Select MRS1.DIC driver impedance control.\r
+ UINT8 DramRttNomVal; ///< 0=40ohm, 1=60ohm, 2=120ohm, others=RESERVED.\r
+ UINT8 DramRttWrVal; ///< 0=off others=RESERVED.\r
+ UINT8 SocRdOdtVal; ///< 0=off, 1=60ohm, 2=120ohm, 3=180ohm, others=RESERVED.\r
+ UINT8 SocWrRonVal; ///< 0=27ohm, 1=32ohm, 2=40ohm, others=RESERVED.\r
+ UINT8 SocWrSlewRate; ///< 0=2.5V/ns, 1=4V/ns, others=RESERVED.\r
+ UINT8 DramDensity; ///< 0=512Mb, 1=1Gb, 2=2Gb, 3=4Gb, others=RESERVED.\r
+ UINT32 tRAS; ///< ACT to PRE command period in picoseconds.\r
+ UINT32 tWTR; ///< Delay from start of internal write transaction to internal read command in picoseconds.\r
+ UINT32 tRRD; ///< ACT to ACT command period (JESD79 specific to page size 1K/2K) in picoseconds.\r
+ UINT32 tFAW; ///< Four activate window (JESD79 specific to page size 1K/2K) in picoseconds.\r
+ UINT8 tCL; ///< DRAM CAS Latency in clocks.\r
+} PDAT_MRC_ITEM;\r
+\r
+//\r
+// Memory range types\r
+//\r
+typedef enum {\r
+ DualChannelDdrMainMemory,\r
+ DualChannelDdrSmramCacheable,\r
+ DualChannelDdrSmramNonCacheable,\r
+ DualChannelDdrGraphicsMemoryCacheable,\r
+ DualChannelDdrGraphicsMemoryNonCacheable,\r
+ DualChannelDdrReservedMemory,\r
+ DualChannelDdrMaxMemoryRangeType\r
+} PEI_DUAL_CHANNEL_DDR_MEMORY_RANGE_TYPE;\r
+\r
+//\r
+// Memory map range information\r
+//\r
+typedef struct {\r
+ EFI_PHYSICAL_ADDRESS PhysicalAddress;\r
+ EFI_PHYSICAL_ADDRESS CpuAddress;\r
+ EFI_PHYSICAL_ADDRESS RangeLength;\r
+ PEI_DUAL_CHANNEL_DDR_MEMORY_RANGE_TYPE Type;\r
+} PEI_DUAL_CHANNEL_DDR_MEMORY_MAP_RANGE;\r
+\r
+//\r
+// Function prototypes.\r
+//\r
+\r
+EFI_STATUS\r
+InstallEfiMemory (\r
+ IN EFI_PEI_SERVICES **PeiServices,\r
+ IN EFI_PEI_READ_ONLY_VARIABLE2_PPI *VariableServices,\r
+ IN EFI_BOOT_MODE BootMode,\r
+ IN UINT32 TotalMemorySize\r
+ );\r
+\r
+EFI_STATUS\r
+InstallS3Memory (\r
+ IN EFI_PEI_SERVICES **PeiServices,\r
+ IN EFI_PEI_READ_ONLY_VARIABLE2_PPI *VariableServices,\r
+ IN UINT32 TotalMemorySize\r
+ );\r
+\r
+EFI_STATUS\r
+MemoryInit (\r
+ IN EFI_PEI_SERVICES **PeiServices\r
+ );\r
+\r
+\r
+EFI_STATUS\r
+LoadConfig (\r
+ IN EFI_PEI_SERVICES **PeiServices,\r
+ IN EFI_PEI_READ_ONLY_VARIABLE2_PPI *VariableServices,\r
+ IN OUT MRCParams_t *MrcData\r
+ );\r
+\r
+EFI_STATUS\r
+SaveConfig (\r
+ IN MRCParams_t *MrcData\r
+ );\r
+\r
+VOID\r
+RetriveRequiredMemorySize (\r
+ IN EFI_PEI_SERVICES **PeiServices,\r
+ OUT UINTN *Size\r
+ );\r
+\r
+EFI_STATUS\r
+GetMemoryMap (\r
+ IN EFI_PEI_SERVICES **PeiServices,\r
+ IN UINT32 TotalMemorySize,\r
+ IN OUT PEI_DUAL_CHANNEL_DDR_MEMORY_MAP_RANGE *MemoryMap,\r
+ IN OUT UINT8 *NumRanges\r
+ );\r
+\r
+EFI_STATUS\r
+ChooseRanges (\r
+ IN OUT PEI_MEMORY_RANGE_OPTION_ROM *OptionRomMask,\r
+ IN OUT PEI_MEMORY_RANGE_SMRAM *SmramMask,\r
+ IN OUT PEI_MEMORY_RANGE_PCI_MEMORY *PciMemoryMask\r
+ );\r
+\r
+EFI_STATUS\r
+GetPlatformMemorySize (\r
+ IN EFI_PEI_SERVICES **PeiServices,\r
+ IN EFI_BOOT_MODE BootMode,\r
+ IN OUT UINT64 *MemorySize\r
+ );\r
+\r
+EFI_STATUS\r
+BaseMemoryTest (\r
+ IN EFI_PEI_SERVICES **PeiServices,\r
+ IN EFI_PHYSICAL_ADDRESS BeginAddress,\r
+ IN UINT64 MemoryLength,\r
+ IN PEI_MEMORY_TEST_OP Operation,\r
+ OUT EFI_PHYSICAL_ADDRESS *ErrorAddress\r
+ );\r
+\r
+EFI_STATUS\r
+SetPlatformImrPolicy (\r
+ IN EFI_PHYSICAL_ADDRESS PeiMemoryBaseAddress,\r
+ IN UINT64 PeiMemoryLength,\r
+ IN UINTN RequiredMemSize\r
+ );\r
+\r
+VOID\r
+EFIAPI\r
+InfoPostInstallMemory (\r
+ OUT UINT32 *RmuBaseAddressPtr OPTIONAL,\r
+ OUT EFI_SMRAM_DESCRIPTOR **SmramDescriptorPtr OPTIONAL,\r
+ OUT UINTN *NumSmramRegionsPtr OPTIONAL\r
+ );\r
+\r
+#endif\r
--- /dev/null
+/** @file\r
+EFI PEI Platform Security services\r
+\r
+Copyright (c) 2013 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#include "PeiFvSecurity.h"\r
+\r
+EFI_PEI_NOTIFY_DESCRIPTOR mNotifyOnFvInfoSecurityList = {\r
+ (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),\r
+ &gEfiPeiFirmwareVolumeInfoPpiGuid,\r
+ FirmwareVolmeInfoPpiNotifySecurityCallback\r
+};\r
+\r
+/**\r
+ Callback function to perform FV security checking on a FV Info PPI.\r
+\r
+ @param PeiServices An indirect pointer to the EFI_PEI_SERVICES table published by the PEI Foundation\r
+ @param NotifyDescriptor Address of the notification descriptor data structure.\r
+ @param Ppi Address of the PPI that was installed.\r
+\r
+ @retval EFI_SUCCESS\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+FirmwareVolmeInfoPpiNotifySecurityCallback (\r
+ IN EFI_PEI_SERVICES **PeiServices,\r
+ IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,\r
+ IN VOID *Ppi\r
+ )\r
+{\r
+ EFI_STATUS Status;\r
+ EFI_PEI_FIRMWARE_VOLUME_INFO_PPI *FvInfoPpi;\r
+ EFI_PEI_FIRMWARE_VOLUME_PPI *FvPpi;\r
+\r
+ FvInfoPpi = (EFI_PEI_FIRMWARE_VOLUME_INFO_PPI *)Ppi;\r
+\r
+ //\r
+ // Locate the corresponding FV_PPI according to founded FV's format guid\r
+ //\r
+ Status = PeiServicesLocatePpi (\r
+ &FvInfoPpi->FvFormat,\r
+ 0,\r
+ NULL,\r
+ (VOID**)&FvPpi\r
+ );\r
+ ASSERT_EFI_ERROR (Status);\r
+\r
+ //\r
+ // Only authenticate parent Firmware Volume (child firmware volumes are covered by the parent)\r
+ //\r
+ if ((VOID *)FvInfoPpi->ParentFvName == NULL && (VOID *)FvInfoPpi->ParentFileName == NULL) {\r
+ Status = PeiSecurityVerifyFv ((EFI_FIRMWARE_VOLUME_HEADER*) FvInfoPpi->FvInfo);\r
+ ASSERT_EFI_ERROR (Status);\r
+ }\r
+\r
+ return EFI_SUCCESS;\r
+}\r
+\r
+/**\r
+ Authenticates the Firmware Volume\r
+\r
+ @param CurrentFvAddress Pointer to the current Firmware Volume under consideration\r
+\r
+ @retval EFI_SUCCESS Firmware Volume is legal\r
+\r
+**/\r
+EFI_STATUS\r
+PeiSecurityVerifyFv (\r
+ IN EFI_FIRMWARE_VOLUME_HEADER *CurrentFvAddress\r
+ )\r
+{\r
+ EFI_STATUS Status;\r
+\r
+ //\r
+ // Call Security library to authenticate the Firmware Volume\r
+ //\r
+ DEBUG ((DEBUG_INFO, "PeiSecurityVerifyFv - CurrentFvAddress=0x%8x\n", (UINT32)CurrentFvAddress));\r
+ Status = EFI_SUCCESS;\r
+\r
+ return Status;\r
+}\r
+\r
+/**\r
+\r
+ Entry point for the PEI Security PEIM\r
+ Sets up a notification to perform PEI security checking\r
+\r
+ @param FfsHeader Not used.\r
+ @param PeiServices General purpose services available to every PEIM.\r
+\r
+ @return EFI_SUCCESS PEI Security notification installed successfully.\r
+ All others: PEI Security notification failed to install.\r
+\r
+**/\r
+EFI_STATUS\r
+PeiInitializeFvSecurity (\r
+ VOID\r
+ )\r
+{\r
+ EFI_STATUS Status;\r
+\r
+ Status = PeiServicesNotifyPpi (&mNotifyOnFvInfoSecurityList);\r
+\r
+ return Status;\r
+}\r
+\r
--- /dev/null
+/** @file\r
+Definition of Pei Core Structures and Services\r
+\r
+Copyright (c) 2013 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#ifndef _PEI_FV_SECURITY_H_\r
+#define _PEI_FV_SECURITY_H_\r
+\r
+#include <Ppi/FirmwareVolume.h>\r
+#include <Ppi/FirmwareVolumeInfo.h>\r
+#include <Library/DebugLib.h>\r
+#include <Library/PeiServicesLib.h>\r
+#include <Library/MemoryAllocationLib.h>\r
+\r
+/**\r
+ Callback function to perform FV security checking on a FV Info PPI.\r
+\r
+ @param PeiServices An indirect pointer to the EFI_PEI_SERVICES table published by the PEI Foundation\r
+ @param NotifyDescriptor Address of the notification descriptor data structure.\r
+ @param Ppi Address of the PPI that was installed.\r
+\r
+ @retval EFI_SUCCESS\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+FirmwareVolmeInfoPpiNotifySecurityCallback (\r
+ IN EFI_PEI_SERVICES **PeiServices,\r
+ IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,\r
+ IN VOID *Ppi\r
+ );\r
+\r
+/**\r
+ Authenticates the Firmware Volume\r
+\r
+ @param CurrentFvAddress Pointer to the current Firmware Volume under consideration\r
+\r
+ @retval EFI_SUCCESS Firmware Volume is legal\r
+\r
+**/\r
+EFI_STATUS\r
+PeiSecurityVerifyFv (\r
+ IN EFI_FIRMWARE_VOLUME_HEADER *CurrentFvAddress\r
+ );\r
+\r
+/**\r
+\r
+ Entry point for the PEI Security PEIM\r
+ Sets up a notification to perform PEI security checking\r
+\r
+ @param FfsHeader Not used.\r
+ @param PeiServices General purpose services available to every PEIM.\r
+\r
+ @return EFI_SUCCESS PEI Security notification installed successfully.\r
+ All others: PEI Security notification failed to install.\r
+\r
+**/\r
+EFI_STATUS\r
+PeiInitializeFvSecurity (\r
+ VOID\r
+ );\r
+\r
+#endif\r
--- /dev/null
+/** @file\r
+This PEIM initialize platform for MRC, following action is performed,\r
+1. Initizluize GMCH\r
+2. Detect boot mode\r
+3. Detect video adapter to determine whether we need pre allocated memory\r
+4. Calls MRC to initialize memory and install a PPI notify to do post memory initialization.\r
+This file contains the main entrypoint of the PEIM.\r
+\r
+Copyright (c) 2013 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+\r
+#include "CommonHeader.h"\r
+#include "PlatformEarlyInit.h"\r
+#include "PeiFvSecurity.h"\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+EndOfPeiSignalPpiNotifyCallback (\r
+ IN EFI_PEI_SERVICES **PeiServices,\r
+ IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,\r
+ IN VOID *Ppi\r
+ );\r
+\r
+//\r
+// Function prototypes to routines implemented in other source modules\r
+// within this component.\r
+//\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+PlatformErratasPostMrc (\r
+ VOID\r
+ );\r
+\r
+//\r
+// The global indicator, the FvFileLoader callback will modify it to TRUE after loading PEIM into memory\r
+//\r
+BOOLEAN ImageInMemory = FALSE;\r
+\r
+BOARD_LEGACY_GPIO_CONFIG mBoardLegacyGpioConfigTable[] = { PLATFORM_LEGACY_GPIO_TABLE_DEFINITION };\r
+UINTN mBoardLegacyGpioConfigTableLen = (sizeof(mBoardLegacyGpioConfigTable) / sizeof(BOARD_LEGACY_GPIO_CONFIG));\r
+BOARD_GPIO_CONTROLLER_CONFIG mBoardGpioControllerConfigTable[] = { PLATFORM_GPIO_CONTROLLER_CONFIG_DEFINITION };\r
+UINTN mBoardGpioControllerConfigTableLen = (sizeof(mBoardGpioControllerConfigTable) / sizeof(BOARD_GPIO_CONTROLLER_CONFIG));\r
+UINT8 ChipsetDefaultMac [6] = {0xff,0xff,0xff,0xff,0xff,0xff};\r
+\r
+EFI_PEI_PPI_DESCRIPTOR mPpiBootMode[1] = {\r
+ {\r
+ (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),\r
+ &gEfiPeiMasterBootModePpiGuid,\r
+ NULL\r
+ }\r
+};\r
+\r
+EFI_PEI_NOTIFY_DESCRIPTOR mMemoryDiscoveredNotifyList[1] = {\r
+ {\r
+ (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),\r
+ &gEfiPeiMemoryDiscoveredPpiGuid,\r
+ MemoryDiscoveredPpiNotifyCallback\r
+ }\r
+};\r
+\r
+EFI_PEI_NOTIFY_DESCRIPTOR mEndOfPeiSignalPpiNotifyList[1] = {\r
+ {\r
+ (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),\r
+ &gEfiEndOfPeiSignalPpiGuid,\r
+ EndOfPeiSignalPpiNotifyCallback\r
+ }\r
+};\r
+\r
+EFI_PEI_STALL_PPI mStallPpi = {\r
+ PEI_STALL_RESOLUTION,\r
+ Stall\r
+};\r
+\r
+EFI_PEI_PPI_DESCRIPTOR mPpiStall[1] = {\r
+ {\r
+ (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),\r
+ &gEfiPeiStallPpiGuid,\r
+ &mStallPpi\r
+ }\r
+};\r
+\r
+/**\r
+ Set Mac address on chipset ethernet device.\r
+\r
+ @param Bus PCI Bus number of chipset ethernet device.\r
+ @param Device Device number of chipset ethernet device.\r
+ @param Func PCI Function number of chipset ethernet device.\r
+ @param MacAddr MAC Address to set.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+SetLanControllerMacAddr (\r
+ IN CONST UINT8 Bus,\r
+ IN CONST UINT8 Device,\r
+ IN CONST UINT8 Func,\r
+ IN CONST UINT8 *MacAddr,\r
+ IN CONST UINT32 Bar0\r
+ )\r
+{\r
+ UINT32 Data32;\r
+ UINT16 PciVid;\r
+ UINT16 PciDid;\r
+ UINT32 Addr;\r
+ UINT32 MacVer;\r
+ volatile UINT8 *Wrote;\r
+ UINT32 DevPcieAddr;\r
+ UINT16 SaveCmdReg;\r
+ UINT32 SaveBarReg;\r
+\r
+ DevPcieAddr = PCI_LIB_ADDRESS (\r
+ Bus,\r
+ Device,\r
+ Func,\r
+ 0\r
+ );\r
+\r
+ //\r
+ // Do nothing if not a supported device.\r
+ //\r
+ PciVid = PciRead16 (DevPcieAddr + PCI_VENDOR_ID_OFFSET);\r
+ PciDid = PciRead16 (DevPcieAddr + PCI_DEVICE_ID_OFFSET);\r
+ if((PciVid != V_IOH_MAC_VENDOR_ID) || (PciDid != V_IOH_MAC_DEVICE_ID)) {\r
+ return;\r
+ }\r
+\r
+ //\r
+ // Save current settings for PCI CMD/BAR registers\r
+ //\r
+ SaveCmdReg = PciRead16 (DevPcieAddr + PCI_COMMAND_OFFSET);\r
+ SaveBarReg = PciRead32 (DevPcieAddr + R_IOH_MAC_MEMBAR);\r
+\r
+ //\r
+ // Use predefined tempory memory resource\r
+ //\r
+ PciWrite32 ( DevPcieAddr + R_IOH_MAC_MEMBAR, Bar0);\r
+ PciWrite8 ( DevPcieAddr + PCI_COMMAND_OFFSET, EFI_PCI_COMMAND_MEMORY_SPACE);\r
+\r
+ Addr = Bar0 + R_IOH_MAC_GMAC_REG_8;\r
+ MacVer = *((volatile UINT32 *) (UINTN)(Addr));\r
+\r
+ DEBUG ((EFI_D_INFO, "Ioh MAC [B:%d, D:%d, F:%d] VER:%04x ADDR:",\r
+ (UINTN) Bus,\r
+ (UINTN) Device,\r
+ (UINTN) Func,\r
+ (UINTN) MacVer\r
+ ));\r
+\r
+ //\r
+ // Set MAC Address0 Low Register (GMAC_REG_17) ADDRLO bits.\r
+ //\r
+ Addr = Bar0 + R_IOH_MAC_GMAC_REG_17;\r
+ Data32 = *((UINT32 *) (UINTN)(&MacAddr[0]));\r
+ *((volatile UINT32 *) (UINTN)(Addr)) = Data32;\r
+ Wrote = (volatile UINT8 *) (UINTN)(Addr);\r
+ DEBUG ((EFI_D_INFO, "%02x-%02x-%02x-%02x-",\r
+ (UINTN) Wrote[0],\r
+ (UINTN) Wrote[1],\r
+ (UINTN) Wrote[2],\r
+ (UINTN) Wrote[3]\r
+ ));\r
+\r
+ //\r
+ // Set MAC Address0 High Register (GMAC_REG_16) ADDRHI bits\r
+ // and Address Enable (AE) bit.\r
+ //\r
+ Addr = Bar0 + R_IOH_MAC_GMAC_REG_16;\r
+ Data32 =\r
+ ((UINT32) MacAddr[4]) |\r
+ (((UINT32)MacAddr[5]) << 8) |\r
+ B_IOH_MAC_AE;\r
+ *((volatile UINT32 *) (UINTN)(Addr)) = Data32;\r
+ Wrote = (volatile UINT8 *) (UINTN)(Addr);\r
+\r
+ DEBUG ((EFI_D_INFO, "%02x-%02x\n", (UINTN) Wrote[0], (UINTN) Wrote[1]));\r
+\r
+ //\r
+ // Restore settings for PCI CMD/BAR registers\r
+ //\r
+ PciWrite32 ((DevPcieAddr + R_IOH_MAC_MEMBAR), SaveBarReg);\r
+ PciWrite16 (DevPcieAddr + PCI_COMMAND_OFFSET, SaveCmdReg);\r
+}\r
+\r
+/**\r
+ This is the entrypoint of PEIM\r
+\r
+ @param FileHandle Handle of the file being invoked.\r
+ @param PeiServices Describes the list of possible PEI Services.\r
+\r
+ @retval EFI_SUCCESS if it completed successfully.\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+PeiInitPlatform (\r
+ IN EFI_PEI_FILE_HANDLE FileHandle,\r
+ IN CONST EFI_PEI_SERVICES **PeiServices\r
+ )\r
+{\r
+ EFI_STATUS Status;\r
+ EFI_BOOT_MODE BootMode;\r
+ EFI_PEI_STALL_PPI *StallPpi;\r
+ EFI_PEI_PPI_DESCRIPTOR *StallPeiPpiDescriptor;\r
+ EFI_FV_FILE_INFO FileInfo;\r
+ EFI_PLATFORM_TYPE PlatformType;\r
+\r
+ PlatformType = (EFI_PLATFORM_TYPE)PcdGet16 (PcdPlatformType);\r
+\r
+ //\r
+ // Initialize Firmware Volume security.\r
+ // This must be done before any firmware volume accesses (excl. BFV)\r
+ //\r
+ Status = PeiInitializeFvSecurity();\r
+ ASSERT_EFI_ERROR (Status);\r
+\r
+ //\r
+ // Do any early platform specific initialization.\r
+ //\r
+ EarlyPlatformInit ();\r
+\r
+ //\r
+ // This is a second path on entry, in recovery boot path the Stall PPI need to be memory-based\r
+ // to improve recovery performance.\r
+ //\r
+ Status = PeiServicesFfsGetFileInfo (FileHandle, &FileInfo);\r
+ ASSERT_EFI_ERROR (Status);\r
+ //\r
+ // The follow conditional check only works for memory-mapped FFS,\r
+ // so we ASSERT that the file is really a MM FFS.\r
+ //\r
+ ASSERT (FileInfo.Buffer != NULL);\r
+ if (!(((UINTN) FileInfo.Buffer <= (UINTN) PeiInitPlatform) &&\r
+ ((UINTN) PeiInitPlatform <= (UINTN) FileInfo.Buffer + FileInfo.BufferSize))) {\r
+ //\r
+ // Now that module in memory, update the\r
+ // PPI that describes the Stall to other modules\r
+ //\r
+ Status = PeiServicesLocatePpi (\r
+ &gEfiPeiStallPpiGuid,\r
+ 0,\r
+ &StallPeiPpiDescriptor,\r
+ (VOID **) &StallPpi\r
+ );\r
+\r
+ if (!EFI_ERROR (Status)) {\r
+\r
+ Status = PeiServicesReInstallPpi (\r
+ StallPeiPpiDescriptor,\r
+ &mPpiStall[0]\r
+ );\r
+ } else {\r
+\r
+ Status = PeiServicesInstallPpi (&mPpiStall[0]);\r
+ }\r
+ return Status;\r
+ }\r
+\r
+ //\r
+ // Initialize System Phys\r
+ //\r
+\r
+ // Program USB Phy\r
+ InitializeUSBPhy();\r
+\r
+ //\r
+ // Do platform specific logic to create a boot mode\r
+ //\r
+ Status = UpdateBootMode ((EFI_PEI_SERVICES**)PeiServices, &BootMode);\r
+ ASSERT_EFI_ERROR (Status);\r
+\r
+ //\r
+ // Signal possible dependent modules that there has been a\r
+ // final boot mode determination\r
+ //\r
+ if (!EFI_ERROR(Status)) {\r
+ Status = PeiServicesInstallPpi (&mPpiBootMode[0]);\r
+ ASSERT_EFI_ERROR (Status);\r
+ }\r
+\r
+ if (BootMode != BOOT_ON_S3_RESUME) {\r
+ QNCClearSmiAndWake ();\r
+ }\r
+\r
+ DEBUG ((EFI_D_INFO, "MRC Entry\n"));\r
+ MemoryInit ((EFI_PEI_SERVICES**)PeiServices);\r
+\r
+ //\r
+ // Do Early PCIe init.\r
+ //\r
+ DEBUG ((EFI_D_INFO, "Early PCIe controller initialization\n"));\r
+ PlatformPciExpressEarlyInit (PlatformType);\r
+\r
+\r
+ DEBUG ((EFI_D_INFO, "Platform Erratas After MRC\n"));\r
+ PlatformErratasPostMrc ();\r
+\r
+ //\r
+ // Now that all of the pre-permanent memory activities have\r
+ // been taken care of, post a call-back for the permanent-memory\r
+ // resident services, such as HOB construction.\r
+ // PEI Core will switch stack after this PEIM exit. After that the MTRR\r
+ // can be set.\r
+ //\r
+ Status = PeiServicesNotifyPpi (&mMemoryDiscoveredNotifyList[0]);\r
+ ASSERT_EFI_ERROR (Status);\r
+/*\r
+\r
+ if (BootMode != BOOT_ON_S3_RESUME) {\r
+ Status = PeiServicesNotifyPpi (mEndOfPeiSignalPpiNotifyList);\r
+ ASSERT_EFI_ERROR (Status);\r
+ }\r
+*/\r
+ if (BootMode == BOOT_IN_RECOVERY_MODE) {\r
+ PeiServicesRegisterForShadow (FileHandle);\r
+ }\r
+\r
+ return Status;\r
+}\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+EndOfPeiSignalPpiNotifyCallback (\r
+ IN EFI_PEI_SERVICES **PeiServices,\r
+ IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,\r
+ IN VOID *Ppi\r
+ )\r
+{\r
+ EFI_STATUS Status;\r
+\r
+ DEBUG ((EFI_D_INFO, "End of PEI Signal Callback\n"));\r
+\r
+ //\r
+ // Restore the flash region to be UC\r
+ // for both normal boot as we build a Resource Hob to\r
+ // describe this region as UC to DXE core.\r
+ //\r
+ WriteBackInvalidateDataCacheRange (\r
+ (VOID *) (UINTN) PcdGet32 (PcdFlashAreaBaseAddress),\r
+ PcdGet32 (PcdFlashAreaSize)\r
+ );\r
+\r
+ Status = MtrrSetMemoryAttribute (PcdGet32 (PcdFlashAreaBaseAddress), PcdGet32 (PcdFlashAreaSize), CacheUncacheable);\r
+ ASSERT_EFI_ERROR (Status);\r
+\r
+ return EFI_SUCCESS;\r
+}\r
+\r
+/**\r
+ This function will initialize USB Phy registers associated with QuarkSouthCluster.\r
+\r
+ @param VOID No Argument\r
+\r
+ @retval EFI_SUCCESS All registers have been initialized\r
+**/\r
+VOID\r
+EFIAPI\r
+InitializeUSBPhy (\r
+ VOID\r
+ )\r
+{\r
+ UINT32 RegData32;\r
+\r
+ /** In order to configure the PHY to use clk120 (ickusbcoreclk) as PLL reference clock\r
+ * and Port2 as a USB device port, the following sequence must be followed\r
+ *\r
+ **/\r
+\r
+ // Sideband register write to USB AFE (Phy)\r
+ RegData32 = QNCAltPortRead (QUARK_SC_USB_AFE_SB_PORT_ID, USB2_GLOBAL_PORT);\r
+ RegData32 &= ~(BIT1);\r
+ //\r
+ // Sighting #4930631 PDNRESCFG [8:7] of USB2_GLOBAL_PORT = 11b.\r
+ // For port 0 & 1 as host and port 2 as device.\r
+ //\r
+ RegData32 |= (BIT8 | BIT7);\r
+ QNCAltPortWrite (QUARK_SC_USB_AFE_SB_PORT_ID, USB2_GLOBAL_PORT, RegData32);\r
+\r
+ //\r
+ // Sighting #4930653 Required BIOS change on Disconnect vref to change to 600mV.\r
+ //\r
+ RegData32 = QNCAltPortRead (QUARK_SC_USB_AFE_SB_PORT_ID, USB2_COMPBG);\r
+ RegData32 &= ~(BIT10 | BIT9 | BIT8 | BIT7);\r
+ RegData32 |= (BIT10 | BIT7);\r
+ QNCAltPortWrite (QUARK_SC_USB_AFE_SB_PORT_ID, USB2_COMPBG, RegData32);\r
+\r
+ // Sideband register write to USB AFE (Phy)\r
+ // (pllbypass) to bypass/Disable PLL before switch\r
+ RegData32 = QNCAltPortRead (QUARK_SC_USB_AFE_SB_PORT_ID, USB2_PLL2);\r
+ RegData32 |= BIT29;\r
+ QNCAltPortWrite (QUARK_SC_USB_AFE_SB_PORT_ID, USB2_PLL2, RegData32);\r
+\r
+ // Sideband register write to USB AFE (Phy)\r
+ // (coreclksel) to select 120MHz (ickusbcoreclk) clk source.\r
+ // (Default 0 to select 96MHz (ickusbclk96_npad/ppad))\r
+ RegData32 = QNCAltPortRead (QUARK_SC_USB_AFE_SB_PORT_ID, USB2_PLL1);\r
+ RegData32 |= BIT1;\r
+ QNCAltPortWrite (QUARK_SC_USB_AFE_SB_PORT_ID, USB2_PLL1, RegData32);\r
+\r
+ // Sideband register write to USB AFE (Phy)\r
+ // (divide by 8) to achieve internal 480MHz clock\r
+ // for 120MHz input refclk. (Default: 4'b1000 (divide by 10) for 96MHz)\r
+ RegData32 = QNCAltPortRead (QUARK_SC_USB_AFE_SB_PORT_ID, USB2_PLL1);\r
+ RegData32 &= ~(BIT5 | BIT4 | BIT3);\r
+ RegData32 |= BIT6;\r
+ QNCAltPortWrite (QUARK_SC_USB_AFE_SB_PORT_ID, USB2_PLL1, RegData32);\r
+\r
+ // Sideband register write to USB AFE (Phy)\r
+ // Clear (pllbypass)\r
+ RegData32 = QNCAltPortRead (QUARK_SC_USB_AFE_SB_PORT_ID, USB2_PLL2);\r
+ RegData32 &= ~BIT29;\r
+ QNCAltPortWrite (QUARK_SC_USB_AFE_SB_PORT_ID, USB2_PLL2, RegData32);\r
+\r
+ // Sideband register write to USB AFE (Phy)\r
+ // Set (startlock) to force the PLL FSM to restart the lock\r
+ // sequence due to input clock/freq switch.\r
+ RegData32 = QNCAltPortRead (QUARK_SC_USB_AFE_SB_PORT_ID, USB2_PLL2);\r
+ RegData32 |= BIT24;\r
+ QNCAltPortWrite (QUARK_SC_USB_AFE_SB_PORT_ID, USB2_PLL2, RegData32);\r
+\r
+ // At this point the PLL FSM and COMP FSM will complete\r
+\r
+}\r
+\r
+/**\r
+ This function provides early platform Thermal sensor initialisation.\r
+**/\r
+VOID\r
+EFIAPI\r
+EarlyPlatformThermalSensorInit (\r
+ VOID\r
+ )\r
+{\r
+ DEBUG ((EFI_D_INFO, "Early Platform Thermal Sensor Init\n"));\r
+\r
+ //\r
+ // Set Thermal sensor mode.\r
+ //\r
+ QNCThermalSensorSetRatiometricMode ();\r
+\r
+ //\r
+ // Enable RMU Thermal sensor with a Catastrophic Trip point.\r
+ //\r
+ QNCThermalSensorEnableWithCatastrophicTrip (PLATFORM_CATASTROPHIC_TRIP_CELSIUS);\r
+\r
+ //\r
+ // Lock all RMU Thermal sensor control & trip point registers.\r
+ //\r
+ QNCThermalSensorLockAllRegisters ();\r
+}\r
+\r
+/**\r
+ Print early platform info messages includeing the Stage1 module that's\r
+ running, MFH item list and platform data item list.\r
+**/\r
+VOID\r
+EFIAPI\r
+EarlyPlatformInfoMessages (\r
+ VOID\r
+ )\r
+{\r
+ DEBUG_CODE_BEGIN ();\r
+ QUARK_EDKII_STAGE1_HEADER *Edk2ImageHeader;\r
+\r
+ //\r
+ // Find which 'Stage1' image we are running and print the details\r
+ //\r
+ Edk2ImageHeader = (QUARK_EDKII_STAGE1_HEADER *) PcdGet32 (PcdEsramStage1Base);\r
+ DEBUG ((EFI_D_INFO, "\n************************************************************\n"));\r
+\r
+ switch ((UINT8)Edk2ImageHeader->ImageIndex & QUARK_STAGE1_IMAGE_TYPE_MASK) {\r
+ case QUARK_STAGE1_BOOT_IMAGE_TYPE:\r
+ DEBUG ((EFI_D_INFO, "**** Quark EDKII Stage 1 Boot Image %d ****\n", ((UINT8)Edk2ImageHeader->ImageIndex & ~(QUARK_STAGE1_IMAGE_TYPE_MASK))));\r
+ break;\r
+\r
+ case QUARK_STAGE1_RECOVERY_IMAGE_TYPE:\r
+ DEBUG ((EFI_D_INFO, "**** Quark EDKII Stage 1 Recovery Image %d ****\n", ((UINT8)Edk2ImageHeader->ImageIndex & ~(QUARK_STAGE1_IMAGE_TYPE_MASK))));\r
+ break;\r
+\r
+ default:\r
+ DEBUG ((EFI_D_INFO, "**** Quark EDKII Unknown Stage 1 Image !!!! ****\n"));\r
+ break;\r
+ }\r
+ DEBUG (\r
+ (EFI_D_INFO,\r
+ "**** Quark EDKII Stage 2 Image 0x%08X:0x%08X ****\n" ,\r
+ (UINTN) PcdGet32 (PcdFlashFvMainBase),\r
+ (UINTN) PcdGet32 (PcdFlashFvMainSize)\r
+ ));\r
+\r
+ DEBUG (\r
+ (EFI_D_INFO,\r
+ "**** Quark EDKII Payload Image 0x%08X:0x%08X ****\n" ,\r
+ (UINTN) PcdGet32 (PcdFlashFvPayloadBase),\r
+ (UINTN) PcdGet32 (PcdFlashFvPayloadSize)\r
+ ));\r
+\r
+ DEBUG ((EFI_D_INFO, "************************************************************\n\n"));\r
+\r
+ DEBUG_CODE_END ();\r
+}\r
+\r
+/**\r
+ Check if system reset due to error condition.\r
+\r
+ @param ClearErrorBits If TRUE clear error flags and value bits.\r
+\r
+ @retval TRUE if system reset due to error condition.\r
+ @retval FALSE if NO reset error conditions.\r
+**/\r
+BOOLEAN\r
+CheckForResetDueToErrors (\r
+ IN BOOLEAN ClearErrorBits\r
+ )\r
+{\r
+ UINT32 RegValue;\r
+ BOOLEAN ResetDueToError;\r
+\r
+ ResetDueToError = FALSE;\r
+\r
+ //\r
+ // Check if RMU reset system due to access violations.\r
+ // RMU updates a SOC Unit register before reseting the system.\r
+ //\r
+ RegValue = QNCAltPortRead (QUARK_SCSS_SOC_UNIT_SB_PORT_ID, QUARK_SCSS_SOC_UNIT_CFG_STICKY_RW);\r
+ if ((RegValue & B_CFG_STICKY_RW_VIOLATION) != 0) {\r
+ ResetDueToError = TRUE;\r
+\r
+ DEBUG (\r
+ (EFI_D_ERROR,\r
+ "\nReset due to access violation: %s %s %s %s\n",\r
+ ((RegValue & B_CFG_STICKY_RW_IMR_VIOLATION) != 0) ? L"'IMR'" : L".",\r
+ ((RegValue & B_CFG_STICKY_RW_DECC_VIOLATION) != 0) ? L"'DECC'" : L".",\r
+ ((RegValue & B_CFG_STICKY_RW_SMM_VIOLATION) != 0) ? L"'SMM'" : L".",\r
+ ((RegValue & B_CFG_STICKY_RW_HMB_VIOLATION) != 0) ? L"'HMB'" : L"."\r
+ ));\r
+\r
+ //\r
+ // Clear error bits.\r
+ //\r
+ if (ClearErrorBits) {\r
+ RegValue &= ~(B_CFG_STICKY_RW_VIOLATION);\r
+ QNCAltPortWrite (QUARK_SCSS_SOC_UNIT_SB_PORT_ID, QUARK_SCSS_SOC_UNIT_CFG_STICKY_RW, RegValue);\r
+ }\r
+ }\r
+\r
+ return ResetDueToError;\r
+}\r
+\r
+/**\r
+ This function provides early platform initialization.\r
+\r
+ @param PlatformInfo Pointer to platform Info structure.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+EarlyPlatformInit (\r
+ VOID\r
+ )\r
+{\r
+ EFI_PLATFORM_TYPE PlatformType;\r
+\r
+ PlatformType = (EFI_PLATFORM_TYPE) PcdGet16 (PcdPlatformType);\r
+\r
+ DEBUG ((EFI_D_INFO, "EarlyPlatformInit for PlatType=0x%02x\n", (UINTN) PlatformType));\r
+\r
+ //\r
+ // Check if system reset due to error condition.\r
+ //\r
+ if (CheckForResetDueToErrors (TRUE)) {\r
+ if(FeaturePcdGet (WaitIfResetDueToError)) {\r
+ DEBUG ((EFI_D_ERROR, "Press any key to continue.\n"));\r
+ PlatformDebugPortGetChar8 ();\r
+ }\r
+ }\r
+\r
+ //\r
+ // Display platform info messages.\r
+ //\r
+ EarlyPlatformInfoMessages ();\r
+\r
+ //\r
+ // Early Legacy Gpio Init.\r
+ //\r
+ EarlyPlatformLegacyGpioInit (PlatformType);\r
+\r
+ //\r
+ // Early platform Legacy GPIO manipulation depending on GPIOs\r
+ // setup by EarlyPlatformLegacyGpioInit.\r
+ //\r
+ EarlyPlatformLegacyGpioManipulation (PlatformType);\r
+\r
+ //\r
+ // Early platform specific GPIO Controller init & manipulation.\r
+ // Combined for sharing of temp. memory bar.\r
+ //\r
+ EarlyPlatformGpioCtrlerInitAndManipulation (PlatformType);\r
+\r
+ //\r
+ // Early Thermal Sensor Init.\r
+ //\r
+ EarlyPlatformThermalSensorInit ();\r
+\r
+ //\r
+ // Early Lan Ethernet Mac Init.\r
+ //\r
+ EarlyPlatformMacInit (\r
+ PcdGetPtr (PcdIohEthernetMac0),\r
+ PcdGetPtr (PcdIohEthernetMac1)\r
+ );\r
+}\r
+\r
+/**\r
+ This function provides early platform Legacy GPIO initialisation.\r
+\r
+ @param PlatformType Platform type for GPIO init.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+EarlyPlatformLegacyGpioInit (\r
+ IN CONST EFI_PLATFORM_TYPE PlatformType\r
+ )\r
+{\r
+ BOARD_LEGACY_GPIO_CONFIG *LegacyGpioConfig;\r
+ UINT32 NewValue;\r
+ UINT32 GpioBaseAddress;\r
+\r
+ //\r
+ // Assert if platform type outside table range.\r
+ //\r
+ ASSERT ((UINTN) PlatformType < mBoardLegacyGpioConfigTableLen);\r
+ LegacyGpioConfig = &mBoardLegacyGpioConfigTable[(UINTN) PlatformType];\r
+\r
+ GpioBaseAddress = (UINT32)PcdGet16 (PcdGbaIoBaseAddress);\r
+\r
+ NewValue = 0x0;\r
+ //\r
+ // Program QNC GPIO Registers.\r
+ //\r
+ NewValue = (IoRead32 (GpioBaseAddress + R_QNC_GPIO_CGEN_CORE_WELL) & 0xFFFFFFFC) | LegacyGpioConfig->CoreWellEnable;\r
+ IoWrite32 (GpioBaseAddress + R_QNC_GPIO_CGEN_CORE_WELL, NewValue );\r
+ NewValue = (IoRead32 (GpioBaseAddress + R_QNC_GPIO_CGIO_CORE_WELL) & 0xFFFFFFFC) | LegacyGpioConfig->CoreWellIoSelect;\r
+ IoWrite32 (GpioBaseAddress + R_QNC_GPIO_CGIO_CORE_WELL, NewValue);\r
+ NewValue = (IoRead32 (GpioBaseAddress + R_QNC_GPIO_CGLVL_CORE_WELL) & 0xFFFFFFFC) | LegacyGpioConfig->CoreWellLvlForInputOrOutput;\r
+ IoWrite32 (GpioBaseAddress + R_QNC_GPIO_CGLVL_CORE_WELL, NewValue);\r
+ NewValue = (IoRead32 (GpioBaseAddress + R_QNC_GPIO_CGTPE_CORE_WELL) & 0xFFFFFFFC) | LegacyGpioConfig->CoreWellTriggerPositiveEdge;\r
+ IoWrite32 (GpioBaseAddress + R_QNC_GPIO_CGTPE_CORE_WELL, NewValue );\r
+ NewValue = (IoRead32 (GpioBaseAddress + R_QNC_GPIO_CGTNE_CORE_WELL) & 0xFFFFFFFC) | LegacyGpioConfig->CoreWellTriggerNegativeEdge;\r
+ IoWrite32 (GpioBaseAddress + R_QNC_GPIO_CGTNE_CORE_WELL, NewValue);\r
+ NewValue = (IoRead32 (GpioBaseAddress + R_QNC_GPIO_CGGPE_CORE_WELL) & 0xFFFFFFFC) | LegacyGpioConfig->CoreWellGPEEnable;\r
+ IoWrite32 (GpioBaseAddress + R_QNC_GPIO_CGGPE_CORE_WELL, NewValue);\r
+ NewValue = (IoRead32 (GpioBaseAddress + R_QNC_GPIO_CGSMI_CORE_WELL) & 0xFFFFFFFC) | LegacyGpioConfig->CoreWellSMIEnable;\r
+ IoWrite32 (GpioBaseAddress + R_QNC_GPIO_CGSMI_CORE_WELL, NewValue );\r
+ NewValue = (IoRead32 (GpioBaseAddress + R_QNC_GPIO_CGTS_CORE_WELL) & 0xFFFFFFFC) | LegacyGpioConfig->CoreWellTriggerStatus;\r
+ IoWrite32 (GpioBaseAddress + R_QNC_GPIO_CGTS_CORE_WELL, NewValue);\r
+ NewValue = (IoRead32 (GpioBaseAddress + R_QNC_GPIO_CNMIEN_CORE_WELL) & 0xFFFFFFFC) | LegacyGpioConfig->CoreWellNMIEnable;\r
+ IoWrite32 (GpioBaseAddress + R_QNC_GPIO_CNMIEN_CORE_WELL, NewValue);\r
+\r
+ NewValue = (IoRead32 (GpioBaseAddress + R_QNC_GPIO_RGEN_RESUME_WELL) & 0xFFFFFFC0) | LegacyGpioConfig->ResumeWellEnable;\r
+ IoWrite32 (GpioBaseAddress + R_QNC_GPIO_RGEN_RESUME_WELL, NewValue );\r
+ NewValue = (IoRead32 (GpioBaseAddress + R_QNC_GPIO_RGIO_RESUME_WELL) & 0xFFFFFFC0) | LegacyGpioConfig->ResumeWellIoSelect;\r
+ IoWrite32 (GpioBaseAddress + R_QNC_GPIO_RGIO_RESUME_WELL, NewValue) ;\r
+ NewValue = (IoRead32 (GpioBaseAddress + R_QNC_GPIO_RGLVL_RESUME_WELL) & 0xFFFFFFC0) | LegacyGpioConfig->ResumeWellLvlForInputOrOutput;\r
+ IoWrite32 (GpioBaseAddress + R_QNC_GPIO_RGLVL_RESUME_WELL, NewValue);\r
+ NewValue = (IoRead32 (GpioBaseAddress + R_QNC_GPIO_RGTPE_RESUME_WELL) & 0xFFFFFFC0) | LegacyGpioConfig->ResumeWellTriggerPositiveEdge;\r
+ IoWrite32 (GpioBaseAddress + R_QNC_GPIO_RGTPE_RESUME_WELL, NewValue );\r
+ NewValue = (IoRead32 (GpioBaseAddress + R_QNC_GPIO_RGTNE_RESUME_WELL) & 0xFFFFFFC0) | LegacyGpioConfig->ResumeWellTriggerNegativeEdge;\r
+ IoWrite32 (GpioBaseAddress + R_QNC_GPIO_RGTNE_RESUME_WELL, NewValue) ;\r
+ NewValue = (IoRead32 (GpioBaseAddress + R_QNC_GPIO_RGGPE_RESUME_WELL) & 0xFFFFFFC0) | LegacyGpioConfig->ResumeWellGPEEnable;\r
+ IoWrite32 (GpioBaseAddress + R_QNC_GPIO_RGGPE_RESUME_WELL, NewValue);\r
+ NewValue = (IoRead32 (GpioBaseAddress + R_QNC_GPIO_RGSMI_RESUME_WELL) & 0xFFFFFFC0) | LegacyGpioConfig->ResumeWellSMIEnable;\r
+ IoWrite32 (GpioBaseAddress + R_QNC_GPIO_RGSMI_RESUME_WELL, NewValue );\r
+ NewValue = (IoRead32 (GpioBaseAddress + R_QNC_GPIO_RGTS_RESUME_WELL) & 0xFFFFFFC0) | LegacyGpioConfig->ResumeWellTriggerStatus;\r
+ IoWrite32 (GpioBaseAddress + R_QNC_GPIO_RGTS_RESUME_WELL, NewValue) ;\r
+ NewValue = (IoRead32 (GpioBaseAddress + R_QNC_GPIO_RNMIEN_RESUME_WELL) & 0xFFFFFFC0) | LegacyGpioConfig->ResumeWellNMIEnable;\r
+ IoWrite32 (GpioBaseAddress + R_QNC_GPIO_RNMIEN_RESUME_WELL, NewValue);\r
+}\r
+\r
+/**\r
+ Performs any early platform specific Legacy GPIO manipulation.\r
+\r
+ @param PlatformType Platform type GPIO manipulation.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+EarlyPlatformLegacyGpioManipulation (\r
+ IN CONST EFI_PLATFORM_TYPE PlatformType\r
+ )\r
+{\r
+ if (PlatformType == CrossHill) {\r
+\r
+ //\r
+ // Pull TPM reset low for 80us (equivalent to cold reset, Table 39\r
+ // Infineon SLB9645 Databook), then pull TPM reset high and wait for\r
+ // 150ms to give time for TPM to stabilise (Section 4.7.1 Infineon\r
+ // SLB9645 Databook states TPM is ready to receive command after 30ms\r
+ // but section 4.7 states some TPM commands may take longer to execute\r
+ // upto 150ms after test).\r
+ //\r
+\r
+ PlatformLegacyGpioSetLevel (\r
+ R_QNC_GPIO_RGLVL_RESUME_WELL,\r
+ PLATFORM_RESUMEWELL_TPM_RST_GPIO,\r
+ FALSE\r
+ );\r
+ MicroSecondDelay (80);\r
+\r
+ PlatformLegacyGpioSetLevel (\r
+ R_QNC_GPIO_RGLVL_RESUME_WELL,\r
+ PLATFORM_RESUMEWELL_TPM_RST_GPIO,\r
+ TRUE\r
+ );\r
+ MicroSecondDelay (150000);\r
+ }\r
+\r
+}\r
+\r
+/**\r
+ Performs any early platform specific GPIO Controller init & manipulation.\r
+\r
+ @param PlatformType Platform type for GPIO init & manipulation.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+EarlyPlatformGpioCtrlerInitAndManipulation (\r
+ IN CONST EFI_PLATFORM_TYPE PlatformType\r
+ )\r
+{\r
+ UINT32 IohGpioBase;\r
+ UINT32 Data32;\r
+ UINT32 Addr;\r
+ BOARD_GPIO_CONTROLLER_CONFIG *GpioConfig;\r
+ UINT32 DevPcieAddr;\r
+ UINT16 SaveCmdReg;\r
+ UINT32 SaveBarReg;\r
+ UINT16 PciVid;\r
+ UINT16 PciDid;\r
+\r
+ ASSERT ((UINTN) PlatformType < mBoardGpioControllerConfigTableLen);\r
+ GpioConfig = &mBoardGpioControllerConfigTable[(UINTN) PlatformType];\r
+\r
+ IohGpioBase = (UINT32) PcdGet64 (PcdIohGpioMmioBase);\r
+\r
+ DevPcieAddr = PCI_LIB_ADDRESS (\r
+ PcdGet8 (PcdIohGpioBusNumber),\r
+ PcdGet8 (PcdIohGpioDevNumber),\r
+ PcdGet8 (PcdIohGpioFunctionNumber),\r
+ 0\r
+ );\r
+\r
+ //\r
+ // Do nothing if not a supported device.\r
+ //\r
+ PciVid = PciRead16 (DevPcieAddr + PCI_VENDOR_ID_OFFSET);\r
+ PciDid = PciRead16 (DevPcieAddr + PCI_DEVICE_ID_OFFSET);\r
+ if((PciVid != V_IOH_I2C_GPIO_VENDOR_ID) || (PciDid != V_IOH_I2C_GPIO_DEVICE_ID)) {\r
+ return;\r
+ }\r
+\r
+ //\r
+ // Save current settings for PCI CMD/BAR registers.\r
+ //\r
+ SaveCmdReg = PciRead16 (DevPcieAddr + PCI_COMMAND_OFFSET);\r
+ SaveBarReg = PciRead32 (DevPcieAddr + PcdGet8 (PcdIohGpioBarRegister));\r
+\r
+ //\r
+ // Use predefined tempory memory resource.\r
+ //\r
+ PciWrite32 ( DevPcieAddr + PcdGet8 (PcdIohGpioBarRegister), IohGpioBase);\r
+ PciWrite8 ( DevPcieAddr + PCI_COMMAND_OFFSET, EFI_PCI_COMMAND_MEMORY_SPACE);\r
+\r
+ //\r
+ // Gpio Controller Init Tasks.\r
+ //\r
+\r
+ //\r
+ // IEN- Interrupt Enable Register\r
+ //\r
+ Addr = IohGpioBase + GPIO_INTEN;\r
+ Data32 = *((volatile UINT32 *) (UINTN)(Addr)) & 0xFFFFFF00; // Keep reserved bits [31:8]\r
+ Data32 |= (GpioConfig->IntEn & 0x000FFFFF);\r
+ *((volatile UINT32 *) (UINTN)(Addr)) = Data32;\r
+\r
+ //\r
+ // ISTATUS- Interrupt Status Register\r
+ //\r
+ Addr = IohGpioBase + GPIO_INTSTATUS;\r
+ Data32 = *((volatile UINT32 *) (UINTN)(Addr)) & 0xFFFFFF00; // Keep reserved bits [31:8]\r
+ *((volatile UINT32 *) (UINTN)(Addr)) = Data32;\r
+\r
+ //\r
+ // GPIO SWPORTA Direction Register - GPIO_SWPORTA_DR\r
+ //\r
+ Addr = IohGpioBase + GPIO_SWPORTA_DR;\r
+ Data32 = *((volatile UINT32 *) (UINTN)(Addr)) & 0xFFFFFF00; // Keep reserved bits [31:8]\r
+ Data32 |= (GpioConfig->PortADR & 0x000FFFFF);\r
+ *((volatile UINT32 *) (UINTN)(Addr)) = Data32;\r
+\r
+ //\r
+ // GPIO SWPORTA Data Direction Register - GPIO_SWPORTA_DDR - default input\r
+ //\r
+ Addr = IohGpioBase + GPIO_SWPORTA_DDR;\r
+ Data32 = *((volatile UINT32 *) (UINTN)(Addr)) & 0xFFFFFF00; // Keep reserved bits [31:8]\r
+ Data32 |= (GpioConfig->PortADir & 0x000FFFFF);\r
+ *((volatile UINT32 *) (UINTN)(Addr)) = Data32;\r
+\r
+ //\r
+ // Interrupt Mask Register - GPIO_INTMASK - default interrupts unmasked\r
+ //\r
+ Addr = IohGpioBase + GPIO_INTMASK;\r
+ Data32 = *((volatile UINT32 *) (UINTN)(Addr)) & 0xFFFFFF00; // Keep reserved bits [31:8]\r
+ Data32 |= (GpioConfig->IntMask & 0x000FFFFF);\r
+ *((volatile UINT32 *) (UINTN)(Addr)) = Data32;\r
+\r
+ //\r
+ // Interrupt Level Type Register - GPIO_INTTYPE_LEVEL - default is level sensitive\r
+ //\r
+ Addr = IohGpioBase + GPIO_INTTYPE_LEVEL;\r
+ Data32 = *((volatile UINT32 *) (UINTN)(Addr)) & 0xFFFFFF00; // Keep reserved bits [31:8]\r
+ Data32 |= (GpioConfig->IntType & 0x000FFFFF);\r
+ *((volatile UINT32 *) (UINTN)(Addr)) = Data32;\r
+\r
+ //\r
+ // Interrupt Polarity Type Register - GPIO_INT_POLARITY - default is active low\r
+ //\r
+ Addr = IohGpioBase + GPIO_INT_POLARITY;\r
+ Data32 = *((volatile UINT32 *) (UINTN)(Addr)) & 0xFFFFFF00; // Keep reserved bits [31:8]\r
+ Data32 |= (GpioConfig->IntPolarity & 0x000FFFFF);\r
+ *((volatile UINT32 *) (UINTN)(Addr)) = Data32;\r
+\r
+ //\r
+ // Interrupt Debounce Type Register - GPIO_DEBOUNCE - default no debounce\r
+ //\r
+ Addr = IohGpioBase + GPIO_DEBOUNCE;\r
+ Data32 = *((volatile UINT32 *) (UINTN)(Addr)) & 0xFFFFFF00; // Keep reserved bits [31:8]\r
+ Data32 |= (GpioConfig->Debounce & 0x000FFFFF);\r
+ *((volatile UINT32 *) (UINTN)(Addr)) = Data32;\r
+\r
+ //\r
+ // Interrupt Clock Synchronisation Register - GPIO_LS_SYNC - default no sync with pclk_intr(APB bus clk)\r
+ //\r
+ Addr = IohGpioBase + GPIO_LS_SYNC;\r
+ Data32 = *((volatile UINT32 *) (UINTN)(Addr)) & 0xFFFFFF00; // Keep reserved bits [31:8]\r
+ Data32 |= (GpioConfig->LsSync & 0x000FFFFF);\r
+ *((volatile UINT32 *) (UINTN)(Addr)) = Data32;\r
+\r
+ //\r
+ // Gpio Controller Manipulation Tasks.\r
+ //\r
+\r
+ if (PlatformType == (EFI_PLATFORM_TYPE) Galileo) {\r
+ //\r
+ // Reset Cypress Expander on Galileo Platform\r
+ //\r
+ Addr = IohGpioBase + GPIO_SWPORTA_DR;\r
+ Data32 = *((volatile UINT32 *) (UINTN)(Addr));\r
+ Data32 |= BIT4; // Cypress Reset line controlled by GPIO<4>\r
+ *((volatile UINT32 *) (UINTN)(Addr)) = Data32;\r
+\r
+ Data32 = *((volatile UINT32 *) (UINTN)(Addr));\r
+ Data32 &= ~BIT4; // Cypress Reset line controlled by GPIO<4>\r
+ *((volatile UINT32 *) (UINTN)(Addr)) = Data32;\r
+\r
+ }\r
+\r
+ //\r
+ // Restore settings for PCI CMD/BAR registers\r
+ //\r
+ PciWrite32 ((DevPcieAddr + PcdGet8 (PcdIohGpioBarRegister)), SaveBarReg);\r
+ PciWrite16 (DevPcieAddr + PCI_COMMAND_OFFSET, SaveCmdReg);\r
+}\r
+\r
+/**\r
+ Performs any early platform init of SoC Ethernet Mac devices.\r
+\r
+ @param IohMac0Address Mac address to program into Mac0 device.\r
+ @param IohMac1Address Mac address to program into Mac1 device.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+EarlyPlatformMacInit (\r
+ IN CONST UINT8 *IohMac0Address,\r
+ IN CONST UINT8 *IohMac1Address\r
+ )\r
+{\r
+ BOOLEAN SetMacAddr;\r
+\r
+ //\r
+ // Set chipset MAC0 address if configured.\r
+ //\r
+ SetMacAddr =\r
+ (CompareMem (ChipsetDefaultMac, IohMac0Address, sizeof (ChipsetDefaultMac))) != 0;\r
+ if (SetMacAddr) {\r
+ if ((*(IohMac0Address) & BIT0) != 0) {\r
+ DEBUG ((EFI_D_ERROR, "HALT: Multicast Mac Address configured for Ioh MAC [B:%d, D:%d, F:%d]\n",\r
+ (UINTN) IOH_MAC0_BUS_NUMBER,\r
+ (UINTN) IOH_MAC0_DEVICE_NUMBER,\r
+ (UINTN) IOH_MAC0_FUNCTION_NUMBER\r
+ ));\r
+ ASSERT (FALSE);\r
+ } else {\r
+ SetLanControllerMacAddr (\r
+ IOH_MAC0_BUS_NUMBER,\r
+ IOH_MAC0_DEVICE_NUMBER,\r
+ IOH_MAC0_FUNCTION_NUMBER,\r
+ IohMac0Address,\r
+ (UINT32) PcdGet64(PcdIohMac0MmioBase)\r
+ );\r
+ }\r
+ } else {\r
+ DEBUG ((EFI_D_WARN, "WARNING: Ioh MAC [B:%d, D:%d, F:%d] NO HW ADDR CONFIGURED!!!\n",\r
+ (UINTN) IOH_MAC0_BUS_NUMBER,\r
+ (UINTN) IOH_MAC0_DEVICE_NUMBER,\r
+ (UINTN) IOH_MAC0_FUNCTION_NUMBER\r
+ ));\r
+ }\r
+\r
+ //\r
+ // Set chipset MAC1 address if configured.\r
+ //\r
+ SetMacAddr =\r
+ (CompareMem (ChipsetDefaultMac, IohMac1Address, sizeof (ChipsetDefaultMac))) != 0;\r
+ if (SetMacAddr) {\r
+ if ((*(IohMac1Address) & BIT0) != 0) {\r
+ DEBUG ((EFI_D_ERROR, "HALT: Multicast Mac Address configured for Ioh MAC [B:%d, D:%d, F:%d]\n",\r
+ (UINTN) IOH_MAC1_BUS_NUMBER,\r
+ (UINTN) IOH_MAC1_DEVICE_NUMBER,\r
+ (UINTN) IOH_MAC1_FUNCTION_NUMBER\r
+ ));\r
+ ASSERT (FALSE);\r
+ } else {\r
+ SetLanControllerMacAddr (\r
+ IOH_MAC1_BUS_NUMBER,\r
+ IOH_MAC1_DEVICE_NUMBER,\r
+ IOH_MAC1_FUNCTION_NUMBER,\r
+ IohMac1Address,\r
+ (UINT32) PcdGet64(PcdIohMac1MmioBase)\r
+ );\r
+ }\r
+ } else {\r
+ DEBUG ((EFI_D_WARN, "WARNING: Ioh MAC [B:%d, D:%d, F:%d] NO HW ADDR CONFIGURED!!!\n",\r
+ (UINTN) IOH_MAC1_BUS_NUMBER,\r
+ (UINTN) IOH_MAC1_DEVICE_NUMBER,\r
+ (UINTN) IOH_MAC1_FUNCTION_NUMBER\r
+ ));\r
+ }\r
+}\r
+\r
--- /dev/null
+/** @file\r
+The header file of Platform PEIM.\r
+\r
+Copyright (c) 2013 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+\r
+#ifndef __PLATFORM_EARLY_INIT_H__\r
+#define __PLATFORM_EARLY_INIT_H__\r
+\r
+#define PEI_STALL_RESOLUTION 1\r
+#define STALL_PEIM_SIGNATURE SIGNATURE_32('p','p','u','s')\r
+\r
+typedef struct {\r
+ UINT32 Signature;\r
+ EFI_FFS_FILE_HEADER *FfsHeader;\r
+ EFI_PEI_NOTIFY_DESCRIPTOR StallNotify;\r
+} STALL_CALLBACK_STATE_INFORMATION;\r
+\r
+#define STALL_PEIM_FROM_THIS(a) CR (a, STALL_CALLBACK_STATE_INFORMATION, StallNotify, STALL_PEIM_SIGNATURE)\r
+\r
+//\r
+// USB Phy Registers\r
+//\r
+#define USB2_GLOBAL_PORT 0x4001\r
+#define USB2_PLL1 0x7F02\r
+#define USB2_PLL2 0x7F03\r
+#define USB2_COMPBG 0x7F04\r
+\r
+/**\r
+ Peform the boot mode determination logic\r
+ If the box is closed, then\r
+ 1. If it's first time to boot, it's boot with full config .\r
+ 2. If the ChassisIntrution is selected, force to be a boot with full config\r
+ 3. Otherwise it's boot with no change.\r
+\r
+ @param PeiServices General purpose services available to every PEIM.\r
+\r
+ @param BootMode The detected boot mode.\r
+\r
+ @retval EFI_SUCCESS if the boot mode could be set\r
+**/\r
+EFI_STATUS\r
+UpdateBootMode (\r
+ IN EFI_PEI_SERVICES **PeiServices,\r
+ OUT EFI_BOOT_MODE *BootMode\r
+ );\r
+\r
+/**\r
+ This function reset the entire platform, including all processor and devices, and\r
+ reboots the system.\r
+\r
+ @param PeiServices General purpose services available to every PEIM.\r
+\r
+ @retval EFI_SUCCESS if it completed successfully.\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+ResetSystem (\r
+ IN CONST EFI_PEI_SERVICES **PeiServices\r
+ );\r
+\r
+/**\r
+ This function will be called when MRC is done.\r
+\r
+ @param PeiServices General purpose services available to every PEIM.\r
+\r
+ @param NotifyDescriptor Information about the notify event..\r
+\r
+ @param Ppi The notify context.\r
+\r
+ @retval EFI_SUCCESS If the function completed successfully.\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+MemoryDiscoveredPpiNotifyCallback (\r
+ IN EFI_PEI_SERVICES **PeiServices,\r
+ IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,\r
+ IN VOID *Ppi\r
+ );\r
+\r
+/**\r
+ This is the callback function notified by FvFileLoader PPI, it depends on FvFileLoader PPI to load\r
+ the PEIM into memory.\r
+\r
+ @param PeiServices General purpose services available to every PEIM.\r
+ @param NotifyDescriptor The context of notification.\r
+ @param Ppi The notify PPI.\r
+\r
+ @retval EFI_SUCCESS if it completed successfully.\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+FvFileLoaderPpiNotifyCallback (\r
+ IN EFI_PEI_SERVICES **PeiServices,\r
+ IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,\r
+ IN VOID *Ppi\r
+ );\r
+\r
+/**\r
+ This function provides a blocking stall for reset at least the given number of microseconds\r
+ stipulated in the final argument.\r
+\r
+ @param PeiServices General purpose services available to every PEIM.\r
+\r
+ @param this Pointer to the local data for the interface.\r
+\r
+ @param Microseconds number of microseconds for which to stall.\r
+\r
+ @retval EFI_SUCCESS the function provided at least the required stall.\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+Stall (\r
+ IN CONST EFI_PEI_SERVICES **PeiServices,\r
+ IN CONST EFI_PEI_STALL_PPI *This,\r
+ IN UINTN Microseconds\r
+ );\r
+\r
+/**\r
+ This function initialize recovery functionality by installing the recovery PPI.\r
+\r
+ @param PeiServices General purpose services available to every PEIM.\r
+\r
+ @retval EFI_SUCCESS if the interface could be successfully installed.\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+PeimInitializeRecovery (\r
+ IN EFI_PEI_SERVICES **PeiServices\r
+ );\r
+\r
+/**\r
+ This function\r
+ 1. Calling MRC to initialize memory.\r
+ 2. Install EFI Memory.\r
+ 3. Create HOB of system memory.\r
+\r
+ @param PeiServices Pointer to the PEI Service Table\r
+\r
+ @retval EFI_SUCCESS If it completes successfully.\r
+\r
+**/\r
+EFI_STATUS\r
+MemoryInit (\r
+ IN EFI_PEI_SERVICES **PeiServices\r
+ );\r
+\r
+/** Return info derived from Installing Memory by MemoryInit.\r
+\r
+ @param[out] RmuMainBaseAddressPtr Return RmuMainBaseAddress to this location.\r
+ @param[out] SmramDescriptorPtr Return start of Smram descriptor list to this location.\r
+ @param[out] NumSmramRegionsPtr Return numbers of Smram regions to this location.\r
+\r
+ @return Address of RMU shadow region at the top of available memory.\r
+ @return List of Smram descriptors for each Smram region.\r
+ @return Numbers of Smram regions.\r
+**/\r
+VOID\r
+EFIAPI\r
+InfoPostInstallMemory (\r
+ OUT UINT32 *RmuMainBaseAddressPtr OPTIONAL,\r
+ OUT EFI_SMRAM_DESCRIPTOR **SmramDescriptorPtr OPTIONAL,\r
+ OUT UINTN *NumSmramRegionsPtr OPTIONAL\r
+ );\r
+\r
+/**\r
+ This function provides the implementation of AtaController PPI Enable Channel function.\r
+\r
+ @param PeiServices General purpose services available to every PEIM.\r
+ @param this Pointer to the local data for the interface.\r
+ @param ChannelMask This parameter is used to specify primary or slavery IDE channel.\r
+\r
+ @retval EFI_SUCCESS Procedure returned successfully.\r
+**/\r
+\r
+EFI_STATUS\r
+EnableAtaChannel (\r
+ IN EFI_PEI_SERVICES **PeiServices,\r
+ IN PEI_ATA_CONTROLLER_PPI *This,\r
+ IN UINT8 ChannelMask\r
+ );\r
+\r
+/**\r
+ This function provides the implementation of AtaController PPI Get IDE channel Register Base Address\r
+\r
+ @param PeiServices General purpose services available to every PEIM.\r
+ @param this Pointer to the local data for the interface.\r
+ @param IdeRegsBaseAddr Pointer to IDE_REGS_BASE_ADDR struct, which is used to record\r
+ IDE Command and Control regeisters Base Address.\r
+\r
+ @retval EFI_SUCCESS Procedure returned successfully.\r
+**/\r
+\r
+EFI_STATUS\r
+GetIdeRegsBaseAddr (\r
+ IN EFI_PEI_SERVICES **PeiServices,\r
+ IN PEI_ATA_CONTROLLER_PPI *This,\r
+ IN IDE_REGS_BASE_ADDR *IdeRegsBaseAddr\r
+ );\r
+\r
+VOID\r
+EFIAPI\r
+InitializeUSBPhy (\r
+ VOID\r
+ );\r
+\r
+/**\r
+ This function provides early platform initialisation.\r
+\r
+ @param PlatformInfo Pointer to platform Info structure.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+EarlyPlatformInit (\r
+ VOID\r
+ );\r
+\r
+/**\r
+ This function provides early platform GPIO initialisation.\r
+\r
+ @param PlatformType Platform type for GPIO init.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+EarlyPlatformLegacyGpioInit (\r
+ IN CONST EFI_PLATFORM_TYPE PlatformType\r
+ );\r
+\r
+/**\r
+ Performs any early platform specific GPIO manipulation.\r
+\r
+ @param PlatformType Platform type GPIO manipulation.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+EarlyPlatformLegacyGpioManipulation (\r
+ IN CONST EFI_PLATFORM_TYPE PlatformType\r
+ );\r
+\r
+/**\r
+ Performs any early platform specific GPIO Controller init & manipulation.\r
+\r
+ @param PlatformType Platform type for GPIO init & manipulation.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+EarlyPlatformGpioCtrlerInitAndManipulation (\r
+ IN CONST EFI_PLATFORM_TYPE PlatformType\r
+ );\r
+\r
+/**\r
+ Performs any early platform init of SoC Ethernet Mac devices.\r
+\r
+ @param IohMac0Address Mac address to program into Mac0 device.\r
+ @param IohMac1Address Mac address to program into Mac1 device.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+EarlyPlatformMacInit (\r
+ IN CONST UINT8 *IohMac0Address,\r
+ IN CONST UINT8 *IohMac1Address\r
+ );\r
+\r
+/**\r
+ Find security headers using EFI_CAPSULE_VARIABLE_NAME variables and build Hobs.\r
+\r
+ @param PeiServices General purpose services available to every PEIM.\r
+\r
+ @retval 0 if no security headers found.\r
+ @return number of security header hobs built.\r
+**/\r
+UINTN\r
+EFIAPI\r
+FindCapsuleSecurityHeadersAndBuildHobs (\r
+ IN EFI_PEI_SERVICES **PeiServices\r
+ );\r
+\r
+/**\r
+ Build capsule security header hob.\r
+\r
+ @param SecHdr Pointer to security header.\r
+\r
+ @retval NULL if failure to build HOB.\r
+ @return pointer to built hob.\r
+**/\r
+VOID *\r
+EFIAPI\r
+BuildCapsuleSecurityHeaderHob (\r
+ IN VOID *SecHdr\r
+ );\r
+\r
+#endif\r
--- /dev/null
+## @file\r
+# This is the Platform PEIM to initialize whole platform on PEI phase.\r
+#\r
+# This PEIM includes 3 parts, pre memory initialization, MRC\r
+# wrapper and post memory initialization.\r
+# On pre memory, following action is performed,\r
+# 1. Initizluize GMCH.\r
+# 2. Detect boot mode.\r
+# 3. Detect video adapter to determine whether we need pre allocated\r
+# memory.\r
+#\r
+# After that MRC wrapper calls MRC to initialize memory and install a PPI\r
+# notify to do post memory\r
+# initialization. MRC wrapper performance following actions,\r
+# 1. Install EFI Memory.\r
+# 2. Create HOB of system memory.\r
+#\r
+# On post memory, following action is performed,\r
+# 1. QNC initialization after MRC.\r
+# 2. SIO initialization.\r
+# 3. Install ResetSystem and FinvFv PPI, relocate Stall to memory on\r
+# recovery boot mode.\r
+# 4. Set MTRR for PEI\r
+# 5. Create FV HOB and Flash HOB\r
+# 6. Install RecoveryModule and AtaController PPI if on recovery boot mode.\r
+#\r
+# This PEIM does not have any register access directly, it depends on\r
+# IntelQNCLib, QNCAccess libraries to access Chipset\r
+# registers.\r
+#\r
+# Platform.c - Provide main flow and entrypoint of PEIM.\r
+# MemoryCallback.c - Includes a memory call back function notified when\r
+# MRC is done.\r
+# Recovery.c - provides the platform recoveyr functionality.\r
+# MrcWrapper.c - Contains the logic to call MRC PPI and do Framework\r
+# memory specific stuff like build memory map, build\r
+# resource description hob for DXE phase,etc.\r
+# Bootmode.c - Detect boot mode.\r
+# Copyright (c) 2013 Intel Corporation.\r
+#\r
+# This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution. The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php\r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+##\r
+\r
+[Defines]\r
+ INF_VERSION = 0x00010005\r
+ BASE_NAME = PlatformEarlyInitPei\r
+ FILE_GUID = 9618C0DC-50A4-496c-994F-7241F282ED01\r
+ MODULE_TYPE = PEIM\r
+ VERSION_STRING = 1.0\r
+ ENTRY_POINT = PeiInitPlatform\r
+\r
+#\r
+# The following information is for reference only and not required by the build tools.\r
+#\r
+# VALID_ARCHITECTURES = IA32 X64\r
+#\r
+\r
+[Sources]\r
+ Generic/Recovery.c\r
+ PlatformErratas.c\r
+ MrcWrapper.c\r
+ MrcWrapper.h\r
+ PlatformEarlyInit.c\r
+ PlatformEarlyInit.h\r
+ MemoryCallback.c\r
+ BootMode.c\r
+ CommonHeader.h\r
+ PeiFvSecurity.c\r
+ PeiFvSecurity.h\r
+\r
+[Packages]\r
+ MdePkg/MdePkg.dec\r
+ MdeModulePkg/MdeModulePkg.dec\r
+ UefiCpuPkg/UefiCpuPkg.dec\r
+ IntelFrameworkPkg/IntelFrameworkPkg.dec\r
+ IntelFrameworkModulePkg/IntelFrameworkModulePkg.dec\r
+ QuarkPlatformPkg/QuarkPlatformPkg.dec\r
+ QuarkSocPkg/QuarkSocPkg.dec\r
+\r
+[LibraryClasses]\r
+ ResetSystemLib\r
+ PrintLib\r
+ TimerLib\r
+ RecoveryOemHookLib\r
+ PcdLib\r
+ IntelQNCLib\r
+ ReportStatusCodeLib\r
+ PciLib\r
+ PciExpressLib\r
+ IoLib\r
+ PciCf8Lib\r
+ HobLib\r
+ BaseMemoryLib\r
+ PeiServicesTablePointerLib\r
+ PeiServicesLib\r
+ BaseLib\r
+ PeimEntryPoint\r
+ DebugLib\r
+ MemoryAllocationLib\r
+ PerformanceLib\r
+ CacheMaintenanceLib\r
+ MtrrLib\r
+ QNCAccessLib\r
+ PlatformHelperLib\r
+ PlatformPcieHelperLib\r
+\r
+[Guids]\r
+ gEfiMemoryConfigDataGuid # ALWAYS_CONSUMED L"MemoryConfig"\r
+ gEfiAcpiVariableGuid # ALWAYS_CONSUMED L"AcpiGlobalVariab"\r
+ gEfiMemoryTypeInformationGuid # ALWAYS_CONSUMED L"MemoryTypeInformation"\r
+ gEfiMemoryConfigDataGuid # SOMETIMES_PRODUCED Hob: GUID_EXTENSION\r
+ gEfiSmmPeiSmramMemoryReserveGuid # ALWAYS_PRODUCED Hob: GUID_EXTENSION\r
+ gEfiFirmwareFileSystem2Guid # ALWAYS_CONSUMED\r
+ gEfiCapsuleGuid # ALWAYS_CONSUMED\r
+ gPeiCapsuleOnDataCDGuid\r
+ gPeiCapsuleOnFatIdeDiskGuid\r
+ gPeiCapsuleOnFatUsbDiskGuid\r
+ gEfiMemoryOverwriteControlDataGuid # SOMETIMES_CONSUMED\r
+ gEfiQuarkCapsuleGuid\r
+\r
+[Ppis]\r
+ gQNCMemoryInitPpiGuid # PPI ALWAYS_CONSUMED\r
+ gEfiPeiMemoryDiscoveredPpiGuid # PPI ALWAYS_PRODUCED\r
+ gPeiAtaControllerPpiGuid # PPI SOMETIMES_PRODUCED\r
+ gEfiPeiStallPpiGuid # PPI ALWAYS_PRODUCED\r
+ gEfiPeiDeviceRecoveryModulePpiGuid # PPI SOMETIMES_CONSUMED\r
+ gEfiPeiRecoveryModulePpiGuid # PPI SOMETIMES_PRODUCED\r
+ gEfiPeiResetPpiGuid # PPI ALWAYS_PRODUCED\r
+ gEfiPeiReadOnlyVariable2PpiGuid # PPI ALWAYS_CONSUMED\r
+ gEfiPeiBootInRecoveryModePpiGuid # PPI SOMETIMES_PRODUCED\r
+ gEfiPeiMasterBootModePpiGuid # PPI ALWAYS_PRODUCED\r
+ gEfiPeiFirmwareVolumeInfoPpiGuid\r
+ gEfiEndOfPeiSignalPpiGuid\r
+ gEfiPeiVirtualBlockIoPpiGuid\r
+ gPeiCapsulePpiGuid # PPI ALWAYS_CONSUMED\r
+\r
+[FeaturePcd]\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdRecoveryOnFatUsbDisk\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdRecoveryOnDataCD\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdRecoveryOnFatFloppyDisk\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdRecoveryOnIdeDisk\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFrameworkCompatibilitySupport\r
+ gQuarkPlatformTokenSpaceGuid.WaitIfResetDueToError\r
+\r
+[Pcd]\r
+ gQuarkPlatformTokenSpaceGuid.PcdEsramStage1Base\r
+ gQuarkPlatformTokenSpaceGuid.PcdFlashAreaSize\r
+ gQuarkPlatformTokenSpaceGuid.PcdFlashAreaBaseAddress\r
+ gQuarkPlatformTokenSpaceGuid.PcdEccScrubBlkSize\r
+ gQuarkPlatformTokenSpaceGuid.PcdEccScrubInterval\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize\r
+ gQuarkPlatformTokenSpaceGuid.PcdFlashQNCMicrocodeSize\r
+ gEfiQuarkNcSocIdTokenSpaceGuid.PcdPmbaIoBaseAddress\r
+ gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress\r
+ gEfiQuarkNcSocIdTokenSpaceGuid.PcdPciHostBridgeIoBase\r
+ gEfiQuarkNcSocIdTokenSpaceGuid.PcdPciHostBridgeIoSize\r
+ gEfiQuarkSCSocIdTokenSpaceGuid.PcdIohUartFunctionNumber\r
+ gEfiQuarkSCSocIdTokenSpaceGuid.PcdIohUartBusNumber\r
+ gEfiQuarkSCSocIdTokenSpaceGuid.PcdIohUartDevNumber\r
+ gEfiQuarkSCSocIdTokenSpaceGuid.PcdIohGpioBusNumber\r
+ gEfiQuarkSCSocIdTokenSpaceGuid.PcdIohGpioDevNumber\r
+ gEfiQuarkSCSocIdTokenSpaceGuid.PcdIohGpioFunctionNumber\r
+ gEfiQuarkSCSocIdTokenSpaceGuid.PcdIohGpioBarRegister\r
+ gEfiQuarkSCSocIdTokenSpaceGuid.PcdIohGpioMmioBase\r
+ gEfiQuarkSCSocIdTokenSpaceGuid.PcdIohMac0MmioBase\r
+ gEfiQuarkSCSocIdTokenSpaceGuid.PcdIohMac1MmioBase\r
+ gEfiQuarkSCSocIdTokenSpaceGuid.PcdPeiQNCUsbControllerMemoryBaseAddress\r
+ gEfiQuarkNcSocIdTokenSpaceGuid.PcdRcbaMmioBaseAddress\r
+ gEfiQuarkNcSocIdTokenSpaceGuid.PcdPciHostBridgeMemory32Base\r
+ gEfiQuarkNcSocIdTokenSpaceGuid.PcdPciHostBridgeMemory32Size\r
+ gEfiQuarkNcSocIdTokenSpaceGuid.PcdPciHostBridgeMemory64Base\r
+ gEfiQuarkNcSocIdTokenSpaceGuid.PcdPciHostBridgeMemory64Size\r
+ gEfiQuarkNcSocIdTokenSpaceGuid.PcdPciExpressSize\r
+ gEfiQuarkNcSocIdTokenSpaceGuid.PcdGbaIoBaseAddress\r
+ gEfiQuarkNcSocIdTokenSpaceGuid.PcdQuarkMicrocodeFile\r
+ gEfiQuarkNcSocIdTokenSpaceGuid.PcdTSegSize\r
+ gEfiQuarkNcSocIdTokenSpaceGuid.PcdESramMemorySize\r
+ gQuarkPlatformTokenSpaceGuid.PcdFlashFvRecoverySize\r
+ gQuarkPlatformTokenSpaceGuid.PcdFlashFvRecoveryBase\r
+ gQuarkPlatformTokenSpaceGuid.PcdFlashFvMainSize\r
+ gQuarkPlatformTokenSpaceGuid.PcdFlashFvMainBase\r
+ gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdBootState\r
+ gQuarkPlatformTokenSpaceGuid.PcdFlashFvPayloadBase\r
+ gQuarkPlatformTokenSpaceGuid.PcdFlashFvPayloadSize\r
+ gQuarkPlatformTokenSpaceGuid.PcdEnableFastBoot\r
+ gQuarkPlatformTokenSpaceGuid.PcdPlatformType\r
+ gEfiQuarkNcSocIdTokenSpaceGuid.PcdMrcParameters\r
+ gEfiQuarkSCSocIdTokenSpaceGuid.PcdIohEthernetMac0\r
+ gEfiQuarkSCSocIdTokenSpaceGuid.PcdIohEthernetMac1\r
+\r
+[Depex]\r
+ gEfiPeiReadOnlyVariable2PpiGuid AND gQNCMemoryInitPpiGuid\r
--- /dev/null
+/** @file\r
+Platform Erratas performed by early init PEIM driver.\r
+\r
+Copyright (c) 2013 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#include "CommonHeader.h"\r
+#include "PlatformEarlyInit.h"\r
+\r
+//\r
+// Constants.\r
+//\r
+\r
+//\r
+// Platform EHCI Packet Buffer OUT/IN Thresholds, values in number of DWORDs.\r
+//\r
+#define EHCI_OUT_THRESHOLD_VALUE (0x7f)\r
+#define EHCI_IN_THRESHOLD_VALUE (0x7f)\r
+\r
+//\r
+// Platform init USB device interrupt masks.\r
+//\r
+#define V_IOH_USBDEVICE_D_INTR_MSK_UDC_REG (0x0000007f)\r
+#define V_IOH_USBDEVICE_EP_INTR_MSK_UDC_REG (B_IOH_USBDEVICE_EP_INTR_MSK_UDC_REG_OUT_EP_MASK | B_IOH_USBDEVICE_EP_INTR_MSK_UDC_REG_IN_EP_MASK)\r
+\r
+//\r
+// Global variables defined within this source module.\r
+//\r
+\r
+UINTN IohEhciPciReg[IOH_MAX_EHCI_USB_CONTROLLERS] = {\r
+ PCI_LIB_ADDRESS (IOH_USB_BUS_NUMBER, IOH_USB_EHCI_DEVICE_NUMBER, IOH_EHCI_FUNCTION_NUMBER, 0),\r
+};\r
+\r
+UINTN IohUsbDevicePciReg[IOH_MAX_USBDEVICE_USB_CONTROLLERS] = {\r
+ PCI_LIB_ADDRESS (IOH_USB_BUS_NUMBER, IOH_USBDEVICE_DEVICE_NUMBER, IOH_USBDEVICE_FUNCTION_NUMBER, 0),\r
+};\r
+\r
+//\r
+// Routines local to this source module.\r
+//\r
+\r
+/** Perform USB erratas after MRC init.\r
+\r
+**/\r
+VOID\r
+PlatformUsbErratasPostMrc (\r
+ VOID\r
+ )\r
+{\r
+ UINT32 Index;\r
+ UINT32 TempBar0Addr;\r
+ UINT16 SaveCmdReg;\r
+ UINT32 SaveBar0Reg;\r
+\r
+ TempBar0Addr = PcdGet32(PcdPeiQNCUsbControllerMemoryBaseAddress);\r
+\r
+ //\r
+ // Apply EHCI controller erratas.\r
+ //\r
+ for (Index = 0; Index < IOH_MAX_EHCI_USB_CONTROLLERS; Index++, TempBar0Addr += IOH_USB_CONTROLLER_MMIO_RANGE) {\r
+\r
+ if ((PciRead16 (IohEhciPciReg[Index] + R_IOH_USB_VENDOR_ID)) != V_IOH_USB_VENDOR_ID) {\r
+ continue; // Device not enabled, skip.\r
+ }\r
+\r
+ //\r
+ // Save current settings for PCI CMD/BAR0 registers\r
+ //\r
+ SaveCmdReg = PciRead16 (IohEhciPciReg[Index] + R_IOH_USB_COMMAND);\r
+ SaveBar0Reg = PciRead32 (IohEhciPciReg[Index] + R_IOH_USB_MEMBAR);\r
+\r
+ //\r
+ // Temp. assign base address register, Enable Memory Space.\r
+ //\r
+ PciWrite32 ((IohEhciPciReg[Index] + R_IOH_USB_MEMBAR), TempBar0Addr);\r
+ PciWrite16 (IohEhciPciReg[Index] + R_IOH_USB_COMMAND, SaveCmdReg | B_IOH_USB_COMMAND_MSE);\r
+\r
+\r
+ //\r
+ // Set packet buffer OUT/IN thresholds.\r
+ //\r
+ MmioAndThenOr32 (\r
+ TempBar0Addr + R_IOH_EHCI_INSNREG01,\r
+ (UINT32) (~(B_IOH_EHCI_INSNREG01_OUT_THRESHOLD_MASK | B_IOH_EHCI_INSNREG01_IN_THRESHOLD_MASK)),\r
+ (UINT32) ((EHCI_OUT_THRESHOLD_VALUE << B_IOH_EHCI_INSNREG01_OUT_THRESHOLD_BP) | (EHCI_IN_THRESHOLD_VALUE << B_IOH_EHCI_INSNREG01_IN_THRESHOLD_BP))\r
+ );\r
+\r
+ //\r
+ // Restore settings for PCI CMD/BAR0 registers\r
+ //\r
+ PciWrite32 ((IohEhciPciReg[Index] + R_IOH_USB_MEMBAR), SaveBar0Reg);\r
+ PciWrite16 (IohEhciPciReg[Index] + R_IOH_USB_COMMAND, SaveCmdReg);\r
+ }\r
+\r
+ //\r
+ // Apply USB device controller erratas.\r
+ //\r
+ for (Index = 0; Index < IOH_MAX_USBDEVICE_USB_CONTROLLERS; Index++, TempBar0Addr += IOH_USB_CONTROLLER_MMIO_RANGE) {\r
+\r
+ if ((PciRead16 (IohUsbDevicePciReg[Index] + R_IOH_USB_VENDOR_ID)) != V_IOH_USB_VENDOR_ID) {\r
+ continue; // Device not enabled, skip.\r
+ }\r
+\r
+ //\r
+ // Save current settings for PCI CMD/BAR0 registers\r
+ //\r
+ SaveCmdReg = PciRead16 (IohUsbDevicePciReg[Index] + R_IOH_USB_COMMAND);\r
+ SaveBar0Reg = PciRead32 (IohUsbDevicePciReg[Index] + R_IOH_USB_MEMBAR);\r
+\r
+ //\r
+ // Temp. assign base address register, Enable Memory Space.\r
+ //\r
+ PciWrite32 ((IohUsbDevicePciReg[Index] + R_IOH_USB_MEMBAR), TempBar0Addr);\r
+ PciWrite16 (IohUsbDevicePciReg[Index] + R_IOH_USB_COMMAND, SaveCmdReg | B_IOH_USB_COMMAND_MSE);\r
+\r
+ //\r
+ // Erratas for USB Device interrupt registers.\r
+ //\r
+\r
+ //\r
+ // 1st Mask interrupts.\r
+ //\r
+ MmioWrite32 (\r
+ TempBar0Addr + R_IOH_USBDEVICE_D_INTR_MSK_UDC_REG,\r
+ V_IOH_USBDEVICE_D_INTR_MSK_UDC_REG\r
+ );\r
+ //\r
+ // 2nd RW/1C of equivalent status bits.\r
+ //\r
+ MmioWrite32 (\r
+ TempBar0Addr + R_IOH_USBDEVICE_D_INTR_UDC_REG,\r
+ V_IOH_USBDEVICE_D_INTR_MSK_UDC_REG\r
+ );\r
+\r
+ //\r
+ // 1st Mask end point interrupts.\r
+ //\r
+ MmioWrite32 (\r
+ TempBar0Addr + R_IOH_USBDEVICE_EP_INTR_MSK_UDC_REG,\r
+ V_IOH_USBDEVICE_EP_INTR_MSK_UDC_REG\r
+ );\r
+ //\r
+ // 2nd RW/1C of equivalent end point status bits.\r
+ //\r
+ MmioWrite32 (\r
+ TempBar0Addr + R_IOH_USBDEVICE_EP_INTR_UDC_REG,\r
+ V_IOH_USBDEVICE_EP_INTR_MSK_UDC_REG\r
+ );\r
+\r
+ //\r
+ // Restore settings for PCI CMD/BAR0 registers\r
+ //\r
+ PciWrite32 ((IohUsbDevicePciReg[Index] + R_IOH_USB_MEMBAR), SaveBar0Reg);\r
+ PciWrite16 (IohUsbDevicePciReg[Index] + R_IOH_USB_COMMAND, SaveCmdReg);\r
+ }\r
+}\r
+\r
+//\r
+// Routines exported by this source module.\r
+//\r
+\r
+/** Perform Platform Erratas after MRC.\r
+\r
+ @retval EFI_SUCCESS Operation success.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+PlatformErratasPostMrc (\r
+ VOID\r
+ )\r
+{\r
+ PlatformUsbErratasPostMrc ();\r
+ return EFI_SUCCESS;\r
+}\r
--- /dev/null
+/** @file\r
+Defines data structure that is the volume header found.These data is intent\r
+to decouple FVB driver with FV header.\r
+\r
+Copyright (c) 2013 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+**/\r
+\r
+#include <PiDxe.h>\r
+#include "FwBlockService.h"\r
+\r
+\r
+//#define FVB_MEDIA_BLOCK_SIZE PcdGet32(PcdFlashMinEraseSize)\r
+#define FVB_MEDIA_BLOCK_SIZE 0x1000\r
+\r
+typedef struct {\r
+ EFI_PHYSICAL_ADDRESS BaseAddress;\r
+ EFI_FIRMWARE_VOLUME_HEADER FvbInfo;\r
+ //\r
+ //EFI_FV_BLOCK_MAP_ENTRY ExtraBlockMap[n];//n=0\r
+ //\r
+ EFI_FV_BLOCK_MAP_ENTRY End[1];\r
+} EFI_FVB2_MEDIA_INFO;\r
+\r
+//\r
+// This data structure contains a template of all correct FV headers, which is used to restore\r
+// Fv header if it's corrupted.\r
+//\r
+EFI_FVB2_MEDIA_INFO mPlatformFvbMediaInfo[] = {\r
+ //\r
+ // Main BIOS FVB\r
+ //\r
+ {\r
+ 0,\r
+ {\r
+ {0,}, //ZeroVector[16]\r
+ EFI_FIRMWARE_FILE_SYSTEM2_GUID,\r
+ 0,\r
+ EFI_FVH_SIGNATURE,\r
+ 0x0004feff, // check MdePkg/Include/Pi/PiFirmwareVolume.h for details on EFI_FVB_ATTRIBUTES_2\r
+ sizeof (EFI_FIRMWARE_VOLUME_HEADER) + sizeof (EFI_FV_BLOCK_MAP_ENTRY),\r
+ 0, //CheckSum, check the FD for the value.\r
+ 0, //ExtHeaderOffset\r
+ {0,}, //Reserved[1]\r
+ 2, //Revision\r
+ {\r
+ {\r
+ 0,\r
+ 0,\r
+ }\r
+ }\r
+ },\r
+ {\r
+ {\r
+ 0,\r
+ 0\r
+ }\r
+ }\r
+ },\r
+ //\r
+ // Systen NvStorage FVB\r
+ //\r
+ {\r
+ 0,\r
+ {\r
+ {0,}, //ZeroVector[16]\r
+ EFI_SYSTEM_NV_DATA_FV_GUID,\r
+ 0,\r
+ EFI_FVH_SIGNATURE,\r
+ 0x0004feff, // check MdePkg/Include/Pi/PiFirmwareVolume.h for details on EFI_FVB_ATTRIBUTES_2\r
+ sizeof (EFI_FIRMWARE_VOLUME_HEADER) + sizeof (EFI_FV_BLOCK_MAP_ENTRY),\r
+ 0, //CheckSum which will be calucated dynamically.\r
+ 0, //ExtHeaderOffset\r
+ {0,}, //Reserved[1]\r
+ 2, //Revision\r
+ {\r
+ {\r
+ 0,\r
+ 0,\r
+ }\r
+ }\r
+ },\r
+ {\r
+ {\r
+ 0,\r
+ 0\r
+ }\r
+ }\r
+ },\r
+ //\r
+ // Recovery BIOS FVB\r
+ //\r
+ {\r
+ 0,\r
+ {\r
+ {0,}, //ZeroVector[16]\r
+ EFI_FIRMWARE_FILE_SYSTEM2_GUID,\r
+ 0,\r
+ EFI_FVH_SIGNATURE,\r
+ 0x0004feff, // check MdePkg/Include/Pi/PiFirmwareVolume.h for details on EFI_FVB_ATTRIBUTES_2\r
+ sizeof (EFI_FIRMWARE_VOLUME_HEADER) + sizeof (EFI_FV_BLOCK_MAP_ENTRY),\r
+ 0, //CheckSum which will be calucated dynamically.\r
+ 0, //ExtHeaderOffset\r
+ {0,}, //Reserved[1]\r
+ 2, //Revision\r
+ {\r
+ {\r
+ 0,\r
+ 0,\r
+ }\r
+ }\r
+ },\r
+ {\r
+ {\r
+ 0,\r
+ 0\r
+ }\r
+ }\r
+ },\r
+ //\r
+ // Payload FVB\r
+ //\r
+ {\r
+ 0,\r
+ {\r
+ {0,}, //ZeroVector[16]\r
+ EFI_FIRMWARE_FILE_SYSTEM2_GUID,\r
+ 0,\r
+ EFI_FVH_SIGNATURE,\r
+ 0x0004feff, // check MdePkg/Include/Pi/PiFirmwareVolume.h for details on EFI_FVB_ATTRIBUTES_2\r
+ sizeof (EFI_FIRMWARE_VOLUME_HEADER) + sizeof (EFI_FV_BLOCK_MAP_ENTRY),\r
+ 0, //CheckSum which will be calucated dynamically.\r
+ 0x60, //ExtHeaderOffset\r
+ {0,}, //Reserved[1]\r
+ 2, //Revision\r
+ {\r
+ {\r
+ 0,\r
+ 0,\r
+ }\r
+ }\r
+ },\r
+ {\r
+ {\r
+ 0,\r
+ 0\r
+ }\r
+ }\r
+ }\r
+};\r
+\r
+\r
+//\r
+// FTW working space and FTW spare space don't have FV header.\r
+// We need create one for them and use it for FVB protocol.\r
+//\r
+EFI_FVB2_MEDIA_INFO mPlatformFtwFvbInfo[] = {\r
+ //\r
+ // System variable FTW working FVB\r
+ //\r
+ {\r
+ 0,\r
+ {\r
+ {0,}, //ZeroVector[16]\r
+ EFI_SYSTEM_NV_DATA_FV_GUID,\r
+ 0,\r
+ EFI_FVH_SIGNATURE,\r
+ 0x0004feff, // check MdePkg/Include/Pi/PiFirmwareVolume.h for details on EFI_FVB_ATTRIBUTES_2\r
+ sizeof (EFI_FIRMWARE_VOLUME_HEADER) + sizeof (EFI_FV_BLOCK_MAP_ENTRY),\r
+ 0, //CheckSum which will be calucated dynamically.\r
+ 0, //ExtHeaderOffset\r
+ {0,}, //Reserved[1]\r
+ 2, //Revision\r
+ {\r
+ {\r
+ 0,\r
+ 0,\r
+ }\r
+ }\r
+ },\r
+ {\r
+ {\r
+ 0,\r
+ 0\r
+ }\r
+ }\r
+ },\r
+ //\r
+ // Systen NV variable FTW spare FVB\r
+ //\r
+ {\r
+ 0,\r
+ {\r
+ {0,}, //ZeroVector[16]\r
+ EFI_SYSTEM_NV_DATA_FV_GUID,\r
+ 0,\r
+ EFI_FVH_SIGNATURE,\r
+ 0x0004feff, // check MdePkg/Include/Pi/PiFirmwareVolume.h for details on EFI_FVB_ATTRIBUTES_2\r
+ sizeof (EFI_FIRMWARE_VOLUME_HEADER) + sizeof (EFI_FV_BLOCK_MAP_ENTRY),\r
+ 0, //CheckSum which will be calucated dynamically.\r
+ 0, //ExtHeaderOffset\r
+ {0,}, //Reserved[1]\r
+ 2, //Revision\r
+ {\r
+ {\r
+ 0,\r
+ 0,\r
+ }\r
+ }\r
+ },\r
+ {\r
+ {\r
+ 0,\r
+ 0\r
+ }\r
+ }\r
+ }\r
+};\r
+\r
+\r
+\r
+EFI_STATUS\r
+GetFtwFvbInfo (\r
+ IN EFI_PHYSICAL_ADDRESS FvBaseAddress,\r
+ OUT EFI_FIRMWARE_VOLUME_HEADER **FvbInfo\r
+ )\r
+{\r
+ UINTN Index;\r
+ EFI_FIRMWARE_VOLUME_HEADER *FvHeader;\r
+\r
+ //\r
+ // Init Fvb data\r
+ //\r
+ mPlatformFtwFvbInfo[0].BaseAddress = PcdGet32 (PcdFlashNvStorageFtwWorkingBase);\r
+ mPlatformFtwFvbInfo[0].FvbInfo.FvLength = PcdGet32 (PcdFlashNvStorageFtwWorkingSize);\r
+ mPlatformFtwFvbInfo[0].FvbInfo.BlockMap[0].NumBlocks = PcdGet32 (PcdFlashNvStorageFtwWorkingSize) / FVB_MEDIA_BLOCK_SIZE;\r
+ mPlatformFtwFvbInfo[0].FvbInfo.BlockMap[0].Length = FVB_MEDIA_BLOCK_SIZE;\r
+ ASSERT ((PcdGet32 (PcdFlashNvStorageFtwWorkingSize) % FVB_MEDIA_BLOCK_SIZE) == 0);\r
+\r
+ mPlatformFtwFvbInfo[1].BaseAddress = PcdGet32 (PcdFlashNvStorageFtwSpareBase);\r
+ mPlatformFtwFvbInfo[1].FvbInfo.FvLength = PcdGet32 (PcdFlashNvStorageFtwSpareSize);\r
+ mPlatformFtwFvbInfo[1].FvbInfo.BlockMap[0].NumBlocks = PcdGet32 (PcdFlashNvStorageFtwSpareSize) / FVB_MEDIA_BLOCK_SIZE;\r
+ mPlatformFtwFvbInfo[1].FvbInfo.BlockMap[0].Length = FVB_MEDIA_BLOCK_SIZE;\r
+ ASSERT ((PcdGet32 (PcdFlashNvStorageFtwSpareSize) % FVB_MEDIA_BLOCK_SIZE) == 0);\r
+\r
+ for (Index=0; Index < sizeof (mPlatformFtwFvbInfo)/sizeof (mPlatformFtwFvbInfo[0]); Index += 1) {\r
+ if (mPlatformFtwFvbInfo[Index].BaseAddress == FvBaseAddress) {\r
+ FvHeader = &mPlatformFtwFvbInfo[Index].FvbInfo;\r
+ //\r
+ // Update the checksum value of FV header.\r
+ //\r
+ FvHeader->Checksum = CalculateCheckSum16 ((UINT16 *) FvHeader, FvHeader->HeaderLength / sizeof (UINT16));\r
+\r
+ *FvbInfo = FvHeader;\r
+\r
+ DEBUG ((EFI_D_INFO, "\nFTW BaseAddr: 0x%lx \n", FvBaseAddress));\r
+ DEBUG ((EFI_D_INFO, "FvLength: 0x%lx \n", (*FvbInfo)->FvLength));\r
+ DEBUG ((EFI_D_INFO, "HeaderLength: 0x%x \n", (*FvbInfo)->HeaderLength));\r
+ DEBUG ((EFI_D_INFO, "FvBlockMap[0].NumBlocks: 0x%x \n", (*FvbInfo)->BlockMap[0].NumBlocks));\r
+ DEBUG ((EFI_D_INFO, "FvBlockMap[0].BlockLength: 0x%x \n", (*FvbInfo)->BlockMap[0].Length));\r
+ DEBUG ((EFI_D_INFO, "FvBlockMap[1].NumBlocks: 0x%x \n", (*FvbInfo)->BlockMap[1].NumBlocks));\r
+ DEBUG ((EFI_D_INFO, "FvBlockMap[1].BlockLength: 0x%x \n\n", (*FvbInfo)->BlockMap[1].Length));\r
+\r
+ return EFI_SUCCESS;\r
+ }\r
+ }\r
+ return EFI_NOT_FOUND;\r
+}\r
+\r
+\r
+EFI_STATUS\r
+GetFvbInfo (\r
+ IN EFI_PHYSICAL_ADDRESS FvBaseAddress,\r
+ OUT EFI_FIRMWARE_VOLUME_HEADER **FvbInfo\r
+ )\r
+{\r
+ UINTN Index;\r
+ EFI_FIRMWARE_VOLUME_HEADER *FvHeader;\r
+\r
+ //\r
+ // Init Fvb data\r
+ //\r
+ mPlatformFvbMediaInfo[0].BaseAddress = PcdGet32 (PcdFlashFvMainBase);\r
+ mPlatformFvbMediaInfo[0].FvbInfo.FvLength = PcdGet32 (PcdFlashFvMainSize);\r
+ mPlatformFvbMediaInfo[0].FvbInfo.BlockMap[0].NumBlocks = PcdGet32 (PcdFlashFvMainSize) / FVB_MEDIA_BLOCK_SIZE;\r
+ mPlatformFvbMediaInfo[0].FvbInfo.BlockMap[0].Length = FVB_MEDIA_BLOCK_SIZE;\r
+ ASSERT ((PcdGet32 (PcdFlashFvMainSize) % FVB_MEDIA_BLOCK_SIZE) == 0);\r
+\r
+ mPlatformFvbMediaInfo[1].BaseAddress = PcdGet32 (PcdFlashNvStorageVariableBase);\r
+ mPlatformFvbMediaInfo[1].FvbInfo.FvLength = PcdGet32 (PcdFlashNvStorageVariableSize);\r
+ mPlatformFvbMediaInfo[1].FvbInfo.BlockMap[0].NumBlocks = PcdGet32 (PcdFlashNvStorageVariableSize) / FVB_MEDIA_BLOCK_SIZE;\r
+ mPlatformFvbMediaInfo[1].FvbInfo.BlockMap[0].Length = FVB_MEDIA_BLOCK_SIZE;\r
+ ASSERT ((PcdGet32 (PcdFlashNvStorageVariableSize) % FVB_MEDIA_BLOCK_SIZE) == 0);\r
+\r
+ mPlatformFvbMediaInfo[2].BaseAddress = PcdGet32 (PcdFlashFvRecoveryBase);\r
+ mPlatformFvbMediaInfo[2].FvbInfo.FvLength = PcdGet32 (PcdFlashFvRecoverySize);\r
+ mPlatformFvbMediaInfo[2].FvbInfo.BlockMap[0].NumBlocks = PcdGet32 (PcdFlashFvRecoverySize) / FVB_MEDIA_BLOCK_SIZE;\r
+ mPlatformFvbMediaInfo[2].FvbInfo.BlockMap[0].Length = FVB_MEDIA_BLOCK_SIZE;\r
+ ASSERT ((PcdGet32 (PcdFlashFvRecoverySize) % FVB_MEDIA_BLOCK_SIZE) == 0);\r
+\r
+ mPlatformFvbMediaInfo[3].BaseAddress = PcdGet32 (PcdFlashFvPayloadBase);\r
+ mPlatformFvbMediaInfo[3].FvbInfo.FvLength = PcdGet32 (PcdFlashFvPayloadSize);\r
+ mPlatformFvbMediaInfo[3].FvbInfo.BlockMap[0].NumBlocks = PcdGet32 (PcdFlashFvPayloadSize) / FVB_MEDIA_BLOCK_SIZE;\r
+ mPlatformFvbMediaInfo[3].FvbInfo.BlockMap[0].Length = FVB_MEDIA_BLOCK_SIZE;\r
+ ASSERT ((PcdGet32 (PcdFlashFvPayloadSize) % FVB_MEDIA_BLOCK_SIZE) == 0);\r
+\r
+ for (Index=0; Index < sizeof (mPlatformFvbMediaInfo)/sizeof (mPlatformFvbMediaInfo[0]); Index += 1) {\r
+ if (mPlatformFvbMediaInfo[Index].BaseAddress == FvBaseAddress) {\r
+ FvHeader = &mPlatformFvbMediaInfo[Index].FvbInfo;\r
+ //\r
+ // Update the checksum value of FV header.\r
+ //\r
+ FvHeader->Checksum = CalculateCheckSum16 ((UINT16 *) FvHeader, FvHeader->HeaderLength / sizeof (UINT16));\r
+\r
+ *FvbInfo = FvHeader;\r
+\r
+ DEBUG ((EFI_D_INFO, "\nBaseAddr: 0x%lx \n", FvBaseAddress));\r
+ DEBUG ((EFI_D_INFO, "FvLength: 0x%lx \n", (*FvbInfo)->FvLength));\r
+ DEBUG ((EFI_D_INFO, "HeaderLength: 0x%x \n", (*FvbInfo)->HeaderLength));\r
+ DEBUG ((EFI_D_INFO, "FvBlockMap[0].NumBlocks: 0x%x \n", (*FvbInfo)->BlockMap[0].NumBlocks));\r
+ DEBUG ((EFI_D_INFO, "FvBlockMap[0].BlockLength: 0x%x \n", (*FvbInfo)->BlockMap[0].Length));\r
+ DEBUG ((EFI_D_INFO, "FvBlockMap[1].NumBlocks: 0x%x \n", (*FvbInfo)->BlockMap[1].NumBlocks));\r
+ DEBUG ((EFI_D_INFO, "FvBlockMap[1].BlockLength: 0x%x \n\n", (*FvbInfo)->BlockMap[1].Length));\r
+\r
+ return EFI_SUCCESS;\r
+ }\r
+ }\r
+ return EFI_NOT_FOUND;\r
+}\r
--- /dev/null
+/** @file\r
+\r
+Copyright (c) 2013-2015 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+**/\r
+\r
+#include "FwBlockService.h"\r
+\r
+ESAL_FWB_GLOBAL *mFvbModuleGlobal;\r
+EFI_GUID gEfiFirmwareVolumeBlockProtocolGuid;\r
+EFI_GUID gEfiSmmFirmwareVolumeBlockProtocolGuid;\r
+\r
+EFI_FW_VOL_BLOCK_DEVICE mFvbDeviceTemplate = {\r
+ FVB_DEVICE_SIGNATURE, // Signature\r
+ //\r
+ // FV_DEVICE_PATH FvDevicePath\r
+ //\r
+ {\r
+ {\r
+ {\r
+ HARDWARE_DEVICE_PATH,\r
+ HW_MEMMAP_DP,\r
+ {\r
+ (UINT8)(sizeof (MEMMAP_DEVICE_PATH)),\r
+ (UINT8)(sizeof (MEMMAP_DEVICE_PATH) >> 8)\r
+ }\r
+ },\r
+ EfiMemoryMappedIO,\r
+ (EFI_PHYSICAL_ADDRESS) 0,\r
+ (EFI_PHYSICAL_ADDRESS) 0\r
+ },\r
+ {\r
+ END_DEVICE_PATH_TYPE,\r
+ END_ENTIRE_DEVICE_PATH_SUBTYPE,\r
+ {\r
+ END_DEVICE_PATH_LENGTH,\r
+ 0\r
+ }\r
+ }\r
+ },\r
+ //\r
+ // UEFI_FV_DEVICE_PATH UefiFvDevicePath\r
+ //\r
+ {\r
+ {\r
+ {\r
+ MEDIA_DEVICE_PATH,\r
+ MEDIA_PIWG_FW_VOL_DP,\r
+ {\r
+ (UINT8)(sizeof (MEDIA_FW_VOL_DEVICE_PATH)),\r
+ (UINT8)(sizeof (MEDIA_FW_VOL_DEVICE_PATH) >> 8)\r
+ }\r
+ },\r
+ { 0 }\r
+ },\r
+ {\r
+ END_DEVICE_PATH_TYPE,\r
+ END_ENTIRE_DEVICE_PATH_SUBTYPE,\r
+ {\r
+ END_DEVICE_PATH_LENGTH,\r
+ 0\r
+ }\r
+ }\r
+ },\r
+ 0, // Instance\r
+ //\r
+ // EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL FwVolBlockInstance\r
+ //\r
+ {\r
+ FvbProtocolGetAttributes,\r
+ FvbProtocolSetAttributes,\r
+ FvbProtocolGetPhysicalAddress,\r
+ FvbProtocolGetBlockSize,\r
+ FvbProtocolRead,\r
+ FvbProtocolWrite,\r
+ FvbProtocolEraseBlocks,\r
+ NULL\r
+ }\r
+};\r
+\r
+UINT32 mInSmmMode = 0;\r
+EFI_SMM_SYSTEM_TABLE2* mSmst = NULL;\r
+\r
+VOID\r
+PublishFlashDeviceInfo (\r
+ IN SPI_INIT_TABLE *Found\r
+ )\r
+/*++\r
+\r
+Routine Description:\r
+\r
+ Publish info on found flash device to other drivers via PcdSpiFlashDeviceSize.\r
+\r
+Arguments:\r
+ Found - Pointer to entry in mSpiInitTable for found flash part.\r
+\r
+Returns:\r
+ None\r
+\r
+--*/\r
+{\r
+ EFI_STATUS Status;\r
+\r
+ //\r
+ // Publish Byte Size of found flash device.\r
+ //\r
+ Status = PcdSet32S (PcdSpiFlashDeviceSize, (UINT32)(Found->BiosStartOffset + Found->BiosSize));\r
+ ASSERT_EFI_ERROR (Status);\r
+}\r
+\r
+VOID\r
+FvbVirtualddressChangeEvent (\r
+ IN EFI_EVENT Event,\r
+ IN VOID *Context\r
+ )\r
+/*++\r
+\r
+Routine Description:\r
+\r
+ Fixup internal data so that EFI and SAL can be call in virtual mode.\r
+ Call the passed in Child Notify event and convert the mFvbModuleGlobal\r
+ date items to there virtual address.\r
+\r
+ mFvbModuleGlobal->FvInstance[FVB_PHYSICAL] - Physical copy of instance data\r
+ mFvbModuleGlobal->FvInstance[FVB_VIRTUAL] - Virtual pointer to common\r
+ instance data.\r
+\r
+Arguments:\r
+\r
+ (Standard EFI notify event - EFI_EVENT_NOTIFY)\r
+\r
+Returns:\r
+\r
+ None\r
+\r
+--*/\r
+{\r
+ EFI_FW_VOL_INSTANCE *FwhInstance;\r
+ UINTN Index;\r
+\r
+ gRT->ConvertPointer (EFI_INTERNAL_POINTER, (VOID **) &mFvbModuleGlobal->FvInstance[FVB_VIRTUAL]);\r
+\r
+ //\r
+ // Convert the base address of all the instances\r
+ //\r
+ Index = 0;\r
+ FwhInstance = mFvbModuleGlobal->FvInstance[FVB_PHYSICAL];\r
+ while (Index < mFvbModuleGlobal->NumFv) {\r
+\r
+ gRT->ConvertPointer (EFI_INTERNAL_POINTER, (VOID **) &FwhInstance->FvBase[FVB_VIRTUAL]);\r
+ //\r
+ // SpiWrite and SpiErase always use Physical Address instead of\r
+ // Virtual Address, even in Runtime. So we need not convert pointer\r
+ // for FvWriteBase[FVB_VIRTUAL]\r
+ //\r
+ // EfiConvertPointer (0, (VOID **) &FwhInstance->FvWriteBase[FVB_VIRTUAL]);\r
+ //\r
+ FwhInstance = (EFI_FW_VOL_INSTANCE *)\r
+ (\r
+ (UINTN) ((UINT8 *) FwhInstance) + FwhInstance->VolumeHeader.HeaderLength +\r
+ (sizeof (EFI_FW_VOL_INSTANCE) - sizeof (EFI_FIRMWARE_VOLUME_HEADER))\r
+ );\r
+ Index++;\r
+ }\r
+\r
+ gRT->ConvertPointer (EFI_INTERNAL_POINTER, (VOID **) &mFvbModuleGlobal->FvbScratchSpace[FVB_VIRTUAL]);\r
+ //\r
+ // Convert SPI_PROTOCOL instance for runtime\r
+ //\r
+ gRT->ConvertPointer (EFI_INTERNAL_POINTER, (VOID **) &mFvbModuleGlobal->SpiProtocol);\r
+ gRT->ConvertPointer (EFI_INTERNAL_POINTER, (VOID **) &mFvbModuleGlobal);\r
+}\r
+\r
+VOID\r
+FvbMemWrite8 (\r
+ IN UINT64 Dest,\r
+ IN UINT8 Byte\r
+ )\r
+{\r
+ MmioWrite8 ((UINTN)Dest, Byte);\r
+\r
+ return ;\r
+}\r
+\r
+EFI_STATUS\r
+GetFvbInstance (\r
+ IN UINTN Instance,\r
+ IN ESAL_FWB_GLOBAL *Global,\r
+ OUT EFI_FW_VOL_INSTANCE **FwhInstance,\r
+ IN BOOLEAN Virtual\r
+ )\r
+/*++\r
+\r
+Routine Description:\r
+ Retrieves the physical address of a memory mapped FV\r
+\r
+Arguments:\r
+ Instance - The FV instance whose base address is going to be\r
+ returned\r
+ Global - Pointer to ESAL_FWB_GLOBAL that contains all\r
+ instance data\r
+ FwhInstance - The EFI_FW_VOL_INSTANCE fimrware instance structure\r
+ Virtual - Whether CPU is in virtual or physical mode\r
+\r
+Returns:\r
+ EFI_SUCCESS - Successfully returns\r
+ EFI_INVALID_PARAMETER - Instance not found\r
+\r
+--*/\r
+{\r
+ EFI_FW_VOL_INSTANCE *FwhRecord;\r
+\r
+ if (Instance >= Global->NumFv) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+ //\r
+ // Find the right instance of the FVB private data\r
+ //\r
+ FwhRecord = Global->FvInstance[Virtual];\r
+ while (Instance > 0) {\r
+ FwhRecord = (EFI_FW_VOL_INSTANCE *)\r
+ (\r
+ (UINTN) ((UINT8 *) FwhRecord) + FwhRecord->VolumeHeader.HeaderLength +\r
+ (sizeof (EFI_FW_VOL_INSTANCE) - sizeof (EFI_FIRMWARE_VOLUME_HEADER))\r
+ );\r
+ Instance--;\r
+ }\r
+\r
+ *FwhInstance = FwhRecord;\r
+\r
+ return EFI_SUCCESS;\r
+}\r
+\r
+EFI_STATUS\r
+FvbGetPhysicalAddress (\r
+ IN UINTN Instance,\r
+ OUT EFI_PHYSICAL_ADDRESS *Address,\r
+ IN ESAL_FWB_GLOBAL *Global,\r
+ IN BOOLEAN Virtual\r
+ )\r
+/*++\r
+\r
+Routine Description:\r
+ Retrieves the physical address of a memory mapped FV\r
+\r
+Arguments:\r
+ Instance - The FV instance whose base address is going to be\r
+ returned\r
+ Address - Pointer to a caller allocated EFI_PHYSICAL_ADDRESS\r
+ that on successful return, contains the base address\r
+ of the firmware volume.\r
+ Global - Pointer to ESAL_FWB_GLOBAL that contains all\r
+ instance data\r
+ Virtual - Whether CPU is in virtual or physical mode\r
+\r
+Returns:\r
+ EFI_SUCCESS - Successfully returns\r
+ EFI_INVALID_PARAMETER - Instance not found\r
+\r
+--*/\r
+{\r
+ EFI_FW_VOL_INSTANCE *FwhInstance;\r
+ EFI_STATUS Status;\r
+\r
+ FwhInstance = NULL;\r
+\r
+ //\r
+ // Find the right instance of the FVB private data\r
+ //\r
+ Status = GetFvbInstance (Instance, Global, &FwhInstance, Virtual);\r
+ ASSERT_EFI_ERROR (Status);\r
+ *Address = FwhInstance->FvBase[Virtual];\r
+\r
+ return EFI_SUCCESS;\r
+}\r
+\r
+EFI_STATUS\r
+FvbGetVolumeAttributes (\r
+ IN UINTN Instance,\r
+ OUT EFI_FVB_ATTRIBUTES_2 *Attributes,\r
+ IN ESAL_FWB_GLOBAL *Global,\r
+ IN BOOLEAN Virtual\r
+ )\r
+/*++\r
+\r
+Routine Description:\r
+ Retrieves attributes, insures positive polarity of attribute bits, returns\r
+ resulting attributes in output parameter\r
+\r
+Arguments:\r
+ Instance - The FV instance whose attributes is going to be\r
+ returned\r
+ Attributes - Output buffer which contains attributes\r
+ Global - Pointer to ESAL_FWB_GLOBAL that contains all\r
+ instance data\r
+ Virtual - Whether CPU is in virtual or physical mode\r
+\r
+Returns:\r
+ EFI_SUCCESS - Successfully returns\r
+ EFI_INVALID_PARAMETER - Instance not found\r
+\r
+--*/\r
+{\r
+ EFI_FW_VOL_INSTANCE *FwhInstance;\r
+ EFI_STATUS Status;\r
+\r
+ FwhInstance = NULL;\r
+\r
+ //\r
+ // Find the right instance of the FVB private data\r
+ //\r
+ Status = GetFvbInstance (Instance, Global, &FwhInstance, Virtual);\r
+ ASSERT_EFI_ERROR (Status);\r
+ *Attributes = FwhInstance->VolumeHeader.Attributes;\r
+\r
+ return EFI_SUCCESS;\r
+}\r
+\r
+EFI_STATUS\r
+FvbGetLbaAddress (\r
+ IN UINTN Instance,\r
+ IN EFI_LBA Lba,\r
+ OUT UINTN *LbaAddress,\r
+ OUT UINTN *LbaWriteAddress,\r
+ OUT UINTN *LbaLength,\r
+ OUT UINTN *NumOfBlocks,\r
+ IN ESAL_FWB_GLOBAL *Global,\r
+ IN BOOLEAN Virtual\r
+ )\r
+/*++\r
+\r
+Routine Description:\r
+ Retrieves the starting address of an LBA in an FV\r
+\r
+Arguments:\r
+ Instance - The FV instance which the Lba belongs to\r
+ Lba - The logical block address\r
+ LbaAddress - On output, contains the physical starting address\r
+ of the Lba\r
+ LbaWriteAddress - On output, contains the physical starting address\r
+ of the Lba for writing\r
+ LbaLength - On output, contains the length of the block\r
+ NumOfBlocks - A pointer to a caller allocated UINTN in which the\r
+ number of consecutive blocks starting with Lba is\r
+ returned. All blocks in this range have a size of\r
+ BlockSize\r
+ Global - Pointer to ESAL_FWB_GLOBAL that contains all\r
+ instance data\r
+ Virtual - Whether CPU is in virtual or physical mode\r
+\r
+Returns:\r
+ EFI_SUCCESS - Successfully returns\r
+ EFI_INVALID_PARAMETER - Instance not found\r
+\r
+--*/\r
+{\r
+ UINT32 NumBlocks;\r
+ UINT32 BlockLength;\r
+ UINTN Offset;\r
+ EFI_LBA StartLba;\r
+ EFI_LBA NextLba;\r
+ EFI_FW_VOL_INSTANCE *FwhInstance;\r
+ EFI_FV_BLOCK_MAP_ENTRY *BlockMap;\r
+ EFI_STATUS Status;\r
+\r
+ FwhInstance = NULL;\r
+\r
+ //\r
+ // Find the right instance of the FVB private data\r
+ //\r
+ Status = GetFvbInstance (Instance, Global, &FwhInstance, Virtual);\r
+ ASSERT_EFI_ERROR (Status);\r
+\r
+ StartLba = 0;\r
+ Offset = 0;\r
+ BlockMap = &(FwhInstance->VolumeHeader.BlockMap[0]);\r
+\r
+ //\r
+ // Parse the blockmap of the FV to find which map entry the Lba belongs to\r
+ //\r
+ while (TRUE) {\r
+ NumBlocks = BlockMap->NumBlocks;\r
+ BlockLength = BlockMap->Length;\r
+\r
+ if ((NumBlocks == 0) || (BlockLength == 0)) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+\r
+ NextLba = StartLba + NumBlocks;\r
+\r
+ //\r
+ // The map entry found\r
+ //\r
+ if (Lba >= StartLba && Lba < NextLba) {\r
+ Offset = Offset + (UINTN) MultU64x32 ((Lba - StartLba), BlockLength);\r
+ if (LbaAddress) {\r
+ *LbaAddress = FwhInstance->FvBase[Virtual] + Offset;\r
+ }\r
+\r
+ if (LbaWriteAddress) {\r
+ *LbaWriteAddress = FwhInstance->FvWriteBase[Virtual] + Offset;\r
+ }\r
+\r
+ if (LbaLength) {\r
+ *LbaLength = BlockLength;\r
+ }\r
+\r
+ if (NumOfBlocks) {\r
+ *NumOfBlocks = (UINTN) (NextLba - Lba);\r
+ }\r
+\r
+ return EFI_SUCCESS;\r
+ }\r
+\r
+ StartLba = NextLba;\r
+ Offset = Offset + NumBlocks * BlockLength;\r
+ BlockMap++;\r
+ }\r
+}\r
+\r
+EFI_STATUS\r
+FvbReadBlock (\r
+ IN UINTN Instance,\r
+ IN EFI_LBA Lba,\r
+ IN UINTN BlockOffset,\r
+ IN OUT UINTN *NumBytes,\r
+ IN UINT8 *Buffer,\r
+ IN ESAL_FWB_GLOBAL *Global,\r
+ IN BOOLEAN Virtual\r
+ )\r
+/*++\r
+\r
+Routine Description:\r
+ Reads specified number of bytes into a buffer from the specified block\r
+\r
+Arguments:\r
+ Instance - The FV instance to be read from\r
+ Lba - The logical block address to be read from\r
+ BlockOffset - Offset into the block at which to begin reading\r
+ NumBytes - Pointer that on input contains the total size of\r
+ the buffer. On output, it contains the total number\r
+ of bytes read\r
+ Buffer - Pointer to a caller allocated buffer that will be\r
+ used to hold the data read\r
+ Global - Pointer to ESAL_FWB_GLOBAL that contains all\r
+ instance data\r
+ Virtual - Whether CPU is in virtual or physical mode\r
+\r
+Returns:\r
+ EFI_SUCCESS - The firmware volume was read successfully and\r
+ contents are in Buffer\r
+ EFI_BAD_BUFFER_SIZE - Read attempted across a LBA boundary. On output,\r
+ NumBytes contains the total number of bytes returned\r
+ in Buffer\r
+ EFI_ACCESS_DENIED - The firmware volume is in the ReadDisabled state\r
+ EFI_DEVICE_ERROR - The block device is not functioning correctly and\r
+ could not be read\r
+ EFI_INVALID_PARAMETER - Instance not found, or NumBytes, Buffer are NULL\r
+\r
+--*/\r
+{\r
+ EFI_FVB_ATTRIBUTES_2 Attributes;\r
+ UINTN LbaAddress;\r
+ UINTN LbaLength;\r
+ EFI_STATUS Status;\r
+\r
+ //\r
+ // Check for invalid conditions\r
+ //\r
+ if ((NumBytes == NULL) || (Buffer == NULL)) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+\r
+ if (*NumBytes == 0) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+\r
+ Status = FvbGetLbaAddress (Instance, Lba, &LbaAddress, NULL, &LbaLength, NULL, Global, Virtual);\r
+ if (EFI_ERROR (Status)) {\r
+ return Status;\r
+ }\r
+ //\r
+ // Check if the FV is read enabled\r
+ //\r
+ FvbGetVolumeAttributes (Instance, &Attributes, Global, Virtual);\r
+\r
+ if ((Attributes & EFI_FVB2_READ_STATUS) == 0) {\r
+ return EFI_ACCESS_DENIED;\r
+ }\r
+ //\r
+ // Perform boundary checks and adjust NumBytes\r
+ //\r
+ if (BlockOffset > LbaLength) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+\r
+ if (LbaLength < (*NumBytes + BlockOffset)) {\r
+ *NumBytes = (UINT32) (LbaLength - BlockOffset);\r
+ Status = EFI_BAD_BUFFER_SIZE;\r
+ }\r
+\r
+ MmioReadBuffer8 (LbaAddress + BlockOffset, (UINTN) *NumBytes, Buffer);\r
+\r
+ return Status;\r
+}\r
+\r
+EFI_STATUS\r
+FlashFdWrite (\r
+ IN UINTN WriteAddress,\r
+ IN UINTN Address,\r
+ IN OUT UINTN *NumBytes,\r
+ IN UINT8 *Buffer,\r
+ IN UINTN LbaLength\r
+ )\r
+/*++\r
+\r
+Routine Description:\r
+ Writes specified number of bytes from the input buffer to the address\r
+\r
+Arguments:\r
+\r
+Returns:\r
+\r
+--*/\r
+{\r
+ EFI_STATUS Status;\r
+\r
+ Status = EFI_SUCCESS;\r
+\r
+ //\r
+ // TODO: Suggested that this code be "critical section"\r
+ //\r
+ WriteAddress -= ( PcdGet32 (PcdFlashAreaBaseAddress) );\r
+ if (mInSmmMode == 0) { // !(EfiInManagementInterrupt ())) {\r
+ Status = mFvbModuleGlobal->SpiProtocol->Execute (\r
+ mFvbModuleGlobal->SpiProtocol,\r
+ SPI_OPCODE_WRITE_INDEX, // OpcodeIndex\r
+ 0, // PrefixOpcodeIndex\r
+ TRUE, // DataCycle\r
+ TRUE, // Atomic\r
+ TRUE, // ShiftOut\r
+ WriteAddress, // Address\r
+ (UINT32) (*NumBytes), // Data Number\r
+ Buffer,\r
+ EnumSpiRegionBios\r
+ );\r
+\r
+ } else {\r
+ Status = mFvbModuleGlobal->SmmSpiProtocol->Execute (\r
+ mFvbModuleGlobal->SmmSpiProtocol,\r
+ SPI_OPCODE_WRITE_INDEX, // OpcodeIndex\r
+ 0, // PrefixOpcodeIndex\r
+ TRUE, // DataCycle\r
+ TRUE, // Atomic\r
+ TRUE, // ShiftOut\r
+ WriteAddress, // Address\r
+ (UINT32) (*NumBytes), // Data Number\r
+ Buffer,\r
+ EnumSpiRegionBios\r
+ );\r
+ }\r
+\r
+ AsmWbinvd ();\r
+\r
+ return Status;\r
+}\r
+\r
+EFI_STATUS\r
+FlashFdErase (\r
+ IN UINTN WriteAddress,\r
+ IN UINTN Address,\r
+ IN UINTN LbaLength\r
+ )\r
+/*++\r
+\r
+Routine Description:\r
+ Erase a certain block from address LbaWriteAddress\r
+\r
+Arguments:\r
+\r
+Returns:\r
+\r
+--*/\r
+{\r
+ EFI_STATUS Status;\r
+ UINTN NumBytes;\r
+\r
+ NumBytes = LbaLength;\r
+\r
+ WriteAddress -= (PcdGet32 (PcdFlashAreaBaseAddress));\r
+ if (mInSmmMode == 0 ) { // !(EfiInManagementInterrupt ())) {\r
+ Status = mFvbModuleGlobal->SpiProtocol->Execute (\r
+ mFvbModuleGlobal->SpiProtocol,\r
+ SPI_OPCODE_ERASE_INDEX, // OpcodeIndex\r
+ 0, // PrefixOpcodeIndex\r
+ FALSE, // DataCycle\r
+ TRUE, // Atomic\r
+ FALSE, // ShiftOut\r
+ WriteAddress, // Address\r
+ 0, // Data Number\r
+ NULL,\r
+ EnumSpiRegionBios // SPI_REGION_TYPE\r
+ );\r
+ } else {\r
+ Status = mFvbModuleGlobal->SmmSpiProtocol->Execute (\r
+ mFvbModuleGlobal->SmmSpiProtocol,\r
+ SPI_OPCODE_ERASE_INDEX, // OpcodeIndex\r
+ 0, // PrefixOpcodeIndex\r
+ FALSE, // DataCycle\r
+ TRUE, // Atomic\r
+ FALSE, // ShiftOut\r
+ WriteAddress, // Address\r
+ 0, // Data Number\r
+ NULL,\r
+ EnumSpiRegionBios // SPI_REGION_TYPE\r
+ );\r
+ }\r
+\r
+ AsmWbinvd ();\r
+\r
+ return Status;\r
+}\r
+\r
+EFI_STATUS\r
+FvbWriteBlock (\r
+ IN UINTN Instance,\r
+ IN EFI_LBA Lba,\r
+ IN UINTN BlockOffset,\r
+ IN OUT UINTN *NumBytes,\r
+ IN UINT8 *Buffer,\r
+ IN ESAL_FWB_GLOBAL *Global,\r
+ IN BOOLEAN Virtual\r
+ )\r
+/*++\r
+\r
+Routine Description:\r
+ Writes specified number of bytes from the input buffer to the block\r
+\r
+Arguments:\r
+ Instance - The FV instance to be written to\r
+ Lba - The starting logical block index to write to\r
+ BlockOffset - Offset into the block at which to begin writing\r
+ NumBytes - Pointer that on input contains the total size of\r
+ the buffer. On output, it contains the total number\r
+ of bytes actually written\r
+ Buffer - Pointer to a caller allocated buffer that contains\r
+ the source for the write\r
+ Global - Pointer to ESAL_FWB_GLOBAL that contains all\r
+ instance data\r
+ Virtual - Whether CPU is in virtual or physical mode\r
+\r
+Returns:\r
+ EFI_SUCCESS - The firmware volume was written successfully\r
+ EFI_BAD_BUFFER_SIZE - Write attempted across a LBA boundary. On output,\r
+ NumBytes contains the total number of bytes\r
+ actually written\r
+ EFI_ACCESS_DENIED - The firmware volume is in the WriteDisabled state\r
+ EFI_DEVICE_ERROR - The block device is not functioning correctly and\r
+ could not be written\r
+ EFI_INVALID_PARAMETER - Instance not found, or NumBytes, Buffer are NULL\r
+\r
+--*/\r
+{\r
+ EFI_FVB_ATTRIBUTES_2 Attributes;\r
+ UINTN LbaAddress;\r
+ UINTN LbaWriteAddress;\r
+ UINTN LbaLength;\r
+ EFI_FW_VOL_INSTANCE *FwhInstance;\r
+ EFI_STATUS Status;\r
+ EFI_STATUS ReturnStatus;\r
+\r
+ FwhInstance = NULL;\r
+\r
+ //\r
+ // Find the right instance of the FVB private data\r
+ //\r
+ Status = GetFvbInstance (Instance, Global, &FwhInstance, Virtual);\r
+ ASSERT_EFI_ERROR (Status);\r
+\r
+ //\r
+ // Writes are enabled in the init routine itself\r
+ //\r
+ if (!FwhInstance->WriteEnabled) {\r
+ return EFI_ACCESS_DENIED;\r
+ }\r
+ //\r
+ // Check for invalid conditions\r
+ //\r
+ if ((NumBytes == NULL) || (Buffer == NULL)) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+\r
+ if (*NumBytes == 0) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+\r
+ Status = FvbGetLbaAddress (Instance, Lba, &LbaAddress, &LbaWriteAddress, &LbaLength, NULL, Global, Virtual);\r
+ if (EFI_ERROR (Status)) {\r
+ return Status;\r
+ }\r
+ //\r
+ // Check if the FV is write enabled\r
+ //\r
+ FvbGetVolumeAttributes (Instance, &Attributes, Global, Virtual);\r
+\r
+ if ((Attributes & EFI_FVB2_WRITE_STATUS) == 0) {\r
+ return EFI_ACCESS_DENIED;\r
+ }\r
+ //\r
+ // Perform boundary checks and adjust NumBytes\r
+ //\r
+ if (BlockOffset > LbaLength) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+\r
+ if (LbaLength < (*NumBytes + BlockOffset)) {\r
+ *NumBytes = (UINT32) (LbaLength - BlockOffset);\r
+ Status = EFI_BAD_BUFFER_SIZE;\r
+ }\r
+\r
+ ReturnStatus = FlashFdWrite (\r
+ LbaWriteAddress + BlockOffset,\r
+ LbaAddress,\r
+ NumBytes,\r
+ Buffer,\r
+ LbaLength\r
+ );\r
+ if (EFI_ERROR (ReturnStatus)) {\r
+ return ReturnStatus;\r
+ }\r
+\r
+ return Status;\r
+}\r
+\r
+EFI_STATUS\r
+FvbEraseBlock (\r
+ IN UINTN Instance,\r
+ IN EFI_LBA Lba,\r
+ IN ESAL_FWB_GLOBAL *Global,\r
+ IN BOOLEAN Virtual\r
+ )\r
+/*++\r
+\r
+Routine Description:\r
+ Erases and initializes a firmware volume block\r
+\r
+Arguments:\r
+ Instance - The FV instance to be erased\r
+ Lba - The logical block index to be erased\r
+ Global - Pointer to ESAL_FWB_GLOBAL that contains all\r
+ instance data\r
+ Virtual - Whether CPU is in virtual or physical mode\r
+\r
+Returns:\r
+ EFI_SUCCESS - The erase request was successfully completed\r
+ EFI_ACCESS_DENIED - The firmware volume is in the WriteDisabled state\r
+ EFI_DEVICE_ERROR - The block device is not functioning correctly and\r
+ could not be written. Firmware device may have been\r
+ partially erased\r
+ EFI_INVALID_PARAMETER - Instance not found\r
+\r
+--*/\r
+{\r
+\r
+ EFI_FVB_ATTRIBUTES_2 Attributes;\r
+ UINTN LbaAddress;\r
+ UINTN LbaWriteAddress;\r
+ EFI_FW_VOL_INSTANCE *FwhInstance;\r
+ UINTN LbaLength;\r
+ EFI_STATUS Status;\r
+ UINTN SectorNum;\r
+ UINTN Index;\r
+\r
+ FwhInstance = NULL;\r
+\r
+ //\r
+ // Find the right instance of the FVB private data\r
+ //\r
+ Status = GetFvbInstance (Instance, Global, &FwhInstance, Virtual);\r
+ ASSERT_EFI_ERROR (Status);\r
+\r
+ //\r
+ // Writes are enabled in the init routine itself\r
+ //\r
+ if (!FwhInstance->WriteEnabled) {\r
+ return EFI_ACCESS_DENIED;\r
+ }\r
+ //\r
+ // Check if the FV is write enabled\r
+ //\r
+ FvbGetVolumeAttributes (Instance, &Attributes, Global, Virtual);\r
+\r
+ if ((Attributes & EFI_FVB2_WRITE_STATUS) == 0) {\r
+ return EFI_ACCESS_DENIED;\r
+ }\r
+ //\r
+ // Get the starting address of the block for erase. For debug reasons,\r
+ // LbaWriteAddress may not be the same as LbaAddress.\r
+ //\r
+ Status = FvbGetLbaAddress (Instance, Lba, &LbaAddress, &LbaWriteAddress, &LbaLength, NULL, Global, Virtual);\r
+ if (EFI_ERROR (Status)) {\r
+ return Status;\r
+ }\r
+\r
+ SectorNum = LbaLength / SPI_ERASE_SECTOR_SIZE;\r
+ for (Index = 0; Index < SectorNum; Index++){\r
+ Status = FlashFdErase (\r
+ LbaWriteAddress + Index * SPI_ERASE_SECTOR_SIZE,\r
+ LbaAddress,\r
+ SPI_ERASE_SECTOR_SIZE\r
+ );\r
+ if (Status != EFI_SUCCESS){\r
+ break;\r
+ }\r
+ }\r
+\r
+ return Status;\r
+}\r
+\r
+EFI_STATUS\r
+FvbEraseCustomBlockRange (\r
+ IN UINTN Instance,\r
+ IN EFI_LBA StartLba,\r
+ IN UINTN OffsetStartLba,\r
+ IN EFI_LBA LastLba,\r
+ IN UINTN OffsetLastLba,\r
+ IN ESAL_FWB_GLOBAL *Global,\r
+ IN BOOLEAN Virtual\r
+ )\r
+/*++\r
+\r
+Routine Description:\r
+ Erases and initializes a specified range of a firmware volume\r
+\r
+Arguments:\r
+ Instance - The FV instance to be erased\r
+ StartLba - The starting logical block index to be erased\r
+ OffsetStartLba - Offset into the starting block at which to\r
+ begin erasing\r
+ LastLba - The last logical block index to be erased\r
+ OffsetStartLba - Offset into the last block at which to end erasing\r
+ Global - Pointer to ESAL_FWB_GLOBAL that contains all\r
+ instance data\r
+ Virtual - Whether CPU is in virtual or physical mode\r
+\r
+Returns:\r
+ EFI_SUCCESS - The firmware volume was erased successfully\r
+ EFI_ACCESS_DENIED - The firmware volume is in the WriteDisabled state\r
+ EFI_DEVICE_ERROR - The block device is not functioning correctly and\r
+ could not be written. Firmware device may have been\r
+ partially erased\r
+ EFI_INVALID_PARAMETER - Instance not found\r
+\r
+--*/\r
+{\r
+ EFI_LBA Index;\r
+ UINTN LbaSize;\r
+ UINTN ScratchLbaSizeData;\r
+\r
+ //\r
+ // First LBA.\r
+ //\r
+ FvbGetLbaAddress (Instance, StartLba, NULL, NULL, &LbaSize, NULL, Global, Virtual);\r
+\r
+ //\r
+ // Use the scratch space as the intermediate buffer to transfer data\r
+ // Back up the first LBA in scratch space.\r
+ //\r
+ FvbReadBlock (Instance, StartLba, 0, &LbaSize, Global->FvbScratchSpace[Virtual], Global, Virtual);\r
+\r
+ //\r
+ // erase now\r
+ //\r
+ FvbEraseBlock (Instance, StartLba, Global, Virtual);\r
+ ScratchLbaSizeData = OffsetStartLba;\r
+\r
+ //\r
+ // write the data back to the first block\r
+ //\r
+ if (ScratchLbaSizeData > 0) {\r
+ FvbWriteBlock (Instance, StartLba, 0, &ScratchLbaSizeData, Global->FvbScratchSpace[Virtual], Global, Virtual);\r
+ }\r
+ //\r
+ // Middle LBAs\r
+ //\r
+ if (LastLba > (StartLba + 1)) {\r
+ for (Index = (StartLba + 1); Index <= (LastLba - 1); Index++) {\r
+ FvbEraseBlock (Instance, Index, Global, Virtual);\r
+ }\r
+ }\r
+ //\r
+ // Last LBAs, the same as first LBAs\r
+ //\r
+ if (LastLba > StartLba) {\r
+ FvbGetLbaAddress (Instance, LastLba, NULL, NULL, &LbaSize, NULL, Global, Virtual);\r
+ FvbReadBlock (Instance, LastLba, 0, &LbaSize, Global->FvbScratchSpace[Virtual], Global, Virtual);\r
+ FvbEraseBlock (Instance, LastLba, Global, Virtual);\r
+ }\r
+\r
+ ScratchLbaSizeData = LbaSize - (OffsetStartLba + 1);\r
+\r
+ return FvbWriteBlock (\r
+ Instance,\r
+ LastLba,\r
+ (OffsetLastLba + 1),\r
+ &ScratchLbaSizeData,\r
+ Global->FvbScratchSpace[Virtual],\r
+ Global,\r
+ Virtual\r
+ );\r
+}\r
+\r
+EFI_STATUS\r
+FvbSetVolumeAttributes (\r
+ IN UINTN Instance,\r
+ IN OUT EFI_FVB_ATTRIBUTES_2 *Attributes,\r
+ IN ESAL_FWB_GLOBAL *Global,\r
+ IN BOOLEAN Virtual\r
+ )\r
+/*++\r
+\r
+Routine Description:\r
+ Modifies the current settings of the firmware volume according to the\r
+ input parameter, and returns the new setting of the volume\r
+\r
+Arguments:\r
+ Instance - The FV instance whose attributes is going to be\r
+ modified\r
+ Attributes - On input, it is a pointer to EFI_FVB_ATTRIBUTES_2\r
+ containing the desired firmware volume settings.\r
+ On successful return, it contains the new settings\r
+ of the firmware volume\r
+ Global - Pointer to ESAL_FWB_GLOBAL that contains all\r
+ instance data\r
+ Virtual - Whether CPU is in virtual or physical mode\r
+\r
+Returns:\r
+ EFI_SUCCESS - Successfully returns\r
+ EFI_ACCESS_DENIED - The volume setting is locked and cannot be modified\r
+ EFI_INVALID_PARAMETER - Instance not found, or The attributes requested are\r
+ in conflict with the capabilities as declared in the\r
+ firmware volume header\r
+\r
+--*/\r
+{\r
+ EFI_FW_VOL_INSTANCE *FwhInstance;\r
+ EFI_FVB_ATTRIBUTES_2 OldAttributes;\r
+ EFI_FVB_ATTRIBUTES_2 *AttribPtr;\r
+ UINT32 Capabilities;\r
+ UINT32 OldStatus;\r
+ UINT32 NewStatus;\r
+ EFI_STATUS Status;\r
+\r
+ FwhInstance = NULL;\r
+\r
+ //\r
+ // Find the right instance of the FVB private data\r
+ //\r
+ Status = GetFvbInstance (Instance, Global, &FwhInstance, Virtual);\r
+ ASSERT_EFI_ERROR (Status);\r
+\r
+ AttribPtr = (EFI_FVB_ATTRIBUTES_2 *) &(FwhInstance->VolumeHeader.Attributes);\r
+ OldAttributes = *AttribPtr;\r
+ Capabilities = OldAttributes & EFI_FVB2_CAPABILITIES;\r
+ OldStatus = OldAttributes & EFI_FVB2_STATUS;\r
+ NewStatus = *Attributes & EFI_FVB2_STATUS;\r
+\r
+ //\r
+ // If firmware volume is locked, no status bit can be updated\r
+ //\r
+ if (OldAttributes & EFI_FVB2_LOCK_STATUS) {\r
+ if (OldStatus ^ NewStatus) {\r
+ return EFI_ACCESS_DENIED;\r
+ }\r
+ }\r
+ //\r
+ // Test read disable\r
+ //\r
+ if ((Capabilities & EFI_FVB2_READ_DISABLED_CAP) == 0) {\r
+ if ((NewStatus & EFI_FVB2_READ_STATUS) == 0) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+ }\r
+ //\r
+ // Test read enable\r
+ //\r
+ if ((Capabilities & EFI_FVB2_READ_ENABLED_CAP) == 0) {\r
+ if (NewStatus & EFI_FVB2_READ_STATUS) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+ }\r
+ //\r
+ // Test write disable\r
+ //\r
+ if ((Capabilities & EFI_FVB2_WRITE_DISABLED_CAP) == 0) {\r
+ if ((NewStatus & EFI_FVB2_WRITE_STATUS) == 0) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+ }\r
+ //\r
+ // Test write enable\r
+ //\r
+ if ((Capabilities & EFI_FVB2_WRITE_ENABLED_CAP) == 0) {\r
+ if (NewStatus & EFI_FVB2_WRITE_STATUS) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+ }\r
+ //\r
+ // Test lock\r
+ //\r
+ if ((Capabilities & EFI_FVB2_LOCK_CAP) == 0) {\r
+ if (NewStatus & EFI_FVB2_LOCK_STATUS) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+ }\r
+\r
+ *AttribPtr = (*AttribPtr) & (0xFFFFFFFF & (~EFI_FVB2_STATUS));\r
+ *AttribPtr = (*AttribPtr) | NewStatus;\r
+ *Attributes = *AttribPtr;\r
+\r
+ return EFI_SUCCESS;\r
+}\r
+//\r
+// FVB protocol APIs\r
+//\r
+EFI_STATUS\r
+EFIAPI\r
+FvbProtocolGetPhysicalAddress (\r
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL *This,\r
+ OUT EFI_PHYSICAL_ADDRESS *Address\r
+ )\r
+/*++\r
+\r
+Routine Description:\r
+\r
+ Retrieves the physical address of the device.\r
+\r
+Arguments:\r
+\r
+ This - Calling context\r
+ Address - Output buffer containing the address.\r
+\r
+Returns:\r
+\r
+Returns:\r
+ EFI_SUCCESS - Successfully returns\r
+\r
+--*/\r
+{\r
+ EFI_FW_VOL_BLOCK_DEVICE *FvbDevice;\r
+\r
+ FvbDevice = FVB_DEVICE_FROM_THIS (This);\r
+\r
+ return FvbGetPhysicalAddress (FvbDevice->Instance, Address, mFvbModuleGlobal, EfiGoneVirtual ());\r
+}\r
+\r
+EFI_STATUS\r
+FvbProtocolGetBlockSize (\r
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL *This,\r
+ IN EFI_LBA Lba,\r
+ OUT UINTN *BlockSize,\r
+ OUT UINTN *NumOfBlocks\r
+ )\r
+/*++\r
+\r
+Routine Description:\r
+ Retrieve the size of a logical block\r
+\r
+Arguments:\r
+ This - Calling context\r
+ Lba - Indicates which block to return the size for.\r
+ BlockSize - A pointer to a caller allocated UINTN in which\r
+ the size of the block is returned\r
+ NumOfBlocks - a pointer to a caller allocated UINTN in which the\r
+ number of consecutive blocks starting with Lba is\r
+ returned. All blocks in this range have a size of\r
+ BlockSize\r
+\r
+Returns:\r
+ EFI_SUCCESS - The firmware volume was read successfully and\r
+ contents are in Buffer\r
+\r
+--*/\r
+{\r
+ EFI_FW_VOL_BLOCK_DEVICE *FvbDevice;\r
+\r
+ FvbDevice = FVB_DEVICE_FROM_THIS (This);\r
+\r
+ return FvbGetLbaAddress (\r
+ FvbDevice->Instance,\r
+ Lba,\r
+ NULL,\r
+ NULL,\r
+ BlockSize,\r
+ NumOfBlocks,\r
+ mFvbModuleGlobal,\r
+ EfiGoneVirtual ()\r
+ );\r
+}\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+FvbProtocolGetAttributes (\r
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL *This,\r
+ OUT EFI_FVB_ATTRIBUTES_2 *Attributes\r
+ )\r
+/*++\r
+\r
+Routine Description:\r
+ Retrieves Volume attributes. No polarity translations are done.\r
+\r
+Arguments:\r
+ This - Calling context\r
+ Attributes - output buffer which contains attributes\r
+\r
+Returns:\r
+ EFI_SUCCESS - Successfully returns\r
+\r
+--*/\r
+{\r
+ EFI_FW_VOL_BLOCK_DEVICE *FvbDevice;\r
+\r
+ FvbDevice = FVB_DEVICE_FROM_THIS (This);\r
+\r
+ return FvbGetVolumeAttributes (FvbDevice->Instance, Attributes, mFvbModuleGlobal, EfiGoneVirtual ());\r
+}\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+FvbProtocolSetAttributes (\r
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL *This,\r
+ IN OUT EFI_FVB_ATTRIBUTES_2 *Attributes\r
+ )\r
+/*++\r
+\r
+Routine Description:\r
+ Sets Volume attributes. No polarity translations are done.\r
+\r
+Arguments:\r
+ This - Calling context\r
+ Attributes - output buffer which contains attributes\r
+\r
+Returns:\r
+ EFI_SUCCESS - Successfully returns\r
+\r
+--*/\r
+{\r
+ EFI_FW_VOL_BLOCK_DEVICE *FvbDevice;\r
+\r
+ FvbDevice = FVB_DEVICE_FROM_THIS (This);\r
+\r
+ return FvbSetVolumeAttributes (FvbDevice->Instance, Attributes, mFvbModuleGlobal, EfiGoneVirtual ());\r
+}\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+FvbProtocolEraseBlocks (\r
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL *This,\r
+ ...\r
+ )\r
+/*++\r
+\r
+Routine Description:\r
+\r
+ The EraseBlock() function erases one or more blocks as denoted by the\r
+ variable argument list. The entire parameter list of blocks must be verified\r
+ prior to erasing any blocks. If a block is requested that does not exist\r
+ within the associated firmware volume (it has a larger index than the last\r
+ block of the firmware volume), the EraseBlock() function must return\r
+ EFI_INVALID_PARAMETER without modifying the contents of the firmware volume.\r
+\r
+Arguments:\r
+ This - Calling context\r
+ ... - Starting LBA followed by Number of Lba to erase.\r
+ a -1 to terminate the list.\r
+\r
+Returns:\r
+ EFI_SUCCESS - The erase request was successfully completed\r
+ EFI_ACCESS_DENIED - The firmware volume is in the WriteDisabled state\r
+ EFI_DEVICE_ERROR - The block device is not functioning correctly and\r
+ could not be written. Firmware device may have been\r
+ partially erased\r
+\r
+--*/\r
+{\r
+ EFI_FW_VOL_BLOCK_DEVICE *FvbDevice;\r
+ EFI_FW_VOL_INSTANCE *FwhInstance;\r
+ UINTN NumOfBlocks;\r
+ VA_LIST args;\r
+ EFI_LBA StartingLba;\r
+ UINTN NumOfLba;\r
+ EFI_STATUS Status;\r
+\r
+ FwhInstance = NULL;\r
+ FvbDevice = FVB_DEVICE_FROM_THIS (This);\r
+\r
+ Status = GetFvbInstance (FvbDevice->Instance, mFvbModuleGlobal, &FwhInstance, EfiGoneVirtual ());\r
+ ASSERT_EFI_ERROR (Status);\r
+\r
+ NumOfBlocks = FwhInstance->NumOfBlocks;\r
+\r
+ VA_START (args, This);\r
+\r
+ do {\r
+ StartingLba = VA_ARG (args, EFI_LBA);\r
+ if (StartingLba == EFI_LBA_LIST_TERMINATOR) {\r
+ break;\r
+ }\r
+\r
+ NumOfLba = VA_ARG (args, UINT32);\r
+\r
+ //\r
+ // Check input parameters\r
+ //\r
+ if (NumOfLba == 0) {\r
+ VA_END (args);\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+\r
+ if ((StartingLba + NumOfLba) > NumOfBlocks) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+ } while (TRUE);\r
+\r
+ VA_END (args);\r
+\r
+ VA_START (args, This);\r
+ do {\r
+ StartingLba = VA_ARG (args, EFI_LBA);\r
+ if (StartingLba == EFI_LBA_LIST_TERMINATOR) {\r
+ break;\r
+ }\r
+\r
+ NumOfLba = VA_ARG (args, UINT32);\r
+\r
+ while (NumOfLba > 0) {\r
+ Status = FvbEraseBlock (FvbDevice->Instance, StartingLba, mFvbModuleGlobal, EfiGoneVirtual ());\r
+ if (EFI_ERROR (Status)) {\r
+ VA_END (args);\r
+ return Status;\r
+ }\r
+\r
+ StartingLba++;\r
+ NumOfLba--;\r
+ }\r
+\r
+ } while (TRUE);\r
+\r
+ VA_END (args);\r
+\r
+ return EFI_SUCCESS;\r
+}\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+FvbProtocolWrite (\r
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL *This,\r
+ IN EFI_LBA Lba,\r
+ IN UINTN Offset,\r
+ IN OUT UINTN *NumBytes,\r
+ IN UINT8 *Buffer\r
+ )\r
+/*++\r
+\r
+Routine Description:\r
+\r
+ Writes data beginning at Lba:Offset from FV. The write terminates either\r
+ when *NumBytes of data have been written, or when a block boundary is\r
+ reached. *NumBytes is updated to reflect the actual number of bytes\r
+ written. The write opertion does not include erase. This routine will\r
+ attempt to write only the specified bytes. If the writes do not stick,\r
+ it will return an error.\r
+\r
+Arguments:\r
+ This - Calling context\r
+ Lba - Block in which to begin write\r
+ Offset - Offset in the block at which to begin write\r
+ NumBytes - On input, indicates the requested write size. On\r
+ output, indicates the actual number of bytes written\r
+ Buffer - Buffer containing source data for the write.\r
+\r
+Returns:\r
+ EFI_SUCCESS - The firmware volume was written successfully\r
+ EFI_BAD_BUFFER_SIZE - Write attempted across a LBA boundary. On output,\r
+ NumBytes contains the total number of bytes\r
+ actually written\r
+ EFI_ACCESS_DENIED - The firmware volume is in the WriteDisabled state\r
+ EFI_DEVICE_ERROR - The block device is not functioning correctly and\r
+ could not be written\r
+ EFI_INVALID_PARAMETER - NumBytes or Buffer are NULL\r
+\r
+--*/\r
+{\r
+\r
+ EFI_FW_VOL_BLOCK_DEVICE *FvbDevice;\r
+\r
+ FvbDevice = FVB_DEVICE_FROM_THIS (This);\r
+\r
+ return FvbWriteBlock (FvbDevice->Instance, Lba, Offset, NumBytes, Buffer, mFvbModuleGlobal, EfiGoneVirtual ());\r
+}\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+FvbProtocolRead (\r
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL *This,\r
+ IN EFI_LBA Lba,\r
+ IN UINTN Offset,\r
+ IN OUT UINTN *NumBytes,\r
+ IN UINT8 *Buffer\r
+ )\r
+/*++\r
+\r
+Routine Description:\r
+\r
+ Reads data beginning at Lba:Offset from FV. The Read terminates either\r
+ when *NumBytes of data have been read, or when a block boundary is\r
+ reached. *NumBytes is updated to reflect the actual number of bytes\r
+ written. The write opertion does not include erase. This routine will\r
+ attempt to write only the specified bytes. If the writes do not stick,\r
+ it will return an error.\r
+\r
+Arguments:\r
+ This - Calling context\r
+ Lba - Block in which to begin Read\r
+ Offset - Offset in the block at which to begin Read\r
+ NumBytes - On input, indicates the requested write size. On\r
+ output, indicates the actual number of bytes Read\r
+ Buffer - Buffer containing source data for the Read.\r
+\r
+Returns:\r
+ EFI_SUCCESS - The firmware volume was read successfully and\r
+ contents are in Buffer\r
+ EFI_BAD_BUFFER_SIZE - Read attempted across a LBA boundary. On output,\r
+ NumBytes contains the total number of bytes returned\r
+ in Buffer\r
+ EFI_ACCESS_DENIED - The firmware volume is in the ReadDisabled state\r
+ EFI_DEVICE_ERROR - The block device is not functioning correctly and\r
+ could not be read\r
+ EFI_INVALID_PARAMETER - NumBytes or Buffer are NULL\r
+\r
+--*/\r
+{\r
+\r
+ EFI_FW_VOL_BLOCK_DEVICE *FvbDevice;\r
+ EFI_STATUS Status;\r
+\r
+ FvbDevice = FVB_DEVICE_FROM_THIS (This);\r
+ Status = FvbReadBlock (FvbDevice->Instance, Lba, Offset, NumBytes, Buffer, mFvbModuleGlobal, EfiGoneVirtual ());\r
+\r
+ return Status;\r
+}\r
+\r
+EFI_STATUS\r
+ValidateFvHeader (\r
+ EFI_FIRMWARE_VOLUME_HEADER *FwVolHeader\r
+ )\r
+/*++\r
+\r
+Routine Description:\r
+ Check the integrity of firmware volume header\r
+\r
+Arguments:\r
+ FwVolHeader - A pointer to a firmware volume header\r
+\r
+Returns:\r
+ EFI_SUCCESS - The firmware volume is consistent\r
+ EFI_NOT_FOUND - The firmware volume has corrupted. So it is not an FV\r
+\r
+--*/\r
+{\r
+ UINT16 *Ptr;\r
+ UINT16 HeaderLength;\r
+ UINT16 Checksum;\r
+\r
+ //\r
+ // Verify the header revision, header signature, length\r
+ // Length of FvBlock cannot be 2**64-1\r
+ // HeaderLength cannot be an odd number\r
+ //\r
+ #ifndef R864_BUILD\r
+ if (((FwVolHeader->Revision != EFI_FVH_REVISION) && (FwVolHeader->Revision != EFI_FVH_REVISION)) ||\r
+ #else\r
+ if ((FwVolHeader->Revision != EFI_FVH_REVISION) ||\r
+ #endif\r
+ (FwVolHeader->Signature != EFI_FVH_SIGNATURE) ||\r
+ (FwVolHeader->FvLength == ((UINTN) -1)) ||\r
+ ((FwVolHeader->HeaderLength & 0x01) != 0)\r
+ ) {\r
+ return EFI_NOT_FOUND;\r
+ }\r
+ //\r
+ // Verify the header checksum\r
+ //\r
+ HeaderLength = (UINT16) (FwVolHeader->HeaderLength / 2);\r
+ Ptr = (UINT16 *) FwVolHeader;\r
+ Checksum = 0;\r
+ while (HeaderLength > 0) {\r
+ Checksum = Checksum + (*Ptr);\r
+ Ptr++;\r
+ HeaderLength--;\r
+ }\r
+\r
+ if (Checksum != 0) {\r
+ return EFI_NOT_FOUND;\r
+ }\r
+\r
+ return EFI_SUCCESS;\r
+}\r
+\r
+EFI_STATUS\r
+GetFvbHeader (\r
+ VOID **HobList,\r
+ OUT EFI_FIRMWARE_VOLUME_HEADER **FwVolHeader,\r
+ OUT EFI_PHYSICAL_ADDRESS *BaseAddress,\r
+ OUT BOOLEAN *WriteBack\r
+ )\r
+{\r
+ EFI_STATUS Status;\r
+\r
+ Status = EFI_SUCCESS;\r
+ *WriteBack = FALSE;\r
+\r
+ if (*FwVolHeader == NULL) {\r
+ *BaseAddress = PcdGet32 (PcdFlashFvRecoveryBase);\r
+ } else if (*FwVolHeader == (VOID *)(UINTN)PcdGet32 (PcdFlashFvRecoveryBase)) {\r
+ *BaseAddress = PcdGet32 (PcdFlashFvMainBase);\r
+ } else if (*FwVolHeader == (VOID *)(UINTN)PcdGet32 (PcdFlashFvMainBase)) {\r
+ *BaseAddress = PcdGet32 (PcdFlashNvStorageVariableBase);\r
+ } else {\r
+ return EFI_NOT_FOUND;\r
+ }\r
+\r
+ DEBUG((EFI_D_INFO, "Fvb base : %08x\n",*BaseAddress));\r
+\r
+ *FwVolHeader = (EFI_FIRMWARE_VOLUME_HEADER *) (UINTN) (*BaseAddress);\r
+ Status = ValidateFvHeader (*FwVolHeader);\r
+ if (EFI_ERROR (Status)) {\r
+ //\r
+ // Get FvbInfo\r
+ //\r
+ *WriteBack = TRUE;\r
+\r
+ Status = GetFvbInfo (*BaseAddress, FwVolHeader);\r
+ DEBUG(( DEBUG_ERROR, "Through GetFvbInfo: %08x!\n",*BaseAddress));\r
+\r
+ ASSERT_EFI_ERROR (Status);\r
+ }\r
+\r
+ return EFI_SUCCESS;\r
+}\r
+\r
+\r
+EFI_STATUS\r
+SmmSpiInit (\r
+ VOID\r
+ )\r
+{\r
+ UINT8 SpiStatus;\r
+ UINT8 FlashIndex;\r
+ UINT8 FlashID[3];\r
+ EFI_STATUS Status;\r
+\r
+ //\r
+ // Obtain a handle for ICH SPI Protocol\r
+ //\r
+ ASSERT(mSmst != NULL);\r
+ if (mFvbModuleGlobal->SmmSpiProtocol == NULL){\r
+ Status = mSmst->SmmLocateProtocol (&gEfiSmmSpiProtocolGuid, NULL, (VOID **) &mFvbModuleGlobal->SmmSpiProtocol);\r
+ ASSERT_EFI_ERROR(Status);\r
+ }\r
+ //\r
+ // attempt to identify flash part and initialize spi table\r
+ //\r
+ for (FlashIndex = 0; FlashIndex < EnumSpiFlashMax; FlashIndex++) {\r
+ Status = mFvbModuleGlobal->SmmSpiProtocol->Init (\r
+ mFvbModuleGlobal->SmmSpiProtocol,\r
+ &(mSpiInitTable[FlashIndex])\r
+ );\r
+ if (!EFI_ERROR (Status)) {\r
+ //\r
+ // read vendor/device IDs to check if flash device is supported\r
+ //\r
+ Status = mFvbModuleGlobal->SmmSpiProtocol->Execute (\r
+ mFvbModuleGlobal->SmmSpiProtocol,\r
+ SPI_OPCODE_JEDEC_ID_INDEX,\r
+ SPI_WREN_INDEX,\r
+ TRUE,\r
+ FALSE,\r
+ FALSE,\r
+ 0,\r
+ 3,\r
+ FlashID,\r
+ EnumSpiRegionAll\r
+ );\r
+ if (!EFI_ERROR (Status)) {\r
+ if (((FlashID[0] == mSpiInitTable[FlashIndex].VendorId) &&\r
+ (FlashID[2] == mSpiInitTable[FlashIndex].DeviceId1)) ||\r
+ ((FlashID[0] == SPI_AT26DF321_ID1) &&\r
+ (FlashID[0] == mSpiInitTable[FlashIndex].VendorId) &&\r
+ (FlashID[1] == mSpiInitTable[FlashIndex].DeviceId0))) {\r
+ //\r
+ // Supported SPI device found\r
+ //\r
+ DEBUG (\r
+ ((EFI_D_INFO),\r
+ "Smm Mode: Supported SPI Flash device found, Vendor Id: 0x%02x, Device ID: 0x%02x%02x!\n",\r
+ FlashID[0],\r
+ FlashID[1],\r
+ FlashID[2])\r
+ );\r
+ break;\r
+ }\r
+ }\r
+ }\r
+ }\r
+\r
+ if (FlashIndex >= EnumSpiFlashMax) {\r
+ Status = EFI_UNSUPPORTED;\r
+ DEBUG (\r
+ (EFI_D_ERROR,\r
+ "ERROR - Unknown SPI Flash Device, Vendor Id: 0x%02x, Device ID: 0x%02x%02x!\n",\r
+ FlashID[0],\r
+ FlashID[1],\r
+ FlashID[2])\r
+ );\r
+ ASSERT_EFI_ERROR (Status);\r
+ }\r
+\r
+ SpiStatus = 0;\r
+ Status = mFvbModuleGlobal->SmmSpiProtocol->Execute (\r
+ mFvbModuleGlobal->SmmSpiProtocol,\r
+ SPI_OPCODE_WRITE_S_INDEX, // OpcodeIndex\r
+ 1, // PrefixOpcodeIndex\r
+ TRUE, // DataCycle\r
+ TRUE, // Atomic\r
+ TRUE, // ShiftOut\r
+ 0, // Address\r
+ 1, // Data Number\r
+ &SpiStatus,\r
+ EnumSpiRegionAll // SPI_REGION_TYPE\r
+ );\r
+ return Status;\r
+}\r
+\r
+EFI_STATUS\r
+SmmSpiNotificationFunction (\r
+ IN CONST EFI_GUID *Protocol,\r
+ IN VOID *Interface,\r
+ IN EFI_HANDLE Handle\r
+ )\r
+{\r
+ return SmmSpiInit();\r
+}\r
+\r
+\r
+VOID\r
+EFIAPI\r
+GetFullDriverPath (\r
+ IN EFI_HANDLE ImageHandle,\r
+ IN EFI_SYSTEM_TABLE *SystemTable,\r
+ OUT EFI_DEVICE_PATH_PROTOCOL **CompleteFilePath\r
+ )\r
+/*++\r
+\r
+Routine Description:\r
+\r
+ Function is used to get the full device path for this driver.\r
+\r
+Arguments:\r
+\r
+ ImageHandle - The loaded image handle of this driver.\r
+ SystemTable - The pointer of system table.\r
+ CompleteFilePath - The pointer of returned full file path\r
+\r
+Returns:\r
+\r
+ none\r
+\r
+--*/\r
+{\r
+ EFI_STATUS Status;\r
+ EFI_LOADED_IMAGE_PROTOCOL *LoadedImage;\r
+ EFI_DEVICE_PATH_PROTOCOL *ImageDevicePath;\r
+\r
+\r
+ Status = gBS->HandleProtocol (\r
+ ImageHandle,\r
+ &gEfiLoadedImageProtocolGuid,\r
+ (VOID **) &LoadedImage\r
+ );\r
+ ASSERT_EFI_ERROR (Status);\r
+\r
+ Status = gBS->HandleProtocol (\r
+ LoadedImage->DeviceHandle,\r
+ &gEfiDevicePathProtocolGuid,\r
+ (VOID *) &ImageDevicePath\r
+ );\r
+ ASSERT_EFI_ERROR (Status);\r
+\r
+ *CompleteFilePath = AppendDevicePath (\r
+ ImageDevicePath,\r
+ LoadedImage->FilePath\r
+ );\r
+\r
+ return ;\r
+}\r
+\r
+\r
+\r
+EFI_STATUS\r
+FvbInitialize (\r
+ IN EFI_HANDLE ImageHandle,\r
+ IN EFI_SYSTEM_TABLE *SystemTable\r
+ )\r
+/*++\r
+\r
+Routine Description:\r
+ This function does common initialization for FVB services\r
+\r
+Arguments:\r
+\r
+Returns:\r
+\r
+--*/\r
+{\r
+ EFI_STATUS Status;\r
+ EFI_FW_VOL_INSTANCE *FwhInstance;\r
+ EFI_FIRMWARE_VOLUME_HEADER *FwVolHeader;\r
+ EFI_FIRMWARE_VOLUME_HEADER *TempFwVolHeader;\r
+ VOID *HobList;\r
+ VOID *FirmwareVolumeHobList;\r
+ UINT32 BufferSize;\r
+ EFI_FV_BLOCK_MAP_ENTRY *PtrBlockMapEntry;\r
+ UINTN LbaAddress;\r
+ BOOLEAN WriteEnabled;\r
+ BOOLEAN WriteLocked;\r
+ EFI_HANDLE FwbHandle;\r
+ EFI_FW_VOL_BLOCK_DEVICE *FvbDevice;\r
+ EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL *OldFwbInterface;\r
+ EFI_DEVICE_PATH_PROTOCOL *FwbDevicePath;\r
+ EFI_DEVICE_PATH_PROTOCOL *TempFwbDevicePath;\r
+ UINT32 MaxLbaSize;\r
+ EFI_PHYSICAL_ADDRESS BaseAddress;\r
+ BOOLEAN WriteBack;\r
+ UINTN NumOfBlocks;\r
+ UINTN HeaderLength;\r
+ UINT8 SpiStatus;\r
+ UINT8 FlashIndex;\r
+ UINT8 FlashID[3];\r
+ EFI_DEVICE_PATH_PROTOCOL *CompleteFilePath;\r
+ UINT8 PrefixOpcodeIndex;\r
+ BOOLEAN InSmm;\r
+ EFI_SMM_BASE2_PROTOCOL *mSmmBase2;\r
+ EFI_HANDLE Handle;\r
+\r
+ VOID *Registration;\r
+ EFI_EVENT Event;\r
+\r
+ CompleteFilePath = NULL;\r
+ GetFullDriverPath (ImageHandle, SystemTable, &CompleteFilePath);\r
+\r
+ Status = EfiGetSystemConfigurationTable (&gEfiHobListGuid, &HobList);\r
+\r
+ //\r
+ // No FV HOBs found\r
+ //\r
+ ASSERT_EFI_ERROR (Status);\r
+\r
+\r
+ //\r
+ // Allocate runtime services data for global variable, which contains\r
+ // the private data of all firmware volume block instances\r
+ //\r
+ mFvbModuleGlobal = (ESAL_FWB_GLOBAL *)AllocateRuntimeZeroPool(sizeof (ESAL_FWB_GLOBAL ));\r
+ ASSERT(mFvbModuleGlobal);\r
+ mSmmBase2 = NULL;\r
+ Status = gBS->LocateProtocol (\r
+ &gEfiSmmBase2ProtocolGuid,\r
+ NULL,\r
+ (VOID **) &mSmmBase2\r
+ );\r
+\r
+ if (mSmmBase2 == NULL) {\r
+ InSmm = FALSE;\r
+ } else {\r
+ mSmmBase2->InSmm (mSmmBase2, &InSmm);\r
+ mSmmBase2->GetSmstLocation (mSmmBase2, &mSmst);\r
+\r
+ }\r
+\r
+ if (!InSmm) {\r
+ mInSmmMode = 0;\r
+ //\r
+ // Obtain a handle for ICH SPI Protocol\r
+ //\r
+ Status = gBS->LocateProtocol (&gEfiSpiProtocolGuid, NULL, (VOID **) &mFvbModuleGlobal->SpiProtocol);\r
+ ASSERT_EFI_ERROR (Status);\r
+\r
+ //\r
+ // attempt to identify flash part and initialize spi table\r
+ //\r
+ for (FlashIndex = 0; FlashIndex < EnumSpiFlashMax; FlashIndex++) {\r
+ Status = mFvbModuleGlobal->SpiProtocol->Init (\r
+ mFvbModuleGlobal->SpiProtocol,\r
+ &(mSpiInitTable[FlashIndex])\r
+ );\r
+ if (!EFI_ERROR (Status)) {\r
+ //\r
+ // read vendor/device IDs to check if flash device is supported\r
+ //\r
+ Status = mFvbModuleGlobal->SpiProtocol->Execute (\r
+ mFvbModuleGlobal->SpiProtocol,\r
+ SPI_OPCODE_JEDEC_ID_INDEX,\r
+ SPI_WREN_INDEX,\r
+ TRUE,\r
+ FALSE,\r
+ FALSE,\r
+ 0,\r
+ 3,\r
+ FlashID,\r
+ EnumSpiRegionAll\r
+ );\r
+ if (!EFI_ERROR (Status)) {\r
+ if (((FlashID[0] == mSpiInitTable[FlashIndex].VendorId) &&\r
+ (FlashID[2] == mSpiInitTable[FlashIndex].DeviceId1)) ||\r
+ ((FlashID[0] == SPI_AT26DF321_ID1) &&\r
+ (FlashID[0] == mSpiInitTable[FlashIndex].VendorId) &&\r
+ (FlashID[1] == mSpiInitTable[FlashIndex].DeviceId0))) {\r
+ //\r
+ // Supported SPI device found\r
+ //\r
+ DEBUG (\r
+ ((EFI_D_INFO),\r
+ "Supported SPI Flash device found, Vendor Id: 0x%02x, Device ID: 0x%02x%02x!\n",\r
+ FlashID[0],\r
+ FlashID[1],\r
+ FlashID[2])\r
+ );\r
+\r
+ PublishFlashDeviceInfo (&mSpiInitTable[FlashIndex]);\r
+ break;\r
+ }\r
+ }\r
+ }\r
+ }\r
+\r
+ if (FlashIndex >= EnumSpiFlashMax) {\r
+ Status = EFI_UNSUPPORTED;\r
+ DEBUG (\r
+ (DEBUG_ERROR,\r
+ "ERROR - Unknown SPI Flash Device, Vendor Id: 0x%02x, Device ID: 0x%02x%02x!\n",\r
+ FlashID[0],\r
+ FlashID[1],\r
+ FlashID[2])\r
+ );\r
+ ASSERT_EFI_ERROR (Status);\r
+ }\r
+\r
+ //\r
+ // Unlock all regions by writing to status register\r
+ // This could be SPI device specific, need to follow the datasheet\r
+ // To write to Write Status Register the Spi PrefixOpcode needs to be:\r
+ // 0 for Atmel parts\r
+ // 0 for Intel parts\r
+ // 0 for Macronix parts\r
+ // 0 for Winbond parts\r
+ // 1 for SST parts\r
+ SpiStatus = 0;\r
+ if (FlashID[0] == SPI_SST25VF016B_ID1) {\r
+ PrefixOpcodeIndex = 1;\r
+ } else {\r
+ PrefixOpcodeIndex = 0;\r
+ }\r
+ Status = mFvbModuleGlobal->SpiProtocol->Execute (\r
+ mFvbModuleGlobal->SpiProtocol,\r
+ SPI_OPCODE_WRITE_S_INDEX, // OpcodeIndex\r
+ PrefixOpcodeIndex, // PrefixOpcodeIndex\r
+ TRUE, // DataCycle\r
+ TRUE, // Atomic\r
+ TRUE, // ShiftOut\r
+ 0, // Address\r
+ 1, // Data Number\r
+ &SpiStatus,\r
+ EnumSpiRegionAll // SPI_REGION_TYPE\r
+ );\r
+\r
+\r
+ } else {\r
+ mInSmmMode = 1;\r
+\r
+ Status = mSmst->SmmLocateProtocol (&gEfiSmmSpiProtocolGuid, NULL, (VOID **) &mFvbModuleGlobal->SmmSpiProtocol);\r
+ if (EFI_ERROR(Status)) {\r
+ Registration = NULL;\r
+ Status = mSmst->SmmRegisterProtocolNotify (\r
+ &gEfiSmmSpiProtocolGuid,\r
+ SmmSpiNotificationFunction,\r
+ &Registration\r
+ );\r
+ } else {\r
+ Status = SmmSpiInit();\r
+ }\r
+\r
+ }\r
+\r
+ //\r
+ // Calculate the total size for all firmware volume block instances\r
+ //\r
+ BufferSize = 0;\r
+ FirmwareVolumeHobList = HobList;\r
+ FwVolHeader = NULL;\r
+ do {\r
+ Status = GetFvbHeader (&FirmwareVolumeHobList, &FwVolHeader, &BaseAddress, &WriteBack);\r
+ if (EFI_ERROR (Status)) {\r
+ break;\r
+ }\r
+\r
+ if (FwVolHeader) {\r
+ BufferSize += (FwVolHeader->HeaderLength + sizeof (EFI_FW_VOL_INSTANCE) - sizeof (EFI_FIRMWARE_VOLUME_HEADER));\r
+ }\r
+ } while (TRUE);\r
+\r
+ //\r
+ // Only need to allocate once. There is only one copy of physical memory for\r
+ // the private data of each FV instance. But in virtual mode or in physical\r
+ // mode, the address of the the physical memory may be different.\r
+ //\r
+ mFvbModuleGlobal->FvInstance[FVB_PHYSICAL] = (EFI_FW_VOL_INSTANCE *) AllocateRuntimeZeroPool (BufferSize);\r
+ ASSERT(mFvbModuleGlobal->FvInstance[FVB_PHYSICAL]);\r
+ //\r
+ // Make a virtual copy of the FvInstance pointer.\r
+ //\r
+ FwhInstance = mFvbModuleGlobal->FvInstance[FVB_PHYSICAL];\r
+ mFvbModuleGlobal->FvInstance[FVB_VIRTUAL] = FwhInstance;\r
+\r
+ mFvbModuleGlobal->NumFv = 0;\r
+ FirmwareVolumeHobList = HobList;\r
+ TempFwVolHeader = NULL;\r
+\r
+ MaxLbaSize = 0;\r
+\r
+ //\r
+ // Fill in the private data of each firmware volume block instance\r
+ //\r
+ // Foreach Fv HOB in the FirmwareVolumeHobList, loop\r
+ //\r
+ do {\r
+ Status = GetFvbHeader (&FirmwareVolumeHobList, &TempFwVolHeader, &BaseAddress, &WriteBack);\r
+ if (EFI_ERROR (Status)) {\r
+ break;\r
+ }\r
+ FwVolHeader = TempFwVolHeader;\r
+\r
+ if (!FwVolHeader) {\r
+ continue;\r
+ }\r
+\r
+\r
+ CopyMem ((UINTN *) &(FwhInstance->VolumeHeader), (UINTN *) FwVolHeader, FwVolHeader->HeaderLength);\r
+ FwVolHeader = &(FwhInstance->VolumeHeader);\r
+\r
+ FwhInstance->FvBase[FVB_PHYSICAL] = (UINTN) BaseAddress;\r
+ FwhInstance->FvBase[FVB_VIRTUAL] = (UINTN) BaseAddress;\r
+\r
+ //\r
+ // FwhInstance->FvWriteBase may not be the same as FwhInstance->FvBase\r
+ //\r
+ FwhInstance->FvWriteBase[FVB_PHYSICAL] = (UINTN) BaseAddress;\r
+ WriteEnabled = TRUE;\r
+\r
+ //\r
+ // Every pointer should have a virtual copy.\r
+ //\r
+ FwhInstance->FvWriteBase[FVB_VIRTUAL] = FwhInstance->FvWriteBase[FVB_PHYSICAL];\r
+\r
+ FwhInstance->WriteEnabled = WriteEnabled;\r
+ EfiInitializeLock (&(FwhInstance->FvbDevLock), TPL_HIGH_LEVEL);\r
+\r
+ LbaAddress = (UINTN) FwhInstance->FvWriteBase[0];\r
+ NumOfBlocks = 0;\r
+ WriteLocked = FALSE;\r
+\r
+ if (WriteEnabled) {\r
+ for (PtrBlockMapEntry = FwVolHeader->BlockMap; PtrBlockMapEntry->NumBlocks != 0; PtrBlockMapEntry++) {\r
+ //\r
+ // Get the maximum size of a block. The size will be used to allocate\r
+ // buffer for Scratch space, the intermediate buffer for FVB extension\r
+ // protocol\r
+ //\r
+ if (MaxLbaSize < PtrBlockMapEntry->Length) {\r
+ MaxLbaSize = PtrBlockMapEntry->Length;\r
+ }\r
+\r
+ NumOfBlocks = NumOfBlocks + PtrBlockMapEntry->NumBlocks;\r
+ }\r
+ //\r
+ // Write back a healthy FV header\r
+ //\r
+ if (WriteBack && (!WriteLocked)) {\r
+\r
+ Status = FlashFdErase (\r
+ (UINTN) FwhInstance->FvWriteBase[0],\r
+ (UINTN) BaseAddress,\r
+ FwVolHeader->BlockMap->Length\r
+ );\r
+\r
+ HeaderLength = (UINTN) FwVolHeader->HeaderLength;\r
+ Status = FlashFdWrite (\r
+ (UINTN) FwhInstance->FvWriteBase[0],\r
+ (UINTN) BaseAddress,\r
+ &HeaderLength,\r
+ (UINT8 *) FwVolHeader,\r
+ FwVolHeader->BlockMap->Length\r
+ );\r
+\r
+ }\r
+ }\r
+ //\r
+ // The total number of blocks in the FV.\r
+ //\r
+ FwhInstance->NumOfBlocks = NumOfBlocks;\r
+\r
+ //\r
+ // If the FV is write locked, set the appropriate attributes\r
+ //\r
+ if (WriteLocked) {\r
+ //\r
+ // write disabled\r
+ //\r
+ FwhInstance->VolumeHeader.Attributes &= ~EFI_FVB2_WRITE_STATUS;\r
+ //\r
+ // lock enabled\r
+ //\r
+ FwhInstance->VolumeHeader.Attributes |= EFI_FVB2_LOCK_STATUS;\r
+ }\r
+\r
+ //\r
+ // Allocate and initialize FVB Device in a runtime data buffer\r
+ //\r
+ FvbDevice = AllocateRuntimeCopyPool (sizeof (EFI_FW_VOL_BLOCK_DEVICE), &mFvbDeviceTemplate);\r
+ ASSERT (FvbDevice);\r
+\r
+ FvbDevice->Instance = mFvbModuleGlobal->NumFv;\r
+ mFvbModuleGlobal->NumFv++;\r
+\r
+ //\r
+ // FV does not contains extension header, then produce MEMMAP_DEVICE_PATH\r
+ //\r
+ if (FwVolHeader->ExtHeaderOffset == 0) {\r
+ FvbDevice->FvDevicePath.MemMapDevPath.StartingAddress = BaseAddress;\r
+ FvbDevice->FvDevicePath.MemMapDevPath.EndingAddress = BaseAddress + (FwVolHeader->FvLength - 1);\r
+ FwbDevicePath = (EFI_DEVICE_PATH_PROTOCOL *)&FvbDevice->FvDevicePath;\r
+ } else {\r
+ CopyGuid (\r
+ &FvbDevice->UefiFvDevicePath.FvDevPath.FvName,\r
+ (EFI_GUID *)(UINTN)(BaseAddress + FwVolHeader->ExtHeaderOffset)\r
+ );\r
+ FwbDevicePath = (EFI_DEVICE_PATH_PROTOCOL *)&FvbDevice->UefiFvDevicePath;\r
+ }\r
+\r
+ if (!InSmm) {\r
+ //\r
+ // Find a handle with a matching device path that has supports FW Block protocol\r
+ //\r
+ TempFwbDevicePath = FwbDevicePath;\r
+ Status = gBS->LocateDevicePath (&gEfiFirmwareVolumeBlockProtocolGuid, &TempFwbDevicePath, &FwbHandle);\r
+ if (EFI_ERROR (Status)) {\r
+ //\r
+ // LocateDevicePath fails so install a new interface and device path\r
+ //\r
+ FwbHandle = NULL;\r
+ Status = gBS->InstallMultipleProtocolInterfaces (\r
+ &FwbHandle,\r
+ &gEfiFirmwareVolumeBlockProtocolGuid,\r
+ &FvbDevice->FwVolBlockInstance,\r
+ &gEfiDevicePathProtocolGuid,\r
+ FwbDevicePath,\r
+ NULL\r
+ );\r
+ ASSERT_EFI_ERROR (Status);\r
+ } else if (EfiIsDevicePathEnd (TempFwbDevicePath)) {\r
+ //\r
+ // Device already exists, so reinstall the FVB protocol\r
+ //\r
+ Status = gBS->HandleProtocol (\r
+ FwbHandle,\r
+ &gEfiFirmwareVolumeBlockProtocolGuid,\r
+ (VOID **) &OldFwbInterface\r
+ );\r
+ ASSERT_EFI_ERROR (Status);\r
+\r
+ Status = gBS->ReinstallProtocolInterface (\r
+ FwbHandle,\r
+ &gEfiFirmwareVolumeBlockProtocolGuid,\r
+ OldFwbInterface,\r
+ &FvbDevice->FwVolBlockInstance\r
+ );\r
+ ASSERT_EFI_ERROR (Status);\r
+\r
+ } else {\r
+ //\r
+ // There was a FVB protocol on an End Device Path node\r
+ //\r
+ ASSERT (FALSE);\r
+ }\r
+ } else {\r
+ FwbHandle = NULL;\r
+ Status = mSmst->SmmInstallProtocolInterface (\r
+ &FwbHandle,\r
+ &gEfiSmmFirmwareVolumeBlockProtocolGuid,\r
+ EFI_NATIVE_INTERFACE,\r
+ &FvbDevice->FwVolBlockInstance\r
+ );\r
+ ASSERT_EFI_ERROR (Status);\r
+ }\r
+\r
+ FwhInstance = (EFI_FW_VOL_INSTANCE *)\r
+ (\r
+ (UINTN) ((UINT8 *) FwhInstance) + FwVolHeader->HeaderLength +\r
+ (sizeof (EFI_FW_VOL_INSTANCE) - sizeof (EFI_FIRMWARE_VOLUME_HEADER))\r
+ );\r
+ } while (TRUE);\r
+\r
+ //\r
+ // Allocate for scratch space, an intermediate buffer for FVB extention\r
+ //\r
+\r
+ mFvbModuleGlobal->FvbScratchSpace[FVB_PHYSICAL] = AllocateRuntimeZeroPool (MaxLbaSize);\r
+\r
+ ASSERT (mFvbModuleGlobal->FvbScratchSpace[FVB_PHYSICAL]);\r
+\r
+ mFvbModuleGlobal->FvbScratchSpace[FVB_VIRTUAL] = mFvbModuleGlobal->FvbScratchSpace[FVB_PHYSICAL];\r
+\r
+ if (!InSmm) {\r
+ Status = gBS->CreateEventEx (\r
+ EVT_NOTIFY_SIGNAL,\r
+ TPL_NOTIFY,\r
+ FvbVirtualddressChangeEvent,\r
+ NULL,\r
+ &gEfiEventVirtualAddressChangeGuid,\r
+ &Event\r
+ );\r
+ ASSERT_EFI_ERROR (Status);\r
+ } else {\r
+ //\r
+ // Inform other platform drivers that SPI device discovered and\r
+ // SPI interface ready for use.\r
+ //\r
+ Handle = NULL;\r
+ Status = gBS->InstallProtocolInterface (\r
+ &Handle,\r
+ &gEfiSmmSpiReadyProtocolGuid,\r
+ EFI_NATIVE_INTERFACE,\r
+ NULL\r
+ );\r
+ }\r
+ return EFI_SUCCESS;\r
+}\r
--- /dev/null
+/** @file\r
+Firmware volume block driver for SPI device\r
+\r
+Copyright (c) 2013-2015 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+**/\r
+\r
+#ifndef _FW_BLOCK_SERVICE_H\r
+#define _FW_BLOCK_SERVICE_H\r
+\r
+\r
+#include "SpiFlashDevice.h"\r
+\r
+//\r
+// Statements that include other header files\r
+\r
+#include <Library/IoLib.h>\r
+#include <Library/HobLib.h>\r
+#include <Library/PcdLib.h>\r
+#include <Library/UefiLib.h>\r
+#include <Library/DebugLib.h>\r
+#include <Library/BaseMemoryLib.h>\r
+#include <Library/DevicePathLib.h>\r
+#include <Library/UefiRuntimeLib.h>\r
+#include <Library/UefiDriverEntryPoint.h>\r
+#include <Library/UefiBootServicesTableLib.h>\r
+#include <Library/UefiRuntimeServicesTableLib.h>\r
+#include <Library/DxeServicesTableLib.h>\r
+#include <Library/MemoryAllocationLib.h>\r
+\r
+#include <Guid/EventGroup.h>\r
+#include <Guid/HobList.h>\r
+#include <Guid/FirmwareFileSystem2.h>\r
+#include <Guid/SystemNvDataGuid.h>\r
+\r
+#include <Protocol/SmmBase2.h>\r
+#include <Protocol/LoadedImage.h>\r
+#include <Protocol/PlatformSmmSpiReady.h>\r
+\r
+//\r
+// Define two helper macro to extract the Capability field or Status field in FVB\r
+// bit fields\r
+//\r
+#define EFI_FVB2_CAPABILITIES (EFI_FVB2_READ_DISABLED_CAP | \\r
+ EFI_FVB2_READ_ENABLED_CAP | \\r
+ EFI_FVB2_WRITE_DISABLED_CAP | \\r
+ EFI_FVB2_WRITE_ENABLED_CAP | \\r
+ EFI_FVB2_LOCK_CAP \\r
+ )\r
+\r
+#define EFI_FVB2_STATUS (EFI_FVB2_READ_STATUS | EFI_FVB2_WRITE_STATUS | EFI_FVB2_LOCK_STATUS)\r
+\r
+#define EFI_INTERNAL_POINTER 0x00000004\r
+#define FVB_PHYSICAL 0\r
+#define FVB_VIRTUAL 1\r
+\r
+typedef struct {\r
+ EFI_LOCK FvbDevLock;\r
+ UINTN FvBase[2];\r
+ UINTN FvWriteBase[2];\r
+ UINTN NumOfBlocks;\r
+ BOOLEAN WriteEnabled;\r
+ EFI_FIRMWARE_VOLUME_HEADER VolumeHeader;\r
+} EFI_FW_VOL_INSTANCE;\r
+\r
+typedef struct {\r
+ UINT32 NumFv;\r
+ EFI_FW_VOL_INSTANCE *FvInstance[2];\r
+ UINT8 *FvbScratchSpace[2];\r
+ EFI_SPI_PROTOCOL *SpiProtocol;\r
+ EFI_SPI_PROTOCOL *SmmSpiProtocol;\r
+} ESAL_FWB_GLOBAL;\r
+\r
+//\r
+// SPI default opcode slots\r
+//\r
+#define SPI_OPCODE_JEDEC_ID_INDEX 0\r
+#define SPI_OPCODE_READ_ID_INDEX 1\r
+#define SPI_OPCODE_WRITE_S_INDEX 2\r
+#define SPI_OPCODE_WRITE_INDEX 3\r
+#define SPI_OPCODE_READ_INDEX 4\r
+#define SPI_OPCODE_ERASE_INDEX 5\r
+#define SPI_OPCODE_READ_S_INDEX 6\r
+#define SPI_OPCODE_CHIP_ERASE_INDEX 7\r
+\r
+#define SPI_ERASE_SECTOR_SIZE SIZE_4KB //This is the chipset requirement\r
+\r
+//\r
+// Fvb Protocol instance data\r
+//\r
+#define FVB_DEVICE_FROM_THIS(a) CR (a, EFI_FW_VOL_BLOCK_DEVICE, FwVolBlockInstance, FVB_DEVICE_SIGNATURE)\r
+#define FVB_EXTEND_DEVICE_FROM_THIS(a) CR (a, EFI_FW_VOL_BLOCK_DEVICE, FvbExtension, FVB_DEVICE_SIGNATURE)\r
+#define FVB_DEVICE_SIGNATURE SIGNATURE_32 ('F', 'V', 'B', 'C')\r
+//\r
+// Device Path\r
+//\r
+#define EFI_END_ENTIRE_DEVICE_PATH_SUBTYPE 0xff\r
+#define EfiDevicePathType(a) (((a)->Type) & 0x7f)\r
+#define EfiIsDevicePathEndType(a) (EfiDevicePathType (a) == 0x7f)\r
+#define EfiIsDevicePathEndSubType(a) ((a)->SubType == EFI_END_ENTIRE_DEVICE_PATH_SUBTYPE)\r
+#define EfiIsDevicePathEnd(a) (EfiIsDevicePathEndType (a) && EfiIsDevicePathEndSubType (a))\r
+\r
+typedef struct {\r
+ MEMMAP_DEVICE_PATH MemMapDevPath;\r
+ EFI_DEVICE_PATH_PROTOCOL EndDevPath;\r
+} FV_DEVICE_PATH;\r
+\r
+//\r
+// UEFI Specification define FV device path format if FV provide name GUID in extension header\r
+//\r
+typedef struct {\r
+ MEDIA_FW_VOL_DEVICE_PATH FvDevPath;\r
+ EFI_DEVICE_PATH_PROTOCOL EndDevPath;\r
+} UEFI_FV_DEVICE_PATH;\r
+\r
+typedef struct {\r
+ UINTN Signature;\r
+ FV_DEVICE_PATH FvDevicePath;\r
+ UEFI_FV_DEVICE_PATH UefiFvDevicePath;\r
+ UINTN Instance;\r
+ EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL FwVolBlockInstance;\r
+} EFI_FW_VOL_BLOCK_DEVICE;\r
+\r
+typedef struct {\r
+ EFI_PHYSICAL_ADDRESS BaseAddress;\r
+ EFI_FIRMWARE_VOLUME_HEADER FvbInfo;\r
+ //\r
+ // EFI_FV_BLOCK_MAP_ENTRY ExtraBlockMap[n];//n=0\r
+ //\r
+ EFI_FV_BLOCK_MAP_ENTRY End[1];\r
+} EFI_FVB_MEDIA_INFO;\r
+\r
+VOID\r
+FvbVirtualddressChangeEvent (\r
+ IN EFI_EVENT Event,\r
+ IN VOID *Context\r
+ );\r
+\r
+EFI_STATUS\r
+GetFvbInfo (\r
+ IN EFI_PHYSICAL_ADDRESS FvBaseAddress,\r
+ OUT EFI_FIRMWARE_VOLUME_HEADER **FvbInfo\r
+ );\r
+\r
+BOOLEAN\r
+SetPlatformFvbLock (\r
+ IN UINTN LbaAddress\r
+ );\r
+\r
+EFI_STATUS\r
+FvbReadBlock (\r
+ IN UINTN Instance,\r
+ IN EFI_LBA Lba,\r
+ IN UINTN BlockOffset,\r
+ IN OUT UINTN *NumBytes,\r
+ IN UINT8 *Buffer,\r
+ IN ESAL_FWB_GLOBAL *Global,\r
+ IN BOOLEAN Virtual\r
+ );\r
+\r
+EFI_STATUS\r
+FvbWriteBlock (\r
+ IN UINTN Instance,\r
+ IN EFI_LBA Lba,\r
+ IN UINTN BlockOffset,\r
+ IN OUT UINTN *NumBytes,\r
+ IN UINT8 *Buffer,\r
+ IN ESAL_FWB_GLOBAL *Global,\r
+ IN BOOLEAN Virtual\r
+ );\r
+\r
+EFI_STATUS\r
+FvbEraseBlock (\r
+ IN UINTN Instance,\r
+ IN EFI_LBA Lba,\r
+ IN ESAL_FWB_GLOBAL *Global,\r
+ IN BOOLEAN Virtual\r
+ );\r
+\r
+EFI_STATUS\r
+FvbSetVolumeAttributes (\r
+ IN UINTN Instance,\r
+ IN OUT EFI_FVB_ATTRIBUTES_2 *Attributes,\r
+ IN ESAL_FWB_GLOBAL *Global,\r
+ IN BOOLEAN Virtual\r
+ );\r
+\r
+EFI_STATUS\r
+FvbGetVolumeAttributes (\r
+ IN UINTN Instance,\r
+ OUT EFI_FVB_ATTRIBUTES_2 *Attributes,\r
+ IN ESAL_FWB_GLOBAL *Global,\r
+ IN BOOLEAN Virtual\r
+ );\r
+\r
+EFI_STATUS\r
+FvbGetPhysicalAddress (\r
+ IN UINTN Instance,\r
+ OUT EFI_PHYSICAL_ADDRESS *Address,\r
+ IN ESAL_FWB_GLOBAL *Global,\r
+ IN BOOLEAN Virtual\r
+ );\r
+\r
+EFI_STATUS\r
+FvbInitialize (\r
+ IN EFI_HANDLE ImageHandle,\r
+ IN EFI_SYSTEM_TABLE *SystemTable\r
+ );\r
+\r
+VOID\r
+FvbClassAddressChangeEvent (\r
+ IN EFI_EVENT Event,\r
+ IN VOID *Context\r
+ );\r
+\r
+EFI_STATUS\r
+FvbSpecificInitialize (\r
+ IN ESAL_FWB_GLOBAL *mFvbModuleGlobal\r
+ );\r
+\r
+EFI_STATUS\r
+FvbGetLbaAddress (\r
+ IN UINTN Instance,\r
+ IN EFI_LBA Lba,\r
+ OUT UINTN *LbaAddress,\r
+ OUT UINTN *LbaWriteAddress,\r
+ OUT UINTN *LbaLength,\r
+ OUT UINTN *NumOfBlocks,\r
+ IN ESAL_FWB_GLOBAL *Global,\r
+ IN BOOLEAN Virtual\r
+ );\r
+\r
+EFI_STATUS\r
+FvbEraseCustomBlockRange (\r
+ IN UINTN Instance,\r
+ IN EFI_LBA StartLba,\r
+ IN UINTN OffsetStartLba,\r
+ IN EFI_LBA LastLba,\r
+ IN UINTN OffsetLastLba,\r
+ IN ESAL_FWB_GLOBAL *Global,\r
+ IN BOOLEAN Virtual\r
+ );\r
+\r
+//\r
+// Protocol APIs\r
+//\r
+EFI_STATUS\r
+EFIAPI\r
+FvbProtocolGetAttributes (\r
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL *This,\r
+ OUT EFI_FVB_ATTRIBUTES_2 *Attributes\r
+ );\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+FvbProtocolSetAttributes (\r
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL *This,\r
+ IN OUT EFI_FVB_ATTRIBUTES_2 *Attributes\r
+ );\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+FvbProtocolGetPhysicalAddress (\r
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL *This,\r
+ OUT EFI_PHYSICAL_ADDRESS *Address\r
+ );\r
+\r
+EFI_STATUS\r
+FvbProtocolGetBlockSize (\r
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL *This,\r
+ IN EFI_LBA Lba,\r
+ OUT UINTN *BlockSize,\r
+ OUT UINTN *NumOfBlocks\r
+ );\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+FvbProtocolRead (\r
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL *This,\r
+ IN EFI_LBA Lba,\r
+ IN UINTN Offset,\r
+ IN OUT UINTN *NumBytes,\r
+ IN UINT8 *Buffer\r
+ );\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+FvbProtocolWrite (\r
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL *This,\r
+ IN EFI_LBA Lba,\r
+ IN UINTN Offset,\r
+ IN OUT UINTN *NumBytes,\r
+ IN UINT8 *Buffer\r
+ );\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+FvbProtocolEraseBlocks (\r
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL *This,\r
+ ...\r
+ );\r
+\r
+extern SPI_INIT_TABLE mSpiInitTable[];\r
+\r
+#endif\r
--- /dev/null
+/** @file\r
+\r
+Copyright (c) 2013-2015 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+**/\r
+\r
+#include "FwBlockService.h"\r
+\r
+\r
+/**\r
+ This function allows the caller to determine if UEFI SetVirtualAddressMap() has been called.\r
+\r
+ This function returns TRUE after all the EVT_SIGNAL_VIRTUAL_ADDRESS_CHANGE functions have\r
+ executed as a result of the OS calling SetVirtualAddressMap(). Prior to this time FALSE\r
+ is returned. This function is used by runtime code to decide it is legal to access services\r
+ that go away after SetVirtualAddressMap().\r
+\r
+ @retval TRUE The system has finished executing the EVT_SIGNAL_VIRTUAL_ADDRESS_CHANGE event.\r
+ @retval FALSE The system has not finished executing the EVT_SIGNAL_VIRTUAL_ADDRESS_CHANGE event.\r
+\r
+**/\r
+BOOLEAN\r
+EfiGoneVirtual (\r
+ VOID\r
+ )\r
+{\r
+ return FALSE; //Hard coded to FALSE for SMM driver.\r
+}\r
--- /dev/null
+## @file\r
+# Component description file for SpiFvbServices Module\r
+#\r
+# Copyright (c) 2013-2015 Intel Corporation.\r
+#\r
+# This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution. The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php\r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+##\r
+\r
+\r
+[Defines]\r
+ INF_VERSION = 0x00010005\r
+ BASE_NAME = FwBlockServiceSmm\r
+ FILE_GUID = A469DDBD-16D0-4535-BAE3-77274BD70B4C\r
+ MODULE_TYPE = DXE_SMM_DRIVER\r
+ VERSION_STRING = 1.0\r
+ PI_SPECIFICATION_VERSION = 0x0001000A\r
+ ENTRY_POINT = FvbInitialize\r
+\r
+[Sources]\r
+ FwBlockService.c\r
+ FwBlockService.h\r
+ FvbInfo.c\r
+ SpiFlashDevice.c\r
+ SpiFlashDevice.h\r
+ PlatformSmmSpi.c\r
+\r
+[Packages]\r
+ MdePkg/MdePkg.dec\r
+ MdeModulePkg/MdeModulePkg.dec\r
+ QuarkSocPkg/QuarkSocPkg.dec\r
+ QuarkPlatformPkg/QuarkPlatformPkg.dec\r
+\r
+[LibraryClasses]\r
+ IoLib\r
+ PcdLib\r
+ HobLib\r
+ UefiLib\r
+ BaseMemoryLib\r
+ UefiDriverEntryPoint\r
+ MemoryAllocationLib\r
+ UefiRuntimeServicesTableLib\r
+ UefiBootServicesTableLib\r
+ DxeServicesTableLib\r
+\r
+[Guids]\r
+ gEfiEventVirtualAddressChangeGuid\r
+ gEfiHobListGuid\r
+\r
+ [Protocols]\r
+ gEfiFirmwareVolumeBlockProtocolGuid ##Produces\r
+ gEfiSpiProtocolGuid\r
+ gEfiDevicePathProtocolGuid\r
+ gEfiLoadedImageProtocolGuid\r
+ gEfiSmmBase2ProtocolGuid\r
+ gEfiSmmSpiProtocolGuid\r
+ gEfiSmmFirmwareVolumeBlockProtocolGuid\r
+ gEfiSmmSpiReadyProtocolGuid\r
+\r
+[FixedPcd]\r
+ gQuarkPlatformTokenSpaceGuid.PcdFlashAreaSize\r
+\r
+[Pcd]\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize\r
+ gQuarkPlatformTokenSpaceGuid.PcdFlashAreaBaseAddress\r
+ gQuarkPlatformTokenSpaceGuid.PcdFlashFvMainSize\r
+ gQuarkPlatformTokenSpaceGuid.PcdFlashFvMainBase\r
+ gQuarkPlatformTokenSpaceGuid.PcdFlashFvRecoveryBase\r
+ gQuarkPlatformTokenSpaceGuid.PcdFlashFvRecoverySize\r
+ gQuarkPlatformTokenSpaceGuid.PcdFlashFvPayloadBase\r
+ gQuarkPlatformTokenSpaceGuid.PcdFlashFvPayloadSize\r
+ gQuarkPlatformTokenSpaceGuid.PcdSpiFlashDeviceSize\r
+\r
+[Depex]\r
+ gEfiSpiProtocolGuid\r
--- /dev/null
+## @file\r
+# Component description file for SpiFvbServices Module\r
+#\r
+# Copyright (c) 2013-2015 Intel Corporation.\r
+#\r
+# This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution. The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php\r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+##\r
+\r
+\r
+[Defines]\r
+ INF_VERSION = 0x00010005\r
+ BASE_NAME = FwBlockService\r
+ FILE_GUID = 4D35A5A7-622E-4955-A5D2-CDA812940D74\r
+ MODULE_TYPE = DXE_RUNTIME_DRIVER\r
+ VERSION_STRING = 1.0\r
+ ENTRY_POINT = FvbInitialize\r
+\r
+[Sources]\r
+ FwBlockService.c\r
+ FwBlockService.h\r
+ FvbInfo.c\r
+ SpiFlashDevice.c\r
+ SpiFlashDevice.h\r
+\r
+[Packages]\r
+ MdePkg/MdePkg.dec\r
+ MdeModulePkg/MdeModulePkg.dec\r
+ QuarkSocPkg/QuarkSocPkg.dec\r
+ QuarkPlatformPkg/QuarkPlatformPkg.dec\r
+\r
+[LibraryClasses]\r
+ IoLib\r
+ PcdLib\r
+ HobLib\r
+ UefiLib\r
+ BaseMemoryLib\r
+ UefiDriverEntryPoint\r
+ MemoryAllocationLib\r
+ UefiRuntimeLib\r
+ UefiRuntimeServicesTableLib\r
+ UefiBootServicesTableLib\r
+ DxeServicesTableLib\r
+\r
+[Guids]\r
+ gEfiEventVirtualAddressChangeGuid\r
+ gEfiHobListGuid\r
+\r
+ [Protocols]\r
+ gEfiFirmwareVolumeBlockProtocolGuid ##Produces\r
+ gEfiSpiProtocolGuid\r
+ gEfiDevicePathProtocolGuid\r
+ gEfiLoadedImageProtocolGuid\r
+ gEfiSmmBase2ProtocolGuid\r
+ gEfiSmmSpiProtocolGuid\r
+ gEfiSmmFirmwareVolumeBlockProtocolGuid\r
+ gEfiSmmSpiReadyProtocolGuid\r
+\r
+[FixedPcd]\r
+ gQuarkPlatformTokenSpaceGuid.PcdFlashAreaSize\r
+\r
+[Pcd]\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize\r
+ gQuarkPlatformTokenSpaceGuid.PcdFlashAreaBaseAddress\r
+ gQuarkPlatformTokenSpaceGuid.PcdFlashFvMainSize\r
+ gQuarkPlatformTokenSpaceGuid.PcdFlashFvMainBase\r
+ gQuarkPlatformTokenSpaceGuid.PcdFlashFvRecoveryBase\r
+ gQuarkPlatformTokenSpaceGuid.PcdFlashFvRecoverySize\r
+ gQuarkPlatformTokenSpaceGuid.PcdFlashFvPayloadBase\r
+ gQuarkPlatformTokenSpaceGuid.PcdFlashFvPayloadSize\r
+ gQuarkPlatformTokenSpaceGuid.PcdSpiFlashDeviceSize\r
+\r
+[Depex]\r
+ gEfiSpiProtocolGuid\r
--- /dev/null
+/** @file\r
+Initializes Platform Specific Drivers.\r
+\r
+Copyright (c) 2013-2015 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+**/\r
+\r
+#include "SpiFlashDevice.h"\r
+\r
+#define FLASH_SIZE (FixedPcdGet32 (PcdFlashAreaSize))\r
+\r
+SPI_INIT_TABLE mSpiInitTable[] = {\r
+ //\r
+ // Macronix 32Mbit part\r
+ //\r
+ {\r
+ SPI_MX25L3205_ID1,\r
+ SPI_MX25L3205_ID2,\r
+ SPI_MX25L3205_ID3,\r
+ {\r
+ SPI_COMMAND_WRITE_ENABLE,\r
+ SPI_COMMAND_WRITE_S_EN\r
+ },\r
+ {\r
+ {EnumSpiOpcodeReadNoAddr, SPI_COMMAND_JEDEC_ID, EnumSpiCycle33MHz, EnumSpiOperationJedecId},\r
+ {EnumSpiOpcodeRead, SPI_COMMAND_READ_ID, EnumSpiCycle33MHz, EnumSpiOperationOther},\r
+ {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S, EnumSpiCycle33MHz, EnumSpiOperationWriteStatus},\r
+ {EnumSpiOpcodeWrite, SPI_COMMAND_WRITE, EnumSpiCycle33MHz, EnumSpiOperationProgramData_1_Byte},\r
+ {EnumSpiOpcodeRead, SPI_COMMAND_READ, EnumSpiCycle20MHz, EnumSpiOperationReadData},\r
+ {EnumSpiOpcodeWrite, SPI_COMMAND_BLOCK_ERASE, EnumSpiCycle33MHz, EnumSpiOperationErase_64K_Byte},\r
+ {EnumSpiOpcodeReadNoAddr, SPI_COMMAND_READ_S, EnumSpiCycle33MHz, EnumSpiOperationReadStatus},\r
+ {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE, EnumSpiCycle33MHz, EnumSpiOperationFullChipErase}\r
+ },\r
+ 0x400000 - FLASH_SIZE, // BIOS Start Offset\r
+ FLASH_SIZE // BIOS image size in flash\r
+ },\r
+ //\r
+ // Winbond 32Mbit part\r
+ //\r
+ {\r
+ SPI_W25X32_ID1,\r
+ SF_DEVICE_ID0_W25QXX,\r
+ SF_DEVICE_ID1_W25Q32,\r
+ {\r
+ SPI_COMMAND_WRITE_ENABLE,\r
+ SPI_COMMAND_WRITE_S_EN\r
+ },\r
+ {\r
+ {EnumSpiOpcodeReadNoAddr, SPI_COMMAND_JEDEC_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId},\r
+ {EnumSpiOpcodeRead, SPI_COMMAND_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationOther},\r
+ {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus},\r
+ {EnumSpiOpcodeWrite, SPI_COMMAND_WRITE, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},\r
+ {EnumSpiOpcodeRead, SPI_COMMAND_READ, EnumSpiCycle50MHz, EnumSpiOperationReadData},\r
+ {EnumSpiOpcodeWrite, SPI_COMMAND_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte},\r
+ {EnumSpiOpcodeReadNoAddr, SPI_COMMAND_READ_S, EnumSpiCycle50MHz, EnumSpiOperationReadStatus},\r
+ {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE, EnumSpiCycle50MHz, EnumSpiOperationFullChipErase}\r
+ },\r
+ 0x400000 - FLASH_SIZE, // BIOS Start Offset\r
+ FLASH_SIZE // BIOS image size in flash\r
+ },\r
+ //\r
+ // Winbond 32Mbit part\r
+ //\r
+ {\r
+ SPI_W25X32_ID1,\r
+ SPI_W25X32_ID2,\r
+ SPI_W25X32_ID3,\r
+ {\r
+ SPI_COMMAND_WRITE_ENABLE,\r
+ SPI_COMMAND_WRITE_S_EN\r
+ },\r
+ {\r
+ {EnumSpiOpcodeReadNoAddr, SPI_COMMAND_JEDEC_ID, EnumSpiCycle33MHz, EnumSpiOperationJedecId},\r
+ {EnumSpiOpcodeRead, SPI_COMMAND_READ_ID, EnumSpiCycle33MHz, EnumSpiOperationOther},\r
+ {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S, EnumSpiCycle33MHz, EnumSpiOperationWriteStatus},\r
+ {EnumSpiOpcodeWrite, SPI_COMMAND_WRITE, EnumSpiCycle33MHz, EnumSpiOperationProgramData_1_Byte},\r
+ {EnumSpiOpcodeRead, SPI_COMMAND_READ, EnumSpiCycle33MHz, EnumSpiOperationReadData},\r
+ {EnumSpiOpcodeWrite, SPI_COMMAND_ERASE, EnumSpiCycle33MHz, EnumSpiOperationErase_4K_Byte},\r
+ {EnumSpiOpcodeReadNoAddr, SPI_COMMAND_READ_S, EnumSpiCycle33MHz, EnumSpiOperationReadStatus},\r
+ {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE, EnumSpiCycle33MHz, EnumSpiOperationFullChipErase}\r
+ },\r
+ 0x400000 - FLASH_SIZE, // BIOS Start Offset\r
+ FLASH_SIZE // BIOS image size in flash\r
+ },\r
+ //\r
+ // Atmel 32Mbit part\r
+ //\r
+ {\r
+ SPI_AT26DF321_ID1,\r
+ SPI_AT26DF321_ID2, // issue: byte 2 identifies family/density for Atmel\r
+ SPI_AT26DF321_ID3,\r
+ {\r
+ SPI_COMMAND_WRITE_ENABLE,\r
+ SPI_COMMAND_WRITE_S_EN\r
+ },\r
+ {\r
+ {EnumSpiOpcodeReadNoAddr, SPI_COMMAND_JEDEC_ID, EnumSpiCycle33MHz, EnumSpiOperationJedecId},\r
+ {EnumSpiOpcodeRead, SPI_COMMAND_READ_ID, EnumSpiCycle33MHz, EnumSpiOperationOther},\r
+ {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S, EnumSpiCycle33MHz, EnumSpiOperationWriteStatus},\r
+ {EnumSpiOpcodeWrite, SPI_COMMAND_WRITE, EnumSpiCycle33MHz, EnumSpiOperationProgramData_1_Byte},\r
+ {EnumSpiOpcodeRead, SPI_COMMAND_READ, EnumSpiCycle33MHz, EnumSpiOperationReadData},\r
+ {EnumSpiOpcodeWrite, SPI_COMMAND_BLOCK_ERASE, EnumSpiCycle33MHz, EnumSpiOperationErase_64K_Byte},\r
+ {EnumSpiOpcodeReadNoAddr, SPI_COMMAND_READ_S, EnumSpiCycle33MHz, EnumSpiOperationReadStatus},\r
+ {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE, EnumSpiCycle33MHz, EnumSpiOperationFullChipErase}\r
+ },\r
+ 0x400000 - FLASH_SIZE, // BIOS Start Offset\r
+ FLASH_SIZE // BIOS image size in flash\r
+ },\r
+\r
+ //\r
+ // Intel 32Mbit part bottom boot\r
+ //\r
+ {\r
+ SPI_QH25F320_ID1,\r
+ SPI_QH25F320_ID2,\r
+ SPI_QH25F320_ID3,\r
+ {\r
+ SPI_COMMAND_WRITE_ENABLE,\r
+ SPI_COMMAND_WRITE_ENABLE\r
+ },\r
+ {\r
+ {EnumSpiOpcodeReadNoAddr, SPI_COMMAND_JEDEC_ID, EnumSpiCycle33MHz, EnumSpiOperationJedecId},\r
+ {EnumSpiOpcodeRead, SPI_COMMAND_READ_ID, EnumSpiCycle33MHz, EnumSpiOperationOther},\r
+ {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S, EnumSpiCycle33MHz, EnumSpiOperationWriteStatus},\r
+ {EnumSpiOpcodeWrite, SPI_COMMAND_WRITE, EnumSpiCycle33MHz, EnumSpiOperationProgramData_1_Byte},\r
+ {EnumSpiOpcodeRead, SPI_COMMAND_READ, EnumSpiCycle33MHz, EnumSpiOperationReadData},\r
+ {EnumSpiOpcodeWrite, SPI_COMMAND_BLOCK_ERASE, EnumSpiCycle33MHz, EnumSpiOperationErase_64K_Byte},\r
+ {EnumSpiOpcodeReadNoAddr, SPI_COMMAND_READ_S, EnumSpiCycle33MHz, EnumSpiOperationReadStatus},\r
+ {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE, EnumSpiCycle33MHz, EnumSpiOperationFullChipErase}\r
+ },\r
+ 0, // BIOS Start Offset\r
+ FLASH_SIZE // BIOS image size in flash\r
+ },\r
+ //\r
+ // SST 64Mbit part\r
+ //\r
+ {\r
+ SPI_SST25VF080B_ID1, // VendorId\r
+ SF_DEVICE_ID0_25VF064C, // DeviceId 0\r
+ SF_DEVICE_ID1_25VF064C, // DeviceId 1\r
+ {\r
+ SPI_COMMAND_WRITE_ENABLE,\r
+ SPI_COMMAND_WRITE_S_EN\r
+ },\r
+ {\r
+ {EnumSpiOpcodeReadNoAddr, SPI_COMMAND_JEDEC_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId},\r
+ {EnumSpiOpcodeRead, SPI_COMMAND_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationOther},\r
+ {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus},\r
+ {EnumSpiOpcodeWrite, SPI_COMMAND_WRITE, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},\r
+ {EnumSpiOpcodeRead, SPI_COMMAND_READ, EnumSpiCycle50MHz, EnumSpiOperationReadData},\r
+ {EnumSpiOpcodeWrite, SPI_COMMAND_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte},\r
+ {EnumSpiOpcodeReadNoAddr, SPI_COMMAND_READ_S, EnumSpiCycle50MHz, EnumSpiOperationReadStatus},\r
+ {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE, EnumSpiCycle50MHz, EnumSpiOperationFullChipErase}\r
+ },\r
+ 0x800000 - FLASH_SIZE, // BIOS Start Offset\r
+ FLASH_SIZE // BIOS image size in flash\r
+ },\r
+ //\r
+ // NUMONYX 64Mbit part\r
+ //\r
+ {\r
+ SF_VENDOR_ID_NUMONYX, // VendorId\r
+ SF_DEVICE_ID0_M25PX64, // DeviceId 0\r
+ SF_DEVICE_ID1_M25PX64, // DeviceId 1\r
+ {\r
+ SPI_COMMAND_WRITE_ENABLE,\r
+ SPI_COMMAND_WRITE_S_EN\r
+ },\r
+ {\r
+ {EnumSpiOpcodeReadNoAddr, SPI_COMMAND_JEDEC_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId},\r
+ {EnumSpiOpcodeRead, SPI_COMMAND_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationOther},\r
+ {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus},\r
+ {EnumSpiOpcodeWrite, SPI_COMMAND_WRITE, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},\r
+ {EnumSpiOpcodeRead, SPI_COMMAND_READ, EnumSpiCycle50MHz, EnumSpiOperationReadData},\r
+ {EnumSpiOpcodeWrite, SPI_COMMAND_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte},\r
+ {EnumSpiOpcodeReadNoAddr, SPI_COMMAND_READ_S, EnumSpiCycle50MHz, EnumSpiOperationReadStatus},\r
+ {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE, EnumSpiCycle50MHz, EnumSpiOperationFullChipErase}\r
+ },\r
+ 0x800000 - FLASH_SIZE, // BIOS Start Offset\r
+ FLASH_SIZE // BIOS image size in flash\r
+ },\r
+ //\r
+ // Atmel 64Mbit part\r
+ //\r
+ {\r
+ SF_VENDOR_ID_ATMEL, // VendorId\r
+ SF_DEVICE_ID0_AT25DF641, // DeviceId 0\r
+ SF_DEVICE_ID1_AT25DF641, // DeviceId 1\r
+ {\r
+ SPI_COMMAND_WRITE_ENABLE,\r
+ SPI_COMMAND_WRITE_S_EN\r
+ },\r
+ {\r
+ {EnumSpiOpcodeReadNoAddr, SPI_COMMAND_JEDEC_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId},\r
+ {EnumSpiOpcodeRead, SPI_COMMAND_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationOther},\r
+ {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus},\r
+ {EnumSpiOpcodeWrite, SPI_COMMAND_WRITE, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},\r
+ {EnumSpiOpcodeRead, SPI_COMMAND_READ, EnumSpiCycle50MHz, EnumSpiOperationReadData},\r
+ {EnumSpiOpcodeWrite, SPI_COMMAND_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte},\r
+ {EnumSpiOpcodeReadNoAddr, SPI_COMMAND_READ_S, EnumSpiCycle50MHz, EnumSpiOperationReadStatus},\r
+ {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE, EnumSpiCycle50MHz, EnumSpiOperationFullChipErase}\r
+ },\r
+ 0x800000 - FLASH_SIZE, // BIOS Start Offset\r
+ FLASH_SIZE // BIOS image size in flash\r
+ },\r
+\r
+ //\r
+ // Spansion 64Mbit part\r
+ //\r
+ {\r
+ SF_VENDOR_ID_SPANSION, // VendorId\r
+ SF_DEVICE_ID0_S25FL064K, // DeviceId 0\r
+ SF_DEVICE_ID1_S25FL064K, // DeviceId 1\r
+ {\r
+ SPI_COMMAND_WRITE_ENABLE,\r
+ SPI_COMMAND_WRITE_S_EN\r
+ },\r
+ {\r
+ {EnumSpiOpcodeReadNoAddr, SPI_COMMAND_JEDEC_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId},\r
+ {EnumSpiOpcodeRead, SPI_COMMAND_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationOther},\r
+ {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus},\r
+ {EnumSpiOpcodeWrite, SPI_COMMAND_WRITE, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},\r
+ {EnumSpiOpcodeRead, SPI_COMMAND_READ, EnumSpiCycle50MHz, EnumSpiOperationReadData},\r
+ {EnumSpiOpcodeWrite, SPI_COMMAND_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte},\r
+ {EnumSpiOpcodeReadNoAddr, SPI_COMMAND_READ_S, EnumSpiCycle50MHz, EnumSpiOperationReadStatus},\r
+ {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE, EnumSpiCycle50MHz, EnumSpiOperationFullChipErase}\r
+ },\r
+ 0x800000 - FLASH_SIZE, // BIOS Start Offset\r
+ FLASH_SIZE // BIOS image size in flash\r
+ },\r
+\r
+ //\r
+ // Macronix 64Mbit part bottom boot\r
+ //\r
+ {\r
+ SF_VENDOR_ID_MX, // VendorId\r
+ SF_DEVICE_ID0_25L6405D, // DeviceId 0\r
+ SF_DEVICE_ID1_25L6405D, // DeviceId 1\r
+ {\r
+ SPI_COMMAND_WRITE_ENABLE,\r
+ SPI_COMMAND_WRITE_S_EN\r
+ },\r
+ {\r
+ {EnumSpiOpcodeReadNoAddr, SPI_COMMAND_JEDEC_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId},\r
+ {EnumSpiOpcodeRead, SPI_COMMAND_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationOther},\r
+ {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus},\r
+ {EnumSpiOpcodeWrite, SPI_COMMAND_WRITE, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},\r
+ {EnumSpiOpcodeRead, SPI_COMMAND_READ, EnumSpiCycle50MHz, EnumSpiOperationReadData},\r
+ {EnumSpiOpcodeWrite, SPI_COMMAND_BLOCK_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte},\r
+ {EnumSpiOpcodeReadNoAddr, SPI_COMMAND_READ_S, EnumSpiCycle50MHz, EnumSpiOperationReadStatus},\r
+ {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE, EnumSpiCycle50MHz, EnumSpiOperationFullChipErase}\r
+ },\r
+ 0x800000 - FLASH_SIZE, // BIOS Start Offset\r
+ FLASH_SIZE // BIOS image size in flash\r
+ },\r
+ //\r
+ // Winbond 64Mbit part bottom boot\r
+ //\r
+ {\r
+ SPI_W25X64_ID1,\r
+ SF_DEVICE_ID0_W25QXX,\r
+ SF_DEVICE_ID1_W25Q64,\r
+ {\r
+ SPI_COMMAND_WRITE_ENABLE,\r
+ SPI_COMMAND_WRITE_S_EN\r
+ },\r
+ {\r
+ {EnumSpiOpcodeReadNoAddr, SPI_COMMAND_JEDEC_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId},\r
+ {EnumSpiOpcodeRead, SPI_COMMAND_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationOther},\r
+ {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus},\r
+ {EnumSpiOpcodeWrite, SPI_COMMAND_WRITE, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},\r
+ {EnumSpiOpcodeRead, SPI_COMMAND_READ, EnumSpiCycle50MHz, EnumSpiOperationReadData},\r
+ {EnumSpiOpcodeWrite, SPI_COMMAND_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte},\r
+ {EnumSpiOpcodeReadNoAddr, SPI_COMMAND_READ_S, EnumSpiCycle50MHz, EnumSpiOperationReadStatus},\r
+ {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE, EnumSpiCycle50MHz, EnumSpiOperationFullChipErase}\r
+ },\r
+ 0x800000 - FLASH_SIZE, // BIOS Start Offset\r
+ FLASH_SIZE // BIOS image size in flash\r
+ },\r
+ //\r
+ // Winbond 64Mbit part bottom boot\r
+ //\r
+ {\r
+ SPI_W25X64_ID1,\r
+ SPI_W25X64_ID2,\r
+ SPI_W25X64_ID3,\r
+ {\r
+ SPI_COMMAND_WRITE_ENABLE,\r
+ SPI_COMMAND_WRITE_S_EN\r
+ },\r
+ {\r
+ {EnumSpiOpcodeReadNoAddr, SPI_COMMAND_JEDEC_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId},\r
+ {EnumSpiOpcodeRead, SPI_COMMAND_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationOther},\r
+ {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus},\r
+ {EnumSpiOpcodeWrite, SPI_COMMAND_WRITE, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},\r
+ {EnumSpiOpcodeRead, SPI_COMMAND_READ, EnumSpiCycle50MHz, EnumSpiOperationReadData},\r
+ {EnumSpiOpcodeWrite, SPI_COMMAND_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte},\r
+ {EnumSpiOpcodeReadNoAddr, SPI_COMMAND_READ_S, EnumSpiCycle50MHz, EnumSpiOperationReadStatus},\r
+ {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE, EnumSpiCycle50MHz, EnumSpiOperationFullChipErase}\r
+ },\r
+ 0x800000 - FLASH_SIZE, // BIOS Start Offset\r
+ FLASH_SIZE // BIOS image size in flash\r
+ },\r
+ //\r
+ // Intel 64Mbit part bottom boot\r
+ //\r
+ {\r
+ SPI_QH25F640_ID1,\r
+ SPI_QH25F640_ID2,\r
+ SPI_QH25F640_ID3,\r
+ {\r
+ SPI_COMMAND_WRITE_ENABLE,\r
+ SPI_COMMAND_WRITE_S_EN\r
+ },\r
+ {\r
+ {EnumSpiOpcodeReadNoAddr, SPI_COMMAND_JEDEC_ID, EnumSpiCycle33MHz, EnumSpiOperationJedecId},\r
+ {EnumSpiOpcodeRead, SPI_COMMAND_READ_ID, EnumSpiCycle33MHz, EnumSpiOperationOther},\r
+ {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S, EnumSpiCycle33MHz, EnumSpiOperationWriteStatus},\r
+ {EnumSpiOpcodeWrite, SPI_COMMAND_WRITE, EnumSpiCycle33MHz, EnumSpiOperationProgramData_1_Byte},\r
+ {EnumSpiOpcodeRead, SPI_COMMAND_READ, EnumSpiCycle33MHz, EnumSpiOperationReadData},\r
+ {EnumSpiOpcodeWrite, SPI_COMMAND_BLOCK_ERASE, EnumSpiCycle33MHz, EnumSpiOperationErase_64K_Byte},\r
+ {EnumSpiOpcodeReadNoAddr, SPI_COMMAND_READ_S, EnumSpiCycle33MHz, EnumSpiOperationReadStatus},\r
+ {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE, EnumSpiCycle33MHz, EnumSpiOperationFullChipErase}\r
+ },\r
+ 0x800000 - FLASH_SIZE, // BIOS Start Offset\r
+ FLASH_SIZE // BIOS image size in flash\r
+ }\r
+};\r
--- /dev/null
+/** @file\r
+\r
+Copyright (c) 2013-2015 Intel Corporation.\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+**/\r
+\r
+#ifndef _SPI_FLASH_DEVICE_H_\r
+#define _SPI_FLASH_DEVICE_H_\r
+\r
+#include <PiDxe.h>\r
+#include <Protocol/Spi.h>\r
+#include <Protocol/FirmwareVolumeBlock.h>\r
+\r
+//\r
+// Supported SPI Flash Devices\r
+//\r
+typedef enum {\r
+ EnumSpiFlash25L3205D, // Macronix 32Mbit part\r
+ EnumSpiFlashW25Q32, // Winbond 32Mbit part\r
+ EnumSpiFlashW25X32, // Winbond 32Mbit part\r
+ EnumSpiFlashAT25DF321, // Atmel 32Mbit part\r
+ EnumSpiFlashQH25F320, // Intel 32Mbit part\r
+ EnumSpiFlash25VF064C, // SST 64Mbit part\r
+ EnumSpiFlashM25PX64, // NUMONYX 64Mbit part\r
+ EnumSpiFlashAT25DF641, // Atmel 64Mbit part\r
+ EnumSpiFlashS25FL064K, // Spansion 64Mbit part\r
+ EnumSpiFlash25L6405D, // Macronix 64Mbit part\r
+ EnumSpiFlashW25Q64, // Winbond 64Mbit part\r
+ EnumSpiFlashW25X64, // Winbond 64Mbit part\r
+ EnumSpiFlashQH25F640, // Intel 64Mbit part\r
+ EnumSpiFlashMax\r
+} SPI_FLASH_TYPES_SUPPORTED;\r
+\r
+//\r
+// Flash Device commands\r
+//\r
+// If a supported device uses a command different from the list below, a device specific command\r
+// will be defined just below it's JEDEC id section.\r
+//\r
+#define SPI_COMMAND_WRITE 0x02\r
+#define SPI_COMMAND_WRITE_AAI 0xAD\r
+#define SPI_COMMAND_READ 0x03\r
+#define SPI_COMMAND_ERASE 0x20\r
+#define SPI_COMMAND_WRITE_DISABLE 0x04\r
+#define SPI_COMMAND_READ_S 0x05\r
+#define SPI_COMMAND_WRITE_ENABLE 0x06\r
+#define SPI_COMMAND_READ_ID 0xAB\r
+#define SPI_COMMAND_JEDEC_ID 0x9F\r
+#define SPI_COMMAND_WRITE_S_EN 0x50\r
+#define SPI_COMMAND_WRITE_S 0x01\r
+#define SPI_COMMAND_CHIP_ERASE 0xC7\r
+#define SPI_COMMAND_BLOCK_ERASE 0xD8\r
+\r
+//\r
+// Flash JEDEC device ids\r
+//\r
+// SST 8Mbit part\r
+//\r
+#define SPI_SST25VF080B_ID1 0xBF\r
+#define SPI_SST25VF080B_ID2 0x25\r
+#define SPI_SST25VF080B_ID3 0x8E\r
+//\r
+// SST 16Mbit part\r
+//\r
+#define SPI_SST25VF016B_ID1 0xBF\r
+#define SPI_SST25VF016B_ID2 0x25\r
+#define SPI_SST25V016BF_ID3 0x41\r
+//\r
+// Macronix 32Mbit part\r
+//\r
+// MX25 part does not support WRITE_AAI comand (0xAD)\r
+//\r
+#define SPI_MX25L3205_ID1 0xC2\r
+#define SPI_MX25L3205_ID2 0x20\r
+#define SPI_MX25L3205_ID3 0x16\r
+//\r
+// Intel 32Mbit part bottom boot\r
+//\r
+#define SPI_QH25F320_ID1 0x89\r
+#define SPI_QH25F320_ID2 0x89\r
+#define SPI_QH25F320_ID3 0x12 // 32Mbit bottom boot\r
+//\r
+// Intel 64Mbit part bottom boot\r
+//\r
+#define SPI_QH25F640_ID1 0x89\r
+#define SPI_QH25F640_ID2 0x89\r
+#define SPI_QH25F640_ID3 0x13 // 64Mbit bottom boot\r
+//\r
+// QH part does not support command 0x20 for erase; only 0xD8 (sector erase)\r
+// QH part has 0x40 command for erase of parameter block (8 x 8K blocks at bottom of part)\r
+// 0x40 command ignored if address outside of parameter block range\r
+//\r
+#define SPI_QH25F320_COMMAND_PBLOCK_ERASE 0x40\r
+//\r
+// Winbond 32Mbit part\r
+//\r
+#define SPI_W25X32_ID1 0xEF\r
+#define SPI_W25X32_ID2 0x30 // Memory Type\r
+#define SPI_W25X32_ID3 0x16 // Capacity\r
+#define SF_DEVICE_ID1_W25Q32 0x16\r
+\r
+//\r
+// Winbond 64Mbit part\r
+//\r
+#define SPI_W25X64_ID1 0xEF\r
+#define SPI_W25X64_ID2 0x30 // Memory Type\r
+#define SPI_W25X64_ID3 0x17 // Capacity\r
+#define SF_DEVICE_ID0_W25QXX 0x40\r
+#define SF_DEVICE_ID1_W25Q64 0x17\r
+//\r
+// Winbond 128Mbit part\r
+//\r
+#define SF_DEVICE_ID0_W25Q128 0x40\r
+#define SF_DEVICE_ID1_W25Q128 0x18\r
+\r
+//\r
+// Atmel 32Mbit part\r
+//\r
+#define SPI_AT26DF321_ID1 0x1F\r
+#define SPI_AT26DF321_ID2 0x47 // [7:5]=Family, [4:0]=Density\r
+#define SPI_AT26DF321_ID3 0x00\r
+\r
+#define SF_VENDOR_ID_ATMEL 0x1F\r
+#define SF_DEVICE_ID0_AT25DF641 0x48\r
+#define SF_DEVICE_ID1_AT25DF641 0x00\r
+\r
+//\r
+// SST 8Mbit part\r
+//\r
+#define SPI_SST25VF080B_ID1 0xBF\r
+#define SPI_SST25VF080B_ID2 0x25\r
+#define SPI_SST25VF080B_ID3 0x8E\r
+#define SF_DEVICE_ID0_25VF064C 0x25\r
+#define SF_DEVICE_ID1_25VF064C 0x4B\r
+\r
+//\r
+// SST 16Mbit part\r
+//\r
+#define SPI_SST25VF016B_ID1 0xBF\r
+#define SPI_SST25VF016B_ID2 0x25\r
+#define SPI_SST25V016BF_ID3 0x41\r
+\r
+//\r
+// Winbond 32Mbit part\r
+//\r
+#define SPI_W25X32_ID1 0xEF\r
+#define SPI_W25X32_ID2 0x30 // Memory Type\r
+#define SPI_W25X32_ID3 0x16 // Capacity\r
+\r
+#define SF_VENDOR_ID_MX 0xC2\r
+#define SF_DEVICE_ID0_25L6405D 0x20\r
+#define SF_DEVICE_ID1_25L6405D 0x17\r
+\r
+#define SF_VENDOR_ID_NUMONYX 0x20\r
+#define SF_DEVICE_ID0_M25PX64 0x71\r
+#define SF_DEVICE_ID1_M25PX64 0x17\r
+\r
+//\r
+// Spansion 64Mbit part\r
+//\r
+#define SF_VENDOR_ID_SPANSION 0xEF\r
+#define SF_DEVICE_ID0_S25FL064K 0x40\r
+#define SF_DEVICE_ID1_S25FL064K 0x00\r
+\r
+//\r
+// index for prefix opcodes\r
+//\r
+#define SPI_WREN_INDEX 0 // Prefix Opcode 0: SPI_COMMAND_WRITE_ENABLE\r
+#define SPI_EWSR_INDEX 1 // Prefix Opcode 1: SPI_COMMAND_WRITE_S_EN\r
+#define BIOS_CTRL 0xDC\r
+\r
+#define PFAB_CARD_DEVICE_ID 0x5150\r
+#define PFAB_CARD_VENDOR_ID 0x8086\r
+#define PFAB_CARD_SETUP_REGISTER 0x40\r
+#define PFAB_CARD_SETUP_BYTE 0x0d\r
+\r
+\r
+#endif\r
--- /dev/null
+## @file\r
+# Clanton Peak CRB platform with 32-bit DXE for 4MB/8MB flash devices.\r
+#\r
+# This package provides Clanton Peak CRB platform specific modules.\r
+# Copyright (c) 2013 - 2014 Intel Corporation.\r
+#\r
+# This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution. The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php\r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+##\r
+\r
+################################################################################\r
+#\r
+# Defines Section - statements that will be processed to create a Makefile.\r
+#\r
+################################################################################\r
+[Defines]\r
+ DSC_SPECIFICATION = 0x00010005\r
+ PLATFORM_NAME = Quark\r
+ PLATFORM_GUID = F6E7730E-0C7A-4741-9DFC-6BC8B86CD865\r
+ PLATFORM_VERSION = 0.1\r
+ FLASH_DEFINITION = QuarkPlatformPkg/Quark.fdf\r
+ OUTPUT_DIRECTORY = Build/Quark\r
+ SUPPORTED_ARCHITECTURES = IA32\r
+ BUILD_TARGETS = DEBUG|RELEASE\r
+ SKUID_IDENTIFIER = DEFAULT\r
+ VPD_TOOL_GUID = 8C3D856A-9BE6-468E-850A-24F7A8D38E08\r
+\r
+ #\r
+ # Platform On/Off features are defined here\r
+ #\r
+ DEFINE GALILEO = GEN2\r
+ DEFINE SECURE_BOOT_ENABLE = FALSE\r
+ DEFINE SOURCE_DEBUG_ENABLE = FALSE\r
+ DEFINE PERFORMANCE_ENABLE = FALSE\r
+ DEFINE LOGGING = FALSE\r
+\r
+ !if $(TARGET) == "DEBUG"\r
+ DEFINE LOGGING = TRUE\r
+ !endif\r
+\r
+ !if $(PERFORMANCE_ENABLE)\r
+ DEFINE SOURCE_DEBUG_ENABLE = FALSE\r
+ DEFINE LOGGING = FALSE\r
+ !endif\r
+\r
+################################################################################\r
+#\r
+# SKU Identification section - list of all SKU IDs supported by this\r
+# Platform.\r
+#\r
+################################################################################\r
+[SkuIds]\r
+ 0|DEFAULT # The entry: 0|DEFAULT is reserved and always required.\r
+\r
+################################################################################\r
+#\r
+# Library Class section - list of all Library Classes needed by this Platform.\r
+#\r
+################################################################################\r
+[LibraryClasses]\r
+ #\r
+ # Entry point\r
+ #\r
+ PeiCoreEntryPoint|MdePkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.inf\r
+ PeimEntryPoint|MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf\r
+ DxeCoreEntryPoint|MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf\r
+ UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf\r
+ UefiApplicationEntryPoint|MdePkg/Library/UefiApplicationEntryPoint/UefiApplicationEntryPoint.inf\r
+\r
+ #\r
+ # Basic\r
+ #\r
+ BaseLib|MdePkg/Library/BaseLib/BaseLib.inf\r
+ BaseMemoryLib|MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf\r
+ PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf\r
+ CpuLib|MdePkg/Library/BaseCpuLib/BaseCpuLib.inf\r
+ CpuExceptionHandlerLib|UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf\r
+ IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf\r
+ PciLib|MdePkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf\r
+ PciCf8Lib|MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf\r
+ PciExpressLib|MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf\r
+ CacheMaintenanceLib|MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf\r
+ PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf\r
+!if $(SOURCE_DEBUG_ENABLE)\r
+ PeCoffExtraActionLib|SourceLevelDebugPkg/Library/PeCoffExtraActionLibDebug/PeCoffExtraActionLibDebug.inf\r
+ DebugCommunicationLib|SourceLevelDebugPkg/Library/DebugCommunicationLibSerialPort/DebugCommunicationLibSerialPort.inf\r
+!else\r
+ PeCoffExtraActionLib|MdePkg/Library/BasePeCoffExtraActionLibNull/BasePeCoffExtraActionLibNull.inf\r
+!endif\r
+ DebugAgentLib|MdeModulePkg/Library/DebugAgentLibNull/DebugAgentLibNull.inf\r
+ PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf\r
+\r
+ #\r
+ # UEFI & PI\r
+ #\r
+ UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf\r
+ UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf\r
+ UefiRuntimeLib|MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf\r
+ UefiLib|MdePkg/Library/UefiLib/UefiLib.inf\r
+ HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf\r
+ UefiHiiServicesLib|MdeModulePkg/Library/UefiHiiServicesLib/UefiHiiServicesLib.inf\r
+ DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf\r
+ UefiDecompressLib|IntelFrameworkModulePkg/Library/BaseUefiTianoCustomDecompressLib/BaseUefiTianoCustomDecompressLib.inf\r
+ PeiServicesTablePointerLib|MdePkg/Library/PeiServicesTablePointerLibIdt/PeiServicesTablePointerLibIdt.inf\r
+ PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf\r
+ DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf\r
+ DxeServicesTableLib|MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf\r
+ UefiCpuLib|UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.inf\r
+ SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf\r
+\r
+ #\r
+ # Generic Modules\r
+ #\r
+ S3BootScriptLib|MdeModulePkg/Library/PiDxeS3BootScriptLib/DxeS3BootScriptLib.inf\r
+ S3IoLib|MdePkg/Library/BaseS3IoLib/BaseS3IoLib.inf\r
+ S3PciLib|MdePkg/Library/BaseS3PciLib/BaseS3PciLib.inf\r
+ UefiUsbLib|MdePkg/Library/UefiUsbLib/UefiUsbLib.inf\r
+ UefiScsiLib|MdePkg/Library/UefiScsiLib/UefiScsiLib.inf\r
+ NetLib|MdeModulePkg/Library/DxeNetLib/DxeNetLib.inf\r
+ IpIoLib|MdeModulePkg/Library/DxeIpIoLib/DxeIpIoLib.inf\r
+ UdpIoLib|MdeModulePkg/Library/DxeUdpIoLib/DxeUdpIoLib.inf\r
+ DpcLib|MdeModulePkg/Library/DxeDpcLib/DxeDpcLib.inf\r
+ OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.inf\r
+ SynchronizationLib|MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf\r
+ SecurityManagementLib|MdeModulePkg/Library/DxeSecurityManagementLib/DxeSecurityManagementLib.inf\r
+ SmmCorePlatformHookLib|MdeModulePkg/Library/SmmCorePlatformHookLibNull/SmmCorePlatformHookLibNull.inf\r
+ PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf\r
+ HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf\r
+ MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf\r
+ ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeReportStatusCodeLib.inf\r
+ ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf\r
+ LockBoxLib|MdeModulePkg/Library/SmmLockBoxLib/SmmLockBoxDxeLib.inf\r
+ VarCheckLib|MdeModulePkg/Library/VarCheckLib/VarCheckLib.inf\r
+ DebugPrintErrorLevelLib|MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.inf\r
+!if $(LOGGING)\r
+ DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf\r
+!else\r
+ DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf\r
+!endif\r
+!if $(PERFORMANCE_ENABLE)\r
+ PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf\r
+!else\r
+ PerformanceLib|MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibNull.inf\r
+!endif\r
+!if $(SECURE_BOOT_ENABLE)\r
+ BaseCryptLib|CryptoPkg/Library/BaseCryptLib/BaseCryptLib.inf\r
+ PlatformSecureLib|QuarkPlatformPkg/Library/PlatformSecureLib/PlatformSecureLib.inf\r
+ IntrinsicLib|CryptoPkg/Library/IntrinsicLib/IntrinsicLib.inf\r
+ OpensslLib|CryptoPkg/Library/OpensslLib/OpensslLib.inf\r
+ TpmMeasurementLib|SecurityPkg/Library/DxeTpmMeasurementLib/DxeTpmMeasurementLib.inf\r
+ AuthVariableLib|SecurityPkg/Library/AuthVariableLib/AuthVariableLib.inf\r
+!else\r
+ TpmMeasurementLib|MdeModulePkg/Library/TpmMeasurementLibNull/TpmMeasurementLibNull.inf\r
+ AuthVariableLib|MdeModulePkg/Library/AuthVariableLibNull/AuthVariableLibNull.inf\r
+!endif\r
+ FileExplorerLib|MdeModulePkg/Library/FileExplorerLib/FileExplorerLib.inf\r
+\r
+ #\r
+ # CPU\r
+ #\r
+ MtrrLib|QuarkSocPkg/QuarkNorthCluster/Library/MtrrLib/MtrrLib.inf\r
+ LocalApicLib|UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.inf\r
+\r
+ #\r
+ # Quark North Cluster\r
+ #\r
+ SmmLib|QuarkSocPkg/QuarkNorthCluster/Library/QNCSmmLib/QNCSmmLib.inf\r
+ SmbusLib|QuarkSocPkg/QuarkNorthCluster/Library/SmbusLib/SmbusLib.inf\r
+ TimerLib|PcAtChipsetPkg/Library/AcpiTimerLib/DxeAcpiTimerLib.inf\r
+ ResetSystemLib|QuarkSocPkg/QuarkNorthCluster/Library/ResetSystemLib/ResetSystemLib.inf\r
+ IntelQNCLib|QuarkSocPkg/QuarkNorthCluster/Library/IntelQNCLib/IntelQNCLib.inf\r
+ QNCAccessLib|QuarkSocPkg/QuarkNorthCluster/Library/QNCAccessLib/QNCAccessLib.inf\r
+ IoApicLib|PcAtChipsetPkg/Library/BaseIoApicLib/BaseIoApicLib.inf\r
+\r
+ #\r
+ # Quark South Cluster\r
+ #\r
+ IohLib|QuarkSocPkg/QuarkSouthCluster/Library/IohLib/IohLib.inf\r
+ I2cLib|QuarkSocPkg/QuarkSouthCluster/Library/I2cLib/I2cLib.inf\r
+ SerialPortLib|MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.inf\r
+ PlatformHookLib|MdeModulePkg/Library/BasePlatformHookLibNull/BasePlatformHookLibNull.inf\r
+\r
+ #\r
+ # Quark Platform\r
+ #\r
+ RecoveryOemHookLib|QuarkPlatformPkg/Library/RecoveryOemHookLib/RecoveryOemHookLib.inf\r
+ PlatformSecLib|QuarkPlatformPkg/Library/PlatformSecLib/PlatformSecLib.inf\r
+ PlatformPcieHelperLib|QuarkPlatformPkg/Library/PlatformPcieHelperLib/PlatformPcieHelperLib.inf\r
+ PlatformHelperLib|QuarkPlatformPkg/Library/PlatformHelperLib/DxePlatformHelperLib.inf\r
+\r
+[LibraryClasses.common.SEC]\r
+ #\r
+ # SEC specific phase\r
+ #\r
+ ReportStatusCodeLib|MdePkg/Library/BaseReportStatusCodeLibNull/BaseReportStatusCodeLibNull.inf\r
+ PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf\r
+ TimerLib|PcAtChipsetPkg/Library/AcpiTimerLib/BaseAcpiTimerLib.inf\r
+ HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf\r
+ MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf\r
+ CpuExceptionHandlerLib|UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHandlerLib.inf\r
+\r
+[LibraryClasses.IA32.PEIM,LibraryClasses.IA32.PEI_CORE]\r
+ #\r
+ # PEI phase common\r
+ #\r
+ PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf\r
+ HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf\r
+ MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf\r
+ ReportStatusCodeLib|MdeModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf\r
+ ExtractGuidedSectionLib|MdePkg/Library/PeiExtractGuidedSectionLib/PeiExtractGuidedSectionLib.inf\r
+ LockBoxLib|MdeModulePkg/Library/SmmLockBoxLib/SmmLockBoxPeiLib.inf\r
+ TimerLib|PcAtChipsetPkg/Library/AcpiTimerLib/BaseAcpiTimerLib.inf\r
+ PlatformHelperLib|QuarkPlatformPkg/Library/PlatformHelperLib/PeiPlatformHelperLib.inf\r
+ CpuExceptionHandlerLib|UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHandlerLib.inf\r
+!if $(SECURE_BOOT_ENABLE)\r
+ BaseCryptLib|CryptoPkg/Library/BaseCryptLib/PeiCryptLib.inf\r
+!endif\r
+!if $(PERFORMANCE_ENABLE)\r
+ PerformanceLib|MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanceLib.inf\r
+!endif\r
+\r
+[LibraryClasses.IA32.DXE_CORE]\r
+ HobLib|MdePkg/Library/DxeCoreHobLib/DxeCoreHobLib.inf\r
+ MemoryAllocationLib|MdeModulePkg/Library/DxeCoreMemoryAllocationLib/DxeCoreMemoryAllocationLib.inf\r
+ CpuExceptionHandlerLib|UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf\r
+!if $(PERFORMANCE_ENABLE)\r
+ PerformanceLib|MdeModulePkg/Library/DxeCorePerformanceLib/DxeCorePerformanceLib.inf\r
+!endif\r
+\r
+[LibraryClasses.IA32.DXE_SMM_DRIVER]\r
+ SmmServicesTableLib|MdePkg/Library/SmmServicesTableLib/SmmServicesTableLib.inf\r
+ ReportStatusCodeLib|MdeModulePkg/Library/SmmReportStatusCodeLib/SmmReportStatusCodeLib.inf\r
+ MemoryAllocationLib|MdePkg/Library/SmmMemoryAllocationLib/SmmMemoryAllocationLib.inf\r
+ LockBoxLib|MdeModulePkg/Library/SmmLockBoxLib/SmmLockBoxSmmLib.inf\r
+ PciLib|MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf\r
+ CpuExceptionHandlerLib|UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmCpuExceptionHandlerLib.inf\r
+ SmmMemLib|MdePkg/Library/SmmMemLib/SmmMemLib.inf\r
+!if $(SECURE_BOOT_ENABLE)\r
+ BaseCryptLib|CryptoPkg/Library/BaseCryptLib/SmmCryptLib.inf\r
+!endif\r
+!if $(PERFORMANCE_ENABLE)\r
+ PerformanceLib|MdeModulePkg/Library/SmmPerformanceLib/SmmPerformanceLib.inf\r
+!endif\r
+\r
+[LibraryClasses.IA32.SMM_CORE]\r
+ SmmServicesTableLib|MdeModulePkg/Library/PiSmmCoreSmmServicesTableLib/PiSmmCoreSmmServicesTableLib.inf\r
+ ReportStatusCodeLib|MdeModulePkg/Library/SmmReportStatusCodeLib/SmmReportStatusCodeLib.inf\r
+ MemoryAllocationLib|MdeModulePkg/Library/PiSmmCoreMemoryAllocationLib/PiSmmCoreMemoryAllocationLib.inf\r
+ PciLib|MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf\r
+ SmmMemLib|MdePkg/Library/SmmMemLib/SmmMemLib.inf\r
+!if $(SECURE_BOOT_ENABLE)\r
+ BaseCryptLib|CryptoPkg/Library/BaseCryptLib/SmmCryptLib.inf\r
+!endif\r
+!if $(PERFORMANCE_ENABLE)\r
+ PerformanceLib|MdeModulePkg/Library/SmmCorePerformanceLib/SmmCorePerformanceLib.inf\r
+!endif\r
+\r
+[LibraryClasses.IA32.DXE_RUNTIME_DRIVER]\r
+ ReportStatusCodeLib|MdeModulePkg/Library/RuntimeDxeReportStatusCodeLib/RuntimeDxeReportStatusCodeLib.inf\r
+ QNCAccessLib|QuarkSocPkg/QuarkNorthCluster/Library/QNCAccessLib/RuntimeQNCAccessLib.inf\r
+ PciLib|MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf\r
+!if $(SECURE_BOOT_ENABLE)\r
+ BaseCryptLib|CryptoPkg/Library/BaseCryptLib/RuntimeCryptLib.inf\r
+!endif\r
+\r
+[LibraryClasses.IA32.UEFI_DRIVER,LibraryClasses.IA32.UEFI_APPLICATION]\r
+ PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf\r
+\r
+################################################################################\r
+#\r
+# Pcd Section - list of all EDK II PCD Entries defined by this Platform\r
+#\r
+################################################################################\r
+[PcdsFeatureFlag]\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdDevicePathSupportDevicePathToText|TRUE\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdDevicePathSupportDevicePathFromText|TRUE\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSupportUpdateCapsuleReset|TRUE\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdDxeIplSwitchToLongMode|FALSE\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdPciBusHotplugDeviceSupport|FALSE\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdInstallAcpiSdtProtocol|TRUE\r
+!if $(SOURCE_DEBUG_ENABLE)\r
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmDebug|TRUE\r
+!endif\r
+\r
+!if $(TARGET) == "RELEASE"\r
+ gQuarkPlatformTokenSpaceGuid.WaitIfResetDueToError|FALSE\r
+!else\r
+ gQuarkPlatformTokenSpaceGuid.WaitIfResetDueToError|TRUE\r
+!endif\r
+\r
+[PcdsFixedAtBuild]\r
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber|1\r
+ gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdS3AcpiReservedMemorySize|0x20000\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|TRUE\r
+!if $(LOGGING)\r
+ !if $(SOURCE_DEBUG_ENABLE)\r
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x17\r
+ !else\r
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x27\r
+ !endif\r
+ gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07\r
+!else\r
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x0\r
+ gEfiMdePkgTokenSpaceGuid.PcdPostCodePropertyMask|0x0\r
+ gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x3\r
+!endif\r
+ gEfiMdePkgTokenSpaceGuid.PcdPostCodePropertyMask|0x18\r
+ gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xE0000000\r
+!if $(GALILEO) == GEN1\r
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|460800\r
+!endif\r
+!if $(GALILEO) == GEN2\r
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|921600\r
+!endif\r
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits|8\r
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity|1\r
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits|1\r
+ gEfiMdePkgTokenSpaceGuid.PcdDefaultTerminalType|0\r
+!if $(PERFORMANCE_ENABLE)\r
+ gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|0x1\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdMaxPeiPerformanceLogEntries|80\r
+!else\r
+ gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|0x00\r
+!endif\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdLoadModuleAtFixAddressEnable|0\r
+!if $(SECURE_BOOT_ENABLE)\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x2000\r
+!endif\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdHwErrStorageSize|0x00002000\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdMaxHardwareErrorVariableSize|0x1000\r
+ ## RTC Update Timeout Value, need to increase timeout since also\r
+ # waiting for RTC to be busy.\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdRealTimeClockUpdateTimeout|500000\r
+\r
+!if $(SECURE_BOOT_ENABLE)\r
+ # override the default values from SecurityPkg to ensure images from all sources are verified in secure boot\r
+ gEfiSecurityPkgTokenSpaceGuid.PcdOptionRomImageVerificationPolicy|0x04\r
+ gEfiSecurityPkgTokenSpaceGuid.PcdFixedMediaImageVerificationPolicy|0x04\r
+ gEfiSecurityPkgTokenSpaceGuid.PcdRemovableMediaImageVerificationPolicy|0x04\r
+!endif\r
+ gQuarkPlatformTokenSpaceGuid.PcdEsramStage1Base|0x80000000\r
+\r
+!if $(SOURCE_DEBUG_ENABLE)\r
+ gEfiSourceLevelDebugPkgTokenSpaceGuid.PcdDebugLoadImageMethod|0x2\r
+!endif\r
+\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseMmio|TRUE\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x9000B000\r
+!if $(GALILEO) == GEN1\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialBaudRate|460800\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseHardwareFlowControl|FALSE\r
+!endif\r
+!if $(GALILEO) == GEN2\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialBaudRate|921600\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseHardwareFlowControl|FALSE\r
+!endif\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialLineControl|0x03\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialFifoControl|0x07\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialDetectCable|FALSE\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialClockRate|44236800\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialPciDeviceInfo|{0x14, 0x05, 0x84, 0x00, 0xFF}\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterStride|4\r
+\r
+ #\r
+ # typedef struct {\r
+ # UINT16 VendorId; ///< Vendor ID to match the PCI device. The value 0xFFFF terminates the list of entries.\r
+ # UINT16 DeviceId; ///< Device ID to match the PCI device\r
+ # UINT32 ClockRate; ///< UART clock rate. Set to 0 for default clock rate of 1843200 Hz\r
+ # UINT64 Offset; ///< The byte offset into to the BAR\r
+ # UINT8 BarIndex; ///< Which BAR to get the UART base address\r
+ # UINT8 RegisterStride; ///< UART register stride in bytes. Set to 0 for default register stride of 1 byte.\r
+ # UINT16 ReceiveFifoDepth; ///< UART receive FIFO depth in bytes. Set to 0 for a default FIFO depth of 16 bytes.\r
+ # UINT16 TransmitFifoDepth; ///< UART transmit FIFO depth in bytes. Set to 0 for a default FIFO depth of 16 bytes.\r
+ # UINT8 Reserved[2];\r
+ # } PCI_SERIAL_PARAMETER;\r
+ #\r
+ # Vendor 8086 Device 0936 Prog Interface 2, BAR #0, Offset 0, Stride = 4, Clock 44236800 (0x2a300000)\r
+ # Vendor 8086 Device 0936 Prog Interface 2, BAR #0, Offset 0, Stride = 4, Clock 44236800 (0x2a300000)\r
+ #\r
+ # [Vendor] [Device] [---ClockRate---] [------------Offset-----------] [Bar] [Stride] [RxFifo] [TxFifo] [Rsvd] [Vendor]\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdPciSerialParameters|{0x86,0x80, 0x36,0x09, 0x0,0x0,0xA3,0x02, 0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0, 0x00, 0x04, 0x0,0x0, 0x0,0x0, 0x0,0x0, 0xff,0xff}\r
+\r
+ gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciBusNumber |0\r
+ gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciDeviceNumber |31\r
+ gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciFunctionNumber |0\r
+ gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciEnableRegisterOffset|0x4b\r
+ gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoBarEnableMask |0x80\r
+ gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciBarRegisterOffset |0x48\r
+ gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPortBaseAddress |0x1000\r
+ gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiPm1TmrOffset |0x0008\r
+\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdBootManagerMenuFile|{ 0x21, 0xaa, 0x2c, 0x46, 0x14, 0x76, 0x03, 0x45, 0x83, 0x6e, 0x8a, 0xb6, 0xf4, 0x66, 0x23, 0x31 }\r
+\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdConInConnectOnDemand|FALSE\r
+\r
+[PcdsPatchableInModule]\r
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x803000C7\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdVpdBaseAddress|0x0\r
+\r
+[PcdsDynamicExHii.common.DEFAULT]\r
+!if $(PERFORMANCE_ENABLE)\r
+ gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVariableGuid|0x0|0\r
+!else\r
+ gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVariableGuid|0x0|5\r
+!endif\r
+ gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdBootState|L"BootState"|gQuarkPlatformTokenSpaceGuid|0x0|TRUE\r
+\r
+[PcdsDynamicExDefault.common.DEFAULT]\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateDataPtr|0x0\r
+ gQuarkPlatformTokenSpaceGuid.PcdEnableFastBoot|TRUE\r
+ gQuarkPlatformTokenSpaceGuid.PcdUserIsPhysicallyPresent|FALSE\r
+ gQuarkPlatformTokenSpaceGuid.PcdSpiFlashDeviceSize|0\r
+\r
+[PcdsDynamicExVpd]\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVendor|*|32|L"EDK II"\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareRevision|*|0x01000400\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|*|64|L"Galileo 1.0.4"\r
+\r
+#\r
+# ClantonPeakSVP\r
+# gQuarkPlatformTokenSpaceGuid.PcdPlatformType|*|0x0002\r
+# gQuarkPlatformTokenSpaceGuid.PcdPlatformTypeName|*|64|L"ClantonPeakSVP"\r
+# gEfiQuarkNcSocIdTokenSpaceGuid.PcdMrcParameters|*|40|{0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x01, 0x01, 0x00, 0x03, 0x00, 0x00, 0x02, 0x00, 0x00, 0x01, 0x01, 0x03, 0x7c, 0x92, 0x00, 0x00, 0x10, 0x27, 0x00, 0x00, 0x10, 0x27, 0x00, 0x00, 0x40, 0x9c, 0x00, 0x00, 0x06}\r
+#\r
+# KipsBay\r
+# gQuarkPlatformTokenSpaceGuid.PcdPlatformType|*|0x0003\r
+# gQuarkPlatformTokenSpaceGuid.PcdPlatformTypeName|*|64|L"KipsBay"\r
+# gEfiQuarkNcSocIdTokenSpaceGuid.PcdMrcParameters|*|40|{0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x01, 0x00, 0x03, 0x00, 0x00, 0x02, 0x00, 0x00, 0x01, 0x01, 0x01, 0x7c, 0x92, 0x00, 0x00, 0x10, 0x27, 0x00, 0x00, 0x10, 0x27, 0x00, 0x00, 0x40, 0x9c, 0x00, 0x00, 0x06}\r
+#\r
+# CrossHill\r
+# gQuarkPlatformTokenSpaceGuid.PcdPlatformType|*|0x0004\r
+# gQuarkPlatformTokenSpaceGuid.PcdPlatformTypeName|*|64|L"CrossHill"\r
+# gEfiQuarkNcSocIdTokenSpaceGuid.PcdMrcParameters|*|40|{0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x01, 0x00, 0x03, 0x00, 0x00, 0x02, 0x00, 0x00, 0x01, 0x01, 0x03, 0x7c, 0x92, 0x00, 0x00, 0x10, 0x27, 0x00, 0x00, 0x10, 0x27, 0x00, 0x00, 0x40, 0x9c, 0x00, 0x00, 0x06}\r
+#\r
+# ClantonHill\r
+# gQuarkPlatformTokenSpaceGuid.PcdPlatformType|*|0x0005\r
+# gQuarkPlatformTokenSpaceGuid.PcdPlatformTypeName|*|64|L"ClantonHill"\r
+# gEfiQuarkNcSocIdTokenSpaceGuid.PcdMrcParameters|*|40|{0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x01, 0x00, 0x03, 0x00, 0x00, 0x02, 0x00, 0x00, 0x01, 0x01, 0x02, 0x7c, 0x92, 0x00, 0x00, 0x10, 0x27, 0x00, 0x00, 0x10, 0x27, 0x00, 0x00, 0x40, 0x9c, 0x00, 0x00, 0x06}\r
+#\r
+# Galileo\r
+# gQuarkPlatformTokenSpaceGuid.PcdPlatformType|*|0x0006\r
+# gQuarkPlatformTokenSpaceGuid.PcdPlatformTypeName|*|64|L"Galileo"\r
+# gEfiQuarkNcSocIdTokenSpaceGuid.PcdMrcParameters|*|40|{0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x01, 0x00, 0x03, 0x00, 0x00, 0x02, 0x00, 0x00, 0x01, 0x01, 0x01, 0x7c, 0x92, 0x00, 0x00, 0x10, 0x27, 0x00, 0x00, 0x10, 0x27, 0x00, 0x00, 0x40, 0x9c, 0x00, 0x00, 0x06}\r
+#\r
+# GalileoGen2\r
+# gQuarkPlatformTokenSpaceGuid.PcdPlatformType|*|0x0008\r
+# gQuarkPlatformTokenSpaceGuid.PcdPlatformTypeName|*|64|L"GalileoGen2"\r
+# gEfiQuarkNcSocIdTokenSpaceGuid.PcdMrcParameters|*|40|{0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x01, 0x00, 0x03, 0x00, 0x00, 0x02, 0x00, 0x00, 0x01, 0x01, 0x01, 0x7c, 0x92, 0x00, 0x00, 0x10, 0x27, 0x00, 0x00, 0x10, 0x27, 0x00, 0x00, 0x40, 0x9c, 0x00, 0x00, 0x06}\r
+#\r
+!if $(GALILEO) == GEN1\r
+ gQuarkPlatformTokenSpaceGuid.PcdPlatformType|*|0x0006\r
+ gQuarkPlatformTokenSpaceGuid.PcdPlatformTypeName|*|64|L"Galileo"\r
+ gEfiQuarkNcSocIdTokenSpaceGuid.PcdMrcParameters|*|40|{0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x01, 0x00, 0x03, 0x00, 0x00, 0x02, 0x00, 0x00, 0x01, 0x01, 0x01, 0x7c, 0x92, 0x00, 0x00, 0x10, 0x27, 0x00, 0x00, 0x10, 0x27, 0x00, 0x00, 0x40, 0x9c, 0x00, 0x00, 0x06}\r
+!endif\r
+!if $(GALILEO) == GEN2\r
+ gQuarkPlatformTokenSpaceGuid.PcdPlatformType|*|0x0008\r
+ gQuarkPlatformTokenSpaceGuid.PcdPlatformTypeName|*|64|L"GalileoGen2"\r
+ gEfiQuarkNcSocIdTokenSpaceGuid.PcdMrcParameters|*|40|{0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x01, 0x00, 0x03, 0x00, 0x00, 0x02, 0x00, 0x00, 0x01, 0x01, 0x01, 0x7c, 0x92, 0x00, 0x00, 0x10, 0x27, 0x00, 0x00, 0x10, 0x27, 0x00, 0x00, 0x40, 0x9c, 0x00, 0x00, 0x06}\r
+!endif\r
+ gEfiQuarkSCSocIdTokenSpaceGuid.PcdIohEthernetMac0|*|8|{0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\r
+ gEfiQuarkSCSocIdTokenSpaceGuid.PcdIohEthernetMac1|*|8|{0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\r
+\r
+###################################################################################################\r
+#\r
+# Components Section - list of the modules and components that will be processed by compilation\r
+# tools and the EDK II tools to generate PE32/PE32+/Coff image files.\r
+#\r
+# Note: The EDK II DSC file is not used to specify how compiled binary images get placed\r
+# into firmware volume images. This section is just a list of modules to compile from\r
+# source into UEFI-compliant binaries.\r
+# It is the FDF file that contains information on combining binary files into firmware\r
+# volume images, whose concept is beyond UEFI and is described in PI specification.\r
+# Binary modules do not need to be listed in this section, as they should be\r
+# specified in the FDF file. For example: Shell binary, FAT binary (Fat.efi),\r
+# Logo (Logo.bmp), and etc.\r
+# There may also be modules listed in this section that are not required in the FDF file,\r
+# When a module listed here is excluded from FDF file, then UEFI-compliant binary will be\r
+# generated for it, but the binary will not be put into any firmware volume.\r
+#\r
+###################################################################################################\r
+\r
+[Components.IA32]\r
+ #\r
+ # SEC Core\r
+ #\r
+ UefiCpuPkg/SecCore/SecCore.inf {\r
+ !if $(SOURCE_DEBUG_ENABLE)\r
+ <LibraryClasses>\r
+ PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf\r
+ DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/SecPeiDebugAgentLib.inf\r
+ ResetSystemLib|QuarkSocPkg/QuarkNorthCluster/Library/ResetSystemLib/ResetSystemLib.inf\r
+ !endif\r
+ }\r
+\r
+ #\r
+ # PEI Core\r
+ #\r
+ MdeModulePkg/Core/Pei/PeiMain.inf\r
+\r
+ #\r
+ # PEIM\r
+ #\r
+ MdeModulePkg/Universal/PCD/Pei/Pcd.inf {\r
+ <LibraryClasses>\r
+ PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf\r
+ }\r
+ MdeModulePkg/Universal/ReportStatusCodeRouter/Pei/ReportStatusCodeRouterPei.inf\r
+ MdeModulePkg/Universal/StatusCodeHandler/Pei/StatusCodeHandlerPei.inf {\r
+ <LibraryClasses>\r
+ !if $(LOGGING)\r
+ DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf\r
+ !else\r
+ SerialPortLib|MdePkg/Library/BaseSerialPortLibNull/BaseSerialPortLibNull.inf\r
+ !endif\r
+ }\r
+\r
+ MdeModulePkg/Universal/FaultTolerantWritePei/FaultTolerantWritePei.inf\r
+ MdeModulePkg/Universal/Variable/Pei/VariablePei.inf\r
+ MdeModulePkg/Universal/PcatSingleSegmentPciCfg2Pei/PcatSingleSegmentPciCfg2Pei.inf\r
+ UefiCpuPkg/CpuMpPei/CpuMpPei.inf\r
+ MdeModulePkg/Universal/CapsulePei/CapsulePei.inf\r
+\r
+ QuarkSocPkg/QuarkNorthCluster/MemoryInit/Pei/MemoryInitPei.inf\r
+ QuarkPlatformPkg/Platform/Pei/PlatformInit/PlatformEarlyInit.inf\r
+ QuarkPlatformPkg/Platform/Pei/PlatformConfig/PlatformConfigPei.inf\r
+\r
+ UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationPei.inf\r
+\r
+ MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf\r
+\r
+ #\r
+ # S3\r
+ #\r
+ QuarkSocPkg/QuarkNorthCluster/Smm/Pei/SmmAccessPei/SmmAccessPei.inf\r
+ QuarkSocPkg/QuarkNorthCluster/Smm/Pei/SmmControlPei/SmmControlPei.inf\r
+ UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume2Pei.inf\r
+\r
+ #\r
+ # Recovery\r
+ #\r
+ QuarkSocPkg/QuarkSouthCluster/Usb/Common/Pei/UsbPei.inf\r
+ MdeModulePkg/Bus/Pci/EhciPei/EhciPei.inf\r
+ QuarkSocPkg/QuarkSouthCluster/Usb/Ohci/Pei/OhciPei.inf\r
+ MdeModulePkg/Bus/Usb/UsbBotPei/UsbBotPei.inf\r
+ MdeModulePkg/Bus/Usb/UsbBusPei/UsbBusPei.inf\r
+ FatPkg/FatPei/FatPei.inf\r
+ MdeModulePkg/Universal/Disk/CdExpressPei/CdExpressPei.inf\r
+\r
+[Components.IA32]\r
+ #\r
+ # DXE Core\r
+ #\r
+ MdeModulePkg/Core/Dxe/DxeMain.inf\r
+\r
+!if $(SOURCE_DEBUG_ENABLE)\r
+ SourceLevelDebugPkg/DebugAgentDxe/DebugAgentDxe.inf {\r
+ <LibraryClasses>\r
+ DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/DxeDebugAgentLib.inf\r
+ ResetSystemLib|QuarkSocPkg/QuarkNorthCluster/Library/ResetSystemLib/ResetSystemLib.inf\r
+ }\r
+!endif\r
+\r
+\r
+ QuarkPlatformPkg/Platform/Dxe/PlatformInit/PlatformInitDxe.inf\r
+\r
+ #\r
+ # Components that produce the architectural protocols\r
+ #\r
+ MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf {\r
+ <LibraryClasses>\r
+!if $(SECURE_BOOT_ENABLE)\r
+ NULL|SecurityPkg/Library/DxeImageVerificationLib/DxeImageVerificationLib.inf\r
+!endif\r
+ NULL|SecurityPkg/Library/DxeImageAuthenticationStatusLib/DxeImageAuthenticationStatusLib.inf\r
+ }\r
+ UefiCpuPkg/CpuDxe/CpuDxe.inf\r
+ MdeModulePkg/Universal/Metronome/Metronome.inf\r
+ MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf\r
+ MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf\r
+ MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteSmm.inf\r
+!if $(SECURE_BOOT_ENABLE)\r
+ SecurityPkg/VariableAuthenticated/SecureBootConfigDxe/SecureBootConfigDxe.inf\r
+!endif\r
+ MdeModulePkg/Universal/Variable/RuntimeDxe/VariableSmmRuntimeDxe.inf\r
+ MdeModulePkg/Universal/Variable/RuntimeDxe/VariableSmm.inf {\r
+ <LibraryClasses>\r
+ NULL|MdeModulePkg/Library/VarCheckUefiLib/VarCheckUefiLib.inf\r
+ NULL|MdeModulePkg/Library/VarCheckHiiLib/VarCheckHiiLib.inf\r
+ NULL|MdeModulePkg/Library/VarCheckPcdLib/VarCheckPcdLib.inf\r
+ }\r
+\r
+ MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf {\r
+ <LibraryClasses>\r
+ GenericBdsLib|IntelFrameworkModulePkg/Library/GenericBdsLib/GenericBdsLib.inf\r
+ CapsuleLib|IntelFrameworkModulePkg/Library/DxeCapsuleLib/DxeCapsuleLib.inf\r
+ }\r
+ MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf\r
+ MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf\r
+ PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcatRealTimeClockRuntimeDxe.inf\r
+\r
+ #\r
+ # Following are the DXE drivers (alphabetical order)\r
+ #\r
+ MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf\r
+ MdeModulePkg/Universal/PCD/Dxe/Pcd.inf {\r
+ <LibraryClasses>\r
+ PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf\r
+ }\r
+\r
+ QuarkPlatformPkg/Pci/Dxe/PciHostBridge/PciHostBridge.inf\r
+ QuarkPlatformPkg/Platform/SpiFvbServices/PlatformSpi.inf\r
+ QuarkPlatformPkg/Platform/SpiFvbServices/PlatformSmmSpi.inf\r
+ UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.inf\r
+\r
+ #\r
+ # Platform\r
+ #\r
+ MdeModulePkg/Universal/BdsDxe/BdsDxe.inf {\r
+ <LibraryClasses>\r
+ UefiBootManagerLib|MdeModulePkg/Library/UefiBootManagerLib/UefiBootManagerLib.inf\r
+ PlatformBootManagerLib|QuarkPlatformPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf\r
+ }\r
+ MdeModulePkg/Application/UiApp/UiApp.inf {\r
+ <LibraryClasses>\r
+ NULL|MdeModulePkg/Library/DeviceManagerLib/DeviceManagerLib.inf\r
+ NULL|MdeModulePkg/Library/BootManagerLib/BootManagerLib.inf\r
+ NULL|MdeModulePkg/Library/BootMaintenanceManagerLib/BootMaintenanceManagerLib.inf\r
+\r
+ UefiBootManagerLib|MdeModulePkg/Library/UefiBootManagerLib/UefiBootManagerLib.inf\r
+ PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf\r
+ }\r
+\r
+ QuarkSocPkg/QuarkNorthCluster/QNCInit/Dxe/QNCInitDxe.inf\r
+ PcAtChipsetPkg/HpetTimerDxe/HpetTimerDxe.inf\r
+ QuarkSocPkg/QuarkNorthCluster/Smm/Dxe/SmmAccessDxe/SmmAccess.inf\r
+ QuarkPlatformPkg/Platform/Dxe/Setup/DxePlatform.inf\r
+ QuarkSocPkg/QuarkNorthCluster/Spi/PchSpiRuntime.inf {\r
+ <LibraryClasses>\r
+ PciExpressLib|MdePkg/Library/DxeRuntimePciExpressLib/DxeRuntimePciExpressLib.inf\r
+ }\r
+ QuarkSocPkg/QuarkNorthCluster/Spi/PchSpiSmm.inf\r
+ QuarkSocPkg/QuarkNorthCluster/S3Support/Dxe/QncS3Support.inf\r
+ MdeModulePkg/Universal/SectionExtractionDxe/SectionExtractionDxe.inf\r
+ MdeModulePkg/Universal/MemoryTest/NullMemoryTestDxe/NullMemoryTestDxe.inf\r
+ MdeModulePkg/Universal/ReportStatusCodeRouter/RuntimeDxe/ReportStatusCodeRouterRuntimeDxe.inf\r
+ MdeModulePkg/Universal/StatusCodeHandler/RuntimeDxe/StatusCodeHandlerRuntimeDxe.inf {\r
+ <LibraryClasses>\r
+ !if $(LOGGING)\r
+ DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf\r
+ !else\r
+ SerialPortLib|MdePkg/Library/BaseSerialPortLibNull/BaseSerialPortLibNull.inf\r
+ !endif\r
+ }\r
+ MdeModulePkg/Universal/ReportStatusCodeRouter/Smm/ReportStatusCodeRouterSmm.inf\r
+ MdeModulePkg/Universal/StatusCodeHandler/Smm/StatusCodeHandlerSmm.inf {\r
+ <LibraryClasses>\r
+ !if $(LOGGING)\r
+ DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf\r
+ !else\r
+ SerialPortLib|MdePkg/Library/BaseSerialPortLibNull/BaseSerialPortLibNull.inf\r
+ !endif\r
+ }\r
+ #\r
+ # ACPI\r
+ #\r
+ QuarkPlatformPkg/Platform/Dxe/SaveMemoryConfig/SaveMemoryConfig.inf\r
+ MdeModulePkg/Universal/Acpi/S3SaveStateDxe/S3SaveStateDxe.inf\r
+# MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/BootScriptExecutorDxe.inf {\r
+ QuarkPlatformPkg/Acpi/Dxe/BootScriptExecutorDxe/BootScriptExecutorDxe.inf {\r
+ <LibraryClasses>\r
+ !if $(LOGGING)\r
+ DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf\r
+ !else\r
+ SerialPortLib|MdePkg/Library/BaseSerialPortLibNull/BaseSerialPortLibNull.inf\r
+ !endif\r
+ !if $(SOURCE_DEBUG_ENABLE)\r
+ DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/DxeDebugAgentLib.inf\r
+ ResetSystemLib|QuarkSocPkg/QuarkNorthCluster/Library/ResetSystemLib/ResetSystemLib.inf\r
+ !endif\r
+ }\r
+ MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf\r
+ IntelFrameworkModulePkg/Universal/Acpi/AcpiS3SaveDxe/AcpiS3SaveDxe.inf\r
+ QuarkPlatformPkg/Acpi/AcpiTables/AcpiTables.inf\r
+ QuarkPlatformPkg/Acpi/Dxe/AcpiPlatform/AcpiPlatform.inf\r
+\r
+ #\r
+ # SMM\r
+ #\r
+ MdeModulePkg/Core/PiSmmCore/PiSmmIpl.inf\r
+ MdeModulePkg/Core/PiSmmCore/PiSmmCore.inf\r
+ UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf {\r
+ <LibraryClasses>\r
+ SmmCpuFeaturesLib|QuarkSocPkg/QuarkNorthCluster/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf\r
+ SmmCpuPlatformHookLib|UefiCpuPkg/Library/SmmCpuPlatformHookLibNull/SmmCpuPlatformHookLibNull.inf\r
+\r
+ !if $(LOGGING)\r
+ DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf\r
+ !else\r
+ SerialPortLib|MdePkg/Library/BaseSerialPortLibNull/BaseSerialPortLibNull.inf\r
+ !endif\r
+ !if $(SOURCE_DEBUG_ENABLE)\r
+ DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/SmmDebugAgentLib.inf\r
+ ResetSystemLib|QuarkSocPkg/QuarkNorthCluster/Library/ResetSystemLib/ResetSystemLib.inf\r
+ !endif\r
+ <PcdsPatchableInModule>\r
+ #\r
+ # Disable DEBUG_CACHE because SMI entry/exit may change MTRRs\r
+ #\r
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x801000C7\r
+ }\r
+\r
+ UefiCpuPkg/CpuIo2Smm/CpuIo2Smm.inf\r
+ QuarkSocPkg/QuarkNorthCluster/Smm/Dxe/SmmControlDxe/SmmControlDxe.inf\r
+ QuarkSocPkg/QuarkNorthCluster/Smm/DxeSmm/QncSmmDispatcher/QNCSmmDispatcher.inf\r
+ QuarkPlatformPkg/Acpi/DxeSmm/AcpiSmm/AcpiSmmPlatform.inf\r
+ QuarkPlatformPkg/Acpi/DxeSmm/SmmPowerManagement/SmmPowerManagement.inf\r
+ MdeModulePkg/Universal/LockBox/SmmLockBox/SmmLockBox.inf\r
+ UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationSmm.inf\r
+\r
+ #\r
+ # SMBIOS\r
+ #\r
+ MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf\r
+ QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/SmbiosMiscDxe.inf\r
+ QuarkPlatformPkg/Platform/Dxe/MemorySubClass/MemorySubClass.inf\r
+ #\r
+ # PCI\r
+ #\r
+ QuarkPlatformPkg/Pci/Dxe/PciPlatform/PciPlatform.inf\r
+ MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf\r
+ QuarkSocPkg/QuarkSouthCluster/IohInit/Dxe/IohInitDxe.inf\r
+ MdeModulePkg/Bus/Pci/PciSioSerialDxe/PciSioSerialDxe.inf\r
+\r
+ #\r
+ # USB\r
+ #\r
+ MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf\r
+ QuarkSocPkg/QuarkSouthCluster/Usb/Ohci/Dxe/OhciDxe.inf\r
+ MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf\r
+ MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf\r
+ MdeModulePkg/Bus/Usb/UsbMouseDxe/UsbMouseDxe.inf\r
+ MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf\r
+\r
+ #\r
+ # SDIO\r
+ #\r
+ QuarkSocPkg/QuarkSouthCluster/Sdio/Dxe/SDControllerDxe/SDControllerDxe.inf {\r
+ <PcdsPatchableInModule>\r
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80300087\r
+ }\r
+ QuarkSocPkg/QuarkSouthCluster/Sdio/Dxe/SDMediaDeviceDxe/SDMediaDeviceDxe.inf {\r
+ <PcdsPatchableInModule>\r
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80300087\r
+ }\r
+\r
+ #\r
+ # Console\r
+ #\r
+ MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf\r
+ MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf {\r
+ <LibraryClasses>\r
+ PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf\r
+ }\r
+ MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf\r
+ MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf\r
+ MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf {\r
+ <LibraryClasses>\r
+ CustomizedDisplayLib|MdeModulePkg/Library/CustomizedDisplayLib/CustomizedDisplayLib.inf\r
+ }\r
+ MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf\r
+ MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf\r
+\r
+ #\r
+ # File System Modules\r
+ #\r
+ MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf\r
+ MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf\r
+ FatPkg/EnhancedFatDxe/Fat.inf\r
+!if $(PERFORMANCE_ENABLE)\r
+ MdeModulePkg/Universal/FvSimpleFileSystemDxe/FvSimpleFileSystemDxe.inf\r
+!endif\r
+\r
+ #\r
+ # Capsule update\r
+ #\r
+ IntelFrameworkModulePkg/Universal/FirmwareVolume/FwVolDxe/FwVolDxe.inf\r
+ IntelFrameworkModulePkg/Universal/FirmwareVolume/UpdateDriverDxe/UpdateDriverDxe.inf\r
+\r
+ #\r
+ # Performance Application\r
+ #\r
+!if $(PERFORMANCE_ENABLE)\r
+ PerformancePkg/Dp_App/Dp.inf {\r
+ <LibraryClasses>\r
+ ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf\r
+ FileHandleLib|MdePkg/Library/UefiFileHandleLib/UefiFileHandleLib.inf\r
+ }\r
+!endif\r
+\r
+ ShellPkg/Application/Shell/Shell.inf {\r
+ <LibraryClasses>\r
+ ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellCommandLib.inf\r
+ NULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2CommandsLib.inf\r
+ NULL|ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1CommandsLib.inf\r
+ NULL|ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3CommandsLib.inf\r
+ NULL|ShellPkg/Library/UefiShellDriver1CommandsLib/UefiShellDriver1CommandsLib.inf\r
+ NULL|ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1CommandsLib.inf\r
+ NULL|ShellPkg/Library/UefiShellInstall1CommandsLib/UefiShellInstall1CommandsLib.inf\r
+ NULL|ShellPkg/Library/UefiShellNetwork1CommandsLib/UefiShellNetwork1CommandsLib.inf\r
+ HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingLib.inf\r
+ ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf\r
+ FileHandleLib|MdePkg/Library/UefiFileHandleLib/UefiFileHandleLib.inf\r
+ PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf\r
+ BcfgCommandLib|ShellPkg/Library/UefiShellBcfgCommandLib/UefiShellBcfgCommandLib.inf\r
+\r
+ <PcdsFixedAtBuild>\r
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0xFF\r
+ gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE\r
+ gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|8000\r
+ }\r
+\r
+[BuildOptions.common.EDKII.DXE_RUNTIME_DRIVER]\r
+ MSFT:*_*_*_DLINK_FLAGS = /ALIGN:4096\r
--- /dev/null
+## @file\r
+# FDF file of Clanton Peak CRB platform with 32-bit DXE\r
+#\r
+# This package provides QuarkNcSocId platform specific modules.\r
+# Copyright (c) 2013 - 2015 Intel Corporation.\r
+#\r
+# This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution. The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php\r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+##\r
+\r
+################################################################################\r
+#\r
+# Defines Section - statements that will be processed to create a Makefile.\r
+#\r
+################################################################################\r
+[Defines]\r
+# Address 0x100000000 (4 GB reset address)\r
+# Base Size\r
+# +---------------------------+\r
+# FLASH_BASE | FD.Quark: | 0x800000 (8 MB)\r
+# 0xFF800000 | BaseAddress |\r
+# +---------------------------+\r
+#\r
+# Flash offsets are 0 based, but are relative to FD.Quark BaseAddress, e.g. Payload Base is at 0x400000, Flash Base is at 0xFF800000 for 8 MB SPI part.\r
+# 0xFF800000 + 0x400000 = 0xFFC00000.\r
+#\r
+# Address 0x0 (0xFF800000 for 8 MB SPI part)\r
+# +---------------------------+\r
+# FLASH_FV_PAYLOAD_BASE | Payload Image | FLASH_FV_PAYLOAD_SIZE\r
+# 0x00400000 | | 0x00100000\r
+# +---------------------------+\r
+# FLASH_FV_MAIN_BASE | FvMain Image (Compressed) | FLASH_FV_MAIN_SIZE\r
+# 0x00500000 | | 0x001E0000\r
+# +---------------------------+\r
+# NVRAM_AREA_BASE | NVRAM Area= | NVRAM_AREA_SIZE\r
+# 0x006E0000 | Variable + FTW Working + |\r
+# | FTW Spare |\r
+# +---+-------------------+---+\r
+# NVRAM_AREA_VARIABLE_BASE | | NVRAM_AREA_VARIABLE_SIZE\r
+# | |\r
+# +-------------------+\r
+# FTW_WORKING_BASE | | FTW_WORKING_SIZE\r
+# | |\r
+# +-------------------+\r
+# FTW_SPARE_BASE | | FTW_SPARE_SIZE\r
+# | |\r
+# +---+-------------------+---+\r
+# RMU_BINARY_BASE | RMU Binary | RMU_BINARY_SIZE\r
+# 0x00700000 | | 0x00008000\r
+# +---------------------------+\r
+# PLATFORM_DATA_BASE | PlatformData Binary | PLATFORM_DATA_SIZE\r
+# 0x00710000 | | 0x00001000\r
+# +---------------------------+\r
+# FVRECOVERY_IMAGE_BASE | FVRECOVERY Image | FVRECOVERY_IMAGE_SIZE\r
+# 0x720000 | | 0x000E0000\r
+# +---------------------------+\r
+\r
+ #\r
+ # Define value used to compute FLASH regions below reset vector location just below 4GB\r
+ #\r
+ DEFINE RESET_ADDRESS = 0x100000000 # 4 GB\r
+\r
+ #\r
+ # Set size of FLASH to 8MB\r
+ #\r
+ DEFINE FLASH_SIZE = 0x800000\r
+ DEFINE FLASH_BASE = $(RESET_ADDRESS) - $(FLASH_SIZE) # The base address of the Flash Device\r
+\r
+ #\r
+ # Set FLASH block size to 4KB\r
+ #\r
+ DEFINE FLASH_BLOCKSIZE = 0x1000 # 4 KB\r
+\r
+ #\r
+ # Misc settings\r
+ #\r
+ DEFINE FLASH_BLOCKSIZE_DATA = 0x00, 0x10, 0x00, 0x00 # equivalent for DATA blocks\r
+\r
+ #\r
+ # Start PAYLOAD at 4MB into 8MB FLASH\r
+ #\r
+ DEFINE FLASH_FV_PAYLOAD_BASE = 0x00400000\r
+ DEFINE FLASH_FV_PAYLOAD_SIZE = 0x00100000\r
+\r
+ #\r
+ # Put FVMAIN between PAYLOAD and RMU Binary\r
+ #\r
+ DEFINE FLASH_FV_MAIN_BASE = 0x00500000\r
+ DEFINE FLASH_FV_MAIN_SIZE = 0x001E0000\r
+\r
+ #\r
+ # Place NV Storage just above Platform Data Base\r
+ #\r
+ DEFINE NVRAM_AREA_VARIABLE_BASE = 0x006E0000\r
+ DEFINE NVRAM_AREA_SIZE = 0x00020000\r
+\r
+ DEFINE NVRAM_AREA_VARIABLE_SIZE = 0x0000E000\r
+ DEFINE FTW_WORKING_BASE = $(NVRAM_AREA_VARIABLE_BASE) + $(NVRAM_AREA_VARIABLE_SIZE)\r
+ DEFINE FTW_WORKING_SIZE = 0x00002000\r
+ DEFINE FTW_SPARE_BASE = $(FTW_WORKING_BASE) + $(FTW_WORKING_SIZE)\r
+ DEFINE FTW_SPARE_SIZE = $(NVRAM_AREA_SIZE) - $(NVRAM_AREA_VARIABLE_SIZE) - $(FTW_WORKING_SIZE)\r
+\r
+ #\r
+ # RMU Binary must be at fixed address 1MB below 4GB (0xFFF00000)\r
+ #\r
+ DEFINE RMU_BINARY_BASE = 0x00700000 # HW fixed address\r
+ DEFINE RMU_BINARY_SIZE = 0x00008000 # HW fixed address, so fixed size\r
+\r
+ #\r
+ # Platform Data Base must be 64KB above RMU\r
+ #\r
+ DEFINE VPD_BASE = 0x00708000\r
+ DEFINE VPD_SIZE = 0x00001000\r
+\r
+ #\r
+ # Place FV Recovery above NV Storage\r
+ #\r
+ DEFINE FVRECOVERY_IMAGE_SIZE = 0x000F0000\r
+ DEFINE FVRECOVERY_IMAGE_BASE = $(FLASH_SIZE) - $(FVRECOVERY_IMAGE_SIZE)\r
+\r
+################################################################################\r
+#\r
+# FD Section\r
+# The [FD] Section is made up of the definition statements and a\r
+# description of what goes into the Flash Device Image. Each FD section\r
+# defines one flash "device" image. A flash device image may be one of\r
+# the following: Removable media bootable image (like a boot floppy\r
+# image,) an Option ROM image (that would be "flashed" into an add-in\r
+# card,) a System "Flash" image (that would be burned into a system's\r
+# flash) or an Update ("Capsule") image that will be used to update and\r
+# existing system flash.\r
+#\r
+################################################################################\r
+[FD.Quark]\r
+BaseAddress = 0xFF800000 #The base address of the Flash Device; set to same value as FLASH_BASE.\r
+Size = 0x800000 #The size in bytes of the Flash Device; set to same value as FLASH_SIZE.\r
+ErasePolarity = 1\r
+BlockSize = $(FLASH_BLOCKSIZE)\r
+NumBlocks = 0x800 #The number of blocks for the Flash Device.\r
+\r
+SET gQuarkPlatformTokenSpaceGuid.PcdFlashAreaBaseAddress = $(FLASH_BASE)\r
+SET gQuarkPlatformTokenSpaceGuid.PcdFlashAreaSize = $(FLASH_SIZE)\r
+\r
+################################################################################\r
+#\r
+# Following are lists of FD Region layout which correspond to the locations of different\r
+# images within the flash device.\r
+#\r
+# Regions must be defined in ascending order and may not overlap.\r
+#\r
+# A Layout Region start with a eight digit hex offset (leading "0x" required) followed by\r
+# the pipe "|" character, followed by the size of the region, also in hex with the leading\r
+# "0x" characters. Like:\r
+# Offset|Size\r
+# PcdOffsetCName|PcdSizeCName\r
+# RegionType <FV, DATA, or FILE>\r
+#\r
+################################################################################\r
+\r
+########################################################\r
+# Quark Payload Image\r
+########################################################\r
+$(FLASH_FV_PAYLOAD_BASE)|$(FLASH_FV_PAYLOAD_SIZE)\r
+gQuarkPlatformTokenSpaceGuid.PcdFlashFvPayloadBase|gQuarkPlatformTokenSpaceGuid.PcdFlashFvPayloadSize\r
+FV = PAYLOAD\r
+\r
+########################################################\r
+# Quark FVMAIN Image (Compressed)\r
+########################################################\r
+$(FLASH_FV_MAIN_BASE)|$(FLASH_FV_MAIN_SIZE)\r
+gQuarkPlatformTokenSpaceGuid.PcdFlashFvMainBase|gQuarkPlatformTokenSpaceGuid.PcdFlashFvMainSize\r
+FV = FVMAIN_COMPACT\r
+\r
+#############################################################################\r
+# Quark NVRAM Area\r
+# Quark NVRAM Area contains: Variable + FTW Working + FTW Spare\r
+#############################################################################\r
+$(NVRAM_AREA_VARIABLE_BASE)|$(NVRAM_AREA_VARIABLE_SIZE)\r
+gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize\r
+#NV_VARIABLE_STORE\r
+DATA = {\r
+ ## This is the EFI_FIRMWARE_VOLUME_HEADER\r
+ # ZeroVector []\r
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r
+ # FileSystemGuid: gEfiSystemNvDataFvGuid =\r
+ # { 0xFFF12B8D, 0x7696, 0x4C8B, { 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50 }}\r
+ 0x8D, 0x2B, 0xF1, 0xFF, 0x96, 0x76, 0x8B, 0x4C,\r
+ 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50,\r
+ # FvLength: 0x20000\r
+ 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00,\r
+ #Signature "_FVH" #Attributes\r
+ 0x5f, 0x46, 0x56, 0x48, 0xff, 0xfe, 0x04, 0x00,\r
+ #HeaderLength #CheckSum #ExtHeaderOffset #Reserved #Revision\r
+ 0x48, 0x00, 0x19, 0xF9, 0x00, 0x00, 0x00, 0x02,\r
+ #Blockmap[0]: 32 Blocks * 0x1000 Bytes / Block\r
+ 0x20, 0x00, 0x00, 0x00, $(FLASH_BLOCKSIZE_DATA),\r
+ #Blockmap[1]: End\r
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r
+ ## This is the VARIABLE_STORE_HEADER\r
+ !if $(SECURE_BOOT_ENABLE)\r
+ # Signature: gEfiAuthenticatedVariableGuid = { 0xaaf32c78, 0x947b, 0x439a, { 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92 } }\r
+ 0x78, 0x2c, 0xf3, 0xaa, 0x7b, 0x94, 0x9a, 0x43,\r
+ 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92,\r
+ !else\r
+ # Signature: gEfiVariableGuid = { 0xddcf3616, 0x3275, 0x4164, { 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d }}\r
+ 0x16, 0x36, 0xcf, 0xdd, 0x75, 0x32, 0x64, 0x41,\r
+ 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d,\r
+ !endif\r
+ #Size: 0x0E000 (gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize) - 0x48 (size of EFI_FIRMWARE_VOLUME_HEADER) = 0x0DFB8\r
+ # This can speed up the Variable Dispatch a bit.\r
+ 0xB8, 0xDF, 0x00, 0x00,\r
+ #FORMATTED: 0x5A #HEALTHY: 0xFE #Reserved: UINT16 #Reserved1: UINT32\r
+ 0x5A, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00\r
+}\r
+\r
+$(FTW_WORKING_BASE)|$(FTW_WORKING_SIZE)\r
+gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize\r
+#NV_FTW_WORKING\r
+DATA = {\r
+ # EFI_FAULT_TOLERANT_WORKING_BLOCK_HEADER->Signature = gEdkiiWorkingBlockSignatureGuid =\r
+ # { 0x9e58292b, 0x7c68, 0x497d, { 0xa0, 0xce, 0x65, 0x0, 0xfd, 0x9f, 0x1b, 0x95 }}\r
+ 0x2b, 0x29, 0x58, 0x9e, 0x68, 0x7c, 0x7d, 0x49,\r
+ 0xa0, 0xce, 0x65, 0x0, 0xfd, 0x9f, 0x1b, 0x95,\r
+ # Crc:UINT32 #WorkingBlockValid:1, WorkingBlockInvalid:1, Reserved\r
+ 0xE2, 0x33, 0xF2, 0x03, 0xFE, 0xFF, 0xFF, 0xFF,\r
+ # WriteQueueSize: UINT64 #Size: 0x2000 - 0x20 (FTW_WORKING_HEADER) = 0x1FE0\r
+ 0xE0, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00\r
+}\r
+\r
+$(FTW_SPARE_BASE)|$(FTW_SPARE_SIZE)\r
+gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize\r
+#NV_FTW_SPARE\r
+\r
+#########################################################\r
+# Quark Remote Management Unit Binary\r
+#########################################################\r
+$(RMU_BINARY_BASE)|$(RMU_BINARY_SIZE)\r
+INF QuarkSocBinPkg/QuarkNorthCluster/Binary/QuarkMicrocode/QuarkMicrocode.inf\r
+\r
+#########################################################\r
+# PlatformData Binary, default for standalone is none built-in so user selects.\r
+#########################################################\r
+$(VPD_BASE)|$(VPD_SIZE)\r
+gEfiMdeModulePkgTokenSpaceGuid.PcdVpdBaseAddress\r
+FILE = $(OUTPUT_DIRECTORY)/$(TARGET)_$(TOOL_CHAIN_TAG)/FV/8C3D856A-9BE6-468E-850A-24F7A8D38E08.bin\r
+\r
+#######################\r
+# Quark FVRECOVERY Image\r
+#######################\r
+$(FVRECOVERY_IMAGE_BASE)|$(FVRECOVERY_IMAGE_SIZE)\r
+gQuarkPlatformTokenSpaceGuid.PcdFlashFvRecoveryBase|gQuarkPlatformTokenSpaceGuid.PcdFlashFvRecoverySize\r
+FV = FVRECOVERY\r
+\r
+################################################################################\r
+#\r
+# FV Section\r
+#\r
+# [FV] section is used to define what components or modules are placed within a flash\r
+# device file. This section also defines order the components and modules are positioned\r
+# within the image. The [FV] section consists of define statements, set statements and\r
+# module statements.\r
+#\r
+################################################################################\r
+[FV.FVRECOVERY]\r
+BlockSize = $(FLASH_BLOCKSIZE)\r
+FvAlignment = 16 #FV alignment and FV attributes setting.\r
+ERASE_POLARITY = 1\r
+MEMORY_MAPPED = TRUE\r
+STICKY_WRITE = TRUE\r
+LOCK_CAP = TRUE\r
+LOCK_STATUS = TRUE\r
+WRITE_DISABLED_CAP = TRUE\r
+WRITE_ENABLED_CAP = TRUE\r
+WRITE_STATUS = TRUE\r
+WRITE_LOCK_CAP = TRUE\r
+WRITE_LOCK_STATUS = TRUE\r
+READ_DISABLED_CAP = TRUE\r
+READ_ENABLED_CAP = TRUE\r
+READ_STATUS = TRUE\r
+READ_LOCK_CAP = TRUE\r
+READ_LOCK_STATUS = TRUE\r
+FvNameGuid = 18D6D9F4-2EEF-4913-AEE6-BE61C6DA6CC8\r
+\r
+################################################################################\r
+#\r
+# The INF statements point to EDK component and EDK II module INF files, which will be placed into this FV image.\r
+# Parsing tools will scan the INF file to determine the type of component or module.\r
+# The component or module type is used to reference the standard rules\r
+# defined elsewhere in the FDF file.\r
+#\r
+# The format for INF statements is:\r
+# INF $(PathAndInfFileName)\r
+#\r
+################################################################################\r
+\r
+##\r
+# PEI Apriori file example, more PEIM module added later.\r
+##\r
+APRIORI PEI {\r
+ INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf\r
+ # PlatformConfigPei should be immediately after Pcd driver.\r
+ INF QuarkPlatformPkg/Platform/Pei/PlatformConfig/PlatformConfigPei.inf\r
+ INF MdeModulePkg/Universal/PcatSingleSegmentPciCfg2Pei/PcatSingleSegmentPciCfg2Pei.inf\r
+ INF MdeModulePkg/Universal/ReportStatusCodeRouter/Pei/ReportStatusCodeRouterPei.inf\r
+ INF MdeModulePkg/Universal/StatusCodeHandler/Pei/StatusCodeHandlerPei.inf\r
+}\r
+\r
+##\r
+# SEC Phase modules\r
+##\r
+INF UefiCpuPkg/SecCore/SecCore.inf\r
+\r
+INF MdeModulePkg/Core/Pei/PeiMain.inf\r
+\r
+##\r
+# PEI Phase RAW Data files.\r
+##\r
+FILE FREEFORM = PCD(gEfiQuarkNcSocIdTokenSpaceGuid.PcdQuarkMicrocodeFile) {\r
+ SECTION RAW = QuarkSocBinPkg/QuarkNorthCluster/Binary/QuarkMicrocode/RMU.bin\r
+}\r
+\r
+INF RuleOverride = NORELOC MdeModulePkg/Universal/PCD/Pei/Pcd.inf\r
+INF QuarkPlatformPkg/Platform/Pei/PlatformConfig/PlatformConfigPei.inf\r
+INF RuleOverride = NORELOC MdeModulePkg/Universal/ReportStatusCodeRouter/Pei/ReportStatusCodeRouterPei.inf\r
+INF RuleOverride = NORELOC MdeModulePkg/Universal/StatusCodeHandler/Pei/StatusCodeHandlerPei.inf\r
+INF RuleOverride = NORELOC MdeModulePkg/Universal/FaultTolerantWritePei/FaultTolerantWritePei.inf\r
+INF RuleOverride = NORELOC MdeModulePkg/Universal/Variable/Pei/VariablePei.inf\r
+INF RuleOverride = NORELOC UefiCpuPkg/CpuMpPei/CpuMpPei.inf\r
+INF RuleOverride = NORELOC MdeModulePkg/Universal/CapsulePei/CapsulePei.inf\r
+INF RuleOverride = NORELOC QuarkSocPkg/QuarkNorthCluster/MemoryInit/Pei/MemoryInitPei.inf\r
+INF RuleOverride = NORELOC QuarkSocPkg/QuarkNorthCluster/Smm/Pei/SmmAccessPei/SmmAccessPei.inf\r
+INF RuleOverride = NORELOC QuarkSocPkg/QuarkNorthCluster/Smm/Pei/SmmControlPei/SmmControlPei.inf\r
+INF QuarkPlatformPkg/Platform/Pei/PlatformInit/PlatformEarlyInit.inf\r
+INF MdeModulePkg/Universal/PcatSingleSegmentPciCfg2Pei/PcatSingleSegmentPciCfg2Pei.inf\r
+INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf\r
+INF UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationPei.inf\r
+INF UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume2Pei.inf\r
+\r
+FILE FV_IMAGE = 1E9D7604-EF45-46a0-BD8A-71AC78C17AC1 {\r
+ SECTION PEI_DEPEX_EXP = {gEfiPeiMemoryDiscoveredPpiGuid AND gEfiPeiBootInRecoveryModePpiGuid}\r
+ SECTION GUIDED A31280AD-481E-41B6-95E8-127F4C984779 { # TIANO COMPRESS GUID\r
+ SECTION FV_IMAGE = FVRECOVERY_COMPONENTS\r
+ }\r
+}\r
+\r
+################################################################################\r
+#\r
+# FV Section\r
+#\r
+# [FV] section is used to define what components or modules are placed within a flash\r
+# device file. This section also defines order the components and modules are positioned\r
+# within the image. The [FV] section consists of define statements, set statements and\r
+# module statements.\r
+#\r
+################################################################################\r
+[FV.FVRECOVERY_COMPONENTS]\r
+BlockSize = $(FLASH_BLOCKSIZE)\r
+FvAlignment = 16 #FV alignment and FV attributes setting.\r
+ERASE_POLARITY = 1\r
+MEMORY_MAPPED = TRUE\r
+STICKY_WRITE = TRUE\r
+LOCK_CAP = TRUE\r
+LOCK_STATUS = TRUE\r
+WRITE_DISABLED_CAP = TRUE\r
+WRITE_ENABLED_CAP = TRUE\r
+WRITE_STATUS = TRUE\r
+WRITE_LOCK_CAP = TRUE\r
+WRITE_LOCK_STATUS = TRUE\r
+READ_DISABLED_CAP = TRUE\r
+READ_ENABLED_CAP = TRUE\r
+READ_STATUS = TRUE\r
+READ_LOCK_CAP = TRUE\r
+READ_LOCK_STATUS = TRUE\r
+\r
+INF QuarkSocPkg/QuarkSouthCluster/Usb/Common/Pei/UsbPei.inf\r
+INF MdeModulePkg/Bus/Pci/EhciPei/EhciPei.inf\r
+INF QuarkSocPkg/QuarkSouthCluster/Usb/Ohci/Pei/OhciPei.inf\r
+INF MdeModulePkg/Bus/Usb/UsbBusPei/UsbBusPei.inf\r
+INF MdeModulePkg/Bus/Usb/UsbBotPei/UsbBotPei.inf\r
+INF FatPkg/FatPei/FatPei.inf\r
+INF MdeModulePkg/Universal/Disk/CdExpressPei/CdExpressPei.inf\r
+\r
+################################################################################\r
+#\r
+# FV Section\r
+#\r
+# [FV] section is used to define what components or modules are placed within a flash\r
+# device file. This section also defines order the components and modules are positioned\r
+# within the image. The [FV] section consists of define statements, set statements and\r
+# module statements.\r
+#\r
+################################################################################\r
+[FV.FVMAIN]\r
+BlockSize = $(FLASH_BLOCKSIZE)\r
+FvAlignment = 16\r
+ERASE_POLARITY = 1\r
+MEMORY_MAPPED = TRUE\r
+STICKY_WRITE = TRUE\r
+LOCK_CAP = TRUE\r
+LOCK_STATUS = TRUE\r
+WRITE_DISABLED_CAP = TRUE\r
+WRITE_ENABLED_CAP = TRUE\r
+WRITE_STATUS = TRUE\r
+WRITE_LOCK_CAP = TRUE\r
+WRITE_LOCK_STATUS = TRUE\r
+READ_DISABLED_CAP = TRUE\r
+READ_ENABLED_CAP = TRUE\r
+READ_STATUS = TRUE\r
+READ_LOCK_CAP = TRUE\r
+READ_LOCK_STATUS = TRUE\r
+FvNameGuid = 30D9ED01-38D2-418a-90D5-C561750BF80F\r
+\r
+##\r
+# DXE Phase modules\r
+##\r
+INF MdeModulePkg/Core/Dxe/DxeMain.inf\r
+INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf\r
+\r
+!if $(SOURCE_DEBUG_ENABLE)\r
+ INF SourceLevelDebugPkg/DebugAgentDxe/DebugAgentDxe.inf\r
+!endif\r
+\r
+#\r
+# Early SoC / Platform modules\r
+#\r
+INF QuarkPlatformPkg/Platform/Dxe/PlatformInit/PlatformInitDxe.inf\r
+\r
+##\r
+# EDK Core modules\r
+##\r
+INF UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.inf\r
+INF MdeModulePkg/Universal/ReportStatusCodeRouter/RuntimeDxe/ReportStatusCodeRouterRuntimeDxe.inf\r
+INF MdeModulePkg/Universal/StatusCodeHandler/RuntimeDxe/StatusCodeHandlerRuntimeDxe.inf\r
+INF MdeModulePkg/Universal/ReportStatusCodeRouter/Smm/ReportStatusCodeRouterSmm.inf\r
+INF MdeModulePkg/Universal/StatusCodeHandler/Smm/StatusCodeHandlerSmm.inf\r
+INF MdeModulePkg/Universal/SectionExtractionDxe/SectionExtractionDxe.inf\r
+\r
+INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf\r
+INF UefiCpuPkg/CpuDxe/CpuDxe.inf\r
+INF MdeModulePkg/Universal/Metronome/Metronome.inf\r
+INF MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf\r
+INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf\r
+INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteSmm.inf\r
+!if $(SECURE_BOOT_ENABLE)\r
+ INF SecurityPkg/VariableAuthenticated/SecureBootConfigDxe/SecureBootConfigDxe.inf\r
+!endif\r
+INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableSmmRuntimeDxe.inf\r
+INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableSmm.inf\r
+INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf\r
+INF MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf\r
+INF MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf\r
+INF PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcatRealTimeClockRuntimeDxe.inf\r
+INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf\r
+INF MdeModulePkg/Universal/MemoryTest/NullMemoryTestDxe/NullMemoryTestDxe.inf\r
+\r
+#\r
+# Platform\r
+#\r
+INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf\r
+INF MdeModulePkg/Application/UiApp/UiApp.inf\r
+\r
+INF QuarkPlatformPkg/Pci/Dxe/PciHostBridge/PciHostBridge.inf\r
+INF QuarkPlatformPkg/Platform/SpiFvbServices/PlatformSpi.inf\r
+INF QuarkPlatformPkg/Platform/SpiFvbServices/PlatformSmmSpi.inf\r
+INF QuarkSocPkg/QuarkNorthCluster/QNCInit/Dxe/QNCInitDxe.inf\r
+INF PcAtChipsetPkg/HpetTimerDxe/HpetTimerDxe.inf\r
+INF QuarkSocPkg/QuarkNorthCluster/Smm/Dxe/SmmAccessDxe/SmmAccess.inf\r
+INF QuarkSocPkg/QuarkNorthCluster/S3Support/Dxe/QncS3Support.inf\r
+INF QuarkSocPkg/QuarkNorthCluster/Spi/PchSpiRuntime.inf\r
+INF QuarkSocPkg/QuarkNorthCluster/Spi/PchSpiSmm.inf\r
+INF QuarkPlatformPkg/Platform/Dxe/Setup/DxePlatform.inf\r
+\r
+#\r
+# ACPI\r
+#\r
+INF QuarkPlatformPkg/Platform/Dxe/SaveMemoryConfig/SaveMemoryConfig.inf\r
+INF MdeModulePkg/Universal/Acpi/S3SaveStateDxe/S3SaveStateDxe.inf\r
+#INF MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/BootScriptExecutorDxe.inf\r
+INF QuarkPlatformPkg/Acpi/Dxe/BootScriptExecutorDxe/BootScriptExecutorDxe.inf\r
+INF MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf\r
+INF IntelFrameworkModulePkg/Universal/Acpi/AcpiS3SaveDxe/AcpiS3SaveDxe.inf\r
+INF QuarkPlatformPkg/Acpi/Dxe/AcpiPlatform/AcpiPlatform.inf\r
+INF RuleOverride = ACPITABLE QuarkPlatformPkg/Acpi/AcpiTables/AcpiTables.inf\r
+\r
+#\r
+# SMM\r
+#\r
+INF MdeModulePkg/Core/PiSmmCore/PiSmmIpl.inf\r
+INF MdeModulePkg/Core/PiSmmCore/PiSmmCore.inf\r
+INF UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf\r
+INF UefiCpuPkg/CpuIo2Smm/CpuIo2Smm.inf\r
+INF QuarkSocPkg/QuarkNorthCluster/Smm/Dxe/SmmControlDxe/SmmControlDxe.inf\r
+INF QuarkSocPkg/QuarkNorthCluster/Smm/DxeSmm/QncSmmDispatcher/QNCSmmDispatcher.inf\r
+INF QuarkPlatformPkg/Acpi/DxeSmm/AcpiSmm/AcpiSmmPlatform.inf\r
+INF QuarkPlatformPkg/Acpi/DxeSmm/SmmPowerManagement/SmmPowerManagement.inf\r
+INF MdeModulePkg/Universal/LockBox/SmmLockBox/SmmLockBox.inf\r
+INF UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationSmm.inf\r
+\r
+#\r
+# SMBIOS\r
+#\r
+INF MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf\r
+INF QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/SmbiosMiscDxe.inf\r
+INF QuarkPlatformPkg/Platform/Dxe/MemorySubClass/MemorySubClass.inf\r
+\r
+#\r
+# PCI\r
+#\r
+INF QuarkPlatformPkg/Pci/Dxe/PciPlatform/PciPlatform.inf\r
+INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf\r
+INF QuarkSocPkg/QuarkSouthCluster/IohInit/Dxe/IohInitDxe.inf\r
+!if $(SOURCE_DEBUG_ENABLE)\r
+!else\r
+INF MdeModulePkg/Bus/Pci/PciSioSerialDxe/PciSioSerialDxe.inf\r
+!endif\r
+\r
+#\r
+# USB\r
+#\r
+!if $(PERFORMANCE_ENABLE)\r
+!else\r
+INF MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf\r
+INF QuarkSocPkg/QuarkSouthCluster/Usb/Ohci/Dxe/OhciDxe.inf\r
+INF MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf\r
+INF MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf\r
+INF MdeModulePkg/Bus/Usb/UsbMouseDxe/UsbMouseDxe.inf\r
+INF MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf\r
+!endif\r
+\r
+#\r
+# SDIO\r
+#\r
+!if $(PERFORMANCE_ENABLE)\r
+!else\r
+INF QuarkSocPkg/QuarkSouthCluster/Sdio/Dxe/SDControllerDxe/SDControllerDxe.inf\r
+INF QuarkSocPkg/QuarkSouthCluster/Sdio/Dxe/SDMediaDeviceDxe/SDMediaDeviceDxe.inf\r
+!endif\r
+\r
+#\r
+# Console\r
+#\r
+INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf\r
+INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf\r
+INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf\r
+\r
+INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf\r
+INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf\r
+INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf\r
+INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf\r
+\r
+#\r
+# File System Modules\r
+#\r
+!if $(PERFORMANCE_ENABLE)\r
+INF MdeModulePkg/Universal/FvSimpleFileSystemDxe/FvSimpleFileSystemDxe.inf\r
+!else\r
+INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf\r
+INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf\r
+INF FatPkg/EnhancedFatDxe/Fat.inf\r
+!endif\r
+\r
+################################################################################\r
+#\r
+# FV Section\r
+#\r
+# [FV] section is used to define what components or modules are placed within a flash\r
+# device file. This section also defines order the components and modules are positioned\r
+# within the image. The [FV] section consists of define statements, set statements and\r
+# module statements.\r
+#\r
+################################################################################\r
+[FV.FVMAIN_COMPACT]\r
+FvAlignment = 16\r
+ERASE_POLARITY = 1\r
+MEMORY_MAPPED = TRUE\r
+STICKY_WRITE = TRUE\r
+LOCK_CAP = TRUE\r
+LOCK_STATUS = TRUE\r
+WRITE_DISABLED_CAP = TRUE\r
+WRITE_ENABLED_CAP = TRUE\r
+WRITE_STATUS = TRUE\r
+WRITE_LOCK_CAP = TRUE\r
+WRITE_LOCK_STATUS = TRUE\r
+READ_DISABLED_CAP = TRUE\r
+READ_ENABLED_CAP = TRUE\r
+READ_STATUS = TRUE\r
+READ_LOCK_CAP = TRUE\r
+READ_LOCK_STATUS = TRUE\r
+\r
+FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 {\r
+ SECTION GUIDED A31280AD-481E-41B6-95E8-127F4C984779 { # TIANO COMPRESS GUID\r
+ SECTION FV_IMAGE = FVMAIN\r
+ }\r
+}\r
+\r
+################################################################################\r
+#\r
+# FV Section\r
+#\r
+# [FV] section is used to define what components or modules are placed within a flash\r
+# device file. This section also defines order the components and modules are positioned\r
+# within the image. The [FV] section consists of define statements, set statements and\r
+# module statements.\r
+#\r
+################################################################################\r
+[FV.PAYLOAD]\r
+BlockSize = $(FLASH_BLOCKSIZE)\r
+FvAlignment = 16 #FV alignment and FV attributes setting.\r
+ERASE_POLARITY = 1\r
+MEMORY_MAPPED = TRUE\r
+STICKY_WRITE = TRUE\r
+LOCK_CAP = TRUE\r
+LOCK_STATUS = TRUE\r
+WRITE_DISABLED_CAP = TRUE\r
+WRITE_ENABLED_CAP = TRUE\r
+WRITE_STATUS = TRUE\r
+WRITE_LOCK_CAP = TRUE\r
+WRITE_LOCK_STATUS = TRUE\r
+READ_DISABLED_CAP = TRUE\r
+READ_ENABLED_CAP = TRUE\r
+READ_STATUS = TRUE\r
+READ_LOCK_CAP = TRUE\r
+READ_LOCK_STATUS = TRUE\r
+\r
+#\r
+# Shell and Applications\r
+#\r
+INF RuleOverride = TIANOCOMPRESSED ShellPkg/Application/Shell/Shell.inf\r
+!if $(PERFORMANCE_ENABLE)\r
+INF RuleOverride = TIANOCOMPRESSED PerformancePkg/Dp_App/Dp.inf\r
+!endif\r
+\r
+################################################################################\r
+#\r
+# Rules are use with the [FV] section's module INF type to define\r
+# how an FFS file is created for a given INF file. The following Rule are the default\r
+# rules for the different module type. User can add the customized rules to define the\r
+# content of the FFS file.\r
+#\r
+################################################################################\r
+[Rule.Common.SEC]\r
+ FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED {\r
+ TE TE Align = 8 $(INF_OUTPUT)/$(MODULE_NAME).efi\r
+ RAW BIN Align = 16 |.com\r
+ }\r
+\r
+[Rule.Common.PEI_CORE]\r
+ FILE PEI_CORE = $(NAMED_GUID) {\r
+ TE TE $(INF_OUTPUT)/$(MODULE_NAME).efi\r
+ UI STRING="$(MODULE_NAME)" Optional\r
+ VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)\r
+ }\r
+\r
+[Rule.Common.PEIM.NORELOC]\r
+ FILE PEIM = $(NAMED_GUID) RELOCS_STRIPPED {\r
+ PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex\r
+ TE TE $(INF_OUTPUT)/$(MODULE_NAME).efi\r
+ UI STRING="$(MODULE_NAME)" Optional\r
+ VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)\r
+ }\r
+\r
+[Rule.Common.PEIM]\r
+ FILE PEIM = $(NAMED_GUID) {\r
+ PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex\r
+ TE TE $(INF_OUTPUT)/$(MODULE_NAME).efi\r
+ UI STRING="$(MODULE_NAME)" Optional\r
+ VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)\r
+ }\r
+\r
+[Rule.Common.DXE_CORE]\r
+ FILE DXE_CORE = $(NAMED_GUID) {\r
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi\r
+ UI STRING="$(MODULE_NAME)" Optional\r
+ VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)\r
+ }\r
+\r
+[Rule.Common.UEFI_DRIVER]\r
+ FILE DRIVER = $(NAMED_GUID) {\r
+ DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex\r
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi\r
+ UI STRING="$(MODULE_NAME)" Optional\r
+ VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)\r
+ }\r
+\r
+[Rule.Common.DXE_DRIVER]\r
+ FILE DRIVER = $(NAMED_GUID) {\r
+ DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex\r
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi\r
+ UI STRING="$(MODULE_NAME)" Optional\r
+ VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)\r
+ }\r
+\r
+[Rule.Common.DXE_RUNTIME_DRIVER]\r
+ FILE DRIVER = $(NAMED_GUID) {\r
+ DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex\r
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi\r
+ UI STRING="$(MODULE_NAME)" Optional\r
+ VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)\r
+ }\r
+\r
+[Rule.Common.DXE_SMM_DRIVER]\r
+ FILE SMM = $(NAMED_GUID) {\r
+ SMM_DEPEX SMM_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex\r
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi\r
+ UI STRING="$(MODULE_NAME)" Optional\r
+ VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)\r
+ }\r
+\r
+[Rule.Common.SMM_CORE]\r
+ FILE SMM_CORE = $(NAMED_GUID) {\r
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi\r
+ UI STRING="$(MODULE_NAME)" Optional\r
+ VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)\r
+ }\r
+\r
+[Rule.Common.UEFI_APPLICATION]\r
+ FILE APPLICATION = $(NAMED_GUID) {\r
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi\r
+ UI STRING="$(MODULE_NAME)" Optional\r
+ VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)\r
+ }\r
+\r
+[Rule.Common.UEFI_APPLICATION.TIANOCOMPRESSED]\r
+ FILE APPLICATION = $(NAMED_GUID) {\r
+ UI STRING="$(MODULE_NAME)" Optional\r
+ VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)\r
+ SECTION GUIDED A31280AD-481E-41B6-95E8-127F4C984779 PROCESSING_REQUIRED = TRUE { # TIANO COMPRESS GUID\r
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi\r
+ }\r
+ }\r
+\r
+[Rule.Common.UEFI_APPLICATION.UI]\r
+ FILE APPLICATION = $(NAMED_GUID) {\r
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi\r
+ UI STRING="Enter Setup"\r
+ VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)\r
+ }\r
+\r
+[Rule.Common.USER_DEFINED.ACPITABLE]\r
+ FILE FREEFORM = $(NAMED_GUID) {\r
+ RAW ACPI |.acpi\r
+ RAW ASL |.aml\r
+ }\r
--- /dev/null
+## @file\r
+# Clanton Peak CRB platform with 32-bit DXE for 4MB/8MB flash devices.\r
+#\r
+# This package provides Clanton Peak CRB platform specific modules.\r
+# Copyright (c) 2013 - 2014 Intel Corporation.\r
+#\r
+# This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution. The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php\r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+##\r
+\r
+################################################################################\r
+#\r
+# Defines Section - statements that will be processed to create a Makefile.\r
+#\r
+################################################################################\r
+[Defines]\r
+ DSC_SPECIFICATION = 0x00010005\r
+ PLATFORM_NAME = QuarkMin\r
+ PLATFORM_GUID = 2655F3CF-4CC7-4e17-A62D-77FE3F10AE7F\r
+ PLATFORM_VERSION = 0.1\r
+ FLASH_DEFINITION = QuarkPlatformPkg/QuarkMin.fdf\r
+ OUTPUT_DIRECTORY = Build/QuarkMin\r
+ SUPPORTED_ARCHITECTURES = IA32\r
+ BUILD_TARGETS = DEBUG|RELEASE\r
+ SKUID_IDENTIFIER = DEFAULT\r
+ VPD_TOOL_GUID = 8C3D856A-9BE6-468E-850A-24F7A8D38E08\r
+\r
+ #\r
+ # Platform On/Off features are defined here\r
+ #\r
+ DEFINE GALILEO = GEN2\r
+ DEFINE SECURE_BOOT_ENABLE = FALSE\r
+ DEFINE SOURCE_DEBUG_ENABLE = FALSE\r
+ DEFINE PERFORMANCE_ENABLE = FALSE\r
+ DEFINE LOGGING = FALSE\r
+\r
+ !if $(TARGET) == "DEBUG"\r
+ DEFINE LOGGING = TRUE\r
+ !endif\r
+\r
+ !if $(PERFORMANCE_ENABLE)\r
+ DEFINE SOURCE_DEBUG_ENABLE = FALSE\r
+ DEFINE LOGGING = FALSE\r
+ !endif\r
+\r
+################################################################################\r
+#\r
+# SKU Identification section - list of all SKU IDs supported by this\r
+# Platform.\r
+#\r
+################################################################################\r
+[SkuIds]\r
+ 0|DEFAULT # The entry: 0|DEFAULT is reserved and always required.\r
+\r
+################################################################################\r
+#\r
+# Library Class section - list of all Library Classes needed by this Platform.\r
+#\r
+################################################################################\r
+[LibraryClasses]\r
+ #\r
+ # Entry point\r
+ #\r
+ PeiCoreEntryPoint|MdePkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.inf\r
+ PeimEntryPoint|MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf\r
+ DxeCoreEntryPoint|MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf\r
+ UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf\r
+ UefiApplicationEntryPoint|MdePkg/Library/UefiApplicationEntryPoint/UefiApplicationEntryPoint.inf\r
+\r
+ #\r
+ # Basic\r
+ #\r
+ BaseLib|MdePkg/Library/BaseLib/BaseLib.inf\r
+ BaseMemoryLib|MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf\r
+ PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf\r
+ CpuLib|MdePkg/Library/BaseCpuLib/BaseCpuLib.inf\r
+ CpuExceptionHandlerLib|UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf\r
+ IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf\r
+ PciLib|MdePkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf\r
+ PciCf8Lib|MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf\r
+ PciExpressLib|MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf\r
+ CacheMaintenanceLib|MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf\r
+ PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf\r
+!if $(SOURCE_DEBUG_ENABLE)\r
+ PeCoffExtraActionLib|SourceLevelDebugPkg/Library/PeCoffExtraActionLibDebug/PeCoffExtraActionLibDebug.inf\r
+ DebugCommunicationLib|SourceLevelDebugPkg/Library/DebugCommunicationLibSerialPort/DebugCommunicationLibSerialPort.inf\r
+!else\r
+ PeCoffExtraActionLib|MdePkg/Library/BasePeCoffExtraActionLibNull/BasePeCoffExtraActionLibNull.inf\r
+!endif\r
+ DebugAgentLib|MdeModulePkg/Library/DebugAgentLibNull/DebugAgentLibNull.inf\r
+ PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf\r
+\r
+ #\r
+ # UEFI & PI\r
+ #\r
+ UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf\r
+ UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf\r
+ UefiRuntimeLib|MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf\r
+ UefiLib|MdePkg/Library/UefiLib/UefiLib.inf\r
+ HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf\r
+ UefiHiiServicesLib|MdeModulePkg/Library/UefiHiiServicesLib/UefiHiiServicesLib.inf\r
+ DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf\r
+ UefiDecompressLib|IntelFrameworkModulePkg/Library/BaseUefiTianoCustomDecompressLib/BaseUefiTianoCustomDecompressLib.inf\r
+ PeiServicesTablePointerLib|MdePkg/Library/PeiServicesTablePointerLibIdt/PeiServicesTablePointerLibIdt.inf\r
+ PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf\r
+ DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf\r
+ DxeServicesTableLib|MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf\r
+ UefiCpuLib|UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.inf\r
+ SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf\r
+\r
+ #\r
+ # Generic Modules\r
+ #\r
+ S3BootScriptLib|MdeModulePkg/Library/PiDxeS3BootScriptLib/DxeS3BootScriptLib.inf\r
+ S3IoLib|MdePkg/Library/BaseS3IoLib/BaseS3IoLib.inf\r
+ S3PciLib|MdePkg/Library/BaseS3PciLib/BaseS3PciLib.inf\r
+ UefiUsbLib|MdePkg/Library/UefiUsbLib/UefiUsbLib.inf\r
+ UefiScsiLib|MdePkg/Library/UefiScsiLib/UefiScsiLib.inf\r
+ NetLib|MdeModulePkg/Library/DxeNetLib/DxeNetLib.inf\r
+ IpIoLib|MdeModulePkg/Library/DxeIpIoLib/DxeIpIoLib.inf\r
+ UdpIoLib|MdeModulePkg/Library/DxeUdpIoLib/DxeUdpIoLib.inf\r
+ DpcLib|MdeModulePkg/Library/DxeDpcLib/DxeDpcLib.inf\r
+ OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.inf\r
+ SynchronizationLib|MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf\r
+ SecurityManagementLib|MdeModulePkg/Library/DxeSecurityManagementLib/DxeSecurityManagementLib.inf\r
+ SmmCorePlatformHookLib|MdeModulePkg/Library/SmmCorePlatformHookLibNull/SmmCorePlatformHookLibNull.inf\r
+ PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf\r
+ HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf\r
+ MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf\r
+ ReportStatusCodeLib|MdePkg/Library/BaseReportStatusCodeLibNull/BaseReportStatusCodeLibNull.inf\r
+ ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf\r
+ LockBoxLib|MdeModulePkg/Library/LockBoxNullLib/LockBoxNullLib.inf\r
+ VarCheckLib|MdeModulePkg/Library/VarCheckLib/VarCheckLib.inf\r
+ DebugPrintErrorLevelLib|MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.inf\r
+!if $(LOGGING)\r
+ DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf\r
+!else\r
+ DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf\r
+!endif\r
+!if $(PERFORMANCE_ENABLE)\r
+ PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf\r
+!else\r
+ PerformanceLib|MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibNull.inf\r
+!endif\r
+!if $(SECURE_BOOT_ENABLE)\r
+ BaseCryptLib|CryptoPkg/Library/BaseCryptLib/BaseCryptLib.inf\r
+ PlatformSecureLib|QuarkPlatformPkg/Library/PlatformSecureLib/PlatformSecureLib.inf\r
+ IntrinsicLib|CryptoPkg/Library/IntrinsicLib/IntrinsicLib.inf\r
+ OpensslLib|CryptoPkg/Library/OpensslLib/OpensslLib.inf\r
+ TpmMeasurementLib|SecurityPkg/Library/DxeTpmMeasurementLib/DxeTpmMeasurementLib.inf\r
+ AuthVariableLib|SecurityPkg/Library/AuthVariableLib/AuthVariableLib.inf\r
+!else\r
+ TpmMeasurementLib|MdeModulePkg/Library/TpmMeasurementLibNull/TpmMeasurementLibNull.inf\r
+ AuthVariableLib|MdeModulePkg/Library/AuthVariableLibNull/AuthVariableLibNull.inf\r
+!endif\r
+\r
+ #\r
+ # CPU\r
+ #\r
+ MtrrLib|QuarkSocPkg/QuarkNorthCluster/Library/MtrrLib/MtrrLib.inf\r
+ LocalApicLib|UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.inf\r
+\r
+ #\r
+ # Quark North Cluster\r
+ #\r
+ SmmLib|QuarkSocPkg/QuarkNorthCluster/Library/QNCSmmLib/QNCSmmLib.inf\r
+ SmbusLib|QuarkSocPkg/QuarkNorthCluster/Library/SmbusLib/SmbusLib.inf\r
+ TimerLib|PcAtChipsetPkg/Library/AcpiTimerLib/DxeAcpiTimerLib.inf\r
+ ResetSystemLib|QuarkSocPkg/QuarkNorthCluster/Library/ResetSystemLib/ResetSystemLib.inf\r
+ IntelQNCLib|QuarkSocPkg/QuarkNorthCluster/Library/IntelQNCLib/IntelQNCLib.inf\r
+ QNCAccessLib|QuarkSocPkg/QuarkNorthCluster/Library/QNCAccessLib/QNCAccessLib.inf\r
+ IoApicLib|PcAtChipsetPkg/Library/BaseIoApicLib/BaseIoApicLib.inf\r
+\r
+ #\r
+ # Quark South Cluster\r
+ #\r
+ IohLib|QuarkSocPkg/QuarkSouthCluster/Library/IohLib/IohLib.inf\r
+ I2cLib|QuarkSocPkg/QuarkSouthCluster/Library/I2cLib/I2cLib.inf\r
+ SerialPortLib|MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.inf\r
+ PlatformHookLib|MdeModulePkg/Library/BasePlatformHookLibNull/BasePlatformHookLibNull.inf\r
+\r
+ #\r
+ # Quark Platform\r
+ #\r
+ RecoveryOemHookLib|QuarkPlatformPkg/Library/RecoveryOemHookLib/RecoveryOemHookLib.inf\r
+ PlatformSecLib|QuarkPlatformPkg/Library/PlatformSecLib/PlatformSecLib.inf\r
+ PlatformPcieHelperLib|QuarkPlatformPkg/Library/PlatformPcieHelperLib/PlatformPcieHelperLib.inf\r
+ PlatformHelperLib|QuarkPlatformPkg/Library/PlatformHelperLib/DxePlatformHelperLib.inf\r
+\r
+[LibraryClasses.common.SEC]\r
+ #\r
+ # SEC specific phase\r
+ #\r
+ ReportStatusCodeLib|MdePkg/Library/BaseReportStatusCodeLibNull/BaseReportStatusCodeLibNull.inf\r
+ PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf\r
+ TimerLib|PcAtChipsetPkg/Library/AcpiTimerLib/BaseAcpiTimerLib.inf\r
+ HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf\r
+ MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf\r
+ CpuExceptionHandlerLib|UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHandlerLib.inf\r
+\r
+[LibraryClasses.IA32.PEIM,LibraryClasses.IA32.PEI_CORE]\r
+ #\r
+ # PEI phase common\r
+ #\r
+ PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf\r
+ HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf\r
+ MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf\r
+ ReportStatusCodeLib|MdePkg/Library/BaseReportStatusCodeLibNull/BaseReportStatusCodeLibNull.inf\r
+ ExtractGuidedSectionLib|MdePkg/Library/PeiExtractGuidedSectionLib/PeiExtractGuidedSectionLib.inf\r
+ LockBoxLib|MdeModulePkg/Library/LockBoxNullLib/LockBoxNullLib.inf\r
+ TimerLib|PcAtChipsetPkg/Library/AcpiTimerLib/BaseAcpiTimerLib.inf\r
+ PlatformHelperLib|QuarkPlatformPkg/Library/PlatformHelperLib/PeiPlatformHelperLib.inf\r
+ CpuExceptionHandlerLib|UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHandlerLib.inf\r
+!if $(SECURE_BOOT_ENABLE)\r
+ BaseCryptLib|CryptoPkg/Library/BaseCryptLib/PeiCryptLib.inf\r
+!endif\r
+!if $(PERFORMANCE_ENABLE)\r
+ PerformanceLib|MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanceLib.inf\r
+!endif\r
+\r
+[LibraryClasses.IA32.DXE_CORE]\r
+ HobLib|MdePkg/Library/DxeCoreHobLib/DxeCoreHobLib.inf\r
+ MemoryAllocationLib|MdeModulePkg/Library/DxeCoreMemoryAllocationLib/DxeCoreMemoryAllocationLib.inf\r
+ CpuExceptionHandlerLib|UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf\r
+!if $(PERFORMANCE_ENABLE)\r
+ PerformanceLib|MdeModulePkg/Library/DxeCorePerformanceLib/DxeCorePerformanceLib.inf\r
+!endif\r
+\r
+[LibraryClasses.IA32.DXE_SMM_DRIVER]\r
+ SmmServicesTableLib|MdePkg/Library/SmmServicesTableLib/SmmServicesTableLib.inf\r
+ ReportStatusCodeLib|MdePkg/Library/BaseReportStatusCodeLibNull/BaseReportStatusCodeLibNull.inf\r
+ MemoryAllocationLib|MdePkg/Library/SmmMemoryAllocationLib/SmmMemoryAllocationLib.inf\r
+ LockBoxLib|MdeModulePkg/Library/LockBoxNullLib/LockBoxNullLib.inf\r
+ PciLib|MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf\r
+ CpuExceptionHandlerLib|UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmCpuExceptionHandlerLib.inf\r
+ SmmMemLib|MdePkg/Library/SmmMemLib/SmmMemLib.inf\r
+!if $(SECURE_BOOT_ENABLE)\r
+ BaseCryptLib|CryptoPkg/Library/BaseCryptLib/SmmCryptLib.inf\r
+!endif\r
+!if $(PERFORMANCE_ENABLE)\r
+ PerformanceLib|MdeModulePkg/Library/SmmPerformanceLib/SmmPerformanceLib.inf\r
+!endif\r
+\r
+[LibraryClasses.IA32.SMM_CORE]\r
+ SmmServicesTableLib|MdeModulePkg/Library/PiSmmCoreSmmServicesTableLib/PiSmmCoreSmmServicesTableLib.inf\r
+ ReportStatusCodeLib|MdePkg/Library/BaseReportStatusCodeLibNull/BaseReportStatusCodeLibNull.inf\r
+ MemoryAllocationLib|MdeModulePkg/Library/PiSmmCoreMemoryAllocationLib/PiSmmCoreMemoryAllocationLib.inf\r
+ PciLib|MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf\r
+ SmmMemLib|MdePkg/Library/SmmMemLib/SmmMemLib.inf\r
+!if $(SECURE_BOOT_ENABLE)\r
+ BaseCryptLib|CryptoPkg/Library/BaseCryptLib/SmmCryptLib.inf\r
+!endif\r
+!if $(PERFORMANCE_ENABLE)\r
+ PerformanceLib|MdeModulePkg/Library/SmmCorePerformanceLib/SmmCorePerformanceLib.inf\r
+!endif\r
+\r
+[LibraryClasses.IA32.DXE_RUNTIME_DRIVER]\r
+ ReportStatusCodeLib|MdePkg/Library/BaseReportStatusCodeLibNull/BaseReportStatusCodeLibNull.inf\r
+ QNCAccessLib|QuarkSocPkg/QuarkNorthCluster/Library/QNCAccessLib/RuntimeQNCAccessLib.inf\r
+ PciLib|MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf\r
+!if $(SECURE_BOOT_ENABLE)\r
+ BaseCryptLib|CryptoPkg/Library/BaseCryptLib/RuntimeCryptLib.inf\r
+!endif\r
+\r
+[LibraryClasses.IA32.UEFI_DRIVER,LibraryClasses.IA32.UEFI_APPLICATION]\r
+ PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf\r
+\r
+################################################################################\r
+#\r
+# Pcd Section - list of all EDK II PCD Entries defined by this Platform\r
+#\r
+################################################################################\r
+[PcdsFeatureFlag]\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdDevicePathSupportDevicePathToText|TRUE\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdDevicePathSupportDevicePathFromText|TRUE\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSupportUpdateCapsuleReset|TRUE\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdDxeIplSwitchToLongMode|FALSE\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdPciBusHotplugDeviceSupport|FALSE\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdInstallAcpiSdtProtocol|TRUE\r
+!if $(SOURCE_DEBUG_ENABLE)\r
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmDebug|TRUE\r
+!endif\r
+\r
+!if $(TARGET) == "RELEASE"\r
+ gQuarkPlatformTokenSpaceGuid.WaitIfResetDueToError|FALSE\r
+!else\r
+ gQuarkPlatformTokenSpaceGuid.WaitIfResetDueToError|TRUE\r
+!endif\r
+\r
+[PcdsFixedAtBuild]\r
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber|1\r
+ gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdS3AcpiReservedMemorySize|0x20000\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|FALSE\r
+!if $(LOGGING)\r
+ !if $(SOURCE_DEBUG_ENABLE)\r
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x17\r
+ !else\r
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x27\r
+ !endif\r
+ gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07\r
+!else\r
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x0\r
+ gEfiMdePkgTokenSpaceGuid.PcdPostCodePropertyMask|0x0\r
+ gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x3\r
+!endif\r
+ gEfiMdePkgTokenSpaceGuid.PcdPostCodePropertyMask|0x18\r
+ gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xE0000000\r
+!if $(GALILEO) == GEN1\r
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|460800\r
+!endif\r
+!if $(GALILEO) == GEN2\r
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|921600\r
+!endif\r
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits|8\r
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity|1\r
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits|1\r
+ gEfiMdePkgTokenSpaceGuid.PcdDefaultTerminalType|0\r
+!if $(PERFORMANCE_ENABLE)\r
+ gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|0x1\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdMaxPeiPerformanceLogEntries|80\r
+!else\r
+ gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|0x00\r
+!endif\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdLoadModuleAtFixAddressEnable|0\r
+!if $(SECURE_BOOT_ENABLE)\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x2000\r
+!endif\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdHwErrStorageSize|0x00002000\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdMaxHardwareErrorVariableSize|0x1000\r
+ ## RTC Update Timeout Value, need to increase timeout since also\r
+ # waiting for RTC to be busy.\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdRealTimeClockUpdateTimeout|500000\r
+\r
+!if $(SECURE_BOOT_ENABLE)\r
+ # override the default values from SecurityPkg to ensure images from all sources are verified in secure boot\r
+ gEfiSecurityPkgTokenSpaceGuid.PcdOptionRomImageVerificationPolicy|0x04\r
+ gEfiSecurityPkgTokenSpaceGuid.PcdFixedMediaImageVerificationPolicy|0x04\r
+ gEfiSecurityPkgTokenSpaceGuid.PcdRemovableMediaImageVerificationPolicy|0x04\r
+!endif\r
+ gQuarkPlatformTokenSpaceGuid.PcdEsramStage1Base|0x80000000\r
+\r
+!if $(SOURCE_DEBUG_ENABLE)\r
+ gEfiSourceLevelDebugPkgTokenSpaceGuid.PcdDebugLoadImageMethod|0x2\r
+!endif\r
+\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseMmio|TRUE\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x9000B000\r
+!if $(GALILEO) == GEN1\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialBaudRate|460800\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseHardwareFlowControl|FALSE\r
+!endif\r
+!if $(GALILEO) == GEN2\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialBaudRate|921600\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseHardwareFlowControl|FALSE\r
+!endif\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialLineControl|0x03\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialFifoControl|0x07\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialDetectCable|FALSE\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialClockRate|44236800\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialPciDeviceInfo|{0x14, 0x05, 0x84, 0x00, 0xFF}\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterStride|4\r
+\r
+ #\r
+ # typedef struct {\r
+ # UINT16 VendorId; ///< Vendor ID to match the PCI device. The value 0xFFFF terminates the list of entries.\r
+ # UINT16 DeviceId; ///< Device ID to match the PCI device\r
+ # UINT32 ClockRate; ///< UART clock rate. Set to 0 for default clock rate of 1843200 Hz\r
+ # UINT64 Offset; ///< The byte offset into to the BAR\r
+ # UINT8 BarIndex; ///< Which BAR to get the UART base address\r
+ # UINT8 RegisterStride; ///< UART register stride in bytes. Set to 0 for default register stride of 1 byte.\r
+ # UINT16 ReceiveFifoDepth; ///< UART receive FIFO depth in bytes. Set to 0 for a default FIFO depth of 16 bytes.\r
+ # UINT16 TransmitFifoDepth; ///< UART transmit FIFO depth in bytes. Set to 0 for a default FIFO depth of 16 bytes.\r
+ # UINT8 Reserved[2];\r
+ # } PCI_SERIAL_PARAMETER;\r
+ #\r
+ # Vendor 8086 Device 0936 Prog Interface 2, BAR #0, Offset 0, Stride = 4, Clock 44236800 (0x2a300000)\r
+ # Vendor 8086 Device 0936 Prog Interface 2, BAR #0, Offset 0, Stride = 4, Clock 44236800 (0x2a300000)\r
+ #\r
+ # [Vendor] [Device] [---ClockRate---] [------------Offset-----------] [Bar] [Stride] [RxFifo] [TxFifo] [Rsvd] [Vendor]\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdPciSerialParameters|{0x86,0x80, 0x36,0x09, 0x0,0x0,0xA3,0x02, 0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0, 0x00, 0x04, 0x0,0x0, 0x0,0x0, 0x0,0x0, 0xff,0xff}\r
+\r
+ gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciBusNumber |0\r
+ gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciDeviceNumber |31\r
+ gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciFunctionNumber |0\r
+ gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciEnableRegisterOffset|0x4b\r
+ gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoBarEnableMask |0x80\r
+ gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciBarRegisterOffset |0x48\r
+ gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPortBaseAddress |0x1000\r
+ gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiPm1TmrOffset |0x0008\r
+\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdBootManagerMenuFile|{ 0x21, 0xaa, 0x2c, 0x46, 0x14, 0x76, 0x03, 0x45, 0x83, 0x6e, 0x8a, 0xb6, 0xf4, 0x66, 0x23, 0x31 }\r
+\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdConInConnectOnDemand|FALSE\r
+\r
+[PcdsPatchableInModule]\r
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x803000C7\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdVpdBaseAddress|0x0\r
+\r
+[PcdsDynamicExHii.common.DEFAULT]\r
+!if $(PERFORMANCE_ENABLE)\r
+ gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVariableGuid|0x0|0\r
+!else\r
+ gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVariableGuid|0x0|5\r
+!endif\r
+ gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdBootState|L"BootState"|gQuarkPlatformTokenSpaceGuid|0x0|TRUE\r
+\r
+[PcdsDynamicExDefault.common.DEFAULT]\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateDataPtr|0x0\r
+ gQuarkPlatformTokenSpaceGuid.PcdEnableFastBoot|TRUE\r
+ gQuarkPlatformTokenSpaceGuid.PcdUserIsPhysicallyPresent|FALSE\r
+ gQuarkPlatformTokenSpaceGuid.PcdSpiFlashDeviceSize|0\r
+\r
+[PcdsDynamicExVpd]\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVendor|*|32|L"EDK II"\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareRevision|*|0x01000400\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|*|64|L"Galileo 1.0.4"\r
+\r
+#\r
+# ClantonPeakSVP\r
+# gQuarkPlatformTokenSpaceGuid.PcdPlatformType|*|0x0002\r
+# gQuarkPlatformTokenSpaceGuid.PcdPlatformTypeName|*|64|L"ClantonPeakSVP"\r
+# gEfiQuarkNcSocIdTokenSpaceGuid.PcdMrcParameters|*|40|{0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x01, 0x01, 0x00, 0x03, 0x00, 0x00, 0x02, 0x00, 0x00, 0x01, 0x01, 0x03, 0x7c, 0x92, 0x00, 0x00, 0x10, 0x27, 0x00, 0x00, 0x10, 0x27, 0x00, 0x00, 0x40, 0x9c, 0x00, 0x00, 0x06}\r
+#\r
+# KipsBay\r
+# gQuarkPlatformTokenSpaceGuid.PcdPlatformType|*|0x0003\r
+# gQuarkPlatformTokenSpaceGuid.PcdPlatformTypeName|*|64|L"KipsBay"\r
+# gEfiQuarkNcSocIdTokenSpaceGuid.PcdMrcParameters|*|40|{0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x01, 0x00, 0x03, 0x00, 0x00, 0x02, 0x00, 0x00, 0x01, 0x01, 0x01, 0x7c, 0x92, 0x00, 0x00, 0x10, 0x27, 0x00, 0x00, 0x10, 0x27, 0x00, 0x00, 0x40, 0x9c, 0x00, 0x00, 0x06}\r
+#\r
+# CrossHill\r
+# gQuarkPlatformTokenSpaceGuid.PcdPlatformType|*|0x0004\r
+# gQuarkPlatformTokenSpaceGuid.PcdPlatformTypeName|*|64|L"CrossHill"\r
+# gEfiQuarkNcSocIdTokenSpaceGuid.PcdMrcParameters|*|40|{0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x01, 0x00, 0x03, 0x00, 0x00, 0x02, 0x00, 0x00, 0x01, 0x01, 0x03, 0x7c, 0x92, 0x00, 0x00, 0x10, 0x27, 0x00, 0x00, 0x10, 0x27, 0x00, 0x00, 0x40, 0x9c, 0x00, 0x00, 0x06}\r
+#\r
+# ClantonHill\r
+# gQuarkPlatformTokenSpaceGuid.PcdPlatformType|*|0x0005\r
+# gQuarkPlatformTokenSpaceGuid.PcdPlatformTypeName|*|64|L"ClantonHill"\r
+# gEfiQuarkNcSocIdTokenSpaceGuid.PcdMrcParameters|*|40|{0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x01, 0x00, 0x03, 0x00, 0x00, 0x02, 0x00, 0x00, 0x01, 0x01, 0x02, 0x7c, 0x92, 0x00, 0x00, 0x10, 0x27, 0x00, 0x00, 0x10, 0x27, 0x00, 0x00, 0x40, 0x9c, 0x00, 0x00, 0x06}\r
+#\r
+# Galileo\r
+# gQuarkPlatformTokenSpaceGuid.PcdPlatformType|*|0x0006\r
+# gQuarkPlatformTokenSpaceGuid.PcdPlatformTypeName|*|64|L"Galileo"\r
+# gEfiQuarkNcSocIdTokenSpaceGuid.PcdMrcParameters|*|40|{0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x01, 0x00, 0x03, 0x00, 0x00, 0x02, 0x00, 0x00, 0x01, 0x01, 0x01, 0x7c, 0x92, 0x00, 0x00, 0x10, 0x27, 0x00, 0x00, 0x10, 0x27, 0x00, 0x00, 0x40, 0x9c, 0x00, 0x00, 0x06}\r
+#\r
+# GalileoGen2\r
+# gQuarkPlatformTokenSpaceGuid.PcdPlatformType|*|0x0008\r
+# gQuarkPlatformTokenSpaceGuid.PcdPlatformTypeName|*|64|L"GalileoGen2"\r
+# gEfiQuarkNcSocIdTokenSpaceGuid.PcdMrcParameters|*|40|{0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x01, 0x00, 0x03, 0x00, 0x00, 0x02, 0x00, 0x00, 0x01, 0x01, 0x01, 0x7c, 0x92, 0x00, 0x00, 0x10, 0x27, 0x00, 0x00, 0x10, 0x27, 0x00, 0x00, 0x40, 0x9c, 0x00, 0x00, 0x06}\r
+#\r
+!if $(GALILEO) == GEN1\r
+ gQuarkPlatformTokenSpaceGuid.PcdPlatformType|*|0x0006\r
+ gQuarkPlatformTokenSpaceGuid.PcdPlatformTypeName|*|64|L"Galileo"\r
+ gEfiQuarkNcSocIdTokenSpaceGuid.PcdMrcParameters|*|40|{0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x01, 0x00, 0x03, 0x00, 0x00, 0x02, 0x00, 0x00, 0x01, 0x01, 0x01, 0x7c, 0x92, 0x00, 0x00, 0x10, 0x27, 0x00, 0x00, 0x10, 0x27, 0x00, 0x00, 0x40, 0x9c, 0x00, 0x00, 0x06}\r
+!endif\r
+!if $(GALILEO) == GEN2\r
+ gQuarkPlatformTokenSpaceGuid.PcdPlatformType|*|0x0008\r
+ gQuarkPlatformTokenSpaceGuid.PcdPlatformTypeName|*|64|L"GalileoGen2"\r
+ gEfiQuarkNcSocIdTokenSpaceGuid.PcdMrcParameters|*|40|{0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x01, 0x00, 0x03, 0x00, 0x00, 0x02, 0x00, 0x00, 0x01, 0x01, 0x01, 0x7c, 0x92, 0x00, 0x00, 0x10, 0x27, 0x00, 0x00, 0x10, 0x27, 0x00, 0x00, 0x40, 0x9c, 0x00, 0x00, 0x06}\r
+!endif\r
+ gEfiQuarkSCSocIdTokenSpaceGuid.PcdIohEthernetMac0|*|8|{0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\r
+ gEfiQuarkSCSocIdTokenSpaceGuid.PcdIohEthernetMac1|*|8|{0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\r
+\r
+###################################################################################################\r
+#\r
+# Components Section - list of the modules and components that will be processed by compilation\r
+# tools and the EDK II tools to generate PE32/PE32+/Coff image files.\r
+#\r
+# Note: The EDK II DSC file is not used to specify how compiled binary images get placed\r
+# into firmware volume images. This section is just a list of modules to compile from\r
+# source into UEFI-compliant binaries.\r
+# It is the FDF file that contains information on combining binary files into firmware\r
+# volume images, whose concept is beyond UEFI and is described in PI specification.\r
+# Binary modules do not need to be listed in this section, as they should be\r
+# specified in the FDF file. For example: Shell binary, FAT binary (Fat.efi),\r
+# Logo (Logo.bmp), and etc.\r
+# There may also be modules listed in this section that are not required in the FDF file,\r
+# When a module listed here is excluded from FDF file, then UEFI-compliant binary will be\r
+# generated for it, but the binary will not be put into any firmware volume.\r
+#\r
+###################################################################################################\r
+\r
+[Components.IA32]\r
+ #\r
+ # SEC Core\r
+ #\r
+ UefiCpuPkg/SecCore/SecCore.inf {\r
+ !if $(SOURCE_DEBUG_ENABLE)\r
+ <LibraryClasses>\r
+ PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf\r
+ DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/SecPeiDebugAgentLib.inf\r
+ ResetSystemLib|QuarkSocPkg/QuarkNorthCluster/Library/ResetSystemLib/ResetSystemLib.inf\r
+ !endif\r
+ }\r
+\r
+ #\r
+ # PEI Core\r
+ #\r
+ MdeModulePkg/Core/Pei/PeiMain.inf\r
+\r
+ #\r
+ # PEIM\r
+ #\r
+ MdeModulePkg/Universal/PCD/Pei/Pcd.inf {\r
+ <LibraryClasses>\r
+ PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf\r
+ }\r
+ MdeModulePkg/Universal/FaultTolerantWritePei/FaultTolerantWritePei.inf\r
+ MdeModulePkg/Universal/Variable/Pei/VariablePei.inf\r
+ MdeModulePkg/Universal/PcatSingleSegmentPciCfg2Pei/PcatSingleSegmentPciCfg2Pei.inf\r
+\r
+ QuarkSocPkg/QuarkNorthCluster/MemoryInit/Pei/MemoryInitPei.inf\r
+ QuarkPlatformPkg/Platform/Pei/PlatformInit/PlatformEarlyInit.inf\r
+ QuarkPlatformPkg/Platform/Pei/PlatformConfig/PlatformConfigPei.inf\r
+\r
+ MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf\r
+\r
+[Components.IA32]\r
+ #\r
+ # DXE Core\r
+ #\r
+ MdeModulePkg/Core/Dxe/DxeMain.inf\r
+\r
+!if $(SOURCE_DEBUG_ENABLE)\r
+ SourceLevelDebugPkg/DebugAgentDxe/DebugAgentDxe.inf {\r
+ <LibraryClasses>\r
+ DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/DxeDebugAgentLib.inf\r
+ ResetSystemLib|QuarkSocPkg/QuarkNorthCluster/Library/ResetSystemLib/ResetSystemLib.inf\r
+ }\r
+!endif\r
+\r
+\r
+ QuarkPlatformPkg/Platform/Dxe/PlatformInit/PlatformInitDxe.inf\r
+\r
+ #\r
+ # Components that produce the architectural protocols\r
+ #\r
+ MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf\r
+ UefiCpuPkg/CpuDxe/CpuDxe.inf\r
+ MdeModulePkg/Universal/Metronome/Metronome.inf\r
+ MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf\r
+ MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf\r
+ MdeModulePkg/Universal/Variable/EmuRuntimeDxe/EmuVariableRuntimeDxe.inf\r
+ MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf {\r
+ <LibraryClasses>\r
+ CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf\r
+ }\r
+ MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf\r
+ MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf\r
+ PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcatRealTimeClockRuntimeDxe.inf\r
+\r
+ #\r
+ # Following are the DXE drivers (alphabetical order)\r
+ #\r
+ MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf\r
+ MdeModulePkg/Universal/PCD/Dxe/Pcd.inf {\r
+ <LibraryClasses>\r
+ PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf\r
+ }\r
+\r
+ QuarkPlatformPkg/Pci/Dxe/PciHostBridge/PciHostBridge.inf\r
+ UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.inf\r
+\r
+ #\r
+ # Platform\r
+ #\r
+ MdeModulePkg/Universal/BdsDxe/BdsDxe.inf {\r
+ <LibraryClasses>\r
+ UefiBootManagerLib|MdeModulePkg/Library/UefiBootManagerLib/UefiBootManagerLib.inf\r
+ PlatformBootManagerLib|QuarkPlatformPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf\r
+ }\r
+\r
+ QuarkSocPkg/QuarkNorthCluster/QNCInit/Dxe/QNCInitDxe.inf\r
+ PcAtChipsetPkg/HpetTimerDxe/HpetTimerDxe.inf\r
+ QuarkPlatformPkg/Platform/Dxe/Setup/DxePlatform.inf\r
+ MdeModulePkg/Universal/MemoryTest/NullMemoryTestDxe/NullMemoryTestDxe.inf\r
+\r
+ #\r
+ # PCI\r
+ #\r
+ QuarkPlatformPkg/Pci/Dxe/PciPlatform/PciPlatform.inf\r
+ MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf\r
+ QuarkSocPkg/QuarkSouthCluster/IohInit/Dxe/IohInitDxe.inf\r
+ MdeModulePkg/Bus/Pci/PciSioSerialDxe/PciSioSerialDxe.inf\r
+\r
+ #\r
+ # Console\r
+ #\r
+ MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf\r
+ MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf {\r
+ <LibraryClasses>\r
+ PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf\r
+ }\r
+ MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf\r
+ MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf\r
+ MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf {\r
+ <LibraryClasses>\r
+ CustomizedDisplayLib|MdeModulePkg/Library/CustomizedDisplayLib/CustomizedDisplayLib.inf\r
+ }\r
+ MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf\r
+ MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf\r
+\r
+ #\r
+ # File System Modules\r
+ #\r
+ MdeModulePkg/Universal/FvSimpleFileSystemDxe/FvSimpleFileSystemDxe.inf\r
+\r
+ #\r
+ # Performance Application\r
+ #\r
+!if $(PERFORMANCE_ENABLE)\r
+ PerformancePkg/Dp_App/Dp.inf {\r
+ <LibraryClasses>\r
+ ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf\r
+ FileHandleLib|MdePkg/Library/UefiFileHandleLib/UefiFileHandleLib.inf\r
+ }\r
+!endif\r
+\r
+ ShellPkg/Application/Shell/Shell.inf {\r
+ <LibraryClasses>\r
+ ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellCommandLib.inf\r
+ NULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2CommandsLib.inf\r
+ NULL|ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1CommandsLib.inf\r
+ NULL|ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3CommandsLib.inf\r
+ NULL|ShellPkg/Library/UefiShellDriver1CommandsLib/UefiShellDriver1CommandsLib.inf\r
+ NULL|ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1CommandsLib.inf\r
+ NULL|ShellPkg/Library/UefiShellInstall1CommandsLib/UefiShellInstall1CommandsLib.inf\r
+ NULL|ShellPkg/Library/UefiShellNetwork1CommandsLib/UefiShellNetwork1CommandsLib.inf\r
+ HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingLib.inf\r
+ ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf\r
+ FileHandleLib|MdePkg/Library/UefiFileHandleLib/UefiFileHandleLib.inf\r
+ PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf\r
+ BcfgCommandLib|ShellPkg/Library/UefiShellBcfgCommandLib/UefiShellBcfgCommandLib.inf\r
+\r
+ <PcdsFixedAtBuild>\r
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0xFF\r
+ gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE\r
+ gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|8000\r
+ }\r
--- /dev/null
+## @file\r
+# FDF file of Clanton Peak CRB platform with 32-bit DXE\r
+#\r
+# This package provides QuarkNcSocId platform specific modules.\r
+# Copyright (c) 2013 - 2015 Intel Corporation.\r
+#\r
+# This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution. The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php\r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+##\r
+\r
+################################################################################\r
+#\r
+# Defines Section - statements that will be processed to create a Makefile.\r
+#\r
+################################################################################\r
+[Defines]\r
+# Address 0x100000000 (4 GB reset address)\r
+# Base Size\r
+# +---------------------------+\r
+# FLASH_BASE | FD.Quark: | 0x800000 (8 MB)\r
+# 0xFF800000 | BaseAddress |\r
+# +---------------------------+\r
+#\r
+# Flash offsets are 0 based, but are relative to FD.Quark BaseAddress, e.g. Payload Base is at 0x400000, Flash Base is at 0xFF800000 for 8 MB SPI part.\r
+# 0xFF800000 + 0x400000 = 0xFFC00000.\r
+#\r
+# Address 0x0 (0xFF800000 for 8 MB SPI part)\r
+# +---------------------------+\r
+# FLASH_FV_PAYLOAD_BASE | Payload Image | FLASH_FV_PAYLOAD_SIZE\r
+# 0x00400000 | | 0x00100000\r
+# +---------------------------+\r
+# FLASH_FV_MAIN_BASE | FvMain Image (Compressed) | FLASH_FV_MAIN_SIZE\r
+# 0x00500000 | | 0x001E0000\r
+# +---------------------------+\r
+# NVRAM_AREA_BASE | NVRAM Area= | NVRAM_AREA_SIZE\r
+# 0x006E0000 | Variable + FTW Working + |\r
+# | FTW Spare |\r
+# +---+-------------------+---+\r
+# NVRAM_AREA_VARIABLE_BASE | | NVRAM_AREA_VARIABLE_SIZE\r
+# | |\r
+# +-------------------+\r
+# FTW_WORKING_BASE | | FTW_WORKING_SIZE\r
+# | |\r
+# +-------------------+\r
+# FTW_SPARE_BASE | | FTW_SPARE_SIZE\r
+# | |\r
+# +---+-------------------+---+\r
+# RMU_BINARY_BASE | RMU Binary | RMU_BINARY_SIZE\r
+# 0x00700000 | | 0x00008000\r
+# +---------------------------+\r
+# PLATFORM_DATA_BASE | PlatformData Binary | PLATFORM_DATA_SIZE\r
+# 0x00710000 | | 0x00001000\r
+# +---------------------------+\r
+# FVRECOVERY_IMAGE_BASE | FVRECOVERY Image | FVRECOVERY_IMAGE_SIZE\r
+# 0x720000 | | 0x000E0000\r
+# +---------------------------+\r
+\r
+ #\r
+ # Define value used to compute FLASH regions below reset vector location just below 4GB\r
+ #\r
+ DEFINE RESET_ADDRESS = 0x100000000 # 4 GB\r
+\r
+ #\r
+ # Set size of FLASH to 8MB\r
+ #\r
+ DEFINE FLASH_SIZE = 0x800000\r
+ DEFINE FLASH_BASE = $(RESET_ADDRESS) - $(FLASH_SIZE) # The base address of the Flash Device\r
+\r
+ #\r
+ # Set FLASH block size to 4KB\r
+ #\r
+ DEFINE FLASH_BLOCKSIZE = 0x1000 # 4 KB\r
+\r
+ #\r
+ # Misc settings\r
+ #\r
+ DEFINE FLASH_BLOCKSIZE_DATA = 0x00, 0x10, 0x00, 0x00 # equivalent for DATA blocks\r
+\r
+ #\r
+ # Start PAYLOAD at 4MB into 8MB FLASH\r
+ #\r
+ DEFINE FLASH_FV_PAYLOAD_BASE = 0x00400000\r
+ DEFINE FLASH_FV_PAYLOAD_SIZE = 0x00100000\r
+\r
+ #\r
+ # Put FVMAIN between PAYLOAD and RMU Binary\r
+ #\r
+ DEFINE FLASH_FV_MAIN_BASE = 0x00500000\r
+ DEFINE FLASH_FV_MAIN_SIZE = 0x001E0000\r
+\r
+ #\r
+ # Place NV Storage just above Platform Data Base\r
+ #\r
+ DEFINE NVRAM_AREA_VARIABLE_BASE = 0x006E0000\r
+ DEFINE NVRAM_AREA_SIZE = 0x00020000\r
+\r
+ DEFINE NVRAM_AREA_VARIABLE_SIZE = 0x0000E000\r
+ DEFINE FTW_WORKING_BASE = $(NVRAM_AREA_VARIABLE_BASE) + $(NVRAM_AREA_VARIABLE_SIZE)\r
+ DEFINE FTW_WORKING_SIZE = 0x00002000\r
+ DEFINE FTW_SPARE_BASE = $(FTW_WORKING_BASE) + $(FTW_WORKING_SIZE)\r
+ DEFINE FTW_SPARE_SIZE = $(NVRAM_AREA_SIZE) - $(NVRAM_AREA_VARIABLE_SIZE) - $(FTW_WORKING_SIZE)\r
+\r
+ #\r
+ # RMU Binary must be at fixed address 1MB below 4GB (0xFFF00000)\r
+ #\r
+ DEFINE RMU_BINARY_BASE = 0x00700000 # HW fixed address\r
+ DEFINE RMU_BINARY_SIZE = 0x00008000 # HW fixed address, so fixed size\r
+\r
+ #\r
+ # Platform Data Base must be 64KB above RMU\r
+ #\r
+ DEFINE VPD_BASE = 0x00708000\r
+ DEFINE VPD_SIZE = 0x00001000\r
+\r
+ #\r
+ # Place FV Recovery above NV Storage\r
+ #\r
+ DEFINE FVRECOVERY_IMAGE_SIZE = 0x000F0000\r
+ DEFINE FVRECOVERY_IMAGE_BASE = $(FLASH_SIZE) - $(FVRECOVERY_IMAGE_SIZE)\r
+\r
+################################################################################\r
+#\r
+# FD Section\r
+# The [FD] Section is made up of the definition statements and a\r
+# description of what goes into the Flash Device Image. Each FD section\r
+# defines one flash "device" image. A flash device image may be one of\r
+# the following: Removable media bootable image (like a boot floppy\r
+# image,) an Option ROM image (that would be "flashed" into an add-in\r
+# card,) a System "Flash" image (that would be burned into a system's\r
+# flash) or an Update ("Capsule") image that will be used to update and\r
+# existing system flash.\r
+#\r
+################################################################################\r
+[FD.Quark]\r
+BaseAddress = 0xFF800000 #The base address of the Flash Device; set to same value as FLASH_BASE.\r
+Size = 0x800000 #The size in bytes of the Flash Device; set to same value as FLASH_SIZE.\r
+ErasePolarity = 1\r
+BlockSize = $(FLASH_BLOCKSIZE)\r
+NumBlocks = 0x800 #The number of blocks for the Flash Device.\r
+\r
+SET gQuarkPlatformTokenSpaceGuid.PcdFlashAreaBaseAddress = $(FLASH_BASE)\r
+SET gQuarkPlatformTokenSpaceGuid.PcdFlashAreaSize = $(FLASH_SIZE)\r
+\r
+################################################################################\r
+#\r
+# Following are lists of FD Region layout which correspond to the locations of different\r
+# images within the flash device.\r
+#\r
+# Regions must be defined in ascending order and may not overlap.\r
+#\r
+# A Layout Region start with a eight digit hex offset (leading "0x" required) followed by\r
+# the pipe "|" character, followed by the size of the region, also in hex with the leading\r
+# "0x" characters. Like:\r
+# Offset|Size\r
+# PcdOffsetCName|PcdSizeCName\r
+# RegionType <FV, DATA, or FILE>\r
+#\r
+################################################################################\r
+\r
+########################################################\r
+# Quark Payload Image\r
+########################################################\r
+$(FLASH_FV_PAYLOAD_BASE)|$(FLASH_FV_PAYLOAD_SIZE)\r
+gQuarkPlatformTokenSpaceGuid.PcdFlashFvPayloadBase|gQuarkPlatformTokenSpaceGuid.PcdFlashFvPayloadSize\r
+FV = PAYLOAD\r
+\r
+########################################################\r
+# Quark FVMAIN Image (Compressed)\r
+########################################################\r
+$(FLASH_FV_MAIN_BASE)|$(FLASH_FV_MAIN_SIZE)\r
+gQuarkPlatformTokenSpaceGuid.PcdFlashFvMainBase|gQuarkPlatformTokenSpaceGuid.PcdFlashFvMainSize\r
+FV = FVMAIN_COMPACT\r
+\r
+#############################################################################\r
+# Quark NVRAM Area\r
+# Quark NVRAM Area contains: Variable + FTW Working + FTW Spare\r
+#############################################################################\r
+$(NVRAM_AREA_VARIABLE_BASE)|$(NVRAM_AREA_VARIABLE_SIZE)\r
+gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize\r
+#NV_VARIABLE_STORE\r
+DATA = {\r
+ ## This is the EFI_FIRMWARE_VOLUME_HEADER\r
+ # ZeroVector []\r
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r
+ # FileSystemGuid: gEfiSystemNvDataFvGuid =\r
+ # { 0xFFF12B8D, 0x7696, 0x4C8B, { 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50 }}\r
+ 0x8D, 0x2B, 0xF1, 0xFF, 0x96, 0x76, 0x8B, 0x4C,\r
+ 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50,\r
+ # FvLength: 0x20000\r
+ 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00,\r
+ #Signature "_FVH" #Attributes\r
+ 0x5f, 0x46, 0x56, 0x48, 0xff, 0xfe, 0x04, 0x00,\r
+ #HeaderLength #CheckSum #ExtHeaderOffset #Reserved #Revision\r
+ 0x48, 0x00, 0x19, 0xF9, 0x00, 0x00, 0x00, 0x02,\r
+ #Blockmap[0]: 32 Blocks * 0x1000 Bytes / Block\r
+ 0x20, 0x00, 0x00, 0x00, $(FLASH_BLOCKSIZE_DATA),\r
+ #Blockmap[1]: End\r
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\r
+ ## This is the VARIABLE_STORE_HEADER\r
+ !if $(SECURE_BOOT_ENABLE)\r
+ # Signature: gEfiAuthenticatedVariableGuid = { 0xaaf32c78, 0x947b, 0x439a, { 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92 } }\r
+ 0x78, 0x2c, 0xf3, 0xaa, 0x7b, 0x94, 0x9a, 0x43,\r
+ 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92,\r
+ !else\r
+ # Signature: gEfiVariableGuid = { 0xddcf3616, 0x3275, 0x4164, { 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d }}\r
+ 0x16, 0x36, 0xcf, 0xdd, 0x75, 0x32, 0x64, 0x41,\r
+ 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d,\r
+ !endif\r
+ #Size: 0x0E000 (gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize) - 0x48 (size of EFI_FIRMWARE_VOLUME_HEADER) = 0x0DFB8\r
+ # This can speed up the Variable Dispatch a bit.\r
+ 0xB8, 0xDF, 0x00, 0x00,\r
+ #FORMATTED: 0x5A #HEALTHY: 0xFE #Reserved: UINT16 #Reserved1: UINT32\r
+ 0x5A, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00\r
+}\r
+\r
+$(FTW_WORKING_BASE)|$(FTW_WORKING_SIZE)\r
+gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize\r
+#NV_FTW_WORKING\r
+DATA = {\r
+ # EFI_FAULT_TOLERANT_WORKING_BLOCK_HEADER->Signature = gEdkiiWorkingBlockSignatureGuid =\r
+ # { 0x9e58292b, 0x7c68, 0x497d, { 0xa0, 0xce, 0x65, 0x0, 0xfd, 0x9f, 0x1b, 0x95 }}\r
+ 0x2b, 0x29, 0x58, 0x9e, 0x68, 0x7c, 0x7d, 0x49,\r
+ 0xa0, 0xce, 0x65, 0x0, 0xfd, 0x9f, 0x1b, 0x95,\r
+ # Crc:UINT32 #WorkingBlockValid:1, WorkingBlockInvalid:1, Reserved\r
+ 0xE2, 0x33, 0xF2, 0x03, 0xFE, 0xFF, 0xFF, 0xFF,\r
+ # WriteQueueSize: UINT64 #Size: 0x2000 - 0x20 (FTW_WORKING_HEADER) = 0x1FE0\r
+ 0xE0, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00\r
+}\r
+\r
+$(FTW_SPARE_BASE)|$(FTW_SPARE_SIZE)\r
+gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize\r
+#NV_FTW_SPARE\r
+\r
+#########################################################\r
+# Quark Remote Management Unit Binary\r
+#########################################################\r
+$(RMU_BINARY_BASE)|$(RMU_BINARY_SIZE)\r
+INF QuarkSocBinPkg/QuarkNorthCluster/Binary/QuarkMicrocode/QuarkMicrocode.inf\r
+\r
+#########################################################\r
+# PlatformData Binary, default for standalone is none built-in so user selects.\r
+#########################################################\r
+$(VPD_BASE)|$(VPD_SIZE)\r
+gEfiMdeModulePkgTokenSpaceGuid.PcdVpdBaseAddress\r
+FILE = $(OUTPUT_DIRECTORY)/$(TARGET)_$(TOOL_CHAIN_TAG)/FV/8C3D856A-9BE6-468E-850A-24F7A8D38E08.bin\r
+\r
+#######################\r
+# Quark FVRECOVERY Image\r
+#######################\r
+$(FVRECOVERY_IMAGE_BASE)|$(FVRECOVERY_IMAGE_SIZE)\r
+gQuarkPlatformTokenSpaceGuid.PcdFlashFvRecoveryBase|gQuarkPlatformTokenSpaceGuid.PcdFlashFvRecoverySize\r
+FV = FVRECOVERY\r
+\r
+################################################################################\r
+#\r
+# FV Section\r
+#\r
+# [FV] section is used to define what components or modules are placed within a flash\r
+# device file. This section also defines order the components and modules are positioned\r
+# within the image. The [FV] section consists of define statements, set statements and\r
+# module statements.\r
+#\r
+################################################################################\r
+[FV.FVRECOVERY]\r
+BlockSize = $(FLASH_BLOCKSIZE)\r
+FvAlignment = 16 #FV alignment and FV attributes setting.\r
+ERASE_POLARITY = 1\r
+MEMORY_MAPPED = TRUE\r
+STICKY_WRITE = TRUE\r
+LOCK_CAP = TRUE\r
+LOCK_STATUS = TRUE\r
+WRITE_DISABLED_CAP = TRUE\r
+WRITE_ENABLED_CAP = TRUE\r
+WRITE_STATUS = TRUE\r
+WRITE_LOCK_CAP = TRUE\r
+WRITE_LOCK_STATUS = TRUE\r
+READ_DISABLED_CAP = TRUE\r
+READ_ENABLED_CAP = TRUE\r
+READ_STATUS = TRUE\r
+READ_LOCK_CAP = TRUE\r
+READ_LOCK_STATUS = TRUE\r
+FvNameGuid = 18D6D9F4-2EEF-4913-AEE6-BE61C6DA6CC8\r
+\r
+################################################################################\r
+#\r
+# The INF statements point to EDK component and EDK II module INF files, which will be placed into this FV image.\r
+# Parsing tools will scan the INF file to determine the type of component or module.\r
+# The component or module type is used to reference the standard rules\r
+# defined elsewhere in the FDF file.\r
+#\r
+# The format for INF statements is:\r
+# INF $(PathAndInfFileName)\r
+#\r
+################################################################################\r
+\r
+##\r
+# PEI Apriori file example, more PEIM module added later.\r
+##\r
+APRIORI PEI {\r
+ INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf\r
+ # PlatformConfigPei should be immediately after Pcd driver.\r
+ INF QuarkPlatformPkg/Platform/Pei/PlatformConfig/PlatformConfigPei.inf\r
+ INF MdeModulePkg/Universal/PcatSingleSegmentPciCfg2Pei/PcatSingleSegmentPciCfg2Pei.inf\r
+}\r
+\r
+##\r
+# SEC Phase modules\r
+##\r
+INF UefiCpuPkg/SecCore/SecCore.inf\r
+\r
+INF MdeModulePkg/Core/Pei/PeiMain.inf\r
+\r
+##\r
+# PEI Phase RAW Data files.\r
+##\r
+FILE FREEFORM = PCD(gEfiQuarkNcSocIdTokenSpaceGuid.PcdQuarkMicrocodeFile) {\r
+ SECTION RAW = QuarkSocBinPkg/QuarkNorthCluster/Binary/QuarkMicrocode/RMU.bin\r
+}\r
+\r
+INF RuleOverride = NORELOC MdeModulePkg/Universal/PCD/Pei/Pcd.inf\r
+INF QuarkPlatformPkg/Platform/Pei/PlatformConfig/PlatformConfigPei.inf\r
+INF RuleOverride = NORELOC MdeModulePkg/Universal/FaultTolerantWritePei/FaultTolerantWritePei.inf\r
+INF RuleOverride = NORELOC MdeModulePkg/Universal/Variable/Pei/VariablePei.inf\r
+INF RuleOverride = NORELOC QuarkSocPkg/QuarkNorthCluster/MemoryInit/Pei/MemoryInitPei.inf\r
+INF QuarkPlatformPkg/Platform/Pei/PlatformInit/PlatformEarlyInit.inf\r
+INF MdeModulePkg/Universal/PcatSingleSegmentPciCfg2Pei/PcatSingleSegmentPciCfg2Pei.inf\r
+INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf\r
+\r
+################################################################################\r
+#\r
+# FV Section\r
+#\r
+# [FV] section is used to define what components or modules are placed within a flash\r
+# device file. This section also defines order the components and modules are positioned\r
+# within the image. The [FV] section consists of define statements, set statements and\r
+# module statements.\r
+#\r
+################################################################################\r
+[FV.FVMAIN]\r
+BlockSize = $(FLASH_BLOCKSIZE)\r
+FvAlignment = 16\r
+ERASE_POLARITY = 1\r
+MEMORY_MAPPED = TRUE\r
+STICKY_WRITE = TRUE\r
+LOCK_CAP = TRUE\r
+LOCK_STATUS = TRUE\r
+WRITE_DISABLED_CAP = TRUE\r
+WRITE_ENABLED_CAP = TRUE\r
+WRITE_STATUS = TRUE\r
+WRITE_LOCK_CAP = TRUE\r
+WRITE_LOCK_STATUS = TRUE\r
+READ_DISABLED_CAP = TRUE\r
+READ_ENABLED_CAP = TRUE\r
+READ_STATUS = TRUE\r
+READ_LOCK_CAP = TRUE\r
+READ_LOCK_STATUS = TRUE\r
+FvNameGuid = 30D9ED01-38D2-418a-90D5-C561750BF80F\r
+\r
+##\r
+# DXE Phase modules\r
+##\r
+INF MdeModulePkg/Core/Dxe/DxeMain.inf\r
+INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf\r
+\r
+!if $(SOURCE_DEBUG_ENABLE)\r
+ INF SourceLevelDebugPkg/DebugAgentDxe/DebugAgentDxe.inf\r
+!endif\r
+\r
+#\r
+# Early SoC / Platform modules\r
+#\r
+INF QuarkPlatformPkg/Platform/Dxe/PlatformInit/PlatformInitDxe.inf\r
+\r
+##\r
+# EDK Core modules\r
+##\r
+INF UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.inf\r
+\r
+INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf\r
+INF UefiCpuPkg/CpuDxe/CpuDxe.inf\r
+INF MdeModulePkg/Universal/Metronome/Metronome.inf\r
+INF MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf\r
+INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf\r
+INF MdeModulePkg/Universal/Variable/EmuRuntimeDxe/EmuVariableRuntimeDxe.inf\r
+INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf\r
+INF MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf\r
+INF MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf\r
+INF PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcatRealTimeClockRuntimeDxe.inf\r
+INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf\r
+INF MdeModulePkg/Universal/MemoryTest/NullMemoryTestDxe/NullMemoryTestDxe.inf\r
+\r
+#\r
+# Platform\r
+#\r
+INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf\r
+#INF MdeModulePkg/Application/UiApp/UiApp.inf\r
+\r
+INF QuarkPlatformPkg/Pci/Dxe/PciHostBridge/PciHostBridge.inf\r
+INF QuarkSocPkg/QuarkNorthCluster/QNCInit/Dxe/QNCInitDxe.inf\r
+INF PcAtChipsetPkg/HpetTimerDxe/HpetTimerDxe.inf\r
+INF QuarkPlatformPkg/Platform/Dxe/Setup/DxePlatform.inf\r
+\r
+#\r
+# PCI\r
+#\r
+INF QuarkPlatformPkg/Pci/Dxe/PciPlatform/PciPlatform.inf\r
+INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf\r
+INF QuarkSocPkg/QuarkSouthCluster/IohInit/Dxe/IohInitDxe.inf\r
+!if $(SOURCE_DEBUG_ENABLE)\r
+!else\r
+INF MdeModulePkg/Bus/Pci/PciSioSerialDxe/PciSioSerialDxe.inf\r
+!endif\r
+\r
+#\r
+# Console\r
+#\r
+INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf\r
+INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf\r
+INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf\r
+\r
+INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf\r
+INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf\r
+INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf\r
+INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf\r
+\r
+#\r
+# File System Modules\r
+#\r
+INF MdeModulePkg/Universal/FvSimpleFileSystemDxe/FvSimpleFileSystemDxe.inf\r
+\r
+################################################################################\r
+#\r
+# FV Section\r
+#\r
+# [FV] section is used to define what components or modules are placed within a flash\r
+# device file. This section also defines order the components and modules are positioned\r
+# within the image. The [FV] section consists of define statements, set statements and\r
+# module statements.\r
+#\r
+################################################################################\r
+[FV.FVMAIN_COMPACT]\r
+FvAlignment = 16\r
+ERASE_POLARITY = 1\r
+MEMORY_MAPPED = TRUE\r
+STICKY_WRITE = TRUE\r
+LOCK_CAP = TRUE\r
+LOCK_STATUS = TRUE\r
+WRITE_DISABLED_CAP = TRUE\r
+WRITE_ENABLED_CAP = TRUE\r
+WRITE_STATUS = TRUE\r
+WRITE_LOCK_CAP = TRUE\r
+WRITE_LOCK_STATUS = TRUE\r
+READ_DISABLED_CAP = TRUE\r
+READ_ENABLED_CAP = TRUE\r
+READ_STATUS = TRUE\r
+READ_LOCK_CAP = TRUE\r
+READ_LOCK_STATUS = TRUE\r
+\r
+FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 {\r
+ SECTION GUIDED A31280AD-481E-41B6-95E8-127F4C984779 { # TIANO COMPRESS GUID\r
+ SECTION FV_IMAGE = FVMAIN\r
+ }\r
+}\r
+\r
+################################################################################\r
+#\r
+# FV Section\r
+#\r
+# [FV] section is used to define what components or modules are placed within a flash\r
+# device file. This section also defines order the components and modules are positioned\r
+# within the image. The [FV] section consists of define statements, set statements and\r
+# module statements.\r
+#\r
+################################################################################\r
+[FV.PAYLOAD]\r
+BlockSize = $(FLASH_BLOCKSIZE)\r
+FvAlignment = 16 #FV alignment and FV attributes setting.\r
+ERASE_POLARITY = 1\r
+MEMORY_MAPPED = TRUE\r
+STICKY_WRITE = TRUE\r
+LOCK_CAP = TRUE\r
+LOCK_STATUS = TRUE\r
+WRITE_DISABLED_CAP = TRUE\r
+WRITE_ENABLED_CAP = TRUE\r
+WRITE_STATUS = TRUE\r
+WRITE_LOCK_CAP = TRUE\r
+WRITE_LOCK_STATUS = TRUE\r
+READ_DISABLED_CAP = TRUE\r
+READ_ENABLED_CAP = TRUE\r
+READ_STATUS = TRUE\r
+READ_LOCK_CAP = TRUE\r
+READ_LOCK_STATUS = TRUE\r
+\r
+#\r
+# Shell and Applications\r
+#\r
+INF ShellPkg/Application/Shell/Shell.inf\r
+!if $(PERFORMANCE_ENABLE)\r
+INF PerformancePkg/Dp_App/Dp.inf\r
+!endif\r
+\r
+################################################################################\r
+#\r
+# Rules are use with the [FV] section's module INF type to define\r
+# how an FFS file is created for a given INF file. The following Rule are the default\r
+# rules for the different module type. User can add the customized rules to define the\r
+# content of the FFS file.\r
+#\r
+################################################################################\r
+[Rule.Common.SEC]\r
+ FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED {\r
+ TE TE Align = 8 $(INF_OUTPUT)/$(MODULE_NAME).efi\r
+ RAW BIN Align = 16 |.com\r
+ }\r
+\r
+[Rule.Common.PEI_CORE]\r
+ FILE PEI_CORE = $(NAMED_GUID) {\r
+ TE TE $(INF_OUTPUT)/$(MODULE_NAME).efi\r
+ UI STRING="$(MODULE_NAME)" Optional\r
+ VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)\r
+ }\r
+\r
+[Rule.Common.PEIM.NORELOC]\r
+ FILE PEIM = $(NAMED_GUID) RELOCS_STRIPPED {\r
+ PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex\r
+ TE TE $(INF_OUTPUT)/$(MODULE_NAME).efi\r
+ UI STRING="$(MODULE_NAME)" Optional\r
+ VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)\r
+ }\r
+\r
+[Rule.Common.PEIM]\r
+ FILE PEIM = $(NAMED_GUID) {\r
+ PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex\r
+ TE TE $(INF_OUTPUT)/$(MODULE_NAME).efi\r
+ UI STRING="$(MODULE_NAME)" Optional\r
+ VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)\r
+ }\r
+\r
+[Rule.Common.DXE_CORE]\r
+ FILE DXE_CORE = $(NAMED_GUID) {\r
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi\r
+ UI STRING="$(MODULE_NAME)" Optional\r
+ VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)\r
+ }\r
+\r
+[Rule.Common.UEFI_DRIVER]\r
+ FILE DRIVER = $(NAMED_GUID) {\r
+ DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex\r
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi\r
+ UI STRING="$(MODULE_NAME)" Optional\r
+ VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)\r
+ }\r
+\r
+[Rule.Common.DXE_DRIVER]\r
+ FILE DRIVER = $(NAMED_GUID) {\r
+ DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex\r
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi\r
+ UI STRING="$(MODULE_NAME)" Optional\r
+ VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)\r
+ }\r
+\r
+[Rule.Common.DXE_RUNTIME_DRIVER]\r
+ FILE DRIVER = $(NAMED_GUID) {\r
+ DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex\r
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi\r
+ UI STRING="$(MODULE_NAME)" Optional\r
+ VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)\r
+ }\r
+\r
+[Rule.Common.DXE_SMM_DRIVER]\r
+ FILE SMM = $(NAMED_GUID) {\r
+ SMM_DEPEX SMM_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex\r
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi\r
+ UI STRING="$(MODULE_NAME)" Optional\r
+ VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)\r
+ }\r
+\r
+[Rule.Common.SMM_CORE]\r
+ FILE SMM_CORE = $(NAMED_GUID) {\r
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi\r
+ UI STRING="$(MODULE_NAME)" Optional\r
+ VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)\r
+ }\r
+\r
+[Rule.Common.UEFI_APPLICATION]\r
+ FILE APPLICATION = $(NAMED_GUID) {\r
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi\r
+ UI STRING="$(MODULE_NAME)" Optional\r
+ VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)\r
+ }\r
+\r
+[Rule.Common.UEFI_APPLICATION.UI]\r
+ FILE APPLICATION = $(NAMED_GUID) {\r
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi\r
+ UI STRING="Enter Setup"\r
+ VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)\r
+ }\r
+\r
+[Rule.Common.USER_DEFINED.ACPITABLE]\r
+ FILE FREEFORM = $(NAMED_GUID) {\r
+ RAW ACPI |.acpi\r
+ RAW ASL |.aml\r
+ }\r
--- /dev/null
+## @file\r
+# Package for support of Clanton Peak CRB platform\r
+#\r
+# This package provides QuarkNcSocId platform specific modules.\r
+# Copyright (c) 2013-2015 Intel Corporation.\r
+#\r
+# This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution. The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php\r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+##\r
+\r
+\r
+################################################################################\r
+#\r
+# Defines Section - statements that will be processed to create a Makefile.\r
+#\r
+################################################################################\r
+\r
+[Defines]\r
+ DEC_SPECIFICATION = 0x00010005\r
+ PACKAGE_NAME = QuarkPlatformPkg\r
+ PACKAGE_GUID = 46C1F476-A85E-49a8-B258-DD4396B87FEF\r
+ PACKAGE_VERSION = 0.1\r
+\r
+\r
+################################################################################\r
+#\r
+# Include Section - list of Include Paths that are provided by this package.\r
+# Comments are used for Keywords and Module Types.\r
+#\r
+# Supported Module Types:\r
+# SEC PEIM DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER\r
+#\r
+################################################################################\r
+[Includes]\r
+ Include\r
+\r
+################################################################################\r
+#\r
+# Library Class Header section - list of Library Class header files that are\r
+# provided by this package.\r
+#\r
+################################################################################\r
+[LibraryClasses]\r
+\r
+################################################################################\r
+#\r
+# Global Guid Definition section - list of Global Guid C Name Data Structures\r
+# that are provided by this package.\r
+#\r
+################################################################################\r
+[Guids]\r
+ gQuarkPlatformTokenSpaceGuid = { 0x199c1ef0, 0x6400, 0x41c5, { 0xb0, 0xa4, 0xff, 0xbf, 0x21, 0x9d, 0xcb, 0xae }}\r
+ gEfiMemoryConfigDataGuid = { 0x80dbd530, 0xb74c, 0x4f11, { 0x8c, 0x03, 0x41, 0x86, 0x65, 0x53, 0x28, 0x31 }}\r
+ gPowerManagementAcpiTableStorageGuid = { 0xc0cc43bd, 0xc920, 0x4064, { 0x93, 0x5b, 0x93, 0xb4, 0x47, 0x37, 0x94, 0x70 }}\r
+ gPeiCapsuleOnFatFloppyDiskGuid = {0x2e3d2e75, 0x9b2e, 0x412d, {0xb4, 0xb1, 0x70, 0x41, 0x6b, 0x87, 0x0, 0xff }}\r
+ gPeiCapsuleOnFatIdeDiskGuid = {0xb38573b6, 0x6200, 0x4ac5, {0xb5, 0x1d, 0x82, 0xe6, 0x59, 0x38, 0xd7, 0x83 }}\r
+ gPeiCapsuleOnFatUsbDiskGuid = {0x0ffbce19, 0x324c, 0x4690, {0xa0, 0x09, 0x98, 0xc6, 0xae, 0x2e, 0xb1, 0x86 }}\r
+ gPeiCapsuleOnDataCDGuid = {0x5cac0099, 0x0dc9, 0x48e5, {0x80, 0x68, 0xbb, 0x95, 0xf5, 0x40, 0x0a, 0x9f }}\r
+ gEfiQuarkCapsuleGuid = { 0xd400d1e4, 0xa314, 0x442b, { 0x89, 0xed, 0xa9, 0x2e, 0x4c, 0x81, 0x97, 0xcb } }\r
+ gQuarkVariableLockGuid = { 0xeef749c2, 0xc047, 0x4d6e, { 0xb1, 0xbc, 0xd3, 0x6e, 0xb3, 0xa5, 0x55, 0x9c }}\r
+\r
+################################################################################\r
+#\r
+# Global Protocols Definition section - list of Global Protocols C Name Data\r
+# Structures that are provided by this package.\r
+#\r
+################################################################################\r
+[Protocols]\r
+ gEfiGlobalNvsAreaProtocolGuid = { 0x074E1E48, 0x8132, 0x47A1, { 0x8C, 0x2C, 0x3F, 0x14, 0xAD, 0x9A, 0x66, 0xDC }}\r
+ gEfiSmmSpiReadyProtocolGuid = { 0x7a5dbc75, 0x5b2b, 0x4e67, { 0xbd, 0xe1, 0xd4, 0x8e, 0xee, 0x76, 0x15, 0x62 }}\r
+ gEfiIioUdsProtocolGuid = { 0xa7ced760, 0xc71c, 0x4e1a, { 0xac, 0xb1, 0x89, 0x60, 0x4d, 0x52, 0x16, 0xcb }}\r
+\r
+################################################################################\r
+#\r
+# PCD Declarations section - list of all PCDs Declared by this Package\r
+# Only this package should be providing the\r
+# declaration, other packages should not.\r
+#\r
+################################################################################\r
+\r
+[PcdsFeatureFlag]\r
+ gQuarkPlatformTokenSpaceGuid.WaitIfResetDueToError|FALSE|BOOLEAN|0x2000000F\r
+\r
+[PcdsFixedAtBuild]\r
+ gQuarkPlatformTokenSpaceGuid.PcdFlashAreaBaseAddress|0xFF800000|UINT32|0x20000001\r
+ gQuarkPlatformTokenSpaceGuid.PcdFlashAreaSize|0x800000|UINT32|0x20000002\r
+ gQuarkPlatformTokenSpaceGuid.PcdFlashNvStorageBase|0xFFF30000|UINT32|0x20000003\r
+ gQuarkPlatformTokenSpaceGuid.PcdFlashNvStorageSize|0x00020000|UINT32|0x20000004\r
+ gQuarkPlatformTokenSpaceGuid.PcdFlashFvRecovery2Base|0xFFEF0400|UINT32|0x2000001C\r
+ gQuarkPlatformTokenSpaceGuid.PcdFlashFvRecovery2Size|0x00007000|UINT32|0x2000001D\r
+ gQuarkPlatformTokenSpaceGuid.PcdFlashQNCMicrocodeSize|0x00004000|UINT32|0x2000000C\r
+ gQuarkPlatformTokenSpaceGuid.PcdPlatformDataBaseAddress|0xFFF10000|UINT32|0x2000001E\r
+ gQuarkPlatformTokenSpaceGuid.PcdPlatformDataMaxLen|0x20000|UINT32|0x2000001F\r
+ gQuarkPlatformTokenSpaceGuid.PcdHpetEnable|TRUE|BOOLEAN|0x20000018\r
+\r
+ gQuarkPlatformTokenSpaceGuid.PcdFlashFvDefaultPayloadBase|0xFFC00400|UINT32|0x20000020\r
+ gQuarkPlatformTokenSpaceGuid.PcdFlashFvDefaultPayloadSize|0x000F0000|UINT32|0x20000021\r
+ gQuarkPlatformTokenSpaceGuid.PcdFlashFvDefaultMainBase|0xFFD00400|UINT32|0x20000022\r
+ gQuarkPlatformTokenSpaceGuid.PcdFlashFvDefaultMainSize|0x000D0000|UINT32|0x20000023\r
+\r
+ gQuarkPlatformTokenSpaceGuid.PcdMemorySize|0x80000000|UINT32|0x20000032\r
+ # ECC scrub interval in miliseconds 1..255 (0 works as feature disable)\r
+ gQuarkPlatformTokenSpaceGuid.PcdEccScrubInterval|0x00|UINT8|0x20000037\r
+ # Number of 32B blocks read for ECC scrub 2..16\r
+ gQuarkPlatformTokenSpaceGuid.PcdEccScrubBlkSize|0x02|UINT8|0x20000038\r
+ gQuarkPlatformTokenSpaceGuid.PcdFlashNvMfh|0xFFF08000|UINT32|0x20000039\r
+ gQuarkPlatformTokenSpaceGuid.PcdFlashFvFixedStage1AreaBase|0xFFF90000|UINT32|0x2000003A\r
+ gQuarkPlatformTokenSpaceGuid.PcdFlashFvFixedStage1AreaSize|0x00040000|UINT32|0x2000003B\r
+ gQuarkPlatformTokenSpaceGuid.PcdEsramStage1Base|0x80000000|UINT32|0x2000003C\r
+\r
+ # Legacy Bridge protected BIOS range register configs, if == 0 then do nothing since register default.\r
+ gQuarkPlatformTokenSpaceGuid.PcdLegacyProtectedBIOSRange0Pei|0x00000000|UINT32|0x2000003D\r
+ gQuarkPlatformTokenSpaceGuid.PcdLegacyProtectedBIOSRange1Pei|0x00000000|UINT32|0x2000003E\r
+ gQuarkPlatformTokenSpaceGuid.PcdLegacyProtectedBIOSRange2Pei|0x00000000|UINT32|0x2000004F\r
+\r
+ # ACPI Power management settings.\r
+\r
+ # Power Management flags.\r
+ # PpmFlags[5] = PPM_C2 = C2 Capable, Enabled.\r
+ gQuarkPlatformTokenSpaceGuid.PcdPpmFlags|0x00000020|UINT32|0xA00000CF\r
+\r
+ # Madt Table Initialize settings.\r
+ # Defines a flag to Enable/Disable interrupt override setting table0,\r
+ # and the source Irq, Polarity, Triger Mode and global Irq of interrupt override setting table0\r
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable0Enable|0x01|UINT8|0xA0000100\r
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable0SourceIrq|0x00|UINT8|0xA0000101\r
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable0Polarity|0x00|UINT8|0xA0000102\r
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable0TrigerMode|0x00|UINT8|0xA0000103\r
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable0GlobalIrq|0x02|UINT32|0xA0000104\r
+\r
+ # Madt Table Initialize settings.\r
+ # Defines a flag to Enable/Disable interrupt override setting table1,\r
+ # and the source Irq, Polarity, Triger Mode and global Irq of interrupt override setting table1\r
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable1Enable|0x01|UINT8|0xA0000105\r
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable1SourceIrq|0x09|UINT8|0xA0000106\r
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable1Polarity|0x01|UINT8|0xA0000107\r
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable1TrigerMode|0x03|UINT8|0xA0000108\r
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable1GlobalIrq|0x09|UINT32|0xA0000109\r
+\r
+ # Madt Table Initialize settings.\r
+ # Defines a flag to Enable/Disable interrupt override setting table2,\r
+ # and the source Irq, Polarity, Triger Mode and global Irq of interrupt override setting table2\r
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable2Enable|0x0|UINT8|0xA000010F\r
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable2SourceIrq|0x0|UINT8|0xA0000110\r
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable2Polarity|0x0|UINT8|0xA0000111\r
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable2TrigerMode|0x0|UINT8|0xA0000112\r
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable2GlobalIrq|0x0|UINT32|0xA0000113\r
+\r
+ # Madt Table Initialize settings.\r
+ # Defines a flag to Enable/Disable interrupt override setting table3,\r
+ # and the source Irq, Polarity, Triger Mode and global Irq of interrupt override setting table3\r
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable3Enable|0x0|UINT8|0xA0000114\r
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable3SourceIrq|0x0|UINT8|0xA0000115\r
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable3Polarity|0x0|UINT8|0xA0000116\r
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable3TrigerMode|0x0|UINT8|0xA0000117\r
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable3GlobalIrq|0x0|UINT32|0xA0000118\r
+\r
+ # Madt Table Initialize settings.\r
+ # Defines a flag to Enable/Disable interrupt override setting table4,\r
+ # and the source Irq, Polarity, Triger Mode and global Irq of interrupt override setting table4\r
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable4Enable|0x0|UINT8|0xA0000119\r
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable4SourceIrq|0x0|UINT8|0xA000011A\r
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable4Polarity|0x0|UINT8|0xA0000120\r
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable4TrigerMode|0x0|UINT8|0xA0000121\r
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable4GlobalIrq|0x0|UINT32|0xA0000122\r
+\r
+ # Madt Table Initialize settings.\r
+ # Defines a flag to Enable/Disable interrupt override setting table5,\r
+ # and the source Irq, Polarity, Triger Mode and global Irq of interrupt override setting table5\r
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable5Enable|0x0|UINT8|0xA0000123\r
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable5SourceIrq|0x0|UINT8|0xA0000124\r
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable5Polarity|0x0|UINT8|0xA0000125\r
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable5TrigerMode|0x0|UINT8|0xA0000126\r
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable5GlobalIrq|0x0|UINT32|0xA0000127\r
+\r
+ # Madt Table Initialize settings.\r
+ # Defines a flag to Enable/Disable interrupt override setting table6,\r
+ # and the source Irq, Polarity, Triger Mode and global Irq of interrupt override setting table6\r
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable6Enable|0x0|UINT8|0xA0000128\r
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable6SourceIrq|0x0|UINT8|0xA0000129\r
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable6Polarity|0x0|UINT8|0xA000012A\r
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable6TrigerMode|0x0|UINT8|0xA000012B\r
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable6GlobalIrq|0x0|UINT32|0xA000012C\r
+\r
+ # Madt Table Initialize settings.\r
+ # Defines a flag to Enable/Disable interrupt override setting table7,\r
+ # and the source Irq, Polarity, Triger Mode and global Irq of interrupt override setting table7\r
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable7Enable|0x0|UINT8|0xA000012D\r
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable7SourceIrq|0x0|UINT8|0xA000012E\r
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable7Polarity|0x0|UINT8|0xA000012F\r
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable7TrigerMode|0x0|UINT8|0xA0000130\r
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable7GlobalIrq|0x0|UINT32|0xA0000131\r
+\r
+ # Madt Table Initialize settings.\r
+ # Defines a flag to Enable/Disable interrupt override setting table8,\r
+ # and the source Irq, Polarity, Triger Mode and global Irq of interrupt override setting table8\r
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable8Enable|0x0|UINT8|0xA0000132\r
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable8SourceIrq|0x0|UINT8|0xA0000133\r
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable8Polarity|0x0|UINT8|0xA0000134\r
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable8TrigerMode|0x0|UINT8|0xA0000135\r
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable8GlobalIrq|0x0|UINT32|0xA0000136\r
+\r
+ # Madt Table Initialize settings.\r
+ # Defines a flag to Enable/Disable interrupt override setting table9,\r
+ # and the source Irq, Polarity, Triger Mode and global Irq of interrupt override setting table9\r
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable9Enable|0x0|UINT8|0xA0000137\r
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable9SourceIrq|0x0|UINT8|0xA0000138\r
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable9Polarity|0x0|UINT8|0xA0000139\r
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable9TrigerMode|0x0|UINT8|0xA000013A\r
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable9GlobalIrq|0x0|UINT32|0xA000013B\r
+\r
+ # Madt Table Initialize settings.\r
+ # Defines a flag to Enable/Disable interrupt override setting table10,\r
+ # and the source Irq, Polarity, Triger Mode and global Irq of interrupt override setting table10\r
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable10Enable|0x0|UINT8|0xA000013C\r
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable10SourceIrq|0x0|UINT8|0xA000013D\r
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable10Polarity|0x0|UINT8|0xA000013E\r
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable10TrigerMode|0x0|UINT8|0xA000013F\r
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable10GlobalIrq|0x0|UINT32|0xA0000140\r
+\r
+ # Madt Table Initialize settings.\r
+ # Defines a flag to Enable/Disable interrupt override setting table11,\r
+ # and the source Irq, Polarity, Triger Mode and global Irq of interrupt override setting table11\r
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable11Enable|0x0|UINT8|0xA0000141\r
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable11SourceIrq|0x0|UINT8|0xA0000142\r
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable11Polarity|0x0|UINT8|0xA0000143\r
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable11TrigerMode|0x0|UINT8|0xA0000144\r
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable11GlobalIrq|0x0|UINT32|0xA0000145\r
+\r
+ # Madt Table Initialize settings.\r
+ # Defines a flag to Enable/Disable interrupt override setting table12,\r
+ # and the source Irq, Polarity, Triger Mode and global Irq of interrupt override setting table12\r
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable12Enable|0x0|UINT8|0xA0000146\r
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable12SourceIrq|0x0|UINT8|0xA0000147\r
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable12Polarity|0x0|UINT8|0xA0000148\r
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable12TrigerMode|0x0|UINT8|0xA0000149\r
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable12GlobalIrq|0x0|UINT32|0xA000014A\r
+\r
+ # Madt Table Initialize settings.\r
+ # Defines a flag to Enable/Disable interrupt override setting table13,\r
+ # and the source Irq, Polarity, Triger Mode and global Irq of interrupt override setting table13\r
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable13Enable|0x0|UINT8|0xA000014B\r
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable13SourceIrq|0x0|UINT8|0xA000014C\r
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable13Polarity|0x0|UINT8|0xA000014D\r
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable13TrigerMode|0x0|UINT8|0xA000014E\r
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable13GlobalIrq|0x0|UINT32|0xA000014F\r
+\r
+ # Madt Table Initialize settings.\r
+ # Defines a flag to Enable/Disable interrupt override setting table14,\r
+ # and the source Irq, Polarity, Triger Mode and global Irq of interrupt override setting table14\r
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable14Enable|0x0|UINT8|0xA0000150\r
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable14SourceIrq|0x0|UINT8|0xA0000151\r
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable14Polarity|0x0|UINT8|0xA0000152\r
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable14TrigerMode|0x0|UINT8|0xA0000153\r
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable14GlobalIrq|0x0|UINT32|0xA0000154\r
+\r
+ # Madt Table Initialize settings.\r
+ # Defines a flag to Enable/Disable interrupt override setting table15,\r
+ # and the source Irq, Polarity, Triger Mode and global Irq of interrupt override setting table15\r
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable15Enable|0x0|UINT8|0xA0000155\r
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable15SourceIrq|0x0|UINT8|0xA0000156\r
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable15Polarity|0x0|UINT8|0xA0000157\r
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable15TrigerMode|0x0|UINT8|0xA0000158\r
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable15GlobalIrq|0x0|UINT32|0xA0000159\r
+\r
+ # Madt Table Initialize settings.\r
+ # Defines a bunch of Pcds for IO APIC setting:\r
+ # IoApicAddress, GlobalInterruptBase, IoApicId, NmiEnable, NmiSource, Polarity and TrigerMode\r
+ gQuarkPlatformTokenSpaceGuid.PcdIoApicSettingIoApicAddress|0xFEC00000|UINT32|0xA0000170\r
+ gQuarkPlatformTokenSpaceGuid.PcdIoApicSettingGlobalInterruptBase|0x0|UINT32|0xA0000171\r
+ gQuarkPlatformTokenSpaceGuid.PcdIoApicSettingIoApicId|0x01|UINT8|0xA0000172\r
+ gQuarkPlatformTokenSpaceGuid.PcdIoApicSettingNmiEnable|0x0|UINT8|0xA0000173\r
+ gQuarkPlatformTokenSpaceGuid.PcdIoApicSettingNmiSource|0x0|UINT8|0xA0000174\r
+ gQuarkPlatformTokenSpaceGuid.PcdIoApicSettingPolarity|0x0|UINT8|0xA0000175\r
+ gQuarkPlatformTokenSpaceGuid.PcdIoApicSettingTrigerMode|0x0|UINT8|0xA0000176\r
+\r
+ # Madt Table Initialize settings.\r
+ # Defines a bunch of Pcds for Local APIC setting:\r
+ # NmiEnabelApicIdMask, AddressOverrideEnable, Polarity, TrigerMode, LocalApicLint, LocalApicAddress and LocalApicAddressOverride\r
+ gQuarkPlatformTokenSpaceGuid.PcdLocalApicSettingNmiEnabelApicIdMask|0x03|UINT8|0xA0000177\r
+ gQuarkPlatformTokenSpaceGuid.PcdLocalApicSettingAddressOverrideEnable|0x00|UINT8|0xA0000178\r
+ gQuarkPlatformTokenSpaceGuid.PcdLocalApicSettingPolarity|0x01|UINT8|0xA0000179\r
+ gQuarkPlatformTokenSpaceGuid.PcdLocalApicSettingTrigerMode|0x01|UINT8|0xA000017A\r
+ gQuarkPlatformTokenSpaceGuid.PcdLocalApicSettingLocalApicLint|0x01|UINT8|0xA000017B\r
+ gQuarkPlatformTokenSpaceGuid.PcdLocalApicAddressOverride|0x00|UINT64|0xA000017C\r
+\r
+ # PCDs for auto provisioning of UEFI SecureBoot.\r
+ gQuarkPlatformTokenSpaceGuid.PcdPkX509File |{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }|VOID*|0xA0000180\r
+ gQuarkPlatformTokenSpaceGuid.PcdKekX509File |{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }|VOID*|0xA0000181\r
+ gQuarkPlatformTokenSpaceGuid.PcdKekRsa2048File |{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }|VOID*|0xA0000182\r
+ gQuarkPlatformTokenSpaceGuid.PcdDbX509File |{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }|VOID*|0xA0000183\r
+ gQuarkPlatformTokenSpaceGuid.PcdDbxX509File |{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }|VOID*|0xA0000184\r
+\r
+[PcdsFixedAtBuild, PcdsPatchableInModule]\r
+ ## This PCD points to the file name GUID of the BootManagerMenuApp\r
+ # Platform can customize the PCD to point to different application for Boot Manager Menu\r
+ gQuarkPlatformTokenSpaceGuid.PcdBootManagerMenuFile|{ 0xdc, 0x5b, 0xc2, 0xee, 0xf2, 0x67, 0x95, 0x4d, 0xb1, 0xd5, 0xf8, 0x1b, 0x20, 0x39, 0xd1, 0x1d }|VOID*|0x00000003\r
+\r
+ #BIOS Information (Type 0), please refer spec SMBIOS 2.4, section 3.3.1 ,for following SMBIOS relates comments.\r
+\r
+ # String number of the BIOS Vendors Name\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSBiosVendor|"Intel Corp."|VOID*|0xA0000033\r
+ # String number of the BIOS Release Data\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSBiosReleaseDate|"01/01/2014"|VOID*|0xA0000035\r
+ # Segment location of BIOS starting address.\r
+ # Note: The size of the runtime BIOS image can be computed by subtracting the Starting Address Segment from 10000h and multiplying the result by 16.\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSBiosStartAddress|0xE000|UINT16|0xA0000036\r
+ #Defines which functions the BIOS supports. PCI, PCMCIA, Flash, etc. See 3.3.1.1.\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSBiosChar|0x03037C099880|UINT64|0xA0000037\r
+ #Defines which functions the BIOS supports. etc.See 3.3.1.2.1.\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSBiosCharEx1|0x03|UINT8|0xA0000038\r
+ #Defines which functions the BIOS supports. etc.See 3.3.1.2.2.\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSBiosCharEx2|0x03|UINT8|0xA0000039\r
+\r
+ # System Information (Type 1), Section 3.3.2\r
+ # System Manufacturer String\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemManufacturer|"Intel Corp."|VOID*|0xA000003A\r
+ # System Product String\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemProductName|"QUARK"|VOID*|0xA000003B\r
+ # System Version\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemVersion|"1.0"|VOID*|0xA000003C\r
+ # System SerialNumber String\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSerialNumber|"Unknown"|VOID*|0xA000003D\r
+ # System UUID\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemUuid|{0x23, 0xef, 0xff, 0x13,0x54, 0x86, 0xda, 0x46, 0xa4, 0x7, 0x39, 0xc9, 0x12, 0x2, 0xd3, 0x56}|VOID*|0xA000003E\r
+ # Manufacturer String\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSKUNumber|"System SKUNumber"|VOID*|0xA000003F\r
+ # System Family String\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemFamily|"X1000"|VOID*|0xA0000040\r
+\r
+ # Base Board (or Module) Information (Type 2), Section 3.3.3\r
+ # Board Manufacturer String\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSBoardManufacturer|"Intel Corp."|VOID*|0xA0000041\r
+ # Board Product Name| String\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSBoardProductName|"QUARK"|VOID*|0xA0000042\r
+ # Board Version String\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSBoardVersion|"FAB-D"|VOID*|0xA0000043\r
+ # Board Serial Number\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSBoardSerialNumber|"3"|VOID*|0xA0000044\r
+ # System Enclosure or Chassis(Type 3) Section 3.3.4\r
+ # Chassis Manufacturer String\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSChassisManufacturer|"Chassis Manufacturer"|VOID*|0xA0000045\r
+ # ChassisVersion\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSChassisVersion|"Chassis Version"|VOID*|0xA0000046\r
+ # Chassis SerialNumber String\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSChassisSerialNumber|"Chassis Serial Number"|VOID*|0xA0000047\r
+ # Chassis Asset Tag\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSChassisAssetTag|"Chassis Asset Tag"|VOID*|0xA0000051\r
+ # Chassis Type\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSChassisType|0x00000003|UINT8|0xA0000048\r
+ # Identifies the state of the enclosure when it was last booted. See 3.3.4.2 for definitions.\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSChassisBootupState|0x03|UINT8|0xA0000049\r
+ # Identifies the state of the enclosures power supply (or supplies) when last booted. See 3.3.4.2 for definitions.\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSChassisPowerSupplyState|0x03|UINT8|0xA000004A\r
+ # Identifies the enclosures physical security status when last booted. See 3.3.4.3 for definitions.\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSChassisSecurityState|0x01|UINT8|0xA000004B\r
+ # Contains OEM- or BIOS vendor-specific information.\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSChassisOemDefined|0x0|UINT32|0xA000004C\r
+ # The height of the enclosure, in 'U's. A U is a standard unit of measure for the height of a rack or rack-mountable component\r
+ # and is equal to 1.75 inches or 4.445 cm. A value of 00h indicates that the enclosure height is unspecified.\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSChassisHeight|0x0|UINT8|0xA000004D\r
+ # Identifies the number of power cords associated with the enclosure or chassis. A value of 00h indicates that the number is unspecified.\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSChassisNumberPowerCords|0x0|UINT8|0xA000004E\r
+ # Identifies the number of Contained Element records that follow, in the range 0 to 255.\r
+ # Each Contained Element group comprises m bytes, as specified by the Contained Element Record Length field that follows.\r
+ # If no Contained Elements are included, this field is set to 0.\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSChassisElementCount|0x0|UINT8|0xA000004F\r
+ # Identifies the byte length of each Contained Element record that follow, in the range 0 to 255.\r
+ # If no Contained Elements are included, this field is set to 0. For v2.3.2 and later of this specification,\r
+ # this field is set to at least 03h when Contained Elements are specified.\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSChassisElementRecordLength|0x0|UINT8|0xA0000050\r
+\r
+ # Defines the number of connectors existent on the board\r
+ # The valid range is between 0 and 16\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSConnectorNumber|16|UINT8|0xA0000060\r
+\r
+ # Defines the designator of port1 internal connector\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort1InternalConnectorDesignator|"X14 "|VOID*|0xA0000061\r
+ # Defines the designator of port1 external connector\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort1ExternalConnectorDesignator|"Keyboard"|VOID*|0xA0000062\r
+ # Defines the type of port1 internal connector\r
+ # The valid range is between 0 to 0xFF, and 0 here means EfiPortConnectorTypeNone\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort1InternalConnectorType|0x0F|UINT8|0xA0000063\r
+ # Defines the type of port1 external connector\r
+ # The valid range is between 0 to 0xFF, and 0x0F here means EfiPortConnectorTypePS2\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort1ExternalConnectorType|0x0F|UINT8|0xA0000064\r
+ # Defines the type of port1\r
+ # The valid range is between 0 to 0xFF, and 0x0D here means EfiPortTypeKeyboard\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort1Type|0x0D|UINT8|0xA0000065\r
+\r
+ # Defines the designator of port2 internal connector\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort2InternalConnectorDesignator|"X15 "|VOID*|0xA0000066\r
+ # Defines the designator of port2 external connector\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort2ExternalConnectorDesignator|"Mouse"|VOID*|0xA0000067\r
+ # Defines the type of port2 internal connector\r
+ # The valid range is between 0 to 0xFF, and 0 here means EfiPortConnectorTypeNone\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort2InternalConnectorType|0x0F|UINT8|0xA0000068\r
+ # Defines the type of port2 external connector\r
+ # The valid range is between 0 to 0xFF, and 0x0F here means EfiPortConnectorTypePS2\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort2ExternalConnectorType|0x0F|UINT8|0xA0000069\r
+ # Defines the type of port2\r
+ # The valid range is between 0 to 0xFF, and 0x0E here means EfiPortTypeMouse\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort2Type|0x0E|UINT8|0xA000006A\r
+\r
+ # Defines the designator of port3 internal connector\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort3InternalConnectorDesignator|"X16 "|VOID*|0xA000006B\r
+ # Defines the designator of port3 external connector\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort3ExternalConnectorDesignator|"COM 1"|VOID*|0xA000006C\r
+ # Defines the type of port3 internal connector\r
+ # The valid range is between 0 to 0xFF, and 0xFF here means EfiPortConnectorTypeOther\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort3InternalConnectorType|0xFF|UINT8|0xA000006D\r
+ # Defines the type of port3 external connector\r
+ # The valid range is between 0 to 0xFF, and 0 here means EfiPortConnectorTypeNone\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort3ExternalConnectorType|0x0|UINT8|0xA000006E\r
+ # Defines the type of port3\r
+ # The valid range is between 0 to 0xFF, and 0x09 here means EfiPortTypeSerial16550ACompatible\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort3Type|0x09|UINT8|0xA000006F\r
+\r
+ # Defines the designator of port4 internal connector\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort4InternalConnectorDesignator|"X17 "|VOID*|0xA0000070\r
+ # Defines the designator of port4 external connector\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort4ExternalConnectorDesignator|"COM 2"|VOID*|0xA0000071\r
+ # Defines the type of port4 internal connector\r
+ # The valid range is between 0 to 0xFF, and 0xFF here means EfiPortConnectorTypeOther\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort4InternalConnectorType|0xFF|UINT8|0xA0000072\r
+ # Defines the type of port4 external connector\r
+ # The valid range is between 0 to 0xFF, and 0 here means EfiPortConnectorTypeNone\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort4ExternalConnectorType|0x0|UINT8|0xA0000073\r
+ # Defines the type of port4\r
+ # The valid range is between 0 to 0xFF, and 0x09 here means EfiPortTypeSerial16550ACompatible\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort4Type|0x09|UINT8|0xA0000074\r
+\r
+ # Defines the designator of port5 internal connector\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort5InternalConnectorDesignator|"X18 "|VOID*|0xA0000075\r
+ # Defines the designator of port5 external connector\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort5ExternalConnectorDesignator|"COM 3"|VOID*|0xA0000076\r
+ # Defines the type of port5 internal connector\r
+ # The valid range is between 0 to 0xFF, and 0xFF here means EfiPortConnectorTypeOther\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort5InternalConnectorType|0xFF|UINT8|0xA0000077\r
+ # Defines the type of port5 external connector\r
+ # The valid range is between 0 to 0xFF, and 0 here means EfiPortConnectorTypeNone\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort5ExternalConnectorType|0x0|UINT8|0xA0000078\r
+ # Defines the type of port5\r
+ # The valid range is between 0 to 0xFF, and 0x09 here means EfiPortTypeSerial16550ACompatible\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort5Type|0x09|UINT8|0xA0000079\r
+\r
+ # Defines the designator of port6 internal connector\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort6InternalConnectorDesignator|"X19 "|VOID*|0xA000007A\r
+ # Defines the designator of port6 external connector\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort6ExternalConnectorDesignator|"COM 4"|VOID*|0xA000007B\r
+ # Defines the type of port6 internal connector\r
+ # The valid range is between 0 to 0xFF, and 0xFF here means EfiPortConnectorTypeOther\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort6InternalConnectorType|0xFF|UINT8|0xA000007C\r
+ # Defines the type of port6 external connector\r
+ # The valid range is between 0 to 0xFF, and 0 here means EfiPortConnectorTypeNone\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort6ExternalConnectorType|0x0|UINT8|0xA000007D\r
+ # Defines the type of port6\r
+ # The valid range is between 0 to 0xFF, and 0x09 here means EfiPortTypeSerial16550ACompatible\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort6Type|0x09|UINT8|0xA000007E\r
+\r
+ # Defines the designator of port7 internal connector\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort7InternalConnectorDesignator|"J4A2"|VOID*|0xA000007F\r
+ # Defines the designator of port7 external connector\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort7ExternalConnectorDesignator|"LPT 1"|VOID*|0xA0000080\r
+ # Defines the type of port7 internal connector\r
+ # The valid range is between 0 to 0xFF, and 0 here means EfiPortConnectorTypeNone\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort7InternalConnectorType|0x0|UINT8|0xA0000081\r
+ # Defines the type of port7 external connector\r
+ # The valid range is between 0 to 0xFF, and 0x12 here means EfiPortConnectorTypeDB25Male\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort7ExternalConnectorType|0x04|UINT8|0xA0000082\r
+ # Defines the type of port7\r
+ # The valid range is between 0 to 0xFF, and 0x10 here means EfiPortTypeEcpEpp\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort7Type|0x05|UINT8|0xA0000083\r
+\r
+ # Defines the designator of port8 internal connector\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort8InternalConnectorDesignator|"X20 "|VOID*|0xA0000084\r
+ # Defines the designator of port8 external connector\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort8ExternalConnectorDesignator|"USB1"|VOID*|0xA0000085\r
+ # Defines the type of port8 internal connector\r
+ # The valid range is between 0 to 0xFF, and 0 here means EfiPortConnectorTypeNone\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort8InternalConnectorType|0x0|UINT8|0xA0000086\r
+ # Defines the type of port8 external connector\r
+ # The valid range is between 0 to 0xFF, and 0x12 here means EfiPortConnectorTypeUsb\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort8ExternalConnectorType|0x12|UINT8|0xA0000087\r
+ # Defines the type of port8\r
+ # The valid range is between 0 to 0xFF, and 0x10 here means EfiPortTypeUsb\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort8Type|0x10|UINT8|0xA0000088\r
+\r
+ # Defines the designator of port9 internal connector\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort9InternalConnectorDesignator|"X21 "|VOID*|0xA0000089\r
+ # Defines the designator of port9 external connector\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort9ExternalConnectorDesignator|"USB2"|VOID*|0xA000008A\r
+ # Defines the type of port9 internal connector\r
+ # The valid range is between 0 to 0xFF, and 0 here means EfiPortConnectorTypeNone\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort9InternalConnectorType|0x0|UINT8|0xA000008B\r
+ # Defines the type of port9 external connector\r
+ # The valid range is between 0 to 0xFF, and 0x12 here means EfiPortConnectorTypeUsb\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort9ExternalConnectorType|0x12|UINT8|0xA000008C\r
+ # Defines the type of port9\r
+ # The valid range is between 0 to 0xFF, and 0x10 here means EfiPortTypeUsb\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort9Type|0x10|UINT8|0xA000008D\r
+\r
+ # Defines the designator of port10 internal connector\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort10InternalConnectorDesignator|"X22 "|VOID*|0xA000008E\r
+ # Defines the designator of port10 external connector\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort10ExternalConnectorDesignator|"USB3"|VOID*|0xA000008F\r
+ # Defines the type of port10 internal connector\r
+ # The valid range is between 0 to 0xFF, and 0 here means EfiPortConnectorTypeNone\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort10InternalConnectorType|0x0|UINT8|0xA0000090\r
+ # Defines the type of port10 external connector\r
+ # The valid range is between 0 to 0xFF, and 0x12 here means EfiPortConnectorTypeUsb\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort10ExternalConnectorType|0x12|UINT8|0xA0000091\r
+ # Defines the type of port10\r
+ # The valid range is between 0 to 0xFF, and 0x10 here means EfiPortTypeUsb\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort10Type|0x10|UINT8|0xA0000092\r
+\r
+ # Defines the designator of port11 internal connector\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort11InternalConnectorDesignator|"X23 "|VOID*|0xA0000093\r
+ # Defines the designator of port11 external connector\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort11ExternalConnectorDesignator|"USB4"|VOID*|0xA0000094\r
+ # Defines the type of port11 internal connector\r
+ # The valid range is between 0 to 0xFF, and 0 here means EfiPortConnectorTypeNone\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort11InternalConnectorType|0x0|UINT8|0xA0000095\r
+ # Defines the type of port11 external connector\r
+ # The valid range is between 0 to 0xFF, and 0x12 here means EfiPortConnectorTypeUsb\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort11ExternalConnectorType|0x12|UINT8|0xA0000096\r
+ # Defines the type of port11\r
+ # The valid range is between 0 to 0xFF, and 0x10 here means EfiPortTypeUsb\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort11Type|0x10|UINT8|0xA0000097\r
+\r
+ # Defines the designator of port12 internal connector\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort12InternalConnectorDesignator|"X28 "|VOID*|0xA0000098\r
+ # Defines the designator of port12 external connector\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort12ExternalConnectorDesignator|"RJ-45 Type"|VOID*|0xA0000099\r
+ # Defines the type of port12 internal connector\r
+ # The valid range is between 0 to 0xFF, and 0 here means EfiPortConnectorTypeNone\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort12InternalConnectorType|0x0|UINT8|0xA000009A\r
+ # Defines the type of port12 external connector\r
+ # The valid range is between 0 to 0xFF, and 0x0B here means EfiPortConnectorTypeRJ45\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort12ExternalConnectorType|0x0B|UINT8|0xA000009B\r
+ # Defines the type of port12\r
+ # The valid range is between 0 to 0xFF, and 0x1F here means EfiPortTypeNetworkPort\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort12Type|0x1F|UINT8|0xA000009C\r
+\r
+ # Defines the designator of port13 internal connector\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort13InternalConnectorDesignator|"J1G1"|VOID*|0xA000009D\r
+ # Defines the designator of port13 external connector\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort13ExternalConnectorDesignator|"Floppy"|VOID*|0xA000009E\r
+ # Defines the type of port13 internal connector\r
+ # The valid range is between 0 to 0xFF, and 0x16 here means EfiPortConnectorTypeOnboardFloppy\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort13InternalConnectorType|0x17|UINT8|0xA000009F\r
+ # Defines the type of port13 external connector\r
+ # The valid range is between 0 to 0xFF, and 0 here means EfiPortConnectorTypeNone\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort13ExternalConnectorType|0x0|UINT8|0xA00000A0\r
+ # Defines the type of port13\r
+ # The valid range is between 0 to 0xFF, and 0xFF here means EfiPortTypeOther\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort13Type|0xFF|UINT8|0xA00000A1\r
+\r
+ # Defines the designator of port14 internal connector\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort14InternalConnectorDesignator|"J2H2"|VOID*|0xA00000A2\r
+ # Defines the designator of port14 external connector\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort14ExternalConnectorDesignator|"IDE"|VOID*|0xA00000A3\r
+ # Defines the type of port14 internal connector\r
+ # The valid range is between 0 to 0xFF, and 0x16 here means EfiPortConnectorTypeOnboardIde\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort14InternalConnectorType|0x16|UINT8|0xA00000A4\r
+ # Defines the type of port14 external connector\r
+ # The valid range is between 0 to 0xFF, and 0 here means EfiPortConnectorTypeNone\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort14ExternalConnectorType|0x0|UINT8|0xA00000A5\r
+ # Defines the type of port14\r
+ # The valid range is between 0 to 0xFF, and 0xFF here means EfiPortTypeOther\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort14Type|0xFF|UINT8|0xA00000A6\r
+\r
+ # Defines the designator of port15 internal connector\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort15InternalConnectorDesignator|"X29 "|VOID*|0xA00000A7\r
+ # Defines the designator of port15 external connector\r
+\r
+ # Defines the type of port15 internal connector\r
+ # The valid range is between 0 to 0xFF, and 0x16 here means EfiPortConnectorTypeOnboardIde\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort15InternalConnectorType|0x16|UINT8|0xA00000A9\r
+ # Defines the type of port15 external connector\r
+ # The valid range is between 0 to 0xFF, and 0 here means EfiPortConnectorTypeNone\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort15ExternalConnectorType|0x0|UINT8|0xA00000AA\r
+ # Defines the type of port15\r
+ # The valid range is between 0 to 0xFF, and 0xFF here means EfiPortTypeOther\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort15Type|0xFF|UINT8|0xA00000AB\r
+\r
+ # Defines the designator of port16 internal connector\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort16InternalConnectorDesignator|"X30 "|VOID*|0xA00000AC\r
+ # Defines the designator of port16 external connector\r
+\r
+ # Defines the type of port16 internal connector\r
+ # The valid range is between 0 to 0xFF, and 0x16 here means EfiPortConnectorTypeOnboardIde\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort16InternalConnectorType|0x16|UINT8|0xA00000AE\r
+ # Defines the type of port16 external connector\r
+ # The valid range is between 0 to 0xFF, and 0 here means EfiPortConnectorTypeNone\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort16ExternalConnectorType|0x0|UINT8|0xA00000AF\r
+ # Defines the type of port16\r
+ # The valid range is between 0 to 0xFF, and 0xFF here means EfiPortTypeOther\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSPort16Type|0xFF|UINT8|0xA00000B0\r
+\r
+ # Defines the number of the slots existent on board\r
+ # The valid range is between 0 and 14\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlotNumber|5|UINT8|0xA000023F\r
+ # Defines the designation of system slot1\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot1Designation|"PCI SLOT1"|VOID*|0xA0000240\r
+ # Defines the type of system slot1\r
+ # The valid range is between 0x01 to 0xA5, and 0x06 here means EfiSlotTypePci\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot1Type|0x6|UINT8|0xA0000241\r
+ # Defines the data bus width of system slot1\r
+ # The valid range is between 0x01 to 0x07, and 0x05 here means EfiSlotDataBusWidth32Bit\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot1DataBusWidth|0x5|UINT8|0xA0000242\r
+ # Defines the usage of system slot1\r
+ # The valid range is between 0x01 to 0x04, and 0x03 here means EfiSlotUsageAvailable\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot1Usage|0x3|UINT8|0xA0000243\r
+ # Defines the length of system slot1\r
+ # The valid range is between 0x01 to 0x04, and 0x04 here means EfiSlotLengthLong\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot1Length|0x4|UINT8|0xA0000244\r
+ # Defines the ID of system slot1, a number of UINT16\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot1Id|0x01|UINT16|0xA0000245\r
+ # Defines the characteristics of system slot1 , a bit mask of EFI_MISC_SLOT_CHARACTERISTICS\r
+ # typedef struct {\r
+ # UINT32 CharacteristicsUnknown :1;\r
+ # UINT32 Provides50Volts :1;\r
+ # UINT32 Provides33Volts :1;\r
+ # UINT32 SharedSlot :1;\r
+ # UINT32 PcCard16Supported :1;\r
+ # UINT32 CardBusSupported :1;\r
+ # UINT32 ZoomVideoSupported :1;\r
+ # UINT32 ModemRingResumeSupported:1;\r
+ # UINT32 PmeSignalSupported :1;\r
+ # UINT32 HotPlugDevicesSupported :1;\r
+ # UINT32 SmbusSignalSupported :1;\r
+ # UINT32 Reserved :21;\r
+ # } EFI_MISC_SLOT_CHARACTERISTICS;\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot1Characteristics|0x504|UINT32|0xA0000246\r
+\r
+ # Defines the designation of system slot2\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot2Designation|"PCI-Express 1"|VOID*|0xA0000247\r
+\r
+ # Defines the type of system slot2\r
+ # The valid range is between 0x01 to 0xA5, and 0x06 here means EfiSlotTypePci\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot2Type|0xA5|UINT8|0xA0000248\r
+ # Defines the data bus width of system slot2\r
+ # The valid range is between 0x01 to 0x07, and 0x05 here means EfiSlotDataBusWidth32Bit\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot2DataBusWidth|0x5|UINT8|0xA0000249\r
+ # Defines the usage of system slot2\r
+ # The valid range is between 0x01 to 0x04, and 0x03 here means EfiSlotUsageAvailable\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot2Usage|0x3|UINT8|0xA000024A\r
+ # Defines the length of system slot2\r
+ # The valid range is between 0x01 to 0x04, and 0x04 here means EfiSlotLengthLong\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot2Length|0x4|UINT8|0xA000024B\r
+ # Defines the ID of system slot2, a number of UINT16\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot2Id|0x02|UINT16|0xA000024C\r
+ # Defines the characteristics of system slot2 , a bit mask of EFI_MISC_SLOT_CHARACTERISTICS\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot2Characteristics|0x504|UINT32|0xA000024D\r
+\r
+ # Defines the designation of system slot3\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot3Designation|"PCI-Express 2"|VOID*|0xA000024E\r
+ # Defines the type of system slot3\r
+ # The valid range is between 0x01 to 0xA5, and 0x06 here means EfiSlotTypePci\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot3Type|0xA5|UINT8|0xA000024F\r
+ # Defines the data bus width of system slot3\r
+ # The valid range is between 0x01 to 0x07, and 0x05 here means EfiSlotDataBusWidth32Bit\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot3DataBusWidth|0x5|UINT8|0xA0000250\r
+ # Defines the usage of system slot3\r
+ # The valid range is between 0x01 to 0x04, and 0x03 here means EfiSlotUsageAvailable\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot3Usage|0x3|UINT8|0xA0000251\r
+ # Defines the length of system slot3\r
+ # The valid range is between 0x01 to 0x04, and 0x04 here means EfiSlotLengthLong\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot3Length|0x4|UINT8|0xA0000252\r
+ # Defines the ID of system slot3, a number of UINT16\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot3Id|0x03|UINT16|0xA0000253\r
+ # Defines the characteristics of system slot3 , a bit mask of EFI_MISC_SLOT_CHARACTERISTICS\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot3Characteristics|0x504|UINT32|0xA000254\r
+\r
+ # Defines the designation of system slot4\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot4Designation|"PCI-Express 3"|VOID*|0xA0000255\r
+ # Defines the type of system slot4\r
+ # The valid range is between 0x01 to 0xA5, and 0xA5 here means EfiSlotTypePciExpress\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot4Type|0xA5|UINT8|0xA0000256\r
+ # Defines the data bus width of system slot4\r
+ # The valid range is between 0x01 to 0x07, and 0x05 here means EfiSlotDataBusWidth32Bit\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot4DataBusWidth|0x5|UINT8|0xA0000257\r
+ # Defines the usage of system slot4\r
+ # The valid range is between 0x01 to 0x04, and 0x03 here means EfiSlotUsageAvailable\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot4Usage|0x3|UINT8|0xA0000258\r
+ # Defines the length of system slot4\r
+ # The valid range is between 0x01 to 0x04, and 0x04 here means EfiSlotLengthLong\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot4Length|0x4|UINT8|0xA0000259\r
+ # Defines the ID of system slot4, a number of UINT16\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot4Id|0x04|UINT16|0xA0000260\r
+ # Defines the characteristics of system slot4 , a bit mask of EFI_MISC_SLOT_CHARACTERISTICS\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot4Characteristics|0x504|UINT32|0xA0000261\r
+\r
+ # Defines the designation of system slot5\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot5Designation|"Mini PCI-E"|VOID*|0xA0000262\r
+ # Defines the type of system slot5\r
+ # The valid range is between 0x01 to 0xA5, and 0xA5 here means EfiSlotTypePciExpress\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot5Type|0xA5|UINT8|0xA0000263\r
+ # Defines the data bus width of system slot5\r
+ # The valid range is between 0x01 to 0x07, and 0x05 here means EfiSlotDataBusWidth32Bit\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot5DataBusWidth|0x5|UINT8|0xA0000264\r
+ # Defines the usage of system slot5\r
+ # The valid range is between 0x01 to 0x04, and 0x03 here means EfiSlotUsageAvailable\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot5Usage|0x3|UINT8|0xA0000265\r
+ # Defines the length of system slot5\r
+ # The valid range is between 0x01 to 0x04, and 0x04 here means EfiSlotLengthLong\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot5Length|0x4|UINT8|0xA0000266\r
+ # Defines the ID of system slot5, a number of UINT16\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot5Id|0x05|UINT16|0xA0000267\r
+ # Defines the characteristics of system slot5 , a bit mask of EFI_MISC_SLOT_CHARACTERISTICS\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot5Characteristics|0x504|UINT32|0xA0000268\r
+\r
+ # Defines the designation of system slot6\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot6Designation|"NONE"|VOID*|0xA0000269\r
+ # Defines the type of system slot6\r
+ # The valid range is between 0x01 to 0xA5, and 0x02 here means EfiSlotTypeUnknown\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot6Type|0x2|UINT8|0xA000026A\r
+ # Defines the data bus width of system slot6\r
+ # The valid range is between 0x01 to 0x07, and 0x02 here means EfiSlotDataBusWidthUnknown\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot6DataBusWidth|0x2|UINT8|0xA000026B\r
+ # Defines the usage of system slot6\r
+ # The valid range is between 0x01 to 0x04, and 0x02 here means EfiSlotUsageUnknown\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot6Usage|0x2|UINT8|0xA000026C\r
+ # Defines the length of system slot6\r
+ # The valid range is between 0x01 to 0x04, and 0x02 here means EfiSlotLengthUnknown\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot6Length|0x2|UINT8|0xA000026D\r
+ # Defines the ID of system slot6, a number of UINT16\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot6Id|0x0|UINT16|0xA000026E\r
+ # Defines the characteristics of system slot6 , a bit mask of EFI_MISC_SLOT_CHARACTERISTICS\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot6Characteristics|0x0|UINT32|0xA000026F\r
+\r
+ # Defines the designation of system slot7\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot7Designation|"NONE"|VOID*|0xA0000270\r
+ # Defines the type of system slot7\r
+ # The valid range is between 0x01 to 0xA5, and 0x02 here means EfiSlotTypeUnknown\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot7Type|0x2|UINT8|0xA0000271\r
+ # Defines the data bus width of system slot7\r
+ # The valid range is between 0x01 to 0x07, and 0x02 here means EfiSlotDataBusWidthUnknown\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot7DataBusWidth|0x2|UINT8|0xA0000272\r
+ # Defines the usage of system slot7\r
+ # The valid range is between 0x01 to 0x04, and 0x02 here means EfiSlotUsageUnknown\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot7Usage|0x2|UINT8|0xA0000273\r
+ # Defines the length of system slot7\r
+ # The valid range is between 0x01 to 0x04, and 0x02 here means EfiSlotLengthUnknown\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot7Length|0x2|UINT8|0xA0000274\r
+ # Defines the ID of system slot7, a number of UINT16\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot7Id|0x0|UINT16|0xA0000275\r
+ # Defines the characteristics of system slot7 , a bit mask of EFI_MISC_SLOT_CHARACTERISTICS\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot7Characteristics|0x0|UINT32|0xA0000276\r
+\r
+ # Defines the designation of system slot8\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot8Designation|"NONE"|VOID*|0xA0000277\r
+ # Defines the type of system slot8\r
+ # The valid range is between 0x01 to 0xA5, and 0x02 here means EfiSlotTypeUnknown\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot8Type|0x2|UINT8|0xA0000278\r
+ # Defines the data bus width of system slot8\r
+ # The valid range is between 0x01 to 0x07, and 0x02 here means EfiSlotDataBusWidthUnknown\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot8DataBusWidth|0x2|UINT8|0xA0000279\r
+ # Defines the usage of system slot8\r
+ # The valid range is between 0x01 to 0x04, and 0x02 here means EfiSlotUsageUnknown\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot8Usage|0x2|UINT8|0xA000027A\r
+ # Defines the length of system slot8\r
+ # The valid range is between 0x01 to 0x04, and 0x02 here means EfiSlotLengthUnknown\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot8Length|0x2|UINT8|0xA000027B\r
+ # Defines the ID of system slot8, a number of UINT16\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot8Id|0x0|UINT16|0xA000027C\r
+ # Defines the characteristics of system slot8 , a bit mask of EFI_MISC_SLOT_CHARACTERISTICS\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot8Characteristics|0x0|UINT32|0xA000027D\r
+\r
+ # Defines the designation of system slot9\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot9Designation|"NONE"|VOID*|0xA000027E\r
+ # Defines the type of system slot9\r
+ # The valid range is between 0x01 to 0xA5, and 0x02 here means EfiSlotTypeUnknown\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot9Type|0x2|UINT8|0xA000027F\r
+ # Defines the data bus width of system slot9\r
+ # The valid range is between 0x01 to 0x07, and 0x02 here means EfiSlotDataBusWidthUnknown\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot9DataBusWidth|0x2|UINT8|0xA0000280\r
+ # Defines the usage of system slot9\r
+ # The valid range is between 0x01 to 0x04, and 0x02 here means EfiSlotUsageUnknown\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot9Usage|0x2|UINT8|0xA0000281\r
+ # Defines the length of system slot9\r
+ # The valid range is between 0x01 to 0x04, and 0x02 here means EfiSlotLengthUnknown\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot9Length|0x2|UINT8|0xA0000282\r
+ # Defines the ID of system slot9, a number of UINT16\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot9Id|0x0|UINT16|0xA0000283\r
+ # Defines the characteristics of system slot9 , a bit mask of EFI_MISC_SLOT_CHARACTERISTICS\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot9Characteristics|0x0|UINT32|0xA0000284\r
+\r
+ # Defines the designation of system slot10\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot10Designation|"None"|VOID*|0xA0000285\r
+ # Defines the type of system slot10\r
+ # The valid range is between 0x01 to 0xA5, and 0x02 here means EfiSlotTypeUnknown\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot10Type|0x2|UINT8|0xA0000286\r
+ # Defines the data bus width of system slot10\r
+ # The valid range is between 0x01 to 0x07, and 0x02 here means EfiSlotDataBusWidthUnknown\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot10DataBusWidth|0x2|UINT8|0xA0000287\r
+ # Defines the usage of system slot10\r
+ # The valid range is between 0x01 to 0x04, and 0x02 here means EfiSlotUsageUnknown\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot10Usage|0x2|UINT8|0xA0000288\r
+ # Defines the length of system slot10\r
+ # The valid range is between 0x01 to 0x04, and 0x02 here means EfiSlotLengthUnknown\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot10Length|0x2|UINT8|0xA0000289\r
+ # Defines the ID of system slot10, a number of UINT16\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot10Id|0x0|UINT16|0xA000028A\r
+ # Defines the characteristics of system slot10 , a bit mask of EFI_MISC_SLOT_CHARACTERISTICS\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot10Characteristics|0x0|UINT32|0xA000028B\r
+\r
+ # Defines the designation of system slot11\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot11Designation|"None"|VOID*|0xA000028C\r
+ # Defines the type of system slot11\r
+ # The valid range is between 0x01 to 0xA5, and 0x02 here means EfiSlotTypeUnknown\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot11Type|0x2|UINT8|0xA000028D\r
+ # Defines the data bus width of system slot11\r
+ # The valid range is between 0x01 to 0x07, and 0x02 here means EfiSlotDataBusWidthUnknown\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot11DataBusWidth|0x2|UINT8|0xA000028E\r
+ # Defines the usage of system slot11\r
+ # The valid range is between 0x01 to 0x04, and 0x02 here means EfiSlotUsageUnknown\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot11Usage|0x2|UINT8|0xA000028F\r
+ # Defines the length of system slot11\r
+ # The valid range is between 0x01 to 0x04, and 0x02 here means EfiSlotLengthUnknown\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot11Length|0x2|UINT8|0xA0000290\r
+ # Defines the ID of system slot11, a number of UINT16\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot11Id|0x0|UINT16|0xA00000EE\r
+ # Defines the characteristics of system slot11 , a bit mask of EFI_MISC_SLOT_CHARACTERISTICS\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot11Characteristics|0x0|UINT32|0xA0000291\r
+\r
+ # Defines the designation of system slot12\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot12Designation|"None"|VOID*|0xA0000292\r
+ # Defines the type of system slot12\r
+ # The valid range is between 0x01 to 0xA5, and 0x02 here means EfiSlotTypeUnknown\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot12Type|0x2|UINT8|0xA0000293\r
+ # Defines the data bus width of system slot12\r
+ # The valid range is between 0x01 to 0x07, and 0x02 here means EfiSlotDataBusWidthUnknown\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot12DataBusWidth|0x2|UINT8|0xA0000294\r
+ # Defines the usage of system slot12\r
+ # The valid range is between 0x01 to 0x04, and 0x02 here means EfiSlotUsageUnknown\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot12Usage|0x2|UINT8|0xA0000295\r
+ # Defines the length of system slot12\r
+ # The valid range is between 0x01 to 0x04, and 0x02 here means EfiSlotLengthUnknown\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot12Length|0x2|UINT8|0xA0000296\r
+ # Defines the ID of system slot12, a number of UINT16\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot12Id|0x0|UINT16|0xA0000297\r
+ # Defines the characteristics of system slot12 , a bit mask of EFI_MISC_SLOT_CHARACTERISTICS\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot12Characteristics|0x0|UINT32|0xA0000298\r
+\r
+ # Defines the designation of system slot13\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot13Designation|"None"|VOID*|0xA0000299\r
+ # Defines the type of system slot13\r
+ # The valid range is between 0x01 to 0xA5, and 0x02 here means EfiSlotTypeUnknown\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot13Type|0x2|UINT8|0xA000029A\r
+ # Defines the data bus width of system slot13\r
+ # The valid range is between 0x01 to 0x07, and 0x02 here means EfiSlotDataBusWidthUnknown\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot13DataBusWidth|0x2|UINT8|0xA000029B\r
+ # Defines the usage of system slot13\r
+ # The valid range is between 0x01 to 0x04, and 0x02 here means EfiSlotUsageUnknown\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot13Usage|0x2|UINT8|0xA000029C\r
+ # Defines the length of system slot13\r
+ # The valid range is between 0x01 to 0x04, and 0x02 here means EfiSlotLengthUnknown\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot13Length|0x2|UINT8|0xA000029D\r
+ # Defines the ID of system slot13, a number of UINT16\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot13Id|0x0|UINT16|0xA000029E\r
+ # Defines the characteristics of system slot13 , a bit mask of EFI_MISC_SLOT_CHARACTERISTICS\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot13Characteristics|0x0|UINT32|0xA000029F\r
+\r
+ # Defines the designation of system slot14\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot14Designation|"None"|VOID*|0xA00002A0\r
+ # Defines the type of system slot14\r
+ # The valid range is between 0x01 to 0xA5, and 0x02 here means EfiSlotTypeUnknown\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot14Type|0x2|UINT8|0xA00002A1\r
+ # Defines the data bus width of system slot14\r
+ # The valid range is between 0x01 to 0x07, and 0x02 here means EfiSlotDataBusWidthUnknown\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot14DataBusWidth|0x2|UINT8|0xA00002A2\r
+ # Defines the usage of system slot14\r
+ # The valid range is between 0x01 to 0x04, and 0x02 here means EfiSlotUsageUnknown\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot14Usage|0x2|UINT8|0xA00002A3\r
+ # Defines the length of system slot14\r
+ # The valid range is between 0x01 to 0x04, and 0x02 here means EfiSlotLengthUnknown\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot14Length|0x2|UINT8|0xA00002A4\r
+ # Defines the ID of system slot14, a number of UINT16\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot14Id|0x0|UINT16|0xA00002A5\r
+ # Defines the characteristics of system slot14 , a bit mask of EFI_MISC_SLOT_CHARACTERISTICS\r
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot14Characteristics|0x0|UINT32|0xA00002A6\r
+\r
+ gQuarkPlatformTokenSpaceGuid.PcdFlashFvPayloadBase|0xFFC00400|UINT32|0xA00002A7\r
+ gQuarkPlatformTokenSpaceGuid.PcdFlashFvPayloadSize|0x000F0000|UINT32|0xA00002A8\r
+ gQuarkPlatformTokenSpaceGuid.PcdFlashFvMainBase|0xFFD00400|UINT32|0xA00002A9\r
+ gQuarkPlatformTokenSpaceGuid.PcdFlashFvMainSize|0x000D0000|UINT32|0xA00002AA\r
+ gQuarkPlatformTokenSpaceGuid.PcdFlashFvRecoveryBase|0xFFEC0400|UINT32|0xA00002AB\r
+ gQuarkPlatformTokenSpaceGuid.PcdFlashFvRecoverySize|0x0003F000|UINT32|0xA00002AC\r
+\r
+[PcdsDynamic, PcdsDynamicEx]\r
+ ## Provides the ability to enable the Fast Boot feature of the BIOS. This\r
+ # enables the system to boot faster but may only enumerate the hardware\r
+ # that is required to boot the system.<BR>\r
+ #\r
+ # @Prompt Fast Boot Support\r
+ #\r
+ gQuarkPlatformTokenSpaceGuid.PcdEnableFastBoot|FALSE|BOOLEAN|0xB000004\r
+\r
+ ## Determines if the user is physically present. This information is collected and shared\r
+ # with all other modules using a dynamic PCD.<BR>\r
+ #\r
+ # @Prompt The User is Physically Present\r
+ #\r
+ gQuarkPlatformTokenSpaceGuid.PcdUserIsPhysicallyPresent|FALSE|BOOLEAN|0xB000006\r
+\r
+ ## The Quark SOC X1000 Based Platform Type.<BR>\r
+ # 0x0000 - Unknown<BR>\r
+ # 0x0001 - Quark Emulation<BR>\r
+ # 0x0002 - ClantonPeak SVP<BR>\r
+ # 0x0003 - KipsBay<BR>\r
+ # 0x0004 - CrossHill<BR>\r
+ # 0x0005 - ClantonHill<BR>\r
+ # 0x0006 - Galileo Gen 1<BR>\r
+ # 0x0007 - Reserved<BR>\r
+ # 0x0008 - Galileo Gen 2<BR>\r
+ #\r
+ # @Prompt The Quark SOC X1000 Based Platform Type\r
+ #\r
+ gQuarkPlatformTokenSpaceGuid.PcdPlatformType|0x0008|UINT16|0xB000007\r
+\r
+ ## The Quark SOC X1000 Based Platform Type Name.<BR>\r
+ #\r
+ # @Prompt The Quark SOC X1000 Based Platform Type Name\r
+ #\r
+ gQuarkPlatformTokenSpaceGuid.PcdPlatformTypeName|L"GalileoGen2"|VOID*|0xB000008\r
+\r
+ ## The size, in bytes, of the SPI FLASH part attached to Quark SOC X1000\r
+ #\r
+ # @Prompt The SPI FALSH Part Size\r
+ #\r
+ gQuarkPlatformTokenSpaceGuid.PcdSpiFlashDeviceSize|0|UINT32|0xB000009\r
projects / mirror_edk2.git / commitdiff