QuarkPlatformPkg/Library/PlatformSecLib/Ia32/Platform.inc

   1 ;
   2 ; Copyright (c) 2013-2015 Intel Corporation.
   3 ;
   4 ; This program and the accompanying materials
   5 ; are licensed and made available under the terms and conditions of the BSD License
   6 ; which accompanies this distribution.  The full text of the license may be found at
   7 ; http://opensource.org/licenses/bsd-license.php
   8 ;
   9 ; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  10 ; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  11 ;
  12 ;------------------------------------------------------------------------------
  13 ;
  14 ; Module Name:
  15 ;
  16 ;   Platform.inc
  17 ;
  18 ; Abstract:
  19 ;
  20 ;   Quark A0 Platform Specific Definitions
  21 ;
  22 ;------------------------------------------------------------------------------
  23
  24 JMP32 MACRO FunctionName
  25   lea  esp, @F
  26   jmp  FunctionName
  27 @@:
  28 ENDM
  29
  30 RET32 MACRO
  31     jmp    esp
  32 ENDM
  33
  34 ;
  35 ; ROM/SPI/MEMORY Definitions
  36 ;
  37 QUARK_DDR3_MEM_BASE_ADDRESS    EQU 000000000h    ; Memory Base Address = 0
  38 QUARK_MAX_DDR3_MEM_SIZE_BYTES    EQU 080000000h    ; DDR3 Memory Size = 2GB
  39 QUARK_ESRAM_MEM_SIZE_BYTES    EQU 000080000h    ; eSRAM Memory Size = 512K
  40 QUARK_STACK_SIZE_BYTES      EQU 008000h      ; Quark stack size = 32K
  41
  42 ;
  43 ; RTC/CMOS definitions
  44 ;
  45 RTC_INDEX      EQU 070h
  46   NMI_DISABLE  EQU 080h    ; Bit7=1 disables NMI
  47   NMI_ENABLE  EQU 000h    ; Bit7=0 disables NMI
  48 RTC_DATA      EQU 071h
  49
  50 ;
  51 ; PCI Configuration definitions
  52 ;
  53 PCI_CFG            EQU 1 SHL 01Fh  ; PCI configuration access mechanism
  54 PCI_ADDRESS_PORT  EQU 0CF8h
  55 PCI_DATA_PORT      EQU 0CFCh
  56
  57 ;
  58 ; Quark PCI devices
  59 ;
  60 HOST_BRIDGE_PFA        EQU 0000h          ; B0:D0:F0 (Host Bridge)
  61 ILB_PFA          EQU 00F8h          ; B0:D31:F0 (Legacy Block)
  62
  63 ;
  64 ; ILB PCI Config Registers
  65 ;
  66 BDE                              EQU 0D4h        ; BIOS Decode Enable register
  67   DECODE_ALL_REGIONS_ENABLE      EQU 0FF000000h  ; Decode all BIOS decode ranges
  68
  69
  70 ;
  71 ; iLB Reset Register
  72 ;
  73 ILB_RESET_REG      EQU 0CF9h
  74   CF9_WARM_RESET    EQU  02h
  75   CF9_COLD_RESET    EQU  08h
  76
  77 ;
  78 ; Host Bridge PCI Config Registers
  79 ;
  80 MESSAGE_BUS_CONTROL_REG                    EQU 0D0h  ; Message Bus Control Register
  81   SB_OPCODE_FIELD                EQU 018h  ; Bit location of Opcode field
  82     OPCODE_SIDEBAND_REG_READ    EQU 010h  ; Read opcode
  83     OPCODE_SIDEBAND_REG_WRITE    EQU 011h  ; Write opcode
  84     OPCODE_SIDEBAND_ALT_REG_READ  EQU 06h    ; Alternate Read opcode
  85     OPCODE_SIDEBAND_ALT_REG_WRITE  EQU 07h    ; Alternate Write opcode
  86     OPCODE_WARM_RESET_REQUEST    EQU 0F4h  ; Reset Warm
  87     OPCODE_COLD_RESET_REQUEST    EQU 0F5h  ; Reset Cold
  88   SB_PORT_FIELD                  EQU 010h  ; Bit location of Port ID field
  89     MEMORY_ARBITER_PORT_ID                EQU 00h
  90     HOST_BRIDGE_PORT_ID                EQU 03h
  91     RMU_PORT_ID                EQU 04h
  92     MEMORY_MANAGER_PORT_ID                EQU 05h
  93     SOC_UNIT_PORT_ID              EQU  031h
  94   SB_ADDR_FIELD                  EQU 008h  ; Bit location of Register field
  95   SB_BE_FIELD                    EQU  004h  ; Bit location of Byte Enables field
  96     ALL_BYTE_EN                  EQU  00Fh  ; All Byte Enables
  97 MESSAGE_DATA_REG                      EQU 0D4h  ; Message Data Register
  98
  99 ;
 100 ; Memory Arbiter Config Registers
 101 ;
 102 AEC_CTRL_OFFSET    EQU 00h
 103
 104 ;
 105 ; Host Bridge Config Registers
 106 ;
 107 HMISC2_OFFSET      EQU 03h
 108   OR_PM_FIELD      EQU 010h
 109     SMI_EN        EQU 1 SHL 13h
 110
 111 HMBOUND_OFFSET    EQU 08h
 112   HMBOUND_ADDRESS  EQU (QUARK_DDR3_MEM_BASE_ADDRESS + QUARK_MAX_DDR3_MEM_SIZE_BYTES + QUARK_ESRAM_MEM_SIZE_BYTES)
 113   HMBOUND_LOCK  EQU 00000001h
 114 HECREG_OFFSET    EQU 09h
 115   EC_BASE      EQU 0E0000000h
 116   EC_ENABLE    EQU 01h
 117 HLEGACY_OFFSET    EQU 0Ah
 118   NMI              EQU 1 SHL 0Eh  ; Pin 14
 119   SMI              EQU 1 SHL 0Ch  ; Pin 12
 120   INTR             EQU 1 SHL 0Ah  ; Pin 10
 121
 122
 123 ;
 124 ; Memory Manager Config Registers
 125 ;
 126 ESRAMPGCTRL_BLOCK_OFFSET  EQU 082h
 127   BLOCK_ENABLE_PG      EQU 010000000h
 128 BIMRVCTL_OFFSET        EQU 019h
 129   ENABLE_IMR_INTERRUPT  EQU 080000000h
 130
 131 ;
 132 ; SOC UNIT Debug Registers
 133 ;
 134 CFGSTICKY_W1_OFFSET          EQU 050h
 135   FORCE_COLD_RESET      EQU  00000001h
 136 CFGSTICKY_RW_OFFSET            EQU 051h
 137   RESET_FOR_ESRAM_LOCK    EQU  00000020h
 138   RESET_FOR_HMBOUND_LOCK    EQU  00000040h
 139 CFGNONSTICKY_W1_OFFSET        EQU 052h
 140   FORCE_WARM_RESET      EQU  00000001h