QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/Platform.asl

   1 /** @file
   2 Contains root level name space objects for the platform
   3
   4 Copyright (c) 2013-2015 Intel Corporation.
   5
   6 This program and the accompanying materials
   7 are licensed and made available under the terms and conditions of the BSD License
   8 which accompanies this distribution.  The full text of the license may be found at
   9 http://opensource.org/licenses/bsd-license.php
  10
  11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  13
  14 **/
  15
  16 //
  17 // OS TYPE DEFINITION
  18 //
  19 #define WINDOWS_XP          0x01
  20 #define WINDOWS_XP_SP1      0x02
  21 #define WINDOWS_XP_SP2      0x04
  22 #define WINDOWS_2003        0x08
  23 #define WINDOWS_Vista       0x10
  24 #define WINDOWS_WIN7        0x11
  25 #define WINDOWS_WIN8        0x12
  26 #define WINDOWS_WIN8_1      0x13
  27 #define LINUX               0xF0
  28
  29 //
  30 // GPIO Interrupt Connection Resource Descriptor (GpioInt) usage.
  31 // GpioInt() descriptors maybe used in this file and included .asi files.
  32 //
  33 // The mapping below was provided by the first OS user that requested
  34 // GpioInt() support.
  35 // Other OS users that need GpioInt() support must use the following mapping.
  36 //
  37 #define QUARK_GPIO8_MAPPING         0x00
  38 #define QUARK_GPIO9_MAPPING         0x01
  39 #define QUARK_GPIO_SUS0_MAPPING     0x02
  40 #define QUARK_GPIO_SUS1_MAPPING     0x03
  41 #define QUARK_GPIO_SUS2_MAPPING     0x04
  42 #define QUARK_GPIO_SUS3_MAPPING     0x05
  43 #define QUARK_GPIO_SUS4_MAPPING     0x06
  44 #define QUARK_GPIO_SUS5_MAPPING     0x07
  45 #define QUARK_GPIO0_MAPPING         0x08
  46 #define QUARK_GPIO1_MAPPING         0x09
  47 #define QUARK_GPIO2_MAPPING         0x0A
  48 #define QUARK_GPIO3_MAPPING         0x0B
  49 #define QUARK_GPIO4_MAPPING         0x0C
  50 #define QUARK_GPIO5_MAPPING         0x0D
  51 #define QUARK_GPIO6_MAPPING         0x0E
  52 #define QUARK_GPIO7_MAPPING         0x0F
  53
  54 DefinitionBlock (
  55   "Platform.aml",
  56   "DSDT",
  57   1,
  58   "INTEL ",
  59   "QuarkNcSocId",
  60   3)
  61 {
  62     //
  63     // Global Variables
  64     //
  65     Name(\GPIC, 0x0)
  66
  67     //
  68     // Port 80
  69     //
  70     OperationRegion (DBG0, SystemIO, 0x80, 1)
  71     Field (DBG0, ByteAcc, NoLock, Preserve)
  72     { IO80,8 }
  73
  74     //
  75     // Access CMOS range
  76     //
  77     OperationRegion (ACMS, SystemIO, 0x72, 2)
  78     Field (ACMS, ByteAcc, NoLock, Preserve)
  79     { INDX, 8, DATA, 8 }
  80
  81     //
  82     // Global NVS Memory Block
  83     //
  84     OperationRegion (MNVS, SystemMemory, 0xFFFF0000, 512)
  85     Field (MNVS, ByteAcc, NoLock, Preserve)
  86     {
  87       OSTP, 32,
  88       CFGD, 32,
  89       HPEA, 32,  // HPET Enabled ?
  90
  91       P1BB, 32,  // Pm1blkIoBaseAddress;
  92       PBAB, 32,  // PmbaIoBaseAddress;
  93       GP0B, 32,  // Gpe0blkIoBaseAddress;
  94       GPAB, 32,  // GbaIoBaseAddress;
  95
  96       SMBB, 32,  // SmbaIoBaseAddress;
  97       NRV1, 32,  // GNVS reserved field 1.
  98       WDTB, 32,  // WdtbaIoBaseAddress;
  99
 100       HPTB, 32,  // HpetBaseAddress;
 101       HPTS, 32,  // HpetSize;
 102       PEXB, 32,  // PciExpressBaseAddress;
 103       PEXS, 32,  // PciExpressSize;
 104
 105       RCBB, 32,  // RcbaMmioBaseAddress;
 106       RCBS, 32,  // RcbaMmioSize;
 107       APCB, 32,  // IoApicBaseAddress;
 108       APCS, 32,  // IoApicSize;
 109
 110       TPMP, 32,  // TpmPresent ?
 111       DBGP, 32,  // DBG2 Present?
 112       PTYP, 32,  // Set to one of EFI_PLATFORM_TYPE enums.
 113       ALTS, 32,  // Use alternate I2c SLA addresses.
 114     }
 115
 116     OperationRegion (GPEB, SystemIO, 0x1100, 0x40)  //GPE Block
 117     Field (GPEB, AnyAcc, NoLock, Preserve)
 118     {
 119       Offset(0x10),
 120       SMIE, 32,                 // SMI Enable
 121       SMIS, 32,                 // SMI Status
 122     }
 123
 124     //
 125     //  Processor Objects
 126     //
 127     Scope(\_PR) {
 128         //
 129         // IO base will be updated at runtime with search key "PRIO"
 130         //
 131         Processor (CPU0, 0x01, 0x4F495250, 0x06) {}
 132     }
 133
 134     //
 135     // System Sleep States
 136     //
 137     Name (\_S0,Package (){0,0,0,0})
 138     Name (\_S3,Package (){5,0,0,0})
 139     Name (\_S4,Package (){6,0,0,0})
 140     Name (\_S5,Package (){7,0,0,0})
 141
 142     //
 143     //  General Purpose Event
 144     //
 145     Scope(\_GPE)
 146     {
 147         //
 148         // EGPE generated GPE
 149         //
 150         Method(_L0D, 0x0, NotSerialized)
 151         {
 152             //
 153             // Check EGPE for this wake event
 154             //
 155             Notify (\_SB.SLPB, 0x02)
 156
 157         }
 158
 159         //
 160         // GPIO generated GPE
 161         //
 162         Method(_L0E, 0x0, NotSerialized)
 163         {
 164             //
 165             // Check GPIO for this wake event
 166             //
 167             Notify (\_SB.PWRB, 0x02)
 168
 169         }
 170
 171         //
 172         // SCLT generated GPE
 173         //
 174         Method(_L0F, 0x0, NotSerialized)
 175         {
 176             //
 177             // Check SCLT for this wake event
 178             //
 179             Notify (\_SB.PCI0.SDIO, 0x02)
 180             Notify (\_SB.PCI0.URT0, 0x02)
 181             Notify (\_SB.PCI0.USBD, 0x02)
 182             Notify (\_SB.PCI0.EHCI, 0x02)
 183             Notify (\_SB.PCI0.OHCI, 0x02)
 184             Notify (\_SB.PCI0.URT1, 0x02)
 185             Notify (\_SB.PCI0.ENT0, 0x02)
 186             Notify (\_SB.PCI0.ENT1, 0x02)
 187             Notify (\_SB.PCI0.SPI0, 0x02)
 188             Notify (\_SB.PCI0.SPI1, 0x02)
 189             Notify (\_SB.PCI0.GIP0, 0x02)
 190
 191         }
 192
 193         //
 194         // Remote Management Unit generated GPE
 195         //
 196         Method(_L10, 0x0, NotSerialized)
 197         {
 198             //
 199             // Check Remote Management Unit for this wake event.
 200             //
 201         }
 202
 203         //
 204         // PCIE generated GPE
 205         //
 206         Method(_L11, 0x0, NotSerialized)
 207         {
 208             //
 209             // Check PCIE for this wake event
 210             //
 211             Notify (\_SB.PCI0.PEX0, 0x02)
 212             Notify (\_SB.PCI0.PEX1, 0x02)
 213         }
 214     }
 215
 216     //
 217     // define Sleeping button as mentioned in ACPI spec 2.0
 218     //
 219     Device (\_SB.SLPB)
 220     {
 221         Name (_HID, EISAID ("PNP0C0E"))
 222         Method (_PRW, 0, NotSerialized)
 223         {
 224             Return (Package (0x02) {0x0D,0x04})
 225         }
 226     }
 227
 228     //
 229     // define Power Button
 230     //
 231      Device (\_SB.PWRB)
 232     {
 233         Name (_HID, EISAID ("PNP0C0C"))
 234         Method (_PRW, 0, NotSerialized)
 235         {
 236             Return (Package (0x02) {0x0E,0x04})
 237         }
 238     }
 239     //
 240     // System Wake up
 241     //
 242     Method(_WAK, 1, Serialized)
 243     {
 244        // Do nothing here
 245        Return (0)
 246     }
 247
 248     //
 249     // System sleep down
 250     //
 251     Method (_PTS, 1, NotSerialized)
 252     {
 253         // Get ready for S3 sleep
 254         if (Lequal(Arg0,3))
 255         {
 256                 Store(0xffffffff,SMIS)     // clear SMI status
 257                 Store(SMIE, Local0)        // SMI Enable
 258                 Or(Local0,0x4,SMIE)        // Generate SMI on sleep
 259         }
 260     }
 261
 262     //
 263     // Determing PIC mode
 264     //
 265     Method(\_PIC, 1, NotSerialized)
 266     {
 267         Store(Arg0,\GPIC)
 268     }
 269
 270     //
 271     //  System Bus
 272     //
 273     Scope(\_SB)
 274     {
 275         Device(PCI0)
 276         {
 277             Name(_HID,EISAID ("PNP0A08"))          // PCI Express Root Bridge
 278             Name(_CID,EISAID ("PNP0A03"))          // Compatible PCI Root Bridge
 279
 280             Name(_ADR,0x00000000)                  // Device (HI WORD)=0, Func (LO WORD)=0
 281             Method (_INI)
 282             {
 283                 Store(LINUX, OSTP)                 // Set the default os is Linux
 284                 If (CondRefOf (_OSI, local0))
 285                 {
 286                     //
 287                     //_OSI is supported, so it is WinXp or Win2003Server
 288                     //
 289                     If (\_OSI("Windows 2001"))
 290                     {
 291                         Store (WINDOWS_XP, OSTP)
 292                     }
 293                     If (\_OSI("Windows 2001 SP1"))
 294                     {
 295                         Store (WINDOWS_XP_SP1, OSTP)
 296                     }
 297                     If (\_OSI("Windows 2001 SP2"))
 298                     {
 299                         Store (WINDOWS_XP_SP2, OSTP)
 300                     }
 301                     If (\_OSI("Windows 2001.1"))
 302                     {
 303                         Store (WINDOWS_2003, OSTP)
 304                     }
 305                     If (\_OSI("Windows 2006"))
 306                     {
 307                         Store (WINDOWS_Vista, OSTP)
 308                     }
 309                     If (\_OSI("Windows 2009"))
 310                     {
 311                         Store (WINDOWS_WIN7, OSTP)
 312                     }
 313                     If (\_OSI("Windows 2012"))
 314                     {
 315                         Store (WINDOWS_WIN8, OSTP)
 316                     }
 317                     If (\_OSI("Windows 2013"))
 318                     {
 319                         Store (WINDOWS_WIN8_1, OSTP)
 320                     }
 321                     If (\_OSI("Linux"))
 322                     {
 323                       Store (LINUX, OSTP)
 324                     }
 325                 }
 326             }
 327
 328             Include ("PciHostBridge.asi")     // PCI0 Host bridge
 329             Include ("QNC.asi")               // QNC miscellaneous
 330             Include ("PcieExpansionPrt.asi")  // PCIe expansion bridges/devices
 331             Include ("QuarkSouthCluster.asi") // Quark South Cluster devices
 332             Include ("QNCLpc.asi")            // LPC bridge device
 333             Include ("QNCApic.asi")           // QNC I/O Apic device
 334
 335         }
 336
 337         //
 338         // Include asi files for I2C and SPI onboard devices.
 339         // Devices placed here instead of below relevant controllers.
 340         // Hardware topology information is maintained by the
 341         // ResourceSource arg to the I2CSerialBus/SPISerialBus macros
 342         // within the device asi files.
 343         //
 344         Include ("Tpm.asi")          // TPM device.
 345         Include ("CY8C9540A.asi")    // CY8C9540A 40Bit I/O Expander & EEPROM
 346         Include ("PCAL9555A.asi")    // NXP PCAL9555A I/O expander.
 347         Include ("PCA9685.asi")      // NXP PCA9685 PWM/LED controller.
 348         Include ("CAT24C08.asi")     // ONSEMI CAT24C08 I2C 8KB EEPROM.
 349         Include ("AD7298.asi")       // Analog devices AD7298 ADC.
 350         Include ("ADC108S102.asi")   // TI ADC108S102 ADC.
 351         Include ("GpioClient.asi")   // Software device to expose GPIO
 352     }
 353 }