projects / mirror_edk2.git / blame
| Commit | Line | Data |
|---|---|---|
| b303605e MK |
1 | /** @file\r |
| 2 | This code supports a the private implementation\r | |
| 3 | of the Legacy BIOS Platform protocol\r | |
| 4 | \r | |
| 5 | Copyright (c) 2013-2015 Intel Corporation.\r | |
| 6 | \r | |
| 7 | This program and the accompanying materials\r | |
| 8 | are licensed and made available under the terms and conditions of the BSD License\r | |
| 9 | which accompanies this distribution. The full text of the license may be found at\r | |
| 10 | http://opensource.org/licenses/bsd-license.php\r | |
| 11 | \r | |
| 12 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
| 13 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
| 14 | \r | |
| 15 | \r | |
| 16 | **/\r | |
| 17 | \r | |
| 18 | #ifndef PCI_PLATFORM_H_\r | |
| 19 | #define PCI_PLATFORM_H_\r | |
| 20 | \r | |
| 21 | #include <IndustryStandard/Pci.h>\r | |
| 22 | #include <Library/PcdLib.h>\r | |
| 23 | //\r | |
| 24 | // Global variables for Option ROMs\r | |
| 25 | //\r | |
| 26 | #define NULL_ROM_FILE_GUID \\r | |
| 27 | { 0x00000000, 0x0000, 0x0000, {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }}\r | |
| 28 | \r | |
| 29 | #define ONBOARD_VIDEO_OPTION_ROM_FILE_GUID \\r | |
| 30 | { 0x8dfae5d4, 0xb50e, 0x4c10, {0x96, 0xe6, 0xf2, 0xc2, 0x66, 0xca, 0xcb, 0xb6 }}\r | |
| 31 | \r | |
| 32 | #define IDE_RAID_OPTION_ROM_FILE_GUID \\r | |
| 33 | { 0x3392A8E1, 0x1881, 0x4398, {0x83, 0xa6, 0x53, 0xd3, 0x87, 0xdb, 0x20, 0x20 }}\r | |
| 34 | \r | |
| 35 | #define TANX_UNDI_OPTION_ROM_FILE_GUID \\r | |
| 36 | { 0x84c24ab0, 0x124e, 0x4aed, {0x8e, 0xfe, 0xf9, 0x1b, 0xb9, 0x73, 0x69, 0xf4 }}\r | |
| 37 | \r | |
| 38 | #define PXE_UNDI_OPTION_ROM_FILE_GUID \\r | |
| 39 | { 0xea34cd48, 0x5fdf, 0x46f0, {0xb5, 0xfa, 0xeb, 0xe0, 0x76, 0xa4, 0xf1, 0x2c }}\r | |
| 40 | \r | |
| 41 | \r | |
| 42 | typedef struct {\r | |
| 43 | EFI_GUID FileName;\r | |
| 44 | UINTN Segment;\r | |
| 45 | UINTN Bus;\r | |
| 46 | UINTN Device;\r | |
| 47 | UINTN Function;\r | |
| 48 | UINT16 VendorId;\r | |
| 49 | UINT16 DeviceId;\r | |
| 50 | } PCI_OPTION_ROM_TABLE;\r | |
| 51 | \r | |
| 52 | \r | |
| 53 | EFI_STATUS\r | |
| 54 | PhaseNotify (\r | |
| 55 | IN EFI_PCI_PLATFORM_PROTOCOL *This,\r | |
| 56 | IN EFI_HANDLE HostBridge,\r | |
| 57 | IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PHASE Phase,\r | |
| 58 | IN EFI_PCI_CHIPSET_EXECUTION_PHASE ChipsetPhase\r | |
| 59 | );\r | |
| 60 | \r | |
| 61 | \r | |
| 62 | EFI_STATUS\r | |
| 63 | PlatformPrepController (\r | |
| 64 | IN EFI_PCI_PLATFORM_PROTOCOL *This,\r | |
| 65 | IN EFI_HANDLE HostBridge,\r | |
| 66 | IN EFI_HANDLE RootBridge,\r | |
| 67 | IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS PciAddress,\r | |
| 68 | IN EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE Phase,\r | |
| 69 | IN EFI_PCI_CHIPSET_EXECUTION_PHASE ChipsetPhase\r | |
| 70 | );\r | |
| 71 | \r | |
| 72 | EFI_STATUS\r | |
| 73 | GetPlatformPolicy (\r | |
| 74 | IN CONST EFI_PCI_PLATFORM_PROTOCOL *This,\r | |
| 75 | OUT EFI_PCI_PLATFORM_POLICY *PciPolicy\r | |
| 76 | );\r | |
| 77 | \r | |
| 78 | EFI_STATUS\r | |
| 79 | GetPciRom (\r | |
| 80 | IN CONST EFI_PCI_PLATFORM_PROTOCOL *This,\r | |
| 81 | IN EFI_HANDLE PciHandle,\r | |
| 82 | OUT VOID **RomImage,\r | |
| 83 | OUT UINTN *RomSize\r | |
| 84 | );\r | |
| 85 | \r | |
| 86 | #endif\r | |
| 87 | \r | |
| 88 | \r |