[mirror_edk2.git] / QuarkPlatformPkg / Platform / Pei / PlatformInit / MrcWrapper.h

/** @file\r
Framework PEIM to initialize memory on an DDR2 SDRAM Memory Controller.\r
\r
Copyright (c) 2013 - 2016 Intel Corporation.\r
\r
SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
**/\r
\r
#ifndef _MRC_WRAPPER_H\r
#define _MRC_WRAPPER_H\r
\r
#include <Ppi/QNCMemoryInit.h>\r
#include "PlatformEarlyInit.h"\r
\r
//\r
// Define the default memory areas required\r
//\r
#define EDKII_RESERVED_SIZE_PAGES         0x20\r
#define ACPI_NVS_SIZE_PAGES               0x60\r
#define RUNTIME_SERVICES_DATA_SIZE_PAGES  0x20\r
#define RUNTIME_SERVICES_CODE_SIZE_PAGES  0x80\r
#define ACPI_RECLAIM_SIZE_PAGES           0x20\r
#define EDKII_DXE_MEM_SIZE_PAGES          0x20\r
\r
//\r
// Maximum number of "Socket Sets", where a "Socket Set is a set of matching\r
// DIMM's from the various channels\r
//\r
#define MAX_SOCKET_SETS      2\r
\r
//\r
// Maximum number of memory ranges supported by the memory controller\r
//\r
#define MAX_RANGES (MAX_ROWS + 5)\r
\r
//\r
// Min. of 48MB PEI phase\r
//\r
#define  PEI_MIN_MEMORY_SIZE               (6 * 0x800000)\r
#define  PEI_RECOVERY_MIN_MEMORY_SIZE      (6 * 0x800000)\r
\r
#define PEI_MEMORY_RANGE_OPTION_ROM UINT32\r
#define PEI_MR_OPTION_ROM_NONE      0x00000000\r
\r
//\r
// SMRAM Memory Range\r
//\r
#define PEI_MEMORY_RANGE_SMRAM      UINT32\r
#define PEI_MR_SMRAM_ALL            0xFFFFFFFF\r
#define PEI_MR_SMRAM_NONE           0x00000000\r
#define PEI_MR_SMRAM_CACHEABLE_MASK 0x80000000\r
#define PEI_MR_SMRAM_SEGTYPE_MASK   0x00FF0000\r
#define PEI_MR_SMRAM_ABSEG_MASK     0x00010000\r
#define PEI_MR_SMRAM_HSEG_MASK      0x00020000\r
#define PEI_MR_SMRAM_TSEG_MASK      0x00040000\r
//\r
// SMRAM Size is a multiple of 128KB.\r
//\r
#define PEI_MR_SMRAM_SIZE_MASK          0x0000FFFF\r
\r
//\r
// Pci Memory Hole\r
//\r
#define PEI_MEMORY_RANGE_PCI_MEMORY       UINT32\r
\r
typedef enum {\r
  Ignore,\r
  Quick,\r
  Sparse,\r
  Extensive\r
} PEI_MEMORY_TEST_OP;\r
\r
//\r
// MRC Params Variable structure.\r
//\r
\r
typedef struct {\r
  MrcTimings_t timings;              // Actual MRC config values saved in variable store.\r
  UINT8        VariableStorePad[8];  // Allow for data stored in variable is required to be multiple of 8bytes.\r
} PLATFORM_VARIABLE_MEMORY_CONFIG_DATA;\r
\r
///\r
/// MRC Params Platform Data Flags bits\r
///\r
#define PDAT_MRC_FLAG_ECC_EN            BIT0\r
#define PDAT_MRC_FLAG_SCRAMBLE_EN       BIT1\r
#define PDAT_MRC_FLAG_MEMTEST_EN        BIT2\r
#define PDAT_MRC_FLAG_TOP_TREE_EN       BIT3  ///< 0b DDR "fly-by" topology else 1b DDR "tree" topology.\r
#define PDAT_MRC_FLAG_WR_ODT_EN         BIT4  ///< If set ODR signal is asserted to DRAM devices on writes.\r
\r
///\r
/// MRC Params Platform Data.\r
///\r
typedef struct {\r
  UINT32       Flags;                   ///< Bitmap of PDAT_MRC_FLAG_XXX defs above.\r
  UINT8        DramWidth;               ///< 0=x8, 1=x16, others=RESERVED.\r
  UINT8        DramSpeed;               ///< 0=DDRFREQ_800, 1=DDRFREQ_1066, others=RESERVED. Only 533MHz SKU support 1066 memory.\r
  UINT8        DramType;                ///< 0=DDR3,1=DDR3L, others=RESERVED.\r
  UINT8        RankMask;                ///< bit[0] RANK0_EN, bit[1] RANK1_EN, others=RESERVED.\r
  UINT8        ChanMask;                ///< bit[0] CHAN0_EN, others=RESERVED.\r
  UINT8        ChanWidth;               ///< 1=x16, others=RESERVED.\r
  UINT8        AddrMode;                ///< 0, 1, 2 (mode 2 forced if ecc enabled), others=RESERVED.\r
  UINT8        SrInt;                   ///< 1=1.95us, 2=3.9us, 3=7.8us, others=RESERVED. REFRESH_RATE.\r
  UINT8        SrTemp;                  ///< 0=normal, 1=extended, others=RESERVED.\r
  UINT8        DramRonVal;              ///< 0=34ohm, 1=40ohm, others=RESERVED. RON_VALUE Select MRS1.DIC driver impedance control.\r
  UINT8        DramRttNomVal;           ///< 0=40ohm, 1=60ohm, 2=120ohm, others=RESERVED.\r
  UINT8        DramRttWrVal;            ///< 0=off others=RESERVED.\r
  UINT8        SocRdOdtVal;             ///< 0=off, 1=60ohm, 2=120ohm, 3=180ohm, others=RESERVED.\r
  UINT8        SocWrRonVal;             ///< 0=27ohm, 1=32ohm, 2=40ohm, others=RESERVED.\r
  UINT8        SocWrSlewRate;           ///< 0=2.5V/ns, 1=4V/ns, others=RESERVED.\r
  UINT8        DramDensity;             ///< 0=512Mb, 1=1Gb, 2=2Gb, 3=4Gb, others=RESERVED.\r
  UINT32       tRAS;                    ///< ACT to PRE command period in picoseconds.\r
  UINT32       tWTR;                    ///< Delay from start of internal write transaction to internal read command in picoseconds.\r
  UINT32       tRRD;                    ///< ACT to ACT command period (JESD79 specific to page size 1K/2K) in picoseconds.\r
  UINT32       tFAW;                    ///< Four activate window (JESD79 specific to page size 1K/2K) in picoseconds.\r
  UINT8        tCL;                     ///< DRAM CAS Latency in clocks.\r
} PDAT_MRC_ITEM;\r
\r
//\r
// Memory range types\r
//\r
typedef enum {\r
  DualChannelDdrMainMemory,\r
  DualChannelDdrSmramCacheable,\r
  DualChannelDdrSmramNonCacheable,\r
  DualChannelDdrGraphicsMemoryCacheable,\r
  DualChannelDdrGraphicsMemoryNonCacheable,\r
  DualChannelDdrReservedMemory,\r
  DualChannelDdrMaxMemoryRangeType\r
} PEI_DUAL_CHANNEL_DDR_MEMORY_RANGE_TYPE;\r
\r
//\r
// Memory map range information\r
//\r
typedef struct {\r
  EFI_PHYSICAL_ADDRESS                          PhysicalAddress;\r
  EFI_PHYSICAL_ADDRESS                          CpuAddress;\r
  EFI_PHYSICAL_ADDRESS                          RangeLength;\r
  PEI_DUAL_CHANNEL_DDR_MEMORY_RANGE_TYPE        Type;\r
} PEI_DUAL_CHANNEL_DDR_MEMORY_MAP_RANGE;\r
\r
//\r
// Function prototypes.\r
//\r
\r
EFI_STATUS\r
InstallEfiMemory (\r
  IN      EFI_PEI_SERVICES                           **PeiServices,\r
  IN      EFI_PEI_READ_ONLY_VARIABLE2_PPI            *VariableServices,\r
  IN      EFI_BOOT_MODE                              BootMode,\r
  IN      UINT32                                     TotalMemorySize\r
  );\r
\r
EFI_STATUS\r
InstallS3Memory (\r
  IN      EFI_PEI_SERVICES                      **PeiServices,\r
  IN      EFI_PEI_READ_ONLY_VARIABLE2_PPI       *VariableServices,\r
  IN      UINT32                                TotalMemorySize\r
  );\r
\r
EFI_STATUS\r
MemoryInit (\r
  IN EFI_PEI_SERVICES                       **PeiServices\r
  );\r
\r
\r
EFI_STATUS\r
LoadConfig (\r
  IN      EFI_PEI_SERVICES                        **PeiServices,\r
  IN      EFI_PEI_READ_ONLY_VARIABLE2_PPI         *VariableServices,\r
  IN OUT  MRCParams_t                             *MrcData\r
  );\r
\r
EFI_STATUS\r
SaveConfig (\r
  IN      MRCParams_t                      *MrcData\r
  );\r
\r
EFI_STATUS\r
GetMemoryMap (\r
  IN     EFI_PEI_SERVICES                                    **PeiServices,\r
  IN     UINT32                                              TotalMemorySize,\r
  IN OUT PEI_DUAL_CHANNEL_DDR_MEMORY_MAP_RANGE               *MemoryMap,\r
  IN OUT UINT8                                               *NumRanges\r
  );\r
\r
EFI_STATUS\r
ChooseRanges (\r
  IN OUT   PEI_MEMORY_RANGE_OPTION_ROM      *OptionRomMask,\r
  IN OUT   PEI_MEMORY_RANGE_SMRAM           *SmramMask,\r
  IN OUT   PEI_MEMORY_RANGE_PCI_MEMORY      *PciMemoryMask\r
  );\r
\r
EFI_STATUS\r
GetPlatformMemorySize (\r
  IN      EFI_PEI_SERVICES                       **PeiServices,\r
  IN      EFI_BOOT_MODE                          BootMode,\r
  IN OUT  UINT64                                 *MemorySize\r
  );\r
\r
EFI_STATUS\r
BaseMemoryTest (\r
  IN  EFI_PEI_SERVICES                   **PeiServices,\r
  IN  EFI_PHYSICAL_ADDRESS               BeginAddress,\r
  IN  UINT64                             MemoryLength,\r
  IN  PEI_MEMORY_TEST_OP                 Operation,\r
  OUT EFI_PHYSICAL_ADDRESS               *ErrorAddress\r
  );\r
\r
EFI_STATUS\r
SetPlatformImrPolicy (\r
  IN      EFI_PHYSICAL_ADDRESS    PeiMemoryBaseAddress,\r
  IN      UINT64                  PeiMemoryLength\r
  );\r
\r
VOID\r
EFIAPI\r
InfoPostInstallMemory (\r
  OUT     UINT32                  *RmuBaseAddressPtr OPTIONAL,\r
  OUT     EFI_SMRAM_DESCRIPTOR    **SmramDescriptorPtr OPTIONAL,\r
  OUT     UINTN                   *NumSmramRegionsPtr OPTIONAL\r
  );\r
\r
#endif\r
Commit	Line	Data
b303605e MK	1	/** @file\r
	2	Framework PEIM to initialize memory on an DDR2 SDRAM Memory Controller.\r
	3	\r
8b43c84e	4	Copyright (c) 2013 - 2016 Intel Corporation.\r
b303605e	5	\r
0eb3de2e	6	SPDX-License-Identifier: BSD-2-Clause-Patent\r
b303605e MK	7	\r
	8	**/\r
	9	\r
	10	#ifndef _MRC_WRAPPER_H\r
	11	#define _MRC_WRAPPER_H\r
	12	\r
	13	#include <Ppi/QNCMemoryInit.h>\r
	14	#include "PlatformEarlyInit.h"\r
	15	\r
	16	//\r
	17	// Define the default memory areas required\r
	18	//\r
8b43c84e MK	19	#define EDKII_RESERVED_SIZE_PAGES 0x20\r
8b43c84e MK	20	#define ACPI_NVS_SIZE_PAGES 0x60\r
b303605e	21	#define RUNTIME_SERVICES_DATA_SIZE_PAGES 0x20\r
8b43c84e MK	22	#define RUNTIME_SERVICES_CODE_SIZE_PAGES 0x80\r
8b43c84e MK	23	#define ACPI_RECLAIM_SIZE_PAGES 0x20\r
b303605e MK	24	#define EDKII_DXE_MEM_SIZE_PAGES 0x20\r
b303605e MK	25	\r
b303605e MK	26	//\r
	27	// Maximum number of "Socket Sets", where a "Socket Set is a set of matching\r
	28	// DIMM's from the various channels\r
	29	//\r
	30	#define MAX_SOCKET_SETS 2\r
	31	\r
	32	//\r
	33	// Maximum number of memory ranges supported by the memory controller\r
	34	//\r
	35	#define MAX_RANGES (MAX_ROWS + 5)\r
	36	\r
	37	//\r
	38	// Min. of 48MB PEI phase\r
	39	//\r
	40	#define PEI_MIN_MEMORY_SIZE (6 * 0x800000)\r
	41	#define PEI_RECOVERY_MIN_MEMORY_SIZE (6 * 0x800000)\r
	42	\r
	43	#define PEI_MEMORY_RANGE_OPTION_ROM UINT32\r
	44	#define PEI_MR_OPTION_ROM_NONE 0x00000000\r
	45	\r
	46	//\r
	47	// SMRAM Memory Range\r
	48	//\r
	49	#define PEI_MEMORY_RANGE_SMRAM UINT32\r
	50	#define PEI_MR_SMRAM_ALL 0xFFFFFFFF\r
	51	#define PEI_MR_SMRAM_NONE 0x00000000\r
	52	#define PEI_MR_SMRAM_CACHEABLE_MASK 0x80000000\r
	53	#define PEI_MR_SMRAM_SEGTYPE_MASK 0x00FF0000\r
	54	#define PEI_MR_SMRAM_ABSEG_MASK 0x00010000\r
	55	#define PEI_MR_SMRAM_HSEG_MASK 0x00020000\r
	56	#define PEI_MR_SMRAM_TSEG_MASK 0x00040000\r
	57	//\r
	58	// SMRAM Size is a multiple of 128KB.\r
	59	//\r
	60	#define PEI_MR_SMRAM_SIZE_MASK 0x0000FFFF\r
	61	\r
	62	//\r
	63	// Pci Memory Hole\r
	64	//\r
	65	#define PEI_MEMORY_RANGE_PCI_MEMORY UINT32\r
	66	\r
	67	typedef enum {\r
	68	Ignore,\r
	69	Quick,\r
	70	Sparse,\r
	71	Extensive\r
	72	} PEI_MEMORY_TEST_OP;\r
	73	\r
	74	//\r
	75	// MRC Params Variable structure.\r
	76	//\r
	77	\r
	78	typedef struct {\r
	79	MrcTimings_t timings; // Actual MRC config values saved in variable store.\r
	80	UINT8 VariableStorePad[8]; // Allow for data stored in variable is required to be multiple of 8bytes.\r
	81	} PLATFORM_VARIABLE_MEMORY_CONFIG_DATA;\r
	82	\r
	83	///\r
	84	/// MRC Params Platform Data Flags bits\r
	85	///\r
	86	#define PDAT_MRC_FLAG_ECC_EN BIT0\r
	87	#define PDAT_MRC_FLAG_SCRAMBLE_EN BIT1\r
	88	#define PDAT_MRC_FLAG_MEMTEST_EN BIT2\r
	89	#define PDAT_MRC_FLAG_TOP_TREE_EN BIT3 ///< 0b DDR "fly-by" topology else 1b DDR "tree" topology.\r
90	#define PDAT_MRC_FLAG_WR_ODT_EN BIT4 ///< If set ODR signal is asserted to DRAM devices on writes.\r
91	\r
92	///\r
93	/// MRC Params Platform Data.\r
94	///\r
95	typedef struct {\r
96	UINT32 Flags; ///< Bitmap of PDAT_MRC_FLAG_XXX defs above.\r
97	UINT8 DramWidth; ///< 0=x8, 1=x16, others=RESERVED.\r
98	UINT8 DramSpeed; ///< 0=DDRFREQ_800, 1=DDRFREQ_1066, others=RESERVED. Only 533MHz SKU support 1066 memory.\r
99	UINT8 DramType; ///< 0=DDR3,1=DDR3L, others=RESERVED.\r
100	UINT8 RankMask; ///< bit[0] RANK0_EN, bit[1] RANK1_EN, others=RESERVED.\r
101	UINT8 ChanMask; ///< bit[0] CHAN0_EN, others=RESERVED.\r
102	UINT8 ChanWidth; ///< 1=x16, others=RESERVED.\r
103	UINT8 AddrMode; ///< 0, 1, 2 (mode 2 forced if ecc enabled), others=RESERVED.\r
104	UINT8 SrInt; ///< 1=1.95us, 2=3.9us, 3=7.8us, others=RESERVED. REFRESH_RATE.\r
105	UINT8 SrTemp; ///< 0=normal, 1=extended, others=RESERVED.\r
106	UINT8 DramRonVal; ///< 0=34ohm, 1=40ohm, others=RESERVED. RON_VALUE Select MRS1.DIC driver impedance control.\r
107	UINT8 DramRttNomVal; ///< 0=40ohm, 1=60ohm, 2=120ohm, others=RESERVED.\r
108	UINT8 DramRttWrVal; ///< 0=off others=RESERVED.\r
109	UINT8 SocRdOdtVal; ///< 0=off, 1=60ohm, 2=120ohm, 3=180ohm, others=RESERVED.\r
110	UINT8 SocWrRonVal; ///< 0=27ohm, 1=32ohm, 2=40ohm, others=RESERVED.\r
111	UINT8 SocWrSlewRate; ///< 0=2.5V/ns, 1=4V/ns, others=RESERVED.\r
112	UINT8 DramDensity; ///< 0=512Mb, 1=1Gb, 2=2Gb, 3=4Gb, others=RESERVED.\r
113	UINT32 tRAS; ///< ACT to PRE command period in picoseconds.\r
114	UINT32 tWTR; ///< Delay from start of internal write transaction to internal read command in picoseconds.\r
115	UINT32 tRRD; ///< ACT to ACT command period (JESD79 specific to page size 1K/2K) in picoseconds.\r
116	UINT32 tFAW; ///< Four activate window (JESD79 specific to page size 1K/2K) in picoseconds.\r
117	UINT8 tCL; ///< DRAM CAS Latency in clocks.\r
118	} PDAT_MRC_ITEM;\r
119	\r
120	//\r
121	// Memory range types\r
122	//\r
123	typedef enum {\r
124	DualChannelDdrMainMemory,\r
125	DualChannelDdrSmramCacheable,\r
126	DualChannelDdrSmramNonCacheable,\r
127	DualChannelDdrGraphicsMemoryCacheable,\r
128	DualChannelDdrGraphicsMemoryNonCacheable,\r
129	DualChannelDdrReservedMemory,\r
130	DualChannelDdrMaxMemoryRangeType\r
131	} PEI_DUAL_CHANNEL_DDR_MEMORY_RANGE_TYPE;\r
132	\r
133	//\r
134	// Memory map range information\r
135	//\r
136	typedef struct {\r
137	EFI_PHYSICAL_ADDRESS PhysicalAddress;\r
138	EFI_PHYSICAL_ADDRESS CpuAddress;\r
139	EFI_PHYSICAL_ADDRESS RangeLength;\r
140	PEI_DUAL_CHANNEL_DDR_MEMORY_RANGE_TYPE Type;\r
141	} PEI_DUAL_CHANNEL_DDR_MEMORY_MAP_RANGE;\r
142	\r
143	//\r
144	// Function prototypes.\r
145	//\r
146	\r
147	EFI_STATUS\r
148	InstallEfiMemory (\r
149	IN EFI_PEI_SERVICES **PeiServices,\r
150	IN EFI_PEI_READ_ONLY_VARIABLE2_PPI *VariableServices,\r
151	IN EFI_BOOT_MODE BootMode,\r
152	IN UINT32 TotalMemorySize\r
153	);\r
154	\r
155	EFI_STATUS\r
156	InstallS3Memory (\r
157	IN EFI_PEI_SERVICES **PeiServices,\r
158	IN EFI_PEI_READ_ONLY_VARIABLE2_PPI *VariableServices,\r
159	IN UINT32 TotalMemorySize\r
160	);\r
161	\r
162	EFI_STATUS\r
163	MemoryInit (\r
164	IN EFI_PEI_SERVICES **PeiServices\r
165	);\r
166	\r
167	\r
168	EFI_STATUS\r
169	LoadConfig (\r
170	IN EFI_PEI_SERVICES **PeiServices,\r
171	IN EFI_PEI_READ_ONLY_VARIABLE2_PPI *VariableServices,\r
172	IN OUT MRCParams_t *MrcData\r
173	);\r
174	\r
175	EFI_STATUS\r
176	SaveConfig (\r
177	IN MRCParams_t *MrcData\r
178	);\r
179	\r
b303605e MK	180	EFI_STATUS\r
	181	GetMemoryMap (\r
	182	IN EFI_PEI_SERVICES **PeiServices,\r
	183	IN UINT32 TotalMemorySize,\r
	184	IN OUT PEI_DUAL_CHANNEL_DDR_MEMORY_MAP_RANGE *MemoryMap,\r
	185	IN OUT UINT8 *NumRanges\r
	186	);\r
	187	\r
	188	EFI_STATUS\r
	189	ChooseRanges (\r
	190	IN OUT PEI_MEMORY_RANGE_OPTION_ROM *OptionRomMask,\r
	191	IN OUT PEI_MEMORY_RANGE_SMRAM *SmramMask,\r
	192	IN OUT PEI_MEMORY_RANGE_PCI_MEMORY *PciMemoryMask\r
	193	);\r
	194	\r
	195	EFI_STATUS\r
	196	GetPlatformMemorySize (\r
	197	IN EFI_PEI_SERVICES **PeiServices,\r
	198	IN EFI_BOOT_MODE BootMode,\r
	199	IN OUT UINT64 *MemorySize\r
	200	);\r
	201	\r
	202	EFI_STATUS\r
	203	BaseMemoryTest (\r
	204	IN EFI_PEI_SERVICES **PeiServices,\r
	205	IN EFI_PHYSICAL_ADDRESS BeginAddress,\r
	206	IN UINT64 MemoryLength,\r
	207	IN PEI_MEMORY_TEST_OP Operation,\r
	208	OUT EFI_PHYSICAL_ADDRESS *ErrorAddress\r
	209	);\r
	210	\r
	211	EFI_STATUS\r
	212	SetPlatformImrPolicy (\r
	213	IN EFI_PHYSICAL_ADDRESS PeiMemoryBaseAddress,\r
69a0854b	214	IN UINT64 PeiMemoryLength\r
b303605e MK	215	);\r
	216	\r
	217	VOID\r
	218	EFIAPI\r
	219	InfoPostInstallMemory (\r
	220	OUT UINT32 *RmuBaseAddressPtr OPTIONAL,\r
	221	OUT EFI_SMRAM_DESCRIPTOR **SmramDescriptorPtr OPTIONAL,\r
	222	OUT UINTN *NumSmramRegionsPtr OPTIONAL\r
	223	);\r
	224	\r
	225	#endif\r