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1 | /** @file\r |
2 | Initializes Platform Specific Drivers.\r | |
3 | \r | |
4 | Copyright (c) 2013-2015 Intel Corporation.\r | |
5 | \r | |
6 | This program and the accompanying materials\r | |
7 | are licensed and made available under the terms and conditions of the BSD License\r | |
8 | which accompanies this distribution. The full text of the license may be found at\r | |
9 | http://opensource.org/licenses/bsd-license.php\r | |
10 | \r | |
11 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
12 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
13 | \r | |
14 | \r | |
15 | **/\r | |
16 | \r | |
17 | #include "SpiFlashDevice.h"\r | |
18 | \r | |
19 | #define FLASH_SIZE (FixedPcdGet32 (PcdFlashAreaSize))\r | |
20 | \r | |
21 | SPI_INIT_TABLE mSpiInitTable[] = {\r | |
22 | //\r | |
23 | // Macronix 32Mbit part\r | |
24 | //\r | |
25 | {\r | |
26 | SPI_MX25L3205_ID1,\r | |
27 | SPI_MX25L3205_ID2,\r | |
28 | SPI_MX25L3205_ID3,\r | |
29 | {\r | |
30 | SPI_COMMAND_WRITE_ENABLE,\r | |
31 | SPI_COMMAND_WRITE_S_EN\r | |
32 | },\r | |
33 | {\r | |
34 | {EnumSpiOpcodeReadNoAddr, SPI_COMMAND_JEDEC_ID, EnumSpiCycle33MHz, EnumSpiOperationJedecId},\r | |
35 | {EnumSpiOpcodeRead, SPI_COMMAND_READ_ID, EnumSpiCycle33MHz, EnumSpiOperationOther},\r | |
36 | {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S, EnumSpiCycle33MHz, EnumSpiOperationWriteStatus},\r | |
37 | {EnumSpiOpcodeWrite, SPI_COMMAND_WRITE, EnumSpiCycle33MHz, EnumSpiOperationProgramData_1_Byte},\r | |
38 | {EnumSpiOpcodeRead, SPI_COMMAND_READ, EnumSpiCycle20MHz, EnumSpiOperationReadData},\r | |
39 | {EnumSpiOpcodeWrite, SPI_COMMAND_BLOCK_ERASE, EnumSpiCycle33MHz, EnumSpiOperationErase_64K_Byte},\r | |
40 | {EnumSpiOpcodeReadNoAddr, SPI_COMMAND_READ_S, EnumSpiCycle33MHz, EnumSpiOperationReadStatus},\r | |
41 | {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE, EnumSpiCycle33MHz, EnumSpiOperationFullChipErase}\r | |
42 | },\r | |
43 | 0x400000 - FLASH_SIZE, // BIOS Start Offset\r | |
44 | FLASH_SIZE // BIOS image size in flash\r | |
45 | },\r | |
46 | //\r | |
47 | // Winbond 32Mbit part\r | |
48 | //\r | |
49 | {\r | |
50 | SPI_W25X32_ID1,\r | |
51 | SF_DEVICE_ID0_W25QXX,\r | |
52 | SF_DEVICE_ID1_W25Q32,\r | |
53 | {\r | |
54 | SPI_COMMAND_WRITE_ENABLE,\r | |
55 | SPI_COMMAND_WRITE_S_EN\r | |
56 | },\r | |
57 | {\r | |
58 | {EnumSpiOpcodeReadNoAddr, SPI_COMMAND_JEDEC_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId},\r | |
59 | {EnumSpiOpcodeRead, SPI_COMMAND_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationOther},\r | |
60 | {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus},\r | |
61 | {EnumSpiOpcodeWrite, SPI_COMMAND_WRITE, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},\r | |
62 | {EnumSpiOpcodeRead, SPI_COMMAND_READ, EnumSpiCycle50MHz, EnumSpiOperationReadData},\r | |
63 | {EnumSpiOpcodeWrite, SPI_COMMAND_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte},\r | |
64 | {EnumSpiOpcodeReadNoAddr, SPI_COMMAND_READ_S, EnumSpiCycle50MHz, EnumSpiOperationReadStatus},\r | |
65 | {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE, EnumSpiCycle50MHz, EnumSpiOperationFullChipErase}\r | |
66 | },\r | |
67 | 0x400000 - FLASH_SIZE, // BIOS Start Offset\r | |
68 | FLASH_SIZE // BIOS image size in flash\r | |
69 | },\r | |
70 | //\r | |
71 | // Winbond 32Mbit part\r | |
72 | //\r | |
73 | {\r | |
74 | SPI_W25X32_ID1,\r | |
75 | SPI_W25X32_ID2,\r | |
76 | SPI_W25X32_ID3,\r | |
77 | {\r | |
78 | SPI_COMMAND_WRITE_ENABLE,\r | |
79 | SPI_COMMAND_WRITE_S_EN\r | |
80 | },\r | |
81 | {\r | |
82 | {EnumSpiOpcodeReadNoAddr, SPI_COMMAND_JEDEC_ID, EnumSpiCycle33MHz, EnumSpiOperationJedecId},\r | |
83 | {EnumSpiOpcodeRead, SPI_COMMAND_READ_ID, EnumSpiCycle33MHz, EnumSpiOperationOther},\r | |
84 | {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S, EnumSpiCycle33MHz, EnumSpiOperationWriteStatus},\r | |
85 | {EnumSpiOpcodeWrite, SPI_COMMAND_WRITE, EnumSpiCycle33MHz, EnumSpiOperationProgramData_1_Byte},\r | |
86 | {EnumSpiOpcodeRead, SPI_COMMAND_READ, EnumSpiCycle33MHz, EnumSpiOperationReadData},\r | |
87 | {EnumSpiOpcodeWrite, SPI_COMMAND_ERASE, EnumSpiCycle33MHz, EnumSpiOperationErase_4K_Byte},\r | |
88 | {EnumSpiOpcodeReadNoAddr, SPI_COMMAND_READ_S, EnumSpiCycle33MHz, EnumSpiOperationReadStatus},\r | |
89 | {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE, EnumSpiCycle33MHz, EnumSpiOperationFullChipErase}\r | |
90 | },\r | |
91 | 0x400000 - FLASH_SIZE, // BIOS Start Offset\r | |
92 | FLASH_SIZE // BIOS image size in flash\r | |
93 | },\r | |
94 | //\r | |
95 | // Atmel 32Mbit part\r | |
96 | //\r | |
97 | {\r | |
98 | SPI_AT26DF321_ID1,\r | |
99 | SPI_AT26DF321_ID2, // issue: byte 2 identifies family/density for Atmel\r | |
100 | SPI_AT26DF321_ID3,\r | |
101 | {\r | |
102 | SPI_COMMAND_WRITE_ENABLE,\r | |
103 | SPI_COMMAND_WRITE_S_EN\r | |
104 | },\r | |
105 | {\r | |
106 | {EnumSpiOpcodeReadNoAddr, SPI_COMMAND_JEDEC_ID, EnumSpiCycle33MHz, EnumSpiOperationJedecId},\r | |
107 | {EnumSpiOpcodeRead, SPI_COMMAND_READ_ID, EnumSpiCycle33MHz, EnumSpiOperationOther},\r | |
108 | {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S, EnumSpiCycle33MHz, EnumSpiOperationWriteStatus},\r | |
109 | {EnumSpiOpcodeWrite, SPI_COMMAND_WRITE, EnumSpiCycle33MHz, EnumSpiOperationProgramData_1_Byte},\r | |
110 | {EnumSpiOpcodeRead, SPI_COMMAND_READ, EnumSpiCycle33MHz, EnumSpiOperationReadData},\r | |
111 | {EnumSpiOpcodeWrite, SPI_COMMAND_BLOCK_ERASE, EnumSpiCycle33MHz, EnumSpiOperationErase_64K_Byte},\r | |
112 | {EnumSpiOpcodeReadNoAddr, SPI_COMMAND_READ_S, EnumSpiCycle33MHz, EnumSpiOperationReadStatus},\r | |
113 | {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE, EnumSpiCycle33MHz, EnumSpiOperationFullChipErase}\r | |
114 | },\r | |
115 | 0x400000 - FLASH_SIZE, // BIOS Start Offset\r | |
116 | FLASH_SIZE // BIOS image size in flash\r | |
117 | },\r | |
118 | \r | |
119 | //\r | |
120 | // Intel 32Mbit part bottom boot\r | |
121 | //\r | |
122 | {\r | |
123 | SPI_QH25F320_ID1,\r | |
124 | SPI_QH25F320_ID2,\r | |
125 | SPI_QH25F320_ID3,\r | |
126 | {\r | |
127 | SPI_COMMAND_WRITE_ENABLE,\r | |
128 | SPI_COMMAND_WRITE_ENABLE\r | |
129 | },\r | |
130 | {\r | |
131 | {EnumSpiOpcodeReadNoAddr, SPI_COMMAND_JEDEC_ID, EnumSpiCycle33MHz, EnumSpiOperationJedecId},\r | |
132 | {EnumSpiOpcodeRead, SPI_COMMAND_READ_ID, EnumSpiCycle33MHz, EnumSpiOperationOther},\r | |
133 | {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S, EnumSpiCycle33MHz, EnumSpiOperationWriteStatus},\r | |
134 | {EnumSpiOpcodeWrite, SPI_COMMAND_WRITE, EnumSpiCycle33MHz, EnumSpiOperationProgramData_1_Byte},\r | |
135 | {EnumSpiOpcodeRead, SPI_COMMAND_READ, EnumSpiCycle33MHz, EnumSpiOperationReadData},\r | |
136 | {EnumSpiOpcodeWrite, SPI_COMMAND_BLOCK_ERASE, EnumSpiCycle33MHz, EnumSpiOperationErase_64K_Byte},\r | |
137 | {EnumSpiOpcodeReadNoAddr, SPI_COMMAND_READ_S, EnumSpiCycle33MHz, EnumSpiOperationReadStatus},\r | |
138 | {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE, EnumSpiCycle33MHz, EnumSpiOperationFullChipErase}\r | |
139 | },\r | |
140 | 0, // BIOS Start Offset\r | |
141 | FLASH_SIZE // BIOS image size in flash\r | |
142 | },\r | |
143 | //\r | |
144 | // SST 64Mbit part\r | |
145 | //\r | |
146 | {\r | |
147 | SPI_SST25VF080B_ID1, // VendorId\r | |
148 | SF_DEVICE_ID0_25VF064C, // DeviceId 0\r | |
149 | SF_DEVICE_ID1_25VF064C, // DeviceId 1\r | |
150 | {\r | |
151 | SPI_COMMAND_WRITE_ENABLE,\r | |
152 | SPI_COMMAND_WRITE_S_EN\r | |
153 | },\r | |
154 | {\r | |
155 | {EnumSpiOpcodeReadNoAddr, SPI_COMMAND_JEDEC_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId},\r | |
156 | {EnumSpiOpcodeRead, SPI_COMMAND_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationOther},\r | |
157 | {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus},\r | |
158 | {EnumSpiOpcodeWrite, SPI_COMMAND_WRITE, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},\r | |
159 | {EnumSpiOpcodeRead, SPI_COMMAND_READ, EnumSpiCycle50MHz, EnumSpiOperationReadData},\r | |
160 | {EnumSpiOpcodeWrite, SPI_COMMAND_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte},\r | |
161 | {EnumSpiOpcodeReadNoAddr, SPI_COMMAND_READ_S, EnumSpiCycle50MHz, EnumSpiOperationReadStatus},\r | |
162 | {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE, EnumSpiCycle50MHz, EnumSpiOperationFullChipErase}\r | |
163 | },\r | |
164 | 0x800000 - FLASH_SIZE, // BIOS Start Offset\r | |
165 | FLASH_SIZE // BIOS image size in flash\r | |
166 | },\r | |
167 | //\r | |
168 | // NUMONYX 64Mbit part\r | |
169 | //\r | |
170 | {\r | |
171 | SF_VENDOR_ID_NUMONYX, // VendorId\r | |
172 | SF_DEVICE_ID0_M25PX64, // DeviceId 0\r | |
173 | SF_DEVICE_ID1_M25PX64, // DeviceId 1\r | |
174 | {\r | |
175 | SPI_COMMAND_WRITE_ENABLE,\r | |
176 | SPI_COMMAND_WRITE_S_EN\r | |
177 | },\r | |
178 | {\r | |
179 | {EnumSpiOpcodeReadNoAddr, SPI_COMMAND_JEDEC_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId},\r | |
180 | {EnumSpiOpcodeRead, SPI_COMMAND_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationOther},\r | |
181 | {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus},\r | |
182 | {EnumSpiOpcodeWrite, SPI_COMMAND_WRITE, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},\r | |
183 | {EnumSpiOpcodeRead, SPI_COMMAND_READ, EnumSpiCycle50MHz, EnumSpiOperationReadData},\r | |
184 | {EnumSpiOpcodeWrite, SPI_COMMAND_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte},\r | |
185 | {EnumSpiOpcodeReadNoAddr, SPI_COMMAND_READ_S, EnumSpiCycle50MHz, EnumSpiOperationReadStatus},\r | |
186 | {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE, EnumSpiCycle50MHz, EnumSpiOperationFullChipErase}\r | |
187 | },\r | |
188 | 0x800000 - FLASH_SIZE, // BIOS Start Offset\r | |
189 | FLASH_SIZE // BIOS image size in flash\r | |
190 | },\r | |
191 | //\r | |
192 | // Atmel 64Mbit part\r | |
193 | //\r | |
194 | {\r | |
195 | SF_VENDOR_ID_ATMEL, // VendorId\r | |
196 | SF_DEVICE_ID0_AT25DF641, // DeviceId 0\r | |
197 | SF_DEVICE_ID1_AT25DF641, // DeviceId 1\r | |
198 | {\r | |
199 | SPI_COMMAND_WRITE_ENABLE,\r | |
200 | SPI_COMMAND_WRITE_S_EN\r | |
201 | },\r | |
202 | {\r | |
203 | {EnumSpiOpcodeReadNoAddr, SPI_COMMAND_JEDEC_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId},\r | |
204 | {EnumSpiOpcodeRead, SPI_COMMAND_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationOther},\r | |
205 | {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus},\r | |
206 | {EnumSpiOpcodeWrite, SPI_COMMAND_WRITE, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},\r | |
207 | {EnumSpiOpcodeRead, SPI_COMMAND_READ, EnumSpiCycle50MHz, EnumSpiOperationReadData},\r | |
208 | {EnumSpiOpcodeWrite, SPI_COMMAND_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte},\r | |
209 | {EnumSpiOpcodeReadNoAddr, SPI_COMMAND_READ_S, EnumSpiCycle50MHz, EnumSpiOperationReadStatus},\r | |
210 | {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE, EnumSpiCycle50MHz, EnumSpiOperationFullChipErase}\r | |
211 | },\r | |
212 | 0x800000 - FLASH_SIZE, // BIOS Start Offset\r | |
213 | FLASH_SIZE // BIOS image size in flash\r | |
214 | },\r | |
215 | \r | |
216 | //\r | |
217 | // Spansion 64Mbit part\r | |
218 | //\r | |
219 | {\r | |
220 | SF_VENDOR_ID_SPANSION, // VendorId\r | |
221 | SF_DEVICE_ID0_S25FL064K, // DeviceId 0\r | |
222 | SF_DEVICE_ID1_S25FL064K, // DeviceId 1\r | |
223 | {\r | |
224 | SPI_COMMAND_WRITE_ENABLE,\r | |
225 | SPI_COMMAND_WRITE_S_EN\r | |
226 | },\r | |
227 | {\r | |
228 | {EnumSpiOpcodeReadNoAddr, SPI_COMMAND_JEDEC_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId},\r | |
229 | {EnumSpiOpcodeRead, SPI_COMMAND_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationOther},\r | |
230 | {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus},\r | |
231 | {EnumSpiOpcodeWrite, SPI_COMMAND_WRITE, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},\r | |
232 | {EnumSpiOpcodeRead, SPI_COMMAND_READ, EnumSpiCycle50MHz, EnumSpiOperationReadData},\r | |
233 | {EnumSpiOpcodeWrite, SPI_COMMAND_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte},\r | |
234 | {EnumSpiOpcodeReadNoAddr, SPI_COMMAND_READ_S, EnumSpiCycle50MHz, EnumSpiOperationReadStatus},\r | |
235 | {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE, EnumSpiCycle50MHz, EnumSpiOperationFullChipErase}\r | |
236 | },\r | |
237 | 0x800000 - FLASH_SIZE, // BIOS Start Offset\r | |
238 | FLASH_SIZE // BIOS image size in flash\r | |
239 | },\r | |
240 | \r | |
241 | //\r | |
242 | // Macronix 64Mbit part bottom boot\r | |
243 | //\r | |
244 | {\r | |
245 | SF_VENDOR_ID_MX, // VendorId\r | |
246 | SF_DEVICE_ID0_25L6405D, // DeviceId 0\r | |
247 | SF_DEVICE_ID1_25L6405D, // DeviceId 1\r | |
248 | {\r | |
249 | SPI_COMMAND_WRITE_ENABLE,\r | |
250 | SPI_COMMAND_WRITE_S_EN\r | |
251 | },\r | |
252 | {\r | |
253 | {EnumSpiOpcodeReadNoAddr, SPI_COMMAND_JEDEC_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId},\r | |
254 | {EnumSpiOpcodeRead, SPI_COMMAND_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationOther},\r | |
255 | {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus},\r | |
256 | {EnumSpiOpcodeWrite, SPI_COMMAND_WRITE, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},\r | |
257 | {EnumSpiOpcodeRead, SPI_COMMAND_READ, EnumSpiCycle50MHz, EnumSpiOperationReadData},\r | |
258 | {EnumSpiOpcodeWrite, SPI_COMMAND_BLOCK_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte},\r | |
259 | {EnumSpiOpcodeReadNoAddr, SPI_COMMAND_READ_S, EnumSpiCycle50MHz, EnumSpiOperationReadStatus},\r | |
260 | {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE, EnumSpiCycle50MHz, EnumSpiOperationFullChipErase}\r | |
261 | },\r | |
262 | 0x800000 - FLASH_SIZE, // BIOS Start Offset\r | |
263 | FLASH_SIZE // BIOS image size in flash\r | |
264 | },\r | |
265 | //\r | |
266 | // Winbond 64Mbit part bottom boot\r | |
267 | //\r | |
268 | {\r | |
269 | SPI_W25X64_ID1,\r | |
270 | SF_DEVICE_ID0_W25QXX,\r | |
271 | SF_DEVICE_ID1_W25Q64,\r | |
272 | {\r | |
273 | SPI_COMMAND_WRITE_ENABLE,\r | |
274 | SPI_COMMAND_WRITE_S_EN\r | |
275 | },\r | |
276 | {\r | |
277 | {EnumSpiOpcodeReadNoAddr, SPI_COMMAND_JEDEC_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId},\r | |
278 | {EnumSpiOpcodeRead, SPI_COMMAND_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationOther},\r | |
279 | {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus},\r | |
280 | {EnumSpiOpcodeWrite, SPI_COMMAND_WRITE, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},\r | |
281 | {EnumSpiOpcodeRead, SPI_COMMAND_READ, EnumSpiCycle50MHz, EnumSpiOperationReadData},\r | |
282 | {EnumSpiOpcodeWrite, SPI_COMMAND_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte},\r | |
283 | {EnumSpiOpcodeReadNoAddr, SPI_COMMAND_READ_S, EnumSpiCycle50MHz, EnumSpiOperationReadStatus},\r | |
284 | {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE, EnumSpiCycle50MHz, EnumSpiOperationFullChipErase}\r | |
285 | },\r | |
286 | 0x800000 - FLASH_SIZE, // BIOS Start Offset\r | |
287 | FLASH_SIZE // BIOS image size in flash\r | |
288 | },\r | |
289 | //\r | |
290 | // Winbond 64Mbit part bottom boot\r | |
291 | //\r | |
292 | {\r | |
293 | SPI_W25X64_ID1,\r | |
294 | SPI_W25X64_ID2,\r | |
295 | SPI_W25X64_ID3,\r | |
296 | {\r | |
297 | SPI_COMMAND_WRITE_ENABLE,\r | |
298 | SPI_COMMAND_WRITE_S_EN\r | |
299 | },\r | |
300 | {\r | |
301 | {EnumSpiOpcodeReadNoAddr, SPI_COMMAND_JEDEC_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId},\r | |
302 | {EnumSpiOpcodeRead, SPI_COMMAND_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationOther},\r | |
303 | {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus},\r | |
304 | {EnumSpiOpcodeWrite, SPI_COMMAND_WRITE, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},\r | |
305 | {EnumSpiOpcodeRead, SPI_COMMAND_READ, EnumSpiCycle50MHz, EnumSpiOperationReadData},\r | |
306 | {EnumSpiOpcodeWrite, SPI_COMMAND_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte},\r | |
307 | {EnumSpiOpcodeReadNoAddr, SPI_COMMAND_READ_S, EnumSpiCycle50MHz, EnumSpiOperationReadStatus},\r | |
308 | {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE, EnumSpiCycle50MHz, EnumSpiOperationFullChipErase}\r | |
309 | },\r | |
310 | 0x800000 - FLASH_SIZE, // BIOS Start Offset\r | |
311 | FLASH_SIZE // BIOS image size in flash\r | |
312 | },\r | |
313 | //\r | |
314 | // Intel 64Mbit part bottom boot\r | |
315 | //\r | |
316 | {\r | |
317 | SPI_QH25F640_ID1,\r | |
318 | SPI_QH25F640_ID2,\r | |
319 | SPI_QH25F640_ID3,\r | |
320 | {\r | |
321 | SPI_COMMAND_WRITE_ENABLE,\r | |
322 | SPI_COMMAND_WRITE_S_EN\r | |
323 | },\r | |
324 | {\r | |
325 | {EnumSpiOpcodeReadNoAddr, SPI_COMMAND_JEDEC_ID, EnumSpiCycle33MHz, EnumSpiOperationJedecId},\r | |
326 | {EnumSpiOpcodeRead, SPI_COMMAND_READ_ID, EnumSpiCycle33MHz, EnumSpiOperationOther},\r | |
327 | {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S, EnumSpiCycle33MHz, EnumSpiOperationWriteStatus},\r | |
328 | {EnumSpiOpcodeWrite, SPI_COMMAND_WRITE, EnumSpiCycle33MHz, EnumSpiOperationProgramData_1_Byte},\r | |
329 | {EnumSpiOpcodeRead, SPI_COMMAND_READ, EnumSpiCycle33MHz, EnumSpiOperationReadData},\r | |
330 | {EnumSpiOpcodeWrite, SPI_COMMAND_BLOCK_ERASE, EnumSpiCycle33MHz, EnumSpiOperationErase_64K_Byte},\r | |
331 | {EnumSpiOpcodeReadNoAddr, SPI_COMMAND_READ_S, EnumSpiCycle33MHz, EnumSpiOperationReadStatus},\r | |
332 | {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE, EnumSpiCycle33MHz, EnumSpiOperationFullChipErase}\r | |
333 | },\r | |
334 | 0x800000 - FLASH_SIZE, // BIOS Start Offset\r | |
335 | FLASH_SIZE // BIOS image size in flash\r | |
336 | }\r | |
337 | };\r |