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a47463f2 | 1 | /** @file\r |
7fadaacd | 2 | CPU DXE Module to produce CPU ARCH Protocol.\r |
a47463f2 | 3 | \r |
22292ed3 | 4 | Copyright (c) 2008 - 2017, Intel Corporation. All rights reserved.<BR>\r |
01a1c0fc | 5 | This program and the accompanying materials\r |
a47463f2 | 6 | are licensed and made available under the terms and conditions of the BSD License\r |
7 | which accompanies this distribution. The full text of the license may be found at\r | |
8 | http://opensource.org/licenses/bsd-license.php\r | |
9 | \r | |
10 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
11 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
12 | \r | |
13 | **/\r | |
14 | \r | |
15 | #include "CpuDxe.h"\r | |
6022e28c | 16 | #include "CpuMp.h"\r |
22292ed3 JY |
17 | #include "CpuPageTable.h"\r |
18 | \r | |
19 | #define CACHE_ATTRIBUTE_MASK (EFI_MEMORY_UC | EFI_MEMORY_WC | EFI_MEMORY_WT | EFI_MEMORY_WB | EFI_MEMORY_UCE | EFI_MEMORY_WP)\r | |
20 | #define MEMORY_ATTRIBUTE_MASK (EFI_MEMORY_RP | EFI_MEMORY_XP | EFI_MEMORY_RO)\r | |
a47463f2 | 21 | \r |
22 | //\r | |
23 | // Global Variables\r | |
24 | //\r | |
a47463f2 | 25 | BOOLEAN InterruptState = FALSE;\r |
26 | EFI_HANDLE mCpuHandle = NULL;\r | |
27 | BOOLEAN mIsFlushingGCD;\r | |
c894f83f ED |
28 | UINT64 mValidMtrrAddressMask;\r |
29 | UINT64 mValidMtrrBitsMask;\r | |
7537f8c0 | 30 | UINT64 mTimerPeriod = 0;\r |
a47463f2 | 31 | \r |
32 | FIXED_MTRR mFixedMtrrTable[] = {\r | |
33 | {\r | |
b1bd0d74 | 34 | MSR_IA32_MTRR_FIX64K_00000,\r |
a47463f2 | 35 | 0,\r |
36 | 0x10000\r | |
37 | },\r | |
38 | {\r | |
b1bd0d74 | 39 | MSR_IA32_MTRR_FIX16K_80000,\r |
a47463f2 | 40 | 0x80000,\r |
41 | 0x4000\r | |
42 | },\r | |
43 | {\r | |
b1bd0d74 | 44 | MSR_IA32_MTRR_FIX16K_A0000,\r |
a47463f2 | 45 | 0xA0000,\r |
46 | 0x4000\r | |
47 | },\r | |
48 | {\r | |
b1bd0d74 | 49 | MSR_IA32_MTRR_FIX4K_C0000,\r |
a47463f2 | 50 | 0xC0000,\r |
51 | 0x1000\r | |
52 | },\r | |
53 | {\r | |
b1bd0d74 | 54 | MSR_IA32_MTRR_FIX4K_C8000,\r |
a47463f2 | 55 | 0xC8000,\r |
56 | 0x1000\r | |
57 | },\r | |
58 | {\r | |
b1bd0d74 | 59 | MSR_IA32_MTRR_FIX4K_D0000,\r |
a47463f2 | 60 | 0xD0000,\r |
61 | 0x1000\r | |
62 | },\r | |
63 | {\r | |
b1bd0d74 | 64 | MSR_IA32_MTRR_FIX4K_D8000,\r |
a47463f2 | 65 | 0xD8000,\r |
66 | 0x1000\r | |
67 | },\r | |
68 | {\r | |
b1bd0d74 | 69 | MSR_IA32_MTRR_FIX4K_E0000,\r |
a47463f2 | 70 | 0xE0000,\r |
71 | 0x1000\r | |
72 | },\r | |
73 | {\r | |
b1bd0d74 | 74 | MSR_IA32_MTRR_FIX4K_E8000,\r |
a47463f2 | 75 | 0xE8000,\r |
76 | 0x1000\r | |
77 | },\r | |
78 | {\r | |
b1bd0d74 | 79 | MSR_IA32_MTRR_FIX4K_F0000,\r |
a47463f2 | 80 | 0xF0000,\r |
81 | 0x1000\r | |
82 | },\r | |
83 | {\r | |
b1bd0d74 | 84 | MSR_IA32_MTRR_FIX4K_F8000,\r |
a47463f2 | 85 | 0xF8000,\r |
86 | 0x1000\r | |
87 | },\r | |
88 | };\r | |
89 | \r | |
90 | \r | |
91 | EFI_CPU_ARCH_PROTOCOL gCpu = {\r | |
92 | CpuFlushCpuDataCache,\r | |
93 | CpuEnableInterrupt,\r | |
94 | CpuDisableInterrupt,\r | |
95 | CpuGetInterruptState,\r | |
96 | CpuInit,\r | |
97 | CpuRegisterInterruptHandler,\r | |
98 | CpuGetTimerValue,\r | |
99 | CpuSetMemoryAttributes,\r | |
100 | 1, // NumberOfTimers\r | |
101 | 4 // DmaBufferAlignment\r | |
102 | };\r | |
103 | \r | |
a47463f2 | 104 | //\r |
105 | // CPU Arch Protocol Functions\r | |
106 | //\r | |
107 | \r | |
a47463f2 | 108 | /**\r |
109 | Flush CPU data cache. If the instruction cache is fully coherent\r | |
110 | with all DMA operations then function can just return EFI_SUCCESS.\r | |
111 | \r | |
112 | @param This Protocol instance structure\r | |
113 | @param Start Physical address to start flushing from.\r | |
114 | @param Length Number of bytes to flush. Round up to chipset\r | |
115 | granularity.\r | |
116 | @param FlushType Specifies the type of flush operation to perform.\r | |
117 | \r | |
118 | @retval EFI_SUCCESS If cache was flushed\r | |
119 | @retval EFI_UNSUPPORTED If flush type is not supported.\r | |
120 | @retval EFI_DEVICE_ERROR If requested range could not be flushed.\r | |
121 | \r | |
122 | **/\r | |
123 | EFI_STATUS\r | |
124 | EFIAPI\r | |
125 | CpuFlushCpuDataCache (\r | |
126 | IN EFI_CPU_ARCH_PROTOCOL *This,\r | |
127 | IN EFI_PHYSICAL_ADDRESS Start,\r | |
128 | IN UINT64 Length,\r | |
129 | IN EFI_CPU_FLUSH_TYPE FlushType\r | |
130 | )\r | |
131 | {\r | |
132 | if (FlushType == EfiCpuFlushTypeWriteBackInvalidate) {\r | |
133 | AsmWbinvd ();\r | |
134 | return EFI_SUCCESS;\r | |
135 | } else if (FlushType == EfiCpuFlushTypeInvalidate) {\r | |
136 | AsmInvd ();\r | |
137 | return EFI_SUCCESS;\r | |
138 | } else {\r | |
139 | return EFI_UNSUPPORTED;\r | |
140 | }\r | |
141 | }\r | |
142 | \r | |
143 | \r | |
144 | /**\r | |
145 | Enables CPU interrupts.\r | |
146 | \r | |
147 | @param This Protocol instance structure\r | |
148 | \r | |
149 | @retval EFI_SUCCESS If interrupts were enabled in the CPU\r | |
150 | @retval EFI_DEVICE_ERROR If interrupts could not be enabled on the CPU.\r | |
151 | \r | |
152 | **/\r | |
153 | EFI_STATUS\r | |
154 | EFIAPI\r | |
155 | CpuEnableInterrupt (\r | |
156 | IN EFI_CPU_ARCH_PROTOCOL *This\r | |
157 | )\r | |
158 | {\r | |
159 | EnableInterrupts ();\r | |
160 | \r | |
161 | InterruptState = TRUE;\r | |
162 | return EFI_SUCCESS;\r | |
163 | }\r | |
164 | \r | |
165 | \r | |
166 | /**\r | |
167 | Disables CPU interrupts.\r | |
168 | \r | |
169 | @param This Protocol instance structure\r | |
170 | \r | |
171 | @retval EFI_SUCCESS If interrupts were disabled in the CPU.\r | |
172 | @retval EFI_DEVICE_ERROR If interrupts could not be disabled on the CPU.\r | |
173 | \r | |
174 | **/\r | |
175 | EFI_STATUS\r | |
176 | EFIAPI\r | |
177 | CpuDisableInterrupt (\r | |
178 | IN EFI_CPU_ARCH_PROTOCOL *This\r | |
179 | )\r | |
180 | {\r | |
181 | DisableInterrupts ();\r | |
182 | \r | |
183 | InterruptState = FALSE;\r | |
184 | return EFI_SUCCESS;\r | |
185 | }\r | |
186 | \r | |
187 | \r | |
188 | /**\r | |
189 | Return the state of interrupts.\r | |
190 | \r | |
191 | @param This Protocol instance structure\r | |
192 | @param State Pointer to the CPU's current interrupt state\r | |
193 | \r | |
194 | @retval EFI_SUCCESS If interrupts were disabled in the CPU.\r | |
195 | @retval EFI_INVALID_PARAMETER State is NULL.\r | |
196 | \r | |
197 | **/\r | |
198 | EFI_STATUS\r | |
199 | EFIAPI\r | |
200 | CpuGetInterruptState (\r | |
201 | IN EFI_CPU_ARCH_PROTOCOL *This,\r | |
202 | OUT BOOLEAN *State\r | |
203 | )\r | |
204 | {\r | |
205 | if (State == NULL) {\r | |
206 | return EFI_INVALID_PARAMETER;\r | |
207 | }\r | |
208 | \r | |
209 | *State = InterruptState;\r | |
210 | return EFI_SUCCESS;\r | |
211 | }\r | |
212 | \r | |
213 | \r | |
214 | /**\r | |
215 | Generates an INIT to the CPU.\r | |
216 | \r | |
217 | @param This Protocol instance structure\r | |
218 | @param InitType Type of CPU INIT to perform\r | |
219 | \r | |
220 | @retval EFI_SUCCESS If CPU INIT occurred. This value should never be\r | |
221 | seen.\r | |
222 | @retval EFI_DEVICE_ERROR If CPU INIT failed.\r | |
223 | @retval EFI_UNSUPPORTED Requested type of CPU INIT not supported.\r | |
224 | \r | |
225 | **/\r | |
226 | EFI_STATUS\r | |
227 | EFIAPI\r | |
228 | CpuInit (\r | |
229 | IN EFI_CPU_ARCH_PROTOCOL *This,\r | |
230 | IN EFI_CPU_INIT_TYPE InitType\r | |
231 | )\r | |
232 | {\r | |
233 | return EFI_UNSUPPORTED;\r | |
234 | }\r | |
235 | \r | |
236 | \r | |
237 | /**\r | |
238 | Registers a function to be called from the CPU interrupt handler.\r | |
239 | \r | |
240 | @param This Protocol instance structure\r | |
241 | @param InterruptType Defines which interrupt to hook. IA-32\r | |
242 | valid range is 0x00 through 0xFF\r | |
243 | @param InterruptHandler A pointer to a function of type\r | |
244 | EFI_CPU_INTERRUPT_HANDLER that is called\r | |
245 | when a processor interrupt occurs. A null\r | |
246 | pointer is an error condition.\r | |
247 | \r | |
248 | @retval EFI_SUCCESS If handler installed or uninstalled.\r | |
249 | @retval EFI_ALREADY_STARTED InterruptHandler is not NULL, and a handler\r | |
250 | for InterruptType was previously installed.\r | |
251 | @retval EFI_INVALID_PARAMETER InterruptHandler is NULL, and a handler for\r | |
252 | InterruptType was not previously installed.\r | |
253 | @retval EFI_UNSUPPORTED The interrupt specified by InterruptType\r | |
254 | is not supported.\r | |
255 | \r | |
256 | **/\r | |
257 | EFI_STATUS\r | |
258 | EFIAPI\r | |
259 | CpuRegisterInterruptHandler (\r | |
260 | IN EFI_CPU_ARCH_PROTOCOL *This,\r | |
261 | IN EFI_EXCEPTION_TYPE InterruptType,\r | |
262 | IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler\r | |
263 | )\r | |
264 | {\r | |
e41aad15 | 265 | return RegisterCpuInterruptHandler (InterruptType, InterruptHandler);\r |
a47463f2 | 266 | }\r |
267 | \r | |
268 | \r | |
269 | /**\r | |
270 | Returns a timer value from one of the CPU's internal timers. There is no\r | |
271 | inherent time interval between ticks but is a function of the CPU frequency.\r | |
272 | \r | |
273 | @param This - Protocol instance structure.\r | |
274 | @param TimerIndex - Specifies which CPU timer is requested.\r | |
275 | @param TimerValue - Pointer to the returned timer value.\r | |
276 | @param TimerPeriod - A pointer to the amount of time that passes\r | |
277 | in femtoseconds (10-15) for each increment\r | |
278 | of TimerValue. If TimerValue does not\r | |
279 | increment at a predictable rate, then 0 is\r | |
280 | returned. The amount of time that has\r | |
281 | passed between two calls to GetTimerValue()\r | |
282 | can be calculated with the formula\r | |
283 | (TimerValue2 - TimerValue1) * TimerPeriod.\r | |
284 | This parameter is optional and may be NULL.\r | |
285 | \r | |
286 | @retval EFI_SUCCESS - If the CPU timer count was returned.\r | |
287 | @retval EFI_UNSUPPORTED - If the CPU does not have any readable timers.\r | |
288 | @retval EFI_DEVICE_ERROR - If an error occurred while reading the timer.\r | |
289 | @retval EFI_INVALID_PARAMETER - TimerIndex is not valid or TimerValue is NULL.\r | |
290 | \r | |
291 | **/\r | |
292 | EFI_STATUS\r | |
293 | EFIAPI\r | |
294 | CpuGetTimerValue (\r | |
295 | IN EFI_CPU_ARCH_PROTOCOL *This,\r | |
296 | IN UINT32 TimerIndex,\r | |
297 | OUT UINT64 *TimerValue,\r | |
298 | OUT UINT64 *TimerPeriod OPTIONAL\r | |
299 | )\r | |
300 | {\r | |
7537f8c0 JF |
301 | UINT64 BeginValue;\r |
302 | UINT64 EndValue;\r | |
303 | \r | |
a47463f2 | 304 | if (TimerValue == NULL) {\r |
305 | return EFI_INVALID_PARAMETER;\r | |
306 | }\r | |
307 | \r | |
308 | if (TimerIndex != 0) {\r | |
309 | return EFI_INVALID_PARAMETER;\r | |
310 | }\r | |
311 | \r | |
312 | *TimerValue = AsmReadTsc ();\r | |
313 | \r | |
314 | if (TimerPeriod != NULL) {\r | |
7537f8c0 JF |
315 | if (mTimerPeriod == 0) {\r |
316 | //\r | |
317 | // Read time stamp counter before and after delay of 100 microseconds\r | |
318 | //\r | |
319 | BeginValue = AsmReadTsc ();\r | |
320 | MicroSecondDelay (100);\r | |
321 | EndValue = AsmReadTsc ();\r | |
a47463f2 | 322 | //\r |
7537f8c0 | 323 | // Calculate the actual frequency\r |
a47463f2 | 324 | //\r |
7537f8c0 JF |
325 | mTimerPeriod = DivU64x64Remainder (\r |
326 | MultU64x32 (\r | |
327 | 1000 * 1000 * 1000,\r | |
328 | 100\r | |
329 | ),\r | |
330 | EndValue - BeginValue,\r | |
331 | NULL\r | |
332 | );\r | |
333 | }\r | |
334 | *TimerPeriod = mTimerPeriod;\r | |
a47463f2 | 335 | }\r |
336 | \r | |
337 | return EFI_SUCCESS;\r | |
338 | }\r | |
339 | \r | |
0b9f0dd6 JF |
340 | /**\r |
341 | A minimal wrapper function that allows MtrrSetAllMtrrs() to be passed to\r | |
342 | EFI_MP_SERVICES_PROTOCOL.StartupAllAPs() as Procedure.\r | |
343 | \r | |
344 | @param[in] Buffer Pointer to an MTRR_SETTINGS object, to be passed to\r | |
345 | MtrrSetAllMtrrs().\r | |
346 | **/\r | |
347 | VOID\r | |
348 | EFIAPI\r | |
349 | SetMtrrsFromBuffer (\r | |
350 | IN VOID *Buffer\r | |
351 | )\r | |
352 | {\r | |
353 | MtrrSetAllMtrrs (Buffer);\r | |
354 | }\r | |
a47463f2 | 355 | \r |
356 | /**\r | |
4ec21e8b | 357 | Implementation of SetMemoryAttributes() service of CPU Architecture Protocol.\r |
358 | \r | |
359 | This function modifies the attributes for the memory region specified by BaseAddress and\r | |
360 | Length from their current attributes to the attributes specified by Attributes.\r | |
361 | \r | |
362 | @param This The EFI_CPU_ARCH_PROTOCOL instance.\r | |
363 | @param BaseAddress The physical address that is the start address of a memory region.\r | |
364 | @param Length The size in bytes of the memory region.\r | |
365 | @param Attributes The bit mask of attributes to set for the memory region.\r | |
366 | \r | |
367 | @retval EFI_SUCCESS The attributes were set for the memory region.\r | |
368 | @retval EFI_ACCESS_DENIED The attributes for the memory resource range specified by\r | |
369 | BaseAddress and Length cannot be modified.\r | |
370 | @retval EFI_INVALID_PARAMETER Length is zero.\r | |
371 | Attributes specified an illegal combination of attributes that\r | |
372 | cannot be set together.\r | |
373 | @retval EFI_OUT_OF_RESOURCES There are not enough system resources to modify the attributes of\r | |
374 | the memory resource range.\r | |
375 | @retval EFI_UNSUPPORTED The processor does not support one or more bytes of the memory\r | |
376 | resource range specified by BaseAddress and Length.\r | |
377 | The bit mask of attributes is not support for the memory resource\r | |
378 | range specified by BaseAddress and Length.\r | |
a47463f2 | 379 | \r |
380 | **/\r | |
381 | EFI_STATUS\r | |
382 | EFIAPI\r | |
383 | CpuSetMemoryAttributes (\r | |
384 | IN EFI_CPU_ARCH_PROTOCOL *This,\r | |
385 | IN EFI_PHYSICAL_ADDRESS BaseAddress,\r | |
386 | IN UINT64 Length,\r | |
387 | IN UINT64 Attributes\r | |
388 | )\r | |
389 | {\r | |
390 | RETURN_STATUS Status;\r | |
391 | MTRR_MEMORY_CACHE_TYPE CacheType;\r | |
94941c88 LE |
392 | EFI_STATUS MpStatus;\r |
393 | EFI_MP_SERVICES_PROTOCOL *MpService;\r | |
394 | MTRR_SETTINGS MtrrSettings;\r | |
22292ed3 JY |
395 | UINT64 CacheAttributes;\r |
396 | UINT64 MemoryAttributes;\r | |
397 | MTRR_MEMORY_CACHE_TYPE CurrentCacheType;\r | |
947a573a | 398 | \r |
a47463f2 | 399 | //\r |
400 | // If this function is called because GCD SetMemorySpaceAttributes () is called\r | |
401 | // by RefreshGcdMemoryAttributes (), then we are just synchronzing GCD memory\r | |
402 | // map with MTRR values. So there is no need to modify MTRRs, just return immediately\r | |
403 | // to avoid unnecessary computing.\r | |
404 | //\r | |
405 | if (mIsFlushingGCD) {\r | |
af9bce40 | 406 | DEBUG((DEBUG_INFO, " Flushing GCD\n"));\r |
79aca636 SEHM |
407 | return EFI_SUCCESS;\r |
408 | }\r | |
a47463f2 | 409 | \r |
a47463f2 | 410 | \r |
22292ed3 JY |
411 | CacheAttributes = Attributes & CACHE_ATTRIBUTE_MASK;\r |
412 | MemoryAttributes = Attributes & MEMORY_ATTRIBUTE_MASK;\r | |
a47463f2 | 413 | \r |
22292ed3 JY |
414 | if (Attributes != (CacheAttributes | MemoryAttributes)) {\r |
415 | return EFI_INVALID_PARAMETER;\r | |
416 | }\r | |
a47463f2 | 417 | \r |
22292ed3 JY |
418 | if (CacheAttributes != 0) {\r |
419 | if (!IsMtrrSupported ()) {\r | |
420 | return EFI_UNSUPPORTED;\r | |
421 | }\r | |
a47463f2 | 422 | \r |
22292ed3 JY |
423 | switch (CacheAttributes) {\r |
424 | case EFI_MEMORY_UC:\r | |
425 | CacheType = CacheUncacheable;\r | |
426 | break;\r | |
a47463f2 | 427 | \r |
22292ed3 JY |
428 | case EFI_MEMORY_WC:\r |
429 | CacheType = CacheWriteCombining;\r | |
430 | break;\r | |
4ec21e8b | 431 | \r |
22292ed3 JY |
432 | case EFI_MEMORY_WT:\r |
433 | CacheType = CacheWriteThrough;\r | |
434 | break;\r | |
a47463f2 | 435 | \r |
22292ed3 JY |
436 | case EFI_MEMORY_WP:\r |
437 | CacheType = CacheWriteProtected;\r | |
438 | break;\r | |
439 | \r | |
440 | case EFI_MEMORY_WB:\r | |
441 | CacheType = CacheWriteBack;\r | |
442 | break;\r | |
443 | \r | |
444 | default:\r | |
445 | return EFI_INVALID_PARAMETER;\r | |
446 | }\r | |
447 | CurrentCacheType = MtrrGetMemoryAttribute(BaseAddress);\r | |
448 | if (CurrentCacheType != CacheType) {\r | |
449 | //\r | |
450 | // call MTRR libary function\r | |
451 | //\r | |
452 | Status = MtrrSetMemoryAttribute (\r | |
453 | BaseAddress,\r | |
454 | Length,\r | |
455 | CacheType\r | |
456 | );\r | |
457 | \r | |
458 | if (!RETURN_ERROR (Status)) {\r | |
459 | MpStatus = gBS->LocateProtocol (\r | |
460 | &gEfiMpServiceProtocolGuid,\r | |
461 | NULL,\r | |
462 | (VOID **)&MpService\r | |
463 | );\r | |
464 | //\r | |
465 | // Synchronize the update with all APs\r | |
466 | //\r | |
467 | if (!EFI_ERROR (MpStatus)) {\r | |
468 | MtrrGetAllMtrrs (&MtrrSettings);\r | |
469 | MpStatus = MpService->StartupAllAPs (\r | |
470 | MpService, // This\r | |
471 | SetMtrrsFromBuffer, // Procedure\r | |
472 | FALSE, // SingleThread\r | |
473 | NULL, // WaitEvent\r | |
474 | 0, // TimeoutInMicrosecsond\r | |
475 | &MtrrSettings, // ProcedureArgument\r | |
476 | NULL // FailedCpuList\r | |
477 | );\r | |
478 | ASSERT (MpStatus == EFI_SUCCESS || MpStatus == EFI_NOT_STARTED);\r | |
479 | }\r | |
480 | }\r | |
481 | if (EFI_ERROR(Status)) {\r | |
482 | return Status;\r | |
483 | }\r | |
94941c88 LE |
484 | }\r |
485 | }\r | |
22292ed3 JY |
486 | \r |
487 | //\r | |
488 | // Set memory attribute by page table\r | |
489 | //\r | |
490 | return AssignMemoryPageAttributes (NULL, BaseAddress, Length, MemoryAttributes, AllocatePages);\r | |
a47463f2 | 491 | }\r |
492 | \r | |
493 | /**\r | |
494 | Initializes the valid bits mask and valid address mask for MTRRs.\r | |
495 | \r | |
496 | This function initializes the valid bits mask and valid address mask for MTRRs.\r | |
497 | \r | |
498 | **/\r | |
499 | VOID\r | |
500 | InitializeMtrrMask (\r | |
501 | VOID\r | |
502 | )\r | |
503 | {\r | |
504 | UINT32 RegEax;\r | |
505 | UINT8 PhysicalAddressBits;\r | |
506 | \r | |
507 | AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL);\r | |
508 | \r | |
509 | if (RegEax >= 0x80000008) {\r | |
510 | AsmCpuid (0x80000008, &RegEax, NULL, NULL, NULL);\r | |
511 | \r | |
512 | PhysicalAddressBits = (UINT8) RegEax;\r | |
a47463f2 | 513 | } else {\r |
c894f83f | 514 | PhysicalAddressBits = 36;\r |
a47463f2 | 515 | }\r |
c894f83f ED |
516 | \r |
517 | mValidMtrrBitsMask = LShiftU64 (1, PhysicalAddressBits) - 1;\r | |
518 | mValidMtrrAddressMask = mValidMtrrBitsMask & 0xfffffffffffff000ULL;\r | |
a47463f2 | 519 | }\r |
520 | \r | |
521 | /**\r | |
430fbbe0 | 522 | Gets GCD Mem Space type from MTRR Type.\r |
a47463f2 | 523 | \r |
430fbbe0 | 524 | This function gets GCD Mem Space type from MTRR Type.\r |
a47463f2 | 525 | \r |
430fbbe0 | 526 | @param MtrrAttributes MTRR memory type\r |
a47463f2 | 527 | \r |
528 | @return GCD Mem Space type\r | |
529 | \r | |
530 | **/\r | |
531 | UINT64\r | |
532 | GetMemorySpaceAttributeFromMtrrType (\r | |
2c4b1bdc | 533 | IN UINT8 MtrrAttributes\r |
a47463f2 | 534 | )\r |
535 | {\r | |
536 | switch (MtrrAttributes) {\r | |
537 | case MTRR_CACHE_UNCACHEABLE:\r | |
538 | return EFI_MEMORY_UC;\r | |
539 | case MTRR_CACHE_WRITE_COMBINING:\r | |
540 | return EFI_MEMORY_WC;\r | |
541 | case MTRR_CACHE_WRITE_THROUGH:\r | |
542 | return EFI_MEMORY_WT;\r | |
543 | case MTRR_CACHE_WRITE_PROTECTED:\r | |
544 | return EFI_MEMORY_WP;\r | |
545 | case MTRR_CACHE_WRITE_BACK:\r | |
546 | return EFI_MEMORY_WB;\r | |
547 | default:\r | |
548 | return 0;\r | |
549 | }\r | |
550 | }\r | |
551 | \r | |
552 | /**\r | |
553 | Searches memory descriptors covered by given memory range.\r | |
554 | \r | |
555 | This function searches into the Gcd Memory Space for descriptors\r | |
556 | (from StartIndex to EndIndex) that contains the memory range\r | |
557 | specified by BaseAddress and Length.\r | |
558 | \r | |
559 | @param MemorySpaceMap Gcd Memory Space Map as array.\r | |
560 | @param NumberOfDescriptors Number of descriptors in map.\r | |
561 | @param BaseAddress BaseAddress for the requested range.\r | |
562 | @param Length Length for the requested range.\r | |
563 | @param StartIndex Start index into the Gcd Memory Space Map.\r | |
564 | @param EndIndex End index into the Gcd Memory Space Map.\r | |
565 | \r | |
566 | @retval EFI_SUCCESS Search successfully.\r | |
567 | @retval EFI_NOT_FOUND The requested descriptors does not exist.\r | |
568 | \r | |
569 | **/\r | |
570 | EFI_STATUS\r | |
571 | SearchGcdMemorySpaces (\r | |
572 | IN EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap,\r | |
573 | IN UINTN NumberOfDescriptors,\r | |
574 | IN EFI_PHYSICAL_ADDRESS BaseAddress,\r | |
575 | IN UINT64 Length,\r | |
576 | OUT UINTN *StartIndex,\r | |
577 | OUT UINTN *EndIndex\r | |
578 | )\r | |
579 | {\r | |
580 | UINTN Index;\r | |
581 | \r | |
582 | *StartIndex = 0;\r | |
583 | *EndIndex = 0;\r | |
584 | for (Index = 0; Index < NumberOfDescriptors; Index++) {\r | |
585 | if (BaseAddress >= MemorySpaceMap[Index].BaseAddress &&\r | |
586 | BaseAddress < MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length) {\r | |
587 | *StartIndex = Index;\r | |
588 | }\r | |
589 | if (BaseAddress + Length - 1 >= MemorySpaceMap[Index].BaseAddress &&\r | |
590 | BaseAddress + Length - 1 < MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length) {\r | |
591 | *EndIndex = Index;\r | |
592 | return EFI_SUCCESS;\r | |
593 | }\r | |
594 | }\r | |
595 | return EFI_NOT_FOUND;\r | |
596 | }\r | |
597 | \r | |
598 | /**\r | |
599 | Sets the attributes for a specified range in Gcd Memory Space Map.\r | |
600 | \r | |
601 | This function sets the attributes for a specified range in\r | |
602 | Gcd Memory Space Map.\r | |
603 | \r | |
604 | @param MemorySpaceMap Gcd Memory Space Map as array\r | |
605 | @param NumberOfDescriptors Number of descriptors in map\r | |
606 | @param BaseAddress BaseAddress for the range\r | |
607 | @param Length Length for the range\r | |
608 | @param Attributes Attributes to set\r | |
609 | \r | |
610 | @retval EFI_SUCCESS Memory attributes set successfully\r | |
611 | @retval EFI_NOT_FOUND The specified range does not exist in Gcd Memory Space\r | |
612 | \r | |
613 | **/\r | |
614 | EFI_STATUS\r | |
615 | SetGcdMemorySpaceAttributes (\r | |
616 | IN EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap,\r | |
617 | IN UINTN NumberOfDescriptors,\r | |
618 | IN EFI_PHYSICAL_ADDRESS BaseAddress,\r | |
619 | IN UINT64 Length,\r | |
620 | IN UINT64 Attributes\r | |
621 | )\r | |
622 | {\r | |
623 | EFI_STATUS Status;\r | |
624 | UINTN Index;\r | |
625 | UINTN StartIndex;\r | |
626 | UINTN EndIndex;\r | |
627 | EFI_PHYSICAL_ADDRESS RegionStart;\r | |
628 | UINT64 RegionLength;\r | |
629 | \r | |
630 | //\r | |
631 | // Get all memory descriptors covered by the memory range\r | |
632 | //\r | |
633 | Status = SearchGcdMemorySpaces (\r | |
634 | MemorySpaceMap,\r | |
635 | NumberOfDescriptors,\r | |
636 | BaseAddress,\r | |
637 | Length,\r | |
638 | &StartIndex,\r | |
639 | &EndIndex\r | |
640 | );\r | |
641 | if (EFI_ERROR (Status)) {\r | |
642 | return Status;\r | |
643 | }\r | |
644 | \r | |
645 | //\r | |
646 | // Go through all related descriptors and set attributes accordingly\r | |
647 | //\r | |
648 | for (Index = StartIndex; Index <= EndIndex; Index++) {\r | |
649 | if (MemorySpaceMap[Index].GcdMemoryType == EfiGcdMemoryTypeNonExistent) {\r | |
650 | continue;\r | |
651 | }\r | |
652 | //\r | |
653 | // Calculate the start and end address of the overlapping range\r | |
654 | //\r | |
655 | if (BaseAddress >= MemorySpaceMap[Index].BaseAddress) {\r | |
656 | RegionStart = BaseAddress;\r | |
657 | } else {\r | |
658 | RegionStart = MemorySpaceMap[Index].BaseAddress;\r | |
659 | }\r | |
660 | if (BaseAddress + Length - 1 < MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length) {\r | |
661 | RegionLength = BaseAddress + Length - RegionStart;\r | |
662 | } else {\r | |
663 | RegionLength = MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length - RegionStart;\r | |
664 | }\r | |
665 | //\r | |
666 | // Set memory attributes according to MTRR attribute and the original attribute of descriptor\r | |
667 | //\r | |
668 | gDS->SetMemorySpaceAttributes (\r | |
669 | RegionStart,\r | |
670 | RegionLength,\r | |
671 | (MemorySpaceMap[Index].Attributes & ~EFI_MEMORY_CACHETYPE_MASK) | (MemorySpaceMap[Index].Capabilities & Attributes)\r | |
672 | );\r | |
673 | }\r | |
674 | \r | |
675 | return EFI_SUCCESS;\r | |
676 | }\r | |
677 | \r | |
678 | \r | |
679 | /**\r | |
680 | Refreshes the GCD Memory Space attributes according to MTRRs.\r | |
681 | \r | |
682 | This function refreshes the GCD Memory Space attributes according to MTRRs.\r | |
683 | \r | |
684 | **/\r | |
685 | VOID\r | |
686 | RefreshGcdMemoryAttributes (\r | |
687 | VOID\r | |
688 | )\r | |
689 | {\r | |
690 | EFI_STATUS Status;\r | |
691 | UINTN Index;\r | |
692 | UINTN SubIndex;\r | |
693 | UINT64 RegValue;\r | |
694 | EFI_PHYSICAL_ADDRESS BaseAddress;\r | |
695 | UINT64 Length;\r | |
696 | UINT64 Attributes;\r | |
697 | UINT64 CurrentAttributes;\r | |
2c4b1bdc | 698 | UINT8 MtrrType;\r |
a47463f2 | 699 | UINTN NumberOfDescriptors;\r |
700 | EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap;\r | |
701 | UINT64 DefaultAttributes;\r | |
6640eb36 | 702 | VARIABLE_MTRR VariableMtrr[MTRR_NUMBER_OF_VARIABLE_MTRR];\r |
a47463f2 | 703 | MTRR_FIXED_SETTINGS MtrrFixedSettings;\r |
3b9be416 | 704 | UINT32 FirmwareVariableMtrrCount;\r |
2c4b1bdc | 705 | UINT8 DefaultMemoryType;\r |
3b9be416 | 706 | \r |
947a573a | 707 | if (!IsMtrrSupported ()) {\r |
708 | return;\r | |
709 | }\r | |
710 | \r | |
3b9be416 | 711 | FirmwareVariableMtrrCount = GetFirmwareVariableMtrrCount ();\r |
5bdfa4e5 | 712 | ASSERT (FirmwareVariableMtrrCount <= MTRR_NUMBER_OF_VARIABLE_MTRR);\r |
a47463f2 | 713 | \r |
91ec7824 | 714 | mIsFlushingGCD = TRUE;\r |
a47463f2 | 715 | MemorySpaceMap = NULL;\r |
716 | \r | |
717 | //\r | |
718 | // Initialize the valid bits mask and valid address mask for MTRRs\r | |
719 | //\r | |
720 | InitializeMtrrMask ();\r | |
721 | \r | |
722 | //\r | |
723 | // Get the memory attribute of variable MTRRs\r | |
724 | //\r | |
725 | MtrrGetMemoryAttributeInVariableMtrr (\r | |
726 | mValidMtrrBitsMask,\r | |
727 | mValidMtrrAddressMask,\r | |
728 | VariableMtrr\r | |
729 | );\r | |
730 | \r | |
731 | //\r | |
732 | // Get the memory space map from GCD\r | |
733 | //\r | |
734 | Status = gDS->GetMemorySpaceMap (\r | |
735 | &NumberOfDescriptors,\r | |
736 | &MemorySpaceMap\r | |
737 | );\r | |
738 | ASSERT_EFI_ERROR (Status);\r | |
739 | \r | |
2c4b1bdc | 740 | DefaultMemoryType = (UINT8) MtrrGetDefaultMemoryType ();\r |
91ec7824 | 741 | DefaultAttributes = GetMemorySpaceAttributeFromMtrrType (DefaultMemoryType);\r |
a47463f2 | 742 | \r |
743 | //\r | |
744 | // Set default attributes to all spaces.\r | |
745 | //\r | |
746 | for (Index = 0; Index < NumberOfDescriptors; Index++) {\r | |
747 | if (MemorySpaceMap[Index].GcdMemoryType == EfiGcdMemoryTypeNonExistent) {\r | |
748 | continue;\r | |
749 | }\r | |
750 | gDS->SetMemorySpaceAttributes (\r | |
751 | MemorySpaceMap[Index].BaseAddress,\r | |
752 | MemorySpaceMap[Index].Length,\r | |
753 | (MemorySpaceMap[Index].Attributes & ~EFI_MEMORY_CACHETYPE_MASK) |\r | |
754 | (MemorySpaceMap[Index].Capabilities & DefaultAttributes)\r | |
755 | );\r | |
756 | }\r | |
757 | \r | |
758 | //\r | |
759 | // Go for variable MTRRs with WB attribute\r | |
760 | //\r | |
3b9be416 | 761 | for (Index = 0; Index < FirmwareVariableMtrrCount; Index++) {\r |
a47463f2 | 762 | if (VariableMtrr[Index].Valid &&\r |
763 | VariableMtrr[Index].Type == MTRR_CACHE_WRITE_BACK) {\r | |
764 | SetGcdMemorySpaceAttributes (\r | |
765 | MemorySpaceMap,\r | |
766 | NumberOfDescriptors,\r | |
767 | VariableMtrr[Index].BaseAddress,\r | |
768 | VariableMtrr[Index].Length,\r | |
769 | EFI_MEMORY_WB\r | |
770 | );\r | |
771 | }\r | |
772 | }\r | |
91ec7824 | 773 | \r |
a47463f2 | 774 | //\r |
91ec7824 | 775 | // Go for variable MTRRs with the attribute except for WB and UC attributes\r |
a47463f2 | 776 | //\r |
3b9be416 | 777 | for (Index = 0; Index < FirmwareVariableMtrrCount; Index++) {\r |
d4605c23 | 778 | if (VariableMtrr[Index].Valid &&\r |
91ec7824 | 779 | VariableMtrr[Index].Type != MTRR_CACHE_WRITE_BACK &&\r |
780 | VariableMtrr[Index].Type != MTRR_CACHE_UNCACHEABLE) {\r | |
2c4b1bdc | 781 | Attributes = GetMemorySpaceAttributeFromMtrrType ((UINT8) VariableMtrr[Index].Type);\r |
a47463f2 | 782 | SetGcdMemorySpaceAttributes (\r |
783 | MemorySpaceMap,\r | |
784 | NumberOfDescriptors,\r | |
785 | VariableMtrr[Index].BaseAddress,\r | |
786 | VariableMtrr[Index].Length,\r | |
787 | Attributes\r | |
788 | );\r | |
789 | }\r | |
790 | }\r | |
791 | \r | |
91ec7824 | 792 | //\r |
793 | // Go for variable MTRRs with UC attribute\r | |
794 | //\r | |
795 | for (Index = 0; Index < FirmwareVariableMtrrCount; Index++) {\r | |
796 | if (VariableMtrr[Index].Valid &&\r | |
797 | VariableMtrr[Index].Type == MTRR_CACHE_UNCACHEABLE) {\r | |
798 | SetGcdMemorySpaceAttributes (\r | |
799 | MemorySpaceMap,\r | |
800 | NumberOfDescriptors,\r | |
801 | VariableMtrr[Index].BaseAddress,\r | |
802 | VariableMtrr[Index].Length,\r | |
803 | EFI_MEMORY_UC\r | |
804 | );\r | |
805 | }\r | |
806 | }\r | |
807 | \r | |
a47463f2 | 808 | //\r |
809 | // Go for fixed MTRRs\r | |
810 | //\r | |
811 | Attributes = 0;\r | |
812 | BaseAddress = 0;\r | |
813 | Length = 0;\r | |
814 | MtrrGetFixedMtrr (&MtrrFixedSettings);\r | |
815 | for (Index = 0; Index < MTRR_NUMBER_OF_FIXED_MTRR; Index++) {\r | |
816 | RegValue = MtrrFixedSettings.Mtrr[Index];\r | |
817 | //\r | |
818 | // Check for continuous fixed MTRR sections\r | |
819 | //\r | |
820 | for (SubIndex = 0; SubIndex < 8; SubIndex++) {\r | |
2c4b1bdc | 821 | MtrrType = (UINT8) RShiftU64 (RegValue, SubIndex * 8);\r |
a47463f2 | 822 | CurrentAttributes = GetMemorySpaceAttributeFromMtrrType (MtrrType);\r |
823 | if (Length == 0) {\r | |
824 | //\r | |
825 | // A new MTRR attribute begins\r | |
826 | //\r | |
827 | Attributes = CurrentAttributes;\r | |
828 | } else {\r | |
829 | //\r | |
830 | // If fixed MTRR attribute changed, then set memory attribute for previous atrribute\r | |
831 | //\r | |
832 | if (CurrentAttributes != Attributes) {\r | |
833 | SetGcdMemorySpaceAttributes (\r | |
834 | MemorySpaceMap,\r | |
835 | NumberOfDescriptors,\r | |
836 | BaseAddress,\r | |
837 | Length,\r | |
838 | Attributes\r | |
839 | );\r | |
840 | BaseAddress = mFixedMtrrTable[Index].BaseAddress + mFixedMtrrTable[Index].Length * SubIndex;\r | |
841 | Length = 0;\r | |
842 | Attributes = CurrentAttributes;\r | |
843 | }\r | |
844 | }\r | |
845 | Length += mFixedMtrrTable[Index].Length;\r | |
846 | }\r | |
847 | }\r | |
848 | //\r | |
849 | // Handle the last fixed MTRR region\r | |
850 | //\r | |
851 | SetGcdMemorySpaceAttributes (\r | |
852 | MemorySpaceMap,\r | |
853 | NumberOfDescriptors,\r | |
854 | BaseAddress,\r | |
855 | Length,\r | |
856 | Attributes\r | |
857 | );\r | |
858 | \r | |
859 | //\r | |
860 | // Free memory space map allocated by GCD service GetMemorySpaceMap ()\r | |
861 | //\r | |
862 | if (MemorySpaceMap != NULL) {\r | |
863 | FreePool (MemorySpaceMap);\r | |
864 | }\r | |
865 | \r | |
c1cab54c JW |
866 | //\r |
867 | // Update page attributes\r | |
868 | //\r | |
869 | RefreshGcdMemoryAttributesFromPaging();\r | |
870 | \r | |
a47463f2 | 871 | mIsFlushingGCD = FALSE;\r |
872 | }\r | |
873 | \r | |
a47463f2 | 874 | /**\r |
875 | Initialize Interrupt Descriptor Table for interrupt handling.\r | |
876 | \r | |
877 | **/\r | |
a47463f2 | 878 | VOID\r |
879 | InitInterruptDescriptorTable (\r | |
880 | VOID\r | |
881 | )\r | |
882 | {\r | |
e41aad15 JF |
883 | EFI_STATUS Status;\r |
884 | EFI_VECTOR_HANDOFF_INFO *VectorInfoList;\r | |
885 | EFI_VECTOR_HANDOFF_INFO *VectorInfo;\r | |
886 | \r | |
887 | VectorInfo = NULL;\r | |
888 | Status = EfiGetSystemConfigurationTable (&gEfiVectorHandoffTableGuid, (VOID **) &VectorInfoList);\r | |
889 | if (Status == EFI_SUCCESS && VectorInfoList != NULL) {\r | |
890 | VectorInfo = VectorInfoList;\r | |
a47463f2 | 891 | }\r |
e41aad15 JF |
892 | Status = InitializeCpuInterruptHandlers (VectorInfo);\r |
893 | ASSERT_EFI_ERROR (Status);\r | |
a47463f2 | 894 | }\r |
895 | \r | |
896 | \r | |
32394027 | 897 | /**\r |
898 | Callback function for idle events.\r | |
d4605c23 | 899 | \r |
32394027 | 900 | @param Event Event whose notification function is being invoked.\r |
901 | @param Context The pointer to the notification function's context,\r | |
902 | which is implementation-dependent.\r | |
903 | \r | |
904 | **/\r | |
905 | VOID\r | |
906 | EFIAPI\r | |
907 | IdleLoopEventCallback (\r | |
908 | IN EFI_EVENT Event,\r | |
909 | IN VOID *Context\r | |
910 | )\r | |
911 | {\r | |
912 | CpuSleep ();\r | |
913 | }\r | |
914 | \r | |
410590f1 JF |
915 | /**\r |
916 | Ensure the compatibility of a memory space descriptor with the MMIO aperture.\r | |
917 | \r | |
918 | The memory space descriptor can come from the GCD memory space map, or it can\r | |
919 | represent a gap between two neighboring memory space descriptors. In the\r | |
920 | latter case, the GcdMemoryType field is expected to be\r | |
921 | EfiGcdMemoryTypeNonExistent.\r | |
922 | \r | |
923 | If the memory space descriptor already has type\r | |
924 | EfiGcdMemoryTypeMemoryMappedIo, and its capabilities are a superset of the\r | |
925 | required capabilities, then no action is taken -- it is by definition\r | |
926 | compatible with the aperture.\r | |
927 | \r | |
928 | Otherwise, the intersection of the memory space descriptor is calculated with\r | |
929 | the aperture. If the intersection is the empty set (no overlap), no action is\r | |
930 | taken; the memory space descriptor is compatible with the aperture.\r | |
931 | \r | |
932 | Otherwise, the type of the descriptor is investigated again. If the type is\r | |
933 | EfiGcdMemoryTypeNonExistent (representing a gap, or a genuine descriptor with\r | |
934 | such a type), then an attempt is made to add the intersection as MMIO space\r | |
935 | to the GCD memory space map, with the specified capabilities. This ensures\r | |
936 | continuity for the aperture, and the descriptor is deemed compatible with the\r | |
937 | aperture.\r | |
938 | \r | |
939 | Otherwise, the memory space descriptor is incompatible with the MMIO\r | |
940 | aperture.\r | |
941 | \r | |
942 | @param[in] Base Base address of the aperture.\r | |
943 | @param[in] Length Length of the aperture.\r | |
944 | @param[in] Capabilities Capabilities required by the aperture.\r | |
945 | @param[in] Descriptor The descriptor to ensure compatibility with the\r | |
946 | aperture for.\r | |
947 | \r | |
948 | @retval EFI_SUCCESS The descriptor is compatible. The GCD memory\r | |
949 | space map may have been updated, for\r | |
950 | continuity within the aperture.\r | |
951 | @retval EFI_INVALID_PARAMETER The descriptor is incompatible.\r | |
952 | @return Error codes from gDS->AddMemorySpace().\r | |
953 | **/\r | |
954 | EFI_STATUS\r | |
955 | IntersectMemoryDescriptor (\r | |
956 | IN UINT64 Base,\r | |
957 | IN UINT64 Length,\r | |
958 | IN UINT64 Capabilities,\r | |
959 | IN CONST EFI_GCD_MEMORY_SPACE_DESCRIPTOR *Descriptor\r | |
960 | )\r | |
961 | {\r | |
962 | UINT64 IntersectionBase;\r | |
963 | UINT64 IntersectionEnd;\r | |
964 | EFI_STATUS Status;\r | |
965 | \r | |
966 | if (Descriptor->GcdMemoryType == EfiGcdMemoryTypeMemoryMappedIo &&\r | |
967 | (Descriptor->Capabilities & Capabilities) == Capabilities) {\r | |
968 | return EFI_SUCCESS;\r | |
969 | }\r | |
970 | \r | |
971 | IntersectionBase = MAX (Base, Descriptor->BaseAddress);\r | |
972 | IntersectionEnd = MIN (Base + Length,\r | |
973 | Descriptor->BaseAddress + Descriptor->Length);\r | |
974 | if (IntersectionBase >= IntersectionEnd) {\r | |
975 | //\r | |
976 | // The descriptor and the aperture don't overlap.\r | |
977 | //\r | |
978 | return EFI_SUCCESS;\r | |
979 | }\r | |
980 | \r | |
981 | if (Descriptor->GcdMemoryType == EfiGcdMemoryTypeNonExistent) {\r | |
982 | Status = gDS->AddMemorySpace (EfiGcdMemoryTypeMemoryMappedIo,\r | |
983 | IntersectionBase, IntersectionEnd - IntersectionBase,\r | |
984 | Capabilities);\r | |
985 | \r | |
af9bce40 | 986 | DEBUG ((EFI_ERROR (Status) ? DEBUG_ERROR : DEBUG_VERBOSE,\r |
410590f1 JF |
987 | "%a: %a: add [%Lx, %Lx): %r\n", gEfiCallerBaseName, __FUNCTION__,\r |
988 | IntersectionBase, IntersectionEnd, Status));\r | |
989 | return Status;\r | |
990 | }\r | |
991 | \r | |
af9bce40 | 992 | DEBUG ((DEBUG_ERROR, "%a: %a: desc [%Lx, %Lx) type %u cap %Lx conflicts "\r |
410590f1 JF |
993 | "with aperture [%Lx, %Lx) cap %Lx\n", gEfiCallerBaseName, __FUNCTION__,\r |
994 | Descriptor->BaseAddress, Descriptor->BaseAddress + Descriptor->Length,\r | |
995 | (UINT32)Descriptor->GcdMemoryType, Descriptor->Capabilities,\r | |
996 | Base, Base + Length, Capabilities));\r | |
997 | return EFI_INVALID_PARAMETER;\r | |
998 | }\r | |
999 | \r | |
1000 | /**\r | |
1001 | Add MMIO space to GCD.\r | |
1002 | The routine checks the GCD database and only adds those which are\r | |
1003 | not added in the specified range to GCD.\r | |
1004 | \r | |
1005 | @param Base Base address of the MMIO space.\r | |
1006 | @param Length Length of the MMIO space.\r | |
1007 | @param Capabilities Capabilities of the MMIO space.\r | |
1008 | \r | |
1009 | @retval EFI_SUCCES The MMIO space was added successfully.\r | |
1010 | **/\r | |
1011 | EFI_STATUS\r | |
1012 | AddMemoryMappedIoSpace (\r | |
1013 | IN UINT64 Base,\r | |
1014 | IN UINT64 Length,\r | |
1015 | IN UINT64 Capabilities\r | |
1016 | )\r | |
1017 | {\r | |
1018 | EFI_STATUS Status;\r | |
1019 | UINTN Index;\r | |
1020 | UINTN NumberOfDescriptors;\r | |
1021 | EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap;\r | |
1022 | \r | |
1023 | Status = gDS->GetMemorySpaceMap (&NumberOfDescriptors, &MemorySpaceMap);\r | |
1024 | if (EFI_ERROR (Status)) {\r | |
af9bce40 | 1025 | DEBUG ((DEBUG_ERROR, "%a: %a: GetMemorySpaceMap(): %r\n",\r |
410590f1 JF |
1026 | gEfiCallerBaseName, __FUNCTION__, Status));\r |
1027 | return Status;\r | |
1028 | }\r | |
1029 | \r | |
1030 | for (Index = 0; Index < NumberOfDescriptors; Index++) {\r | |
1031 | Status = IntersectMemoryDescriptor (Base, Length, Capabilities,\r | |
1032 | &MemorySpaceMap[Index]);\r | |
1033 | if (EFI_ERROR (Status)) {\r | |
1034 | goto FreeMemorySpaceMap;\r | |
1035 | }\r | |
1036 | }\r | |
1037 | \r | |
1038 | DEBUG_CODE (\r | |
1039 | //\r | |
1040 | // Make sure there are adjacent descriptors covering [Base, Base + Length).\r | |
1041 | // It is possible that they have not been merged; merging can be prevented\r | |
1042 | // by allocation and different capabilities.\r | |
1043 | //\r | |
1044 | UINT64 CheckBase;\r | |
1045 | EFI_STATUS CheckStatus;\r | |
1046 | EFI_GCD_MEMORY_SPACE_DESCRIPTOR Descriptor;\r | |
1047 | \r | |
1048 | for (CheckBase = Base;\r | |
1049 | CheckBase < Base + Length;\r | |
1050 | CheckBase = Descriptor.BaseAddress + Descriptor.Length) {\r | |
1051 | CheckStatus = gDS->GetMemorySpaceDescriptor (CheckBase, &Descriptor);\r | |
1052 | ASSERT_EFI_ERROR (CheckStatus);\r | |
1053 | ASSERT (Descriptor.GcdMemoryType == EfiGcdMemoryTypeMemoryMappedIo);\r | |
1054 | ASSERT ((Descriptor.Capabilities & Capabilities) == Capabilities);\r | |
1055 | }\r | |
1056 | );\r | |
1057 | \r | |
1058 | FreeMemorySpaceMap:\r | |
1059 | FreePool (MemorySpaceMap);\r | |
1060 | \r | |
1061 | return Status;\r | |
1062 | }\r | |
32394027 | 1063 | \r |
14f92ded JF |
1064 | /**\r |
1065 | Add and allocate CPU local APIC memory mapped space. \r | |
1066 | \r | |
1067 | @param[in]ImageHandle Image handle this driver.\r | |
1068 | \r | |
1069 | **/\r | |
1070 | VOID\r | |
1071 | AddLocalApicMemorySpace (\r | |
1072 | IN EFI_HANDLE ImageHandle\r | |
1073 | )\r | |
1074 | {\r | |
1075 | EFI_STATUS Status;\r | |
1076 | EFI_PHYSICAL_ADDRESS BaseAddress;\r | |
1077 | \r | |
1078 | BaseAddress = (EFI_PHYSICAL_ADDRESS) GetLocalApicBaseAddress();\r | |
1079 | Status = AddMemoryMappedIoSpace (BaseAddress, SIZE_4KB, EFI_MEMORY_UC);\r | |
1080 | ASSERT_EFI_ERROR (Status);\r | |
1081 | \r | |
29c90f14 JF |
1082 | //\r |
1083 | // Try to allocate APIC memory mapped space, does not check return \r | |
1084 | // status because it may be allocated by other driver, or DXE Core if\r | |
1085 | // this range is built into Memory Allocation HOB.\r | |
1086 | //\r | |
14f92ded JF |
1087 | Status = gDS->AllocateMemorySpace (\r |
1088 | EfiGcdAllocateAddress,\r | |
1089 | EfiGcdMemoryTypeMemoryMappedIo,\r | |
1090 | 0,\r | |
1091 | SIZE_4KB,\r | |
1092 | &BaseAddress,\r | |
1093 | ImageHandle,\r | |
1094 | NULL\r | |
1095 | );\r | |
29c90f14 JF |
1096 | if (EFI_ERROR (Status)) {\r |
1097 | DEBUG ((DEBUG_INFO, "%a: %a: AllocateMemorySpace() Status - %r\n",\r | |
1098 | gEfiCallerBaseName, __FUNCTION__, Status));\r | |
1099 | }\r | |
14f92ded JF |
1100 | }\r |
1101 | \r | |
a47463f2 | 1102 | /**\r |
1103 | Initialize the state information for the CPU Architectural Protocol.\r | |
1104 | \r | |
1105 | @param ImageHandle Image handle this driver.\r | |
1106 | @param SystemTable Pointer to the System Table.\r | |
1107 | \r | |
1108 | @retval EFI_SUCCESS Thread can be successfully created\r | |
1109 | @retval EFI_OUT_OF_RESOURCES Cannot allocate protocol data structure\r | |
1110 | @retval EFI_DEVICE_ERROR Cannot create the thread\r | |
1111 | \r | |
1112 | **/\r | |
1113 | EFI_STATUS\r | |
1114 | EFIAPI\r | |
1115 | InitializeCpu (\r | |
1116 | IN EFI_HANDLE ImageHandle,\r | |
1117 | IN EFI_SYSTEM_TABLE *SystemTable\r | |
1118 | )\r | |
1119 | {\r | |
1120 | EFI_STATUS Status;\r | |
32394027 | 1121 | EFI_EVENT IdleLoopEvent;\r |
22292ed3 JY |
1122 | \r |
1123 | InitializePageTableLib();\r | |
a47463f2 | 1124 | \r |
661cab5d | 1125 | InitializeFloatingPointUnits ();\r |
1126 | \r | |
a47463f2 | 1127 | //\r |
1128 | // Make sure interrupts are disabled\r | |
1129 | //\r | |
1130 | DisableInterrupts ();\r | |
1131 | \r | |
1132 | //\r | |
1133 | // Init GDT for DXE\r | |
1134 | //\r | |
1135 | InitGlobalDescriptorTable ();\r | |
1136 | \r | |
1137 | //\r | |
1138 | // Setup IDT pointer, IDT and interrupt entry points\r | |
1139 | //\r | |
1140 | InitInterruptDescriptorTable ();\r | |
1141 | \r | |
1142 | //\r | |
1143 | // Install CPU Architectural Protocol\r | |
1144 | //\r | |
1145 | Status = gBS->InstallMultipleProtocolInterfaces (\r | |
1146 | &mCpuHandle,\r | |
1147 | &gEfiCpuArchProtocolGuid, &gCpu,\r | |
1148 | NULL\r | |
1149 | );\r | |
1150 | ASSERT_EFI_ERROR (Status);\r | |
1151 | \r | |
1152 | //\r | |
1153 | // Refresh GCD memory space map according to MTRR value.\r | |
1154 | //\r | |
1155 | RefreshGcdMemoryAttributes ();\r | |
1156 | \r | |
14f92ded JF |
1157 | //\r |
1158 | // Add and allocate local APIC memory mapped space\r | |
1159 | //\r | |
1160 | AddLocalApicMemorySpace (ImageHandle);\r | |
1161 | \r | |
32394027 | 1162 | //\r |
1163 | // Setup a callback for idle events\r | |
1164 | //\r | |
1165 | Status = gBS->CreateEventEx (\r | |
1166 | EVT_NOTIFY_SIGNAL,\r | |
1167 | TPL_NOTIFY,\r | |
1168 | IdleLoopEventCallback,\r | |
1169 | NULL,\r | |
1170 | &gIdleLoopEventGuid,\r | |
1171 | &IdleLoopEvent\r | |
1172 | );\r | |
1173 | ASSERT_EFI_ERROR (Status);\r | |
1174 | \r | |
6022e28c JJ |
1175 | InitializeMpSupport ();\r |
1176 | \r | |
a47463f2 | 1177 | return Status;\r |
1178 | }\r | |
1179 | \r |