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1 | /** @file\r |
2 | MSR Definitions for the Intel(R) Atom(TM) Processor Family.\r | |
3 | \r | |
4 | Provides defines for Machine Specific Registers(MSR) indexes. Data structures\r | |
5 | are provided for MSRs that contain one or more bit fields. If the MSR value\r | |
6 | returned is a single 32-bit or 64-bit value, then a data structure is not\r | |
7 | provided for that MSR.\r | |
8 | \r | |
ba1a2d11 | 9 | Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>\r |
a646000f MK |
10 | This program and the accompanying materials\r |
11 | are licensed and made available under the terms and conditions of the BSD License\r | |
12 | which accompanies this distribution. The full text of the license may be found at\r | |
13 | http://opensource.org/licenses/bsd-license.php\r | |
14 | \r | |
15 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
16 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
17 | \r | |
18 | @par Specification Reference:\r | |
ba1a2d11 ED |
19 | Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,\r |
20 | May 2018, Volume 4: Model-Specific-Registers (MSR)\r | |
a646000f MK |
21 | \r |
22 | **/\r | |
23 | \r | |
24 | #ifndef __ATOM_MSR_H__\r | |
25 | #define __ATOM_MSR_H__\r | |
26 | \r | |
27 | #include <Register/ArchitecturalMsr.h>\r | |
28 | \r | |
f4c982bf JF |
29 | /**\r |
30 | Is Intel(R) Atom(TM) Processor Family?\r | |
31 | \r | |
32 | @param DisplayFamily Display Family ID\r | |
33 | @param DisplayModel Display Model ID\r | |
34 | \r | |
35 | @retval TRUE Yes, it is.\r | |
36 | @retval FALSE No, it isn't.\r | |
37 | **/\r | |
38 | #define IS_ATOM_PROCESSOR(DisplayFamily, DisplayModel) \\r | |
39 | (DisplayFamily == 0x06 && \\r | |
40 | ( \\r | |
41 | DisplayModel == 0x1C || \\r | |
42 | DisplayModel == 0x26 || \\r | |
43 | DisplayModel == 0x27 || \\r | |
44 | DisplayModel == 0x35 || \\r | |
45 | DisplayModel == 0x36 \\r | |
46 | ) \\r | |
47 | )\r | |
48 | \r | |
a646000f MK |
49 | /**\r |
50 | Shared. Model Specific Platform ID (R).\r | |
51 | \r | |
52 | @param ECX MSR_ATOM_PLATFORM_ID (0x00000017)\r | |
53 | @param EAX Lower 32-bits of MSR value.\r | |
54 | Described by the type MSR_ATOM_PLATFORM_ID_REGISTER.\r | |
55 | @param EDX Upper 32-bits of MSR value.\r | |
56 | Described by the type MSR_ATOM_PLATFORM_ID_REGISTER.\r | |
57 | \r | |
58 | <b>Example usage</b>\r | |
59 | @code\r | |
60 | MSR_ATOM_PLATFORM_ID_REGISTER Msr;\r | |
61 | \r | |
62 | Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_PLATFORM_ID);\r | |
63 | @endcode\r | |
800a651d | 64 | @note MSR_ATOM_PLATFORM_ID is defined as MSR_PLATFORM_ID in SDM.\r |
a646000f MK |
65 | **/\r |
66 | #define MSR_ATOM_PLATFORM_ID 0x00000017\r | |
67 | \r | |
68 | /**\r | |
69 | MSR information returned for MSR index #MSR_ATOM_PLATFORM_ID\r | |
70 | **/\r | |
71 | typedef union {\r | |
72 | ///\r | |
73 | /// Individual bit fields\r | |
74 | ///\r | |
75 | struct {\r | |
76 | UINT32 Reserved1:8;\r | |
77 | ///\r | |
78 | /// [Bits 12:8] Maximum Qualified Ratio (R) The maximum allowed bus ratio.\r | |
79 | ///\r | |
80 | UINT32 MaximumQualifiedRatio:5;\r | |
81 | UINT32 Reserved2:19;\r | |
82 | UINT32 Reserved3:32;\r | |
83 | } Bits;\r | |
84 | ///\r | |
85 | /// All bit fields as a 32-bit value\r | |
86 | ///\r | |
87 | UINT32 Uint32;\r | |
88 | ///\r | |
89 | /// All bit fields as a 64-bit value\r | |
90 | ///\r | |
91 | UINT64 Uint64;\r | |
92 | } MSR_ATOM_PLATFORM_ID_REGISTER;\r | |
93 | \r | |
94 | \r | |
95 | /**\r | |
96 | Shared. Processor Hard Power-On Configuration (R/W) Enables and disables\r | |
97 | processor features; (R) indicates current processor configuration.\r | |
98 | \r | |
99 | @param ECX MSR_ATOM_EBL_CR_POWERON (0x0000002A)\r | |
100 | @param EAX Lower 32-bits of MSR value.\r | |
101 | Described by the type MSR_ATOM_EBL_CR_POWERON_REGISTER.\r | |
102 | @param EDX Upper 32-bits of MSR value.\r | |
103 | Described by the type MSR_ATOM_EBL_CR_POWERON_REGISTER.\r | |
104 | \r | |
105 | <b>Example usage</b>\r | |
106 | @code\r | |
107 | MSR_ATOM_EBL_CR_POWERON_REGISTER Msr;\r | |
108 | \r | |
109 | Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_EBL_CR_POWERON);\r | |
110 | AsmWriteMsr64 (MSR_ATOM_EBL_CR_POWERON, Msr.Uint64);\r | |
111 | @endcode\r | |
800a651d | 112 | @note MSR_ATOM_EBL_CR_POWERON is defined as MSR_EBL_CR_POWERON in SDM.\r |
a646000f MK |
113 | **/\r |
114 | #define MSR_ATOM_EBL_CR_POWERON 0x0000002A\r | |
115 | \r | |
116 | /**\r | |
117 | MSR information returned for MSR index #MSR_ATOM_EBL_CR_POWERON\r | |
118 | **/\r | |
119 | typedef union {\r | |
120 | ///\r | |
121 | /// Individual bit fields\r | |
122 | ///\r | |
123 | struct {\r | |
124 | UINT32 Reserved1:1;\r | |
125 | ///\r | |
126 | /// [Bit 1] Data Error Checking Enable (R/W) 1 = Enabled; 0 = Disabled\r | |
127 | /// Always 0.\r | |
128 | ///\r | |
129 | UINT32 DataErrorCheckingEnable:1;\r | |
130 | ///\r | |
131 | /// [Bit 2] Response Error Checking Enable (R/W) 1 = Enabled; 0 = Disabled\r | |
132 | /// Always 0.\r | |
133 | ///\r | |
134 | UINT32 ResponseErrorCheckingEnable:1;\r | |
135 | ///\r | |
136 | /// [Bit 3] AERR# Drive Enable (R/W) 1 = Enabled; 0 = Disabled Always 0.\r | |
137 | ///\r | |
138 | UINT32 AERR_DriveEnable:1;\r | |
139 | ///\r | |
140 | /// [Bit 4] BERR# Enable for initiator bus requests (R/W) 1 = Enabled; 0 =\r | |
141 | /// Disabled Always 0.\r | |
142 | ///\r | |
143 | UINT32 BERR_Enable:1;\r | |
144 | UINT32 Reserved2:1;\r | |
145 | UINT32 Reserved3:1;\r | |
146 | ///\r | |
147 | /// [Bit 7] BINIT# Driver Enable (R/W) 1 = Enabled; 0 = Disabled Always 0.\r | |
148 | ///\r | |
149 | UINT32 BINIT_DriverEnable:1;\r | |
150 | UINT32 Reserved4:1;\r | |
151 | ///\r | |
152 | /// [Bit 9] Execute BIST (R/O) 1 = Enabled; 0 = Disabled.\r | |
153 | ///\r | |
154 | UINT32 ExecuteBIST:1;\r | |
155 | ///\r | |
156 | /// [Bit 10] AERR# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled\r | |
157 | /// Always 0.\r | |
158 | ///\r | |
159 | UINT32 AERR_ObservationEnabled:1;\r | |
160 | UINT32 Reserved5:1;\r | |
161 | ///\r | |
162 | /// [Bit 12] BINIT# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled\r | |
163 | /// Always 0.\r | |
164 | ///\r | |
165 | UINT32 BINIT_ObservationEnabled:1;\r | |
166 | UINT32 Reserved6:1;\r | |
167 | ///\r | |
168 | /// [Bit 14] 1 MByte Power on Reset Vector (R/O) 1 = 1 MByte; 0 = 4 GBytes.\r | |
169 | ///\r | |
170 | UINT32 ResetVector:1;\r | |
171 | UINT32 Reserved7:1;\r | |
172 | ///\r | |
173 | /// [Bits 17:16] APIC Cluster ID (R/O) Always 00B.\r | |
174 | ///\r | |
175 | UINT32 APICClusterID:2;\r | |
176 | UINT32 Reserved8:2;\r | |
177 | ///\r | |
178 | /// [Bits 21:20] Symmetric Arbitration ID (R/O) Always 00B.\r | |
179 | ///\r | |
180 | UINT32 SymmetricArbitrationID:2;\r | |
181 | ///\r | |
182 | /// [Bits 26:22] Integer Bus Frequency Ratio (R/O).\r | |
183 | ///\r | |
184 | UINT32 IntegerBusFrequencyRatio:5;\r | |
185 | UINT32 Reserved9:5;\r | |
186 | UINT32 Reserved10:32;\r | |
187 | } Bits;\r | |
188 | ///\r | |
189 | /// All bit fields as a 32-bit value\r | |
190 | ///\r | |
191 | UINT32 Uint32;\r | |
192 | ///\r | |
193 | /// All bit fields as a 64-bit value\r | |
194 | ///\r | |
195 | UINT64 Uint64;\r | |
196 | } MSR_ATOM_EBL_CR_POWERON_REGISTER;\r | |
197 | \r | |
198 | \r | |
199 | /**\r | |
0f16be6d HW |
200 | Unique. Last Branch Record n From IP (R/W) One of eight pairs of last branch\r |
201 | record registers on the last branch record stack. The From_IP part of the\r | |
202 | stack contains pointers to the source instruction . See also: - Last Branch\r | |
203 | Record Stack TOS at 1C9H - Section 17.5.\r | |
a646000f MK |
204 | \r |
205 | @param ECX MSR_ATOM_LASTBRANCH_n_FROM_IP\r | |
206 | @param EAX Lower 32-bits of MSR value.\r | |
207 | @param EDX Upper 32-bits of MSR value.\r | |
208 | \r | |
209 | <b>Example usage</b>\r | |
210 | @code\r | |
211 | UINT64 Msr;\r | |
212 | \r | |
213 | Msr = AsmReadMsr64 (MSR_ATOM_LASTBRANCH_0_FROM_IP);\r | |
214 | AsmWriteMsr64 (MSR_ATOM_LASTBRANCH_0_FROM_IP, Msr);\r | |
215 | @endcode\r | |
800a651d JF |
216 | @note MSR_ATOM_LASTBRANCH_0_FROM_IP is defined as MSR_LASTBRANCH_0_FROM_IP in SDM.\r |
217 | MSR_ATOM_LASTBRANCH_1_FROM_IP is defined as MSR_LASTBRANCH_1_FROM_IP in SDM.\r | |
218 | MSR_ATOM_LASTBRANCH_2_FROM_IP is defined as MSR_LASTBRANCH_2_FROM_IP in SDM.\r | |
219 | MSR_ATOM_LASTBRANCH_3_FROM_IP is defined as MSR_LASTBRANCH_3_FROM_IP in SDM.\r | |
220 | MSR_ATOM_LASTBRANCH_4_FROM_IP is defined as MSR_LASTBRANCH_4_FROM_IP in SDM.\r | |
221 | MSR_ATOM_LASTBRANCH_5_FROM_IP is defined as MSR_LASTBRANCH_5_FROM_IP in SDM.\r | |
222 | MSR_ATOM_LASTBRANCH_6_FROM_IP is defined as MSR_LASTBRANCH_6_FROM_IP in SDM.\r | |
223 | MSR_ATOM_LASTBRANCH_7_FROM_IP is defined as MSR_LASTBRANCH_7_FROM_IP in SDM.\r | |
a646000f MK |
224 | @{\r |
225 | **/\r | |
226 | #define MSR_ATOM_LASTBRANCH_0_FROM_IP 0x00000040\r | |
227 | #define MSR_ATOM_LASTBRANCH_1_FROM_IP 0x00000041\r | |
228 | #define MSR_ATOM_LASTBRANCH_2_FROM_IP 0x00000042\r | |
229 | #define MSR_ATOM_LASTBRANCH_3_FROM_IP 0x00000043\r | |
230 | #define MSR_ATOM_LASTBRANCH_4_FROM_IP 0x00000044\r | |
231 | #define MSR_ATOM_LASTBRANCH_5_FROM_IP 0x00000045\r | |
232 | #define MSR_ATOM_LASTBRANCH_6_FROM_IP 0x00000046\r | |
233 | #define MSR_ATOM_LASTBRANCH_7_FROM_IP 0x00000047\r | |
234 | /// @}\r | |
235 | \r | |
236 | \r | |
237 | /**\r | |
0f16be6d HW |
238 | Unique. Last Branch Record n To IP (R/W) One of eight pairs of last branch\r |
239 | record registers on the last branch record stack. The To_IP part of the\r | |
240 | stack contains pointers to the destination instruction.\r | |
a646000f MK |
241 | \r |
242 | @param ECX MSR_ATOM_LASTBRANCH_n_TO_IP\r | |
243 | @param EAX Lower 32-bits of MSR value.\r | |
244 | @param EDX Upper 32-bits of MSR value.\r | |
245 | \r | |
246 | <b>Example usage</b>\r | |
247 | @code\r | |
248 | UINT64 Msr;\r | |
249 | \r | |
250 | Msr = AsmReadMsr64 (MSR_ATOM_LASTBRANCH_0_TO_IP);\r | |
251 | AsmWriteMsr64 (MSR_ATOM_LASTBRANCH_0_TO_IP, Msr);\r | |
252 | @endcode\r | |
800a651d JF |
253 | @note MSR_ATOM_LASTBRANCH_0_TO_IP is defined as MSR_LASTBRANCH_0_TO_IP in SDM.\r |
254 | MSR_ATOM_LASTBRANCH_1_TO_IP is defined as MSR_LASTBRANCH_1_TO_IP in SDM.\r | |
255 | MSR_ATOM_LASTBRANCH_2_TO_IP is defined as MSR_LASTBRANCH_2_TO_IP in SDM.\r | |
256 | MSR_ATOM_LASTBRANCH_3_TO_IP is defined as MSR_LASTBRANCH_3_TO_IP in SDM.\r | |
257 | MSR_ATOM_LASTBRANCH_4_TO_IP is defined as MSR_LASTBRANCH_4_TO_IP in SDM.\r | |
258 | MSR_ATOM_LASTBRANCH_5_TO_IP is defined as MSR_LASTBRANCH_5_TO_IP in SDM.\r | |
259 | MSR_ATOM_LASTBRANCH_6_TO_IP is defined as MSR_LASTBRANCH_6_TO_IP in SDM.\r | |
260 | MSR_ATOM_LASTBRANCH_7_TO_IP is defined as MSR_LASTBRANCH_7_TO_IP in SDM.\r | |
a646000f MK |
261 | @{\r |
262 | **/\r | |
263 | #define MSR_ATOM_LASTBRANCH_0_TO_IP 0x00000060\r | |
264 | #define MSR_ATOM_LASTBRANCH_1_TO_IP 0x00000061\r | |
265 | #define MSR_ATOM_LASTBRANCH_2_TO_IP 0x00000062\r | |
266 | #define MSR_ATOM_LASTBRANCH_3_TO_IP 0x00000063\r | |
267 | #define MSR_ATOM_LASTBRANCH_4_TO_IP 0x00000064\r | |
268 | #define MSR_ATOM_LASTBRANCH_5_TO_IP 0x00000065\r | |
269 | #define MSR_ATOM_LASTBRANCH_6_TO_IP 0x00000066\r | |
270 | #define MSR_ATOM_LASTBRANCH_7_TO_IP 0x00000067\r | |
271 | /// @}\r | |
272 | \r | |
273 | \r | |
274 | /**\r | |
275 | Shared. Scalable Bus Speed(RO) This field indicates the intended scalable\r | |
276 | bus clock speed for processors based on Intel Atom microarchitecture:.\r | |
277 | \r | |
278 | @param ECX MSR_ATOM_FSB_FREQ (0x000000CD)\r | |
279 | @param EAX Lower 32-bits of MSR value.\r | |
280 | Described by the type MSR_ATOM_FSB_FREQ_REGISTER.\r | |
281 | @param EDX Upper 32-bits of MSR value.\r | |
282 | Described by the type MSR_ATOM_FSB_FREQ_REGISTER.\r | |
283 | \r | |
284 | <b>Example usage</b>\r | |
285 | @code\r | |
286 | MSR_ATOM_FSB_FREQ_REGISTER Msr;\r | |
287 | \r | |
288 | Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_FSB_FREQ);\r | |
289 | @endcode\r | |
800a651d | 290 | @note MSR_ATOM_FSB_FREQ is defined as MSR_FSB_FREQ in SDM.\r |
a646000f MK |
291 | **/\r |
292 | #define MSR_ATOM_FSB_FREQ 0x000000CD\r | |
293 | \r | |
294 | /**\r | |
295 | MSR information returned for MSR index #MSR_ATOM_FSB_FREQ\r | |
296 | **/\r | |
297 | typedef union {\r | |
298 | ///\r | |
299 | /// Individual bit fields\r | |
300 | ///\r | |
301 | struct {\r | |
302 | ///\r | |
303 | /// [Bits 2:0] - Scalable Bus Speed\r | |
304 | ///\r | |
305 | /// Atom Processor Family\r | |
306 | /// ---------------------\r | |
307 | /// 111B: 083 MHz (FSB 333)\r | |
308 | /// 101B: 100 MHz (FSB 400)\r | |
309 | /// 001B: 133 MHz (FSB 533)\r | |
310 | /// 011B: 167 MHz (FSB 667)\r | |
311 | ///\r | |
312 | /// 133.33 MHz should be utilized if performing calculation with\r | |
313 | /// System Bus Speed when encoding is 001B.\r | |
314 | /// 166.67 MHz should be utilized if performing calculation with\r | |
315 | /// System Bus Speed when\r | |
316 | /// encoding is 011B.\r | |
317 | ///\r | |
318 | UINT32 ScalableBusSpeed:3;\r | |
319 | UINT32 Reserved1:29;\r | |
320 | UINT32 Reserved2:32;\r | |
321 | } Bits;\r | |
322 | ///\r | |
323 | /// All bit fields as a 32-bit value\r | |
324 | ///\r | |
325 | UINT32 Uint32;\r | |
326 | ///\r | |
327 | /// All bit fields as a 64-bit value\r | |
328 | ///\r | |
329 | UINT64 Uint64;\r | |
330 | } MSR_ATOM_FSB_FREQ_REGISTER;\r | |
331 | \r | |
332 | \r | |
333 | /**\r | |
334 | Shared.\r | |
335 | \r | |
336 | @param ECX MSR_ATOM_BBL_CR_CTL3 (0x0000011E)\r | |
337 | @param EAX Lower 32-bits of MSR value.\r | |
338 | Described by the type MSR_ATOM_BBL_CR_CTL3_REGISTER.\r | |
339 | @param EDX Upper 32-bits of MSR value.\r | |
340 | Described by the type MSR_ATOM_BBL_CR_CTL3_REGISTER.\r | |
341 | \r | |
342 | <b>Example usage</b>\r | |
343 | @code\r | |
344 | MSR_ATOM_BBL_CR_CTL3_REGISTER Msr;\r | |
345 | \r | |
346 | Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_BBL_CR_CTL3);\r | |
347 | AsmWriteMsr64 (MSR_ATOM_BBL_CR_CTL3, Msr.Uint64);\r | |
348 | @endcode\r | |
800a651d | 349 | @note MSR_ATOM_BBL_CR_CTL3 is defined as MSR_BBL_CR_CTL3 in SDM.\r |
a646000f MK |
350 | **/\r |
351 | #define MSR_ATOM_BBL_CR_CTL3 0x0000011E\r | |
352 | \r | |
353 | /**\r | |
354 | MSR information returned for MSR index #MSR_ATOM_BBL_CR_CTL3\r | |
355 | **/\r | |
356 | typedef union {\r | |
357 | ///\r | |
358 | /// Individual bit fields\r | |
359 | ///\r | |
360 | struct {\r | |
361 | ///\r | |
362 | /// [Bit 0] L2 Hardware Enabled (RO) 1 = If the L2 is hardware-enabled 0 =\r | |
363 | /// Indicates if the L2 is hardware-disabled.\r | |
364 | ///\r | |
365 | UINT32 L2HardwareEnabled:1;\r | |
366 | UINT32 Reserved1:7;\r | |
367 | ///\r | |
368 | /// [Bit 8] L2 Enabled. (R/W) 1 = L2 cache has been initialized 0 =\r | |
369 | /// Disabled (default) Until this bit is set the processor will not\r | |
370 | /// respond to the WBINVD instruction or the assertion of the FLUSH# input.\r | |
371 | ///\r | |
372 | UINT32 L2Enabled:1;\r | |
373 | UINT32 Reserved2:14;\r | |
374 | ///\r | |
375 | /// [Bit 23] L2 Not Present (RO) 1. = L2 Present 2. = L2 Not Present.\r | |
376 | ///\r | |
377 | UINT32 L2NotPresent:1;\r | |
378 | UINT32 Reserved3:8;\r | |
379 | UINT32 Reserved4:32;\r | |
380 | } Bits;\r | |
381 | ///\r | |
382 | /// All bit fields as a 32-bit value\r | |
383 | ///\r | |
384 | UINT32 Uint32;\r | |
385 | ///\r | |
386 | /// All bit fields as a 64-bit value\r | |
387 | ///\r | |
388 | UINT64 Uint64;\r | |
389 | } MSR_ATOM_BBL_CR_CTL3_REGISTER;\r | |
390 | \r | |
391 | \r | |
392 | /**\r | |
393 | Shared.\r | |
394 | \r | |
395 | @param ECX MSR_ATOM_PERF_STATUS (0x00000198)\r | |
396 | @param EAX Lower 32-bits of MSR value.\r | |
397 | Described by the type MSR_ATOM_PERF_STATUS_REGISTER.\r | |
398 | @param EDX Upper 32-bits of MSR value.\r | |
399 | Described by the type MSR_ATOM_PERF_STATUS_REGISTER.\r | |
400 | \r | |
401 | <b>Example usage</b>\r | |
402 | @code\r | |
403 | MSR_ATOM_PERF_STATUS_REGISTER Msr;\r | |
404 | \r | |
405 | Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_PERF_STATUS);\r | |
406 | AsmWriteMsr64 (MSR_ATOM_PERF_STATUS, Msr.Uint64);\r | |
407 | @endcode\r | |
800a651d | 408 | @note MSR_ATOM_PERF_STATUS is defined as MSR_PERF_STATUS in SDM.\r |
a646000f MK |
409 | **/\r |
410 | #define MSR_ATOM_PERF_STATUS 0x00000198\r | |
411 | \r | |
412 | /**\r | |
413 | MSR information returned for MSR index #MSR_ATOM_PERF_STATUS\r | |
414 | **/\r | |
415 | typedef union {\r | |
416 | ///\r | |
417 | /// Individual bit fields\r | |
418 | ///\r | |
419 | struct {\r | |
420 | ///\r | |
421 | /// [Bits 15:0] Current Performance State Value.\r | |
422 | ///\r | |
423 | UINT32 CurrentPerformanceStateValue:16;\r | |
424 | UINT32 Reserved1:16;\r | |
425 | UINT32 Reserved2:8;\r | |
426 | ///\r | |
427 | /// [Bits 44:40] Maximum Bus Ratio (R/O) Indicates maximum bus ratio\r | |
428 | /// configured for the processor.\r | |
429 | ///\r | |
430 | UINT32 MaximumBusRatio:5;\r | |
431 | UINT32 Reserved3:19;\r | |
432 | } Bits;\r | |
433 | ///\r | |
434 | /// All bit fields as a 64-bit value\r | |
435 | ///\r | |
436 | UINT64 Uint64;\r | |
437 | } MSR_ATOM_PERF_STATUS_REGISTER;\r | |
438 | \r | |
439 | \r | |
440 | /**\r | |
441 | Shared.\r | |
442 | \r | |
443 | @param ECX MSR_ATOM_THERM2_CTL (0x0000019D)\r | |
444 | @param EAX Lower 32-bits of MSR value.\r | |
445 | Described by the type MSR_ATOM_THERM2_CTL_REGISTER.\r | |
446 | @param EDX Upper 32-bits of MSR value.\r | |
447 | Described by the type MSR_ATOM_THERM2_CTL_REGISTER.\r | |
448 | \r | |
449 | <b>Example usage</b>\r | |
450 | @code\r | |
451 | MSR_ATOM_THERM2_CTL_REGISTER Msr;\r | |
452 | \r | |
453 | Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_THERM2_CTL);\r | |
454 | AsmWriteMsr64 (MSR_ATOM_THERM2_CTL, Msr.Uint64);\r | |
455 | @endcode\r | |
800a651d | 456 | @note MSR_ATOM_THERM2_CTL is defined as MSR_THERM2_CTL in SDM.\r |
a646000f MK |
457 | **/\r |
458 | #define MSR_ATOM_THERM2_CTL 0x0000019D\r | |
459 | \r | |
460 | /**\r | |
461 | MSR information returned for MSR index #MSR_ATOM_THERM2_CTL\r | |
462 | **/\r | |
463 | typedef union {\r | |
464 | ///\r | |
465 | /// Individual bit fields\r | |
466 | ///\r | |
467 | struct {\r | |
468 | UINT32 Reserved1:16;\r | |
469 | ///\r | |
470 | /// [Bit 16] TM_SELECT (R/W) Mode of automatic thermal monitor: 1. =\r | |
471 | /// Thermal Monitor 1 (thermally-initiated on-die modulation of the\r | |
472 | /// stop-clock duty cycle) 2. = Thermal Monitor 2 (thermally-initiated\r | |
473 | /// frequency transitions) If bit 3 of the IA32_MISC_ENABLE register is\r | |
474 | /// cleared, TM_SELECT has no effect. Neither TM1 nor TM2 are enabled.\r | |
475 | ///\r | |
476 | UINT32 TM_SELECT:1;\r | |
477 | UINT32 Reserved2:15;\r | |
478 | UINT32 Reserved3:32;\r | |
479 | } Bits;\r | |
480 | ///\r | |
481 | /// All bit fields as a 32-bit value\r | |
482 | ///\r | |
483 | UINT32 Uint32;\r | |
484 | ///\r | |
485 | /// All bit fields as a 64-bit value\r | |
486 | ///\r | |
487 | UINT64 Uint64;\r | |
488 | } MSR_ATOM_THERM2_CTL_REGISTER;\r | |
489 | \r | |
490 | \r | |
491 | /**\r | |
492 | Unique. Enable Misc. Processor Features (R/W) Allows a variety of processor\r | |
493 | functions to be enabled and disabled.\r | |
494 | \r | |
495 | @param ECX MSR_ATOM_IA32_MISC_ENABLE (0x000001A0)\r | |
496 | @param EAX Lower 32-bits of MSR value.\r | |
497 | Described by the type MSR_ATOM_IA32_MISC_ENABLE_REGISTER.\r | |
498 | @param EDX Upper 32-bits of MSR value.\r | |
499 | Described by the type MSR_ATOM_IA32_MISC_ENABLE_REGISTER.\r | |
500 | \r | |
501 | <b>Example usage</b>\r | |
502 | @code\r | |
503 | MSR_ATOM_IA32_MISC_ENABLE_REGISTER Msr;\r | |
504 | \r | |
505 | Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_IA32_MISC_ENABLE);\r | |
506 | AsmWriteMsr64 (MSR_ATOM_IA32_MISC_ENABLE, Msr.Uint64);\r | |
507 | @endcode\r | |
800a651d | 508 | @note MSR_ATOM_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.\r |
a646000f MK |
509 | **/\r |
510 | #define MSR_ATOM_IA32_MISC_ENABLE 0x000001A0\r | |
511 | \r | |
512 | /**\r | |
513 | MSR information returned for MSR index #MSR_ATOM_IA32_MISC_ENABLE\r | |
514 | **/\r | |
515 | typedef union {\r | |
516 | ///\r | |
517 | /// Individual bit fields\r | |
518 | ///\r | |
519 | struct {\r | |
520 | ///\r | |
ba1a2d11 | 521 | /// [Bit 0] Fast-Strings Enable See Table 2-2.\r |
a646000f MK |
522 | ///\r |
523 | UINT32 FastStrings:1;\r | |
524 | UINT32 Reserved1:2;\r | |
525 | ///\r | |
526 | /// [Bit 3] Unique. Automatic Thermal Control Circuit Enable (R/W) See\r | |
ba1a2d11 | 527 | /// Table 2-2. Default value is 0.\r |
a646000f MK |
528 | ///\r |
529 | UINT32 AutomaticThermalControlCircuit:1;\r | |
530 | UINT32 Reserved2:3;\r | |
531 | ///\r | |
ba1a2d11 | 532 | /// [Bit 7] Shared. Performance Monitoring Available (R) See Table 2-2.\r |
a646000f MK |
533 | ///\r |
534 | UINT32 PerformanceMonitoring:1;\r | |
535 | UINT32 Reserved3:1;\r | |
536 | UINT32 Reserved4:1;\r | |
537 | ///\r | |
538 | /// [Bit 10] Shared. FERR# Multiplexing Enable (R/W) 1 = FERR# asserted by\r | |
539 | /// the processor to indicate a pending break event within the processor 0\r | |
540 | /// = Indicates compatible FERR# signaling behavior This bit must be set\r | |
541 | /// to 1 to support XAPIC interrupt model usage.\r | |
542 | ///\r | |
543 | UINT32 FERR:1;\r | |
544 | ///\r | |
ba1a2d11 | 545 | /// [Bit 11] Shared. Branch Trace Storage Unavailable (RO) See Table 2-2.\r |
a646000f MK |
546 | ///\r |
547 | UINT32 BTS:1;\r | |
548 | ///\r | |
0f16be6d | 549 | /// [Bit 12] Shared. Processor Event Based Sampling Unavailable (RO) See\r |
ba1a2d11 | 550 | /// Table 2-2.\r |
a646000f MK |
551 | ///\r |
552 | UINT32 PEBS:1;\r | |
553 | ///\r | |
554 | /// [Bit 13] Shared. TM2 Enable (R/W) When this bit is set (1) and the\r | |
555 | /// thermal sensor indicates that the die temperature is at the\r | |
556 | /// pre-determined threshold, the Thermal Monitor 2 mechanism is engaged.\r | |
557 | /// TM2 will reduce the bus to core ratio and voltage according to the\r | |
558 | /// value last written to MSR_THERM2_CTL bits 15:0.\r | |
559 | /// When this bit is clear (0, default), the processor does not change\r | |
560 | /// the VID signals or the bus to core ratio when the processor enters a\r | |
561 | /// thermally managed state. The BIOS must enable this feature if the\r | |
562 | /// TM2 feature flag (CPUID.1:ECX[8]) is set; if the TM2 feature flag is\r | |
563 | /// not set, this feature is not supported and BIOS must not alter the\r | |
564 | /// contents of the TM2 bit location. The processor is operating out of\r | |
565 | /// specification if both this bit and the TM1 bit are set to 0.\r | |
566 | ///\r | |
567 | UINT32 TM2:1;\r | |
568 | UINT32 Reserved5:2;\r | |
569 | ///\r | |
570 | /// [Bit 16] Shared. Enhanced Intel SpeedStep Technology Enable (R/W) See\r | |
ba1a2d11 | 571 | /// Table 2-2.\r |
a646000f MK |
572 | ///\r |
573 | UINT32 EIST:1;\r | |
574 | UINT32 Reserved6:1;\r | |
575 | ///\r | |
ba1a2d11 | 576 | /// [Bit 18] Shared. ENABLE MONITOR FSM (R/W) See Table 2-2.\r |
a646000f MK |
577 | ///\r |
578 | UINT32 MONITOR:1;\r | |
579 | UINT32 Reserved7:1;\r | |
580 | ///\r | |
581 | /// [Bit 20] Shared. Enhanced Intel SpeedStep Technology Select Lock\r | |
582 | /// (R/WO) When set, this bit causes the following bits to become\r | |
583 | /// read-only: - Enhanced Intel SpeedStep Technology Select Lock (this\r | |
584 | /// bit), - Enhanced Intel SpeedStep Technology Enable bit. The bit must\r | |
585 | /// be set before an Enhanced Intel SpeedStep Technology transition is\r | |
586 | /// requested. This bit is cleared on reset.\r | |
587 | ///\r | |
588 | UINT32 EISTLock:1;\r | |
589 | UINT32 Reserved8:1;\r | |
590 | ///\r | |
ba1a2d11 | 591 | /// [Bit 22] Unique. Limit CPUID Maxval (R/W) See Table 2-2.\r |
a646000f MK |
592 | ///\r |
593 | UINT32 LimitCpuidMaxval:1;\r | |
594 | ///\r | |
ba1a2d11 | 595 | /// [Bit 23] Shared. xTPR Message Disable (R/W) See Table 2-2.\r |
a646000f MK |
596 | ///\r |
597 | UINT32 xTPR_Message_Disable:1;\r | |
598 | UINT32 Reserved9:8;\r | |
599 | UINT32 Reserved10:2;\r | |
600 | ///\r | |
ba1a2d11 | 601 | /// [Bit 34] Unique. XD Bit Disable (R/W) See Table 2-2.\r |
a646000f MK |
602 | ///\r |
603 | UINT32 XD:1;\r | |
604 | UINT32 Reserved11:29;\r | |
605 | } Bits;\r | |
606 | ///\r | |
607 | /// All bit fields as a 64-bit value\r | |
608 | ///\r | |
609 | UINT64 Uint64;\r | |
610 | } MSR_ATOM_IA32_MISC_ENABLE_REGISTER;\r | |
611 | \r | |
612 | \r | |
613 | /**\r | |
614 | Unique. Last Branch Record Stack TOS (R/W) Contains an index (bits 0-2)\r | |
615 | that points to the MSR containing the most recent branch record. See\r | |
616 | MSR_LASTBRANCH_0_FROM_IP (at 40H).\r | |
617 | \r | |
618 | @param ECX MSR_ATOM_LASTBRANCH_TOS (0x000001C9)\r | |
619 | @param EAX Lower 32-bits of MSR value.\r | |
620 | @param EDX Upper 32-bits of MSR value.\r | |
621 | \r | |
622 | <b>Example usage</b>\r | |
623 | @code\r | |
624 | UINT64 Msr;\r | |
625 | \r | |
626 | Msr = AsmReadMsr64 (MSR_ATOM_LASTBRANCH_TOS);\r | |
627 | AsmWriteMsr64 (MSR_ATOM_LASTBRANCH_TOS, Msr);\r | |
628 | @endcode\r | |
800a651d | 629 | @note MSR_ATOM_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.\r |
a646000f MK |
630 | **/\r |
631 | #define MSR_ATOM_LASTBRANCH_TOS 0x000001C9\r | |
632 | \r | |
633 | \r | |
634 | /**\r | |
635 | Unique. Last Exception Record From Linear IP (R) Contains a pointer to the\r | |
636 | last branch instruction that the processor executed prior to the last\r | |
637 | exception that was generated or the last interrupt that was handled.\r | |
638 | \r | |
639 | @param ECX MSR_ATOM_LER_FROM_LIP (0x000001DD)\r | |
640 | @param EAX Lower 32-bits of MSR value.\r | |
641 | @param EDX Upper 32-bits of MSR value.\r | |
642 | \r | |
643 | <b>Example usage</b>\r | |
644 | @code\r | |
645 | UINT64 Msr;\r | |
646 | \r | |
647 | Msr = AsmReadMsr64 (MSR_ATOM_LER_FROM_LIP);\r | |
648 | @endcode\r | |
800a651d | 649 | @note MSR_ATOM_LER_FROM_LIP is defined as MSR_LER_FROM_LIP in SDM.\r |
a646000f MK |
650 | **/\r |
651 | #define MSR_ATOM_LER_FROM_LIP 0x000001DD\r | |
652 | \r | |
653 | \r | |
654 | /**\r | |
655 | Unique. Last Exception Record To Linear IP (R) This area contains a pointer\r | |
656 | to the target of the last branch instruction that the processor executed\r | |
657 | prior to the last exception that was generated or the last interrupt that\r | |
658 | was handled.\r | |
659 | \r | |
660 | @param ECX MSR_ATOM_LER_TO_LIP (0x000001DE)\r | |
661 | @param EAX Lower 32-bits of MSR value.\r | |
662 | @param EDX Upper 32-bits of MSR value.\r | |
663 | \r | |
664 | <b>Example usage</b>\r | |
665 | @code\r | |
666 | UINT64 Msr;\r | |
667 | \r | |
668 | Msr = AsmReadMsr64 (MSR_ATOM_LER_TO_LIP);\r | |
669 | @endcode\r | |
800a651d | 670 | @note MSR_ATOM_LER_TO_LIP is defined as MSR_LER_TO_LIP in SDM.\r |
a646000f MK |
671 | **/\r |
672 | #define MSR_ATOM_LER_TO_LIP 0x000001DE\r | |
673 | \r | |
674 | \r | |
675 | /**\r | |
ba1a2d11 | 676 | Unique. See Table 2-2. See Section 18.6.2.4, "Processor Event Based Sampling\r |
a646000f MK |
677 | (PEBS).".\r |
678 | \r | |
679 | @param ECX MSR_ATOM_PEBS_ENABLE (0x000003F1)\r | |
680 | @param EAX Lower 32-bits of MSR value.\r | |
681 | Described by the type MSR_ATOM_PEBS_ENABLE_REGISTER.\r | |
682 | @param EDX Upper 32-bits of MSR value.\r | |
683 | Described by the type MSR_ATOM_PEBS_ENABLE_REGISTER.\r | |
684 | \r | |
685 | <b>Example usage</b>\r | |
686 | @code\r | |
687 | MSR_ATOM_PEBS_ENABLE_REGISTER Msr;\r | |
688 | \r | |
689 | Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_PEBS_ENABLE);\r | |
690 | AsmWriteMsr64 (MSR_ATOM_PEBS_ENABLE, Msr.Uint64);\r | |
691 | @endcode\r | |
800a651d | 692 | @note MSR_ATOM_PEBS_ENABLE is defined as MSR_PEBS_ENABLE in SDM.\r |
a646000f MK |
693 | **/\r |
694 | #define MSR_ATOM_PEBS_ENABLE 0x000003F1\r | |
695 | \r | |
696 | /**\r | |
697 | MSR information returned for MSR index #MSR_ATOM_PEBS_ENABLE\r | |
698 | **/\r | |
699 | typedef union {\r | |
700 | ///\r | |
701 | /// Individual bit fields\r | |
702 | ///\r | |
703 | struct {\r | |
704 | ///\r | |
705 | /// [Bit 0] Enable PEBS on IA32_PMC0. (R/W).\r | |
706 | ///\r | |
707 | UINT32 Enable:1;\r | |
708 | UINT32 Reserved1:31;\r | |
709 | UINT32 Reserved2:32;\r | |
710 | } Bits;\r | |
711 | ///\r | |
712 | /// All bit fields as a 32-bit value\r | |
713 | ///\r | |
714 | UINT32 Uint32;\r | |
715 | ///\r | |
716 | /// All bit fields as a 64-bit value\r | |
717 | ///\r | |
718 | UINT64 Uint64;\r | |
719 | } MSR_ATOM_PEBS_ENABLE_REGISTER;\r | |
720 | \r | |
721 | \r | |
a646000f MK |
722 | /**\r |
723 | Package. Package C2 Residency Note: C-state values are processor specific\r | |
724 | C-state code names, unrelated to MWAIT extension C-state parameters or ACPI\r | |
725 | C-States. Package. Package C2 Residency Counter. (R/O) Time that this\r | |
726 | package is in processor-specific C2 states since last reset. Counts at 1 Mhz\r | |
727 | frequency.\r | |
728 | \r | |
729 | @param ECX MSR_ATOM_PKG_C2_RESIDENCY (0x000003F8)\r | |
730 | @param EAX Lower 32-bits of MSR value.\r | |
731 | @param EDX Upper 32-bits of MSR value.\r | |
732 | \r | |
733 | <b>Example usage</b>\r | |
734 | @code\r | |
735 | UINT64 Msr;\r | |
736 | \r | |
737 | Msr = AsmReadMsr64 (MSR_ATOM_PKG_C2_RESIDENCY);\r | |
738 | AsmWriteMsr64 (MSR_ATOM_PKG_C2_RESIDENCY, Msr);\r | |
739 | @endcode\r | |
800a651d | 740 | @note MSR_ATOM_PKG_C2_RESIDENCY is defined as MSR_PKG_C2_RESIDENCY in SDM.\r |
a646000f MK |
741 | **/\r |
742 | #define MSR_ATOM_PKG_C2_RESIDENCY 0x000003F8\r | |
743 | \r | |
744 | \r | |
745 | /**\r | |
746 | Package. Package C4 Residency Note: C-state values are processor specific\r | |
747 | C-state code names, unrelated to MWAIT extension C-state parameters or ACPI\r | |
748 | C-States. Package. Package C4 Residency Counter. (R/O) Time that this\r | |
749 | package is in processor-specific C4 states since last reset. Counts at 1 Mhz\r | |
750 | frequency.\r | |
751 | \r | |
752 | @param ECX MSR_ATOM_PKG_C4_RESIDENCY (0x000003F9)\r | |
753 | @param EAX Lower 32-bits of MSR value.\r | |
754 | @param EDX Upper 32-bits of MSR value.\r | |
755 | \r | |
756 | <b>Example usage</b>\r | |
757 | @code\r | |
758 | UINT64 Msr;\r | |
759 | \r | |
760 | Msr = AsmReadMsr64 (MSR_ATOM_PKG_C4_RESIDENCY);\r | |
761 | AsmWriteMsr64 (MSR_ATOM_PKG_C4_RESIDENCY, Msr);\r | |
762 | @endcode\r | |
800a651d | 763 | @note MSR_ATOM_PKG_C4_RESIDENCY is defined as MSR_PKG_C4_RESIDENCY in SDM.\r |
a646000f MK |
764 | **/\r |
765 | #define MSR_ATOM_PKG_C4_RESIDENCY 0x000003F9\r | |
766 | \r | |
767 | \r | |
768 | /**\r | |
769 | Package. Package C6 Residency Note: C-state values are processor specific\r | |
770 | C-state code names, unrelated to MWAIT extension C-state parameters or ACPI\r | |
771 | C-States. Package. Package C6 Residency Counter. (R/O) Time that this\r | |
772 | package is in processor-specific C6 states since last reset. Counts at 1 Mhz\r | |
773 | frequency.\r | |
774 | \r | |
775 | @param ECX MSR_ATOM_PKG_C6_RESIDENCY (0x000003FA)\r | |
776 | @param EAX Lower 32-bits of MSR value.\r | |
777 | @param EDX Upper 32-bits of MSR value.\r | |
778 | \r | |
779 | <b>Example usage</b>\r | |
780 | @code\r | |
781 | UINT64 Msr;\r | |
782 | \r | |
783 | Msr = AsmReadMsr64 (MSR_ATOM_PKG_C6_RESIDENCY);\r | |
784 | AsmWriteMsr64 (MSR_ATOM_PKG_C6_RESIDENCY, Msr);\r | |
785 | @endcode\r | |
800a651d | 786 | @note MSR_ATOM_PKG_C6_RESIDENCY is defined as MSR_PKG_C6_RESIDENCY in SDM.\r |
a646000f MK |
787 | **/\r |
788 | #define MSR_ATOM_PKG_C6_RESIDENCY 0x000003FA\r | |
789 | \r | |
790 | #endif\r |