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1 | /** @file\r |
2 | MSR Definitions for Intel processors based on the Broadwell microarchitecture.\r | |
3 | \r | |
4 | Provides defines for Machine Specific Registers(MSR) indexes. Data structures\r | |
5 | are provided for MSRs that contain one or more bit fields. If the MSR value\r | |
6 | returned is a single 32-bit or 64-bit value, then a data structure is not\r | |
7 | provided for that MSR.\r | |
8 | \r | |
9 | Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>\r | |
10 | This program and the accompanying materials\r | |
11 | are licensed and made available under the terms and conditions of the BSD License\r | |
12 | which accompanies this distribution. The full text of the license may be found at\r | |
13 | http://opensource.org/licenses/bsd-license.php\r | |
14 | \r | |
15 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
16 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
17 | \r | |
18 | @par Specification Reference:\r | |
19 | Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,\r | |
0f16be6d | 20 | September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.13.\r |
d57201c0 MK |
21 | \r |
22 | **/\r | |
23 | \r | |
24 | #ifndef __BROADWELL_MSR_H__\r | |
25 | #define __BROADWELL_MSR_H__\r | |
26 | \r | |
27 | #include <Register/ArchitecturalMsr.h>\r | |
28 | \r | |
29 | /**\r | |
30 | Thread. See Table 35-2. See Section 18.4.2, "Global Counter Control\r | |
31 | Facilities.".\r | |
32 | \r | |
0f16be6d | 33 | @param ECX MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS (0x0000038E)\r |
d57201c0 | 34 | @param EAX Lower 32-bits of MSR value.\r |
0f16be6d | 35 | Described by the type MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS_REGISTER.\r |
d57201c0 | 36 | @param EDX Upper 32-bits of MSR value.\r |
0f16be6d | 37 | Described by the type MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS_REGISTER.\r |
d57201c0 MK |
38 | \r |
39 | <b>Example usage</b>\r | |
40 | @code\r | |
0f16be6d | 41 | MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS_REGISTER Msr;\r |
d57201c0 | 42 | \r |
0f16be6d HW |
43 | Msr.Uint64 = AsmReadMsr64 (MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS);\r |
44 | AsmWriteMsr64 (MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS, Msr.Uint64);\r | |
d57201c0 | 45 | @endcode\r |
0f16be6d | 46 | @note MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS is defined as IA32_PERF_GLOBAL_STATUS in SDM.\r |
d57201c0 | 47 | **/\r |
0f16be6d | 48 | #define MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS 0x0000038E\r |
d57201c0 MK |
49 | \r |
50 | /**\r | |
0f16be6d | 51 | MSR information returned for MSR index #MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS\r |
d57201c0 MK |
52 | **/\r |
53 | typedef union {\r | |
54 | ///\r | |
55 | /// Individual bit fields\r | |
56 | ///\r | |
57 | struct {\r | |
58 | ///\r | |
59 | /// [Bit 0] Ovf_PMC0.\r | |
60 | ///\r | |
61 | UINT32 Ovf_PMC0:1;\r | |
62 | ///\r | |
63 | /// [Bit 1] Ovf_PMC1.\r | |
64 | ///\r | |
65 | UINT32 Ovf_PMC1:1;\r | |
66 | ///\r | |
67 | /// [Bit 2] Ovf_PMC2.\r | |
68 | ///\r | |
69 | UINT32 Ovf_PMC2:1;\r | |
70 | ///\r | |
71 | /// [Bit 3] Ovf_PMC3.\r | |
72 | ///\r | |
73 | UINT32 Ovf_PMC3:1;\r | |
74 | UINT32 Reserved1:28;\r | |
75 | ///\r | |
76 | /// [Bit 32] Ovf_FixedCtr0.\r | |
77 | ///\r | |
78 | UINT32 Ovf_FixedCtr0:1;\r | |
79 | ///\r | |
80 | /// [Bit 33] Ovf_FixedCtr1.\r | |
81 | ///\r | |
82 | UINT32 Ovf_FixedCtr1:1;\r | |
83 | ///\r | |
84 | /// [Bit 34] Ovf_FixedCtr2.\r | |
85 | ///\r | |
86 | UINT32 Ovf_FixedCtr2:1;\r | |
87 | UINT32 Reserved2:20;\r | |
88 | ///\r | |
0f16be6d | 89 | /// [Bit 55] Trace_ToPA_PMI. See Section 36.2.6.2, "Table of Physical\r |
d57201c0 MK |
90 | /// Addresses (ToPA).".\r |
91 | ///\r | |
92 | UINT32 Trace_ToPA_PMI:1;\r | |
93 | UINT32 Reserved3:5;\r | |
94 | ///\r | |
95 | /// [Bit 61] Ovf_Uncore.\r | |
96 | ///\r | |
97 | UINT32 Ovf_Uncore:1;\r | |
98 | ///\r | |
99 | /// [Bit 62] Ovf_BufDSSAVE.\r | |
100 | ///\r | |
101 | UINT32 OvfBuf:1;\r | |
102 | ///\r | |
103 | /// [Bit 63] CondChgd.\r | |
104 | ///\r | |
105 | UINT32 CondChgd:1;\r | |
106 | } Bits;\r | |
107 | ///\r | |
108 | /// All bit fields as a 64-bit value\r | |
109 | ///\r | |
110 | UINT64 Uint64;\r | |
0f16be6d | 111 | } MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS_REGISTER;\r |
d57201c0 MK |
112 | \r |
113 | \r | |
114 | /**\r | |
115 | Core. C-State Configuration Control (R/W) Note: C-state values are processor\r | |
116 | specific C-state code names, unrelated to MWAIT extension C-state parameters\r | |
117 | or ACPI C-states. `See http://biosbits.org. <http://biosbits.org>`__.\r | |
118 | \r | |
119 | @param ECX MSR_BROADWELL_PKG_CST_CONFIG_CONTROL (0x000000E2)\r | |
120 | @param EAX Lower 32-bits of MSR value.\r | |
121 | Described by the type MSR_BROADWELL_PKG_CST_CONFIG_CONTROL_REGISTER.\r | |
122 | @param EDX Upper 32-bits of MSR value.\r | |
123 | Described by the type MSR_BROADWELL_PKG_CST_CONFIG_CONTROL_REGISTER.\r | |
124 | \r | |
125 | <b>Example usage</b>\r | |
126 | @code\r | |
127 | MSR_BROADWELL_PKG_CST_CONFIG_CONTROL_REGISTER Msr;\r | |
128 | \r | |
129 | Msr.Uint64 = AsmReadMsr64 (MSR_BROADWELL_PKG_CST_CONFIG_CONTROL);\r | |
130 | AsmWriteMsr64 (MSR_BROADWELL_PKG_CST_CONFIG_CONTROL, Msr.Uint64);\r | |
131 | @endcode\r | |
a6b7bc3c | 132 | @note MSR_BROADWELL_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM.\r |
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133 | **/\r |
134 | #define MSR_BROADWELL_PKG_CST_CONFIG_CONTROL 0x000000E2\r | |
135 | \r | |
136 | /**\r | |
137 | MSR information returned for MSR index #MSR_BROADWELL_PKG_CST_CONFIG_CONTROL\r | |
138 | **/\r | |
139 | typedef union {\r | |
140 | ///\r | |
141 | /// Individual bit fields\r | |
142 | ///\r | |
143 | struct {\r | |
144 | ///\r | |
145 | /// [Bits 3:0] Package C-State Limit (R/W) Specifies the lowest\r | |
146 | /// processor-specific C-state code name (consuming the least power) for\r | |
147 | /// the package. The default is set as factory-configured package C-state\r | |
148 | /// limit. The following C-state code name encodings are supported: 0000b:\r | |
149 | /// C0/C1 (no package C-state support) 0001b: C2 0010b: C3 0011b: C6\r | |
150 | /// 0100b: C7 0101b: C7s 0110b: C8 0111b: C9 1000b: C10.\r | |
151 | ///\r | |
152 | UINT32 Limit:4;\r | |
153 | UINT32 Reserved1:6;\r | |
154 | ///\r | |
155 | /// [Bit 10] I/O MWAIT Redirection Enable (R/W).\r | |
156 | ///\r | |
157 | UINT32 IO_MWAIT:1;\r | |
158 | UINT32 Reserved2:4;\r | |
159 | ///\r | |
160 | /// [Bit 15] CFG Lock (R/WO).\r | |
161 | ///\r | |
162 | UINT32 CFGLock:1;\r | |
163 | UINT32 Reserved3:9;\r | |
164 | ///\r | |
165 | /// [Bit 25] C3 State Auto Demotion Enable (R/W).\r | |
166 | ///\r | |
167 | UINT32 C3AutoDemotion:1;\r | |
168 | ///\r | |
169 | /// [Bit 26] C1 State Auto Demotion Enable (R/W).\r | |
170 | ///\r | |
171 | UINT32 C1AutoDemotion:1;\r | |
172 | ///\r | |
173 | /// [Bit 27] Enable C3 Undemotion (R/W).\r | |
174 | ///\r | |
175 | UINT32 C3Undemotion:1;\r | |
176 | ///\r | |
177 | /// [Bit 28] Enable C1 Undemotion (R/W).\r | |
178 | ///\r | |
179 | UINT32 C1Undemotion:1;\r | |
180 | ///\r | |
181 | /// [Bit 29] Enable Package C-State Auto-demotion (R/W).\r | |
182 | ///\r | |
183 | UINT32 CStateAutoDemotion:1;\r | |
184 | ///\r | |
185 | /// [Bit 30] Enable Package C-State Undemotion (R/W).\r | |
186 | ///\r | |
187 | UINT32 CStateUndemotion:1;\r | |
188 | UINT32 Reserved4:1;\r | |
189 | UINT32 Reserved5:32;\r | |
190 | } Bits;\r | |
191 | ///\r | |
192 | /// All bit fields as a 32-bit value\r | |
193 | ///\r | |
194 | UINT32 Uint32;\r | |
195 | ///\r | |
196 | /// All bit fields as a 64-bit value\r | |
197 | ///\r | |
198 | UINT64 Uint64;\r | |
199 | } MSR_BROADWELL_PKG_CST_CONFIG_CONTROL_REGISTER;\r | |
200 | \r | |
201 | \r | |
202 | /**\r | |
203 | Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,\r | |
204 | RW if MSR_PLATFORM_INFO.[28] = 1.\r | |
205 | \r | |
206 | @param ECX MSR_BROADWELL_TURBO_RATIO_LIMIT (0x000001AD)\r | |
207 | @param EAX Lower 32-bits of MSR value.\r | |
208 | Described by the type MSR_BROADWELL_TURBO_RATIO_LIMIT_REGISTER.\r | |
209 | @param EDX Upper 32-bits of MSR value.\r | |
210 | Described by the type MSR_BROADWELL_TURBO_RATIO_LIMIT_REGISTER.\r | |
211 | \r | |
212 | <b>Example usage</b>\r | |
213 | @code\r | |
214 | MSR_BROADWELL_TURBO_RATIO_LIMIT_REGISTER Msr;\r | |
215 | \r | |
216 | Msr.Uint64 = AsmReadMsr64 (MSR_BROADWELL_TURBO_RATIO_LIMIT);\r | |
217 | @endcode\r | |
a6b7bc3c | 218 | @note MSR_BROADWELL_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.\r |
d57201c0 MK |
219 | **/\r |
220 | #define MSR_BROADWELL_TURBO_RATIO_LIMIT 0x000001AD\r | |
221 | \r | |
222 | /**\r | |
223 | MSR information returned for MSR index #MSR_BROADWELL_TURBO_RATIO_LIMIT\r | |
224 | **/\r | |
225 | typedef union {\r | |
226 | ///\r | |
227 | /// Individual bit fields\r | |
228 | ///\r | |
229 | struct {\r | |
230 | ///\r | |
231 | /// [Bits 7:0] Package. Maximum Ratio Limit for 1C Maximum turbo ratio\r | |
232 | /// limit of 1 core active.\r | |
233 | ///\r | |
234 | UINT32 Maximum1C:8;\r | |
235 | ///\r | |
236 | /// [Bits 15:8] Package. Maximum Ratio Limit for 2C Maximum turbo ratio\r | |
237 | /// limit of 2 core active.\r | |
238 | ///\r | |
239 | UINT32 Maximum2C:8;\r | |
240 | ///\r | |
241 | /// [Bits 23:16] Package. Maximum Ratio Limit for 3C Maximum turbo ratio\r | |
242 | /// limit of 3 core active.\r | |
243 | ///\r | |
244 | UINT32 Maximum3C:8;\r | |
245 | ///\r | |
246 | /// [Bits 31:24] Package. Maximum Ratio Limit for 4C Maximum turbo ratio\r | |
247 | /// limit of 4 core active.\r | |
248 | ///\r | |
249 | UINT32 Maximum4C:8;\r | |
250 | ///\r | |
251 | /// [Bits 39:32] Package. Maximum Ratio Limit for 5C Maximum turbo ratio\r | |
252 | /// limit of 5core active.\r | |
253 | ///\r | |
254 | UINT32 Maximum5C:8;\r | |
255 | ///\r | |
256 | /// [Bits 47:40] Package. Maximum Ratio Limit for 6C Maximum turbo ratio\r | |
257 | /// limit of 6core active.\r | |
258 | ///\r | |
259 | UINT32 Maximum6C:8;\r | |
260 | UINT32 Reserved:16;\r | |
261 | } Bits;\r | |
262 | ///\r | |
263 | /// All bit fields as a 64-bit value\r | |
264 | ///\r | |
265 | UINT64 Uint64;\r | |
266 | } MSR_BROADWELL_TURBO_RATIO_LIMIT_REGISTER;\r | |
267 | \r | |
0f16be6d HW |
268 | \r |
269 | /**\r | |
270 | Package. PP0 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL\r | |
271 | Domains.".\r | |
272 | \r | |
273 | @param ECX MSR_BROADWELL_PP0_ENERGY_STATUS (0x00000639)\r | |
274 | @param EAX Lower 32-bits of MSR value.\r | |
275 | @param EDX Upper 32-bits of MSR value.\r | |
276 | \r | |
277 | <b>Example usage</b>\r | |
278 | @code\r | |
279 | UINT64 Msr;\r | |
280 | \r | |
281 | Msr = AsmReadMsr64 (MSR_BROADWELL_PP0_ENERGY_STATUS);\r | |
282 | @endcode\r | |
283 | @note MSR_BROADWELL_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM.\r | |
284 | **/\r | |
285 | #define MSR_BROADWELL_PP0_ENERGY_STATUS 0x00000639\r | |
286 | \r | |
d57201c0 | 287 | #endif\r |