]>
Commit | Line | Data |
---|---|---|
d57201c0 MK |
1 | /** @file\r |
2 | MSR Definitions for Intel processors based on the Broadwell microarchitecture.\r | |
3 | \r | |
4 | Provides defines for Machine Specific Registers(MSR) indexes. Data structures\r | |
5 | are provided for MSRs that contain one or more bit fields. If the MSR value\r | |
6 | returned is a single 32-bit or 64-bit value, then a data structure is not\r | |
7 | provided for that MSR.\r | |
8 | \r | |
9 | Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>\r | |
10 | This program and the accompanying materials\r | |
11 | are licensed and made available under the terms and conditions of the BSD License\r | |
12 | which accompanies this distribution. The full text of the license may be found at\r | |
13 | http://opensource.org/licenses/bsd-license.php\r | |
14 | \r | |
15 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
16 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
17 | \r | |
18 | @par Specification Reference:\r | |
19 | Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,\r | |
20 | December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-12.\r | |
21 | \r | |
22 | **/\r | |
23 | \r | |
24 | #ifndef __BROADWELL_MSR_H__\r | |
25 | #define __BROADWELL_MSR_H__\r | |
26 | \r | |
27 | #include <Register/ArchitecturalMsr.h>\r | |
28 | \r | |
29 | /**\r | |
30 | Thread. See Table 35-2. See Section 18.4.2, "Global Counter Control\r | |
31 | Facilities.".\r | |
32 | \r | |
33 | @param ECX MSR_BROADWELL_IA32_PERF_GLOBAL_STAUS (0x0000038E)\r | |
34 | @param EAX Lower 32-bits of MSR value.\r | |
35 | Described by the type MSR_BROADWELL_IA32_PERF_GLOBAL_STAUS_REGISTER.\r | |
36 | @param EDX Upper 32-bits of MSR value.\r | |
37 | Described by the type MSR_BROADWELL_IA32_PERF_GLOBAL_STAUS_REGISTER.\r | |
38 | \r | |
39 | <b>Example usage</b>\r | |
40 | @code\r | |
41 | MSR_BROADWELL_IA32_PERF_GLOBAL_STAUS_REGISTER Msr;\r | |
42 | \r | |
43 | Msr.Uint64 = AsmReadMsr64 (MSR_BROADWELL_IA32_PERF_GLOBAL_STAUS);\r | |
44 | AsmWriteMsr64 (MSR_BROADWELL_IA32_PERF_GLOBAL_STAUS, Msr.Uint64);\r | |
45 | @endcode\r | |
46 | **/\r | |
47 | #define MSR_BROADWELL_IA32_PERF_GLOBAL_STAUS 0x0000038E\r | |
48 | \r | |
49 | /**\r | |
50 | MSR information returned for MSR index #MSR_BROADWELL_IA32_PERF_GLOBAL_STAUS\r | |
51 | **/\r | |
52 | typedef union {\r | |
53 | ///\r | |
54 | /// Individual bit fields\r | |
55 | ///\r | |
56 | struct {\r | |
57 | ///\r | |
58 | /// [Bit 0] Ovf_PMC0.\r | |
59 | ///\r | |
60 | UINT32 Ovf_PMC0:1;\r | |
61 | ///\r | |
62 | /// [Bit 1] Ovf_PMC1.\r | |
63 | ///\r | |
64 | UINT32 Ovf_PMC1:1;\r | |
65 | ///\r | |
66 | /// [Bit 2] Ovf_PMC2.\r | |
67 | ///\r | |
68 | UINT32 Ovf_PMC2:1;\r | |
69 | ///\r | |
70 | /// [Bit 3] Ovf_PMC3.\r | |
71 | ///\r | |
72 | UINT32 Ovf_PMC3:1;\r | |
73 | UINT32 Reserved1:28;\r | |
74 | ///\r | |
75 | /// [Bit 32] Ovf_FixedCtr0.\r | |
76 | ///\r | |
77 | UINT32 Ovf_FixedCtr0:1;\r | |
78 | ///\r | |
79 | /// [Bit 33] Ovf_FixedCtr1.\r | |
80 | ///\r | |
81 | UINT32 Ovf_FixedCtr1:1;\r | |
82 | ///\r | |
83 | /// [Bit 34] Ovf_FixedCtr2.\r | |
84 | ///\r | |
85 | UINT32 Ovf_FixedCtr2:1;\r | |
86 | UINT32 Reserved2:20;\r | |
87 | ///\r | |
88 | /// [Bit 55] Trace_ToPA_PMI. See Section 36.2.4.2, "Table of Physical\r | |
89 | /// Addresses (ToPA).".\r | |
90 | ///\r | |
91 | UINT32 Trace_ToPA_PMI:1;\r | |
92 | UINT32 Reserved3:5;\r | |
93 | ///\r | |
94 | /// [Bit 61] Ovf_Uncore.\r | |
95 | ///\r | |
96 | UINT32 Ovf_Uncore:1;\r | |
97 | ///\r | |
98 | /// [Bit 62] Ovf_BufDSSAVE.\r | |
99 | ///\r | |
100 | UINT32 OvfBuf:1;\r | |
101 | ///\r | |
102 | /// [Bit 63] CondChgd.\r | |
103 | ///\r | |
104 | UINT32 CondChgd:1;\r | |
105 | } Bits;\r | |
106 | ///\r | |
107 | /// All bit fields as a 64-bit value\r | |
108 | ///\r | |
109 | UINT64 Uint64;\r | |
110 | } MSR_BROADWELL_IA32_PERF_GLOBAL_STAUS_REGISTER;\r | |
111 | \r | |
112 | \r | |
113 | /**\r | |
114 | Core. C-State Configuration Control (R/W) Note: C-state values are processor\r | |
115 | specific C-state code names, unrelated to MWAIT extension C-state parameters\r | |
116 | or ACPI C-states. `See http://biosbits.org. <http://biosbits.org>`__.\r | |
117 | \r | |
118 | @param ECX MSR_BROADWELL_PKG_CST_CONFIG_CONTROL (0x000000E2)\r | |
119 | @param EAX Lower 32-bits of MSR value.\r | |
120 | Described by the type MSR_BROADWELL_PKG_CST_CONFIG_CONTROL_REGISTER.\r | |
121 | @param EDX Upper 32-bits of MSR value.\r | |
122 | Described by the type MSR_BROADWELL_PKG_CST_CONFIG_CONTROL_REGISTER.\r | |
123 | \r | |
124 | <b>Example usage</b>\r | |
125 | @code\r | |
126 | MSR_BROADWELL_PKG_CST_CONFIG_CONTROL_REGISTER Msr;\r | |
127 | \r | |
128 | Msr.Uint64 = AsmReadMsr64 (MSR_BROADWELL_PKG_CST_CONFIG_CONTROL);\r | |
129 | AsmWriteMsr64 (MSR_BROADWELL_PKG_CST_CONFIG_CONTROL, Msr.Uint64);\r | |
130 | @endcode\r | |
131 | **/\r | |
132 | #define MSR_BROADWELL_PKG_CST_CONFIG_CONTROL 0x000000E2\r | |
133 | \r | |
134 | /**\r | |
135 | MSR information returned for MSR index #MSR_BROADWELL_PKG_CST_CONFIG_CONTROL\r | |
136 | **/\r | |
137 | typedef union {\r | |
138 | ///\r | |
139 | /// Individual bit fields\r | |
140 | ///\r | |
141 | struct {\r | |
142 | ///\r | |
143 | /// [Bits 3:0] Package C-State Limit (R/W) Specifies the lowest\r | |
144 | /// processor-specific C-state code name (consuming the least power) for\r | |
145 | /// the package. The default is set as factory-configured package C-state\r | |
146 | /// limit. The following C-state code name encodings are supported: 0000b:\r | |
147 | /// C0/C1 (no package C-state support) 0001b: C2 0010b: C3 0011b: C6\r | |
148 | /// 0100b: C7 0101b: C7s 0110b: C8 0111b: C9 1000b: C10.\r | |
149 | ///\r | |
150 | UINT32 Limit:4;\r | |
151 | UINT32 Reserved1:6;\r | |
152 | ///\r | |
153 | /// [Bit 10] I/O MWAIT Redirection Enable (R/W).\r | |
154 | ///\r | |
155 | UINT32 IO_MWAIT:1;\r | |
156 | UINT32 Reserved2:4;\r | |
157 | ///\r | |
158 | /// [Bit 15] CFG Lock (R/WO).\r | |
159 | ///\r | |
160 | UINT32 CFGLock:1;\r | |
161 | UINT32 Reserved3:9;\r | |
162 | ///\r | |
163 | /// [Bit 25] C3 State Auto Demotion Enable (R/W).\r | |
164 | ///\r | |
165 | UINT32 C3AutoDemotion:1;\r | |
166 | ///\r | |
167 | /// [Bit 26] C1 State Auto Demotion Enable (R/W).\r | |
168 | ///\r | |
169 | UINT32 C1AutoDemotion:1;\r | |
170 | ///\r | |
171 | /// [Bit 27] Enable C3 Undemotion (R/W).\r | |
172 | ///\r | |
173 | UINT32 C3Undemotion:1;\r | |
174 | ///\r | |
175 | /// [Bit 28] Enable C1 Undemotion (R/W).\r | |
176 | ///\r | |
177 | UINT32 C1Undemotion:1;\r | |
178 | ///\r | |
179 | /// [Bit 29] Enable Package C-State Auto-demotion (R/W).\r | |
180 | ///\r | |
181 | UINT32 CStateAutoDemotion:1;\r | |
182 | ///\r | |
183 | /// [Bit 30] Enable Package C-State Undemotion (R/W).\r | |
184 | ///\r | |
185 | UINT32 CStateUndemotion:1;\r | |
186 | UINT32 Reserved4:1;\r | |
187 | UINT32 Reserved5:32;\r | |
188 | } Bits;\r | |
189 | ///\r | |
190 | /// All bit fields as a 32-bit value\r | |
191 | ///\r | |
192 | UINT32 Uint32;\r | |
193 | ///\r | |
194 | /// All bit fields as a 64-bit value\r | |
195 | ///\r | |
196 | UINT64 Uint64;\r | |
197 | } MSR_BROADWELL_PKG_CST_CONFIG_CONTROL_REGISTER;\r | |
198 | \r | |
199 | \r | |
200 | /**\r | |
201 | Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,\r | |
202 | RW if MSR_PLATFORM_INFO.[28] = 1.\r | |
203 | \r | |
204 | @param ECX MSR_BROADWELL_TURBO_RATIO_LIMIT (0x000001AD)\r | |
205 | @param EAX Lower 32-bits of MSR value.\r | |
206 | Described by the type MSR_BROADWELL_TURBO_RATIO_LIMIT_REGISTER.\r | |
207 | @param EDX Upper 32-bits of MSR value.\r | |
208 | Described by the type MSR_BROADWELL_TURBO_RATIO_LIMIT_REGISTER.\r | |
209 | \r | |
210 | <b>Example usage</b>\r | |
211 | @code\r | |
212 | MSR_BROADWELL_TURBO_RATIO_LIMIT_REGISTER Msr;\r | |
213 | \r | |
214 | Msr.Uint64 = AsmReadMsr64 (MSR_BROADWELL_TURBO_RATIO_LIMIT);\r | |
215 | @endcode\r | |
216 | **/\r | |
217 | #define MSR_BROADWELL_TURBO_RATIO_LIMIT 0x000001AD\r | |
218 | \r | |
219 | /**\r | |
220 | MSR information returned for MSR index #MSR_BROADWELL_TURBO_RATIO_LIMIT\r | |
221 | **/\r | |
222 | typedef union {\r | |
223 | ///\r | |
224 | /// Individual bit fields\r | |
225 | ///\r | |
226 | struct {\r | |
227 | ///\r | |
228 | /// [Bits 7:0] Package. Maximum Ratio Limit for 1C Maximum turbo ratio\r | |
229 | /// limit of 1 core active.\r | |
230 | ///\r | |
231 | UINT32 Maximum1C:8;\r | |
232 | ///\r | |
233 | /// [Bits 15:8] Package. Maximum Ratio Limit for 2C Maximum turbo ratio\r | |
234 | /// limit of 2 core active.\r | |
235 | ///\r | |
236 | UINT32 Maximum2C:8;\r | |
237 | ///\r | |
238 | /// [Bits 23:16] Package. Maximum Ratio Limit for 3C Maximum turbo ratio\r | |
239 | /// limit of 3 core active.\r | |
240 | ///\r | |
241 | UINT32 Maximum3C:8;\r | |
242 | ///\r | |
243 | /// [Bits 31:24] Package. Maximum Ratio Limit for 4C Maximum turbo ratio\r | |
244 | /// limit of 4 core active.\r | |
245 | ///\r | |
246 | UINT32 Maximum4C:8;\r | |
247 | ///\r | |
248 | /// [Bits 39:32] Package. Maximum Ratio Limit for 5C Maximum turbo ratio\r | |
249 | /// limit of 5core active.\r | |
250 | ///\r | |
251 | UINT32 Maximum5C:8;\r | |
252 | ///\r | |
253 | /// [Bits 47:40] Package. Maximum Ratio Limit for 6C Maximum turbo ratio\r | |
254 | /// limit of 6core active.\r | |
255 | ///\r | |
256 | UINT32 Maximum6C:8;\r | |
257 | UINT32 Reserved:16;\r | |
258 | } Bits;\r | |
259 | ///\r | |
260 | /// All bit fields as a 64-bit value\r | |
261 | ///\r | |
262 | UINT64 Uint64;\r | |
263 | } MSR_BROADWELL_TURBO_RATIO_LIMIT_REGISTER;\r | |
264 | \r | |
265 | #endif\r |