projects / mirror_edk2.git / blame
| Commit | Line | Data |
|---|---|---|
| 7ae88a62 MK |
1 | /** @file\r |
| 2 | MSR Definitions for Intel processors based on the Haswell microarchitecture.\r | |
| 3 | \r | |
| 4 | Provides defines for Machine Specific Registers(MSR) indexes. Data structures\r | |
| 5 | are provided for MSRs that contain one or more bit fields. If the MSR value\r | |
| 6 | returned is a single 32-bit or 64-bit value, then a data structure is not\r | |
| 7 | provided for that MSR.\r | |
| 8 | \r | |
| 9 | Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>\r | |
| 10 | This program and the accompanying materials\r | |
| 11 | are licensed and made available under the terms and conditions of the BSD License\r | |
| 12 | which accompanies this distribution. The full text of the license may be found at\r | |
| 13 | http://opensource.org/licenses/bsd-license.php\r | |
| 14 | \r | |
| 15 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
| 16 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
| 17 | \r | |
| 18 | @par Specification Reference:\r | |
| 19 | Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,\r | |
| 0f16be6d | 20 | September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.11.\r |
| 7ae88a62 MK |
21 | \r |
| 22 | **/\r | |
| 23 | \r | |
| 24 | #ifndef __HASWELL_MSR_H__\r | |
| 25 | #define __HASWELL_MSR_H__\r | |
| 26 | \r | |
| 27 | #include <Register/ArchitecturalMsr.h>\r | |
| 28 | \r | |
| 29 | /**\r | |
| 30 | Package.\r | |
| 31 | \r | |
| 32 | @param ECX MSR_HASWELL_PLATFORM_INFO (0x000000CE)\r | |
| 33 | @param EAX Lower 32-bits of MSR value.\r | |
| 34 | Described by the type MSR_HASWELL_PLATFORM_INFO_REGISTER.\r | |
| 35 | @param EDX Upper 32-bits of MSR value.\r | |
| 36 | Described by the type MSR_HASWELL_PLATFORM_INFO_REGISTER.\r | |
| 37 | \r | |
| 38 | <b>Example usage</b>\r | |
| 39 | @code\r | |
| 40 | MSR_HASWELL_PLATFORM_INFO_REGISTER Msr;\r | |
| 41 | \r | |
| 42 | Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_PLATFORM_INFO);\r | |
| 43 | AsmWriteMsr64 (MSR_HASWELL_PLATFORM_INFO, Msr.Uint64);\r | |
| 44 | @endcode\r | |
| e108c3f6 | 45 | @note MSR_HASWELL_PLATFORM_INFO is defined as MSR_PLATFORM_INFO in SDM.\r |
| 7ae88a62 MK |
46 | **/\r |
| 47 | #define MSR_HASWELL_PLATFORM_INFO 0x000000CE\r | |
| 48 | \r | |
| 49 | /**\r | |
| 50 | MSR information returned for MSR index #MSR_HASWELL_PLATFORM_INFO\r | |
| 51 | **/\r | |
| 52 | typedef union {\r | |
| 53 | ///\r | |
| 54 | /// Individual bit fields\r | |
| 55 | ///\r | |
| 56 | struct {\r | |
| 57 | UINT32 Reserved1:8;\r | |
| 58 | ///\r | |
| 59 | /// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) The is the ratio\r | |
| 60 | /// of the frequency that invariant TSC runs at. Frequency = ratio * 100\r | |
| 61 | /// MHz.\r | |
| 62 | ///\r | |
| 63 | UINT32 MaximumNonTurboRatio:8;\r | |
| 64 | UINT32 Reserved2:12;\r | |
| 65 | ///\r | |
| 66 | /// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O) When\r | |
| 67 | /// set to 1, indicates that Programmable Ratio Limits for Turbo mode is\r | |
| 68 | /// enabled, and when set to 0, indicates Programmable Ratio Limits for\r | |
| 69 | /// Turbo mode is disabled.\r | |
| 70 | ///\r | |
| 71 | UINT32 RatioLimit:1;\r | |
| 72 | ///\r | |
| 73 | /// [Bit 29] Package. Programmable TDP Limit for Turbo Mode (R/O) When\r | |
| 74 | /// set to 1, indicates that TDP Limits for Turbo mode are programmable,\r | |
| 75 | /// and when set to 0, indicates TDP Limit for Turbo mode is not\r | |
| 76 | /// programmable.\r | |
| 77 | ///\r | |
| 78 | UINT32 TDPLimit:1;\r | |
| 79 | UINT32 Reserved3:2;\r | |
| 80 | ///\r | |
| 81 | /// [Bit 32] Package. Low Power Mode Support (LPM) (R/O) When set to 1,\r | |
| 82 | /// indicates that LPM is supported, and when set to 0, indicates LPM is\r | |
| 83 | /// not supported.\r | |
| 84 | ///\r | |
| 85 | UINT32 LowPowerModeSupport:1;\r | |
| 86 | ///\r | |
| 87 | /// [Bits 34:33] Package. Number of ConfigTDP Levels (R/O) 00: Only Base\r | |
| 88 | /// TDP level available. 01: One additional TDP level available. 02: Two\r | |
| 89 | /// additional TDP level available. 11: Reserved.\r | |
| 90 | ///\r | |
| 91 | UINT32 ConfigTDPLevels:2;\r | |
| 92 | UINT32 Reserved4:5;\r | |
| 93 | ///\r | |
| 94 | /// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O) The is the\r | |
| 95 | /// minimum ratio (maximum efficiency) that the processor can operates, in\r | |
| 96 | /// units of 100MHz.\r | |
| 97 | ///\r | |
| 98 | UINT32 MaximumEfficiencyRatio:8;\r | |
| 99 | ///\r | |
| 100 | /// [Bits 55:48] Package. Minimum Operating Ratio (R/O) Contains the\r | |
| 101 | /// minimum supported operating ratio in units of 100 MHz.\r | |
| 102 | ///\r | |
| 103 | UINT32 MinimumOperatingRatio:8;\r | |
| 104 | UINT32 Reserved5:8;\r | |
| 105 | } Bits;\r | |
| 106 | ///\r | |
| 107 | /// All bit fields as a 64-bit value\r | |
| 108 | ///\r | |
| 109 | UINT64 Uint64;\r | |
| 110 | } MSR_HASWELL_PLATFORM_INFO_REGISTER;\r | |
| 111 | \r | |
| 112 | \r | |
| 113 | /**\r | |
| 114 | THREAD. Performance Event Select for Counter n (R/W) Supports all fields\r | |
| 115 | described inTable 35-2 and the fields below.\r | |
| 116 | \r | |
| 117 | @param ECX MSR_HASWELL_IA32_PERFEVTSELn\r | |
| 118 | @param EAX Lower 32-bits of MSR value.\r | |
| 119 | Described by the type MSR_HASWELL_IA32_PERFEVTSEL_REGISTER.\r | |
| 120 | @param EDX Upper 32-bits of MSR value.\r | |
| 121 | Described by the type MSR_HASWELL_IA32_PERFEVTSEL_REGISTER.\r | |
| 122 | \r | |
| 123 | <b>Example usage</b>\r | |
| 124 | @code\r | |
| 125 | MSR_HASWELL_IA32_PERFEVTSEL_REGISTER Msr;\r | |
| 126 | \r | |
| 127 | Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_IA32_PERFEVTSEL0);\r | |
| 128 | AsmWriteMsr64 (MSR_HASWELL_IA32_PERFEVTSEL0, Msr.Uint64);\r | |
| 129 | @endcode\r | |
| e108c3f6 JF |
130 | @note MSR_HASWELL_IA32_PERFEVTSEL0 is defined as IA32_PERFEVTSEL0 in SDM.\r |
| 131 | MSR_HASWELL_IA32_PERFEVTSEL1 is defined as IA32_PERFEVTSEL1 in SDM.\r | |
| 132 | MSR_HASWELL_IA32_PERFEVTSEL3 is defined as IA32_PERFEVTSEL3 in SDM.\r | |
| 7ae88a62 MK |
133 | @{\r |
| 134 | **/\r | |
| 135 | #define MSR_HASWELL_IA32_PERFEVTSEL0 0x00000186\r | |
| 136 | #define MSR_HASWELL_IA32_PERFEVTSEL1 0x00000187\r | |
| 137 | #define MSR_HASWELL_IA32_PERFEVTSEL3 0x00000189\r | |
| 138 | /// @}\r | |
| 139 | \r | |
| 140 | /**\r | |
| 141 | MSR information returned for MSR indexes #MSR_HASWELL_IA32_PERFEVTSEL0,\r | |
| 142 | #MSR_HASWELL_IA32_PERFEVTSEL1, and #MSR_HASWELL_IA32_PERFEVTSEL3.\r | |
| 143 | **/\r | |
| 144 | typedef union {\r | |
| 145 | ///\r | |
| 146 | /// Individual bit fields\r | |
| 147 | ///\r | |
| 148 | struct {\r | |
| 149 | ///\r | |
| 150 | /// [Bits 7:0] Event Select: Selects a performance event logic unit.\r | |
| 151 | ///\r | |
| 152 | UINT32 EventSelect:8;\r | |
| 153 | ///\r | |
| 154 | /// [Bits 15:8] UMask: Qualifies the microarchitectural condition to\r | |
| 155 | /// detect on the selected event logic.\r | |
| 156 | ///\r | |
| 157 | UINT32 UMASK:8;\r | |
| 158 | ///\r | |
| 159 | /// [Bit 16] USR: Counts while in privilege level is not ring 0.\r | |
| 160 | ///\r | |
| 161 | UINT32 USR:1;\r | |
| 162 | ///\r | |
| 163 | /// [Bit 17] OS: Counts while in privilege level is ring 0.\r | |
| 164 | ///\r | |
| 165 | UINT32 OS:1;\r | |
| 166 | ///\r | |
| 167 | /// [Bit 18] Edge: Enables edge detection if set.\r | |
| 168 | ///\r | |
| 169 | UINT32 E:1;\r | |
| 170 | ///\r | |
| 171 | /// [Bit 19] PC: enables pin control.\r | |
| 172 | ///\r | |
| 173 | UINT32 PC:1;\r | |
| 174 | ///\r | |
| 175 | /// [Bit 20] INT: enables interrupt on counter overflow.\r | |
| 176 | ///\r | |
| 177 | UINT32 INT:1;\r | |
| 178 | ///\r | |
| 179 | /// [Bit 21] AnyThread: When set to 1, it enables counting the associated\r | |
| 180 | /// event conditions occurring across all logical processors sharing a\r | |
| 181 | /// processor core. When set to 0, the counter only increments the\r | |
| 182 | /// associated event conditions occurring in the logical processor which\r | |
| 183 | /// programmed the MSR.\r | |
| 184 | ///\r | |
| 185 | UINT32 ANY:1;\r | |
| 186 | ///\r | |
| 187 | /// [Bit 22] EN: enables the corresponding performance counter to commence\r | |
| 188 | /// counting when this bit is set.\r | |
| 189 | ///\r | |
| 190 | UINT32 EN:1;\r | |
| 191 | ///\r | |
| 192 | /// [Bit 23] INV: invert the CMASK.\r | |
| 193 | ///\r | |
| 194 | UINT32 INV:1;\r | |
| 195 | ///\r | |
| 196 | /// [Bits 31:24] CMASK: When CMASK is not zero, the corresponding\r | |
| 197 | /// performance counter increments each cycle if the event count is\r | |
| 198 | /// greater than or equal to the CMASK.\r | |
| 199 | ///\r | |
| 200 | UINT32 CMASK:8;\r | |
| 201 | UINT32 Reserved:32;\r | |
| 202 | ///\r | |
| 203 | /// [Bit 32] IN_TX: see Section 18.11.5.1 When IN_TX (bit 32) is set,\r | |
| 204 | /// AnyThread (bit 21) should be cleared to prevent incorrect results.\r | |
| 205 | ///\r | |
| 206 | UINT32 IN_TX:1;\r | |
| 207 | UINT32 Reserved2:31;\r | |
| 208 | } Bits;\r | |
| 209 | ///\r | |
| 210 | /// All bit fields as a 64-bit value\r | |
| 211 | ///\r | |
| 212 | UINT64 Uint64;\r | |
| 213 | } MSR_HASWELL_IA32_PERFEVTSEL_REGISTER;\r | |
| 214 | \r | |
| 215 | \r | |
| 216 | /**\r | |
| 217 | THREAD. Performance Event Select for Counter 2 (R/W) Supports all fields\r | |
| 218 | described inTable 35-2 and the fields below.\r | |
| 219 | \r | |
| 220 | @param ECX MSR_HASWELL_IA32_PERFEVTSEL2 (0x00000188)\r | |
| 221 | @param EAX Lower 32-bits of MSR value.\r | |
| 222 | Described by the type MSR_HASWELL_IA32_PERFEVTSEL2_REGISTER.\r | |
| 223 | @param EDX Upper 32-bits of MSR value.\r | |
| 224 | Described by the type MSR_HASWELL_IA32_PERFEVTSEL2_REGISTER.\r | |
| 225 | \r | |
| 226 | <b>Example usage</b>\r | |
| 227 | @code\r | |
| 228 | MSR_HASWELL_IA32_PERFEVTSEL2_REGISTER Msr;\r | |
| 229 | \r | |
| 230 | Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_IA32_PERFEVTSEL2);\r | |
| 231 | AsmWriteMsr64 (MSR_HASWELL_IA32_PERFEVTSEL2, Msr.Uint64);\r | |
| 232 | @endcode\r | |
| e108c3f6 | 233 | @note MSR_HASWELL_IA32_PERFEVTSEL2 is defined as IA32_PERFEVTSEL2 in SDM.\r |
| 7ae88a62 MK |
234 | **/\r |
| 235 | #define MSR_HASWELL_IA32_PERFEVTSEL2 0x00000188\r | |
| 236 | \r | |
| 237 | /**\r | |
| 238 | MSR information returned for MSR index #MSR_HASWELL_IA32_PERFEVTSEL2\r | |
| 239 | **/\r | |
| 240 | typedef union {\r | |
| 241 | ///\r | |
| 242 | /// Individual bit fields\r | |
| 243 | ///\r | |
| 244 | struct {\r | |
| 245 | ///\r | |
| 246 | /// [Bits 7:0] Event Select: Selects a performance event logic unit.\r | |
| 247 | ///\r | |
| 248 | UINT32 EventSelect:8;\r | |
| 249 | ///\r | |
| 250 | /// [Bits 15:8] UMask: Qualifies the microarchitectural condition to\r | |
| 251 | /// detect on the selected event logic.\r | |
| 252 | ///\r | |
| 253 | UINT32 UMASK:8;\r | |
| 254 | ///\r | |
| 255 | /// [Bit 16] USR: Counts while in privilege level is not ring 0.\r | |
| 256 | ///\r | |
| 257 | UINT32 USR:1;\r | |
| 258 | ///\r | |
| 259 | /// [Bit 17] OS: Counts while in privilege level is ring 0.\r | |
| 260 | ///\r | |
| 261 | UINT32 OS:1;\r | |
| 262 | ///\r | |
| 263 | /// [Bit 18] Edge: Enables edge detection if set.\r | |
| 264 | ///\r | |
| 265 | UINT32 E:1;\r | |
| 266 | ///\r | |
| 267 | /// [Bit 19] PC: enables pin control.\r | |
| 268 | ///\r | |
| 269 | UINT32 PC:1;\r | |
| 270 | ///\r | |
| 271 | /// [Bit 20] INT: enables interrupt on counter overflow.\r | |
| 272 | ///\r | |
| 273 | UINT32 INT:1;\r | |
| 274 | ///\r | |
| 275 | /// [Bit 21] AnyThread: When set to 1, it enables counting the associated\r | |
| 276 | /// event conditions occurring across all logical processors sharing a\r | |
| 277 | /// processor core. When set to 0, the counter only increments the\r | |
| 278 | /// associated event conditions occurring in the logical processor which\r | |
| 279 | /// programmed the MSR.\r | |
| 280 | ///\r | |
| 281 | UINT32 ANY:1;\r | |
| 282 | ///\r | |
| 283 | /// [Bit 22] EN: enables the corresponding performance counter to commence\r | |
| 284 | /// counting when this bit is set.\r | |
| 285 | ///\r | |
| 286 | UINT32 EN:1;\r | |
| 287 | ///\r | |
| 288 | /// [Bit 23] INV: invert the CMASK.\r | |
| 289 | ///\r | |
| 290 | UINT32 INV:1;\r | |
| 291 | ///\r | |
| 292 | /// [Bits 31:24] CMASK: When CMASK is not zero, the corresponding\r | |
| 293 | /// performance counter increments each cycle if the event count is\r | |
| 294 | /// greater than or equal to the CMASK.\r | |
| 295 | ///\r | |
| 296 | UINT32 CMASK:8;\r | |
| 297 | UINT32 Reserved:32;\r | |
| 298 | ///\r | |
| 299 | /// [Bit 32] IN_TX: see Section 18.11.5.1 When IN_TX (bit 32) is set,\r | |
| 300 | /// AnyThread (bit 21) should be cleared to prevent incorrect results.\r | |
| 301 | ///\r | |
| 302 | UINT32 IN_TX:1;\r | |
| 303 | ///\r | |
| 304 | /// [Bit 33] IN_TXCP: see Section 18.11.5.1 When IN_TXCP=1 & IN_TX=1 and\r | |
| 305 | /// in sampling, spurious PMI may occur and transactions may continuously\r | |
| 306 | /// abort near overflow conditions. Software should favor using IN_TXCP\r | |
| 307 | /// for counting over sampling. If sampling, software should use large\r | |
| 308 | /// "sample-after" value after clearing the counter configured to use\r | |
| 309 | /// IN_TXCP and also always reset the counter even when no overflow\r | |
| 310 | /// condition was reported.\r | |
| 311 | ///\r | |
| 312 | UINT32 IN_TXCP:1;\r | |
| 313 | UINT32 Reserved2:30;\r | |
| 314 | } Bits;\r | |
| 315 | ///\r | |
| 316 | /// All bit fields as a 64-bit value\r | |
| 317 | ///\r | |
| 318 | UINT64 Uint64;\r | |
| 319 | } MSR_HASWELL_IA32_PERFEVTSEL2_REGISTER;\r | |
| 320 | \r | |
| 321 | \r | |
| 322 | /**\r | |
| 323 | Thread. Last Branch Record Filtering Select Register (R/W).\r | |
| 324 | \r | |
| 325 | @param ECX MSR_HASWELL_LBR_SELECT (0x000001C8)\r | |
| 326 | @param EAX Lower 32-bits of MSR value.\r | |
| 327 | Described by the type MSR_HASWELL_LBR_SELECT_REGISTER.\r | |
| 328 | @param EDX Upper 32-bits of MSR value.\r | |
| 329 | Described by the type MSR_HASWELL_LBR_SELECT_REGISTER.\r | |
| 330 | \r | |
| 331 | <b>Example usage</b>\r | |
| 332 | @code\r | |
| 333 | MSR_HASWELL_LBR_SELECT_REGISTER Msr;\r | |
| 334 | \r | |
| 335 | Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_LBR_SELECT);\r | |
| 336 | AsmWriteMsr64 (MSR_HASWELL_LBR_SELECT, Msr.Uint64);\r | |
| 337 | @endcode\r | |
| e108c3f6 | 338 | @note MSR_HASWELL_LBR_SELECT is defined as MSR_LBR_SELECT in SDM.\r |
| 7ae88a62 MK |
339 | **/\r |
| 340 | #define MSR_HASWELL_LBR_SELECT 0x000001C8\r | |
| 341 | \r | |
| 342 | /**\r | |
| 343 | MSR information returned for MSR index #MSR_HASWELL_LBR_SELECT\r | |
| 344 | **/\r | |
| 345 | typedef union {\r | |
| 346 | ///\r | |
| 347 | /// Individual bit fields\r | |
| 348 | ///\r | |
| 349 | struct {\r | |
| 350 | ///\r | |
| 351 | /// [Bit 0] CPL_EQ_0.\r | |
| 352 | ///\r | |
| 353 | UINT32 CPL_EQ_0:1;\r | |
| 354 | ///\r | |
| 355 | /// [Bit 1] CPL_NEQ_0.\r | |
| 356 | ///\r | |
| 357 | UINT32 CPL_NEQ_0:1;\r | |
| 358 | ///\r | |
| 359 | /// [Bit 2] JCC.\r | |
| 360 | ///\r | |
| 361 | UINT32 JCC:1;\r | |
| 362 | ///\r | |
| 363 | /// [Bit 3] NEAR_REL_CALL.\r | |
| 364 | ///\r | |
| 365 | UINT32 NEAR_REL_CALL:1;\r | |
| 366 | ///\r | |
| 367 | /// [Bit 4] NEAR_IND_CALL.\r | |
| 368 | ///\r | |
| 369 | UINT32 NEAR_IND_CALL:1;\r | |
| 370 | ///\r | |
| 371 | /// [Bit 5] NEAR_RET.\r | |
| 372 | ///\r | |
| 373 | UINT32 NEAR_RET:1;\r | |
| 374 | ///\r | |
| 375 | /// [Bit 6] NEAR_IND_JMP.\r | |
| 376 | ///\r | |
| 377 | UINT32 NEAR_IND_JMP:1;\r | |
| 378 | ///\r | |
| 379 | /// [Bit 7] NEAR_REL_JMP.\r | |
| 380 | ///\r | |
| 381 | UINT32 NEAR_REL_JMP:1;\r | |
| 382 | ///\r | |
| 383 | /// [Bit 8] FAR_BRANCH.\r | |
| 384 | ///\r | |
| 385 | UINT32 FAR_BRANCH:1;\r | |
| 386 | ///\r | |
| 387 | /// [Bit 9] EN_CALL_STACK.\r | |
| 388 | ///\r | |
| 389 | UINT32 EN_CALL_STACK:1;\r | |
| 390 | UINT32 Reserved1:22;\r | |
| 391 | UINT32 Reserved2:32;\r | |
| 392 | } Bits;\r | |
| 393 | ///\r | |
| 394 | /// All bit fields as a 32-bit value\r | |
| 395 | ///\r | |
| 396 | UINT32 Uint32;\r | |
| 397 | ///\r | |
| 398 | /// All bit fields as a 64-bit value\r | |
| 399 | ///\r | |
| 400 | UINT64 Uint64;\r | |
| 401 | } MSR_HASWELL_LBR_SELECT_REGISTER;\r | |
| 402 | \r | |
| 403 | \r | |
| 404 | /**\r | |
| 405 | Package. Package C6/C7 Interrupt Response Limit 1 (R/W) This MSR defines\r | |
| 406 | the interrupt response time limit used by the processor to manage transition\r | |
| 407 | to package C6 or C7 state. The latency programmed in this register is for\r | |
| 408 | the shorter-latency sub C-states used by an MWAIT hint to C6 or C7 state.\r | |
| 409 | Note: C-state values are processor specific C-state code names, unrelated to\r | |
| 410 | MWAIT extension C-state parameters or ACPI C-States.\r | |
| 411 | \r | |
| 412 | @param ECX MSR_HASWELL_PKGC_IRTL1 (0x0000060B)\r | |
| 413 | @param EAX Lower 32-bits of MSR value.\r | |
| 414 | Described by the type MSR_HASWELL_PKGC_IRTL1_REGISTER.\r | |
| 415 | @param EDX Upper 32-bits of MSR value.\r | |
| 416 | Described by the type MSR_HASWELL_PKGC_IRTL1_REGISTER.\r | |
| 417 | \r | |
| 418 | <b>Example usage</b>\r | |
| 419 | @code\r | |
| 420 | MSR_HASWELL_PKGC_IRTL1_REGISTER Msr;\r | |
| 421 | \r | |
| 422 | Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_PKGC_IRTL1);\r | |
| 423 | AsmWriteMsr64 (MSR_HASWELL_PKGC_IRTL1, Msr.Uint64);\r | |
| 424 | @endcode\r | |
| e108c3f6 | 425 | @note MSR_HASWELL_PKGC_IRTL1 is defined as MSR_PKGC_IRTL1 in SDM.\r |
| 7ae88a62 MK |
426 | **/\r |
| 427 | #define MSR_HASWELL_PKGC_IRTL1 0x0000060B\r | |
| 428 | \r | |
| 429 | /**\r | |
| 430 | MSR information returned for MSR index #MSR_HASWELL_PKGC_IRTL1\r | |
| 431 | **/\r | |
| 432 | typedef union {\r | |
| 433 | ///\r | |
| 434 | /// Individual bit fields\r | |
| 435 | ///\r | |
| 436 | struct {\r | |
| 437 | ///\r | |
| 438 | /// [Bits 9:0] Interrupt response time limit (R/W) Specifies the limit\r | |
| 439 | /// that should be used to decide if the package should be put into a\r | |
| 440 | /// package C6 or C7 state.\r | |
| 441 | ///\r | |
| 442 | UINT32 InterruptResponseTimeLimit:10;\r | |
| 443 | ///\r | |
| 444 | /// [Bits 12:10] Time Unit (R/W) Specifies the encoding value of time\r | |
| 0f16be6d HW |
445 | /// unit of the interrupt response time limit. See Table 35-18 for\r |
| 446 | /// supported time unit encodings.\r | |
| 7ae88a62 MK |
447 | ///\r |
| 448 | UINT32 TimeUnit:3;\r | |
| 449 | UINT32 Reserved1:2;\r | |
| 450 | ///\r | |
| 451 | /// [Bit 15] Valid (R/W) Indicates whether the values in bits 12:0 are\r | |
| 452 | /// valid and can be used by the processor for package C-sate management.\r | |
| 453 | ///\r | |
| 454 | UINT32 Valid:1;\r | |
| 455 | UINT32 Reserved2:16;\r | |
| 456 | UINT32 Reserved3:32;\r | |
| 457 | } Bits;\r | |
| 458 | ///\r | |
| 459 | /// All bit fields as a 32-bit value\r | |
| 460 | ///\r | |
| 461 | UINT32 Uint32;\r | |
| 462 | ///\r | |
| 463 | /// All bit fields as a 64-bit value\r | |
| 464 | ///\r | |
| 465 | UINT64 Uint64;\r | |
| 466 | } MSR_HASWELL_PKGC_IRTL1_REGISTER;\r | |
| 467 | \r | |
| 468 | \r | |
| 469 | /**\r | |
| 470 | Package. Package C6/C7 Interrupt Response Limit 2 (R/W) This MSR defines\r | |
| 471 | the interrupt response time limit used by the processor to manage transition\r | |
| 472 | to package C6 or C7 state. The latency programmed in this register is for\r | |
| 473 | the longer-latency sub Cstates used by an MWAIT hint to C6 or C7 state.\r | |
| 474 | Note: C-state values are processor specific C-state code names, unrelated to\r | |
| 475 | MWAIT extension C-state parameters or ACPI C-States.\r | |
| 476 | \r | |
| 477 | @param ECX MSR_HASWELL_PKGC_IRTL2 (0x0000060C)\r | |
| 478 | @param EAX Lower 32-bits of MSR value.\r | |
| 479 | Described by the type MSR_HASWELL_PKGC_IRTL2_REGISTER.\r | |
| 480 | @param EDX Upper 32-bits of MSR value.\r | |
| 481 | Described by the type MSR_HASWELL_PKGC_IRTL2_REGISTER.\r | |
| 482 | \r | |
| 483 | <b>Example usage</b>\r | |
| 484 | @code\r | |
| 485 | MSR_HASWELL_PKGC_IRTL2_REGISTER Msr;\r | |
| 486 | \r | |
| 487 | Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_PKGC_IRTL2);\r | |
| 488 | AsmWriteMsr64 (MSR_HASWELL_PKGC_IRTL2, Msr.Uint64);\r | |
| 489 | @endcode\r | |
| e108c3f6 | 490 | @note MSR_HASWELL_PKGC_IRTL2 is defined as MSR_PKGC_IRTL2 in SDM.\r |
| 7ae88a62 MK |
491 | **/\r |
| 492 | #define MSR_HASWELL_PKGC_IRTL2 0x0000060C\r | |
| 493 | \r | |
| 494 | /**\r | |
| 495 | MSR information returned for MSR index #MSR_HASWELL_PKGC_IRTL2\r | |
| 496 | **/\r | |
| 497 | typedef union {\r | |
| 498 | ///\r | |
| 499 | /// Individual bit fields\r | |
| 500 | ///\r | |
| 501 | struct {\r | |
| 502 | ///\r | |
| 503 | /// [Bits 9:0] Interrupt response time limit (R/W) Specifies the limit\r | |
| 504 | /// that should be used to decide if the package should be put into a\r | |
| 505 | /// package C6 or C7 state.\r | |
| 506 | ///\r | |
| 507 | UINT32 InterruptResponseTimeLimit:10;\r | |
| 508 | ///\r | |
| 509 | /// [Bits 12:10] Time Unit (R/W) Specifies the encoding value of time\r | |
| 0f16be6d HW |
510 | /// unit of the interrupt response time limit. See Table 35-18 for\r |
| 511 | /// supported time unit encodings.\r | |
| 7ae88a62 MK |
512 | ///\r |
| 513 | UINT32 TimeUnit:3;\r | |
| 514 | UINT32 Reserved1:2;\r | |
| 515 | ///\r | |
| 516 | /// [Bit 15] Valid (R/W) Indicates whether the values in bits 12:0 are\r | |
| 517 | /// valid and can be used by the processor for package C-sate management.\r | |
| 518 | ///\r | |
| 519 | UINT32 Valid:1;\r | |
| 520 | UINT32 Reserved2:16;\r | |
| 521 | UINT32 Reserved3:32;\r | |
| 522 | } Bits;\r | |
| 523 | ///\r | |
| 524 | /// All bit fields as a 32-bit value\r | |
| 525 | ///\r | |
| 526 | UINT32 Uint32;\r | |
| 527 | ///\r | |
| 528 | /// All bit fields as a 64-bit value\r | |
| 529 | ///\r | |
| 530 | UINT64 Uint64;\r | |
| 531 | } MSR_HASWELL_PKGC_IRTL2_REGISTER;\r | |
| 532 | \r | |
| 533 | \r | |
| 534 | /**\r | |
| 535 | Package. PKG Perf Status (R/O) See Section 14.9.3, "Package RAPL Domain.".\r | |
| 536 | \r | |
| 537 | @param ECX MSR_HASWELL_PKG_PERF_STATUS (0x00000613)\r | |
| 538 | @param EAX Lower 32-bits of MSR value.\r | |
| 539 | @param EDX Upper 32-bits of MSR value.\r | |
| 540 | \r | |
| 541 | <b>Example usage</b>\r | |
| 542 | @code\r | |
| 543 | UINT64 Msr;\r | |
| 544 | \r | |
| 545 | Msr = AsmReadMsr64 (MSR_HASWELL_PKG_PERF_STATUS);\r | |
| 546 | @endcode\r | |
| e108c3f6 | 547 | @note MSR_HASWELL_PKG_PERF_STATUS is defined as MSR_PKG_PERF_STATUS in SDM.\r |
| 7ae88a62 MK |
548 | **/\r |
| 549 | #define MSR_HASWELL_PKG_PERF_STATUS 0x00000613\r | |
| 550 | \r | |
| 551 | \r | |
| 552 | /**\r | |
| 553 | Package. DRAM Energy Status (R/O) See Section 14.9.5, "DRAM RAPL Domain.".\r | |
| 554 | \r | |
| 555 | @param ECX MSR_HASWELL_DRAM_ENERGY_STATUS (0x00000619)\r | |
| 556 | @param EAX Lower 32-bits of MSR value.\r | |
| 557 | @param EDX Upper 32-bits of MSR value.\r | |
| 558 | \r | |
| 559 | <b>Example usage</b>\r | |
| 560 | @code\r | |
| 561 | UINT64 Msr;\r | |
| 562 | \r | |
| 563 | Msr = AsmReadMsr64 (MSR_HASWELL_DRAM_ENERGY_STATUS);\r | |
| 564 | @endcode\r | |
| e108c3f6 | 565 | @note MSR_HASWELL_DRAM_ENERGY_STATUS is defined as MSR_DRAM_ENERGY_STATUS in SDM.\r |
| 7ae88a62 MK |
566 | **/\r |
| 567 | #define MSR_HASWELL_DRAM_ENERGY_STATUS 0x00000619\r | |
| 568 | \r | |
| 569 | \r | |
| 570 | /**\r | |
| 571 | Package. DRAM Performance Throttling Status (R/O) See Section 14.9.5, "DRAM\r | |
| 572 | RAPL Domain.".\r | |
| 573 | \r | |
| 574 | @param ECX MSR_HASWELL_DRAM_PERF_STATUS (0x0000061B)\r | |
| 575 | @param EAX Lower 32-bits of MSR value.\r | |
| 576 | @param EDX Upper 32-bits of MSR value.\r | |
| 577 | \r | |
| 578 | <b>Example usage</b>\r | |
| 579 | @code\r | |
| 580 | UINT64 Msr;\r | |
| 581 | \r | |
| 582 | Msr = AsmReadMsr64 (MSR_HASWELL_DRAM_PERF_STATUS);\r | |
| 583 | @endcode\r | |
| e108c3f6 | 584 | @note MSR_HASWELL_DRAM_PERF_STATUS is defined as MSR_DRAM_PERF_STATUS in SDM.\r |
| 7ae88a62 MK |
585 | **/\r |
| 586 | #define MSR_HASWELL_DRAM_PERF_STATUS 0x0000061B\r | |
| 587 | \r | |
| 588 | \r | |
| 589 | /**\r | |
| 590 | Package. Base TDP Ratio (R/O).\r | |
| 591 | \r | |
| 592 | @param ECX MSR_HASWELL_CONFIG_TDP_NOMINAL (0x00000648)\r | |
| 593 | @param EAX Lower 32-bits of MSR value.\r | |
| 594 | Described by the type MSR_HASWELL_CONFIG_TDP_NOMINAL_REGISTER.\r | |
| 595 | @param EDX Upper 32-bits of MSR value.\r | |
| 596 | Described by the type MSR_HASWELL_CONFIG_TDP_NOMINAL_REGISTER.\r | |
| 597 | \r | |
| 598 | <b>Example usage</b>\r | |
| 599 | @code\r | |
| 600 | MSR_HASWELL_CONFIG_TDP_NOMINAL_REGISTER Msr;\r | |
| 601 | \r | |
| 602 | Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_CONFIG_TDP_NOMINAL);\r | |
| 603 | @endcode\r | |
| e108c3f6 | 604 | @note MSR_HASWELL_CONFIG_TDP_NOMINAL is defined as MSR_CONFIG_TDP_NOMINAL in SDM.\r |
| 7ae88a62 MK |
605 | **/\r |
| 606 | #define MSR_HASWELL_CONFIG_TDP_NOMINAL 0x00000648\r | |
| 607 | \r | |
| 608 | /**\r | |
| 609 | MSR information returned for MSR index #MSR_HASWELL_CONFIG_TDP_NOMINAL\r | |
| 610 | **/\r | |
| 611 | typedef union {\r | |
| 612 | ///\r | |
| 613 | /// Individual bit fields\r | |
| 614 | ///\r | |
| 615 | struct {\r | |
| 616 | ///\r | |
| 617 | /// [Bits 7:0] Config_TDP_Base Base TDP level ratio to be used for this\r | |
| 618 | /// specific processor (in units of 100 MHz).\r | |
| 619 | ///\r | |
| 620 | UINT32 Config_TDP_Base:8;\r | |
| 621 | UINT32 Reserved1:24;\r | |
| 622 | UINT32 Reserved2:32;\r | |
| 623 | } Bits;\r | |
| 624 | ///\r | |
| 625 | /// All bit fields as a 32-bit value\r | |
| 626 | ///\r | |
| 627 | UINT32 Uint32;\r | |
| 628 | ///\r | |
| 629 | /// All bit fields as a 64-bit value\r | |
| 630 | ///\r | |
| 631 | UINT64 Uint64;\r | |
| 632 | } MSR_HASWELL_CONFIG_TDP_NOMINAL_REGISTER;\r | |
| 633 | \r | |
| 634 | \r | |
| 635 | /**\r | |
| 636 | Package. ConfigTDP Level 1 ratio and power level (R/O).\r | |
| 637 | \r | |
| 638 | @param ECX MSR_HASWELL_CONFIG_TDP_LEVEL1 (0x00000649)\r | |
| 639 | @param EAX Lower 32-bits of MSR value.\r | |
| 640 | Described by the type MSR_HASWELL_CONFIG_TDP_LEVEL1_REGISTER.\r | |
| 641 | @param EDX Upper 32-bits of MSR value.\r | |
| 642 | Described by the type MSR_HASWELL_CONFIG_TDP_LEVEL1_REGISTER.\r | |
| 643 | \r | |
| 644 | <b>Example usage</b>\r | |
| 645 | @code\r | |
| 646 | MSR_HASWELL_CONFIG_TDP_LEVEL1_REGISTER Msr;\r | |
| 647 | \r | |
| 648 | Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_CONFIG_TDP_LEVEL1);\r | |
| 649 | @endcode\r | |
| e108c3f6 | 650 | @note MSR_HASWELL_CONFIG_TDP_LEVEL1 is defined as MSR_CONFIG_TDP_LEVEL1 in SDM.\r |
| 7ae88a62 MK |
651 | **/\r |
| 652 | #define MSR_HASWELL_CONFIG_TDP_LEVEL1 0x00000649\r | |
| 653 | \r | |
| 654 | /**\r | |
| 655 | MSR information returned for MSR index #MSR_HASWELL_CONFIG_TDP_LEVEL1\r | |
| 656 | **/\r | |
| 657 | typedef union {\r | |
| 658 | ///\r | |
| 659 | /// Individual bit fields\r | |
| 660 | ///\r | |
| 661 | struct {\r | |
| 662 | ///\r | |
| 663 | /// [Bits 14:0] PKG_TDP_LVL1. Power setting for ConfigTDP Level 1.\r | |
| 664 | ///\r | |
| 665 | UINT32 PKG_TDP_LVL1:15;\r | |
| 666 | UINT32 Reserved1:1;\r | |
| 667 | ///\r | |
| 668 | /// [Bits 23:16] Config_TDP_LVL1_Ratio. ConfigTDP level 1 ratio to be used\r | |
| 669 | /// for this specific processor.\r | |
| 670 | ///\r | |
| 671 | UINT32 Config_TDP_LVL1_Ratio:8;\r | |
| 672 | UINT32 Reserved2:8;\r | |
| 673 | ///\r | |
| 674 | /// [Bits 46:32] PKG_MAX_PWR_LVL1. Max Power setting allowed for ConfigTDP\r | |
| 675 | /// Level 1.\r | |
| 676 | ///\r | |
| 677 | UINT32 PKG_MAX_PWR_LVL1:15;\r | |
| 678 | ///\r | |
| 679 | /// [Bits 62:47] PKG_MIN_PWR_LVL1. MIN Power setting allowed for ConfigTDP\r | |
| 680 | /// Level 1.\r | |
| 681 | ///\r | |
| 682 | UINT32 PKG_MIN_PWR_LVL1:16;\r | |
| 683 | UINT32 Reserved3:1;\r | |
| 684 | } Bits;\r | |
| 685 | ///\r | |
| 686 | /// All bit fields as a 64-bit value\r | |
| 687 | ///\r | |
| 688 | UINT64 Uint64;\r | |
| 689 | } MSR_HASWELL_CONFIG_TDP_LEVEL1_REGISTER;\r | |
| 690 | \r | |
| 691 | \r | |
| 692 | /**\r | |
| 693 | Package. ConfigTDP Level 2 ratio and power level (R/O).\r | |
| 694 | \r | |
| 695 | @param ECX MSR_HASWELL_CONFIG_TDP_LEVEL2 (0x0000064A)\r | |
| 696 | @param EAX Lower 32-bits of MSR value.\r | |
| 697 | Described by the type MSR_HASWELL_CONFIG_TDP_LEVEL2_REGISTER.\r | |
| 698 | @param EDX Upper 32-bits of MSR value.\r | |
| 699 | Described by the type MSR_HASWELL_CONFIG_TDP_LEVEL2_REGISTER.\r | |
| 700 | \r | |
| 701 | <b>Example usage</b>\r | |
| 702 | @code\r | |
| 703 | MSR_HASWELL_CONFIG_TDP_LEVEL2_REGISTER Msr;\r | |
| 704 | \r | |
| 705 | Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_CONFIG_TDP_LEVEL2);\r | |
| 706 | @endcode\r | |
| e108c3f6 | 707 | @note MSR_HASWELL_CONFIG_TDP_LEVEL2 is defined as MSR_CONFIG_TDP_LEVEL2 in SDM.\r |
| 7ae88a62 MK |
708 | **/\r |
| 709 | #define MSR_HASWELL_CONFIG_TDP_LEVEL2 0x0000064A\r | |
| 710 | \r | |
| 711 | /**\r | |
| 712 | MSR information returned for MSR index #MSR_HASWELL_CONFIG_TDP_LEVEL2\r | |
| 713 | **/\r | |
| 714 | typedef union {\r | |
| 715 | ///\r | |
| 716 | /// Individual bit fields\r | |
| 717 | ///\r | |
| 718 | struct {\r | |
| 719 | ///\r | |
| 720 | /// [Bits 14:0] PKG_TDP_LVL2. Power setting for ConfigTDP Level 2.\r | |
| 721 | ///\r | |
| 722 | UINT32 PKG_TDP_LVL2:15;\r | |
| 723 | UINT32 Reserved1:1;\r | |
| 724 | ///\r | |
| 725 | /// [Bits 23:16] Config_TDP_LVL2_Ratio. ConfigTDP level 2 ratio to be used\r | |
| 726 | /// for this specific processor.\r | |
| 727 | ///\r | |
| 728 | UINT32 Config_TDP_LVL2_Ratio:8;\r | |
| 729 | UINT32 Reserved2:8;\r | |
| 730 | ///\r | |
| 731 | /// [Bits 46:32] PKG_MAX_PWR_LVL2. Max Power setting allowed for ConfigTDP\r | |
| 732 | /// Level 2.\r | |
| 733 | ///\r | |
| 734 | UINT32 PKG_MAX_PWR_LVL2:15;\r | |
| 735 | ///\r | |
| 736 | /// [Bits 62:47] PKG_MIN_PWR_LVL2. MIN Power setting allowed for ConfigTDP\r | |
| 737 | /// Level 2.\r | |
| 738 | ///\r | |
| 739 | UINT32 PKG_MIN_PWR_LVL2:16;\r | |
| 740 | UINT32 Reserved3:1;\r | |
| 741 | } Bits;\r | |
| 742 | ///\r | |
| 743 | /// All bit fields as a 64-bit value\r | |
| 744 | ///\r | |
| 745 | UINT64 Uint64;\r | |
| 746 | } MSR_HASWELL_CONFIG_TDP_LEVEL2_REGISTER;\r | |
| 747 | \r | |
| 748 | \r | |
| 749 | /**\r | |
| 750 | Package. ConfigTDP Control (R/W).\r | |
| 751 | \r | |
| 752 | @param ECX MSR_HASWELL_CONFIG_TDP_CONTROL (0x0000064B)\r | |
| 753 | @param EAX Lower 32-bits of MSR value.\r | |
| 754 | Described by the type MSR_HASWELL_CONFIG_TDP_CONTROL_REGISTER.\r | |
| 755 | @param EDX Upper 32-bits of MSR value.\r | |
| 756 | Described by the type MSR_HASWELL_CONFIG_TDP_CONTROL_REGISTER.\r | |
| 757 | \r | |
| 758 | <b>Example usage</b>\r | |
| 759 | @code\r | |
| 760 | MSR_HASWELL_CONFIG_TDP_CONTROL_REGISTER Msr;\r | |
| 761 | \r | |
| 762 | Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_CONFIG_TDP_CONTROL);\r | |
| 763 | AsmWriteMsr64 (MSR_HASWELL_CONFIG_TDP_CONTROL, Msr.Uint64);\r | |
| 764 | @endcode\r | |
| e108c3f6 | 765 | @note MSR_HASWELL_CONFIG_TDP_CONTROL is defined as MSR_CONFIG_TDP_CONTROL in SDM.\r |
| 7ae88a62 MK |
766 | **/\r |
| 767 | #define MSR_HASWELL_CONFIG_TDP_CONTROL 0x0000064B\r | |
| 768 | \r | |
| 769 | /**\r | |
| 770 | MSR information returned for MSR index #MSR_HASWELL_CONFIG_TDP_CONTROL\r | |
| 771 | **/\r | |
| 772 | typedef union {\r | |
| 773 | ///\r | |
| 774 | /// Individual bit fields\r | |
| 775 | ///\r | |
| 776 | struct {\r | |
| 777 | ///\r | |
| 778 | /// [Bits 1:0] TDP_LEVEL (RW/L) System BIOS can program this field.\r | |
| 779 | ///\r | |
| 780 | UINT32 TDP_LEVEL:2;\r | |
| 781 | UINT32 Reserved1:29;\r | |
| 782 | ///\r | |
| 783 | /// [Bit 31] Config_TDP_Lock (RW/L) When this bit is set, the content of\r | |
| 784 | /// this register is locked until a reset.\r | |
| 785 | ///\r | |
| 786 | UINT32 Config_TDP_Lock:1;\r | |
| 787 | UINT32 Reserved2:32;\r | |
| 788 | } Bits;\r | |
| 789 | ///\r | |
| 790 | /// All bit fields as a 32-bit value\r | |
| 791 | ///\r | |
| 792 | UINT32 Uint32;\r | |
| 793 | ///\r | |
| 794 | /// All bit fields as a 64-bit value\r | |
| 795 | ///\r | |
| 796 | UINT64 Uint64;\r | |
| 797 | } MSR_HASWELL_CONFIG_TDP_CONTROL_REGISTER;\r | |
| 798 | \r | |
| 799 | \r | |
| 800 | /**\r | |
| 801 | Package. ConfigTDP Control (R/W).\r | |
| 802 | \r | |
| 803 | @param ECX MSR_HASWELL_TURBO_ACTIVATION_RATIO (0x0000064C)\r | |
| 804 | @param EAX Lower 32-bits of MSR value.\r | |
| 805 | Described by the type MSR_HASWELL_TURBO_ACTIVATION_RATIO_REGISTER.\r | |
| 806 | @param EDX Upper 32-bits of MSR value.\r | |
| 807 | Described by the type MSR_HASWELL_TURBO_ACTIVATION_RATIO_REGISTER.\r | |
| 808 | \r | |
| 809 | <b>Example usage</b>\r | |
| 810 | @code\r | |
| 811 | MSR_HASWELL_TURBO_ACTIVATION_RATIO_REGISTER Msr;\r | |
| 812 | \r | |
| 813 | Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_TURBO_ACTIVATION_RATIO);\r | |
| 814 | AsmWriteMsr64 (MSR_HASWELL_TURBO_ACTIVATION_RATIO, Msr.Uint64);\r | |
| 815 | @endcode\r | |
| e108c3f6 | 816 | @note MSR_HASWELL_TURBO_ACTIVATION_RATIO is defined as MSR_TURBO_ACTIVATION_RATIO in SDM.\r |
| 7ae88a62 MK |
817 | **/\r |
| 818 | #define MSR_HASWELL_TURBO_ACTIVATION_RATIO 0x0000064C\r | |
| 819 | \r | |
| 820 | /**\r | |
| 821 | MSR information returned for MSR index #MSR_HASWELL_TURBO_ACTIVATION_RATIO\r | |
| 822 | **/\r | |
| 823 | typedef union {\r | |
| 824 | ///\r | |
| 825 | /// Individual bit fields\r | |
| 826 | ///\r | |
| 827 | struct {\r | |
| 828 | ///\r | |
| 829 | /// [Bits 7:0] MAX_NON_TURBO_RATIO (RW/L) System BIOS can program this\r | |
| 830 | /// field.\r | |
| 831 | ///\r | |
| 832 | UINT32 MAX_NON_TURBO_RATIO:8;\r | |
| 833 | UINT32 Reserved1:23;\r | |
| 834 | ///\r | |
| 835 | /// [Bit 31] TURBO_ACTIVATION_RATIO_Lock (RW/L) When this bit is set, the\r | |
| 836 | /// content of this register is locked until a reset.\r | |
| 837 | ///\r | |
| 838 | UINT32 TURBO_ACTIVATION_RATIO_Lock:1;\r | |
| 839 | UINT32 Reserved2:32;\r | |
| 840 | } Bits;\r | |
| 841 | ///\r | |
| 842 | /// All bit fields as a 32-bit value\r | |
| 843 | ///\r | |
| 844 | UINT32 Uint32;\r | |
| 845 | ///\r | |
| 846 | /// All bit fields as a 64-bit value\r | |
| 847 | ///\r | |
| 848 | UINT64 Uint64;\r | |
| 849 | } MSR_HASWELL_TURBO_ACTIVATION_RATIO_REGISTER;\r | |
| 850 | \r | |
| 851 | \r | |
| 7ae88a62 MK |
852 | /**\r |
| 853 | Core. C-State Configuration Control (R/W) Note: C-state values are processor\r | |
| 854 | specific C-state code names, unrelated to MWAIT extension C-state parameters\r | |
| 855 | or ACPI Cstates. `See http://biosbits.org. <http://biosbits.org>`__.\r | |
| 856 | \r | |
| 857 | @param ECX MSR_HASWELL_PKG_CST_CONFIG_CONTROL (0x000000E2)\r | |
| 858 | @param EAX Lower 32-bits of MSR value.\r | |
| 859 | Described by the type MSR_HASWELL_PKG_CST_CONFIG_CONTROL_REGISTER.\r | |
| 860 | @param EDX Upper 32-bits of MSR value.\r | |
| 861 | Described by the type MSR_HASWELL_PKG_CST_CONFIG_CONTROL_REGISTER.\r | |
| 862 | \r | |
| 863 | <b>Example usage</b>\r | |
| 864 | @code\r | |
| 865 | MSR_HASWELL_PKG_CST_CONFIG_CONTROL_REGISTER Msr;\r | |
| 866 | \r | |
| 867 | Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_PKG_CST_CONFIG_CONTROL);\r | |
| 868 | AsmWriteMsr64 (MSR_HASWELL_PKG_CST_CONFIG_CONTROL, Msr.Uint64);\r | |
| 869 | @endcode\r | |
| e108c3f6 | 870 | @note MSR_HASWELL_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM.\r |
| 7ae88a62 MK |
871 | **/\r |
| 872 | #define MSR_HASWELL_PKG_CST_CONFIG_CONTROL 0x000000E2\r | |
| 873 | \r | |
| 874 | /**\r | |
| 875 | MSR information returned for MSR index #MSR_HASWELL_PKG_CST_CONFIG_CONTROL\r | |
| 876 | **/\r | |
| 877 | typedef union {\r | |
| 878 | ///\r | |
| 879 | /// Individual bit fields\r | |
| 880 | ///\r | |
| 881 | struct {\r | |
| 882 | ///\r | |
| 883 | /// [Bits 3:0] Package C-State Limit (R/W) Specifies the lowest\r | |
| 884 | /// processor-specific C-state code name (consuming the least power) for\r | |
| 885 | /// the package. The default is set as factory-configured package C-state\r | |
| 886 | /// limit. The following C-state code name encodings are supported: 0000b:\r | |
| 887 | /// C0/C1 (no package C-state support) 0001b: C2 0010b: C3 0011b: C6\r | |
| 888 | /// 0100b: C7 0101b: C7s Package C states C7 are not available to\r | |
| 889 | /// processor with signature 06_3CH.\r | |
| 890 | ///\r | |
| 891 | UINT32 Limit:4;\r | |
| 892 | UINT32 Reserved1:6;\r | |
| 893 | ///\r | |
| 894 | /// [Bit 10] I/O MWAIT Redirection Enable (R/W).\r | |
| 895 | ///\r | |
| 896 | UINT32 IO_MWAIT:1;\r | |
| 897 | UINT32 Reserved2:4;\r | |
| 898 | ///\r | |
| 899 | /// [Bit 15] CFG Lock (R/WO).\r | |
| 900 | ///\r | |
| 901 | UINT32 CFGLock:1;\r | |
| 902 | UINT32 Reserved3:9;\r | |
| 903 | ///\r | |
| 904 | /// [Bit 25] C3 State Auto Demotion Enable (R/W).\r | |
| 905 | ///\r | |
| 906 | UINT32 C3AutoDemotion:1;\r | |
| 907 | ///\r | |
| 908 | /// [Bit 26] C1 State Auto Demotion Enable (R/W).\r | |
| 909 | ///\r | |
| 910 | UINT32 C1AutoDemotion:1;\r | |
| 911 | ///\r | |
| 912 | /// [Bit 27] Enable C3 Undemotion (R/W).\r | |
| 913 | ///\r | |
| 914 | UINT32 C3Undemotion:1;\r | |
| 915 | ///\r | |
| 916 | /// [Bit 28] Enable C1 Undemotion (R/W).\r | |
| 917 | ///\r | |
| 918 | UINT32 C1Undemotion:1;\r | |
| 919 | UINT32 Reserved4:3;\r | |
| 920 | UINT32 Reserved5:32;\r | |
| 921 | } Bits;\r | |
| 922 | ///\r | |
| 923 | /// All bit fields as a 32-bit value\r | |
| 924 | ///\r | |
| 925 | UINT32 Uint32;\r | |
| 926 | ///\r | |
| 927 | /// All bit fields as a 64-bit value\r | |
| 928 | ///\r | |
| 929 | UINT64 Uint64;\r | |
| 930 | } MSR_HASWELL_PKG_CST_CONFIG_CONTROL_REGISTER;\r | |
| 931 | \r | |
| 932 | \r | |
| 933 | /**\r | |
| 934 | THREAD. Enhanced SMM Capabilities (SMM-RO) Reports SMM capability\r | |
| 935 | Enhancement. Accessible only while in SMM.\r | |
| 936 | \r | |
| 937 | @param ECX MSR_HASWELL_SMM_MCA_CAP (0x0000017D)\r | |
| 938 | @param EAX Lower 32-bits of MSR value.\r | |
| 939 | Described by the type MSR_HASWELL_SMM_MCA_CAP_REGISTER.\r | |
| 940 | @param EDX Upper 32-bits of MSR value.\r | |
| 941 | Described by the type MSR_HASWELL_SMM_MCA_CAP_REGISTER.\r | |
| 942 | \r | |
| 943 | <b>Example usage</b>\r | |
| 944 | @code\r | |
| 945 | MSR_HASWELL_SMM_MCA_CAP_REGISTER Msr;\r | |
| 946 | \r | |
| 947 | Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_SMM_MCA_CAP);\r | |
| 948 | AsmWriteMsr64 (MSR_HASWELL_SMM_MCA_CAP, Msr.Uint64);\r | |
| 949 | @endcode\r | |
| e108c3f6 | 950 | @note MSR_HASWELL_SMM_MCA_CAP is defined as MSR_SMM_MCA_CAP in SDM.\r |
| 7ae88a62 MK |
951 | **/\r |
| 952 | #define MSR_HASWELL_SMM_MCA_CAP 0x0000017D\r | |
| 953 | \r | |
| 954 | /**\r | |
| 955 | MSR information returned for MSR index #MSR_HASWELL_SMM_MCA_CAP\r | |
| 956 | **/\r | |
| 957 | typedef union {\r | |
| 958 | ///\r | |
| 959 | /// Individual bit fields\r | |
| 960 | ///\r | |
| 961 | struct {\r | |
| 962 | UINT32 Reserved1:32;\r | |
| 963 | UINT32 Reserved2:26;\r | |
| 964 | ///\r | |
| 965 | /// [Bit 58] SMM_Code_Access_Chk (SMM-RO) If set to 1 indicates that the\r | |
| 966 | /// SMM code access restriction is supported and the\r | |
| 967 | /// MSR_SMM_FEATURE_CONTROL is supported.\r | |
| 968 | ///\r | |
| 969 | UINT32 SMM_Code_Access_Chk:1;\r | |
| 970 | ///\r | |
| 971 | /// [Bit 59] Long_Flow_Indication (SMM-RO) If set to 1 indicates that the\r | |
| 972 | /// SMM long flow indicator is supported and the MSR_SMM_DELAYED is\r | |
| 973 | /// supported.\r | |
| 974 | ///\r | |
| 975 | UINT32 Long_Flow_Indication:1;\r | |
| 976 | UINT32 Reserved3:4;\r | |
| 977 | } Bits;\r | |
| 978 | ///\r | |
| 979 | /// All bit fields as a 64-bit value\r | |
| 980 | ///\r | |
| 981 | UINT64 Uint64;\r | |
| 982 | } MSR_HASWELL_SMM_MCA_CAP_REGISTER;\r | |
| 983 | \r | |
| 984 | \r | |
| 985 | /**\r | |
| 986 | Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,\r | |
| 987 | RW if MSR_PLATFORM_INFO.[28] = 1.\r | |
| 988 | \r | |
| 989 | @param ECX MSR_HASWELL_TURBO_RATIO_LIMIT (0x000001AD)\r | |
| 990 | @param EAX Lower 32-bits of MSR value.\r | |
| 991 | Described by the type MSR_HASWELL_TURBO_RATIO_LIMIT_REGISTER.\r | |
| 992 | @param EDX Upper 32-bits of MSR value.\r | |
| 993 | Described by the type MSR_HASWELL_TURBO_RATIO_LIMIT_REGISTER.\r | |
| 994 | \r | |
| 995 | <b>Example usage</b>\r | |
| 996 | @code\r | |
| 997 | MSR_HASWELL_TURBO_RATIO_LIMIT_REGISTER Msr;\r | |
| 998 | \r | |
| 999 | Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_TURBO_RATIO_LIMIT);\r | |
| 1000 | @endcode\r | |
| e108c3f6 | 1001 | @note MSR_HASWELL_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.\r |
| 7ae88a62 MK |
1002 | **/\r |
| 1003 | #define MSR_HASWELL_TURBO_RATIO_LIMIT 0x000001AD\r | |
| 1004 | \r | |
| 1005 | /**\r | |
| 1006 | MSR information returned for MSR index #MSR_HASWELL_TURBO_RATIO_LIMIT\r | |
| 1007 | **/\r | |
| 1008 | typedef union {\r | |
| 1009 | ///\r | |
| 1010 | /// Individual bit fields\r | |
| 1011 | ///\r | |
| 1012 | struct {\r | |
| 1013 | ///\r | |
| 1014 | /// [Bits 7:0] Package. Maximum Ratio Limit for 1C Maximum turbo ratio\r | |
| 1015 | /// limit of 1 core active.\r | |
| 1016 | ///\r | |
| 1017 | UINT32 Maximum1C:8;\r | |
| 1018 | ///\r | |
| 1019 | /// [Bits 15:8] Package. Maximum Ratio Limit for 2C Maximum turbo ratio\r | |
| 1020 | /// limit of 2 core active.\r | |
| 1021 | ///\r | |
| 1022 | UINT32 Maximum2C:8;\r | |
| 1023 | ///\r | |
| 1024 | /// [Bits 23:16] Package. Maximum Ratio Limit for 3C Maximum turbo ratio\r | |
| 1025 | /// limit of 3 core active.\r | |
| 1026 | ///\r | |
| 1027 | UINT32 Maximum3C:8;\r | |
| 1028 | ///\r | |
| 1029 | /// [Bits 31:24] Package. Maximum Ratio Limit for 4C Maximum turbo ratio\r | |
| 1030 | /// limit of 4 core active.\r | |
| 1031 | ///\r | |
| 1032 | UINT32 Maximum4C:8;\r | |
| 1033 | UINT32 Reserved:32;\r | |
| 1034 | } Bits;\r | |
| 1035 | ///\r | |
| 1036 | /// All bit fields as a 32-bit value\r | |
| 1037 | ///\r | |
| 1038 | UINT32 Uint32;\r | |
| 1039 | ///\r | |
| 1040 | /// All bit fields as a 64-bit value\r | |
| 1041 | ///\r | |
| 1042 | UINT64 Uint64;\r | |
| 1043 | } MSR_HASWELL_TURBO_RATIO_LIMIT_REGISTER;\r | |
| 1044 | \r | |
| 1045 | \r | |
| 1046 | /**\r | |
| 1047 | Package. Uncore PMU global control.\r | |
| 1048 | \r | |
| 1049 | @param ECX MSR_HASWELL_UNC_PERF_GLOBAL_CTRL (0x00000391)\r | |
| 1050 | @param EAX Lower 32-bits of MSR value.\r | |
| 1051 | Described by the type MSR_HASWELL_UNC_PERF_GLOBAL_CTRL_REGISTER.\r | |
| 1052 | @param EDX Upper 32-bits of MSR value.\r | |
| 1053 | Described by the type MSR_HASWELL_UNC_PERF_GLOBAL_CTRL_REGISTER.\r | |
| 1054 | \r | |
| 1055 | <b>Example usage</b>\r | |
| 1056 | @code\r | |
| 1057 | MSR_HASWELL_UNC_PERF_GLOBAL_CTRL_REGISTER Msr;\r | |
| 1058 | \r | |
| 1059 | Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_UNC_PERF_GLOBAL_CTRL);\r | |
| 1060 | AsmWriteMsr64 (MSR_HASWELL_UNC_PERF_GLOBAL_CTRL, Msr.Uint64);\r | |
| 1061 | @endcode\r | |
| e108c3f6 | 1062 | @note MSR_HASWELL_UNC_PERF_GLOBAL_CTRL is defined as MSR_UNC_PERF_GLOBAL_CTRL in SDM.\r |
| 7ae88a62 MK |
1063 | **/\r |
| 1064 | #define MSR_HASWELL_UNC_PERF_GLOBAL_CTRL 0x00000391\r | |
| 1065 | \r | |
| 1066 | /**\r | |
| 1067 | MSR information returned for MSR index #MSR_HASWELL_UNC_PERF_GLOBAL_CTRL\r | |
| 1068 | **/\r | |
| 1069 | typedef union {\r | |
| 1070 | ///\r | |
| 1071 | /// Individual bit fields\r | |
| 1072 | ///\r | |
| 1073 | struct {\r | |
| 1074 | ///\r | |
| 1075 | /// [Bit 0] Core 0 select.\r | |
| 1076 | ///\r | |
| 1077 | UINT32 PMI_Sel_Core0:1;\r | |
| 1078 | ///\r | |
| 1079 | /// [Bit 1] Core 1 select.\r | |
| 1080 | ///\r | |
| 1081 | UINT32 PMI_Sel_Core1:1;\r | |
| 1082 | ///\r | |
| 1083 | /// [Bit 2] Core 2 select.\r | |
| 1084 | ///\r | |
| 1085 | UINT32 PMI_Sel_Core2:1;\r | |
| 1086 | ///\r | |
| 1087 | /// [Bit 3] Core 3 select.\r | |
| 1088 | ///\r | |
| 1089 | UINT32 PMI_Sel_Core3:1;\r | |
| 1090 | UINT32 Reserved1:15;\r | |
| 1091 | UINT32 Reserved2:10;\r | |
| 1092 | ///\r | |
| 1093 | /// [Bit 29] Enable all uncore counters.\r | |
| 1094 | ///\r | |
| 1095 | UINT32 EN:1;\r | |
| 1096 | ///\r | |
| 1097 | /// [Bit 30] Enable wake on PMI.\r | |
| 1098 | ///\r | |
| 1099 | UINT32 WakePMI:1;\r | |
| 1100 | ///\r | |
| 1101 | /// [Bit 31] Enable Freezing counter when overflow.\r | |
| 1102 | ///\r | |
| 1103 | UINT32 FREEZE:1;\r | |
| 1104 | UINT32 Reserved3:32;\r | |
| 1105 | } Bits;\r | |
| 1106 | ///\r | |
| 1107 | /// All bit fields as a 32-bit value\r | |
| 1108 | ///\r | |
| 1109 | UINT32 Uint32;\r | |
| 1110 | ///\r | |
| 1111 | /// All bit fields as a 64-bit value\r | |
| 1112 | ///\r | |
| 1113 | UINT64 Uint64;\r | |
| 1114 | } MSR_HASWELL_UNC_PERF_GLOBAL_CTRL_REGISTER;\r | |
| 1115 | \r | |
| 1116 | \r | |
| 1117 | /**\r | |
| 1118 | Package. Uncore PMU main status.\r | |
| 1119 | \r | |
| 1120 | @param ECX MSR_HASWELL_UNC_PERF_GLOBAL_STATUS (0x00000392)\r | |
| 1121 | @param EAX Lower 32-bits of MSR value.\r | |
| 1122 | Described by the type MSR_HASWELL_UNC_PERF_GLOBAL_STATUS_REGISTER.\r | |
| 1123 | @param EDX Upper 32-bits of MSR value.\r | |
| 1124 | Described by the type MSR_HASWELL_UNC_PERF_GLOBAL_STATUS_REGISTER.\r | |
| 1125 | \r | |
| 1126 | <b>Example usage</b>\r | |
| 1127 | @code\r | |
| 1128 | MSR_HASWELL_UNC_PERF_GLOBAL_STATUS_REGISTER Msr;\r | |
| 1129 | \r | |
| 1130 | Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_UNC_PERF_GLOBAL_STATUS);\r | |
| 1131 | AsmWriteMsr64 (MSR_HASWELL_UNC_PERF_GLOBAL_STATUS, Msr.Uint64);\r | |
| 1132 | @endcode\r | |
| e108c3f6 | 1133 | @note MSR_HASWELL_UNC_PERF_GLOBAL_STATUS is defined as MSR_UNC_PERF_GLOBAL_STATUS in SDM.\r |
| 7ae88a62 MK |
1134 | **/\r |
| 1135 | #define MSR_HASWELL_UNC_PERF_GLOBAL_STATUS 0x00000392\r | |
| 1136 | \r | |
| 1137 | /**\r | |
| 1138 | MSR information returned for MSR index #MSR_HASWELL_UNC_PERF_GLOBAL_STATUS\r | |
| 1139 | **/\r | |
| 1140 | typedef union {\r | |
| 1141 | ///\r | |
| 1142 | /// Individual bit fields\r | |
| 1143 | ///\r | |
| 1144 | struct {\r | |
| 1145 | ///\r | |
| 1146 | /// [Bit 0] Fixed counter overflowed.\r | |
| 1147 | ///\r | |
| 1148 | UINT32 Fixed:1;\r | |
| 1149 | ///\r | |
| 1150 | /// [Bit 1] An ARB counter overflowed.\r | |
| 1151 | ///\r | |
| 1152 | UINT32 ARB:1;\r | |
| 1153 | UINT32 Reserved1:1;\r | |
| 1154 | ///\r | |
| 1155 | /// [Bit 3] A CBox counter overflowed (on any slice).\r | |
| 1156 | ///\r | |
| 1157 | UINT32 CBox:1;\r | |
| 1158 | UINT32 Reserved2:28;\r | |
| 1159 | UINT32 Reserved3:32;\r | |
| 1160 | } Bits;\r | |
| 1161 | ///\r | |
| 1162 | /// All bit fields as a 32-bit value\r | |
| 1163 | ///\r | |
| 1164 | UINT32 Uint32;\r | |
| 1165 | ///\r | |
| 1166 | /// All bit fields as a 64-bit value\r | |
| 1167 | ///\r | |
| 1168 | UINT64 Uint64;\r | |
| 1169 | } MSR_HASWELL_UNC_PERF_GLOBAL_STATUS_REGISTER;\r | |
| 1170 | \r | |
| 1171 | \r | |
| 1172 | /**\r | |
| 1173 | Package. Uncore fixed counter control (R/W).\r | |
| 1174 | \r | |
| 1175 | @param ECX MSR_HASWELL_UNC_PERF_FIXED_CTRL (0x00000394)\r | |
| 1176 | @param EAX Lower 32-bits of MSR value.\r | |
| 1177 | Described by the type MSR_HASWELL_UNC_PERF_FIXED_CTRL_REGISTER.\r | |
| 1178 | @param EDX Upper 32-bits of MSR value.\r | |
| 1179 | Described by the type MSR_HASWELL_UNC_PERF_FIXED_CTRL_REGISTER.\r | |
| 1180 | \r | |
| 1181 | <b>Example usage</b>\r | |
| 1182 | @code\r | |
| 1183 | MSR_HASWELL_UNC_PERF_FIXED_CTRL_REGISTER Msr;\r | |
| 1184 | \r | |
| 1185 | Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_UNC_PERF_FIXED_CTRL);\r | |
| 1186 | AsmWriteMsr64 (MSR_HASWELL_UNC_PERF_FIXED_CTRL, Msr.Uint64);\r | |
| 1187 | @endcode\r | |
| e108c3f6 | 1188 | @note MSR_HASWELL_UNC_PERF_FIXED_CTRL is defined as MSR_UNC_PERF_FIXED_CTRL in SDM.\r |
| 7ae88a62 MK |
1189 | **/\r |
| 1190 | #define MSR_HASWELL_UNC_PERF_FIXED_CTRL 0x00000394\r | |
| 1191 | \r | |
| 1192 | /**\r | |
| 1193 | MSR information returned for MSR index #MSR_HASWELL_UNC_PERF_FIXED_CTRL\r | |
| 1194 | **/\r | |
| 1195 | typedef union {\r | |
| 1196 | ///\r | |
| 1197 | /// Individual bit fields\r | |
| 1198 | ///\r | |
| 1199 | struct {\r | |
| 1200 | UINT32 Reserved1:20;\r | |
| 1201 | ///\r | |
| 1202 | /// [Bit 20] Enable overflow propagation.\r | |
| 1203 | ///\r | |
| 1204 | UINT32 EnableOverflow:1;\r | |
| 1205 | UINT32 Reserved2:1;\r | |
| 1206 | ///\r | |
| 1207 | /// [Bit 22] Enable counting.\r | |
| 1208 | ///\r | |
| 1209 | UINT32 EnableCounting:1;\r | |
| 1210 | UINT32 Reserved3:9;\r | |
| 1211 | UINT32 Reserved4:32;\r | |
| 1212 | } Bits;\r | |
| 1213 | ///\r | |
| 1214 | /// All bit fields as a 32-bit value\r | |
| 1215 | ///\r | |
| 1216 | UINT32 Uint32;\r | |
| 1217 | ///\r | |
| 1218 | /// All bit fields as a 64-bit value\r | |
| 1219 | ///\r | |
| 1220 | UINT64 Uint64;\r | |
| 1221 | } MSR_HASWELL_UNC_PERF_FIXED_CTRL_REGISTER;\r | |
| 1222 | \r | |
| 1223 | \r | |
| 1224 | /**\r | |
| 1225 | Package. Uncore fixed counter.\r | |
| 1226 | \r | |
| 1227 | @param ECX MSR_HASWELL_UNC_PERF_FIXED_CTR (0x00000395)\r | |
| 1228 | @param EAX Lower 32-bits of MSR value.\r | |
| 1229 | Described by the type MSR_HASWELL_UNC_PERF_FIXED_CTR_REGISTER.\r | |
| 1230 | @param EDX Upper 32-bits of MSR value.\r | |
| 1231 | Described by the type MSR_HASWELL_UNC_PERF_FIXED_CTR_REGISTER.\r | |
| 1232 | \r | |
| 1233 | <b>Example usage</b>\r | |
| 1234 | @code\r | |
| 1235 | MSR_HASWELL_UNC_PERF_FIXED_CTR_REGISTER Msr;\r | |
| 1236 | \r | |
| 1237 | Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_UNC_PERF_FIXED_CTR);\r | |
| 1238 | AsmWriteMsr64 (MSR_HASWELL_UNC_PERF_FIXED_CTR, Msr.Uint64);\r | |
| 1239 | @endcode\r | |
| e108c3f6 | 1240 | @note MSR_HASWELL_UNC_PERF_FIXED_CTR is defined as MSR_UNC_PERF_FIXED_CTR in SDM.\r |
| 7ae88a62 MK |
1241 | **/\r |
| 1242 | #define MSR_HASWELL_UNC_PERF_FIXED_CTR 0x00000395\r | |
| 1243 | \r | |
| 1244 | /**\r | |
| 1245 | MSR information returned for MSR index #MSR_HASWELL_UNC_PERF_FIXED_CTR\r | |
| 1246 | **/\r | |
| 1247 | typedef union {\r | |
| 1248 | ///\r | |
| 1249 | /// Individual bit fields\r | |
| 1250 | ///\r | |
| 1251 | struct {\r | |
| 1252 | ///\r | |
| 1253 | /// [Bits 31:0] Current count.\r | |
| 1254 | ///\r | |
| 1255 | UINT32 CurrentCount:32;\r | |
| 1256 | ///\r | |
| 1257 | /// [Bits 47:32] Current count.\r | |
| 1258 | ///\r | |
| 1259 | UINT32 CurrentCountHi:16;\r | |
| 1260 | UINT32 Reserved:16;\r | |
| 1261 | } Bits;\r | |
| 1262 | ///\r | |
| 1263 | /// All bit fields as a 64-bit value\r | |
| 1264 | ///\r | |
| 1265 | UINT64 Uint64;\r | |
| 1266 | } MSR_HASWELL_UNC_PERF_FIXED_CTR_REGISTER;\r | |
| 1267 | \r | |
| 1268 | \r | |
| 1269 | /**\r | |
| 1270 | Package. Uncore C-Box configuration information (R/O).\r | |
| 1271 | \r | |
| 1272 | @param ECX MSR_HASWELL_UNC_CBO_CONFIG (0x00000396)\r | |
| 1273 | @param EAX Lower 32-bits of MSR value.\r | |
| 1274 | Described by the type MSR_HASWELL_UNC_CBO_CONFIG_REGISTER.\r | |
| 1275 | @param EDX Upper 32-bits of MSR value.\r | |
| 1276 | Described by the type MSR_HASWELL_UNC_CBO_CONFIG_REGISTER.\r | |
| 1277 | \r | |
| 1278 | <b>Example usage</b>\r | |
| 1279 | @code\r | |
| 1280 | MSR_HASWELL_UNC_CBO_CONFIG_REGISTER Msr;\r | |
| 1281 | \r | |
| 1282 | Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_CONFIG);\r | |
| 1283 | @endcode\r | |
| e108c3f6 | 1284 | @note MSR_HASWELL_UNC_CBO_CONFIG is defined as MSR_UNC_CBO_CONFIG in SDM.\r |
| 7ae88a62 MK |
1285 | **/\r |
| 1286 | #define MSR_HASWELL_UNC_CBO_CONFIG 0x00000396\r | |
| 1287 | \r | |
| 1288 | /**\r | |
| 1289 | MSR information returned for MSR index #MSR_HASWELL_UNC_CBO_CONFIG\r | |
| 1290 | **/\r | |
| 1291 | typedef union {\r | |
| 1292 | ///\r | |
| 1293 | /// Individual bit fields\r | |
| 1294 | ///\r | |
| 1295 | struct {\r | |
| 1296 | ///\r | |
| 1297 | /// [Bits 3:0] Encoded number of C-Box, derive value by "-1".\r | |
| 1298 | ///\r | |
| 1299 | UINT32 CBox:4;\r | |
| 1300 | UINT32 Reserved1:28;\r | |
| 1301 | UINT32 Reserved2:32;\r | |
| 1302 | } Bits;\r | |
| 1303 | ///\r | |
| 1304 | /// All bit fields as a 32-bit value\r | |
| 1305 | ///\r | |
| 1306 | UINT32 Uint32;\r | |
| 1307 | ///\r | |
| 1308 | /// All bit fields as a 64-bit value\r | |
| 1309 | ///\r | |
| 1310 | UINT64 Uint64;\r | |
| 1311 | } MSR_HASWELL_UNC_CBO_CONFIG_REGISTER;\r | |
| 1312 | \r | |
| 1313 | \r | |
| 1314 | /**\r | |
| 1315 | Package. Uncore Arb unit, performance counter 0.\r | |
| 1316 | \r | |
| 1317 | @param ECX MSR_HASWELL_UNC_ARB_PERFCTR0 (0x000003B0)\r | |
| 1318 | @param EAX Lower 32-bits of MSR value.\r | |
| 1319 | @param EDX Upper 32-bits of MSR value.\r | |
| 1320 | \r | |
| 1321 | <b>Example usage</b>\r | |
| 1322 | @code\r | |
| 1323 | UINT64 Msr;\r | |
| 1324 | \r | |
| 1325 | Msr = AsmReadMsr64 (MSR_HASWELL_UNC_ARB_PERFCTR0);\r | |
| 1326 | AsmWriteMsr64 (MSR_HASWELL_UNC_ARB_PERFCTR0, Msr);\r | |
| 1327 | @endcode\r | |
| e108c3f6 | 1328 | @note MSR_HASWELL_UNC_ARB_PERFCTR0 is defined as MSR_UNC_ARB_PERFCTR0 in SDM.\r |
| 7ae88a62 MK |
1329 | **/\r |
| 1330 | #define MSR_HASWELL_UNC_ARB_PERFCTR0 0x000003B0\r | |
| 1331 | \r | |
| 1332 | \r | |
| 1333 | /**\r | |
| 1334 | Package. Uncore Arb unit, performance counter 1.\r | |
| 1335 | \r | |
| 1336 | @param ECX MSR_HASWELL_UNC_ARB_PERFCTR1 (0x000003B1)\r | |
| 1337 | @param EAX Lower 32-bits of MSR value.\r | |
| 1338 | @param EDX Upper 32-bits of MSR value.\r | |
| 1339 | \r | |
| 1340 | <b>Example usage</b>\r | |
| 1341 | @code\r | |
| 1342 | UINT64 Msr;\r | |
| 1343 | \r | |
| 1344 | Msr = AsmReadMsr64 (MSR_HASWELL_UNC_ARB_PERFCTR1);\r | |
| 1345 | AsmWriteMsr64 (MSR_HASWELL_UNC_ARB_PERFCTR1, Msr);\r | |
| 1346 | @endcode\r | |
| e108c3f6 | 1347 | @note MSR_HASWELL_UNC_ARB_PERFCTR1 is defined as MSR_UNC_ARB_PERFCTR1 in SDM.\r |
| 7ae88a62 MK |
1348 | **/\r |
| 1349 | #define MSR_HASWELL_UNC_ARB_PERFCTR1 0x000003B1\r | |
| 1350 | \r | |
| 1351 | \r | |
| 1352 | /**\r | |
| 1353 | Package. Uncore Arb unit, counter 0 event select MSR.\r | |
| 1354 | \r | |
| 1355 | @param ECX MSR_HASWELL_UNC_ARB_PERFEVTSEL0 (0x000003B2)\r | |
| 1356 | @param EAX Lower 32-bits of MSR value.\r | |
| 1357 | @param EDX Upper 32-bits of MSR value.\r | |
| 1358 | \r | |
| 1359 | <b>Example usage</b>\r | |
| 1360 | @code\r | |
| 1361 | UINT64 Msr;\r | |
| 1362 | \r | |
| 1363 | Msr = AsmReadMsr64 (MSR_HASWELL_UNC_ARB_PERFEVTSEL0);\r | |
| 1364 | AsmWriteMsr64 (MSR_HASWELL_UNC_ARB_PERFEVTSEL0, Msr);\r | |
| 1365 | @endcode\r | |
| e108c3f6 | 1366 | @note MSR_HASWELL_UNC_ARB_PERFEVTSEL0 is defined as MSR_UNC_ARB_PERFEVTSEL0 in SDM.\r |
| 7ae88a62 MK |
1367 | **/\r |
| 1368 | #define MSR_HASWELL_UNC_ARB_PERFEVTSEL0 0x000003B2\r | |
| 1369 | \r | |
| 1370 | \r | |
| 1371 | /**\r | |
| 1372 | Package. Uncore Arb unit, counter 1 event select MSR.\r | |
| 1373 | \r | |
| 1374 | @param ECX MSR_HASWELL_UNC_ARB_PERFEVTSEL1 (0x000003B3)\r | |
| 1375 | @param EAX Lower 32-bits of MSR value.\r | |
| 1376 | @param EDX Upper 32-bits of MSR value.\r | |
| 1377 | \r | |
| 1378 | <b>Example usage</b>\r | |
| 1379 | @code\r | |
| 1380 | UINT64 Msr;\r | |
| 1381 | \r | |
| 1382 | Msr = AsmReadMsr64 (MSR_HASWELL_UNC_ARB_PERFEVTSEL1);\r | |
| 1383 | AsmWriteMsr64 (MSR_HASWELL_UNC_ARB_PERFEVTSEL1, Msr);\r | |
| 1384 | @endcode\r | |
| e108c3f6 | 1385 | @note MSR_HASWELL_UNC_ARB_PERFEVTSEL1 is defined as MSR_UNC_ARB_PERFEVTSEL1 in SDM.\r |
| 7ae88a62 MK |
1386 | **/\r |
| 1387 | #define MSR_HASWELL_UNC_ARB_PERFEVTSEL1 0x000003B3\r | |
| 1388 | \r | |
| 1389 | \r | |
| 1390 | /**\r | |
| 1391 | Package. Enhanced SMM Feature Control (SMM-RW) Reports SMM capability\r | |
| 1392 | Enhancement. Accessible only while in SMM.\r | |
| 1393 | \r | |
| 1394 | @param ECX MSR_HASWELL_SMM_FEATURE_CONTROL (0x000004E0)\r | |
| 1395 | @param EAX Lower 32-bits of MSR value.\r | |
| 1396 | Described by the type MSR_HASWELL_SMM_FEATURE_CONTROL_REGISTER.\r | |
| 1397 | @param EDX Upper 32-bits of MSR value.\r | |
| 1398 | Described by the type MSR_HASWELL_SMM_FEATURE_CONTROL_REGISTER.\r | |
| 1399 | \r | |
| 1400 | <b>Example usage</b>\r | |
| 1401 | @code\r | |
| 1402 | MSR_HASWELL_SMM_FEATURE_CONTROL_REGISTER Msr;\r | |
| 1403 | \r | |
| 1404 | Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_SMM_FEATURE_CONTROL);\r | |
| 1405 | AsmWriteMsr64 (MSR_HASWELL_SMM_FEATURE_CONTROL, Msr.Uint64);\r | |
| 1406 | @endcode\r | |
| e108c3f6 | 1407 | @note MSR_HASWELL_SMM_FEATURE_CONTROL is defined as MSR_SMM_FEATURE_CONTROL in SDM.\r |
| 7ae88a62 MK |
1408 | **/\r |
| 1409 | #define MSR_HASWELL_SMM_FEATURE_CONTROL 0x000004E0\r | |
| 1410 | \r | |
| 1411 | /**\r | |
| 1412 | MSR information returned for MSR index #MSR_HASWELL_SMM_FEATURE_CONTROL\r | |
| 1413 | **/\r | |
| 1414 | typedef union {\r | |
| 1415 | ///\r | |
| 1416 | /// Individual bit fields\r | |
| 1417 | ///\r | |
| 1418 | struct {\r | |
| 1419 | ///\r | |
| 1420 | /// [Bit 0] Lock (SMM-RWO) When set to '1' locks this register from\r | |
| 1421 | /// further changes.\r | |
| 1422 | ///\r | |
| 1423 | UINT32 Lock:1;\r | |
| 1424 | UINT32 Reserved1:1;\r | |
| 1425 | ///\r | |
| 1426 | /// [Bit 2] SMM_Code_Chk_En (SMM-RW) This control bit is available only if\r | |
| 1427 | /// MSR_SMM_MCA_CAP[58] == 1. When set to '0' (default) none of the\r | |
| 1428 | /// logical processors are prevented from executing SMM code outside the\r | |
| 1429 | /// ranges defined by the SMRR. When set to '1' any logical processor in\r | |
| 1430 | /// the package that attempts to execute SMM code not within the ranges\r | |
| 1431 | /// defined by the SMRR will assert an unrecoverable MCE.\r | |
| 1432 | ///\r | |
| 1433 | UINT32 SMM_Code_Chk_En:1;\r | |
| 1434 | UINT32 Reserved2:29;\r | |
| 1435 | UINT32 Reserved3:32;\r | |
| 1436 | } Bits;\r | |
| 1437 | ///\r | |
| 1438 | /// All bit fields as a 32-bit value\r | |
| 1439 | ///\r | |
| 1440 | UINT32 Uint32;\r | |
| 1441 | ///\r | |
| 1442 | /// All bit fields as a 64-bit value\r | |
| 1443 | ///\r | |
| 1444 | UINT64 Uint64;\r | |
| 1445 | } MSR_HASWELL_SMM_FEATURE_CONTROL_REGISTER;\r | |
| 1446 | \r | |
| 1447 | \r | |
| 1448 | /**\r | |
| 1449 | Package. SMM Delayed (SMM-RO) Reports the interruptible state of all logical\r | |
| 1450 | processors in the package. Available only while in SMM and\r | |
| 1451 | MSR_SMM_MCA_CAP[LONG_FLOW_INDICATION] == 1.\r | |
| 1452 | \r | |
| 1453 | [Bits 31:0] LOG_PROC_STATE (SMM-RO) Each bit represents a logical\r | |
| 1454 | processor of its state in a long flow of internal operation which\r | |
| 1455 | delays servicing an interrupt. The corresponding bit will be set at\r | |
| 1456 | the start of long events such as: Microcode Update Load, C6, WBINVD,\r | |
| 1457 | Ratio Change, Throttle. The bit is automatically cleared at the end of\r | |
| 1458 | each long event. The reset value of this field is 0. Only bit\r | |
| 1459 | positions below N = CPUID.(EAX=0BH, ECX=PKG_LVL):EBX[15:0] can be\r | |
| 1460 | updated.\r | |
| 1461 | \r | |
| 1462 | [Bits 63:32] LOG_PROC_STATE (SMM-RO) Each bit represents a logical\r | |
| 1463 | processor of its state in a long flow of internal operation which\r | |
| 1464 | delays servicing an interrupt. The corresponding bit will be set at\r | |
| 1465 | the start of long events such as: Microcode Update Load, C6, WBINVD,\r | |
| 1466 | Ratio Change, Throttle. The bit is automatically cleared at the end of\r | |
| 1467 | each long event. The reset value of this field is 0. Only bit\r | |
| 1468 | positions below N = CPUID.(EAX=0BH, ECX=PKG_LVL):EBX[15:0] can be\r | |
| 1469 | updated.\r | |
| 1470 | \r | |
| 1471 | @param ECX MSR_HASWELL_SMM_DELAYED (0x000004E2)\r | |
| 1472 | @param EAX Lower 32-bits of MSR value.\r | |
| 1473 | @param EDX Upper 32-bits of MSR value.\r | |
| 1474 | \r | |
| 1475 | <b>Example usage</b>\r | |
| 1476 | @code\r | |
| 1477 | UINT64 Msr;\r | |
| 1478 | \r | |
| 1479 | Msr = AsmReadMsr64 (MSR_HASWELL_SMM_DELAYED);\r | |
| 1480 | @endcode\r | |
| e108c3f6 | 1481 | @note MSR_HASWELL_SMM_DELAYED is defined as MSR_SMM_DELAYED in SDM.\r |
| 7ae88a62 MK |
1482 | **/\r |
| 1483 | #define MSR_HASWELL_SMM_DELAYED 0x000004E2\r | |
| 1484 | \r | |
| 1485 | \r | |
| 1486 | /**\r | |
| 1487 | Package. SMM Blocked (SMM-RO) Reports the blocked state of all logical\r | |
| 1488 | processors in the package. Available only while in SMM.\r | |
| 1489 | \r | |
| 1490 | [Bits 31:0] LOG_PROC_STATE (SMM-RO) Each bit represents a logical\r | |
| 1491 | processor of its blocked state to service an SMI. The corresponding\r | |
| 1492 | bit will be set if the logical processor is in one of the following\r | |
| 1493 | states: Wait For SIPI or SENTER Sleep. The reset value of this field\r | |
| 1494 | is 0FFFH. Only bit positions below N = CPUID.(EAX=0BH,\r | |
| 1495 | ECX=PKG_LVL):EBX[15:0] can be updated.\r | |
| 1496 | \r | |
| 1497 | \r | |
| 1498 | [Bits 63:32] LOG_PROC_STATE (SMM-RO) Each bit represents a logical\r | |
| 1499 | processor of its blocked state to service an SMI. The corresponding\r | |
| 1500 | bit will be set if the logical processor is in one of the following\r | |
| 1501 | states: Wait For SIPI or SENTER Sleep. The reset value of this field\r | |
| 1502 | is 0FFFH. Only bit positions below N = CPUID.(EAX=0BH,\r | |
| 1503 | ECX=PKG_LVL):EBX[15:0] can be updated.\r | |
| 1504 | \r | |
| 1505 | @param ECX MSR_HASWELL_SMM_BLOCKED (0x000004E3)\r | |
| 1506 | @param EAX Lower 32-bits of MSR value.\r | |
| 1507 | @param EDX Upper 32-bits of MSR value.\r | |
| 1508 | \r | |
| 1509 | <b>Example usage</b>\r | |
| 1510 | @code\r | |
| 1511 | UINT64 Msr;\r | |
| 1512 | \r | |
| 1513 | Msr = AsmReadMsr64 (MSR_HASWELL_SMM_BLOCKED);\r | |
| 1514 | @endcode\r | |
| e108c3f6 | 1515 | @note MSR_HASWELL_SMM_BLOCKED is defined as MSR_SMM_BLOCKED in SDM.\r |
| 7ae88a62 MK |
1516 | **/\r |
| 1517 | #define MSR_HASWELL_SMM_BLOCKED 0x000004E3\r | |
| 1518 | \r | |
| 1519 | \r | |
| 1520 | /**\r | |
| 1521 | Package. Unit Multipliers used in RAPL Interfaces (R/O).\r | |
| 1522 | \r | |
| 1523 | @param ECX MSR_HASWELL_RAPL_POWER_UNIT (0x00000606)\r | |
| 1524 | @param EAX Lower 32-bits of MSR value.\r | |
| 1525 | Described by the type MSR_HASWELL_RAPL_POWER_UNIT_REGISTER.\r | |
| 1526 | @param EDX Upper 32-bits of MSR value.\r | |
| 1527 | Described by the type MSR_HASWELL_RAPL_POWER_UNIT_REGISTER.\r | |
| 1528 | \r | |
| 1529 | <b>Example usage</b>\r | |
| 1530 | @code\r | |
| 1531 | MSR_HASWELL_RAPL_POWER_UNIT_REGISTER Msr;\r | |
| 1532 | \r | |
| 1533 | Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_RAPL_POWER_UNIT);\r | |
| 1534 | @endcode\r | |
| e108c3f6 | 1535 | @note MSR_HASWELL_RAPL_POWER_UNIT is defined as MSR_RAPL_POWER_UNIT in SDM.\r |
| 7ae88a62 MK |
1536 | **/\r |
| 1537 | #define MSR_HASWELL_RAPL_POWER_UNIT 0x00000606\r | |
| 1538 | \r | |
| 1539 | /**\r | |
| 1540 | MSR information returned for MSR index #MSR_HASWELL_RAPL_POWER_UNIT\r | |
| 1541 | **/\r | |
| 1542 | typedef union {\r | |
| 1543 | ///\r | |
| 1544 | /// Individual bit fields\r | |
| 1545 | ///\r | |
| 1546 | struct {\r | |
| 1547 | ///\r | |
| 1548 | /// [Bits 3:0] Package. Power Units See Section 14.9.1, "RAPL Interfaces.".\r | |
| 1549 | ///\r | |
| 1550 | UINT32 PowerUnits:4;\r | |
| 1551 | UINT32 Reserved1:4;\r | |
| 1552 | ///\r | |
| 1553 | /// [Bits 12:8] Package. Energy Status Units Energy related information\r | |
| 1554 | /// (in Joules) is based on the multiplier, 1/2^ESU; where ESU is an\r | |
| 1555 | /// unsigned integer represented by bits 12:8. Default value is 0EH (or 61\r | |
| 1556 | /// micro-joules).\r | |
| 1557 | ///\r | |
| 1558 | UINT32 EnergyStatusUnits:5;\r | |
| 1559 | UINT32 Reserved2:3;\r | |
| 1560 | ///\r | |
| 1561 | /// [Bits 19:16] Package. Time Units See Section 14.9.1, "RAPL\r | |
| 1562 | /// Interfaces.".\r | |
| 1563 | ///\r | |
| 1564 | UINT32 TimeUnits:4;\r | |
| 1565 | UINT32 Reserved3:12;\r | |
| 1566 | UINT32 Reserved4:32;\r | |
| 1567 | } Bits;\r | |
| 1568 | ///\r | |
| 1569 | /// All bit fields as a 32-bit value\r | |
| 1570 | ///\r | |
| 1571 | UINT32 Uint32;\r | |
| 1572 | ///\r | |
| 1573 | /// All bit fields as a 64-bit value\r | |
| 1574 | ///\r | |
| 1575 | UINT64 Uint64;\r | |
| 1576 | } MSR_HASWELL_RAPL_POWER_UNIT_REGISTER;\r | |
| 1577 | \r | |
| 1578 | \r | |
| 0f16be6d HW |
1579 | /**\r |
| 1580 | Package. PP0 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL\r | |
| 1581 | Domains.".\r | |
| 1582 | \r | |
| 1583 | @param ECX MSR_HASWELL_PP0_ENERGY_STATUS (0x00000639)\r | |
| 1584 | @param EAX Lower 32-bits of MSR value.\r | |
| 1585 | @param EDX Upper 32-bits of MSR value.\r | |
| 1586 | \r | |
| 1587 | <b>Example usage</b>\r | |
| 1588 | @code\r | |
| 1589 | UINT64 Msr;\r | |
| 1590 | \r | |
| 1591 | Msr = AsmReadMsr64 (MSR_HASWELL_PP0_ENERGY_STATUS);\r | |
| 1592 | @endcode\r | |
| 1593 | @note MSR_HASWELL_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM.\r | |
| 1594 | **/\r | |
| 1595 | #define MSR_HASWELL_PP0_ENERGY_STATUS 0x00000639\r | |
| 1596 | \r | |
| 1597 | \r | |
| 7ae88a62 MK |
1598 | /**\r |
| 1599 | Package. PP1 RAPL Power Limit Control (R/W) See Section 14.9.4, "PP0/PP1\r | |
| 1600 | RAPL Domains.".\r | |
| 1601 | \r | |
| 1602 | @param ECX MSR_HASWELL_PP1_POWER_LIMIT (0x00000640)\r | |
| 1603 | @param EAX Lower 32-bits of MSR value.\r | |
| 1604 | @param EDX Upper 32-bits of MSR value.\r | |
| 1605 | \r | |
| 1606 | <b>Example usage</b>\r | |
| 1607 | @code\r | |
| 1608 | UINT64 Msr;\r | |
| 1609 | \r | |
| 1610 | Msr = AsmReadMsr64 (MSR_HASWELL_PP1_POWER_LIMIT);\r | |
| 1611 | AsmWriteMsr64 (MSR_HASWELL_PP1_POWER_LIMIT, Msr);\r | |
| 1612 | @endcode\r | |
| e108c3f6 | 1613 | @note MSR_HASWELL_PP1_POWER_LIMIT is defined as MSR_PP1_POWER_LIMIT in SDM.\r |
| 7ae88a62 MK |
1614 | **/\r |
| 1615 | #define MSR_HASWELL_PP1_POWER_LIMIT 0x00000640\r | |
| 1616 | \r | |
| 1617 | \r | |
| 1618 | /**\r | |
| 1619 | Package. PP1 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL\r | |
| 1620 | Domains.".\r | |
| 1621 | \r | |
| 1622 | @param ECX MSR_HASWELL_PP1_ENERGY_STATUS (0x00000641)\r | |
| 1623 | @param EAX Lower 32-bits of MSR value.\r | |
| 1624 | @param EDX Upper 32-bits of MSR value.\r | |
| 1625 | \r | |
| 1626 | <b>Example usage</b>\r | |
| 1627 | @code\r | |
| 1628 | UINT64 Msr;\r | |
| 1629 | \r | |
| 1630 | Msr = AsmReadMsr64 (MSR_HASWELL_PP1_ENERGY_STATUS);\r | |
| 1631 | @endcode\r | |
| e108c3f6 | 1632 | @note MSR_HASWELL_PP1_ENERGY_STATUS is defined as MSR_PP1_ENERGY_STATUS in SDM.\r |
| 7ae88a62 MK |
1633 | **/\r |
| 1634 | #define MSR_HASWELL_PP1_ENERGY_STATUS 0x00000641\r | |
| 1635 | \r | |
| 1636 | \r | |
| 1637 | /**\r | |
| 1638 | Package. PP1 Balance Policy (R/W) See Section 14.9.4, "PP0/PP1 RAPL\r | |
| 1639 | Domains.".\r | |
| 1640 | \r | |
| 1641 | @param ECX MSR_HASWELL_PP1_POLICY (0x00000642)\r | |
| 1642 | @param EAX Lower 32-bits of MSR value.\r | |
| 1643 | @param EDX Upper 32-bits of MSR value.\r | |
| 1644 | \r | |
| 1645 | <b>Example usage</b>\r | |
| 1646 | @code\r | |
| 1647 | UINT64 Msr;\r | |
| 1648 | \r | |
| 1649 | Msr = AsmReadMsr64 (MSR_HASWELL_PP1_POLICY);\r | |
| 1650 | AsmWriteMsr64 (MSR_HASWELL_PP1_POLICY, Msr);\r | |
| 1651 | @endcode\r | |
| e108c3f6 | 1652 | @note MSR_HASWELL_PP1_POLICY is defined as MSR_PP1_POLICY in SDM.\r |
| 7ae88a62 MK |
1653 | **/\r |
| 1654 | #define MSR_HASWELL_PP1_POLICY 0x00000642\r | |
| 1655 | \r | |
| 1656 | \r | |
| 1657 | /**\r | |
| 1658 | Package. Indicator of Frequency Clipping in Processor Cores (R/W) (frequency\r | |
| 1659 | refers to processor core frequency).\r | |
| 1660 | \r | |
| 1661 | @param ECX MSR_HASWELL_CORE_PERF_LIMIT_REASONS (0x00000690)\r | |
| 1662 | @param EAX Lower 32-bits of MSR value.\r | |
| 1663 | Described by the type MSR_HASWELL_CORE_PERF_LIMIT_REASONS_REGISTER.\r | |
| 1664 | @param EDX Upper 32-bits of MSR value.\r | |
| 1665 | Described by the type MSR_HASWELL_CORE_PERF_LIMIT_REASONS_REGISTER.\r | |
| 1666 | \r | |
| 1667 | <b>Example usage</b>\r | |
| 1668 | @code\r | |
| 1669 | MSR_HASWELL_CORE_PERF_LIMIT_REASONS_REGISTER Msr;\r | |
| 1670 | \r | |
| 1671 | Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_CORE_PERF_LIMIT_REASONS);\r | |
| 1672 | AsmWriteMsr64 (MSR_HASWELL_CORE_PERF_LIMIT_REASONS, Msr.Uint64);\r | |
| 1673 | @endcode\r | |
| e108c3f6 | 1674 | @note MSR_HASWELL_CORE_PERF_LIMIT_REASONS is defined as MSR_CORE_PERF_LIMIT_REASONS in SDM.\r |
| 7ae88a62 MK |
1675 | **/\r |
| 1676 | #define MSR_HASWELL_CORE_PERF_LIMIT_REASONS 0x00000690\r | |
| 1677 | \r | |
| 1678 | /**\r | |
| 1679 | MSR information returned for MSR index #MSR_HASWELL_CORE_PERF_LIMIT_REASONS\r | |
| 1680 | **/\r | |
| 1681 | typedef union {\r | |
| 1682 | ///\r | |
| 1683 | /// Individual bit fields\r | |
| 1684 | ///\r | |
| 1685 | struct {\r | |
| 1686 | ///\r | |
| 1687 | /// [Bit 0] PROCHOT Status (R0) When set, processor core frequency is\r | |
| 1688 | /// reduced below the operating system request due to assertion of\r | |
| 1689 | /// external PROCHOT.\r | |
| 1690 | ///\r | |
| 1691 | UINT32 PROCHOT_Status:1;\r | |
| 1692 | ///\r | |
| 1693 | /// [Bit 1] Thermal Status (R0) When set, frequency is reduced below the\r | |
| 1694 | /// operating system request due to a thermal event.\r | |
| 1695 | ///\r | |
| 1696 | UINT32 ThermalStatus:1;\r | |
| 1697 | UINT32 Reserved1:2;\r | |
| 1698 | ///\r | |
| 1699 | /// [Bit 4] Graphics Driver Status (R0) When set, frequency is reduced\r | |
| 1700 | /// below the operating system request due to Processor Graphics driver\r | |
| 1701 | /// override.\r | |
| 1702 | ///\r | |
| 1703 | UINT32 GraphicsDriverStatus:1;\r | |
| 1704 | ///\r | |
| 1705 | /// [Bit 5] Autonomous Utilization-Based Frequency Control Status (R0)\r | |
| 1706 | /// When set, frequency is reduced below the operating system request\r | |
| 1707 | /// because the processor has detected that utilization is low.\r | |
| 1708 | ///\r | |
| 1709 | UINT32 AutonomousUtilizationBasedFrequencyControlStatus:1;\r | |
| 1710 | ///\r | |
| 1711 | /// [Bit 6] VR Therm Alert Status (R0) When set, frequency is reduced\r | |
| 1712 | /// below the operating system request due to a thermal alert from the\r | |
| 1713 | /// Voltage Regulator.\r | |
| 1714 | ///\r | |
| 1715 | UINT32 VRThermAlertStatus:1;\r | |
| 1716 | UINT32 Reserved2:1;\r | |
| 1717 | ///\r | |
| 1718 | /// [Bit 8] Electrical Design Point Status (R0) When set, frequency is\r | |
| 1719 | /// reduced below the operating system request due to electrical design\r | |
| 1720 | /// point constraints (e.g. maximum electrical current consumption).\r | |
| 1721 | ///\r | |
| 1722 | UINT32 ElectricalDesignPointStatus:1;\r | |
| 1723 | ///\r | |
| 1724 | /// [Bit 9] Core Power Limiting Status (R0) When set, frequency is reduced\r | |
| 1725 | /// below the operating system request due to domain-level power limiting.\r | |
| 1726 | ///\r | |
| 1727 | UINT32 PLStatus:1;\r | |
| 1728 | ///\r | |
| 1729 | /// [Bit 10] Package-Level Power Limiting PL1 Status (R0) When set,\r | |
| 1730 | /// frequency is reduced below the operating system request due to\r | |
| 1731 | /// package-level power limiting PL1.\r | |
| 1732 | ///\r | |
| 1733 | UINT32 PL1Status:1;\r | |
| 1734 | ///\r | |
| 1735 | /// [Bit 11] Package-Level PL2 Power Limiting Status (R0) When set,\r | |
| 1736 | /// frequency is reduced below the operating system request due to\r | |
| 1737 | /// package-level power limiting PL2.\r | |
| 1738 | ///\r | |
| 1739 | UINT32 PL2Status:1;\r | |
| 1740 | ///\r | |
| 1741 | /// [Bit 12] Max Turbo Limit Status (R0) When set, frequency is reduced\r | |
| 1742 | /// below the operating system request due to multi-core turbo limits.\r | |
| 1743 | ///\r | |
| 1744 | UINT32 MaxTurboLimitStatus:1;\r | |
| 1745 | ///\r | |
| 1746 | /// [Bit 13] Turbo Transition Attenuation Status (R0) When set, frequency\r | |
| 1747 | /// is reduced below the operating system request due to Turbo transition\r | |
| 1748 | /// attenuation. This prevents performance degradation due to frequent\r | |
| 1749 | /// operating ratio changes.\r | |
| 1750 | ///\r | |
| 1751 | UINT32 TurboTransitionAttenuationStatus:1;\r | |
| 1752 | UINT32 Reserved3:2;\r | |
| 1753 | ///\r | |
| 1754 | /// [Bit 16] PROCHOT Log When set, indicates that the PROCHOT Status bit\r | |
| 1755 | /// has asserted since the log bit was last cleared. This log bit will\r | |
| 1756 | /// remain set until cleared by software writing 0.\r | |
| 1757 | ///\r | |
| 1758 | UINT32 PROCHOT_Log:1;\r | |
| 1759 | ///\r | |
| 1760 | /// [Bit 17] Thermal Log When set, indicates that the Thermal Status bit\r | |
| 1761 | /// has asserted since the log bit was last cleared. This log bit will\r | |
| 1762 | /// remain set until cleared by software writing 0.\r | |
| 1763 | ///\r | |
| 1764 | UINT32 ThermalLog:1;\r | |
| 1765 | UINT32 Reserved4:2;\r | |
| 1766 | ///\r | |
| 1767 | /// [Bit 20] Graphics Driver Log When set, indicates that the Graphics\r | |
| 1768 | /// Driver Status bit has asserted since the log bit was last cleared.\r | |
| 1769 | /// This log bit will remain set until cleared by software writing 0.\r | |
| 1770 | ///\r | |
| 1771 | UINT32 GraphicsDriverLog:1;\r | |
| 1772 | ///\r | |
| 1773 | /// [Bit 21] Autonomous Utilization-Based Frequency Control Log When set,\r | |
| 1774 | /// indicates that the Autonomous Utilization-Based Frequency Control\r | |
| 1775 | /// Status bit has asserted since the log bit was last cleared. This log\r | |
| 1776 | /// bit will remain set until cleared by software writing 0.\r | |
| 1777 | ///\r | |
| 1778 | UINT32 AutonomousUtilizationBasedFrequencyControlLog:1;\r | |
| 1779 | ///\r | |
| 1780 | /// [Bit 22] VR Therm Alert Log When set, indicates that the VR Therm\r | |
| 1781 | /// Alert Status bit has asserted since the log bit was last cleared. This\r | |
| 1782 | /// log bit will remain set until cleared by software writing 0.\r | |
| 1783 | ///\r | |
| 1784 | UINT32 VRThermAlertLog:1;\r | |
| 1785 | UINT32 Reserved5:1;\r | |
| 1786 | ///\r | |
| 1787 | /// [Bit 24] Electrical Design Point Log When set, indicates that the EDP\r | |
| 1788 | /// Status bit has asserted since the log bit was last cleared. This log\r | |
| 1789 | /// bit will remain set until cleared by software writing 0.\r | |
| 1790 | ///\r | |
| 1791 | UINT32 ElectricalDesignPointLog:1;\r | |
| 1792 | ///\r | |
| 1793 | /// [Bit 25] Core Power Limiting Log When set, indicates that the Core\r | |
| 1794 | /// Power Limiting Status bit has asserted since the log bit was last\r | |
| 1795 | /// cleared. This log bit will remain set until cleared by software\r | |
| 1796 | /// writing 0.\r | |
| 1797 | ///\r | |
| 1798 | UINT32 PLLog:1;\r | |
| 1799 | ///\r | |
| 1800 | /// [Bit 26] Package-Level PL1 Power Limiting Log When set, indicates\r | |
| 1801 | /// that the Package Level PL1 Power Limiting Status bit has asserted\r | |
| 1802 | /// since the log bit was last cleared. This log bit will remain set until\r | |
| 1803 | /// cleared by software writing 0.\r | |
| 1804 | ///\r | |
| 1805 | UINT32 PL1Log:1;\r | |
| 1806 | ///\r | |
| 1807 | /// [Bit 27] Package-Level PL2 Power Limiting Log When set, indicates that\r | |
| 1808 | /// the Package Level PL2 Power Limiting Status bit has asserted since the\r | |
| 1809 | /// log bit was last cleared. This log bit will remain set until cleared\r | |
| 1810 | /// by software writing 0.\r | |
| 1811 | ///\r | |
| 1812 | UINT32 PL2Log:1;\r | |
| 1813 | ///\r | |
| 1814 | /// [Bit 28] Max Turbo Limit Log When set, indicates that the Max Turbo\r | |
| 1815 | /// Limit Status bit has asserted since the log bit was last cleared. This\r | |
| 1816 | /// log bit will remain set until cleared by software writing 0.\r | |
| 1817 | ///\r | |
| 1818 | UINT32 MaxTurboLimitLog:1;\r | |
| 1819 | ///\r | |
| 1820 | /// [Bit 29] Turbo Transition Attenuation Log When set, indicates that the\r | |
| 1821 | /// Turbo Transition Attenuation Status bit has asserted since the log bit\r | |
| 1822 | /// was last cleared. This log bit will remain set until cleared by\r | |
| 1823 | /// software writing 0.\r | |
| 1824 | ///\r | |
| 1825 | UINT32 TurboTransitionAttenuationLog:1;\r | |
| 1826 | UINT32 Reserved6:2;\r | |
| 1827 | UINT32 Reserved7:32;\r | |
| 1828 | } Bits;\r | |
| 1829 | ///\r | |
| 1830 | /// All bit fields as a 32-bit value\r | |
| 1831 | ///\r | |
| 1832 | UINT32 Uint32;\r | |
| 1833 | ///\r | |
| 1834 | /// All bit fields as a 64-bit value\r | |
| 1835 | ///\r | |
| 1836 | UINT64 Uint64;\r | |
| 1837 | } MSR_HASWELL_CORE_PERF_LIMIT_REASONS_REGISTER;\r | |
| 1838 | \r | |
| 1839 | \r | |
| 1840 | /**\r | |
| 1841 | Package. Indicator of Frequency Clipping in the Processor Graphics (R/W)\r | |
| 1842 | (frequency refers to processor graphics frequency).\r | |
| 1843 | \r | |
| 1844 | @param ECX MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS (0x000006B0)\r | |
| 1845 | @param EAX Lower 32-bits of MSR value.\r | |
| 1846 | Described by the type MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS_REGISTER.\r | |
| 1847 | @param EDX Upper 32-bits of MSR value.\r | |
| 1848 | Described by the type MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS_REGISTER.\r | |
| 1849 | \r | |
| 1850 | <b>Example usage</b>\r | |
| 1851 | @code\r | |
| 1852 | MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS_REGISTER Msr;\r | |
| 1853 | \r | |
| 1854 | Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS);\r | |
| 1855 | AsmWriteMsr64 (MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS, Msr.Uint64);\r | |
| 1856 | @endcode\r | |
| e108c3f6 | 1857 | @note MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS is defined as MSR_GRAPHICS_PERF_LIMIT_REASONS in SDM.\r |
| 7ae88a62 MK |
1858 | **/\r |
| 1859 | #define MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS 0x000006B0\r | |
| 1860 | \r | |
| 1861 | /**\r | |
| 1862 | MSR information returned for MSR index\r | |
| 1863 | #MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS\r | |
| 1864 | **/\r | |
| 1865 | typedef union {\r | |
| 1866 | ///\r | |
| 1867 | /// Individual bit fields\r | |
| 1868 | ///\r | |
| 1869 | struct {\r | |
| 1870 | ///\r | |
| 1871 | /// [Bit 0] PROCHOT Status (R0) When set, frequency is reduced below the\r | |
| 1872 | /// operating system request due to assertion of external PROCHOT.\r | |
| 1873 | ///\r | |
| 1874 | UINT32 PROCHOT_Status:1;\r | |
| 1875 | ///\r | |
| 1876 | /// [Bit 1] Thermal Status (R0) When set, frequency is reduced below the\r | |
| 1877 | /// operating system request due to a thermal event.\r | |
| 1878 | ///\r | |
| 1879 | UINT32 ThermalStatus:1;\r | |
| 1880 | UINT32 Reserved1:2;\r | |
| 1881 | ///\r | |
| 1882 | /// [Bit 4] Graphics Driver Status (R0) When set, frequency is reduced\r | |
| 1883 | /// below the operating system request due to Processor Graphics driver\r | |
| 1884 | /// override.\r | |
| 1885 | ///\r | |
| 1886 | UINT32 GraphicsDriverStatus:1;\r | |
| 1887 | ///\r | |
| 1888 | /// [Bit 5] Autonomous Utilization-Based Frequency Control Status (R0)\r | |
| 1889 | /// When set, frequency is reduced below the operating system request\r | |
| 1890 | /// because the processor has detected that utilization is low.\r | |
| 1891 | ///\r | |
| 1892 | UINT32 AutonomousUtilizationBasedFrequencyControlStatus:1;\r | |
| 1893 | ///\r | |
| 1894 | /// [Bit 6] VR Therm Alert Status (R0) When set, frequency is reduced\r | |
| 1895 | /// below the operating system request due to a thermal alert from the\r | |
| 1896 | /// Voltage Regulator.\r | |
| 1897 | ///\r | |
| 1898 | UINT32 VRThermAlertStatus:1;\r | |
| 1899 | UINT32 Reserved2:1;\r | |
| 1900 | ///\r | |
| 1901 | /// [Bit 8] Electrical Design Point Status (R0) When set, frequency is\r | |
| 1902 | /// reduced below the operating system request due to electrical design\r | |
| 1903 | /// point constraints (e.g. maximum electrical current consumption).\r | |
| 1904 | ///\r | |
| 1905 | UINT32 ElectricalDesignPointStatus:1;\r | |
| 1906 | ///\r | |
| 1907 | /// [Bit 9] Graphics Power Limiting Status (R0) When set, frequency is\r | |
| 1908 | /// reduced below the operating system request due to domain-level power\r | |
| 1909 | /// limiting.\r | |
| 1910 | ///\r | |
| 1911 | UINT32 GraphicsPowerLimitingStatus:1;\r | |
| 1912 | ///\r | |
| 1913 | /// [Bit 10] Package-Level Power Limiting PL1 Status (R0) When set,\r | |
| 1914 | /// frequency is reduced below the operating system request due to\r | |
| 1915 | /// package-level power limiting PL1.\r | |
| 1916 | ///\r | |
| 1917 | UINT32 PL1STatus:1;\r | |
| 1918 | ///\r | |
| 1919 | /// [Bit 11] Package-Level PL2 Power Limiting Status (R0) When set,\r | |
| 1920 | /// frequency is reduced below the operating system request due to\r | |
| 1921 | /// package-level power limiting PL2.\r | |
| 1922 | ///\r | |
| 1923 | UINT32 PL2Status:1;\r | |
| 1924 | UINT32 Reserved3:4;\r | |
| 1925 | ///\r | |
| 1926 | /// [Bit 16] PROCHOT Log When set, indicates that the PROCHOT Status bit\r | |
| 1927 | /// has asserted since the log bit was last cleared. This log bit will\r | |
| 1928 | /// remain set until cleared by software writing 0.\r | |
| 1929 | ///\r | |
| 1930 | UINT32 PROCHOT_Log:1;\r | |
| 1931 | ///\r | |
| 1932 | /// [Bit 17] Thermal Log When set, indicates that the Thermal Status bit\r | |
| 1933 | /// has asserted since the log bit was last cleared. This log bit will\r | |
| 1934 | /// remain set until cleared by software writing 0.\r | |
| 1935 | ///\r | |
| 1936 | UINT32 ThermalLog:1;\r | |
| 1937 | UINT32 Reserved4:2;\r | |
| 1938 | ///\r | |
| 1939 | /// [Bit 20] Graphics Driver Log When set, indicates that the Graphics\r | |
| 1940 | /// Driver Status bit has asserted since the log bit was last cleared.\r | |
| 1941 | /// This log bit will remain set until cleared by software writing 0.\r | |
| 1942 | ///\r | |
| 1943 | UINT32 GraphicsDriverLog:1;\r | |
| 1944 | ///\r | |
| 1945 | /// [Bit 21] Autonomous Utilization-Based Frequency Control Log When set,\r | |
| 1946 | /// indicates that the Autonomous Utilization-Based Frequency Control\r | |
| 1947 | /// Status bit has asserted since the log bit was last cleared. This log\r | |
| 1948 | /// bit will remain set until cleared by software writing 0.\r | |
| 1949 | ///\r | |
| 1950 | UINT32 AutonomousUtilizationBasedFrequencyControlLog:1;\r | |
| 1951 | ///\r | |
| 1952 | /// [Bit 22] VR Therm Alert Log When set, indicates that the VR Therm\r | |
| 1953 | /// Alert Status bit has asserted since the log bit was last cleared. This\r | |
| 1954 | /// log bit will remain set until cleared by software writing 0.\r | |
| 1955 | ///\r | |
| 1956 | UINT32 VRThermAlertLog:1;\r | |
| 1957 | UINT32 Reserved5:1;\r | |
| 1958 | ///\r | |
| 1959 | /// [Bit 24] Electrical Design Point Log When set, indicates that the EDP\r | |
| 1960 | /// Status bit has asserted since the log bit was last cleared. This log\r | |
| 1961 | /// bit will remain set until cleared by software writing 0.\r | |
| 1962 | ///\r | |
| 1963 | UINT32 ElectricalDesignPointLog:1;\r | |
| 1964 | ///\r | |
| 1965 | /// [Bit 25] Core Power Limiting Log When set, indicates that the Core\r | |
| 1966 | /// Power Limiting Status bit has asserted since the log bit was last\r | |
| 1967 | /// cleared. This log bit will remain set until cleared by software\r | |
| 1968 | /// writing 0.\r | |
| 1969 | ///\r | |
| 1970 | UINT32 CorePowerLimitingLog:1;\r | |
| 1971 | ///\r | |
| 1972 | /// [Bit 26] Package-Level PL1 Power Limiting Log When set, indicates\r | |
| 1973 | /// that the Package Level PL1 Power Limiting Status bit has asserted\r | |
| 1974 | /// since the log bit was last cleared. This log bit will remain set until\r | |
| 1975 | /// cleared by software writing 0.\r | |
| 1976 | ///\r | |
| 1977 | UINT32 PL1Log:1;\r | |
| 1978 | ///\r | |
| 1979 | /// [Bit 27] Package-Level PL2 Power Limiting Log When set, indicates that\r | |
| 1980 | /// the Package Level PL2 Power Limiting Status bit has asserted since the\r | |
| 1981 | /// log bit was last cleared. This log bit will remain set until cleared\r | |
| 1982 | /// by software writing 0.\r | |
| 1983 | ///\r | |
| 1984 | UINT32 PL2Log:1;\r | |
| 1985 | ///\r | |
| 1986 | /// [Bit 28] Max Turbo Limit Log When set, indicates that the Max Turbo\r | |
| 1987 | /// Limit Status bit has asserted since the log bit was last cleared. This\r | |
| 1988 | /// log bit will remain set until cleared by software writing 0.\r | |
| 1989 | ///\r | |
| 1990 | UINT32 MaxTurboLimitLog:1;\r | |
| 1991 | ///\r | |
| 1992 | /// [Bit 29] Turbo Transition Attenuation Log When set, indicates that the\r | |
| 1993 | /// Turbo Transition Attenuation Status bit has asserted since the log bit\r | |
| 1994 | /// was last cleared. This log bit will remain set until cleared by\r | |
| 1995 | /// software writing 0.\r | |
| 1996 | ///\r | |
| 1997 | UINT32 TurboTransitionAttenuationLog:1;\r | |
| 1998 | UINT32 Reserved6:2;\r | |
| 1999 | UINT32 Reserved7:32;\r | |
| 2000 | } Bits;\r | |
| 2001 | ///\r | |
| 2002 | /// All bit fields as a 32-bit value\r | |
| 2003 | ///\r | |
| 2004 | UINT32 Uint32;\r | |
| 2005 | ///\r | |
| 2006 | /// All bit fields as a 64-bit value\r | |
| 2007 | ///\r | |
| 2008 | UINT64 Uint64;\r | |
| 2009 | } MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS_REGISTER;\r | |
| 2010 | \r | |
| 2011 | \r | |
| 2012 | /**\r | |
| 2013 | Package. Indicator of Frequency Clipping in the Ring Interconnect (R/W)\r | |
| 2014 | (frequency refers to ring interconnect in the uncore).\r | |
| 2015 | \r | |
| 2016 | @param ECX MSR_HASWELL_RING_PERF_LIMIT_REASONS (0x000006B1)\r | |
| 2017 | @param EAX Lower 32-bits of MSR value.\r | |
| 2018 | Described by the type MSR_HASWELL_RING_PERF_LIMIT_REASONS_REGISTER.\r | |
| 2019 | @param EDX Upper 32-bits of MSR value.\r | |
| 2020 | Described by the type MSR_HASWELL_RING_PERF_LIMIT_REASONS_REGISTER.\r | |
| 2021 | \r | |
| 2022 | <b>Example usage</b>\r | |
| 2023 | @code\r | |
| 2024 | MSR_HASWELL_RING_PERF_LIMIT_REASONS_REGISTER Msr;\r | |
| 2025 | \r | |
| 2026 | Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_RING_PERF_LIMIT_REASONS);\r | |
| 2027 | AsmWriteMsr64 (MSR_HASWELL_RING_PERF_LIMIT_REASONS, Msr.Uint64);\r | |
| 2028 | @endcode\r | |
| e108c3f6 | 2029 | @note MSR_HASWELL_RING_PERF_LIMIT_REASONS is defined as MSR_RING_PERF_LIMIT_REASONS in SDM.\r |
| 7ae88a62 MK |
2030 | **/\r |
| 2031 | #define MSR_HASWELL_RING_PERF_LIMIT_REASONS 0x000006B1\r | |
| 2032 | \r | |
| 2033 | /**\r | |
| 2034 | MSR information returned for MSR index #MSR_HASWELL_RING_PERF_LIMIT_REASONS\r | |
| 2035 | **/\r | |
| 2036 | typedef union {\r | |
| 2037 | ///\r | |
| 2038 | /// Individual bit fields\r | |
| 2039 | ///\r | |
| 2040 | struct {\r | |
| 2041 | ///\r | |
| 2042 | /// [Bit 0] PROCHOT Status (R0) When set, frequency is reduced below the\r | |
| 2043 | /// operating system request due to assertion of external PROCHOT.\r | |
| 2044 | ///\r | |
| 2045 | UINT32 PROCHOT_Status:1;\r | |
| 2046 | ///\r | |
| 2047 | /// [Bit 1] Thermal Status (R0) When set, frequency is reduced below the\r | |
| 2048 | /// operating system request due to a thermal event.\r | |
| 2049 | ///\r | |
| 2050 | UINT32 ThermalStatus:1;\r | |
| 2051 | UINT32 Reserved1:4;\r | |
| 2052 | ///\r | |
| 2053 | /// [Bit 6] VR Therm Alert Status (R0) When set, frequency is reduced\r | |
| 2054 | /// below the operating system request due to a thermal alert from the\r | |
| 2055 | /// Voltage Regulator.\r | |
| 2056 | ///\r | |
| 2057 | UINT32 VRThermAlertStatus:1;\r | |
| 2058 | UINT32 Reserved2:1;\r | |
| 2059 | ///\r | |
| 2060 | /// [Bit 8] Electrical Design Point Status (R0) When set, frequency is\r | |
| 2061 | /// reduced below the operating system request due to electrical design\r | |
| 2062 | /// point constraints (e.g. maximum electrical current consumption).\r | |
| 2063 | ///\r | |
| 2064 | UINT32 ElectricalDesignPointStatus:1;\r | |
| 2065 | UINT32 Reserved3:1;\r | |
| 2066 | ///\r | |
| 2067 | /// [Bit 10] Package-Level Power Limiting PL1 Status (R0) When set,\r | |
| 2068 | /// frequency is reduced below the operating system request due to\r | |
| 2069 | /// package-level power limiting PL1.\r | |
| 2070 | ///\r | |
| 2071 | UINT32 PL1STatus:1;\r | |
| 2072 | ///\r | |
| 2073 | /// [Bit 11] Package-Level PL2 Power Limiting Status (R0) When set,\r | |
| 2074 | /// frequency is reduced below the operating system request due to\r | |
| 2075 | /// package-level power limiting PL2.\r | |
| 2076 | ///\r | |
| 2077 | UINT32 PL2Status:1;\r | |
| 2078 | UINT32 Reserved4:4;\r | |
| 2079 | ///\r | |
| 2080 | /// [Bit 16] PROCHOT Log When set, indicates that the PROCHOT Status bit\r | |
| 2081 | /// has asserted since the log bit was last cleared. This log bit will\r | |
| 2082 | /// remain set until cleared by software writing 0.\r | |
| 2083 | ///\r | |
| 2084 | UINT32 PROCHOT_Log:1;\r | |
| 2085 | ///\r | |
| 2086 | /// [Bit 17] Thermal Log When set, indicates that the Thermal Status bit\r | |
| 2087 | /// has asserted since the log bit was last cleared. This log bit will\r | |
| 2088 | /// remain set until cleared by software writing 0.\r | |
| 2089 | ///\r | |
| 2090 | UINT32 ThermalLog:1;\r | |
| 2091 | UINT32 Reserved5:2;\r | |
| 2092 | ///\r | |
| 2093 | /// [Bit 20] Graphics Driver Log When set, indicates that the Graphics\r | |
| 2094 | /// Driver Status bit has asserted since the log bit was last cleared.\r | |
| 2095 | /// This log bit will remain set until cleared by software writing 0.\r | |
| 2096 | ///\r | |
| 2097 | UINT32 GraphicsDriverLog:1;\r | |
| 2098 | ///\r | |
| 2099 | /// [Bit 21] Autonomous Utilization-Based Frequency Control Log When set,\r | |
| 2100 | /// indicates that the Autonomous Utilization-Based Frequency Control\r | |
| 2101 | /// Status bit has asserted since the log bit was last cleared. This log\r | |
| 2102 | /// bit will remain set until cleared by software writing 0.\r | |
| 2103 | ///\r | |
| 2104 | UINT32 AutonomousUtilizationBasedFrequencyControlLog:1;\r | |
| 2105 | ///\r | |
| 2106 | /// [Bit 22] VR Therm Alert Log When set, indicates that the VR Therm\r | |
| 2107 | /// Alert Status bit has asserted since the log bit was last cleared. This\r | |
| 2108 | /// log bit will remain set until cleared by software writing 0.\r | |
| 2109 | ///\r | |
| 2110 | UINT32 VRThermAlertLog:1;\r | |
| 2111 | UINT32 Reserved6:1;\r | |
| 2112 | ///\r | |
| 2113 | /// [Bit 24] Electrical Design Point Log When set, indicates that the EDP\r | |
| 2114 | /// Status bit has asserted since the log bit was last cleared. This log\r | |
| 2115 | /// bit will remain set until cleared by software writing 0.\r | |
| 2116 | ///\r | |
| 2117 | UINT32 ElectricalDesignPointLog:1;\r | |
| 2118 | ///\r | |
| 2119 | /// [Bit 25] Core Power Limiting Log When set, indicates that the Core\r | |
| 2120 | /// Power Limiting Status bit has asserted since the log bit was last\r | |
| 2121 | /// cleared. This log bit will remain set until cleared by software\r | |
| 2122 | /// writing 0.\r | |
| 2123 | ///\r | |
| 2124 | UINT32 CorePowerLimitingLog:1;\r | |
| 2125 | ///\r | |
| 2126 | /// [Bit 26] Package-Level PL1 Power Limiting Log When set, indicates\r | |
| 2127 | /// that the Package Level PL1 Power Limiting Status bit has asserted\r | |
| 2128 | /// since the log bit was last cleared. This log bit will remain set until\r | |
| 2129 | /// cleared by software writing 0.\r | |
| 2130 | ///\r | |
| 2131 | UINT32 PL1Log:1;\r | |
| 2132 | ///\r | |
| 2133 | /// [Bit 27] Package-Level PL2 Power Limiting Log When set, indicates that\r | |
| 2134 | /// the Package Level PL2 Power Limiting Status bit has asserted since the\r | |
| 2135 | /// log bit was last cleared. This log bit will remain set until cleared\r | |
| 2136 | /// by software writing 0.\r | |
| 2137 | ///\r | |
| 2138 | UINT32 PL2Log:1;\r | |
| 2139 | ///\r | |
| 2140 | /// [Bit 28] Max Turbo Limit Log When set, indicates that the Max Turbo\r | |
| 2141 | /// Limit Status bit has asserted since the log bit was last cleared. This\r | |
| 2142 | /// log bit will remain set until cleared by software writing 0.\r | |
| 2143 | ///\r | |
| 2144 | UINT32 MaxTurboLimitLog:1;\r | |
| 2145 | ///\r | |
| 2146 | /// [Bit 29] Turbo Transition Attenuation Log When set, indicates that the\r | |
| 2147 | /// Turbo Transition Attenuation Status bit has asserted since the log bit\r | |
| 2148 | /// was last cleared. This log bit will remain set until cleared by\r | |
| 2149 | /// software writing 0.\r | |
| 2150 | ///\r | |
| 2151 | UINT32 TurboTransitionAttenuationLog:1;\r | |
| 2152 | UINT32 Reserved7:2;\r | |
| 2153 | UINT32 Reserved8:32;\r | |
| 2154 | } Bits;\r | |
| 2155 | ///\r | |
| 2156 | /// All bit fields as a 32-bit value\r | |
| 2157 | ///\r | |
| 2158 | UINT32 Uint32;\r | |
| 2159 | ///\r | |
| 2160 | /// All bit fields as a 64-bit value\r | |
| 2161 | ///\r | |
| 2162 | UINT64 Uint64;\r | |
| 2163 | } MSR_HASWELL_RING_PERF_LIMIT_REASONS_REGISTER;\r | |
| 2164 | \r | |
| 2165 | \r | |
| 2166 | /**\r | |
| 2167 | Package. Uncore C-Box 0, counter 0 event select MSR.\r | |
| 2168 | \r | |
| 2169 | @param ECX MSR_HASWELL_UNC_CBO_0_PERFEVTSEL0 (0x00000700)\r | |
| 2170 | @param EAX Lower 32-bits of MSR value.\r | |
| 2171 | @param EDX Upper 32-bits of MSR value.\r | |
| 2172 | \r | |
| 2173 | <b>Example usage</b>\r | |
| 2174 | @code\r | |
| 2175 | UINT64 Msr;\r | |
| 2176 | \r | |
| 2177 | Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_0_PERFEVTSEL0);\r | |
| 2178 | AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_0_PERFEVTSEL0, Msr);\r | |
| 2179 | @endcode\r | |
| e108c3f6 | 2180 | @note MSR_HASWELL_UNC_CBO_0_PERFEVTSEL0 is defined as MSR_UNC_CBO_0_PERFEVTSEL0 in SDM.\r |
| 7ae88a62 MK |
2181 | **/\r |
| 2182 | #define MSR_HASWELL_UNC_CBO_0_PERFEVTSEL0 0x00000700\r | |
| 2183 | \r | |
| 2184 | \r | |
| 2185 | /**\r | |
| 2186 | Package. Uncore C-Box 0, counter 1 event select MSR.\r | |
| 2187 | \r | |
| 2188 | @param ECX MSR_HASWELL_UNC_CBO_0_PERFEVTSEL1 (0x00000701)\r | |
| 2189 | @param EAX Lower 32-bits of MSR value.\r | |
| 2190 | @param EDX Upper 32-bits of MSR value.\r | |
| 2191 | \r | |
| 2192 | <b>Example usage</b>\r | |
| 2193 | @code\r | |
| 2194 | UINT64 Msr;\r | |
| 2195 | \r | |
| 2196 | Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_0_PERFEVTSEL1);\r | |
| 2197 | AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_0_PERFEVTSEL1, Msr);\r | |
| 2198 | @endcode\r | |
| e108c3f6 | 2199 | @note MSR_HASWELL_UNC_CBO_0_PERFEVTSEL1 is defined as MSR_UNC_CBO_0_PERFEVTSEL1 in SDM.\r |
| 7ae88a62 MK |
2200 | **/\r |
| 2201 | #define MSR_HASWELL_UNC_CBO_0_PERFEVTSEL1 0x00000701\r | |
| 2202 | \r | |
| 2203 | \r | |
| 2204 | /**\r | |
| 2205 | Package. Uncore C-Box 0, performance counter 0.\r | |
| 2206 | \r | |
| 2207 | @param ECX MSR_HASWELL_UNC_CBO_0_PERFCTR0 (0x00000706)\r | |
| 2208 | @param EAX Lower 32-bits of MSR value.\r | |
| 2209 | @param EDX Upper 32-bits of MSR value.\r | |
| 2210 | \r | |
| 2211 | <b>Example usage</b>\r | |
| 2212 | @code\r | |
| 2213 | UINT64 Msr;\r | |
| 2214 | \r | |
| 2215 | Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_0_PERFCTR0);\r | |
| 2216 | AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_0_PERFCTR0, Msr);\r | |
| 2217 | @endcode\r | |
| e108c3f6 | 2218 | @note MSR_HASWELL_UNC_CBO_0_PERFCTR0 is defined as MSR_UNC_CBO_0_PERFCTR0 in SDM.\r |
| 7ae88a62 MK |
2219 | **/\r |
| 2220 | #define MSR_HASWELL_UNC_CBO_0_PERFCTR0 0x00000706\r | |
| 2221 | \r | |
| 2222 | \r | |
| 2223 | /**\r | |
| 2224 | Package. Uncore C-Box 0, performance counter 1.\r | |
| 2225 | \r | |
| 2226 | @param ECX MSR_HASWELL_UNC_CBO_0_PERFCTR1 (0x00000707)\r | |
| 2227 | @param EAX Lower 32-bits of MSR value.\r | |
| 2228 | @param EDX Upper 32-bits of MSR value.\r | |
| 2229 | \r | |
| 2230 | <b>Example usage</b>\r | |
| 2231 | @code\r | |
| 2232 | UINT64 Msr;\r | |
| 2233 | \r | |
| 2234 | Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_0_PERFCTR1);\r | |
| 2235 | AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_0_PERFCTR1, Msr);\r | |
| 2236 | @endcode\r | |
| e108c3f6 | 2237 | @note MSR_HASWELL_UNC_CBO_0_PERFCTR1 is defined as MSR_UNC_CBO_0_PERFCTR1 in SDM.\r |
| 7ae88a62 MK |
2238 | **/\r |
| 2239 | #define MSR_HASWELL_UNC_CBO_0_PERFCTR1 0x00000707\r | |
| 2240 | \r | |
| 2241 | \r | |
| 2242 | /**\r | |
| 2243 | Package. Uncore C-Box 1, counter 0 event select MSR.\r | |
| 2244 | \r | |
| 2245 | @param ECX MSR_HASWELL_UNC_CBO_1_PERFEVTSEL0 (0x00000710)\r | |
| 2246 | @param EAX Lower 32-bits of MSR value.\r | |
| 2247 | @param EDX Upper 32-bits of MSR value.\r | |
| 2248 | \r | |
| 2249 | <b>Example usage</b>\r | |
| 2250 | @code\r | |
| 2251 | UINT64 Msr;\r | |
| 2252 | \r | |
| 2253 | Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_1_PERFEVTSEL0);\r | |
| 2254 | AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_1_PERFEVTSEL0, Msr);\r | |
| 2255 | @endcode\r | |
| e108c3f6 | 2256 | @note MSR_HASWELL_UNC_CBO_1_PERFEVTSEL0 is defined as MSR_UNC_CBO_1_PERFEVTSEL0 in SDM.\r |
| 7ae88a62 MK |
2257 | **/\r |
| 2258 | #define MSR_HASWELL_UNC_CBO_1_PERFEVTSEL0 0x00000710\r | |
| 2259 | \r | |
| 2260 | \r | |
| 2261 | /**\r | |
| 2262 | Package. Uncore C-Box 1, counter 1 event select MSR.\r | |
| 2263 | \r | |
| 2264 | @param ECX MSR_HASWELL_UNC_CBO_1_PERFEVTSEL1 (0x00000711)\r | |
| 2265 | @param EAX Lower 32-bits of MSR value.\r | |
| 2266 | @param EDX Upper 32-bits of MSR value.\r | |
| 2267 | \r | |
| 2268 | <b>Example usage</b>\r | |
| 2269 | @code\r | |
| 2270 | UINT64 Msr;\r | |
| 2271 | \r | |
| 2272 | Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_1_PERFEVTSEL1);\r | |
| 2273 | AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_1_PERFEVTSEL1, Msr);\r | |
| 2274 | @endcode\r | |
| e108c3f6 | 2275 | @note MSR_HASWELL_UNC_CBO_1_PERFEVTSEL1 is defined as MSR_UNC_CBO_1_PERFEVTSEL1 in SDM.\r |
| 7ae88a62 MK |
2276 | **/\r |
| 2277 | #define MSR_HASWELL_UNC_CBO_1_PERFEVTSEL1 0x00000711\r | |
| 2278 | \r | |
| 2279 | \r | |
| 2280 | /**\r | |
| 2281 | Package. Uncore C-Box 1, performance counter 0.\r | |
| 2282 | \r | |
| 2283 | @param ECX MSR_HASWELL_UNC_CBO_1_PERFCTR0 (0x00000716)\r | |
| 2284 | @param EAX Lower 32-bits of MSR value.\r | |
| 2285 | @param EDX Upper 32-bits of MSR value.\r | |
| 2286 | \r | |
| 2287 | <b>Example usage</b>\r | |
| 2288 | @code\r | |
| 2289 | UINT64 Msr;\r | |
| 2290 | \r | |
| 2291 | Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_1_PERFCTR0);\r | |
| 2292 | AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_1_PERFCTR0, Msr);\r | |
| 2293 | @endcode\r | |
| e108c3f6 | 2294 | @note MSR_HASWELL_UNC_CBO_1_PERFCTR0 is defined as MSR_UNC_CBO_1_PERFCTR0 in SDM.\r |
| 7ae88a62 MK |
2295 | **/\r |
| 2296 | #define MSR_HASWELL_UNC_CBO_1_PERFCTR0 0x00000716\r | |
| 2297 | \r | |
| 2298 | \r | |
| 2299 | /**\r | |
| 2300 | Package. Uncore C-Box 1, performance counter 1.\r | |
| 2301 | \r | |
| 2302 | @param ECX MSR_HASWELL_UNC_CBO_1_PERFCTR1 (0x00000717)\r | |
| 2303 | @param EAX Lower 32-bits of MSR value.\r | |
| 2304 | @param EDX Upper 32-bits of MSR value.\r | |
| 2305 | \r | |
| 2306 | <b>Example usage</b>\r | |
| 2307 | @code\r | |
| 2308 | UINT64 Msr;\r | |
| 2309 | \r | |
| 2310 | Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_1_PERFCTR1);\r | |
| 2311 | AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_1_PERFCTR1, Msr);\r | |
| 2312 | @endcode\r | |
| e108c3f6 | 2313 | @note MSR_HASWELL_UNC_CBO_1_PERFCTR1 is defined as MSR_UNC_CBO_1_PERFCTR1 in SDM.\r |
| 7ae88a62 MK |
2314 | **/\r |
| 2315 | #define MSR_HASWELL_UNC_CBO_1_PERFCTR1 0x00000717\r | |
| 2316 | \r | |
| 2317 | \r | |
| 2318 | /**\r | |
| 2319 | Package. Uncore C-Box 2, counter 0 event select MSR.\r | |
| 2320 | \r | |
| 2321 | @param ECX MSR_HASWELL_UNC_CBO_2_PERFEVTSEL0 (0x00000720)\r | |
| 2322 | @param EAX Lower 32-bits of MSR value.\r | |
| 2323 | @param EDX Upper 32-bits of MSR value.\r | |
| 2324 | \r | |
| 2325 | <b>Example usage</b>\r | |
| 2326 | @code\r | |
| 2327 | UINT64 Msr;\r | |
| 2328 | \r | |
| 2329 | Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_2_PERFEVTSEL0);\r | |
| 2330 | AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_2_PERFEVTSEL0, Msr);\r | |
| 2331 | @endcode\r | |
| e108c3f6 | 2332 | @note MSR_HASWELL_UNC_CBO_2_PERFEVTSEL0 is defined as MSR_UNC_CBO_2_PERFEVTSEL0 in SDM.\r |
| 7ae88a62 MK |
2333 | **/\r |
| 2334 | #define MSR_HASWELL_UNC_CBO_2_PERFEVTSEL0 0x00000720\r | |
| 2335 | \r | |
| 2336 | \r | |
| 2337 | /**\r | |
| 2338 | Package. Uncore C-Box 2, counter 1 event select MSR.\r | |
| 2339 | \r | |
| 2340 | @param ECX MSR_HASWELL_UNC_CBO_2_PERFEVTSEL1 (0x00000721)\r | |
| 2341 | @param EAX Lower 32-bits of MSR value.\r | |
| 2342 | @param EDX Upper 32-bits of MSR value.\r | |
| 2343 | \r | |
| 2344 | <b>Example usage</b>\r | |
| 2345 | @code\r | |
| 2346 | UINT64 Msr;\r | |
| 2347 | \r | |
| 2348 | Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_2_PERFEVTSEL1);\r | |
| 2349 | AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_2_PERFEVTSEL1, Msr);\r | |
| 2350 | @endcode\r | |
| e108c3f6 | 2351 | @note MSR_HASWELL_UNC_CBO_2_PERFEVTSEL1 is defined as MSR_UNC_CBO_2_PERFEVTSEL1 in SDM.\r |
| 7ae88a62 MK |
2352 | **/\r |
| 2353 | #define MSR_HASWELL_UNC_CBO_2_PERFEVTSEL1 0x00000721\r | |
| 2354 | \r | |
| 2355 | \r | |
| 2356 | /**\r | |
| 2357 | Package. Uncore C-Box 2, performance counter 0.\r | |
| 2358 | \r | |
| 2359 | @param ECX MSR_HASWELL_UNC_CBO_2_PERFCTR0 (0x00000726)\r | |
| 2360 | @param EAX Lower 32-bits of MSR value.\r | |
| 2361 | @param EDX Upper 32-bits of MSR value.\r | |
| 2362 | \r | |
| 2363 | <b>Example usage</b>\r | |
| 2364 | @code\r | |
| 2365 | UINT64 Msr;\r | |
| 2366 | \r | |
| 2367 | Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_2_PERFCTR0);\r | |
| 2368 | AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_2_PERFCTR0, Msr);\r | |
| 2369 | @endcode\r | |
| e108c3f6 | 2370 | @note MSR_HASWELL_UNC_CBO_2_PERFCTR0 is defined as MSR_UNC_CBO_2_PERFCTR0 in SDM.\r |
| 7ae88a62 MK |
2371 | **/\r |
| 2372 | #define MSR_HASWELL_UNC_CBO_2_PERFCTR0 0x00000726\r | |
| 2373 | \r | |
| 2374 | \r | |
| 2375 | /**\r | |
| 2376 | Package. Uncore C-Box 2, performance counter 1.\r | |
| 2377 | \r | |
| 2378 | @param ECX MSR_HASWELL_UNC_CBO_2_PERFCTR1 (0x00000727)\r | |
| 2379 | @param EAX Lower 32-bits of MSR value.\r | |
| 2380 | @param EDX Upper 32-bits of MSR value.\r | |
| 2381 | \r | |
| 2382 | <b>Example usage</b>\r | |
| 2383 | @code\r | |
| 2384 | UINT64 Msr;\r | |
| 2385 | \r | |
| 2386 | Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_2_PERFCTR1);\r | |
| 2387 | AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_2_PERFCTR1, Msr);\r | |
| 2388 | @endcode\r | |
| e108c3f6 | 2389 | @note MSR_HASWELL_UNC_CBO_2_PERFCTR1 is defined as MSR_UNC_CBO_2_PERFCTR1 in SDM.\r |
| 7ae88a62 MK |
2390 | **/\r |
| 2391 | #define MSR_HASWELL_UNC_CBO_2_PERFCTR1 0x00000727\r | |
| 2392 | \r | |
| 2393 | \r | |
| 2394 | /**\r | |
| 2395 | Package. Uncore C-Box 3, counter 0 event select MSR.\r | |
| 2396 | \r | |
| 2397 | @param ECX MSR_HASWELL_UNC_CBO_3_PERFEVTSEL0 (0x00000730)\r | |
| 2398 | @param EAX Lower 32-bits of MSR value.\r | |
| 2399 | @param EDX Upper 32-bits of MSR value.\r | |
| 2400 | \r | |
| 2401 | <b>Example usage</b>\r | |
| 2402 | @code\r | |
| 2403 | UINT64 Msr;\r | |
| 2404 | \r | |
| 2405 | Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_3_PERFEVTSEL0);\r | |
| 2406 | AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_3_PERFEVTSEL0, Msr);\r | |
| 2407 | @endcode\r | |
| e108c3f6 | 2408 | @note MSR_HASWELL_UNC_CBO_3_PERFEVTSEL0 is defined as MSR_UNC_CBO_3_PERFEVTSEL0 in SDM.\r |
| 7ae88a62 MK |
2409 | **/\r |
| 2410 | #define MSR_HASWELL_UNC_CBO_3_PERFEVTSEL0 0x00000730\r | |
| 2411 | \r | |
| 2412 | \r | |
| 2413 | /**\r | |
| 2414 | Package. Uncore C-Box 3, counter 1 event select MSR.\r | |
| 2415 | \r | |
| 2416 | @param ECX MSR_HASWELL_UNC_CBO_3_PERFEVTSEL1 (0x00000731)\r | |
| 2417 | @param EAX Lower 32-bits of MSR value.\r | |
| 2418 | @param EDX Upper 32-bits of MSR value.\r | |
| 2419 | \r | |
| 2420 | <b>Example usage</b>\r | |
| 2421 | @code\r | |
| 2422 | UINT64 Msr;\r | |
| 2423 | \r | |
| 2424 | Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_3_PERFEVTSEL1);\r | |
| 2425 | AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_3_PERFEVTSEL1, Msr);\r | |
| 2426 | @endcode\r | |
| e108c3f6 | 2427 | @note MSR_HASWELL_UNC_CBO_3_PERFEVTSEL1 is defined as MSR_UNC_CBO_3_PERFEVTSEL1 in SDM.\r |
| 7ae88a62 MK |
2428 | **/\r |
| 2429 | #define MSR_HASWELL_UNC_CBO_3_PERFEVTSEL1 0x00000731\r | |
| 2430 | \r | |
| 2431 | \r | |
| 2432 | /**\r | |
| 2433 | Package. Uncore C-Box 3, performance counter 0.\r | |
| 2434 | \r | |
| 2435 | @param ECX MSR_HASWELL_UNC_CBO_3_PERFCTR0 (0x00000736)\r | |
| 2436 | @param EAX Lower 32-bits of MSR value.\r | |
| 2437 | @param EDX Upper 32-bits of MSR value.\r | |
| 2438 | \r | |
| 2439 | <b>Example usage</b>\r | |
| 2440 | @code\r | |
| 2441 | UINT64 Msr;\r | |
| 2442 | \r | |
| 2443 | Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_3_PERFCTR0);\r | |
| 2444 | AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_3_PERFCTR0, Msr);\r | |
| 2445 | @endcode\r | |
| e108c3f6 | 2446 | @note MSR_HASWELL_UNC_CBO_3_PERFCTR0 is defined as MSR_UNC_CBO_3_PERFCTR0 in SDM.\r |
| 7ae88a62 MK |
2447 | **/\r |
| 2448 | #define MSR_HASWELL_UNC_CBO_3_PERFCTR0 0x00000736\r | |
| 2449 | \r | |
| 2450 | \r | |
| 2451 | /**\r | |
| 2452 | Package. Uncore C-Box 3, performance counter 1.\r | |
| 2453 | \r | |
| 2454 | @param ECX MSR_HASWELL_UNC_CBO_3_PERFCTR1 (0x00000737)\r | |
| 2455 | @param EAX Lower 32-bits of MSR value.\r | |
| 2456 | @param EDX Upper 32-bits of MSR value.\r | |
| 2457 | \r | |
| 2458 | <b>Example usage</b>\r | |
| 2459 | @code\r | |
| 2460 | UINT64 Msr;\r | |
| 2461 | \r | |
| 2462 | Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_3_PERFCTR1);\r | |
| 2463 | AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_3_PERFCTR1, Msr);\r | |
| 2464 | @endcode\r | |
| e108c3f6 | 2465 | @note MSR_HASWELL_UNC_CBO_3_PERFCTR1 is defined as MSR_UNC_CBO_3_PERFCTR1 in SDM.\r |
| 7ae88a62 MK |
2466 | **/\r |
| 2467 | #define MSR_HASWELL_UNC_CBO_3_PERFCTR1 0x00000737\r | |
| 2468 | \r | |
| 2469 | \r | |
| 2470 | /**\r | |
| 2471 | Package. Note: C-state values are processor specific C-state code names,\r | |
| 2472 | unrelated to MWAIT extension C-state parameters or ACPI C-States.\r | |
| 2473 | \r | |
| 2474 | @param ECX MSR_HASWELL_PKG_C8_RESIDENCY (0x00000630)\r | |
| 2475 | @param EAX Lower 32-bits of MSR value.\r | |
| 2476 | Described by the type MSR_HASWELL_PKG_C8_RESIDENCY_REGISTER.\r | |
| 2477 | @param EDX Upper 32-bits of MSR value.\r | |
| 2478 | Described by the type MSR_HASWELL_PKG_C8_RESIDENCY_REGISTER.\r | |
| 2479 | \r | |
| 2480 | <b>Example usage</b>\r | |
| 2481 | @code\r | |
| 2482 | MSR_HASWELL_PKG_C8_RESIDENCY_REGISTER Msr;\r | |
| 2483 | \r | |
| 2484 | Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_PKG_C8_RESIDENCY);\r | |
| 2485 | AsmWriteMsr64 (MSR_HASWELL_PKG_C8_RESIDENCY, Msr.Uint64);\r | |
| 2486 | @endcode\r | |
| e108c3f6 | 2487 | @note MSR_HASWELL_PKG_C8_RESIDENCY is defined as MSR_PKG_C8_RESIDENCY in SDM.\r |
| 7ae88a62 MK |
2488 | **/\r |
| 2489 | #define MSR_HASWELL_PKG_C8_RESIDENCY 0x00000630\r | |
| 2490 | \r | |
| 2491 | /**\r | |
| 2492 | MSR information returned for MSR index #MSR_HASWELL_PKG_C8_RESIDENCY\r | |
| 2493 | **/\r | |
| 2494 | typedef union {\r | |
| 2495 | ///\r | |
| 2496 | /// Individual bit fields\r | |
| 2497 | ///\r | |
| 2498 | struct {\r | |
| 2499 | ///\r | |
| 2500 | /// [Bits 31:0] Package C8 Residency Counter. (R/O) Value since last reset\r | |
| 2501 | /// that this package is in processor-specific C8 states. Count at the\r | |
| 2502 | /// same frequency as the TSC.\r | |
| 2503 | ///\r | |
| 2504 | UINT32 C8ResidencyCounter:32;\r | |
| 2505 | ///\r | |
| 2506 | /// [Bits 59:32] Package C8 Residency Counter. (R/O) Value since last\r | |
| 2507 | /// reset that this package is in processor-specific C8 states. Count at\r | |
| 2508 | /// the same frequency as the TSC.\r | |
| 2509 | ///\r | |
| 2510 | UINT32 C8ResidencyCounterHi:28;\r | |
| 2511 | UINT32 Reserved:4;\r | |
| 2512 | } Bits;\r | |
| 2513 | ///\r | |
| 2514 | /// All bit fields as a 64-bit value\r | |
| 2515 | ///\r | |
| 2516 | UINT64 Uint64;\r | |
| 2517 | } MSR_HASWELL_PKG_C8_RESIDENCY_REGISTER;\r | |
| 2518 | \r | |
| 2519 | \r | |
| 2520 | /**\r | |
| 2521 | Package. Note: C-state values are processor specific C-state code names,\r | |
| 2522 | unrelated to MWAIT extension C-state parameters or ACPI C-States.\r | |
| 2523 | \r | |
| 2524 | @param ECX MSR_HASWELL_PKG_C9_RESIDENCY (0x00000631)\r | |
| 2525 | @param EAX Lower 32-bits of MSR value.\r | |
| 2526 | Described by the type MSR_HASWELL_PKG_C9_RESIDENCY_REGISTER.\r | |
| 2527 | @param EDX Upper 32-bits of MSR value.\r | |
| 2528 | Described by the type MSR_HASWELL_PKG_C9_RESIDENCY_REGISTER.\r | |
| 2529 | \r | |
| 2530 | <b>Example usage</b>\r | |
| 2531 | @code\r | |
| 2532 | MSR_HASWELL_PKG_C9_RESIDENCY_REGISTER Msr;\r | |
| 2533 | \r | |
| 2534 | Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_PKG_C9_RESIDENCY);\r | |
| 2535 | AsmWriteMsr64 (MSR_HASWELL_PKG_C9_RESIDENCY, Msr.Uint64);\r | |
| 2536 | @endcode\r | |
| e108c3f6 | 2537 | @note MSR_HASWELL_PKG_C9_RESIDENCY is defined as MSR_PKG_C9_RESIDENCY in SDM.\r |
| 7ae88a62 MK |
2538 | **/\r |
| 2539 | #define MSR_HASWELL_PKG_C9_RESIDENCY 0x00000631\r | |
| 2540 | \r | |
| 2541 | /**\r | |
| 2542 | MSR information returned for MSR index #MSR_HASWELL_PKG_C9_RESIDENCY\r | |
| 2543 | **/\r | |
| 2544 | typedef union {\r | |
| 2545 | ///\r | |
| 2546 | /// Individual bit fields\r | |
| 2547 | ///\r | |
| 2548 | struct {\r | |
| 2549 | ///\r | |
| 2550 | /// [Bits 31:0] Package C9 Residency Counter. (R/O) Value since last reset\r | |
| 2551 | /// that this package is in processor-specific C9 states. Count at the\r | |
| 2552 | /// same frequency as the TSC.\r | |
| 2553 | ///\r | |
| 2554 | UINT32 C9ResidencyCounter:32;\r | |
| 2555 | ///\r | |
| 2556 | /// [Bits 59:32] Package C9 Residency Counter. (R/O) Value since last\r | |
| 2557 | /// reset that this package is in processor-specific C9 states. Count at\r | |
| 2558 | /// the same frequency as the TSC.\r | |
| 2559 | ///\r | |
| 2560 | UINT32 C9ResidencyCounterHi:28;\r | |
| 2561 | UINT32 Reserved:4;\r | |
| 2562 | } Bits;\r | |
| 2563 | ///\r | |
| 2564 | /// All bit fields as a 64-bit value\r | |
| 2565 | ///\r | |
| 2566 | UINT64 Uint64;\r | |
| 2567 | } MSR_HASWELL_PKG_C9_RESIDENCY_REGISTER;\r | |
| 2568 | \r | |
| 2569 | \r | |
| 2570 | /**\r | |
| 2571 | Package. Note: C-state values are processor specific C-state code names,\r | |
| 2572 | unrelated to MWAIT extension C-state parameters or ACPI C-States.\r | |
| 2573 | \r | |
| 2574 | @param ECX MSR_HASWELL_PKG_C10_RESIDENCY (0x00000632)\r | |
| 2575 | @param EAX Lower 32-bits of MSR value.\r | |
| 2576 | Described by the type MSR_HASWELL_PKG_C10_RESIDENCY_REGISTER.\r | |
| 2577 | @param EDX Upper 32-bits of MSR value.\r | |
| 2578 | Described by the type MSR_HASWELL_PKG_C10_RESIDENCY_REGISTER.\r | |
| 2579 | \r | |
| 2580 | <b>Example usage</b>\r | |
| 2581 | @code\r | |
| 2582 | MSR_HASWELL_PKG_C10_RESIDENCY_REGISTER Msr;\r | |
| 2583 | \r | |
| 2584 | Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_PKG_C10_RESIDENCY);\r | |
| 2585 | AsmWriteMsr64 (MSR_HASWELL_PKG_C10_RESIDENCY, Msr.Uint64);\r | |
| 2586 | @endcode\r | |
| e108c3f6 | 2587 | @note MSR_HASWELL_PKG_C10_RESIDENCY is defined as MSR_PKG_C10_RESIDENCY in SDM.\r |
| 7ae88a62 MK |
2588 | **/\r |
| 2589 | #define MSR_HASWELL_PKG_C10_RESIDENCY 0x00000632\r | |
| 2590 | \r | |
| 2591 | /**\r | |
| 2592 | MSR information returned for MSR index #MSR_HASWELL_PKG_C10_RESIDENCY\r | |
| 2593 | **/\r | |
| 2594 | typedef union {\r | |
| 2595 | ///\r | |
| 2596 | /// Individual bit fields\r | |
| 2597 | ///\r | |
| 2598 | struct {\r | |
| 2599 | ///\r | |
| 2600 | /// [Bits 31:0] Package C10 Residency Counter. (R/O) Value since last\r | |
| 2601 | /// reset that this package is in processor-specific C10 states. Count at\r | |
| 2602 | /// the same frequency as the TSC.\r | |
| 2603 | ///\r | |
| 2604 | UINT32 C10ResidencyCounter:32;\r | |
| 2605 | ///\r | |
| 2606 | /// [Bits 59:32] Package C10 Residency Counter. (R/O) Value since last\r | |
| 2607 | /// reset that this package is in processor-specific C10 states. Count at\r | |
| 2608 | /// the same frequency as the TSC.\r | |
| 2609 | ///\r | |
| 2610 | UINT32 C10ResidencyCounterHi:28;\r | |
| 2611 | UINT32 Reserved:4;\r | |
| 2612 | } Bits;\r | |
| 2613 | ///\r | |
| 2614 | /// All bit fields as a 64-bit value\r | |
| 2615 | ///\r | |
| 2616 | UINT64 Uint64;\r | |
| 2617 | } MSR_HASWELL_PKG_C10_RESIDENCY_REGISTER;\r | |
| 2618 | \r | |
| 2619 | #endif\r |