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UefiCpuPkg/Include: Add Haswell MSR include file
[mirror_edk2.git] / UefiCpuPkg / Include / Register / Msr / HaswellMsr.h
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MK		 1/** @file\r
2 MSR Definitions for Intel processors based on the Haswell microarchitecture.\r
3\r
4 Provides defines for Machine Specific Registers(MSR) indexes. Data structures\r
5 are provided for MSRs that contain one or more bit fields. If the MSR value\r
6 returned is a single 32-bit or 64-bit value, then a data structure is not\r
7 provided for that MSR.\r
8\r
9 Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>\r
10 This program and the accompanying materials\r
11 are licensed and made available under the terms and conditions of the BSD License\r
12 which accompanies this distribution. The full text of the license may be found at\r
13 http://opensource.org/licenses/bsd-license.php\r
14\r
15 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
16 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
17\r
18 @par Specification Reference:\r
19 Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,\r
20 December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-10.\r
21\r
22**/\r
23\r
24#ifndef __HASWELL_MSR_H__\r
25#define __HASWELL_MSR_H__\r
26\r
27#include <Register/ArchitecturalMsr.h>\r
28\r
29/**\r
30 Package.\r
31\r
32 @param ECX MSR_HASWELL_PLATFORM_INFO (0x000000CE)\r
33 @param EAX Lower 32-bits of MSR value.\r
34 Described by the type MSR_HASWELL_PLATFORM_INFO_REGISTER.\r
35 @param EDX Upper 32-bits of MSR value.\r
36 Described by the type MSR_HASWELL_PLATFORM_INFO_REGISTER.\r
37\r
38 <b>Example usage</b>\r
39 @code\r
40 MSR_HASWELL_PLATFORM_INFO_REGISTER Msr;\r
41\r
42 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_PLATFORM_INFO);\r
43 AsmWriteMsr64 (MSR_HASWELL_PLATFORM_INFO, Msr.Uint64);\r
44 @endcode\r
45**/\r
46#define MSR_HASWELL_PLATFORM_INFO 0x000000CE\r
47\r
48/**\r
49 MSR information returned for MSR index #MSR_HASWELL_PLATFORM_INFO\r
50**/\r
51typedef union {\r
52 ///\r
53 /// Individual bit fields\r
54 ///\r
55 struct {\r
56 UINT32 Reserved1:8;\r
57 ///\r
58 /// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) The is the ratio\r
59 /// of the frequency that invariant TSC runs at. Frequency = ratio * 100\r
60 /// MHz.\r
61 ///\r
62 UINT32 MaximumNonTurboRatio:8;\r
63 UINT32 Reserved2:12;\r
64 ///\r
65 /// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O) When\r
66 /// set to 1, indicates that Programmable Ratio Limits for Turbo mode is\r
67 /// enabled, and when set to 0, indicates Programmable Ratio Limits for\r
68 /// Turbo mode is disabled.\r
69 ///\r
70 UINT32 RatioLimit:1;\r
71 ///\r
72 /// [Bit 29] Package. Programmable TDP Limit for Turbo Mode (R/O) When\r
73 /// set to 1, indicates that TDP Limits for Turbo mode are programmable,\r
74 /// and when set to 0, indicates TDP Limit for Turbo mode is not\r
75 /// programmable.\r
76 ///\r
77 UINT32 TDPLimit:1;\r
78 UINT32 Reserved3:2;\r
79 ///\r
80 /// [Bit 32] Package. Low Power Mode Support (LPM) (R/O) When set to 1,\r
81 /// indicates that LPM is supported, and when set to 0, indicates LPM is\r
82 /// not supported.\r
83 ///\r
84 UINT32 LowPowerModeSupport:1;\r
85 ///\r
86 /// [Bits 34:33] Package. Number of ConfigTDP Levels (R/O) 00: Only Base\r
87 /// TDP level available. 01: One additional TDP level available. 02: Two\r
88 /// additional TDP level available. 11: Reserved.\r
89 ///\r
90 UINT32 ConfigTDPLevels:2;\r
91 UINT32 Reserved4:5;\r
92 ///\r
93 /// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O) The is the\r
94 /// minimum ratio (maximum efficiency) that the processor can operates, in\r
95 /// units of 100MHz.\r
96 ///\r
97 UINT32 MaximumEfficiencyRatio:8;\r
98 ///\r
99 /// [Bits 55:48] Package. Minimum Operating Ratio (R/O) Contains the\r
100 /// minimum supported operating ratio in units of 100 MHz.\r
101 ///\r
102 UINT32 MinimumOperatingRatio:8;\r
103 UINT32 Reserved5:8;\r
104 } Bits;\r
105 ///\r
106 /// All bit fields as a 64-bit value\r
107 ///\r
108 UINT64 Uint64;\r
109} MSR_HASWELL_PLATFORM_INFO_REGISTER;\r
110\r
111\r
112/**\r
113 THREAD. Performance Event Select for Counter n (R/W) Supports all fields\r
114 described inTable 35-2 and the fields below.\r
115\r
116 @param ECX MSR_HASWELL_IA32_PERFEVTSELn\r
117 @param EAX Lower 32-bits of MSR value.\r
118 Described by the type MSR_HASWELL_IA32_PERFEVTSEL_REGISTER.\r
119 @param EDX Upper 32-bits of MSR value.\r
120 Described by the type MSR_HASWELL_IA32_PERFEVTSEL_REGISTER.\r
121\r
122 <b>Example usage</b>\r
123 @code\r
124 MSR_HASWELL_IA32_PERFEVTSEL_REGISTER Msr;\r
125\r
126 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_IA32_PERFEVTSEL0);\r
127 AsmWriteMsr64 (MSR_HASWELL_IA32_PERFEVTSEL0, Msr.Uint64);\r
128 @endcode\r
129 @{\r
130**/\r
131#define MSR_HASWELL_IA32_PERFEVTSEL0 0x00000186\r
132#define MSR_HASWELL_IA32_PERFEVTSEL1 0x00000187\r
133#define MSR_HASWELL_IA32_PERFEVTSEL3 0x00000189\r
134/// @}\r
135\r
136/**\r
137 MSR information returned for MSR indexes #MSR_HASWELL_IA32_PERFEVTSEL0,\r
138 #MSR_HASWELL_IA32_PERFEVTSEL1, and #MSR_HASWELL_IA32_PERFEVTSEL3.\r
139**/\r
140typedef union {\r
141 ///\r
142 /// Individual bit fields\r
143 ///\r
144 struct {\r
145 ///\r
146 /// [Bits 7:0] Event Select: Selects a performance event logic unit.\r
147 ///\r
148 UINT32 EventSelect:8;\r
149 ///\r
150 /// [Bits 15:8] UMask: Qualifies the microarchitectural condition to\r
151 /// detect on the selected event logic.\r
152 ///\r
153 UINT32 UMASK:8;\r
154 ///\r
155 /// [Bit 16] USR: Counts while in privilege level is not ring 0.\r
156 ///\r
157 UINT32 USR:1;\r
158 ///\r
159 /// [Bit 17] OS: Counts while in privilege level is ring 0.\r
160 ///\r
161 UINT32 OS:1;\r
162 ///\r
163 /// [Bit 18] Edge: Enables edge detection if set.\r
164 ///\r
165 UINT32 E:1;\r
166 ///\r
167 /// [Bit 19] PC: enables pin control.\r
168 ///\r
169 UINT32 PC:1;\r
170 ///\r
171 /// [Bit 20] INT: enables interrupt on counter overflow.\r
172 ///\r
173 UINT32 INT:1;\r
174 ///\r
175 /// [Bit 21] AnyThread: When set to 1, it enables counting the associated\r
176 /// event conditions occurring across all logical processors sharing a\r
177 /// processor core. When set to 0, the counter only increments the\r
178 /// associated event conditions occurring in the logical processor which\r
179 /// programmed the MSR.\r
180 ///\r
181 UINT32 ANY:1;\r
182 ///\r
183 /// [Bit 22] EN: enables the corresponding performance counter to commence\r
184 /// counting when this bit is set.\r
185 ///\r
186 UINT32 EN:1;\r
187 ///\r
188 /// [Bit 23] INV: invert the CMASK.\r
189 ///\r
190 UINT32 INV:1;\r
191 ///\r
192 /// [Bits 31:24] CMASK: When CMASK is not zero, the corresponding\r
193 /// performance counter increments each cycle if the event count is\r
194 /// greater than or equal to the CMASK.\r
195 ///\r
196 UINT32 CMASK:8;\r
197 UINT32 Reserved:32;\r
198 ///\r
199 /// [Bit 32] IN_TX: see Section 18.11.5.1 When IN_TX (bit 32) is set,\r
200 /// AnyThread (bit 21) should be cleared to prevent incorrect results.\r
201 ///\r
202 UINT32 IN_TX:1;\r
203 UINT32 Reserved2:31;\r
204 } Bits;\r
205 ///\r
206 /// All bit fields as a 64-bit value\r
207 ///\r
208 UINT64 Uint64;\r
209} MSR_HASWELL_IA32_PERFEVTSEL_REGISTER;\r
210\r
211\r
212/**\r
213 THREAD. Performance Event Select for Counter 2 (R/W) Supports all fields\r
214 described inTable 35-2 and the fields below.\r
215\r
216 @param ECX MSR_HASWELL_IA32_PERFEVTSEL2 (0x00000188)\r
217 @param EAX Lower 32-bits of MSR value.\r
218 Described by the type MSR_HASWELL_IA32_PERFEVTSEL2_REGISTER.\r
219 @param EDX Upper 32-bits of MSR value.\r
220 Described by the type MSR_HASWELL_IA32_PERFEVTSEL2_REGISTER.\r
221\r
222 <b>Example usage</b>\r
223 @code\r
224 MSR_HASWELL_IA32_PERFEVTSEL2_REGISTER Msr;\r
225\r
226 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_IA32_PERFEVTSEL2);\r
227 AsmWriteMsr64 (MSR_HASWELL_IA32_PERFEVTSEL2, Msr.Uint64);\r
228 @endcode\r
229**/\r
230#define MSR_HASWELL_IA32_PERFEVTSEL2 0x00000188\r
231\r
232/**\r
233 MSR information returned for MSR index #MSR_HASWELL_IA32_PERFEVTSEL2\r
234**/\r
235typedef union {\r
236 ///\r
237 /// Individual bit fields\r
238 ///\r
239 struct {\r
240 ///\r
241 /// [Bits 7:0] Event Select: Selects a performance event logic unit.\r
242 ///\r
243 UINT32 EventSelect:8;\r
244 ///\r
245 /// [Bits 15:8] UMask: Qualifies the microarchitectural condition to\r
246 /// detect on the selected event logic.\r
247 ///\r
248 UINT32 UMASK:8;\r
249 ///\r
250 /// [Bit 16] USR: Counts while in privilege level is not ring 0.\r
251 ///\r
252 UINT32 USR:1;\r
253 ///\r
254 /// [Bit 17] OS: Counts while in privilege level is ring 0.\r
255 ///\r
256 UINT32 OS:1;\r
257 ///\r
258 /// [Bit 18] Edge: Enables edge detection if set.\r
259 ///\r
260 UINT32 E:1;\r
261 ///\r
262 /// [Bit 19] PC: enables pin control.\r
263 ///\r
264 UINT32 PC:1;\r
265 ///\r
266 /// [Bit 20] INT: enables interrupt on counter overflow.\r
267 ///\r
268 UINT32 INT:1;\r
269 ///\r
270 /// [Bit 21] AnyThread: When set to 1, it enables counting the associated\r
271 /// event conditions occurring across all logical processors sharing a\r
272 /// processor core. When set to 0, the counter only increments the\r
273 /// associated event conditions occurring in the logical processor which\r
274 /// programmed the MSR.\r
275 ///\r
276 UINT32 ANY:1;\r
277 ///\r
278 /// [Bit 22] EN: enables the corresponding performance counter to commence\r
279 /// counting when this bit is set.\r
280 ///\r
281 UINT32 EN:1;\r
282 ///\r
283 /// [Bit 23] INV: invert the CMASK.\r
284 ///\r
285 UINT32 INV:1;\r
286 ///\r
287 /// [Bits 31:24] CMASK: When CMASK is not zero, the corresponding\r
288 /// performance counter increments each cycle if the event count is\r
289 /// greater than or equal to the CMASK.\r
290 ///\r
291 UINT32 CMASK:8;\r
292 UINT32 Reserved:32;\r
293 ///\r
294 /// [Bit 32] IN_TX: see Section 18.11.5.1 When IN_TX (bit 32) is set,\r
295 /// AnyThread (bit 21) should be cleared to prevent incorrect results.\r
296 ///\r
297 UINT32 IN_TX:1;\r
298 ///\r
299 /// [Bit 33] IN_TXCP: see Section 18.11.5.1 When IN_TXCP=1 & IN_TX=1 and\r
300 /// in sampling, spurious PMI may occur and transactions may continuously\r
301 /// abort near overflow conditions. Software should favor using IN_TXCP\r
302 /// for counting over sampling. If sampling, software should use large\r
303 /// "sample-after" value after clearing the counter configured to use\r
304 /// IN_TXCP and also always reset the counter even when no overflow\r
305 /// condition was reported.\r
306 ///\r
307 UINT32 IN_TXCP:1;\r
308 UINT32 Reserved2:30;\r
309 } Bits;\r
310 ///\r
311 /// All bit fields as a 64-bit value\r
312 ///\r
313 UINT64 Uint64;\r
314} MSR_HASWELL_IA32_PERFEVTSEL2_REGISTER;\r
315\r
316\r
317/**\r
318 Thread. Last Branch Record Filtering Select Register (R/W).\r
319\r
320 @param ECX MSR_HASWELL_LBR_SELECT (0x000001C8)\r
321 @param EAX Lower 32-bits of MSR value.\r
322 Described by the type MSR_HASWELL_LBR_SELECT_REGISTER.\r
323 @param EDX Upper 32-bits of MSR value.\r
324 Described by the type MSR_HASWELL_LBR_SELECT_REGISTER.\r
325\r
326 <b>Example usage</b>\r
327 @code\r
328 MSR_HASWELL_LBR_SELECT_REGISTER Msr;\r
329\r
330 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_LBR_SELECT);\r
331 AsmWriteMsr64 (MSR_HASWELL_LBR_SELECT, Msr.Uint64);\r
332 @endcode\r
333**/\r
334#define MSR_HASWELL_LBR_SELECT 0x000001C8\r
335\r
336/**\r
337 MSR information returned for MSR index #MSR_HASWELL_LBR_SELECT\r
338**/\r
339typedef union {\r
340 ///\r
341 /// Individual bit fields\r
342 ///\r
343 struct {\r
344 ///\r
345 /// [Bit 0] CPL_EQ_0.\r
346 ///\r
347 UINT32 CPL_EQ_0:1;\r
348 ///\r
349 /// [Bit 1] CPL_NEQ_0.\r
350 ///\r
351 UINT32 CPL_NEQ_0:1;\r
352 ///\r
353 /// [Bit 2] JCC.\r
354 ///\r
355 UINT32 JCC:1;\r
356 ///\r
357 /// [Bit 3] NEAR_REL_CALL.\r
358 ///\r
359 UINT32 NEAR_REL_CALL:1;\r
360 ///\r
361 /// [Bit 4] NEAR_IND_CALL.\r
362 ///\r
363 UINT32 NEAR_IND_CALL:1;\r
364 ///\r
365 /// [Bit 5] NEAR_RET.\r
366 ///\r
367 UINT32 NEAR_RET:1;\r
368 ///\r
369 /// [Bit 6] NEAR_IND_JMP.\r
370 ///\r
371 UINT32 NEAR_IND_JMP:1;\r
372 ///\r
373 /// [Bit 7] NEAR_REL_JMP.\r
374 ///\r
375 UINT32 NEAR_REL_JMP:1;\r
376 ///\r
377 /// [Bit 8] FAR_BRANCH.\r
378 ///\r
379 UINT32 FAR_BRANCH:1;\r
380 ///\r
381 /// [Bit 9] EN_CALL_STACK.\r
382 ///\r
383 UINT32 EN_CALL_STACK:1;\r
384 UINT32 Reserved1:22;\r
385 UINT32 Reserved2:32;\r
386 } Bits;\r
387 ///\r
388 /// All bit fields as a 32-bit value\r
389 ///\r
390 UINT32 Uint32;\r
391 ///\r
392 /// All bit fields as a 64-bit value\r
393 ///\r
394 UINT64 Uint64;\r
395} MSR_HASWELL_LBR_SELECT_REGISTER;\r
396\r
397\r
398/**\r
399 Package. Package C6/C7 Interrupt Response Limit 1 (R/W) This MSR defines\r
400 the interrupt response time limit used by the processor to manage transition\r
401 to package C6 or C7 state. The latency programmed in this register is for\r
402 the shorter-latency sub C-states used by an MWAIT hint to C6 or C7 state.\r
403 Note: C-state values are processor specific C-state code names, unrelated to\r
404 MWAIT extension C-state parameters or ACPI C-States.\r
405\r
406 @param ECX MSR_HASWELL_PKGC_IRTL1 (0x0000060B)\r
407 @param EAX Lower 32-bits of MSR value.\r
408 Described by the type MSR_HASWELL_PKGC_IRTL1_REGISTER.\r
409 @param EDX Upper 32-bits of MSR value.\r
410 Described by the type MSR_HASWELL_PKGC_IRTL1_REGISTER.\r
411\r
412 <b>Example usage</b>\r
413 @code\r
414 MSR_HASWELL_PKGC_IRTL1_REGISTER Msr;\r
415\r
416 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_PKGC_IRTL1);\r
417 AsmWriteMsr64 (MSR_HASWELL_PKGC_IRTL1, Msr.Uint64);\r
418 @endcode\r
419**/\r
420#define MSR_HASWELL_PKGC_IRTL1 0x0000060B\r
421\r
422/**\r
423 MSR information returned for MSR index #MSR_HASWELL_PKGC_IRTL1\r
424**/\r
425typedef union {\r
426 ///\r
427 /// Individual bit fields\r
428 ///\r
429 struct {\r
430 ///\r
431 /// [Bits 9:0] Interrupt response time limit (R/W) Specifies the limit\r
432 /// that should be used to decide if the package should be put into a\r
433 /// package C6 or C7 state.\r
434 ///\r
435 UINT32 InterruptResponseTimeLimit:10;\r
436 ///\r
437 /// [Bits 12:10] Time Unit (R/W) Specifies the encoding value of time\r
438 /// unit of the interrupt response time limit. The following time unit\r
439 /// encodings are supported:\r
440 ///\r
441 /// 000b: 1 ns\r
442 /// 001b: 32 ns\r
443 /// 010b: 1024 ns\r
444 /// 011b: 32768 ns\r
445 /// 100b: 1048576 ns\r
446 /// 101b: 33554432 ns.\r
447 ///\r
448 UINT32 TimeUnit:3;\r
449 UINT32 Reserved1:2;\r
450 ///\r
451 /// [Bit 15] Valid (R/W) Indicates whether the values in bits 12:0 are\r
452 /// valid and can be used by the processor for package C-sate management.\r
453 ///\r
454 UINT32 Valid:1;\r
455 UINT32 Reserved2:16;\r
456 UINT32 Reserved3:32;\r
457 } Bits;\r
458 ///\r
459 /// All bit fields as a 32-bit value\r
460 ///\r
461 UINT32 Uint32;\r
462 ///\r
463 /// All bit fields as a 64-bit value\r
464 ///\r
465 UINT64 Uint64;\r
466} MSR_HASWELL_PKGC_IRTL1_REGISTER;\r
467\r
468\r
469/**\r
470 Package. Package C6/C7 Interrupt Response Limit 2 (R/W) This MSR defines\r
471 the interrupt response time limit used by the processor to manage transition\r
472 to package C6 or C7 state. The latency programmed in this register is for\r
473 the longer-latency sub Cstates used by an MWAIT hint to C6 or C7 state.\r
474 Note: C-state values are processor specific C-state code names, unrelated to\r
475 MWAIT extension C-state parameters or ACPI C-States.\r
476\r
477 @param ECX MSR_HASWELL_PKGC_IRTL2 (0x0000060C)\r
478 @param EAX Lower 32-bits of MSR value.\r
479 Described by the type MSR_HASWELL_PKGC_IRTL2_REGISTER.\r
480 @param EDX Upper 32-bits of MSR value.\r
481 Described by the type MSR_HASWELL_PKGC_IRTL2_REGISTER.\r
482\r
483 <b>Example usage</b>\r
484 @code\r
485 MSR_HASWELL_PKGC_IRTL2_REGISTER Msr;\r
486\r
487 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_PKGC_IRTL2);\r
488 AsmWriteMsr64 (MSR_HASWELL_PKGC_IRTL2, Msr.Uint64);\r
489 @endcode\r
490**/\r
491#define MSR_HASWELL_PKGC_IRTL2 0x0000060C\r
492\r
493/**\r
494 MSR information returned for MSR index #MSR_HASWELL_PKGC_IRTL2\r
495**/\r
496typedef union {\r
497 ///\r
498 /// Individual bit fields\r
499 ///\r
500 struct {\r
501 ///\r
502 /// [Bits 9:0] Interrupt response time limit (R/W) Specifies the limit\r
503 /// that should be used to decide if the package should be put into a\r
504 /// package C6 or C7 state.\r
505 ///\r
506 UINT32 InterruptResponseTimeLimit:10;\r
507 ///\r
508 /// [Bits 12:10] Time Unit (R/W) Specifies the encoding value of time\r
509 /// unit of the interrupt response time limit. The following time unit\r
510 /// encodings are supported:\r
511 ///\r
512 /// 000b: 1 ns\r
513 /// 001b: 32 ns\r
514 /// 010b: 1024 ns\r
515 /// 011b: 32768 ns\r
516 /// 100b: 1048576 ns\r
517 /// 101b: 33554432 ns.\r
518 ///\r
519 UINT32 TimeUnit:3;\r
520 UINT32 Reserved1:2;\r
521 ///\r
522 /// [Bit 15] Valid (R/W) Indicates whether the values in bits 12:0 are\r
523 /// valid and can be used by the processor for package C-sate management.\r
524 ///\r
525 UINT32 Valid:1;\r
526 UINT32 Reserved2:16;\r
527 UINT32 Reserved3:32;\r
528 } Bits;\r
529 ///\r
530 /// All bit fields as a 32-bit value\r
531 ///\r
532 UINT32 Uint32;\r
533 ///\r
534 /// All bit fields as a 64-bit value\r
535 ///\r
536 UINT64 Uint64;\r
537} MSR_HASWELL_PKGC_IRTL2_REGISTER;\r
538\r
539\r
540/**\r
541 Package. PKG Perf Status (R/O) See Section 14.9.3, "Package RAPL Domain.".\r
542\r
543 @param ECX MSR_HASWELL_PKG_PERF_STATUS (0x00000613)\r
544 @param EAX Lower 32-bits of MSR value.\r
545 @param EDX Upper 32-bits of MSR value.\r
546\r
547 <b>Example usage</b>\r
548 @code\r
549 UINT64 Msr;\r
550\r
551 Msr = AsmReadMsr64 (MSR_HASWELL_PKG_PERF_STATUS);\r
552 @endcode\r
553**/\r
554#define MSR_HASWELL_PKG_PERF_STATUS 0x00000613\r
555\r
556\r
557/**\r
558 Package. DRAM Energy Status (R/O) See Section 14.9.5, "DRAM RAPL Domain.".\r
559\r
560 @param ECX MSR_HASWELL_DRAM_ENERGY_STATUS (0x00000619)\r
561 @param EAX Lower 32-bits of MSR value.\r
562 @param EDX Upper 32-bits of MSR value.\r
563\r
564 <b>Example usage</b>\r
565 @code\r
566 UINT64 Msr;\r
567\r
568 Msr = AsmReadMsr64 (MSR_HASWELL_DRAM_ENERGY_STATUS);\r
569 @endcode\r
570**/\r
571#define MSR_HASWELL_DRAM_ENERGY_STATUS 0x00000619\r
572\r
573\r
574/**\r
575 Package. DRAM Performance Throttling Status (R/O) See Section 14.9.5, "DRAM\r
576 RAPL Domain.".\r
577\r
578 @param ECX MSR_HASWELL_DRAM_PERF_STATUS (0x0000061B)\r
579 @param EAX Lower 32-bits of MSR value.\r
580 @param EDX Upper 32-bits of MSR value.\r
581\r
582 <b>Example usage</b>\r
583 @code\r
584 UINT64 Msr;\r
585\r
586 Msr = AsmReadMsr64 (MSR_HASWELL_DRAM_PERF_STATUS);\r
587 @endcode\r
588**/\r
589#define MSR_HASWELL_DRAM_PERF_STATUS 0x0000061B\r
590\r
591\r
592/**\r
593 Package. Base TDP Ratio (R/O).\r
594\r
595 @param ECX MSR_HASWELL_CONFIG_TDP_NOMINAL (0x00000648)\r
596 @param EAX Lower 32-bits of MSR value.\r
597 Described by the type MSR_HASWELL_CONFIG_TDP_NOMINAL_REGISTER.\r
598 @param EDX Upper 32-bits of MSR value.\r
599 Described by the type MSR_HASWELL_CONFIG_TDP_NOMINAL_REGISTER.\r
600\r
601 <b>Example usage</b>\r
602 @code\r
603 MSR_HASWELL_CONFIG_TDP_NOMINAL_REGISTER Msr;\r
604\r
605 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_CONFIG_TDP_NOMINAL);\r
606 @endcode\r
607**/\r
608#define MSR_HASWELL_CONFIG_TDP_NOMINAL 0x00000648\r
609\r
610/**\r
611 MSR information returned for MSR index #MSR_HASWELL_CONFIG_TDP_NOMINAL\r
612**/\r
613typedef union {\r
614 ///\r
615 /// Individual bit fields\r
616 ///\r
617 struct {\r
618 ///\r
619 /// [Bits 7:0] Config_TDP_Base Base TDP level ratio to be used for this\r
620 /// specific processor (in units of 100 MHz).\r
621 ///\r
622 UINT32 Config_TDP_Base:8;\r
623 UINT32 Reserved1:24;\r
624 UINT32 Reserved2:32;\r
625 } Bits;\r
626 ///\r
627 /// All bit fields as a 32-bit value\r
628 ///\r
629 UINT32 Uint32;\r
630 ///\r
631 /// All bit fields as a 64-bit value\r
632 ///\r
633 UINT64 Uint64;\r
634} MSR_HASWELL_CONFIG_TDP_NOMINAL_REGISTER;\r
635\r
636\r
637/**\r
638 Package. ConfigTDP Level 1 ratio and power level (R/O).\r
639\r
640 @param ECX MSR_HASWELL_CONFIG_TDP_LEVEL1 (0x00000649)\r
641 @param EAX Lower 32-bits of MSR value.\r
642 Described by the type MSR_HASWELL_CONFIG_TDP_LEVEL1_REGISTER.\r
643 @param EDX Upper 32-bits of MSR value.\r
644 Described by the type MSR_HASWELL_CONFIG_TDP_LEVEL1_REGISTER.\r
645\r
646 <b>Example usage</b>\r
647 @code\r
648 MSR_HASWELL_CONFIG_TDP_LEVEL1_REGISTER Msr;\r
649\r
650 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_CONFIG_TDP_LEVEL1);\r
651 @endcode\r
652**/\r
653#define MSR_HASWELL_CONFIG_TDP_LEVEL1 0x00000649\r
654\r
655/**\r
656 MSR information returned for MSR index #MSR_HASWELL_CONFIG_TDP_LEVEL1\r
657**/\r
658typedef union {\r
659 ///\r
660 /// Individual bit fields\r
661 ///\r
662 struct {\r
663 ///\r
664 /// [Bits 14:0] PKG_TDP_LVL1. Power setting for ConfigTDP Level 1.\r
665 ///\r
666 UINT32 PKG_TDP_LVL1:15;\r
667 UINT32 Reserved1:1;\r
668 ///\r
669 /// [Bits 23:16] Config_TDP_LVL1_Ratio. ConfigTDP level 1 ratio to be used\r
670 /// for this specific processor.\r
671 ///\r
672 UINT32 Config_TDP_LVL1_Ratio:8;\r
673 UINT32 Reserved2:8;\r
674 ///\r
675 /// [Bits 46:32] PKG_MAX_PWR_LVL1. Max Power setting allowed for ConfigTDP\r
676 /// Level 1.\r
677 ///\r
678 UINT32 PKG_MAX_PWR_LVL1:15;\r
679 ///\r
680 /// [Bits 62:47] PKG_MIN_PWR_LVL1. MIN Power setting allowed for ConfigTDP\r
681 /// Level 1.\r
682 ///\r
683 UINT32 PKG_MIN_PWR_LVL1:16;\r
684 UINT32 Reserved3:1;\r
685 } Bits;\r
686 ///\r
687 /// All bit fields as a 64-bit value\r
688 ///\r
689 UINT64 Uint64;\r
690} MSR_HASWELL_CONFIG_TDP_LEVEL1_REGISTER;\r
691\r
692\r
693/**\r
694 Package. ConfigTDP Level 2 ratio and power level (R/O).\r
695\r
696 @param ECX MSR_HASWELL_CONFIG_TDP_LEVEL2 (0x0000064A)\r
697 @param EAX Lower 32-bits of MSR value.\r
698 Described by the type MSR_HASWELL_CONFIG_TDP_LEVEL2_REGISTER.\r
699 @param EDX Upper 32-bits of MSR value.\r
700 Described by the type MSR_HASWELL_CONFIG_TDP_LEVEL2_REGISTER.\r
701\r
702 <b>Example usage</b>\r
703 @code\r
704 MSR_HASWELL_CONFIG_TDP_LEVEL2_REGISTER Msr;\r
705\r
706 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_CONFIG_TDP_LEVEL2);\r
707 @endcode\r
708**/\r
709#define MSR_HASWELL_CONFIG_TDP_LEVEL2 0x0000064A\r
710\r
711/**\r
712 MSR information returned for MSR index #MSR_HASWELL_CONFIG_TDP_LEVEL2\r
713**/\r
714typedef union {\r
715 ///\r
716 /// Individual bit fields\r
717 ///\r
718 struct {\r
719 ///\r
720 /// [Bits 14:0] PKG_TDP_LVL2. Power setting for ConfigTDP Level 2.\r
721 ///\r
722 UINT32 PKG_TDP_LVL2:15;\r
723 UINT32 Reserved1:1;\r
724 ///\r
725 /// [Bits 23:16] Config_TDP_LVL2_Ratio. ConfigTDP level 2 ratio to be used\r
726 /// for this specific processor.\r
727 ///\r
728 UINT32 Config_TDP_LVL2_Ratio:8;\r
729 UINT32 Reserved2:8;\r
730 ///\r
731 /// [Bits 46:32] PKG_MAX_PWR_LVL2. Max Power setting allowed for ConfigTDP\r
732 /// Level 2.\r
733 ///\r
734 UINT32 PKG_MAX_PWR_LVL2:15;\r
735 ///\r
736 /// [Bits 62:47] PKG_MIN_PWR_LVL2. MIN Power setting allowed for ConfigTDP\r
737 /// Level 2.\r
738 ///\r
739 UINT32 PKG_MIN_PWR_LVL2:16;\r
740 UINT32 Reserved3:1;\r
741 } Bits;\r
742 ///\r
743 /// All bit fields as a 64-bit value\r
744 ///\r
745 UINT64 Uint64;\r
746} MSR_HASWELL_CONFIG_TDP_LEVEL2_REGISTER;\r
747\r
748\r
749/**\r
750 Package. ConfigTDP Control (R/W).\r
751\r
752 @param ECX MSR_HASWELL_CONFIG_TDP_CONTROL (0x0000064B)\r
753 @param EAX Lower 32-bits of MSR value.\r
754 Described by the type MSR_HASWELL_CONFIG_TDP_CONTROL_REGISTER.\r
755 @param EDX Upper 32-bits of MSR value.\r
756 Described by the type MSR_HASWELL_CONFIG_TDP_CONTROL_REGISTER.\r
757\r
758 <b>Example usage</b>\r
759 @code\r
760 MSR_HASWELL_CONFIG_TDP_CONTROL_REGISTER Msr;\r
761\r
762 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_CONFIG_TDP_CONTROL);\r
763 AsmWriteMsr64 (MSR_HASWELL_CONFIG_TDP_CONTROL, Msr.Uint64);\r
764 @endcode\r
765**/\r
766#define MSR_HASWELL_CONFIG_TDP_CONTROL 0x0000064B\r
767\r
768/**\r
769 MSR information returned for MSR index #MSR_HASWELL_CONFIG_TDP_CONTROL\r
770**/\r
771typedef union {\r
772 ///\r
773 /// Individual bit fields\r
774 ///\r
775 struct {\r
776 ///\r
777 /// [Bits 1:0] TDP_LEVEL (RW/L) System BIOS can program this field.\r
778 ///\r
779 UINT32 TDP_LEVEL:2;\r
780 UINT32 Reserved1:29;\r
781 ///\r
782 /// [Bit 31] Config_TDP_Lock (RW/L) When this bit is set, the content of\r
783 /// this register is locked until a reset.\r
784 ///\r
785 UINT32 Config_TDP_Lock:1;\r
786 UINT32 Reserved2:32;\r
787 } Bits;\r
788 ///\r
789 /// All bit fields as a 32-bit value\r
790 ///\r
791 UINT32 Uint32;\r
792 ///\r
793 /// All bit fields as a 64-bit value\r
794 ///\r
795 UINT64 Uint64;\r
796} MSR_HASWELL_CONFIG_TDP_CONTROL_REGISTER;\r
797\r
798\r
799/**\r
800 Package. ConfigTDP Control (R/W).\r
801\r
802 @param ECX MSR_HASWELL_TURBO_ACTIVATION_RATIO (0x0000064C)\r
803 @param EAX Lower 32-bits of MSR value.\r
804 Described by the type MSR_HASWELL_TURBO_ACTIVATION_RATIO_REGISTER.\r
805 @param EDX Upper 32-bits of MSR value.\r
806 Described by the type MSR_HASWELL_TURBO_ACTIVATION_RATIO_REGISTER.\r
807\r
808 <b>Example usage</b>\r
809 @code\r
810 MSR_HASWELL_TURBO_ACTIVATION_RATIO_REGISTER Msr;\r
811\r
812 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_TURBO_ACTIVATION_RATIO);\r
813 AsmWriteMsr64 (MSR_HASWELL_TURBO_ACTIVATION_RATIO, Msr.Uint64);\r
814 @endcode\r
815**/\r
816#define MSR_HASWELL_TURBO_ACTIVATION_RATIO 0x0000064C\r
817\r
818/**\r
819 MSR information returned for MSR index #MSR_HASWELL_TURBO_ACTIVATION_RATIO\r
820**/\r
821typedef union {\r
822 ///\r
823 /// Individual bit fields\r
824 ///\r
825 struct {\r
826 ///\r
827 /// [Bits 7:0] MAX_NON_TURBO_RATIO (RW/L) System BIOS can program this\r
828 /// field.\r
829 ///\r
830 UINT32 MAX_NON_TURBO_RATIO:8;\r
831 UINT32 Reserved1:23;\r
832 ///\r
833 /// [Bit 31] TURBO_ACTIVATION_RATIO_Lock (RW/L) When this bit is set, the\r
834 /// content of this register is locked until a reset.\r
835 ///\r
836 UINT32 TURBO_ACTIVATION_RATIO_Lock:1;\r
837 UINT32 Reserved2:32;\r
838 } Bits;\r
839 ///\r
840 /// All bit fields as a 32-bit value\r
841 ///\r
842 UINT32 Uint32;\r
843 ///\r
844 /// All bit fields as a 64-bit value\r
845 ///\r
846 UINT64 Uint64;\r
847} MSR_HASWELL_TURBO_ACTIVATION_RATIO_REGISTER;\r
848\r
849\r
850/**\r
851 Package. Silicon Debug Feature Control (R/W) See Table 35-2.\r
852\r
853 @param ECX MSR_HASWELL_IA32_DEBUG_FEATURE (0x00000C80)\r
854 @param EAX Lower 32-bits of MSR value.\r
855 @param EDX Upper 32-bits of MSR value.\r
856\r
857 <b>Example usage</b>\r
858 @code\r
859 UINT64 Msr;\r
860\r
861 Msr = AsmReadMsr64 (MSR_HASWELL_IA32_DEBUG_FEATURE);\r
862 AsmWriteMsr64 (MSR_HASWELL_IA32_DEBUG_FEATURE, Msr);\r
863 @endcode\r
864**/\r
865#define MSR_HASWELL_IA32_DEBUG_FEATURE 0x00000C80\r
866\r
867\r
868/**\r
869 Core. C-State Configuration Control (R/W) Note: C-state values are processor\r
870 specific C-state code names, unrelated to MWAIT extension C-state parameters\r
871 or ACPI Cstates. `See http://biosbits.org. <http://biosbits.org>`__.\r
872\r
873 @param ECX MSR_HASWELL_PKG_CST_CONFIG_CONTROL (0x000000E2)\r
874 @param EAX Lower 32-bits of MSR value.\r
875 Described by the type MSR_HASWELL_PKG_CST_CONFIG_CONTROL_REGISTER.\r
876 @param EDX Upper 32-bits of MSR value.\r
877 Described by the type MSR_HASWELL_PKG_CST_CONFIG_CONTROL_REGISTER.\r
878\r
879 <b>Example usage</b>\r
880 @code\r
881 MSR_HASWELL_PKG_CST_CONFIG_CONTROL_REGISTER Msr;\r
882\r
883 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_PKG_CST_CONFIG_CONTROL);\r
884 AsmWriteMsr64 (MSR_HASWELL_PKG_CST_CONFIG_CONTROL, Msr.Uint64);\r
885 @endcode\r
886**/\r
887#define MSR_HASWELL_PKG_CST_CONFIG_CONTROL 0x000000E2\r
888\r
889/**\r
890 MSR information returned for MSR index #MSR_HASWELL_PKG_CST_CONFIG_CONTROL\r
891**/\r
892typedef union {\r
893 ///\r
894 /// Individual bit fields\r
895 ///\r
896 struct {\r
897 ///\r
898 /// [Bits 3:0] Package C-State Limit (R/W) Specifies the lowest\r
899 /// processor-specific C-state code name (consuming the least power) for\r
900 /// the package. The default is set as factory-configured package C-state\r
901 /// limit. The following C-state code name encodings are supported: 0000b:\r
902 /// C0/C1 (no package C-state support) 0001b: C2 0010b: C3 0011b: C6\r
903 /// 0100b: C7 0101b: C7s Package C states C7 are not available to\r
904 /// processor with signature 06_3CH.\r
905 ///\r
906 UINT32 Limit:4;\r
907 UINT32 Reserved1:6;\r
908 ///\r
909 /// [Bit 10] I/O MWAIT Redirection Enable (R/W).\r
910 ///\r
911 UINT32 IO_MWAIT:1;\r
912 UINT32 Reserved2:4;\r
913 ///\r
914 /// [Bit 15] CFG Lock (R/WO).\r
915 ///\r
916 UINT32 CFGLock:1;\r
917 UINT32 Reserved3:9;\r
918 ///\r
919 /// [Bit 25] C3 State Auto Demotion Enable (R/W).\r
920 ///\r
921 UINT32 C3AutoDemotion:1;\r
922 ///\r
923 /// [Bit 26] C1 State Auto Demotion Enable (R/W).\r
924 ///\r
925 UINT32 C1AutoDemotion:1;\r
926 ///\r
927 /// [Bit 27] Enable C3 Undemotion (R/W).\r
928 ///\r
929 UINT32 C3Undemotion:1;\r
930 ///\r
931 /// [Bit 28] Enable C1 Undemotion (R/W).\r
932 ///\r
933 UINT32 C1Undemotion:1;\r
934 UINT32 Reserved4:3;\r
935 UINT32 Reserved5:32;\r
936 } Bits;\r
937 ///\r
938 /// All bit fields as a 32-bit value\r
939 ///\r
940 UINT32 Uint32;\r
941 ///\r
942 /// All bit fields as a 64-bit value\r
943 ///\r
944 UINT64 Uint64;\r
945} MSR_HASWELL_PKG_CST_CONFIG_CONTROL_REGISTER;\r
946\r
947\r
948/**\r
949 THREAD. Enhanced SMM Capabilities (SMM-RO) Reports SMM capability\r
950 Enhancement. Accessible only while in SMM.\r
951\r
952 @param ECX MSR_HASWELL_SMM_MCA_CAP (0x0000017D)\r
953 @param EAX Lower 32-bits of MSR value.\r
954 Described by the type MSR_HASWELL_SMM_MCA_CAP_REGISTER.\r
955 @param EDX Upper 32-bits of MSR value.\r
956 Described by the type MSR_HASWELL_SMM_MCA_CAP_REGISTER.\r
957\r
958 <b>Example usage</b>\r
959 @code\r
960 MSR_HASWELL_SMM_MCA_CAP_REGISTER Msr;\r
961\r
962 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_SMM_MCA_CAP);\r
963 AsmWriteMsr64 (MSR_HASWELL_SMM_MCA_CAP, Msr.Uint64);\r
964 @endcode\r
965**/\r
966#define MSR_HASWELL_SMM_MCA_CAP 0x0000017D\r
967\r
968/**\r
969 MSR information returned for MSR index #MSR_HASWELL_SMM_MCA_CAP\r
970**/\r
971typedef union {\r
972 ///\r
973 /// Individual bit fields\r
974 ///\r
975 struct {\r
976 UINT32 Reserved1:32;\r
977 UINT32 Reserved2:26;\r
978 ///\r
979 /// [Bit 58] SMM_Code_Access_Chk (SMM-RO) If set to 1 indicates that the\r
980 /// SMM code access restriction is supported and the\r
981 /// MSR_SMM_FEATURE_CONTROL is supported.\r
982 ///\r
983 UINT32 SMM_Code_Access_Chk:1;\r
984 ///\r
985 /// [Bit 59] Long_Flow_Indication (SMM-RO) If set to 1 indicates that the\r
986 /// SMM long flow indicator is supported and the MSR_SMM_DELAYED is\r
987 /// supported.\r
988 ///\r
989 UINT32 Long_Flow_Indication:1;\r
990 UINT32 Reserved3:4;\r
991 } Bits;\r
992 ///\r
993 /// All bit fields as a 64-bit value\r
994 ///\r
995 UINT64 Uint64;\r
996} MSR_HASWELL_SMM_MCA_CAP_REGISTER;\r
997\r
998\r
999/**\r
1000 Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,\r
1001 RW if MSR_PLATFORM_INFO.[28] = 1.\r
1002\r
1003 @param ECX MSR_HASWELL_TURBO_RATIO_LIMIT (0x000001AD)\r
1004 @param EAX Lower 32-bits of MSR value.\r
1005 Described by the type MSR_HASWELL_TURBO_RATIO_LIMIT_REGISTER.\r
1006 @param EDX Upper 32-bits of MSR value.\r
1007 Described by the type MSR_HASWELL_TURBO_RATIO_LIMIT_REGISTER.\r
1008\r
1009 <b>Example usage</b>\r
1010 @code\r
1011 MSR_HASWELL_TURBO_RATIO_LIMIT_REGISTER Msr;\r
1012\r
1013 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_TURBO_RATIO_LIMIT);\r
1014 @endcode\r
1015**/\r
1016#define MSR_HASWELL_TURBO_RATIO_LIMIT 0x000001AD\r
1017\r
1018/**\r
1019 MSR information returned for MSR index #MSR_HASWELL_TURBO_RATIO_LIMIT\r
1020**/\r
1021typedef union {\r
1022 ///\r
1023 /// Individual bit fields\r
1024 ///\r
1025 struct {\r
1026 ///\r
1027 /// [Bits 7:0] Package. Maximum Ratio Limit for 1C Maximum turbo ratio\r
1028 /// limit of 1 core active.\r
1029 ///\r
1030 UINT32 Maximum1C:8;\r
1031 ///\r
1032 /// [Bits 15:8] Package. Maximum Ratio Limit for 2C Maximum turbo ratio\r
1033 /// limit of 2 core active.\r
1034 ///\r
1035 UINT32 Maximum2C:8;\r
1036 ///\r
1037 /// [Bits 23:16] Package. Maximum Ratio Limit for 3C Maximum turbo ratio\r
1038 /// limit of 3 core active.\r
1039 ///\r
1040 UINT32 Maximum3C:8;\r
1041 ///\r
1042 /// [Bits 31:24] Package. Maximum Ratio Limit for 4C Maximum turbo ratio\r
1043 /// limit of 4 core active.\r
1044 ///\r
1045 UINT32 Maximum4C:8;\r
1046 UINT32 Reserved:32;\r
1047 } Bits;\r
1048 ///\r
1049 /// All bit fields as a 32-bit value\r
1050 ///\r
1051 UINT32 Uint32;\r
1052 ///\r
1053 /// All bit fields as a 64-bit value\r
1054 ///\r
1055 UINT64 Uint64;\r
1056} MSR_HASWELL_TURBO_RATIO_LIMIT_REGISTER;\r
1057\r
1058\r
1059/**\r
1060 Package. Uncore PMU global control.\r
1061\r
1062 @param ECX MSR_HASWELL_UNC_PERF_GLOBAL_CTRL (0x00000391)\r
1063 @param EAX Lower 32-bits of MSR value.\r
1064 Described by the type MSR_HASWELL_UNC_PERF_GLOBAL_CTRL_REGISTER.\r
1065 @param EDX Upper 32-bits of MSR value.\r
1066 Described by the type MSR_HASWELL_UNC_PERF_GLOBAL_CTRL_REGISTER.\r
1067\r
1068 <b>Example usage</b>\r
1069 @code\r
1070 MSR_HASWELL_UNC_PERF_GLOBAL_CTRL_REGISTER Msr;\r
1071\r
1072 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_UNC_PERF_GLOBAL_CTRL);\r
1073 AsmWriteMsr64 (MSR_HASWELL_UNC_PERF_GLOBAL_CTRL, Msr.Uint64);\r
1074 @endcode\r
1075**/\r
1076#define MSR_HASWELL_UNC_PERF_GLOBAL_CTRL 0x00000391\r
1077\r
1078/**\r
1079 MSR information returned for MSR index #MSR_HASWELL_UNC_PERF_GLOBAL_CTRL\r
1080**/\r
1081typedef union {\r
1082 ///\r
1083 /// Individual bit fields\r
1084 ///\r
1085 struct {\r
1086 ///\r
1087 /// [Bit 0] Core 0 select.\r
1088 ///\r
1089 UINT32 PMI_Sel_Core0:1;\r
1090 ///\r
1091 /// [Bit 1] Core 1 select.\r
1092 ///\r
1093 UINT32 PMI_Sel_Core1:1;\r
1094 ///\r
1095 /// [Bit 2] Core 2 select.\r
1096 ///\r
1097 UINT32 PMI_Sel_Core2:1;\r
1098 ///\r
1099 /// [Bit 3] Core 3 select.\r
1100 ///\r
1101 UINT32 PMI_Sel_Core3:1;\r
1102 UINT32 Reserved1:15;\r
1103 UINT32 Reserved2:10;\r
1104 ///\r
1105 /// [Bit 29] Enable all uncore counters.\r
1106 ///\r
1107 UINT32 EN:1;\r
1108 ///\r
1109 /// [Bit 30] Enable wake on PMI.\r
1110 ///\r
1111 UINT32 WakePMI:1;\r
1112 ///\r
1113 /// [Bit 31] Enable Freezing counter when overflow.\r
1114 ///\r
1115 UINT32 FREEZE:1;\r
1116 UINT32 Reserved3:32;\r
1117 } Bits;\r
1118 ///\r
1119 /// All bit fields as a 32-bit value\r
1120 ///\r
1121 UINT32 Uint32;\r
1122 ///\r
1123 /// All bit fields as a 64-bit value\r
1124 ///\r
1125 UINT64 Uint64;\r
1126} MSR_HASWELL_UNC_PERF_GLOBAL_CTRL_REGISTER;\r
1127\r
1128\r
1129/**\r
1130 Package. Uncore PMU main status.\r
1131\r
1132 @param ECX MSR_HASWELL_UNC_PERF_GLOBAL_STATUS (0x00000392)\r
1133 @param EAX Lower 32-bits of MSR value.\r
1134 Described by the type MSR_HASWELL_UNC_PERF_GLOBAL_STATUS_REGISTER.\r
1135 @param EDX Upper 32-bits of MSR value.\r
1136 Described by the type MSR_HASWELL_UNC_PERF_GLOBAL_STATUS_REGISTER.\r
1137\r
1138 <b>Example usage</b>\r
1139 @code\r
1140 MSR_HASWELL_UNC_PERF_GLOBAL_STATUS_REGISTER Msr;\r
1141\r
1142 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_UNC_PERF_GLOBAL_STATUS);\r
1143 AsmWriteMsr64 (MSR_HASWELL_UNC_PERF_GLOBAL_STATUS, Msr.Uint64);\r
1144 @endcode\r
1145**/\r
1146#define MSR_HASWELL_UNC_PERF_GLOBAL_STATUS 0x00000392\r
1147\r
1148/**\r
1149 MSR information returned for MSR index #MSR_HASWELL_UNC_PERF_GLOBAL_STATUS\r
1150**/\r
1151typedef union {\r
1152 ///\r
1153 /// Individual bit fields\r
1154 ///\r
1155 struct {\r
1156 ///\r
1157 /// [Bit 0] Fixed counter overflowed.\r
1158 ///\r
1159 UINT32 Fixed:1;\r
1160 ///\r
1161 /// [Bit 1] An ARB counter overflowed.\r
1162 ///\r
1163 UINT32 ARB:1;\r
1164 UINT32 Reserved1:1;\r
1165 ///\r
1166 /// [Bit 3] A CBox counter overflowed (on any slice).\r
1167 ///\r
1168 UINT32 CBox:1;\r
1169 UINT32 Reserved2:28;\r
1170 UINT32 Reserved3:32;\r
1171 } Bits;\r
1172 ///\r
1173 /// All bit fields as a 32-bit value\r
1174 ///\r
1175 UINT32 Uint32;\r
1176 ///\r
1177 /// All bit fields as a 64-bit value\r
1178 ///\r
1179 UINT64 Uint64;\r
1180} MSR_HASWELL_UNC_PERF_GLOBAL_STATUS_REGISTER;\r
1181\r
1182\r
1183/**\r
1184 Package. Uncore fixed counter control (R/W).\r
1185\r
1186 @param ECX MSR_HASWELL_UNC_PERF_FIXED_CTRL (0x00000394)\r
1187 @param EAX Lower 32-bits of MSR value.\r
1188 Described by the type MSR_HASWELL_UNC_PERF_FIXED_CTRL_REGISTER.\r
1189 @param EDX Upper 32-bits of MSR value.\r
1190 Described by the type MSR_HASWELL_UNC_PERF_FIXED_CTRL_REGISTER.\r
1191\r
1192 <b>Example usage</b>\r
1193 @code\r
1194 MSR_HASWELL_UNC_PERF_FIXED_CTRL_REGISTER Msr;\r
1195\r
1196 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_UNC_PERF_FIXED_CTRL);\r
1197 AsmWriteMsr64 (MSR_HASWELL_UNC_PERF_FIXED_CTRL, Msr.Uint64);\r
1198 @endcode\r
1199**/\r
1200#define MSR_HASWELL_UNC_PERF_FIXED_CTRL 0x00000394\r
1201\r
1202/**\r
1203 MSR information returned for MSR index #MSR_HASWELL_UNC_PERF_FIXED_CTRL\r
1204**/\r
1205typedef union {\r
1206 ///\r
1207 /// Individual bit fields\r
1208 ///\r
1209 struct {\r
1210 UINT32 Reserved1:20;\r
1211 ///\r
1212 /// [Bit 20] Enable overflow propagation.\r
1213 ///\r
1214 UINT32 EnableOverflow:1;\r
1215 UINT32 Reserved2:1;\r
1216 ///\r
1217 /// [Bit 22] Enable counting.\r
1218 ///\r
1219 UINT32 EnableCounting:1;\r
1220 UINT32 Reserved3:9;\r
1221 UINT32 Reserved4:32;\r
1222 } Bits;\r
1223 ///\r
1224 /// All bit fields as a 32-bit value\r
1225 ///\r
1226 UINT32 Uint32;\r
1227 ///\r
1228 /// All bit fields as a 64-bit value\r
1229 ///\r
1230 UINT64 Uint64;\r
1231} MSR_HASWELL_UNC_PERF_FIXED_CTRL_REGISTER;\r
1232\r
1233\r
1234/**\r
1235 Package. Uncore fixed counter.\r
1236\r
1237 @param ECX MSR_HASWELL_UNC_PERF_FIXED_CTR (0x00000395)\r
1238 @param EAX Lower 32-bits of MSR value.\r
1239 Described by the type MSR_HASWELL_UNC_PERF_FIXED_CTR_REGISTER.\r
1240 @param EDX Upper 32-bits of MSR value.\r
1241 Described by the type MSR_HASWELL_UNC_PERF_FIXED_CTR_REGISTER.\r
1242\r
1243 <b>Example usage</b>\r
1244 @code\r
1245 MSR_HASWELL_UNC_PERF_FIXED_CTR_REGISTER Msr;\r
1246\r
1247 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_UNC_PERF_FIXED_CTR);\r
1248 AsmWriteMsr64 (MSR_HASWELL_UNC_PERF_FIXED_CTR, Msr.Uint64);\r
1249 @endcode\r
1250**/\r
1251#define MSR_HASWELL_UNC_PERF_FIXED_CTR 0x00000395\r
1252\r
1253/**\r
1254 MSR information returned for MSR index #MSR_HASWELL_UNC_PERF_FIXED_CTR\r
1255**/\r
1256typedef union {\r
1257 ///\r
1258 /// Individual bit fields\r
1259 ///\r
1260 struct {\r
1261 ///\r
1262 /// [Bits 31:0] Current count.\r
1263 ///\r
1264 UINT32 CurrentCount:32;\r
1265 ///\r
1266 /// [Bits 47:32] Current count.\r
1267 ///\r
1268 UINT32 CurrentCountHi:16;\r
1269 UINT32 Reserved:16;\r
1270 } Bits;\r
1271 ///\r
1272 /// All bit fields as a 64-bit value\r
1273 ///\r
1274 UINT64 Uint64;\r
1275} MSR_HASWELL_UNC_PERF_FIXED_CTR_REGISTER;\r
1276\r
1277\r
1278/**\r
1279 Package. Uncore C-Box configuration information (R/O).\r
1280\r
1281 @param ECX MSR_HASWELL_UNC_CBO_CONFIG (0x00000396)\r
1282 @param EAX Lower 32-bits of MSR value.\r
1283 Described by the type MSR_HASWELL_UNC_CBO_CONFIG_REGISTER.\r
1284 @param EDX Upper 32-bits of MSR value.\r
1285 Described by the type MSR_HASWELL_UNC_CBO_CONFIG_REGISTER.\r
1286\r
1287 <b>Example usage</b>\r
1288 @code\r
1289 MSR_HASWELL_UNC_CBO_CONFIG_REGISTER Msr;\r
1290\r
1291 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_CONFIG);\r
1292 @endcode\r
1293**/\r
1294#define MSR_HASWELL_UNC_CBO_CONFIG 0x00000396\r
1295\r
1296/**\r
1297 MSR information returned for MSR index #MSR_HASWELL_UNC_CBO_CONFIG\r
1298**/\r
1299typedef union {\r
1300 ///\r
1301 /// Individual bit fields\r
1302 ///\r
1303 struct {\r
1304 ///\r
1305 /// [Bits 3:0] Encoded number of C-Box, derive value by "-1".\r
1306 ///\r
1307 UINT32 CBox:4;\r
1308 UINT32 Reserved1:28;\r
1309 UINT32 Reserved2:32;\r
1310 } Bits;\r
1311 ///\r
1312 /// All bit fields as a 32-bit value\r
1313 ///\r
1314 UINT32 Uint32;\r
1315 ///\r
1316 /// All bit fields as a 64-bit value\r
1317 ///\r
1318 UINT64 Uint64;\r
1319} MSR_HASWELL_UNC_CBO_CONFIG_REGISTER;\r
1320\r
1321\r
1322/**\r
1323 Package. Uncore Arb unit, performance counter 0.\r
1324\r
1325 @param ECX MSR_HASWELL_UNC_ARB_PERFCTR0 (0x000003B0)\r
1326 @param EAX Lower 32-bits of MSR value.\r
1327 @param EDX Upper 32-bits of MSR value.\r
1328\r
1329 <b>Example usage</b>\r
1330 @code\r
1331 UINT64 Msr;\r
1332\r
1333 Msr = AsmReadMsr64 (MSR_HASWELL_UNC_ARB_PERFCTR0);\r
1334 AsmWriteMsr64 (MSR_HASWELL_UNC_ARB_PERFCTR0, Msr);\r
1335 @endcode\r
1336**/\r
1337#define MSR_HASWELL_UNC_ARB_PERFCTR0 0x000003B0\r
1338\r
1339\r
1340/**\r
1341 Package. Uncore Arb unit, performance counter 1.\r
1342\r
1343 @param ECX MSR_HASWELL_UNC_ARB_PERFCTR1 (0x000003B1)\r
1344 @param EAX Lower 32-bits of MSR value.\r
1345 @param EDX Upper 32-bits of MSR value.\r
1346\r
1347 <b>Example usage</b>\r
1348 @code\r
1349 UINT64 Msr;\r
1350\r
1351 Msr = AsmReadMsr64 (MSR_HASWELL_UNC_ARB_PERFCTR1);\r
1352 AsmWriteMsr64 (MSR_HASWELL_UNC_ARB_PERFCTR1, Msr);\r
1353 @endcode\r
1354**/\r
1355#define MSR_HASWELL_UNC_ARB_PERFCTR1 0x000003B1\r
1356\r
1357\r
1358/**\r
1359 Package. Uncore Arb unit, counter 0 event select MSR.\r
1360\r
1361 @param ECX MSR_HASWELL_UNC_ARB_PERFEVTSEL0 (0x000003B2)\r
1362 @param EAX Lower 32-bits of MSR value.\r
1363 @param EDX Upper 32-bits of MSR value.\r
1364\r
1365 <b>Example usage</b>\r
1366 @code\r
1367 UINT64 Msr;\r
1368\r
1369 Msr = AsmReadMsr64 (MSR_HASWELL_UNC_ARB_PERFEVTSEL0);\r
1370 AsmWriteMsr64 (MSR_HASWELL_UNC_ARB_PERFEVTSEL0, Msr);\r
1371 @endcode\r
1372**/\r
1373#define MSR_HASWELL_UNC_ARB_PERFEVTSEL0 0x000003B2\r
1374\r
1375\r
1376/**\r
1377 Package. Uncore Arb unit, counter 1 event select MSR.\r
1378\r
1379 @param ECX MSR_HASWELL_UNC_ARB_PERFEVTSEL1 (0x000003B3)\r
1380 @param EAX Lower 32-bits of MSR value.\r
1381 @param EDX Upper 32-bits of MSR value.\r
1382\r
1383 <b>Example usage</b>\r
1384 @code\r
1385 UINT64 Msr;\r
1386\r
1387 Msr = AsmReadMsr64 (MSR_HASWELL_UNC_ARB_PERFEVTSEL1);\r
1388 AsmWriteMsr64 (MSR_HASWELL_UNC_ARB_PERFEVTSEL1, Msr);\r
1389 @endcode\r
1390**/\r
1391#define MSR_HASWELL_UNC_ARB_PERFEVTSEL1 0x000003B3\r
1392\r
1393\r
1394/**\r
1395 Package. Enhanced SMM Feature Control (SMM-RW) Reports SMM capability\r
1396 Enhancement. Accessible only while in SMM.\r
1397\r
1398 @param ECX MSR_HASWELL_SMM_FEATURE_CONTROL (0x000004E0)\r
1399 @param EAX Lower 32-bits of MSR value.\r
1400 Described by the type MSR_HASWELL_SMM_FEATURE_CONTROL_REGISTER.\r
1401 @param EDX Upper 32-bits of MSR value.\r
1402 Described by the type MSR_HASWELL_SMM_FEATURE_CONTROL_REGISTER.\r
1403\r
1404 <b>Example usage</b>\r
1405 @code\r
1406 MSR_HASWELL_SMM_FEATURE_CONTROL_REGISTER Msr;\r
1407\r
1408 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_SMM_FEATURE_CONTROL);\r
1409 AsmWriteMsr64 (MSR_HASWELL_SMM_FEATURE_CONTROL, Msr.Uint64);\r
1410 @endcode\r
1411**/\r
1412#define MSR_HASWELL_SMM_FEATURE_CONTROL 0x000004E0\r
1413\r
1414/**\r
1415 MSR information returned for MSR index #MSR_HASWELL_SMM_FEATURE_CONTROL\r
1416**/\r
1417typedef union {\r
1418 ///\r
1419 /// Individual bit fields\r
1420 ///\r
1421 struct {\r
1422 ///\r
1423 /// [Bit 0] Lock (SMM-RWO) When set to '1' locks this register from\r
1424 /// further changes.\r
1425 ///\r
1426 UINT32 Lock:1;\r
1427 UINT32 Reserved1:1;\r
1428 ///\r
1429 /// [Bit 2] SMM_Code_Chk_En (SMM-RW) This control bit is available only if\r
1430 /// MSR_SMM_MCA_CAP[58] == 1. When set to '0' (default) none of the\r
1431 /// logical processors are prevented from executing SMM code outside the\r
1432 /// ranges defined by the SMRR. When set to '1' any logical processor in\r
1433 /// the package that attempts to execute SMM code not within the ranges\r
1434 /// defined by the SMRR will assert an unrecoverable MCE.\r
1435 ///\r
1436 UINT32 SMM_Code_Chk_En:1;\r
1437 UINT32 Reserved2:29;\r
1438 UINT32 Reserved3:32;\r
1439 } Bits;\r
1440 ///\r
1441 /// All bit fields as a 32-bit value\r
1442 ///\r
1443 UINT32 Uint32;\r
1444 ///\r
1445 /// All bit fields as a 64-bit value\r
1446 ///\r
1447 UINT64 Uint64;\r
1448} MSR_HASWELL_SMM_FEATURE_CONTROL_REGISTER;\r
1449\r
1450\r
1451/**\r
1452 Package. SMM Delayed (SMM-RO) Reports the interruptible state of all logical\r
1453 processors in the package. Available only while in SMM and\r
1454 MSR_SMM_MCA_CAP[LONG_FLOW_INDICATION] == 1.\r
1455\r
1456 [Bits 31:0] LOG_PROC_STATE (SMM-RO) Each bit represents a logical\r
1457 processor of its state in a long flow of internal operation which\r
1458 delays servicing an interrupt. The corresponding bit will be set at\r
1459 the start of long events such as: Microcode Update Load, C6, WBINVD,\r
1460 Ratio Change, Throttle. The bit is automatically cleared at the end of\r
1461 each long event. The reset value of this field is 0. Only bit\r
1462 positions below N = CPUID.(EAX=0BH, ECX=PKG_LVL):EBX[15:0] can be\r
1463 updated.\r
1464\r
1465 [Bits 63:32] LOG_PROC_STATE (SMM-RO) Each bit represents a logical\r
1466 processor of its state in a long flow of internal operation which\r
1467 delays servicing an interrupt. The corresponding bit will be set at\r
1468 the start of long events such as: Microcode Update Load, C6, WBINVD,\r
1469 Ratio Change, Throttle. The bit is automatically cleared at the end of\r
1470 each long event. The reset value of this field is 0. Only bit\r
1471 positions below N = CPUID.(EAX=0BH, ECX=PKG_LVL):EBX[15:0] can be\r
1472 updated.\r
1473\r
1474 @param ECX MSR_HASWELL_SMM_DELAYED (0x000004E2)\r
1475 @param EAX Lower 32-bits of MSR value.\r
1476 @param EDX Upper 32-bits of MSR value.\r
1477\r
1478 <b>Example usage</b>\r
1479 @code\r
1480 UINT64 Msr;\r
1481\r
1482 Msr = AsmReadMsr64 (MSR_HASWELL_SMM_DELAYED);\r
1483 @endcode\r
1484**/\r
1485#define MSR_HASWELL_SMM_DELAYED 0x000004E2\r
1486\r
1487\r
1488/**\r
1489 Package. SMM Blocked (SMM-RO) Reports the blocked state of all logical\r
1490 processors in the package. Available only while in SMM.\r
1491\r
1492 [Bits 31:0] LOG_PROC_STATE (SMM-RO) Each bit represents a logical\r
1493 processor of its blocked state to service an SMI. The corresponding\r
1494 bit will be set if the logical processor is in one of the following\r
1495 states: Wait For SIPI or SENTER Sleep. The reset value of this field\r
1496 is 0FFFH. Only bit positions below N = CPUID.(EAX=0BH,\r
1497 ECX=PKG_LVL):EBX[15:0] can be updated.\r
1498\r
1499\r
1500 [Bits 63:32] LOG_PROC_STATE (SMM-RO) Each bit represents a logical\r
1501 processor of its blocked state to service an SMI. The corresponding\r
1502 bit will be set if the logical processor is in one of the following\r
1503 states: Wait For SIPI or SENTER Sleep. The reset value of this field\r
1504 is 0FFFH. Only bit positions below N = CPUID.(EAX=0BH,\r
1505 ECX=PKG_LVL):EBX[15:0] can be updated.\r
1506\r
1507 @param ECX MSR_HASWELL_SMM_BLOCKED (0x000004E3)\r
1508 @param EAX Lower 32-bits of MSR value.\r
1509 @param EDX Upper 32-bits of MSR value.\r
1510\r
1511 <b>Example usage</b>\r
1512 @code\r
1513 UINT64 Msr;\r
1514\r
1515 Msr = AsmReadMsr64 (MSR_HASWELL_SMM_BLOCKED);\r
1516 @endcode\r
1517**/\r
1518#define MSR_HASWELL_SMM_BLOCKED 0x000004E3\r
1519\r
1520\r
1521/**\r
1522 Package. Unit Multipliers used in RAPL Interfaces (R/O).\r
1523\r
1524 @param ECX MSR_HASWELL_RAPL_POWER_UNIT (0x00000606)\r
1525 @param EAX Lower 32-bits of MSR value.\r
1526 Described by the type MSR_HASWELL_RAPL_POWER_UNIT_REGISTER.\r
1527 @param EDX Upper 32-bits of MSR value.\r
1528 Described by the type MSR_HASWELL_RAPL_POWER_UNIT_REGISTER.\r
1529\r
1530 <b>Example usage</b>\r
1531 @code\r
1532 MSR_HASWELL_RAPL_POWER_UNIT_REGISTER Msr;\r
1533\r
1534 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_RAPL_POWER_UNIT);\r
1535 @endcode\r
1536**/\r
1537#define MSR_HASWELL_RAPL_POWER_UNIT 0x00000606\r
1538\r
1539/**\r
1540 MSR information returned for MSR index #MSR_HASWELL_RAPL_POWER_UNIT\r
1541**/\r
1542typedef union {\r
1543 ///\r
1544 /// Individual bit fields\r
1545 ///\r
1546 struct {\r
1547 ///\r
1548 /// [Bits 3:0] Package. Power Units See Section 14.9.1, "RAPL Interfaces.".\r
1549 ///\r
1550 UINT32 PowerUnits:4;\r
1551 UINT32 Reserved1:4;\r
1552 ///\r
1553 /// [Bits 12:8] Package. Energy Status Units Energy related information\r
1554 /// (in Joules) is based on the multiplier, 1/2^ESU; where ESU is an\r
1555 /// unsigned integer represented by bits 12:8. Default value is 0EH (or 61\r
1556 /// micro-joules).\r
1557 ///\r
1558 UINT32 EnergyStatusUnits:5;\r
1559 UINT32 Reserved2:3;\r
1560 ///\r
1561 /// [Bits 19:16] Package. Time Units See Section 14.9.1, "RAPL\r
1562 /// Interfaces.".\r
1563 ///\r
1564 UINT32 TimeUnits:4;\r
1565 UINT32 Reserved3:12;\r
1566 UINT32 Reserved4:32;\r
1567 } Bits;\r
1568 ///\r
1569 /// All bit fields as a 32-bit value\r
1570 ///\r
1571 UINT32 Uint32;\r
1572 ///\r
1573 /// All bit fields as a 64-bit value\r
1574 ///\r
1575 UINT64 Uint64;\r
1576} MSR_HASWELL_RAPL_POWER_UNIT_REGISTER;\r
1577\r
1578\r
1579/**\r
1580 Package. PP1 RAPL Power Limit Control (R/W) See Section 14.9.4, "PP0/PP1\r
1581 RAPL Domains.".\r
1582\r
1583 @param ECX MSR_HASWELL_PP1_POWER_LIMIT (0x00000640)\r
1584 @param EAX Lower 32-bits of MSR value.\r
1585 @param EDX Upper 32-bits of MSR value.\r
1586\r
1587 <b>Example usage</b>\r
1588 @code\r
1589 UINT64 Msr;\r
1590\r
1591 Msr = AsmReadMsr64 (MSR_HASWELL_PP1_POWER_LIMIT);\r
1592 AsmWriteMsr64 (MSR_HASWELL_PP1_POWER_LIMIT, Msr);\r
1593 @endcode\r
1594**/\r
1595#define MSR_HASWELL_PP1_POWER_LIMIT 0x00000640\r
1596\r
1597\r
1598/**\r
1599 Package. PP1 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL\r
1600 Domains.".\r
1601\r
1602 @param ECX MSR_HASWELL_PP1_ENERGY_STATUS (0x00000641)\r
1603 @param EAX Lower 32-bits of MSR value.\r
1604 @param EDX Upper 32-bits of MSR value.\r
1605\r
1606 <b>Example usage</b>\r
1607 @code\r
1608 UINT64 Msr;\r
1609\r
1610 Msr = AsmReadMsr64 (MSR_HASWELL_PP1_ENERGY_STATUS);\r
1611 @endcode\r
1612**/\r
1613#define MSR_HASWELL_PP1_ENERGY_STATUS 0x00000641\r
1614\r
1615\r
1616/**\r
1617 Package. PP1 Balance Policy (R/W) See Section 14.9.4, "PP0/PP1 RAPL\r
1618 Domains.".\r
1619\r
1620 @param ECX MSR_HASWELL_PP1_POLICY (0x00000642)\r
1621 @param EAX Lower 32-bits of MSR value.\r
1622 @param EDX Upper 32-bits of MSR value.\r
1623\r
1624 <b>Example usage</b>\r
1625 @code\r
1626 UINT64 Msr;\r
1627\r
1628 Msr = AsmReadMsr64 (MSR_HASWELL_PP1_POLICY);\r
1629 AsmWriteMsr64 (MSR_HASWELL_PP1_POLICY, Msr);\r
1630 @endcode\r
1631**/\r
1632#define MSR_HASWELL_PP1_POLICY 0x00000642\r
1633\r
1634\r
1635/**\r
1636 Package. Indicator of Frequency Clipping in Processor Cores (R/W) (frequency\r
1637 refers to processor core frequency).\r
1638\r
1639 @param ECX MSR_HASWELL_CORE_PERF_LIMIT_REASONS (0x00000690)\r
1640 @param EAX Lower 32-bits of MSR value.\r
1641 Described by the type MSR_HASWELL_CORE_PERF_LIMIT_REASONS_REGISTER.\r
1642 @param EDX Upper 32-bits of MSR value.\r
1643 Described by the type MSR_HASWELL_CORE_PERF_LIMIT_REASONS_REGISTER.\r
1644\r
1645 <b>Example usage</b>\r
1646 @code\r
1647 MSR_HASWELL_CORE_PERF_LIMIT_REASONS_REGISTER Msr;\r
1648\r
1649 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_CORE_PERF_LIMIT_REASONS);\r
1650 AsmWriteMsr64 (MSR_HASWELL_CORE_PERF_LIMIT_REASONS, Msr.Uint64);\r
1651 @endcode\r
1652**/\r
1653#define MSR_HASWELL_CORE_PERF_LIMIT_REASONS 0x00000690\r
1654\r
1655/**\r
1656 MSR information returned for MSR index #MSR_HASWELL_CORE_PERF_LIMIT_REASONS\r
1657**/\r
1658typedef union {\r
1659 ///\r
1660 /// Individual bit fields\r
1661 ///\r
1662 struct {\r
1663 ///\r
1664 /// [Bit 0] PROCHOT Status (R0) When set, processor core frequency is\r
1665 /// reduced below the operating system request due to assertion of\r
1666 /// external PROCHOT.\r
1667 ///\r
1668 UINT32 PROCHOT_Status:1;\r
1669 ///\r
1670 /// [Bit 1] Thermal Status (R0) When set, frequency is reduced below the\r
1671 /// operating system request due to a thermal event.\r
1672 ///\r
1673 UINT32 ThermalStatus:1;\r
1674 UINT32 Reserved1:2;\r
1675 ///\r
1676 /// [Bit 4] Graphics Driver Status (R0) When set, frequency is reduced\r
1677 /// below the operating system request due to Processor Graphics driver\r
1678 /// override.\r
1679 ///\r
1680 UINT32 GraphicsDriverStatus:1;\r
1681 ///\r
1682 /// [Bit 5] Autonomous Utilization-Based Frequency Control Status (R0)\r
1683 /// When set, frequency is reduced below the operating system request\r
1684 /// because the processor has detected that utilization is low.\r
1685 ///\r
1686 UINT32 AutonomousUtilizationBasedFrequencyControlStatus:1;\r
1687 ///\r
1688 /// [Bit 6] VR Therm Alert Status (R0) When set, frequency is reduced\r
1689 /// below the operating system request due to a thermal alert from the\r
1690 /// Voltage Regulator.\r
1691 ///\r
1692 UINT32 VRThermAlertStatus:1;\r
1693 UINT32 Reserved2:1;\r
1694 ///\r
1695 /// [Bit 8] Electrical Design Point Status (R0) When set, frequency is\r
1696 /// reduced below the operating system request due to electrical design\r
1697 /// point constraints (e.g. maximum electrical current consumption).\r
1698 ///\r
1699 UINT32 ElectricalDesignPointStatus:1;\r
1700 ///\r
1701 /// [Bit 9] Core Power Limiting Status (R0) When set, frequency is reduced\r
1702 /// below the operating system request due to domain-level power limiting.\r
1703 ///\r
1704 UINT32 PLStatus:1;\r
1705 ///\r
1706 /// [Bit 10] Package-Level Power Limiting PL1 Status (R0) When set,\r
1707 /// frequency is reduced below the operating system request due to\r
1708 /// package-level power limiting PL1.\r
1709 ///\r
1710 UINT32 PL1Status:1;\r
1711 ///\r
1712 /// [Bit 11] Package-Level PL2 Power Limiting Status (R0) When set,\r
1713 /// frequency is reduced below the operating system request due to\r
1714 /// package-level power limiting PL2.\r
1715 ///\r
1716 UINT32 PL2Status:1;\r
1717 ///\r
1718 /// [Bit 12] Max Turbo Limit Status (R0) When set, frequency is reduced\r
1719 /// below the operating system request due to multi-core turbo limits.\r
1720 ///\r
1721 UINT32 MaxTurboLimitStatus:1;\r
1722 ///\r
1723 /// [Bit 13] Turbo Transition Attenuation Status (R0) When set, frequency\r
1724 /// is reduced below the operating system request due to Turbo transition\r
1725 /// attenuation. This prevents performance degradation due to frequent\r
1726 /// operating ratio changes.\r
1727 ///\r
1728 UINT32 TurboTransitionAttenuationStatus:1;\r
1729 UINT32 Reserved3:2;\r
1730 ///\r
1731 /// [Bit 16] PROCHOT Log When set, indicates that the PROCHOT Status bit\r
1732 /// has asserted since the log bit was last cleared. This log bit will\r
1733 /// remain set until cleared by software writing 0.\r
1734 ///\r
1735 UINT32 PROCHOT_Log:1;\r
1736 ///\r
1737 /// [Bit 17] Thermal Log When set, indicates that the Thermal Status bit\r
1738 /// has asserted since the log bit was last cleared. This log bit will\r
1739 /// remain set until cleared by software writing 0.\r
1740 ///\r
1741 UINT32 ThermalLog:1;\r
1742 UINT32 Reserved4:2;\r
1743 ///\r
1744 /// [Bit 20] Graphics Driver Log When set, indicates that the Graphics\r
1745 /// Driver Status bit has asserted since the log bit was last cleared.\r
1746 /// This log bit will remain set until cleared by software writing 0.\r
1747 ///\r
1748 UINT32 GraphicsDriverLog:1;\r
1749 ///\r
1750 /// [Bit 21] Autonomous Utilization-Based Frequency Control Log When set,\r
1751 /// indicates that the Autonomous Utilization-Based Frequency Control\r
1752 /// Status bit has asserted since the log bit was last cleared. This log\r
1753 /// bit will remain set until cleared by software writing 0.\r
1754 ///\r
1755 UINT32 AutonomousUtilizationBasedFrequencyControlLog:1;\r
1756 ///\r
1757 /// [Bit 22] VR Therm Alert Log When set, indicates that the VR Therm\r
1758 /// Alert Status bit has asserted since the log bit was last cleared. This\r
1759 /// log bit will remain set until cleared by software writing 0.\r
1760 ///\r
1761 UINT32 VRThermAlertLog:1;\r
1762 UINT32 Reserved5:1;\r
1763 ///\r
1764 /// [Bit 24] Electrical Design Point Log When set, indicates that the EDP\r
1765 /// Status bit has asserted since the log bit was last cleared. This log\r
1766 /// bit will remain set until cleared by software writing 0.\r
1767 ///\r
1768 UINT32 ElectricalDesignPointLog:1;\r
1769 ///\r
1770 /// [Bit 25] Core Power Limiting Log When set, indicates that the Core\r
1771 /// Power Limiting Status bit has asserted since the log bit was last\r
1772 /// cleared. This log bit will remain set until cleared by software\r
1773 /// writing 0.\r
1774 ///\r
1775 UINT32 PLLog:1;\r
1776 ///\r
1777 /// [Bit 26] Package-Level PL1 Power Limiting Log When set, indicates\r
1778 /// that the Package Level PL1 Power Limiting Status bit has asserted\r
1779 /// since the log bit was last cleared. This log bit will remain set until\r
1780 /// cleared by software writing 0.\r
1781 ///\r
1782 UINT32 PL1Log:1;\r
1783 ///\r
1784 /// [Bit 27] Package-Level PL2 Power Limiting Log When set, indicates that\r
1785 /// the Package Level PL2 Power Limiting Status bit has asserted since the\r
1786 /// log bit was last cleared. This log bit will remain set until cleared\r
1787 /// by software writing 0.\r
1788 ///\r
1789 UINT32 PL2Log:1;\r
1790 ///\r
1791 /// [Bit 28] Max Turbo Limit Log When set, indicates that the Max Turbo\r
1792 /// Limit Status bit has asserted since the log bit was last cleared. This\r
1793 /// log bit will remain set until cleared by software writing 0.\r
1794 ///\r
1795 UINT32 MaxTurboLimitLog:1;\r
1796 ///\r
1797 /// [Bit 29] Turbo Transition Attenuation Log When set, indicates that the\r
1798 /// Turbo Transition Attenuation Status bit has asserted since the log bit\r
1799 /// was last cleared. This log bit will remain set until cleared by\r
1800 /// software writing 0.\r
1801 ///\r
1802 UINT32 TurboTransitionAttenuationLog:1;\r
1803 UINT32 Reserved6:2;\r
1804 UINT32 Reserved7:32;\r
1805 } Bits;\r
1806 ///\r
1807 /// All bit fields as a 32-bit value\r
1808 ///\r
1809 UINT32 Uint32;\r
1810 ///\r
1811 /// All bit fields as a 64-bit value\r
1812 ///\r
1813 UINT64 Uint64;\r
1814} MSR_HASWELL_CORE_PERF_LIMIT_REASONS_REGISTER;\r
1815\r
1816\r
1817/**\r
1818 Package. Indicator of Frequency Clipping in the Processor Graphics (R/W)\r
1819 (frequency refers to processor graphics frequency).\r
1820\r
1821 @param ECX MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS (0x000006B0)\r
1822 @param EAX Lower 32-bits of MSR value.\r
1823 Described by the type MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS_REGISTER.\r
1824 @param EDX Upper 32-bits of MSR value.\r
1825 Described by the type MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS_REGISTER.\r
1826\r
1827 <b>Example usage</b>\r
1828 @code\r
1829 MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS_REGISTER Msr;\r
1830\r
1831 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS);\r
1832 AsmWriteMsr64 (MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS, Msr.Uint64);\r
1833 @endcode\r
1834**/\r
1835#define MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS 0x000006B0\r
1836\r
1837/**\r
1838 MSR information returned for MSR index\r
1839 #MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS\r
1840**/\r
1841typedef union {\r
1842 ///\r
1843 /// Individual bit fields\r
1844 ///\r
1845 struct {\r
1846 ///\r
1847 /// [Bit 0] PROCHOT Status (R0) When set, frequency is reduced below the\r
1848 /// operating system request due to assertion of external PROCHOT.\r
1849 ///\r
1850 UINT32 PROCHOT_Status:1;\r
1851 ///\r
1852 /// [Bit 1] Thermal Status (R0) When set, frequency is reduced below the\r
1853 /// operating system request due to a thermal event.\r
1854 ///\r
1855 UINT32 ThermalStatus:1;\r
1856 UINT32 Reserved1:2;\r
1857 ///\r
1858 /// [Bit 4] Graphics Driver Status (R0) When set, frequency is reduced\r
1859 /// below the operating system request due to Processor Graphics driver\r
1860 /// override.\r
1861 ///\r
1862 UINT32 GraphicsDriverStatus:1;\r
1863 ///\r
1864 /// [Bit 5] Autonomous Utilization-Based Frequency Control Status (R0)\r
1865 /// When set, frequency is reduced below the operating system request\r
1866 /// because the processor has detected that utilization is low.\r
1867 ///\r
1868 UINT32 AutonomousUtilizationBasedFrequencyControlStatus:1;\r
1869 ///\r
1870 /// [Bit 6] VR Therm Alert Status (R0) When set, frequency is reduced\r
1871 /// below the operating system request due to a thermal alert from the\r
1872 /// Voltage Regulator.\r
1873 ///\r
1874 UINT32 VRThermAlertStatus:1;\r
1875 UINT32 Reserved2:1;\r
1876 ///\r
1877 /// [Bit 8] Electrical Design Point Status (R0) When set, frequency is\r
1878 /// reduced below the operating system request due to electrical design\r
1879 /// point constraints (e.g. maximum electrical current consumption).\r
1880 ///\r
1881 UINT32 ElectricalDesignPointStatus:1;\r
1882 ///\r
1883 /// [Bit 9] Graphics Power Limiting Status (R0) When set, frequency is\r
1884 /// reduced below the operating system request due to domain-level power\r
1885 /// limiting.\r
1886 ///\r
1887 UINT32 GraphicsPowerLimitingStatus:1;\r
1888 ///\r
1889 /// [Bit 10] Package-Level Power Limiting PL1 Status (R0) When set,\r
1890 /// frequency is reduced below the operating system request due to\r
1891 /// package-level power limiting PL1.\r
1892 ///\r
1893 UINT32 PL1STatus:1;\r
1894 ///\r
1895 /// [Bit 11] Package-Level PL2 Power Limiting Status (R0) When set,\r
1896 /// frequency is reduced below the operating system request due to\r
1897 /// package-level power limiting PL2.\r
1898 ///\r
1899 UINT32 PL2Status:1;\r
1900 UINT32 Reserved3:4;\r
1901 ///\r
1902 /// [Bit 16] PROCHOT Log When set, indicates that the PROCHOT Status bit\r
1903 /// has asserted since the log bit was last cleared. This log bit will\r
1904 /// remain set until cleared by software writing 0.\r
1905 ///\r
1906 UINT32 PROCHOT_Log:1;\r
1907 ///\r
1908 /// [Bit 17] Thermal Log When set, indicates that the Thermal Status bit\r
1909 /// has asserted since the log bit was last cleared. This log bit will\r
1910 /// remain set until cleared by software writing 0.\r
1911 ///\r
1912 UINT32 ThermalLog:1;\r
1913 UINT32 Reserved4:2;\r
1914 ///\r
1915 /// [Bit 20] Graphics Driver Log When set, indicates that the Graphics\r
1916 /// Driver Status bit has asserted since the log bit was last cleared.\r
1917 /// This log bit will remain set until cleared by software writing 0.\r
1918 ///\r
1919 UINT32 GraphicsDriverLog:1;\r
1920 ///\r
1921 /// [Bit 21] Autonomous Utilization-Based Frequency Control Log When set,\r
1922 /// indicates that the Autonomous Utilization-Based Frequency Control\r
1923 /// Status bit has asserted since the log bit was last cleared. This log\r
1924 /// bit will remain set until cleared by software writing 0.\r
1925 ///\r
1926 UINT32 AutonomousUtilizationBasedFrequencyControlLog:1;\r
1927 ///\r
1928 /// [Bit 22] VR Therm Alert Log When set, indicates that the VR Therm\r
1929 /// Alert Status bit has asserted since the log bit was last cleared. This\r
1930 /// log bit will remain set until cleared by software writing 0.\r
1931 ///\r
1932 UINT32 VRThermAlertLog:1;\r
1933 UINT32 Reserved5:1;\r
1934 ///\r
1935 /// [Bit 24] Electrical Design Point Log When set, indicates that the EDP\r
1936 /// Status bit has asserted since the log bit was last cleared. This log\r
1937 /// bit will remain set until cleared by software writing 0.\r
1938 ///\r
1939 UINT32 ElectricalDesignPointLog:1;\r
1940 ///\r
1941 /// [Bit 25] Core Power Limiting Log When set, indicates that the Core\r
1942 /// Power Limiting Status bit has asserted since the log bit was last\r
1943 /// cleared. This log bit will remain set until cleared by software\r
1944 /// writing 0.\r
1945 ///\r
1946 UINT32 CorePowerLimitingLog:1;\r
1947 ///\r
1948 /// [Bit 26] Package-Level PL1 Power Limiting Log When set, indicates\r
1949 /// that the Package Level PL1 Power Limiting Status bit has asserted\r
1950 /// since the log bit was last cleared. This log bit will remain set until\r
1951 /// cleared by software writing 0.\r
1952 ///\r
1953 UINT32 PL1Log:1;\r
1954 ///\r
1955 /// [Bit 27] Package-Level PL2 Power Limiting Log When set, indicates that\r
1956 /// the Package Level PL2 Power Limiting Status bit has asserted since the\r
1957 /// log bit was last cleared. This log bit will remain set until cleared\r
1958 /// by software writing 0.\r
1959 ///\r
1960 UINT32 PL2Log:1;\r
1961 ///\r
1962 /// [Bit 28] Max Turbo Limit Log When set, indicates that the Max Turbo\r
1963 /// Limit Status bit has asserted since the log bit was last cleared. This\r
1964 /// log bit will remain set until cleared by software writing 0.\r
1965 ///\r
1966 UINT32 MaxTurboLimitLog:1;\r
1967 ///\r
1968 /// [Bit 29] Turbo Transition Attenuation Log When set, indicates that the\r
1969 /// Turbo Transition Attenuation Status bit has asserted since the log bit\r
1970 /// was last cleared. This log bit will remain set until cleared by\r
1971 /// software writing 0.\r
1972 ///\r
1973 UINT32 TurboTransitionAttenuationLog:1;\r
1974 UINT32 Reserved6:2;\r
1975 UINT32 Reserved7:32;\r
1976 } Bits;\r
1977 ///\r
1978 /// All bit fields as a 32-bit value\r
1979 ///\r
1980 UINT32 Uint32;\r
1981 ///\r
1982 /// All bit fields as a 64-bit value\r
1983 ///\r
1984 UINT64 Uint64;\r
1985} MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS_REGISTER;\r
1986\r
1987\r
1988/**\r
1989 Package. Indicator of Frequency Clipping in the Ring Interconnect (R/W)\r
1990 (frequency refers to ring interconnect in the uncore).\r
1991\r
1992 @param ECX MSR_HASWELL_RING_PERF_LIMIT_REASONS (0x000006B1)\r
1993 @param EAX Lower 32-bits of MSR value.\r
1994 Described by the type MSR_HASWELL_RING_PERF_LIMIT_REASONS_REGISTER.\r
1995 @param EDX Upper 32-bits of MSR value.\r
1996 Described by the type MSR_HASWELL_RING_PERF_LIMIT_REASONS_REGISTER.\r
1997\r
1998 <b>Example usage</b>\r
1999 @code\r
2000 MSR_HASWELL_RING_PERF_LIMIT_REASONS_REGISTER Msr;\r
2001\r
2002 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_RING_PERF_LIMIT_REASONS);\r
2003 AsmWriteMsr64 (MSR_HASWELL_RING_PERF_LIMIT_REASONS, Msr.Uint64);\r
2004 @endcode\r
2005**/\r
2006#define MSR_HASWELL_RING_PERF_LIMIT_REASONS 0x000006B1\r
2007\r
2008/**\r
2009 MSR information returned for MSR index #MSR_HASWELL_RING_PERF_LIMIT_REASONS\r
2010**/\r
2011typedef union {\r
2012 ///\r
2013 /// Individual bit fields\r
2014 ///\r
2015 struct {\r
2016 ///\r
2017 /// [Bit 0] PROCHOT Status (R0) When set, frequency is reduced below the\r
2018 /// operating system request due to assertion of external PROCHOT.\r
2019 ///\r
2020 UINT32 PROCHOT_Status:1;\r
2021 ///\r
2022 /// [Bit 1] Thermal Status (R0) When set, frequency is reduced below the\r
2023 /// operating system request due to a thermal event.\r
2024 ///\r
2025 UINT32 ThermalStatus:1;\r
2026 UINT32 Reserved1:4;\r
2027 ///\r
2028 /// [Bit 6] VR Therm Alert Status (R0) When set, frequency is reduced\r
2029 /// below the operating system request due to a thermal alert from the\r
2030 /// Voltage Regulator.\r
2031 ///\r
2032 UINT32 VRThermAlertStatus:1;\r
2033 UINT32 Reserved2:1;\r
2034 ///\r
2035 /// [Bit 8] Electrical Design Point Status (R0) When set, frequency is\r
2036 /// reduced below the operating system request due to electrical design\r
2037 /// point constraints (e.g. maximum electrical current consumption).\r
2038 ///\r
2039 UINT32 ElectricalDesignPointStatus:1;\r
2040 UINT32 Reserved3:1;\r
2041 ///\r
2042 /// [Bit 10] Package-Level Power Limiting PL1 Status (R0) When set,\r
2043 /// frequency is reduced below the operating system request due to\r
2044 /// package-level power limiting PL1.\r
2045 ///\r
2046 UINT32 PL1STatus:1;\r
2047 ///\r
2048 /// [Bit 11] Package-Level PL2 Power Limiting Status (R0) When set,\r
2049 /// frequency is reduced below the operating system request due to\r
2050 /// package-level power limiting PL2.\r
2051 ///\r
2052 UINT32 PL2Status:1;\r
2053 UINT32 Reserved4:4;\r
2054 ///\r
2055 /// [Bit 16] PROCHOT Log When set, indicates that the PROCHOT Status bit\r
2056 /// has asserted since the log bit was last cleared. This log bit will\r
2057 /// remain set until cleared by software writing 0.\r
2058 ///\r
2059 UINT32 PROCHOT_Log:1;\r
2060 ///\r
2061 /// [Bit 17] Thermal Log When set, indicates that the Thermal Status bit\r
2062 /// has asserted since the log bit was last cleared. This log bit will\r
2063 /// remain set until cleared by software writing 0.\r
2064 ///\r
2065 UINT32 ThermalLog:1;\r
2066 UINT32 Reserved5:2;\r
2067 ///\r
2068 /// [Bit 20] Graphics Driver Log When set, indicates that the Graphics\r
2069 /// Driver Status bit has asserted since the log bit was last cleared.\r
2070 /// This log bit will remain set until cleared by software writing 0.\r
2071 ///\r
2072 UINT32 GraphicsDriverLog:1;\r
2073 ///\r
2074 /// [Bit 21] Autonomous Utilization-Based Frequency Control Log When set,\r
2075 /// indicates that the Autonomous Utilization-Based Frequency Control\r
2076 /// Status bit has asserted since the log bit was last cleared. This log\r
2077 /// bit will remain set until cleared by software writing 0.\r
2078 ///\r
2079 UINT32 AutonomousUtilizationBasedFrequencyControlLog:1;\r
2080 ///\r
2081 /// [Bit 22] VR Therm Alert Log When set, indicates that the VR Therm\r
2082 /// Alert Status bit has asserted since the log bit was last cleared. This\r
2083 /// log bit will remain set until cleared by software writing 0.\r
2084 ///\r
2085 UINT32 VRThermAlertLog:1;\r
2086 UINT32 Reserved6:1;\r
2087 ///\r
2088 /// [Bit 24] Electrical Design Point Log When set, indicates that the EDP\r
2089 /// Status bit has asserted since the log bit was last cleared. This log\r
2090 /// bit will remain set until cleared by software writing 0.\r
2091 ///\r
2092 UINT32 ElectricalDesignPointLog:1;\r
2093 ///\r
2094 /// [Bit 25] Core Power Limiting Log When set, indicates that the Core\r
2095 /// Power Limiting Status bit has asserted since the log bit was last\r
2096 /// cleared. This log bit will remain set until cleared by software\r
2097 /// writing 0.\r
2098 ///\r
2099 UINT32 CorePowerLimitingLog:1;\r
2100 ///\r
2101 /// [Bit 26] Package-Level PL1 Power Limiting Log When set, indicates\r
2102 /// that the Package Level PL1 Power Limiting Status bit has asserted\r
2103 /// since the log bit was last cleared. This log bit will remain set until\r
2104 /// cleared by software writing 0.\r
2105 ///\r
2106 UINT32 PL1Log:1;\r
2107 ///\r
2108 /// [Bit 27] Package-Level PL2 Power Limiting Log When set, indicates that\r
2109 /// the Package Level PL2 Power Limiting Status bit has asserted since the\r
2110 /// log bit was last cleared. This log bit will remain set until cleared\r
2111 /// by software writing 0.\r
2112 ///\r
2113 UINT32 PL2Log:1;\r
2114 ///\r
2115 /// [Bit 28] Max Turbo Limit Log When set, indicates that the Max Turbo\r
2116 /// Limit Status bit has asserted since the log bit was last cleared. This\r
2117 /// log bit will remain set until cleared by software writing 0.\r
2118 ///\r
2119 UINT32 MaxTurboLimitLog:1;\r
2120 ///\r
2121 /// [Bit 29] Turbo Transition Attenuation Log When set, indicates that the\r
2122 /// Turbo Transition Attenuation Status bit has asserted since the log bit\r
2123 /// was last cleared. This log bit will remain set until cleared by\r
2124 /// software writing 0.\r
2125 ///\r
2126 UINT32 TurboTransitionAttenuationLog:1;\r
2127 UINT32 Reserved7:2;\r
2128 UINT32 Reserved8:32;\r
2129 } Bits;\r
2130 ///\r
2131 /// All bit fields as a 32-bit value\r
2132 ///\r
2133 UINT32 Uint32;\r
2134 ///\r
2135 /// All bit fields as a 64-bit value\r
2136 ///\r
2137 UINT64 Uint64;\r
2138} MSR_HASWELL_RING_PERF_LIMIT_REASONS_REGISTER;\r
2139\r
2140\r
2141/**\r
2142 Package. Uncore C-Box 0, counter 0 event select MSR.\r
2143\r
2144 @param ECX MSR_HASWELL_UNC_CBO_0_PERFEVTSEL0 (0x00000700)\r
2145 @param EAX Lower 32-bits of MSR value.\r
2146 @param EDX Upper 32-bits of MSR value.\r
2147\r
2148 <b>Example usage</b>\r
2149 @code\r
2150 UINT64 Msr;\r
2151\r
2152 Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_0_PERFEVTSEL0);\r
2153 AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_0_PERFEVTSEL0, Msr);\r
2154 @endcode\r
2155**/\r
2156#define MSR_HASWELL_UNC_CBO_0_PERFEVTSEL0 0x00000700\r
2157\r
2158\r
2159/**\r
2160 Package. Uncore C-Box 0, counter 1 event select MSR.\r
2161\r
2162 @param ECX MSR_HASWELL_UNC_CBO_0_PERFEVTSEL1 (0x00000701)\r
2163 @param EAX Lower 32-bits of MSR value.\r
2164 @param EDX Upper 32-bits of MSR value.\r
2165\r
2166 <b>Example usage</b>\r
2167 @code\r
2168 UINT64 Msr;\r
2169\r
2170 Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_0_PERFEVTSEL1);\r
2171 AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_0_PERFEVTSEL1, Msr);\r
2172 @endcode\r
2173**/\r
2174#define MSR_HASWELL_UNC_CBO_0_PERFEVTSEL1 0x00000701\r
2175\r
2176\r
2177/**\r
2178 Package. Uncore C-Box 0, performance counter 0.\r
2179\r
2180 @param ECX MSR_HASWELL_UNC_CBO_0_PERFCTR0 (0x00000706)\r
2181 @param EAX Lower 32-bits of MSR value.\r
2182 @param EDX Upper 32-bits of MSR value.\r
2183\r
2184 <b>Example usage</b>\r
2185 @code\r
2186 UINT64 Msr;\r
2187\r
2188 Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_0_PERFCTR0);\r
2189 AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_0_PERFCTR0, Msr);\r
2190 @endcode\r
2191**/\r
2192#define MSR_HASWELL_UNC_CBO_0_PERFCTR0 0x00000706\r
2193\r
2194\r
2195/**\r
2196 Package. Uncore C-Box 0, performance counter 1.\r
2197\r
2198 @param ECX MSR_HASWELL_UNC_CBO_0_PERFCTR1 (0x00000707)\r
2199 @param EAX Lower 32-bits of MSR value.\r
2200 @param EDX Upper 32-bits of MSR value.\r
2201\r
2202 <b>Example usage</b>\r
2203 @code\r
2204 UINT64 Msr;\r
2205\r
2206 Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_0_PERFCTR1);\r
2207 AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_0_PERFCTR1, Msr);\r
2208 @endcode\r
2209**/\r
2210#define MSR_HASWELL_UNC_CBO_0_PERFCTR1 0x00000707\r
2211\r
2212\r
2213/**\r
2214 Package. Uncore C-Box 1, counter 0 event select MSR.\r
2215\r
2216 @param ECX MSR_HASWELL_UNC_CBO_1_PERFEVTSEL0 (0x00000710)\r
2217 @param EAX Lower 32-bits of MSR value.\r
2218 @param EDX Upper 32-bits of MSR value.\r
2219\r
2220 <b>Example usage</b>\r
2221 @code\r
2222 UINT64 Msr;\r
2223\r
2224 Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_1_PERFEVTSEL0);\r
2225 AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_1_PERFEVTSEL0, Msr);\r
2226 @endcode\r
2227**/\r
2228#define MSR_HASWELL_UNC_CBO_1_PERFEVTSEL0 0x00000710\r
2229\r
2230\r
2231/**\r
2232 Package. Uncore C-Box 1, counter 1 event select MSR.\r
2233\r
2234 @param ECX MSR_HASWELL_UNC_CBO_1_PERFEVTSEL1 (0x00000711)\r
2235 @param EAX Lower 32-bits of MSR value.\r
2236 @param EDX Upper 32-bits of MSR value.\r
2237\r
2238 <b>Example usage</b>\r
2239 @code\r
2240 UINT64 Msr;\r
2241\r
2242 Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_1_PERFEVTSEL1);\r
2243 AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_1_PERFEVTSEL1, Msr);\r
2244 @endcode\r
2245**/\r
2246#define MSR_HASWELL_UNC_CBO_1_PERFEVTSEL1 0x00000711\r
2247\r
2248\r
2249/**\r
2250 Package. Uncore C-Box 1, performance counter 0.\r
2251\r
2252 @param ECX MSR_HASWELL_UNC_CBO_1_PERFCTR0 (0x00000716)\r
2253 @param EAX Lower 32-bits of MSR value.\r
2254 @param EDX Upper 32-bits of MSR value.\r
2255\r
2256 <b>Example usage</b>\r
2257 @code\r
2258 UINT64 Msr;\r
2259\r
2260 Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_1_PERFCTR0);\r
2261 AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_1_PERFCTR0, Msr);\r
2262 @endcode\r
2263**/\r
2264#define MSR_HASWELL_UNC_CBO_1_PERFCTR0 0x00000716\r
2265\r
2266\r
2267/**\r
2268 Package. Uncore C-Box 1, performance counter 1.\r
2269\r
2270 @param ECX MSR_HASWELL_UNC_CBO_1_PERFCTR1 (0x00000717)\r
2271 @param EAX Lower 32-bits of MSR value.\r
2272 @param EDX Upper 32-bits of MSR value.\r
2273\r
2274 <b>Example usage</b>\r
2275 @code\r
2276 UINT64 Msr;\r
2277\r
2278 Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_1_PERFCTR1);\r
2279 AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_1_PERFCTR1, Msr);\r
2280 @endcode\r
2281**/\r
2282#define MSR_HASWELL_UNC_CBO_1_PERFCTR1 0x00000717\r
2283\r
2284\r
2285/**\r
2286 Package. Uncore C-Box 2, counter 0 event select MSR.\r
2287\r
2288 @param ECX MSR_HASWELL_UNC_CBO_2_PERFEVTSEL0 (0x00000720)\r
2289 @param EAX Lower 32-bits of MSR value.\r
2290 @param EDX Upper 32-bits of MSR value.\r
2291\r
2292 <b>Example usage</b>\r
2293 @code\r
2294 UINT64 Msr;\r
2295\r
2296 Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_2_PERFEVTSEL0);\r
2297 AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_2_PERFEVTSEL0, Msr);\r
2298 @endcode\r
2299**/\r
2300#define MSR_HASWELL_UNC_CBO_2_PERFEVTSEL0 0x00000720\r
2301\r
2302\r
2303/**\r
2304 Package. Uncore C-Box 2, counter 1 event select MSR.\r
2305\r
2306 @param ECX MSR_HASWELL_UNC_CBO_2_PERFEVTSEL1 (0x00000721)\r
2307 @param EAX Lower 32-bits of MSR value.\r
2308 @param EDX Upper 32-bits of MSR value.\r
2309\r
2310 <b>Example usage</b>\r
2311 @code\r
2312 UINT64 Msr;\r
2313\r
2314 Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_2_PERFEVTSEL1);\r
2315 AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_2_PERFEVTSEL1, Msr);\r
2316 @endcode\r
2317**/\r
2318#define MSR_HASWELL_UNC_CBO_2_PERFEVTSEL1 0x00000721\r
2319\r
2320\r
2321/**\r
2322 Package. Uncore C-Box 2, performance counter 0.\r
2323\r
2324 @param ECX MSR_HASWELL_UNC_CBO_2_PERFCTR0 (0x00000726)\r
2325 @param EAX Lower 32-bits of MSR value.\r
2326 @param EDX Upper 32-bits of MSR value.\r
2327\r
2328 <b>Example usage</b>\r
2329 @code\r
2330 UINT64 Msr;\r
2331\r
2332 Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_2_PERFCTR0);\r
2333 AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_2_PERFCTR0, Msr);\r
2334 @endcode\r
2335**/\r
2336#define MSR_HASWELL_UNC_CBO_2_PERFCTR0 0x00000726\r
2337\r
2338\r
2339/**\r
2340 Package. Uncore C-Box 2, performance counter 1.\r
2341\r
2342 @param ECX MSR_HASWELL_UNC_CBO_2_PERFCTR1 (0x00000727)\r
2343 @param EAX Lower 32-bits of MSR value.\r
2344 @param EDX Upper 32-bits of MSR value.\r
2345\r
2346 <b>Example usage</b>\r
2347 @code\r
2348 UINT64 Msr;\r
2349\r
2350 Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_2_PERFCTR1);\r
2351 AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_2_PERFCTR1, Msr);\r
2352 @endcode\r
2353**/\r
2354#define MSR_HASWELL_UNC_CBO_2_PERFCTR1 0x00000727\r
2355\r
2356\r
2357/**\r
2358 Package. Uncore C-Box 3, counter 0 event select MSR.\r
2359\r
2360 @param ECX MSR_HASWELL_UNC_CBO_3_PERFEVTSEL0 (0x00000730)\r
2361 @param EAX Lower 32-bits of MSR value.\r
2362 @param EDX Upper 32-bits of MSR value.\r
2363\r
2364 <b>Example usage</b>\r
2365 @code\r
2366 UINT64 Msr;\r
2367\r
2368 Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_3_PERFEVTSEL0);\r
2369 AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_3_PERFEVTSEL0, Msr);\r
2370 @endcode\r
2371**/\r
2372#define MSR_HASWELL_UNC_CBO_3_PERFEVTSEL0 0x00000730\r
2373\r
2374\r
2375/**\r
2376 Package. Uncore C-Box 3, counter 1 event select MSR.\r
2377\r
2378 @param ECX MSR_HASWELL_UNC_CBO_3_PERFEVTSEL1 (0x00000731)\r
2379 @param EAX Lower 32-bits of MSR value.\r
2380 @param EDX Upper 32-bits of MSR value.\r
2381\r
2382 <b>Example usage</b>\r
2383 @code\r
2384 UINT64 Msr;\r
2385\r
2386 Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_3_PERFEVTSEL1);\r
2387 AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_3_PERFEVTSEL1, Msr);\r
2388 @endcode\r
2389**/\r
2390#define MSR_HASWELL_UNC_CBO_3_PERFEVTSEL1 0x00000731\r
2391\r
2392\r
2393/**\r
2394 Package. Uncore C-Box 3, performance counter 0.\r
2395\r
2396 @param ECX MSR_HASWELL_UNC_CBO_3_PERFCTR0 (0x00000736)\r
2397 @param EAX Lower 32-bits of MSR value.\r
2398 @param EDX Upper 32-bits of MSR value.\r
2399\r
2400 <b>Example usage</b>\r
2401 @code\r
2402 UINT64 Msr;\r
2403\r
2404 Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_3_PERFCTR0);\r
2405 AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_3_PERFCTR0, Msr);\r
2406 @endcode\r
2407**/\r
2408#define MSR_HASWELL_UNC_CBO_3_PERFCTR0 0x00000736\r
2409\r
2410\r
2411/**\r
2412 Package. Uncore C-Box 3, performance counter 1.\r
2413\r
2414 @param ECX MSR_HASWELL_UNC_CBO_3_PERFCTR1 (0x00000737)\r
2415 @param EAX Lower 32-bits of MSR value.\r
2416 @param EDX Upper 32-bits of MSR value.\r
2417\r
2418 <b>Example usage</b>\r
2419 @code\r
2420 UINT64 Msr;\r
2421\r
2422 Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_3_PERFCTR1);\r
2423 AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_3_PERFCTR1, Msr);\r
2424 @endcode\r
2425**/\r
2426#define MSR_HASWELL_UNC_CBO_3_PERFCTR1 0x00000737\r
2427\r
2428\r
2429/**\r
2430 Package. Note: C-state values are processor specific C-state code names,\r
2431 unrelated to MWAIT extension C-state parameters or ACPI C-States.\r
2432\r
2433 @param ECX MSR_HASWELL_PKG_C8_RESIDENCY (0x00000630)\r
2434 @param EAX Lower 32-bits of MSR value.\r
2435 Described by the type MSR_HASWELL_PKG_C8_RESIDENCY_REGISTER.\r
2436 @param EDX Upper 32-bits of MSR value.\r
2437 Described by the type MSR_HASWELL_PKG_C8_RESIDENCY_REGISTER.\r
2438\r
2439 <b>Example usage</b>\r
2440 @code\r
2441 MSR_HASWELL_PKG_C8_RESIDENCY_REGISTER Msr;\r
2442\r
2443 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_PKG_C8_RESIDENCY);\r
2444 AsmWriteMsr64 (MSR_HASWELL_PKG_C8_RESIDENCY, Msr.Uint64);\r
2445 @endcode\r
2446**/\r
2447#define MSR_HASWELL_PKG_C8_RESIDENCY 0x00000630\r
2448\r
2449/**\r
2450 MSR information returned for MSR index #MSR_HASWELL_PKG_C8_RESIDENCY\r
2451**/\r
2452typedef union {\r
2453 ///\r
2454 /// Individual bit fields\r
2455 ///\r
2456 struct {\r
2457 ///\r
2458 /// [Bits 31:0] Package C8 Residency Counter. (R/O) Value since last reset\r
2459 /// that this package is in processor-specific C8 states. Count at the\r
2460 /// same frequency as the TSC.\r
2461 ///\r
2462 UINT32 C8ResidencyCounter:32;\r
2463 ///\r
2464 /// [Bits 59:32] Package C8 Residency Counter. (R/O) Value since last\r
2465 /// reset that this package is in processor-specific C8 states. Count at\r
2466 /// the same frequency as the TSC.\r
2467 ///\r
2468 UINT32 C8ResidencyCounterHi:28;\r
2469 UINT32 Reserved:4;\r
2470 } Bits;\r
2471 ///\r
2472 /// All bit fields as a 64-bit value\r
2473 ///\r
2474 UINT64 Uint64;\r
2475} MSR_HASWELL_PKG_C8_RESIDENCY_REGISTER;\r
2476\r
2477\r
2478/**\r
2479 Package. Note: C-state values are processor specific C-state code names,\r
2480 unrelated to MWAIT extension C-state parameters or ACPI C-States.\r
2481\r
2482 @param ECX MSR_HASWELL_PKG_C9_RESIDENCY (0x00000631)\r
2483 @param EAX Lower 32-bits of MSR value.\r
2484 Described by the type MSR_HASWELL_PKG_C9_RESIDENCY_REGISTER.\r
2485 @param EDX Upper 32-bits of MSR value.\r
2486 Described by the type MSR_HASWELL_PKG_C9_RESIDENCY_REGISTER.\r
2487\r
2488 <b>Example usage</b>\r
2489 @code\r
2490 MSR_HASWELL_PKG_C9_RESIDENCY_REGISTER Msr;\r
2491\r
2492 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_PKG_C9_RESIDENCY);\r
2493 AsmWriteMsr64 (MSR_HASWELL_PKG_C9_RESIDENCY, Msr.Uint64);\r
2494 @endcode\r
2495**/\r
2496#define MSR_HASWELL_PKG_C9_RESIDENCY 0x00000631\r
2497\r
2498/**\r
2499 MSR information returned for MSR index #MSR_HASWELL_PKG_C9_RESIDENCY\r
2500**/\r
2501typedef union {\r
2502 ///\r
2503 /// Individual bit fields\r
2504 ///\r
2505 struct {\r
2506 ///\r
2507 /// [Bits 31:0] Package C9 Residency Counter. (R/O) Value since last reset\r
2508 /// that this package is in processor-specific C9 states. Count at the\r
2509 /// same frequency as the TSC.\r
2510 ///\r
2511 UINT32 C9ResidencyCounter:32;\r
2512 ///\r
2513 /// [Bits 59:32] Package C9 Residency Counter. (R/O) Value since last\r
2514 /// reset that this package is in processor-specific C9 states. Count at\r
2515 /// the same frequency as the TSC.\r
2516 ///\r
2517 UINT32 C9ResidencyCounterHi:28;\r
2518 UINT32 Reserved:4;\r
2519 } Bits;\r
2520 ///\r
2521 /// All bit fields as a 64-bit value\r
2522 ///\r
2523 UINT64 Uint64;\r
2524} MSR_HASWELL_PKG_C9_RESIDENCY_REGISTER;\r
2525\r
2526\r
2527/**\r
2528 Package. Note: C-state values are processor specific C-state code names,\r
2529 unrelated to MWAIT extension C-state parameters or ACPI C-States.\r
2530\r
2531 @param ECX MSR_HASWELL_PKG_C10_RESIDENCY (0x00000632)\r
2532 @param EAX Lower 32-bits of MSR value.\r
2533 Described by the type MSR_HASWELL_PKG_C10_RESIDENCY_REGISTER.\r
2534 @param EDX Upper 32-bits of MSR value.\r
2535 Described by the type MSR_HASWELL_PKG_C10_RESIDENCY_REGISTER.\r
2536\r
2537 <b>Example usage</b>\r
2538 @code\r
2539 MSR_HASWELL_PKG_C10_RESIDENCY_REGISTER Msr;\r
2540\r
2541 Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_PKG_C10_RESIDENCY);\r
2542 AsmWriteMsr64 (MSR_HASWELL_PKG_C10_RESIDENCY, Msr.Uint64);\r
2543 @endcode\r
2544**/\r
2545#define MSR_HASWELL_PKG_C10_RESIDENCY 0x00000632\r
2546\r
2547/**\r
2548 MSR information returned for MSR index #MSR_HASWELL_PKG_C10_RESIDENCY\r
2549**/\r
2550typedef union {\r
2551 ///\r
2552 /// Individual bit fields\r
2553 ///\r
2554 struct {\r
2555 ///\r
2556 /// [Bits 31:0] Package C10 Residency Counter. (R/O) Value since last\r
2557 /// reset that this package is in processor-specific C10 states. Count at\r
2558 /// the same frequency as the TSC.\r
2559 ///\r
2560 UINT32 C10ResidencyCounter:32;\r
2561 ///\r
2562 /// [Bits 59:32] Package C10 Residency Counter. (R/O) Value since last\r
2563 /// reset that this package is in processor-specific C10 states. Count at\r
2564 /// the same frequency as the TSC.\r
2565 ///\r
2566 UINT32 C10ResidencyCounterHi:28;\r
2567 UINT32 Reserved:4;\r
2568 } Bits;\r
2569 ///\r
2570 /// All bit fields as a 64-bit value\r
2571 ///\r
2572 UINT64 Uint64;\r
2573} MSR_HASWELL_PKG_C10_RESIDENCY_REGISTER;\r
2574\r
2575#endif\r
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