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1 | /** @file\r |
2 | MSR Definitions for P6 Family Processors.\r | |
3 | \r | |
4 | Provides defines for Machine Specific Registers(MSR) indexes. Data structures\r | |
5 | are provided for MSRs that contain one or more bit fields. If the MSR value\r | |
6 | returned is a single 32-bit or 64-bit value, then a data structure is not\r | |
7 | provided for that MSR.\r | |
8 | \r | |
ba1a2d11 | 9 | Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>\r |
8e6bff88 MK |
10 | This program and the accompanying materials\r |
11 | are licensed and made available under the terms and conditions of the BSD License\r | |
12 | which accompanies this distribution. The full text of the license may be found at\r | |
13 | http://opensource.org/licenses/bsd-license.php\r | |
14 | \r | |
15 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
16 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
17 | \r | |
18 | @par Specification Reference:\r | |
ba1a2d11 ED |
19 | Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,\r |
20 | May 2018, Volume 4: Model-Specific-Registers (MSR)\r | |
8e6bff88 MK |
21 | \r |
22 | **/\r | |
23 | \r | |
24 | #ifndef __P6_MSR_H__\r | |
25 | #define __P6_MSR_H__\r | |
26 | \r | |
27 | #include <Register/ArchitecturalMsr.h>\r | |
28 | \r | |
f4c982bf JF |
29 | /**\r |
30 | Is P6 Family Processors?\r | |
31 | \r | |
32 | @param DisplayFamily Display Family ID\r | |
33 | @param DisplayModel Display Model ID\r | |
34 | \r | |
35 | @retval TRUE Yes, it is.\r | |
36 | @retval FALSE No, it isn't.\r | |
37 | **/\r | |
38 | #define IS_P6_PROCESSOR(DisplayFamily, DisplayModel) \\r | |
39 | (DisplayFamily == 0x06 && \\r | |
40 | ( \\r | |
41 | DisplayModel == 0x03 || \\r | |
42 | DisplayModel == 0x05 || \\r | |
43 | DisplayModel == 0x07 || \\r | |
44 | DisplayModel == 0x08 || \\r | |
45 | DisplayModel == 0x0A || \\r | |
46 | DisplayModel == 0x0B \\r | |
47 | ) \\r | |
48 | )\r | |
49 | \r | |
8e6bff88 | 50 | /**\r |
ba1a2d11 | 51 | See Section 2.22, "MSRs in Pentium Processors.".\r |
8e6bff88 MK |
52 | \r |
53 | @param ECX MSR_P6_P5_MC_ADDR (0x00000000)\r | |
54 | @param EAX Lower 32-bits of MSR value.\r | |
55 | @param EDX Upper 32-bits of MSR value.\r | |
56 | \r | |
57 | <b>Example usage</b>\r | |
58 | @code\r | |
59 | UINT64 Msr;\r | |
60 | \r | |
61 | Msr = AsmReadMsr64 (MSR_P6_P5_MC_ADDR);\r | |
62 | AsmWriteMsr64 (MSR_P6_P5_MC_ADDR, Msr);\r | |
63 | @endcode\r | |
91e3003c | 64 | @note MSR_P6_P5_MC_ADDR is defined as P5_MC_ADDR in SDM.\r |
8e6bff88 MK |
65 | **/\r |
66 | #define MSR_P6_P5_MC_ADDR 0x00000000\r | |
67 | \r | |
68 | \r | |
69 | /**\r | |
ba1a2d11 | 70 | See Section 2.22, "MSRs in Pentium Processors.".\r |
8e6bff88 MK |
71 | \r |
72 | @param ECX MSR_P6_P5_MC_TYPE (0x00000001)\r | |
73 | @param EAX Lower 32-bits of MSR value.\r | |
74 | @param EDX Upper 32-bits of MSR value.\r | |
75 | \r | |
76 | <b>Example usage</b>\r | |
77 | @code\r | |
78 | UINT64 Msr;\r | |
79 | \r | |
80 | Msr = AsmReadMsr64 (MSR_P6_P5_MC_TYPE);\r | |
81 | AsmWriteMsr64 (MSR_P6_P5_MC_TYPE, Msr);\r | |
82 | @endcode\r | |
91e3003c | 83 | @note MSR_P6_P5_MC_TYPE is defined as P5_MC_TYPE in SDM.\r |
8e6bff88 MK |
84 | **/\r |
85 | #define MSR_P6_P5_MC_TYPE 0x00000001\r | |
86 | \r | |
87 | \r | |
88 | /**\r | |
ba1a2d11 | 89 | See Section 17.17, "Time-Stamp Counter.".\r |
8e6bff88 MK |
90 | \r |
91 | @param ECX MSR_P6_TSC (0x00000010)\r | |
92 | @param EAX Lower 32-bits of MSR value.\r | |
93 | @param EDX Upper 32-bits of MSR value.\r | |
94 | \r | |
95 | <b>Example usage</b>\r | |
96 | @code\r | |
97 | UINT64 Msr;\r | |
98 | \r | |
99 | Msr = AsmReadMsr64 (MSR_P6_TSC);\r | |
100 | AsmWriteMsr64 (MSR_P6_TSC, Msr);\r | |
101 | @endcode\r | |
91e3003c | 102 | @note MSR_P6_TSC is defined as TSC in SDM.\r |
8e6bff88 MK |
103 | **/\r |
104 | #define MSR_P6_TSC 0x00000010\r | |
105 | \r | |
106 | \r | |
107 | /**\r | |
108 | Platform ID (R) The operating system can use this MSR to determine "slot"\r | |
109 | information for the processor and the proper microcode update to load.\r | |
110 | \r | |
111 | @param ECX MSR_P6_IA32_PLATFORM_ID (0x00000017)\r | |
112 | @param EAX Lower 32-bits of MSR value.\r | |
113 | Described by the type MSR_P6_IA32_PLATFORM_ID_REGISTER.\r | |
114 | @param EDX Upper 32-bits of MSR value.\r | |
115 | Described by the type MSR_P6_IA32_PLATFORM_ID_REGISTER.\r | |
116 | \r | |
117 | <b>Example usage</b>\r | |
118 | @code\r | |
119 | MSR_P6_IA32_PLATFORM_ID_REGISTER Msr;\r | |
120 | \r | |
121 | Msr.Uint64 = AsmReadMsr64 (MSR_P6_IA32_PLATFORM_ID);\r | |
122 | @endcode\r | |
91e3003c | 123 | @note MSR_P6_IA32_PLATFORM_ID is defined as IA32_PLATFORM_ID in SDM.\r |
8e6bff88 MK |
124 | **/\r |
125 | #define MSR_P6_IA32_PLATFORM_ID 0x00000017\r | |
126 | \r | |
127 | /**\r | |
128 | MSR information returned for MSR index #MSR_P6_IA32_PLATFORM_ID\r | |
129 | **/\r | |
130 | typedef union {\r | |
131 | ///\r | |
132 | /// Individual bit fields\r | |
133 | ///\r | |
134 | struct {\r | |
135 | UINT32 Reserved1:32;\r | |
136 | UINT32 Reserved2:18;\r | |
137 | ///\r | |
138 | /// [Bits 52:50] Platform Id (R) Contains information concerning the\r | |
139 | /// intended platform for the processor.\r | |
140 | ///\r | |
141 | /// 52 51 50\r | |
142 | /// 0 0 0 Processor Flag 0.\r | |
143 | /// 0 0 1 Processor Flag 1\r | |
144 | /// 0 1 0 Processor Flag 2\r | |
145 | /// 0 1 1 Processor Flag 3\r | |
146 | /// 1 0 0 Processor Flag 4\r | |
147 | /// 1 0 1 Processor Flag 5\r | |
148 | /// 1 1 0 Processor Flag 6\r | |
149 | /// 1 1 1 Processor Flag 7\r | |
150 | ///\r | |
151 | UINT32 PlatformId:3;\r | |
152 | ///\r | |
153 | /// [Bits 56:53] L2 Cache Latency Read.\r | |
154 | ///\r | |
155 | UINT32 L2CacheLatencyRead:4;\r | |
156 | UINT32 Reserved3:3;\r | |
157 | ///\r | |
158 | /// [Bit 60] Clock Frequency Ratio Read.\r | |
159 | ///\r | |
160 | UINT32 ClockFrequencyRatioRead:1;\r | |
161 | UINT32 Reserved4:3;\r | |
162 | } Bits;\r | |
163 | ///\r | |
164 | /// All bit fields as a 64-bit value\r | |
165 | ///\r | |
166 | UINT64 Uint64;\r | |
167 | } MSR_P6_IA32_PLATFORM_ID_REGISTER;\r | |
168 | \r | |
169 | \r | |
170 | /**\r | |
171 | Section 10.4.4, "Local APIC Status and Location.".\r | |
172 | \r | |
173 | @param ECX MSR_P6_APIC_BASE (0x0000001B)\r | |
174 | @param EAX Lower 32-bits of MSR value.\r | |
175 | Described by the type MSR_P6_APIC_BASE_REGISTER.\r | |
176 | @param EDX Upper 32-bits of MSR value.\r | |
177 | Described by the type MSR_P6_APIC_BASE_REGISTER.\r | |
178 | \r | |
179 | <b>Example usage</b>\r | |
180 | @code\r | |
181 | MSR_P6_APIC_BASE_REGISTER Msr;\r | |
182 | \r | |
183 | Msr.Uint64 = AsmReadMsr64 (MSR_P6_APIC_BASE);\r | |
184 | AsmWriteMsr64 (MSR_P6_APIC_BASE, Msr.Uint64);\r | |
185 | @endcode\r | |
91e3003c | 186 | @note MSR_P6_APIC_BASE is defined as APIC_BASE in SDM.\r |
8e6bff88 MK |
187 | **/\r |
188 | #define MSR_P6_APIC_BASE 0x0000001B\r | |
189 | \r | |
190 | /**\r | |
191 | MSR information returned for MSR index #MSR_P6_APIC_BASE\r | |
192 | **/\r | |
193 | typedef union {\r | |
194 | ///\r | |
195 | /// Individual bit fields\r | |
196 | ///\r | |
197 | struct {\r | |
198 | UINT32 Reserved1:8;\r | |
199 | ///\r | |
200 | /// [Bit 8] Boot Strap Processor indicator Bit 1 = BSP.\r | |
201 | ///\r | |
202 | UINT32 BSP:1;\r | |
203 | UINT32 Reserved2:2;\r | |
204 | ///\r | |
205 | /// [Bit 11] APIC Global Enable Bit - Permanent till reset 1 = Enabled 0 =\r | |
206 | /// Disabled.\r | |
207 | ///\r | |
208 | UINT32 EN:1;\r | |
209 | ///\r | |
210 | /// [Bits 31:12] APIC Base Address.\r | |
211 | ///\r | |
212 | UINT32 ApicBase:20;\r | |
213 | UINT32 Reserved3:32;\r | |
214 | } Bits;\r | |
215 | ///\r | |
216 | /// All bit fields as a 32-bit value\r | |
217 | ///\r | |
218 | UINT32 Uint32;\r | |
219 | ///\r | |
220 | /// All bit fields as a 64-bit value\r | |
221 | ///\r | |
222 | UINT64 Uint64;\r | |
223 | } MSR_P6_APIC_BASE_REGISTER;\r | |
224 | \r | |
225 | \r | |
226 | /**\r | |
227 | Processor Hard Power-On Configuration (R/W) Enables and disables processor\r | |
228 | features; (R) indicates current processor configuration.\r | |
229 | \r | |
230 | @param ECX MSR_P6_EBL_CR_POWERON (0x0000002A)\r | |
231 | @param EAX Lower 32-bits of MSR value.\r | |
232 | Described by the type MSR_P6_EBL_CR_POWERON_REGISTER.\r | |
233 | @param EDX Upper 32-bits of MSR value.\r | |
234 | Described by the type MSR_P6_EBL_CR_POWERON_REGISTER.\r | |
235 | \r | |
236 | <b>Example usage</b>\r | |
237 | @code\r | |
238 | MSR_P6_EBL_CR_POWERON_REGISTER Msr;\r | |
239 | \r | |
240 | Msr.Uint64 = AsmReadMsr64 (MSR_P6_EBL_CR_POWERON);\r | |
241 | AsmWriteMsr64 (MSR_P6_EBL_CR_POWERON, Msr.Uint64);\r | |
242 | @endcode\r | |
91e3003c | 243 | @note MSR_P6_EBL_CR_POWERON is defined as EBL_CR_POWERON in SDM.\r |
8e6bff88 MK |
244 | **/\r |
245 | #define MSR_P6_EBL_CR_POWERON 0x0000002A\r | |
246 | \r | |
247 | /**\r | |
248 | MSR information returned for MSR index #MSR_P6_EBL_CR_POWERON\r | |
249 | **/\r | |
250 | typedef union {\r | |
251 | ///\r | |
252 | /// Individual bit fields\r | |
253 | ///\r | |
254 | struct {\r | |
255 | UINT32 Reserved1:1;\r | |
256 | ///\r | |
257 | /// [Bit 1] Data Error Checking Enable (R/W) 1 = Enabled 0 = Disabled.\r | |
258 | ///\r | |
259 | UINT32 DataErrorCheckingEnable:1;\r | |
260 | ///\r | |
261 | /// [Bit 2] Response Error Checking Enable FRCERR Observation Enable (R/W)\r | |
262 | /// 1 = Enabled 0 = Disabled.\r | |
263 | ///\r | |
264 | UINT32 ResponseErrorCheckingEnable:1;\r | |
265 | ///\r | |
266 | /// [Bit 3] AERR# Drive Enable (R/W) 1 = Enabled 0 = Disabled.\r | |
267 | ///\r | |
268 | UINT32 AERR_DriveEnable:1;\r | |
269 | ///\r | |
270 | /// [Bit 4] BERR# Enable for Initiator Bus Requests (R/W) 1 = Enabled 0 =\r | |
271 | /// Disabled.\r | |
272 | ///\r | |
273 | UINT32 BERR_Enable:1;\r | |
274 | UINT32 Reserved2:1;\r | |
275 | ///\r | |
276 | /// [Bit 6] BERR# Driver Enable for Initiator Internal Errors (R/W) 1 =\r | |
277 | /// Enabled 0 = Disabled.\r | |
278 | ///\r | |
279 | UINT32 BERR_DriverEnable:1;\r | |
280 | ///\r | |
281 | /// [Bit 7] BINIT# Driver Enable (R/W) 1 = Enabled 0 = Disabled.\r | |
282 | ///\r | |
283 | UINT32 BINIT_DriverEnable:1;\r | |
284 | ///\r | |
285 | /// [Bit 8] Output Tri-state Enabled (R) 1 = Enabled 0 = Disabled.\r | |
286 | ///\r | |
287 | UINT32 OutputTriStateEnable:1;\r | |
288 | ///\r | |
289 | /// [Bit 9] Execute BIST (R) 1 = Enabled 0 = Disabled.\r | |
290 | ///\r | |
291 | UINT32 ExecuteBIST:1;\r | |
292 | ///\r | |
293 | /// [Bit 10] AERR# Observation Enabled (R) 1 = Enabled 0 = Disabled.\r | |
294 | ///\r | |
295 | UINT32 AERR_ObservationEnabled:1;\r | |
296 | UINT32 Reserved3:1;\r | |
297 | ///\r | |
298 | /// [Bit 12] BINIT# Observation Enabled (R) 1 = Enabled 0 = Disabled.\r | |
299 | ///\r | |
300 | UINT32 BINIT_ObservationEnabled:1;\r | |
301 | ///\r | |
302 | /// [Bit 13] In Order Queue Depth (R) 1 = 1 0 = 8.\r | |
303 | ///\r | |
304 | UINT32 InOrderQueueDepth:1;\r | |
305 | ///\r | |
306 | /// [Bit 14] 1-MByte Power on Reset Vector (R) 1 = 1MByte 0 = 4GBytes.\r | |
307 | ///\r | |
308 | UINT32 ResetVector:1;\r | |
309 | ///\r | |
310 | /// [Bit 15] FRC Mode Enable (R) 1 = Enabled 0 = Disabled.\r | |
311 | ///\r | |
312 | UINT32 FRCModeEnable:1;\r | |
313 | ///\r | |
314 | /// [Bits 17:16] APIC Cluster ID (R).\r | |
315 | ///\r | |
316 | UINT32 APICClusterID:2;\r | |
317 | ///\r | |
318 | /// [Bits 19:18] System Bus Frequency (R) 00 = 66MHz 10 = 100Mhz 01 =\r | |
319 | /// 133MHz 11 = Reserved.\r | |
320 | ///\r | |
321 | UINT32 SystemBusFrequency:2;\r | |
322 | ///\r | |
323 | /// [Bits 21:20] Symmetric Arbitration ID (R).\r | |
324 | ///\r | |
325 | UINT32 SymmetricArbitrationID:2;\r | |
326 | ///\r | |
327 | /// [Bits 25:22] Clock Frequency Ratio (R).\r | |
328 | ///\r | |
329 | UINT32 ClockFrequencyRatio:4;\r | |
330 | ///\r | |
331 | /// [Bit 26] Low Power Mode Enable (R/W).\r | |
332 | ///\r | |
333 | UINT32 LowPowerModeEnable:1;\r | |
334 | ///\r | |
335 | /// [Bit 27] Clock Frequency Ratio.\r | |
336 | ///\r | |
337 | UINT32 ClockFrequencyRatio1:1;\r | |
338 | UINT32 Reserved4:4;\r | |
339 | UINT32 Reserved5:32;\r | |
340 | } Bits;\r | |
341 | ///\r | |
342 | /// All bit fields as a 32-bit value\r | |
343 | ///\r | |
344 | UINT32 Uint32;\r | |
345 | ///\r | |
346 | /// All bit fields as a 64-bit value\r | |
347 | ///\r | |
348 | UINT64 Uint64;\r | |
349 | } MSR_P6_EBL_CR_POWERON_REGISTER;\r | |
350 | \r | |
351 | \r | |
352 | /**\r | |
353 | Test Control Register.\r | |
354 | \r | |
355 | @param ECX MSR_P6_TEST_CTL (0x00000033)\r | |
356 | @param EAX Lower 32-bits of MSR value.\r | |
357 | Described by the type MSR_P6_TEST_CTL_REGISTER.\r | |
358 | @param EDX Upper 32-bits of MSR value.\r | |
359 | Described by the type MSR_P6_TEST_CTL_REGISTER.\r | |
360 | \r | |
361 | <b>Example usage</b>\r | |
362 | @code\r | |
363 | MSR_P6_TEST_CTL_REGISTER Msr;\r | |
364 | \r | |
365 | Msr.Uint64 = AsmReadMsr64 (MSR_P6_TEST_CTL);\r | |
366 | AsmWriteMsr64 (MSR_P6_TEST_CTL, Msr.Uint64);\r | |
367 | @endcode\r | |
91e3003c | 368 | @note MSR_P6_TEST_CTL is defined as TEST_CTL in SDM.\r |
8e6bff88 MK |
369 | **/\r |
370 | #define MSR_P6_TEST_CTL 0x00000033\r | |
371 | \r | |
372 | /**\r | |
373 | MSR information returned for MSR index #MSR_P6_TEST_CTL\r | |
374 | **/\r | |
375 | typedef union {\r | |
376 | ///\r | |
377 | /// Individual bit fields\r | |
378 | ///\r | |
379 | struct {\r | |
380 | UINT32 Reserved1:30;\r | |
381 | ///\r | |
382 | /// [Bit 30] Streaming Buffer Disable.\r | |
383 | ///\r | |
384 | UINT32 StreamingBufferDisable:1;\r | |
385 | ///\r | |
386 | /// [Bit 31] Disable LOCK# Assertion for split locked access.\r | |
387 | ///\r | |
388 | UINT32 Disable_LOCK:1;\r | |
389 | UINT32 Reserved2:32;\r | |
390 | } Bits;\r | |
391 | ///\r | |
392 | /// All bit fields as a 32-bit value\r | |
393 | ///\r | |
394 | UINT32 Uint32;\r | |
395 | ///\r | |
396 | /// All bit fields as a 64-bit value\r | |
397 | ///\r | |
398 | UINT64 Uint64;\r | |
399 | } MSR_P6_TEST_CTL_REGISTER;\r | |
400 | \r | |
401 | \r | |
402 | /**\r | |
403 | BIOS Update Trigger Register.\r | |
404 | \r | |
405 | @param ECX MSR_P6_BIOS_UPDT_TRIG (0x00000079)\r | |
406 | @param EAX Lower 32-bits of MSR value.\r | |
407 | @param EDX Upper 32-bits of MSR value.\r | |
408 | \r | |
409 | <b>Example usage</b>\r | |
410 | @code\r | |
411 | UINT64 Msr;\r | |
412 | \r | |
413 | Msr = AsmReadMsr64 (MSR_P6_BIOS_UPDT_TRIG);\r | |
414 | AsmWriteMsr64 (MSR_P6_BIOS_UPDT_TRIG, Msr);\r | |
415 | @endcode\r | |
91e3003c | 416 | @note MSR_P6_BIOS_UPDT_TRIG is defined as BIOS_UPDT_TRIG in SDM.\r |
8e6bff88 MK |
417 | **/\r |
418 | #define MSR_P6_BIOS_UPDT_TRIG 0x00000079\r | |
419 | \r | |
420 | \r | |
421 | /**\r | |
422 | Chunk n data register D[63:0]: used to write to and read from the L2.\r | |
423 | \r | |
424 | @param ECX MSR_P6_BBL_CR_Dn\r | |
425 | @param EAX Lower 32-bits of MSR value.\r | |
426 | @param EDX Upper 32-bits of MSR value.\r | |
427 | \r | |
428 | <b>Example usage</b>\r | |
429 | @code\r | |
430 | UINT64 Msr;\r | |
431 | \r | |
432 | Msr = AsmReadMsr64 (MSR_P6_BBL_CR_D0);\r | |
433 | AsmWriteMsr64 (MSR_P6_BBL_CR_D0, Msr);\r | |
434 | @endcode\r | |
91e3003c JF |
435 | @note MSR_P6_BBL_CR_D0 is defined as BBL_CR_D0 in SDM.\r |
436 | MSR_P6_BBL_CR_D1 is defined as BBL_CR_D1 in SDM.\r | |
437 | MSR_P6_BBL_CR_D2 is defined as BBL_CR_D2 in SDM.\r | |
8e6bff88 MK |
438 | @{\r |
439 | **/\r | |
440 | #define MSR_P6_BBL_CR_D0 0x00000088\r | |
441 | #define MSR_P6_BBL_CR_D1 0x00000089\r | |
442 | #define MSR_P6_BBL_CR_D2 0x0000008A\r | |
443 | /// @}\r | |
444 | \r | |
445 | \r | |
446 | /**\r | |
447 | BIOS Update Signature Register or Chunk 3 data register D[63:0] Used to\r | |
448 | write to and read from the L2 depending on the usage model.\r | |
449 | \r | |
450 | @param ECX MSR_P6_BIOS_SIGN (0x0000008B)\r | |
451 | @param EAX Lower 32-bits of MSR value.\r | |
452 | @param EDX Upper 32-bits of MSR value.\r | |
453 | \r | |
454 | <b>Example usage</b>\r | |
455 | @code\r | |
456 | UINT64 Msr;\r | |
457 | \r | |
458 | Msr = AsmReadMsr64 (MSR_P6_BIOS_SIGN);\r | |
459 | AsmWriteMsr64 (MSR_P6_BIOS_SIGN, Msr);\r | |
460 | @endcode\r | |
91e3003c | 461 | @note MSR_P6_BIOS_SIGN is defined as BIOS_SIGN in SDM.\r |
8e6bff88 MK |
462 | **/\r |
463 | #define MSR_P6_BIOS_SIGN 0x0000008B\r | |
464 | \r | |
465 | \r | |
466 | /**\r | |
467 | \r | |
468 | \r | |
469 | @param ECX MSR_P6_PERFCTR0 (0x000000C1)\r | |
470 | @param EAX Lower 32-bits of MSR value.\r | |
471 | @param EDX Upper 32-bits of MSR value.\r | |
472 | \r | |
473 | <b>Example usage</b>\r | |
474 | @code\r | |
475 | UINT64 Msr;\r | |
476 | \r | |
477 | Msr = AsmReadMsr64 (MSR_P6_PERFCTR0);\r | |
478 | AsmWriteMsr64 (MSR_P6_PERFCTR0, Msr);\r | |
479 | @endcode\r | |
91e3003c JF |
480 | @note MSR_P6_PERFCTR0 is defined as PERFCTR0 in SDM.\r |
481 | MSR_P6_PERFCTR1 is defined as PERFCTR1 in SDM.\r | |
8e6bff88 MK |
482 | @{\r |
483 | **/\r | |
484 | #define MSR_P6_PERFCTR0 0x000000C1\r | |
485 | #define MSR_P6_PERFCTR1 0x000000C2\r | |
486 | /// @}\r | |
487 | \r | |
488 | \r | |
489 | /**\r | |
490 | \r | |
491 | \r | |
492 | @param ECX MSR_P6_MTRRCAP (0x000000FE)\r | |
493 | @param EAX Lower 32-bits of MSR value.\r | |
494 | @param EDX Upper 32-bits of MSR value.\r | |
495 | \r | |
496 | <b>Example usage</b>\r | |
497 | @code\r | |
498 | UINT64 Msr;\r | |
499 | \r | |
500 | Msr = AsmReadMsr64 (MSR_P6_MTRRCAP);\r | |
501 | AsmWriteMsr64 (MSR_P6_MTRRCAP, Msr);\r | |
502 | @endcode\r | |
91e3003c | 503 | @note MSR_P6_MTRRCAP is defined as MTRRCAP in SDM.\r |
8e6bff88 MK |
504 | **/\r |
505 | #define MSR_P6_MTRRCAP 0x000000FE\r | |
506 | \r | |
507 | \r | |
508 | /**\r | |
509 | Address register: used to send specified address (A31-A3) to L2 during cache\r | |
510 | initialization accesses.\r | |
511 | \r | |
512 | @param ECX MSR_P6_BBL_CR_ADDR (0x00000116)\r | |
513 | @param EAX Lower 32-bits of MSR value.\r | |
514 | Described by the type MSR_P6_BBL_CR_ADDR_REGISTER.\r | |
515 | @param EDX Upper 32-bits of MSR value.\r | |
516 | Described by the type MSR_P6_BBL_CR_ADDR_REGISTER.\r | |
517 | \r | |
518 | <b>Example usage</b>\r | |
519 | @code\r | |
520 | MSR_P6_BBL_CR_ADDR_REGISTER Msr;\r | |
521 | \r | |
522 | Msr.Uint64 = AsmReadMsr64 (MSR_P6_BBL_CR_ADDR);\r | |
523 | AsmWriteMsr64 (MSR_P6_BBL_CR_ADDR, Msr.Uint64);\r | |
524 | @endcode\r | |
91e3003c | 525 | @note MSR_P6_BBL_CR_ADDR is defined as BBL_CR_ADDR in SDM.\r |
8e6bff88 MK |
526 | **/\r |
527 | #define MSR_P6_BBL_CR_ADDR 0x00000116\r | |
528 | \r | |
529 | /**\r | |
530 | MSR information returned for MSR index #MSR_P6_BBL_CR_ADDR\r | |
531 | **/\r | |
532 | typedef union {\r | |
533 | ///\r | |
534 | /// Individual bit fields\r | |
535 | ///\r | |
536 | struct {\r | |
537 | UINT32 Reserved1:3;\r | |
538 | ///\r | |
539 | /// [Bits 31:3] Address bits\r | |
540 | ///\r | |
541 | UINT32 Address:29;\r | |
542 | UINT32 Reserved2:32;\r | |
543 | } Bits;\r | |
544 | ///\r | |
545 | /// All bit fields as a 32-bit value\r | |
546 | ///\r | |
547 | UINT32 Uint32;\r | |
548 | ///\r | |
549 | /// All bit fields as a 64-bit value\r | |
550 | ///\r | |
551 | UINT64 Uint64;\r | |
552 | } MSR_P6_BBL_CR_ADDR_REGISTER;\r | |
553 | \r | |
554 | \r | |
555 | /**\r | |
556 | Data ECC register D[7:0]: used to write ECC and read ECC to/from L2.\r | |
557 | \r | |
558 | @param ECX MSR_P6_BBL_CR_DECC (0x00000118)\r | |
559 | @param EAX Lower 32-bits of MSR value.\r | |
560 | @param EDX Upper 32-bits of MSR value.\r | |
561 | \r | |
562 | <b>Example usage</b>\r | |
563 | @code\r | |
564 | UINT64 Msr;\r | |
565 | \r | |
566 | Msr = AsmReadMsr64 (MSR_P6_BBL_CR_DECC);\r | |
567 | AsmWriteMsr64 (MSR_P6_BBL_CR_DECC, Msr);\r | |
568 | @endcode\r | |
91e3003c | 569 | @note MSR_P6_BBL_CR_DECC is defined as BBL_CR_DECC in SDM.\r |
8e6bff88 MK |
570 | **/\r |
571 | #define MSR_P6_BBL_CR_DECC 0x00000118\r | |
572 | \r | |
573 | \r | |
574 | /**\r | |
575 | Control register: used to program L2 commands to be issued via cache\r | |
576 | configuration accesses mechanism. Also receives L2 lookup response.\r | |
577 | \r | |
578 | @param ECX MSR_P6_BBL_CR_CTL (0x00000119)\r | |
579 | @param EAX Lower 32-bits of MSR value.\r | |
580 | Described by the type MSR_P6_BBL_CR_CTL_REGISTER.\r | |
581 | @param EDX Upper 32-bits of MSR value.\r | |
582 | Described by the type MSR_P6_BBL_CR_CTL_REGISTER.\r | |
583 | \r | |
584 | <b>Example usage</b>\r | |
585 | @code\r | |
586 | MSR_P6_BBL_CR_CTL_REGISTER Msr;\r | |
587 | \r | |
588 | Msr.Uint64 = AsmReadMsr64 (MSR_P6_BBL_CR_CTL);\r | |
589 | AsmWriteMsr64 (MSR_P6_BBL_CR_CTL, Msr.Uint64);\r | |
590 | @endcode\r | |
91e3003c | 591 | @note MSR_P6_BBL_CR_CTL is defined as BBL_CR_CTL in SDM.\r |
8e6bff88 MK |
592 | **/\r |
593 | #define MSR_P6_BBL_CR_CTL 0x00000119\r | |
594 | \r | |
595 | /**\r | |
596 | MSR information returned for MSR index #MSR_P6_BBL_CR_CTL\r | |
597 | **/\r | |
598 | typedef union {\r | |
599 | ///\r | |
600 | /// Individual bit fields\r | |
601 | ///\r | |
602 | struct {\r | |
603 | ///\r | |
604 | /// [Bits 4:0] L2 Command\r | |
605 | /// Data Read w/ LRU update (RLU)\r | |
606 | /// Tag Read w/ Data Read (TRR)\r | |
607 | /// Tag Inquire (TI)\r | |
608 | /// L2 Control Register Read (CR)\r | |
609 | /// L2 Control Register Write (CW)\r | |
610 | /// Tag Write w/ Data Read (TWR)\r | |
611 | /// Tag Write w/ Data Write (TWW)\r | |
612 | /// Tag Write (TW).\r | |
613 | ///\r | |
614 | UINT32 L2Command:5;\r | |
615 | ///\r | |
616 | /// [Bits 6:5] State to L2\r | |
617 | ///\r | |
618 | UINT32 StateToL2:2;\r | |
619 | UINT32 Reserved:1;\r | |
620 | ///\r | |
621 | /// [Bits 9:8] Way to L2.\r | |
622 | ///\r | |
623 | UINT32 WayToL2:2;\r | |
624 | ///\r | |
625 | /// [Bits 11:10] Way 0 - 00, Way 1 - 01, Way 2 - 10, Way 3 - 11.\r | |
626 | ///\r | |
627 | UINT32 Way:2;\r | |
628 | ///\r | |
629 | /// [Bits 13:12] Modified - 11,Exclusive - 10, Shared - 01, Invalid - 00.\r | |
630 | ///\r | |
631 | UINT32 MESI:2;\r | |
632 | ///\r | |
633 | /// [Bits 15:14] State from L2.\r | |
634 | ///\r | |
635 | UINT32 StateFromL2:2;\r | |
636 | UINT32 Reserved2:1;\r | |
637 | ///\r | |
638 | /// [Bit 17] L2 Hit.\r | |
639 | ///\r | |
640 | UINT32 L2Hit:1;\r | |
641 | UINT32 Reserved3:1;\r | |
642 | ///\r | |
643 | /// [Bits 20:19] User supplied ECC.\r | |
644 | ///\r | |
645 | UINT32 UserEcc:2;\r | |
646 | ///\r | |
647 | /// [Bit 21] Processor number Disable = 1 Enable = 0 Reserved.\r | |
648 | ///\r | |
649 | UINT32 ProcessorNumber:1;\r | |
650 | UINT32 Reserved4:10;\r | |
651 | UINT32 Reserved5:32;\r | |
652 | } Bits;\r | |
653 | ///\r | |
654 | /// All bit fields as a 32-bit value\r | |
655 | ///\r | |
656 | UINT32 Uint32;\r | |
657 | ///\r | |
658 | /// All bit fields as a 64-bit value\r | |
659 | ///\r | |
660 | UINT64 Uint64;\r | |
661 | } MSR_P6_BBL_CR_CTL_REGISTER;\r | |
662 | \r | |
663 | \r | |
664 | /**\r | |
665 | Trigger register: used to initiate a cache configuration accesses access,\r | |
666 | Write only with Data = 0.\r | |
667 | \r | |
668 | @param ECX MSR_P6_BBL_CR_TRIG (0x0000011A)\r | |
669 | @param EAX Lower 32-bits of MSR value.\r | |
670 | @param EDX Upper 32-bits of MSR value.\r | |
671 | \r | |
672 | <b>Example usage</b>\r | |
673 | @code\r | |
674 | UINT64 Msr;\r | |
675 | \r | |
676 | Msr = AsmReadMsr64 (MSR_P6_BBL_CR_TRIG);\r | |
677 | AsmWriteMsr64 (MSR_P6_BBL_CR_TRIG, Msr);\r | |
678 | @endcode\r | |
91e3003c | 679 | @note MSR_P6_BBL_CR_TRIG is defined as BBL_CR_TRIG in SDM.\r |
8e6bff88 MK |
680 | **/\r |
681 | #define MSR_P6_BBL_CR_TRIG 0x0000011A\r | |
682 | \r | |
683 | \r | |
684 | /**\r | |
685 | Busy register: indicates when a cache configuration accesses L2 command is\r | |
686 | in progress. D[0] = 1 = BUSY.\r | |
687 | \r | |
688 | @param ECX MSR_P6_BBL_CR_BUSY (0x0000011B)\r | |
689 | @param EAX Lower 32-bits of MSR value.\r | |
690 | @param EDX Upper 32-bits of MSR value.\r | |
691 | \r | |
692 | <b>Example usage</b>\r | |
693 | @code\r | |
694 | UINT64 Msr;\r | |
695 | \r | |
696 | Msr = AsmReadMsr64 (MSR_P6_BBL_CR_BUSY);\r | |
697 | AsmWriteMsr64 (MSR_P6_BBL_CR_BUSY, Msr);\r | |
698 | @endcode\r | |
91e3003c | 699 | @note MSR_P6_BBL_CR_BUSY is defined as BBL_CR_BUSY in SDM.\r |
8e6bff88 MK |
700 | **/\r |
701 | #define MSR_P6_BBL_CR_BUSY 0x0000011B\r | |
702 | \r | |
703 | \r | |
704 | /**\r | |
705 | Control register 3: used to configure the L2 Cache.\r | |
706 | \r | |
707 | @param ECX MSR_P6_BBL_CR_CTL3 (0x0000011E)\r | |
708 | @param EAX Lower 32-bits of MSR value.\r | |
709 | Described by the type MSR_P6_BBL_CR_CTL3_REGISTER.\r | |
710 | @param EDX Upper 32-bits of MSR value.\r | |
711 | Described by the type MSR_P6_BBL_CR_CTL3_REGISTER.\r | |
712 | \r | |
713 | <b>Example usage</b>\r | |
714 | @code\r | |
715 | MSR_P6_BBL_CR_CTL3_REGISTER Msr;\r | |
716 | \r | |
717 | Msr.Uint64 = AsmReadMsr64 (MSR_P6_BBL_CR_CTL3);\r | |
718 | AsmWriteMsr64 (MSR_P6_BBL_CR_CTL3, Msr.Uint64);\r | |
719 | @endcode\r | |
91e3003c | 720 | @note MSR_P6_BBL_CR_CTL3 is defined as BBL_CR_CTL3 in SDM.\r |
8e6bff88 MK |
721 | **/\r |
722 | #define MSR_P6_BBL_CR_CTL3 0x0000011E\r | |
723 | \r | |
724 | /**\r | |
725 | MSR information returned for MSR index #MSR_P6_BBL_CR_CTL3\r | |
726 | **/\r | |
727 | typedef union {\r | |
728 | ///\r | |
729 | /// Individual bit fields\r | |
730 | ///\r | |
731 | struct {\r | |
732 | ///\r | |
733 | /// [Bit 0] L2 Configured (read/write ).\r | |
734 | ///\r | |
735 | UINT32 L2Configured:1;\r | |
736 | ///\r | |
737 | /// [Bits 4:1] L2 Cache Latency (read/write).\r | |
738 | ///\r | |
739 | UINT32 L2CacheLatency:4;\r | |
740 | ///\r | |
741 | /// [Bit 5] ECC Check Enable (read/write).\r | |
742 | ///\r | |
743 | UINT32 ECCCheckEnable:1;\r | |
744 | ///\r | |
745 | /// [Bit 6] Address Parity Check Enable (read/write).\r | |
746 | ///\r | |
747 | UINT32 AddressParityCheckEnable:1;\r | |
748 | ///\r | |
749 | /// [Bit 7] CRTN Parity Check Enable (read/write).\r | |
750 | ///\r | |
751 | UINT32 CRTNParityCheckEnable:1;\r | |
752 | ///\r | |
753 | /// [Bit 8] L2 Enabled (read/write).\r | |
754 | ///\r | |
755 | UINT32 L2Enabled:1;\r | |
756 | ///\r | |
757 | /// [Bits 10:9] L2 Associativity (read only) Direct Mapped 2 Way 4 Way\r | |
758 | /// Reserved.\r | |
759 | ///\r | |
760 | UINT32 L2Associativity:2;\r | |
761 | ///\r | |
762 | /// [Bits 12:11] Number of L2 banks (read only).\r | |
763 | ///\r | |
764 | UINT32 L2Banks:2;\r | |
765 | ///\r | |
766 | /// [Bits 17:13] Cache size per bank (read/write) 256KBytes 512KBytes\r | |
767 | /// 1MByte 2MByte 4MBytes.\r | |
768 | ///\r | |
769 | UINT32 CacheSizePerBank:5;\r | |
770 | ///\r | |
771 | /// [Bit 18] Cache State error checking enable (read/write).\r | |
772 | ///\r | |
773 | UINT32 CacheStateErrorEnable:1;\r | |
774 | UINT32 Reserved1:1;\r | |
775 | ///\r | |
776 | /// [Bits 22:20] L2 Physical Address Range support 64GBytes 32GBytes\r | |
777 | /// 16GBytes 8GBytes 4GBytes 2GBytes 1GBytes 512MBytes.\r | |
778 | ///\r | |
779 | UINT32 L2AddressRange:3;\r | |
780 | ///\r | |
781 | /// [Bit 23] L2 Hardware Disable (read only).\r | |
782 | ///\r | |
783 | UINT32 L2HardwareDisable:1;\r | |
784 | UINT32 Reserved2:1;\r | |
785 | ///\r | |
786 | /// [Bit 25] Cache bus fraction (read only).\r | |
787 | ///\r | |
788 | UINT32 CacheBusFraction:1;\r | |
789 | UINT32 Reserved3:6;\r | |
790 | UINT32 Reserved4:32;\r | |
791 | } Bits;\r | |
792 | ///\r | |
793 | /// All bit fields as a 32-bit value\r | |
794 | ///\r | |
795 | UINT32 Uint32;\r | |
796 | ///\r | |
797 | /// All bit fields as a 64-bit value\r | |
798 | ///\r | |
799 | UINT64 Uint64;\r | |
800 | } MSR_P6_BBL_CR_CTL3_REGISTER;\r | |
801 | \r | |
802 | \r | |
803 | /**\r | |
804 | CS register target for CPL 0 code.\r | |
805 | \r | |
806 | @param ECX MSR_P6_SYSENTER_CS_MSR (0x00000174)\r | |
807 | @param EAX Lower 32-bits of MSR value.\r | |
808 | @param EDX Upper 32-bits of MSR value.\r | |
809 | \r | |
810 | <b>Example usage</b>\r | |
811 | @code\r | |
812 | UINT64 Msr;\r | |
813 | \r | |
814 | Msr = AsmReadMsr64 (MSR_P6_SYSENTER_CS_MSR);\r | |
815 | AsmWriteMsr64 (MSR_P6_SYSENTER_CS_MSR, Msr);\r | |
816 | @endcode\r | |
91e3003c | 817 | @note MSR_P6_SYSENTER_CS_MSR is defined as SYSENTER_CS_MSR in SDM.\r |
8e6bff88 MK |
818 | **/\r |
819 | #define MSR_P6_SYSENTER_CS_MSR 0x00000174\r | |
820 | \r | |
821 | \r | |
822 | /**\r | |
823 | Stack pointer for CPL 0 stack.\r | |
824 | \r | |
825 | @param ECX MSR_P6_SYSENTER_ESP_MSR (0x00000175)\r | |
826 | @param EAX Lower 32-bits of MSR value.\r | |
827 | @param EDX Upper 32-bits of MSR value.\r | |
828 | \r | |
829 | <b>Example usage</b>\r | |
830 | @code\r | |
831 | UINT64 Msr;\r | |
832 | \r | |
833 | Msr = AsmReadMsr64 (MSR_P6_SYSENTER_ESP_MSR);\r | |
834 | AsmWriteMsr64 (MSR_P6_SYSENTER_ESP_MSR, Msr);\r | |
835 | @endcode\r | |
91e3003c | 836 | @note MSR_P6_SYSENTER_ESP_MSR is defined as SYSENTER_ESP_MSR in SDM.\r |
8e6bff88 MK |
837 | **/\r |
838 | #define MSR_P6_SYSENTER_ESP_MSR 0x00000175\r | |
839 | \r | |
840 | \r | |
841 | /**\r | |
842 | CPL 0 code entry point.\r | |
843 | \r | |
844 | @param ECX MSR_P6_SYSENTER_EIP_MSR (0x00000176)\r | |
845 | @param EAX Lower 32-bits of MSR value.\r | |
846 | @param EDX Upper 32-bits of MSR value.\r | |
847 | \r | |
848 | <b>Example usage</b>\r | |
849 | @code\r | |
850 | UINT64 Msr;\r | |
851 | \r | |
852 | Msr = AsmReadMsr64 (MSR_P6_SYSENTER_EIP_MSR);\r | |
853 | AsmWriteMsr64 (MSR_P6_SYSENTER_EIP_MSR, Msr);\r | |
854 | @endcode\r | |
91e3003c | 855 | @note MSR_P6_SYSENTER_EIP_MSR is defined as SYSENTER_EIP_MSR in SDM.\r |
8e6bff88 MK |
856 | **/\r |
857 | #define MSR_P6_SYSENTER_EIP_MSR 0x00000176\r | |
858 | \r | |
859 | \r | |
860 | /**\r | |
861 | \r | |
862 | \r | |
863 | @param ECX MSR_P6_MCG_CAP (0x00000179)\r | |
864 | @param EAX Lower 32-bits of MSR value.\r | |
865 | @param EDX Upper 32-bits of MSR value.\r | |
866 | \r | |
867 | <b>Example usage</b>\r | |
868 | @code\r | |
869 | UINT64 Msr;\r | |
870 | \r | |
871 | Msr = AsmReadMsr64 (MSR_P6_MCG_CAP);\r | |
872 | AsmWriteMsr64 (MSR_P6_MCG_CAP, Msr);\r | |
873 | @endcode\r | |
91e3003c | 874 | @note MSR_P6_MCG_CAP is defined as MCG_CAP in SDM.\r |
8e6bff88 MK |
875 | **/\r |
876 | #define MSR_P6_MCG_CAP 0x00000179\r | |
877 | \r | |
878 | \r | |
879 | /**\r | |
880 | \r | |
881 | \r | |
882 | @param ECX MSR_P6_MCG_STATUS (0x0000017A)\r | |
883 | @param EAX Lower 32-bits of MSR value.\r | |
884 | @param EDX Upper 32-bits of MSR value.\r | |
885 | \r | |
886 | <b>Example usage</b>\r | |
887 | @code\r | |
888 | UINT64 Msr;\r | |
889 | \r | |
890 | Msr = AsmReadMsr64 (MSR_P6_MCG_STATUS);\r | |
891 | AsmWriteMsr64 (MSR_P6_MCG_STATUS, Msr);\r | |
892 | @endcode\r | |
91e3003c | 893 | @note MSR_P6_MCG_STATUS is defined as MCG_STATUS in SDM.\r |
8e6bff88 MK |
894 | **/\r |
895 | #define MSR_P6_MCG_STATUS 0x0000017A\r | |
896 | \r | |
897 | \r | |
898 | /**\r | |
899 | \r | |
900 | \r | |
901 | @param ECX MSR_P6_MCG_CTL (0x0000017B)\r | |
902 | @param EAX Lower 32-bits of MSR value.\r | |
903 | @param EDX Upper 32-bits of MSR value.\r | |
904 | \r | |
905 | <b>Example usage</b>\r | |
906 | @code\r | |
907 | UINT64 Msr;\r | |
908 | \r | |
909 | Msr = AsmReadMsr64 (MSR_P6_MCG_CTL);\r | |
910 | AsmWriteMsr64 (MSR_P6_MCG_CTL, Msr);\r | |
911 | @endcode\r | |
91e3003c | 912 | @note MSR_P6_MCG_CTL is defined as MCG_CTL in SDM.\r |
8e6bff88 MK |
913 | **/\r |
914 | #define MSR_P6_MCG_CTL 0x0000017B\r | |
915 | \r | |
916 | \r | |
917 | /**\r | |
918 | \r | |
919 | \r | |
920 | @param ECX MSR_P6_PERFEVTSELn\r | |
921 | @param EAX Lower 32-bits of MSR value.\r | |
922 | Described by the type MSR_P6_PERFEVTSEL_REGISTER.\r | |
923 | @param EDX Upper 32-bits of MSR value.\r | |
924 | Described by the type MSR_P6_PERFEVTSEL_REGISTER.\r | |
925 | \r | |
926 | <b>Example usage</b>\r | |
927 | @code\r | |
928 | MSR_P6_PERFEVTSEL_REGISTER Msr;\r | |
929 | \r | |
930 | Msr.Uint64 = AsmReadMsr64 (MSR_P6_PERFEVTSEL0);\r | |
931 | AsmWriteMsr64 (MSR_P6_PERFEVTSEL0, Msr.Uint64);\r | |
932 | @endcode\r | |
91e3003c JF |
933 | @note MSR_P6_PERFEVTSEL0 is defined as PERFEVTSEL0 in SDM.\r |
934 | MSR_P6_PERFEVTSEL1 is defined as PERFEVTSEL1 in SDM.\r | |
8e6bff88 MK |
935 | @{\r |
936 | **/\r | |
937 | #define MSR_P6_PERFEVTSEL0 0x00000186\r | |
938 | #define MSR_P6_PERFEVTSEL1 0x00000187\r | |
939 | /// @}\r | |
940 | \r | |
941 | /**\r | |
942 | MSR information returned for MSR indexes #MSR_P6_PERFEVTSEL0 and\r | |
943 | #MSR_P6_PERFEVTSEL1.\r | |
944 | **/\r | |
945 | typedef union {\r | |
946 | ///\r | |
947 | /// Individual bit fields\r | |
948 | ///\r | |
949 | struct {\r | |
950 | ///\r | |
951 | /// [Bits 7:0] Event Select Refer to Performance Counter section for a\r | |
952 | /// list of event encodings.\r | |
953 | ///\r | |
954 | UINT32 EventSelect:8;\r | |
955 | ///\r | |
956 | /// [Bits 15:8] UMASK (Unit Mask) Unit mask register set to 0 to enable\r | |
957 | /// all count options.\r | |
958 | ///\r | |
959 | UINT32 UMASK:8;\r | |
960 | ///\r | |
961 | /// [Bit 16] USER Controls the counting of events at Privilege levels of\r | |
962 | /// 1, 2, and 3.\r | |
963 | ///\r | |
964 | UINT32 USR:1;\r | |
965 | ///\r | |
966 | /// [Bit 17] OS Controls the counting of events at Privilege level of 0.\r | |
967 | ///\r | |
968 | UINT32 OS:1;\r | |
969 | ///\r | |
970 | /// [Bit 18] E Occurrence/Duration Mode Select 1 = Occurrence 0 = Duration.\r | |
971 | ///\r | |
972 | UINT32 E:1;\r | |
973 | ///\r | |
974 | /// [Bit 19] PC Enabled the signaling of performance counter overflow via\r | |
975 | /// BP0 pin.\r | |
976 | ///\r | |
977 | UINT32 PC:1;\r | |
978 | ///\r | |
979 | /// [Bit 20] INT Enables the signaling of counter overflow via input to\r | |
980 | /// APIC 1 = Enable 0 = Disable.\r | |
981 | ///\r | |
982 | UINT32 INT:1;\r | |
983 | UINT32 Reserved1:1;\r | |
984 | ///\r | |
985 | /// [Bit 22] ENABLE Enables the counting of performance events in both\r | |
986 | /// counters 1 = Enable 0 = Disable.\r | |
987 | ///\r | |
988 | UINT32 EN:1;\r | |
989 | ///\r | |
990 | /// [Bit 23] INV Inverts the result of the CMASK condition 1 = Inverted 0\r | |
991 | /// = Non-Inverted.\r | |
992 | ///\r | |
993 | UINT32 INV:1;\r | |
994 | ///\r | |
995 | /// [Bits 31:24] CMASK (Counter Mask).\r | |
996 | ///\r | |
997 | UINT32 CMASK:8;\r | |
998 | UINT32 Reserved2:32;\r | |
999 | } Bits;\r | |
1000 | ///\r | |
1001 | /// All bit fields as a 32-bit value\r | |
1002 | ///\r | |
1003 | UINT32 Uint32;\r | |
1004 | ///\r | |
1005 | /// All bit fields as a 64-bit value\r | |
1006 | ///\r | |
1007 | UINT64 Uint64;\r | |
1008 | } MSR_P6_PERFEVTSEL_REGISTER;\r | |
1009 | \r | |
1010 | \r | |
1011 | /**\r | |
1012 | \r | |
1013 | \r | |
1014 | @param ECX MSR_P6_DEBUGCTLMSR (0x000001D9)\r | |
1015 | @param EAX Lower 32-bits of MSR value.\r | |
1016 | Described by the type MSR_P6_DEBUGCTLMSR_REGISTER.\r | |
1017 | @param EDX Upper 32-bits of MSR value.\r | |
1018 | Described by the type MSR_P6_DEBUGCTLMSR_REGISTER.\r | |
1019 | \r | |
1020 | <b>Example usage</b>\r | |
1021 | @code\r | |
1022 | MSR_P6_DEBUGCTLMSR_REGISTER Msr;\r | |
1023 | \r | |
1024 | Msr.Uint64 = AsmReadMsr64 (MSR_P6_DEBUGCTLMSR);\r | |
1025 | AsmWriteMsr64 (MSR_P6_DEBUGCTLMSR, Msr.Uint64);\r | |
1026 | @endcode\r | |
91e3003c | 1027 | @note MSR_P6_DEBUGCTLMSR is defined as DEBUGCTLMSR in SDM.\r |
8e6bff88 MK |
1028 | **/\r |
1029 | #define MSR_P6_DEBUGCTLMSR 0x000001D9\r | |
1030 | \r | |
1031 | /**\r | |
1032 | MSR information returned for MSR index #MSR_P6_DEBUGCTLMSR\r | |
1033 | **/\r | |
1034 | typedef union {\r | |
1035 | ///\r | |
1036 | /// Individual bit fields\r | |
1037 | ///\r | |
1038 | struct {\r | |
1039 | ///\r | |
1040 | /// [Bit 0] Enable/Disable Last Branch Records.\r | |
1041 | ///\r | |
1042 | UINT32 LBR:1;\r | |
1043 | ///\r | |
1044 | /// [Bit 1] Branch Trap Flag.\r | |
1045 | ///\r | |
1046 | UINT32 BTF:1;\r | |
1047 | ///\r | |
1048 | /// [Bit 2] Performance Monitoring/Break Point Pins.\r | |
1049 | ///\r | |
1050 | UINT32 PB0:1;\r | |
1051 | ///\r | |
1052 | /// [Bit 3] Performance Monitoring/Break Point Pins.\r | |
1053 | ///\r | |
1054 | UINT32 PB1:1;\r | |
1055 | ///\r | |
1056 | /// [Bit 4] Performance Monitoring/Break Point Pins.\r | |
1057 | ///\r | |
1058 | UINT32 PB2:1;\r | |
1059 | ///\r | |
1060 | /// [Bit 5] Performance Monitoring/Break Point Pins.\r | |
1061 | ///\r | |
1062 | UINT32 PB3:1;\r | |
1063 | ///\r | |
1064 | /// [Bit 6] Enable/Disable Execution Trace Messages.\r | |
1065 | ///\r | |
1066 | UINT32 TR:1;\r | |
1067 | UINT32 Reserved1:25;\r | |
1068 | UINT32 Reserved2:32;\r | |
1069 | } Bits;\r | |
1070 | ///\r | |
1071 | /// All bit fields as a 32-bit value\r | |
1072 | ///\r | |
1073 | UINT32 Uint32;\r | |
1074 | ///\r | |
1075 | /// All bit fields as a 64-bit value\r | |
1076 | ///\r | |
1077 | UINT64 Uint64;\r | |
1078 | } MSR_P6_DEBUGCTLMSR_REGISTER;\r | |
1079 | \r | |
1080 | \r | |
1081 | /**\r | |
1082 | \r | |
1083 | \r | |
1084 | @param ECX MSR_P6_LASTBRANCHFROMIP (0x000001DB)\r | |
1085 | @param EAX Lower 32-bits of MSR value.\r | |
1086 | @param EDX Upper 32-bits of MSR value.\r | |
1087 | \r | |
1088 | <b>Example usage</b>\r | |
1089 | @code\r | |
1090 | UINT64 Msr;\r | |
1091 | \r | |
1092 | Msr = AsmReadMsr64 (MSR_P6_LASTBRANCHFROMIP);\r | |
1093 | AsmWriteMsr64 (MSR_P6_LASTBRANCHFROMIP, Msr);\r | |
1094 | @endcode\r | |
91e3003c | 1095 | @note MSR_P6_LASTBRANCHFROMIP is defined as LASTBRANCHFROMIP in SDM.\r |
8e6bff88 MK |
1096 | **/\r |
1097 | #define MSR_P6_LASTBRANCHFROMIP 0x000001DB\r | |
1098 | \r | |
1099 | \r | |
1100 | /**\r | |
1101 | \r | |
1102 | \r | |
1103 | @param ECX MSR_P6_LASTBRANCHTOIP (0x000001DC)\r | |
1104 | @param EAX Lower 32-bits of MSR value.\r | |
1105 | @param EDX Upper 32-bits of MSR value.\r | |
1106 | \r | |
1107 | <b>Example usage</b>\r | |
1108 | @code\r | |
1109 | UINT64 Msr;\r | |
1110 | \r | |
1111 | Msr = AsmReadMsr64 (MSR_P6_LASTBRANCHTOIP);\r | |
1112 | AsmWriteMsr64 (MSR_P6_LASTBRANCHTOIP, Msr);\r | |
1113 | @endcode\r | |
91e3003c | 1114 | @note MSR_P6_LASTBRANCHTOIP is defined as LASTBRANCHTOIP in SDM.\r |
8e6bff88 MK |
1115 | **/\r |
1116 | #define MSR_P6_LASTBRANCHTOIP 0x000001DC\r | |
1117 | \r | |
1118 | \r | |
1119 | /**\r | |
1120 | \r | |
1121 | \r | |
1122 | @param ECX MSR_P6_LASTINTFROMIP (0x000001DD)\r | |
1123 | @param EAX Lower 32-bits of MSR value.\r | |
1124 | @param EDX Upper 32-bits of MSR value.\r | |
1125 | \r | |
1126 | <b>Example usage</b>\r | |
1127 | @code\r | |
1128 | UINT64 Msr;\r | |
1129 | \r | |
1130 | Msr = AsmReadMsr64 (MSR_P6_LASTINTFROMIP);\r | |
1131 | AsmWriteMsr64 (MSR_P6_LASTINTFROMIP, Msr);\r | |
1132 | @endcode\r | |
91e3003c | 1133 | @note MSR_P6_LASTINTFROMIP is defined as LASTINTFROMIP in SDM.\r |
8e6bff88 MK |
1134 | **/\r |
1135 | #define MSR_P6_LASTINTFROMIP 0x000001DD\r | |
1136 | \r | |
1137 | \r | |
1138 | /**\r | |
1139 | \r | |
1140 | \r | |
1141 | @param ECX MSR_P6_LASTINTTOIP (0x000001DE)\r | |
1142 | @param EAX Lower 32-bits of MSR value.\r | |
1143 | @param EDX Upper 32-bits of MSR value.\r | |
1144 | \r | |
1145 | <b>Example usage</b>\r | |
1146 | @code\r | |
1147 | UINT64 Msr;\r | |
1148 | \r | |
1149 | Msr = AsmReadMsr64 (MSR_P6_LASTINTTOIP);\r | |
1150 | AsmWriteMsr64 (MSR_P6_LASTINTTOIP, Msr);\r | |
1151 | @endcode\r | |
91e3003c | 1152 | @note MSR_P6_LASTINTTOIP is defined as LASTINTTOIP in SDM.\r |
8e6bff88 MK |
1153 | **/\r |
1154 | #define MSR_P6_LASTINTTOIP 0x000001DE\r | |
1155 | \r | |
1156 | \r | |
1157 | /**\r | |
1158 | \r | |
1159 | \r | |
1160 | @param ECX MSR_P6_ROB_CR_BKUPTMPDR6 (0x000001E0)\r | |
1161 | @param EAX Lower 32-bits of MSR value.\r | |
1162 | Described by the type MSR_P6_ROB_CR_BKUPTMPDR6_REGISTER.\r | |
1163 | @param EDX Upper 32-bits of MSR value.\r | |
1164 | Described by the type MSR_P6_ROB_CR_BKUPTMPDR6_REGISTER.\r | |
1165 | \r | |
1166 | <b>Example usage</b>\r | |
1167 | @code\r | |
1168 | MSR_P6_ROB_CR_BKUPTMPDR6_REGISTER Msr;\r | |
1169 | \r | |
1170 | Msr.Uint64 = AsmReadMsr64 (MSR_P6_ROB_CR_BKUPTMPDR6);\r | |
1171 | AsmWriteMsr64 (MSR_P6_ROB_CR_BKUPTMPDR6, Msr.Uint64);\r | |
1172 | @endcode\r | |
91e3003c | 1173 | @note MSR_P6_ROB_CR_BKUPTMPDR6 is defined as ROB_CR_BKUPTMPDR6 in SDM.\r |
8e6bff88 MK |
1174 | **/\r |
1175 | #define MSR_P6_ROB_CR_BKUPTMPDR6 0x000001E0\r | |
1176 | \r | |
1177 | /**\r | |
1178 | MSR information returned for MSR index #MSR_P6_ROB_CR_BKUPTMPDR6\r | |
1179 | **/\r | |
1180 | typedef union {\r | |
1181 | ///\r | |
1182 | /// Individual bit fields\r | |
1183 | ///\r | |
1184 | struct {\r | |
1185 | UINT32 Reserved1:2;\r | |
1186 | ///\r | |
1187 | /// [Bit 2] Fast Strings Enable bit. Default is enabled.\r | |
1188 | ///\r | |
1189 | UINT32 FastStrings:1;\r | |
1190 | UINT32 Reserved2:29;\r | |
1191 | UINT32 Reserved3:32;\r | |
1192 | } Bits;\r | |
1193 | ///\r | |
1194 | /// All bit fields as a 32-bit value\r | |
1195 | ///\r | |
1196 | UINT32 Uint32;\r | |
1197 | ///\r | |
1198 | /// All bit fields as a 64-bit value\r | |
1199 | ///\r | |
1200 | UINT64 Uint64;\r | |
1201 | } MSR_P6_ROB_CR_BKUPTMPDR6_REGISTER;\r | |
1202 | \r | |
1203 | \r | |
1204 | /**\r | |
1205 | \r | |
1206 | \r | |
1207 | @param ECX MSR_P6_MTRRPHYSBASEn\r | |
1208 | @param EAX Lower 32-bits of MSR value.\r | |
1209 | @param EDX Upper 32-bits of MSR value.\r | |
1210 | \r | |
1211 | <b>Example usage</b>\r | |
1212 | @code\r | |
1213 | UINT64 Msr;\r | |
1214 | \r | |
1215 | Msr = AsmReadMsr64 (MSR_P6_MTRRPHYSBASE0);\r | |
1216 | AsmWriteMsr64 (MSR_P6_MTRRPHYSBASE0, Msr);\r | |
1217 | @endcode\r | |
91e3003c JF |
1218 | @note MSR_P6_MTRRPHYSBASE0 is defined as MTRRPHYSBASE0 in SDM.\r |
1219 | MSR_P6_MTRRPHYSBASE1 is defined as MTRRPHYSBASE1 in SDM.\r | |
1220 | MSR_P6_MTRRPHYSBASE2 is defined as MTRRPHYSBASE2 in SDM.\r | |
1221 | MSR_P6_MTRRPHYSBASE3 is defined as MTRRPHYSBASE3 in SDM.\r | |
1222 | MSR_P6_MTRRPHYSBASE4 is defined as MTRRPHYSBASE4 in SDM.\r | |
1223 | MSR_P6_MTRRPHYSBASE5 is defined as MTRRPHYSBASE5 in SDM.\r | |
1224 | MSR_P6_MTRRPHYSBASE6 is defined as MTRRPHYSBASE6 in SDM.\r | |
1225 | MSR_P6_MTRRPHYSBASE7 is defined as MTRRPHYSBASE7 in SDM.\r | |
8e6bff88 MK |
1226 | @{\r |
1227 | **/\r | |
1228 | #define MSR_P6_MTRRPHYSBASE0 0x00000200\r | |
1229 | #define MSR_P6_MTRRPHYSBASE1 0x00000202\r | |
1230 | #define MSR_P6_MTRRPHYSBASE2 0x00000204\r | |
1231 | #define MSR_P6_MTRRPHYSBASE3 0x00000206\r | |
1232 | #define MSR_P6_MTRRPHYSBASE4 0x00000208\r | |
1233 | #define MSR_P6_MTRRPHYSBASE5 0x0000020A\r | |
1234 | #define MSR_P6_MTRRPHYSBASE6 0x0000020C\r | |
1235 | #define MSR_P6_MTRRPHYSBASE7 0x0000020E\r | |
1236 | /// @}\r | |
1237 | \r | |
1238 | \r | |
1239 | /**\r | |
1240 | \r | |
1241 | \r | |
1242 | @param ECX MSR_P6_MTRRPHYSMASKn\r | |
1243 | @param EAX Lower 32-bits of MSR value.\r | |
1244 | @param EDX Upper 32-bits of MSR value.\r | |
1245 | \r | |
1246 | <b>Example usage</b>\r | |
1247 | @code\r | |
1248 | UINT64 Msr;\r | |
1249 | \r | |
1250 | Msr = AsmReadMsr64 (MSR_P6_MTRRPHYSMASK0);\r | |
1251 | AsmWriteMsr64 (MSR_P6_MTRRPHYSMASK0, Msr);\r | |
1252 | @endcode\r | |
91e3003c JF |
1253 | @note MSR_P6_MTRRPHYSMASK0 is defined as MTRRPHYSMASK0 in SDM.\r |
1254 | MSR_P6_MTRRPHYSMASK1 is defined as MTRRPHYSMASK1 in SDM.\r | |
1255 | MSR_P6_MTRRPHYSMASK2 is defined as MTRRPHYSMASK2 in SDM.\r | |
1256 | MSR_P6_MTRRPHYSMASK3 is defined as MTRRPHYSMASK3 in SDM.\r | |
1257 | MSR_P6_MTRRPHYSMASK4 is defined as MTRRPHYSMASK4 in SDM.\r | |
1258 | MSR_P6_MTRRPHYSMASK5 is defined as MTRRPHYSMASK5 in SDM.\r | |
1259 | MSR_P6_MTRRPHYSMASK6 is defined as MTRRPHYSMASK6 in SDM.\r | |
1260 | MSR_P6_MTRRPHYSMASK7 is defined as MTRRPHYSMASK7 in SDM.\r | |
8e6bff88 MK |
1261 | @{\r |
1262 | **/\r | |
1263 | #define MSR_P6_MTRRPHYSMASK0 0x00000201\r | |
1264 | #define MSR_P6_MTRRPHYSMASK1 0x00000203\r | |
1265 | #define MSR_P6_MTRRPHYSMASK2 0x00000205\r | |
1266 | #define MSR_P6_MTRRPHYSMASK3 0x00000207\r | |
1267 | #define MSR_P6_MTRRPHYSMASK4 0x00000209\r | |
1268 | #define MSR_P6_MTRRPHYSMASK5 0x0000020B\r | |
1269 | #define MSR_P6_MTRRPHYSMASK6 0x0000020D\r | |
1270 | #define MSR_P6_MTRRPHYSMASK7 0x0000020F\r | |
1271 | /// @}\r | |
1272 | \r | |
1273 | \r | |
1274 | /**\r | |
1275 | \r | |
1276 | \r | |
1277 | @param ECX MSR_P6_MTRRFIX64K_00000 (0x00000250)\r | |
1278 | @param EAX Lower 32-bits of MSR value.\r | |
1279 | @param EDX Upper 32-bits of MSR value.\r | |
1280 | \r | |
1281 | <b>Example usage</b>\r | |
1282 | @code\r | |
1283 | UINT64 Msr;\r | |
1284 | \r | |
1285 | Msr = AsmReadMsr64 (MSR_P6_MTRRFIX64K_00000);\r | |
1286 | AsmWriteMsr64 (MSR_P6_MTRRFIX64K_00000, Msr);\r | |
1287 | @endcode\r | |
91e3003c | 1288 | @note MSR_P6_MTRRFIX64K_00000 is defined as MTRRFIX64K_00000 in SDM.\r |
8e6bff88 MK |
1289 | **/\r |
1290 | #define MSR_P6_MTRRFIX64K_00000 0x00000250\r | |
1291 | \r | |
1292 | \r | |
1293 | /**\r | |
1294 | \r | |
1295 | \r | |
1296 | @param ECX MSR_P6_MTRRFIX16K_80000 (0x00000258)\r | |
1297 | @param EAX Lower 32-bits of MSR value.\r | |
1298 | @param EDX Upper 32-bits of MSR value.\r | |
1299 | \r | |
1300 | <b>Example usage</b>\r | |
1301 | @code\r | |
1302 | UINT64 Msr;\r | |
1303 | \r | |
1304 | Msr = AsmReadMsr64 (MSR_P6_MTRRFIX16K_80000);\r | |
1305 | AsmWriteMsr64 (MSR_P6_MTRRFIX16K_80000, Msr);\r | |
1306 | @endcode\r | |
91e3003c | 1307 | @note MSR_P6_MTRRFIX16K_80000 is defined as MTRRFIX16K_80000 in SDM.\r |
8e6bff88 MK |
1308 | **/\r |
1309 | #define MSR_P6_MTRRFIX16K_80000 0x00000258\r | |
1310 | \r | |
1311 | \r | |
1312 | /**\r | |
1313 | \r | |
1314 | \r | |
1315 | @param ECX MSR_P6_MTRRFIX16K_A0000 (0x00000259)\r | |
1316 | @param EAX Lower 32-bits of MSR value.\r | |
1317 | @param EDX Upper 32-bits of MSR value.\r | |
1318 | \r | |
1319 | <b>Example usage</b>\r | |
1320 | @code\r | |
1321 | UINT64 Msr;\r | |
1322 | \r | |
1323 | Msr = AsmReadMsr64 (MSR_P6_MTRRFIX16K_A0000);\r | |
1324 | AsmWriteMsr64 (MSR_P6_MTRRFIX16K_A0000, Msr);\r | |
1325 | @endcode\r | |
91e3003c | 1326 | @note MSR_P6_MTRRFIX16K_A0000 is defined as MTRRFIX16K_A0000 in SDM.\r |
8e6bff88 MK |
1327 | **/\r |
1328 | #define MSR_P6_MTRRFIX16K_A0000 0x00000259\r | |
1329 | \r | |
1330 | \r | |
1331 | /**\r | |
1332 | \r | |
1333 | \r | |
1334 | @param ECX MSR_P6_MTRRFIX4K_C0000 (0x00000268)\r | |
1335 | @param EAX Lower 32-bits of MSR value.\r | |
1336 | @param EDX Upper 32-bits of MSR value.\r | |
1337 | \r | |
1338 | <b>Example usage</b>\r | |
1339 | @code\r | |
1340 | UINT64 Msr;\r | |
1341 | \r | |
1342 | Msr = AsmReadMsr64 (MSR_P6_MTRRFIX4K_C0000);\r | |
1343 | AsmWriteMsr64 (MSR_P6_MTRRFIX4K_C0000, Msr);\r | |
1344 | @endcode\r | |
91e3003c | 1345 | @note MSR_P6_MTRRFIX4K_C0000 is defined as MTRRFIX4K_C0000 in SDM.\r |
8e6bff88 MK |
1346 | **/\r |
1347 | #define MSR_P6_MTRRFIX4K_C0000 0x00000268\r | |
1348 | \r | |
1349 | \r | |
1350 | /**\r | |
1351 | \r | |
1352 | \r | |
1353 | @param ECX MSR_P6_MTRRFIX4K_C8000 (0x00000269)\r | |
1354 | @param EAX Lower 32-bits of MSR value.\r | |
1355 | @param EDX Upper 32-bits of MSR value.\r | |
1356 | \r | |
1357 | <b>Example usage</b>\r | |
1358 | @code\r | |
1359 | UINT64 Msr;\r | |
1360 | \r | |
1361 | Msr = AsmReadMsr64 (MSR_P6_MTRRFIX4K_C8000);\r | |
1362 | AsmWriteMsr64 (MSR_P6_MTRRFIX4K_C8000, Msr);\r | |
1363 | @endcode\r | |
91e3003c | 1364 | @note MSR_P6_MTRRFIX4K_C8000 is defined as MTRRFIX4K_C8000 in SDM.\r |
8e6bff88 MK |
1365 | **/\r |
1366 | #define MSR_P6_MTRRFIX4K_C8000 0x00000269\r | |
1367 | \r | |
1368 | \r | |
1369 | /**\r | |
1370 | \r | |
1371 | \r | |
1372 | @param ECX MSR_P6_MTRRFIX4K_D0000 (0x0000026A)\r | |
1373 | @param EAX Lower 32-bits of MSR value.\r | |
1374 | @param EDX Upper 32-bits of MSR value.\r | |
1375 | \r | |
1376 | <b>Example usage</b>\r | |
1377 | @code\r | |
1378 | UINT64 Msr;\r | |
1379 | \r | |
1380 | Msr = AsmReadMsr64 (MSR_P6_MTRRFIX4K_D0000);\r | |
1381 | AsmWriteMsr64 (MSR_P6_MTRRFIX4K_D0000, Msr);\r | |
1382 | @endcode\r | |
91e3003c | 1383 | @note MSR_P6_MTRRFIX4K_D0000 is defined as MTRRFIX4K_D0000 in SDM.\r |
8e6bff88 MK |
1384 | **/\r |
1385 | #define MSR_P6_MTRRFIX4K_D0000 0x0000026A\r | |
1386 | \r | |
1387 | \r | |
1388 | /**\r | |
1389 | \r | |
1390 | \r | |
1391 | @param ECX MSR_P6_MTRRFIX4K_D8000 (0x0000026B)\r | |
1392 | @param EAX Lower 32-bits of MSR value.\r | |
1393 | @param EDX Upper 32-bits of MSR value.\r | |
1394 | \r | |
1395 | <b>Example usage</b>\r | |
1396 | @code\r | |
1397 | UINT64 Msr;\r | |
1398 | \r | |
1399 | Msr = AsmReadMsr64 (MSR_P6_MTRRFIX4K_D8000);\r | |
1400 | AsmWriteMsr64 (MSR_P6_MTRRFIX4K_D8000, Msr);\r | |
1401 | @endcode\r | |
91e3003c | 1402 | @note MSR_P6_MTRRFIX4K_D8000 is defined as MTRRFIX4K_D8000 in SDM.\r |
8e6bff88 MK |
1403 | **/\r |
1404 | #define MSR_P6_MTRRFIX4K_D8000 0x0000026B\r | |
1405 | \r | |
1406 | \r | |
1407 | /**\r | |
1408 | \r | |
1409 | \r | |
1410 | @param ECX MSR_P6_MTRRFIX4K_E0000 (0x0000026C)\r | |
1411 | @param EAX Lower 32-bits of MSR value.\r | |
1412 | @param EDX Upper 32-bits of MSR value.\r | |
1413 | \r | |
1414 | <b>Example usage</b>\r | |
1415 | @code\r | |
1416 | UINT64 Msr;\r | |
1417 | \r | |
1418 | Msr = AsmReadMsr64 (MSR_P6_MTRRFIX4K_E0000);\r | |
1419 | AsmWriteMsr64 (MSR_P6_MTRRFIX4K_E0000, Msr);\r | |
1420 | @endcode\r | |
91e3003c | 1421 | @note MSR_P6_MTRRFIX4K_E0000 is defined as MTRRFIX4K_E0000 in SDM.\r |
8e6bff88 MK |
1422 | **/\r |
1423 | #define MSR_P6_MTRRFIX4K_E0000 0x0000026C\r | |
1424 | \r | |
1425 | \r | |
1426 | /**\r | |
1427 | \r | |
1428 | \r | |
1429 | @param ECX MSR_P6_MTRRFIX4K_E8000 (0x0000026D)\r | |
1430 | @param EAX Lower 32-bits of MSR value.\r | |
1431 | @param EDX Upper 32-bits of MSR value.\r | |
1432 | \r | |
1433 | <b>Example usage</b>\r | |
1434 | @code\r | |
1435 | UINT64 Msr;\r | |
1436 | \r | |
1437 | Msr = AsmReadMsr64 (MSR_P6_MTRRFIX4K_E8000);\r | |
1438 | AsmWriteMsr64 (MSR_P6_MTRRFIX4K_E8000, Msr);\r | |
1439 | @endcode\r | |
91e3003c | 1440 | @note MSR_P6_MTRRFIX4K_E8000 is defined as MTRRFIX4K_E8000 in SDM.\r |
8e6bff88 MK |
1441 | **/\r |
1442 | #define MSR_P6_MTRRFIX4K_E8000 0x0000026D\r | |
1443 | \r | |
1444 | \r | |
1445 | /**\r | |
1446 | \r | |
1447 | \r | |
1448 | @param ECX MSR_P6_MTRRFIX4K_F0000 (0x0000026E)\r | |
1449 | @param EAX Lower 32-bits of MSR value.\r | |
1450 | @param EDX Upper 32-bits of MSR value.\r | |
1451 | \r | |
1452 | <b>Example usage</b>\r | |
1453 | @code\r | |
1454 | UINT64 Msr;\r | |
1455 | \r | |
1456 | Msr = AsmReadMsr64 (MSR_P6_MTRRFIX4K_F0000);\r | |
1457 | AsmWriteMsr64 (MSR_P6_MTRRFIX4K_F0000, Msr);\r | |
1458 | @endcode\r | |
91e3003c | 1459 | @note MSR_P6_MTRRFIX4K_F0000 is defined as MTRRFIX4K_F0000 in SDM.\r |
8e6bff88 MK |
1460 | **/\r |
1461 | #define MSR_P6_MTRRFIX4K_F0000 0x0000026E\r | |
1462 | \r | |
1463 | \r | |
1464 | /**\r | |
1465 | \r | |
1466 | \r | |
1467 | @param ECX MSR_P6_MTRRFIX4K_F8000 (0x0000026F)\r | |
1468 | @param EAX Lower 32-bits of MSR value.\r | |
1469 | @param EDX Upper 32-bits of MSR value.\r | |
1470 | \r | |
1471 | <b>Example usage</b>\r | |
1472 | @code\r | |
1473 | UINT64 Msr;\r | |
1474 | \r | |
1475 | Msr = AsmReadMsr64 (MSR_P6_MTRRFIX4K_F8000);\r | |
1476 | AsmWriteMsr64 (MSR_P6_MTRRFIX4K_F8000, Msr);\r | |
1477 | @endcode\r | |
91e3003c | 1478 | @note MSR_P6_MTRRFIX4K_F8000 is defined as MTRRFIX4K_F8000 in SDM.\r |
8e6bff88 MK |
1479 | **/\r |
1480 | #define MSR_P6_MTRRFIX4K_F8000 0x0000026F\r | |
1481 | \r | |
1482 | \r | |
1483 | /**\r | |
1484 | \r | |
1485 | \r | |
1486 | @param ECX MSR_P6_MTRRDEFTYPE (0x000002FF)\r | |
1487 | @param EAX Lower 32-bits of MSR value.\r | |
1488 | Described by the type MSR_P6_MTRRDEFTYPE_REGISTER.\r | |
1489 | @param EDX Upper 32-bits of MSR value.\r | |
1490 | Described by the type MSR_P6_MTRRDEFTYPE_REGISTER.\r | |
1491 | \r | |
1492 | <b>Example usage</b>\r | |
1493 | @code\r | |
1494 | MSR_P6_MTRRDEFTYPE_REGISTER Msr;\r | |
1495 | \r | |
1496 | Msr.Uint64 = AsmReadMsr64 (MSR_P6_MTRRDEFTYPE);\r | |
1497 | AsmWriteMsr64 (MSR_P6_MTRRDEFTYPE, Msr.Uint64);\r | |
1498 | @endcode\r | |
91e3003c | 1499 | @note MSR_P6_MTRRDEFTYPE is defined as MTRRDEFTYPE in SDM.\r |
8e6bff88 MK |
1500 | **/\r |
1501 | #define MSR_P6_MTRRDEFTYPE 0x000002FF\r | |
1502 | \r | |
1503 | /**\r | |
1504 | MSR information returned for MSR index #MSR_P6_MTRRDEFTYPE\r | |
1505 | **/\r | |
1506 | typedef union {\r | |
1507 | ///\r | |
1508 | /// Individual bit fields\r | |
1509 | ///\r | |
1510 | struct {\r | |
1511 | ///\r | |
1512 | /// [Bits 2:0] Default memory type.\r | |
1513 | ///\r | |
1514 | UINT32 Type:3;\r | |
1515 | UINT32 Reserved1:7;\r | |
1516 | ///\r | |
1517 | /// [Bit 10] Fixed MTRR enable.\r | |
1518 | ///\r | |
1519 | UINT32 FE:1;\r | |
1520 | ///\r | |
1521 | /// [Bit 11] MTRR Enable.\r | |
1522 | ///\r | |
1523 | UINT32 E:1;\r | |
1524 | UINT32 Reserved2:20;\r | |
1525 | UINT32 Reserved3:32;\r | |
1526 | } Bits;\r | |
1527 | ///\r | |
1528 | /// All bit fields as a 32-bit value\r | |
1529 | ///\r | |
1530 | UINT32 Uint32;\r | |
1531 | ///\r | |
1532 | /// All bit fields as a 64-bit value\r | |
1533 | ///\r | |
1534 | UINT64 Uint64;\r | |
1535 | } MSR_P6_MTRRDEFTYPE_REGISTER;\r | |
1536 | \r | |
1537 | \r | |
1538 | /**\r | |
1539 | \r | |
1540 | \r | |
1541 | @param ECX MSR_P6_MC0_CTL (0x00000400)\r | |
1542 | @param EAX Lower 32-bits of MSR value.\r | |
1543 | @param EDX Upper 32-bits of MSR value.\r | |
1544 | \r | |
1545 | <b>Example usage</b>\r | |
1546 | @code\r | |
1547 | UINT64 Msr;\r | |
1548 | \r | |
1549 | Msr = AsmReadMsr64 (MSR_P6_MC0_CTL);\r | |
1550 | AsmWriteMsr64 (MSR_P6_MC0_CTL, Msr);\r | |
1551 | @endcode\r | |
91e3003c JF |
1552 | @note MSR_P6_MC0_CTL is defined as MC0_CTL in SDM.\r |
1553 | MSR_P6_MC1_CTL is defined as MC1_CTL in SDM.\r | |
1554 | MSR_P6_MC2_CTL is defined as MC2_CTL in SDM.\r | |
1555 | MSR_P6_MC3_CTL is defined as MC3_CTL in SDM.\r | |
1556 | MSR_P6_MC4_CTL is defined as MC4_CTL in SDM.\r | |
8e6bff88 MK |
1557 | @{\r |
1558 | **/\r | |
1559 | #define MSR_P6_MC0_CTL 0x00000400\r | |
1560 | #define MSR_P6_MC1_CTL 0x00000404\r | |
1561 | #define MSR_P6_MC2_CTL 0x00000408\r | |
1562 | #define MSR_P6_MC3_CTL 0x00000410\r | |
1563 | #define MSR_P6_MC4_CTL 0x0000040C\r | |
1564 | /// @}\r | |
1565 | \r | |
1566 | \r | |
1567 | /**\r | |
1568 | \r | |
1569 | Bit definitions for MSR_P6_MC4_STATUS are the same as MSR_P6_MC0_STATUS,\r | |
1570 | except bits 0, 4, 57, and 61 are hardcoded to 1.\r | |
1571 | \r | |
1572 | @param ECX MSR_P6_MCn_STATUS\r | |
1573 | @param EAX Lower 32-bits of MSR value.\r | |
1574 | Described by the type MSR_P6_MC_STATUS_REGISTER.\r | |
1575 | @param EDX Upper 32-bits of MSR value.\r | |
1576 | Described by the type MSR_P6_MC_STATUS_REGISTER.\r | |
1577 | \r | |
1578 | <b>Example usage</b>\r | |
1579 | @code\r | |
1580 | MSR_P6_MC_STATUS_REGISTER Msr;\r | |
1581 | \r | |
1582 | Msr.Uint64 = AsmReadMsr64 (MSR_P6_MC0_STATUS);\r | |
1583 | AsmWriteMsr64 (MSR_P6_MC0_STATUS, Msr.Uint64);\r | |
1584 | @endcode\r | |
91e3003c JF |
1585 | @note MSR_P6_MC0_STATUS is defined as MC0_STATUS in SDM.\r |
1586 | MSR_P6_MC1_STATUS is defined as MC1_STATUS in SDM.\r | |
1587 | MSR_P6_MC2_STATUS is defined as MC2_STATUS in SDM.\r | |
1588 | MSR_P6_MC3_STATUS is defined as MC3_STATUS in SDM.\r | |
1589 | MSR_P6_MC4_STATUS is defined as MC4_STATUS in SDM.\r | |
8e6bff88 MK |
1590 | @{\r |
1591 | **/\r | |
1592 | #define MSR_P6_MC0_STATUS 0x00000401\r | |
1593 | #define MSR_P6_MC1_STATUS 0x00000405\r | |
1594 | #define MSR_P6_MC2_STATUS 0x00000409\r | |
1595 | #define MSR_P6_MC3_STATUS 0x00000411\r | |
1596 | #define MSR_P6_MC4_STATUS 0x0000040D\r | |
1597 | /// @}\r | |
1598 | \r | |
1599 | /**\r | |
1600 | MSR information returned for MSR index #MSR_P6_MC0_STATUS to\r | |
1601 | #MSR_P6_MC4_STATUS\r | |
1602 | **/\r | |
1603 | typedef union {\r | |
1604 | ///\r | |
1605 | /// Individual bit fields\r | |
1606 | ///\r | |
1607 | struct {\r | |
1608 | ///\r | |
1609 | /// [Bits 15:0] MC_STATUS_MCACOD.\r | |
1610 | ///\r | |
1611 | UINT32 MC_STATUS_MCACOD:16;\r | |
1612 | ///\r | |
1613 | /// [Bits 31:16] MC_STATUS_MSCOD.\r | |
1614 | ///\r | |
1615 | UINT32 MC_STATUS_MSCOD:16;\r | |
1616 | UINT32 Reserved:25;\r | |
1617 | ///\r | |
1618 | /// [Bit 57] MC_STATUS_DAM.\r | |
1619 | ///\r | |
1620 | UINT32 MC_STATUS_DAM:1;\r | |
1621 | ///\r | |
1622 | /// [Bit 58] MC_STATUS_ADDRV.\r | |
1623 | ///\r | |
1624 | UINT32 MC_STATUS_ADDRV:1;\r | |
1625 | ///\r | |
1626 | /// [Bit 59] MC_STATUS_MISCV.\r | |
1627 | ///\r | |
1628 | UINT32 MC_STATUS_MISCV:1;\r | |
1629 | ///\r | |
1630 | /// [Bit 60] MC_STATUS_EN. (Note: For MC0_STATUS only, this bit is\r | |
1631 | /// hardcoded to 1.).\r | |
1632 | ///\r | |
1633 | UINT32 MC_STATUS_EN:1;\r | |
1634 | ///\r | |
1635 | /// [Bit 61] MC_STATUS_UC.\r | |
1636 | ///\r | |
1637 | UINT32 MC_STATUS_UC:1;\r | |
1638 | ///\r | |
1639 | /// [Bit 62] MC_STATUS_O.\r | |
1640 | ///\r | |
1641 | UINT32 MC_STATUS_O:1;\r | |
1642 | ///\r | |
1643 | /// [Bit 63] MC_STATUS_V.\r | |
1644 | ///\r | |
1645 | UINT32 MC_STATUS_V:1;\r | |
1646 | } Bits;\r | |
1647 | ///\r | |
1648 | /// All bit fields as a 64-bit value\r | |
1649 | ///\r | |
1650 | UINT64 Uint64;\r | |
1651 | } MSR_P6_MC_STATUS_REGISTER;\r | |
1652 | \r | |
1653 | \r | |
1654 | /**\r | |
1655 | \r | |
1656 | MSR_P6_MC4_ADDR is defined in MCA architecture but not implemented in P6 Family processors.\r | |
1657 | \r | |
1658 | @param ECX MSR_P6_MC0_ADDR (0x00000402)\r | |
1659 | @param EAX Lower 32-bits of MSR value.\r | |
1660 | @param EDX Upper 32-bits of MSR value.\r | |
1661 | \r | |
1662 | <b>Example usage</b>\r | |
1663 | @code\r | |
1664 | UINT64 Msr;\r | |
1665 | \r | |
1666 | Msr = AsmReadMsr64 (MSR_P6_MC0_ADDR);\r | |
1667 | AsmWriteMsr64 (MSR_P6_MC0_ADDR, Msr);\r | |
1668 | @endcode\r | |
91e3003c JF |
1669 | @note MSR_P6_MC0_ADDR is defined as MC0_ADDR in SDM.\r |
1670 | MSR_P6_MC1_ADDR is defined as MC1_ADDR in SDM.\r | |
1671 | MSR_P6_MC2_ADDR is defined as MC2_ADDR in SDM.\r | |
1672 | MSR_P6_MC3_ADDR is defined as MC3_ADDR in SDM.\r | |
1673 | MSR_P6_MC4_ADDR is defined as MC4_ADDR in SDM.\r | |
8e6bff88 MK |
1674 | @{\r |
1675 | **/\r | |
1676 | #define MSR_P6_MC0_ADDR 0x00000402\r | |
1677 | #define MSR_P6_MC1_ADDR 0x00000406\r | |
1678 | #define MSR_P6_MC2_ADDR 0x0000040A\r | |
1679 | #define MSR_P6_MC3_ADDR 0x00000412\r | |
1680 | #define MSR_P6_MC4_ADDR 0x0000040E\r | |
1681 | /// @}\r | |
1682 | \r | |
1683 | \r | |
1684 | /**\r | |
1685 | Defined in MCA architecture but not implemented in the P6 family processors.\r | |
1686 | \r | |
1687 | @param ECX MSR_P6_MC0_MISC (0x00000403)\r | |
1688 | @param EAX Lower 32-bits of MSR value.\r | |
1689 | @param EDX Upper 32-bits of MSR value.\r | |
1690 | \r | |
1691 | <b>Example usage</b>\r | |
1692 | @code\r | |
1693 | UINT64 Msr;\r | |
1694 | \r | |
1695 | Msr = AsmReadMsr64 (MSR_P6_MC0_MISC);\r | |
1696 | AsmWriteMsr64 (MSR_P6_MC0_MISC, Msr);\r | |
1697 | @endcode\r | |
91e3003c JF |
1698 | @note MSR_P6_MC0_MISC is defined as MC0_MISC in SDM.\r |
1699 | MSR_P6_MC1_MISC is defined as MC1_MISC in SDM.\r | |
1700 | MSR_P6_MC2_MISC is defined as MC2_MISC in SDM.\r | |
1701 | MSR_P6_MC3_MISC is defined as MC3_MISC in SDM.\r | |
1702 | MSR_P6_MC4_MISC is defined as MC4_MISC in SDM.\r | |
8e6bff88 MK |
1703 | @{\r |
1704 | **/\r | |
1705 | #define MSR_P6_MC0_MISC 0x00000403\r | |
1706 | #define MSR_P6_MC1_MISC 0x00000407\r | |
1707 | #define MSR_P6_MC2_MISC 0x0000040B\r | |
1708 | #define MSR_P6_MC3_MISC 0x00000413\r | |
1709 | #define MSR_P6_MC4_MISC 0x0000040F\r | |
1710 | /// @}\r | |
1711 | \r | |
1712 | #endif\r |