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UefiCpuPkg/IvyBridgeMsr.h: add MSR reference from SDM in comment
[mirror_edk2.git] / UefiCpuPkg / Include / Register / Msr / Pentium4Msr.h
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f4d9afde
MK		 1/** @file\r
2 MSR Definitions for Pentium(R) 4 Processors.\r
3\r
4 Provides defines for Machine Specific Registers(MSR) indexes. Data structures\r
5 are provided for MSRs that contain one or more bit fields. If the MSR value\r
6 returned is a single 32-bit or 64-bit value, then a data structure is not\r
7 provided for that MSR.\r
8\r
9 Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>\r
10 This program and the accompanying materials\r
11 are licensed and made available under the terms and conditions of the BSD License\r
12 which accompanies this distribution. The full text of the license may be found at\r
13 http://opensource.org/licenses/bsd-license.php\r
14\r
15 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
16 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
17\r
18 @par Specification Reference:\r
19 Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,\r
20 December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-16.\r
21\r
22**/\r
23\r
24#ifndef __PENTIUM_4_MSR_H__\r
25#define __PENTIUM_4_MSR_H__\r
26\r
27#include <Register/ArchitecturalMsr.h>\r
28\r
29/**\r
30 3, 4, 6. Shared. See Section 8.10.5, "Monitor/Mwait Address Range\r
31 Determination.".\r
32\r
33 @param ECX MSR_PENTIUM_4_IA32_MONITOR_FILTER_LINE_SIZE (0x00000006)\r
34 @param EAX Lower 32-bits of MSR value.\r
35 @param EDX Upper 32-bits of MSR value.\r
36\r
37 <b>Example usage</b>\r
38 @code\r
39 UINT64 Msr;\r
40\r
41 Msr = AsmReadMsr64 (MSR_PENTIUM_4_IA32_MONITOR_FILTER_LINE_SIZE);\r
42 AsmWriteMsr64 (MSR_PENTIUM_4_IA32_MONITOR_FILTER_LINE_SIZE, Msr);\r
43 @endcode\r
44**/\r
45#define MSR_PENTIUM_4_IA32_MONITOR_FILTER_LINE_SIZE 0x00000006\r
46\r
47\r
48/**\r
49 0, 1, 2, 3, 4, 6. Shared. Processor Hard Power-On Configuration (R/W)\r
50 Enables and disables processor features; (R) indicates current processor\r
51 configuration.\r
52\r
53 @param ECX MSR_PENTIUM_4_EBC_HARD_POWERON (0x0000002A)\r
54 @param EAX Lower 32-bits of MSR value.\r
55 Described by the type MSR_PENTIUM_4_EBC_HARD_POWERON_REGISTER.\r
56 @param EDX Upper 32-bits of MSR value.\r
57 Described by the type MSR_PENTIUM_4_EBC_HARD_POWERON_REGISTER.\r
58\r
59 <b>Example usage</b>\r
60 @code\r
61 MSR_PENTIUM_4_EBC_HARD_POWERON_REGISTER Msr;\r
62\r
63 Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_4_EBC_HARD_POWERON);\r
64 AsmWriteMsr64 (MSR_PENTIUM_4_EBC_HARD_POWERON, Msr.Uint64);\r
65 @endcode\r
66**/\r
67#define MSR_PENTIUM_4_EBC_HARD_POWERON 0x0000002A\r
68\r
69/**\r
70 MSR information returned for MSR index #MSR_PENTIUM_4_EBC_HARD_POWERON\r
71**/\r
72typedef union {\r
73 ///\r
74 /// Individual bit fields\r
75 ///\r
76 struct {\r
77 ///\r
78 /// [Bit 0] Output Tri-state Enabled (R) Indicates whether tri-state\r
79 /// output is enabled (1) or disabled (0) as set by the strapping of SMI#.\r
80 /// The value in this bit is written on the deassertion of RESET#; the bit\r
81 /// is set to 1 when the address bus signal is asserted.\r
82 ///\r
83 UINT32 OutputTriStateEnabled:1;\r
84 ///\r
85 /// [Bit 1] Execute BIST (R) Indicates whether the execution of the BIST\r
86 /// is enabled (1) or disabled (0) as set by the strapping of INIT#. The\r
87 /// value in this bit is written on the deassertion of RESET#; the bit is\r
88 /// set to 1 when the address bus signal is asserted.\r
89 ///\r
90 UINT32 ExecuteBIST:1;\r
91 ///\r
92 /// [Bit 2] In Order Queue Depth (R) Indicates whether the in order queue\r
93 /// depth for the system bus is 1 (1) or up to 12 (0) as set by the\r
94 /// strapping of A7#. The value in this bit is written on the deassertion\r
95 /// of RESET#; the bit is set to 1 when the address bus signal is asserted.\r
96 ///\r
97 UINT32 InOrderQueueDepth:1;\r
98 ///\r
99 /// [Bit 3] MCERR# Observation Disabled (R) Indicates whether MCERR#\r
100 /// observation is enabled (0) or disabled (1) as determined by the\r
101 /// strapping of A9#. The value in this bit is written on the deassertion\r
102 /// of RESET#; the bit is set to 1 when the address bus signal is asserted.\r
103 ///\r
104 UINT32 MCERR_ObservationDisabled:1;\r
105 ///\r
106 /// [Bit 4] BINIT# Observation Enabled (R) Indicates whether BINIT#\r
107 /// observation is enabled (0) or disabled (1) as determined by the\r
108 /// strapping of A10#. The value in this bit is written on the deassertion\r
109 /// of RESET#; the bit is set to 1 when the address bus signal is asserted.\r
110 ///\r
111 UINT32 BINIT_ObservationEnabled:1;\r
112 ///\r
113 /// [Bits 6:5] APIC Cluster ID (R) Contains the logical APIC cluster ID\r
114 /// value as set by the strapping of A12# and A11#. The logical cluster ID\r
115 /// value is written into the field on the deassertion of RESET#; the\r
116 /// field is set to 1 when the address bus signal is asserted.\r
117 ///\r
118 UINT32 APICClusterID:2;\r
119 ///\r
120 /// [Bit 7] Bus Park Disable (R) Indicates whether bus park is enabled\r
121 /// (0) or disabled (1) as set by the strapping of A15#. The value in this\r
122 /// bit is written on the deassertion of RESET#; the bit is set to 1 when\r
123 /// the address bus signal is asserted.\r
124 ///\r
125 UINT32 BusParkDisable:1;\r
126 UINT32 Reserved1:4;\r
127 ///\r
128 /// [Bits 13:12] Agent ID (R) Contains the logical agent ID value as set\r
129 /// by the strapping of BR[3:0]. The logical ID value is written into the\r
130 /// field on the deassertion of RESET#; the field is set to 1 when the\r
131 /// address bus signal is asserted.\r
132 ///\r
133 UINT32 AgentID:2;\r
134 UINT32 Reserved2:18;\r
135 UINT32 Reserved3:32;\r
136 } Bits;\r
137 ///\r
138 /// All bit fields as a 32-bit value\r
139 ///\r
140 UINT32 Uint32;\r
141 ///\r
142 /// All bit fields as a 64-bit value\r
143 ///\r
144 UINT64 Uint64;\r
145} MSR_PENTIUM_4_EBC_HARD_POWERON_REGISTER;\r
146\r
147\r
148/**\r
149 0, 1, 2, 3, 4, 6. Shared. Processor Soft Power-On Configuration (R/W)\r
150 Enables and disables processor features.\r
151\r
152 @param ECX MSR_PENTIUM_4_EBC_SOFT_POWERON (0x0000002B)\r
153 @param EAX Lower 32-bits of MSR value.\r
154 Described by the type MSR_PENTIUM_4_EBC_SOFT_POWERON_REGISTER.\r
155 @param EDX Upper 32-bits of MSR value.\r
156 Described by the type MSR_PENTIUM_4_EBC_SOFT_POWERON_REGISTER.\r
157\r
158 <b>Example usage</b>\r
159 @code\r
160 MSR_PENTIUM_4_EBC_SOFT_POWERON_REGISTER Msr;\r
161\r
162 Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_4_EBC_SOFT_POWERON);\r
163 AsmWriteMsr64 (MSR_PENTIUM_4_EBC_SOFT_POWERON, Msr.Uint64);\r
164 @endcode\r
165**/\r
166#define MSR_PENTIUM_4_EBC_SOFT_POWERON 0x0000002B\r
167\r
168/**\r
169 MSR information returned for MSR index #MSR_PENTIUM_4_EBC_SOFT_POWERON\r
170**/\r
171typedef union {\r
172 ///\r
173 /// Individual bit fields\r
174 ///\r
175 struct {\r
176 ///\r
177 /// [Bit 0] RCNT/SCNT On Request Encoding Enable (R/W) Controls the\r
178 /// driving of RCNT/SCNT on the request encoding. Set to enable (1); clear\r
179 /// to disabled (0, default).\r
180 ///\r
181 UINT32 RCNT_SCNT:1;\r
182 ///\r
183 /// [Bit 1] Data Error Checking Disable (R/W) Set to disable system data\r
184 /// bus parity checking; clear to enable parity checking.\r
185 ///\r
186 UINT32 DataErrorCheckingDisable:1;\r
187 ///\r
188 /// [Bit 2] Response Error Checking Disable (R/W) Set to disable\r
189 /// (default); clear to enable.\r
190 ///\r
191 UINT32 ResponseErrorCheckingDisable:1;\r
192 ///\r
193 /// [Bit 3] Address/Request Error Checking Disable (R/W) Set to disable\r
194 /// (default); clear to enable.\r
195 ///\r
196 UINT32 AddressRequestErrorCheckingDisable:1;\r
197 ///\r
198 /// [Bit 4] Initiator MCERR# Disable (R/W) Set to disable MCERR# driving\r
199 /// for initiator bus requests (default); clear to enable.\r
200 ///\r
201 UINT32 InitiatorMCERR_Disable:1;\r
202 ///\r
203 /// [Bit 5] Internal MCERR# Disable (R/W) Set to disable MCERR# driving\r
204 /// for initiator internal errors (default); clear to enable.\r
205 ///\r
206 UINT32 InternalMCERR_Disable:1;\r
207 ///\r
208 /// [Bit 6] BINIT# Driver Disable (R/W) Set to disable BINIT# driver\r
209 /// (default); clear to enable driver.\r
210 ///\r
211 UINT32 BINIT_DriverDisable:1;\r
212 UINT32 Reserved1:25;\r
213 UINT32 Reserved2:32;\r
214 } Bits;\r
215 ///\r
216 /// All bit fields as a 32-bit value\r
217 ///\r
218 UINT32 Uint32;\r
219 ///\r
220 /// All bit fields as a 64-bit value\r
221 ///\r
222 UINT64 Uint64;\r
223} MSR_PENTIUM_4_EBC_SOFT_POWERON_REGISTER;\r
224\r
225\r
226/**\r
227 2,3, 4, 6. Shared. Processor Frequency Configuration The bit field layout of\r
228 this MSR varies according to the MODEL value in the CPUID version\r
229 information. The following bit field layout applies to Pentium 4 and Xeon\r
230 Processors with MODEL encoding equal or greater than 2. (R) The field\r
231 Indicates the current processor frequency configuration.\r
232\r
233 @param ECX MSR_PENTIUM_4_EBC_FREQUENCY_ID (0x0000002C)\r
234 @param EAX Lower 32-bits of MSR value.\r
235 Described by the type MSR_PENTIUM_4_EBC_FREQUENCY_ID_REGISTER.\r
236 @param EDX Upper 32-bits of MSR value.\r
237 Described by the type MSR_PENTIUM_4_EBC_FREQUENCY_ID_REGISTER.\r
238\r
239 <b>Example usage</b>\r
240 @code\r
241 MSR_PENTIUM_4_EBC_FREQUENCY_ID_REGISTER Msr;\r
242\r
243 Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_4_EBC_FREQUENCY_ID);\r
244 @endcode\r
245**/\r
246#define MSR_PENTIUM_4_EBC_FREQUENCY_ID 0x0000002C\r
247\r
248/**\r
249 MSR information returned for MSR index #MSR_PENTIUM_4_EBC_FREQUENCY_ID\r
250**/\r
251typedef union {\r
252 ///\r
253 /// Individual bit fields\r
254 ///\r
255 struct {\r
256 UINT32 Reserved1:16;\r
257 ///\r
258 /// [Bits 18:16] Scalable Bus Speed (R/W) Indicates the intended scalable\r
259 /// bus speed: *EncodingScalable Bus Speed*\r
260 ///\r
261 /// 000B 100 MHz (Model 2).\r
262 /// 000B 266 MHz (Model 3 or 4)\r
263 /// 001B 133 MHz\r
264 /// 010B 200 MHz\r
265 /// 011B 166 MHz\r
266 /// 100B 333 MHz (Model 6)\r
267 ///\r
268 /// 133.33 MHz should be utilized if performing calculation with System\r
269 /// Bus Speed when encoding is 001B. 166.67 MHz should be utilized if\r
270 /// performing calculation with System Bus Speed when encoding is 011B.\r
271 /// 266.67 MHz should be utilized if performing calculation with System\r
272 /// Bus Speed when encoding is 000B and model encoding = 3 or 4. 333.33\r
273 /// MHz should be utilized if performing calculation with System Bus\r
274 /// Speed when encoding is 100B and model encoding = 6. All other values\r
275 /// are reserved.\r
276 ///\r
277 UINT32 ScalableBusSpeed:3;\r
278 UINT32 Reserved2:5;\r
279 ///\r
280 /// [Bits 31:24] Core Clock Frequency to System Bus Frequency Ratio (R)\r
281 /// The processor core clock frequency to system bus frequency ratio\r
282 /// observed at the de-assertion of the reset pin.\r
283 ///\r
284 UINT32 ClockRatio:8;\r
285 UINT32 Reserved3:32;\r
286 } Bits;\r
287 ///\r
288 /// All bit fields as a 32-bit value\r
289 ///\r
290 UINT32 Uint32;\r
291 ///\r
292 /// All bit fields as a 64-bit value\r
293 ///\r
294 UINT64 Uint64;\r
295} MSR_PENTIUM_4_EBC_FREQUENCY_ID_REGISTER;\r
296\r
297\r
298/**\r
299 0, 1. Shared. Processor Frequency Configuration (R) The bit field layout of\r
300 this MSR varies according to the MODEL value of the CPUID version\r
301 information. This bit field layout applies to Pentium 4 and Xeon Processors\r
302 with MODEL encoding less than 2. Indicates current processor frequency\r
303 configuration.\r
304\r
305 @param ECX MSR_PENTIUM_4_EBC_FREQUENCY_ID_1 (0x0000002C)\r
306 @param EAX Lower 32-bits of MSR value.\r
307 Described by the type MSR_PENTIUM_4_EBC_FREQUENCY_ID_1_REGISTER.\r
308 @param EDX Upper 32-bits of MSR value.\r
309 Described by the type MSR_PENTIUM_4_EBC_FREQUENCY_ID_1_REGISTER.\r
310\r
311 <b>Example usage</b>\r
312 @code\r
313 MSR_PENTIUM_4_EBC_FREQUENCY_ID_1_REGISTER Msr;\r
314\r
315 Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_4_EBC_FREQUENCY_ID_1);\r
316 @endcode\r
317**/\r
318#define MSR_PENTIUM_4_EBC_FREQUENCY_ID_1 0x0000002C\r
319\r
320/**\r
321 MSR information returned for MSR index #MSR_PENTIUM_4_EBC_FREQUENCY_ID_1\r
322**/\r
323typedef union {\r
324 ///\r
325 /// Individual bit fields\r
326 ///\r
327 struct {\r
328 UINT32 Reserved1:21;\r
329 ///\r
330 /// [Bits 23:21] Scalable Bus Speed (R/W) Indicates the intended scalable\r
331 /// bus speed: *Encoding* *Scalable Bus Speed*\r
332 ///\r
333 /// 000B 100 MHz All others values reserved.\r
334 ///\r
335 UINT32 ScalableBusSpeed:3;\r
336 UINT32 Reserved2:8;\r
337 UINT32 Reserved3:32;\r
338 } Bits;\r
339 ///\r
340 /// All bit fields as a 32-bit value\r
341 ///\r
342 UINT32 Uint32;\r
343 ///\r
344 /// All bit fields as a 64-bit value\r
345 ///\r
346 UINT64 Uint64;\r
347} MSR_PENTIUM_4_EBC_FREQUENCY_ID_1_REGISTER;\r
348\r
349\r
350/**\r
351 0, 1, 2, 3, 4, 6. Unique. Machine Check EAX/RAX Save State See Section\r
352 15.3.2.6, "IA32_MCG Extended Machine Check State MSRs.". Contains register\r
353 state at time of machine check error. When in non-64-bit modes at the time\r
354 of the error, bits 63-32 do not contain valid data.\r
355\r
356 @param ECX MSR_PENTIUM_4_MCG_RAX (0x00000180)\r
357 @param EAX Lower 32-bits of MSR value.\r
358 @param EDX Upper 32-bits of MSR value.\r
359\r
360 <b>Example usage</b>\r
361 @code\r
362 UINT64 Msr;\r
363\r
364 Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_RAX);\r
365 AsmWriteMsr64 (MSR_PENTIUM_4_MCG_RAX, Msr);\r
366 @endcode\r
367**/\r
368#define MSR_PENTIUM_4_MCG_RAX 0x00000180\r
369\r
370\r
371/**\r
372 0, 1, 2, 3, 4, 6. Unique. Machine Check EBX/RBX Save State See Section\r
373 15.3.2.6, "IA32_MCG Extended Machine Check State MSRs.". Contains register\r
374 state at time of machine check error. When in non-64-bit modes at the time\r
375 of the error, bits 63-32 do not contain valid data.\r
376\r
377 @param ECX MSR_PENTIUM_4_MCG_RBX (0x00000181)\r
378 @param EAX Lower 32-bits of MSR value.\r
379 @param EDX Upper 32-bits of MSR value.\r
380\r
381 <b>Example usage</b>\r
382 @code\r
383 UINT64 Msr;\r
384\r
385 Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_RBX);\r
386 AsmWriteMsr64 (MSR_PENTIUM_4_MCG_RBX, Msr);\r
387 @endcode\r
388**/\r
389#define MSR_PENTIUM_4_MCG_RBX 0x00000181\r
390\r
391\r
392/**\r
393 0, 1, 2, 3, 4, 6. Unique. Machine Check ECX/RCX Save State See Section\r
394 15.3.2.6, "IA32_MCG Extended Machine Check State MSRs.". Contains register\r
395 state at time of machine check error. When in non-64-bit modes at the time\r
396 of the error, bits 63-32 do not contain valid data.\r
397\r
398 @param ECX MSR_PENTIUM_4_MCG_RCX (0x00000182)\r
399 @param EAX Lower 32-bits of MSR value.\r
400 @param EDX Upper 32-bits of MSR value.\r
401\r
402 <b>Example usage</b>\r
403 @code\r
404 UINT64 Msr;\r
405\r
406 Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_RCX);\r
407 AsmWriteMsr64 (MSR_PENTIUM_4_MCG_RCX, Msr);\r
408 @endcode\r
409**/\r
410#define MSR_PENTIUM_4_MCG_RCX 0x00000182\r
411\r
412\r
413/**\r
414 0, 1, 2, 3, 4, 6. Unique. Machine Check EDX/RDX Save State See Section\r
415 15.3.2.6, "IA32_MCG Extended Machine Check State MSRs.". Contains register\r
416 state at time of machine check error. When in non-64-bit modes at the time\r
417 of the error, bits 63-32 do not contain valid data.\r
418\r
419 @param ECX MSR_PENTIUM_4_MCG_RDX (0x00000183)\r
420 @param EAX Lower 32-bits of MSR value.\r
421 @param EDX Upper 32-bits of MSR value.\r
422\r
423 <b>Example usage</b>\r
424 @code\r
425 UINT64 Msr;\r
426\r
427 Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_RDX);\r
428 AsmWriteMsr64 (MSR_PENTIUM_4_MCG_RDX, Msr);\r
429 @endcode\r
430**/\r
431#define MSR_PENTIUM_4_MCG_RDX 0x00000183\r
432\r
433\r
434/**\r
435 0, 1, 2, 3, 4, 6. Unique. Machine Check ESI/RSI Save State See Section\r
436 15.3.2.6, "IA32_MCG Extended Machine Check State MSRs.". Contains register\r
437 state at time of machine check error. When in non-64-bit modes at the time\r
438 of the error, bits 63-32 do not contain valid data.\r
439\r
440 @param ECX MSR_PENTIUM_4_MCG_RSI (0x00000184)\r
441 @param EAX Lower 32-bits of MSR value.\r
442 @param EDX Upper 32-bits of MSR value.\r
443\r
444 <b>Example usage</b>\r
445 @code\r
446 UINT64 Msr;\r
447\r
448 Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_RSI);\r
449 AsmWriteMsr64 (MSR_PENTIUM_4_MCG_RSI, Msr);\r
450 @endcode\r
451**/\r
452#define MSR_PENTIUM_4_MCG_RSI 0x00000184\r
453\r
454\r
455/**\r
456 0, 1, 2, 3, 4, 6. Unique. Machine Check EDI/RDI Save State See Section\r
457 15.3.2.6, "IA32_MCG Extended Machine Check State MSRs.". Contains register\r
458 state at time of machine check error. When in non-64-bit modes at the time\r
459 of the error, bits 63-32 do not contain valid data.\r
460\r
461 @param ECX MSR_PENTIUM_4_MCG_RDI (0x00000185)\r
462 @param EAX Lower 32-bits of MSR value.\r
463 @param EDX Upper 32-bits of MSR value.\r
464\r
465 <b>Example usage</b>\r
466 @code\r
467 UINT64 Msr;\r
468\r
469 Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_RDI);\r
470 AsmWriteMsr64 (MSR_PENTIUM_4_MCG_RDI, Msr);\r
471 @endcode\r
472**/\r
473#define MSR_PENTIUM_4_MCG_RDI 0x00000185\r
474\r
475\r
476/**\r
477 0, 1, 2, 3, 4, 6. Unique. Machine Check EBP/RBP Save State See Section\r
478 15.3.2.6, "IA32_MCG Extended Machine Check State MSRs.". Contains register\r
479 state at time of machine check error. When in non-64-bit modes at the time\r
480 of the error, bits 63-32 do not contain valid data.\r
481\r
482 @param ECX MSR_PENTIUM_4_MCG_RBP (0x00000186)\r
483 @param EAX Lower 32-bits of MSR value.\r
484 @param EDX Upper 32-bits of MSR value.\r
485\r
486 <b>Example usage</b>\r
487 @code\r
488 UINT64 Msr;\r
489\r
490 Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_RBP);\r
491 AsmWriteMsr64 (MSR_PENTIUM_4_MCG_RBP, Msr);\r
492 @endcode\r
493**/\r
494#define MSR_PENTIUM_4_MCG_RBP 0x00000186\r
495\r
496\r
497/**\r
498 0, 1, 2, 3, 4, 6. Unique. Machine Check ESP/RSP Save State See Section\r
499 15.3.2.6, "IA32_MCG Extended Machine Check State MSRs.". Contains register\r
500 state at time of machine check error. When in non-64-bit modes at the time\r
501 of the error, bits 63-32 do not contain valid data.\r
502\r
503 @param ECX MSR_PENTIUM_4_MCG_RSP (0x00000187)\r
504 @param EAX Lower 32-bits of MSR value.\r
505 @param EDX Upper 32-bits of MSR value.\r
506\r
507 <b>Example usage</b>\r
508 @code\r
509 UINT64 Msr;\r
510\r
511 Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_RSP);\r
512 AsmWriteMsr64 (MSR_PENTIUM_4_MCG_RSP, Msr);\r
513 @endcode\r
514**/\r
515#define MSR_PENTIUM_4_MCG_RSP 0x00000187\r
516\r
517\r
518/**\r
519 0, 1, 2, 3, 4, 6. Unique. Machine Check EFLAGS/RFLAG Save State See Section\r
520 15.3.2.6, "IA32_MCG Extended Machine Check State MSRs.". Contains register\r
521 state at time of machine check error. When in non-64-bit modes at the time\r
522 of the error, bits 63-32 do not contain valid data.\r
523\r
524 @param ECX MSR_PENTIUM_4_MCG_RFLAGS (0x00000188)\r
525 @param EAX Lower 32-bits of MSR value.\r
526 @param EDX Upper 32-bits of MSR value.\r
527\r
528 <b>Example usage</b>\r
529 @code\r
530 UINT64 Msr;\r
531\r
532 Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_RFLAGS);\r
533 AsmWriteMsr64 (MSR_PENTIUM_4_MCG_RFLAGS, Msr);\r
534 @endcode\r
535**/\r
536#define MSR_PENTIUM_4_MCG_RFLAGS 0x00000188\r
537\r
538\r
539/**\r
540 0, 1, 2, 3, 4, 6. Unique. Machine Check EIP/RIP Save State See Section\r
541 15.3.2.6, "IA32_MCG Extended Machine Check State MSRs.". Contains register\r
542 state at time of machine check error. When in non-64-bit modes at the time\r
543 of the error, bits 63-32 do not contain valid data.\r
544\r
545 @param ECX MSR_PENTIUM_4_MCG_RIP (0x00000189)\r
546 @param EAX Lower 32-bits of MSR value.\r
547 @param EDX Upper 32-bits of MSR value.\r
548\r
549 <b>Example usage</b>\r
550 @code\r
551 UINT64 Msr;\r
552\r
553 Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_RIP);\r
554 AsmWriteMsr64 (MSR_PENTIUM_4_MCG_RIP, Msr);\r
555 @endcode\r
556**/\r
557#define MSR_PENTIUM_4_MCG_RIP 0x00000189\r
558\r
559\r
560/**\r
561 0, 1, 2, 3, 4, 6. Unique. Machine Check Miscellaneous See Section 15.3.2.6,\r
562 "IA32_MCG Extended Machine Check State MSRs.".\r
563\r
564 @param ECX MSR_PENTIUM_4_MCG_MISC (0x0000018A)\r
565 @param EAX Lower 32-bits of MSR value.\r
566 Described by the type MSR_PENTIUM_4_MCG_MISC_REGISTER.\r
567 @param EDX Upper 32-bits of MSR value.\r
568 Described by the type MSR_PENTIUM_4_MCG_MISC_REGISTER.\r
569\r
570 <b>Example usage</b>\r
571 @code\r
572 MSR_PENTIUM_4_MCG_MISC_REGISTER Msr;\r
573\r
574 Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_4_MCG_MISC);\r
575 AsmWriteMsr64 (MSR_PENTIUM_4_MCG_MISC, Msr.Uint64);\r
576 @endcode\r
577**/\r
578#define MSR_PENTIUM_4_MCG_MISC 0x0000018A\r
579\r
580/**\r
581 MSR information returned for MSR index #MSR_PENTIUM_4_MCG_MISC\r
582**/\r
583typedef union {\r
584 ///\r
585 /// Individual bit fields\r
586 ///\r
587 struct {\r
588 ///\r
589 /// [Bit 0] DS When set, the bit indicates that a page assist or page\r
590 /// fault occurred during DS normal operation. The processors response is\r
591 /// to shut down. The bit is used as an aid for debugging DS handling\r
592 /// code. It is the responsibility of the user (BIOS or operating system)\r
593 /// to clear this bit for normal operation.\r
594 ///\r
595 UINT32 DS:1;\r
596 UINT32 Reserved1:31;\r
597 UINT32 Reserved2:32;\r
598 } Bits;\r
599 ///\r
600 /// All bit fields as a 32-bit value\r
601 ///\r
602 UINT32 Uint32;\r
603 ///\r
604 /// All bit fields as a 64-bit value\r
605 ///\r
606 UINT64 Uint64;\r
607} MSR_PENTIUM_4_MCG_MISC_REGISTER;\r
608\r
609\r
610/**\r
611 0, 1, 2, 3, 4, 6. Unique. Machine Check R8 See Section 15.3.2.6, "IA32_MCG\r
612 Extended Machine Check State MSRs.". Registers R8-15 (and the associated\r
613 state-save MSRs) exist only in Intel 64 processors. These registers contain\r
614 valid information only when the processor is operating in 64-bit mode at the\r
615 time of the error.\r
616\r
617 @param ECX MSR_PENTIUM_4_MCG_R8 (0x00000190)\r
618 @param EAX Lower 32-bits of MSR value.\r
619 @param EDX Upper 32-bits of MSR value.\r
620\r
621 <b>Example usage</b>\r
622 @code\r
623 UINT64 Msr;\r
624\r
625 Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_R8);\r
626 AsmWriteMsr64 (MSR_PENTIUM_4_MCG_R8, Msr);\r
627 @endcode\r
628**/\r
629#define MSR_PENTIUM_4_MCG_R8 0x00000190\r
630\r
631\r
632/**\r
633 0, 1, 2, 3, 4, 6. Unique. Machine Check R9D/R9 See Section 15.3.2.6,\r
634 "IA32_MCG Extended Machine Check State MSRs.". Registers R8-15 (and the\r
635 associated state-save MSRs) exist only in Intel 64 processors. These\r
636 registers contain valid information only when the processor is operating in\r
637 64-bit mode at the time of the error.\r
638\r
639 @param ECX MSR_PENTIUM_4_MCG_R9 (0x00000191)\r
640 @param EAX Lower 32-bits of MSR value.\r
641 @param EDX Upper 32-bits of MSR value.\r
642\r
643 <b>Example usage</b>\r
644 @code\r
645 UINT64 Msr;\r
646\r
647 Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_R9);\r
648 AsmWriteMsr64 (MSR_PENTIUM_4_MCG_R9, Msr);\r
649 @endcode\r
650**/\r
651#define MSR_PENTIUM_4_MCG_R9 0x00000191\r
652\r
653\r
654/**\r
655 0, 1, 2, 3, 4, 6. Unique. Machine Check R10 See Section 15.3.2.6, "IA32_MCG\r
656 Extended Machine Check State MSRs.". Registers R8-15 (and the associated\r
657 state-save MSRs) exist only in Intel 64 processors. These registers contain\r
658 valid information only when the processor is operating in 64-bit mode at the\r
659 time of the error.\r
660\r
661 @param ECX MSR_PENTIUM_4_MCG_R10 (0x00000192)\r
662 @param EAX Lower 32-bits of MSR value.\r
663 @param EDX Upper 32-bits of MSR value.\r
664\r
665 <b>Example usage</b>\r
666 @code\r
667 UINT64 Msr;\r
668\r
669 Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_R10);\r
670 AsmWriteMsr64 (MSR_PENTIUM_4_MCG_R10, Msr);\r
671 @endcode\r
672**/\r
673#define MSR_PENTIUM_4_MCG_R10 0x00000192\r
674\r
675\r
676/**\r
677 0, 1, 2, 3, 4, 6. Unique. Machine Check R11 See Section 15.3.2.6, "IA32_MCG\r
678 Extended Machine Check State MSRs.". Registers R8-15 (and the associated\r
679 state-save MSRs) exist only in Intel 64 processors. These registers contain\r
680 valid information only when the processor is operating in 64-bit mode at the\r
681 time of the error.\r
682\r
683 @param ECX MSR_PENTIUM_4_MCG_R11 (0x00000193)\r
684 @param EAX Lower 32-bits of MSR value.\r
685 @param EDX Upper 32-bits of MSR value.\r
686\r
687 <b>Example usage</b>\r
688 @code\r
689 UINT64 Msr;\r
690\r
691 Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_R11);\r
692 AsmWriteMsr64 (MSR_PENTIUM_4_MCG_R11, Msr);\r
693 @endcode\r
694**/\r
695#define MSR_PENTIUM_4_MCG_R11 0x00000193\r
696\r
697\r
698/**\r
699 0, 1, 2, 3, 4, 6. Unique. Machine Check R12 See Section 15.3.2.6, "IA32_MCG\r
700 Extended Machine Check State MSRs.". Registers R8-15 (and the associated\r
701 state-save MSRs) exist only in Intel 64 processors. These registers contain\r
702 valid information only when the processor is operating in 64-bit mode at the\r
703 time of the error.\r
704\r
705 @param ECX MSR_PENTIUM_4_MCG_R12 (0x00000194)\r
706 @param EAX Lower 32-bits of MSR value.\r
707 @param EDX Upper 32-bits of MSR value.\r
708\r
709 <b>Example usage</b>\r
710 @code\r
711 UINT64 Msr;\r
712\r
713 Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_R12);\r
714 AsmWriteMsr64 (MSR_PENTIUM_4_MCG_R12, Msr);\r
715 @endcode\r
716**/\r
717#define MSR_PENTIUM_4_MCG_R12 0x00000194\r
718\r
719\r
720/**\r
721 0, 1, 2, 3, 4, 6. Unique. Machine Check R13 See Section 15.3.2.6, "IA32_MCG\r
722 Extended Machine Check State MSRs.". Registers R8-15 (and the associated\r
723 state-save MSRs) exist only in Intel 64 processors. These registers contain\r
724 valid information only when the processor is operating in 64-bit mode at the\r
725 time of the error.\r
726\r
727 @param ECX MSR_PENTIUM_4_MCG_R13 (0x00000195)\r
728 @param EAX Lower 32-bits of MSR value.\r
729 @param EDX Upper 32-bits of MSR value.\r
730\r
731 <b>Example usage</b>\r
732 @code\r
733 UINT64 Msr;\r
734\r
735 Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_R13);\r
736 AsmWriteMsr64 (MSR_PENTIUM_4_MCG_R13, Msr);\r
737 @endcode\r
738**/\r
739#define MSR_PENTIUM_4_MCG_R13 0x00000195\r
740\r
741\r
742/**\r
743 0, 1, 2, 3, 4, 6. Unique. Machine Check R14 See Section 15.3.2.6, "IA32_MCG\r
744 Extended Machine Check State MSRs.". Registers R8-15 (and the associated\r
745 state-save MSRs) exist only in Intel 64 processors. These registers contain\r
746 valid information only when the processor is operating in 64-bit mode at the\r
747 time of the error.\r
748\r
749 @param ECX MSR_PENTIUM_4_MCG_R14 (0x00000196)\r
750 @param EAX Lower 32-bits of MSR value.\r
751 @param EDX Upper 32-bits of MSR value.\r
752\r
753 <b>Example usage</b>\r
754 @code\r
755 UINT64 Msr;\r
756\r
757 Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_R14);\r
758 AsmWriteMsr64 (MSR_PENTIUM_4_MCG_R14, Msr);\r
759 @endcode\r
760**/\r
761#define MSR_PENTIUM_4_MCG_R14 0x00000196\r
762\r
763\r
764/**\r
765 0, 1, 2, 3, 4, 6. Unique. Machine Check R15 See Section 15.3.2.6, "IA32_MCG\r
766 Extended Machine Check State MSRs.". Registers R8-15 (and the associated\r
767 state-save MSRs) exist only in Intel 64 processors. These registers contain\r
768 valid information only when the processor is operating in 64-bit mode at the\r
769 time of the error.\r
770\r
771 @param ECX MSR_PENTIUM_4_MCG_R15 (0x00000197)\r
772 @param EAX Lower 32-bits of MSR value.\r
773 @param EDX Upper 32-bits of MSR value.\r
774\r
775 <b>Example usage</b>\r
776 @code\r
777 UINT64 Msr;\r
778\r
779 Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_R15);\r
780 AsmWriteMsr64 (MSR_PENTIUM_4_MCG_R15, Msr);\r
781 @endcode\r
782**/\r
783#define MSR_PENTIUM_4_MCG_R15 0x00000197\r
784\r
785\r
786/**\r
787 Thermal Monitor 2 Control. 3,. Shared. For Family F, Model 3 processors:\r
788 When read, specifies the value of the target TM2 transition last written.\r
789 When set, it sets the next target value for TM2 transition. 4, 6. Shared.\r
790 For Family F, Model 4 and Model 6 processors: When read, specifies the value\r
791 of the target TM2 transition last written. Writes may cause #GP exceptions.\r
792\r
793 @param ECX MSR_PENTIUM_4_THERM2_CTL (0x0000019D)\r
794 @param EAX Lower 32-bits of MSR value.\r
795 @param EDX Upper 32-bits of MSR value.\r
796\r
797 <b>Example usage</b>\r
798 @code\r
799 UINT64 Msr;\r
800\r
801 Msr = AsmReadMsr64 (MSR_PENTIUM_4_THERM2_CTL);\r
802 AsmWriteMsr64 (MSR_PENTIUM_4_THERM2_CTL, Msr);\r
803 @endcode\r
804**/\r
805#define MSR_PENTIUM_4_THERM2_CTL 0x0000019D\r
806\r
807\r
808/**\r
809 0, 1, 2, 3, 4, 6. Shared. Enable Miscellaneous Processor Features (R/W).\r
810\r
811 @param ECX MSR_PENTIUM_4_IA32_MISC_ENABLE (0x000001A0)\r
812 @param EAX Lower 32-bits of MSR value.\r
813 Described by the type MSR_PENTIUM_4_IA32_MISC_ENABLE_REGISTER.\r
814 @param EDX Upper 32-bits of MSR value.\r
815 Described by the type MSR_PENTIUM_4_IA32_MISC_ENABLE_REGISTER.\r
816\r
817 <b>Example usage</b>\r
818 @code\r
819 MSR_PENTIUM_4_IA32_MISC_ENABLE_REGISTER Msr;\r
820\r
821 Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_4_IA32_MISC_ENABLE);\r
822 AsmWriteMsr64 (MSR_PENTIUM_4_IA32_MISC_ENABLE, Msr.Uint64);\r
823 @endcode\r
824**/\r
825#define MSR_PENTIUM_4_IA32_MISC_ENABLE 0x000001A0\r
826\r
827/**\r
828 MSR information returned for MSR index #MSR_PENTIUM_4_IA32_MISC_ENABLE\r
829**/\r
830typedef union {\r
831 ///\r
832 /// Individual bit fields\r
833 ///\r
834 struct {\r
835 ///\r
836 /// [Bit 0] Fast-Strings Enable. See Table 35-2.\r
837 ///\r
838 UINT32 FastStrings:1;\r
839 UINT32 Reserved1:1;\r
840 ///\r
841 /// [Bit 2] x87 FPU Fopcode Compatibility Mode Enable.\r
842 ///\r
843 UINT32 FPU:1;\r
844 ///\r
845 /// [Bit 3] Thermal Monitor 1 Enable See Section 14.7.2, "Thermal\r
846 /// Monitor," and see Table 35-2.\r
847 ///\r
848 UINT32 TM1:1;\r
849 ///\r
850 /// [Bit 4] Split-Lock Disable When set, the bit causes an #AC exception\r
851 /// to be issued instead of a split-lock cycle. Operating systems that set\r
852 /// this bit must align system structures to avoid split-lock scenarios.\r
853 /// When the bit is clear (default), normal split-locks are issued to the\r
854 /// bus.\r
855 /// This debug feature is specific to the Pentium 4 processor.\r
856 ///\r
857 UINT32 SplitLockDisable:1;\r
858 UINT32 Reserved2:1;\r
859 ///\r
860 /// [Bit 6] Third-Level Cache Disable (R/W) When set, the third-level\r
861 /// cache is disabled; when clear (default) the third-level cache is\r
862 /// enabled. This flag is reserved for processors that do not have a\r
863 /// third-level cache. Note that the bit controls only the third-level\r
864 /// cache; and only if overall caching is enabled through the CD flag of\r
865 /// control register CR0, the page-level cache controls, and/or the MTRRs.\r
866 /// See Section 11.5.4, "Disabling and Enabling the L3 Cache.".\r
867 ///\r
868 UINT32 ThirdLevelCacheDisable:1;\r
869 ///\r
870 /// [Bit 7] Performance Monitoring Available (R) See Table 35-2.\r
871 ///\r
872 UINT32 PerformanceMonitoring:1;\r
873 ///\r
874 /// [Bit 8] Suppress Lock Enable When set, assertion of LOCK on the bus is\r
875 /// suppressed during a Split Lock access. When clear (default), LOCK is\r
876 /// not suppressed.\r
877 ///\r
878 UINT32 SuppressLockEnable:1;\r
879 ///\r
880 /// [Bit 9] Prefetch Queue Disable When set, disables the prefetch queue.\r
881 /// When clear (default), enables the prefetch queue.\r
882 ///\r
883 UINT32 PrefetchQueueDisable:1;\r
884 ///\r
885 /// [Bit 10] FERR# Interrupt Reporting Enable (R/W) When set, interrupt\r
886 /// reporting through the FERR# pin is enabled; when clear, this interrupt\r
887 /// reporting function is disabled.\r
888 /// When this flag is set and the processor is in the stop-clock state\r
889 /// (STPCLK# is asserted), asserting the FERR# pin signals to the\r
890 /// processor that an interrupt (such as, INIT#, BINIT#, INTR, NMI,\r
891 /// SMI#, or RESET#) is pending and that the processor should return to\r
892 /// normal operation to handle the interrupt. This flag does not affect\r
893 /// the normal operation of the FERR# pin (to indicate an unmasked\r
894 /// floatingpoint error) when the STPCLK# pin is not asserted.\r
895 ///\r
896 UINT32 FERR:1;\r
897 ///\r
898 /// [Bit 11] Branch Trace Storage Unavailable (BTS_UNAVILABLE) (R) See\r
899 /// Table 35-2. When set, the processor does not support branch trace\r
900 /// storage (BTS); when clear, BTS is supported.\r
901 ///\r
902 UINT32 BTS:1;\r
903 ///\r
904 /// [Bit 12] PEBS_UNAVILABLE: Precise Event Based Sampling Unavailable (R)\r
905 /// See Table 35-2. When set, the processor does not support precise\r
906 /// event-based sampling (PEBS); when clear, PEBS is supported.\r
907 ///\r
908 UINT32 PEBS:1;\r
909 ///\r
910 /// [Bit 13] 3. TM2 Enable (R/W) When this bit is set (1) and the thermal\r
911 /// sensor indicates that the die temperature is at the predetermined\r
912 /// threshold, the Thermal Monitor 2 mechanism is engaged. TM2 will reduce\r
913 /// the bus to core ratio and voltage according to the value last written\r
914 /// to MSR_THERM2_CTL bits 15:0. When this bit is clear (0, default), the\r
915 /// processor does not change the VID signals or the bus to core ratio\r
916 /// when the processor enters a thermal managed state. If the TM2 feature\r
917 /// flag (ECX[8]) is not set to 1 after executing CPUID with EAX = 1, then\r
918 /// this feature is not supported and BIOS must not alter the contents of\r
919 /// this bit location. The processor is operating out of spec if both this\r
920 /// bit and the TM1 bit are set to disabled states.\r
921 ///\r
922 UINT32 TM2:1;\r
923 UINT32 Reserved3:4;\r
924 ///\r
925 /// [Bit 18] 3, 4, 6. ENABLE MONITOR FSM (R/W) See Table 35-2.\r
926 ///\r
927 UINT32 MONITOR:1;\r
928 ///\r
929 /// [Bit 19] Adjacent Cache Line Prefetch Disable (R/W) When set to 1,\r
930 /// the processor fetches the cache line of the 128-byte sector containing\r
931 /// currently required data. When set to 0, the processor fetches both\r
932 /// cache lines in the sector.\r
933 /// Single processor platforms should not set this bit. Server platforms\r
934 /// should set or clear this bit based on platform performance observed\r
935 /// in validation and testing. BIOS may contain a setup option that\r
936 /// controls the setting of this bit.\r
937 ///\r
938 UINT32 AdjacentCacheLinePrefetchDisable:1;\r
939 UINT32 Reserved4:2;\r
940 ///\r
941 /// [Bit 22] 3, 4, 6. Limit CPUID MAXVAL (R/W) See Table 35-2. Setting\r
942 /// this can cause unexpected behavior to software that depends on the\r
943 /// availability of CPUID leaves greater than 3.\r
944 ///\r
945 UINT32 LimitCpuidMaxval:1;\r
946 ///\r
947 /// [Bit 23] Shared. xTPR Message Disable (R/W) See Table 35-2.\r
948 ///\r
949 UINT32 xTPR_Message_Disable:1;\r
950 ///\r
951 /// [Bit 24] L1 Data Cache Context Mode (R/W) When set, the L1 data cache\r
952 /// is placed in shared mode; when clear (default), the cache is placed in\r
953 /// adaptive mode. This bit is only enabled for IA-32 processors that\r
954 /// support Intel Hyper-Threading Technology. See Section 11.5.6, "L1 Data\r
955 /// Cache Context Mode." When L1 is running in adaptive mode and CR3s are\r
956 /// identical, data in L1 is shared across logical processors. Otherwise,\r
957 /// L1 is not shared and cache use is competitive. If the Context ID\r
958 /// feature flag (ECX[10]) is set to 0 after executing CPUID with EAX = 1,\r
959 /// the ability to switch modes is not supported. BIOS must not alter the\r
960 /// contents of IA32_MISC_ENABLE[24].\r
961 ///\r
962 UINT32 L1DataCacheContextMode:1;\r
963 UINT32 Reserved5:7;\r
964 UINT32 Reserved6:2;\r
965 ///\r
966 /// [Bit 34] Unique. XD Bit Disable (R/W) See Table 35-2.\r
967 ///\r
968 UINT32 XD:1;\r
969 UINT32 Reserved7:29;\r
970 } Bits;\r
971 ///\r
972 /// All bit fields as a 64-bit value\r
973 ///\r
974 UINT64 Uint64;\r
975} MSR_PENTIUM_4_IA32_MISC_ENABLE_REGISTER;\r
976\r
977\r
978/**\r
979 3, 4, 6. Shared. Platform Feature Requirements (R).\r
980\r
981 @param ECX MSR_PENTIUM_4_PLATFORM_BRV (0x000001A1)\r
982 @param EAX Lower 32-bits of MSR value.\r
983 Described by the type MSR_PENTIUM_4_PLATFORM_BRV_REGISTER.\r
984 @param EDX Upper 32-bits of MSR value.\r
985 Described by the type MSR_PENTIUM_4_PLATFORM_BRV_REGISTER.\r
986\r
987 <b>Example usage</b>\r
988 @code\r
989 MSR_PENTIUM_4_PLATFORM_BRV_REGISTER Msr;\r
990\r
991 Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_4_PLATFORM_BRV);\r
992 @endcode\r
993**/\r
994#define MSR_PENTIUM_4_PLATFORM_BRV 0x000001A1\r
995\r
996/**\r
997 MSR information returned for MSR index #MSR_PENTIUM_4_PLATFORM_BRV\r
998**/\r
999typedef union {\r
1000 ///\r
1001 /// Individual bit fields\r
1002 ///\r
1003 struct {\r
1004 UINT32 Reserved1:18;\r
1005 ///\r
1006 /// [Bit 18] PLATFORM Requirements When set to 1, indicates the processor\r
1007 /// has specific platform requirements. The details of the platform\r
1008 /// requirements are listed in the respective data sheets of the processor.\r
1009 ///\r
1010 UINT32 PLATFORM:1;\r
1011 UINT32 Reserved2:13;\r
1012 UINT32 Reserved3:32;\r
1013 } Bits;\r
1014 ///\r
1015 /// All bit fields as a 32-bit value\r
1016 ///\r
1017 UINT32 Uint32;\r
1018 ///\r
1019 /// All bit fields as a 64-bit value\r
1020 ///\r
1021 UINT64 Uint64;\r
1022} MSR_PENTIUM_4_PLATFORM_BRV_REGISTER;\r
1023\r
1024\r
1025/**\r
1026 0, 1, 2, 3, 4, 6. Unique. Last Exception Record From Linear IP (R) Contains\r
1027 a pointer to the last branch instruction that the processor executed prior\r
1028 to the last exception that was generated or the last interrupt that was\r
1029 handled. See Section 17.10.3, "Last Exception Records.". Unique. From Linear\r
1030 IP Linear address of the last branch instruction (If IA32e mode is active).\r
1031 From Linear IP Linear address of the last branch instruction. Reserved.\r
1032\r
1033 @param ECX MSR_PENTIUM_4_LER_FROM_LIP (0x000001D7)\r
1034 @param EAX Lower 32-bits of MSR value.\r
1035 @param EDX Upper 32-bits of MSR value.\r
1036\r
1037 <b>Example usage</b>\r
1038 @code\r
1039 UINT64 Msr;\r
1040\r
1041 Msr = AsmReadMsr64 (MSR_PENTIUM_4_LER_FROM_LIP);\r
1042 @endcode\r
1043**/\r
1044#define MSR_PENTIUM_4_LER_FROM_LIP 0x000001D7\r
1045\r
1046\r
1047/**\r
1048 0, 1, 2, 3, 4, 6. Unique. Last Exception Record To Linear IP (R) This area\r
1049 contains a pointer to the target of the last branch instruction that the\r
1050 processor executed prior to the last exception that was generated or the\r
1051 last interrupt that was handled. See Section 17.10.3, "Last Exception\r
1052 Records.". Unique. From Linear IP Linear address of the target of the last\r
1053 branch instruction (If IA-32e mode is active). From Linear IP Linear address\r
1054 of the target of the last branch instruction. Reserved.\r
1055\r
1056 @param ECX MSR_PENTIUM_4_LER_TO_LIP (0x000001D8)\r
1057 @param EAX Lower 32-bits of MSR value.\r
1058 @param EDX Upper 32-bits of MSR value.\r
1059\r
1060 <b>Example usage</b>\r
1061 @code\r
1062 UINT64 Msr;\r
1063\r
1064 Msr = AsmReadMsr64 (MSR_PENTIUM_4_LER_TO_LIP);\r
1065 @endcode\r
1066**/\r
1067#define MSR_PENTIUM_4_LER_TO_LIP 0x000001D8\r
1068\r
1069\r
1070/**\r
1071 0, 1, 2, 3, 4, 6. Unique. Debug Control (R/W) Controls how several debug\r
1072 features are used. Bit definitions are discussed in the referenced section.\r
1073 See Section 17.10.1, "MSR_DEBUGCTLA MSR.".\r
1074\r
1075 @param ECX MSR_PENTIUM_4_DEBUGCTLA (0x000001D9)\r
1076 @param EAX Lower 32-bits of MSR value.\r
1077 @param EDX Upper 32-bits of MSR value.\r
1078\r
1079 <b>Example usage</b>\r
1080 @code\r
1081 UINT64 Msr;\r
1082\r
1083 Msr = AsmReadMsr64 (MSR_PENTIUM_4_DEBUGCTLA);\r
1084 AsmWriteMsr64 (MSR_PENTIUM_4_DEBUGCTLA, Msr);\r
1085 @endcode\r
1086**/\r
1087#define MSR_PENTIUM_4_DEBUGCTLA 0x000001D9\r
1088\r
1089\r
1090/**\r
1091 0, 1, 2, 3, 4, 6. Unique. Last Branch Record Stack TOS (R/W) Contains an\r
1092 index (0-3 or 0-15) that points to the top of the last branch record stack\r
1093 (that is, that points the index of the MSR containing the most recent branch\r
1094 record). See Section 17.10.2, "LBR Stack for Processors Based on Intel\r
1095 NetBurst(R) Microarchitecture"; and addresses 1DBH-1DEH and 680H-68FH.\r
1096\r
1097 @param ECX MSR_PENTIUM_4_LASTBRANCH_TOS (0x000001DA)\r
1098 @param EAX Lower 32-bits of MSR value.\r
1099 @param EDX Upper 32-bits of MSR value.\r
1100\r
1101 <b>Example usage</b>\r
1102 @code\r
1103 UINT64 Msr;\r
1104\r
1105 Msr = AsmReadMsr64 (MSR_PENTIUM_4_LASTBRANCH_TOS);\r
1106 AsmWriteMsr64 (MSR_PENTIUM_4_LASTBRANCH_TOS, Msr);\r
1107 @endcode\r
1108**/\r
1109#define MSR_PENTIUM_4_LASTBRANCH_TOS 0x000001DA\r
1110\r
1111\r
1112/**\r
1113 0, 1, 2. Unique. Last Branch Record n (R/W) One of four last branch record\r
1114 registers on the last branch record stack. It contains pointers to the\r
1115 source and destination instruction for one of the last four branches,\r
1116 exceptions, or interrupts that the processor took. MSR_LASTBRANCH_0 through\r
1117 MSR_LASTBRANCH_3 at 1DBH-1DEH are available only on family 0FH, models\r
1118 0H-02H. They have been replaced by the MSRs at 680H68FH and 6C0H-6CFH. See\r
1119 Section 17.9, "Last Branch, Call Stack, Interrupt, and Exception Recording\r
1120 for Processors based on Skylake Microarchitecture.".\r
1121\r
1122 @param ECX MSR_PENTIUM_4_LASTBRANCH_n\r
1123 @param EAX Lower 32-bits of MSR value.\r
1124 @param EDX Upper 32-bits of MSR value.\r
1125\r
1126 <b>Example usage</b>\r
1127 @code\r
1128 UINT64 Msr;\r
1129\r
1130 Msr = AsmReadMsr64 (MSR_PENTIUM_4_LASTBRANCH_0);\r
1131 AsmWriteMsr64 (MSR_PENTIUM_4_LASTBRANCH_0, Msr);\r
1132 @endcode\r
1133 @{\r
1134**/\r
1135#define MSR_PENTIUM_4_LASTBRANCH_0 0x000001DB\r
1136#define MSR_PENTIUM_4_LASTBRANCH_1 0x000001DC\r
1137#define MSR_PENTIUM_4_LASTBRANCH_2 0x000001DD\r
1138#define MSR_PENTIUM_4_LASTBRANCH_3 0x000001DE\r
1139/// @}\r
1140\r
1141\r
1142/**\r
1143 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.2, "Performance Counters.".\r
1144\r
1145 @param ECX MSR_PENTIUM_4_BPU_COUNTERn\r
1146 @param EAX Lower 32-bits of MSR value.\r
1147 @param EDX Upper 32-bits of MSR value.\r
1148\r
1149 <b>Example usage</b>\r
1150 @code\r
1151 UINT64 Msr;\r
1152\r
1153 Msr = AsmReadMsr64 (MSR_PENTIUM_4_BPU_COUNTER0);\r
1154 AsmWriteMsr64 (MSR_PENTIUM_4_BPU_COUNTER0, Msr);\r
1155 @endcode\r
1156 @{\r
1157**/\r
1158#define MSR_PENTIUM_4_BPU_COUNTER0 0x00000300\r
1159#define MSR_PENTIUM_4_BPU_COUNTER1 0x00000301\r
1160#define MSR_PENTIUM_4_BPU_COUNTER2 0x00000302\r
1161#define MSR_PENTIUM_4_BPU_COUNTER3 0x00000303\r
1162/// @}\r
1163\r
1164\r
1165/**\r
1166 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.2, "Performance Counters.".\r
1167\r
1168 @param ECX MSR_PENTIUM_4_MS_COUNTERn\r
1169 @param EAX Lower 32-bits of MSR value.\r
1170 @param EDX Upper 32-bits of MSR value.\r
1171\r
1172 <b>Example usage</b>\r
1173 @code\r
1174 UINT64 Msr;\r
1175\r
1176 Msr = AsmReadMsr64 (MSR_PENTIUM_4_MS_COUNTER0);\r
1177 AsmWriteMsr64 (MSR_PENTIUM_4_MS_COUNTER0, Msr);\r
1178 @endcode\r
1179 @{\r
1180**/\r
1181#define MSR_PENTIUM_4_MS_COUNTER0 0x00000304\r
1182#define MSR_PENTIUM_4_MS_COUNTER1 0x00000305\r
1183#define MSR_PENTIUM_4_MS_COUNTER2 0x00000306\r
1184#define MSR_PENTIUM_4_MS_COUNTER3 0x00000307\r
1185/// @}\r
1186\r
1187\r
1188/**\r
1189 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.2, "Performance Counters.".\r
1190\r
1191 @param ECX MSR_PENTIUM_4_FLAME_COUNTERn (0x00000308)\r
1192 @param EAX Lower 32-bits of MSR value.\r
1193 @param EDX Upper 32-bits of MSR value.\r
1194\r
1195 <b>Example usage</b>\r
1196 @code\r
1197 UINT64 Msr;\r
1198\r
1199 Msr = AsmReadMsr64 (MSR_PENTIUM_4_FLAME_COUNTER0);\r
1200 AsmWriteMsr64 (MSR_PENTIUM_4_FLAME_COUNTER0, Msr);\r
1201 @endcode\r
1202 @{\r
1203**/\r
1204#define MSR_PENTIUM_4_FLAME_COUNTER0 0x00000308\r
1205#define MSR_PENTIUM_4_FLAME_COUNTER1 0x00000309\r
1206#define MSR_PENTIUM_4_FLAME_COUNTER2 0x0000030A\r
1207#define MSR_PENTIUM_4_FLAME_COUNTER3 0x0000030B\r
1208/// @}\r
1209\r
1210\r
1211/**\r
1212 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.2, "Performance Counters.".\r
1213\r
1214 @param ECX MSR_PENTIUM_4_IQ_COUNTERn\r
1215 @param EAX Lower 32-bits of MSR value.\r
1216 @param EDX Upper 32-bits of MSR value.\r
1217\r
1218 <b>Example usage</b>\r
1219 @code\r
1220 UINT64 Msr;\r
1221\r
1222 Msr = AsmReadMsr64 (MSR_PENTIUM_4_IQ_COUNTER0);\r
1223 AsmWriteMsr64 (MSR_PENTIUM_4_IQ_COUNTER0, Msr);\r
1224 @endcode\r
1225 @{\r
1226**/\r
1227#define MSR_PENTIUM_4_IQ_COUNTER0 0x0000030C\r
1228#define MSR_PENTIUM_4_IQ_COUNTER1 0x0000030D\r
1229#define MSR_PENTIUM_4_IQ_COUNTER2 0x0000030E\r
1230#define MSR_PENTIUM_4_IQ_COUNTER3 0x0000030F\r
1231#define MSR_PENTIUM_4_IQ_COUNTER4 0x00000310\r
1232#define MSR_PENTIUM_4_IQ_COUNTER5 0x00000311\r
1233/// @}\r
1234\r
1235\r
1236/**\r
1237 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.3, "CCCR MSRs.".\r
1238\r
1239 @param ECX MSR_PENTIUM_4_BPU_CCCRn\r
1240 @param EAX Lower 32-bits of MSR value.\r
1241 @param EDX Upper 32-bits of MSR value.\r
1242\r
1243 <b>Example usage</b>\r
1244 @code\r
1245 UINT64 Msr;\r
1246\r
1247 Msr = AsmReadMsr64 (MSR_PENTIUM_4_BPU_CCCR0);\r
1248 AsmWriteMsr64 (MSR_PENTIUM_4_BPU_CCCR0, Msr);\r
1249 @endcode\r
1250 @{\r
1251**/\r
1252#define MSR_PENTIUM_4_BPU_CCCR0 0x00000360\r
1253#define MSR_PENTIUM_4_BPU_CCCR1 0x00000361\r
1254#define MSR_PENTIUM_4_BPU_CCCR2 0x00000362\r
1255#define MSR_PENTIUM_4_BPU_CCCR3 0x00000363\r
1256/// @}\r
1257\r
1258\r
1259/**\r
1260 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.3, "CCCR MSRs.".\r
1261\r
1262 @param ECX MSR_PENTIUM_4_MS_CCCRn\r
1263 @param EAX Lower 32-bits of MSR value.\r
1264 @param EDX Upper 32-bits of MSR value.\r
1265\r
1266 <b>Example usage</b>\r
1267 @code\r
1268 UINT64 Msr;\r
1269\r
1270 Msr = AsmReadMsr64 (MSR_PENTIUM_4_MS_CCCR0);\r
1271 AsmWriteMsr64 (MSR_PENTIUM_4_MS_CCCR0, Msr);\r
1272 @endcode\r
1273 @{\r
1274**/\r
1275#define MSR_PENTIUM_4_MS_CCCR0 0x00000364\r
1276#define MSR_PENTIUM_4_MS_CCCR1 0x00000365\r
1277#define MSR_PENTIUM_4_MS_CCCR2 0x00000366\r
1278#define MSR_PENTIUM_4_MS_CCCR3 0x00000367\r
1279/// @}\r
1280\r
1281\r
1282/**\r
1283 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.3, "CCCR MSRs.".\r
1284\r
1285 @param ECX MSR_PENTIUM_4_FLAME_CCCRn\r
1286 @param EAX Lower 32-bits of MSR value.\r
1287 @param EDX Upper 32-bits of MSR value.\r
1288\r
1289 <b>Example usage</b>\r
1290 @code\r
1291 UINT64 Msr;\r
1292\r
1293 Msr = AsmReadMsr64 (MSR_PENTIUM_4_FLAME_CCCR0);\r
1294 AsmWriteMsr64 (MSR_PENTIUM_4_FLAME_CCCR0, Msr);\r
1295 @endcode\r
1296 @{\r
1297**/\r
1298#define MSR_PENTIUM_4_FLAME_CCCR0 0x00000368\r
1299#define MSR_PENTIUM_4_FLAME_CCCR1 0x00000369\r
1300#define MSR_PENTIUM_4_FLAME_CCCR2 0x0000036A\r
1301#define MSR_PENTIUM_4_FLAME_CCCR3 0x0000036B\r
1302/// @}\r
1303\r
1304\r
1305/**\r
1306 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.3, "CCCR MSRs.".\r
1307\r
1308 @param ECX MSR_PENTIUM_4_IQ_CCCRn\r
1309 @param EAX Lower 32-bits of MSR value.\r
1310 @param EDX Upper 32-bits of MSR value.\r
1311\r
1312 <b>Example usage</b>\r
1313 @code\r
1314 UINT64 Msr;\r
1315\r
1316 Msr = AsmReadMsr64 (MSR_PENTIUM_4_IQ_CCCR0);\r
1317 AsmWriteMsr64 (MSR_PENTIUM_4_IQ_CCCR0, Msr);\r
1318 @endcode\r
1319 @{\r
1320**/\r
1321#define MSR_PENTIUM_4_IQ_CCCR0 0x0000036C\r
1322#define MSR_PENTIUM_4_IQ_CCCR1 0x0000036D\r
1323#define MSR_PENTIUM_4_IQ_CCCR2 0x0000036E\r
1324#define MSR_PENTIUM_4_IQ_CCCR3 0x0000036F\r
1325#define MSR_PENTIUM_4_IQ_CCCR4 0x00000370\r
1326#define MSR_PENTIUM_4_IQ_CCCR5 0x00000371\r
1327/// @}\r
1328\r
1329\r
1330/**\r
1331 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".\r
1332\r
1333 @param ECX MSR_PENTIUM_4_BSU_ESCR0 (0x000003A0)\r
1334 @param EAX Lower 32-bits of MSR value.\r
1335 @param EDX Upper 32-bits of MSR value.\r
1336\r
1337 <b>Example usage</b>\r
1338 @code\r
1339 UINT64 Msr;\r
1340\r
1341 Msr = AsmReadMsr64 (MSR_PENTIUM_4_BSU_ESCR0);\r
1342 AsmWriteMsr64 (MSR_PENTIUM_4_BSU_ESCR0, Msr);\r
1343 @endcode\r
1344**/\r
1345#define MSR_PENTIUM_4_BSU_ESCR0 0x000003A0\r
1346\r
1347\r
1348/**\r
1349 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".\r
1350\r
1351 @param ECX MSR_PENTIUM_4_BSU_ESCR1 (0x000003A1)\r
1352 @param EAX Lower 32-bits of MSR value.\r
1353 @param EDX Upper 32-bits of MSR value.\r
1354\r
1355 <b>Example usage</b>\r
1356 @code\r
1357 UINT64 Msr;\r
1358\r
1359 Msr = AsmReadMsr64 (MSR_PENTIUM_4_BSU_ESCR1);\r
1360 AsmWriteMsr64 (MSR_PENTIUM_4_BSU_ESCR1, Msr);\r
1361 @endcode\r
1362**/\r
1363#define MSR_PENTIUM_4_BSU_ESCR1 0x000003A1\r
1364\r
1365\r
1366/**\r
1367 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".\r
1368\r
1369 @param ECX MSR_PENTIUM_4_FSB_ESCR0 (0x000003A2)\r
1370 @param EAX Lower 32-bits of MSR value.\r
1371 @param EDX Upper 32-bits of MSR value.\r
1372\r
1373 <b>Example usage</b>\r
1374 @code\r
1375 UINT64 Msr;\r
1376\r
1377 Msr = AsmReadMsr64 (MSR_PENTIUM_4_FSB_ESCR0);\r
1378 AsmWriteMsr64 (MSR_PENTIUM_4_FSB_ESCR0, Msr);\r
1379 @endcode\r
1380**/\r
1381#define MSR_PENTIUM_4_FSB_ESCR0 0x000003A2\r
1382\r
1383\r
1384/**\r
1385 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".\r
1386\r
1387 @param ECX MSR_PENTIUM_4_FSB_ESCR1 (0x000003A3)\r
1388 @param EAX Lower 32-bits of MSR value.\r
1389 @param EDX Upper 32-bits of MSR value.\r
1390\r
1391 <b>Example usage</b>\r
1392 @code\r
1393 UINT64 Msr;\r
1394\r
1395 Msr = AsmReadMsr64 (MSR_PENTIUM_4_FSB_ESCR1);\r
1396 AsmWriteMsr64 (MSR_PENTIUM_4_FSB_ESCR1, Msr);\r
1397 @endcode\r
1398**/\r
1399#define MSR_PENTIUM_4_FSB_ESCR1 0x000003A3\r
1400\r
1401\r
1402/**\r
1403 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".\r
1404\r
1405 @param ECX MSR_PENTIUM_4_FIRM_ESCR0 (0x000003A4)\r
1406 @param EAX Lower 32-bits of MSR value.\r
1407 @param EDX Upper 32-bits of MSR value.\r
1408\r
1409 <b>Example usage</b>\r
1410 @code\r
1411 UINT64 Msr;\r
1412\r
1413 Msr = AsmReadMsr64 (MSR_PENTIUM_4_FIRM_ESCR0);\r
1414 AsmWriteMsr64 (MSR_PENTIUM_4_FIRM_ESCR0, Msr);\r
1415 @endcode\r
1416**/\r
1417#define MSR_PENTIUM_4_FIRM_ESCR0 0x000003A4\r
1418\r
1419\r
1420/**\r
1421 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".\r
1422\r
1423 @param ECX MSR_PENTIUM_4_FIRM_ESCR1 (0x000003A5)\r
1424 @param EAX Lower 32-bits of MSR value.\r
1425 @param EDX Upper 32-bits of MSR value.\r
1426\r
1427 <b>Example usage</b>\r
1428 @code\r
1429 UINT64 Msr;\r
1430\r
1431 Msr = AsmReadMsr64 (MSR_PENTIUM_4_FIRM_ESCR1);\r
1432 AsmWriteMsr64 (MSR_PENTIUM_4_FIRM_ESCR1, Msr);\r
1433 @endcode\r
1434**/\r
1435#define MSR_PENTIUM_4_FIRM_ESCR1 0x000003A5\r
1436\r
1437\r
1438/**\r
1439 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".\r
1440\r
1441 @param ECX MSR_PENTIUM_4_FLAME_ESCR0 (0x000003A6)\r
1442 @param EAX Lower 32-bits of MSR value.\r
1443 @param EDX Upper 32-bits of MSR value.\r
1444\r
1445 <b>Example usage</b>\r
1446 @code\r
1447 UINT64 Msr;\r
1448\r
1449 Msr = AsmReadMsr64 (MSR_PENTIUM_4_FLAME_ESCR0);\r
1450 AsmWriteMsr64 (MSR_PENTIUM_4_FLAME_ESCR0, Msr);\r
1451 @endcode\r
1452**/\r
1453#define MSR_PENTIUM_4_FLAME_ESCR0 0x000003A6\r
1454\r
1455\r
1456/**\r
1457 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".\r
1458\r
1459 @param ECX MSR_PENTIUM_4_FLAME_ESCR1 (0x000003A7)\r
1460 @param EAX Lower 32-bits of MSR value.\r
1461 @param EDX Upper 32-bits of MSR value.\r
1462\r
1463 <b>Example usage</b>\r
1464 @code\r
1465 UINT64 Msr;\r
1466\r
1467 Msr = AsmReadMsr64 (MSR_PENTIUM_4_FLAME_ESCR1);\r
1468 AsmWriteMsr64 (MSR_PENTIUM_4_FLAME_ESCR1, Msr);\r
1469 @endcode\r
1470**/\r
1471#define MSR_PENTIUM_4_FLAME_ESCR1 0x000003A7\r
1472\r
1473\r
1474/**\r
1475 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".\r
1476\r
1477 @param ECX MSR_PENTIUM_4_DAC_ESCR0 (0x000003A8)\r
1478 @param EAX Lower 32-bits of MSR value.\r
1479 @param EDX Upper 32-bits of MSR value.\r
1480\r
1481 <b>Example usage</b>\r
1482 @code\r
1483 UINT64 Msr;\r
1484\r
1485 Msr = AsmReadMsr64 (MSR_PENTIUM_4_DAC_ESCR0);\r
1486 AsmWriteMsr64 (MSR_PENTIUM_4_DAC_ESCR0, Msr);\r
1487 @endcode\r
1488**/\r
1489#define MSR_PENTIUM_4_DAC_ESCR0 0x000003A8\r
1490\r
1491\r
1492/**\r
1493 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".\r
1494\r
1495 @param ECX MSR_PENTIUM_4_DAC_ESCR1 (0x000003A9)\r
1496 @param EAX Lower 32-bits of MSR value.\r
1497 @param EDX Upper 32-bits of MSR value.\r
1498\r
1499 <b>Example usage</b>\r
1500 @code\r
1501 UINT64 Msr;\r
1502\r
1503 Msr = AsmReadMsr64 (MSR_PENTIUM_4_DAC_ESCR1);\r
1504 AsmWriteMsr64 (MSR_PENTIUM_4_DAC_ESCR1, Msr);\r
1505 @endcode\r
1506**/\r
1507#define MSR_PENTIUM_4_DAC_ESCR1 0x000003A9\r
1508\r
1509\r
1510/**\r
1511 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".\r
1512\r
1513 @param ECX MSR_PENTIUM_4_MOB_ESCR0 (0x000003AA)\r
1514 @param EAX Lower 32-bits of MSR value.\r
1515 @param EDX Upper 32-bits of MSR value.\r
1516\r
1517 <b>Example usage</b>\r
1518 @code\r
1519 UINT64 Msr;\r
1520\r
1521 Msr = AsmReadMsr64 (MSR_PENTIUM_4_MOB_ESCR0);\r
1522 AsmWriteMsr64 (MSR_PENTIUM_4_MOB_ESCR0, Msr);\r
1523 @endcode\r
1524**/\r
1525#define MSR_PENTIUM_4_MOB_ESCR0 0x000003AA\r
1526\r
1527\r
1528/**\r
1529 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".\r
1530\r
1531 @param ECX MSR_PENTIUM_4_MOB_ESCR1 (0x000003AB)\r
1532 @param EAX Lower 32-bits of MSR value.\r
1533 @param EDX Upper 32-bits of MSR value.\r
1534\r
1535 <b>Example usage</b>\r
1536 @code\r
1537 UINT64 Msr;\r
1538\r
1539 Msr = AsmReadMsr64 (MSR_PENTIUM_4_MOB_ESCR1);\r
1540 AsmWriteMsr64 (MSR_PENTIUM_4_MOB_ESCR1, Msr);\r
1541 @endcode\r
1542**/\r
1543#define MSR_PENTIUM_4_MOB_ESCR1 0x000003AB\r
1544\r
1545\r
1546/**\r
1547 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".\r
1548\r
1549 @param ECX MSR_PENTIUM_4_PMH_ESCR0 (0x000003AC)\r
1550 @param EAX Lower 32-bits of MSR value.\r
1551 @param EDX Upper 32-bits of MSR value.\r
1552\r
1553 <b>Example usage</b>\r
1554 @code\r
1555 UINT64 Msr;\r
1556\r
1557 Msr = AsmReadMsr64 (MSR_PENTIUM_4_PMH_ESCR0);\r
1558 AsmWriteMsr64 (MSR_PENTIUM_4_PMH_ESCR0, Msr);\r
1559 @endcode\r
1560**/\r
1561#define MSR_PENTIUM_4_PMH_ESCR0 0x000003AC\r
1562\r
1563\r
1564/**\r
1565 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".\r
1566\r
1567 @param ECX MSR_PENTIUM_4_PMH_ESCR1 (0x000003AD)\r
1568 @param EAX Lower 32-bits of MSR value.\r
1569 @param EDX Upper 32-bits of MSR value.\r
1570\r
1571 <b>Example usage</b>\r
1572 @code\r
1573 UINT64 Msr;\r
1574\r
1575 Msr = AsmReadMsr64 (MSR_PENTIUM_4_PMH_ESCR1);\r
1576 AsmWriteMsr64 (MSR_PENTIUM_4_PMH_ESCR1, Msr);\r
1577 @endcode\r
1578**/\r
1579#define MSR_PENTIUM_4_PMH_ESCR1 0x000003AD\r
1580\r
1581\r
1582/**\r
1583 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".\r
1584\r
1585 @param ECX MSR_PENTIUM_4_SAAT_ESCR0 (0x000003AE)\r
1586 @param EAX Lower 32-bits of MSR value.\r
1587 @param EDX Upper 32-bits of MSR value.\r
1588\r
1589 <b>Example usage</b>\r
1590 @code\r
1591 UINT64 Msr;\r
1592\r
1593 Msr = AsmReadMsr64 (MSR_PENTIUM_4_SAAT_ESCR0);\r
1594 AsmWriteMsr64 (MSR_PENTIUM_4_SAAT_ESCR0, Msr);\r
1595 @endcode\r
1596**/\r
1597#define MSR_PENTIUM_4_SAAT_ESCR0 0x000003AE\r
1598\r
1599\r
1600/**\r
1601 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".\r
1602\r
1603 @param ECX MSR_PENTIUM_4_SAAT_ESCR1 (0x000003AF)\r
1604 @param EAX Lower 32-bits of MSR value.\r
1605 @param EDX Upper 32-bits of MSR value.\r
1606\r
1607 <b>Example usage</b>\r
1608 @code\r
1609 UINT64 Msr;\r
1610\r
1611 Msr = AsmReadMsr64 (MSR_PENTIUM_4_SAAT_ESCR1);\r
1612 AsmWriteMsr64 (MSR_PENTIUM_4_SAAT_ESCR1, Msr);\r
1613 @endcode\r
1614**/\r
1615#define MSR_PENTIUM_4_SAAT_ESCR1 0x000003AF\r
1616\r
1617\r
1618/**\r
1619 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".\r
1620\r
1621 @param ECX MSR_PENTIUM_4_U2L_ESCR0 (0x000003B0)\r
1622 @param EAX Lower 32-bits of MSR value.\r
1623 @param EDX Upper 32-bits of MSR value.\r
1624\r
1625 <b>Example usage</b>\r
1626 @code\r
1627 UINT64 Msr;\r
1628\r
1629 Msr = AsmReadMsr64 (MSR_PENTIUM_4_U2L_ESCR0);\r
1630 AsmWriteMsr64 (MSR_PENTIUM_4_U2L_ESCR0, Msr);\r
1631 @endcode\r
1632**/\r
1633#define MSR_PENTIUM_4_U2L_ESCR0 0x000003B0\r
1634\r
1635\r
1636/**\r
1637 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".\r
1638\r
1639 @param ECX MSR_PENTIUM_4_U2L_ESCR1 (0x000003B1)\r
1640 @param EAX Lower 32-bits of MSR value.\r
1641 @param EDX Upper 32-bits of MSR value.\r
1642\r
1643 <b>Example usage</b>\r
1644 @code\r
1645 UINT64 Msr;\r
1646\r
1647 Msr = AsmReadMsr64 (MSR_PENTIUM_4_U2L_ESCR1);\r
1648 AsmWriteMsr64 (MSR_PENTIUM_4_U2L_ESCR1, Msr);\r
1649 @endcode\r
1650**/\r
1651#define MSR_PENTIUM_4_U2L_ESCR1 0x000003B1\r
1652\r
1653\r
1654/**\r
1655 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".\r
1656\r
1657 @param ECX MSR_PENTIUM_4_BPU_ESCR0 (0x000003B2)\r
1658 @param EAX Lower 32-bits of MSR value.\r
1659 @param EDX Upper 32-bits of MSR value.\r
1660\r
1661 <b>Example usage</b>\r
1662 @code\r
1663 UINT64 Msr;\r
1664\r
1665 Msr = AsmReadMsr64 (MSR_PENTIUM_4_BPU_ESCR0);\r
1666 AsmWriteMsr64 (MSR_PENTIUM_4_BPU_ESCR0, Msr);\r
1667 @endcode\r
1668**/\r
1669#define MSR_PENTIUM_4_BPU_ESCR0 0x000003B2\r
1670\r
1671\r
1672/**\r
1673 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".\r
1674\r
1675 @param ECX MSR_PENTIUM_4_BPU_ESCR1 (0x000003B3)\r
1676 @param EAX Lower 32-bits of MSR value.\r
1677 @param EDX Upper 32-bits of MSR value.\r
1678\r
1679 <b>Example usage</b>\r
1680 @code\r
1681 UINT64 Msr;\r
1682\r
1683 Msr = AsmReadMsr64 (MSR_PENTIUM_4_BPU_ESCR1);\r
1684 AsmWriteMsr64 (MSR_PENTIUM_4_BPU_ESCR1, Msr);\r
1685 @endcode\r
1686**/\r
1687#define MSR_PENTIUM_4_BPU_ESCR1 0x000003B3\r
1688\r
1689\r
1690/**\r
1691 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".\r
1692\r
1693 @param ECX MSR_PENTIUM_4_IS_ESCR0 (0x000003B4)\r
1694 @param EAX Lower 32-bits of MSR value.\r
1695 @param EDX Upper 32-bits of MSR value.\r
1696\r
1697 <b>Example usage</b>\r
1698 @code\r
1699 UINT64 Msr;\r
1700\r
1701 Msr = AsmReadMsr64 (MSR_PENTIUM_4_IS_ESCR0);\r
1702 AsmWriteMsr64 (MSR_PENTIUM_4_IS_ESCR0, Msr);\r
1703 @endcode\r
1704**/\r
1705#define MSR_PENTIUM_4_IS_ESCR0 0x000003B4\r
1706\r
1707\r
1708/**\r
1709 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".\r
1710\r
1711 @param ECX MSR_PENTIUM_4_IS_ESCR1 (0x000003B5)\r
1712 @param EAX Lower 32-bits of MSR value.\r
1713 @param EDX Upper 32-bits of MSR value.\r
1714\r
1715 <b>Example usage</b>\r
1716 @code\r
1717 UINT64 Msr;\r
1718\r
1719 Msr = AsmReadMsr64 (MSR_PENTIUM_4_IS_ESCR1);\r
1720 AsmWriteMsr64 (MSR_PENTIUM_4_IS_ESCR1, Msr);\r
1721 @endcode\r
1722**/\r
1723#define MSR_PENTIUM_4_IS_ESCR1 0x000003B5\r
1724\r
1725\r
1726/**\r
1727 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".\r
1728\r
1729 @param ECX MSR_PENTIUM_4_ITLB_ESCR0 (0x000003B6)\r
1730 @param EAX Lower 32-bits of MSR value.\r
1731 @param EDX Upper 32-bits of MSR value.\r
1732\r
1733 <b>Example usage</b>\r
1734 @code\r
1735 UINT64 Msr;\r
1736\r
1737 Msr = AsmReadMsr64 (MSR_PENTIUM_4_ITLB_ESCR0);\r
1738 AsmWriteMsr64 (MSR_PENTIUM_4_ITLB_ESCR0, Msr);\r
1739 @endcode\r
1740**/\r
1741#define MSR_PENTIUM_4_ITLB_ESCR0 0x000003B6\r
1742\r
1743\r
1744/**\r
1745 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".\r
1746\r
1747 @param ECX MSR_PENTIUM_4_ITLB_ESCR1 (0x000003B7)\r
1748 @param EAX Lower 32-bits of MSR value.\r
1749 @param EDX Upper 32-bits of MSR value.\r
1750\r
1751 <b>Example usage</b>\r
1752 @code\r
1753 UINT64 Msr;\r
1754\r
1755 Msr = AsmReadMsr64 (MSR_PENTIUM_4_ITLB_ESCR1);\r
1756 AsmWriteMsr64 (MSR_PENTIUM_4_ITLB_ESCR1, Msr);\r
1757 @endcode\r
1758**/\r
1759#define MSR_PENTIUM_4_ITLB_ESCR1 0x000003B7\r
1760\r
1761\r
1762/**\r
1763 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".\r
1764\r
1765 @param ECX MSR_PENTIUM_4_CRU_ESCR0 (0x000003B8)\r
1766 @param EAX Lower 32-bits of MSR value.\r
1767 @param EDX Upper 32-bits of MSR value.\r
1768\r
1769 <b>Example usage</b>\r
1770 @code\r
1771 UINT64 Msr;\r
1772\r
1773 Msr = AsmReadMsr64 (MSR_PENTIUM_4_CRU_ESCR0);\r
1774 AsmWriteMsr64 (MSR_PENTIUM_4_CRU_ESCR0, Msr);\r
1775 @endcode\r
1776**/\r
1777#define MSR_PENTIUM_4_CRU_ESCR0 0x000003B8\r
1778\r
1779\r
1780/**\r
1781 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".\r
1782\r
1783 @param ECX MSR_PENTIUM_4_CRU_ESCR1 (0x000003B9)\r
1784 @param EAX Lower 32-bits of MSR value.\r
1785 @param EDX Upper 32-bits of MSR value.\r
1786\r
1787 <b>Example usage</b>\r
1788 @code\r
1789 UINT64 Msr;\r
1790\r
1791 Msr = AsmReadMsr64 (MSR_PENTIUM_4_CRU_ESCR1);\r
1792 AsmWriteMsr64 (MSR_PENTIUM_4_CRU_ESCR1, Msr);\r
1793 @endcode\r
1794**/\r
1795#define MSR_PENTIUM_4_CRU_ESCR1 0x000003B9\r
1796\r
1797\r
1798/**\r
1799 0, 1, 2. Shared. See Section 18.12.1, "ESCR MSRs." This MSR is not available\r
1800 on later processors. It is only available on processor family 0FH, models\r
1801 01H-02H.\r
1802\r
1803 @param ECX MSR_PENTIUM_4_IQ_ESCR0 (0x000003BA)\r
1804 @param EAX Lower 32-bits of MSR value.\r
1805 @param EDX Upper 32-bits of MSR value.\r
1806\r
1807 <b>Example usage</b>\r
1808 @code\r
1809 UINT64 Msr;\r
1810\r
1811 Msr = AsmReadMsr64 (MSR_PENTIUM_4_IQ_ESCR0);\r
1812 AsmWriteMsr64 (MSR_PENTIUM_4_IQ_ESCR0, Msr);\r
1813 @endcode\r
1814**/\r
1815#define MSR_PENTIUM_4_IQ_ESCR0 0x000003BA\r
1816\r
1817\r
1818/**\r
1819 0, 1, 2. Shared. See Section 18.12.1, "ESCR MSRs." This MSR is not available\r
1820 on later processors. It is only available on processor family 0FH, models\r
1821 01H-02H.\r
1822\r
1823 @param ECX MSR_PENTIUM_4_IQ_ESCR1 (0x000003BB)\r
1824 @param EAX Lower 32-bits of MSR value.\r
1825 @param EDX Upper 32-bits of MSR value.\r
1826\r
1827 <b>Example usage</b>\r
1828 @code\r
1829 UINT64 Msr;\r
1830\r
1831 Msr = AsmReadMsr64 (MSR_PENTIUM_4_IQ_ESCR1);\r
1832 AsmWriteMsr64 (MSR_PENTIUM_4_IQ_ESCR1, Msr);\r
1833 @endcode\r
1834**/\r
1835#define MSR_PENTIUM_4_IQ_ESCR1 0x000003BB\r
1836\r
1837\r
1838/**\r
1839 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".\r
1840\r
1841 @param ECX MSR_PENTIUM_4_RAT_ESCR0 (0x000003BC)\r
1842 @param EAX Lower 32-bits of MSR value.\r
1843 @param EDX Upper 32-bits of MSR value.\r
1844\r
1845 <b>Example usage</b>\r
1846 @code\r
1847 UINT64 Msr;\r
1848\r
1849 Msr = AsmReadMsr64 (MSR_PENTIUM_4_RAT_ESCR0);\r
1850 AsmWriteMsr64 (MSR_PENTIUM_4_RAT_ESCR0, Msr);\r
1851 @endcode\r
1852**/\r
1853#define MSR_PENTIUM_4_RAT_ESCR0 0x000003BC\r
1854\r
1855\r
1856/**\r
1857 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".\r
1858\r
1859 @param ECX MSR_PENTIUM_4_RAT_ESCR1 (0x000003BD)\r
1860 @param EAX Lower 32-bits of MSR value.\r
1861 @param EDX Upper 32-bits of MSR value.\r
1862\r
1863 <b>Example usage</b>\r
1864 @code\r
1865 UINT64 Msr;\r
1866\r
1867 Msr = AsmReadMsr64 (MSR_PENTIUM_4_RAT_ESCR1);\r
1868 AsmWriteMsr64 (MSR_PENTIUM_4_RAT_ESCR1, Msr);\r
1869 @endcode\r
1870**/\r
1871#define MSR_PENTIUM_4_RAT_ESCR1 0x000003BD\r
1872\r
1873\r
1874/**\r
1875 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".\r
1876\r
1877 @param ECX MSR_PENTIUM_4_SSU_ESCR0 (0x000003BE)\r
1878 @param EAX Lower 32-bits of MSR value.\r
1879 @param EDX Upper 32-bits of MSR value.\r
1880\r
1881 <b>Example usage</b>\r
1882 @code\r
1883 UINT64 Msr;\r
1884\r
1885 Msr = AsmReadMsr64 (MSR_PENTIUM_4_SSU_ESCR0);\r
1886 AsmWriteMsr64 (MSR_PENTIUM_4_SSU_ESCR0, Msr);\r
1887 @endcode\r
1888**/\r
1889#define MSR_PENTIUM_4_SSU_ESCR0 0x000003BE\r
1890\r
1891\r
1892/**\r
1893 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".\r
1894\r
1895 @param ECX MSR_PENTIUM_4_MS_ESCR0 (0x000003C0)\r
1896 @param EAX Lower 32-bits of MSR value.\r
1897 @param EDX Upper 32-bits of MSR value.\r
1898\r
1899 <b>Example usage</b>\r
1900 @code\r
1901 UINT64 Msr;\r
1902\r
1903 Msr = AsmReadMsr64 (MSR_PENTIUM_4_MS_ESCR0);\r
1904 AsmWriteMsr64 (MSR_PENTIUM_4_MS_ESCR0, Msr);\r
1905 @endcode\r
1906**/\r
1907#define MSR_PENTIUM_4_MS_ESCR0 0x000003C0\r
1908\r
1909\r
1910/**\r
1911 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".\r
1912\r
1913 @param ECX MSR_PENTIUM_4_MS_ESCR1 (0x000003C1)\r
1914 @param EAX Lower 32-bits of MSR value.\r
1915 @param EDX Upper 32-bits of MSR value.\r
1916\r
1917 <b>Example usage</b>\r
1918 @code\r
1919 UINT64 Msr;\r
1920\r
1921 Msr = AsmReadMsr64 (MSR_PENTIUM_4_MS_ESCR1);\r
1922 AsmWriteMsr64 (MSR_PENTIUM_4_MS_ESCR1, Msr);\r
1923 @endcode\r
1924**/\r
1925#define MSR_PENTIUM_4_MS_ESCR1 0x000003C1\r
1926\r
1927\r
1928/**\r
1929 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".\r
1930\r
1931 @param ECX MSR_PENTIUM_4_TBPU_ESCR0 (0x000003C2)\r
1932 @param EAX Lower 32-bits of MSR value.\r
1933 @param EDX Upper 32-bits of MSR value.\r
1934\r
1935 <b>Example usage</b>\r
1936 @code\r
1937 UINT64 Msr;\r
1938\r
1939 Msr = AsmReadMsr64 (MSR_PENTIUM_4_TBPU_ESCR0);\r
1940 AsmWriteMsr64 (MSR_PENTIUM_4_TBPU_ESCR0, Msr);\r
1941 @endcode\r
1942**/\r
1943#define MSR_PENTIUM_4_TBPU_ESCR0 0x000003C2\r
1944\r
1945\r
1946/**\r
1947 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".\r
1948\r
1949 @param ECX MSR_PENTIUM_4_TBPU_ESCR1 (0x000003C3)\r
1950 @param EAX Lower 32-bits of MSR value.\r
1951 @param EDX Upper 32-bits of MSR value.\r
1952\r
1953 <b>Example usage</b>\r
1954 @code\r
1955 UINT64 Msr;\r
1956\r
1957 Msr = AsmReadMsr64 (MSR_PENTIUM_4_TBPU_ESCR1);\r
1958 AsmWriteMsr64 (MSR_PENTIUM_4_TBPU_ESCR1, Msr);\r
1959 @endcode\r
1960**/\r
1961#define MSR_PENTIUM_4_TBPU_ESCR1 0x000003C3\r
1962\r
1963\r
1964/**\r
1965 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".\r
1966\r
1967 @param ECX MSR_PENTIUM_4_TC_ESCR0 (0x000003C4)\r
1968 @param EAX Lower 32-bits of MSR value.\r
1969 @param EDX Upper 32-bits of MSR value.\r
1970\r
1971 <b>Example usage</b>\r
1972 @code\r
1973 UINT64 Msr;\r
1974\r
1975 Msr = AsmReadMsr64 (MSR_PENTIUM_4_TC_ESCR0);\r
1976 AsmWriteMsr64 (MSR_PENTIUM_4_TC_ESCR0, Msr);\r
1977 @endcode\r
1978**/\r
1979#define MSR_PENTIUM_4_TC_ESCR0 0x000003C4\r
1980\r
1981\r
1982/**\r
1983 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".\r
1984\r
1985 @param ECX MSR_PENTIUM_4_TC_ESCR1 (0x000003C5)\r
1986 @param EAX Lower 32-bits of MSR value.\r
1987 @param EDX Upper 32-bits of MSR value.\r
1988\r
1989 <b>Example usage</b>\r
1990 @code\r
1991 UINT64 Msr;\r
1992\r
1993 Msr = AsmReadMsr64 (MSR_PENTIUM_4_TC_ESCR1);\r
1994 AsmWriteMsr64 (MSR_PENTIUM_4_TC_ESCR1, Msr);\r
1995 @endcode\r
1996**/\r
1997#define MSR_PENTIUM_4_TC_ESCR1 0x000003C5\r
1998\r
1999\r
2000/**\r
2001 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".\r
2002\r
2003 @param ECX MSR_PENTIUM_4_IX_ESCR0 (0x000003C8)\r
2004 @param EAX Lower 32-bits of MSR value.\r
2005 @param EDX Upper 32-bits of MSR value.\r
2006\r
2007 <b>Example usage</b>\r
2008 @code\r
2009 UINT64 Msr;\r
2010\r
2011 Msr = AsmReadMsr64 (MSR_PENTIUM_4_IX_ESCR0);\r
2012 AsmWriteMsr64 (MSR_PENTIUM_4_IX_ESCR0, Msr);\r
2013 @endcode\r
2014**/\r
2015#define MSR_PENTIUM_4_IX_ESCR0 0x000003C8\r
2016\r
2017\r
2018/**\r
2019 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".\r
2020\r
2021 @param ECX MSR_PENTIUM_4_IX_ESCR1 (0x000003C9)\r
2022 @param EAX Lower 32-bits of MSR value.\r
2023 @param EDX Upper 32-bits of MSR value.\r
2024\r
2025 <b>Example usage</b>\r
2026 @code\r
2027 UINT64 Msr;\r
2028\r
2029 Msr = AsmReadMsr64 (MSR_PENTIUM_4_IX_ESCR1);\r
2030 AsmWriteMsr64 (MSR_PENTIUM_4_IX_ESCR1, Msr);\r
2031 @endcode\r
2032**/\r
2033#define MSR_PENTIUM_4_IX_ESCR1 0x000003C9\r
2034\r
2035\r
2036/**\r
2037 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".\r
2038\r
2039 @param ECX MSR_PENTIUM_4_ALF_ESCRn\r
2040 @param EAX Lower 32-bits of MSR value.\r
2041 @param EDX Upper 32-bits of MSR value.\r
2042\r
2043 <b>Example usage</b>\r
2044 @code\r
2045 UINT64 Msr;\r
2046\r
2047 Msr = AsmReadMsr64 (MSR_PENTIUM_4_ALF_ESCR0);\r
2048 AsmWriteMsr64 (MSR_PENTIUM_4_ALF_ESCR0, Msr);\r
2049 @endcode\r
2050 @{\r
2051**/\r
2052#define MSR_PENTIUM_4_ALF_ESCR0 0x000003CA\r
2053#define MSR_PENTIUM_4_ALF_ESCR1 0x000003CB\r
2054#define MSR_PENTIUM_4_CRU_ESCR2 0x000003CC\r
2055#define MSR_PENTIUM_4_CRU_ESCR3 0x000003CD\r
2056#define MSR_PENTIUM_4_CRU_ESCR4 0x000003E0\r
2057#define MSR_PENTIUM_4_CRU_ESCR5 0x000003E1\r
2058/// @}\r
2059\r
2060\r
2061/**\r
2062 0, 1, 2, 3, 4, 6. Shared. See Section 18.12.1, "ESCR MSRs.".\r
2063\r
2064 @param ECX MSR_PENTIUM_4_TC_PRECISE_EVENT (0x000003F0)\r
2065 @param EAX Lower 32-bits of MSR value.\r
2066 @param EDX Upper 32-bits of MSR value.\r
2067\r
2068 <b>Example usage</b>\r
2069 @code\r
2070 UINT64 Msr;\r
2071\r
2072 Msr = AsmReadMsr64 (MSR_PENTIUM_4_TC_PRECISE_EVENT);\r
2073 AsmWriteMsr64 (MSR_PENTIUM_4_TC_PRECISE_EVENT, Msr);\r
2074 @endcode\r
2075**/\r
2076#define MSR_PENTIUM_4_TC_PRECISE_EVENT 0x000003F0\r
2077\r
2078\r
2079/**\r
2080 0, 1, 2, 3, 4, 6. Shared. Precise Event-Based Sampling (PEBS) (R/W)\r
2081 Controls the enabling of precise event sampling and replay tagging.\r
2082\r
2083 @param ECX MSR_PENTIUM_4_PEBS_ENABLE (0x000003F1)\r
2084 @param EAX Lower 32-bits of MSR value.\r
2085 Described by the type MSR_PENTIUM_4_PEBS_ENABLE_REGISTER.\r
2086 @param EDX Upper 32-bits of MSR value.\r
2087 Described by the type MSR_PENTIUM_4_PEBS_ENABLE_REGISTER.\r
2088\r
2089 <b>Example usage</b>\r
2090 @code\r
2091 MSR_PENTIUM_4_PEBS_ENABLE_REGISTER Msr;\r
2092\r
2093 Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_4_PEBS_ENABLE);\r
2094 AsmWriteMsr64 (MSR_PENTIUM_4_PEBS_ENABLE, Msr.Uint64);\r
2095 @endcode\r
2096**/\r
2097#define MSR_PENTIUM_4_PEBS_ENABLE 0x000003F1\r
2098\r
2099/**\r
2100 MSR information returned for MSR index #MSR_PENTIUM_4_PEBS_ENABLE\r
2101**/\r
2102typedef union {\r
2103 ///\r
2104 /// Individual bit fields\r
2105 ///\r
2106 struct {\r
2107 ///\r
2108 /// [Bits 12:0] See Table 19-26.\r
2109 ///\r
2110 UINT32 EventNum:13;\r
2111 UINT32 Reserved1:11;\r
2112 ///\r
2113 /// [Bit 24] UOP Tag Enables replay tagging when set.\r
2114 ///\r
2115 UINT32 UOP:1;\r
2116 ///\r
2117 /// [Bit 25] ENABLE_PEBS_MY_THR (R/W) Enables PEBS for the target logical\r
2118 /// processor when set; disables PEBS when clear (default). See Section\r
2119 /// 18.13.3, "IA32_PEBS_ENABLE MSR," for an explanation of the target\r
2120 /// logical processor. This bit is called ENABLE_PEBS in IA-32 processors\r
2121 /// that do not support Intel HyperThreading Technology.\r
2122 ///\r
2123 UINT32 ENABLE_PEBS_MY_THR:1;\r
2124 ///\r
2125 /// [Bit 26] ENABLE_PEBS_OTH_THR (R/W) Enables PEBS for the target logical\r
2126 /// processor when set; disables PEBS when clear (default). See Section\r
2127 /// 18.13.3, "IA32_PEBS_ENABLE MSR," for an explanation of the target\r
2128 /// logical processor. This bit is reserved for IA-32 processors that do\r
2129 /// not support Intel Hyper-Threading Technology.\r
2130 ///\r
2131 UINT32 ENABLE_PEBS_OTH_THR:1;\r
2132 UINT32 Reserved2:5;\r
2133 UINT32 Reserved3:32;\r
2134 } Bits;\r
2135 ///\r
2136 /// All bit fields as a 32-bit value\r
2137 ///\r
2138 UINT32 Uint32;\r
2139 ///\r
2140 /// All bit fields as a 64-bit value\r
2141 ///\r
2142 UINT64 Uint64;\r
2143} MSR_PENTIUM_4_PEBS_ENABLE_REGISTER;\r
2144\r
2145\r
2146/**\r
2147 0, 1, 2, 3, 4, 6. Shared. See Table 19-26.\r
2148\r
2149 @param ECX MSR_PENTIUM_4_PEBS_MATRIX_VERT (0x000003F2)\r
2150 @param EAX Lower 32-bits of MSR value.\r
2151 @param EDX Upper 32-bits of MSR value.\r
2152\r
2153 <b>Example usage</b>\r
2154 @code\r
2155 UINT64 Msr;\r
2156\r
2157 Msr = AsmReadMsr64 (MSR_PENTIUM_4_PEBS_MATRIX_VERT);\r
2158 AsmWriteMsr64 (MSR_PENTIUM_4_PEBS_MATRIX_VERT, Msr);\r
2159 @endcode\r
2160**/\r
2161#define MSR_PENTIUM_4_PEBS_MATRIX_VERT 0x000003F2\r
2162\r
2163\r
2164/**\r
2165 3, 4, 6. Unique. Last Branch Record n (R/W) One of 16 pairs of last branch\r
2166 record registers on the last branch record stack (680H-68FH). This part of\r
2167 the stack contains pointers to the source instruction for one of the last 16\r
2168 branches, exceptions, or interrupts taken by the processor. The MSRs at\r
2169 680H-68FH, 6C0H-6CfH are not available in processor releases before family\r
2170 0FH, model 03H. These MSRs replace MSRs previously located at\r
2171 1DBH-1DEH.which performed the same function for early releases. See Section\r
2172 17.9, "Last Branch, Call Stack, Interrupt, and Exception Recording for\r
2173 Processors based on Skylake Microarchitecture.".\r
2174\r
2175 @param ECX MSR_PENTIUM_4_LASTBRANCH_n_FROM_IP\r
2176 @param EAX Lower 32-bits of MSR value.\r
2177 @param EDX Upper 32-bits of MSR value.\r
2178\r
2179 <b>Example usage</b>\r
2180 @code\r
2181 UINT64 Msr;\r
2182\r
2183 Msr = AsmReadMsr64 (MSR_PENTIUM_4_LASTBRANCH_0_FROM_IP);\r
2184 AsmWriteMsr64 (MSR_PENTIUM_4_LASTBRANCH_0_FROM_IP, Msr);\r
2185 @endcode\r
2186 @{\r
2187**/\r
2188#define MSR_PENTIUM_4_LASTBRANCH_0_FROM_IP 0x00000680\r
2189#define MSR_PENTIUM_4_LASTBRANCH_1_FROM_IP 0x00000681\r
2190#define MSR_PENTIUM_4_LASTBRANCH_2_FROM_IP 0x00000682\r
2191#define MSR_PENTIUM_4_LASTBRANCH_3_FROM_IP 0x00000683\r
2192#define MSR_PENTIUM_4_LASTBRANCH_4_FROM_IP 0x00000684\r
2193#define MSR_PENTIUM_4_LASTBRANCH_5_FROM_IP 0x00000685\r
2194#define MSR_PENTIUM_4_LASTBRANCH_6_FROM_IP 0x00000686\r
2195#define MSR_PENTIUM_4_LASTBRANCH_7_FROM_IP 0x00000687\r
2196#define MSR_PENTIUM_4_LASTBRANCH_8_FROM_IP 0x00000688\r
2197#define MSR_PENTIUM_4_LASTBRANCH_9_FROM_IP 0x00000689\r
2198#define MSR_PENTIUM_4_LASTBRANCH_10_FROM_IP 0x0000068A\r
2199#define MSR_PENTIUM_4_LASTBRANCH_11_FROM_IP 0x0000068B\r
2200#define MSR_PENTIUM_4_LASTBRANCH_12_FROM_IP 0x0000068C\r
2201#define MSR_PENTIUM_4_LASTBRANCH_13_FROM_IP 0x0000068D\r
2202#define MSR_PENTIUM_4_LASTBRANCH_14_FROM_IP 0x0000068E\r
2203#define MSR_PENTIUM_4_LASTBRANCH_15_FROM_IP 0x0000068F\r
2204/// @}\r
2205\r
2206\r
2207/**\r
2208 3, 4, 6. Unique. Last Branch Record n (R/W) One of 16 pairs of last branch\r
2209 record registers on the last branch record stack (6C0H-6CFH). This part of\r
2210 the stack contains pointers to the destination instruction for one of the\r
2211 last 16 branches, exceptions, or interrupts that the processor took. See\r
2212 Section 17.9, "Last Branch, Call Stack, Interrupt, and Exception Recording\r
2213 for Processors based on Skylake Microarchitecture.".\r
2214\r
2215 @param ECX MSR_PENTIUM_4_LASTBRANCH_n_TO_IP\r
2216 @param EAX Lower 32-bits of MSR value.\r
2217 @param EDX Upper 32-bits of MSR value.\r
2218\r
2219 <b>Example usage</b>\r
2220 @code\r
2221 UINT64 Msr;\r
2222\r
2223 Msr = AsmReadMsr64 (MSR_PENTIUM_4_LASTBRANCH_0_TO_IP);\r
2224 AsmWriteMsr64 (MSR_PENTIUM_4_LASTBRANCH_0_TO_IP, Msr);\r
2225 @endcode\r
2226 @{\r
2227**/\r
2228#define MSR_PENTIUM_4_LASTBRANCH_0_TO_IP 0x000006C0\r
2229#define MSR_PENTIUM_4_LASTBRANCH_1_TO_IP 0x000006C1\r
2230#define MSR_PENTIUM_4_LASTBRANCH_2_TO_IP 0x000006C2\r
2231#define MSR_PENTIUM_4_LASTBRANCH_3_TO_IP 0x000006C3\r
2232#define MSR_PENTIUM_4_LASTBRANCH_4_TO_IP 0x000006C4\r
2233#define MSR_PENTIUM_4_LASTBRANCH_5_TO_IP 0x000006C5\r
2234#define MSR_PENTIUM_4_LASTBRANCH_6_TO_IP 0x000006C6\r
2235#define MSR_PENTIUM_4_LASTBRANCH_7_TO_IP 0x000006C7\r
2236#define MSR_PENTIUM_4_LASTBRANCH_8_TO_IP 0x000006C8\r
2237#define MSR_PENTIUM_4_LASTBRANCH_9_TO_IP 0x000006C9\r
2238#define MSR_PENTIUM_4_LASTBRANCH_10_TO_IP 0x000006CA\r
2239#define MSR_PENTIUM_4_LASTBRANCH_11_TO_IP 0x000006CB\r
2240#define MSR_PENTIUM_4_LASTBRANCH_12_TO_IP 0x000006CC\r
2241#define MSR_PENTIUM_4_LASTBRANCH_13_TO_IP 0x000006CD\r
2242#define MSR_PENTIUM_4_LASTBRANCH_14_TO_IP 0x000006CE\r
2243#define MSR_PENTIUM_4_LASTBRANCH_15_TO_IP 0x000006CF\r
2244/// @}\r
2245\r
2246\r
2247/**\r
2248 3, 4. Shared. IFSB BUSQ Event Control and Counter Register (R/W) See\r
2249 Section 18.17, "Performance Monitoring on 64-bit Intel Xeon Processor MP\r
2250 with Up to 8-MByte L3 Cache.".\r
2251\r
2252 @param ECX MSR_PENTIUM_4_IFSB_BUSQ0 (0x000107CC)\r
2253 @param EAX Lower 32-bits of MSR value.\r
2254 @param EDX Upper 32-bits of MSR value.\r
2255\r
2256 <b>Example usage</b>\r
2257 @code\r
2258 UINT64 Msr;\r
2259\r
2260 Msr = AsmReadMsr64 (MSR_PENTIUM_4_IFSB_BUSQ0);\r
2261 AsmWriteMsr64 (MSR_PENTIUM_4_IFSB_BUSQ0, Msr);\r
2262 @endcode\r
2263**/\r
2264#define MSR_PENTIUM_4_IFSB_BUSQ0 0x000107CC\r
2265\r
2266\r
2267/**\r
2268 3, 4. Shared. IFSB BUSQ Event Control and Counter Register (R/W).\r
2269\r
2270 @param ECX MSR_PENTIUM_4_IFSB_BUSQ1 (0x000107CD)\r
2271 @param EAX Lower 32-bits of MSR value.\r
2272 @param EDX Upper 32-bits of MSR value.\r
2273\r
2274 <b>Example usage</b>\r
2275 @code\r
2276 UINT64 Msr;\r
2277\r
2278 Msr = AsmReadMsr64 (MSR_PENTIUM_4_IFSB_BUSQ1);\r
2279 AsmWriteMsr64 (MSR_PENTIUM_4_IFSB_BUSQ1, Msr);\r
2280 @endcode\r
2281**/\r
2282#define MSR_PENTIUM_4_IFSB_BUSQ1 0x000107CD\r
2283\r
2284\r
2285/**\r
2286 3, 4. Shared. IFSB SNPQ Event Control and Counter Register (R/W) See\r
2287 Section 18.17, "Performance Monitoring on 64-bit Intel Xeon Processor MP\r
2288 with Up to 8-MByte L3 Cache.".\r
2289\r
2290 @param ECX MSR_PENTIUM_4_IFSB_SNPQ0 (0x000107CE)\r
2291 @param EAX Lower 32-bits of MSR value.\r
2292 @param EDX Upper 32-bits of MSR value.\r
2293\r
2294 <b>Example usage</b>\r
2295 @code\r
2296 UINT64 Msr;\r
2297\r
2298 Msr = AsmReadMsr64 (MSR_PENTIUM_4_IFSB_SNPQ0);\r
2299 AsmWriteMsr64 (MSR_PENTIUM_4_IFSB_SNPQ0, Msr);\r
2300 @endcode\r
2301**/\r
2302#define MSR_PENTIUM_4_IFSB_SNPQ0 0x000107CE\r
2303\r
2304\r
2305/**\r
2306 3, 4. Shared. IFSB SNPQ Event Control and Counter Register (R/W).\r
2307\r
2308 @param ECX MSR_PENTIUM_4_IFSB_SNPQ1 (0x000107CF)\r
2309 @param EAX Lower 32-bits of MSR value.\r
2310 @param EDX Upper 32-bits of MSR value.\r
2311\r
2312 <b>Example usage</b>\r
2313 @code\r
2314 UINT64 Msr;\r
2315\r
2316 Msr = AsmReadMsr64 (MSR_PENTIUM_4_IFSB_SNPQ1);\r
2317 AsmWriteMsr64 (MSR_PENTIUM_4_IFSB_SNPQ1, Msr);\r
2318 @endcode\r
2319**/\r
2320#define MSR_PENTIUM_4_IFSB_SNPQ1 0x000107CF\r
2321\r
2322\r
2323/**\r
2324 3, 4. Shared. EFSB DRDY Event Control and Counter Register (R/W) See\r
2325 Section 18.17, "Performance Monitoring on 64-bit Intel Xeon Processor MP\r
2326 with Up to 8-MByte L3 Cache" for details.\r
2327\r
2328 @param ECX MSR_PENTIUM_4_EFSB_DRDY0 (0x000107D0)\r
2329 @param EAX Lower 32-bits of MSR value.\r
2330 @param EDX Upper 32-bits of MSR value.\r
2331\r
2332 <b>Example usage</b>\r
2333 @code\r
2334 UINT64 Msr;\r
2335\r
2336 Msr = AsmReadMsr64 (MSR_PENTIUM_4_EFSB_DRDY0);\r
2337 AsmWriteMsr64 (MSR_PENTIUM_4_EFSB_DRDY0, Msr);\r
2338 @endcode\r
2339**/\r
2340#define MSR_PENTIUM_4_EFSB_DRDY0 0x000107D0\r
2341\r
2342\r
2343/**\r
2344 3, 4. Shared. EFSB DRDY Event Control and Counter Register (R/W).\r
2345\r
2346 @param ECX MSR_PENTIUM_4_EFSB_DRDY1 (0x000107D1)\r
2347 @param EAX Lower 32-bits of MSR value.\r
2348 @param EDX Upper 32-bits of MSR value.\r
2349\r
2350 <b>Example usage</b>\r
2351 @code\r
2352 UINT64 Msr;\r
2353\r
2354 Msr = AsmReadMsr64 (MSR_PENTIUM_4_EFSB_DRDY1);\r
2355 AsmWriteMsr64 (MSR_PENTIUM_4_EFSB_DRDY1, Msr);\r
2356 @endcode\r
2357**/\r
2358#define MSR_PENTIUM_4_EFSB_DRDY1 0x000107D1\r
2359\r
2360\r
2361/**\r
2362 3, 4. Shared. IFSB Latency Event Control Register (R/W) See Section 18.17,\r
2363 "Performance Monitoring on 64-bit Intel Xeon Processor MP with Up to 8-MByte\r
2364 L3 Cache" for details.\r
2365\r
2366 @param ECX MSR_PENTIUM_4_IFSB_CTL6 (0x000107D2)\r
2367 @param EAX Lower 32-bits of MSR value.\r
2368 @param EDX Upper 32-bits of MSR value.\r
2369\r
2370 <b>Example usage</b>\r
2371 @code\r
2372 UINT64 Msr;\r
2373\r
2374 Msr = AsmReadMsr64 (MSR_PENTIUM_4_IFSB_CTL6);\r
2375 AsmWriteMsr64 (MSR_PENTIUM_4_IFSB_CTL6, Msr);\r
2376 @endcode\r
2377**/\r
2378#define MSR_PENTIUM_4_IFSB_CTL6 0x000107D2\r
2379\r
2380\r
2381/**\r
2382 3, 4. Shared. IFSB Latency Event Counter Register (R/W) See Section 18.17,\r
2383 "Performance Monitoring on 64-bit Intel Xeon Processor MP with Up to 8-MByte\r
2384 L3 Cache.".\r
2385\r
2386 @param ECX MSR_PENTIUM_4_IFSB_CNTR7 (0x000107D3)\r
2387 @param EAX Lower 32-bits of MSR value.\r
2388 @param EDX Upper 32-bits of MSR value.\r
2389\r
2390 <b>Example usage</b>\r
2391 @code\r
2392 UINT64 Msr;\r
2393\r
2394 Msr = AsmReadMsr64 (MSR_PENTIUM_4_IFSB_CNTR7);\r
2395 AsmWriteMsr64 (MSR_PENTIUM_4_IFSB_CNTR7, Msr);\r
2396 @endcode\r
2397**/\r
2398#define MSR_PENTIUM_4_IFSB_CNTR7 0x000107D3\r
2399\r
2400\r
2401/**\r
2402 6. Shared. GBUSQ Event Control and Counter Register (R/W) See Section 18.17,\r
2403 "Performance Monitoring on 64-bit Intel Xeon Processor MP with Up to 8-MByte\r
2404 L3 Cache.".\r
2405\r
2406 @param ECX MSR_PENTIUM_4_EMON_L3_CTR_CTL0 (0x000107CC)\r
2407 @param EAX Lower 32-bits of MSR value.\r
2408 @param EDX Upper 32-bits of MSR value.\r
2409\r
2410 <b>Example usage</b>\r
2411 @code\r
2412 UINT64 Msr;\r
2413\r
2414 Msr = AsmReadMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL0);\r
2415 AsmWriteMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL0, Msr);\r
2416 @endcode\r
2417**/\r
2418#define MSR_PENTIUM_4_EMON_L3_CTR_CTL0 0x000107CC\r
2419\r
2420\r
2421/**\r
2422 6. Shared. GBUSQ Event Control and Counter Register (R/W).\r
2423\r
2424 @param ECX MSR_PENTIUM_4_EMON_L3_CTR_CTL1 (0x000107CD)\r
2425 @param EAX Lower 32-bits of MSR value.\r
2426 @param EDX Upper 32-bits of MSR value.\r
2427\r
2428 <b>Example usage</b>\r
2429 @code\r
2430 UINT64 Msr;\r
2431\r
2432 Msr = AsmReadMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL1);\r
2433 AsmWriteMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL1, Msr);\r
2434 @endcode\r
2435**/\r
2436#define MSR_PENTIUM_4_EMON_L3_CTR_CTL1 0x000107CD\r
2437\r
2438\r
2439/**\r
2440 6. Shared. GSNPQ Event Control and Counter Register (R/W) See Section\r
2441 18.17, "Performance Monitoring on 64-bit Intel Xeon Processor MP with Up to\r
2442 8-MByte L3 Cache.".\r
2443\r
2444 @param ECX MSR_PENTIUM_4_EMON_L3_CTR_CTL2 (0x000107CE)\r
2445 @param EAX Lower 32-bits of MSR value.\r
2446 @param EDX Upper 32-bits of MSR value.\r
2447\r
2448 <b>Example usage</b>\r
2449 @code\r
2450 UINT64 Msr;\r
2451\r
2452 Msr = AsmReadMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL2);\r
2453 AsmWriteMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL2, Msr);\r
2454 @endcode\r
2455**/\r
2456#define MSR_PENTIUM_4_EMON_L3_CTR_CTL2 0x000107CE\r
2457\r
2458\r
2459/**\r
2460 6. Shared. GSNPQ Event Control and Counter Register (R/W).\r
2461\r
2462 @param ECX MSR_PENTIUM_4_EMON_L3_CTR_CTL3 (0x000107CF)\r
2463 @param EAX Lower 32-bits of MSR value.\r
2464 @param EDX Upper 32-bits of MSR value.\r
2465\r
2466 <b>Example usage</b>\r
2467 @code\r
2468 UINT64 Msr;\r
2469\r
2470 Msr = AsmReadMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL3);\r
2471 AsmWriteMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL3, Msr);\r
2472 @endcode\r
2473**/\r
2474#define MSR_PENTIUM_4_EMON_L3_CTR_CTL3 0x000107CF\r
2475\r
2476\r
2477/**\r
2478 6. Shared. FSB Event Control and Counter Register (R/W) See Section 18.17,\r
2479 "Performance Monitoring on 64-bit Intel Xeon Processor MP with Up to 8-MByte\r
2480 L3 Cache" for details.\r
2481\r
2482 @param ECX MSR_PENTIUM_4_EMON_L3_CTR_CTL4 (0x000107D0)\r
2483 @param EAX Lower 32-bits of MSR value.\r
2484 @param EDX Upper 32-bits of MSR value.\r
2485\r
2486 <b>Example usage</b>\r
2487 @code\r
2488 UINT64 Msr;\r
2489\r
2490 Msr = AsmReadMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL4);\r
2491 AsmWriteMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL4, Msr);\r
2492 @endcode\r
2493**/\r
2494#define MSR_PENTIUM_4_EMON_L3_CTR_CTL4 0x000107D0\r
2495\r
2496\r
2497/**\r
2498 6. Shared. FSB Event Control and Counter Register (R/W).\r
2499\r
2500 @param ECX MSR_PENTIUM_4_EMON_L3_CTR_CTL5 (0x000107D1)\r
2501 @param EAX Lower 32-bits of MSR value.\r
2502 @param EDX Upper 32-bits of MSR value.\r
2503\r
2504 <b>Example usage</b>\r
2505 @code\r
2506 UINT64 Msr;\r
2507\r
2508 Msr = AsmReadMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL5);\r
2509 AsmWriteMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL5, Msr);\r
2510 @endcode\r
2511**/\r
2512#define MSR_PENTIUM_4_EMON_L3_CTR_CTL5 0x000107D1\r
2513\r
2514\r
2515/**\r
2516 6. Shared. FSB Event Control and Counter Register (R/W).\r
2517\r
2518 @param ECX MSR_PENTIUM_4_EMON_L3_CTR_CTL6 (0x000107D2)\r
2519 @param EAX Lower 32-bits of MSR value.\r
2520 @param EDX Upper 32-bits of MSR value.\r
2521\r
2522 <b>Example usage</b>\r
2523 @code\r
2524 UINT64 Msr;\r
2525\r
2526 Msr = AsmReadMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL6);\r
2527 AsmWriteMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL6, Msr);\r
2528 @endcode\r
2529**/\r
2530#define MSR_PENTIUM_4_EMON_L3_CTR_CTL6 0x000107D2\r
2531\r
2532\r
2533/**\r
2534 6. Shared. FSB Event Control and Counter Register (R/W).\r
2535\r
2536 @param ECX MSR_PENTIUM_4_EMON_L3_CTR_CTL7 (0x000107D3)\r
2537 @param EAX Lower 32-bits of MSR value.\r
2538 @param EDX Upper 32-bits of MSR value.\r
2539\r
2540 <b>Example usage</b>\r
2541 @code\r
2542 UINT64 Msr;\r
2543\r
2544 Msr = AsmReadMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL7);\r
2545 AsmWriteMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL7, Msr);\r
2546 @endcode\r
2547**/\r
2548#define MSR_PENTIUM_4_EMON_L3_CTR_CTL7 0x000107D3\r
2549\r
2550#endif\r
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