Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_PLATFORM_INFO);\r
AsmWriteMsr64 (MSR_IVY_BRIDGE_PLATFORM_INFO, Msr.Uint64);\r
@endcode\r
+ @note MSR_IVY_BRIDGE_PLATFORM_INFO is defined as MSR_PLATFORM_INFO in SDM.\r
**/\r
#define MSR_IVY_BRIDGE_PLATFORM_INFO 0x000000CE\r
\r
Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL);\r
AsmWriteMsr64 (MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL, Msr.Uint64);\r
@endcode\r
+ @note MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM.\r
**/\r
#define MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL 0x000000E2\r
\r
\r
Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL);\r
@endcode\r
+ @note MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL is defined as MSR_CONFIG_TDP_NOMINAL in SDM.\r
**/\r
#define MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL 0x00000648\r
\r
\r
Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1);\r
@endcode\r
+ @note MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1 is defined as MSR_CONFIG_TDP_LEVEL1 in SDM.\r
**/\r
#define MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1 0x00000649\r
\r
\r
Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2);\r
@endcode\r
+ @note MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2 is defined as MSR_CONFIG_TDP_LEVEL2 in SDM.\r
**/\r
#define MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2 0x0000064A\r
\r
Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL);\r
AsmWriteMsr64 (MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL, Msr.Uint64);\r
@endcode\r
+ @note MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL is defined as MSR_CONFIG_TDP_CONTROL in SDM.\r
**/\r
#define MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL 0x0000064B\r
\r
Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO);\r
AsmWriteMsr64 (MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO, Msr.Uint64);\r
@endcode\r
+ @note MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO is defined as MSR_TURBO_ACTIVATION_RATIO in SDM.\r
**/\r
#define MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO 0x0000064C\r
\r
Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_PPIN_CTL);\r
AsmWriteMsr64 (MSR_IVY_BRIDGE_PPIN_CTL, Msr.Uint64);\r
@endcode\r
+ @note MSR_IVY_BRIDGE_PPIN_CTL is defined as MSR_PPIN_CTL in SDM.\r
**/\r
#define MSR_IVY_BRIDGE_PPIN_CTL 0x0000004E\r
\r
\r
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_PPIN);\r
@endcode\r
+ @note MSR_IVY_BRIDGE_PPIN is defined as MSR_PPIN in SDM.\r
**/\r
#define MSR_IVY_BRIDGE_PPIN 0x0000004F\r
\r
Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_PLATFORM_INFO_1);\r
AsmWriteMsr64 (MSR_IVY_BRIDGE_PLATFORM_INFO_1, Msr.Uint64);\r
@endcode\r
+ @note MSR_IVY_BRIDGE_PLATFORM_INFO_1 is defined as MSR_PLATFORM_INFO_1 in SDM.\r
**/\r
#define MSR_IVY_BRIDGE_PLATFORM_INFO_1 0x000000CE\r
\r
Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_ERROR_CONTROL);\r
AsmWriteMsr64 (MSR_IVY_BRIDGE_ERROR_CONTROL, Msr.Uint64);\r
@endcode\r
+ @note MSR_IVY_BRIDGE_ERROR_CONTROL is defined as MSR_ERROR_CONTROL in SDM.\r
**/\r
#define MSR_IVY_BRIDGE_ERROR_CONTROL 0x0000017F\r
\r
Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_TEMPERATURE_TARGET);\r
AsmWriteMsr64 (MSR_IVY_BRIDGE_TEMPERATURE_TARGET, Msr.Uint64);\r
@endcode\r
+ @note MSR_IVY_BRIDGE_TEMPERATURE_TARGET is defined as MSR_TEMPERATURE_TARGET in SDM.\r
**/\r
#define MSR_IVY_BRIDGE_TEMPERATURE_TARGET 0x000001A2\r
\r
\r
Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1);\r
@endcode\r
+ @note MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1 is defined as MSR_TURBO_RATIO_LIMIT1 in SDM.\r
**/\r
#define MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1 0x000001AE\r
\r
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_MC5_CTL);\r
AsmWriteMsr64 (MSR_IVY_BRIDGE_MC5_CTL, Msr);\r
@endcode\r
+ @note MSR_IVY_BRIDGE_MC5_CTL is defined as MSR_MC5_CTL in SDM.\r
+ MSR_IVY_BRIDGE_MC6_CTL is defined as MSR_MC6_CTL in SDM.\r
+ MSR_IVY_BRIDGE_MC7_CTL is defined as MSR_MC7_CTL in SDM.\r
+ MSR_IVY_BRIDGE_MC8_CTL is defined as MSR_MC8_CTL in SDM.\r
+ MSR_IVY_BRIDGE_MC9_CTL is defined as MSR_MC9_CTL in SDM.\r
+ MSR_IVY_BRIDGE_MC10_CTL is defined as MSR_MC10_CTL in SDM.\r
+ MSR_IVY_BRIDGE_MC11_CTL is defined as MSR_MC11_CTL in SDM.\r
+ MSR_IVY_BRIDGE_MC12_CTL is defined as MSR_MC12_CTL in SDM.\r
+ MSR_IVY_BRIDGE_MC13_CTL is defined as MSR_MC13_CTL in SDM.\r
+ MSR_IVY_BRIDGE_MC14_CTL is defined as MSR_MC14_CTL in SDM.\r
+ MSR_IVY_BRIDGE_MC15_CTL is defined as MSR_MC15_CTL in SDM.\r
+ MSR_IVY_BRIDGE_MC16_CTL is defined as MSR_MC16_CTL in SDM.\r
+ MSR_IVY_BRIDGE_MC17_CTL is defined as MSR_MC17_CTL in SDM.\r
+ MSR_IVY_BRIDGE_MC18_CTL is defined as MSR_MC18_CTL in SDM.\r
+ MSR_IVY_BRIDGE_MC19_CTL is defined as MSR_MC19_CTL in SDM.\r
+ MSR_IVY_BRIDGE_MC20_CTL is defined as MSR_MC20_CTL in SDM.\r
+ MSR_IVY_BRIDGE_MC21_CTL is defined as MSR_MC21_CTL in SDM.\r
+ MSR_IVY_BRIDGE_MC22_CTL is defined as MSR_MC22_CTL in SDM.\r
+ MSR_IVY_BRIDGE_MC23_CTL is defined as MSR_MC23_CTL in SDM.\r
+ MSR_IVY_BRIDGE_MC24_CTL is defined as MSR_MC24_CTL in SDM.\r
+ MSR_IVY_BRIDGE_MC25_CTL is defined as MSR_MC25_CTL in SDM.\r
+ MSR_IVY_BRIDGE_MC26_CTL is defined as MSR_MC26_CTL in SDM.\r
+ MSR_IVY_BRIDGE_MC27_CTL is defined as MSR_MC27_CTL in SDM.\r
+ MSR_IVY_BRIDGE_MC28_CTL is defined as MSR_MC28_CTL in SDM.\r
+ MSR_IVY_BRIDGE_MC29_CTL is defined as MSR_MC29_CTL in SDM.\r
+ MSR_IVY_BRIDGE_MC30_CTL is defined as MSR_MC30_CTL in SDM.\r
+ MSR_IVY_BRIDGE_MC31_CTL is defined as MSR_MC31_CTL in SDM.\r
@{\r
**/\r
#define MSR_IVY_BRIDGE_MC5_CTL 0x00000414\r
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_MC5_STATUS);\r
AsmWriteMsr64 (MSR_IVY_BRIDGE_MC5_STATUS, Msr);\r
@endcode\r
+ @note MSR_IVY_BRIDGE_MC5_STATUS is defined as MSR_MC5_STATUS in SDM.\r
+ MSR_IVY_BRIDGE_MC6_STATUS is defined as MSR_MC6_STATUS in SDM.\r
+ MSR_IVY_BRIDGE_MC7_STATUS is defined as MSR_MC7_STATUS in SDM.\r
+ MSR_IVY_BRIDGE_MC8_STATUS is defined as MSR_MC8_STATUS in SDM.\r
+ MSR_IVY_BRIDGE_MC9_STATUS is defined as MSR_MC9_STATUS in SDM.\r
+ MSR_IVY_BRIDGE_MC10_STATUS is defined as MSR_MC10_STATUS in SDM.\r
+ MSR_IVY_BRIDGE_MC11_STATUS is defined as MSR_MC11_STATUS in SDM.\r
+ MSR_IVY_BRIDGE_MC12_STATUS is defined as MSR_MC12_STATUS in SDM.\r
+ MSR_IVY_BRIDGE_MC13_STATUS is defined as MSR_MC13_STATUS in SDM.\r
+ MSR_IVY_BRIDGE_MC14_STATUS is defined as MSR_MC14_STATUS in SDM.\r
+ MSR_IVY_BRIDGE_MC15_STATUS is defined as MSR_MC15_STATUS in SDM.\r
+ MSR_IVY_BRIDGE_MC16_STATUS is defined as MSR_MC16_STATUS in SDM.\r
+ MSR_IVY_BRIDGE_MC17_STATUS is defined as MSR_MC17_STATUS in SDM.\r
+ MSR_IVY_BRIDGE_MC18_STATUS is defined as MSR_MC18_STATUS in SDM.\r
+ MSR_IVY_BRIDGE_MC19_STATUS is defined as MSR_MC19_STATUS in SDM.\r
+ MSR_IVY_BRIDGE_MC20_STATUS is defined as MSR_MC20_STATUS in SDM.\r
+ MSR_IVY_BRIDGE_MC21_STATUS is defined as MSR_MC21_STATUS in SDM.\r
+ MSR_IVY_BRIDGE_MC22_STATUS is defined as MSR_MC22_STATUS in SDM.\r
+ MSR_IVY_BRIDGE_MC23_STATUS is defined as MSR_MC23_STATUS in SDM.\r
+ MSR_IVY_BRIDGE_MC24_STATUS is defined as MSR_MC24_STATUS in SDM.\r
+ MSR_IVY_BRIDGE_MC25_STATUS is defined as MSR_MC25_STATUS in SDM.\r
+ MSR_IVY_BRIDGE_MC26_STATUS is defined as MSR_MC26_STATUS in SDM.\r
+ MSR_IVY_BRIDGE_MC27_STATUS is defined as MSR_MC27_STATUS in SDM.\r
+ MSR_IVY_BRIDGE_MC28_STATUS is defined as MSR_MC28_STATUS in SDM.\r
+ MSR_IVY_BRIDGE_MC29_STATUS is defined as MSR_MC29_STATUS in SDM.\r
+ MSR_IVY_BRIDGE_MC30_STATUS is defined as MSR_MC30_STATUS in SDM.\r
+ MSR_IVY_BRIDGE_MC31_STATUS is defined as MSR_MC31_STATUS in SDM.\r
@{\r
**/\r
#define MSR_IVY_BRIDGE_MC5_STATUS 0x00000415\r
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_MC5_ADDR);\r
AsmWriteMsr64 (MSR_IVY_BRIDGE_MC5_ADDR, Msr);\r
@endcode\r
+ @note MSR_IVY_BRIDGE_MC5_ADDR is defined as MSR_MC5_ADDR in SDM.\r
+ MSR_IVY_BRIDGE_MC6_ADDR is defined as MSR_MC6_ADDR in SDM.\r
+ MSR_IVY_BRIDGE_MC7_ADDR is defined as MSR_MC7_ADDR in SDM.\r
+ MSR_IVY_BRIDGE_MC8_ADDR is defined as MSR_MC8_ADDR in SDM.\r
+ MSR_IVY_BRIDGE_MC9_ADDR is defined as MSR_MC9_ADDR in SDM.\r
+ MSR_IVY_BRIDGE_MC10_ADDR is defined as MSR_MC10_ADDR in SDM.\r
+ MSR_IVY_BRIDGE_MC11_ADDR is defined as MSR_MC11_ADDR in SDM.\r
+ MSR_IVY_BRIDGE_MC12_ADDR is defined as MSR_MC12_ADDR in SDM.\r
+ MSR_IVY_BRIDGE_MC13_ADDR is defined as MSR_MC13_ADDR in SDM.\r
+ MSR_IVY_BRIDGE_MC14_ADDR is defined as MSR_MC14_ADDR in SDM.\r
+ MSR_IVY_BRIDGE_MC15_ADDR is defined as MSR_MC15_ADDR in SDM.\r
+ MSR_IVY_BRIDGE_MC16_ADDR is defined as MSR_MC16_ADDR in SDM.\r
+ MSR_IVY_BRIDGE_MC17_ADDR is defined as MSR_MC17_ADDR in SDM.\r
+ MSR_IVY_BRIDGE_MC18_ADDR is defined as MSR_MC18_ADDR in SDM.\r
+ MSR_IVY_BRIDGE_MC19_ADDR is defined as MSR_MC19_ADDR in SDM.\r
+ MSR_IVY_BRIDGE_MC20_ADDR is defined as MSR_MC20_ADDR in SDM.\r
+ MSR_IVY_BRIDGE_MC21_ADDR is defined as MSR_MC21_ADDR in SDM.\r
+ MSR_IVY_BRIDGE_MC22_ADDR is defined as MSR_MC22_ADDR in SDM.\r
+ MSR_IVY_BRIDGE_MC23_ADDR is defined as MSR_MC23_ADDR in SDM.\r
+ MSR_IVY_BRIDGE_MC24_ADDR is defined as MSR_MC24_ADDR in SDM.\r
+ MSR_IVY_BRIDGE_MC25_ADDR is defined as MSR_MC25_ADDR in SDM.\r
+ MSR_IVY_BRIDGE_MC26_ADDR is defined as MSR_MC26_ADDR in SDM.\r
+ MSR_IVY_BRIDGE_MC27_ADDR is defined as MSR_MC27_ADDR in SDM.\r
+ MSR_IVY_BRIDGE_MC28_ADDR is defined as MSR_MC28_ADDR in SDM.\r
+ MSR_IVY_BRIDGE_MC29_ADDR is defined as MSR_MC29_ADDR in SDM.\r
+ MSR_IVY_BRIDGE_MC30_ADDR is defined as MSR_MC30_ADDR in SDM.\r
+ MSR_IVY_BRIDGE_MC31_ADDR is defined as MSR_MC31_ADDR in SDM.\r
@{\r
**/\r
#define MSR_IVY_BRIDGE_MC5_ADDR 0x00000416\r
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_MC5_MISC);\r
AsmWriteMsr64 (MSR_IVY_BRIDGE_MC5_MISC, Msr);\r
@endcode\r
+ @note MSR_IVY_BRIDGE_MC5_MISC is defined as MSR_MC5_MISC in SDM.\r
+ MSR_IVY_BRIDGE_MC6_MISC is defined as MSR_MC6_MISC in SDM.\r
+ MSR_IVY_BRIDGE_MC7_MISC is defined as MSR_MC7_MISC in SDM.\r
+ MSR_IVY_BRIDGE_MC8_MISC is defined as MSR_MC8_MISC in SDM.\r
+ MSR_IVY_BRIDGE_MC9_MISC is defined as MSR_MC9_MISC in SDM.\r
+ MSR_IVY_BRIDGE_MC10_MISC is defined as MSR_MC10_MISC in SDM.\r
+ MSR_IVY_BRIDGE_MC11_MISC is defined as MSR_MC11_MISC in SDM.\r
+ MSR_IVY_BRIDGE_MC12_MISC is defined as MSR_MC12_MISC in SDM.\r
+ MSR_IVY_BRIDGE_MC13_MISC is defined as MSR_MC13_MISC in SDM.\r
+ MSR_IVY_BRIDGE_MC14_MISC is defined as MSR_MC14_MISC in SDM.\r
+ MSR_IVY_BRIDGE_MC15_MISC is defined as MSR_MC15_MISC in SDM.\r
+ MSR_IVY_BRIDGE_MC16_MISC is defined as MSR_MC16_MISC in SDM.\r
+ MSR_IVY_BRIDGE_MC17_MISC is defined as MSR_MC17_MISC in SDM.\r
+ MSR_IVY_BRIDGE_MC18_MISC is defined as MSR_MC18_MISC in SDM.\r
+ MSR_IVY_BRIDGE_MC19_MISC is defined as MSR_MC19_MISC in SDM.\r
+ MSR_IVY_BRIDGE_MC20_MISC is defined as MSR_MC20_MISC in SDM.\r
+ MSR_IVY_BRIDGE_MC21_MISC is defined as MSR_MC21_MISC in SDM.\r
+ MSR_IVY_BRIDGE_MC22_MISC is defined as MSR_MC22_MISC in SDM.\r
+ MSR_IVY_BRIDGE_MC23_MISC is defined as MSR_MC23_MISC in SDM.\r
+ MSR_IVY_BRIDGE_MC24_MISC is defined as MSR_MC24_MISC in SDM.\r
+ MSR_IVY_BRIDGE_MC25_MISC is defined as MSR_MC25_MISC in SDM.\r
+ MSR_IVY_BRIDGE_MC26_MISC is defined as MSR_MC26_MISC in SDM.\r
+ MSR_IVY_BRIDGE_MC27_MISC is defined as MSR_MC27_MISC in SDM.\r
+ MSR_IVY_BRIDGE_MC28_MISC is defined as MSR_MC28_MISC in SDM.\r
+ MSR_IVY_BRIDGE_MC29_MISC is defined as MSR_MC29_MISC in SDM.\r
+ MSR_IVY_BRIDGE_MC30_MISC is defined as MSR_MC30_MISC in SDM.\r
+ MSR_IVY_BRIDGE_MC31_MISC is defined as MSR_MC31_MISC in SDM.\r
@{\r
**/\r
#define MSR_IVY_BRIDGE_MC5_MISC 0x00000417\r
\r
Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_IA32_MC6_MISC);\r
@endcode\r
+ @note MSR_IVY_BRIDGE_IA32_MC6_MISC is defined as IA32_MC6_MISC in SDM.\r
**/\r
#define MSR_IVY_BRIDGE_IA32_MC6_MISC 0x0000041B\r
\r
\r
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_PKG_PERF_STATUS);\r
@endcode\r
+ @note MSR_IVY_BRIDGE_PKG_PERF_STATUS is defined as MSR_PKG_PERF_STATUS in SDM.\r
**/\r
#define MSR_IVY_BRIDGE_PKG_PERF_STATUS 0x00000613\r
\r
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_DRAM_POWER_LIMIT);\r
AsmWriteMsr64 (MSR_IVY_BRIDGE_DRAM_POWER_LIMIT, Msr);\r
@endcode\r
+ @note MSR_IVY_BRIDGE_DRAM_POWER_LIMIT is defined as MSR_DRAM_POWER_LIMIT in SDM.\r
**/\r
#define MSR_IVY_BRIDGE_DRAM_POWER_LIMIT 0x00000618\r
\r
\r
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_DRAM_ENERGY_STATUS);\r
@endcode\r
+ @note MSR_IVY_BRIDGE_DRAM_ENERGY_STATUS is defined as MSR_DRAM_ENERGY_STATUS in SDM.\r
**/\r
#define MSR_IVY_BRIDGE_DRAM_ENERGY_STATUS 0x00000619\r
\r
\r
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_DRAM_PERF_STATUS);\r
@endcode\r
+ @note MSR_IVY_BRIDGE_DRAM_PERF_STATUS is defined as MSR_DRAM_PERF_STATUS in SDM.\r
**/\r
#define MSR_IVY_BRIDGE_DRAM_PERF_STATUS 0x0000061B\r
\r
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_DRAM_POWER_INFO);\r
AsmWriteMsr64 (MSR_IVY_BRIDGE_DRAM_POWER_INFO, Msr);\r
@endcode\r
+ @note MSR_IVY_BRIDGE_DRAM_POWER_INFO is defined as MSR_DRAM_POWER_INFO in SDM.\r
**/\r
#define MSR_IVY_BRIDGE_DRAM_POWER_INFO 0x0000061C\r
\r
Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_PEBS_ENABLE);\r
AsmWriteMsr64 (MSR_IVY_BRIDGE_PEBS_ENABLE, Msr.Uint64);\r
@endcode\r
+ @note MSR_IVY_BRIDGE_PEBS_ENABLE is defined as MSR_PEBS_ENABLE in SDM.\r
**/\r
#define MSR_IVY_BRIDGE_PEBS_ENABLE 0x000003F1\r
\r
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_PMON_GLOBAL_CTL);\r
AsmWriteMsr64 (MSR_IVY_BRIDGE_PMON_GLOBAL_CTL, Msr);\r
@endcode\r
+ @note MSR_IVY_BRIDGE_PMON_GLOBAL_CTL is defined as MSR_PMON_GLOBAL_CTL in SDM.\r
**/\r
#define MSR_IVY_BRIDGE_PMON_GLOBAL_CTL 0x00000C00\r
\r
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_PMON_GLOBAL_STATUS);\r
AsmWriteMsr64 (MSR_IVY_BRIDGE_PMON_GLOBAL_STATUS, Msr);\r
@endcode\r
+ @note MSR_IVY_BRIDGE_PMON_GLOBAL_STATUS is defined as MSR_PMON_GLOBAL_STATUS in SDM.\r
**/\r
#define MSR_IVY_BRIDGE_PMON_GLOBAL_STATUS 0x00000C01\r
\r
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_PMON_GLOBAL_CONFIG);\r
AsmWriteMsr64 (MSR_IVY_BRIDGE_PMON_GLOBAL_CONFIG, Msr);\r
@endcode\r
+ @note MSR_IVY_BRIDGE_PMON_GLOBAL_CONFIG is defined as MSR_PMON_GLOBAL_CONFIG in SDM.\r
**/\r
#define MSR_IVY_BRIDGE_PMON_GLOBAL_CONFIG 0x00000C06\r
\r
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_U_PMON_BOX_STATUS);\r
AsmWriteMsr64 (MSR_IVY_BRIDGE_U_PMON_BOX_STATUS, Msr);\r
@endcode\r
+ @note MSR_IVY_BRIDGE_U_PMON_BOX_STATUS is defined as MSR_U_PMON_BOX_STATUS in SDM.\r
**/\r
#define MSR_IVY_BRIDGE_U_PMON_BOX_STATUS 0x00000C15\r
\r
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_PCU_PMON_BOX_STATUS);\r
AsmWriteMsr64 (MSR_IVY_BRIDGE_PCU_PMON_BOX_STATUS, Msr);\r
@endcode\r
+ @note MSR_IVY_BRIDGE_PCU_PMON_BOX_STATUS is defined as MSR_PCU_PMON_BOX_STATUS in SDM.\r
**/\r
#define MSR_IVY_BRIDGE_PCU_PMON_BOX_STATUS 0x00000C35\r
\r
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C0_PMON_BOX_FILTER1);\r
AsmWriteMsr64 (MSR_IVY_BRIDGE_C0_PMON_BOX_FILTER1, Msr);\r
@endcode\r
+ @note MSR_IVY_BRIDGE_C0_PMON_BOX_FILTER1 is defined as MSR_C0_PMON_BOX_FILTER1 in SDM.\r
**/\r
#define MSR_IVY_BRIDGE_C0_PMON_BOX_FILTER1 0x00000D1A\r
\r
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C1_PMON_BOX_FILTER1);\r
AsmWriteMsr64 (MSR_IVY_BRIDGE_C1_PMON_BOX_FILTER1, Msr);\r
@endcode\r
+ @note MSR_IVY_BRIDGE_C1_PMON_BOX_FILTER1 is defined as MSR_C1_PMON_BOX_FILTER1 in SDM.\r
**/\r
#define MSR_IVY_BRIDGE_C1_PMON_BOX_FILTER1 0x00000D3A\r
\r
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C2_PMON_BOX_FILTER1);\r
AsmWriteMsr64 (MSR_IVY_BRIDGE_C2_PMON_BOX_FILTER1, Msr);\r
@endcode\r
+ @note MSR_IVY_BRIDGE_C2_PMON_BOX_FILTER1 is defined as MSR_C2_PMON_BOX_FILTER1 in SDM.\r
**/\r
#define MSR_IVY_BRIDGE_C2_PMON_BOX_FILTER1 0x00000D5A\r
\r
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C3_PMON_BOX_FILTER1);\r
AsmWriteMsr64 (MSR_IVY_BRIDGE_C3_PMON_BOX_FILTER1, Msr);\r
@endcode\r
+ @note MSR_IVY_BRIDGE_C3_PMON_BOX_FILTER1 is defined as MSR_C3_PMON_BOX_FILTER1 in SDM.\r
**/\r
#define MSR_IVY_BRIDGE_C3_PMON_BOX_FILTER1 0x00000D7A\r
\r
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C4_PMON_BOX_FILTER1);\r
AsmWriteMsr64 (MSR_IVY_BRIDGE_C4_PMON_BOX_FILTER1, Msr);\r
@endcode\r
+ @note MSR_IVY_BRIDGE_C4_PMON_BOX_FILTER1 is defined as MSR_C4_PMON_BOX_FILTER1 in SDM.\r
**/\r
#define MSR_IVY_BRIDGE_C4_PMON_BOX_FILTER1 0x00000D9A\r
\r
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C5_PMON_BOX_FILTER1);\r
AsmWriteMsr64 (MSR_IVY_BRIDGE_C5_PMON_BOX_FILTER1, Msr);\r
@endcode\r
+ @note MSR_IVY_BRIDGE_C5_PMON_BOX_FILTER1 is defined as MSR_C5_PMON_BOX_FILTER1 in SDM.\r
**/\r
#define MSR_IVY_BRIDGE_C5_PMON_BOX_FILTER1 0x00000DBA\r
\r
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C6_PMON_BOX_FILTER1);\r
AsmWriteMsr64 (MSR_IVY_BRIDGE_C6_PMON_BOX_FILTER1, Msr);\r
@endcode\r
+ @note MSR_IVY_BRIDGE_C6_PMON_BOX_FILTER1 is defined as MSR_C6_PMON_BOX_FILTER1 in SDM.\r
**/\r
#define MSR_IVY_BRIDGE_C6_PMON_BOX_FILTER1 0x00000DDA\r
\r
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C7_PMON_BOX_FILTER1);\r
AsmWriteMsr64 (MSR_IVY_BRIDGE_C7_PMON_BOX_FILTER1, Msr);\r
@endcode\r
+ @note MSR_IVY_BRIDGE_C7_PMON_BOX_FILTER1 is defined as MSR_C7_PMON_BOX_FILTER1 in SDM.\r
**/\r
#define MSR_IVY_BRIDGE_C7_PMON_BOX_FILTER1 0x00000DFA\r
\r
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_BOX_CTL);\r
AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_BOX_CTL, Msr);\r
@endcode\r
+ @note MSR_IVY_BRIDGE_C8_PMON_BOX_CTL is defined as MSR_C8_PMON_BOX_CTL in SDM.\r
**/\r
#define MSR_IVY_BRIDGE_C8_PMON_BOX_CTL 0x00000E04\r
\r
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_EVNTSEL0);\r
AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_EVNTSEL0, Msr);\r
@endcode\r
+ @note MSR_IVY_BRIDGE_C8_PMON_EVNTSEL0 is defined as MSR_C8_PMON_EVNTSEL0 in SDM.\r
**/\r
#define MSR_IVY_BRIDGE_C8_PMON_EVNTSEL0 0x00000E10\r
\r
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_EVNTSEL1);\r
AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_EVNTSEL1, Msr);\r
@endcode\r
+ @note MSR_IVY_BRIDGE_C8_PMON_EVNTSEL1 is defined as MSR_C8_PMON_EVNTSEL1 in SDM.\r
**/\r
#define MSR_IVY_BRIDGE_C8_PMON_EVNTSEL1 0x00000E11\r
\r
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_EVNTSEL2);\r
AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_EVNTSEL2, Msr);\r
@endcode\r
+ @note MSR_IVY_BRIDGE_C8_PMON_EVNTSEL2 is defined as MSR_C8_PMON_EVNTSEL2 in SDM.\r
**/\r
#define MSR_IVY_BRIDGE_C8_PMON_EVNTSEL2 0x00000E12\r
\r
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_EVNTSEL3);\r
AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_EVNTSEL3, Msr);\r
@endcode\r
+ @note MSR_IVY_BRIDGE_C8_PMON_EVNTSEL3 is defined as MSR_C8_PMON_EVNTSEL3 in SDM.\r
**/\r
#define MSR_IVY_BRIDGE_C8_PMON_EVNTSEL3 0x00000E13\r
\r
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER);\r
AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER, Msr);\r
@endcode\r
+ @note MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER is defined as MSR_C8_PMON_BOX_FILTER in SDM.\r
**/\r
#define MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER 0x00000E14\r
\r
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_CTR0);\r
AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_CTR0, Msr);\r
@endcode\r
+ @note MSR_IVY_BRIDGE_C8_PMON_CTR0 is defined as MSR_C8_PMON_CTR0 in SDM.\r
**/\r
#define MSR_IVY_BRIDGE_C8_PMON_CTR0 0x00000E16\r
\r
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_CTR1);\r
AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_CTR1, Msr);\r
@endcode\r
+ @note MSR_IVY_BRIDGE_C8_PMON_CTR1 is defined as MSR_C8_PMON_CTR1 in SDM.\r
**/\r
#define MSR_IVY_BRIDGE_C8_PMON_CTR1 0x00000E17\r
\r
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_CTR2);\r
AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_CTR2, Msr);\r
@endcode\r
+ @note MSR_IVY_BRIDGE_C8_PMON_CTR2 is defined as MSR_C8_PMON_CTR2 in SDM.\r
**/\r
#define MSR_IVY_BRIDGE_C8_PMON_CTR2 0x00000E18\r
\r
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_CTR3);\r
AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_CTR3, Msr);\r
@endcode\r
+ @note MSR_IVY_BRIDGE_C8_PMON_CTR3 is defined as MSR_C8_PMON_CTR3 in SDM.\r
**/\r
#define MSR_IVY_BRIDGE_C8_PMON_CTR3 0x00000E19\r
\r
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER1);\r
AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER1, Msr);\r
@endcode\r
+ @note MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER1 is defined as MSR_C8_PMON_BOX_FILTER1 in SDM.\r
**/\r
#define MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER1 0x00000E1A\r
\r
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_BOX_CTL);\r
AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_BOX_CTL, Msr);\r
@endcode\r
+ @note MSR_IVY_BRIDGE_C9_PMON_BOX_CTL is defined as MSR_C9_PMON_BOX_CTL in SDM.\r
**/\r
#define MSR_IVY_BRIDGE_C9_PMON_BOX_CTL 0x00000E24\r
\r
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_EVNTSEL0);\r
AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_EVNTSEL0, Msr);\r
@endcode\r
+ @note MSR_IVY_BRIDGE_C9_PMON_EVNTSEL0 is defined as MSR_C9_PMON_EVNTSEL0 in SDM.\r
**/\r
#define MSR_IVY_BRIDGE_C9_PMON_EVNTSEL0 0x00000E30\r
\r
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_EVNTSEL1);\r
AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_EVNTSEL1, Msr);\r
@endcode\r
+ @note MSR_IVY_BRIDGE_C9_PMON_EVNTSEL1 is defined as MSR_C9_PMON_EVNTSEL1 in SDM.\r
**/\r
#define MSR_IVY_BRIDGE_C9_PMON_EVNTSEL1 0x00000E31\r
\r
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_EVNTSEL2);\r
AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_EVNTSEL2, Msr);\r
@endcode\r
+ @note MSR_IVY_BRIDGE_C9_PMON_EVNTSEL2 is defined as MSR_C9_PMON_EVNTSEL2 in SDM.\r
**/\r
#define MSR_IVY_BRIDGE_C9_PMON_EVNTSEL2 0x00000E32\r
\r
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_EVNTSEL3);\r
AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_EVNTSEL3, Msr);\r
@endcode\r
+ @note MSR_IVY_BRIDGE_C9_PMON_EVNTSEL3 is defined as MSR_C9_PMON_EVNTSEL3 in SDM.\r
**/\r
#define MSR_IVY_BRIDGE_C9_PMON_EVNTSEL3 0x00000E33\r
\r
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER);\r
AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER, Msr);\r
@endcode\r
+ @note MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER is defined as MSR_C9_PMON_BOX_FILTER in SDM.\r
**/\r
#define MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER 0x00000E34\r
\r
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_CTR0);\r
AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_CTR0, Msr);\r
@endcode\r
+ @note MSR_IVY_BRIDGE_C9_PMON_CTR0 is defined as MSR_C9_PMON_CTR0 in SDM.\r
**/\r
#define MSR_IVY_BRIDGE_C9_PMON_CTR0 0x00000E36\r
\r
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_CTR1);\r
AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_CTR1, Msr);\r
@endcode\r
+ @note MSR_IVY_BRIDGE_C9_PMON_CTR1 is defined as MSR_C9_PMON_CTR1 in SDM.\r
**/\r
#define MSR_IVY_BRIDGE_C9_PMON_CTR1 0x00000E37\r
\r
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_CTR2);\r
AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_CTR2, Msr);\r
@endcode\r
+ @note MSR_IVY_BRIDGE_C9_PMON_CTR2 is defined as MSR_C9_PMON_CTR2 in SDM.\r
**/\r
#define MSR_IVY_BRIDGE_C9_PMON_CTR2 0x00000E38\r
\r
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_CTR3);\r
AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_CTR3, Msr);\r
@endcode\r
+ @note MSR_IVY_BRIDGE_C9_PMON_CTR3 is defined as MSR_C9_PMON_CTR3 in SDM.\r
**/\r
#define MSR_IVY_BRIDGE_C9_PMON_CTR3 0x00000E39\r
\r
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER1);\r
AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER1, Msr);\r
@endcode\r
+ @note MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER1 is defined as MSR_C9_PMON_BOX_FILTER1 in SDM.\r
**/\r
#define MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER1 0x00000E3A\r
\r
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_BOX_CTL);\r
AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_BOX_CTL, Msr);\r
@endcode\r
+ @note MSR_IVY_BRIDGE_C10_PMON_BOX_CTL is defined as MSR_C10_PMON_BOX_CTL in SDM.\r
**/\r
#define MSR_IVY_BRIDGE_C10_PMON_BOX_CTL 0x00000E44\r
\r
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_EVNTSEL0);\r
AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_EVNTSEL0, Msr);\r
@endcode\r
+ @note MSR_IVY_BRIDGE_C10_PMON_EVNTSEL0 is defined as MSR_C10_PMON_EVNTSEL0 in SDM.\r
**/\r
#define MSR_IVY_BRIDGE_C10_PMON_EVNTSEL0 0x00000E50\r
\r
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_EVNTSEL1);\r
AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_EVNTSEL1, Msr);\r
@endcode\r
+ @note MSR_IVY_BRIDGE_C10_PMON_EVNTSEL1 is defined as MSR_C10_PMON_EVNTSEL1 in SDM.\r
**/\r
#define MSR_IVY_BRIDGE_C10_PMON_EVNTSEL1 0x00000E51\r
\r
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_EVNTSEL2);\r
AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_EVNTSEL2, Msr);\r
@endcode\r
+ @note MSR_IVY_BRIDGE_C10_PMON_EVNTSEL2 is defined as MSR_C10_PMON_EVNTSEL2 in SDM.\r
**/\r
#define MSR_IVY_BRIDGE_C10_PMON_EVNTSEL2 0x00000E52\r
\r
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_EVNTSEL3);\r
AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_EVNTSEL3, Msr);\r
@endcode\r
+ @note MSR_IVY_BRIDGE_C10_PMON_EVNTSEL3 is defined as MSR_C10_PMON_EVNTSEL3 in SDM.\r
**/\r
#define MSR_IVY_BRIDGE_C10_PMON_EVNTSEL3 0x00000E53\r
\r
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER);\r
AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER, Msr);\r
@endcode\r
+ @note MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER is defined as MSR_C10_PMON_BOX_FILTER in SDM.\r
**/\r
#define MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER 0x00000E54\r
\r
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_CTR0);\r
AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_CTR0, Msr);\r
@endcode\r
+ @note MSR_IVY_BRIDGE_C10_PMON_CTR0 is defined as MSR_C10_PMON_CTR0 in SDM.\r
**/\r
#define MSR_IVY_BRIDGE_C10_PMON_CTR0 0x00000E56\r
\r
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_CTR1);\r
AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_CTR1, Msr);\r
@endcode\r
+ @note MSR_IVY_BRIDGE_C10_PMON_CTR1 is defined as MSR_C10_PMON_CTR1 in SDM.\r
**/\r
#define MSR_IVY_BRIDGE_C10_PMON_CTR1 0x00000E57\r
\r
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_CTR2);\r
AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_CTR2, Msr);\r
@endcode\r
+ @note MSR_IVY_BRIDGE_C10_PMON_CTR2 is defined as MSR_C10_PMON_CTR2 in SDM.\r
**/\r
#define MSR_IVY_BRIDGE_C10_PMON_CTR2 0x00000E58\r
\r
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_CTR3);\r
AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_CTR3, Msr);\r
@endcode\r
+ @note MSR_IVY_BRIDGE_C10_PMON_CTR3 is defined as MSR_C10_PMON_CTR3 in SDM.\r
**/\r
#define MSR_IVY_BRIDGE_C10_PMON_CTR3 0x00000E59\r
\r
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER1);\r
AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER1, Msr);\r
@endcode\r
+ @note MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER1 is defined as MSR_C10_PMON_BOX_FILTER1 in SDM.\r
**/\r
#define MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER1 0x00000E5A\r
\r
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_BOX_CTL);\r
AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_BOX_CTL, Msr);\r
@endcode\r
+ @note MSR_IVY_BRIDGE_C11_PMON_BOX_CTL is defined as MSR_C11_PMON_BOX_CTL in SDM.\r
**/\r
#define MSR_IVY_BRIDGE_C11_PMON_BOX_CTL 0x00000E64\r
\r
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_EVNTSEL0);\r
AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_EVNTSEL0, Msr);\r
@endcode\r
+ @note MSR_IVY_BRIDGE_C11_PMON_EVNTSEL0 is defined as MSR_C11_PMON_EVNTSEL0 in SDM.\r
**/\r
#define MSR_IVY_BRIDGE_C11_PMON_EVNTSEL0 0x00000E70\r
\r
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_EVNTSEL1);\r
AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_EVNTSEL1, Msr);\r
@endcode\r
+ @note MSR_IVY_BRIDGE_C11_PMON_EVNTSEL1 is defined as MSR_C11_PMON_EVNTSEL1 in SDM.\r
**/\r
#define MSR_IVY_BRIDGE_C11_PMON_EVNTSEL1 0x00000E71\r
\r
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_EVNTSEL2);\r
AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_EVNTSEL2, Msr);\r
@endcode\r
+ @note MSR_IVY_BRIDGE_C11_PMON_EVNTSEL2 is defined as MSR_C11_PMON_EVNTSEL2 in SDM.\r
**/\r
#define MSR_IVY_BRIDGE_C11_PMON_EVNTSEL2 0x00000E72\r
\r
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_EVNTSEL3);\r
AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_EVNTSEL3, Msr);\r
@endcode\r
+ @note MSR_IVY_BRIDGE_C11_PMON_EVNTSEL3 is defined as MSR_C11_PMON_EVNTSEL3 in SDM.\r
**/\r
#define MSR_IVY_BRIDGE_C11_PMON_EVNTSEL3 0x00000E73\r
\r
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER);\r
AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER, Msr);\r
@endcode\r
+ @note MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER is defined as MSR_C11_PMON_BOX_FILTER in SDM.\r
**/\r
#define MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER 0x00000E74\r
\r
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_CTR0);\r
AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_CTR0, Msr);\r
@endcode\r
+ @note MSR_IVY_BRIDGE_C11_PMON_CTR0 is defined as MSR_C11_PMON_CTR0 in SDM.\r
**/\r
#define MSR_IVY_BRIDGE_C11_PMON_CTR0 0x00000E76\r
\r
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_CTR1);\r
AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_CTR1, Msr);\r
@endcode\r
+ @note MSR_IVY_BRIDGE_C11_PMON_CTR1 is defined as MSR_C11_PMON_CTR1 in SDM.\r
**/\r
#define MSR_IVY_BRIDGE_C11_PMON_CTR1 0x00000E77\r
\r
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_CTR2);\r
AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_CTR2, Msr);\r
@endcode\r
+ @note MSR_IVY_BRIDGE_C11_PMON_CTR2 is defined as MSR_C11_PMON_CTR2 in SDM.\r
**/\r
#define MSR_IVY_BRIDGE_C11_PMON_CTR2 0x00000E78\r
\r
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_CTR3);\r
AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_CTR3, Msr);\r
@endcode\r
+ @note MSR_IVY_BRIDGE_C11_PMON_CTR3 is defined as MSR_C11_PMON_CTR3 in SDM.\r
**/\r
#define MSR_IVY_BRIDGE_C11_PMON_CTR3 0x00000E79\r
\r
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER1);\r
AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER1, Msr);\r
@endcode\r
+ @note MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER1 is defined as MSR_C11_PMON_BOX_FILTER1 in SDM.\r
**/\r
#define MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER1 0x00000E7A\r
\r
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_BOX_CTL);\r
AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_BOX_CTL, Msr);\r
@endcode\r
+ @note MSR_IVY_BRIDGE_C12_PMON_BOX_CTL is defined as MSR_C12_PMON_BOX_CTL in SDM.\r
**/\r
#define MSR_IVY_BRIDGE_C12_PMON_BOX_CTL 0x00000E84\r
\r
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_EVNTSEL0);\r
AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_EVNTSEL0, Msr);\r
@endcode\r
+ @note MSR_IVY_BRIDGE_C12_PMON_EVNTSEL0 is defined as MSR_C12_PMON_EVNTSEL0 in SDM.\r
**/\r
#define MSR_IVY_BRIDGE_C12_PMON_EVNTSEL0 0x00000E90\r
\r
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_EVNTSEL1);\r
AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_EVNTSEL1, Msr);\r
@endcode\r
+ @note MSR_IVY_BRIDGE_C12_PMON_EVNTSEL1 is defined as MSR_C12_PMON_EVNTSEL1 in SDM.\r
**/\r
#define MSR_IVY_BRIDGE_C12_PMON_EVNTSEL1 0x00000E91\r
\r
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_EVNTSEL2);\r
AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_EVNTSEL2, Msr);\r
@endcode\r
+ @note MSR_IVY_BRIDGE_C12_PMON_EVNTSEL2 is defined as MSR_C12_PMON_EVNTSEL2 in SDM.\r
**/\r
#define MSR_IVY_BRIDGE_C12_PMON_EVNTSEL2 0x00000E92\r
\r
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_EVNTSEL3);\r
AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_EVNTSEL3, Msr);\r
@endcode\r
+ @note MSR_IVY_BRIDGE_C12_PMON_EVNTSEL3 is defined as MSR_C12_PMON_EVNTSEL3 in SDM.\r
**/\r
#define MSR_IVY_BRIDGE_C12_PMON_EVNTSEL3 0x00000E93\r
\r
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER);\r
AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER, Msr);\r
@endcode\r
+ @note MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER is defined as MSR_C12_PMON_BOX_FILTER in SDM.\r
**/\r
#define MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER 0x00000E94\r
\r
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_CTR0);\r
AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_CTR0, Msr);\r
@endcode\r
+ @note MSR_IVY_BRIDGE_C12_PMON_CTR0 is defined as MSR_C12_PMON_CTR0 in SDM.\r
**/\r
#define MSR_IVY_BRIDGE_C12_PMON_CTR0 0x00000E96\r
\r
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_CTR1);\r
AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_CTR1, Msr);\r
@endcode\r
+ @note MSR_IVY_BRIDGE_C12_PMON_CTR1 is defined as MSR_C12_PMON_CTR1 in SDM.\r
**/\r
#define MSR_IVY_BRIDGE_C12_PMON_CTR1 0x00000E97\r
\r
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_CTR2);\r
AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_CTR2, Msr);\r
@endcode\r
+ @note MSR_IVY_BRIDGE_C12_PMON_CTR2 is defined as MSR_C12_PMON_CTR2 in SDM.\r
**/\r
#define MSR_IVY_BRIDGE_C12_PMON_CTR2 0x00000E98\r
\r
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_CTR3);\r
AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_CTR3, Msr);\r
@endcode\r
+ @note MSR_IVY_BRIDGE_C12_PMON_CTR3 is defined as MSR_C12_PMON_CTR3 in SDM.\r
**/\r
#define MSR_IVY_BRIDGE_C12_PMON_CTR3 0x00000E99\r
\r
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER1);\r
AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER1, Msr);\r
@endcode\r
+ @note MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER1 is defined as MSR_C12_PMON_BOX_FILTER1 in SDM.\r
**/\r
#define MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER1 0x00000E9A\r
\r
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_BOX_CTL);\r
AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_BOX_CTL, Msr);\r
@endcode\r
+ @note MSR_IVY_BRIDGE_C13_PMON_BOX_CTL is defined as MSR_C13_PMON_BOX_CTL in SDM.\r
**/\r
#define MSR_IVY_BRIDGE_C13_PMON_BOX_CTL 0x00000EA4\r
\r
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_EVNTSEL0);\r
AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_EVNTSEL0, Msr);\r
@endcode\r
+ @note MSR_IVY_BRIDGE_C13_PMON_EVNTSEL0 is defined as MSR_C13_PMON_EVNTSEL0 in SDM.\r
**/\r
#define MSR_IVY_BRIDGE_C13_PMON_EVNTSEL0 0x00000EB0\r
\r
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_EVNTSEL1);\r
AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_EVNTSEL1, Msr);\r
@endcode\r
+ @note MSR_IVY_BRIDGE_C13_PMON_EVNTSEL1 is defined as MSR_C13_PMON_EVNTSEL1 in SDM.\r
**/\r
#define MSR_IVY_BRIDGE_C13_PMON_EVNTSEL1 0x00000EB1\r
\r
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_EVNTSEL2);\r
AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_EVNTSEL2, Msr);\r
@endcode\r
+ @note MSR_IVY_BRIDGE_C13_PMON_EVNTSEL2 is defined as MSR_C13_PMON_EVNTSEL2 in SDM.\r
**/\r
#define MSR_IVY_BRIDGE_C13_PMON_EVNTSEL2 0x00000EB2\r
\r
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_EVNTSEL3);\r
AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_EVNTSEL3, Msr);\r
@endcode\r
+ @note MSR_IVY_BRIDGE_C13_PMON_EVNTSEL3 is defined as MSR_C13_PMON_EVNTSEL3 in SDM.\r
**/\r
#define MSR_IVY_BRIDGE_C13_PMON_EVNTSEL3 0x00000EB3\r
\r
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER);\r
AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER, Msr);\r
@endcode\r
+ @note MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER is defined as MSR_C13_PMON_BOX_FILTER in SDM.\r
**/\r
#define MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER 0x00000EB4\r
\r
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_CTR0);\r
AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_CTR0, Msr);\r
@endcode\r
+ @note MSR_IVY_BRIDGE_C13_PMON_CTR0 is defined as MSR_C13_PMON_CTR0 in SDM.\r
**/\r
#define MSR_IVY_BRIDGE_C13_PMON_CTR0 0x00000EB6\r
\r
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_CTR1);\r
AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_CTR1, Msr);\r
@endcode\r
+ @note MSR_IVY_BRIDGE_C13_PMON_CTR1 is defined as MSR_C13_PMON_CTR1 in SDM.\r
**/\r
#define MSR_IVY_BRIDGE_C13_PMON_CTR1 0x00000EB7\r
\r
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_CTR2);\r
AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_CTR2, Msr);\r
@endcode\r
+ @note MSR_IVY_BRIDGE_C13_PMON_CTR2 is defined as MSR_C13_PMON_CTR2 in SDM.\r
**/\r
#define MSR_IVY_BRIDGE_C13_PMON_CTR2 0x00000EB8\r
\r
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_CTR3);\r
AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_CTR3, Msr);\r
@endcode\r
+ @note MSR_IVY_BRIDGE_C13_PMON_CTR3 is defined as MSR_C13_PMON_CTR3 in SDM.\r
**/\r
#define MSR_IVY_BRIDGE_C13_PMON_CTR3 0x00000EB9\r
\r
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER1);\r
AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER1, Msr);\r
@endcode\r
+ @note MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER1 is defined as MSR_C13_PMON_BOX_FILTER1 in SDM.\r
**/\r
#define MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER1 0x00000EBA\r
\r
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_BOX_CTL);\r
AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_BOX_CTL, Msr);\r
@endcode\r
+ @note MSR_IVY_BRIDGE_C14_PMON_BOX_CTL is defined as MSR_C14_PMON_BOX_CTL in SDM.\r
**/\r
#define MSR_IVY_BRIDGE_C14_PMON_BOX_CTL 0x00000EC4\r
\r
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_EVNTSEL0);\r
AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_EVNTSEL0, Msr);\r
@endcode\r
+ @note MSR_IVY_BRIDGE_C14_PMON_EVNTSEL0 is defined as MSR_C14_PMON_EVNTSEL0 in SDM.\r
**/\r
#define MSR_IVY_BRIDGE_C14_PMON_EVNTSEL0 0x00000ED0\r
\r
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_EVNTSEL1);\r
AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_EVNTSEL1, Msr);\r
@endcode\r
+ @note MSR_IVY_BRIDGE_C14_PMON_EVNTSEL1 is defined as MSR_C14_PMON_EVNTSEL1 in SDM.\r
**/\r
#define MSR_IVY_BRIDGE_C14_PMON_EVNTSEL1 0x00000ED1\r
\r
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_EVNTSEL2);\r
AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_EVNTSEL2, Msr);\r
@endcode\r
+ @note MSR_IVY_BRIDGE_C14_PMON_EVNTSEL2 is defined as MSR_C14_PMON_EVNTSEL2 in SDM.\r
**/\r
#define MSR_IVY_BRIDGE_C14_PMON_EVNTSEL2 0x00000ED2\r
\r
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_EVNTSEL3);\r
AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_EVNTSEL3, Msr);\r
@endcode\r
+ @note MSR_IVY_BRIDGE_C14_PMON_EVNTSEL3 is defined as MSR_C14_PMON_EVNTSEL3 in SDM.\r
**/\r
#define MSR_IVY_BRIDGE_C14_PMON_EVNTSEL3 0x00000ED3\r
\r
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER);\r
AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER, Msr);\r
@endcode\r
+ @note MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER is defined as MSR_C14_PMON_BOX_FILTER in SDM.\r
**/\r
#define MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER 0x00000ED4\r
\r
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_CTR0);\r
AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_CTR0, Msr);\r
@endcode\r
+ @note MSR_IVY_BRIDGE_C14_PMON_CTR0 is defined as MSR_C14_PMON_CTR0 in SDM.\r
**/\r
#define MSR_IVY_BRIDGE_C14_PMON_CTR0 0x00000ED6\r
\r
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_CTR1);\r
AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_CTR1, Msr);\r
@endcode\r
+ @note MSR_IVY_BRIDGE_C14_PMON_CTR1 is defined as MSR_C14_PMON_CTR1 in SDM.\r
**/\r
#define MSR_IVY_BRIDGE_C14_PMON_CTR1 0x00000ED7\r
\r
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_CTR2);\r
AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_CTR2, Msr);\r
@endcode\r
+ @note MSR_IVY_BRIDGE_C14_PMON_CTR2 is defined as MSR_C14_PMON_CTR2 in SDM.\r
**/\r
#define MSR_IVY_BRIDGE_C14_PMON_CTR2 0x00000ED8\r
\r
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_CTR3);\r
AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_CTR3, Msr);\r
@endcode\r
+ @note MSR_IVY_BRIDGE_C14_PMON_CTR3 is defined as MSR_C14_PMON_CTR3 in SDM.\r
**/\r
#define MSR_IVY_BRIDGE_C14_PMON_CTR3 0x00000ED9\r
\r
Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER1);\r
AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER1, Msr);\r
@endcode\r
+ @note MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER1 is defined as MSR_C14_PMON_BOX_FILTER1 in SDM.\r
**/\r
#define MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER1 0x00000EDA\r
\r