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1 | /** @file\r |
2 | MSR Definitions for Intel processors based on the Silvermont microarchitecture.\r | |
3 | \r | |
4 | Provides defines for Machine Specific Registers(MSR) indexes. Data structures\r | |
5 | are provided for MSRs that contain one or more bit fields. If the MSR value\r | |
6 | returned is a single 32-bit or 64-bit value, then a data structure is not\r | |
7 | provided for that MSR.\r | |
8 | \r | |
9 | Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>\r | |
10 | This program and the accompanying materials\r | |
11 | are licensed and made available under the terms and conditions of the BSD License\r | |
12 | which accompanies this distribution. The full text of the license may be found at\r | |
13 | http://opensource.org/licenses/bsd-license.php\r | |
14 | \r | |
15 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
16 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
17 | \r | |
18 | @par Specification Reference:\r | |
19 | Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,\r | |
20 | December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-4.\r | |
21 | \r | |
22 | **/\r | |
23 | \r | |
24 | #ifndef __SILVERMONT_MSR_H__\r | |
25 | #define __SILVERMONT_MSR_H__\r | |
26 | \r | |
27 | #include <Register/ArchitecturalMsr.h>\r | |
28 | \r | |
29 | /**\r | |
30 | Shared. Model Specific Platform ID (R).\r | |
31 | \r | |
32 | @param ECX MSR_SILVERMONT_PLATFORM_ID (0x00000017)\r | |
33 | @param EAX Lower 32-bits of MSR value.\r | |
34 | Described by the type MSR_SILVERMONT_PLATFORM_ID_REGISTER.\r | |
35 | @param EDX Upper 32-bits of MSR value.\r | |
36 | Described by the type MSR_SILVERMONT_PLATFORM_ID_REGISTER.\r | |
37 | \r | |
38 | <b>Example usage</b>\r | |
39 | @code\r | |
40 | MSR_SILVERMONT_PLATFORM_ID_REGISTER Msr;\r | |
41 | \r | |
42 | Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_PLATFORM_ID);\r | |
43 | @endcode\r | |
44 | **/\r | |
45 | #define MSR_SILVERMONT_PLATFORM_ID 0x00000017\r | |
46 | \r | |
47 | /**\r | |
48 | MSR information returned for MSR index #MSR_SILVERMONT_PLATFORM_ID\r | |
49 | **/\r | |
50 | typedef union {\r | |
51 | ///\r | |
52 | /// Individual bit fields\r | |
53 | ///\r | |
54 | struct {\r | |
55 | UINT32 Reserved1:8;\r | |
56 | ///\r | |
57 | /// [Bits 12:8] Maximum Qualified Ratio (R) The maximum allowed bus ratio.\r | |
58 | ///\r | |
59 | UINT32 MaximumQualifiedRatio:5;\r | |
60 | UINT32 Reserved2:19;\r | |
61 | UINT32 Reserved3:18;\r | |
62 | ///\r | |
63 | /// [Bits 52:50] See Table 35-2.\r | |
64 | ///\r | |
65 | UINT32 PlatformId:3;\r | |
66 | UINT32 Reserved4:11;\r | |
67 | } Bits;\r | |
68 | ///\r | |
69 | /// All bit fields as a 64-bit value\r | |
70 | ///\r | |
71 | UINT64 Uint64;\r | |
72 | } MSR_SILVERMONT_PLATFORM_ID_REGISTER;\r | |
73 | \r | |
74 | \r | |
75 | /**\r | |
76 | Shared. Processor Hard Power-On Configuration (R/W) Enables and disables\r | |
77 | processor features; (R) indicates current processor configuration.\r | |
78 | \r | |
79 | @param ECX MSR_SILVERMONT_EBL_CR_POWERON (0x0000002A)\r | |
80 | @param EAX Lower 32-bits of MSR value.\r | |
81 | Described by the type MSR_SILVERMONT_EBL_CR_POWERON_REGISTER.\r | |
82 | @param EDX Upper 32-bits of MSR value.\r | |
83 | Described by the type MSR_SILVERMONT_EBL_CR_POWERON_REGISTER.\r | |
84 | \r | |
85 | <b>Example usage</b>\r | |
86 | @code\r | |
87 | MSR_SILVERMONT_EBL_CR_POWERON_REGISTER Msr;\r | |
88 | \r | |
89 | Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_EBL_CR_POWERON);\r | |
90 | AsmWriteMsr64 (MSR_SILVERMONT_EBL_CR_POWERON, Msr.Uint64);\r | |
91 | @endcode\r | |
92 | **/\r | |
93 | #define MSR_SILVERMONT_EBL_CR_POWERON 0x0000002A\r | |
94 | \r | |
95 | /**\r | |
96 | MSR information returned for MSR index #MSR_SILVERMONT_EBL_CR_POWERON\r | |
97 | **/\r | |
98 | typedef union {\r | |
99 | ///\r | |
100 | /// Individual bit fields\r | |
101 | ///\r | |
102 | struct {\r | |
103 | UINT32 Reserved1:1;\r | |
104 | ///\r | |
105 | /// [Bit 1] Data Error Checking Enable (R/W) 1 = Enabled; 0 = Disabled\r | |
106 | /// Always 0.\r | |
107 | ///\r | |
108 | UINT32 DataErrorCheckingEnable:1;\r | |
109 | ///\r | |
110 | /// [Bit 2] Response Error Checking Enable (R/W) 1 = Enabled; 0 = Disabled\r | |
111 | /// Always 0.\r | |
112 | ///\r | |
113 | UINT32 ResponseErrorCheckingEnable:1;\r | |
114 | ///\r | |
115 | /// [Bit 3] AERR# Drive Enable (R/W) 1 = Enabled; 0 = Disabled Always 0.\r | |
116 | ///\r | |
117 | UINT32 AERR_DriveEnable:1;\r | |
118 | ///\r | |
119 | /// [Bit 4] BERR# Enable for initiator bus requests (R/W) 1 = Enabled; 0 =\r | |
120 | /// Disabled Always 0.\r | |
121 | ///\r | |
122 | UINT32 BERR_Enable:1;\r | |
123 | UINT32 Reserved2:1;\r | |
124 | UINT32 Reserved3:1;\r | |
125 | ///\r | |
126 | /// [Bit 7] BINIT# Driver Enable (R/W) 1 = Enabled; 0 = Disabled Always 0.\r | |
127 | ///\r | |
128 | UINT32 BINIT_DriverEnable:1;\r | |
129 | UINT32 Reserved4:1;\r | |
130 | ///\r | |
131 | /// [Bit 9] Execute BIST (R/O) 1 = Enabled; 0 = Disabled.\r | |
132 | ///\r | |
133 | UINT32 ExecuteBIST:1;\r | |
134 | ///\r | |
135 | /// [Bit 10] AERR# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled\r | |
136 | /// Always 0.\r | |
137 | ///\r | |
138 | UINT32 AERR_ObservationEnabled:1;\r | |
139 | UINT32 Reserved5:1;\r | |
140 | ///\r | |
141 | /// [Bit 12] BINIT# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled\r | |
142 | /// Always 0.\r | |
143 | ///\r | |
144 | UINT32 BINIT_ObservationEnabled:1;\r | |
145 | UINT32 Reserved6:1;\r | |
146 | ///\r | |
147 | /// [Bit 14] 1 MByte Power on Reset Vector (R/O) 1 = 1 MByte; 0 = 4 GBytes.\r | |
148 | ///\r | |
149 | UINT32 ResetVector:1;\r | |
150 | UINT32 Reserved7:1;\r | |
151 | ///\r | |
152 | /// [Bits 17:16] APIC Cluster ID (R/O) Always 00B.\r | |
153 | ///\r | |
154 | UINT32 APICClusterID:2;\r | |
155 | UINT32 Reserved8:2;\r | |
156 | ///\r | |
157 | /// [Bits 21:20] Symmetric Arbitration ID (R/O) Always 00B.\r | |
158 | ///\r | |
159 | UINT32 SymmetricArbitrationID:2;\r | |
160 | ///\r | |
161 | /// [Bits 26:22] Integer Bus Frequency Ratio (R/O).\r | |
162 | ///\r | |
163 | UINT32 IntegerBusFrequencyRatio:5;\r | |
164 | UINT32 Reserved9:5;\r | |
165 | UINT32 Reserved10:32;\r | |
166 | } Bits;\r | |
167 | ///\r | |
168 | /// All bit fields as a 32-bit value\r | |
169 | ///\r | |
170 | UINT32 Uint32;\r | |
171 | ///\r | |
172 | /// All bit fields as a 64-bit value\r | |
173 | ///\r | |
174 | UINT64 Uint64;\r | |
175 | } MSR_SILVERMONT_EBL_CR_POWERON_REGISTER;\r | |
176 | \r | |
177 | \r | |
178 | /**\r | |
179 | Core. SMI Counter (R/O).\r | |
180 | \r | |
181 | @param ECX MSR_SILVERMONT_SMI_COUNT (0x00000034)\r | |
182 | @param EAX Lower 32-bits of MSR value.\r | |
183 | Described by the type MSR_SILVERMONT_SMI_COUNT_REGISTER.\r | |
184 | @param EDX Upper 32-bits of MSR value.\r | |
185 | Described by the type MSR_SILVERMONT_SMI_COUNT_REGISTER.\r | |
186 | \r | |
187 | <b>Example usage</b>\r | |
188 | @code\r | |
189 | MSR_SILVERMONT_SMI_COUNT_REGISTER Msr;\r | |
190 | \r | |
191 | Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_SMI_COUNT);\r | |
192 | @endcode\r | |
193 | **/\r | |
194 | #define MSR_SILVERMONT_SMI_COUNT 0x00000034\r | |
195 | \r | |
196 | /**\r | |
197 | MSR information returned for MSR index #MSR_SILVERMONT_SMI_COUNT\r | |
198 | **/\r | |
199 | typedef union {\r | |
200 | ///\r | |
201 | /// Individual bit fields\r | |
202 | ///\r | |
203 | struct {\r | |
204 | ///\r | |
205 | /// [Bits 31:0] SMI Count (R/O) Running count of SMI events since last\r | |
206 | /// RESET.\r | |
207 | ///\r | |
208 | UINT32 SMICount:32;\r | |
209 | UINT32 Reserved:32;\r | |
210 | } Bits;\r | |
211 | ///\r | |
212 | /// All bit fields as a 32-bit value\r | |
213 | ///\r | |
214 | UINT32 Uint32;\r | |
215 | ///\r | |
216 | /// All bit fields as a 64-bit value\r | |
217 | ///\r | |
218 | UINT64 Uint64;\r | |
219 | } MSR_SILVERMONT_SMI_COUNT_REGISTER;\r | |
220 | \r | |
221 | \r | |
222 | /**\r | |
223 | Core. Last Branch Record n From IP (R/W) One of eight pairs of last branch\r | |
224 | record registers on the last branch record stack. This part of the stack\r | |
225 | contains pointers to the source instruction for one of the last eight\r | |
226 | branches, exceptions, or interrupts taken by the processor. See also: -\r | |
227 | Last Branch Record Stack TOS at 1C9H - Section 17.12, "Last Branch,\r | |
228 | Interrupt, and Exception Recording (Pentium M Processors).".\r | |
229 | \r | |
230 | @param ECX MSR_SILVERMONT_LASTBRANCH_n_FROM_IP\r | |
231 | @param EAX Lower 32-bits of MSR value.\r | |
232 | @param EDX Upper 32-bits of MSR value.\r | |
233 | \r | |
234 | <b>Example usage</b>\r | |
235 | @code\r | |
236 | UINT64 Msr;\r | |
237 | \r | |
238 | Msr = AsmReadMsr64 (MSR_SILVERMONT_LASTBRANCH_0_FROM_IP);\r | |
239 | AsmWriteMsr64 (MSR_SILVERMONT_LASTBRANCH_0_FROM_IP, Msr);\r | |
240 | @endcode\r | |
241 | @{\r | |
242 | **/\r | |
243 | #define MSR_SILVERMONT_LASTBRANCH_0_FROM_IP 0x00000040\r | |
244 | #define MSR_SILVERMONT_LASTBRANCH_1_FROM_IP 0x00000041\r | |
245 | #define MSR_SILVERMONT_LASTBRANCH_2_FROM_IP 0x00000042\r | |
246 | #define MSR_SILVERMONT_LASTBRANCH_3_FROM_IP 0x00000043\r | |
247 | #define MSR_SILVERMONT_LASTBRANCH_4_FROM_IP 0x00000044\r | |
248 | #define MSR_SILVERMONT_LASTBRANCH_5_FROM_IP 0x00000045\r | |
249 | #define MSR_SILVERMONT_LASTBRANCH_6_FROM_IP 0x00000046\r | |
250 | #define MSR_SILVERMONT_LASTBRANCH_7_FROM_IP 0x00000047\r | |
251 | /// @}\r | |
252 | \r | |
253 | \r | |
254 | /**\r | |
255 | Core. Last Branch Record n To IP (R/W) One of eight pairs of last branch\r | |
256 | record registers on the last branch record stack. This part of the stack\r | |
257 | contains pointers to the destination instruction for one of the last eight\r | |
258 | branches, exceptions, or interrupts taken by the processor.\r | |
259 | \r | |
260 | @param ECX MSR_SILVERMONT_LASTBRANCH_n_TO_IP\r | |
261 | @param EAX Lower 32-bits of MSR value.\r | |
262 | @param EDX Upper 32-bits of MSR value.\r | |
263 | \r | |
264 | <b>Example usage</b>\r | |
265 | @code\r | |
266 | UINT64 Msr;\r | |
267 | \r | |
268 | Msr = AsmReadMsr64 (MSR_SILVERMONT_LASTBRANCH_0_TO_IP);\r | |
269 | AsmWriteMsr64 (MSR_SILVERMONT_LASTBRANCH_0_TO_IP, Msr);\r | |
270 | @endcode\r | |
271 | @{\r | |
272 | **/\r | |
273 | #define MSR_SILVERMONT_LASTBRANCH_0_TO_IP 0x00000060\r | |
274 | #define MSR_SILVERMONT_LASTBRANCH_1_TO_IP 0x00000061\r | |
275 | #define MSR_SILVERMONT_LASTBRANCH_2_TO_IP 0x00000062\r | |
276 | #define MSR_SILVERMONT_LASTBRANCH_3_TO_IP 0x00000063\r | |
277 | #define MSR_SILVERMONT_LASTBRANCH_4_TO_IP 0x00000064\r | |
278 | #define MSR_SILVERMONT_LASTBRANCH_5_TO_IP 0x00000065\r | |
279 | #define MSR_SILVERMONT_LASTBRANCH_6_TO_IP 0x00000066\r | |
280 | #define MSR_SILVERMONT_LASTBRANCH_7_TO_IP 0x00000067\r | |
281 | /// @}\r | |
282 | \r | |
283 | \r | |
284 | /**\r | |
285 | Shared. Scalable Bus Speed(RO) This field indicates the intended scalable\r | |
286 | bus clock speed for processors based on Silvermont microarchitecture:.\r | |
287 | \r | |
288 | @param ECX MSR_SILVERMONT_FSB_FREQ (0x000000CD)\r | |
289 | @param EAX Lower 32-bits of MSR value.\r | |
290 | Described by the type MSR_SILVERMONT_FSB_FREQ_REGISTER.\r | |
291 | @param EDX Upper 32-bits of MSR value.\r | |
292 | Described by the type MSR_SILVERMONT_FSB_FREQ_REGISTER.\r | |
293 | \r | |
294 | <b>Example usage</b>\r | |
295 | @code\r | |
296 | MSR_SILVERMONT_FSB_FREQ_REGISTER Msr;\r | |
297 | \r | |
298 | Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_FSB_FREQ);\r | |
299 | @endcode\r | |
300 | **/\r | |
301 | #define MSR_SILVERMONT_FSB_FREQ 0x000000CD\r | |
302 | \r | |
303 | /**\r | |
304 | MSR information returned for MSR index #MSR_SILVERMONT_FSB_FREQ\r | |
305 | **/\r | |
306 | typedef union {\r | |
307 | ///\r | |
308 | /// Individual bit fields\r | |
309 | ///\r | |
310 | struct {\r | |
311 | ///\r | |
312 | /// [Bits 3:0] Scalable Bus Speed\r | |
313 | ///\r | |
314 | /// Silvermont Processor Family\r | |
315 | /// ---------------------------\r | |
316 | /// 100B: 080.0 MHz\r | |
317 | /// 000B: 083.3 MHz\r | |
318 | /// 001B: 100.0 MHz\r | |
319 | /// 010B: 133.3 MHz\r | |
320 | /// 011B: 116.7 MHz\r | |
321 | ///\r | |
322 | /// Airmont Processor Family\r | |
323 | /// ---------------------------\r | |
324 | /// 0000B: 083.3 MHz\r | |
325 | /// 0001B: 100.0 MHz\r | |
326 | /// 0010B: 133.3 MHz\r | |
327 | /// 0011B: 116.7 MHz\r | |
328 | /// 0100B: 080.0 MHz\r | |
329 | /// 0101B: 093.3 MHz\r | |
330 | /// 0110B: 090.0 MHz\r | |
331 | /// 0111B: 088.9 MHz\r | |
332 | /// 1000B: 087.5 MHz\r | |
333 | ///\r | |
334 | UINT32 ScalableBusSpeed:4;\r | |
335 | UINT32 Reserved1:28;\r | |
336 | UINT32 Reserved2:32;\r | |
337 | } Bits;\r | |
338 | ///\r | |
339 | /// All bit fields as a 32-bit value\r | |
340 | ///\r | |
341 | UINT32 Uint32;\r | |
342 | ///\r | |
343 | /// All bit fields as a 64-bit value\r | |
344 | ///\r | |
345 | UINT64 Uint64;\r | |
346 | } MSR_SILVERMONT_FSB_FREQ_REGISTER;\r | |
347 | \r | |
348 | \r | |
349 | /**\r | |
350 | Shared. C-State Configuration Control (R/W) Note: C-state values are\r | |
351 | processor specific C-state code names, unrelated to MWAIT extension C-state\r | |
352 | parameters or ACPI CStates. See http://biosbits.org.\r | |
353 | \r | |
354 | @param ECX MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL (0x000000E2)\r | |
355 | @param EAX Lower 32-bits of MSR value.\r | |
356 | Described by the type MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL_REGISTER.\r | |
357 | @param EDX Upper 32-bits of MSR value.\r | |
358 | Described by the type MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL_REGISTER.\r | |
359 | \r | |
360 | <b>Example usage</b>\r | |
361 | @code\r | |
362 | MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL_REGISTER Msr;\r | |
363 | \r | |
364 | Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL);\r | |
365 | AsmWriteMsr64 (MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL, Msr.Uint64);\r | |
366 | @endcode\r | |
367 | **/\r | |
368 | #define MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL 0x000000E2\r | |
369 | \r | |
370 | /**\r | |
371 | MSR information returned for MSR index #MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL\r | |
372 | **/\r | |
373 | typedef union {\r | |
374 | ///\r | |
375 | /// Individual bit fields\r | |
376 | ///\r | |
377 | struct {\r | |
378 | ///\r | |
379 | /// [Bits 2:0] Package C-State Limit (R/W) Specifies the lowest\r | |
380 | /// processor-specific C-state code name (consuming the least power). for\r | |
381 | /// the package. The default is set as factory-configured package C-state\r | |
382 | /// limit. The following C-state code name encodings are supported: 000b:\r | |
383 | /// C0 (no package C-sate support) 001b: C1 (Behavior is the same as 000b)\r | |
384 | /// 100b: C4 110b: C6 111b: C7 (Silvermont only).\r | |
385 | ///\r | |
386 | UINT32 Limit:3;\r | |
387 | UINT32 Reserved1:7;\r | |
388 | ///\r | |
389 | /// [Bit 10] I/O MWAIT Redirection Enable (R/W) When set, will map\r | |
390 | /// IO_read instructions sent to IO register specified by\r | |
391 | /// MSR_PMG_IO_CAPTURE_BASE to MWAIT instructions.\r | |
392 | ///\r | |
393 | UINT32 IO_MWAIT:1;\r | |
394 | UINT32 Reserved2:4;\r | |
395 | ///\r | |
396 | /// [Bit 15] CFG Lock (R/WO) When set, lock bits 15:0 of this register\r | |
397 | /// until next reset.\r | |
398 | ///\r | |
399 | UINT32 CFGLock:1;\r | |
400 | UINT32 Reserved3:16;\r | |
401 | UINT32 Reserved4:32;\r | |
402 | } Bits;\r | |
403 | ///\r | |
404 | /// All bit fields as a 32-bit value\r | |
405 | ///\r | |
406 | UINT32 Uint32;\r | |
407 | ///\r | |
408 | /// All bit fields as a 64-bit value\r | |
409 | ///\r | |
410 | UINT64 Uint64;\r | |
411 | } MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL_REGISTER;\r | |
412 | \r | |
413 | \r | |
414 | /**\r | |
415 | Shared. Power Management IO Redirection in C-state (R/W) See\r | |
416 | http://biosbits.org.\r | |
417 | \r | |
418 | @param ECX MSR_SILVERMONT_PMG_IO_CAPTURE_BASE (0x000000E4)\r | |
419 | @param EAX Lower 32-bits of MSR value.\r | |
420 | Described by the type MSR_SILVERMONT_PMG_IO_CAPTURE_BASE_REGISTER.\r | |
421 | @param EDX Upper 32-bits of MSR value.\r | |
422 | Described by the type MSR_SILVERMONT_PMG_IO_CAPTURE_BASE_REGISTER.\r | |
423 | \r | |
424 | <b>Example usage</b>\r | |
425 | @code\r | |
426 | MSR_SILVERMONT_PMG_IO_CAPTURE_BASE_REGISTER Msr;\r | |
427 | \r | |
428 | Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_PMG_IO_CAPTURE_BASE);\r | |
429 | AsmWriteMsr64 (MSR_SILVERMONT_PMG_IO_CAPTURE_BASE, Msr.Uint64);\r | |
430 | @endcode\r | |
431 | **/\r | |
432 | #define MSR_SILVERMONT_PMG_IO_CAPTURE_BASE 0x000000E4\r | |
433 | \r | |
434 | /**\r | |
435 | MSR information returned for MSR index #MSR_SILVERMONT_PMG_IO_CAPTURE_BASE\r | |
436 | **/\r | |
437 | typedef union {\r | |
438 | ///\r | |
439 | /// Individual bit fields\r | |
440 | ///\r | |
441 | struct {\r | |
442 | ///\r | |
443 | /// [Bits 15:0] LVL_2 Base Address (R/W) Specifies the base address\r | |
444 | /// visible to software for IO redirection. If IO MWAIT Redirection is\r | |
445 | /// enabled, reads to this address will be consumed by the power\r | |
446 | /// management logic and decoded to MWAIT instructions. When IO port\r | |
447 | /// address redirection is enabled, this is the IO port address reported\r | |
448 | /// to the OS/software.\r | |
449 | ///\r | |
450 | UINT32 Lvl2Base:16;\r | |
451 | ///\r | |
452 | /// [Bits 18:16] C-state Range (R/W) Specifies the encoding value of the\r | |
453 | /// maximum C-State code name to be included when IO read to MWAIT\r | |
454 | /// redirection is enabled by MSR_PKG_CST_CONFIG_CONTROL[bit10]: 100b - C4\r | |
455 | /// is the max C-State to include 110b - C6 is the max C-State to include\r | |
456 | /// 111b - C7 is the max C-State to include.\r | |
457 | ///\r | |
458 | UINT32 CStateRange:3;\r | |
459 | UINT32 Reserved1:13;\r | |
460 | UINT32 Reserved2:32;\r | |
461 | } Bits;\r | |
462 | ///\r | |
463 | /// All bit fields as a 32-bit value\r | |
464 | ///\r | |
465 | UINT32 Uint32;\r | |
466 | ///\r | |
467 | /// All bit fields as a 64-bit value\r | |
468 | ///\r | |
469 | UINT64 Uint64;\r | |
470 | } MSR_SILVERMONT_PMG_IO_CAPTURE_BASE_REGISTER;\r | |
471 | \r | |
472 | \r | |
473 | /**\r | |
474 | Shared.\r | |
475 | \r | |
476 | @param ECX MSR_SILVERMONT_BBL_CR_CTL3 (0x0000011E)\r | |
477 | @param EAX Lower 32-bits of MSR value.\r | |
478 | Described by the type MSR_SILVERMONT_BBL_CR_CTL3_REGISTER.\r | |
479 | @param EDX Upper 32-bits of MSR value.\r | |
480 | Described by the type MSR_SILVERMONT_BBL_CR_CTL3_REGISTER.\r | |
481 | \r | |
482 | <b>Example usage</b>\r | |
483 | @code\r | |
484 | MSR_SILVERMONT_BBL_CR_CTL3_REGISTER Msr;\r | |
485 | \r | |
486 | Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_BBL_CR_CTL3);\r | |
487 | AsmWriteMsr64 (MSR_SILVERMONT_BBL_CR_CTL3, Msr.Uint64);\r | |
488 | @endcode\r | |
489 | **/\r | |
490 | #define MSR_SILVERMONT_BBL_CR_CTL3 0x0000011E\r | |
491 | \r | |
492 | /**\r | |
493 | MSR information returned for MSR index #MSR_SILVERMONT_BBL_CR_CTL3\r | |
494 | **/\r | |
495 | typedef union {\r | |
496 | ///\r | |
497 | /// Individual bit fields\r | |
498 | ///\r | |
499 | struct {\r | |
500 | ///\r | |
501 | /// [Bit 0] L2 Hardware Enabled (RO) 1 = If the L2 is hardware-enabled 0 =\r | |
502 | /// Indicates if the L2 is hardware-disabled.\r | |
503 | ///\r | |
504 | UINT32 L2HardwareEnabled:1;\r | |
505 | UINT32 Reserved1:7;\r | |
506 | ///\r | |
507 | /// [Bit 8] L2 Enabled. (R/W) 1 = L2 cache has been initialized 0 =\r | |
508 | /// Disabled (default) Until this bit is set the processor will not\r | |
509 | /// respond to the WBINVD instruction or the assertion of the FLUSH# input.\r | |
510 | ///\r | |
511 | UINT32 L2Enabled:1;\r | |
512 | UINT32 Reserved2:14;\r | |
513 | ///\r | |
514 | /// [Bit 23] L2 Not Present (RO) 1. = L2 Present 2. = L2 Not Present.\r | |
515 | ///\r | |
516 | UINT32 L2NotPresent:1;\r | |
517 | UINT32 Reserved3:8;\r | |
518 | UINT32 Reserved4:32;\r | |
519 | } Bits;\r | |
520 | ///\r | |
521 | /// All bit fields as a 32-bit value\r | |
522 | ///\r | |
523 | UINT32 Uint32;\r | |
524 | ///\r | |
525 | /// All bit fields as a 64-bit value\r | |
526 | ///\r | |
527 | UINT64 Uint64;\r | |
528 | } MSR_SILVERMONT_BBL_CR_CTL3_REGISTER;\r | |
529 | \r | |
530 | \r | |
531 | /**\r | |
532 | Core. AES Configuration (RW-L) Privileged post-BIOS agent must provide a #GP\r | |
533 | handler to handle unsuccessful read of this MSR.\r | |
534 | \r | |
535 | @param ECX MSR_SILVERMONT_FEATURE_CONFIG (0x0000013C)\r | |
536 | @param EAX Lower 32-bits of MSR value.\r | |
537 | Described by the type MSR_SILVERMONT_FEATURE_CONFIG_REGISTER.\r | |
538 | @param EDX Upper 32-bits of MSR value.\r | |
539 | Described by the type MSR_SILVERMONT_FEATURE_CONFIG_REGISTER.\r | |
540 | \r | |
541 | <b>Example usage</b>\r | |
542 | @code\r | |
543 | MSR_SILVERMONT_FEATURE_CONFIG_REGISTER Msr;\r | |
544 | \r | |
545 | Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_FEATURE_CONFIG);\r | |
546 | AsmWriteMsr64 (MSR_SILVERMONT_FEATURE_CONFIG, Msr.Uint64);\r | |
547 | @endcode\r | |
548 | **/\r | |
549 | #define MSR_SILVERMONT_FEATURE_CONFIG 0x0000013C\r | |
550 | \r | |
551 | /**\r | |
552 | MSR information returned for MSR index #MSR_SILVERMONT_FEATURE_CONFIG\r | |
553 | **/\r | |
554 | typedef union {\r | |
555 | ///\r | |
556 | /// Individual bit fields\r | |
557 | ///\r | |
558 | struct {\r | |
559 | ///\r | |
560 | /// [Bits 1:0] AES Configuration (RW-L) Upon a successful read of this\r | |
561 | /// MSR, the configuration of AES instruction set availability is as\r | |
562 | /// follows: 11b: AES instructions are not available until next RESET.\r | |
563 | /// otherwise, AES instructions are available. Note, AES instruction set\r | |
564 | /// is not available if read is unsuccessful. If the configuration is not\r | |
565 | /// 01b, AES instruction can be mis-configured if a privileged agent\r | |
566 | /// unintentionally writes 11b.\r | |
567 | ///\r | |
568 | UINT32 AESConfiguration:2;\r | |
569 | UINT32 Reserved1:30;\r | |
570 | UINT32 Reserved2:32;\r | |
571 | } Bits;\r | |
572 | ///\r | |
573 | /// All bit fields as a 32-bit value\r | |
574 | ///\r | |
575 | UINT32 Uint32;\r | |
576 | ///\r | |
577 | /// All bit fields as a 64-bit value\r | |
578 | ///\r | |
579 | UINT64 Uint64;\r | |
580 | } MSR_SILVERMONT_FEATURE_CONFIG_REGISTER;\r | |
581 | \r | |
582 | \r | |
583 | /**\r | |
584 | Enable Misc. Processor Features (R/W) Allows a variety of processor\r | |
585 | functions to be enabled and disabled.\r | |
586 | \r | |
587 | @param ECX MSR_SILVERMONT_IA32_MISC_ENABLE (0x000001A0)\r | |
588 | @param EAX Lower 32-bits of MSR value.\r | |
589 | Described by the type MSR_SILVERMONT_IA32_MISC_ENABLE_REGISTER.\r | |
590 | @param EDX Upper 32-bits of MSR value.\r | |
591 | Described by the type MSR_SILVERMONT_IA32_MISC_ENABLE_REGISTER.\r | |
592 | \r | |
593 | <b>Example usage</b>\r | |
594 | @code\r | |
595 | MSR_SILVERMONT_IA32_MISC_ENABLE_REGISTER Msr;\r | |
596 | \r | |
597 | Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_IA32_MISC_ENABLE);\r | |
598 | AsmWriteMsr64 (MSR_SILVERMONT_IA32_MISC_ENABLE, Msr.Uint64);\r | |
599 | @endcode\r | |
600 | **/\r | |
601 | #define MSR_SILVERMONT_IA32_MISC_ENABLE 0x000001A0\r | |
602 | \r | |
603 | /**\r | |
604 | MSR information returned for MSR index #MSR_SILVERMONT_IA32_MISC_ENABLE\r | |
605 | **/\r | |
606 | typedef union {\r | |
607 | ///\r | |
608 | /// Individual bit fields\r | |
609 | ///\r | |
610 | struct {\r | |
611 | ///\r | |
612 | /// [Bit 0] Core. Fast-Strings Enable See Table 35-2.\r | |
613 | ///\r | |
614 | UINT32 FastStrings:1;\r | |
615 | UINT32 Reserved1:2;\r | |
616 | ///\r | |
617 | /// [Bit 3] Shared. Automatic Thermal Control Circuit Enable (R/W) See\r | |
618 | /// Table 35-2.\r | |
619 | ///\r | |
620 | UINT32 AutomaticThermalControlCircuit:1;\r | |
621 | UINT32 Reserved2:3;\r | |
622 | ///\r | |
623 | /// [Bit 7] Core. Performance Monitoring Available (R) See Table 35-2.\r | |
624 | ///\r | |
625 | UINT32 PerformanceMonitoring:1;\r | |
626 | UINT32 Reserved3:3;\r | |
627 | ///\r | |
628 | /// [Bit 11] Core. Branch Trace Storage Unavailable (RO) See Table 35-2.\r | |
629 | ///\r | |
630 | UINT32 BTS:1;\r | |
631 | ///\r | |
632 | /// [Bit 12] Core. Precise Event Based Sampling Unavailable (RO) See Table\r | |
633 | /// 35-2.\r | |
634 | ///\r | |
635 | UINT32 PEBS:1;\r | |
636 | UINT32 Reserved4:3;\r | |
637 | ///\r | |
638 | /// [Bit 16] Shared. Enhanced Intel SpeedStep Technology Enable (R/W) See\r | |
639 | /// Table 35-2.\r | |
640 | ///\r | |
641 | UINT32 EIST:1;\r | |
642 | UINT32 Reserved5:1;\r | |
643 | ///\r | |
644 | /// [Bit 18] Core. ENABLE MONITOR FSM (R/W) See Table 35-2.\r | |
645 | ///\r | |
646 | UINT32 MONITOR:1;\r | |
647 | UINT32 Reserved6:3;\r | |
648 | ///\r | |
649 | /// [Bit 22] Core. Limit CPUID Maxval (R/W) See Table 35-2.\r | |
650 | ///\r | |
651 | UINT32 LimitCpuidMaxval:1;\r | |
652 | ///\r | |
653 | /// [Bit 23] Shared. xTPR Message Disable (R/W) See Table 35-2.\r | |
654 | ///\r | |
655 | UINT32 xTPR_Message_Disable:1;\r | |
656 | UINT32 Reserved7:8;\r | |
657 | UINT32 Reserved8:2;\r | |
658 | ///\r | |
659 | /// [Bit 34] Core. XD Bit Disable (R/W) See Table 35-2.\r | |
660 | ///\r | |
661 | UINT32 XD:1;\r | |
662 | UINT32 Reserved9:3;\r | |
663 | ///\r | |
664 | /// [Bit 38] Shared. Turbo Mode Disable (R/W) When set to 1 on processors\r | |
665 | /// that support Intel Turbo Boost Technology, the turbo mode feature is\r | |
666 | /// disabled and the IDA_Enable feature flag will be clear (CPUID.06H:\r | |
667 | /// EAX[1]=0). When set to a 0 on processors that support IDA, CPUID.06H:\r | |
668 | /// EAX[1] reports the processor's support of turbo mode is enabled. Note:\r | |
669 | /// the power-on default value is used by BIOS to detect hardware support\r | |
670 | /// of turbo mode. If power-on default value is 1, turbo mode is available\r | |
671 | /// in the processor. If power-on default value is 0, turbo mode is not\r | |
672 | /// available.\r | |
673 | ///\r | |
674 | UINT32 TurboModeDisable:1;\r | |
675 | UINT32 Reserved10:25;\r | |
676 | } Bits;\r | |
677 | ///\r | |
678 | /// All bit fields as a 64-bit value\r | |
679 | ///\r | |
680 | UINT64 Uint64;\r | |
681 | } MSR_SILVERMONT_IA32_MISC_ENABLE_REGISTER;\r | |
682 | \r | |
683 | \r | |
684 | /**\r | |
685 | Package.\r | |
686 | \r | |
687 | @param ECX MSR_SILVERMONT_TEMPERATURE_TARGET (0x000001A2)\r | |
688 | @param EAX Lower 32-bits of MSR value.\r | |
689 | Described by the type MSR_SILVERMONT_TEMPERATURE_TARGET_REGISTER.\r | |
690 | @param EDX Upper 32-bits of MSR value.\r | |
691 | Described by the type MSR_SILVERMONT_TEMPERATURE_TARGET_REGISTER.\r | |
692 | \r | |
693 | <b>Example usage</b>\r | |
694 | @code\r | |
695 | MSR_SILVERMONT_TEMPERATURE_TARGET_REGISTER Msr;\r | |
696 | \r | |
697 | Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_TEMPERATURE_TARGET);\r | |
698 | AsmWriteMsr64 (MSR_SILVERMONT_TEMPERATURE_TARGET, Msr.Uint64);\r | |
699 | @endcode\r | |
700 | **/\r | |
701 | #define MSR_SILVERMONT_TEMPERATURE_TARGET 0x000001A2\r | |
702 | \r | |
703 | /**\r | |
704 | MSR information returned for MSR index #MSR_SILVERMONT_TEMPERATURE_TARGET\r | |
705 | **/\r | |
706 | typedef union {\r | |
707 | ///\r | |
708 | /// Individual bit fields\r | |
709 | ///\r | |
710 | struct {\r | |
711 | UINT32 Reserved1:16;\r | |
712 | ///\r | |
713 | /// [Bits 23:16] Temperature Target (R) The default thermal throttling or\r | |
714 | /// PROCHOT# activation temperature in degree C, The effective temperature\r | |
715 | /// for thermal throttling or PROCHOT# activation is "Temperature Target"\r | |
716 | /// + "Target Offset".\r | |
717 | ///\r | |
718 | UINT32 TemperatureTarget:8;\r | |
719 | ///\r | |
720 | /// [Bits 29:24] Target Offset (R/W) Specifies an offset in degrees C to\r | |
721 | /// adjust the throttling and PROCHOT# activation temperature from the\r | |
722 | /// default target specified in TEMPERATURE_TARGET (bits 23:16).\r | |
723 | ///\r | |
724 | UINT32 TargetOffset:6;\r | |
725 | UINT32 Reserved2:2;\r | |
726 | UINT32 Reserved3:32;\r | |
727 | } Bits;\r | |
728 | ///\r | |
729 | /// All bit fields as a 32-bit value\r | |
730 | ///\r | |
731 | UINT32 Uint32;\r | |
732 | ///\r | |
733 | /// All bit fields as a 64-bit value\r | |
734 | ///\r | |
735 | UINT64 Uint64;\r | |
736 | } MSR_SILVERMONT_TEMPERATURE_TARGET_REGISTER;\r | |
737 | \r | |
738 | \r | |
739 | /**\r | |
740 | Shared. Offcore Response Event Select Register (R/W).\r | |
741 | \r | |
742 | @param ECX MSR_SILVERMONT_OFFCORE_RSP_0 (0x000001A6)\r | |
743 | @param EAX Lower 32-bits of MSR value.\r | |
744 | @param EDX Upper 32-bits of MSR value.\r | |
745 | \r | |
746 | <b>Example usage</b>\r | |
747 | @code\r | |
748 | UINT64 Msr;\r | |
749 | \r | |
750 | Msr = AsmReadMsr64 (MSR_SILVERMONT_OFFCORE_RSP_0);\r | |
751 | AsmWriteMsr64 (MSR_SILVERMONT_OFFCORE_RSP_0, Msr);\r | |
752 | @endcode\r | |
753 | **/\r | |
754 | #define MSR_SILVERMONT_OFFCORE_RSP_0 0x000001A6\r | |
755 | \r | |
756 | \r | |
757 | /**\r | |
758 | Shared. Offcore Response Event Select Register (R/W).\r | |
759 | \r | |
760 | @param ECX MSR_SILVERMONT_OFFCORE_RSP_1 (0x000001A7)\r | |
761 | @param EAX Lower 32-bits of MSR value.\r | |
762 | @param EDX Upper 32-bits of MSR value.\r | |
763 | \r | |
764 | <b>Example usage</b>\r | |
765 | @code\r | |
766 | UINT64 Msr;\r | |
767 | \r | |
768 | Msr = AsmReadMsr64 (MSR_SILVERMONT_OFFCORE_RSP_1);\r | |
769 | AsmWriteMsr64 (MSR_SILVERMONT_OFFCORE_RSP_1, Msr);\r | |
770 | @endcode\r | |
771 | **/\r | |
772 | #define MSR_SILVERMONT_OFFCORE_RSP_1 0x000001A7\r | |
773 | \r | |
774 | \r | |
775 | /**\r | |
776 | Package. Maximum Ratio Limit of Turbo Mode (RW).\r | |
777 | \r | |
778 | @param ECX MSR_SILVERMONT_TURBO_RATIO_LIMIT (0x000001AD)\r | |
779 | @param EAX Lower 32-bits of MSR value.\r | |
780 | Described by the type MSR_SILVERMONT_TURBO_RATIO_LIMIT_REGISTER.\r | |
781 | @param EDX Upper 32-bits of MSR value.\r | |
782 | Described by the type MSR_SILVERMONT_TURBO_RATIO_LIMIT_REGISTER.\r | |
783 | \r | |
784 | <b>Example usage</b>\r | |
785 | @code\r | |
786 | MSR_SILVERMONT_TURBO_RATIO_LIMIT_REGISTER Msr;\r | |
787 | \r | |
788 | Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_TURBO_RATIO_LIMIT);\r | |
789 | AsmWriteMsr64 (MSR_SILVERMONT_TURBO_RATIO_LIMIT, Msr.Uint64);\r | |
790 | @endcode\r | |
791 | **/\r | |
792 | #define MSR_SILVERMONT_TURBO_RATIO_LIMIT 0x000001AD\r | |
793 | \r | |
794 | /**\r | |
795 | MSR information returned for MSR index #MSR_SILVERMONT_TURBO_RATIO_LIMIT\r | |
796 | **/\r | |
797 | typedef union {\r | |
798 | ///\r | |
799 | /// Individual bit fields\r | |
800 | ///\r | |
801 | struct {\r | |
802 | ///\r | |
803 | /// [Bits 7:0] Package. Maximum Ratio Limit for 1C Maximum turbo ratio\r | |
804 | /// limit of 1 core active.\r | |
805 | ///\r | |
806 | UINT32 Maximum1C:8;\r | |
807 | ///\r | |
808 | /// [Bits 15:8] Package. Maximum Ratio Limit for 2C Maximum turbo ratio\r | |
809 | /// limit of 2 core active.\r | |
810 | ///\r | |
811 | UINT32 Maximum2C:8;\r | |
812 | ///\r | |
813 | /// [Bits 23:16] Package. Maximum Ratio Limit for 3C Maximum turbo ratio\r | |
814 | /// limit of 3 core active.\r | |
815 | ///\r | |
816 | UINT32 Maximum3C:8;\r | |
817 | ///\r | |
818 | /// [Bits 31:24] Package. Maximum Ratio Limit for 4C Maximum turbo ratio\r | |
819 | /// limit of 4 core active.\r | |
820 | ///\r | |
821 | UINT32 Maximum4C:8;\r | |
822 | ///\r | |
823 | /// [Bits 39:32] Package. Maximum Ratio Limit for 5C Maximum turbo ratio\r | |
824 | /// limit of 5 core active.\r | |
825 | ///\r | |
826 | UINT32 Maximum5C:8;\r | |
827 | ///\r | |
828 | /// [Bits 47:40] Package. Maximum Ratio Limit for 6C Maximum turbo ratio\r | |
829 | /// limit of 6 core active.\r | |
830 | ///\r | |
831 | UINT32 Maximum6C:8;\r | |
832 | ///\r | |
833 | /// [Bits 55:48] Package. Maximum Ratio Limit for 7C Maximum turbo ratio\r | |
834 | /// limit of 7 core active.\r | |
835 | ///\r | |
836 | UINT32 Maximum7C:8;\r | |
837 | ///\r | |
838 | /// [Bits 63:56] Package. Maximum Ratio Limit for 8C Maximum turbo ratio\r | |
839 | /// limit of 8 core active.\r | |
840 | ///\r | |
841 | UINT32 Maximum8C:8;\r | |
842 | } Bits;\r | |
843 | ///\r | |
844 | /// All bit fields as a 64-bit value\r | |
845 | ///\r | |
846 | UINT64 Uint64;\r | |
847 | } MSR_SILVERMONT_TURBO_RATIO_LIMIT_REGISTER;\r | |
848 | \r | |
849 | \r | |
850 | /**\r | |
851 | Core. Last Branch Record Stack TOS (R/W) Contains an index (bits 0-2) that\r | |
852 | points to the MSR containing the most recent branch record. See\r | |
853 | MSR_LASTBRANCH_0_FROM_IP (at 40H).\r | |
854 | \r | |
855 | @param ECX MSR_SILVERMONT_LASTBRANCH_TOS (0x000001C9)\r | |
856 | @param EAX Lower 32-bits of MSR value.\r | |
857 | @param EDX Upper 32-bits of MSR value.\r | |
858 | \r | |
859 | <b>Example usage</b>\r | |
860 | @code\r | |
861 | UINT64 Msr;\r | |
862 | \r | |
863 | Msr = AsmReadMsr64 (MSR_SILVERMONT_LASTBRANCH_TOS);\r | |
864 | AsmWriteMsr64 (MSR_SILVERMONT_LASTBRANCH_TOS, Msr);\r | |
865 | @endcode\r | |
866 | **/\r | |
867 | #define MSR_SILVERMONT_LASTBRANCH_TOS 0x000001C9\r | |
868 | \r | |
869 | \r | |
870 | /**\r | |
871 | Core. Last Exception Record From Linear IP (R) Contains a pointer to the\r | |
872 | last branch instruction that the processor executed prior to the last\r | |
873 | exception that was generated or the last interrupt that was handled.\r | |
874 | \r | |
875 | @param ECX MSR_SILVERMONT_LER_FROM_LIP (0x000001DD)\r | |
876 | @param EAX Lower 32-bits of MSR value.\r | |
877 | @param EDX Upper 32-bits of MSR value.\r | |
878 | \r | |
879 | <b>Example usage</b>\r | |
880 | @code\r | |
881 | UINT64 Msr;\r | |
882 | \r | |
883 | Msr = AsmReadMsr64 (MSR_SILVERMONT_LER_FROM_LIP);\r | |
884 | @endcode\r | |
885 | **/\r | |
886 | #define MSR_SILVERMONT_LER_FROM_LIP 0x000001DD\r | |
887 | \r | |
888 | \r | |
889 | /**\r | |
890 | Core. Last Exception Record To Linear IP (R) This area contains a pointer\r | |
891 | to the target of the last branch instruction that the processor executed\r | |
892 | prior to the last exception that was generated or the last interrupt that\r | |
893 | was handled.\r | |
894 | \r | |
895 | @param ECX MSR_SILVERMONT_LER_TO_LIP (0x000001DE)\r | |
896 | @param EAX Lower 32-bits of MSR value.\r | |
897 | @param EDX Upper 32-bits of MSR value.\r | |
898 | \r | |
899 | <b>Example usage</b>\r | |
900 | @code\r | |
901 | UINT64 Msr;\r | |
902 | \r | |
903 | Msr = AsmReadMsr64 (MSR_SILVERMONT_LER_TO_LIP);\r | |
904 | @endcode\r | |
905 | **/\r | |
906 | #define MSR_SILVERMONT_LER_TO_LIP 0x000001DE\r | |
907 | \r | |
908 | \r | |
909 | /**\r | |
910 | Core. See Table 35-2. See Section 18.4.2, "Global Counter Control\r | |
911 | Facilities.".\r | |
912 | \r | |
913 | @param ECX MSR_SILVERMONT_IA32_PERF_GLOBAL_STAUS (0x0000038E)\r | |
914 | @param EAX Lower 32-bits of MSR value.\r | |
915 | @param EDX Upper 32-bits of MSR value.\r | |
916 | \r | |
917 | <b>Example usage</b>\r | |
918 | @code\r | |
919 | UINT64 Msr;\r | |
920 | \r | |
921 | Msr = AsmReadMsr64 (MSR_SILVERMONT_IA32_PERF_GLOBAL_STAUS);\r | |
922 | AsmWriteMsr64 (MSR_SILVERMONT_IA32_PERF_GLOBAL_STAUS, Msr);\r | |
923 | @endcode\r | |
924 | **/\r | |
925 | #define MSR_SILVERMONT_IA32_PERF_GLOBAL_STAUS 0x0000038E\r | |
926 | \r | |
927 | \r | |
928 | /**\r | |
929 | Core. See Table 35-2. See Section 18.4.4, "Precise Event Based Sampling\r | |
930 | (PEBS).".\r | |
931 | \r | |
932 | @param ECX MSR_SILVERMONT_PEBS_ENABLE (0x000003F1)\r | |
933 | @param EAX Lower 32-bits of MSR value.\r | |
934 | Described by the type MSR_SILVERMONT_PEBS_ENABLE_REGISTER.\r | |
935 | @param EDX Upper 32-bits of MSR value.\r | |
936 | Described by the type MSR_SILVERMONT_PEBS_ENABLE_REGISTER.\r | |
937 | \r | |
938 | <b>Example usage</b>\r | |
939 | @code\r | |
940 | MSR_SILVERMONT_PEBS_ENABLE_REGISTER Msr;\r | |
941 | \r | |
942 | Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_PEBS_ENABLE);\r | |
943 | AsmWriteMsr64 (MSR_SILVERMONT_PEBS_ENABLE, Msr.Uint64);\r | |
944 | @endcode\r | |
945 | **/\r | |
946 | #define MSR_SILVERMONT_PEBS_ENABLE 0x000003F1\r | |
947 | \r | |
948 | /**\r | |
949 | MSR information returned for MSR index #MSR_SILVERMONT_PEBS_ENABLE\r | |
950 | **/\r | |
951 | typedef union {\r | |
952 | ///\r | |
953 | /// Individual bit fields\r | |
954 | ///\r | |
955 | struct {\r | |
956 | ///\r | |
957 | /// [Bit 0] Enable PEBS on IA32_PMC0. (R/W).\r | |
958 | ///\r | |
959 | UINT32 PEBS:1;\r | |
960 | UINT32 Reserved1:31;\r | |
961 | UINT32 Reserved2:32;\r | |
962 | } Bits;\r | |
963 | ///\r | |
964 | /// All bit fields as a 32-bit value\r | |
965 | ///\r | |
966 | UINT32 Uint32;\r | |
967 | ///\r | |
968 | /// All bit fields as a 64-bit value\r | |
969 | ///\r | |
970 | UINT64 Uint64;\r | |
971 | } MSR_SILVERMONT_PEBS_ENABLE_REGISTER;\r | |
972 | \r | |
973 | \r | |
974 | /**\r | |
975 | Package. Note: C-state values are processor specific C-state code names,\r | |
976 | unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C6\r | |
977 | Residency Counter. (R/O) Value since last reset that this package is in\r | |
978 | processor-specific C6 states. Counts at the TSC Frequency.\r | |
979 | \r | |
980 | @param ECX MSR_SILVERMONT_PKG_C6_RESIDENCY (0x000003FA)\r | |
981 | @param EAX Lower 32-bits of MSR value.\r | |
982 | @param EDX Upper 32-bits of MSR value.\r | |
983 | \r | |
984 | <b>Example usage</b>\r | |
985 | @code\r | |
986 | UINT64 Msr;\r | |
987 | \r | |
988 | Msr = AsmReadMsr64 (MSR_SILVERMONT_PKG_C6_RESIDENCY);\r | |
989 | AsmWriteMsr64 (MSR_SILVERMONT_PKG_C6_RESIDENCY, Msr);\r | |
990 | @endcode\r | |
991 | **/\r | |
992 | #define MSR_SILVERMONT_PKG_C6_RESIDENCY 0x000003FA\r | |
993 | \r | |
994 | \r | |
995 | /**\r | |
996 | Core. Note: C-state values are processor specific C-state code names,\r | |
997 | unrelated to MWAIT extension C-state parameters or ACPI CStates. CORE C6\r | |
998 | Residency Counter. (R/O) Value since last reset that this core is in\r | |
999 | processor-specific C6 states. Counts at the TSC Frequency.\r | |
1000 | \r | |
1001 | @param ECX MSR_SILVERMONT_CORE_C6_RESIDENCY (0x000003FD)\r | |
1002 | @param EAX Lower 32-bits of MSR value.\r | |
1003 | @param EDX Upper 32-bits of MSR value.\r | |
1004 | \r | |
1005 | <b>Example usage</b>\r | |
1006 | @code\r | |
1007 | UINT64 Msr;\r | |
1008 | \r | |
1009 | Msr = AsmReadMsr64 (MSR_SILVERMONT_CORE_C6_RESIDENCY);\r | |
1010 | AsmWriteMsr64 (MSR_SILVERMONT_CORE_C6_RESIDENCY, Msr);\r | |
1011 | @endcode\r | |
1012 | **/\r | |
1013 | #define MSR_SILVERMONT_CORE_C6_RESIDENCY 0x000003FD\r | |
1014 | \r | |
1015 | \r | |
1016 | /**\r | |
1017 | Core. See Section 15.3.2.1, "IA32_MCi_CTL MSRs.".\r | |
1018 | \r | |
1019 | @param ECX MSR_SILVERMONT_MCi_CTL\r | |
1020 | @param EAX Lower 32-bits of MSR value.\r | |
1021 | @param EDX Upper 32-bits of MSR value.\r | |
1022 | \r | |
1023 | <b>Example usage</b>\r | |
1024 | @code\r | |
1025 | UINT64 Msr;\r | |
1026 | \r | |
1027 | Msr = AsmReadMsr64 (MSR_SILVERMONT_MC3_CTL);\r | |
1028 | AsmWriteMsr64 (MSR_SILVERMONT_MC3_CTL, Msr);\r | |
1029 | @endcode\r | |
1030 | @{\r | |
1031 | **/\r | |
1032 | #define MSR_SILVERMONT_MC3_CTL 0x0000040C\r | |
1033 | #define MSR_SILVERMONT_MC4_CTL 0x00000410\r | |
1034 | #define MSR_SILVERMONT_MC5_CTL 0x00000414\r | |
1035 | /// @}\r | |
1036 | \r | |
1037 | \r | |
1038 | /**\r | |
1039 | Core. See Section 15.3.2.2, "IA32_MCi_STATUS MSRS.".\r | |
1040 | \r | |
1041 | @param ECX MSR_SILVERMONT_MCi_STATUS\r | |
1042 | @param EAX Lower 32-bits of MSR value.\r | |
1043 | @param EDX Upper 32-bits of MSR value.\r | |
1044 | \r | |
1045 | <b>Example usage</b>\r | |
1046 | @code\r | |
1047 | UINT64 Msr;\r | |
1048 | \r | |
1049 | Msr = AsmReadMsr64 (MSR_SILVERMONT_MC3_STATUS);\r | |
1050 | AsmWriteMsr64 (MSR_SILVERMONT_MC3_STATUS, Msr);\r | |
1051 | @endcode\r | |
1052 | @{\r | |
1053 | **/\r | |
1054 | #define MSR_SILVERMONT_MC3_STATUS 0x0000040D\r | |
1055 | #define MSR_SILVERMONT_MC4_STATUS 0x00000411\r | |
1056 | #define MSR_SILVERMONT_MC5_STATUS 0x00000415\r | |
1057 | /// @}\r | |
1058 | \r | |
1059 | \r | |
1060 | /**\r | |
1061 | Core. See Section 15.3.2.3, "IA32_MCi_ADDR MSRs." The MSR_MCi_ADDR register\r | |
1062 | is either not implemented or contains no address if the ADDRV flag in the\r | |
1063 | MSR_MCi_STATUS register is clear. When not implemented in the processor, all\r | |
1064 | reads and writes to this MSR will cause a general-protection exception.\r | |
1065 | \r | |
1066 | @param ECX MSR_SILVERMONT_MCi_ADDR\r | |
1067 | @param EAX Lower 32-bits of MSR value.\r | |
1068 | @param EDX Upper 32-bits of MSR value.\r | |
1069 | \r | |
1070 | <b>Example usage</b>\r | |
1071 | @code\r | |
1072 | UINT64 Msr;\r | |
1073 | \r | |
1074 | Msr = AsmReadMsr64 (MSR_SILVERMONT_MC3_ADDR);\r | |
1075 | AsmWriteMsr64 (MSR_SILVERMONT_MC3_ADDR, Msr);\r | |
1076 | @endcode\r | |
1077 | @{\r | |
1078 | **/\r | |
1079 | #define MSR_SILVERMONT_MC3_ADDR 0x0000040E\r | |
1080 | #define MSR_SILVERMONT_MC4_ADDR 0x00000412\r | |
1081 | #define MSR_SILVERMONT_MC5_ADDR 0x00000416\r | |
1082 | /// @}\r | |
1083 | \r | |
1084 | \r | |
1085 | /**\r | |
1086 | Core. Capability Reporting Register of EPT and VPID (R/O) See Table 35-2.\r | |
1087 | \r | |
1088 | @param ECX MSR_SILVERMONT_IA32_VMX_EPT_VPID_ENUM (0x0000048C)\r | |
1089 | @param EAX Lower 32-bits of MSR value.\r | |
1090 | @param EDX Upper 32-bits of MSR value.\r | |
1091 | \r | |
1092 | <b>Example usage</b>\r | |
1093 | @code\r | |
1094 | UINT64 Msr;\r | |
1095 | \r | |
1096 | Msr = AsmReadMsr64 (MSR_SILVERMONT_IA32_VMX_EPT_VPID_ENUM);\r | |
1097 | @endcode\r | |
1098 | **/\r | |
1099 | #define MSR_SILVERMONT_IA32_VMX_EPT_VPID_ENUM 0x0000048C\r | |
1100 | \r | |
1101 | \r | |
1102 | /**\r | |
1103 | Core. Capability Reporting Register of VM-function Controls (R/O) See Table\r | |
1104 | 35-2.\r | |
1105 | \r | |
1106 | @param ECX MSR_SILVERMONT_IA32_VMX_FMFUNC (0x00000491)\r | |
1107 | @param EAX Lower 32-bits of MSR value.\r | |
1108 | @param EDX Upper 32-bits of MSR value.\r | |
1109 | \r | |
1110 | <b>Example usage</b>\r | |
1111 | @code\r | |
1112 | UINT64 Msr;\r | |
1113 | \r | |
1114 | Msr = AsmReadMsr64 (MSR_SILVERMONT_IA32_VMX_FMFUNC);\r | |
1115 | @endcode\r | |
1116 | **/\r | |
1117 | #define MSR_SILVERMONT_IA32_VMX_FMFUNC 0x00000491\r | |
1118 | \r | |
1119 | \r | |
1120 | /**\r | |
1121 | Core. Note: C-state values are processor specific C-state code names,\r | |
1122 | unrelated to MWAIT extension C-state parameters or ACPI CStates. CORE C1\r | |
1123 | Residency Counter. (R/O) Value since last reset that this core is in\r | |
1124 | processor-specific C1 states. Counts at the TSC frequency.\r | |
1125 | \r | |
1126 | @param ECX MSR_SILVERMONT_CORE_C1_RESIDENCY (0x00000660)\r | |
1127 | @param EAX Lower 32-bits of MSR value.\r | |
1128 | @param EDX Upper 32-bits of MSR value.\r | |
1129 | \r | |
1130 | <b>Example usage</b>\r | |
1131 | @code\r | |
1132 | UINT64 Msr;\r | |
1133 | \r | |
1134 | Msr = AsmReadMsr64 (MSR_SILVERMONT_CORE_C1_RESIDENCY);\r | |
1135 | AsmWriteMsr64 (MSR_SILVERMONT_CORE_C1_RESIDENCY, Msr);\r | |
1136 | @endcode\r | |
1137 | **/\r | |
1138 | #define MSR_SILVERMONT_CORE_C1_RESIDENCY 0x00000660\r | |
1139 | \r | |
1140 | \r | |
1141 | /**\r | |
1142 | Package. Unit Multipliers used in RAPL Interfaces (R/O) See Section 14.9.1,\r | |
1143 | "RAPL Interfaces.".\r | |
1144 | \r | |
1145 | @param ECX MSR_SILVERMONT_RAPL_POWER_UNIT (0x00000606)\r | |
1146 | @param EAX Lower 32-bits of MSR value.\r | |
1147 | Described by the type MSR_SILVERMONT_RAPL_POWER_UNIT_REGISTER.\r | |
1148 | @param EDX Upper 32-bits of MSR value.\r | |
1149 | Described by the type MSR_SILVERMONT_RAPL_POWER_UNIT_REGISTER.\r | |
1150 | \r | |
1151 | <b>Example usage</b>\r | |
1152 | @code\r | |
1153 | MSR_SILVERMONT_RAPL_POWER_UNIT_REGISTER Msr;\r | |
1154 | \r | |
1155 | Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_RAPL_POWER_UNIT);\r | |
1156 | @endcode\r | |
1157 | **/\r | |
1158 | #define MSR_SILVERMONT_RAPL_POWER_UNIT 0x00000606\r | |
1159 | \r | |
1160 | /**\r | |
1161 | MSR information returned for MSR index #MSR_SILVERMONT_RAPL_POWER_UNIT\r | |
1162 | **/\r | |
1163 | typedef union {\r | |
1164 | ///\r | |
1165 | /// Individual bit fields\r | |
1166 | ///\r | |
1167 | struct {\r | |
1168 | ///\r | |
1169 | /// [Bits 3:0] Power Units. Power related information (in milliWatts) is\r | |
1170 | /// based on the multiplier, 2^PU; where PU is an unsigned integer\r | |
1171 | /// represented by bits 3:0. Default value is 0101b, indicating power unit\r | |
1172 | /// is in 32 milliWatts increment.\r | |
1173 | ///\r | |
1174 | UINT32 PowerUnits:4;\r | |
1175 | UINT32 Reserved1:4;\r | |
1176 | ///\r | |
1177 | /// [Bits 12:8] Energy Status Units. Energy related information (in\r | |
1178 | /// microJoules) is based on the multiplier, 2^ESU; where ESU is an\r | |
1179 | /// unsigned integer represented by bits 12:8. Default value is 00101b,\r | |
1180 | /// indicating energy unit is in 32 microJoules increment.\r | |
1181 | ///\r | |
1182 | UINT32 EnergyStatusUnits:5;\r | |
1183 | UINT32 Reserved2:3;\r | |
1184 | ///\r | |
1185 | /// [Bits 19:16] Time Unit. The value is 0000b, indicating time unit is in\r | |
1186 | /// one second.\r | |
1187 | ///\r | |
1188 | UINT32 TimeUnits:4;\r | |
1189 | UINT32 Reserved3:12;\r | |
1190 | UINT32 Reserved4:32;\r | |
1191 | } Bits;\r | |
1192 | ///\r | |
1193 | /// All bit fields as a 32-bit value\r | |
1194 | ///\r | |
1195 | UINT32 Uint32;\r | |
1196 | ///\r | |
1197 | /// All bit fields as a 64-bit value\r | |
1198 | ///\r | |
1199 | UINT64 Uint64;\r | |
1200 | } MSR_SILVERMONT_RAPL_POWER_UNIT_REGISTER;\r | |
1201 | \r | |
1202 | \r | |
1203 | /**\r | |
1204 | Package. PKG RAPL Power Limit Control (R/W).\r | |
1205 | \r | |
1206 | @param ECX MSR_SILVERMONT_PKG_POWER_LIMIT (0x00000610)\r | |
1207 | @param EAX Lower 32-bits of MSR value.\r | |
1208 | Described by the type MSR_SILVERMONT_PKG_POWER_LIMIT_REGISTER.\r | |
1209 | @param EDX Upper 32-bits of MSR value.\r | |
1210 | Described by the type MSR_SILVERMONT_PKG_POWER_LIMIT_REGISTER.\r | |
1211 | \r | |
1212 | <b>Example usage</b>\r | |
1213 | @code\r | |
1214 | MSR_SILVERMONT_PKG_POWER_LIMIT_REGISTER Msr;\r | |
1215 | \r | |
1216 | Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_PKG_POWER_LIMIT);\r | |
1217 | AsmWriteMsr64 (MSR_SILVERMONT_PKG_POWER_LIMIT, Msr.Uint64);\r | |
1218 | @endcode\r | |
1219 | **/\r | |
1220 | #define MSR_SILVERMONT_PKG_POWER_LIMIT 0x00000610\r | |
1221 | \r | |
1222 | /**\r | |
1223 | MSR information returned for MSR index #MSR_SILVERMONT_PKG_POWER_LIMIT\r | |
1224 | **/\r | |
1225 | typedef union {\r | |
1226 | ///\r | |
1227 | /// Individual bit fields\r | |
1228 | ///\r | |
1229 | struct {\r | |
1230 | ///\r | |
1231 | /// [Bits 14:0] Package Power Limit #1. (R/W) See Section 14.9.3, "Package\r | |
1232 | /// RAPL Domain." and MSR_RAPL_POWER_UNIT in Table 35-7.\r | |
1233 | ///\r | |
1234 | UINT32 Limit:15;\r | |
1235 | ///\r | |
1236 | /// [Bit 15] Enable Power Limit #1. (R/W) See Section 14.9.3, "Package\r | |
1237 | /// RAPL Domain.".\r | |
1238 | ///\r | |
1239 | UINT32 Enable:1;\r | |
1240 | ///\r | |
1241 | /// [Bit 16] Package Clamping Limitation #1. (R/W) See Section 14.9.3,\r | |
1242 | /// "Package RAPL Domain.".\r | |
1243 | ///\r | |
1244 | UINT32 ClampingLimit:1;\r | |
1245 | ///\r | |
1246 | /// [Bits 23:17] Time Window for Power Limit #1. (R/W) in unit of second.\r | |
1247 | /// If 0 is specified in bits [23:17], defaults to 1 second window.\r | |
1248 | ///\r | |
1249 | UINT32 Time:7;\r | |
1250 | UINT32 Reserved1:8;\r | |
1251 | UINT32 Reserved2:32;\r | |
1252 | } Bits;\r | |
1253 | ///\r | |
1254 | /// All bit fields as a 32-bit value\r | |
1255 | ///\r | |
1256 | UINT32 Uint32;\r | |
1257 | ///\r | |
1258 | /// All bit fields as a 64-bit value\r | |
1259 | ///\r | |
1260 | UINT64 Uint64;\r | |
1261 | } MSR_SILVERMONT_PKG_POWER_LIMIT_REGISTER;\r | |
1262 | \r | |
1263 | \r | |
1264 | /**\r | |
1265 | Package. PKG Energy Status (R/O) See Section 14.9.3, "Package RAPL Domain."\r | |
1266 | and MSR_RAPL_POWER_UNIT in Table 35-7.\r | |
1267 | \r | |
1268 | @param ECX MSR_SILVERMONT_PKG_ENERGY_STATUS (0x00000611)\r | |
1269 | @param EAX Lower 32-bits of MSR value.\r | |
1270 | @param EDX Upper 32-bits of MSR value.\r | |
1271 | \r | |
1272 | <b>Example usage</b>\r | |
1273 | @code\r | |
1274 | UINT64 Msr;\r | |
1275 | \r | |
1276 | Msr = AsmReadMsr64 (MSR_SILVERMONT_PKG_ENERGY_STATUS);\r | |
1277 | @endcode\r | |
1278 | **/\r | |
1279 | #define MSR_SILVERMONT_PKG_ENERGY_STATUS 0x00000611\r | |
1280 | \r | |
1281 | \r | |
1282 | /**\r | |
1283 | Package. PP0 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL\r | |
1284 | Domains." and MSR_RAPL_POWER_UNIT in Table 35-7.\r | |
1285 | \r | |
1286 | @param ECX MSR_SILVERMONT_PP0_ENERGY_STATUS (0x00000639)\r | |
1287 | @param EAX Lower 32-bits of MSR value.\r | |
1288 | @param EDX Upper 32-bits of MSR value.\r | |
1289 | \r | |
1290 | <b>Example usage</b>\r | |
1291 | @code\r | |
1292 | UINT64 Msr;\r | |
1293 | \r | |
1294 | Msr = AsmReadMsr64 (MSR_SILVERMONT_PP0_ENERGY_STATUS);\r | |
1295 | @endcode\r | |
1296 | **/\r | |
1297 | #define MSR_SILVERMONT_PP0_ENERGY_STATUS 0x00000639\r | |
1298 | \r | |
1299 | \r | |
1300 | /**\r | |
1301 | Package. Core C6 demotion policy config MSR. Controls per-core C6 demotion\r | |
1302 | policy. Writing a value of 0 disables core level HW demotion policy.\r | |
1303 | \r | |
1304 | @param ECX MSR_SILVERMONT_CC6_DEMOTION_POLICY_CONFIG (0x00000668)\r | |
1305 | @param EAX Lower 32-bits of MSR value.\r | |
1306 | @param EDX Upper 32-bits of MSR value.\r | |
1307 | \r | |
1308 | <b>Example usage</b>\r | |
1309 | @code\r | |
1310 | UINT64 Msr;\r | |
1311 | \r | |
1312 | Msr = AsmReadMsr64 (MSR_SILVERMONT_CC6_DEMOTION_POLICY_CONFIG);\r | |
1313 | AsmWriteMsr64 (MSR_SILVERMONT_CC6_DEMOTION_POLICY_CONFIG, Msr);\r | |
1314 | @endcode\r | |
1315 | **/\r | |
1316 | #define MSR_SILVERMONT_CC6_DEMOTION_POLICY_CONFIG 0x00000668\r | |
1317 | \r | |
1318 | \r | |
1319 | /**\r | |
1320 | Package. Module C6 demotion policy config MSR. Controls module (i.e. two\r | |
1321 | cores sharing the second-level cache) C6 demotion policy. Writing a value of\r | |
1322 | 0 disables module level HW demotion policy.\r | |
1323 | \r | |
1324 | @param ECX MSR_SILVERMONT_MC6_DEMOTION_POLICY_CONFIG (0x00000669)\r | |
1325 | @param EAX Lower 32-bits of MSR value.\r | |
1326 | @param EDX Upper 32-bits of MSR value.\r | |
1327 | \r | |
1328 | <b>Example usage</b>\r | |
1329 | @code\r | |
1330 | UINT64 Msr;\r | |
1331 | \r | |
1332 | Msr = AsmReadMsr64 (MSR_SILVERMONT_MC6_DEMOTION_POLICY_CONFIG);\r | |
1333 | AsmWriteMsr64 (MSR_SILVERMONT_MC6_DEMOTION_POLICY_CONFIG, Msr);\r | |
1334 | @endcode\r | |
1335 | **/\r | |
1336 | #define MSR_SILVERMONT_MC6_DEMOTION_POLICY_CONFIG 0x00000669\r | |
1337 | \r | |
1338 | \r | |
1339 | /**\r | |
1340 | Module. Module C6 Residency Counter (R/0) Note: C-state values are processor\r | |
1341 | specific C-state code names, unrelated to MWAIT extension C-state parameters\r | |
1342 | or ACPI CStates. Time that this module is in module-specific C6 states since\r | |
1343 | last reset. Counts at 1 Mhz frequency.\r | |
1344 | \r | |
1345 | @param ECX MSR_SILVERMONT_MC6_RESIDENCY_COUNTER (0x00000664)\r | |
1346 | @param EAX Lower 32-bits of MSR value.\r | |
1347 | @param EDX Upper 32-bits of MSR value.\r | |
1348 | \r | |
1349 | <b>Example usage</b>\r | |
1350 | @code\r | |
1351 | UINT64 Msr;\r | |
1352 | \r | |
1353 | Msr = AsmReadMsr64 (MSR_SILVERMONT_MC6_RESIDENCY_COUNTER);\r | |
1354 | @endcode\r | |
1355 | **/\r | |
1356 | #define MSR_SILVERMONT_MC6_RESIDENCY_COUNTER 0x00000664\r | |
1357 | \r | |
1358 | \r | |
1359 | /**\r | |
1360 | Package. PKG RAPL Parameter (R/0).\r | |
1361 | \r | |
1362 | @param ECX MSR_SILVERMONT_PKG_POWER_INFO (0x0000066E)\r | |
1363 | @param EAX Lower 32-bits of MSR value.\r | |
1364 | Described by the type MSR_SILVERMONT_PKG_POWER_INFO_REGISTER.\r | |
1365 | @param EDX Upper 32-bits of MSR value.\r | |
1366 | Described by the type MSR_SILVERMONT_PKG_POWER_INFO_REGISTER.\r | |
1367 | \r | |
1368 | <b>Example usage</b>\r | |
1369 | @code\r | |
1370 | MSR_SILVERMONT_PKG_POWER_INFO_REGISTER Msr;\r | |
1371 | \r | |
1372 | Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_PKG_POWER_INFO);\r | |
1373 | @endcode\r | |
1374 | **/\r | |
1375 | #define MSR_SILVERMONT_PKG_POWER_INFO 0x0000066E\r | |
1376 | \r | |
1377 | /**\r | |
1378 | MSR information returned for MSR index #MSR_SILVERMONT_PKG_POWER_INFO\r | |
1379 | **/\r | |
1380 | typedef union {\r | |
1381 | ///\r | |
1382 | /// Individual bit fields\r | |
1383 | ///\r | |
1384 | struct {\r | |
1385 | ///\r | |
1386 | /// [Bits 14:0] Thermal Spec Power. (R/0) The unsigned integer value is\r | |
1387 | /// the equivalent of thermal specification power of the package domain.\r | |
1388 | /// The unit of this field is specified by the "Power Units" field of\r | |
1389 | /// MSR_RAPL_POWER_UNIT.\r | |
1390 | ///\r | |
1391 | UINT32 ThermalSpecPower:15;\r | |
1392 | UINT32 Reserved1:17;\r | |
1393 | UINT32 Reserved2:32;\r | |
1394 | } Bits;\r | |
1395 | ///\r | |
1396 | /// All bit fields as a 32-bit value\r | |
1397 | ///\r | |
1398 | UINT32 Uint32;\r | |
1399 | ///\r | |
1400 | /// All bit fields as a 64-bit value\r | |
1401 | ///\r | |
1402 | UINT64 Uint64;\r | |
1403 | } MSR_SILVERMONT_PKG_POWER_INFO_REGISTER;\r | |
1404 | \r | |
1405 | \r | |
1406 | /**\r | |
1407 | Package. PP0 RAPL Power Limit Control (R/W).\r | |
1408 | \r | |
1409 | @param ECX MSR_SILVERMONT_PP0_POWER_LIMIT (0x00000638)\r | |
1410 | @param EAX Lower 32-bits of MSR value.\r | |
1411 | Described by the type MSR_SILVERMONT_PP0_POWER_LIMIT_REGISTER.\r | |
1412 | @param EDX Upper 32-bits of MSR value.\r | |
1413 | Described by the type MSR_SILVERMONT_PP0_POWER_LIMIT_REGISTER.\r | |
1414 | \r | |
1415 | <b>Example usage</b>\r | |
1416 | @code\r | |
1417 | MSR_SILVERMONT_PP0_POWER_LIMIT_REGISTER Msr;\r | |
1418 | \r | |
1419 | Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_PP0_POWER_LIMIT);\r | |
1420 | AsmWriteMsr64 (MSR_SILVERMONT_PP0_POWER_LIMIT, Msr.Uint64);\r | |
1421 | @endcode\r | |
1422 | **/\r | |
1423 | #define MSR_SILVERMONT_PP0_POWER_LIMIT 0x00000638\r | |
1424 | \r | |
1425 | /**\r | |
1426 | MSR information returned for MSR index #MSR_SILVERMONT_PP0_POWER_LIMIT\r | |
1427 | **/\r | |
1428 | typedef union {\r | |
1429 | ///\r | |
1430 | /// Individual bit fields\r | |
1431 | ///\r | |
1432 | struct {\r | |
1433 | ///\r | |
1434 | /// [Bits 14:0] PP0 Power Limit #1. (R/W) See Section 14.9.4, "PP0/PP1\r | |
1435 | /// RAPL Domains." and MSR_RAPL_POWER_UNIT in Table 35-7.\r | |
1436 | ///\r | |
1437 | UINT32 Limit:15;\r | |
1438 | ///\r | |
1439 | /// [Bit 15] Enable Power Limit #1. (R/W) See Section 14.9.4, "PP0/PP1\r | |
1440 | /// RAPL Domains.".\r | |
1441 | ///\r | |
1442 | UINT32 Enable:1;\r | |
1443 | UINT32 Reserved1:1;\r | |
1444 | ///\r | |
1445 | /// [Bits 23:17] Time Window for Power Limit #1. (R/W) Specifies the time\r | |
1446 | /// duration over which the average power must remain below\r | |
1447 | /// PP0_POWER_LIMIT #1(14:0). Supported Encodings: 0x0: 1 second time\r | |
1448 | /// duration. 0x1: 5 second time duration (Default). 0x2: 10 second time\r | |
1449 | /// duration. 0x3: 15 second time duration. 0x4: 20 second time duration.\r | |
1450 | /// 0x5: 25 second time duration. 0x6: 30 second time duration. 0x7: 35\r | |
1451 | /// second time duration. 0x8: 40 second time duration. 0x9: 45 second\r | |
1452 | /// time duration. 0xA: 50 second time duration. 0xB-0x7F - reserved.\r | |
1453 | ///\r | |
1454 | UINT32 Time:7;\r | |
1455 | UINT32 Reserved2:8;\r | |
1456 | UINT32 Reserved3:32;\r | |
1457 | } Bits;\r | |
1458 | ///\r | |
1459 | /// All bit fields as a 32-bit value\r | |
1460 | ///\r | |
1461 | UINT32 Uint32;\r | |
1462 | ///\r | |
1463 | /// All bit fields as a 64-bit value\r | |
1464 | ///\r | |
1465 | UINT64 Uint64;\r | |
1466 | } MSR_SILVERMONT_PP0_POWER_LIMIT_REGISTER;\r | |
1467 | \r | |
1468 | #endif\r |