]> git.proxmox.com Git - mirror_edk2.git/blame - UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h
projects / mirror_edk2.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
MdeModulePkg/DxeIpl: Create 5-level page table for long mode
[mirror_edk2.git] / UefiCpuPkg / Include / Register / Msr / SkylakeMsr.h
CommitLineData
6b55a245 1/** @file\r
ba1a2d11 2 MSR Defintions for Intel processors based on the Skylake/Kabylake/Coffeelake/Cannonlake microarchitecture.\r
6b55a245
MK		 3\r
4 Provides defines for Machine Specific Registers(MSR) indexes. Data structures\r
5 are provided for MSRs that contain one or more bit fields. If the MSR value\r
6 returned is a single 32-bit or 64-bit value, then a data structure is not\r
7 provided for that MSR.\r
8\r
ba1a2d11 9 Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>\r
0acd8697 10 SPDX-License-Identifier: BSD-2-Clause-Patent\r
6b55a245
MK		 11\r
12 @par Specification Reference:\r
ba1a2d11
ED		 13 Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,\r
14 May 2018, Volume 4: Model-Specific-Registers (MSR)\r
6b55a245
MK		 15\r
16**/\r
17\r
18#ifndef __SKYLAKE_MSR_H__\r
19#define __SKYLAKE_MSR_H__\r
20\r
21#include <Register/ArchitecturalMsr.h>\r
22\r
f4c982bf
JF		 23/**\r
24 Is Intel processors based on the Skylake microarchitecture?\r
25\r
26 @param DisplayFamily Display Family ID\r
27 @param DisplayModel Display Model ID\r
28\r
29 @retval TRUE Yes, it is.\r
30 @retval FALSE No, it isn't.\r
31**/\r
32#define IS_SKYLAKE_PROCESSOR(DisplayFamily, DisplayModel) \\r
33 (DisplayFamily == 0x06 && \\r
34 ( \\r
35 DisplayModel == 0x4E || \\r
3add0205
ED		 36 DisplayModel == 0x5E || \\r
37 DisplayModel == 0x55 || \\r
38 DisplayModel == 0x8E || \\r
39 DisplayModel == 0x9E || \\r
40 DisplayModel == 0x66 \\r
f4c982bf
JF		 41 ) \\r
42 )\r
43\r
6b55a245
MK		 44/**\r
45 Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,\r
46 RW if MSR_PLATFORM_INFO.[28] = 1.\r
47\r
48 @param ECX MSR_SKYLAKE_TURBO_RATIO_LIMIT (0x000001AD)\r
49 @param EAX Lower 32-bits of MSR value.\r
50 Described by the type MSR_SKYLAKE_TURBO_RATIO_LIMIT_REGISTER.\r
51 @param EDX Upper 32-bits of MSR value.\r
52 Described by the type MSR_SKYLAKE_TURBO_RATIO_LIMIT_REGISTER.\r
53\r
54 <b>Example usage</b>\r
55 @code\r
56 MSR_SKYLAKE_TURBO_RATIO_LIMIT_REGISTER Msr;\r
57\r
58 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_TURBO_RATIO_LIMIT);\r
59 @endcode\r
04e7a465 60 @note MSR_SKYLAKE_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.\r
6b55a245
MK		 61**/\r
62#define MSR_SKYLAKE_TURBO_RATIO_LIMIT 0x000001AD\r
63\r
64/**\r
65 MSR information returned for MSR index #MSR_SKYLAKE_TURBO_RATIO_LIMIT\r
66**/\r
67typedef union {\r
68 ///\r
69 /// Individual bit fields\r
70 ///\r
71 struct {\r
72 ///\r
73 /// [Bits 7:0] Package. Maximum Ratio Limit for 1C Maximum turbo ratio\r
74 /// limit of 1 core active.\r
75 ///\r
76 UINT32 Maximum1C:8;\r
77 ///\r
78 /// [Bits 15:8] Package. Maximum Ratio Limit for 2C Maximum turbo ratio\r
79 /// limit of 2 core active.\r
80 ///\r
81 UINT32 Maximum2C:8;\r
82 ///\r
83 /// [Bits 23:16] Package. Maximum Ratio Limit for 3C Maximum turbo ratio\r
84 /// limit of 3 core active.\r
85 ///\r
86 UINT32 Maximum3C:8;\r
87 ///\r
88 /// [Bits 31:24] Package. Maximum Ratio Limit for 4C Maximum turbo ratio\r
89 /// limit of 4 core active.\r
90 ///\r
91 UINT32 Maximum4C:8;\r
92 UINT32 Reserved:32;\r
93 } Bits;\r
94 ///\r
95 /// All bit fields as a 32-bit value\r
96 ///\r
97 UINT32 Uint32;\r
98 ///\r
99 /// All bit fields as a 64-bit value\r
100 ///\r
101 UINT64 Uint64;\r
102} MSR_SKYLAKE_TURBO_RATIO_LIMIT_REGISTER;\r
103\r
104\r
105/**\r
106 Thread. Last Branch Record Stack TOS (R/W) Contains an index (bits 0-4)\r
107 that points to the MSR containing the most recent branch record.\r
108\r
109 @param ECX MSR_SKYLAKE_LASTBRANCH_TOS (0x000001C9)\r
110 @param EAX Lower 32-bits of MSR value.\r
111 @param EDX Upper 32-bits of MSR value.\r
112\r
113 <b>Example usage</b>\r
114 @code\r
115 UINT64 Msr;\r
116\r
117 Msr = AsmReadMsr64 (MSR_SKYLAKE_LASTBRANCH_TOS);\r
118 AsmWriteMsr64 (MSR_SKYLAKE_LASTBRANCH_TOS, Msr);\r
119 @endcode\r
04e7a465 120 @note MSR_SKYLAKE_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.\r
6b55a245
MK		 121**/\r
122#define MSR_SKYLAKE_LASTBRANCH_TOS 0x000001C9\r
123\r
124\r
3add0205
ED		 125/**\r
126 Core. Power Control Register See http://biosbits.org.\r
127\r
128 @param ECX MSR_SKYLAKE_POWER_CTL (0x000001FC)\r
129 @param EAX Lower 32-bits of MSR value.\r
130 Described by the type MSR_SKYLAKE_POWER_CTL_REGISTER.\r
131 @param EDX Upper 32-bits of MSR value.\r
132 Described by the type MSR_SKYLAKE_POWER_CTL_REGISTER.\r
133\r
134 <b>Example usage</b>\r
135 @code\r
136 MSR_SKYLAKE_POWER_CTL_REGISTER Msr;\r
137\r
138 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_POWER_CTL);\r
139 AsmWriteMsr64 (MSR_SKYLAKE_POWER_CTL, Msr.Uint64);\r
140 @endcode\r
141**/\r
142#define MSR_SKYLAKE_POWER_CTL 0x000001FC\r
143\r
144/**\r
145 MSR information returned for MSR index #MSR_SKYLAKE_POWER_CTL\r
146**/\r
147typedef union {\r
148 ///\r
149 /// Individual bit fields\r
150 ///\r
151 struct {\r
152 UINT32 Reserved1:1;\r
153 ///\r
154 /// [Bit 1] Package. C1E Enable (R/W) When set to '1', will enable the CPU\r
155 /// to switch to the Minimum Enhanced Intel SpeedStep Technology operating\r
156 /// point when all execution cores enter MWAIT (C1).\r
157 ///\r
158 UINT32 C1EEnable:1;\r
159 UINT32 Reserved2:17;\r
160 ///\r
161 /// [Bit 19] Disable Race to Halt Optimization (R/W) Setting this bit\r
162 /// disables the Race to Halt optimization and avoids this optimization\r
163 /// limitation to execute below the most efficient frequency ratio.\r
164 /// Default value is 0 for processors that support Race to Halt\r
165 /// optimization. Default value is 1 for processors that do not support\r
166 /// Race to Halt optimization.\r
167 ///\r
168 UINT32 Fix_Me_1:1;\r
169 ///\r
170 /// [Bit 20] Disable Energy Efficiency Optimization (R/W) Setting this bit\r
171 /// disables the P-States energy efficiency optimization. Default value is\r
172 /// 0. Disable/enable the energy efficiency optimization in P-State legacy\r
173 /// mode (when IA32_PM_ENABLE[HWP_ENABLE] = 0), has an effect only in the\r
174 /// turbo range or into PERF_MIN_CTL value if it is not zero set. In HWP\r
175 /// mode (IA32_PM_ENABLE[HWP_ENABLE] == 1), has an effect between the OS\r
176 /// desired or OS maximize to the OS minimize performance setting.\r
177 ///\r
178 UINT32 DisableEnergyEfficiencyOptimization:1;\r
179 UINT32 Reserved3:11;\r
180 UINT32 Reserved4:32;\r
181 } Bits;\r
182 ///\r
183 /// All bit fields as a 32-bit value\r
184 ///\r
185 UINT32 Uint32;\r
186 ///\r
187 /// All bit fields as a 64-bit value\r
188 ///\r
189 UINT64 Uint64;\r
190} MSR_SKYLAKE_POWER_CTL_REGISTER;\r
191\r
192\r
6b55a245 193/**\r
8b344785
ED		 194 Package. Lower 64 Bit CR_SGXOWNEREPOCH (W) Writes do not update\r
195 CR_SGXOWNEREPOCH if CPUID.(EAX=12H, ECX=0):EAX.SGX1 is 1 on any thread in\r
196 the package. Lower 64 bits of an 128-bit external entropy value for key\r
197 derivation of an enclave.\r
6b55a245 198\r
8b344785 199 @param ECX MSR_SKYLAKE_SGXOWNEREPOCH0 (0x00000300)\r
6b55a245
MK		 200 @param EAX Lower 32-bits of MSR value.\r
201 @param EDX Upper 32-bits of MSR value.\r
202\r
203 <b>Example usage</b>\r
204 @code\r
205 UINT64 Msr;\r
206\r
8b344785
ED		 207 Msr = 0;\r
208 AsmWriteMsr64 (MSR_SKYLAKE_SGXOWNEREPOCH0, Msr);\r
6b55a245 209 @endcode\r
8b344785 210 @note MSR_SKYLAKE_SGXOWNEREPOCH0 is defined as MSR_SGXOWNER0 in SDM.\r
6b55a245 211**/\r
8b344785 212#define MSR_SKYLAKE_SGXOWNEREPOCH0 0x00000300\r
6b55a245 213\r
8b344785
ED		 214//\r
215// Define MSR_SKYLAKE_SGXOWNER0 for compatibility due to name change in the SDM.\r
216//\r
217#define MSR_SKYLAKE_SGXOWNER0 MSR_SKYLAKE_SGXOWNEREPOCH0\r
6b55a245 218/**\r
8b344785
ED		 219 Package. Upper 64 Bit CR_SGXOWNEREPOCH (W) Writes do not update\r
220 CR_SGXOWNEREPOCH if CPUID.(EAX=12H, ECX=0):EAX.SGX1 is 1 on any thread in\r
221 the package. Upper 64 bits of an 128-bit external entropy value for key\r
222 derivation of an enclave.\r
6b55a245 223\r
8b344785 224 @param ECX MSR_SKYLAKE_SGXOWNEREPOCH1 (0x00000301)\r
6b55a245
MK		 225 @param EAX Lower 32-bits of MSR value.\r
226 @param EDX Upper 32-bits of MSR value.\r
227\r
228 <b>Example usage</b>\r
229 @code\r
230 UINT64 Msr;\r
231\r
8b344785
ED		 232 Msr = 0;\r
233 AsmWriteMsr64 (MSR_SKYLAKE_SGXOWNEREPOCH1, Msr);\r
6b55a245 234 @endcode\r
8b344785 235 @note MSR_SKYLAKE_SGXOWNEREPOCH1 is defined as MSR_SGXOWNER1 in SDM.\r
6b55a245 236**/\r
8b344785
ED		 237#define MSR_SKYLAKE_SGXOWNEREPOCH1 0x00000301\r
238\r
239//\r
240// Define MSR_SKYLAKE_SGXOWNER1 for compatibility due to name change in the SDM.\r
241//\r
242#define MSR_SKYLAKE_SGXOWNER1 MSR_SKYLAKE_SGXOWNEREPOCH1\r
6b55a245
MK		 243\r
244\r
245/**\r
ba1a2d11 246 See Table 2-2. See Section 18.2.4, "Architectural Performance Monitoring\r
37cea63f 247 Version 4.".\r
6b55a245 248\r
37cea63f 249 @param ECX MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS (0x0000038E)\r
6b55a245 250 @param EAX Lower 32-bits of MSR value.\r
37cea63f 251 Described by the type MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_REGISTER.\r
6b55a245 252 @param EDX Upper 32-bits of MSR value.\r
37cea63f 253 Described by the type MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_REGISTER.\r
6b55a245
MK		 254\r
255 <b>Example usage</b>\r
256 @code\r
37cea63f 257 MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_REGISTER Msr;\r
6b55a245 258\r
37cea63f
HW		 259 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS);\r
260 AsmWriteMsr64 (MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS, Msr.Uint64);\r
6b55a245 261 @endcode\r
37cea63f 262 @note MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS is defined as IA32_PERF_GLOBAL_STATUS in SDM.\r
6b55a245 263**/\r
37cea63f 264#define MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS 0x0000038E\r
6b55a245
MK		 265\r
266/**\r
37cea63f 267 MSR information returned for MSR index #MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS\r
6b55a245
MK		 268**/\r
269typedef union {\r
270 ///\r
271 /// Individual bit fields\r
272 ///\r
273 struct {\r
274 ///\r
275 /// [Bit 0] Thread. Ovf_PMC0.\r
276 ///\r
277 UINT32 Ovf_PMC0:1;\r
278 ///\r
279 /// [Bit 1] Thread. Ovf_PMC1.\r
280 ///\r
281 UINT32 Ovf_PMC1:1;\r
282 ///\r
283 /// [Bit 2] Thread. Ovf_PMC2.\r
284 ///\r
285 UINT32 Ovf_PMC2:1;\r
286 ///\r
287 /// [Bit 3] Thread. Ovf_PMC3.\r
288 ///\r
289 UINT32 Ovf_PMC3:1;\r
290 ///\r
291 /// [Bit 4] Thread. Ovf_PMC4 (if CPUID.0AH:EAX[15:8] > 4).\r
292 ///\r
293 UINT32 Ovf_PMC4:1;\r
294 ///\r
295 /// [Bit 5] Thread. Ovf_PMC5 (if CPUID.0AH:EAX[15:8] > 5).\r
296 ///\r
297 UINT32 Ovf_PMC5:1;\r
298 ///\r
299 /// [Bit 6] Thread. Ovf_PMC6 (if CPUID.0AH:EAX[15:8] > 6).\r
300 ///\r
301 UINT32 Ovf_PMC6:1;\r
302 ///\r
303 /// [Bit 7] Thread. Ovf_PMC7 (if CPUID.0AH:EAX[15:8] > 7).\r
304 ///\r
305 UINT32 Ovf_PMC7:1;\r
306 UINT32 Reserved1:24;\r
307 ///\r
308 /// [Bit 32] Thread. Ovf_FixedCtr0.\r
309 ///\r
310 UINT32 Ovf_FixedCtr0:1;\r
311 ///\r
312 /// [Bit 33] Thread. Ovf_FixedCtr1.\r
313 ///\r
314 UINT32 Ovf_FixedCtr1:1;\r
315 ///\r
316 /// [Bit 34] Thread. Ovf_FixedCtr2.\r
317 ///\r
318 UINT32 Ovf_FixedCtr2:1;\r
319 UINT32 Reserved2:20;\r
320 ///\r
321 /// [Bit 55] Thread. Trace_ToPA_PMI.\r
322 ///\r
323 UINT32 Trace_ToPA_PMI:1;\r
324 UINT32 Reserved3:2;\r
325 ///\r
326 /// [Bit 58] Thread. LBR_Frz.\r
327 ///\r
328 UINT32 LBR_Frz:1;\r
329 ///\r
330 /// [Bit 59] Thread. CTR_Frz.\r
331 ///\r
332 UINT32 CTR_Frz:1;\r
333 ///\r
334 /// [Bit 60] Thread. ASCI.\r
335 ///\r
336 UINT32 ASCI:1;\r
337 ///\r
338 /// [Bit 61] Thread. Ovf_Uncore.\r
339 ///\r
340 UINT32 Ovf_Uncore:1;\r
341 ///\r
342 /// [Bit 62] Thread. Ovf_BufDSSAVE.\r
343 ///\r
344 UINT32 Ovf_BufDSSAVE:1;\r
345 ///\r
346 /// [Bit 63] Thread. CondChgd.\r
347 ///\r
348 UINT32 CondChgd:1;\r
349 } Bits;\r
350 ///\r
351 /// All bit fields as a 64-bit value\r
352 ///\r
353 UINT64 Uint64;\r
37cea63f 354} MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_REGISTER;\r
6b55a245
MK		 355\r
356\r
357/**\r
ba1a2d11 358 See Table 2-2. See Section 18.2.4, "Architectural Performance Monitoring\r
37cea63f 359 Version 4.".\r
6b55a245
MK		 360\r
361 @param ECX MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET (0x00000390)\r
362 @param EAX Lower 32-bits of MSR value.\r
363 Described by the type MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER.\r
364 @param EDX Upper 32-bits of MSR value.\r
365 Described by the type MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER.\r
366\r
367 <b>Example usage</b>\r
368 @code\r
369 MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER Msr;\r
370\r
371 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET);\r
372 AsmWriteMsr64 (MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET, Msr.Uint64);\r
373 @endcode\r
04e7a465 374 @note MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET is defined as IA32_PERF_GLOBAL_STATUS_RESET in SDM.\r
6b55a245
MK		 375**/\r
376#define MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET 0x00000390\r
377\r
378/**\r
379 MSR information returned for MSR index\r
380 #MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET\r
381**/\r
382typedef union {\r
383 ///\r
384 /// Individual bit fields\r
385 ///\r
386 struct {\r
387 ///\r
388 /// [Bit 0] Thread. Set 1 to clear Ovf_PMC0.\r
389 ///\r
390 UINT32 Ovf_PMC0:1;\r
391 ///\r
392 /// [Bit 1] Thread. Set 1 to clear Ovf_PMC1.\r
393 ///\r
394 UINT32 Ovf_PMC1:1;\r
395 ///\r
396 /// [Bit 2] Thread. Set 1 to clear Ovf_PMC2.\r
397 ///\r
398 UINT32 Ovf_PMC2:1;\r
399 ///\r
400 /// [Bit 3] Thread. Set 1 to clear Ovf_PMC3.\r
401 ///\r
402 UINT32 Ovf_PMC3:1;\r
403 ///\r
404 /// [Bit 4] Thread. Set 1 to clear Ovf_PMC4 (if CPUID.0AH:EAX[15:8] > 4).\r
405 ///\r
406 UINT32 Ovf_PMC4:1;\r
407 ///\r
408 /// [Bit 5] Thread. Set 1 to clear Ovf_PMC5 (if CPUID.0AH:EAX[15:8] > 5).\r
409 ///\r
410 UINT32 Ovf_PMC5:1;\r
411 ///\r
412 /// [Bit 6] Thread. Set 1 to clear Ovf_PMC6 (if CPUID.0AH:EAX[15:8] > 6).\r
413 ///\r
414 UINT32 Ovf_PMC6:1;\r
415 ///\r
416 /// [Bit 7] Thread. Set 1 to clear Ovf_PMC7 (if CPUID.0AH:EAX[15:8] > 7).\r
417 ///\r
418 UINT32 Ovf_PMC7:1;\r
419 UINT32 Reserved1:24;\r
420 ///\r
421 /// [Bit 32] Thread. Set 1 to clear Ovf_FixedCtr0.\r
422 ///\r
423 UINT32 Ovf_FixedCtr0:1;\r
424 ///\r
425 /// [Bit 33] Thread. Set 1 to clear Ovf_FixedCtr1.\r
426 ///\r
427 UINT32 Ovf_FixedCtr1:1;\r
428 ///\r
429 /// [Bit 34] Thread. Set 1 to clear Ovf_FixedCtr2.\r
430 ///\r
431 UINT32 Ovf_FixedCtr2:1;\r
432 UINT32 Reserved2:20;\r
433 ///\r
434 /// [Bit 55] Thread. Set 1 to clear Trace_ToPA_PMI.\r
435 ///\r
436 UINT32 Trace_ToPA_PMI:1;\r
437 UINT32 Reserved3:2;\r
438 ///\r
439 /// [Bit 58] Thread. Set 1 to clear LBR_Frz.\r
440 ///\r
441 UINT32 LBR_Frz:1;\r
442 ///\r
443 /// [Bit 59] Thread. Set 1 to clear CTR_Frz.\r
444 ///\r
445 UINT32 CTR_Frz:1;\r
446 ///\r
447 /// [Bit 60] Thread. Set 1 to clear ASCI.\r
448 ///\r
449 UINT32 ASCI:1;\r
450 ///\r
451 /// [Bit 61] Thread. Set 1 to clear Ovf_Uncore.\r
452 ///\r
453 UINT32 Ovf_Uncore:1;\r
454 ///\r
455 /// [Bit 62] Thread. Set 1 to clear Ovf_BufDSSAVE.\r
456 ///\r
457 UINT32 Ovf_BufDSSAVE:1;\r
458 ///\r
459 /// [Bit 63] Thread. Set 1 to clear CondChgd.\r
460 ///\r
461 UINT32 CondChgd:1;\r
462 } Bits;\r
463 ///\r
464 /// All bit fields as a 64-bit value\r
465 ///\r
466 UINT64 Uint64;\r
467} MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER;\r
468\r
469\r
470/**\r
ba1a2d11 471 See Table 2-2. See Section 18.2.4, "Architectural Performance Monitoring\r
37cea63f 472 Version 4.".\r
6b55a245
MK		 473\r
474 @param ECX MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET (0x00000391)\r
475 @param EAX Lower 32-bits of MSR value.\r
476 Described by the type MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET_REGISTER.\r
477 @param EDX Upper 32-bits of MSR value.\r
478 Described by the type MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET_REGISTER.\r
479\r
480 <b>Example usage</b>\r
481 @code\r
482 MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET_REGISTER Msr;\r
483\r
484 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET);\r
485 AsmWriteMsr64 (MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET, Msr.Uint64);\r
486 @endcode\r
04e7a465 487 @note MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET is defined as IA32_PERF_GLOBAL_STATUS_SET in SDM.\r
6b55a245
MK		 488**/\r
489#define MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET 0x00000391\r
490\r
491/**\r
492 MSR information returned for MSR index\r
493 #MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET\r
494**/\r
495typedef union {\r
496 ///\r
497 /// Individual bit fields\r
498 ///\r
499 struct {\r
500 ///\r
501 /// [Bit 0] Thread. Set 1 to cause Ovf_PMC0 = 1.\r
502 ///\r
503 UINT32 Ovf_PMC0:1;\r
504 ///\r
505 /// [Bit 1] Thread. Set 1 to cause Ovf_PMC1 = 1.\r
506 ///\r
507 UINT32 Ovf_PMC1:1;\r
508 ///\r
509 /// [Bit 2] Thread. Set 1 to cause Ovf_PMC2 = 1.\r
510 ///\r
511 UINT32 Ovf_PMC2:1;\r
512 ///\r
513 /// [Bit 3] Thread. Set 1 to cause Ovf_PMC3 = 1.\r
514 ///\r
515 UINT32 Ovf_PMC3:1;\r
516 ///\r
517 /// [Bit 4] Thread. Set 1 to cause Ovf_PMC4=1 (if CPUID.0AH:EAX[15:8] > 4).\r
518 ///\r
519 UINT32 Ovf_PMC4:1;\r
520 ///\r
521 /// [Bit 5] Thread. Set 1 to cause Ovf_PMC5=1 (if CPUID.0AH:EAX[15:8] > 5).\r
522 ///\r
523 UINT32 Ovf_PMC5:1;\r
524 ///\r
525 /// [Bit 6] Thread. Set 1 to cause Ovf_PMC6=1 (if CPUID.0AH:EAX[15:8] > 6).\r
526 ///\r
527 UINT32 Ovf_PMC6:1;\r
528 ///\r
529 /// [Bit 7] Thread. Set 1 to cause Ovf_PMC7=1 (if CPUID.0AH:EAX[15:8] > 7).\r
530 ///\r
531 UINT32 Ovf_PMC7:1;\r
532 UINT32 Reserved1:24;\r
533 ///\r
534 /// [Bit 32] Thread. Set 1 to cause Ovf_FixedCtr0 = 1.\r
535 ///\r
536 UINT32 Ovf_FixedCtr0:1;\r
537 ///\r
538 /// [Bit 33] Thread. Set 1 to cause Ovf_FixedCtr1 = 1.\r
539 ///\r
540 UINT32 Ovf_FixedCtr1:1;\r
541 ///\r
542 /// [Bit 34] Thread. Set 1 to cause Ovf_FixedCtr2 = 1.\r
543 ///\r
544 UINT32 Ovf_FixedCtr2:1;\r
545 UINT32 Reserved2:20;\r
546 ///\r
547 /// [Bit 55] Thread. Set 1 to cause Trace_ToPA_PMI = 1.\r
548 ///\r
549 UINT32 Trace_ToPA_PMI:1;\r
550 UINT32 Reserved3:2;\r
551 ///\r
552 /// [Bit 58] Thread. Set 1 to cause LBR_Frz = 1.\r
553 ///\r
554 UINT32 LBR_Frz:1;\r
555 ///\r
556 /// [Bit 59] Thread. Set 1 to cause CTR_Frz = 1.\r
557 ///\r
558 UINT32 CTR_Frz:1;\r
559 ///\r
560 /// [Bit 60] Thread. Set 1 to cause ASCI = 1.\r
561 ///\r
562 UINT32 ASCI:1;\r
563 ///\r
564 /// [Bit 61] Thread. Set 1 to cause Ovf_Uncore.\r
565 ///\r
566 UINT32 Ovf_Uncore:1;\r
567 ///\r
568 /// [Bit 62] Thread. Set 1 to cause Ovf_BufDSSAVE.\r
569 ///\r
570 UINT32 Ovf_BufDSSAVE:1;\r
571 UINT32 Reserved4:1;\r
572 } Bits;\r
573 ///\r
574 /// All bit fields as a 64-bit value\r
575 ///\r
576 UINT64 Uint64;\r
577} MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET_REGISTER;\r
578\r
579\r
580/**\r
581 Thread. FrontEnd Precise Event Condition Select (R/W).\r
582\r
583 @param ECX MSR_SKYLAKE_PEBS_FRONTEND (0x000003F7)\r
584 @param EAX Lower 32-bits of MSR value.\r
585 Described by the type MSR_SKYLAKE_PEBS_FRONTEND_REGISTER.\r
586 @param EDX Upper 32-bits of MSR value.\r
587 Described by the type MSR_SKYLAKE_PEBS_FRONTEND_REGISTER.\r
588\r
589 <b>Example usage</b>\r
590 @code\r
591 MSR_SKYLAKE_PEBS_FRONTEND_REGISTER Msr;\r
592\r
593 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_PEBS_FRONTEND);\r
594 AsmWriteMsr64 (MSR_SKYLAKE_PEBS_FRONTEND, Msr.Uint64);\r
595 @endcode\r
04e7a465 596 @note MSR_SKYLAKE_PEBS_FRONTEND is defined as MSR_PEBS_FRONTEND in SDM.\r
6b55a245
MK		 597**/\r
598#define MSR_SKYLAKE_PEBS_FRONTEND 0x000003F7\r
599\r
600/**\r
601 MSR information returned for MSR index #MSR_SKYLAKE_PEBS_FRONTEND\r
602**/\r
603typedef union {\r
604 ///\r
605 /// Individual bit fields\r
606 ///\r
607 struct {\r
608 ///\r
609 /// [Bits 2:0] Event Code Select.\r
610 ///\r
611 UINT32 EventCodeSelect:3;\r
612 UINT32 Reserved1:1;\r
613 ///\r
614 /// [Bit 4] Event Code Select High.\r
615 ///\r
616 UINT32 EventCodeSelectHigh:1;\r
617 UINT32 Reserved2:3;\r
618 ///\r
619 /// [Bits 19:8] IDQ_Bubble_Length Specifier.\r
620 ///\r
621 UINT32 IDQ_Bubble_Length:12;\r
622 ///\r
623 /// [Bits 22:20] IDQ_Bubble_Width Specifier.\r
624 ///\r
625 UINT32 IDQ_Bubble_Width:3;\r
626 UINT32 Reserved3:9;\r
627 UINT32 Reserved4:32;\r
628 } Bits;\r
629 ///\r
630 /// All bit fields as a 32-bit value\r
631 ///\r
632 UINT32 Uint32;\r
633 ///\r
634 /// All bit fields as a 64-bit value\r
635 ///\r
636 UINT64 Uint64;\r
637} MSR_SKYLAKE_PEBS_FRONTEND_REGISTER;\r
638\r
639\r
37cea63f
HW		 640/**\r
641 Package. PP0 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL\r
642 Domains.".\r
643\r
644 @param ECX MSR_SKYLAKE_PP0_ENERGY_STATUS (0x00000639)\r
645 @param EAX Lower 32-bits of MSR value.\r
646 @param EDX Upper 32-bits of MSR value.\r
647\r
648 <b>Example usage</b>\r
649 @code\r
650 UINT64 Msr;\r
651\r
652 Msr = AsmReadMsr64 (MSR_SKYLAKE_PP0_ENERGY_STATUS);\r
653 @endcode\r
654 @note MSR_SKYLAKE_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM.\r
655**/\r
656#define MSR_SKYLAKE_PP0_ENERGY_STATUS 0x00000639\r
657\r
658\r
6b55a245
MK		 659/**\r
660 Platform*. Platform Energy Counter. (R/O). This MSR is valid only if both\r
661 platform vendor hardware implementation and BIOS enablement support it. This\r
662 MSR will read 0 if not valid.\r
663\r
664 @param ECX MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER (0x0000064D)\r
665 @param EAX Lower 32-bits of MSR value.\r
666 Described by the type MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER_REGISTER.\r
667 @param EDX Upper 32-bits of MSR value.\r
668 Described by the type MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER_REGISTER.\r
669\r
670 <b>Example usage</b>\r
671 @code\r
672 MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER_REGISTER Msr;\r
673\r
674 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER);\r
675 @endcode\r
04e7a465 676 @note MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER is defined as MSR_PLATFORM_ENERGY_COUNTER in SDM.\r
6b55a245
MK		 677**/\r
678#define MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER 0x0000064D\r
679\r
680/**\r
681 MSR information returned for MSR index #MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER\r
682**/\r
683typedef union {\r
684 ///\r
685 /// Individual bit fields\r
686 ///\r
687 struct {\r
688 ///\r
689 /// [Bits 31:0] Total energy consumed by all devices in the platform that\r
690 /// receive power from integrated power delivery mechanism, Included\r
691 /// platform devices are processor cores, SOC, memory, add-on or\r
692 /// peripheral devices that get powered directly from the platform power\r
693 /// delivery means. The energy units are specified in the\r
694 /// MSR_RAPL_POWER_UNIT.Enery_Status_Unit.\r
695 ///\r
696 UINT32 TotalEnergy:32;\r
697 UINT32 Reserved:32;\r
698 } Bits;\r
699 ///\r
700 /// All bit fields as a 32-bit value\r
701 ///\r
702 UINT32 Uint32;\r
703 ///\r
704 /// All bit fields as a 64-bit value\r
705 ///\r
706 UINT64 Uint64;\r
707} MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER_REGISTER;\r
708\r
709\r
710/**\r
711 Thread. Productive Performance Count. (R/O). Hardware's view of workload\r
712 scalability. See Section 14.4.5.1.\r
713\r
714 @param ECX MSR_SKYLAKE_PPERF (0x0000064E)\r
715 @param EAX Lower 32-bits of MSR value.\r
716 @param EDX Upper 32-bits of MSR value.\r
717\r
718 <b>Example usage</b>\r
719 @code\r
720 UINT64 Msr;\r
721\r
722 Msr = AsmReadMsr64 (MSR_SKYLAKE_PPERF);\r
723 @endcode\r
04e7a465 724 @note MSR_SKYLAKE_PPERF is defined as MSR_PPERF in SDM.\r
6b55a245
MK		 725**/\r
726#define MSR_SKYLAKE_PPERF 0x0000064E\r
727\r
728\r
37cea63f
HW		 729/**\r
730 Package. Indicator of Frequency Clipping in Processor Cores (R/W) (frequency\r
731 refers to processor core frequency).\r
732\r
733 @param ECX MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS (0x0000064F)\r
734 @param EAX Lower 32-bits of MSR value.\r
735 Described by the type MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS_REGISTER.\r
736 @param EDX Upper 32-bits of MSR value.\r
737 Described by the type MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS_REGISTER.\r
738\r
739 <b>Example usage</b>\r
740 @code\r
741 MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS_REGISTER Msr;\r
742\r
743 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS);\r
744 AsmWriteMsr64 (MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS, Msr.Uint64);\r
745 @endcode\r
746 @note MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS is defined as MSR_CORE_PERF_LIMIT_REASONS in SDM.\r
747**/\r
748#define MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS 0x0000064F\r
749\r
750/**\r
751 MSR information returned for MSR index #MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS\r
752**/\r
753typedef union {\r
754 ///\r
755 /// Individual bit fields\r
756 ///\r
757 struct {\r
758 ///\r
759 /// [Bit 0] PROCHOT Status (R0) When set, frequency is reduced below the\r
760 /// operating system request due to assertion of external PROCHOT.\r
761 ///\r
762 UINT32 PROCHOT_Status:1;\r
763 ///\r
764 /// [Bit 1] Thermal Status (R0) When set, frequency is reduced below the\r
765 /// operating system request due to a thermal event.\r
766 ///\r
767 UINT32 ThermalStatus:1;\r
768 UINT32 Reserved1:2;\r
769 ///\r
770 /// [Bit 4] Residency State Regulation Status (R0) When set, frequency is\r
771 /// reduced below the operating system request due to residency state\r
772 /// regulation limit.\r
773 ///\r
774 UINT32 ResidencyStateRegulationStatus:1;\r
775 ///\r
776 /// [Bit 5] Running Average Thermal Limit Status (R0) When set, frequency\r
777 /// is reduced below the operating system request due to Running Average\r
778 /// Thermal Limit (RATL).\r
779 ///\r
780 UINT32 RunningAverageThermalLimitStatus:1;\r
781 ///\r
782 /// [Bit 6] VR Therm Alert Status (R0) When set, frequency is reduced\r
783 /// below the operating system request due to a thermal alert from a\r
784 /// processor Voltage Regulator (VR).\r
785 ///\r
786 UINT32 VRThermAlertStatus:1;\r
787 ///\r
788 /// [Bit 7] VR Therm Design Current Status (R0) When set, frequency is\r
789 /// reduced below the operating system request due to VR thermal design\r
790 /// current limit.\r
791 ///\r
792 UINT32 VRThermDesignCurrentStatus:1;\r
793 ///\r
794 /// [Bit 8] Other Status (R0) When set, frequency is reduced below the\r
795 /// operating system request due to electrical or other constraints.\r
796 ///\r
797 UINT32 OtherStatus:1;\r
798 UINT32 Reserved2:1;\r
799 ///\r
800 /// [Bit 10] Package/Platform-Level Power Limiting PL1 Status (R0) When\r
801 /// set, frequency is reduced below the operating system request due to\r
802 /// package/platform-level power limiting PL1.\r
803 ///\r
804 UINT32 PL1Status:1;\r
805 ///\r
806 /// [Bit 11] Package/Platform-Level PL2 Power Limiting Status (R0) When\r
807 /// set, frequency is reduced below the operating system request due to\r
808 /// package/platform-level power limiting PL2/PL3.\r
809 ///\r
810 UINT32 PL2Status:1;\r
811 ///\r
812 /// [Bit 12] Max Turbo Limit Status (R0) When set, frequency is reduced\r
813 /// below the operating system request due to multi-core turbo limits.\r
814 ///\r
815 UINT32 MaxTurboLimitStatus:1;\r
816 ///\r
817 /// [Bit 13] Turbo Transition Attenuation Status (R0) When set, frequency\r
818 /// is reduced below the operating system request due to Turbo transition\r
819 /// attenuation. This prevents performance degradation due to frequent\r
820 /// operating ratio changes.\r
821 ///\r
822 UINT32 TurboTransitionAttenuationStatus:1;\r
823 UINT32 Reserved3:2;\r
824 ///\r
825 /// [Bit 16] PROCHOT Log When set, indicates that the PROCHOT Status bit\r
826 /// has asserted since the log bit was last cleared. This log bit will\r
827 /// remain set until cleared by software writing 0.\r
828 ///\r
829 UINT32 PROCHOT_Log:1;\r
830 ///\r
831 /// [Bit 17] Thermal Log When set, indicates that the Thermal Status bit\r
832 /// has asserted since the log bit was last cleared. This log bit will\r
833 /// remain set until cleared by software writing 0.\r
834 ///\r
835 UINT32 ThermalLog:1;\r
836 UINT32 Reserved4:2;\r
837 ///\r
838 /// [Bit 20] Residency State Regulation Log When set, indicates that the\r
839 /// Residency State Regulation Status bit has asserted since the log bit\r
840 /// was last cleared. This log bit will remain set until cleared by\r
841 /// software writing 0.\r
842 ///\r
843 UINT32 ResidencyStateRegulationLog:1;\r
844 ///\r
845 /// [Bit 21] Running Average Thermal Limit Log When set, indicates that\r
846 /// the RATL Status bit has asserted since the log bit was last cleared.\r
847 /// This log bit will remain set until cleared by software writing 0.\r
848 ///\r
849 UINT32 RunningAverageThermalLimitLog:1;\r
850 ///\r
851 /// [Bit 22] VR Therm Alert Log When set, indicates that the VR Therm\r
852 /// Alert Status bit has asserted since the log bit was last cleared. This\r
853 /// log bit will remain set until cleared by software writing 0.\r
854 ///\r
855 UINT32 VRThermAlertLog:1;\r
856 ///\r
857 /// [Bit 23] VR Thermal Design Current Log When set, indicates that the\r
858 /// VR TDC Status bit has asserted since the log bit was last cleared.\r
859 /// This log bit will remain set until cleared by software writing 0.\r
860 ///\r
861 UINT32 VRThermalDesignCurrentLog:1;\r
862 ///\r
863 /// [Bit 24] Other Log When set, indicates that the Other Status bit has\r
864 /// asserted since the log bit was last cleared. This log bit will remain\r
865 /// set until cleared by software writing 0.\r
866 ///\r
867 UINT32 OtherLog:1;\r
868 UINT32 Reserved5:1;\r
869 ///\r
870 /// [Bit 26] Package/Platform-Level PL1 Power Limiting Log When set,\r
871 /// indicates that the Package or Platform Level PL1 Power Limiting Status\r
872 /// bit has asserted since the log bit was last cleared. This log bit will\r
873 /// remain set until cleared by software writing 0.\r
874 ///\r
875 UINT32 PL1Log:1;\r
876 ///\r
877 /// [Bit 27] Package/Platform-Level PL2 Power Limiting Log When set,\r
878 /// indicates that the Package or Platform Level PL2/PL3 Power Limiting\r
879 /// Status bit has asserted since the log bit was last cleared. This log\r
880 /// bit will remain set until cleared by software writing 0.\r
881 ///\r
882 UINT32 PL2Log:1;\r
883 ///\r
884 /// [Bit 28] Max Turbo Limit Log When set, indicates that the Max Turbo\r
885 /// Limit Status bit has asserted since the log bit was last cleared. This\r
886 /// log bit will remain set until cleared by software writing 0.\r
887 ///\r
888 UINT32 MaxTurboLimitLog:1;\r
889 ///\r
890 /// [Bit 29] Turbo Transition Attenuation Log When set, indicates that the\r
891 /// Turbo Transition Attenuation Status bit has asserted since the log bit\r
892 /// was last cleared. This log bit will remain set until cleared by\r
893 /// software writing 0.\r
894 ///\r
895 UINT32 TurboTransitionAttenuationLog:1;\r
896 UINT32 Reserved6:2;\r
897 UINT32 Reserved7:32;\r
898 } Bits;\r
899 ///\r
900 /// All bit fields as a 32-bit value\r
901 ///\r
902 UINT32 Uint32;\r
903 ///\r
904 /// All bit fields as a 64-bit value\r
905 ///\r
906 UINT64 Uint64;\r
907} MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS_REGISTER;\r
908\r
909\r
6b55a245
MK		 910/**\r
911 Package. HDC Configuration (R/W)..\r
912\r
913 @param ECX MSR_SKYLAKE_PKG_HDC_CONFIG (0x00000652)\r
914 @param EAX Lower 32-bits of MSR value.\r
915 Described by the type MSR_SKYLAKE_PKG_HDC_CONFIG_REGISTER.\r
916 @param EDX Upper 32-bits of MSR value.\r
917 Described by the type MSR_SKYLAKE_PKG_HDC_CONFIG_REGISTER.\r
918\r
919 <b>Example usage</b>\r
920 @code\r
921 MSR_SKYLAKE_PKG_HDC_CONFIG_REGISTER Msr;\r
922\r
923 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_PKG_HDC_CONFIG);\r
924 AsmWriteMsr64 (MSR_SKYLAKE_PKG_HDC_CONFIG, Msr.Uint64);\r
925 @endcode\r
04e7a465 926 @note MSR_SKYLAKE_PKG_HDC_CONFIG is defined as MSR_PKG_HDC_CONFIG in SDM.\r
6b55a245
MK		 927**/\r
928#define MSR_SKYLAKE_PKG_HDC_CONFIG 0x00000652\r
929\r
930/**\r
931 MSR information returned for MSR index #MSR_SKYLAKE_PKG_HDC_CONFIG\r
932**/\r
933typedef union {\r
934 ///\r
935 /// Individual bit fields\r
936 ///\r
937 struct {\r
938 ///\r
939 /// [Bits 2:0] PKG_Cx_Monitor. Configures Package Cx state threshold for\r
940 /// MSR_PKG_HDC_DEEP_RESIDENCY.\r
941 ///\r
942 UINT32 PKG_Cx_Monitor:3;\r
943 UINT32 Reserved1:29;\r
944 UINT32 Reserved2:32;\r
945 } Bits;\r
946 ///\r
947 /// All bit fields as a 32-bit value\r
948 ///\r
949 UINT32 Uint32;\r
950 ///\r
951 /// All bit fields as a 64-bit value\r
952 ///\r
953 UINT64 Uint64;\r
954} MSR_SKYLAKE_PKG_HDC_CONFIG_REGISTER;\r
955\r
956\r
957/**\r
958 Core. Core HDC Idle Residency. (R/O). Core_Cx_Duty_Cycle_Cnt.\r
959\r
960 @param ECX MSR_SKYLAKE_CORE_HDC_RESIDENCY (0x00000653)\r
961 @param EAX Lower 32-bits of MSR value.\r
962 @param EDX Upper 32-bits of MSR value.\r
963\r
964 <b>Example usage</b>\r
965 @code\r
966 UINT64 Msr;\r
967\r
968 Msr = AsmReadMsr64 (MSR_SKYLAKE_CORE_HDC_RESIDENCY);\r
969 @endcode\r
04e7a465 970 @note MSR_SKYLAKE_CORE_HDC_RESIDENCY is defined as MSR_CORE_HDC_RESIDENCY in SDM.\r
6b55a245
MK		 971**/\r
972#define MSR_SKYLAKE_CORE_HDC_RESIDENCY 0x00000653\r
973\r
974\r
975/**\r
976 Package. Accumulate the cycles the package was in C2 state and at least one\r
977 logical processor was in forced idle. (R/O). Pkg_C2_Duty_Cycle_Cnt.\r
978\r
979 @param ECX MSR_SKYLAKE_PKG_HDC_SHALLOW_RESIDENCY (0x00000655)\r
980 @param EAX Lower 32-bits of MSR value.\r
981 @param EDX Upper 32-bits of MSR value.\r
982\r
983 <b>Example usage</b>\r
984 @code\r
985 UINT64 Msr;\r
986\r
987 Msr = AsmReadMsr64 (MSR_SKYLAKE_PKG_HDC_SHALLOW_RESIDENCY);\r
988 @endcode\r
04e7a465 989 @note MSR_SKYLAKE_PKG_HDC_SHALLOW_RESIDENCY is defined as MSR_PKG_HDC_SHALLOW_RESIDENCY in SDM.\r
6b55a245
MK		 990**/\r
991#define MSR_SKYLAKE_PKG_HDC_SHALLOW_RESIDENCY 0x00000655\r
992\r
993\r
994/**\r
995 Package. Package Cx HDC Idle Residency. (R/O). Pkg_Cx_Duty_Cycle_Cnt.\r
996\r
997 @param ECX MSR_SKYLAKE_PKG_HDC_DEEP_RESIDENCY (0x00000656)\r
998 @param EAX Lower 32-bits of MSR value.\r
999 @param EDX Upper 32-bits of MSR value.\r
1000\r
1001 <b>Example usage</b>\r
1002 @code\r
1003 UINT64 Msr;\r
1004\r
1005 Msr = AsmReadMsr64 (MSR_SKYLAKE_PKG_HDC_DEEP_RESIDENCY);\r
1006 @endcode\r
04e7a465 1007 @note MSR_SKYLAKE_PKG_HDC_DEEP_RESIDENCY is defined as MSR_PKG_HDC_DEEP_RESIDENCY in SDM.\r
6b55a245
MK		 1008**/\r
1009#define MSR_SKYLAKE_PKG_HDC_DEEP_RESIDENCY 0x00000656\r
1010\r
1011\r
1012/**\r
1013 Package. Core-count Weighted C0 Residency. (R/O). Increment at the same rate\r
1014 as the TSC. The increment each cycle is weighted by the number of processor\r
1015 cores in the package that reside in C0. If N cores are simultaneously in C0,\r
1016 then each cycle the counter increments by N.\r
1017\r
1018 @param ECX MSR_SKYLAKE_WEIGHTED_CORE_C0 (0x00000658)\r
1019 @param EAX Lower 32-bits of MSR value.\r
1020 @param EDX Upper 32-bits of MSR value.\r
1021\r
1022 <b>Example usage</b>\r
1023 @code\r
1024 UINT64 Msr;\r
1025\r
1026 Msr = AsmReadMsr64 (MSR_SKYLAKE_WEIGHTED_CORE_C0);\r
1027 @endcode\r
04e7a465 1028 @note MSR_SKYLAKE_WEIGHTED_CORE_C0 is defined as MSR_WEIGHTED_CORE_C0 in SDM.\r
6b55a245
MK		 1029**/\r
1030#define MSR_SKYLAKE_WEIGHTED_CORE_C0 0x00000658\r
1031\r
1032\r
1033/**\r
1034 Package. Any Core C0 Residency. (R/O). Increment at the same rate as the\r
1035 TSC. The increment each cycle is one if any processor core in the package is\r
1036 in C0.\r
1037\r
1038 @param ECX MSR_SKYLAKE_ANY_CORE_C0 (0x00000659)\r
1039 @param EAX Lower 32-bits of MSR value.\r
1040 @param EDX Upper 32-bits of MSR value.\r
1041\r
1042 <b>Example usage</b>\r
1043 @code\r
1044 UINT64 Msr;\r
1045\r
1046 Msr = AsmReadMsr64 (MSR_SKYLAKE_ANY_CORE_C0);\r
1047 @endcode\r
04e7a465 1048 @note MSR_SKYLAKE_ANY_CORE_C0 is defined as MSR_ANY_CORE_C0 in SDM.\r
6b55a245
MK		 1049**/\r
1050#define MSR_SKYLAKE_ANY_CORE_C0 0x00000659\r
1051\r
1052\r
1053/**\r
1054 Package. Any Graphics Engine C0 Residency. (R/O). Increment at the same rate\r
1055 as the TSC. The increment each cycle is one if any processor graphic\r
1056 device's compute engines are in C0.\r
1057\r
1058 @param ECX MSR_SKYLAKE_ANY_GFXE_C0 (0x0000065A)\r
1059 @param EAX Lower 32-bits of MSR value.\r
1060 @param EDX Upper 32-bits of MSR value.\r
1061\r
1062 <b>Example usage</b>\r
1063 @code\r
1064 UINT64 Msr;\r
1065\r
1066 Msr = AsmReadMsr64 (MSR_SKYLAKE_ANY_GFXE_C0);\r
1067 @endcode\r
04e7a465 1068 @note MSR_SKYLAKE_ANY_GFXE_C0 is defined as MSR_ANY_GFXE_C0 in SDM.\r
6b55a245
MK		 1069**/\r
1070#define MSR_SKYLAKE_ANY_GFXE_C0 0x0000065A\r
1071\r
1072\r
1073/**\r
1074 Package. Core and Graphics Engine Overlapped C0 Residency. (R/O). Increment\r
1075 at the same rate as the TSC. The increment each cycle is one if at least one\r
1076 compute engine of the processor graphics is in C0 and at least one processor\r
1077 core in the package is also in C0.\r
1078\r
1079 @param ECX MSR_SKYLAKE_CORE_GFXE_OVERLAP_C0 (0x0000065B)\r
1080 @param EAX Lower 32-bits of MSR value.\r
1081 @param EDX Upper 32-bits of MSR value.\r
1082\r
1083 <b>Example usage</b>\r
1084 @code\r
1085 UINT64 Msr;\r
1086\r
1087 Msr = AsmReadMsr64 (MSR_SKYLAKE_CORE_GFXE_OVERLAP_C0);\r
1088 @endcode\r
04e7a465 1089 @note MSR_SKYLAKE_CORE_GFXE_OVERLAP_C0 is defined as MSR_CORE_GFXE_OVERLAP_C0 in SDM.\r
6b55a245
MK		 1090**/\r
1091#define MSR_SKYLAKE_CORE_GFXE_OVERLAP_C0 0x0000065B\r
1092\r
1093\r
1094/**\r
1095 Platform*. Platform Power Limit Control (R/W-L) Allows platform BIOS to\r
1096 limit power consumption of the platform devices to the specified values. The\r
1097 Long Duration power consumption is specified via Platform_Power_Limit_1 and\r
1098 Platform_Power_Limit_1_Time. The Short Duration power consumption limit is\r
1099 specified via the Platform_Power_Limit_2 with duration chosen by the\r
1100 processor. The processor implements an exponential-weighted algorithm in the\r
1101 placement of the time windows.\r
1102\r
1103 @param ECX MSR_SKYLAKE_PLATFORM_POWER_LIMIT (0x0000065C)\r
1104 @param EAX Lower 32-bits of MSR value.\r
1105 Described by the type MSR_SKYLAKE_PLATFORM_POWER_LIMIT_REGISTER.\r
1106 @param EDX Upper 32-bits of MSR value.\r
1107 Described by the type MSR_SKYLAKE_PLATFORM_POWER_LIMIT_REGISTER.\r
1108\r
1109 <b>Example usage</b>\r
1110 @code\r
1111 MSR_SKYLAKE_PLATFORM_POWER_LIMIT_REGISTER Msr;\r
1112\r
1113 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_PLATFORM_POWER_LIMIT);\r
1114 AsmWriteMsr64 (MSR_SKYLAKE_PLATFORM_POWER_LIMIT, Msr.Uint64);\r
1115 @endcode\r
04e7a465 1116 @note MSR_SKYLAKE_PLATFORM_POWER_LIMIT is defined as MSR_PLATFORM_POWER_LIMIT in SDM.\r
6b55a245
MK		 1117**/\r
1118#define MSR_SKYLAKE_PLATFORM_POWER_LIMIT 0x0000065C\r
1119\r
1120/**\r
1121 MSR information returned for MSR index #MSR_SKYLAKE_PLATFORM_POWER_LIMIT\r
1122**/\r
1123typedef union {\r
1124 ///\r
1125 /// Individual bit fields\r
1126 ///\r
1127 struct {\r
1128 ///\r
1129 /// [Bits 14:0] Platform Power Limit #1. Average Power limit value which\r
1130 /// the platform must not exceed over a time window as specified by\r
1131 /// Power_Limit_1_TIME field. The default value is the Thermal Design\r
1132 /// Power (TDP) and varies with product skus. The unit is specified in\r
1133 /// MSR_RAPLPOWER_UNIT.\r
1134 ///\r
1135 UINT32 PlatformPowerLimit1:15;\r
1136 ///\r
1137 /// [Bit 15] Enable Platform Power Limit #1. When set, enables the\r
1138 /// processor to apply control policy such that the platform power does\r
1139 /// not exceed Platform Power limit #1 over the time window specified by\r
1140 /// Power Limit #1 Time Window.\r
1141 ///\r
1142 UINT32 EnablePlatformPowerLimit1:1;\r
1143 ///\r
1144 /// [Bit 16] Platform Clamping Limitation #1. When set, allows the\r
1145 /// processor to go below the OS requested P states in order to maintain\r
1146 /// the power below specified Platform Power Limit #1 value. This bit is\r
1147 /// writeable only when CPUID (EAX=6):EAX[4] is set.\r
1148 ///\r
1149 UINT32 PlatformClampingLimitation1:1;\r
1150 ///\r
1151 /// [Bits 23:17] Time Window for Platform Power Limit #1. Specifies the\r
1152 /// duration of the time window over which Platform Power Limit 1 value\r
1153 /// should be maintained for sustained long duration. This field is made\r
1154 /// up of two numbers from the following equation: Time Window = (float)\r
1155 /// ((1+(X/4))*(2^Y)), where: X. = POWER_LIMIT_1_TIME[23:22] Y. =\r
1156 /// POWER_LIMIT_1_TIME[21:17]. The maximum allowed value in this field is\r
1157 /// defined in MSR_PKG_POWER_INFO[PKG_MAX_WIN]. The default value is 0DH,\r
1158 /// The unit is specified in MSR_RAPLPOWER_UNIT[Time Unit].\r
1159 ///\r
1160 UINT32 Time:7;\r
1161 UINT32 Reserved1:8;\r
1162 ///\r
1163 /// [Bits 46:32] Platform Power Limit #2. Average Power limit value which\r
1164 /// the platform must not exceed over the Short Duration time window\r
1165 /// chosen by the processor. The recommended default value is 1.25 times\r
1166 /// the Long Duration Power Limit (i.e. Platform Power Limit # 1).\r
1167 ///\r
1168 UINT32 PlatformPowerLimit2:15;\r
1169 ///\r
1170 /// [Bit 47] Enable Platform Power Limit #2. When set, enables the\r
1171 /// processor to apply control policy such that the platform power does\r
1172 /// not exceed Platform Power limit #2 over the Short Duration time window.\r
1173 ///\r
1174 UINT32 EnablePlatformPowerLimit2:1;\r
1175 ///\r
1176 /// [Bit 48] Platform Clamping Limitation #2. When set, allows the\r
1177 /// processor to go below the OS requested P states in order to maintain\r
1178 /// the power below specified Platform Power Limit #2 value.\r
1179 ///\r
1180 UINT32 PlatformClampingLimitation2:1;\r
1181 UINT32 Reserved2:14;\r
1182 ///\r
1183 /// [Bit 63] Lock. Setting this bit will lock all other bits of this MSR\r
1184 /// until system RESET.\r
1185 ///\r
1186 UINT32 Lock:1;\r
1187 } Bits;\r
1188 ///\r
1189 /// All bit fields as a 64-bit value\r
1190 ///\r
1191 UINT64 Uint64;\r
1192} MSR_SKYLAKE_PLATFORM_POWER_LIMIT_REGISTER;\r
1193\r
1194\r
1195/**\r
1196 Thread. Last Branch Record n From IP (R/W) One of 32 triplets of last\r
1197 branch record registers on the last branch record stack. This part of the\r
1198 stack contains pointers to the source instruction. See also: - Last Branch\r
37cea63f 1199 Record Stack TOS at 1C9H - Section 17.10.\r
6b55a245
MK		 1200\r
1201 @param ECX MSR_SKYLAKE_LASTBRANCH_n_FROM_IP\r
1202 @param EAX Lower 32-bits of MSR value.\r
1203 @param EDX Upper 32-bits of MSR value.\r
1204\r
1205 <b>Example usage</b>\r
1206 @code\r
1207 UINT64 Msr;\r
1208\r
1209 Msr = AsmReadMsr64 (MSR_SKYLAKE_LASTBRANCH_16_FROM_IP);\r
1210 AsmWriteMsr64 (MSR_SKYLAKE_LASTBRANCH_16_FROM_IP, Msr);\r
1211 @endcode\r
04e7a465
JF		 1212 @note MSR_SKYLAKE_LASTBRANCH_16_FROM_IP is defined as MSR_LASTBRANCH_16_FROM_IP in SDM.\r
1213 MSR_SKYLAKE_LASTBRANCH_17_FROM_IP is defined as MSR_LASTBRANCH_17_FROM_IP in SDM.\r
1214 MSR_SKYLAKE_LASTBRANCH_18_FROM_IP is defined as MSR_LASTBRANCH_18_FROM_IP in SDM.\r
1215 MSR_SKYLAKE_LASTBRANCH_19_FROM_IP is defined as MSR_LASTBRANCH_19_FROM_IP in SDM.\r
1216 MSR_SKYLAKE_LASTBRANCH_20_FROM_IP is defined as MSR_LASTBRANCH_20_FROM_IP in SDM.\r
1217 MSR_SKYLAKE_LASTBRANCH_21_FROM_IP is defined as MSR_LASTBRANCH_21_FROM_IP in SDM.\r
1218 MSR_SKYLAKE_LASTBRANCH_22_FROM_IP is defined as MSR_LASTBRANCH_22_FROM_IP in SDM.\r
1219 MSR_SKYLAKE_LASTBRANCH_23_FROM_IP is defined as MSR_LASTBRANCH_23_FROM_IP in SDM.\r
1220 MSR_SKYLAKE_LASTBRANCH_24_FROM_IP is defined as MSR_LASTBRANCH_24_FROM_IP in SDM.\r
1221 MSR_SKYLAKE_LASTBRANCH_25_FROM_IP is defined as MSR_LASTBRANCH_25_FROM_IP in SDM.\r
1222 MSR_SKYLAKE_LASTBRANCH_26_FROM_IP is defined as MSR_LASTBRANCH_26_FROM_IP in SDM.\r
1223 MSR_SKYLAKE_LASTBRANCH_27_FROM_IP is defined as MSR_LASTBRANCH_27_FROM_IP in SDM.\r
1224 MSR_SKYLAKE_LASTBRANCH_28_FROM_IP is defined as MSR_LASTBRANCH_28_FROM_IP in SDM.\r
1225 MSR_SKYLAKE_LASTBRANCH_29_FROM_IP is defined as MSR_LASTBRANCH_29_FROM_IP in SDM.\r
1226 MSR_SKYLAKE_LASTBRANCH_30_FROM_IP is defined as MSR_LASTBRANCH_30_FROM_IP in SDM.\r
1227 MSR_SKYLAKE_LASTBRANCH_31_FROM_IP is defined as MSR_LASTBRANCH_31_FROM_IP in SDM.\r
6b55a245
MK		 1228 @{\r
1229**/\r
1230#define MSR_SKYLAKE_LASTBRANCH_16_FROM_IP 0x00000690\r
1231#define MSR_SKYLAKE_LASTBRANCH_17_FROM_IP 0x00000691\r
1232#define MSR_SKYLAKE_LASTBRANCH_18_FROM_IP 0x00000692\r
1233#define MSR_SKYLAKE_LASTBRANCH_19_FROM_IP 0x00000693\r
1234#define MSR_SKYLAKE_LASTBRANCH_20_FROM_IP 0x00000694\r
1235#define MSR_SKYLAKE_LASTBRANCH_21_FROM_IP 0x00000695\r
1236#define MSR_SKYLAKE_LASTBRANCH_22_FROM_IP 0x00000696\r
1237#define MSR_SKYLAKE_LASTBRANCH_23_FROM_IP 0x00000697\r
1238#define MSR_SKYLAKE_LASTBRANCH_24_FROM_IP 0x00000698\r
1239#define MSR_SKYLAKE_LASTBRANCH_25_FROM_IP 0x00000699\r
1240#define MSR_SKYLAKE_LASTBRANCH_26_FROM_IP 0x0000069A\r
1241#define MSR_SKYLAKE_LASTBRANCH_27_FROM_IP 0x0000069B\r
1242#define MSR_SKYLAKE_LASTBRANCH_28_FROM_IP 0x0000069C\r
1243#define MSR_SKYLAKE_LASTBRANCH_29_FROM_IP 0x0000069D\r
1244#define MSR_SKYLAKE_LASTBRANCH_30_FROM_IP 0x0000069E\r
1245#define MSR_SKYLAKE_LASTBRANCH_31_FROM_IP 0x0000069F\r
1246/// @}\r
1247\r
37cea63f
HW		 1248\r
1249/**\r
1250 Package. Indicator of Frequency Clipping in the Processor Graphics (R/W)\r
1251 (frequency refers to processor graphics frequency).\r
1252\r
1253 @param ECX MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS (0x000006B0)\r
1254 @param EAX Lower 32-bits of MSR value.\r
1255 Described by the type MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS_REGISTER.\r
1256 @param EDX Upper 32-bits of MSR value.\r
1257 Described by the type MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS_REGISTER.\r
1258\r
1259 <b>Example usage</b>\r
1260 @code\r
1261 MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS_REGISTER Msr;\r
1262\r
1263 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS);\r
1264 AsmWriteMsr64 (MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS, Msr.Uint64);\r
1265 @endcode\r
1266 @note MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS is defined as MSR_GRAPHICS_PERF_LIMIT_REASONS in SDM.\r
1267**/\r
1268#define MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS 0x000006B0\r
1269\r
1270/**\r
1271 MSR information returned for MSR index\r
1272 #MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS\r
1273**/\r
1274typedef union {\r
1275 ///\r
1276 /// Individual bit fields\r
1277 ///\r
1278 struct {\r
1279 ///\r
1280 /// [Bit 0] PROCHOT Status (R0) When set, frequency is reduced due to\r
1281 /// assertion of external PROCHOT.\r
1282 ///\r
1283 UINT32 PROCHOT_Status:1;\r
1284 ///\r
1285 /// [Bit 1] Thermal Status (R0) When set, frequency is reduced due to a\r
1286 /// thermal event.\r
1287 ///\r
1288 UINT32 ThermalStatus:1;\r
1289 UINT32 Reserved1:3;\r
1290 ///\r
1291 /// [Bit 5] Running Average Thermal Limit Status (R0) When set, frequency\r
1292 /// is reduced due to running average thermal limit.\r
1293 ///\r
1294 UINT32 RunningAverageThermalLimitStatus:1;\r
1295 ///\r
1296 /// [Bit 6] VR Therm Alert Status (R0) When set, frequency is reduced due\r
1297 /// to a thermal alert from a processor Voltage Regulator.\r
1298 ///\r
1299 UINT32 VRThermAlertStatus:1;\r
1300 ///\r
1301 /// [Bit 7] VR Thermal Design Current Status (R0) When set, frequency is\r
1302 /// reduced due to VR TDC limit.\r
1303 ///\r
1304 UINT32 VRThermalDesignCurrentStatus:1;\r
1305 ///\r
1306 /// [Bit 8] Other Status (R0) When set, frequency is reduced due to\r
1307 /// electrical or other constraints.\r
1308 ///\r
1309 UINT32 OtherStatus:1;\r
1310 UINT32 Reserved2:1;\r
1311 ///\r
1312 /// [Bit 10] Package/Platform-Level Power Limiting PL1 Status (R0) When\r
1313 /// set, frequency is reduced due to package/platform-level power limiting\r
1314 /// PL1.\r
1315 ///\r
1316 UINT32 PL1Status:1;\r
1317 ///\r
1318 /// [Bit 11] Package/Platform-Level PL2 Power Limiting Status (R0) When\r
1319 /// set, frequency is reduced due to package/platform-level power limiting\r
1320 /// PL2/PL3.\r
1321 ///\r
1322 UINT32 PL2Status:1;\r
1323 ///\r
1324 /// [Bit 12] Inefficient Operation Status (R0) When set, processor\r
1325 /// graphics frequency is operating below target frequency.\r
1326 ///\r
1327 UINT32 InefficientOperationStatus:1;\r
1328 UINT32 Reserved3:3;\r
1329 ///\r
1330 /// [Bit 16] PROCHOT Log When set, indicates that the PROCHOT Status bit\r
1331 /// has asserted since the log bit was last cleared. This log bit will\r
1332 /// remain set until cleared by software writing 0.\r
1333 ///\r
1334 UINT32 PROCHOT_Log:1;\r
1335 ///\r
1336 /// [Bit 17] Thermal Log When set, indicates that the Thermal Status bit\r
1337 /// has asserted since the log bit was last cleared. This log bit will\r
1338 /// remain set until cleared by software writing 0.\r
1339 ///\r
1340 UINT32 ThermalLog:1;\r
1341 UINT32 Reserved4:3;\r
1342 ///\r
1343 /// [Bit 21] Running Average Thermal Limit Log When set, indicates that\r
1344 /// the RATL Status bit has asserted since the log bit was last cleared.\r
1345 /// This log bit will remain set until cleared by software writing 0.\r
1346 ///\r
1347 UINT32 RunningAverageThermalLimitLog:1;\r
1348 ///\r
1349 /// [Bit 22] VR Therm Alert Log When set, indicates that the VR Therm\r
1350 /// Alert Status bit has asserted since the log bit was last cleared. This\r
1351 /// log bit will remain set until cleared by software writing 0.\r
1352 ///\r
1353 UINT32 VRThermAlertLog:1;\r
1354 ///\r
1355 /// [Bit 23] VR Thermal Design Current Log When set, indicates that the\r
1356 /// VR Therm Alert Status bit has asserted since the log bit was last\r
1357 /// cleared. This log bit will remain set until cleared by software\r
1358 /// writing 0.\r
1359 ///\r
1360 UINT32 VRThermalDesignCurrentLog:1;\r
1361 ///\r
1362 /// [Bit 24] Other Log When set, indicates that the OTHER Status bit has\r
1363 /// asserted since the log bit was last cleared. This log bit will remain\r
1364 /// set until cleared by software writing 0.\r
1365 ///\r
1366 UINT32 OtherLog:1;\r
1367 UINT32 Reserved5:1;\r
1368 ///\r
1369 /// [Bit 26] Package/Platform-Level PL1 Power Limiting Log When set,\r
1370 /// indicates that the Package/Platform Level PL1 Power Limiting Status\r
1371 /// bit has asserted since the log bit was last cleared. This log bit will\r
1372 /// remain set until cleared by software writing 0.\r
1373 ///\r
1374 UINT32 PL1Log:1;\r
1375 ///\r
1376 /// [Bit 27] Package/Platform-Level PL2 Power Limiting Log When set,\r
1377 /// indicates that the Package/Platform Level PL2 Power Limiting Status\r
1378 /// bit has asserted since the log bit was last cleared. This log bit will\r
1379 /// remain set until cleared by software writing 0.\r
1380 ///\r
1381 UINT32 PL2Log:1;\r
1382 ///\r
1383 /// [Bit 28] Inefficient Operation Log When set, indicates that the\r
1384 /// Inefficient Operation Status bit has asserted since the log bit was\r
1385 /// last cleared. This log bit will remain set until cleared by software\r
1386 /// writing 0.\r
1387 ///\r
1388 UINT32 InefficientOperationLog:1;\r
1389 UINT32 Reserved6:3;\r
1390 UINT32 Reserved7:32;\r
1391 } Bits;\r
1392 ///\r
1393 /// All bit fields as a 32-bit value\r
1394 ///\r
1395 UINT32 Uint32;\r
1396 ///\r
1397 /// All bit fields as a 64-bit value\r
1398 ///\r
1399 UINT64 Uint64;\r
1400} MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS_REGISTER;\r
1401\r
1402\r
1403/**\r
1404 Package. Indicator of Frequency Clipping in the Ring Interconnect (R/W)\r
1405 (frequency refers to ring interconnect in the uncore).\r
1406\r
1407 @param ECX MSR_SKYLAKE_RING_PERF_LIMIT_REASONS (0x000006B1)\r
1408 @param EAX Lower 32-bits of MSR value.\r
1409 Described by the type MSR_SKYLAKE_RING_PERF_LIMIT_REASONS_REGISTER.\r
1410 @param EDX Upper 32-bits of MSR value.\r
1411 Described by the type MSR_SKYLAKE_RING_PERF_LIMIT_REASONS_REGISTER.\r
1412\r
1413 <b>Example usage</b>\r
1414 @code\r
1415 MSR_SKYLAKE_RING_PERF_LIMIT_REASONS_REGISTER Msr;\r
1416\r
1417 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_RING_PERF_LIMIT_REASONS);\r
1418 AsmWriteMsr64 (MSR_SKYLAKE_RING_PERF_LIMIT_REASONS, Msr.Uint64);\r
1419 @endcode\r
1420 @note MSR_SKYLAKE_RING_PERF_LIMIT_REASONS is defined as MSR_RING_PERF_LIMIT_REASONS in SDM.\r
1421**/\r
1422#define MSR_SKYLAKE_RING_PERF_LIMIT_REASONS 0x000006B1\r
1423\r
1424/**\r
1425 MSR information returned for MSR index #MSR_SKYLAKE_RING_PERF_LIMIT_REASONS\r
1426**/\r
1427typedef union {\r
1428 ///\r
1429 /// Individual bit fields\r
1430 ///\r
1431 struct {\r
1432 ///\r
1433 /// [Bit 0] PROCHOT Status (R0) When set, frequency is reduced due to\r
1434 /// assertion of external PROCHOT.\r
1435 ///\r
1436 UINT32 PROCHOT_Status:1;\r
1437 ///\r
1438 /// [Bit 1] Thermal Status (R0) When set, frequency is reduced due to a\r
1439 /// thermal event.\r
1440 ///\r
1441 UINT32 ThermalStatus:1;\r
1442 UINT32 Reserved1:3;\r
1443 ///\r
1444 /// [Bit 5] Running Average Thermal Limit Status (R0) When set, frequency\r
1445 /// is reduced due to running average thermal limit.\r
1446 ///\r
1447 UINT32 RunningAverageThermalLimitStatus:1;\r
1448 ///\r
1449 /// [Bit 6] VR Therm Alert Status (R0) When set, frequency is reduced due\r
1450 /// to a thermal alert from a processor Voltage Regulator.\r
1451 ///\r
1452 UINT32 VRThermAlertStatus:1;\r
1453 ///\r
1454 /// [Bit 7] VR Thermal Design Current Status (R0) When set, frequency is\r
1455 /// reduced due to VR TDC limit.\r
1456 ///\r
1457 UINT32 VRThermalDesignCurrentStatus:1;\r
1458 ///\r
1459 /// [Bit 8] Other Status (R0) When set, frequency is reduced due to\r
1460 /// electrical or other constraints.\r
1461 ///\r
1462 UINT32 OtherStatus:1;\r
1463 UINT32 Reserved2:1;\r
1464 ///\r
1465 /// [Bit 10] Package/Platform-Level Power Limiting PL1 Status (R0) When\r
1466 /// set, frequency is reduced due to package/Platform-level power limiting\r
1467 /// PL1.\r
1468 ///\r
1469 UINT32 PL1Status:1;\r
1470 ///\r
1471 /// [Bit 11] Package/Platform-Level PL2 Power Limiting Status (R0) When\r
1472 /// set, frequency is reduced due to package/Platform-level power limiting\r
1473 /// PL2/PL3.\r
1474 ///\r
1475 UINT32 PL2Status:1;\r
1476 UINT32 Reserved3:4;\r
1477 ///\r
1478 /// [Bit 16] PROCHOT Log When set, indicates that the PROCHOT Status bit\r
1479 /// has asserted since the log bit was last cleared. This log bit will\r
1480 /// remain set until cleared by software writing 0.\r
1481 ///\r
1482 UINT32 PROCHOT_Log:1;\r
1483 ///\r
1484 /// [Bit 17] Thermal Log When set, indicates that the Thermal Status bit\r
1485 /// has asserted since the log bit was last cleared. This log bit will\r
1486 /// remain set until cleared by software writing 0.\r
1487 ///\r
1488 UINT32 ThermalLog:1;\r
1489 UINT32 Reserved4:3;\r
1490 ///\r
1491 /// [Bit 21] Running Average Thermal Limit Log When set, indicates that\r
1492 /// the RATL Status bit has asserted since the log bit was last cleared.\r
1493 /// This log bit will remain set until cleared by software writing 0.\r
1494 ///\r
1495 UINT32 RunningAverageThermalLimitLog:1;\r
1496 ///\r
1497 /// [Bit 22] VR Therm Alert Log When set, indicates that the VR Therm\r
1498 /// Alert Status bit has asserted since the log bit was last cleared. This\r
1499 /// log bit will remain set until cleared by software writing 0.\r
1500 ///\r
1501 UINT32 VRThermAlertLog:1;\r
1502 ///\r
1503 /// [Bit 23] VR Thermal Design Current Log When set, indicates that the\r
1504 /// VR Therm Alert Status bit has asserted since the log bit was last\r
1505 /// cleared. This log bit will remain set until cleared by software\r
1506 /// writing 0.\r
1507 ///\r
1508 UINT32 VRThermalDesignCurrentLog:1;\r
1509 ///\r
1510 /// [Bit 24] Other Log When set, indicates that the OTHER Status bit has\r
1511 /// asserted since the log bit was last cleared. This log bit will remain\r
1512 /// set until cleared by software writing 0.\r
1513 ///\r
1514 UINT32 OtherLog:1;\r
1515 UINT32 Reserved5:1;\r
1516 ///\r
1517 /// [Bit 26] Package/Platform-Level PL1 Power Limiting Log When set,\r
1518 /// indicates that the Package/Platform Level PL1 Power Limiting Status\r
1519 /// bit has asserted since the log bit was last cleared. This log bit will\r
1520 /// remain set until cleared by software writing 0.\r
1521 ///\r
1522 UINT32 PL1Log:1;\r
1523 ///\r
1524 /// [Bit 27] Package/Platform-Level PL2 Power Limiting Log When set,\r
1525 /// indicates that the Package/Platform Level PL2 Power Limiting Status\r
1526 /// bit has asserted since the log bit was last cleared. This log bit will\r
1527 /// remain set until cleared by software writing 0.\r
1528 ///\r
1529 UINT32 PL2Log:1;\r
1530 UINT32 Reserved6:4;\r
1531 UINT32 Reserved7:32;\r
1532 } Bits;\r
1533 ///\r
1534 /// All bit fields as a 32-bit value\r
1535 ///\r
1536 UINT32 Uint32;\r
1537 ///\r
1538 /// All bit fields as a 64-bit value\r
1539 ///\r
1540 UINT64 Uint64;\r
1541} MSR_SKYLAKE_RING_PERF_LIMIT_REASONS_REGISTER;\r
1542\r
1543\r
6b55a245
MK		 1544/**\r
1545 Thread. Last Branch Record n To IP (R/W) One of 32 triplets of last branch\r
1546 record registers on the last branch record stack. This part of the stack\r
1547 contains pointers to the destination instruction. See also: - Last Branch\r
37cea63f 1548 Record Stack TOS at 1C9H - Section 17.10.\r
6b55a245
MK		 1549\r
1550 @param ECX MSR_SKYLAKE_LASTBRANCH_n_TO_IP\r
1551 @param EAX Lower 32-bits of MSR value.\r
1552 @param EDX Upper 32-bits of MSR value.\r
1553\r
1554 <b>Example usage</b>\r
1555 @code\r
1556 UINT64 Msr;\r
1557\r
1558 Msr = AsmReadMsr64 (MSR_SKYLAKE_LASTBRANCH_16_TO_IP);\r
1559 AsmWriteMsr64 (MSR_SKYLAKE_LASTBRANCH_16_TO_IP, Msr);\r
1560 @endcode\r
04e7a465
JF		 1561 @note MSR_SKYLAKE_LASTBRANCH_16_TO_IP is defined as MSR_LASTBRANCH_16_TO_IP in SDM.\r
1562 MSR_SKYLAKE_LASTBRANCH_17_TO_IP is defined as MSR_LASTBRANCH_17_TO_IP in SDM.\r
1563 MSR_SKYLAKE_LASTBRANCH_18_TO_IP is defined as MSR_LASTBRANCH_18_TO_IP in SDM.\r
1564 MSR_SKYLAKE_LASTBRANCH_19_TO_IP is defined as MSR_LASTBRANCH_19_TO_IP in SDM.\r
1565 MSR_SKYLAKE_LASTBRANCH_20_TO_IP is defined as MSR_LASTBRANCH_20_TO_IP in SDM.\r
1566 MSR_SKYLAKE_LASTBRANCH_21_TO_IP is defined as MSR_LASTBRANCH_21_TO_IP in SDM.\r
1567 MSR_SKYLAKE_LASTBRANCH_22_TO_IP is defined as MSR_LASTBRANCH_22_TO_IP in SDM.\r
1568 MSR_SKYLAKE_LASTBRANCH_23_TO_IP is defined as MSR_LASTBRANCH_23_TO_IP in SDM.\r
1569 MSR_SKYLAKE_LASTBRANCH_24_TO_IP is defined as MSR_LASTBRANCH_24_TO_IP in SDM.\r
1570 MSR_SKYLAKE_LASTBRANCH_25_TO_IP is defined as MSR_LASTBRANCH_25_TO_IP in SDM.\r
1571 MSR_SKYLAKE_LASTBRANCH_26_TO_IP is defined as MSR_LASTBRANCH_26_TO_IP in SDM.\r
1572 MSR_SKYLAKE_LASTBRANCH_27_TO_IP is defined as MSR_LASTBRANCH_27_TO_IP in SDM.\r
1573 MSR_SKYLAKE_LASTBRANCH_28_TO_IP is defined as MSR_LASTBRANCH_28_TO_IP in SDM.\r
1574 MSR_SKYLAKE_LASTBRANCH_29_TO_IP is defined as MSR_LASTBRANCH_29_TO_IP in SDM.\r
1575 MSR_SKYLAKE_LASTBRANCH_30_TO_IP is defined as MSR_LASTBRANCH_30_TO_IP in SDM.\r
1576 MSR_SKYLAKE_LASTBRANCH_31_TO_IP is defined as MSR_LASTBRANCH_31_TO_IP in SDM.\r
6b55a245
MK		 1577 @{\r
1578**/\r
1579#define MSR_SKYLAKE_LASTBRANCH_16_TO_IP 0x000006D0\r
1580#define MSR_SKYLAKE_LASTBRANCH_17_TO_IP 0x000006D1\r
1581#define MSR_SKYLAKE_LASTBRANCH_18_TO_IP 0x000006D2\r
1582#define MSR_SKYLAKE_LASTBRANCH_19_TO_IP 0x000006D3\r
1583#define MSR_SKYLAKE_LASTBRANCH_20_TO_IP 0x000006D4\r
1584#define MSR_SKYLAKE_LASTBRANCH_21_TO_IP 0x000006D5\r
1585#define MSR_SKYLAKE_LASTBRANCH_22_TO_IP 0x000006D6\r
1586#define MSR_SKYLAKE_LASTBRANCH_23_TO_IP 0x000006D7\r
1587#define MSR_SKYLAKE_LASTBRANCH_24_TO_IP 0x000006D8\r
1588#define MSR_SKYLAKE_LASTBRANCH_25_TO_IP 0x000006D9\r
1589#define MSR_SKYLAKE_LASTBRANCH_26_TO_IP 0x000006DA\r
1590#define MSR_SKYLAKE_LASTBRANCH_27_TO_IP 0x000006DB\r
1591#define MSR_SKYLAKE_LASTBRANCH_28_TO_IP 0x000006DC\r
1592#define MSR_SKYLAKE_LASTBRANCH_29_TO_IP 0x000006DD\r
1593#define MSR_SKYLAKE_LASTBRANCH_30_TO_IP 0x000006DE\r
1594#define MSR_SKYLAKE_LASTBRANCH_31_TO_IP 0x000006DF\r
1595/// @}\r
1596\r
1597\r
1598/**\r
1599 Thread. Last Branch Record n Additional Information (R/W) One of 32 triplet\r
1600 of last branch record registers on the last branch record stack. This part\r
1601 of the stack contains flag, TSX-related and elapsed cycle information. See\r
37cea63f 1602 also: - Last Branch Record Stack TOS at 1C9H - Section 17.7.1, "LBR\r
6b55a245
MK		 1603 Stack.".\r
1604\r
1605 @param ECX MSR_SKYLAKE_LBR_INFO_n\r
1606 @param EAX Lower 32-bits of MSR value.\r
1607 @param EDX Upper 32-bits of MSR value.\r
1608\r
1609 <b>Example usage</b>\r
1610 @code\r
1611 UINT64 Msr;\r
1612\r
1613 Msr = AsmReadMsr64 (MSR_SKYLAKE_LBR_INFO_0);\r
1614 AsmWriteMsr64 (MSR_SKYLAKE_LBR_INFO_0, Msr);\r
1615 @endcode\r
04e7a465
JF		 1616 @note MSR_SKYLAKE_LBR_INFO_0 is defined as MSR_LBR_INFO_0 in SDM.\r
1617 MSR_SKYLAKE_LBR_INFO_1 is defined as MSR_LBR_INFO_1 in SDM.\r
1618 MSR_SKYLAKE_LBR_INFO_2 is defined as MSR_LBR_INFO_2 in SDM.\r
1619 MSR_SKYLAKE_LBR_INFO_3 is defined as MSR_LBR_INFO_3 in SDM.\r
1620 MSR_SKYLAKE_LBR_INFO_4 is defined as MSR_LBR_INFO_4 in SDM.\r
1621 MSR_SKYLAKE_LBR_INFO_5 is defined as MSR_LBR_INFO_5 in SDM.\r
1622 MSR_SKYLAKE_LBR_INFO_6 is defined as MSR_LBR_INFO_6 in SDM.\r
1623 MSR_SKYLAKE_LBR_INFO_7 is defined as MSR_LBR_INFO_7 in SDM.\r
1624 MSR_SKYLAKE_LBR_INFO_8 is defined as MSR_LBR_INFO_8 in SDM.\r
1625 MSR_SKYLAKE_LBR_INFO_9 is defined as MSR_LBR_INFO_9 in SDM.\r
1626 MSR_SKYLAKE_LBR_INFO_10 is defined as MSR_LBR_INFO_10 in SDM.\r
1627 MSR_SKYLAKE_LBR_INFO_11 is defined as MSR_LBR_INFO_11 in SDM.\r
1628 MSR_SKYLAKE_LBR_INFO_12 is defined as MSR_LBR_INFO_12 in SDM.\r
1629 MSR_SKYLAKE_LBR_INFO_13 is defined as MSR_LBR_INFO_13 in SDM.\r
1630 MSR_SKYLAKE_LBR_INFO_14 is defined as MSR_LBR_INFO_14 in SDM.\r
1631 MSR_SKYLAKE_LBR_INFO_15 is defined as MSR_LBR_INFO_15 in SDM.\r
1632 MSR_SKYLAKE_LBR_INFO_16 is defined as MSR_LBR_INFO_16 in SDM.\r
1633 MSR_SKYLAKE_LBR_INFO_17 is defined as MSR_LBR_INFO_17 in SDM.\r
1634 MSR_SKYLAKE_LBR_INFO_18 is defined as MSR_LBR_INFO_18 in SDM.\r
1635 MSR_SKYLAKE_LBR_INFO_19 is defined as MSR_LBR_INFO_19 in SDM.\r
1636 MSR_SKYLAKE_LBR_INFO_20 is defined as MSR_LBR_INFO_20 in SDM.\r
1637 MSR_SKYLAKE_LBR_INFO_21 is defined as MSR_LBR_INFO_21 in SDM.\r
1638 MSR_SKYLAKE_LBR_INFO_22 is defined as MSR_LBR_INFO_22 in SDM.\r
1639 MSR_SKYLAKE_LBR_INFO_23 is defined as MSR_LBR_INFO_23 in SDM.\r
1640 MSR_SKYLAKE_LBR_INFO_24 is defined as MSR_LBR_INFO_24 in SDM.\r
1641 MSR_SKYLAKE_LBR_INFO_25 is defined as MSR_LBR_INFO_25 in SDM.\r
1642 MSR_SKYLAKE_LBR_INFO_26 is defined as MSR_LBR_INFO_26 in SDM.\r
1643 MSR_SKYLAKE_LBR_INFO_27 is defined as MSR_LBR_INFO_27 in SDM.\r
1644 MSR_SKYLAKE_LBR_INFO_28 is defined as MSR_LBR_INFO_28 in SDM.\r
1645 MSR_SKYLAKE_LBR_INFO_29 is defined as MSR_LBR_INFO_29 in SDM.\r
1646 MSR_SKYLAKE_LBR_INFO_30 is defined as MSR_LBR_INFO_30 in SDM.\r
1647 MSR_SKYLAKE_LBR_INFO_31 is defined as MSR_LBR_INFO_31 in SDM.\r
6b55a245
MK		 1648 @{\r
1649**/\r
1650#define MSR_SKYLAKE_LBR_INFO_0 0x00000DC0\r
1651#define MSR_SKYLAKE_LBR_INFO_1 0x00000DC1\r
1652#define MSR_SKYLAKE_LBR_INFO_2 0x00000DC2\r
1653#define MSR_SKYLAKE_LBR_INFO_3 0x00000DC3\r
1654#define MSR_SKYLAKE_LBR_INFO_4 0x00000DC4\r
1655#define MSR_SKYLAKE_LBR_INFO_5 0x00000DC5\r
1656#define MSR_SKYLAKE_LBR_INFO_6 0x00000DC6\r
1657#define MSR_SKYLAKE_LBR_INFO_7 0x00000DC7\r
1658#define MSR_SKYLAKE_LBR_INFO_8 0x00000DC8\r
1659#define MSR_SKYLAKE_LBR_INFO_9 0x00000DC9\r
1660#define MSR_SKYLAKE_LBR_INFO_10 0x00000DCA\r
1661#define MSR_SKYLAKE_LBR_INFO_11 0x00000DCB\r
1662#define MSR_SKYLAKE_LBR_INFO_12 0x00000DCC\r
1663#define MSR_SKYLAKE_LBR_INFO_13 0x00000DCD\r
1664#define MSR_SKYLAKE_LBR_INFO_14 0x00000DCE\r
1665#define MSR_SKYLAKE_LBR_INFO_15 0x00000DCF\r
1666#define MSR_SKYLAKE_LBR_INFO_16 0x00000DD0\r
1667#define MSR_SKYLAKE_LBR_INFO_17 0x00000DD1\r
1668#define MSR_SKYLAKE_LBR_INFO_18 0x00000DD2\r
1669#define MSR_SKYLAKE_LBR_INFO_19 0x00000DD3\r
1670#define MSR_SKYLAKE_LBR_INFO_20 0x00000DD4\r
1671#define MSR_SKYLAKE_LBR_INFO_21 0x00000DD5\r
1672#define MSR_SKYLAKE_LBR_INFO_22 0x00000DD6\r
1673#define MSR_SKYLAKE_LBR_INFO_23 0x00000DD7\r
1674#define MSR_SKYLAKE_LBR_INFO_24 0x00000DD8\r
1675#define MSR_SKYLAKE_LBR_INFO_25 0x00000DD9\r
1676#define MSR_SKYLAKE_LBR_INFO_26 0x00000DDA\r
1677#define MSR_SKYLAKE_LBR_INFO_27 0x00000DDB\r
1678#define MSR_SKYLAKE_LBR_INFO_28 0x00000DDC\r
1679#define MSR_SKYLAKE_LBR_INFO_29 0x00000DDD\r
1680#define MSR_SKYLAKE_LBR_INFO_30 0x00000DDE\r
1681#define MSR_SKYLAKE_LBR_INFO_31 0x00000DDF\r
1682/// @}\r
1683\r
37cea63f
HW		 1684\r
1685/**\r
1686 Package. Uncore fixed counter control (R/W).\r
1687\r
1688 @param ECX MSR_SKYLAKE_UNC_PERF_FIXED_CTRL (0x00000394)\r
1689 @param EAX Lower 32-bits of MSR value.\r
1690 Described by the type MSR_SKYLAKE_UNC_PERF_FIXED_CTRL_REGISTER.\r
1691 @param EDX Upper 32-bits of MSR value.\r
1692 Described by the type MSR_SKYLAKE_UNC_PERF_FIXED_CTRL_REGISTER.\r
1693\r
1694 <b>Example usage</b>\r
1695 @code\r
1696 MSR_SKYLAKE_UNC_PERF_FIXED_CTRL_REGISTER Msr;\r
1697\r
1698 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_UNC_PERF_FIXED_CTRL);\r
1699 AsmWriteMsr64 (MSR_SKYLAKE_UNC_PERF_FIXED_CTRL, Msr.Uint64);\r
1700 @endcode\r
1701 @note MSR_SKYLAKE_UNC_PERF_FIXED_CTRL is defined as MSR_UNC_PERF_FIXED_CTRL in SDM.\r
1702**/\r
1703#define MSR_SKYLAKE_UNC_PERF_FIXED_CTRL 0x00000394\r
1704\r
1705/**\r
1706 MSR information returned for MSR index #MSR_SKYLAKE_UNC_PERF_FIXED_CTRL\r
1707**/\r
1708typedef union {\r
1709 ///\r
1710 /// Individual bit fields\r
1711 ///\r
1712 struct {\r
1713 UINT32 Reserved1:20;\r
1714 ///\r
1715 /// [Bit 20] Enable overflow propagation.\r
1716 ///\r
1717 UINT32 EnableOverflow:1;\r
1718 UINT32 Reserved2:1;\r
1719 ///\r
1720 /// [Bit 22] Enable counting.\r
1721 ///\r
1722 UINT32 EnableCounting:1;\r
1723 UINT32 Reserved3:9;\r
1724 UINT32 Reserved4:32;\r
1725 } Bits;\r
1726 ///\r
1727 /// All bit fields as a 32-bit value\r
1728 ///\r
1729 UINT32 Uint32;\r
1730 ///\r
1731 /// All bit fields as a 64-bit value\r
1732 ///\r
1733 UINT64 Uint64;\r
1734} MSR_SKYLAKE_UNC_PERF_FIXED_CTRL_REGISTER;\r
1735\r
1736\r
1737/**\r
1738 Package. Uncore fixed counter.\r
1739\r
1740 @param ECX MSR_SKYLAKE_UNC_PERF_FIXED_CTR (0x00000395)\r
1741 @param EAX Lower 32-bits of MSR value.\r
1742 Described by the type MSR_SKYLAKE_UNC_PERF_FIXED_CTR_REGISTER.\r
1743 @param EDX Upper 32-bits of MSR value.\r
1744 Described by the type MSR_SKYLAKE_UNC_PERF_FIXED_CTR_REGISTER.\r
1745\r
1746 <b>Example usage</b>\r
1747 @code\r
1748 MSR_SKYLAKE_UNC_PERF_FIXED_CTR_REGISTER Msr;\r
1749\r
1750 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_UNC_PERF_FIXED_CTR);\r
1751 AsmWriteMsr64 (MSR_SKYLAKE_UNC_PERF_FIXED_CTR, Msr.Uint64);\r
1752 @endcode\r
1753 @note MSR_SKYLAKE_UNC_PERF_FIXED_CTR is defined as MSR_UNC_PERF_FIXED_CTR in SDM.\r
1754**/\r
1755#define MSR_SKYLAKE_UNC_PERF_FIXED_CTR 0x00000395\r
1756\r
1757/**\r
1758 MSR information returned for MSR index #MSR_SKYLAKE_UNC_PERF_FIXED_CTR\r
1759**/\r
1760typedef union {\r
1761 ///\r
1762 /// Individual bit fields\r
1763 ///\r
1764 struct {\r
1765 ///\r
1766 /// [Bits 31:0] Current count.\r
1767 ///\r
1768 UINT32 CurrentCount:32;\r
1769 ///\r
1770 /// [Bits 43:32] Current count.\r
1771 ///\r
1772 UINT32 CurrentCountHi:12;\r
1773 UINT32 Reserved:20;\r
1774 } Bits;\r
1775 ///\r
1776 /// All bit fields as a 64-bit value\r
1777 ///\r
1778 UINT64 Uint64;\r
1779} MSR_SKYLAKE_UNC_PERF_FIXED_CTR_REGISTER;\r
1780\r
1781\r
1782/**\r
1783 Package. Uncore C-Box configuration information (R/O).\r
1784\r
1785 @param ECX MSR_SKYLAKE_UNC_CBO_CONFIG (0x00000396)\r
1786 @param EAX Lower 32-bits of MSR value.\r
1787 Described by the type MSR_SKYLAKE_UNC_CBO_CONFIG_REGISTER.\r
1788 @param EDX Upper 32-bits of MSR value.\r
1789 Described by the type MSR_SKYLAKE_UNC_CBO_CONFIG_REGISTER.\r
1790\r
1791 <b>Example usage</b>\r
1792 @code\r
1793 MSR_SKYLAKE_UNC_CBO_CONFIG_REGISTER Msr;\r
1794\r
1795 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_CONFIG);\r
1796 @endcode\r
1797 @note MSR_SKYLAKE_UNC_CBO_CONFIG is defined as MSR_UNC_CBO_CONFIG in SDM.\r
1798**/\r
1799#define MSR_SKYLAKE_UNC_CBO_CONFIG 0x00000396\r
1800\r
1801/**\r
1802 MSR information returned for MSR index #MSR_SKYLAKE_UNC_CBO_CONFIG\r
1803**/\r
1804typedef union {\r
1805 ///\r
1806 /// Individual bit fields\r
1807 ///\r
1808 struct {\r
1809 ///\r
1810 /// [Bits 3:0] Specifies the number of C-Box units with programmable\r
1811 /// counters (including processor cores and processor graphics),.\r
1812 ///\r
1813 UINT32 CBox:4;\r
1814 UINT32 Reserved1:28;\r
1815 UINT32 Reserved2:32;\r
1816 } Bits;\r
1817 ///\r
1818 /// All bit fields as a 32-bit value\r
1819 ///\r
1820 UINT32 Uint32;\r
1821 ///\r
1822 /// All bit fields as a 64-bit value\r
1823 ///\r
1824 UINT64 Uint64;\r
1825} MSR_SKYLAKE_UNC_CBO_CONFIG_REGISTER;\r
1826\r
1827\r
1828/**\r
1829 Package. Uncore Arb unit, performance counter 0.\r
1830\r
1831 @param ECX MSR_SKYLAKE_UNC_ARB_PERFCTR0 (0x000003B0)\r
1832 @param EAX Lower 32-bits of MSR value.\r
1833 @param EDX Upper 32-bits of MSR value.\r
1834\r
1835 <b>Example usage</b>\r
1836 @code\r
1837 UINT64 Msr;\r
1838\r
1839 Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_ARB_PERFCTR0);\r
1840 AsmWriteMsr64 (MSR_SKYLAKE_UNC_ARB_PERFCTR0, Msr);\r
1841 @endcode\r
1842 @note MSR_SKYLAKE_UNC_ARB_PERFCTR0 is defined as MSR_UNC_ARB_PERFCTR0 in SDM.\r
1843**/\r
1844#define MSR_SKYLAKE_UNC_ARB_PERFCTR0 0x000003B0\r
1845\r
1846\r
1847/**\r
1848 Package. Uncore Arb unit, performance counter 1.\r
1849\r
1850 @param ECX MSR_SKYLAKE_UNC_ARB_PERFCTR1 (0x000003B1)\r
1851 @param EAX Lower 32-bits of MSR value.\r
1852 @param EDX Upper 32-bits of MSR value.\r
1853\r
1854 <b>Example usage</b>\r
1855 @code\r
1856 UINT64 Msr;\r
1857\r
1858 Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_ARB_PERFCTR1);\r
1859 AsmWriteMsr64 (MSR_SKYLAKE_UNC_ARB_PERFCTR1, Msr);\r
1860 @endcode\r
1861 @note MSR_SKYLAKE_UNC_ARB_PERFCTR1 is defined as MSR_UNC_ARB_PERFCTR1 in SDM.\r
1862**/\r
1863#define MSR_SKYLAKE_UNC_ARB_PERFCTR1 0x000003B1\r
1864\r
1865\r
1866/**\r
1867 Package. Uncore Arb unit, counter 0 event select MSR.\r
1868\r
1869 @param ECX MSR_SKYLAKE_UNC_ARB_PERFEVTSEL0 (0x000003B2)\r
1870 @param EAX Lower 32-bits of MSR value.\r
1871 @param EDX Upper 32-bits of MSR value.\r
1872\r
1873 <b>Example usage</b>\r
1874 @code\r
1875 UINT64 Msr;\r
1876\r
1877 Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_ARB_PERFEVTSEL0);\r
1878 AsmWriteMsr64 (MSR_SKYLAKE_UNC_ARB_PERFEVTSEL0, Msr);\r
1879 @endcode\r
1880 @note MSR_SKYLAKE_UNC_ARB_PERFEVTSEL0 is defined as MSR_UNC_ARB_PERFEVTSEL0 in SDM.\r
1881**/\r
1882#define MSR_SKYLAKE_UNC_ARB_PERFEVTSEL0 0x000003B2\r
1883\r
1884\r
1885/**\r
1886 Package. Uncore Arb unit, counter 1 event select MSR.\r
1887\r
1888 @param ECX MSR_SKYLAKE_UNC_ARB_PERFEVTSEL1 (0x000003B3)\r
1889 @param EAX Lower 32-bits of MSR value.\r
1890 @param EDX Upper 32-bits of MSR value.\r
1891\r
1892 <b>Example usage</b>\r
1893 @code\r
1894 UINT64 Msr;\r
1895\r
1896 Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_ARB_PERFEVTSEL1);\r
1897 AsmWriteMsr64 (MSR_SKYLAKE_UNC_ARB_PERFEVTSEL1, Msr);\r
1898 @endcode\r
1899 @note MSR_SKYLAKE_UNC_ARB_PERFEVTSEL1 is defined as MSR_SKYLAKE_UNC_ARB_PERFEVTSEL1 in SDM.\r
1900**/\r
1901#define MSR_SKYLAKE_UNC_ARB_PERFEVTSEL1 0x000003B3\r
1902\r
1903\r
1904/**\r
1905 Package. Uncore C-Box 0, counter 0 event select MSR.\r
1906\r
1907 @param ECX MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL0 (0x00000700)\r
1908 @param EAX Lower 32-bits of MSR value.\r
1909 @param EDX Upper 32-bits of MSR value.\r
1910\r
1911 <b>Example usage</b>\r
1912 @code\r
1913 UINT64 Msr;\r
1914\r
1915 Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL0);\r
1916 AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL0, Msr);\r
1917 @endcode\r
1918 @note MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL0 is defined as MSR_UNC_CBO_0_PERFEVTSEL0 in SDM.\r
1919**/\r
1920#define MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL0 0x00000700\r
1921\r
1922\r
1923/**\r
1924 Package. Uncore C-Box 0, counter 1 event select MSR.\r
1925\r
1926 @param ECX MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL1 (0x00000701)\r
1927 @param EAX Lower 32-bits of MSR value.\r
1928 @param EDX Upper 32-bits of MSR value.\r
1929\r
1930 <b>Example usage</b>\r
1931 @code\r
1932 UINT64 Msr;\r
1933\r
1934 Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL1);\r
1935 AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL1, Msr);\r
1936 @endcode\r
1937 @note MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL1 is defined as MSR_UNC_CBO_0_PERFEVTSEL1 in SDM.\r
1938**/\r
1939#define MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL1 0x00000701\r
1940\r
1941\r
1942/**\r
1943 Package. Uncore C-Box 0, performance counter 0.\r
1944\r
1945 @param ECX MSR_SKYLAKE_UNC_CBO_0_PERFCTR0 (0x00000706)\r
1946 @param EAX Lower 32-bits of MSR value.\r
1947 @param EDX Upper 32-bits of MSR value.\r
1948\r
1949 <b>Example usage</b>\r
1950 @code\r
1951 UINT64 Msr;\r
1952\r
1953 Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_0_PERFCTR0);\r
1954 AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_0_PERFCTR0, Msr);\r
1955 @endcode\r
1956 @note MSR_SKYLAKE_UNC_CBO_0_PERFCTR0 is defined as MSR_UNC_CBO_0_PERFCTR0 in SDM.\r
1957**/\r
1958#define MSR_SKYLAKE_UNC_CBO_0_PERFCTR0 0x00000706\r
1959\r
1960\r
1961/**\r
1962 Package. Uncore C-Box 0, performance counter 1.\r
1963\r
1964 @param ECX MSR_SKYLAKE_UNC_CBO_0_PERFCTR1 (0x00000707)\r
1965 @param EAX Lower 32-bits of MSR value.\r
1966 @param EDX Upper 32-bits of MSR value.\r
1967\r
1968 <b>Example usage</b>\r
1969 @code\r
1970 UINT64 Msr;\r
1971\r
1972 Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_0_PERFCTR1);\r
1973 AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_0_PERFCTR1, Msr);\r
1974 @endcode\r
1975 @note MSR_SKYLAKE_UNC_CBO_0_PERFCTR1 is defined as MSR_UNC_CBO_0_PERFCTR1 in SDM.\r
1976**/\r
1977#define MSR_SKYLAKE_UNC_CBO_0_PERFCTR1 0x00000707\r
1978\r
1979\r
1980/**\r
1981 Package. Uncore C-Box 1, counter 0 event select MSR.\r
1982\r
1983 @param ECX MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL0 (0x00000710)\r
1984 @param EAX Lower 32-bits of MSR value.\r
1985 @param EDX Upper 32-bits of MSR value.\r
1986\r
1987 <b>Example usage</b>\r
1988 @code\r
1989 UINT64 Msr;\r
1990\r
1991 Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL0);\r
1992 AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL0, Msr);\r
1993 @endcode\r
1994 @note MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL0 is defined as MSR_UNC_CBO_1_PERFEVTSEL0 in SDM.\r
1995**/\r
1996#define MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL0 0x00000710\r
1997\r
1998\r
1999/**\r
2000 Package. Uncore C-Box 1, counter 1 event select MSR.\r
2001\r
2002 @param ECX MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL1 (0x00000711)\r
2003 @param EAX Lower 32-bits of MSR value.\r
2004 @param EDX Upper 32-bits of MSR value.\r
2005\r
2006 <b>Example usage</b>\r
2007 @code\r
2008 UINT64 Msr;\r
2009\r
2010 Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL1);\r
2011 AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL1, Msr);\r
2012 @endcode\r
2013 @note MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL1 is defined as MSR_UNC_CBO_1_PERFEVTSEL1 in SDM.\r
2014**/\r
2015#define MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL1 0x00000711\r
2016\r
2017\r
2018/**\r
2019 Package. Uncore C-Box 1, performance counter 0.\r
2020\r
2021 @param ECX MSR_SKYLAKE_UNC_CBO_1_PERFCTR0 (0x00000716)\r
2022 @param EAX Lower 32-bits of MSR value.\r
2023 @param EDX Upper 32-bits of MSR value.\r
2024\r
2025 <b>Example usage</b>\r
2026 @code\r
2027 UINT64 Msr;\r
2028\r
2029 Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_1_PERFCTR0);\r
2030 AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_1_PERFCTR0, Msr);\r
2031 @endcode\r
2032 @note MSR_SKYLAKE_UNC_CBO_1_PERFCTR0 is defined as MSR_UNC_CBO_1_PERFCTR0 in SDM.\r
2033**/\r
2034#define MSR_SKYLAKE_UNC_CBO_1_PERFCTR0 0x00000716\r
2035\r
2036\r
2037/**\r
2038 Package. Uncore C-Box 1, performance counter 1.\r
2039\r
2040 @param ECX MSR_SKYLAKE_UNC_CBO_1_PERFCTR1 (0x00000717)\r
2041 @param EAX Lower 32-bits of MSR value.\r
2042 @param EDX Upper 32-bits of MSR value.\r
2043\r
2044 <b>Example usage</b>\r
2045 @code\r
2046 UINT64 Msr;\r
2047\r
2048 Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_1_PERFCTR1);\r
2049 AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_1_PERFCTR1, Msr);\r
2050 @endcode\r
2051 @note MSR_SKYLAKE_UNC_CBO_1_PERFCTR1 is defined as MSR_UNC_CBO_1_PERFCTR1 in SDM.\r
2052**/\r
2053#define MSR_SKYLAKE_UNC_CBO_1_PERFCTR1 0x00000717\r
2054\r
2055\r
2056/**\r
2057 Package. Uncore C-Box 2, counter 0 event select MSR.\r
2058\r
2059 @param ECX MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL0 (0x00000720)\r
2060 @param EAX Lower 32-bits of MSR value.\r
2061 @param EDX Upper 32-bits of MSR value.\r
2062\r
2063 <b>Example usage</b>\r
2064 @code\r
2065 UINT64 Msr;\r
2066\r
2067 Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL0);\r
2068 AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL0, Msr);\r
2069 @endcode\r
2070 @note MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL0 is defined as MSR_UNC_CBO_2_PERFEVTSEL0 in SDM.\r
2071**/\r
2072#define MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL0 0x00000720\r
2073\r
2074\r
2075/**\r
2076 Package. Uncore C-Box 2, counter 1 event select MSR.\r
2077\r
2078 @param ECX MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL1 (0x00000721)\r
2079 @param EAX Lower 32-bits of MSR value.\r
2080 @param EDX Upper 32-bits of MSR value.\r
2081\r
2082 <b>Example usage</b>\r
2083 @code\r
2084 UINT64 Msr;\r
2085\r
2086 Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL1);\r
2087 AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL1, Msr);\r
2088 @endcode\r
2089 @note MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL1 is defined as MSR_UNC_CBO_2_PERFEVTSEL1 in SDM.\r
2090**/\r
2091#define MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL1 0x00000721\r
2092\r
2093\r
2094/**\r
2095 Package. Uncore C-Box 2, performance counter 0.\r
2096\r
2097 @param ECX MSR_SKYLAKE_UNC_CBO_2_PERFCTR0 (0x00000726)\r
2098 @param EAX Lower 32-bits of MSR value.\r
2099 @param EDX Upper 32-bits of MSR value.\r
2100\r
2101 <b>Example usage</b>\r
2102 @code\r
2103 UINT64 Msr;\r
2104\r
2105 Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_2_PERFCTR0);\r
2106 AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_2_PERFCTR0, Msr);\r
2107 @endcode\r
2108 @note MSR_SKYLAKE_UNC_CBO_2_PERFCTR0 is defined as MSR_UNC_CBO_2_PERFCTR0 in SDM.\r
2109**/\r
2110#define MSR_SKYLAKE_UNC_CBO_2_PERFCTR0 0x00000726\r
2111\r
2112\r
2113/**\r
2114 Package. Uncore C-Box 2, performance counter 1.\r
2115\r
2116 @param ECX MSR_SKYLAKE_UNC_CBO_2_PERFCTR1 (0x00000727)\r
2117 @param EAX Lower 32-bits of MSR value.\r
2118 @param EDX Upper 32-bits of MSR value.\r
2119\r
2120 <b>Example usage</b>\r
2121 @code\r
2122 UINT64 Msr;\r
2123\r
2124 Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_2_PERFCTR1);\r
2125 AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_2_PERFCTR1, Msr);\r
2126 @endcode\r
2127 @note MSR_SKYLAKE_UNC_CBO_2_PERFCTR1 is defined as MSR_UNC_CBO_2_PERFCTR1 in SDM.\r
2128**/\r
2129#define MSR_SKYLAKE_UNC_CBO_2_PERFCTR1 0x00000727\r
2130\r
2131\r
2132/**\r
2133 Package. Uncore C-Box 3, counter 0 event select MSR.\r
2134\r
2135 @param ECX MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL0 (0x00000730)\r
2136 @param EAX Lower 32-bits of MSR value.\r
2137 @param EDX Upper 32-bits of MSR value.\r
2138\r
2139 <b>Example usage</b>\r
2140 @code\r
2141 UINT64 Msr;\r
2142\r
2143 Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL0);\r
2144 AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL0, Msr);\r
2145 @endcode\r
2146 @note MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL0 is defined as MSR_UNC_CBO_3_PERFEVTSEL0 in SDM.\r
2147**/\r
2148#define MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL0 0x00000730\r
2149\r
2150\r
2151/**\r
2152 Package. Uncore C-Box 3, counter 1 event select MSR.\r
2153\r
2154 @param ECX MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL1 (0x00000731)\r
2155 @param EAX Lower 32-bits of MSR value.\r
2156 @param EDX Upper 32-bits of MSR value.\r
2157\r
2158 <b>Example usage</b>\r
2159 @code\r
2160 UINT64 Msr;\r
2161\r
2162 Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL1);\r
2163 AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL1, Msr);\r
2164 @endcode\r
2165 @note MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL1 is defined as MSR_UNC_CBO_3_PERFEVTSEL1 in SDM.\r
2166**/\r
2167#define MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL1 0x00000731\r
2168\r
2169\r
2170/**\r
2171 Package. Uncore C-Box 3, performance counter 0.\r
2172\r
2173 @param ECX MSR_SKYLAKE_UNC_CBO_3_PERFCTR0 (0x00000736)\r
2174 @param EAX Lower 32-bits of MSR value.\r
2175 @param EDX Upper 32-bits of MSR value.\r
2176\r
2177 <b>Example usage</b>\r
2178 @code\r
2179 UINT64 Msr;\r
2180\r
2181 Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_3_PERFCTR0);\r
2182 AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_3_PERFCTR0, Msr);\r
2183 @endcode\r
2184 @note MSR_SKYLAKE_UNC_CBO_3_PERFCTR0 is defined as MSR_UNC_CBO_3_PERFCTR0 in SDM.\r
2185**/\r
2186#define MSR_SKYLAKE_UNC_CBO_3_PERFCTR0 0x00000736\r
2187\r
2188\r
2189/**\r
2190 Package. Uncore C-Box 3, performance counter 1.\r
2191\r
2192 @param ECX MSR_SKYLAKE_UNC_CBO_3_PERFCTR1 (0x00000737)\r
2193 @param EAX Lower 32-bits of MSR value.\r
2194 @param EDX Upper 32-bits of MSR value.\r
2195\r
2196 <b>Example usage</b>\r
2197 @code\r
2198 UINT64 Msr;\r
2199\r
2200 Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_3_PERFCTR1);\r
2201 AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_3_PERFCTR1, Msr);\r
2202 @endcode\r
2203 @note MSR_SKYLAKE_UNC_CBO_3_PERFCTR1 is defined as MSR_UNC_CBO_3_PERFCTR1 in SDM.\r
2204**/\r
2205#define MSR_SKYLAKE_UNC_CBO_3_PERFCTR1 0x00000737\r
2206\r
2207\r
2208/**\r
2209 Package. Uncore PMU global control.\r
2210\r
2211 @param ECX MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL (0x00000E01)\r
2212 @param EAX Lower 32-bits of MSR value.\r
2213 Described by the type MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL_REGISTER.\r
2214 @param EDX Upper 32-bits of MSR value.\r
2215 Described by the type MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL_REGISTER.\r
2216\r
2217 <b>Example usage</b>\r
2218 @code\r
2219 MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL_REGISTER Msr;\r
2220\r
2221 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL);\r
2222 AsmWriteMsr64 (MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL, Msr.Uint64);\r
2223 @endcode\r
2224 @note MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL is defined as MSR_UNC_PERF_GLOBAL_CTRL in SDM.\r
2225**/\r
2226#define MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL 0x00000E01\r
2227\r
2228/**\r
2229 MSR information returned for MSR index #MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL\r
2230**/\r
2231typedef union {\r
2232 ///\r
2233 /// Individual bit fields\r
2234 ///\r
2235 struct {\r
2236 ///\r
2237 /// [Bit 0] Slice 0 select.\r
2238 ///\r
2239 UINT32 PMI_Sel_Slice0:1;\r
2240 ///\r
2241 /// [Bit 1] Slice 1 select.\r
2242 ///\r
2243 UINT32 PMI_Sel_Slice1:1;\r
2244 ///\r
2245 /// [Bit 2] Slice 2 select.\r
2246 ///\r
2247 UINT32 PMI_Sel_Slice2:1;\r
2248 ///\r
2249 /// [Bit 3] Slice 3 select.\r
2250 ///\r
2251 UINT32 PMI_Sel_Slice3:1;\r
2252 ///\r
2253 /// [Bit 4] Slice 4select.\r
2254 ///\r
2255 UINT32 PMI_Sel_Slice4:1;\r
2256 UINT32 Reserved1:14;\r
2257 UINT32 Reserved2:10;\r
2258 ///\r
2259 /// [Bit 29] Enable all uncore counters.\r
2260 ///\r
2261 UINT32 EN:1;\r
2262 ///\r
2263 /// [Bit 30] Enable wake on PMI.\r
2264 ///\r
2265 UINT32 WakePMI:1;\r
2266 ///\r
2267 /// [Bit 31] Enable Freezing counter when overflow.\r
2268 ///\r
2269 UINT32 FREEZE:1;\r
2270 UINT32 Reserved3:32;\r
2271 } Bits;\r
2272 ///\r
2273 /// All bit fields as a 32-bit value\r
2274 ///\r
2275 UINT32 Uint32;\r
2276 ///\r
2277 /// All bit fields as a 64-bit value\r
2278 ///\r
2279 UINT64 Uint64;\r
2280} MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL_REGISTER;\r
2281\r
2282\r
2283/**\r
2284 Package. Uncore PMU main status.\r
2285\r
2286 @param ECX MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS (0x00000E02)\r
2287 @param EAX Lower 32-bits of MSR value.\r
2288 Described by the type MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS_REGISTER.\r
2289 @param EDX Upper 32-bits of MSR value.\r
2290 Described by the type MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS_REGISTER.\r
2291\r
2292 <b>Example usage</b>\r
2293 @code\r
2294 MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS_REGISTER Msr;\r
2295\r
2296 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS);\r
2297 AsmWriteMsr64 (MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS, Msr.Uint64);\r
2298 @endcode\r
2299 @note MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS is defined as MSR_UNC_PERF_GLOBAL_STATUS in SDM.\r
2300**/\r
2301#define MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS 0x00000E02\r
2302\r
2303/**\r
2304 MSR information returned for MSR index #MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS\r
2305**/\r
2306typedef union {\r
2307 ///\r
2308 /// Individual bit fields\r
2309 ///\r
2310 struct {\r
2311 ///\r
2312 /// [Bit 0] Fixed counter overflowed.\r
2313 ///\r
2314 UINT32 Fixed:1;\r
2315 ///\r
2316 /// [Bit 1] An ARB counter overflowed.\r
2317 ///\r
2318 UINT32 ARB:1;\r
2319 UINT32 Reserved1:1;\r
2320 ///\r
2321 /// [Bit 3] A CBox counter overflowed (on any slice).\r
2322 ///\r
2323 UINT32 CBox:1;\r
2324 UINT32 Reserved2:28;\r
2325 UINT32 Reserved3:32;\r
2326 } Bits;\r
2327 ///\r
2328 /// All bit fields as a 32-bit value\r
2329 ///\r
2330 UINT32 Uint32;\r
2331 ///\r
2332 /// All bit fields as a 64-bit value\r
2333 ///\r
2334 UINT64 Uint64;\r
2335} MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS_REGISTER;\r
2336\r
3add0205
ED		 2337\r
2338/**\r
2339 Package. NPK Address Used by AET Messages (R/W).\r
2340\r
2341 @param ECX MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE (0x00000080)\r
2342 @param EAX Lower 32-bits of MSR value.\r
2343 Described by the type MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE_REGISTER.\r
2344 @param EDX Upper 32-bits of MSR value.\r
2345 Described by the type MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE_REGISTER.\r
2346\r
2347 <b>Example usage</b>\r
2348 @code\r
2349 MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE_REGISTER Msr;\r
2350\r
2351 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE);\r
2352 AsmWriteMsr64 (MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE, Msr.Uint64);\r
2353 @endcode\r
2354**/\r
2355#define MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE 0x00000080\r
2356\r
2357/**\r
2358 MSR information returned for MSR index\r
2359 #MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE\r
2360**/\r
2361typedef union {\r
2362 ///\r
2363 /// Individual bit fields\r
2364 ///\r
2365 struct {\r
2366 ///\r
2367 /// [Bit 0] Lock Bit If set, this MSR cannot be re-written anymore. Lock\r
2368 /// bit has to be set in order for the AET packets to be directed to NPK\r
2369 /// MMIO.\r
2370 ///\r
2371 UINT32 Fix_Me_1:1;\r
2372 UINT32 Reserved:17;\r
2373 ///\r
2374 /// [Bits 31:18] ACPIBAR_BASE_ADDRESS AET target address in NPK MMIO space.\r
2375 ///\r
2376 UINT32 ACPIBAR_BASE_ADDRESS:14;\r
2377 ///\r
2378 /// [Bits 63:32] ACPIBAR_BASE_ADDRESS AET target address in NPK MMIO space.\r
2379 ///\r
2380 UINT32 Fix_Me_2:32;\r
2381 } Bits;\r
2382 ///\r
2383 /// All bit fields as a 64-bit value\r
2384 ///\r
2385 UINT64 Uint64;\r
2386} MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE_REGISTER;\r
2387\r
2388\r
2389/**\r
2390 Core. Processor Reserved Memory Range Register - Physical Base Control\r
2391 Register (R/W).\r
2392\r
2393 @param ECX MSR_SKYLAKE_PRMRR_PHYS_BASE (0x000001F4)\r
2394 @param EAX Lower 32-bits of MSR value.\r
2395 Described by the type MSR_SKYLAKE_PRMRR_PHYS_BASE_REGISTER.\r
2396 @param EDX Upper 32-bits of MSR value.\r
2397 Described by the type MSR_SKYLAKE_PRMRR_PHYS_BASE_REGISTER.\r
2398\r
2399 <b>Example usage</b>\r
2400 @code\r
2401 MSR_SKYLAKE_PRMRR_PHYS_BASE_REGISTER Msr;\r
2402\r
2403 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_PRMRR_PHYS_BASE);\r
2404 AsmWriteMsr64 (MSR_SKYLAKE_PRMRR_PHYS_BASE, Msr.Uint64);\r
2405 @endcode\r
2406**/\r
2407#define MSR_SKYLAKE_PRMRR_PHYS_BASE 0x000001F4\r
2408\r
2409/**\r
2410 MSR information returned for MSR index #MSR_SKYLAKE_PRMRR_PHYS_BASE\r
2411**/\r
2412typedef union {\r
2413 ///\r
2414 /// Individual bit fields\r
2415 ///\r
2416 struct {\r
2417 ///\r
2418 /// [Bits 2:0] MemType PRMRR BASE MemType.\r
2419 ///\r
2420 UINT32 MemTypePRMRRBASEMemType:3;\r
2421 UINT32 Reserved1:9;\r
2422 ///\r
2423 /// [Bits 31:12] Base PRMRR Base Address.\r
2424 ///\r
2425 UINT32 BasePRMRRBaseAddress:20;\r
2426 ///\r
2427 /// [Bits 45:32] Base PRMRR Base Address.\r
2428 ///\r
2429 UINT32 Fix_Me_1:14;\r
2430 UINT32 Reserved2:18;\r
2431 } Bits;\r
2432 ///\r
2433 /// All bit fields as a 64-bit value\r
2434 ///\r
2435 UINT64 Uint64;\r
2436} MSR_SKYLAKE_PRMRR_PHYS_BASE_REGISTER;\r
2437\r
2438\r
2439/**\r
2440 Core. Processor Reserved Memory Range Register - Physical Mask Control\r
2441 Register (R/W).\r
2442\r
2443 @param ECX MSR_SKYLAKE_PRMRR_PHYS_MASK (0x000001F5)\r
2444 @param EAX Lower 32-bits of MSR value.\r
2445 Described by the type MSR_SKYLAKE_PRMRR_PHYS_MASK_REGISTER.\r
2446 @param EDX Upper 32-bits of MSR value.\r
2447 Described by the type MSR_SKYLAKE_PRMRR_PHYS_MASK_REGISTER.\r
2448\r
2449 <b>Example usage</b>\r
2450 @code\r
2451 MSR_SKYLAKE_PRMRR_PHYS_MASK_REGISTER Msr;\r
2452\r
2453 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_PRMRR_PHYS_MASK);\r
2454 AsmWriteMsr64 (MSR_SKYLAKE_PRMRR_PHYS_MASK, Msr.Uint64);\r
2455 @endcode\r
2456**/\r
2457#define MSR_SKYLAKE_PRMRR_PHYS_MASK 0x000001F5\r
2458\r
2459/**\r
2460 MSR information returned for MSR index #MSR_SKYLAKE_PRMRR_PHYS_MASK\r
2461**/\r
2462typedef union {\r
2463 ///\r
2464 /// Individual bit fields\r
2465 ///\r
2466 struct {\r
2467 UINT32 Reserved1:10;\r
2468 ///\r
2469 /// [Bit 10] Lock Lock bit for the PRMRR.\r
2470 ///\r
2471 UINT32 Fix_Me_1:1;\r
2472 ///\r
2473 /// [Bit 11] VLD Enable bit for the PRMRR.\r
2474 ///\r
2475 UINT32 VLD:1;\r
2476 ///\r
2477 /// [Bits 31:12] Mask PRMRR MASK bits.\r
2478 ///\r
2479 UINT32 Fix_Me_2:20;\r
2480 ///\r
2481 /// [Bits 45:32] Mask PRMRR MASK bits.\r
2482 ///\r
2483 UINT32 Fix_Me_3:14;\r
2484 UINT32 Reserved2:18;\r
2485 } Bits;\r
2486 ///\r
2487 /// All bit fields as a 64-bit value\r
2488 ///\r
2489 UINT64 Uint64;\r
2490} MSR_SKYLAKE_PRMRR_PHYS_MASK_REGISTER;\r
2491\r
2492\r
2493/**\r
2494 Core. Valid PRMRR Configurations (R/W).\r
2495\r
2496 @param ECX MSR_SKYLAKE_PRMRR_VALID_CONFIG (0x000001FB)\r
2497 @param EAX Lower 32-bits of MSR value.\r
2498 Described by the type MSR_SKYLAKE_PRMRR_VALID_CONFIG_REGISTER.\r
2499 @param EDX Upper 32-bits of MSR value.\r
2500 Described by the type MSR_SKYLAKE_PRMRR_VALID_CONFIG_REGISTER.\r
2501\r
2502 <b>Example usage</b>\r
2503 @code\r
2504 MSR_SKYLAKE_PRMRR_VALID_CONFIG_REGISTER Msr;\r
2505\r
2506 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_PRMRR_VALID_CONFIG);\r
2507 AsmWriteMsr64 (MSR_SKYLAKE_PRMRR_VALID_CONFIG, Msr.Uint64);\r
2508 @endcode\r
2509**/\r
2510#define MSR_SKYLAKE_PRMRR_VALID_CONFIG 0x000001FB\r
2511\r
2512/**\r
2513 MSR information returned for MSR index #MSR_SKYLAKE_PRMRR_VALID_CONFIG\r
2514**/\r
2515typedef union {\r
2516 ///\r
2517 /// Individual bit fields\r
2518 ///\r
2519 struct {\r
2520 ///\r
2521 /// [Bit 0] 1M supported MEE size.\r
2522 ///\r
2523 UINT32 Fix_Me_1:1;\r
2524 UINT32 Reserved1:4;\r
2525 ///\r
2526 /// [Bit 5] 32M supported MEE size.\r
2527 ///\r
2528 UINT32 Fix_Me_2:1;\r
2529 ///\r
2530 /// [Bit 6] 64M supported MEE size.\r
2531 ///\r
2532 UINT32 Fix_Me_3:1;\r
2533 ///\r
2534 /// [Bit 7] 128M supported MEE size.\r
2535 ///\r
2536 UINT32 Fix_Me_4:1;\r
2537 UINT32 Reserved2:24;\r
2538 UINT32 Reserved3:32;\r
2539 } Bits;\r
2540 ///\r
2541 /// All bit fields as a 32-bit value\r
2542 ///\r
2543 UINT32 Uint32;\r
2544 ///\r
2545 /// All bit fields as a 64-bit value\r
2546 ///\r
2547 UINT64 Uint64;\r
2548} MSR_SKYLAKE_PRMRR_VALID_CONFIG_REGISTER;\r
2549\r
2550\r
2551/**\r
2552 Package. (R/W) The PRMRR range is used to protect Xucode memory from\r
2553 unauthorized reads and writes. Any IO access to this range is aborted. This\r
2554 register controls the location of the PRMRR range by indicating its starting\r
2555 address. It functions in tandem with the PRMRR mask register.\r
2556\r
2557 @param ECX MSR_SKYLAKE_UNCORE_PRMRR_PHYS_BASE (0x000002F4)\r
2558 @param EAX Lower 32-bits of MSR value.\r
2559 Described by the type MSR_SKYLAKE_UNCORE_PRMRR_PHYS_BASE_REGISTER.\r
2560 @param EDX Upper 32-bits of MSR value.\r
2561 Described by the type MSR_SKYLAKE_UNCORE_PRMRR_PHYS_BASE_REGISTER.\r
2562\r
2563 <b>Example usage</b>\r
2564 @code\r
2565 MSR_SKYLAKE_UNCORE_PRMRR_PHYS_BASE_REGISTER Msr;\r
2566\r
2567 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_UNCORE_PRMRR_PHYS_BASE);\r
2568 AsmWriteMsr64 (MSR_SKYLAKE_UNCORE_PRMRR_PHYS_BASE, Msr.Uint64);\r
2569 @endcode\r
2570**/\r
2571#define MSR_SKYLAKE_UNCORE_PRMRR_PHYS_BASE 0x000002F4\r
2572\r
2573/**\r
2574 MSR information returned for MSR index #MSR_SKYLAKE_UNCORE_PRMRR_PHYS_BASE\r
2575**/\r
2576typedef union {\r
2577 ///\r
2578 /// Individual bit fields\r
2579 ///\r
2580 struct {\r
2581 UINT32 Reserved1:12;\r
2582 ///\r
2583 /// [Bits 31:12] Range Base This field corresponds to bits 38:12 of the\r
2584 /// base address memory range which is allocated to PRMRR memory.\r
2585 ///\r
2586 UINT32 Fix_Me_1:20;\r
2587 ///\r
2588 /// [Bits 38:32] Range Base This field corresponds to bits 38:12 of the\r
2589 /// base address memory range which is allocated to PRMRR memory.\r
2590 ///\r
2591 UINT32 Fix_Me_2:7;\r
2592 UINT32 Reserved2:25;\r
2593 } Bits;\r
2594 ///\r
2595 /// All bit fields as a 64-bit value\r
2596 ///\r
2597 UINT64 Uint64;\r
2598} MSR_SKYLAKE_UNCORE_PRMRR_PHYS_BASE_REGISTER;\r
2599\r
2600\r
2601/**\r
2602 Package. (R/W) This register controls the size of the PRMRR range by\r
2603 indicating which address bits must match the PRMRR base register value.\r
2604\r
2605 @param ECX MSR_SKYLAKE_UNCORE_PRMRR_PHYS_MASK (0x000002F5)\r
2606 @param EAX Lower 32-bits of MSR value.\r
2607 Described by the type MSR_SKYLAKE_UNCORE_PRMRR_PHYS_MASK_REGISTER.\r
2608 @param EDX Upper 32-bits of MSR value.\r
2609 Described by the type MSR_SKYLAKE_UNCORE_PRMRR_PHYS_MASK_REGISTER.\r
2610\r
2611 <b>Example usage</b>\r
2612 @code\r
2613 MSR_SKYLAKE_UNCORE_PRMRR_PHYS_MASK_REGISTER Msr;\r
2614\r
2615 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_UNCORE_PRMRR_PHYS_MASK);\r
2616 AsmWriteMsr64 (MSR_SKYLAKE_UNCORE_PRMRR_PHYS_MASK, Msr.Uint64);\r
2617 @endcode\r
2618**/\r
2619#define MSR_SKYLAKE_UNCORE_PRMRR_PHYS_MASK 0x000002F5\r
2620\r
2621/**\r
2622 MSR information returned for MSR index #MSR_SKYLAKE_UNCORE_PRMRR_PHYS_MASK\r
2623**/\r
2624typedef union {\r
2625 ///\r
2626 /// Individual bit fields\r
2627 ///\r
2628 struct {\r
2629 UINT32 Reserved1:10;\r
2630 ///\r
2631 /// [Bit 10] Lock Setting this bit locks all writeable settings in this\r
2632 /// register, including itself.\r
2633 ///\r
2634 UINT32 Fix_Me_1:1;\r
2635 ///\r
2636 /// [Bit 11] Range_En Indicates whether the PRMRR range is enabled and\r
2637 /// valid.\r
2638 ///\r
2639 UINT32 Fix_Me_2:1;\r
2640 UINT32 Reserved2:20;\r
2641 UINT32 Reserved3:32;\r
2642 } Bits;\r
2643 ///\r
2644 /// All bit fields as a 32-bit value\r
2645 ///\r
2646 UINT32 Uint32;\r
2647 ///\r
2648 /// All bit fields as a 64-bit value\r
2649 ///\r
2650 UINT64 Uint64;\r
2651} MSR_SKYLAKE_UNCORE_PRMRR_PHYS_MASK_REGISTER;\r
2652\r
2653/**\r
2654 Package. Ring Ratio Limit (R/W) This register provides Min/Max Ratio Limits\r
2655 for the LLC and Ring.\r
2656\r
2657 @param ECX MSR_SKYLAKE_RING_RATIO_LIMIT (0x00000620)\r
2658 @param EAX Lower 32-bits of MSR value.\r
2659 Described by the type MSR_SKYLAKE_RING_RATIO_LIMIT_REGISTER.\r
2660 @param EDX Upper 32-bits of MSR value.\r
2661 Described by the type MSR_SKYLAKE_RING_RATIO_LIMIT_REGISTER.\r
2662\r
2663 <b>Example usage</b>\r
2664 @code\r
2665 MSR_SKYLAKE_RING_RATIO_LIMIT_REGISTER Msr;\r
2666\r
2667 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_RING_RATIO_LIMIT);\r
2668 AsmWriteMsr64 (MSR_SKYLAKE_RING_RATIO_LIMIT, Msr.Uint64);\r
2669 @endcode\r
2670**/\r
2671#define MSR_SKYLAKE_RING_RATIO_LIMIT 0x00000620\r
2672\r
2673/**\r
2674 MSR information returned for MSR index #MSR_SKYLAKE_RING_RATIO_LIMIT\r
2675**/\r
2676typedef union {\r
2677 ///\r
2678 /// Individual bit fields\r
2679 ///\r
2680 struct {\r
2681 ///\r
2682 /// [Bits 6:0] MAX_Ratio This field is used to limit the max ratio of the\r
2683 /// LLC/Ring.\r
2684 ///\r
2685 UINT32 Fix_Me_1:7;\r
2686 UINT32 Reserved1:1;\r
2687 ///\r
2688 /// [Bits 14:8] MIN_Ratio Writing to this field controls the minimum\r
2689 /// possible ratio of the LLC/Ring.\r
2690 ///\r
2691 UINT32 Fix_Me_2:7;\r
2692 UINT32 Reserved2:17;\r
2693 UINT32 Reserved3:32;\r
2694 } Bits;\r
2695 ///\r
2696 /// All bit fields as a 32-bit value\r
2697 ///\r
2698 UINT32 Uint32;\r
2699 ///\r
2700 /// All bit fields as a 64-bit value\r
2701 ///\r
2702 UINT64 Uint64;\r
2703} MSR_SKYLAKE_RING_RATIO_LIMIT_REGISTER;\r
2704\r
2705\r
2706/**\r
2707 Branch Monitoring Global Control (R/W).\r
2708\r
2709 @param ECX MSR_SKYLAKE_BR_DETECT_CTRL (0x00000350)\r
2710 @param EAX Lower 32-bits of MSR value.\r
2711 Described by the type MSR_SKYLAKE_BR_DETECT_CTRL_REGISTER.\r
2712 @param EDX Upper 32-bits of MSR value.\r
2713 Described by the type MSR_SKYLAKE_BR_DETECT_CTRL_REGISTER.\r
2714\r
2715 <b>Example usage</b>\r
2716 @code\r
2717 MSR_SKYLAKE_BR_DETECT_CTRL_REGISTER Msr;\r
2718\r
2719 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_BR_DETECT_CTRL);\r
2720 AsmWriteMsr64 (MSR_SKYLAKE_BR_DETECT_CTRL, Msr.Uint64);\r
2721 @endcode\r
2722**/\r
2723#define MSR_SKYLAKE_BR_DETECT_CTRL 0x00000350\r
2724\r
2725/**\r
2726 MSR information returned for MSR index #MSR_SKYLAKE_BR_DETECT_CTRL\r
2727**/\r
2728typedef union {\r
2729 ///\r
2730 /// Individual bit fields\r
2731 ///\r
2732 struct {\r
2733 ///\r
2734 /// [Bit 0] EnMonitoring Global enable for branch monitoring.\r
2735 ///\r
2736 UINT32 EnMonitoring:1;\r
2737 ///\r
2738 /// [Bit 1] EnExcept Enable branch monitoring event signaling on threshold\r
2739 /// trip. The branch monitoring event handler is signaled via the existing\r
2740 /// PMI signaling mechanism as programmed from the corresponding local\r
2741 /// APIC LVT entry.\r
2742 ///\r
2743 UINT32 EnExcept:1;\r
2744 ///\r
2745 /// [Bit 2] EnLBRFrz Enable LBR freeze on threshold trip. This will cause\r
2746 /// the LBR frozen bit 58 to be set in IA32_PERF_GLOBAL_STATUS when a\r
2747 /// triggering condition occurs and this bit is enabled.\r
2748 ///\r
2749 UINT32 EnLBRFrz:1;\r
2750 ///\r
2751 /// [Bit 3] DisableInGuest When set to '1', branch monitoring, event\r
2752 /// triggering and LBR freeze actions are disabled when operating at VMX\r
2753 /// non-root operation.\r
2754 ///\r
2755 UINT32 DisableInGuest:1;\r
2756 UINT32 Reserved1:4;\r
2757 ///\r
2758 /// [Bits 17:8] WindowSize Window size defined by WindowCntSel. Values 0 -\r
2759 /// 1023 are supported. Once the Window counter reaches the WindowSize\r
2760 /// count both the Window Counter and all Branch Monitoring Counters are\r
2761 /// cleared.\r
2762 ///\r
2763 UINT32 WindowSize:10;\r
2764 UINT32 Reserved2:6;\r
2765 ///\r
2766 /// [Bits 25:24] WindowCntSel Window event count select: '00 =\r
2767 /// Instructions retired. '01 = Branch instructions retired '10 = Return\r
2768 /// instructions retired. '11 = Indirect branch instructions retired.\r
2769 ///\r
2770 UINT32 WindowCntSel:2;\r
2771 ///\r
2772 /// [Bit 26] CntAndMode When set to '1', the overall branch monitoring\r
2773 /// event triggering condition is true only if all enabled counters'\r
2774 /// threshold conditions are true. When '0', the threshold tripping\r
2775 /// condition is true if any enabled counters' threshold is true.\r
2776 ///\r
2777 UINT32 CntAndMode:1;\r
2778 UINT32 Reserved3:5;\r
2779 UINT32 Reserved4:32;\r
2780 } Bits;\r
2781 ///\r
2782 /// All bit fields as a 32-bit value\r
2783 ///\r
2784 UINT32 Uint32;\r
2785 ///\r
2786 /// All bit fields as a 64-bit value\r
2787 ///\r
2788 UINT64 Uint64;\r
2789} MSR_SKYLAKE_BR_DETECT_CTRL_REGISTER;\r
2790\r
2791/**\r
2792 Branch Monitoring Global Status (R/W).\r
2793\r
2794 @param ECX MSR_SKYLAKE_BR_DETECT_STATUS (0x00000351)\r
2795 @param EAX Lower 32-bits of MSR value.\r
2796 Described by the type MSR_SKYLAKE_BR_DETECT_STATUS_REGISTER.\r
2797 @param EDX Upper 32-bits of MSR value.\r
2798 Described by the type MSR_SKYLAKE_BR_DETECT_STATUS_REGISTER.\r
2799\r
2800 <b>Example usage</b>\r
2801 @code\r
2802 MSR_SKYLAKE_BR_DETECT_STATUS_REGISTER Msr;\r
2803\r
2804 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_BR_DETECT_STATUS);\r
2805 AsmWriteMsr64 (MSR_SKYLAKE_BR_DETECT_STATUS, Msr.Uint64);\r
2806 @endcode\r
2807**/\r
2808#define MSR_SKYLAKE_BR_DETECT_STATUS 0x00000351\r
2809\r
2810/**\r
2811 MSR information returned for MSR index #MSR_SKYLAKE_BR_DETECT_STATUS\r
2812**/\r
2813typedef union {\r
2814 ///\r
2815 /// Individual bit fields\r
2816 ///\r
2817 struct {\r
2818 ///\r
2819 /// [Bit 0] Branch Monitoring Event Signaled When set to '1', Branch\r
2820 /// Monitoring event signaling is blocked until this bit is cleared by\r
2821 /// software.\r
2822 ///\r
2823 UINT32 BranchMonitoringEventSignaled:1;\r
2824 ///\r
2825 /// [Bit 1] LBRsValid This status bit is set to '1' if the LBR state is\r
2826 /// considered valid for sampling by branch monitoring software.\r
2827 ///\r
2828 UINT32 LBRsValid:1;\r
2829 UINT32 Reserved1:6;\r
2830 ///\r
2831 /// [Bit 8] CntrHit0 Branch monitoring counter #0 threshold hit. This\r
2832 /// status bit is sticky and once set requires clearing by software.\r
2833 /// Counter operation continues independent of the state of the bit.\r
2834 ///\r
2835 UINT32 CntrHit0:1;\r
2836 ///\r
2837 /// [Bit 9] CntrHit1 Branch monitoring counter #1 threshold hit. This\r
2838 /// status bit is sticky and once set requires clearing by software.\r
2839 /// Counter operation continues independent of the state of the bit.\r
2840 ///\r
2841 UINT32 CntrHit1:1;\r
2842 UINT32 Reserved2:6;\r
2843 ///\r
2844 /// [Bits 25:16] CountWindow The current value of the window counter. The\r
2845 /// count value is frozen on a valid branch monitoring triggering\r
2846 /// condition. This is a 10-bit unsigned value.\r
2847 ///\r
2848 UINT32 CountWindow:10;\r
2849 UINT32 Reserved3:6;\r
2850 ///\r
2851 /// [Bits 39:32] Count0 The current value of counter 0 updated after each\r
2852 /// occurrence of the event being counted. The count value is frozen on a\r
2853 /// valid branch monitoring triggering condition (in which case CntrHit0\r
2854 /// will also be set). This is an 8-bit signed value (2's complement).\r
2855 /// Heuristic events which only increment will saturate and freeze at\r
2856 /// maximum value 0xFF (256). RET-CALL event counter saturate at maximum\r
2857 /// value 0x7F (+127) and minimum value 0x80 (-128).\r
2858 ///\r
2859 UINT32 Count0:8;\r
2860 ///\r
2861 /// [Bits 47:40] Count1 The current value of counter 1 updated after each\r
2862 /// occurrence of the event being counted. The count value is frozen on a\r
2863 /// valid branch monitoring triggering condition (in which case CntrHit1\r
2864 /// will also be set). This is an 8-bit signed value (2's complement).\r
2865 /// Heuristic events which only increment will saturate and freeze at\r
2866 /// maximum value 0xFF (256). RET-CALL event counter saturate at maximum\r
2867 /// value 0x7F (+127) and minimum value 0x80 (-128).\r
2868 ///\r
2869 UINT32 Count1:8;\r
2870 UINT32 Reserved4:16;\r
2871 } Bits;\r
2872 ///\r
2873 /// All bit fields as a 32-bit value\r
2874 ///\r
2875 UINT32 Uint32;\r
2876 ///\r
2877 /// All bit fields as a 64-bit value\r
2878 ///\r
2879 UINT64 Uint64;\r
2880} MSR_SKYLAKE_BR_DETECT_STATUS_REGISTER;\r
2881\r
2882\r
2883/**\r
2884 Package. Package C3 Residency Counter (R/O). Note: C-state values are\r
2885 processor specific C-state code names, unrelated to MWAIT extension C-state\r
2886 parameters or ACPI C-states.\r
2887\r
2888 @param ECX MSR_SKYLAKE_PKG_C3_RESIDENCY (0x000003F8)\r
2889 @param EAX Lower 32-bits of MSR value.\r
2890 @param EDX Upper 32-bits of MSR value.\r
2891\r
2892 <b>Example usage</b>\r
2893 @code\r
2894 UINT64 Msr;\r
2895\r
2896 Msr = AsmReadMsr64 (MSR_SKYLAKE_PKG_C3_RESIDENCY);\r
2897 @endcode\r
2898**/\r
2899#define MSR_SKYLAKE_PKG_C3_RESIDENCY 0x000003F8\r
2900\r
2901\r
2902/**\r
2903 Core. Core C1 Residency Counter (R/O). Value since last reset for the Core\r
2904 C1 residency. Counter rate is the Max Non-Turbo frequency (same as TSC).\r
2905 This counter counts in case both of the core's threads are in an idle state\r
2906 and at least one of the core's thread residency is in a C1 state or in one\r
2907 of its sub states. The counter is updated only after a core C state exit.\r
2908 Note: Always reads 0 if core C1 is unsupported. A value of zero indicates\r
2909 that this processor does not support core C1 or never entered core C1 level\r
2910 state.\r
2911\r
2912 @param ECX MSR_SKYLAKE_CORE_C1_RESIDENCY (0x00000660)\r
2913 @param EAX Lower 32-bits of MSR value.\r
2914 @param EDX Upper 32-bits of MSR value.\r
2915\r
2916 <b>Example usage</b>\r
2917 @code\r
2918 UINT64 Msr;\r
2919\r
2920 Msr = AsmReadMsr64 (MSR_SKYLAKE_CORE_C1_RESIDENCY);\r
2921 @endcode\r
2922**/\r
2923#define MSR_SKYLAKE_CORE_C1_RESIDENCY 0x00000660\r
2924\r
2925\r
2926/**\r
2927 Core. Core C3 Residency Counter (R/O). Will always return 0.\r
2928\r
2929 @param ECX MSR_SKYLAKE_CORE_C3_RESIDENCY (0x00000662)\r
2930 @param EAX Lower 32-bits of MSR value.\r
2931 @param EDX Upper 32-bits of MSR value.\r
2932\r
2933 <b>Example usage</b>\r
2934 @code\r
2935 UINT64 Msr;\r
2936\r
2937 Msr = AsmReadMsr64 (MSR_SKYLAKE_CORE_C3_RESIDENCY);\r
2938 @endcode\r
2939**/\r
2940#define MSR_SKYLAKE_CORE_C3_RESIDENCY 0x00000662\r
2941\r
2942\r
2943/**\r
2944 Package. Protected Processor Inventory Number Enable Control (R/W).\r
2945\r
2946 @param ECX MSR_SKYLAKE_PPIN_CTL (0x0000004E)\r
2947 @param EAX Lower 32-bits of MSR value.\r
2948 Described by the type MSR_SKYLAKE_PPIN_CTL_REGISTER.\r
2949 @param EDX Upper 32-bits of MSR value.\r
2950 Described by the type MSR_SKYLAKE_PPIN_CTL_REGISTER.\r
2951\r
2952 <b>Example usage</b>\r
2953 @code\r
2954 MSR_SKYLAKE_PPIN_CTL_REGISTER Msr;\r
2955\r
2956 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_PPIN_CTL);\r
2957 AsmWriteMsr64 (MSR_SKYLAKE_PPIN_CTL, Msr.Uint64);\r
2958 @endcode\r
2959**/\r
2960#define MSR_SKYLAKE_PPIN_CTL 0x0000004E\r
2961\r
2962/**\r
2963 MSR information returned for MSR index #MSR_SKYLAKE_PPIN_CTL\r
2964**/\r
2965typedef union {\r
2966 ///\r
2967 /// Individual bit fields\r
2968 ///\r
2969 struct {\r
2970 ///\r
2971 /// [Bit 0] LockOut (R/WO) See Table 2-25.\r
2972 ///\r
2973 UINT32 LockOut:1;\r
2974 ///\r
2975 /// [Bit 1] Enable_PPIN (R/W) See Table 2-25.\r
2976 ///\r
2977 UINT32 Enable_PPIN:1;\r
2978 UINT32 Reserved1:30;\r
2979 UINT32 Reserved2:32;\r
2980 } Bits;\r
2981 ///\r
2982 /// All bit fields as a 32-bit value\r
2983 ///\r
2984 UINT32 Uint32;\r
2985 ///\r
2986 /// All bit fields as a 64-bit value\r
2987 ///\r
2988 UINT64 Uint64;\r
2989} MSR_SKYLAKE_PPIN_CTL_REGISTER;\r
2990\r
2991\r
2992/**\r
2993 Package. Protected Processor Inventory Number (R/O). Protected Processor\r
2994 Inventory Number (R/O) See Table 2-25.\r
2995\r
2996 @param ECX MSR_SKYLAKE_PPIN (0x0000004F)\r
2997 @param EAX Lower 32-bits of MSR value.\r
2998 @param EDX Upper 32-bits of MSR value.\r
2999\r
3000 <b>Example usage</b>\r
3001 @code\r
3002 UINT64 Msr;\r
3003\r
3004 Msr = AsmReadMsr64 (MSR_SKYLAKE_PPIN);\r
3005 @endcode\r
3006**/\r
3007#define MSR_SKYLAKE_PPIN 0x0000004F\r
3008\r
3009\r
3010/**\r
3011 Package. Platform Information Contains power management and other model\r
3012 specific features enumeration. See http://biosbits.org.\r
3013\r
3014 @param ECX MSR_SKYLAKE_PLATFORM_INFO (0x000000CE)\r
3015 @param EAX Lower 32-bits of MSR value.\r
3016 Described by the type MSR_SKYLAKE_PLATFORM_INFO_REGISTER.\r
3017 @param EDX Upper 32-bits of MSR value.\r
3018 Described by the type MSR_SKYLAKE_PLATFORM_INFO_REGISTER.\r
3019\r
3020 <b>Example usage</b>\r
3021 @code\r
3022 MSR_SKYLAKE_PLATFORM_INFO_REGISTER Msr;\r
3023\r
3024 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_PLATFORM_INFO);\r
3025 AsmWriteMsr64 (MSR_SKYLAKE_PLATFORM_INFO, Msr.Uint64);\r
3026 @endcode\r
3027**/\r
3028#define MSR_SKYLAKE_PLATFORM_INFO 0x000000CE\r
3029\r
3030/**\r
3031 MSR information returned for MSR index #MSR_SKYLAKE_PLATFORM_INFO\r
3032**/\r
3033typedef union {\r
3034 ///\r
3035 /// Individual bit fields\r
3036 ///\r
3037 struct {\r
3038 UINT32 Reserved1:8;\r
3039 ///\r
3040 /// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) See Table 2-25.\r
3041 ///\r
3042 UINT32 MaximumNon_TurboRatio:8;\r
3043 UINT32 Reserved2:7;\r
3044 ///\r
3045 /// [Bit 23] Package. PPIN_CAP (R/O) See Table 2-25.\r
3046 ///\r
3047 UINT32 PPIN_CAP:1;\r
3048 UINT32 Reserved3:4;\r
3049 ///\r
3050 /// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O) See\r
3051 /// Table 2-25.\r
3052 ///\r
3053 UINT32 ProgrammableRatioLimit:1;\r
3054 ///\r
3055 /// [Bit 29] Package. Programmable TDP Limit for Turbo Mode (R/O) See\r
3056 /// Table 2-25.\r
3057 ///\r
3058 UINT32 ProgrammableTDPLimit:1;\r
3059 ///\r
3060 /// [Bit 30] Package. Programmable TJ OFFSET (R/O) See Table 2-25.\r
3061 ///\r
3062 UINT32 ProgrammableTJOFFSET:1;\r
3063 UINT32 Reserved4:1;\r
3064 UINT32 Reserved5:8;\r
3065 ///\r
3066 /// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O) See Table 2-25.\r
3067 ///\r
3068 UINT32 MaximumEfficiencyRatio:8;\r
3069 UINT32 Reserved6:16;\r
3070 } Bits;\r
3071 ///\r
3072 /// All bit fields as a 64-bit value\r
3073 ///\r
3074 UINT64 Uint64;\r
3075} MSR_SKYLAKE_PLATFORM_INFO_REGISTER;\r
3076\r
3077\r
3078/**\r
3079 Core. C-State Configuration Control (R/W) Note: C-state values are processor\r
3080 specific C-state code names, unrelated to MWAIT extension C-state parameters\r
3081 or ACPI C-states. `See http://biosbits.org. <http://biosbits.org/>`__.\r
3082\r
3083 @param ECX MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL (0x000000E2)\r
3084 @param EAX Lower 32-bits of MSR value.\r
3085 Described by the type MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL_REGISTER.\r
3086 @param EDX Upper 32-bits of MSR value.\r
3087 Described by the type MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL_REGISTER.\r
3088\r
3089 <b>Example usage</b>\r
3090 @code\r
3091 MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL_REGISTER Msr;\r
3092\r
3093 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL);\r
3094 AsmWriteMsr64 (MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL, Msr.Uint64);\r
3095 @endcode\r
3096**/\r
3097#define MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL 0x000000E2\r
3098\r
3099/**\r
3100 MSR information returned for MSR index #MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL\r
3101**/\r
3102typedef union {\r
3103 ///\r
3104 /// Individual bit fields\r
3105 ///\r
3106 struct {\r
3107 ///\r
3108 /// [Bits 2:0] Package C-State Limit (R/W) Specifies the lowest\r
3109 /// processor-specific C-state code name (consuming the least power) for\r
3110 /// the package. The default is set as factory-configured package Cstate\r
3111 /// limit. The following C-state code name encodings are supported: 000b:\r
3112 /// C0/C1 (no package C-state support) 001b: C2 010b: C6 (non-retention)\r
3113 /// 011b: C6 (retention) 111b: No Package C state limits. All C states\r
3114 /// supported by the processor are available.\r
3115 ///\r
3116 UINT32 C_StateLimit:3;\r
3117 UINT32 Reserved1:7;\r
3118 ///\r
3119 /// [Bit 10] I/O MWAIT Redirection Enable (R/W).\r
3120 ///\r
3121 UINT32 MWAITRedirectionEnable:1;\r
3122 UINT32 Reserved2:4;\r
3123 ///\r
3124 /// [Bit 15] CFG Lock (R/WO).\r
3125 ///\r
3126 UINT32 CFGLock:1;\r
3127 ///\r
3128 /// [Bit 16] Automatic C-State Conversion Enable (R/W) If 1, the processor\r
3129 /// will convert HALT or MWAT(C1) to MWAIT(C6).\r
3130 ///\r
3131 UINT32 AutomaticC_StateConversionEnable:1;\r
3132 UINT32 Reserved3:8;\r
3133 ///\r
3134 /// [Bit 25] C3 State Auto Demotion Enable (R/W).\r
3135 ///\r
3136 UINT32 C3StateAutoDemotionEnable:1;\r
3137 ///\r
3138 /// [Bit 26] C1 State Auto Demotion Enable (R/W).\r
3139 ///\r
3140 UINT32 C1StateAutoDemotionEnable:1;\r
3141 ///\r
3142 /// [Bit 27] Enable C3 Undemotion (R/W).\r
3143 ///\r
3144 UINT32 EnableC3Undemotion:1;\r
3145 ///\r
3146 /// [Bit 28] Enable C1 Undemotion (R/W).\r
3147 ///\r
3148 UINT32 EnableC1Undemotion:1;\r
3149 ///\r
3150 /// [Bit 29] Package C State Demotion Enable (R/W).\r
3151 ///\r
3152 UINT32 CStateDemotionEnable:1;\r
3153 ///\r
3154 /// [Bit 30] Package C State UnDemotion Enable (R/W).\r
3155 ///\r
3156 UINT32 CStateUnDemotionEnable:1;\r
3157 UINT32 Reserved4:1;\r
3158 UINT32 Reserved5:32;\r
3159 } Bits;\r
3160 ///\r
3161 /// All bit fields as a 32-bit value\r
3162 ///\r
3163 UINT32 Uint32;\r
3164 ///\r
3165 /// All bit fields as a 64-bit value\r
3166 ///\r
3167 UINT64 Uint64;\r
3168} MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL_REGISTER;\r
3169\r
3170\r
3171/**\r
3172 Thread. Global Machine Check Capability (R/O).\r
3173\r
3174 @param ECX MSR_SKYLAKE_IA32_MCG_CAP (0x00000179)\r
3175 @param EAX Lower 32-bits of MSR value.\r
3176 Described by the type MSR_SKYLAKE_IA32_MCG_CAP_REGISTER.\r
3177 @param EDX Upper 32-bits of MSR value.\r
3178 Described by the type MSR_SKYLAKE_IA32_MCG_CAP_REGISTER.\r
3179\r
3180 <b>Example usage</b>\r
3181 @code\r
3182 MSR_SKYLAKE_IA32_MCG_CAP_REGISTER Msr;\r
3183\r
3184 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_IA32_MCG_CAP);\r
3185 @endcode\r
3186**/\r
3187#define MSR_SKYLAKE_IA32_MCG_CAP 0x00000179\r
3188\r
3189/**\r
3190 MSR information returned for MSR index #MSR_SKYLAKE_IA32_MCG_CAP\r
3191**/\r
3192typedef union {\r
3193 ///\r
3194 /// Individual bit fields\r
3195 ///\r
3196 struct {\r
3197 ///\r
3198 /// [Bits 7:0] Count.\r
3199 ///\r
3200 UINT32 Count:8;\r
3201 ///\r
3202 /// [Bit 8] MCG_CTL_P.\r
3203 ///\r
3204 UINT32 MCG_CTL_P:1;\r
3205 ///\r
3206 /// [Bit 9] MCG_EXT_P.\r
3207 ///\r
3208 UINT32 MCG_EXT_P:1;\r
3209 ///\r
3210 /// [Bit 10] MCP_CMCI_P.\r
3211 ///\r
3212 UINT32 MCP_CMCI_P:1;\r
3213 ///\r
3214 /// [Bit 11] MCG_TES_P.\r
3215 ///\r
3216 UINT32 MCG_TES_P:1;\r
3217 UINT32 Reserved1:4;\r
3218 ///\r
3219 /// [Bits 23:16] MCG_EXT_CNT.\r
3220 ///\r
3221 UINT32 MCG_EXT_CNT:8;\r
3222 ///\r
3223 /// [Bit 24] MCG_SER_P.\r
3224 ///\r
3225 UINT32 MCG_SER_P:1;\r
3226 ///\r
3227 /// [Bit 25] MCG_EM_P.\r
3228 ///\r
3229 UINT32 MCG_EM_P:1;\r
3230 ///\r
3231 /// [Bit 26] MCG_ELOG_P.\r
3232 ///\r
3233 UINT32 MCG_ELOG_P:1;\r
3234 UINT32 Reserved2:5;\r
3235 UINT32 Reserved3:32;\r
3236 } Bits;\r
3237 ///\r
3238 /// All bit fields as a 32-bit value\r
3239 ///\r
3240 UINT32 Uint32;\r
3241 ///\r
3242 /// All bit fields as a 64-bit value\r
3243 ///\r
3244 UINT64 Uint64;\r
3245} MSR_SKYLAKE_IA32_MCG_CAP_REGISTER;\r
3246\r
3247\r
3248/**\r
3249 THREAD. Enhanced SMM Capabilities (SMM-RO) Reports SMM capability\r
3250 Enhancement. Accessible only while in SMM.\r
3251\r
3252 @param ECX MSR_SKYLAKE_SMM_MCA_CAP (0x0000017D)\r
3253 @param EAX Lower 32-bits of MSR value.\r
3254 Described by the type MSR_SKYLAKE_SMM_MCA_CAP_REGISTER.\r
3255 @param EDX Upper 32-bits of MSR value.\r
3256 Described by the type MSR_SKYLAKE_SMM_MCA_CAP_REGISTER.\r
3257\r
3258 <b>Example usage</b>\r
3259 @code\r
3260 MSR_SKYLAKE_SMM_MCA_CAP_REGISTER Msr;\r
3261\r
3262 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_SMM_MCA_CAP);\r
3263 AsmWriteMsr64 (MSR_SKYLAKE_SMM_MCA_CAP, Msr.Uint64);\r
3264 @endcode\r
3265**/\r
3266#define MSR_SKYLAKE_SMM_MCA_CAP 0x0000017D\r
3267\r
3268/**\r
3269 MSR information returned for MSR index #MSR_SKYLAKE_SMM_MCA_CAP\r
3270**/\r
3271typedef union {\r
3272 ///\r
3273 /// Individual bit fields\r
3274 ///\r
3275 struct {\r
3276 UINT32 Reserved1:32;\r
3277 UINT32 Reserved2:26;\r
3278 ///\r
3279 /// [Bit 58] SMM_Code_Access_Chk (SMM-RO) If set to 1 indicates that the\r
3280 /// SMM code access restriction is supported and a host-space interface is\r
3281 /// available to SMM handler.\r
3282 ///\r
3283 UINT32 SMM_Code_Access_Chk:1;\r
3284 ///\r
3285 /// [Bit 59] Long_Flow_Indication (SMM-RO) If set to 1 indicates that the\r
3286 /// SMM long flow indicator is supported and a host-space interface is\r
3287 /// available to SMM handler.\r
3288 ///\r
3289 UINT32 Long_Flow_Indication:1;\r
3290 UINT32 Reserved3:4;\r
3291 } Bits;\r
3292 ///\r
3293 /// All bit fields as a 64-bit value\r
3294 ///\r
3295 UINT64 Uint64;\r
3296} MSR_SKYLAKE_SMM_MCA_CAP_REGISTER;\r
3297\r
3298\r
3299/**\r
3300 Package. Temperature Target.\r
3301\r
3302 @param ECX MSR_SKYLAKE_TEMPERATURE_TARGET (0x000001A2)\r
3303 @param EAX Lower 32-bits of MSR value.\r
3304 Described by the type MSR_SKYLAKE_TEMPERATURE_TARGET_REGISTER.\r
3305 @param EDX Upper 32-bits of MSR value.\r
3306 Described by the type MSR_SKYLAKE_TEMPERATURE_TARGET_REGISTER.\r
3307\r
3308 <b>Example usage</b>\r
3309 @code\r
3310 MSR_SKYLAKE_TEMPERATURE_TARGET_REGISTER Msr;\r
3311\r
3312 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_TEMPERATURE_TARGET);\r
3313 AsmWriteMsr64 (MSR_SKYLAKE_TEMPERATURE_TARGET, Msr.Uint64);\r
3314 @endcode\r
3315**/\r
3316#define MSR_SKYLAKE_TEMPERATURE_TARGET 0x000001A2\r
3317\r
3318/**\r
3319 MSR information returned for MSR index #MSR_SKYLAKE_TEMPERATURE_TARGET\r
3320**/\r
3321typedef union {\r
3322 ///\r
3323 /// Individual bit fields\r
3324 ///\r
3325 struct {\r
3326 UINT32 Reserved1:16;\r
3327 ///\r
3328 /// [Bits 23:16] Temperature Target (RO) See Table 2-25.\r
3329 ///\r
3330 UINT32 TemperatureTarget:8;\r
3331 ///\r
3332 /// [Bits 27:24] TCC Activation Offset (R/W) See Table 2-25.\r
3333 ///\r
3334 UINT32 TCCActivationOffset:4;\r
3335 UINT32 Reserved2:4;\r
3336 UINT32 Reserved3:32;\r
3337 } Bits;\r
3338 ///\r
3339 /// All bit fields as a 32-bit value\r
3340 ///\r
3341 UINT32 Uint32;\r
3342 ///\r
3343 /// All bit fields as a 64-bit value\r
3344 ///\r
3345 UINT64 Uint64;\r
3346} MSR_SKYLAKE_TEMPERATURE_TARGET_REGISTER;\r
3347\r
3348/**\r
3349 Package. This register defines the active core ranges for each frequency\r
3350 point. NUMCORE[0:7] must be populated in ascending order. NUMCORE[i+1] must\r
3351 be greater than NUMCORE[i]. Entries with NUMCORE[i] == 0 will be ignored.\r
3352 The last valid entry must have NUMCORE >= the number of cores in the SKU. If\r
3353 any of the rules above are broken, the configuration is silently rejected.\r
3354\r
3355 @param ECX MSR_SKYLAKE_TURBO_RATIO_LIMIT_CORES (0x000001AE)\r
3356 @param EAX Lower 32-bits of MSR value.\r
3357 Described by the type MSR_SKYLAKE_TURBO_RATIO_LIMIT_CORES_REGISTER.\r
3358 @param EDX Upper 32-bits of MSR value.\r
3359 Described by the type MSR_SKYLAKE_TURBO_RATIO_LIMIT_CORES_REGISTER.\r
3360\r
3361 <b>Example usage</b>\r
3362 @code\r
3363 MSR_SKYLAKE_TURBO_RATIO_LIMIT_CORES_REGISTER Msr;\r
3364\r
3365 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_TURBO_RATIO_LIMIT_CORES);\r
3366 AsmWriteMsr64 (MSR_SKYLAKE_TURBO_RATIO_LIMIT_CORES, Msr.Uint64);\r
3367 @endcode\r
3368**/\r
3369#define MSR_SKYLAKE_TURBO_RATIO_LIMIT_CORES 0x000001AE\r
3370\r
3371/**\r
3372 MSR information returned for MSR index #MSR_SKYLAKE_TURBO_RATIO_LIMIT_CORES\r
3373**/\r
3374typedef union {\r
3375 ///\r
3376 /// Individual bit fields\r
3377 ///\r
3378 struct {\r
3379 ///\r
3380 /// [Bits 7:0] NUMCORE_0 Defines the active core ranges for each frequency\r
3381 /// point.\r
3382 ///\r
3383 UINT32 NUMCORE_0:8;\r
3384 ///\r
3385 /// [Bits 15:8] NUMCORE_1 Defines the active core ranges for each\r
3386 /// frequency point.\r
3387 ///\r
3388 UINT32 NUMCORE_1:8;\r
3389 ///\r
3390 /// [Bits 23:16] NUMCORE_2 Defines the active core ranges for each\r
3391 /// frequency point.\r
3392 ///\r
3393 UINT32 NUMCORE_2:8;\r
3394 ///\r
3395 /// [Bits 31:24] NUMCORE_3 Defines the active core ranges for each\r
3396 /// frequency point.\r
3397 ///\r
3398 UINT32 NUMCORE_3:8;\r
3399 ///\r
3400 /// [Bits 39:32] NUMCORE_4 Defines the active core ranges for each\r
3401 /// frequency point.\r
3402 ///\r
3403 UINT32 NUMCORE_4:8;\r
3404 ///\r
3405 /// [Bits 47:40] NUMCORE_5 Defines the active core ranges for each\r
3406 /// frequency point.\r
3407 ///\r
3408 UINT32 NUMCORE_5:8;\r
3409 ///\r
3410 /// [Bits 55:48] NUMCORE_6 Defines the active core ranges for each\r
3411 /// frequency point.\r
3412 ///\r
3413 UINT32 NUMCORE_6:8;\r
3414 ///\r
3415 /// [Bits 63:56] NUMCORE_7 Defines the active core ranges for each\r
3416 /// frequency point.\r
3417 ///\r
3418 UINT32 NUMCORE_7:8;\r
3419 } Bits;\r
3420 ///\r
3421 /// All bit fields as a 64-bit value\r
3422 ///\r
3423 UINT64 Uint64;\r
3424} MSR_SKYLAKE_TURBO_RATIO_LIMIT_CORES_REGISTER;\r
3425\r
3426\r
3427/**\r
3428 Package. Unit Multipliers Used in RAPL Interfaces (R/O).\r
3429\r
3430 @param ECX MSR_SKYLAKE_RAPL_POWER_UNIT (0x00000606)\r
3431 @param EAX Lower 32-bits of MSR value.\r
3432 Described by the type MSR_SKYLAKE_RAPL_POWER_UNIT_REGISTER.\r
3433 @param EDX Upper 32-bits of MSR value.\r
3434 Described by the type MSR_SKYLAKE_RAPL_POWER_UNIT_REGISTER.\r
3435\r
3436 <b>Example usage</b>\r
3437 @code\r
3438 MSR_SKYLAKE_RAPL_POWER_UNIT_REGISTER Msr;\r
3439\r
3440 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_RAPL_POWER_UNIT);\r
3441 @endcode\r
3442**/\r
3443#define MSR_SKYLAKE_RAPL_POWER_UNIT 0x00000606\r
3444\r
3445/**\r
3446 MSR information returned for MSR index #MSR_SKYLAKE_RAPL_POWER_UNIT\r
3447**/\r
3448typedef union {\r
3449 ///\r
3450 /// Individual bit fields\r
3451 ///\r
3452 struct {\r
3453 ///\r
3454 /// [Bits 3:0] Package. Power Units See Section 14.9.1, "RAPL Interfaces.".\r
3455 ///\r
3456 UINT32 PowerUnits:4;\r
3457 UINT32 Reserved1:4;\r
3458 ///\r
3459 /// [Bits 12:8] Package. Energy Status Units Energy related information\r
3460 /// (in Joules) is based on the multiplier, 1/2^ESU; where ESU is an\r
3461 /// unsigned integer represented by bits 12:8. Default value is 0EH (or 61\r
3462 /// micro-joules).\r
3463 ///\r
3464 UINT32 EnergyStatusUnits:5;\r
3465 UINT32 Reserved2:3;\r
3466 ///\r
3467 /// [Bits 19:16] Package. Time Units See Section 14.9.1, "RAPL\r
3468 /// Interfaces.".\r
3469 ///\r
3470 UINT32 TimeUnits:4;\r
3471 UINT32 Reserved3:12;\r
3472 UINT32 Reserved4:32;\r
3473 } Bits;\r
3474 ///\r
3475 /// All bit fields as a 32-bit value\r
3476 ///\r
3477 UINT32 Uint32;\r
3478 ///\r
3479 /// All bit fields as a 64-bit value\r
3480 ///\r
3481 UINT64 Uint64;\r
3482} MSR_SKYLAKE_RAPL_POWER_UNIT_REGISTER;\r
3483\r
3484\r
3485/**\r
3486 Package. DRAM RAPL Power Limit Control (R/W) See Section 14.9.5, "DRAM RAPL\r
3487 Domain.".\r
3488\r
3489 @param ECX MSR_SKYLAKE_DRAM_POWER_LIMIT (0x00000618)\r
3490 @param EAX Lower 32-bits of MSR value.\r
3491 @param EDX Upper 32-bits of MSR value.\r
3492\r
3493 <b>Example usage</b>\r
3494 @code\r
3495 UINT64 Msr;\r
3496\r
3497 Msr = AsmReadMsr64 (MSR_SKYLAKE_DRAM_POWER_LIMIT);\r
3498 AsmWriteMsr64 (MSR_SKYLAKE_DRAM_POWER_LIMIT, Msr);\r
3499 @endcode\r
3500**/\r
3501#define MSR_SKYLAKE_DRAM_POWER_LIMIT 0x00000618\r
3502\r
3503\r
3504/**\r
3505 Package. DRAM Energy Status (R/O) Energy consumed by DRAM devices.\r
3506\r
3507 @param ECX MSR_SKYLAKE_DRAM_ENERGY_STATUS (0x00000619)\r
3508 @param EAX Lower 32-bits of MSR value.\r
3509 Described by the type MSR_SKYLAKE_DRAM_ENERGY_STATUS_REGISTER.\r
3510 @param EDX Upper 32-bits of MSR value.\r
3511 Described by the type MSR_SKYLAKE_DRAM_ENERGY_STATUS_REGISTER.\r
3512\r
3513 <b>Example usage</b>\r
3514 @code\r
3515 MSR_SKYLAKE_DRAM_ENERGY_STATUS_REGISTER Msr;\r
3516\r
3517 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_DRAM_ENERGY_STATUS);\r
3518 @endcode\r
3519**/\r
3520#define MSR_SKYLAKE_DRAM_ENERGY_STATUS 0x00000619\r
3521\r
3522/**\r
3523 MSR information returned for MSR index #MSR_SKYLAKE_DRAM_ENERGY_STATUS\r
3524**/\r
3525typedef union {\r
3526 ///\r
3527 /// Individual bit fields\r
3528 ///\r
3529 struct {\r
3530 ///\r
3531 /// [Bits 31:0] Energy in 15.3 micro-joules. Requires BIOS configuration\r
3532 /// to enable DRAM RAPL mode 0 (Direct VR).\r
3533 ///\r
3534 UINT32 Energy:32;\r
3535 UINT32 Reserved:32;\r
3536 } Bits;\r
3537 ///\r
3538 /// All bit fields as a 32-bit value\r
3539 ///\r
3540 UINT32 Uint32;\r
3541 ///\r
3542 /// All bit fields as a 64-bit value\r
3543 ///\r
3544 UINT64 Uint64;\r
3545} MSR_SKYLAKE_DRAM_ENERGY_STATUS_REGISTER;\r
3546\r
3547\r
3548/**\r
3549 Package. DRAM Performance Throttling Status (R/O) See Section 14.9.5, "DRAM\r
3550 RAPL Domain.".\r
3551\r
3552 @param ECX MSR_SKYLAKE_DRAM_PERF_STATUS (0x0000061B)\r
3553 @param EAX Lower 32-bits of MSR value.\r
3554 @param EDX Upper 32-bits of MSR value.\r
3555\r
3556 <b>Example usage</b>\r
3557 @code\r
3558 UINT64 Msr;\r
3559\r
3560 Msr = AsmReadMsr64 (MSR_SKYLAKE_DRAM_PERF_STATUS);\r
3561 @endcode\r
3562**/\r
3563#define MSR_SKYLAKE_DRAM_PERF_STATUS 0x0000061B\r
3564\r
3565\r
3566/**\r
3567 Package. DRAM RAPL Parameters (R/W) See Section 14.9.5, "DRAM RAPL Domain.".\r
3568\r
3569 @param ECX MSR_SKYLAKE_DRAM_POWER_INFO (0x0000061C)\r
3570 @param EAX Lower 32-bits of MSR value.\r
3571 @param EDX Upper 32-bits of MSR value.\r
3572\r
3573 <b>Example usage</b>\r
3574 @code\r
3575 UINT64 Msr;\r
3576\r
3577 Msr = AsmReadMsr64 (MSR_SKYLAKE_DRAM_POWER_INFO);\r
3578 AsmWriteMsr64 (MSR_SKYLAKE_DRAM_POWER_INFO, Msr);\r
3579 @endcode\r
3580**/\r
3581#define MSR_SKYLAKE_DRAM_POWER_INFO 0x0000061C\r
3582\r
3583\r
3584/**\r
3585 Package. Uncore Ratio Limit (R/W) Out of reset, the min_ratio and max_ratio\r
3586 fields represent the widest possible range of uncore frequencies. Writing to\r
3587 these fields allows software to control the minimum and the maximum\r
3588 frequency that hardware will select.\r
3589\r
3590 @param ECX MSR_SKYLAKE_MSRUNCORE_RATIO_LIMIT (0x00000620)\r
3591 @param EAX Lower 32-bits of MSR value.\r
3592 Described by the type MSR_SKYLAKE_MSRUNCORE_RATIO_LIMIT_REGISTER.\r
3593 @param EDX Upper 32-bits of MSR value.\r
3594 Described by the type MSR_SKYLAKE_MSRUNCORE_RATIO_LIMIT_REGISTER.\r
3595\r
3596 <b>Example usage</b>\r
3597 @code\r
3598 MSR_SKYLAKE_MSRUNCORE_RATIO_LIMIT_REGISTER Msr;\r
3599\r
3600 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_MSRUNCORE_RATIO_LIMIT);\r
3601 AsmWriteMsr64 (MSR_SKYLAKE_MSRUNCORE_RATIO_LIMIT, Msr.Uint64);\r
3602 @endcode\r
3603**/\r
3604#define MSR_SKYLAKE_MSRUNCORE_RATIO_LIMIT 0x00000620\r
3605\r
3606/**\r
3607 MSR information returned for MSR index #MSR_SKYLAKE_MSRUNCORE_RATIO_LIMIT\r
3608**/\r
3609typedef union {\r
3610 ///\r
3611 /// Individual bit fields\r
3612 ///\r
3613 struct {\r
3614 ///\r
3615 /// [Bits 6:0] MAX_RATIO This field is used to limit the max ratio of the\r
3616 /// LLC/Ring.\r
3617 ///\r
3618 UINT32 MAX_RATIO:7;\r
3619 UINT32 Reserved1:1;\r
3620 ///\r
3621 /// [Bits 14:8] MIN_RATIO Writing to this field controls the minimum\r
3622 /// possible ratio of the LLC/Ring.\r
3623 ///\r
3624 UINT32 MIN_RATIO:7;\r
3625 UINT32 Reserved2:17;\r
3626 UINT32 Reserved3:32;\r
3627 } Bits;\r
3628 ///\r
3629 /// All bit fields as a 32-bit value\r
3630 ///\r
3631 UINT32 Uint32;\r
3632 ///\r
3633 /// All bit fields as a 64-bit value\r
3634 ///\r
3635 UINT64 Uint64;\r
3636} MSR_SKYLAKE_MSRUNCORE_RATIO_LIMIT_REGISTER;\r
3637\r
3638\r
3639/**\r
3640 Package. Reserved (R/O) Reads return 0.\r
3641\r
3642 @param ECX MSR_SKYLAKE_PP0_ENERGY_STATUS (0x00000639)\r
3643 @param EAX Lower 32-bits of MSR value.\r
3644 @param EDX Upper 32-bits of MSR value.\r
3645\r
3646 <b>Example usage</b>\r
3647 @code\r
3648 UINT64 Msr;\r
3649\r
3650 Msr = AsmReadMsr64 (MSR_SKYLAKE_PP0_ENERGY_STATUS);\r
3651 @endcode\r
3652**/\r
3653#define MSR_SKYLAKE_PP0_ENERGY_STATUS 0x00000639\r
3654\r
3655\r
3656/**\r
3657 THREAD. Monitoring Event Select Register (R/W) If CPUID.(EAX=07H,\r
3658 ECX=0):EBX.RDT-M[bit 12] = 1.\r
3659\r
3660 @param ECX MSR_SKYLAKE_IA32_QM_EVTSEL (0x00000C8D)\r
3661 @param EAX Lower 32-bits of MSR value.\r
3662 Described by the type MSR_SKYLAKE_IA32_QM_EVTSEL_REGISTER.\r
3663 @param EDX Upper 32-bits of MSR value.\r
3664 Described by the type MSR_SKYLAKE_IA32_QM_EVTSEL_REGISTER.\r
3665\r
3666 <b>Example usage</b>\r
3667 @code\r
3668 MSR_SKYLAKE_IA32_QM_EVTSEL_REGISTER Msr;\r
3669\r
3670 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_IA32_QM_EVTSEL);\r
3671 AsmWriteMsr64 (MSR_SKYLAKE_IA32_QM_EVTSEL, Msr.Uint64);\r
3672 @endcode\r
3673**/\r
3674#define MSR_SKYLAKE_IA32_QM_EVTSEL 0x00000C8D\r
3675\r
3676/**\r
3677 MSR information returned for MSR index #MSR_SKYLAKE_IA32_QM_EVTSEL\r
3678**/\r
3679typedef union {\r
3680 ///\r
3681 /// Individual bit fields\r
3682 ///\r
3683 struct {\r
3684 ///\r
3685 /// [Bits 7:0] EventID (RW) Event encoding: 0x00: No monitoring. 0x01: L3\r
3686 /// occupancy monitoring. 0x02: Total memory bandwidth monitoring. 0x03:\r
3687 /// Local memory bandwidth monitoring. All other encoding reserved.\r
3688 ///\r
3689 UINT32 EventID:8;\r
3690 UINT32 Reserved1:24;\r
3691 ///\r
3692 /// [Bits 41:32] RMID (RW).\r
3693 ///\r
3694 UINT32 RMID:10;\r
3695 UINT32 Reserved2:22;\r
3696 } Bits;\r
3697 ///\r
3698 /// All bit fields as a 64-bit value\r
3699 ///\r
3700 UINT64 Uint64;\r
3701} MSR_SKYLAKE_IA32_QM_EVTSEL_REGISTER;\r
3702\r
3703\r
3704/**\r
3705 THREAD. Resource Association Register (R/W).\r
3706\r
3707 @param ECX MSR_SKYLAKE_IA32_PQR_ASSOC (0x00000C8F)\r
3708 @param EAX Lower 32-bits of MSR value.\r
3709 Described by the type MSR_SKYLAKE_IA32_PQR_ASSOC_REGISTER.\r
3710 @param EDX Upper 32-bits of MSR value.\r
3711 Described by the type MSR_SKYLAKE_IA32_PQR_ASSOC_REGISTER.\r
3712\r
3713 <b>Example usage</b>\r
3714 @code\r
3715 MSR_SKYLAKE_IA32_PQR_ASSOC_REGISTER Msr;\r
3716\r
3717 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_IA32_PQR_ASSOC);\r
3718 AsmWriteMsr64 (MSR_SKYLAKE_IA32_PQR_ASSOC, Msr.Uint64);\r
3719 @endcode\r
3720**/\r
3721#define MSR_SKYLAKE_IA32_PQR_ASSOC 0x00000C8F\r
3722\r
3723/**\r
3724 MSR information returned for MSR index #MSR_SKYLAKE_IA32_PQR_ASSOC\r
3725**/\r
3726typedef union {\r
3727 ///\r
3728 /// Individual bit fields\r
3729 ///\r
3730 struct {\r
3731 ///\r
3732 /// [Bits 9:0] RMID.\r
3733 ///\r
3734 UINT32 RMID:10;\r
3735 UINT32 Reserved1:22;\r
3736 ///\r
3737 /// [Bits 51:32] COS (R/W).\r
3738 ///\r
3739 UINT32 COS:20;\r
3740 UINT32 Reserved2:12;\r
3741 } Bits;\r
3742 ///\r
3743 /// All bit fields as a 64-bit value\r
3744 ///\r
3745 UINT64 Uint64;\r
3746} MSR_SKYLAKE_IA32_PQR_ASSOC_REGISTER;\r
3747\r
3748\r
3749/**\r
3750 Package. L3 Class Of Service Mask - COS N (R/W) If CPUID.(EAX=10H,\r
3751 ECX=1):EDX.COS_MAX[15:0] >=0.\r
3752\r
3753 @param ECX MSR_SKYLAKE_IA32_L3_QOS_MASK_N\r
3754 @param EAX Lower 32-bits of MSR value.\r
3755 Described by the type MSR_SKYLAKE_IA32_L3_QOS_MASK_REGISTER.\r
3756 @param EDX Upper 32-bits of MSR value.\r
3757 Described by the type MSR_SKYLAKE_IA32_L3_QOS_MASK_REGISTER.\r
3758\r
3759 <b>Example usage</b>\r
3760 @code\r
3761 MSR_SKYLAKE_IA32_L3_QOS_MASK_REGISTER Msr;\r
3762\r
3763 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_IA32_L3_QOS_MASK_N);\r
3764 AsmWriteMsr64 (MSR_SKYLAKE_IA32_L3_QOS_MASK_N, Msr.Uint64);\r
3765 @endcode\r
3766**/\r
3767#define MSR_SKYLAKE_IA32_L3_QOS_MASK_0 0x00000C90\r
3768#define MSR_SKYLAKE_IA32_L3_QOS_MASK_1 0x00000C91\r
3769#define MSR_SKYLAKE_IA32_L3_QOS_MASK_2 0x00000C92\r
3770#define MSR_SKYLAKE_IA32_L3_QOS_MASK_3 0x00000C93\r
3771#define MSR_SKYLAKE_IA32_L3_QOS_MASK_4 0x00000C94\r
3772#define MSR_SKYLAKE_IA32_L3_QOS_MASK_5 0x00000C95\r
3773#define MSR_SKYLAKE_IA32_L3_QOS_MASK_6 0x00000C96\r
3774#define MSR_SKYLAKE_IA32_L3_QOS_MASK_7 0x00000C97\r
3775#define MSR_SKYLAKE_IA32_L3_QOS_MASK_8 0x00000C98\r
3776#define MSR_SKYLAKE_IA32_L3_QOS_MASK_9 0x00000C99\r
3777#define MSR_SKYLAKE_IA32_L3_QOS_MASK_10 0x00000C9A\r
3778#define MSR_SKYLAKE_IA32_L3_QOS_MASK_11 0x00000C9B\r
3779#define MSR_SKYLAKE_IA32_L3_QOS_MASK_12 0x00000C9C\r
3780#define MSR_SKYLAKE_IA32_L3_QOS_MASK_13 0x00000C9D\r
3781#define MSR_SKYLAKE_IA32_L3_QOS_MASK_14 0x00000C9E\r
3782#define MSR_SKYLAKE_IA32_L3_QOS_MASK_15 0x00000C9F\r
3783\r
3784/**\r
3785 MSR information returned for MSR index #MSR_SKYLAKE_IA32_L3_QOS_MASK_N\r
3786**/\r
3787typedef union {\r
3788 ///\r
3789 /// Individual bit fields\r
3790 ///\r
3791 struct {\r
3792 ///\r
3793 /// [Bit 19:0] CBM: Bit vector of available L3 ways for COS N enforcement.\r
3794 ///\r
3795 UINT32 CBM:20;\r
3796 UINT32 Reserved2:12;\r
3797 UINT32 Reserved3:32;\r
3798 } Bits;\r
3799 ///\r
3800 /// All bit fields as a 32-bit value\r
3801 ///\r
3802 UINT32 Uint32;\r
3803 ///\r
3804 /// All bit fields as a 64-bit value\r
3805 ///\r
3806 UINT64 Uint64;\r
3807} MSR_SKYLAKE_IA32_L3_QOS_MASK_REGISTER;\r
3808\r
3809\r
6b55a245 3810#endif\r
EFI Development Kit II mirror for PVE