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1 | /** @file\r |
2 | MSR Definitions for Intel(R) Xeon(R) Processor Series 5600.\r | |
3 | \r | |
4 | Provides defines for Machine Specific Registers(MSR) indexes. Data structures\r | |
5 | are provided for MSRs that contain one or more bit fields. If the MSR value\r | |
6 | returned is a single 32-bit or 64-bit value, then a data structure is not\r | |
7 | provided for that MSR.\r | |
8 | \r | |
9 | Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>\r | |
10 | This program and the accompanying materials\r | |
11 | are licensed and made available under the terms and conditions of the BSD License\r | |
12 | which accompanies this distribution. The full text of the license may be found at\r | |
13 | http://opensource.org/licenses/bsd-license.php\r | |
14 | \r | |
15 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
16 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
17 | \r | |
18 | @par Specification Reference:\r | |
19 | Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,\r | |
20 | December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-6.\r | |
21 | \r | |
22 | **/\r | |
23 | \r | |
24 | #ifndef __XEON_5600_MSR_H__\r | |
25 | #define __XEON_5600_MSR_H__\r | |
26 | \r | |
27 | #include <Register/ArchitecturalMsr.h>\r | |
28 | \r | |
29 | /**\r | |
30 | Core. AES Configuration (RW-L) Privileged post-BIOS agent must provide a #GP\r | |
31 | handler to handle unsuccessful read of this MSR.\r | |
32 | \r | |
33 | @param ECX MSR_XEON_5600_FEATURE_CONFIG (0x0000013C)\r | |
34 | @param EAX Lower 32-bits of MSR value.\r | |
35 | Described by the type MSR_XEON_5600_FEATURE_CONFIG_REGISTER.\r | |
36 | @param EDX Upper 32-bits of MSR value.\r | |
37 | Described by the type MSR_XEON_5600_FEATURE_CONFIG_REGISTER.\r | |
38 | \r | |
39 | <b>Example usage</b>\r | |
40 | @code\r | |
41 | MSR_XEON_5600_FEATURE_CONFIG_REGISTER Msr;\r | |
42 | \r | |
43 | Msr.Uint64 = AsmReadMsr64 (MSR_XEON_5600_FEATURE_CONFIG);\r | |
44 | AsmWriteMsr64 (MSR_XEON_5600_FEATURE_CONFIG, Msr.Uint64);\r | |
45 | @endcode\r | |
46 | **/\r | |
47 | #define MSR_XEON_5600_FEATURE_CONFIG 0x0000013C\r | |
48 | \r | |
49 | /**\r | |
50 | MSR information returned for MSR index #MSR_XEON_5600_FEATURE_CONFIG\r | |
51 | **/\r | |
52 | typedef union {\r | |
53 | ///\r | |
54 | /// Individual bit fields\r | |
55 | ///\r | |
56 | struct {\r | |
57 | ///\r | |
58 | /// [Bits 1:0] AES Configuration (RW-L) Upon a successful read of this\r | |
59 | /// MSR, the configuration of AES instruction set availability is as\r | |
60 | /// follows: 11b: AES instructions are not available until next RESET.\r | |
61 | /// otherwise, AES instructions are available. Note, AES instruction set\r | |
62 | /// is not available if read is unsuccessful. If the configuration is not\r | |
63 | /// 01b, AES instruction can be mis-configured if a privileged agent\r | |
64 | /// unintentionally writes 11b.\r | |
65 | ///\r | |
66 | UINT32 AESConfiguration:2;\r | |
67 | UINT32 Reserved1:30;\r | |
68 | UINT32 Reserved2:32;\r | |
69 | } Bits;\r | |
70 | ///\r | |
71 | /// All bit fields as a 32-bit value\r | |
72 | ///\r | |
73 | UINT32 Uint32;\r | |
74 | ///\r | |
75 | /// All bit fields as a 64-bit value\r | |
76 | ///\r | |
77 | UINT64 Uint64;\r | |
78 | } MSR_XEON_5600_FEATURE_CONFIG_REGISTER;\r | |
79 | \r | |
80 | \r | |
81 | /**\r | |
82 | Thread. Offcore Response Event Select Register (R/W).\r | |
83 | \r | |
84 | @param ECX MSR_XEON_5600_OFFCORE_RSP_1 (0x000001A7)\r | |
85 | @param EAX Lower 32-bits of MSR value.\r | |
86 | @param EDX Upper 32-bits of MSR value.\r | |
87 | \r | |
88 | <b>Example usage</b>\r | |
89 | @code\r | |
90 | UINT64 Msr;\r | |
91 | \r | |
92 | Msr = AsmReadMsr64 (MSR_XEON_5600_OFFCORE_RSP_1);\r | |
93 | AsmWriteMsr64 (MSR_XEON_5600_OFFCORE_RSP_1, Msr);\r | |
94 | @endcode\r | |
95 | **/\r | |
96 | #define MSR_XEON_5600_OFFCORE_RSP_1 0x000001A7\r | |
97 | \r | |
98 | \r | |
99 | /**\r | |
100 | Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,\r | |
101 | RW if MSR_PLATFORM_INFO.[28] = 1.\r | |
102 | \r | |
103 | @param ECX MSR_XEON_5600_TURBO_RATIO_LIMIT (0x000001AD)\r | |
104 | @param EAX Lower 32-bits of MSR value.\r | |
105 | Described by the type MSR_XEON_5600_TURBO_RATIO_LIMIT_REGISTER.\r | |
106 | @param EDX Upper 32-bits of MSR value.\r | |
107 | Described by the type MSR_XEON_5600_TURBO_RATIO_LIMIT_REGISTER.\r | |
108 | \r | |
109 | <b>Example usage</b>\r | |
110 | @code\r | |
111 | MSR_XEON_5600_TURBO_RATIO_LIMIT_REGISTER Msr;\r | |
112 | \r | |
113 | Msr.Uint64 = AsmReadMsr64 (MSR_XEON_5600_TURBO_RATIO_LIMIT);\r | |
114 | @endcode\r | |
115 | **/\r | |
116 | #define MSR_XEON_5600_TURBO_RATIO_LIMIT 0x000001AD\r | |
117 | \r | |
118 | /**\r | |
119 | MSR information returned for MSR index #MSR_XEON_5600_TURBO_RATIO_LIMIT_REGISTER\r | |
120 | **/\r | |
121 | typedef union {\r | |
122 | ///\r | |
123 | /// Individual bit fields\r | |
124 | ///\r | |
125 | struct {\r | |
126 | ///\r | |
127 | /// [Bits 7:0] Package. Maximum Ratio Limit for 1C Maximum turbo ratio\r | |
128 | /// limit of 1 core active.\r | |
129 | ///\r | |
130 | UINT32 Maximum1C:8;\r | |
131 | ///\r | |
132 | /// [Bits 15:8] Package. Maximum Ratio Limit for 2C Maximum turbo ratio\r | |
133 | /// limit of 2 core active.\r | |
134 | ///\r | |
135 | UINT32 Maximum2C:8;\r | |
136 | ///\r | |
137 | /// [Bits 23:16] Package. Maximum Ratio Limit for 3C Maximum turbo ratio\r | |
138 | /// limit of 3 core active.\r | |
139 | ///\r | |
140 | UINT32 Maximum3C:8;\r | |
141 | ///\r | |
142 | /// [Bits 31:24] Package. Maximum Ratio Limit for 4C Maximum turbo ratio\r | |
143 | /// limit of 4 core active.\r | |
144 | ///\r | |
145 | UINT32 Maximum4C:8;\r | |
146 | ///\r | |
147 | /// [Bits 39:32] Package. Maximum Ratio Limit for 5C Maximum turbo ratio\r | |
148 | /// limit of 5 core active.\r | |
149 | ///\r | |
150 | UINT32 Maximum5C:8;\r | |
151 | ///\r | |
152 | /// [Bits 47:40] Package. Maximum Ratio Limit for 6C Maximum turbo ratio\r | |
153 | /// limit of 6 core active.\r | |
154 | ///\r | |
155 | UINT32 Maximum6C:8;\r | |
156 | UINT32 Reserved:16;\r | |
157 | } Bits;\r | |
158 | ///\r | |
159 | /// All bit fields as a 64-bit value\r | |
160 | ///\r | |
161 | UINT64 Uint64;\r | |
162 | } MSR_XEON_5600_TURBO_RATIO_LIMIT_REGISTER;\r | |
163 | \r | |
164 | \r | |
165 | /**\r | |
166 | Package. See Table 35-2.\r | |
167 | \r | |
168 | @param ECX MSR_XEON_5600_IA32_ENERGY_PERF_BIAS (0x000001B0)\r | |
169 | @param EAX Lower 32-bits of MSR value.\r | |
170 | @param EDX Upper 32-bits of MSR value.\r | |
171 | \r | |
172 | <b>Example usage</b>\r | |
173 | @code\r | |
174 | UINT64 Msr;\r | |
175 | \r | |
176 | Msr = AsmReadMsr64 (MSR_XEON_5600_IA32_ENERGY_PERF_BIAS);\r | |
177 | AsmWriteMsr64 (MSR_XEON_5600_IA32_ENERGY_PERF_BIAS, Msr);\r | |
178 | @endcode\r | |
179 | **/\r | |
180 | #define MSR_XEON_5600_IA32_ENERGY_PERF_BIAS 0x000001B0\r | |
181 | \r | |
182 | #endif\r |