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UefiCpuPkg/IvyBridgeMsr.h: add MSR reference from SDM in comment
[mirror_edk2.git] / UefiCpuPkg / Include / Register / Msr / XeonDMsr.h
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54307cea
MK		 1/** @file\r
2 MSR Definitions for Intel(R) Xeon(R) Processor D product Family.\r
3\r
4 Provides defines for Machine Specific Registers(MSR) indexes. Data structures\r
5 are provided for MSRs that contain one or more bit fields. If the MSR value\r
6 returned is a single 32-bit or 64-bit value, then a data structure is not\r
7 provided for that MSR.\r
8\r
9 Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>\r
10 This program and the accompanying materials\r
11 are licensed and made available under the terms and conditions of the BSD License\r
12 which accompanies this distribution. The full text of the license may be found at\r
13 http://opensource.org/licenses/bsd-license.php\r
14\r
15 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
16 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
17\r
18 @par Specification Reference:\r
19 Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,\r
20 December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-13.\r
21\r
22**/\r
23\r
24#ifndef __XEON_D_MSR_H__\r
25#define __XEON_D_MSR_H__\r
26\r
27#include <Register/ArchitecturalMsr.h>\r
28\r
29/**\r
30 Package. Protected Processor Inventory Number Enable Control (R/W).\r
31\r
32 @param ECX MSR_XEON_D_PPIN_CTL (0x0000004E)\r
33 @param EAX Lower 32-bits of MSR value.\r
34 Described by the type MSR_XEON_D_PPIN_CTL_REGISTER.\r
35 @param EDX Upper 32-bits of MSR value.\r
36 Described by the type MSR_XEON_D_PPIN_CTL_REGISTER.\r
37\r
38 <b>Example usage</b>\r
39 @code\r
40 MSR_XEON_D_PPIN_CTL_REGISTER Msr;\r
41\r
42 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_PPIN_CTL);\r
43 AsmWriteMsr64 (MSR_XEON_D_PPIN_CTL, Msr.Uint64);\r
44 @endcode\r
45**/\r
46#define MSR_XEON_D_PPIN_CTL 0x0000004E\r
47\r
48/**\r
49 MSR information returned for MSR index #MSR_XEON_D_PPIN_CTL\r
50**/\r
51typedef union {\r
52 ///\r
53 /// Individual bit fields\r
54 ///\r
55 struct {\r
56 ///\r
57 /// [Bit 0] LockOut (R/WO) See Table 35-21.\r
58 ///\r
59 UINT32 LockOut:1;\r
60 ///\r
61 /// [Bit 1] Enable_PPIN (R/W) See Table 35-21.\r
62 ///\r
63 UINT32 Enable_PPIN:1;\r
64 UINT32 Reserved1:30;\r
65 UINT32 Reserved2:32;\r
66 } Bits;\r
67 ///\r
68 /// All bit fields as a 32-bit value\r
69 ///\r
70 UINT32 Uint32;\r
71 ///\r
72 /// All bit fields as a 64-bit value\r
73 ///\r
74 UINT64 Uint64;\r
75} MSR_XEON_D_PPIN_CTL_REGISTER;\r
76\r
77\r
78/**\r
79 Package. Protected Processor Inventory Number (R/O). Protected Processor\r
80 Inventory Number (R/O) See Table 35-21.\r
81\r
82 @param ECX MSR_XEON_D_PPIN (0x0000004F)\r
83 @param EAX Lower 32-bits of MSR value.\r
84 @param EDX Upper 32-bits of MSR value.\r
85\r
86 <b>Example usage</b>\r
87 @code\r
88 UINT64 Msr;\r
89\r
90 Msr = AsmReadMsr64 (MSR_XEON_D_PPIN);\r
91 @endcode\r
92**/\r
93#define MSR_XEON_D_PPIN 0x0000004F\r
94\r
95\r
96/**\r
97 Package. See http://biosbits.org.\r
98\r
99 @param ECX MSR_XEON_D_PLATFORM_INFO (0x000000CE)\r
100 @param EAX Lower 32-bits of MSR value.\r
101 Described by the type MSR_XEON_D_PLATFORM_INFO_REGISTER.\r
102 @param EDX Upper 32-bits of MSR value.\r
103 Described by the type MSR_XEON_D_PLATFORM_INFO_REGISTER.\r
104\r
105 <b>Example usage</b>\r
106 @code\r
107 MSR_XEON_D_PLATFORM_INFO_REGISTER Msr;\r
108\r
109 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_PLATFORM_INFO);\r
110 AsmWriteMsr64 (MSR_XEON_D_PLATFORM_INFO, Msr.Uint64);\r
111 @endcode\r
112**/\r
113#define MSR_XEON_D_PLATFORM_INFO 0x000000CE\r
114\r
115/**\r
116 MSR information returned for MSR index #MSR_XEON_D_PLATFORM_INFO\r
117**/\r
118typedef union {\r
119 ///\r
120 /// Individual bit fields\r
121 ///\r
122 struct {\r
123 UINT32 Reserved1:8;\r
124 ///\r
125 /// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) See Table 35-21.\r
126 ///\r
127 UINT32 MaximumNonTurboRatio:8;\r
128 UINT32 Reserved2:7;\r
129 ///\r
130 /// [Bit 23] Package. PPIN_CAP (R/O) See Table 35-21.\r
131 ///\r
132 UINT32 PPIN_CAP:1;\r
133 UINT32 Reserved3:4;\r
134 ///\r
135 /// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O) See\r
136 /// Table 35-21.\r
137 ///\r
138 UINT32 RatioLimit:1;\r
139 ///\r
140 /// [Bit 29] Package. Programmable TDP Limit for Turbo Mode (R/O) See\r
141 /// Table 35-21.\r
142 ///\r
143 UINT32 TDPLimit:1;\r
144 ///\r
145 /// [Bit 30] Package. Programmable TJ OFFSET (R/O) See Table 35-21.\r
146 ///\r
147 UINT32 TJOFFSET:1;\r
148 UINT32 Reserved4:1;\r
149 UINT32 Reserved5:8;\r
150 ///\r
151 /// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O) See Table 35-21.\r
152 ///\r
153 UINT32 MaximumEfficiencyRatio:8;\r
154 UINT32 Reserved6:16;\r
155 } Bits;\r
156 ///\r
157 /// All bit fields as a 64-bit value\r
158 ///\r
159 UINT64 Uint64;\r
160} MSR_XEON_D_PLATFORM_INFO_REGISTER;\r
161\r
162\r
163/**\r
164 Core. C-State Configuration Control (R/W) Note: C-state values are processor\r
165 specific C-state code names, unrelated to MWAIT extension C-state parameters\r
166 or ACPI C-states. `See http://biosbits.org. <http://biosbits.org>`__.\r
167\r
168 @param ECX MSR_XEON_D_PKG_CST_CONFIG_CONTROL (0x000000E2)\r
169 @param EAX Lower 32-bits of MSR value.\r
170 Described by the type MSR_XEON_D_PKG_CST_CONFIG_CONTROL_REGISTER.\r
171 @param EDX Upper 32-bits of MSR value.\r
172 Described by the type MSR_XEON_D_PKG_CST_CONFIG_CONTROL_REGISTER.\r
173\r
174 <b>Example usage</b>\r
175 @code\r
176 MSR_XEON_D_PKG_CST_CONFIG_CONTROL_REGISTER Msr;\r
177\r
178 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_PKG_CST_CONFIG_CONTROL);\r
179 AsmWriteMsr64 (MSR_XEON_D_PKG_CST_CONFIG_CONTROL, Msr.Uint64);\r
180 @endcode\r
181**/\r
182#define MSR_XEON_D_PKG_CST_CONFIG_CONTROL 0x000000E2\r
183\r
184/**\r
185 MSR information returned for MSR index #MSR_XEON_D_PKG_CST_CONFIG_CONTROL\r
186**/\r
187typedef union {\r
188 ///\r
189 /// Individual bit fields\r
190 ///\r
191 struct {\r
192 ///\r
193 /// [Bits 2:0] Package C-State Limit (R/W) Specifies the lowest\r
194 /// processor-specific C-state code name (consuming the least power) for\r
195 /// the package. The default is set as factory-configured package C-state\r
196 /// limit. The following C-state code name encodings are supported: 000b:\r
197 /// C0/C1 (no package C-state support) 001b: C2 010b: C6 (non-retention)\r
198 /// 011b: C6 (retention) 111b: No Package C state limits. All C states\r
199 /// supported by the processor are available.\r
200 ///\r
201 UINT32 Limit:3;\r
202 UINT32 Reserved1:7;\r
203 ///\r
204 /// [Bit 10] I/O MWAIT Redirection Enable (R/W).\r
205 ///\r
206 UINT32 IO_MWAIT:1;\r
207 UINT32 Reserved2:4;\r
208 ///\r
209 /// [Bit 15] CFG Lock (R/WO).\r
210 ///\r
211 UINT32 CFGLock:1;\r
212 ///\r
213 /// [Bit 16] Automatic C-State Conversion Enable (R/W) If 1, the processor\r
214 /// will convert HALT or MWAT(C1) to MWAIT(C6).\r
215 ///\r
216 UINT32 CStateConversion:1;\r
217 UINT32 Reserved3:8;\r
218 ///\r
219 /// [Bit 25] C3 State Auto Demotion Enable (R/W).\r
220 ///\r
221 UINT32 C3AutoDemotion:1;\r
222 ///\r
223 /// [Bit 26] C1 State Auto Demotion Enable (R/W).\r
224 ///\r
225 UINT32 C1AutoDemotion:1;\r
226 ///\r
227 /// [Bit 27] Enable C3 Undemotion (R/W).\r
228 ///\r
229 UINT32 C3Undemotion:1;\r
230 ///\r
231 /// [Bit 28] Enable C1 Undemotion (R/W).\r
232 ///\r
233 UINT32 C1Undemotion:1;\r
234 ///\r
235 /// [Bit 29] Package C State Demotion Enable (R/W).\r
236 ///\r
237 UINT32 CStateDemotion:1;\r
238 ///\r
239 /// [Bit 30] Package C State UnDemotion Enable (R/W).\r
240 ///\r
241 UINT32 CStateUndemotion:1;\r
242 UINT32 Reserved4:1;\r
243 UINT32 Reserved5:32;\r
244 } Bits;\r
245 ///\r
246 /// All bit fields as a 32-bit value\r
247 ///\r
248 UINT32 Uint32;\r
249 ///\r
250 /// All bit fields as a 64-bit value\r
251 ///\r
252 UINT64 Uint64;\r
253} MSR_XEON_D_PKG_CST_CONFIG_CONTROL_REGISTER;\r
254\r
255\r
256/**\r
257 Thread. Global Machine Check Capability (R/O).\r
258\r
259 @param ECX MSR_XEON_D_IA32_MCG_CAP (0x00000179)\r
260 @param EAX Lower 32-bits of MSR value.\r
261 Described by the type MSR_XEON_D_IA32_MCG_CAP_REGISTER.\r
262 @param EDX Upper 32-bits of MSR value.\r
263 Described by the type MSR_XEON_D_IA32_MCG_CAP_REGISTER.\r
264\r
265 <b>Example usage</b>\r
266 @code\r
267 MSR_XEON_D_IA32_MCG_CAP_REGISTER Msr;\r
268\r
269 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_IA32_MCG_CAP);\r
270 @endcode\r
271**/\r
272#define MSR_XEON_D_IA32_MCG_CAP 0x00000179\r
273\r
274/**\r
275 MSR information returned for MSR index #MSR_XEON_D_IA32_MCG_CAP\r
276**/\r
277typedef union {\r
278 ///\r
279 /// Individual bit fields\r
280 ///\r
281 struct {\r
282 ///\r
283 /// [Bits 7:0] Count.\r
284 ///\r
285 UINT32 Count:8;\r
286 ///\r
287 /// [Bit 8] MCG_CTL_P.\r
288 ///\r
289 UINT32 MCG_CTL_P:1;\r
290 ///\r
291 /// [Bit 9] MCG_EXT_P.\r
292 ///\r
293 UINT32 MCG_EXT_P:1;\r
294 ///\r
295 /// [Bit 10] MCP_CMCI_P.\r
296 ///\r
297 UINT32 MCP_CMCI_P:1;\r
298 ///\r
299 /// [Bit 11] MCG_TES_P.\r
300 ///\r
301 UINT32 MCG_TES_P:1;\r
302 UINT32 Reserved1:4;\r
303 ///\r
304 /// [Bits 23:16] MCG_EXT_CNT.\r
305 ///\r
306 UINT32 MCG_EXT_CNT:8;\r
307 ///\r
308 /// [Bit 24] MCG_SER_P.\r
309 ///\r
310 UINT32 MCG_SER_P:1;\r
311 ///\r
312 /// [Bit 25] MCG_EM_P.\r
313 ///\r
314 UINT32 MCG_EM_P:1;\r
315 ///\r
316 /// [Bit 26] MCG_ELOG_P.\r
317 ///\r
318 UINT32 MCG_ELOG_P:1;\r
319 UINT32 Reserved2:5;\r
320 UINT32 Reserved3:32;\r
321 } Bits;\r
322 ///\r
323 /// All bit fields as a 32-bit value\r
324 ///\r
325 UINT32 Uint32;\r
326 ///\r
327 /// All bit fields as a 64-bit value\r
328 ///\r
329 UINT64 Uint64;\r
330} MSR_XEON_D_IA32_MCG_CAP_REGISTER;\r
331\r
332\r
333/**\r
334 THREAD. Enhanced SMM Capabilities (SMM-RO) Reports SMM capability\r
335 Enhancement. Accessible only while in SMM.\r
336\r
337 @param ECX MSR_XEON_D_SMM_MCA_CAP (0x0000017D)\r
338 @param EAX Lower 32-bits of MSR value.\r
339 Described by the type MSR_XEON_D_SMM_MCA_CAP_REGISTER.\r
340 @param EDX Upper 32-bits of MSR value.\r
341 Described by the type MSR_XEON_D_SMM_MCA_CAP_REGISTER.\r
342\r
343 <b>Example usage</b>\r
344 @code\r
345 MSR_XEON_D_SMM_MCA_CAP_REGISTER Msr;\r
346\r
347 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_SMM_MCA_CAP);\r
348 AsmWriteMsr64 (MSR_XEON_D_SMM_MCA_CAP, Msr.Uint64);\r
349 @endcode\r
350**/\r
351#define MSR_XEON_D_SMM_MCA_CAP 0x0000017D\r
352\r
353/**\r
354 MSR information returned for MSR index #MSR_XEON_D_SMM_MCA_CAP\r
355**/\r
356typedef union {\r
357 ///\r
358 /// Individual bit fields\r
359 ///\r
360 struct {\r
361 UINT32 Reserved1:32;\r
362 UINT32 Reserved2:26;\r
363 ///\r
364 /// [Bit 58] SMM_Code_Access_Chk (SMM-RO) If set to 1 indicates that the\r
365 /// SMM code access restriction is supported and a host-space interface\r
366 /// available to SMM handler.\r
367 ///\r
368 UINT32 SMM_Code_Access_Chk:1;\r
369 ///\r
370 /// [Bit 59] Long_Flow_Indication (SMM-RO) If set to 1 indicates that the\r
371 /// SMM long flow indicator is supported and a host-space interface\r
372 /// available to SMM handler.\r
373 ///\r
374 UINT32 Long_Flow_Indication:1;\r
375 UINT32 Reserved3:4;\r
376 } Bits;\r
377 ///\r
378 /// All bit fields as a 64-bit value\r
379 ///\r
380 UINT64 Uint64;\r
381} MSR_XEON_D_SMM_MCA_CAP_REGISTER;\r
382\r
383\r
384/**\r
385 Package.\r
386\r
387 @param ECX MSR_XEON_D_TEMPERATURE_TARGET (0x000001A2)\r
388 @param EAX Lower 32-bits of MSR value.\r
389 Described by the type MSR_XEON_D_TEMPERATURE_TARGET_REGISTER.\r
390 @param EDX Upper 32-bits of MSR value.\r
391 Described by the type MSR_XEON_D_TEMPERATURE_TARGET_REGISTER.\r
392\r
393 <b>Example usage</b>\r
394 @code\r
395 MSR_XEON_D_TEMPERATURE_TARGET_REGISTER Msr;\r
396\r
397 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_TEMPERATURE_TARGET);\r
398 AsmWriteMsr64 (MSR_XEON_D_TEMPERATURE_TARGET, Msr.Uint64);\r
399 @endcode\r
400**/\r
401#define MSR_XEON_D_TEMPERATURE_TARGET 0x000001A2\r
402\r
403/**\r
404 MSR information returned for MSR index #MSR_XEON_D_TEMPERATURE_TARGET\r
405**/\r
406typedef union {\r
407 ///\r
408 /// Individual bit fields\r
409 ///\r
410 struct {\r
411 UINT32 Reserved1:16;\r
412 ///\r
413 /// [Bits 23:16] Temperature Target (RO) See Table 35-21.\r
414 ///\r
415 UINT32 TemperatureTarget:8;\r
416 ///\r
417 /// [Bits 27:24] TCC Activation Offset (R/W) See Table 35-21.\r
418 ///\r
419 UINT32 TCCActivationOffset:4;\r
420 UINT32 Reserved2:4;\r
421 UINT32 Reserved3:32;\r
422 } Bits;\r
423 ///\r
424 /// All bit fields as a 32-bit value\r
425 ///\r
426 UINT32 Uint32;\r
427 ///\r
428 /// All bit fields as a 64-bit value\r
429 ///\r
430 UINT64 Uint64;\r
431} MSR_XEON_D_TEMPERATURE_TARGET_REGISTER;\r
432\r
433\r
434/**\r
435 Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,\r
436 RW if MSR_PLATFORM_INFO.[28] = 1.\r
437\r
438 @param ECX MSR_XEON_D_TURBO_RATIO_LIMIT (0x000001AD)\r
439 @param EAX Lower 32-bits of MSR value.\r
440 Described by the type MSR_XEON_D_TURBO_RATIO_LIMIT_REGISTER.\r
441 @param EDX Upper 32-bits of MSR value.\r
442 Described by the type MSR_XEON_D_TURBO_RATIO_LIMIT_REGISTER.\r
443\r
444 <b>Example usage</b>\r
445 @code\r
446 MSR_XEON_D_TURBO_RATIO_LIMIT_REGISTER Msr;\r
447\r
448 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_TURBO_RATIO_LIMIT);\r
449 @endcode\r
450**/\r
451#define MSR_XEON_D_TURBO_RATIO_LIMIT 0x000001AD\r
452\r
453/**\r
454 MSR information returned for MSR index #MSR_XEON_D_TURBO_RATIO_LIMIT\r
455**/\r
456typedef union {\r
457 ///\r
458 /// Individual bit fields\r
459 ///\r
460 struct {\r
461 ///\r
462 /// [Bits 7:0] Package. Maximum Ratio Limit for 1C.\r
463 ///\r
464 UINT32 Maximum1C:8;\r
465 ///\r
466 /// [Bits 15:8] Package. Maximum Ratio Limit for 2C.\r
467 ///\r
468 UINT32 Maximum2C:8;\r
469 ///\r
470 /// [Bits 23:16] Package. Maximum Ratio Limit for 3C.\r
471 ///\r
472 UINT32 Maximum3C:8;\r
473 ///\r
474 /// [Bits 31:24] Package. Maximum Ratio Limit for 4C.\r
475 ///\r
476 UINT32 Maximum4C:8;\r
477 ///\r
478 /// [Bits 39:32] Package. Maximum Ratio Limit for 5C.\r
479 ///\r
480 UINT32 Maximum5C:8;\r
481 ///\r
482 /// [Bits 47:40] Package. Maximum Ratio Limit for 6C.\r
483 ///\r
484 UINT32 Maximum6C:8;\r
485 ///\r
486 /// [Bits 55:48] Package. Maximum Ratio Limit for 7C.\r
487 ///\r
488 UINT32 Maximum7C:8;\r
489 ///\r
490 /// [Bits 63:56] Package. Maximum Ratio Limit for 8C.\r
491 ///\r
492 UINT32 Maximum8C:8;\r
493 } Bits;\r
494 ///\r
495 /// All bit fields as a 64-bit value\r
496 ///\r
497 UINT64 Uint64;\r
498} MSR_XEON_D_TURBO_RATIO_LIMIT_REGISTER;\r
499\r
500\r
501/**\r
502 Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,\r
503 RW if MSR_PLATFORM_INFO.[28] = 1.\r
504\r
505 @param ECX MSR_XEON_D_TURBO_RATIO_LIMIT1 (0x000001AE)\r
506 @param EAX Lower 32-bits of MSR value.\r
507 Described by the type MSR_XEON_D_TURBO_RATIO_LIMIT1_REGISTER.\r
508 @param EDX Upper 32-bits of MSR value.\r
509 Described by the type MSR_XEON_D_TURBO_RATIO_LIMIT1_REGISTER.\r
510\r
511 <b>Example usage</b>\r
512 @code\r
513 MSR_XEON_D_TURBO_RATIO_LIMIT1_REGISTER Msr;\r
514\r
515 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_TURBO_RATIO_LIMIT1);\r
516 @endcode\r
517**/\r
518#define MSR_XEON_D_TURBO_RATIO_LIMIT1 0x000001AE\r
519\r
520/**\r
521 MSR information returned for MSR index #MSR_XEON_D_TURBO_RATIO_LIMIT1\r
522**/\r
523typedef union {\r
524 ///\r
525 /// Individual bit fields\r
526 ///\r
527 struct {\r
528 ///\r
529 /// [Bits 7:0] Package. Maximum Ratio Limit for 9C.\r
530 ///\r
531 UINT32 Maximum9C:8;\r
532 ///\r
533 /// [Bits 15:8] Package. Maximum Ratio Limit for 10C.\r
534 ///\r
535 UINT32 Maximum10C:8;\r
536 ///\r
537 /// [Bits 23:16] Package. Maximum Ratio Limit for 11C.\r
538 ///\r
539 UINT32 Maximum11C:8;\r
540 ///\r
541 /// [Bits 31:24] Package. Maximum Ratio Limit for 12C.\r
542 ///\r
543 UINT32 Maximum12C:8;\r
544 ///\r
545 /// [Bits 39:32] Package. Maximum Ratio Limit for 13C.\r
546 ///\r
547 UINT32 Maximum13C:8;\r
548 ///\r
549 /// [Bits 47:40] Package. Maximum Ratio Limit for 14C.\r
550 ///\r
551 UINT32 Maximum14C:8;\r
552 ///\r
553 /// [Bits 55:48] Package. Maximum Ratio Limit for 15C.\r
554 ///\r
555 UINT32 Maximum15C:8;\r
556 ///\r
557 /// [Bits 63:56] Package. Maximum Ratio Limit for 16C.\r
558 ///\r
559 UINT32 Maximum16C:8;\r
560 } Bits;\r
561 ///\r
562 /// All bit fields as a 64-bit value\r
563 ///\r
564 UINT64 Uint64;\r
565} MSR_XEON_D_TURBO_RATIO_LIMIT1_REGISTER;\r
566\r
567\r
568/**\r
569 Package. Unit Multipliers used in RAPL Interfaces (R/O).\r
570\r
571 @param ECX MSR_XEON_D_RAPL_POWER_UNIT (0x00000606)\r
572 @param EAX Lower 32-bits of MSR value.\r
573 Described by the type MSR_XEON_D_RAPL_POWER_UNIT_REGISTER.\r
574 @param EDX Upper 32-bits of MSR value.\r
575 Described by the type MSR_XEON_D_RAPL_POWER_UNIT_REGISTER.\r
576\r
577 <b>Example usage</b>\r
578 @code\r
579 MSR_XEON_D_RAPL_POWER_UNIT_REGISTER Msr;\r
580\r
581 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_RAPL_POWER_UNIT);\r
582 @endcode\r
583**/\r
584#define MSR_XEON_D_RAPL_POWER_UNIT 0x00000606\r
585\r
586/**\r
587 MSR information returned for MSR index #MSR_XEON_D_RAPL_POWER_UNIT\r
588**/\r
589typedef union {\r
590 ///\r
591 /// Individual bit fields\r
592 ///\r
593 struct {\r
594 ///\r
595 /// [Bits 3:0] Package. Power Units See Section 14.9.1, "RAPL Interfaces.".\r
596 ///\r
597 UINT32 PowerUnits:4;\r
598 UINT32 Reserved1:4;\r
599 ///\r
600 /// [Bits 12:8] Package. Energy Status Units Energy related information\r
601 /// (in Joules) is based on the multiplier, 1/2^ESU; where ESU is an\r
602 /// unsigned integer represented by bits 12:8. Default value is 0EH (or 61\r
603 /// micro-joules).\r
604 ///\r
605 UINT32 EnergyStatusUnits:5;\r
606 UINT32 Reserved2:3;\r
607 ///\r
608 /// [Bits 19:16] Package. Time Units See Section 14.9.1, "RAPL\r
609 /// Interfaces.".\r
610 ///\r
611 UINT32 TimeUnits:4;\r
612 UINT32 Reserved3:12;\r
613 UINT32 Reserved4:32;\r
614 } Bits;\r
615 ///\r
616 /// All bit fields as a 32-bit value\r
617 ///\r
618 UINT32 Uint32;\r
619 ///\r
620 /// All bit fields as a 64-bit value\r
621 ///\r
622 UINT64 Uint64;\r
623} MSR_XEON_D_RAPL_POWER_UNIT_REGISTER;\r
624\r
625\r
626/**\r
627 Package. DRAM RAPL Power Limit Control (R/W) See Section 14.9.5, "DRAM RAPL\r
628 Domain.".\r
629\r
630 @param ECX MSR_XEON_D_DRAM_POWER_LIMIT (0x00000618)\r
631 @param EAX Lower 32-bits of MSR value.\r
632 @param EDX Upper 32-bits of MSR value.\r
633\r
634 <b>Example usage</b>\r
635 @code\r
636 UINT64 Msr;\r
637\r
638 Msr = AsmReadMsr64 (MSR_XEON_D_DRAM_POWER_LIMIT);\r
639 AsmWriteMsr64 (MSR_XEON_D_DRAM_POWER_LIMIT, Msr);\r
640 @endcode\r
641**/\r
642#define MSR_XEON_D_DRAM_POWER_LIMIT 0x00000618\r
643\r
644\r
645/**\r
646 Package. DRAM Energy Status (R/O) See Section 14.9.5, "DRAM RAPL Domain.".\r
647\r
648 @param ECX MSR_XEON_D_DRAM_ENERGY_STATUS (0x00000619)\r
649 @param EAX Lower 32-bits of MSR value.\r
650 @param EDX Upper 32-bits of MSR value.\r
651\r
652 <b>Example usage</b>\r
653 @code\r
654 UINT64 Msr;\r
655\r
656 Msr = AsmReadMsr64 (MSR_XEON_D_DRAM_ENERGY_STATUS);\r
657 @endcode\r
658**/\r
659#define MSR_XEON_D_DRAM_ENERGY_STATUS 0x00000619\r
660\r
661\r
662/**\r
663 Package. DRAM Performance Throttling Status (R/O) See Section 14.9.5, "DRAM\r
664 RAPL Domain.".\r
665\r
666 @param ECX MSR_XEON_D_DRAM_PERF_STATUS (0x0000061B)\r
667 @param EAX Lower 32-bits of MSR value.\r
668 @param EDX Upper 32-bits of MSR value.\r
669\r
670 <b>Example usage</b>\r
671 @code\r
672 UINT64 Msr;\r
673\r
674 Msr = AsmReadMsr64 (MSR_XEON_D_DRAM_PERF_STATUS);\r
675 @endcode\r
676**/\r
677#define MSR_XEON_D_DRAM_PERF_STATUS 0x0000061B\r
678\r
679\r
680/**\r
681 Package. DRAM RAPL Parameters (R/W) See Section 14.9.5, "DRAM RAPL Domain.".\r
682\r
683 @param ECX MSR_XEON_D_DRAM_POWER_INFO (0x0000061C)\r
684 @param EAX Lower 32-bits of MSR value.\r
685 @param EDX Upper 32-bits of MSR value.\r
686\r
687 <b>Example usage</b>\r
688 @code\r
689 UINT64 Msr;\r
690\r
691 Msr = AsmReadMsr64 (MSR_XEON_D_DRAM_POWER_INFO);\r
692 AsmWriteMsr64 (MSR_XEON_D_DRAM_POWER_INFO, Msr);\r
693 @endcode\r
694**/\r
695#define MSR_XEON_D_DRAM_POWER_INFO 0x0000061C\r
696\r
697\r
698/**\r
699 Package. Indicator of Frequency Clipping in Processor Cores (R/W) (frequency\r
700 refers to processor core frequency).\r
701\r
702 @param ECX MSR_XEON_D_CORE_PERF_LIMIT_REASONS (0x00000690)\r
703 @param EAX Lower 32-bits of MSR value.\r
704 Described by the type MSR_XEON_D_CORE_PERF_LIMIT_REASONS_REGISTER.\r
705 @param EDX Upper 32-bits of MSR value.\r
706 Described by the type MSR_XEON_D_CORE_PERF_LIMIT_REASONS_REGISTER.\r
707\r
708 <b>Example usage</b>\r
709 @code\r
710 MSR_XEON_D_CORE_PERF_LIMIT_REASONS_REGISTER Msr;\r
711\r
712 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_CORE_PERF_LIMIT_REASONS);\r
713 AsmWriteMsr64 (MSR_XEON_D_CORE_PERF_LIMIT_REASONS, Msr.Uint64);\r
714 @endcode\r
715**/\r
716#define MSR_XEON_D_CORE_PERF_LIMIT_REASONS 0x00000690\r
717\r
718/**\r
719 MSR information returned for MSR index #MSR_XEON_D_CORE_PERF_LIMIT_REASONS\r
720**/\r
721typedef union {\r
722 ///\r
723 /// Individual bit fields\r
724 ///\r
725 struct {\r
726 ///\r
727 /// [Bit 0] PROCHOT Status (R0) When set, processor core frequency is\r
728 /// reduced below the operating system request due to assertion of\r
729 /// external PROCHOT.\r
730 ///\r
731 UINT32 PROCHOT_Status:1;\r
732 ///\r
733 /// [Bit 1] Thermal Status (R0) When set, frequency is reduced below the\r
734 /// operating system request due to a thermal event.\r
735 ///\r
736 UINT32 ThermalStatus:1;\r
737 ///\r
738 /// [Bit 2] Power Budget Management Status (R0) When set, frequency is\r
739 /// reduced below the operating system request due to PBM limit.\r
740 ///\r
741 UINT32 PowerBudgetManagementStatus:1;\r
742 ///\r
743 /// [Bit 3] Platform Configuration Services Status (R0) When set,\r
744 /// frequency is reduced below the operating system request due to PCS\r
745 /// limit.\r
746 ///\r
747 UINT32 PlatformConfigurationServicesStatus:1;\r
748 UINT32 Reserved1:1;\r
749 ///\r
750 /// [Bit 5] Autonomous Utilization-Based Frequency Control Status (R0)\r
751 /// When set, frequency is reduced below the operating system request\r
752 /// because the processor has detected that utilization is low.\r
753 ///\r
754 UINT32 AutonomousUtilizationBasedFrequencyControlStatus:1;\r
755 ///\r
756 /// [Bit 6] VR Therm Alert Status (R0) When set, frequency is reduced\r
757 /// below the operating system request due to a thermal alert from the\r
758 /// Voltage Regulator.\r
759 ///\r
760 UINT32 VRThermAlertStatus:1;\r
761 UINT32 Reserved2:1;\r
762 ///\r
763 /// [Bit 8] Electrical Design Point Status (R0) When set, frequency is\r
764 /// reduced below the operating system request due to electrical design\r
765 /// point constraints (e.g. maximum electrical current consumption).\r
766 ///\r
767 UINT32 ElectricalDesignPointStatus:1;\r
768 UINT32 Reserved3:1;\r
769 ///\r
770 /// [Bit 10] Multi-Core Turbo Status (R0) When set, frequency is reduced\r
771 /// below the operating system request due to Multi-Core Turbo limits.\r
772 ///\r
773 UINT32 MultiCoreTurboStatus:1;\r
774 UINT32 Reserved4:2;\r
775 ///\r
776 /// [Bit 13] Core Frequency P1 Status (R0) When set, frequency is reduced\r
777 /// below max non-turbo P1.\r
778 ///\r
779 UINT32 FrequencyP1Status:1;\r
780 ///\r
781 /// [Bit 14] Core Max n-core Turbo Frequency Limiting Status (R0) When\r
782 /// set, frequency is reduced below max n-core turbo frequency.\r
783 ///\r
784 UINT32 TurboFrequencyLimitingStatus:1;\r
785 ///\r
786 /// [Bit 15] Core Frequency Limiting Status (R0) When set, frequency is\r
787 /// reduced below the operating system request.\r
788 ///\r
789 UINT32 FrequencyLimitingStatus:1;\r
790 ///\r
791 /// [Bit 16] PROCHOT Log When set, indicates that the PROCHOT Status bit\r
792 /// has asserted since the log bit was last cleared. This log bit will\r
793 /// remain set until cleared by software writing 0.\r
794 ///\r
795 UINT32 PROCHOT_Log:1;\r
796 ///\r
797 /// [Bit 17] Thermal Log When set, indicates that the Thermal Status bit\r
798 /// has asserted since the log bit was last cleared. This log bit will\r
799 /// remain set until cleared by software writing 0.\r
800 ///\r
801 UINT32 ThermalLog:1;\r
802 ///\r
803 /// [Bit 18] Power Budget Management Log When set, indicates that the PBM\r
804 /// Status bit has asserted since the log bit was last cleared. This log\r
805 /// bit will remain set until cleared by software writing 0.\r
806 ///\r
807 UINT32 PowerBudgetManagementLog:1;\r
808 ///\r
809 /// [Bit 19] Platform Configuration Services Log When set, indicates that\r
810 /// the PCS Status bit has asserted since the log bit was last cleared.\r
811 /// This log bit will remain set until cleared by software writing 0.\r
812 ///\r
813 UINT32 PlatformConfigurationServicesLog:1;\r
814 UINT32 Reserved5:1;\r
815 ///\r
816 /// [Bit 21] Autonomous Utilization-Based Frequency Control Log When set,\r
817 /// indicates that the AUBFC Status bit has asserted since the log bit was\r
818 /// last cleared. This log bit will remain set until cleared by software\r
819 /// writing 0.\r
820 ///\r
821 UINT32 AutonomousUtilizationBasedFrequencyControlLog:1;\r
822 ///\r
823 /// [Bit 22] VR Therm Alert Log When set, indicates that the VR Therm\r
824 /// Alert Status bit has asserted since the log bit was last cleared. This\r
825 /// log bit will remain set until cleared by software writing 0.\r
826 ///\r
827 UINT32 VRThermAlertLog:1;\r
828 UINT32 Reserved6:1;\r
829 ///\r
830 /// [Bit 24] Electrical Design Point Log When set, indicates that the EDP\r
831 /// Status bit has asserted since the log bit was last cleared. This log\r
832 /// bit will remain set until cleared by software writing 0.\r
833 ///\r
834 UINT32 ElectricalDesignPointLog:1;\r
835 UINT32 Reserved7:1;\r
836 ///\r
837 /// [Bit 26] Multi-Core Turbo Log When set, indicates that the Multi-Core\r
838 /// Turbo Status bit has asserted since the log bit was last cleared. This\r
839 /// log bit will remain set until cleared by software writing 0.\r
840 ///\r
841 UINT32 MultiCoreTurboLog:1;\r
842 UINT32 Reserved8:2;\r
843 ///\r
844 /// [Bit 29] Core Frequency P1 Log When set, indicates that the Core\r
845 /// Frequency P1 Status bit has asserted since the log bit was last\r
846 /// cleared. This log bit will remain set until cleared by software\r
847 /// writing 0.\r
848 ///\r
849 UINT32 CoreFrequencyP1Log:1;\r
850 ///\r
851 /// [Bit 30] Core Max n-core Turbo Frequency Limiting Log When set,\r
852 /// indicates that the Core Max n-core Turbo Frequency Limiting Status bit\r
853 /// has asserted since the log bit was last cleared. This log bit will\r
854 /// remain set until cleared by software writing 0.\r
855 ///\r
856 UINT32 TurboFrequencyLimitingLog:1;\r
857 ///\r
858 /// [Bit 31] Core Frequency Limiting Log When set, indicates that the Core\r
859 /// Frequency Limiting Status bit has asserted since the log bit was last\r
860 /// cleared. This log bit will remain set until cleared by software\r
861 /// writing 0.\r
862 ///\r
863 UINT32 CoreFrequencyLimitingLog:1;\r
864 UINT32 Reserved9:32;\r
865 } Bits;\r
866 ///\r
867 /// All bit fields as a 32-bit value\r
868 ///\r
869 UINT32 Uint32;\r
870 ///\r
871 /// All bit fields as a 64-bit value\r
872 ///\r
873 UINT64 Uint64;\r
874} MSR_XEON_D_CORE_PERF_LIMIT_REASONS_REGISTER;\r
875\r
876\r
877/**\r
878 THREAD. Monitoring Event Select Register (R/W) if CPUID.(EAX=07H,\r
879 ECX=0):EBX.PQM[bit 12] = 1.\r
880\r
881 @param ECX MSR_XEON_D_IA32_QM_EVTSEL (0x00000C8D)\r
882 @param EAX Lower 32-bits of MSR value.\r
883 Described by the type MSR_XEON_D_IA32_QM_EVTSEL_REGISTER.\r
884 @param EDX Upper 32-bits of MSR value.\r
885 Described by the type MSR_XEON_D_IA32_QM_EVTSEL_REGISTER.\r
886\r
887 <b>Example usage</b>\r
888 @code\r
889 MSR_XEON_D_IA32_QM_EVTSEL_REGISTER Msr;\r
890\r
891 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_IA32_QM_EVTSEL);\r
892 AsmWriteMsr64 (MSR_XEON_D_IA32_QM_EVTSEL, Msr.Uint64);\r
893 @endcode\r
894**/\r
895#define MSR_XEON_D_IA32_QM_EVTSEL 0x00000C8D\r
896\r
897/**\r
898 MSR information returned for MSR index #MSR_XEON_D_IA32_QM_EVTSEL\r
899**/\r
900typedef union {\r
901 ///\r
902 /// Individual bit fields\r
903 ///\r
904 struct {\r
905 ///\r
906 /// [Bits 7:0] EventID (RW) Event encoding: 0x00: no monitoring 0x01: L3\r
907 /// occupancy monitoring 0x02: Total memory bandwidth monitoring 0x03:\r
908 /// Local memory bandwidth monitoring All other encoding reserved.\r
909 ///\r
910 UINT32 EventID:8;\r
911 UINT32 Reserved1:24;\r
912 ///\r
913 /// [Bits 41:32] RMID (RW).\r
914 ///\r
915 UINT32 RMID:10;\r
916 UINT32 Reserved2:22;\r
917 } Bits;\r
918 ///\r
919 /// All bit fields as a 64-bit value\r
920 ///\r
921 UINT64 Uint64;\r
922} MSR_XEON_D_IA32_QM_EVTSEL_REGISTER;\r
923\r
924\r
925/**\r
926 THREAD. Resource Association Register (R/W).\r
927\r
928 @param ECX MSR_XEON_D_IA32_PQR_ASSOC (0x00000C8F)\r
929 @param EAX Lower 32-bits of MSR value.\r
930 Described by the type MSR_XEON_D_IA32_PQR_ASSOC_REGISTER.\r
931 @param EDX Upper 32-bits of MSR value.\r
932 Described by the type MSR_XEON_D_IA32_PQR_ASSOC_REGISTER.\r
933\r
934 <b>Example usage</b>\r
935 @code\r
936 MSR_XEON_D_IA32_PQR_ASSOC_REGISTER Msr;\r
937\r
938 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_IA32_PQR_ASSOC);\r
939 AsmWriteMsr64 (MSR_XEON_D_IA32_PQR_ASSOC, Msr.Uint64);\r
940 @endcode\r
941**/\r
942#define MSR_XEON_D_IA32_PQR_ASSOC 0x00000C8F\r
943\r
944/**\r
945 MSR information returned for MSR index #MSR_XEON_D_IA32_PQR_ASSOC\r
946**/\r
947typedef union {\r
948 ///\r
949 /// Individual bit fields\r
950 ///\r
951 struct {\r
952 ///\r
953 /// [Bits 9:0] RMID.\r
954 ///\r
955 UINT32 RMID:10;\r
956 UINT32 Reserved1:22;\r
957 ///\r
958 /// [Bits 51:32] COS (R/W).\r
959 ///\r
960 UINT32 COS:20;\r
961 UINT32 Reserved2:12;\r
962 } Bits;\r
963 ///\r
964 /// All bit fields as a 64-bit value\r
965 ///\r
966 UINT64 Uint64;\r
967} MSR_XEON_D_IA32_PQR_ASSOC_REGISTER;\r
968\r
969\r
970/**\r
971 Package. L3 Class Of Service Mask - COS n (R/W) if CPUID.(EAX=10H,\r
972 ECX=1):EDX.COS_MAX[15:0] >= n.\r
973\r
974 @param ECX MSR_XEON_D_IA32_L3_QOS_MASK_n\r
975 @param EAX Lower 32-bits of MSR value.\r
976 Described by the type MSR_XEON_D_IA32_L3_QOS_MASK_REGISTER.\r
977 @param EDX Upper 32-bits of MSR value.\r
978 Described by the type MSR_XEON_D_IA32_L3_QOS_MASK_REGISTER.\r
979\r
980 <b>Example usage</b>\r
981 @code\r
982 MSR_XEON_D_IA32_L3_QOS_MASK_REGISTER Msr;\r
983\r
984 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_IA32_L3_QOS_MASK_0);\r
985 AsmWriteMsr64 (MSR_XEON_D_IA32_L3_QOS_MASK_0, Msr.Uint64);\r
986 @endcode\r
987 @{\r
988**/\r
989#define MSR_XEON_D_IA32_L3_QOS_MASK_0 0x00000C90\r
990#define MSR_XEON_D_IA32_L3_QOS_MASK_1 0x00000C91\r
991#define MSR_XEON_D_IA32_L3_QOS_MASK_2 0x00000C92\r
992#define MSR_XEON_D_IA32_L3_QOS_MASK_3 0x00000C93\r
993#define MSR_XEON_D_IA32_L3_QOS_MASK_4 0x00000C94\r
994#define MSR_XEON_D_IA32_L3_QOS_MASK_5 0x00000C95\r
995#define MSR_XEON_D_IA32_L3_QOS_MASK_6 0x00000C96\r
996#define MSR_XEON_D_IA32_L3_QOS_MASK_7 0x00000C97\r
997#define MSR_XEON_D_IA32_L3_QOS_MASK_8 0x00000C98\r
998#define MSR_XEON_D_IA32_L3_QOS_MASK_9 0x00000C99\r
999#define MSR_XEON_D_IA32_L3_QOS_MASK_10 0x00000C9A\r
1000#define MSR_XEON_D_IA32_L3_QOS_MASK_11 0x00000C9B\r
1001#define MSR_XEON_D_IA32_L3_QOS_MASK_12 0x00000C9C\r
1002#define MSR_XEON_D_IA32_L3_QOS_MASK_13 0x00000C9D\r
1003#define MSR_XEON_D_IA32_L3_QOS_MASK_14 0x00000C9E\r
1004#define MSR_XEON_D_IA32_L3_QOS_MASK_15 0x00000C9F\r
1005/// @}\r
1006\r
1007/**\r
1008 MSR information returned for MSR indexes #MSR_XEON_D_IA32_L3_QOS_MASK_0\r
1009 to #MSR_XEON_D_IA32_L3_QOS_MASK_15.\r
1010**/\r
1011typedef union {\r
1012 ///\r
1013 /// Individual bit fields\r
1014 ///\r
1015 struct {\r
1016 ///\r
1017 /// [Bits 19:0] CBM: Bit vector of available L3 ways for COS 0 enforcement.\r
1018 ///\r
1019 UINT32 CBM:20;\r
1020 UINT32 Reserved2:12;\r
1021 UINT32 Reserved3:32;\r
1022 } Bits;\r
1023 ///\r
1024 /// All bit fields as a 32-bit value\r
1025 ///\r
1026 UINT32 Uint32;\r
1027 ///\r
1028 /// All bit fields as a 64-bit value\r
1029 ///\r
1030 UINT64 Uint64;\r
1031} MSR_XEON_D_IA32_L3_QOS_MASK_REGISTER;\r
1032\r
1033\r
1034/**\r
1035 Package. Config Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,\r
1036 RW if MSR_PLATFORM_INFO.[28] = 1.\r
1037\r
1038 @param ECX MSR_XEON_D_TURBO_RATIO_LIMIT3 (0x000001AC)\r
1039 @param EAX Lower 32-bits of MSR value.\r
1040 Described by the type MSR_XEON_D_TURBO_RATIO_LIMIT3_REGISTER.\r
1041 @param EDX Upper 32-bits of MSR value.\r
1042 Described by the type MSR_XEON_D_TURBO_RATIO_LIMIT3_REGISTER.\r
1043\r
1044 <b>Example usage</b>\r
1045 @code\r
1046 MSR_XEON_D_TURBO_RATIO_LIMIT3_REGISTER Msr;\r
1047\r
1048 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_TURBO_RATIO_LIMIT3);\r
1049 @endcode\r
1050**/\r
1051#define MSR_XEON_D_TURBO_RATIO_LIMIT3 0x000001AC\r
1052\r
1053/**\r
1054 MSR information returned for MSR index #MSR_XEON_D_TURBO_RATIO_LIMIT3\r
1055**/\r
1056typedef union {\r
1057 ///\r
1058 /// Individual bit fields\r
1059 ///\r
1060 struct {\r
1061 UINT32 Reserved1:32;\r
1062 UINT32 Reserved2:31;\r
1063 ///\r
1064 /// [Bit 63] Package. Semaphore for Turbo Ratio Limit Configuration If 1,\r
1065 /// the processor uses override configuration specified in\r
1066 /// MSR_TURBO_RATIO_LIMIT, MSR_TURBO_RATIO_LIMIT1. If 0, the processor\r
1067 /// uses factory-set configuration (Default).\r
1068 ///\r
1069 UINT32 TurboRatioLimitConfigurationSemaphore:1;\r
1070 } Bits;\r
1071 ///\r
1072 /// All bit fields as a 64-bit value\r
1073 ///\r
1074 UINT64 Uint64;\r
1075} MSR_XEON_D_TURBO_RATIO_LIMIT3_REGISTER;\r
1076\r
1077\r
1078/**\r
1079 Package. See Section 15.3.2.1, "IA32_MCi_CTL MSRs." through Section\r
1080 15.3.2.4, "IA32_MCi_MISC MSRs.".\r
1081\r
1082 * Bank MC5 reports MC error from the Intel QPI 0 module.\r
1083 * Bank MC6 reports MC error from the integrated I/O module.\r
1084 * Bank MC7 reports MC error from the home agent HA 0.\r
1085 * Bank MC8 reports MC error from the home agent HA 1.\r
1086 * Banks MC9 through MC16 report MC error from each channel of the integrated\r
1087 memory controllers.\r
1088 * Bank MC17 reports MC error from the following pair of CBo/L3 Slices\r
1089 (if the pair is present): CBo0, CBo3, CBo6, CBo9, CBo12, CBo15.\r
1090 * Bank MC18 reports MC error from the following pair of CBo/L3 Slices\r
1091 (if the pair is present): CBo1, CBo4, CBo7, CBo10, CBo13, CBo16.\r
1092 * Bank MC19 reports MC error from the following pair of CBo/L3 Slices\r
1093 (if the pair is present): CBo2, CBo5, CBo8, CBo11, CBo14, CBo17.\r
1094 * Bank MC20 reports MC error from the Intel QPI 1 module.\r
1095 * Bank MC21 reports MC error from the Intel QPI 2 module.\r
1096\r
1097 @param ECX MSR_XEON_D_MCi_CTL\r
1098 @param EAX Lower 32-bits of MSR value.\r
1099 @param EDX Upper 32-bits of MSR value.\r
1100\r
1101 <b>Example usage</b>\r
1102 @code\r
1103 UINT64 Msr;\r
1104\r
1105 Msr = AsmReadMsr64 (MSR_XEON_D_MC5_CTL);\r
1106 AsmWriteMsr64 (MSR_XEON_D_MC5_CTL, Msr);\r
1107 @endcode\r
1108 @{\r
1109**/\r
1110#define MSR_XEON_D_MC5_CTL 0x00000414\r
1111#define MSR_XEON_D_MC6_CTL 0x00000418\r
1112#define MSR_XEON_D_MC7_CTL 0x0000041C\r
1113#define MSR_XEON_D_MC8_CTL 0x00000420\r
1114#define MSR_XEON_D_MC9_CTL 0x00000424\r
1115#define MSR_XEON_D_MC10_CTL 0x00000428\r
1116#define MSR_XEON_D_MC11_CTL 0x0000042C\r
1117#define MSR_XEON_D_MC12_CTL 0x00000430\r
1118#define MSR_XEON_D_MC13_CTL 0x00000434\r
1119#define MSR_XEON_D_MC14_CTL 0x00000438\r
1120#define MSR_XEON_D_MC15_CTL 0x0000043C\r
1121#define MSR_XEON_D_MC16_CTL 0x00000440\r
1122#define MSR_XEON_D_MC17_CTL 0x00000444\r
1123#define MSR_XEON_D_MC18_CTL 0x00000448\r
1124#define MSR_XEON_D_MC19_CTL 0x0000044C\r
1125#define MSR_XEON_D_MC20_CTL 0x00000450\r
1126#define MSR_XEON_D_MC21_CTL 0x00000454\r
1127/// @}\r
1128\r
1129/**\r
1130 Package. See Section 15.3.2.1, "IA32_MCi_CTL MSRs." through Section\r
1131 15.3.2.4, "IA32_MCi_MISC MSRs.".\r
1132\r
1133 @param ECX MSR_XEON_D_MCi_STATUS\r
1134 @param EAX Lower 32-bits of MSR value.\r
1135 @param EDX Upper 32-bits of MSR value.\r
1136\r
1137 <b>Example usage</b>\r
1138 @code\r
1139 UINT64 Msr;\r
1140\r
1141 Msr = AsmReadMsr64 (MSR_XEON_D_MC6_STATUS);\r
1142 AsmWriteMsr64 (MSR_XEON_D_MC6_STATUS, Msr);\r
1143 @endcode\r
1144 @{\r
1145**/\r
1146#define MSR_XEON_D_MC5_STATUS 0x00000415\r
1147#define MSR_XEON_D_MC6_STATUS 0x00000419\r
1148#define MSR_XEON_D_MC7_STATUS 0x0000041D\r
1149#define MSR_XEON_D_MC8_STATUS 0x00000421\r
1150#define MSR_XEON_D_MC9_STATUS 0x00000425\r
1151#define MSR_XEON_D_MC10_STATUS 0x00000429\r
1152#define MSR_XEON_D_MC11_STATUS 0x0000042D\r
1153#define MSR_XEON_D_MC12_STATUS 0x00000431\r
1154#define MSR_XEON_D_MC13_STATUS 0x00000435\r
1155#define MSR_XEON_D_MC14_STATUS 0x00000439\r
1156#define MSR_XEON_D_MC15_STATUS 0x0000043D\r
1157#define MSR_XEON_D_MC16_STATUS 0x00000441\r
1158#define MSR_XEON_D_MC17_STATUS 0x00000445\r
1159#define MSR_XEON_D_MC18_STATUS 0x00000449\r
1160#define MSR_XEON_D_MC19_STATUS 0x0000044D\r
1161#define MSR_XEON_D_MC20_STATUS 0x00000451\r
1162#define MSR_XEON_D_MC21_STATUS 0x00000455\r
1163/// @}\r
1164\r
1165/**\r
1166 Package. See Section 15.3.2.1, "IA32_MCi_CTL MSRs." through Section\r
1167 15.3.2.4, "IA32_MCi_MISC MSRs.".\r
1168\r
1169 @param ECX MSR_XEON_D_MCi_ADDR\r
1170 @param EAX Lower 32-bits of MSR value.\r
1171 @param EDX Upper 32-bits of MSR value.\r
1172\r
1173 <b>Example usage</b>\r
1174 @code\r
1175 UINT64 Msr;\r
1176\r
1177 Msr = AsmReadMsr64 (MSR_XEON_D_MC6_ADDR);\r
1178 AsmWriteMsr64 (MSR_XEON_D_MC6_ADDR, Msr);\r
1179 @endcode\r
1180 @{\r
1181**/\r
1182#define MSR_XEON_D_MC5_ADDR 0x00000416\r
1183#define MSR_XEON_D_MC6_ADDR 0x0000041A\r
1184#define MSR_XEON_D_MC7_ADDR 0x0000041E\r
1185#define MSR_XEON_D_MC8_ADDR 0x00000422\r
1186#define MSR_XEON_D_MC9_ADDR 0x00000426\r
1187#define MSR_XEON_D_MC10_ADDR 0x0000042A\r
1188#define MSR_XEON_D_MC11_ADDR 0x0000042E\r
1189#define MSR_XEON_D_MC12_ADDR 0x00000432\r
1190#define MSR_XEON_D_MC13_ADDR 0x00000436\r
1191#define MSR_XEON_D_MC14_ADDR 0x0000043A\r
1192#define MSR_XEON_D_MC15_ADDR 0x0000043E\r
1193#define MSR_XEON_D_MC16_ADDR 0x00000442\r
1194#define MSR_XEON_D_MC17_ADDR 0x00000446\r
1195#define MSR_XEON_D_MC18_ADDR 0x0000044A\r
1196#define MSR_XEON_D_MC19_ADDR 0x0000044E\r
1197#define MSR_XEON_D_MC20_ADDR 0x00000452\r
1198#define MSR_XEON_D_MC21_ADDR 0x00000456\r
1199/// @}\r
1200\r
1201\r
1202/**\r
1203 Package. See Section 15.3.2.1, "IA32_MCi_CTL MSRs." through Section\r
1204 15.3.2.4, "IA32_MCi_MISC MSRs.".\r
1205\r
1206 @param ECX MSR_XEON_D_MCi_MISC\r
1207 @param EAX Lower 32-bits of MSR value.\r
1208 @param EDX Upper 32-bits of MSR value.\r
1209\r
1210 <b>Example usage</b>\r
1211 @code\r
1212 UINT64 Msr;\r
1213\r
1214 Msr = AsmReadMsr64 (MSR_XEON_D_MC6_MISC);\r
1215 AsmWriteMsr64 (MSR_XEON_D_MC6_MISC, Msr);\r
1216 @endcode\r
1217 @{\r
1218**/\r
1219#define MSR_XEON_D_MC5_MISC 0x00000417\r
1220#define MSR_XEON_D_MC6_MISC 0x0000041B\r
1221#define MSR_XEON_D_MC7_MISC 0x0000041F\r
1222#define MSR_XEON_D_MC8_MISC 0x00000423\r
1223#define MSR_XEON_D_MC9_MISC 0x00000427\r
1224#define MSR_XEON_D_MC10_MISC 0x0000042B\r
1225#define MSR_XEON_D_MC11_MISC 0x0000042F\r
1226#define MSR_XEON_D_MC12_MISC 0x00000433\r
1227#define MSR_XEON_D_MC13_MISC 0x00000437\r
1228#define MSR_XEON_D_MC14_MISC 0x0000043B\r
1229#define MSR_XEON_D_MC15_MISC 0x0000043F\r
1230#define MSR_XEON_D_MC16_MISC 0x00000443\r
1231#define MSR_XEON_D_MC17_MISC 0x00000447\r
1232#define MSR_XEON_D_MC18_MISC 0x0000044B\r
1233#define MSR_XEON_D_MC19_MISC 0x0000044F\r
1234#define MSR_XEON_D_MC20_MISC 0x00000453\r
1235#define MSR_XEON_D_MC21_MISC 0x00000457\r
1236/// @}\r
1237\r
1238\r
1239/**\r
1240 Package. Note: C-state values are processor specific C-state code names,\r
1241 unrelated to MWAIT extension C-state parameters or ACPI C-States.\r
1242\r
1243 @param ECX MSR_XEON_D_PKG_C8_RESIDENCY (0x00000630)\r
1244 @param EAX Lower 32-bits of MSR value.\r
1245 Described by the type MSR_XEON_D_PKG_C8_RESIDENCY_REGISTER.\r
1246 @param EDX Upper 32-bits of MSR value.\r
1247 Described by the type MSR_XEON_D_PKG_C8_RESIDENCY_REGISTER.\r
1248\r
1249 <b>Example usage</b>\r
1250 @code\r
1251 MSR_XEON_D_PKG_C8_RESIDENCY_REGISTER Msr;\r
1252\r
1253 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_PKG_C8_RESIDENCY);\r
1254 AsmWriteMsr64 (MSR_XEON_D_PKG_C8_RESIDENCY, Msr.Uint64);\r
1255 @endcode\r
1256**/\r
1257#define MSR_XEON_D_PKG_C8_RESIDENCY 0x00000630\r
1258\r
1259/**\r
1260 MSR information returned for MSR index #MSR_XEON_D_PKG_C8_RESIDENCY\r
1261**/\r
1262typedef union {\r
1263 ///\r
1264 /// Individual bit fields\r
1265 ///\r
1266 struct {\r
1267 ///\r
1268 /// [Bits 31:0] Package C8 Residency Counter. (R/O) Value since last reset\r
1269 /// that this package is in processor-specific C8 states. Count at the\r
1270 /// same frequency as the TSC.\r
1271 ///\r
1272 UINT32 C8ResidencyCounter:32;\r
1273 ///\r
1274 /// [Bits 59:32] Package C8 Residency Counter. (R/O) Value since last\r
1275 /// reset that this package is in processor-specific C8 states. Count at\r
1276 /// the same frequency as the TSC.\r
1277 ///\r
1278 UINT32 C8ResidencyCounterHi:28;\r
1279 UINT32 Reserved:4;\r
1280 } Bits;\r
1281 ///\r
1282 /// All bit fields as a 64-bit value\r
1283 ///\r
1284 UINT64 Uint64;\r
1285} MSR_XEON_D_PKG_C8_RESIDENCY_REGISTER;\r
1286\r
1287\r
1288/**\r
1289 Package. Note: C-state values are processor specific C-state code names,\r
1290 unrelated to MWAIT extension C-state parameters or ACPI C-States.\r
1291\r
1292 @param ECX MSR_XEON_D_PKG_C9_RESIDENCY (0x00000631)\r
1293 @param EAX Lower 32-bits of MSR value.\r
1294 Described by the type MSR_XEON_D_PKG_C9_RESIDENCY_REGISTER.\r
1295 @param EDX Upper 32-bits of MSR value.\r
1296 Described by the type MSR_XEON_D_PKG_C9_RESIDENCY_REGISTER.\r
1297\r
1298 <b>Example usage</b>\r
1299 @code\r
1300 MSR_XEON_D_PKG_C9_RESIDENCY_REGISTER Msr;\r
1301\r
1302 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_PKG_C9_RESIDENCY);\r
1303 AsmWriteMsr64 (MSR_XEON_D_PKG_C9_RESIDENCY, Msr.Uint64);\r
1304 @endcode\r
1305**/\r
1306#define MSR_XEON_D_PKG_C9_RESIDENCY 0x00000631\r
1307\r
1308/**\r
1309 MSR information returned for MSR index #MSR_XEON_D_PKG_C9_RESIDENCY\r
1310**/\r
1311typedef union {\r
1312 ///\r
1313 /// Individual bit fields\r
1314 ///\r
1315 struct {\r
1316 ///\r
1317 /// [Bits 31:0] Package C9 Residency Counter. (R/O) Value since last reset\r
1318 /// that this package is in processor-specific C9 states. Count at the\r
1319 /// same frequency as the TSC.\r
1320 ///\r
1321 UINT32 C9ResidencyCounter:32;\r
1322 ///\r
1323 /// [Bits 59:32] Package C9 Residency Counter. (R/O) Value since last\r
1324 /// reset that this package is in processor-specific C9 states. Count at\r
1325 /// the same frequency as the TSC.\r
1326 ///\r
1327 UINT32 C9ResidencyCounterHi:28;\r
1328 UINT32 Reserved:4;\r
1329 } Bits;\r
1330 ///\r
1331 /// All bit fields as a 64-bit value\r
1332 ///\r
1333 UINT64 Uint64;\r
1334} MSR_XEON_D_PKG_C9_RESIDENCY_REGISTER;\r
1335\r
1336\r
1337/**\r
1338 Package. Note: C-state values are processor specific C-state code names,\r
1339 unrelated to MWAIT extension C-state parameters or ACPI C-States.\r
1340\r
1341 @param ECX MSR_XEON_D_PKG_C10_RESIDENCY (0x00000632)\r
1342 @param EAX Lower 32-bits of MSR value.\r
1343 Described by the type MSR_XEON_D_PKG_C10_RESIDENCY_REGISTER.\r
1344 @param EDX Upper 32-bits of MSR value.\r
1345 Described by the type MSR_XEON_D_PKG_C10_RESIDENCY_REGISTER.\r
1346\r
1347 <b>Example usage</b>\r
1348 @code\r
1349 MSR_XEON_D_PKG_C10_RESIDENCY_REGISTER Msr;\r
1350\r
1351 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_PKG_C10_RESIDENCY);\r
1352 AsmWriteMsr64 (MSR_XEON_D_PKG_C10_RESIDENCY, Msr.Uint64);\r
1353 @endcode\r
1354**/\r
1355#define MSR_XEON_D_PKG_C10_RESIDENCY 0x00000632\r
1356\r
1357/**\r
1358 MSR information returned for MSR index #MSR_XEON_D_PKG_C10_RESIDENCY\r
1359**/\r
1360typedef union {\r
1361 ///\r
1362 /// Individual bit fields\r
1363 ///\r
1364 struct {\r
1365 ///\r
1366 /// [Bits 31:0] Package C10 Residency Counter. (R/O) Value since last\r
1367 /// reset that this package is in processor-specific C10 states. Count at\r
1368 /// the same frequency as the TSC.\r
1369 ///\r
1370 UINT32 C10ResidencyCounter:32;\r
1371 ///\r
1372 /// [Bits 59:32] Package C10 Residency Counter. (R/O) Value since last\r
1373 /// reset that this package is in processor-specific C10 states. Count at\r
1374 /// the same frequency as the TSC.\r
1375 ///\r
1376 UINT32 C10ResidencyCounterHi:28;\r
1377 UINT32 Reserved:4;\r
1378 } Bits;\r
1379 ///\r
1380 /// All bit fields as a 64-bit value\r
1381 ///\r
1382 UINT64 Uint64;\r
1383} MSR_XEON_D_PKG_C10_RESIDENCY_REGISTER;\r
1384\r
1385\r
1386/**\r
1387 Package. Cache Allocation Technology Configuration (R/W).\r
1388\r
1389 @param ECX MSR_XEON_D_IA32_L3_QOS_CFG (0x00000C81)\r
1390 @param EAX Lower 32-bits of MSR value.\r
1391 Described by the type MSR_XEON_D_IA32_L3_QOS_CFG_REGISTER.\r
1392 @param EDX Upper 32-bits of MSR value.\r
1393 Described by the type MSR_XEON_D_IA32_L3_QOS_CFG_REGISTER.\r
1394\r
1395 <b>Example usage</b>\r
1396 @code\r
1397 MSR_XEON_D_IA32_L3_QOS_CFG_REGISTER Msr;\r
1398\r
1399 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_IA32_L3_QOS_CFG);\r
1400 AsmWriteMsr64 (MSR_XEON_D_IA32_L3_QOS_CFG, Msr.Uint64);\r
1401 @endcode\r
1402**/\r
1403#define MSR_XEON_D_IA32_L3_QOS_CFG 0x00000C81\r
1404\r
1405/**\r
1406 MSR information returned for MSR index #MSR_XEON_D_IA32_L3_QOS_CFG\r
1407**/\r
1408typedef union {\r
1409 ///\r
1410 /// Individual bit fields\r
1411 ///\r
1412 struct {\r
1413 ///\r
1414 /// [Bit 0] CAT Enable. Set 1 to enable Cache Allocation Technology.\r
1415 ///\r
1416 UINT32 CAT:1;\r
1417 UINT32 Reserved1:31;\r
1418 UINT32 Reserved2:32;\r
1419 } Bits;\r
1420 ///\r
1421 /// All bit fields as a 32-bit value\r
1422 ///\r
1423 UINT32 Uint32;\r
1424 ///\r
1425 /// All bit fields as a 64-bit value\r
1426 ///\r
1427 UINT64 Uint64;\r
1428} MSR_XEON_D_IA32_L3_QOS_CFG_REGISTER;\r
1429\r
1430#endif\r
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