]>
Commit | Line | Data |
---|---|---|
80c4b236 JF |
1 | /** @file\r |
2 | Enhanced Intel SpeedStep feature.\r | |
3 | \r | |
4 | Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>\r | |
0acd8697 | 5 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
80c4b236 JF |
6 | \r |
7 | **/\r | |
8 | \r | |
9 | #include "CpuCommonFeatures.h"\r | |
10 | \r | |
11 | /**\r | |
12 | Detects if Enhanced Intel SpeedStep feature supported on current processor.\r | |
13 | \r | |
14 | @param[in] ProcessorNumber The index of the CPU executing this function.\r | |
15 | @param[in] CpuInfo A pointer to the REGISTER_CPU_FEATURE_INFORMATION\r | |
16 | structure for the CPU executing this function.\r | |
17 | @param[in] ConfigData A pointer to the configuration buffer returned\r | |
18 | by CPU_FEATURE_GET_CONFIG_DATA. NULL if\r | |
19 | CPU_FEATURE_GET_CONFIG_DATA was not provided in\r | |
20 | RegisterCpuFeature().\r | |
21 | \r | |
22 | @retval TRUE Enhanced Intel SpeedStep feature is supported.\r | |
23 | @retval FALSE Enhanced Intel SpeedStep feature is not supported.\r | |
24 | \r | |
25 | @note This service could be called by BSP/APs.\r | |
26 | **/\r | |
27 | BOOLEAN\r | |
28 | EFIAPI\r | |
29 | EistSupport (\r | |
30 | IN UINTN ProcessorNumber,\r | |
31 | IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo,\r | |
32 | IN VOID *ConfigData OPTIONAL\r | |
33 | )\r | |
34 | {\r | |
35 | return (CpuInfo->CpuIdVersionInfoEcx.Bits.EIST == 1);\r | |
36 | }\r | |
37 | \r | |
38 | /**\r | |
39 | Initializes Enhanced Intel SpeedStep feature to specific state.\r | |
40 | \r | |
41 | @param[in] ProcessorNumber The index of the CPU executing this function.\r | |
42 | @param[in] CpuInfo A pointer to the REGISTER_CPU_FEATURE_INFORMATION\r | |
43 | structure for the CPU executing this function.\r | |
44 | @param[in] ConfigData A pointer to the configuration buffer returned\r | |
45 | by CPU_FEATURE_GET_CONFIG_DATA. NULL if\r | |
46 | CPU_FEATURE_GET_CONFIG_DATA was not provided in\r | |
47 | RegisterCpuFeature().\r | |
48 | @param[in] State If TRUE, then the Enhanced Intel SpeedStep feature\r | |
49 | must be enabled.\r | |
50 | If FALSE, then the Enhanced Intel SpeedStep feature\r | |
51 | must be disabled.\r | |
52 | \r | |
53 | @retval RETURN_SUCCESS Enhanced Intel SpeedStep feature is initialized.\r | |
54 | \r | |
55 | @note This service could be called by BSP only.\r | |
56 | **/\r | |
57 | RETURN_STATUS\r | |
58 | EFIAPI\r | |
59 | EistInitialize (\r | |
60 | IN UINTN ProcessorNumber,\r | |
61 | IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo,\r | |
62 | IN VOID *ConfigData, OPTIONAL\r | |
63 | IN BOOLEAN State\r | |
64 | )\r | |
65 | {\r | |
d28daadd ED |
66 | //\r |
67 | // The scope of the MSR_IA32_MISC_ENABLE is core for below processor type, only program\r | |
68 | // MSR_IA32_MISC_ENABLE for thread 0 in each core.\r | |
69 | //\r | |
70 | if (IS_ATOM_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||\r | |
71 | IS_CORE_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||\r | |
72 | IS_CORE2_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel)) {\r | |
73 | if (CpuInfo->ProcessorInfo.Location.Thread != 0) {\r | |
74 | return RETURN_SUCCESS;\r | |
75 | }\r | |
76 | }\r | |
77 | \r | |
80c4b236 JF |
78 | CPU_REGISTER_TABLE_WRITE_FIELD (\r |
79 | ProcessorNumber,\r | |
80 | Msr,\r | |
81 | MSR_IA32_MISC_ENABLE,\r | |
82 | MSR_IA32_MISC_ENABLE_REGISTER,\r | |
83 | Bits.EIST,\r | |
84 | (State) ? 1 : 0\r | |
85 | );\r | |
86 | return RETURN_SUCCESS;\r | |
87 | }\r |