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1 | /** @file\r |
2 | Protected Processor Inventory Number(PPIN) feature.\r | |
3 | \r | |
7367cc6c | 4 | Copyright (c) 2017 - 2018, Intel Corporation. All rights reserved.<BR>\r |
0acd8697 | 5 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
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6 | \r |
7 | **/\r | |
8 | \r | |
9 | #include "CpuCommonFeatures.h"\r | |
10 | \r | |
11 | /**\r | |
7367cc6c | 12 | Detects if Protected Processor Inventory Number feature supported on current\r |
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13 | processor.\r |
14 | \r | |
15 | @param[in] ProcessorNumber The index of the CPU executing this function.\r | |
16 | @param[in] CpuInfo A pointer to the REGISTER_CPU_FEATURE_INFORMATION\r | |
17 | structure for the CPU executing this function.\r | |
18 | @param[in] ConfigData A pointer to the configuration buffer returned\r | |
19 | by CPU_FEATURE_GET_CONFIG_DATA. NULL if\r | |
20 | CPU_FEATURE_GET_CONFIG_DATA was not provided in\r | |
21 | RegisterCpuFeature().\r | |
22 | \r | |
91ec57c4 MH |
23 | @retval TRUE Protected Processor Inventory Number feature is supported.\r |
24 | @retval FALSE Protected Processor Inventory Number feature is not supported.\r | |
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25 | \r |
26 | @note This service could be called by BSP/APs.\r | |
27 | **/\r | |
28 | BOOLEAN\r | |
29 | EFIAPI\r | |
30 | PpinSupport (\r | |
31 | IN UINTN ProcessorNumber,\r | |
32 | IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo,\r | |
33 | IN VOID *ConfigData OPTIONAL\r | |
34 | )\r | |
35 | {\r | |
36 | MSR_IVY_BRIDGE_PLATFORM_INFO_1_REGISTER PlatformInfo;\r | |
37 | \r | |
7367cc6c | 38 | if ((CpuInfo->DisplayFamily == 0x06) &&\r |
ee1d736a ED |
39 | ((CpuInfo->DisplayModel == 0x3E) || // Xeon E5 V2\r |
40 | (CpuInfo->DisplayModel == 0x56) || // Xeon Processor D Product\r | |
41 | (CpuInfo->DisplayModel == 0x4F) || // Xeon E5 v4, E7 v4\r | |
42 | (CpuInfo->DisplayModel == 0x55) || // Xeon Processor Scalable\r | |
43 | (CpuInfo->DisplayModel == 0x57) || // Xeon Phi processor 3200, 5200, 7200 series.\r | |
7367cc6c | 44 | (CpuInfo->DisplayModel == 0x85) // Future Xeon phi processor\r |
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45 | )) {\r |
46 | //\r | |
47 | // Check whether platform support this feature.\r | |
48 | //\r | |
49 | PlatformInfo.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_PLATFORM_INFO_1);\r | |
50 | return (PlatformInfo.Bits.PPIN_CAP != 0);\r | |
51 | }\r | |
52 | \r | |
53 | return FALSE;\r | |
54 | }\r | |
55 | \r | |
56 | /**\r | |
57 | Initializes Protected Processor Inventory Number feature to specific state.\r | |
58 | \r | |
59 | @param[in] ProcessorNumber The index of the CPU executing this function.\r | |
60 | @param[in] CpuInfo A pointer to the REGISTER_CPU_FEATURE_INFORMATION\r | |
61 | structure for the CPU executing this function.\r | |
62 | @param[in] ConfigData A pointer to the configuration buffer returned\r | |
63 | by CPU_FEATURE_GET_CONFIG_DATA. NULL if\r | |
64 | CPU_FEATURE_GET_CONFIG_DATA was not provided in\r | |
65 | RegisterCpuFeature().\r | |
7367cc6c | 66 | @param[in] State If TRUE, then the Protected Processor Inventory\r |
ee1d736a | 67 | Number feature must be enabled.\r |
7367cc6c | 68 | If FALSE, then the Protected Processor Inventory\r |
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69 | Number feature must be disabled.\r |
70 | \r | |
7367cc6c | 71 | @retval RETURN_SUCCESS Protected Processor Inventory Number feature is\r |
ee1d736a | 72 | initialized.\r |
7367cc6c | 73 | @retval RETURN_DEVICE_ERROR Device can't change state because it has been\r |
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74 | locked.\r |
75 | \r | |
76 | **/\r | |
77 | RETURN_STATUS\r | |
78 | EFIAPI\r | |
79 | PpinInitialize (\r | |
80 | IN UINTN ProcessorNumber,\r | |
81 | IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo,\r | |
82 | IN VOID *ConfigData, OPTIONAL\r | |
83 | IN BOOLEAN State\r | |
84 | )\r | |
85 | {\r | |
86 | MSR_IVY_BRIDGE_PPIN_CTL_REGISTER MsrPpinCtrl;\r | |
87 | \r | |
88 | //\r | |
89 | // Check whether device already lock this register.\r | |
90 | // If already locked, just base on the request state and\r | |
91 | // the current state to return the status.\r | |
92 | //\r | |
93 | MsrPpinCtrl.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_PPIN_CTL);\r | |
94 | if (MsrPpinCtrl.Bits.LockOut != 0) {\r | |
95 | return MsrPpinCtrl.Bits.Enable_PPIN == State ? RETURN_SUCCESS : RETURN_DEVICE_ERROR;\r | |
96 | }\r | |
97 | \r | |
d28daadd ED |
98 | //\r |
99 | // Support function already check the processor which support PPIN feature, so this function not need\r | |
100 | // to check the processor again.\r | |
101 | //\r | |
102 | // The scope of the MSR_IVY_BRIDGE_PPIN_CTL is package level, only program MSR_IVY_BRIDGE_PPIN_CTL for\r | |
103 | // thread 0 core 0 in each package.\r | |
104 | //\r | |
105 | if ((CpuInfo->ProcessorInfo.Location.Thread != 0) || (CpuInfo->ProcessorInfo.Location.Core != 0)) {\r | |
106 | return RETURN_SUCCESS;\r | |
107 | }\r | |
108 | \r | |
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109 | CPU_REGISTER_TABLE_WRITE_FIELD (\r |
110 | ProcessorNumber,\r | |
111 | Msr,\r | |
112 | MSR_IVY_BRIDGE_PPIN_CTL,\r | |
113 | MSR_IVY_BRIDGE_PPIN_CTL_REGISTER,\r | |
114 | Bits.Enable_PPIN,\r | |
115 | (State) ? 1 : 0\r | |
116 | );\r | |
117 | \r | |
118 | return RETURN_SUCCESS;\r | |
119 | }\r |