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1 | /** @file\r |
2 | Implementation of loading microcode on processors.\r | |
3 | \r | |
4 | Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR>\r | |
5 | This program and the accompanying materials\r | |
6 | are licensed and made available under the terms and conditions of the BSD License\r | |
7 | which accompanies this distribution. The full text of the license may be found at\r | |
8 | http://opensource.org/licenses/bsd-license.php\r | |
9 | \r | |
10 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
11 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
12 | \r | |
13 | **/\r | |
14 | \r | |
15 | #include "MpLib.h"\r | |
16 | \r | |
17 | /**\r | |
18 | Get microcode update signature of currently loaded microcode update.\r | |
19 | \r | |
20 | @return Microcode signature.\r | |
21 | **/\r | |
22 | UINT32\r | |
23 | GetCurrentMicrocodeSignature (\r | |
24 | VOID\r | |
25 | )\r | |
26 | {\r | |
27 | MSR_IA32_BIOS_SIGN_ID_REGISTER BiosSignIdMsr;\r | |
28 | \r | |
29 | AsmWriteMsr64 (MSR_IA32_BIOS_SIGN_ID, 0);\r | |
30 | AsmCpuid (CPUID_VERSION_INFO, NULL, NULL, NULL, NULL);\r | |
31 | BiosSignIdMsr.Uint64 = AsmReadMsr64 (MSR_IA32_BIOS_SIGN_ID);\r | |
32 | return BiosSignIdMsr.Bits.MicrocodeUpdateSignature;\r | |
33 | }\r | |
34 | \r | |
35 | /**\r | |
36 | Detect whether specified processor can find matching microcode patch and load it.\r | |
37 | \r | |
b31c1ad1 | 38 | @param[in] CpuMpData The pointer to CPU MP Data structure.\r |
94f63c76 JF |
39 | **/\r |
40 | VOID\r | |
41 | MicrocodeDetect (\r | |
42 | IN CPU_MP_DATA *CpuMpData\r | |
43 | )\r | |
44 | {\r | |
45 | UINT64 MicrocodePatchAddress;\r | |
46 | UINT64 MicrocodePatchRegionSize;\r | |
47 | UINT32 ExtendedTableLength;\r | |
48 | UINT32 ExtendedTableCount;\r | |
49 | CPU_MICROCODE_EXTENDED_TABLE *ExtendedTable;\r | |
50 | CPU_MICROCODE_EXTENDED_TABLE_HEADER *ExtendedTableHeader;\r | |
51 | CPU_MICROCODE_HEADER *MicrocodeEntryPoint;\r | |
52 | UINTN MicrocodeEnd;\r | |
53 | UINTN Index;\r | |
54 | UINT8 PlatformId;\r | |
55 | CPUID_VERSION_INFO_EAX Eax;\r | |
56 | UINT32 CurrentRevision;\r | |
57 | UINT32 LatestRevision;\r | |
58 | UINTN TotalSize;\r | |
59 | UINT32 CheckSum32;\r | |
60 | BOOLEAN CorrectMicrocode;\r | |
61 | VOID *MicrocodeData;\r | |
62 | MSR_IA32_PLATFORM_ID_REGISTER PlatformIdMsr;\r | |
63 | \r | |
64 | MicrocodePatchAddress = PcdGet64 (PcdCpuMicrocodePatchAddress);\r | |
65 | MicrocodePatchRegionSize = PcdGet64 (PcdCpuMicrocodePatchRegionSize);\r | |
66 | if (MicrocodePatchRegionSize == 0) {\r | |
67 | //\r | |
68 | // There is no microcode patches\r | |
69 | //\r | |
70 | return;\r | |
71 | }\r | |
72 | \r | |
73 | CurrentRevision = GetCurrentMicrocodeSignature ();\r | |
74 | if (CurrentRevision != 0) {\r | |
75 | //\r | |
76 | // Skip loading microcode if it has been loaded successfully\r | |
77 | //\r | |
78 | return;\r | |
79 | }\r | |
80 | \r | |
81 | ExtendedTableLength = 0;\r | |
82 | //\r | |
83 | // Here data of CPUID leafs have not been collected into context buffer, so\r | |
84 | // GetProcessorCpuid() cannot be used here to retrieve sCPUID data.\r | |
85 | //\r | |
86 | AsmCpuid (CPUID_VERSION_INFO, &Eax.Uint32, NULL, NULL, NULL);\r | |
87 | \r | |
88 | //\r | |
89 | // The index of platform information resides in bits 50:52 of MSR IA32_PLATFORM_ID\r | |
90 | //\r | |
91 | PlatformIdMsr.Uint64 = AsmReadMsr64 (MSR_IA32_PLATFORM_ID);\r | |
92 | PlatformId = (UINT8) PlatformIdMsr.Bits.PlatformId;\r | |
93 | \r | |
94 | LatestRevision = 0;\r | |
8cce3c9a | 95 | MicrocodeData = NULL;\r |
94f63c76 JF |
96 | MicrocodeEnd = (UINTN) (MicrocodePatchAddress + MicrocodePatchRegionSize);\r |
97 | MicrocodeEntryPoint = (CPU_MICROCODE_HEADER *) (UINTN) MicrocodePatchAddress;\r | |
98 | do {\r | |
99 | //\r | |
100 | // Check if the microcode is for the Cpu and the version is newer\r | |
101 | // and the update can be processed on the platform\r | |
102 | //\r | |
103 | CorrectMicrocode = FALSE;\r | |
104 | if (MicrocodeEntryPoint->HeaderVersion == 0x1) {\r | |
105 | //\r | |
106 | // It is the microcode header. It is not the padding data between microcode patches\r | |
107 | // because the padding data should not include 0x00000001 and it should be the repeated\r | |
108 | // byte format (like 0xXYXYXYXY....).\r | |
109 | //\r | |
110 | if (MicrocodeEntryPoint->ProcessorSignature.Uint32 == Eax.Uint32 &&\r | |
111 | MicrocodeEntryPoint->UpdateRevision > LatestRevision &&\r | |
112 | (MicrocodeEntryPoint->ProcessorFlags & (1 << PlatformId))\r | |
113 | ) {\r | |
114 | if (MicrocodeEntryPoint->DataSize == 0) {\r | |
115 | CheckSum32 = CalculateSum32 ((UINT32 *) MicrocodeEntryPoint, 2048);\r | |
116 | } else {\r | |
117 | CheckSum32 = CalculateSum32 (\r | |
118 | (UINT32 *) MicrocodeEntryPoint,\r | |
119 | MicrocodeEntryPoint->DataSize + sizeof (CPU_MICROCODE_HEADER)\r | |
120 | );\r | |
121 | }\r | |
122 | if (CheckSum32 == 0) {\r | |
123 | CorrectMicrocode = TRUE;\r | |
124 | }\r | |
125 | } else if ((MicrocodeEntryPoint->DataSize != 0) &&\r | |
126 | (MicrocodeEntryPoint->UpdateRevision > LatestRevision)) {\r | |
127 | ExtendedTableLength = MicrocodeEntryPoint->TotalSize - (MicrocodeEntryPoint->DataSize +\r | |
128 | sizeof (CPU_MICROCODE_HEADER));\r | |
129 | if (ExtendedTableLength != 0) {\r | |
130 | //\r | |
131 | // Extended Table exist, check if the CPU in support list\r | |
132 | //\r | |
133 | ExtendedTableHeader = (CPU_MICROCODE_EXTENDED_TABLE_HEADER *) ((UINT8 *) (MicrocodeEntryPoint)\r | |
134 | + MicrocodeEntryPoint->DataSize + sizeof (CPU_MICROCODE_HEADER));\r | |
135 | //\r | |
136 | // Calculate Extended Checksum\r | |
137 | //\r | |
138 | if ((ExtendedTableLength % 4) == 0) {\r | |
139 | CheckSum32 = CalculateSum32 ((UINT32 *) ExtendedTableHeader, ExtendedTableLength);\r | |
140 | if (CheckSum32 == 0) {\r | |
141 | //\r | |
142 | // Checksum correct\r | |
143 | //\r | |
144 | ExtendedTableCount = ExtendedTableHeader->ExtendedSignatureCount;\r | |
145 | ExtendedTable = (CPU_MICROCODE_EXTENDED_TABLE *) (ExtendedTableHeader + 1);\r | |
146 | for (Index = 0; Index < ExtendedTableCount; Index ++) {\r | |
147 | CheckSum32 = CalculateSum32 ((UINT32 *) ExtendedTable, sizeof(CPU_MICROCODE_EXTENDED_TABLE));\r | |
148 | if (CheckSum32 == 0) {\r | |
149 | //\r | |
150 | // Verify Header\r | |
151 | //\r | |
152 | if ((ExtendedTable->ProcessorSignature.Uint32 == Eax.Uint32) &&\r | |
153 | (ExtendedTable->ProcessorFlag & (1 << PlatformId)) ) {\r | |
154 | //\r | |
155 | // Find one\r | |
156 | //\r | |
157 | CorrectMicrocode = TRUE;\r | |
158 | break;\r | |
159 | }\r | |
160 | }\r | |
161 | ExtendedTable ++;\r | |
162 | }\r | |
163 | }\r | |
164 | }\r | |
165 | }\r | |
166 | }\r | |
167 | } else {\r | |
168 | //\r | |
169 | // It is the padding data between the microcode patches for microcode patches alignment.\r | |
170 | // Because the microcode patch is the multiple of 1-KByte, the padding data should not\r | |
171 | // exist if the microcode patch alignment value is not larger than 1-KByte. So, the microcode\r | |
172 | // alignment value should be larger than 1-KByte. We could skip SIZE_1KB padding data to\r | |
173 | // find the next possible microcode patch header.\r | |
174 | //\r | |
175 | MicrocodeEntryPoint = (CPU_MICROCODE_HEADER *) (((UINTN) MicrocodeEntryPoint) + SIZE_1KB);\r | |
176 | continue;\r | |
177 | }\r | |
178 | //\r | |
179 | // Get the next patch.\r | |
180 | //\r | |
181 | if (MicrocodeEntryPoint->DataSize == 0) {\r | |
182 | TotalSize = 2048;\r | |
183 | } else {\r | |
184 | TotalSize = MicrocodeEntryPoint->TotalSize;\r | |
185 | }\r | |
186 | \r | |
187 | if (CorrectMicrocode) {\r | |
188 | LatestRevision = MicrocodeEntryPoint->UpdateRevision;\r | |
189 | MicrocodeData = (VOID *) ((UINTN) MicrocodeEntryPoint + sizeof (CPU_MICROCODE_HEADER));\r | |
190 | }\r | |
191 | \r | |
192 | MicrocodeEntryPoint = (CPU_MICROCODE_HEADER *) (((UINTN) MicrocodeEntryPoint) + TotalSize);\r | |
193 | } while (((UINTN) MicrocodeEntryPoint < MicrocodeEnd));\r | |
194 | \r | |
195 | if (LatestRevision > CurrentRevision) {\r | |
196 | //\r | |
197 | // BIOS only authenticate updates that contain a numerically larger revision\r | |
198 | // than the currently loaded revision, where Current Signature < New Update\r | |
199 | // Revision. A processor with no loaded update is considered to have a\r | |
200 | // revision equal to zero.\r | |
201 | //\r | |
8cce3c9a | 202 | ASSERT (MicrocodeData != NULL);\r |
94f63c76 JF |
203 | AsmWriteMsr64 (\r |
204 | MSR_IA32_BIOS_UPDT_TRIG,\r | |
205 | (UINT64) (UINTN) MicrocodeData\r | |
206 | );\r | |
207 | //\r | |
208 | // Get and check new microcode signature\r | |
209 | //\r | |
210 | CurrentRevision = GetCurrentMicrocodeSignature ();\r | |
211 | if (CurrentRevision != LatestRevision) {\r | |
212 | AcquireSpinLock(&CpuMpData->MpLock);\r | |
213 | DEBUG ((EFI_D_ERROR, "Updated microcode signature [0x%08x] does not match \\r | |
214 | loaded microcode signature [0x%08x]\n", CurrentRevision, LatestRevision));\r | |
215 | ReleaseSpinLock(&CpuMpData->MpLock);\r | |
216 | }\r | |
217 | }\r | |
218 | }\r |