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7947da3c MK |
1 | ;------------------------------------------------------------------------------ ;\r |
2 | ; Copyright (c) 2009 - 2015, Intel Corporation. All rights reserved.<BR>\r | |
3 | ; This program and the accompanying materials\r | |
4 | ; are licensed and made available under the terms and conditions of the BSD License\r | |
5 | ; which accompanies this distribution. The full text of the license may be found at\r | |
6 | ; http://opensource.org/licenses/bsd-license.php.\r | |
7 | ;\r | |
8 | ; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
9 | ; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
10 | ;\r | |
11 | ; Module Name:\r | |
12 | ;\r | |
13 | ; SmiEntry.asm\r | |
14 | ;\r | |
15 | ; Abstract:\r | |
16 | ;\r | |
17 | ; Code template of the SMI handler for a particular processor\r | |
18 | ;\r | |
19 | ;-------------------------------------------------------------------------------\r | |
20 | \r | |
21 | .686p\r | |
22 | .model flat,C\r | |
23 | .xmm\r | |
24 | \r | |
25 | DSC_OFFSET EQU 0fb00h\r | |
26 | DSC_GDTPTR EQU 30h\r | |
27 | DSC_GDTSIZ EQU 38h\r | |
28 | DSC_CS EQU 14\r | |
29 | DSC_DS EQU 16\r | |
30 | DSC_SS EQU 18\r | |
31 | DSC_OTHERSEG EQU 20\r | |
32 | \r | |
33 | PROTECT_MODE_CS EQU 08h\r | |
34 | PROTECT_MODE_DS EQU 20h\r | |
35 | TSS_SEGMENT EQU 40h\r | |
36 | \r | |
f45f2d4a JY |
37 | SmiRendezvous PROTO C\r |
38 | CpuSmmDebugEntry PROTO C\r | |
39 | CpuSmmDebugExit PROTO C\r | |
7947da3c MK |
40 | \r |
41 | EXTERNDEF gcSmiHandlerTemplate:BYTE\r | |
42 | EXTERNDEF gcSmiHandlerSize:WORD\r | |
43 | EXTERNDEF gSmiCr3:DWORD\r | |
44 | EXTERNDEF gSmiStack:DWORD\r | |
45 | EXTERNDEF gSmbase:DWORD\r | |
7947da3c MK |
46 | EXTERNDEF FeaturePcdGet (PcdCpuSmmStackGuard):BYTE\r |
47 | EXTERNDEF gSmiHandlerIdtr:FWORD\r | |
48 | \r | |
49 | .code\r | |
50 | \r | |
51 | gcSmiHandlerTemplate LABEL BYTE\r | |
52 | \r | |
53 | _SmiEntryPoint:\r | |
54 | DB 0bbh ; mov bx, imm16\r | |
55 | DW offset _GdtDesc - _SmiEntryPoint + 8000h\r | |
56 | DB 2eh, 0a1h ; mov ax, cs:[offset16]\r | |
57 | DW DSC_OFFSET + DSC_GDTSIZ\r | |
58 | dec eax\r | |
59 | mov cs:[edi], eax ; mov cs:[bx], ax\r | |
60 | DB 66h, 2eh, 0a1h ; mov eax, cs:[offset16]\r | |
61 | DW DSC_OFFSET + DSC_GDTPTR\r | |
62 | mov cs:[edi + 2], ax ; mov cs:[bx + 2], eax\r | |
63 | mov bp, ax ; ebp = GDT base\r | |
64 | DB 66h\r | |
65 | lgdt fword ptr cs:[edi] ; lgdt fword ptr cs:[bx]\r | |
66 | ; Patch ProtectedMode Segment\r | |
67 | DB 0b8h ; mov ax, imm16\r | |
68 | DW PROTECT_MODE_CS ; set AX for segment directly\r | |
69 | mov cs:[edi - 2], eax ; mov cs:[bx - 2], ax\r | |
70 | ; Patch ProtectedMode entry\r | |
71 | DB 66h, 0bfh ; mov edi, SMBASE\r | |
72 | gSmbase DD ?\r | |
73 | DB 67h\r | |
74 | lea ax, [edi + (@32bit - _SmiEntryPoint) + 8000h]\r | |
75 | mov cs:[edi - 6], ax ; mov cs:[bx - 6], eax\r | |
76 | mov ebx, cr0\r | |
77 | DB 66h\r | |
78 | and ebx, 9ffafff3h\r | |
79 | DB 66h\r | |
80 | or ebx, 23h\r | |
81 | mov cr0, ebx\r | |
82 | DB 66h, 0eah\r | |
83 | DD ?\r | |
84 | DW ?\r | |
85 | _GdtDesc FWORD ?\r | |
86 | \r | |
87 | @32bit:\r | |
88 | mov ax, PROTECT_MODE_DS\r | |
89 | mov ds, ax\r | |
90 | mov es, ax\r | |
91 | mov fs, ax\r | |
92 | mov gs, ax\r | |
93 | mov ss, ax\r | |
94 | DB 0bch ; mov esp, imm32\r | |
95 | gSmiStack DD ?\r | |
96 | mov eax, offset gSmiHandlerIdtr\r | |
97 | lidt fword ptr [eax]\r | |
98 | jmp ProtFlatMode\r | |
99 | \r | |
100 | ProtFlatMode:\r | |
101 | DB 0b8h ; mov eax, imm32\r | |
102 | gSmiCr3 DD ?\r | |
103 | mov cr3, eax\r | |
104 | ;\r | |
105 | ; Need to test for CR4 specific bit support\r | |
106 | ;\r | |
107 | mov eax, 1\r | |
108 | cpuid ; use CPUID to determine if specific CR4 bits are supported\r | |
109 | xor eax, eax ; Clear EAX\r | |
110 | test edx, BIT2 ; Check for DE capabilities\r | |
111 | jz @f\r | |
112 | or eax, BIT3\r | |
113 | @@:\r | |
114 | test edx, BIT6 ; Check for PAE capabilities\r | |
115 | jz @f\r | |
116 | or eax, BIT5\r | |
117 | @@:\r | |
118 | test edx, BIT7 ; Check for MCE capabilities\r | |
119 | jz @f\r | |
120 | or eax, BIT6\r | |
121 | @@:\r | |
122 | test edx, BIT24 ; Check for FXSR capabilities\r | |
123 | jz @f\r | |
124 | or eax, BIT9\r | |
125 | @@:\r | |
126 | test edx, BIT25 ; Check for SSE capabilities\r | |
127 | jz @f\r | |
128 | or eax, BIT10\r | |
129 | @@: ; as cr4.PGE is not set here, refresh cr3\r | |
130 | mov cr4, eax ; in PreModifyMtrrs() to flush TLB.\r | |
131 | mov ebx, cr0\r | |
53ba3fb8 | 132 | or ebx, 080010000h ; enable paging + WP\r |
7947da3c MK |
133 | mov cr0, ebx\r |
134 | lea ebx, [edi + DSC_OFFSET]\r | |
135 | mov ax, [ebx + DSC_DS]\r | |
136 | mov ds, eax\r | |
137 | mov ax, [ebx + DSC_OTHERSEG]\r | |
138 | mov es, eax\r | |
139 | mov fs, eax\r | |
140 | mov gs, eax\r | |
141 | mov ax, [ebx + DSC_SS]\r | |
142 | mov ss, eax\r | |
143 | \r | |
144 | cmp FeaturePcdGet (PcdCpuSmmStackGuard), 0\r | |
145 | jz @F\r | |
146 | \r | |
147 | ; Load TSS\r | |
148 | mov byte ptr [ebp + TSS_SEGMENT + 5], 89h ; clear busy flag\r | |
149 | mov eax, TSS_SEGMENT\r | |
150 | ltr ax\r | |
151 | @@:\r | |
152 | ; jmp _SmiHandler ; instruction is not needed\r | |
153 | \r | |
154 | _SmiHandler PROC\r | |
f45f2d4a JY |
155 | mov ebx, [esp] ; CPU Index\r |
156 | \r | |
157 | push ebx\r | |
158 | mov eax, CpuSmmDebugEntry\r | |
7947da3c MK |
159 | call eax\r |
160 | pop ecx\r | |
161 | \r | |
f45f2d4a JY |
162 | push ebx\r |
163 | mov eax, SmiRendezvous\r | |
164 | call eax\r | |
165 | pop ecx\r | |
166 | \r | |
167 | push ebx\r | |
168 | mov eax, CpuSmmDebugExit\r | |
169 | call eax\r | |
170 | pop ecx\r | |
7947da3c | 171 | \r |
7947da3c MK |
172 | rsm\r |
173 | _SmiHandler ENDP\r | |
174 | \r | |
175 | gcSmiHandlerSize DW $ - _SmiEntryPoint\r | |
176 | \r | |
177 | END\r |