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fe5f1949 JY |
1 | /** @file\r |
2 | SMM CPU misc functions for Ia32 arch specific.\r | |
3 | \r | |
4a0f88dd | 4 | Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR>\r |
fe5f1949 JY |
5 | This program and the accompanying materials\r |
6 | are licensed and made available under the terms and conditions of the BSD License\r | |
7 | which accompanies this distribution. The full text of the license may be found at\r | |
8 | http://opensource.org/licenses/bsd-license.php\r | |
9 | \r | |
10 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
11 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
12 | \r | |
13 | **/\r | |
14 | \r | |
15 | #include "PiSmmCpuDxeSmm.h"\r | |
16 | \r | |
717fb604 JY |
17 | extern UINT64 gTaskGateDescriptor;\r |
18 | \r | |
19 | EFI_PHYSICAL_ADDRESS mGdtBuffer;\r | |
20 | UINTN mGdtBufferSize;\r | |
21 | \r | |
22 | /**\r | |
23 | Initialize IDT for SMM Stack Guard.\r | |
24 | \r | |
25 | **/\r | |
26 | VOID\r | |
27 | EFIAPI\r | |
28 | InitializeIDTSmmStackGuard (\r | |
29 | VOID\r | |
30 | )\r | |
31 | {\r | |
32 | IA32_IDT_GATE_DESCRIPTOR *IdtGate;\r | |
33 | \r | |
34 | //\r | |
35 | // If SMM Stack Guard feature is enabled, the Page Fault Exception entry in IDT\r | |
36 | // is a Task Gate Descriptor so that when a Page Fault Exception occurs,\r | |
37 | // the processors can use a known good stack in case stack is ran out.\r | |
38 | //\r | |
39 | IdtGate = (IA32_IDT_GATE_DESCRIPTOR *)gcSmiIdtr.Base;\r | |
40 | IdtGate += EXCEPT_IA32_PAGE_FAULT;\r | |
41 | IdtGate->Uint64 = gTaskGateDescriptor;\r | |
42 | }\r | |
43 | \r | |
fe5f1949 JY |
44 | /**\r |
45 | Initialize Gdt for all processors.\r | |
46 | \r | |
47 | @param[in] Cr3 CR3 value.\r | |
48 | @param[out] GdtStepSize The step size for GDT table.\r | |
49 | \r | |
50 | @return GdtBase for processor 0.\r | |
51 | GdtBase for processor X is: GdtBase + (GdtStepSize * X)\r | |
52 | **/\r | |
53 | VOID *\r | |
54 | InitGdt (\r | |
55 | IN UINTN Cr3,\r | |
56 | OUT UINTN *GdtStepSize\r | |
57 | )\r | |
58 | {\r | |
59 | UINTN Index;\r | |
60 | IA32_SEGMENT_DESCRIPTOR *GdtDescriptor;\r | |
61 | UINTN TssBase;\r | |
62 | UINTN GdtTssTableSize;\r | |
63 | UINT8 *GdtTssTables;\r | |
64 | UINTN GdtTableStepSize;\r | |
65 | \r | |
66 | if (FeaturePcdGet (PcdCpuSmmStackGuard)) {\r | |
67 | //\r | |
68 | // For IA32 SMM, if SMM Stack Guard feature is enabled, we use 2 TSS.\r | |
69 | // in this case, we allocate separate GDT/TSS for each CPUs to avoid TSS load contention\r | |
70 | // on each SMI entry.\r | |
71 | //\r | |
72 | \r | |
73 | //\r | |
74 | // Enlarge GDT to contain 2 TSS descriptors\r | |
75 | //\r | |
76 | gcSmiGdtr.Limit += (UINT16)(2 * sizeof (IA32_SEGMENT_DESCRIPTOR));\r | |
77 | \r | |
78 | GdtTssTableSize = (gcSmiGdtr.Limit + 1 + TSS_SIZE * 2 + 7) & ~7; // 8 bytes aligned\r | |
717fb604 JY |
79 | mGdtBufferSize = GdtTssTableSize * gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus;\r |
80 | GdtTssTables = (UINT8*)AllocateCodePages (EFI_SIZE_TO_PAGES (mGdtBufferSize));\r | |
fe5f1949 | 81 | ASSERT (GdtTssTables != NULL);\r |
717fb604 | 82 | mGdtBuffer = (UINTN)GdtTssTables;\r |
fe5f1949 JY |
83 | GdtTableStepSize = GdtTssTableSize;\r |
84 | \r | |
85 | for (Index = 0; Index < gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus; Index++) {\r | |
86 | CopyMem (GdtTssTables + GdtTableStepSize * Index, (VOID*)(UINTN)gcSmiGdtr.Base, gcSmiGdtr.Limit + 1 + TSS_SIZE * 2);\r | |
87 | //\r | |
88 | // Fixup TSS descriptors\r | |
89 | //\r | |
90 | TssBase = (UINTN)(GdtTssTables + GdtTableStepSize * Index + gcSmiGdtr.Limit + 1);\r | |
91 | GdtDescriptor = (IA32_SEGMENT_DESCRIPTOR *)(TssBase) - 2;\r | |
92 | GdtDescriptor->Bits.BaseLow = (UINT16)TssBase;\r | |
93 | GdtDescriptor->Bits.BaseMid = (UINT8)(TssBase >> 16);\r | |
94 | GdtDescriptor->Bits.BaseHigh = (UINT8)(TssBase >> 24);\r | |
95 | \r | |
96 | TssBase += TSS_SIZE;\r | |
97 | GdtDescriptor++;\r | |
98 | GdtDescriptor->Bits.BaseLow = (UINT16)TssBase;\r | |
99 | GdtDescriptor->Bits.BaseMid = (UINT8)(TssBase >> 16);\r | |
100 | GdtDescriptor->Bits.BaseHigh = (UINT8)(TssBase >> 24);\r | |
101 | //\r | |
102 | // Fixup TSS segments\r | |
103 | //\r | |
104 | // ESP as known good stack\r | |
105 | //\r | |
106 | *(UINTN *)(TssBase + TSS_IA32_ESP_OFFSET) = mSmmStackArrayBase + EFI_PAGE_SIZE + Index * mSmmStackSize;\r | |
107 | *(UINT32 *)(TssBase + TSS_IA32_CR3_OFFSET) = Cr3;\r | |
108 | }\r | |
109 | } else {\r | |
110 | //\r | |
111 | // Just use original table, AllocatePage and copy them here to make sure GDTs are covered in page memory.\r | |
112 | //\r | |
113 | GdtTssTableSize = gcSmiGdtr.Limit + 1;\r | |
717fb604 JY |
114 | mGdtBufferSize = GdtTssTableSize * gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus;\r |
115 | GdtTssTables = (UINT8*)AllocateCodePages (EFI_SIZE_TO_PAGES (mGdtBufferSize));\r | |
fe5f1949 | 116 | ASSERT (GdtTssTables != NULL);\r |
717fb604 | 117 | mGdtBuffer = (UINTN)GdtTssTables;\r |
fe5f1949 JY |
118 | GdtTableStepSize = GdtTssTableSize;\r |
119 | \r | |
120 | for (Index = 0; Index < gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus; Index++) {\r | |
121 | CopyMem (GdtTssTables + GdtTableStepSize * Index, (VOID*)(UINTN)gcSmiGdtr.Base, gcSmiGdtr.Limit + 1);\r | |
122 | }\r | |
123 | }\r | |
124 | \r | |
125 | *GdtStepSize = GdtTableStepSize;\r | |
126 | return GdtTssTables;\r | |
127 | }\r | |
4a0f88dd | 128 | \r |
e4435f71 JY |
129 | /**\r |
130 | This function sets GDT/IDT buffer to be RO and XP.\r | |
131 | **/\r | |
132 | VOID\r | |
133 | PatchGdtIdtMap (\r | |
134 | VOID\r | |
135 | )\r | |
136 | {\r | |
137 | EFI_PHYSICAL_ADDRESS BaseAddress;\r | |
138 | UINTN Size;\r | |
139 | \r | |
140 | //\r | |
141 | // GDT\r | |
142 | //\r | |
143 | DEBUG ((DEBUG_INFO, "PatchGdtIdtMap - GDT:\n"));\r | |
144 | \r | |
145 | BaseAddress = mGdtBuffer;\r | |
146 | Size = ALIGN_VALUE(mGdtBufferSize, SIZE_4KB);\r | |
147 | if (!FeaturePcdGet (PcdCpuSmmStackGuard)) {\r | |
148 | //\r | |
149 | // Do not set RO for IA32 when stack guard feature is enabled.\r | |
150 | // Stack Guard need use task switch to switch stack.\r | |
151 | // It need write GDT and TSS.\r | |
152 | //\r | |
153 | SmmSetMemoryAttributes (\r | |
154 | BaseAddress,\r | |
155 | Size,\r | |
156 | EFI_MEMORY_RO\r | |
157 | );\r | |
158 | }\r | |
159 | SmmSetMemoryAttributes (\r | |
160 | BaseAddress,\r | |
161 | Size,\r | |
162 | EFI_MEMORY_XP\r | |
163 | );\r | |
164 | \r | |
165 | //\r | |
166 | // IDT\r | |
167 | //\r | |
168 | DEBUG ((DEBUG_INFO, "PatchGdtIdtMap - IDT:\n"));\r | |
169 | \r | |
170 | BaseAddress = gcSmiIdtr.Base;\r | |
171 | Size = ALIGN_VALUE(gcSmiIdtr.Limit + 1, SIZE_4KB);\r | |
172 | SmmSetMemoryAttributes (\r | |
173 | BaseAddress,\r | |
174 | Size,\r | |
175 | EFI_MEMORY_RO\r | |
176 | );\r | |
177 | SmmSetMemoryAttributes (\r | |
178 | BaseAddress,\r | |
179 | Size,\r | |
180 | EFI_MEMORY_XP\r | |
181 | );\r | |
182 | }\r | |
183 | \r | |
4a0f88dd JF |
184 | /**\r |
185 | Transfer AP to safe hlt-loop after it finished restore CPU features on S3 patch.\r | |
186 | \r | |
672b80c8 MK |
187 | @param[in] ApHltLoopCode The address of the safe hlt-loop function.\r |
188 | @param[in] TopOfStack A pointer to the new stack to use for the ApHltLoopCode.\r | |
189 | @param[in] NumberToFinishAddress Address of Semaphore of APs finish count.\r | |
4a0f88dd JF |
190 | \r |
191 | **/\r | |
192 | VOID\r | |
193 | TransferApToSafeState (\r | |
672b80c8 MK |
194 | IN UINTN ApHltLoopCode,\r |
195 | IN UINTN TopOfStack,\r | |
196 | IN UINTN NumberToFinishAddress\r | |
4a0f88dd JF |
197 | )\r |
198 | {\r | |
199 | SwitchStack (\r | |
672b80c8 MK |
200 | (SWITCH_STACK_ENTRY_POINT)ApHltLoopCode,\r |
201 | (VOID *)NumberToFinishAddress,\r | |
4a0f88dd | 202 | NULL,\r |
672b80c8 | 203 | (VOID *)TopOfStack\r |
4a0f88dd JF |
204 | );\r |
205 | //\r | |
206 | // It should never reach here\r | |
207 | //\r | |
208 | ASSERT (FALSE);\r | |
209 | }\r |