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fe5f1949 JY |
1 | /** @file\r |
2 | SMM CPU misc functions for x64 arch specific.\r | |
3 | \r | |
6e601a41 | 4 | Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.<BR>\r |
fe5f1949 JY |
5 | This program and the accompanying materials\r |
6 | are licensed and made available under the terms and conditions of the BSD License\r | |
7 | which accompanies this distribution. The full text of the license may be found at\r | |
8 | http://opensource.org/licenses/bsd-license.php\r | |
9 | \r | |
10 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
11 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
12 | \r | |
13 | **/\r | |
14 | \r | |
15 | #include "PiSmmCpuDxeSmm.h"\r | |
16 | \r | |
717fb604 JY |
17 | EFI_PHYSICAL_ADDRESS mGdtBuffer;\r |
18 | UINTN mGdtBufferSize;\r | |
19 | \r | |
20 | /**\r | |
21 | Initialize IDT for SMM Stack Guard.\r | |
22 | \r | |
23 | **/\r | |
24 | VOID\r | |
25 | EFIAPI\r | |
26 | InitializeIDTSmmStackGuard (\r | |
27 | VOID\r | |
28 | )\r | |
29 | {\r | |
30 | IA32_IDT_GATE_DESCRIPTOR *IdtGate;\r | |
31 | \r | |
32 | //\r | |
33 | // If SMM Stack Guard feature is enabled, set the IST field of\r | |
34 | // the interrupt gate for Page Fault Exception to be 1\r | |
35 | //\r | |
36 | IdtGate = (IA32_IDT_GATE_DESCRIPTOR *)gcSmiIdtr.Base;\r | |
37 | IdtGate += EXCEPT_IA32_PAGE_FAULT;\r | |
38 | IdtGate->Bits.Reserved_0 = 1;\r | |
39 | }\r | |
40 | \r | |
fe5f1949 JY |
41 | /**\r |
42 | Initialize Gdt for all processors.\r | |
43 | \r | |
44 | @param[in] Cr3 CR3 value.\r | |
45 | @param[out] GdtStepSize The step size for GDT table.\r | |
46 | \r | |
47 | @return GdtBase for processor 0.\r | |
48 | GdtBase for processor X is: GdtBase + (GdtStepSize * X)\r | |
49 | **/\r | |
50 | VOID *\r | |
51 | InitGdt (\r | |
52 | IN UINTN Cr3,\r | |
53 | OUT UINTN *GdtStepSize\r | |
54 | )\r | |
55 | {\r | |
56 | UINTN Index;\r | |
57 | IA32_SEGMENT_DESCRIPTOR *GdtDescriptor;\r | |
58 | UINTN TssBase;\r | |
59 | UINTN GdtTssTableSize;\r | |
60 | UINT8 *GdtTssTables;\r | |
61 | UINTN GdtTableStepSize;\r | |
62 | \r | |
63 | //\r | |
64 | // For X64 SMM, we allocate separate GDT/TSS for each CPUs to avoid TSS load contention\r | |
65 | // on each SMI entry.\r | |
66 | //\r | |
67 | GdtTssTableSize = (gcSmiGdtr.Limit + 1 + TSS_SIZE + 7) & ~7; // 8 bytes aligned\r | |
717fb604 JY |
68 | mGdtBufferSize = GdtTssTableSize * gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus;\r |
69 | GdtTssTables = (UINT8*)AllocateCodePages (EFI_SIZE_TO_PAGES (mGdtBufferSize));\r | |
fe5f1949 | 70 | ASSERT (GdtTssTables != NULL);\r |
717fb604 | 71 | mGdtBuffer = (UINTN)GdtTssTables;\r |
fe5f1949 JY |
72 | GdtTableStepSize = GdtTssTableSize;\r |
73 | \r | |
74 | for (Index = 0; Index < gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus; Index++) {\r | |
75 | CopyMem (GdtTssTables + GdtTableStepSize * Index, (VOID*)(UINTN)gcSmiGdtr.Base, gcSmiGdtr.Limit + 1 + TSS_SIZE);\r | |
76 | \r | |
77 | //\r | |
78 | // Fixup TSS descriptors\r | |
79 | //\r | |
80 | TssBase = (UINTN)(GdtTssTables + GdtTableStepSize * Index + gcSmiGdtr.Limit + 1);\r | |
81 | GdtDescriptor = (IA32_SEGMENT_DESCRIPTOR *)(TssBase) - 2;\r | |
82 | GdtDescriptor->Bits.BaseLow = (UINT16)(UINTN)TssBase;\r | |
83 | GdtDescriptor->Bits.BaseMid = (UINT8)((UINTN)TssBase >> 16);\r | |
84 | GdtDescriptor->Bits.BaseHigh = (UINT8)((UINTN)TssBase >> 24);\r | |
85 | \r | |
86 | if (FeaturePcdGet (PcdCpuSmmStackGuard)) {\r | |
87 | //\r | |
88 | // Setup top of known good stack as IST1 for each processor.\r | |
89 | //\r | |
90 | *(UINTN *)(TssBase + TSS_X64_IST1_OFFSET) = (mSmmStackArrayBase + EFI_PAGE_SIZE + Index * mSmmStackSize);\r | |
91 | }\r | |
92 | }\r | |
93 | \r | |
94 | *GdtStepSize = GdtTableStepSize;\r | |
95 | return GdtTssTables;\r | |
96 | }\r | |
4a0f88dd | 97 | \r |
45e3440a JF |
98 | /**\r |
99 | Get Protected mode code segment from current GDT table.\r | |
100 | \r | |
101 | @return Protected mode code segment value.\r | |
102 | **/\r | |
103 | UINT16\r | |
104 | GetProtectedModeCS (\r | |
105 | VOID\r | |
106 | )\r | |
107 | {\r | |
108 | IA32_DESCRIPTOR GdtrDesc;\r | |
109 | IA32_SEGMENT_DESCRIPTOR *GdtEntry;\r | |
110 | UINTN GdtEntryCount;\r | |
111 | UINT16 Index;\r | |
112 | \r | |
113 | Index = (UINT16) -1;\r | |
114 | AsmReadGdtr (&GdtrDesc);\r | |
115 | GdtEntryCount = (GdtrDesc.Limit + 1) / sizeof (IA32_SEGMENT_DESCRIPTOR);\r | |
116 | GdtEntry = (IA32_SEGMENT_DESCRIPTOR *) GdtrDesc.Base;\r | |
117 | for (Index = 0; Index < GdtEntryCount; Index++) {\r | |
118 | if (GdtEntry->Bits.L == 0) {\r | |
119 | if (GdtEntry->Bits.Type > 8 && GdtEntry->Bits.L == 0) {\r | |
120 | break;\r | |
121 | }\r | |
122 | }\r | |
123 | GdtEntry++;\r | |
124 | }\r | |
125 | ASSERT (Index != -1);\r | |
126 | return Index * 8;\r | |
127 | }\r | |
128 | \r | |
4a0f88dd JF |
129 | /**\r |
130 | Transfer AP to safe hlt-loop after it finished restore CPU features on S3 patch.\r | |
131 | \r | |
672b80c8 MK |
132 | @param[in] ApHltLoopCode The address of the safe hlt-loop function.\r |
133 | @param[in] TopOfStack A pointer to the new stack to use for the ApHltLoopCode.\r | |
134 | @param[in] NumberToFinishAddress Address of Semaphore of APs finish count.\r | |
4a0f88dd JF |
135 | \r |
136 | **/\r | |
137 | VOID\r | |
138 | TransferApToSafeState (\r | |
672b80c8 MK |
139 | IN UINTN ApHltLoopCode,\r |
140 | IN UINTN TopOfStack,\r | |
141 | IN UINTN NumberToFinishAddress\r | |
4a0f88dd JF |
142 | )\r |
143 | {\r | |
45e3440a JF |
144 | AsmDisablePaging64 (\r |
145 | GetProtectedModeCS (),\r | |
672b80c8 MK |
146 | (UINT32)ApHltLoopCode,\r |
147 | (UINT32)NumberToFinishAddress,\r | |
45e3440a | 148 | 0,\r |
672b80c8 | 149 | (UINT32)TopOfStack\r |
4a0f88dd JF |
150 | );\r |
151 | //\r | |
152 | // It should never reach here\r | |
153 | //\r | |
154 | ASSERT (FALSE);\r | |
155 | }\r | |
156 | \r |