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1 | /**************************************************************************;\r |
2 | ;* *;\r | |
3 | ;* *;\r | |
4 | ;* Intel Corporation - ACPI Reference Code for the Baytrail *;\r | |
5 | ;* Family of Customer Reference Boards. *;\r | |
6 | ;* *;\r | |
7 | ;* *;\r | |
8 | ;* Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved *;\r | |
9 | ;\r | |
10 | ; This program and the accompanying materials are licensed and made available under\r | |
11 | ; the terms and conditions of the BSD License that accompanies this distribution.\r | |
12 | ; The full text of the license may be found at\r | |
13 | ; http://opensource.org/licenses/bsd-license.php.\r | |
14 | ;\r | |
15 | ; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
16 | ; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
17 | ;\r | |
18 | ;* *;\r | |
19 | ;* *;\r | |
20 | ;**************************************************************************/\r | |
21 | \r | |
22 | \r | |
23 | \r | |
24 | Scope (\_SB.PCI0)\r | |
25 | {\r | |
26 | \r | |
27 | Device(PDRC) // PCI Device Resource Consumption\r | |
28 | {\r | |
29 | Name(_HID,EISAID("PNP0C02"))\r | |
30 | \r | |
31 | Name(_UID,1)\r | |
32 | \r | |
33 | Name(BUF0,ResourceTemplate()\r | |
34 | {\r | |
35 | //\r | |
36 | // PCI Express BAR _BAS and _LEN will be updated in _CRS below according to B0:D0:F0:Reg.60h\r | |
37 | // Forced hard code at the moment.\r | |
38 | //\r | |
39 | //Memory32Fixed(ReadWrite,0,0,PCIX) // PCIEX BAR\r | |
40 | Memory32Fixed(ReadWrite,0x0E0000000,0x010000000,PCIX)\r | |
41 | \r | |
42 | //\r | |
43 | // SPI BAR. Check if the hard code meets the real configuration.\r | |
44 | // If not, dynamically update it like the _CRS method below.\r | |
45 | //\r | |
46 | Memory32Fixed(ReadWrite,0x0FED01000,0x01000,SPIB) // SPI BAR\r | |
47 | \r | |
48 | //\r | |
49 | // PMC BAR. Check if the hard code meets the real configuration.\r | |
50 | // If not, dynamically update it like the _CRS method below.\r | |
51 | //\r | |
52 | Memory32Fixed(ReadWrite,0x0FED03000,0x01000,PMCB) // PMC BAR\r | |
53 | \r | |
54 | //\r | |
55 | // SMB BAR. Check if the hard code meets the real configuration.\r | |
56 | // If not, dynamically update it like the _CRS method below.\r | |
57 | //\r | |
58 | Memory32Fixed(ReadWrite,0x0FED04000,0x01000,SMBB) // SMB BAR\r | |
59 | \r | |
60 | //\r | |
61 | // IO BAR. Check if the hard code meets the real configuration.\r | |
62 | // If not, dynamically update it like the _CRS method below.\r | |
63 | //\r | |
64 | Memory32Fixed(ReadWrite,0x0FED0C000,0x04000,IOBR) // IO BAR\r | |
65 | \r | |
66 | //\r | |
67 | // ILB BAR. Check if the hard code meets the real configuration.\r | |
68 | // If not, dynamically update it like the _CRS method below.\r | |
69 | //\r | |
70 | Memory32Fixed(ReadWrite,0x0FED08000,0x01000,ILBB) // ILB BAR\r | |
71 | \r | |
72 | //\r | |
73 | // RCRB BAR _BAS will be updated in _CRS below according to B0:D31:F0:Reg.F0h\r | |
74 | //\r | |
75 | Memory32Fixed(ReadWrite,0x0FED1C000,0x01000,RCRB) // RCRB BAR\r | |
76 | \r | |
77 | //\r | |
78 | // Local APIC range(0xFEE0_0000 to 0xFEEF_FFFF)\r | |
79 | //\r | |
80 | Memory32Fixed (ReadOnly, 0x0FEE00000, 0x0100000, LIOH)\r | |
81 | \r | |
82 | //\r | |
83 | // MPHY BAR. Check if the hard code meets the real configuration.\r | |
84 | // If not, dynamically update it like the _CRS method below.\r | |
85 | //\r | |
86 | Memory32Fixed(ReadWrite,0x0FEF00000,0x0100000,MPHB) // MPHY BAR\r | |
87 | })\r | |
88 | \r | |
89 | Method(_CRS,0,Serialized)\r | |
90 | {\r | |
91 | \r | |
92 | Return(BUF0)\r | |
93 | }\r | |
94 | \r | |
95 | }\r | |
96 | }\r |