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1 | /*++\r |
2 | \r | |
3 | Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved\r | |
4 | \r | |
5 | This program and the accompanying materials are licensed and made available under\r | |
6 | the terms and conditions of the BSD License that accompanies this distribution.\r | |
7 | The full text of the license may be found at\r | |
8 | http://opensource.org/licenses/bsd-license.php.\r | |
9 | \r | |
10 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
11 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
12 | \r | |
13 | \r | |
14 | --*/\r | |
15 | \r | |
16 | \r | |
17 | /*++\r | |
18 | Module Name:\r | |
19 | \r | |
20 | SDCard.h\r | |
21 | \r | |
22 | Abstract:\r | |
23 | \r | |
24 | Header file for Industry SD Card 2.0 spec.\r | |
25 | \r | |
26 | --*/\r | |
27 | \r | |
28 | #ifndef _SD_CARD_H\r | |
29 | #define _SD_CARD_H\r | |
30 | \r | |
31 | #include "Mmc.h"\r | |
32 | \r | |
33 | #pragma pack(1)\r | |
34 | \r | |
35 | #define CHECK_PATTERN 0xAA\r | |
36 | \r | |
37 | #define ACMD6 6\r | |
38 | #define ACMD13 13\r | |
39 | #define ACMD23 23\r | |
40 | #define ACMD41 41\r | |
41 | #define ACMD42 42\r | |
42 | #define ACMD51 51\r | |
43 | \r | |
44 | \r | |
45 | #define SWITCH_FUNC CMD6\r | |
46 | #define SEND_IF_COND CMD8\r | |
47 | \r | |
48 | \r | |
49 | #define SET_BUS_WIDTH ACMD6\r | |
50 | #define SD_STATUS ACMD13\r | |
51 | #define SET_WR_BLK_ERASE_COUNT ACMD23\r | |
52 | #define SD_SEND_OP_COND ACMD41\r | |
53 | #define SET_CLR_CARD_DETECT ACMD42\r | |
54 | #define SEND_SCR ACMD51\r | |
55 | \r | |
56 | \r | |
57 | \r | |
58 | #define SD_BUS_WIDTH_1 0\r | |
59 | #define SD_BUS_WIDTH_4 2\r | |
60 | \r | |
61 | \r | |
62 | \r | |
63 | #define FREQUENCY_SD_PP (25 * 1000 * 1000)\r | |
64 | #define FREQUENCY_SD_PP_HIGH (50 * 1000 * 1000)\r | |
65 | \r | |
66 | \r | |
67 | #define SD_SPEC_10 0\r | |
68 | #define SD_SPEC_11 1\r | |
69 | #define SD_SPEC_20 2\r | |
70 | \r | |
71 | \r | |
72 | #define VOLTAGE_27_36 0x1\r | |
73 | \r | |
74 | typedef struct {\r | |
75 | UINT8 NotUsed: 1; // 1 [0:0]\r | |
76 | UINT8 CRC: 7; // CRC [7:1]\r | |
77 | UINT8 ECC: 2; // ECC code [9:8]\r | |
78 | UINT8 FILE_FORMAT: 2; // File format [11:10]\r | |
79 | UINT8 TMP_WRITE_PROTECT: 1; // Temporary write protection [12:12]\r | |
80 | UINT8 PERM_WRITE_PROTECT: 1; // Permanent write protection [13:13]\r | |
81 | UINT8 COPY: 1; // Copy flag (OTP) [14:14]\r | |
82 | UINT8 FILE_FORMAT_GRP: 1; // File format group [15:15]\r | |
83 | UINT16 Reserved0: 5; // 0 [20:16]\r | |
84 | UINT16 WRITE_BL_PARTIAL: 1; // Partial blocks for write allowed [21:21]\r | |
85 | UINT16 WRITE_BL_LEN: 4; // Max. write data block length [25:22]\r | |
86 | UINT16 R2W_FACTOR: 3; // Write speed factor [28:26]\r | |
87 | UINT16 DEFAULT_ECC: 2; // Manufacturer default ECC [30:29]\r | |
88 | UINT16 WP_GRP_ENABLE: 1; // Write protect group enable [31:31]\r | |
89 | UINT16 WP_GRP_SIZE: 7; // Write protect group size [38:32]\r | |
90 | UINT16 SECTOR_SIZE: 7; // Erase sector size [45:39]\r | |
91 | UINT16 ERASE_BLK_EN: 1; // Erase single block enable [46:46]\r | |
92 | UINT16 Reserved1: 1; // 0 [47:47]\r | |
93 | \r | |
94 | UINT32 C_SIZE: 22; // Device size [69:48]\r | |
95 | UINT32 Reserved2: 6; // 0 [75:70]\r | |
96 | UINT32 DSR_IMP: 1; // DSR implemented [76:76]\r | |
97 | UINT32 READ_BLK_MISALIGN: 1; // Read block misalignment [77:77]\r | |
98 | UINT32 WRITE_BLK_MISALIGN: 1; // Write block misalignment [78:78]\r | |
99 | UINT32 READ_BL_PARTIAL: 1; // Partial blocks for read allowed [79:79]\r | |
100 | \r | |
101 | UINT16 READ_BL_LEN: 4; // Max. read data block length [83:80]\r | |
102 | UINT16 CCC: 12; // Card command classes [95:84]\r | |
103 | UINT8 TRAN_SPEED ; // Max. bus clock frequency [103:96]\r | |
104 | UINT8 NSAC ; // Data read access-time 2 in CLK cycles (NSAC*100) [111:104]\r | |
105 | UINT8 TAAC ; // Data read access-time 1 [119:112]\r | |
106 | UINT8 Reserved3: 6; // 0 [125:120]\r | |
107 | UINT8 CSD_STRUCTURE: 2; // CSD structure [127:126]\r | |
108 | } CSD_SDV2;\r | |
109 | \r | |
110 | typedef struct {\r | |
111 | UINT32 Reserved0;\r | |
112 | UINT32 Reserved1: 16;\r | |
113 | UINT32 SD_BUS_WIDTH: 4;\r | |
114 | UINT32 SD_SECURITY: 3;\r | |
115 | UINT32 DATA_STAT_AFTER_ERASE: 1;\r | |
116 | UINT32 SD_SPEC: 4;\r | |
117 | UINT32 SCR_STRUCT: 4;\r | |
118 | } SCR;\r | |
119 | \r | |
120 | \r | |
121 | typedef struct {\r | |
122 | UINT8 Reserved0[50];\r | |
123 | UINT8 ERASE_OFFSET: 2;\r | |
124 | UINT8 ERASE_TIMEOUT: 6;\r | |
125 | UINT16 ERASE_SIZE;\r | |
126 | UINT8 Reserved1: 4;\r | |
127 | UINT8 AU_SIZE: 4;\r | |
128 | UINT8 PERFORMANCE_MOVE;\r | |
129 | UINT8 SPEED_CLASS;\r | |
130 | UINT32 SIZE_OF_PROTECTED_AREA;\r | |
131 | UINT32 SD_CARD_TYPE: 16;\r | |
132 | UINT32 Reserved2: 13;\r | |
133 | UINT32 SECURED_MODE: 1;\r | |
134 | UINT32 DAT_BUS_WIDTH: 2;\r | |
135 | } SD_STATUS_REG;\r | |
136 | \r | |
137 | \r | |
138 | \r | |
139 | typedef struct {\r | |
140 | UINT8 Reserved0[34];\r | |
141 | UINT16 Group1BusyStatus;\r | |
142 | UINT16 Group2BusyStatus;\r | |
143 | UINT16 Group3BusyStatus;\r | |
144 | UINT16 Group4BusyStatus;\r | |
145 | UINT16 Group5BusyStatus;\r | |
146 | UINT16 Group6BusyStatus;\r | |
147 | UINT8 DataStructureVersion;\r | |
148 | UINT8 Group21Status;\r | |
149 | UINT8 Group43Status;\r | |
150 | UINT8 Group65Status;\r | |
151 | UINT16 Group1Function;\r | |
152 | UINT16 Group2Function;\r | |
153 | UINT16 Group3Function;\r | |
154 | UINT16 Group4Function;\r | |
155 | UINT16 Group5Function;\r | |
156 | UINT16 Group6Function;\r | |
157 | UINT16 MaxCurrent;\r | |
158 | } SWITCH_STATUS;\r | |
159 | \r | |
160 | \r | |
161 | #pragma pack()\r | |
162 | #endif\r | |
163 | \r |