--- /dev/null
+/**************************************************************************;\r
+;* *;\r
+;* *;\r
+;* Intel Corporation - ACPI Reference Code for the Baytrail *;\r
+;* Family of Customer Reference Boards. *;\r
+;* *;\r
+;* *;\r
+;* Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved *;\r
+;\r
+; This program and the accompanying materials are licensed and made available under\r
+; the terms and conditions of the BSD License that accompanies this distribution.\r
+; The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php.\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+;* *;\r
+;* *;\r
+;**************************************************************************/\r
+\r
+\r
+\r
+// Use this information when determining the Possible IRQs that can be\r
+// used in a given system.\r
+//\r
+// The following IRQs are always in use by legacy devices:\r
+// 0 = System Timer\r
+// 2 = 8259 PIC\r
+// 8 = RTC\r
+// 9 = SCI Interrupt (It may be used, we choose not to)\r
+// 13 = Co-processor Error\r
+//\r
+// The following may be in use by legacy devices:\r
+// 1 = If using PS/2 Keyboard\r
+// 3 = If COMx Port Enabled and IRQ = 3\r
+// 4 = If COMx Port Enabled and IRQ = 4\r
+// 5 = If LPT Port Enabled and IRQ = 5\r
+// 6 = If FDC Enabled\r
+// 7 = If LPT Port Enabled and IRQ = 7\r
+// 12 = If using PS/2 Mouse\r
+// 14 = Primary IDE (If populated and in Compatibility Mode)\r
+// 15 = Secondary IDE (If populated and in Compatibility Mode)\r
+//\r
+// The following will never be in use by legacy devices:\r
+// 10 = Assign to PARC, PCRC, PERC, PGRC\r
+// 11 = Assign to PBRC, PDRC, PFRC, PHRC\r
+\r
+Device(LNKA) // PARC Routing Resource\r
+{\r
+ Name(_HID,EISAID("PNP0C0F")) // PCI Interrupt Link Device\r
+\r
+ Name(_UID,1) // Unique to other Link Devices\r
+\r
+ // Disable the PCI IRQ.\r
+\r
+ Method(_DIS,0,Serialized)\r
+ {\r
+ Or(PARC,0x80,PARC)\r
+ }\r
+\r
+ // Possible IRQ Resource Setting.\r
+\r
+ Method (_PRS, 0, Serialized)\r
+ {\r
+ return (PRSA)\r
+ }\r
+\r
+ // Current IRQ Resource Setting.\r
+\r
+ Method(_CRS,0,Serialized)\r
+ {\r
+ Name(RTLA,ResourceTemplate()\r
+ {\r
+ IRQ(Level,ActiveLow,Shared) {}\r
+ })\r
+\r
+ // Point to specific byte.\r
+\r
+ CreateWordField(RTLA,1,IRQ0)\r
+\r
+ // Zero out IRQ mask bits 0-15\r
+\r
+ Store(Zero,IRQ0)\r
+\r
+ ShiftLeft(1,And(PARC,0x0F),IRQ0)\r
+\r
+ Return(RTLA)\r
+ }\r
+\r
+ // Set IRQ Resource Setting.\r
+\r
+ Method(_SRS,1,Serialized)\r
+ {\r
+ // Point to the specific byte passed in\r
+\r
+ CreateWordField(Arg0,1,IRQ0)\r
+\r
+ // Determine the IRQ bit to set and store it\r
+\r
+ FindSetRightBit(IRQ0,Local0)\r
+ Decrement(Local0)\r
+ Store(Local0,PARC)\r
+ }\r
+\r
+ // PCI IRQ Status.\r
+\r
+ Method(_STA,0,Serialized)\r
+ {\r
+ If(And(PARC,0x80))\r
+ {\r
+ Return(0x0009)\r
+ }\r
+ Else\r
+ {\r
+ Return(0x000B)\r
+ }\r
+ }\r
+}\r
+\r
+Device(LNKB) // PBRC Routing Resource\r
+{\r
+ Name(_HID,EISAID("PNP0C0F"))\r
+\r
+ Name(_UID,2)\r
+\r
+ // Disable the PCI IRQ.\r
+\r
+ Method(_DIS,0,Serialized)\r
+ {\r
+ Or(PBRC,0x80,PBRC)\r
+ }\r
+\r
+ // Possible IRQ Resource Setting.\r
+\r
+ Method (_PRS, 0, Serialized)\r
+ {\r
+ return (PRSB)\r
+ }\r
+\r
+ // Current IRQ Resource Setting.\r
+\r
+ Method(_CRS,0,Serialized)\r
+ {\r
+ Name(RTLB,ResourceTemplate()\r
+ {\r
+ IRQ(Level,ActiveLow,Shared) {}\r
+ })\r
+\r
+ // Point to specific byte.\r
+\r
+ CreateWordField(RTLB,1,IRQ0)\r
+\r
+ // Zero out IRQ mask bits 0-15\r
+\r
+ Store(Zero,IRQ0)\r
+\r
+ ShiftLeft(1,And(PBRC,0x0F),IRQ0)\r
+\r
+ Return(RTLB)\r
+ }\r
+\r
+ // Set IRQ Resource Setting.\r
+\r
+ Method(_SRS,1,Serialized)\r
+ {\r
+ // Point to the specific byte passed in.\r
+\r
+ CreateWordField(Arg0,1,IRQ0)\r
+\r
+ // Determine the IRQ bit to set and store it,\r
+\r
+ FindSetRightBit(IRQ0,Local0)\r
+ Decrement(Local0)\r
+ Store(Local0,PBRC)\r
+ }\r
+\r
+ // PCI IRQ Status.\r
+\r
+ Method(_STA,0,Serialized)\r
+ {\r
+ If(And(PBRC,0x80))\r
+ {\r
+ Return(0x0009)\r
+ }\r
+ Else\r
+ {\r
+ Return(0x000B)\r
+ }\r
+ }\r
+}\r
+\r
+Device(LNKC) // PCRC Routing Resource\r
+{\r
+ Name(_HID,EISAID("PNP0C0F"))\r
+\r
+ Name(_UID,3)\r
+\r
+ // Disable the PCI IRQ.\r
+\r
+ Method(_DIS,0,Serialized)\r
+ {\r
+ Or(PCRC,0x80,PCRC)\r
+ }\r
+\r
+ // Possible IRQ Resource Setting.\r
+\r
+ Method (_PRS, 0, Serialized)\r
+ {\r
+ return (PRSC)\r
+ }\r
+\r
+ // Current IRQ Resource Setting.\r
+\r
+ Method(_CRS,0,Serialized)\r
+ {\r
+ Name(RTLC,ResourceTemplate()\r
+ {\r
+ IRQ(Level,ActiveLow,Shared) {}\r
+ })\r
+\r
+ // Point to specific byte.\r
+\r
+ CreateWordField(RTLC,1,IRQ0)\r
+\r
+ // Zero out IRQ mask bits 0-15\r
+\r
+ Store(Zero,IRQ0)\r
+\r
+ ShiftLeft(1,And(PCRC,0x0F),IRQ0)\r
+\r
+ Return(RTLC)\r
+ }\r
+\r
+ // Set IRQ Resource Setting.\r
+\r
+ Method(_SRS,1,Serialized)\r
+ {\r
+ // Point to the specific byte passed in.\r
+\r
+ CreateWordField(Arg0,1,IRQ0)\r
+\r
+ // Determine the IRQ bit to set and store it,\r
+\r
+ FindSetRightBit(IRQ0,Local0)\r
+ Decrement(Local0)\r
+ Store(Local0,PCRC)\r
+ }\r
+\r
+ // PCI IRQ Status.\r
+\r
+ Method(_STA,0,Serialized)\r
+ {\r
+ If(And(PCRC,0x80))\r
+ {\r
+ Return(0x0009)\r
+ }\r
+ Else\r
+ {\r
+ Return(0x000B)\r
+ }\r
+ }\r
+}\r
+\r
+Device(LNKD) // PDRC Routing Resource\r
+{\r
+ Name(_HID,EISAID("PNP0C0F"))\r
+\r
+ Name(_UID,4)\r
+\r
+ // Disable the PCI IRQ.\r
+\r
+ Method(_DIS,0,Serialized)\r
+ {\r
+ Or(PDRC,0x80,PDRC)\r
+ }\r
+\r
+ // Possible IRQ Resource Setting.\r
+\r
+ Method (_PRS, 0, Serialized)\r
+ {\r
+ return (PRSD)\r
+ }\r
+\r
+ // Current IRQ Resource Setting.\r
+\r
+ Method(_CRS,0,Serialized)\r
+ {\r
+ Name(RTLD,ResourceTemplate()\r
+ {\r
+ IRQ(Level,ActiveLow,Shared) {}\r
+ })\r
+\r
+ // Point to specific byte.\r
+\r
+ CreateWordField(RTLD,1,IRQ0)\r
+\r
+ // Zero out IRQ mask bits 0-15\r
+\r
+ Store(Zero,IRQ0)\r
+\r
+ ShiftLeft(1,And(PDRC,0x0F),IRQ0)\r
+\r
+ Return(RTLD)\r
+ }\r
+\r
+ // Set IRQ Resource Setting.\r
+\r
+ Method(_SRS,1,Serialized)\r
+ {\r
+ // Point to the specific byte passed in.\r
+\r
+ CreateWordField(Arg0,1,IRQ0)\r
+\r
+ // Determine the IRQ bit to set and store it,\r
+\r
+ FindSetRightBit(IRQ0,Local0)\r
+ Decrement(Local0)\r
+ Store(Local0,PDRC)\r
+ }\r
+\r
+ // PCI IRQ Status.\r
+\r
+ Method(_STA,0,Serialized)\r
+ {\r
+ If(And(PDRC,0x80))\r
+ {\r
+ Return(0x0009)\r
+ }\r
+ Else\r
+ {\r
+ Return(0x000B)\r
+ }\r
+ }\r
+}\r
+\r
+Device(LNKE) // PERC Routing Resource\r
+{\r
+ Name(_HID,EISAID("PNP0C0F"))\r
+\r
+ Name(_UID,5)\r
+\r
+ // Disable the PCI IRQ.\r
+\r
+ Method(_DIS,0,Serialized)\r
+ {\r
+ Or(PERC,0x80,PERC)\r
+ }\r
+\r
+ // Possible IRQ Resource Setting.\r
+\r
+ Method (_PRS, 0, Serialized)\r
+ {\r
+ return (PRSE)\r
+ }\r
+\r
+ // Current IRQ Resource Setting.\r
+\r
+ Method(_CRS,0,Serialized)\r
+ {\r
+ Name(RTLE,ResourceTemplate()\r
+ {\r
+ IRQ(Level,ActiveLow,Shared) {}\r
+ })\r
+\r
+ // Point to specific byte.\r
+\r
+ CreateWordField(RTLE,1,IRQ0)\r
+\r
+ // Zero out IRQ mask bits 0-15\r
+\r
+ Store(Zero,IRQ0)\r
+\r
+ ShiftLeft(1,And(PERC,0x0F),IRQ0)\r
+\r
+ Return(RTLE)\r
+ }\r
+\r
+ // Set IRQ Resource Setting.\r
+\r
+ Method(_SRS,1,Serialized)\r
+ {\r
+ // Point to the specific byte passed in\r
+\r
+ CreateWordField(Arg0,1,IRQ0)\r
+\r
+ // Determine the IRQ bit to set and store it\r
+\r
+ FindSetRightBit(IRQ0,Local0)\r
+ Decrement(Local0)\r
+ Store(Local0,PERC)\r
+ }\r
+\r
+ // PCI IRQ Status.\r
+\r
+ Method(_STA,0,Serialized)\r
+ {\r
+ If(And(PERC,0x80))\r
+ {\r
+ Return(0x0009)\r
+ }\r
+ Else\r
+ {\r
+ Return(0x000B)\r
+ }\r
+ }\r
+}\r
+\r
+Device(LNKF) // PFRC Routing Resource\r
+{\r
+ Name(_HID,EISAID("PNP0C0F"))\r
+\r
+ Name(_UID,6)\r
+\r
+ // Disable the PCI IRQ.\r
+\r
+ Method(_DIS,0,Serialized)\r
+ {\r
+ Or(PFRC,0x80,PFRC)\r
+ }\r
+\r
+ // Possible IRQ Resource Setting.\r
+\r
+ Method (_PRS, 0, Serialized)\r
+ {\r
+ return (PRSF)\r
+ }\r
+\r
+ // Current IRQ Resource Setting.\r
+\r
+ Method(_CRS,0,Serialized)\r
+ {\r
+ Name(RTLF,ResourceTemplate()\r
+ {\r
+ IRQ(Level,ActiveLow,Shared) {}\r
+ })\r
+\r
+ // Point to specific byte.\r
+\r
+ CreateWordField(RTLF,1,IRQ0)\r
+\r
+ // Zero out IRQ mask bits 0-15\r
+\r
+ Store(Zero,IRQ0)\r
+\r
+ ShiftLeft(1,And(PFRC,0x0F),IRQ0)\r
+\r
+ Return(RTLF)\r
+ }\r
+\r
+ // Set IRQ Resource Setting.\r
+\r
+ Method(_SRS,1,Serialized)\r
+ {\r
+ // Point to the specific byte passed in.\r
+\r
+ CreateWordField(Arg0,1,IRQ0)\r
+\r
+ // Determine the IRQ bit to set and store it,\r
+\r
+ FindSetRightBit(IRQ0,Local0)\r
+ Decrement(Local0)\r
+ Store(Local0,PFRC)\r
+ }\r
+\r
+ // PCI IRQ Status.\r
+\r
+ Method(_STA,0,Serialized)\r
+ {\r
+ If(And(PFRC,0x80))\r
+ {\r
+ Return(0x0009)\r
+ }\r
+ Else\r
+ {\r
+ Return(0x000B)\r
+ }\r
+ }\r
+}\r
+\r
+Device(LNKG) // PGRC Routing Resource\r
+{\r
+ Name(_HID,EISAID("PNP0C0F"))\r
+\r
+ Name(_UID,7)\r
+\r
+ // Disable the PCI IRQ.\r
+\r
+ Method(_DIS,0,Serialized)\r
+ {\r
+ Or(PGRC,0x80,PGRC)\r
+ }\r
+\r
+ // Possible IRQ Resource Setting.\r
+\r
+ Method (_PRS, 0, Serialized)\r
+ {\r
+ return (PRSG)\r
+ }\r
+\r
+ // Current IRQ Resource Setting.\r
+\r
+ Method(_CRS,0,Serialized)\r
+ {\r
+ Name(RTLG,ResourceTemplate()\r
+ {\r
+ IRQ(Level,ActiveLow,Shared) {}\r
+ })\r
+\r
+ // Point to specific byte.\r
+\r
+ CreateWordField(RTLG,1,IRQ0)\r
+\r
+ // Zero out IRQ mask bits 0-15\r
+\r
+ Store(Zero,IRQ0)\r
+\r
+ ShiftLeft(1,And(PGRC,0x0F),IRQ0)\r
+\r
+ Return(RTLG)\r
+ }\r
+\r
+ // Set IRQ Resource Setting.\r
+\r
+ Method(_SRS,1,Serialized)\r
+ {\r
+ // Point to the specific byte passed in.\r
+\r
+ CreateWordField(Arg0,1,IRQ0)\r
+\r
+ // Determine the IRQ bit to set and store it,\r
+\r
+ FindSetRightBit(IRQ0,Local0)\r
+ Decrement(Local0)\r
+ Store(Local0,PGRC)\r
+ }\r
+\r
+ // PCI IRQ Status.\r
+\r
+ Method(_STA,0,Serialized)\r
+ {\r
+ If(And(PGRC,0x80))\r
+ {\r
+ Return(0x0009)\r
+ }\r
+ Else\r
+ {\r
+ Return(0x000B)\r
+ }\r
+ }\r
+}\r
+\r
+Device(LNKH) // PHRC Routing Resource\r
+{\r
+ Name(_HID,EISAID("PNP0C0F"))\r
+\r
+ Name(_UID,8)\r
+\r
+ // Disable the PCI IRQ.\r
+\r
+ Method(_DIS,0,Serialized)\r
+ {\r
+ Or(PHRC,0x80,PHRC)\r
+ }\r
+\r
+ // Possible IRQ Resource Setting.\r
+\r
+ Method (_PRS, 0, Serialized)\r
+ {\r
+ return (PRSH)\r
+ }\r
+\r
+ // Current IRQ Resource Setting.\r
+\r
+ Method(_CRS,0,Serialized)\r
+ {\r
+ Name(RTLH,ResourceTemplate()\r
+ {\r
+ IRQ(Level,ActiveLow,Shared) {}\r
+ })\r
+\r
+ // Point to specific byte.\r
+\r
+ CreateWordField(RTLH,1,IRQ0)\r
+\r
+ // Zero out IRQ mask bits 0-15\r
+\r
+ Store(Zero,IRQ0)\r
+\r
+ ShiftLeft(1,And(PHRC,0x0F),IRQ0)\r
+\r
+ Return(RTLH)\r
+ }\r
+\r
+ // Set IRQ Resource Setting.\r
+\r
+ Method(_SRS,1,Serialized)\r
+ {\r
+ // Point to the specific byte passed in.\r
+\r
+ CreateWordField(Arg0,1,IRQ0)\r
+\r
+ // Determine the IRQ bit to set and store it,\r
+\r
+ FindSetRightBit(IRQ0,Local0)\r
+ Decrement(Local0)\r
+ Store(Local0,PHRC)\r
+ }\r
+\r
+ // PCI IRQ Status.\r
+\r
+ Method(_STA,0,Serialized)\r
+ {\r
+ If(And(PHRC,0x80))\r
+ {\r
+ Return(0x0009)\r
+ }\r
+ Else\r
+ {\r
+ Return(0x000B)\r
+ }\r
+ }\r
+}\r
--- /dev/null
+/*++\r
+\r
+Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved\r
+\r
+ This program and the accompanying materials are licensed and made available under\r
+ the terms and conditions of the BSD License that accompanies this distribution.\r
+ The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php.\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+\r
+Module Name:\r
+\r
+ AcpiTablePlatform.h\r
+\r
+\r
+Abstract: File contains platform specific ACPI defines for use in ACPI tables\r
+\r
+\r
+--*/\r
+#ifndef _Platform_h_INCLUDED_\r
+#define _Platform_h_INCLUDED_\r
+\r
+#ifdef ECP_FLAG\r
+#include "EdkIIGlueDxe.h"\r
+#endif\r
+#include <IndustryStandard/Acpi.h>\r
+//\r
+// ACPI table information used to initialize tables.\r
+//\r
+#define EFI_ACPI_OEM_ID 'O','E','M','I','D',' ' // OEMID 6 bytes long\r
+#define EFI_ACPI_OEM_TABLE_ID SIGNATURE_64('O','E','M','T','A','B','L','E') // OEM table id 8 bytes long\r
+#define EFI_ACPI_OEM_REVISION 0x00000005\r
+#define EFI_ACPI_CREATOR_ID SIGNATURE_32('C','R','E','A')\r
+#define EFI_ACPI_CREATOR_REVISION 0x0100000D\r
+#define INT_MODEL 0x01\r
+#define PM_PROFILE EFI_ACPI_4_0_PM_PROFILE_MOBILE\r
+#define SCI_INT_VECTOR 0x0009\r
+#define SMI_CMD_IO_PORT 0x000000B2\r
+#define ACPI_ENABLE 0x0A0\r
+#define ACPI_DISABLE 0x0A1\r
+#define S4BIOS_REQ 0x00\r
+#define PSTATE_CNT 0x00\r
+#define PM1a_EVT_BLK 0x00000400\r
+#define PM1b_EVT_BLK 0x00000000\r
+#define PM1a_CNT_BLK 0x00000404\r
+#define PM1b_CNT_BLK 0x00000000\r
+#define PM2_CNT_BLK 0x00000450\r
+#define PM_TMR_BLK 0x00000408\r
+#define GPE0_BLK 0x00000420\r
+#define GPE1_BLK 0x00000000\r
+#define PM1_EVT_LEN 0x04\r
+#define PM1_CNT_LEN 0x02\r
+#define PM2_CNT_LEN 0x01\r
+#define PM_TM_LEN 0x04\r
+#define GPE0_BLK_LEN 0x10\r
+#define GPE1_BLK_LEN 0x00\r
+#define GPE1_BASE 0x00\r
+#define CST_CNT 0x00\r
+#define P_LVL2_LAT 0x0064\r
+#define P_LVL3_LAT 0x01F4\r
+#define FLUSH_SIZE 0x0400\r
+#define FLUSH_STRIDE 0x0010\r
+#define DUTY_OFFSET 0x01\r
+#define DUTY_WIDTH 0x03\r
+#define DAY_ALRM 0x0D\r
+#define MON_ALRM 0x00\r
+#define CENTURY 0x32\r
+#define FLAG ( EFI_ACPI_4_0_WBINVD | EFI_ACPI_4_0_SLP_BUTTON | EFI_ACPI_4_0_RESET_REG_SUP | EFI_ACPI_4_0_RTC_S4)\r
+#define IAPC_BOOT_ARCH ( EFI_ACPI_4_0_VGA_NOT_PRESENT | EFI_ACPI_4_0_8042 | EFI_ACPI_4_0_LEGACY_DEVICES)\r
+#define RESERVED 0x00\r
+\r
+#endif\r
--- /dev/null
+## @file\r
+# Component description file for PlatformAcpiTable module.\r
+#\r
+# Build acpi table data required by system boot.\r
+# All .asi files tagged with "ToolCode="DUMMY"" in following file list are device description and are included\r
+# by top level ASL file which will be dealed with by asl.exe application.\r
+#\r
+# Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved\r
+#\r
+# This program and the accompanying materials are licensed and made available under\r
+# the terms and conditions of the BSD License that accompanies this distribution.\r
+# The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php.\r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+#\r
+#\r
+##\r
+\r
+[defines]\r
+ INF_VERSION = 0x00010005\r
+ BASE_NAME = AcpiTables\r
+ FILE_GUID = 7E374E25-8E01-4FEE-87F2-390C23C606CD\r
+ MODULE_TYPE = USER_DEFINED\r
+ VERSION_STRING = 1.0\r
+ EDK_RELEASE_VERSION = 0x00020000\r
+ EFI_SPECIFICATION_VERSION = 0x00020000\r
+\r
+[sources.common]\r
+ DSDT.ASL\r
+ Facs/Facs.aslc\r
+ Facp/Facp.aslc\r
+ Madt/Madt30.aslc\r
+ Mcfg/Mcfg.aslc\r
+ Hpet/Hpet.aslc\r
+ Lpit/Lpit.aslc\r
+\r
+\r
+[Packages]\r
+ MdePkg/MdePkg.dec\r
+ Vlv2TbltDevicePkg/PlatformPkg.dec\r
+ Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec\r
--- /dev/null
+/**************************************************************************;\r
+;* *;\r
+;* *;\r
+;* Intel Corporation - ACPI Reference Code for the Baytrail *;\r
+;* Family of Customer Reference Boards. *;\r
+;* *;\r
+;* *;\r
+;* Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved *;\r
+;\r
+; This program and the accompanying materials are licensed and made available under\r
+; the terms and conditions of the BSD License that accompanies this distribution.\r
+; The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php.\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+;* *;\r
+;* *;\r
+;**************************************************************************/\r
+\r
+\r
+\r
+// NOTE: The _PDC Implementation is out of the scope of this\r
+// reference code. Please see the latest Hyper-Threading Technology\r
+// Reference Code for complete implementation details.\r
+\r
+Scope(\_PR)\r
+{\r
+ Processor(CPU0, // Unique name for Processor 0.\r
+ 1, // Unique ID for Processor 0.\r
+ 0x00, // CPU0 ACPI P_BLK address = ACPIBASE + 10h.\r
+ 0) // CPU0 P_BLK length = 6 bytes.\r
+ {}\r
+\r
+ Processor(CPU1, // Unique name for Processor 1.\r
+ 2, // Unique ID for Processor 1.\r
+ 0x00,\r
+ 0) // CPU1 P_BLK length = 6 bytes.\r
+ {}\r
+\r
+ Processor(CPU2, // Unique name for Processor 2.\r
+ 3, // Unique ID for Processor 2.\r
+ 0x00,\r
+ 0) // CPU2 P_BLK length = 6 bytes.\r
+ {}\r
+\r
+ Processor(CPU3, // Unique name for Processor 3.\r
+ 4, // Unique ID for Processor 3.\r
+ 0x00,\r
+ 0) // CPU3 P_BLK length = 6 bytes.\r
+ {}\r
+} // End _PR\r
+\r
+\r
--- /dev/null
+/**************************************************************************;\r
+;* *;\r
+;* *;\r
+;* Intel Corporation - ACPI Reference Code for the Sandy Bridge *;\r
+;* Family of Customer Reference Boards. *;\r
+;* *;\r
+;* *;\r
+;* Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved *;\r
+;\r
+; This program and the accompanying materials are licensed and made available under\r
+; the terms and conditions of the BSD License that accompanies this distribution.\r
+; The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php.\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+;* *;\r
+;* *;\r
+;**************************************************************************/\r
+\r
+DefinitionBlock (\r
+ "DSDT.aml",\r
+ "DSDT",\r
+ 0x02, // DSDT revision.\r
+ "OEMID", // OEM ID (6 byte string)\r
+ "VLV-SOC", // OEM table ID (8 byte string)\r
+ 0x0 // OEM version of DSDT table (4 byte Integer)\r
+)\r
+\r
+// BEGIN OF ASL SCOPE\r
+{\r
+ External(MDBG, MethodObj)\r
+\r
+ Method(ADBG, 1, Serialized)\r
+ {\r
+\r
+ If(CondRefOf(MDBG)) //check if SSDT is loaded\r
+ {\r
+ Return(MDBG(Arg0))\r
+ }\r
+\r
+ Return(0)\r
+ }\r
+\r
+\r
+// Miscellaneous services enabled in Project\r
+ include ("token.asl")\r
+ include ("GloblNvs.asl")\r
+ include ("PciTree.asl")\r
+ include ("Pch.asl")\r
+ include ("Vlv.asl")\r
+ include ("CPU.asl")\r
+ include ("Platform.asl")\r
+ include ("THERMAL.ASL")\r
+ include ("PCI_DRC.ASL")\r
+ include ("Video.asl")\r
+ include ("Gpe.asl")\r
+ include ("IoTVirtualDevice.asl")\r
+\r
+ // Sleep states supported by Chipset/Board.\r
+ // SSx - BIOS setup controlled enabled _Sx Sleep state status\r
+ // Values to be written to SLP_TYPE register are provided by SBACPI.SDL (South Bridge ACPI ModulePart)\r
+\r
+ Name(\_S0, Package(4) {0x0,0x0,0,0}) // mandatory System state\r
+ Name(\_S1, Package(4) {0x1,0x0,0,0})\r
+ Name(\_S3, Package(4) {0x5,0x0,0,0})\r
+ Name(\_S4, Package(4) {0x6,0x0,0,0})\r
+ Name(\_S5, Package(4) {0x7,0x0,0,0}) // mandatory System state\r
+\r
+ Method(PTS, 1) // METHOD CALLED FROM _PTS PRIOR TO ENTER ANY SLEEP STATE\r
+ {\r
+ If(Arg0) // entering any sleep state\r
+ {\r
+ }\r
+ }\r
+ Method(WAK, 1) // METHOD CALLED FROM _WAK RIGHT AFTER WAKE UP\r
+ {\r
+ }\r
+\r
+}// End of ASL File\r
--- /dev/null
+/*++\r
+\r
+Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved\r
+\r
+ This program and the accompanying materials are licensed and made available under\r
+ the terms and conditions of the BSD License that accompanies this distribution.\r
+ The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php.\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+\r
+Module Name:\r
+\r
+ Facp.c\r
+\r
+\r
+Abstract: The fixed ACPI description Table (FADT) Structure\r
+\r
+\r
+--*/\r
+#ifdef ECP_FLAG\r
+#include "EDKIIGlueDxe.h"\r
+#else\r
+#include <PiDxe.h>\r
+#endif\r
+#include <IndustryStandard/Acpi50.h>\r
+#include "AcpiTablePlatform.h"\r
+\r
+EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE FACP = {\r
+ {\r
+ EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE,\r
+ sizeof (EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE),\r
+ EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION,\r
+ 0, // to make sum of entire table == 0\r
+ EFI_ACPI_OEM_ID, // OEMID is a 6 bytes long field\r
+ EFI_ACPI_OEM_TABLE_ID, // OEM table identification(8 bytes long)\r
+ EFI_ACPI_OEM_REVISION, // OEM revision number\r
+ EFI_ACPI_CREATOR_ID, // ASL compiler vendor ID\r
+ EFI_ACPI_CREATOR_REVISION // ASL compiler revision number\r
+ },\r
+ 0, // Physical addesss of FACS\r
+ 0, // Physical address of DSDT\r
+ INT_MODEL, // System Interrupt Model (ignored in 2k and later, must be 0 for 98)\r
+ PM_PROFILE, // Preferred PM Profile\r
+ SCI_INT_VECTOR, // System vector of SCI interrupt\r
+ SMI_CMD_IO_PORT, // Port address of SMI command port\r
+ ACPI_ENABLE, // value to write to port smi_cmd to enable ACPI\r
+ ACPI_DISABLE, // value to write to port smi_cmd to disable ACPI\r
+ S4BIOS_REQ, // Value to write to SMI CMD port to enter the S4BIOS state\r
+ PSTATE_CNT, // PState control\r
+ PM1a_EVT_BLK, // Port address of Power Mgt 1a Event Reg Blk\r
+ PM1b_EVT_BLK, // Port address of Power Mgt 1b Event Reg Blk\r
+ PM1a_CNT_BLK, // Port address of Power Mgt 1a Ctrl Reg Blk\r
+ PM1b_CNT_BLK, // Port address of Power Mgt 1b Ctrl Reg Blk\r
+ PM2_CNT_BLK, // Port address of Power Mgt 2 Ctrl Reg Blk\r
+ PM_TMR_BLK, // Port address of Power Mgt Timer Ctrl Reg Blk\r
+ GPE0_BLK, // Port addr of General Purpose Event 0 Reg Blk\r
+ GPE1_BLK, // Port addr of General Purpose Event 1 Reg Blk\r
+ PM1_EVT_LEN, // Byte Length of ports at pm1X_evt_blk\r
+ PM1_CNT_LEN, // Byte Length of ports at pm1X_cnt_blk\r
+ PM2_CNT_LEN, // Byte Length of ports at pm2_cnt_blk\r
+ PM_TM_LEN, // Byte Length of ports at pm_tm_blk\r
+ GPE0_BLK_LEN, // Byte Length of ports at gpe0_blk\r
+ GPE1_BLK_LEN, // Byte Length of ports at gpe1_blk\r
+ GPE1_BASE, // offset in gpe model where gpe1 events start\r
+ CST_CNT, // _CST support\r
+ P_LVL2_LAT, // worst case HW latency to enter/exit C2 state\r
+ P_LVL3_LAT, // worst case HW latency to enter/exit C3 state\r
+ FLUSH_SIZE, // Size of area read to flush caches\r
+ FLUSH_STRIDE, // Stride used in flushing caches\r
+ DUTY_OFFSET, // bit location of duty cycle field in p_cnt reg\r
+ DUTY_WIDTH, // bit width of duty cycle field in p_cnt reg\r
+ DAY_ALRM, // index to day-of-month alarm in RTC CMOS RAM\r
+ MON_ALRM, // index to month-of-year alarm in RTC CMOS RAM\r
+ CENTURY, // index to century in RTC CMOS RAM\r
+ IAPC_BOOT_ARCH, // IA-PCI Boot Architecture Flag\r
+ RESERVED, // reserved\r
+ FLAG,\r
+ {\r
+ EFI_ACPI_5_0_SYSTEM_IO,\r
+ 8,\r
+ 0,\r
+ 0,\r
+ 0xCF9\r
+ },\r
+ 0x06, // Hardware reset value\r
+ 0, 0, 0, // Reserved\r
+ 0, // XFirmwareCtrl\r
+ 0, // XDsdt\r
+ //\r
+ // X_PM1a Event Register Block\r
+ //\r
+ EFI_ACPI_5_0_SYSTEM_IO,\r
+ 0x20,\r
+ 0x00,\r
+ EFI_ACPI_3_0_DWORD,\r
+ PM1a_EVT_BLK,\r
+\r
+ //\r
+ // X_PM1b Event Register Block\r
+ //\r
+ EFI_ACPI_5_0_SYSTEM_IO,\r
+ 0x00,\r
+ 0x00,\r
+ EFI_ACPI_RESERVED_BYTE,\r
+ PM1b_EVT_BLK,\r
+\r
+ //\r
+ // X_PM1a Control Register Block\r
+ //\r
+ EFI_ACPI_5_0_SYSTEM_IO,\r
+ 0x10,\r
+ 0x00,\r
+ EFI_ACPI_3_0_WORD,\r
+ PM1a_CNT_BLK,\r
+\r
+ //\r
+ // X_PM1b Control Register Block\r
+ //\r
+ EFI_ACPI_5_0_SYSTEM_IO,\r
+ 0x00,\r
+ 0x00,\r
+ EFI_ACPI_RESERVED_BYTE,\r
+ PM1b_CNT_BLK,\r
+\r
+ //\r
+ // X_PM2 Control Register Block\r
+ //\r
+ EFI_ACPI_5_0_SYSTEM_IO,\r
+ 0x08,\r
+ 0x00,\r
+ EFI_ACPI_3_0_BYTE,\r
+ PM2_CNT_BLK,\r
+\r
+ //\r
+ // X_PM Timer Control Register Block\r
+ //\r
+ EFI_ACPI_5_0_SYSTEM_IO,\r
+ 0x20,\r
+ 0x00,\r
+ EFI_ACPI_3_0_DWORD,\r
+ PM_TMR_BLK,\r
+\r
+ //\r
+ // X_General Purpose Event 0 Register Block\r
+ //\r
+ EFI_ACPI_5_0_SYSTEM_IO,\r
+ 0x80,\r
+ 0x00,\r
+ EFI_ACPI_RESERVED_BYTE,\r
+ GPE0_BLK,\r
+\r
+ //\r
+ // X_General Purpose Event 1 Register Block\r
+ //\r
+ EFI_ACPI_5_0_SYSTEM_IO,\r
+ 0x00,\r
+ 0x00,\r
+ EFI_ACPI_RESERVED_BYTE,\r
+ GPE1_BLK,\r
+\r
+ //\r
+ // Sleep Control Register Block\r
+ //\r
+ EFI_ACPI_5_0_SYSTEM_IO,\r
+ 0x08,\r
+ 0x00,\r
+ EFI_ACPI_RESERVED_BYTE,\r
+ 0,\r
+\r
+ //\r
+ // Sleep Status Register Block\r
+ //\r
+ EFI_ACPI_5_0_SYSTEM_IO,\r
+ 0x08,\r
+ 0x00,\r
+ EFI_ACPI_RESERVED_BYTE,\r
+ 0,\r
+};\r
+\r
+VOID*\r
+ReferenceAcpiTable (\r
+ VOID\r
+ )\r
+{\r
+ //\r
+ // Reference the table being generated to prevent the optimizer from\r
+ // removing the data structure from the executable\r
+ //\r
+ return (VOID*)&FACP;\r
+}\r
--- /dev/null
+/*++\r
+\r
+Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved\r
+\r
+ This program and the accompanying materials are licensed and made available under\r
+ the terms and conditions of the BSD License that accompanies this distribution.\r
+ The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php.\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+\r
+Module Name:\r
+\r
+ Ea815acpiFACS.c\r
+\r
+\r
+Abstract:\r
+\r
+ This file contains the FACS structure definition.\r
+\r
+--*/\r
+\r
+//\r
+// Statements that include other files\r
+//\r
+#ifdef ECP_FLAG\r
+#include "EDKIIGlueDxe.h"\r
+#else\r
+#include <PiDxe.h>\r
+#endif\r
+#include <IndustryStandard/Acpi50.h>\r
+#include "AcpiTablePlatform.h"\r
+\r
+EFI_ACPI_5_0_FIRMWARE_ACPI_CONTROL_STRUCTURE FACS = {\r
+ EFI_ACPI_5_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_SIGNATURE,\r
+ sizeof (EFI_ACPI_5_0_FIRMWARE_ACPI_CONTROL_STRUCTURE),\r
+\r
+ //\r
+ // Hardware Signature will be updated at runtime\r
+ //\r
+ 0x00000000, //HardwareSignature\r
+ 0x00000000, //FirmwareWakingVector\r
+ 0x00000000, //GlobalLock\r
+ 0x00000000, //Flags\r
+ 0x0000000000000000, //XFirmwareWakingVector\r
+ EFI_ACPI_5_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_VERSION,\r
+ EFI_ACPI_RESERVED_BYTE, //Reserved0[3]\r
+ EFI_ACPI_RESERVED_BYTE,\r
+ EFI_ACPI_RESERVED_BYTE,\r
+ 0x00000000, //OspmFlags\r
+ EFI_ACPI_RESERVED_BYTE, //Reserved1[24]\r
+ EFI_ACPI_RESERVED_BYTE,\r
+ EFI_ACPI_RESERVED_BYTE,\r
+ EFI_ACPI_RESERVED_BYTE,\r
+ EFI_ACPI_RESERVED_BYTE,\r
+ EFI_ACPI_RESERVED_BYTE,\r
+ EFI_ACPI_RESERVED_BYTE,\r
+ EFI_ACPI_RESERVED_BYTE,\r
+ EFI_ACPI_RESERVED_BYTE,\r
+ EFI_ACPI_RESERVED_BYTE,\r
+ EFI_ACPI_RESERVED_BYTE,\r
+ EFI_ACPI_RESERVED_BYTE,\r
+ EFI_ACPI_RESERVED_BYTE,\r
+ EFI_ACPI_RESERVED_BYTE,\r
+ EFI_ACPI_RESERVED_BYTE,\r
+ EFI_ACPI_RESERVED_BYTE,\r
+ EFI_ACPI_RESERVED_BYTE,\r
+ EFI_ACPI_RESERVED_BYTE,\r
+ EFI_ACPI_RESERVED_BYTE,\r
+ EFI_ACPI_RESERVED_BYTE,\r
+ EFI_ACPI_RESERVED_BYTE,\r
+ EFI_ACPI_RESERVED_BYTE,\r
+ EFI_ACPI_RESERVED_BYTE,\r
+ EFI_ACPI_RESERVED_BYTE\r
+};\r
+\r
+VOID*\r
+ReferenceAcpiTable (\r
+ VOID\r
+ )\r
+{\r
+ //\r
+ // Reference the table being generated to prevent the optimizer from\r
+ // removing the data structure from the executable\r
+ //\r
+ return (VOID*)&FACS;\r
+}\r
--- /dev/null
+/**************************************************************************;\r
+;* *;\r
+;* *;\r
+;* Intel Corporation - ACPI Reference Code for the Baytrail *;\r
+;* Family of Customer Reference Boards. *;\r
+;* *;\r
+;* *;\r
+;* Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved *;\r
+;\r
+; This program and the accompanying materials are licensed and made available under\r
+; the terms and conditions of the BSD License that accompanies this distribution.\r
+; The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php.\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+;* *;\r
+;* *;\r
+;**************************************************************************/\r
+\r
+\r
+\r
+// Define a Global region of ACPI NVS Region that may be used for any\r
+// type of implementation. The starting offset and size will be fixed\r
+// up by the System BIOS during POST. Note that the Size must be a word\r
+// in size to be fixed up correctly.\r
+\r
+OperationRegion(GNVS,SystemMemory,0xFFFF0000,0xAA55)\r
+Field(GNVS,AnyAcc,Lock,Preserve)\r
+{\r
+ Offset(0), // Miscellaneous Dynamic Registers:\r
+ OSYS, 16, // (00) Operating System\r
+ , 8, // (02)\r
+ , 8, // (03)\r
+ , 8, // (04)\r
+ , 8, // (05)\r
+ , 8, // (06)\r
+ , 8, // (07)\r
+ , 8, // (08)\r
+ , 8, // (09)\r
+ , 8, // (10)\r
+ P80D, 32, // (11) Port 80 Debug Port Value\r
+ LIDS, 8, // (15) Lid State (Lid Open = 1)\r
+ , 8, // (16)\r
+ , 8, // (17)\r
+ Offset(18), // Thermal Policy Registers:\r
+ , 8, // (18)\r
+ , 8, // (19)\r
+ ACTT, 8, // (20) Active Trip Point\r
+ PSVT, 8, // (21) Passive Trip Point\r
+ TC1V, 8, // (22) Passive Trip Point TC1 Value\r
+ TC2V, 8, // (23) Passive Trip Point TC2 Value\r
+ TSPV, 8, // (24) Passive Trip Point TSP Value\r
+ CRTT, 8, // (25) Critical Trip Point\r
+ DTSE, 8, // (26) Digital Thermal Sensor Enable\r
+ DTS1, 8, // (27) Digital Thermal Sensor 1 Reading\r
+ DTS2, 8, // (28) Digital Thermal Sensor 2 Reading\r
+ DTSF, 8, // (29) DTS SMI Function Call\r
+ Offset(30), // Battery Support Registers:\r
+ , 8, // (30)\r
+ , 8, // (31)\r
+ , 8, // (32)\r
+ , 8, // (33)\r
+ , 8, // (34)\r
+ , 8, // (35)\r
+ , 8, // (36)\r
+ Offset(40), // CPU Identification Registers:\r
+ APIC, 8, // (40) APIC Enabled by SBIOS (APIC Enabled = 1)\r
+ MPEN, 8, // (41) Number of Logical Processors if MP Enabled != 0\r
+ , 8, // (42)\r
+ , 8, // (43)\r
+ , 8, // (44)\r
+ , 32, // (45)\r
+ Offset(50), // SIO CMOS Configuration Registers:\r
+ , 8, // (50)\r
+ , 8, // (51)\r
+ , 8, // (52)\r
+ , 8, // (53)\r
+ , 8, // (54)\r
+ , 8, // (55)\r
+ , 8, // (56)\r
+ , 8, // (57)\r
+ , 8, // (58)\r
+ Offset(60), // Internal Graphics Registers:\r
+ , 8, // (60)\r
+ , 8, // (61)\r
+ CADL, 8, // (62) Current Attached Device List\r
+ , 8, // (63)\r
+ CSTE, 16, // (64) Current Display State\r
+ NSTE, 16, // (66) Next Display State\r
+ , 16, // (68)\r
+ NDID, 8, // (70) Number of Valid Device IDs\r
+ DID1, 32, // (71) Device ID 1\r
+ DID2, 32, // (75) Device ID 2\r
+ DID3, 32, // (79) Device ID 3\r
+ DID4, 32, // (83) Device ID 4\r
+ DID5, 32, // (87) Device ID 5\r
+ , 32, // (91)\r
+ , 8, // (95) Fifth byte of AKSV (mannufacturing mode)\r
+ Offset(103), // Backlight Control Registers:\r
+ , 8, // (103)\r
+ BRTL, 8, // (104) Brightness Level Percentage\r
+ Offset(105), // Ambiant Light Sensor Registers:\r
+ , 8, // (105)\r
+ , 8, // (106)\r
+ LLOW, 8, // (107) LUX Low Value\r
+ , 8, // (108)\r
+ Offset(110), // EMA Registers:\r
+ , 8, // (110)\r
+ , 16, // (111)\r
+ , 16, // (113)\r
+ Offset(116), // MEF Registers:\r
+ , 8, // (116) MEF Enable\r
+ Offset(117), // PCIe Dock:\r
+ , 8, // (117)\r
+ Offset(120), // TPM Registers:\r
+ , 8, // (120)\r
+ , 8, // (121)\r
+ , 8, // (122)\r
+ , 8, // (123)\r
+ , 32, // (124)\r
+ , 8, // (125)\r
+ , 8, // (129)\r
+ Offset(130), //\r
+ , 56, // (130)\r
+ , 56, // (137)\r
+ , 8, // (144)\r
+ , 56, // (145)\r
+ Offset(170), // IGD OpRegion/Software SCI base address\r
+ ASLB, 32, // (170) IGD OpRegion base address\r
+ Offset(174), // IGD OpRegion/Software SCI shared data\r
+ IBTT, 8, // (174) IGD Boot Display Device\r
+ IPAT, 8, // (175) IGD Panel Type CMOs option\r
+ ITVF, 8, // (176) IGD TV Format CMOS option\r
+ ITVM, 8, // (177) IGD TV Minor Format CMOS option\r
+ IPSC, 8, // (178) IGD Panel Scaling\r
+ IBLC, 8, // (179) IGD BLC Configuration\r
+ IBIA, 8, // (180) IGD BIA Configuration\r
+ ISSC, 8, // (181) IGD SSC Configuration\r
+ I409, 8, // (182) IGD 0409 Modified Settings Flag\r
+ I509, 8, // (183) IGD 0509 Modified Settings Flag\r
+ I609, 8, // (184) IGD 0609 Modified Settings Flag\r
+ I709, 8, // (185) IGD 0709 Modified Settings Flag\r
+ IDMM, 8, // (186) IGD DVMT Mode\r
+ IDMS, 8, // (187) IGD DVMT Memory Size\r
+ IF1E, 8, // (188) IGD Function 1 Enable\r
+ HVCO, 8, // (189) HPLL VCO\r
+ NXD1, 32, // (190) Next state DID1 for _DGS\r
+ NXD2, 32, // (194) Next state DID2 for _DGS\r
+ NXD3, 32, // (198) Next state DID3 for _DGS\r
+ NXD4, 32, // (202) Next state DID4 for _DGS\r
+ NXD5, 32, // (206) Next state DID5 for _DGS\r
+ NXD6, 32, // (210) Next state DID6 for _DGS\r
+ NXD7, 32, // (214) Next state DID7 for _DGS\r
+ NXD8, 32, // (218) Next state DID8 for _DGS\r
+ GSMI, 8, // (222) GMCH SMI/SCI mode (0=SCI)\r
+ PAVP, 8, // (223) IGD PAVP data\r
+ Offset(225),\r
+ OSCC, 8, // (225) PCIE OSC Control\r
+ NEXP, 8, // (226) Native PCIE Setup Value\r
+ Offset(235), // Global Variables\r
+ DSEN, 8, // (235) _DOS Display Support Flag.\r
+ ECON, 8, // (236) Embedded Controller Availability Flag.\r
+ GPIC, 8, // (237) Global IOAPIC/8259 Interrupt Mode Flag.\r
+ CTYP, 8, // (238) Global Cooling Type Flag.\r
+ L01C, 8, // (239) Global L01 Counter.\r
+ VFN0, 8, // (240) Virtual Fan0 Status.\r
+ VFN1, 8, // (241) Virtual Fan1 Status.\r
+ Offset(256),\r
+ NVGA, 32, // (256) NVIG opregion address\r
+ NVHA, 32, // (260) NVHM opregion address\r
+ AMDA, 32, // (264) AMDA opregion address\r
+ DID6, 32, // (268) Device ID 6\r
+ DID7, 32, // (272) Device ID 7\r
+ DID8, 32, // (276) Device ID 8\r
+ Offset(332),\r
+ USEL, 8, // (332) UART Selection\r
+ PU1E, 8, // (333) PCU UART 1 Enabled\r
+ PU2E, 8, // (334) PCU UART 2 Enabled\r
+\r
+ LPE0, 32, // (335) LPE Bar0\r
+ LPE1, 32, // (339) LPE Bar1\r
+ LPE2, 32, // (343) LPE Bar2\r
+\r
+ Offset(347),\r
+ , 8, // (347)\r
+ , 8, // (348)\r
+ PFLV, 8, // (349) Platform Flavor\r
+\r
+ Offset(351),\r
+ ICNF, 8, // (351) ISCT / AOAC Configuration\r
+ XHCI, 8, // (352) xHCI controller mode\r
+ PMEN, 8, // (353) PMIC enable/disable\r
+\r
+ LPEE, 8, // (354) LPE enable/disable\r
+ ISPA, 32, // (355) ISP Base Addr\r
+ ISPD, 8, // (359) ISP Device Selection 0: Disabled; 1: PCI Device 2; 2: PCI Device 3\r
+\r
+ offset(360), // ((4+8+6)*4+2)*4=296\r
+ //\r
+ // Lpss controllers\r
+ //\r
+ PCIB, 32,\r
+ PCIT, 32,\r
+ D10A, 32, //DMA1\r
+ D10L, 32,\r
+ D11A, 32,\r
+ D11L, 32,\r
+ P10A, 32, // PWM1\r
+ P10L, 32,\r
+ P11A, 32,\r
+ P11L, 32,\r
+ P20A, 32, // PWM2\r
+ P20L, 32,\r
+ P21A, 32,\r
+ P21L, 32,\r
+ U10A, 32, // UART1\r
+ U10L, 32,\r
+ U11A, 32,\r
+ U11L, 32,\r
+ U20A, 32, // UART2\r
+ U20L, 32,\r
+ U21A, 32,\r
+ U21L, 32,\r
+ SP0A, 32, // SPI\r
+ SP0L, 32,\r
+ SP1A, 32,\r
+ SP1L, 32,\r
+\r
+ D20A, 32, //DMA2\r
+ D20L, 32,\r
+ D21A, 32,\r
+ D21L, 32,\r
+ I10A, 32, // I2C1\r
+ I10L, 32,\r
+ I11A, 32,\r
+ I11L, 32,\r
+ I20A, 32, // I2C2\r
+ I20L, 32,\r
+ I21A, 32,\r
+ I21L, 32,\r
+ I30A, 32, // I2C3\r
+ I30L, 32,\r
+ I31A, 32,\r
+ I31L, 32,\r
+ I40A, 32, // I2C4\r
+ I40L, 32,\r
+ I41A, 32,\r
+ I41L, 32,\r
+ I50A, 32, // I2C5\r
+ I50L, 32,\r
+ I51A, 32,\r
+ I51L, 32,\r
+ I60A, 32, // I2C6\r
+ I60L, 32,\r
+ I61A, 32,\r
+ I61L, 32,\r
+ I70A, 32, // I2C7\r
+ I70L, 32,\r
+ I71A, 32,\r
+ I71L, 32,\r
+ //\r
+ // Scc controllers\r
+ //\r
+ eM0A, 32, // EMMC\r
+ eM0L, 32,\r
+ eM1A, 32,\r
+ eM1L, 32,\r
+ SI0A, 32, // SDIO\r
+ SI0L, 32,\r
+ SI1A, 32,\r
+ SI1L, 32,\r
+ SD0A, 32, // SDCard\r
+ SD0L, 32,\r
+ SD1A, 32,\r
+ SD1L, 32,\r
+ MH0A, 32, //\r
+ MH0L, 32,\r
+ MH1A, 32,\r
+ MH1L, 32,\r
+\r
+ offset(656),\r
+ SDRM, 8,\r
+ offset(657),\r
+ HLPS, 8, //(657) Hide Devices\r
+ offset(658),\r
+ OSEL, 8, //(658) OS Seletion - Windows/Android\r
+\r
+ offset(659), // VLV1 DPTF\r
+ SDP1, 8, //(659) An enumerated value corresponding to SKU\r
+ DPTE, 8, //(660) DPTF Enable\r
+ THM0, 8, //(661) System Thermal 0\r
+ THM1, 8, //(662) System Thermal 1\r
+ THM2, 8, //(663) System Thermal 2\r
+ THM3, 8, //(664) System Thermal 3\r
+ THM4, 8, //(665) System Thermal 3\r
+ CHGR, 8, //(666) DPTF Changer Device\r
+ DDSP, 8, //(667) DPTF Display Device\r
+ DSOC, 8, //(668) DPTF SoC device\r
+ DPSR, 8, //(669) DPTF Processor device\r
+ DPCT, 32, //(670) DPTF Processor participant critical temperature\r
+ DPPT, 32, //(674) DPTF Processor participant passive temperature\r
+ DGC0, 32, //(678) DPTF Generic sensor0 participant critical temperature\r
+ DGP0, 32, //(682) DPTF Generic sensor0 participant passive temperature\r
+ DGC1, 32, //(686) DPTF Generic sensor1 participant critical temperature\r
+ DGP1, 32, //(690) DPTF Generic sensor1 participant passive temperature\r
+ DGC2, 32, //(694) DPTF Generic sensor2 participant critical temperature\r
+ DGP2, 32, //(698) DPTF Generic sensor2 participant passive temperature\r
+ DGC3, 32, //(702) DPTF Generic sensor3 participant critical temperature\r
+ DGP3, 32, //(706) DPTF Generic sensor3 participant passive temperature\r
+ DGC4, 32, //(710)DPTF Generic sensor3 participant critical temperature\r
+ DGP4, 32, //(714)DPTF Generic sensor3 participant passive temperature\r
+ DLPM, 8, //(718) DPTF Current low power mode setting\r
+ DSC0, 32, //(719) DPTF Critical threshold0 for SCU\r
+ DSC1, 32, //(723) DPTF Critical threshold1 for SCU\r
+ DSC2, 32, //(727) DPTF Critical threshold2 for SCU\r
+ DSC3, 32, //(731) DPTF Critical threshold3 for SCU\r
+ DSC4, 32, //(735) DPTF Critical threshold3 for SCU\r
+ DDBG, 8, //(739) DPTF Super Debug option. 0 - Disabled, 1 - Enabled\r
+ LPOE, 32, //(740) DPTF LPO Enable\r
+ LPPS, 32, //(744) P-State start index\r
+ LPST, 32, //(748) Step size\r
+ LPPC, 32, //(752) Power control setting\r
+ LPPF, 32, //(756) Performance control setting\r
+ DPME, 8, //(760) DPTF DPPM enable/disable\r
+ BCSL, 8, //(761) Battery charging solution 0-CLV 1-ULPMC\r
+ NFCS, 8, //(762) NFCx Select 1: NFC1 2:NFC2\r
+ PCIM, 8, //(763) EMMC device 0-ACPI mode, 1-PCI mode\r
+ TPMA, 32, //(764)\r
+ TPML, 32, //(768)\r
+ ITSA, 8, //(772) I2C Touch Screen Address\r
+ S0IX, 8, //(773) S0ix status\r
+ SDMD, 8, //(774) SDIO Mode\r
+ EMVR, 8, //(775) eMMC controller version\r
+ BMBD, 32, //(776) BM Bound\r
+ FSAS, 8, //(780) FSA Status\r
+ BDID, 8, //(781) Board ID\r
+ FBID, 8, //(782) FAB ID\r
+ OTGM, 8, //(783) OTG mode\r
+ STEP, 8, //(784) Stepping ID\r
+ WITT, 8, //(785) Enable Test Device connected to I2C for WHCK test.\r
+ SOCS, 8, //(786) provide the SoC stepping infomation\r
+ AMTE, 8, //(787) Ambient Trip point change\r
+ UTS, 8, //(788) Enable Test Device connected to URT for WHCK test.\r
+ SCPE, 8, //(789) Allow higher performance on AC/USB - Enable/Disable\r
+ Offset(792),\r
+ EDPV, 8, //(792) Check for eDP display device\r
+ DIDX, 32, //(793) Device ID for eDP device\r
+ IOT, 8, //(794) MinnowBoard Max JP1 is configured for MSFT IOT project. \r
+}\r
+\r
--- /dev/null
+/**************************************************************************;\r
+;* *;\r
+;* *;\r
+;* Intel Corporation - ACPI Reference Code for the Baytrail *;\r
+;* Family of Customer Reference Boards. *;\r
+;* *;\r
+;* *;\r
+;* Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved *;\r
+;\r
+; This program and the accompanying materials are licensed and made available under\r
+; the terms and conditions of the BSD License that accompanies this distribution.\r
+; The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php.\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+;* *;\r
+;* *;\r
+;**************************************************************************/\r
+\r
+\r
+// General Purpose Events. This Scope handles the Run-time and\r
+// Wake-time SCIs. The specific method called will be determined by\r
+// the _Lxx value, where xx equals the bit location in the General\r
+// Purpose Event register(s).\r
+\r
+Scope(\_GPE)\r
+{\r
+ //\r
+ // Software GPE caused the event.\r
+ //\r
+ Method(_L02)\r
+ {\r
+ // Clear GPE status bit.\r
+ Store(0,GPEC)\r
+ //\r
+ // Handle DTS Thermal Events.\r
+ //\r
+ External(DTSE, IntObj)\r
+ If(CondRefOf(DTSE))\r
+ {\r
+ If(LGreaterEqual(DTSE, 0x01))\r
+ {\r
+ Notify(\_TZ.TZ01,0x80)\r
+ }\r
+ }\r
+ }\r
+\r
+ //\r
+ // PUNIT SCI event.\r
+ //\r
+ Method(_L04)\r
+ {\r
+ // Clear the PUNIT Status Bit.\r
+ Store(1, PSCI)\r
+ }\r
+\r
+\r
+ //\r
+ // IGD OpRegion SCI event (see IGD OpRegion/Software SCI BIOS SPEC).\r
+ //\r
+ Method(_L05)\r
+ {\r
+ If(LAnd(\_SB.PCI0.GFX0.GSSE, LNot(GSMI))) // Graphics software SCI event?\r
+ {\r
+ \_SB.PCI0.GFX0.GSCI() // Handle the SWSCI\r
+ }\r
+ }\r
+\r
+ //\r
+ // This PME event (PCH's GPE #13) is received when any PCH internal device with PCI Power Management capabilities\r
+ // on bus 0 asserts the equivalent of the PME# signal.\r
+ //\r
+ Method(_L0D, 0)\r
+ {\r
+ If(LAnd(\_SB.PCI0.EHC1.PMEE, \_SB.PCI0.EHC1.PMES))\r
+ {\r
+ If(LNotEqual(OSEL, 1))\r
+ {\r
+ Store(1, \_SB.PCI0.EHC1.PMES) //Clear PME status\r
+ Store(0, \_SB.PCI0.EHC1.PMEE) //Disable PME\r
+ }\r
+ Notify(\_SB.PCI0.EHC1, 0x02)\r
+ }\r
+ If(LAnd(\_SB.PCI0.XHC1.PMEE, \_SB.PCI0.XHC1.PMES))\r
+ {\r
+ If(LNotEqual(OSEL, 1))\r
+ {\r
+ Store(1, \_SB.PCI0.XHC1.PMES) //Clear PME status\r
+ Store(0, \_SB.PCI0.XHC1.PMEE) //Disable PME\r
+ }\r
+ Notify(\_SB.PCI0.XHC1, 0x02)\r
+ }\r
+ If(LAnd(\_SB.PCI0.HDEF.PMEE, \_SB.PCI0.HDEF.PMES))\r
+ {\r
+ If(LNotEqual(OSEL, 1))\r
+ {\r
+ Store(1, \_SB.PCI0.HDEF.PMES) //Clear PME status\r
+ Store(0, \_SB.PCI0.HDEF.PMEE) //Disable PME\r
+ }\r
+ Notify(\_SB.PCI0.HDEF, 0x02)\r
+ }\r
+ }\r
+}\r
--- /dev/null
+/*++\r
+\r
+Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved\r
+\r
+ This program and the accompanying materials are licensed and made available under\r
+ the terms and conditions of the BSD License that accompanies this distribution.\r
+ The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php.\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+\r
+Module Name:\r
+\r
+ HOST_BUS.ASL\r
+\r
+Abstract:\r
+\r
+ Baytrail PCI configuration space definition.\r
+\r
+---*/\r
+Device(VLVC)\r
+{\r
+ Name(_ADR, 0x00000000) // Device 0, Function 0\r
+\r
+ // Define various MCH Controller PCI Configuration Space\r
+ // registers which will be used to dynamically produce all\r
+ // resources in the Host Bus _CRS.\r
+ OperationRegion(HBUS, PCI_Config, 0x00, 0xFF)\r
+ Field(HBUS, DWordAcc, NoLock, Preserve)\r
+ {\r
+ Offset(0xD0),\r
+ SMCR, 32, // VLV Message Control Register (0xD0)\r
+ Offset(0xD4),\r
+ SMDR, 32, // VLV Message Data Register (0xD4)\r
+ Offset(0xD8),\r
+ MCRX, 32, // VLV Message Control Register Extension (0xD8)\r
+ }\r
+\r
+ // Define a method to read a 32-bit register on the VLV Message bus.\r
+ // Arg0 = Port\r
+ // Arg1 = Register\r
+ //\r
+ // Returns 32-bit register value\r
+\r
+ Method(RMBR, 2, Serialized)\r
+ {\r
+\r
+ // Initiate regsiter read message on VLV Message Bus MCR\r
+\r
+ Or(ShiftLeft(Arg0, 16), ShiftLeft(Arg1, 8), Local0)\r
+ Or(0x100000F0, Local0, SMCR)\r
+\r
+ // Read register value from Message Data Register\r
+\r
+ Return(SMDR)\r
+ }\r
+\r
+\r
+ // Define a method to write a 32-bit register on the VLV Message bus MDR.\r
+ // Arg0 = Port\r
+ // Arg1 = Register\r
+ // Arg2 = 32-bit value\r
+\r
+ Method(WMBR, 3, Serialized)\r
+ {\r
+\r
+ // Write register value to Message Data Register\r
+\r
+ Store(Arg2, SMDR)\r
+\r
+ // Initiate register write message on VLV Message Bus\r
+\r
+ Or(ShiftLeft(Arg0, 16), ShiftLeft(Arg1, 8), Local0)\r
+ Or(0x110000F0, Local0, SMCR)\r
+ }\r
+}\r
+\r
+//\r
+// BUS, I/O, and MMIO resources\r
+//\r
+Method(_CRS,0,Serialized)\r
+{\r
+ //Update ISP0 reserved memory\r
+ CreateDwordField(RES0, ^ISP0._MIN,ISMN)\r
+ CreateDwordField(RES0, ^ISP0._MAX,ISMX)\r
+ CreateDwordField(RES0, ^ISP0._LEN,ISLN)\r
+ If (LEqual(ISPD,1))\r
+ {\r
+ Store (ISPA, ISMN)\r
+ Add (ISMN, ISLN, ISMX)\r
+ Subtract(ISMX, 1, ISMX)\r
+ } Else\r
+ {\r
+ Store (0, ISMN)\r
+ Store (0, ISMX)\r
+ Store (0, ISLN)\r
+ }\r
+\r
+ //PCI MMIO SPACE\r
+ CreateDwordField(RES0, ^PM01._MIN,M1MN)\r
+ CreateDwordField(RES0, ^PM01._MAX,M1MX)\r
+ CreateDwordField(RES0, ^PM01._LEN,M1LN)\r
+\r
+ //Get dBMBOUND Base\r
+ And(BMBD, 0xFF000000, M1MN)\r
+\r
+ //Get ECBASE\r
+ Store(PCIT, M1MX)\r
+ Add(Subtract(M1MX, M1MN), 1, M1LN)\r
+ Subtract(M1MX, 1, M1MX)\r
+\r
+ // Create pointers to Gfx Stolen Memory Sizing values.\r
+ CreateDwordField(RES0, ^STOM._MIN,GSMN)\r
+ CreateDwordField(RES0, ^STOM._MAX,GSMX)\r
+ CreateDwordField(RES0, ^STOM._LEN,GSLN)\r
+\r
+ If (LNotEqual (\_SB.PCI0.GFX0.GSTM, 0xFFFFFFFF))\r
+ {\r
+ Store(0x00, GSMN) //Read the Stolen memory base from B0:D2:F0:R5C\r
+ } else\r
+ {\r
+ Store(\_SB.PCI0.GFX0.GSTM, GSMN) //Read the Stolen memory base from B0:D2:F0:R5C\r
+ }\r
+ If (LNotEqual (\_SB.PCI0.GFX0.GUMA, 0xFFFFFFFF))\r
+ {\r
+ Store(0x00, GSLN) //Read the Stolen memory base from B0:D2:F0:R5C\r
+ } else\r
+ {\r
+ ShiftLeft(\_SB.PCI0.GFX0.GUMA, 25, GSLN) //Read Stolen memory base form B0:D2:F0:R50\r
+ }\r
+ Add(GSMN, GSLN, GSMX) //Store the Stolen Memory Size\r
+ Subtract(GSMX, 1, GSMX)\r
+\r
+ Return(RES0)\r
+}\r
+\r
+Name( RES0,ResourceTemplate()\r
+{\r
+ WORDBusNumber ( // Bus number resource (0); the bridge produces bus numbers for its subsequent buses\r
+ ResourceProducer, // bit 0 of general flags is 1\r
+ MinFixed, // Range is fixed\r
+ MaxFixed, // Range is fixed\r
+ PosDecode, // PosDecode\r
+ 0x0000, // Granularity\r
+ 0x0000, // Min\r
+ 0x00FF, // Max\r
+ 0x0000, // Translation\r
+ 0x0100 // Range Length = Max-Min+1\r
+ )\r
+\r
+ IO (Decode16, 0x70, 0x77, 0x01, 0x08) //Consumed resource (0xCF8-0xCFF)\r
+ IO (Decode16, 0xCF8, 0xCF8, 0x01, 0x08) //Consumed resource (0xCF8-0xCFF)\r
+\r
+ WORDIO ( // Consumed-and-produced resource (all I/O below CF8)\r
+ ResourceProducer, // bit 0 of general flags is 0\r
+ MinFixed, // Range is fixed\r
+ MaxFixed, // Range is fixed\r
+ PosDecode,\r
+ EntireRange,\r
+ 0x0000, // Granularity\r
+ 0x0000, // Min\r
+ 0x006F, // Max\r
+ 0x0000, // Translation\r
+ 0x0070 // Range Length\r
+ )\r
+\r
+ WORDIO ( // Consumed-and-produced resource\r
+ ResourceProducer, // bit 0 of general flags is 0\r
+ MinFixed, // Range is fixed\r
+ MaxFixed, // Range is fixed\r
+ PosDecode,\r
+ EntireRange,\r
+ 0x0000, // Granularity\r
+ 0x0078, // Min\r
+ 0x0CF7, // Max\r
+ 0x0000, // Translation\r
+ 0x0C80 // Range Length\r
+ )\r
+\r
+ WORDIO ( // Consumed-and-produced resource (all I/O above CFF)\r
+ ResourceProducer, // bit 0 of general flags is 0\r
+ MinFixed, // Range is fixed\r
+ MaxFixed, // Range is fixed\r
+ PosDecode,\r
+ EntireRange,\r
+ 0x0000, // Granularity\r
+ 0x0D00, // Min\r
+ 0xFFFF, // Max\r
+ 0x0000, // Translation\r
+ 0xF300 // Range Length\r
+ )\r
+\r
+ DWORDMEMORY ( // Descriptor for legacy VGA video RAM\r
+ ResourceProducer, // bit 0 of general flags is 0\r
+ PosDecode,\r
+ MinFixed, // Range is fixed\r
+ MaxFixed, // Range is fixed\r
+ Cacheable,\r
+ ReadWrite,\r
+ 0x00000000, // Granularity\r
+ 0x000A0000, // Min\r
+ 0x000BFFFF, // Max\r
+ 0x00000000, // Translation\r
+ 0x00020000 // Range Length\r
+ )\r
+\r
+ DWORDMEMORY ( // Descriptor for legacy OptionRom\r
+ ResourceProducer, // bit 0 of general flags is 0\r
+ PosDecode,\r
+ MinFixed, // Range is fixed\r
+ MaxFixed, // Range is fixed\r
+ Cacheable,\r
+ ReadWrite,\r
+ 0x00000000, // Granularity\r
+ 0x000C0000, // Min\r
+ 0x000DFFFF, // Max\r
+ 0x00000000, // Translation\r
+ 0x00020000 // Range Length\r
+ )\r
+\r
+ DWORDMEMORY ( // Descriptor for BIOS Area\r
+ ResourceProducer, // bit 0 of general flags is 0\r
+ PosDecode,\r
+ MinFixed, // Range is fixed\r
+ MaxFixed, // Range is fixed\r
+ Cacheable,\r
+ ReadWrite,\r
+ 0x00000000, // Granularity\r
+ 0x000E0000, // Min\r
+ 0x000FFFFF, // Max\r
+ 0x00000000, // Translation\r
+ 0x00020000 // Range Length\r
+ )\r
+\r
+ DWORDMEMORY ( // Descriptor for ISP0 reserved Mem\r
+ ResourceProducer, // bit 0 of general flags is 0\r
+ PosDecode,\r
+ MinFixed, // Range is fixed\r
+ MaxFixed, // Range is fixed\r
+ Cacheable,\r
+ ReadWrite,\r
+ 0x00000000, // Granularity\r
+ 0x7A000000, // Min\r
+ 0x7A3FFFFF, // Max\r
+ 0x00000000, // Translation\r
+ 0x00400000 // Range Length\r
+ ,,,\r
+ ISP0\r
+ )\r
+\r
+ DWORDMEMORY ( // Descriptor for VGA Stolen Mem\r
+ ResourceProducer, // bit 0 of general flags is 0\r
+ PosDecode,\r
+ MinFixed, // Range is fixed\r
+ MaxFixed, // Range is fixed\r
+ Cacheable,\r
+ ReadWrite,\r
+ 0x00000000, // Granularity\r
+ 0x7C000000, // Min\r
+ 0x7FFFFFFF, // Max\r
+ 0x00000000, // Translation\r
+ 0x04000000 // Range Length\r
+ ,,,\r
+ STOM\r
+ )\r
+\r
+ DWORDMEMORY ( // Descriptor for PCI MMIO\r
+ ResourceProducer, // bit 0 of general flags is 0\r
+ PosDecode,\r
+ MinFixed, // Range is fixed\r
+ MaxFixed, // Range is fixed\r
+ Cacheable,\r
+ ReadWrite,\r
+ 0x00000000, // Granularity\r
+ 0x80000000, // Min\r
+ 0xDFFFFFFF, // Max\r
+ 0x00000000, // Translation\r
+ 0x60000000 // Range Length\r
+ ,,,\r
+ PM01\r
+ )\r
+})\r
+\r
+//Name(GUID,UUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))\r
+Name(GUID,Buffer()\r
+{\r
+ 0x5b, 0x4d, 0xdb, 0x33,\r
+ 0xf7, 0x1f,\r
+ 0x1c, 0x40,\r
+ 0x96, 0x57,\r
+ 0x74, 0x41, 0xc0, 0x3d, 0xd7, 0x66\r
+})\r
+\r
+\r
+Name(SUPP,0) // PCI _OSC Support Field value\r
+Name(CTRL,0) // PCI _OSC Control Field value\r
+\r
+Method(_OSC,4,Serialized)\r
+{\r
+ // Check for proper UUID\r
+ // Save the capabilities buffer\r
+ Store(Arg3,Local0)\r
+\r
+ // Create DWord-adressable fields from the Capabilties Buffer\r
+ CreateDWordField(Local0,0,CDW1)\r
+ CreateDWordField(Local0,4,CDW2)\r
+ CreateDWordField(Local0,8,CDW3)\r
+\r
+ // Check for proper UUID\r
+ If(LAnd(LEqual(Arg0,GUID),NEXP))\r
+ {\r
+ // Save Capabilities DWord2 & 3\r
+ Store(CDW2,SUPP)\r
+ Store(CDW3,CTRL)\r
+\r
+ If(Not(And(CDW1,1))) // Query flag clear?\r
+ {\r
+ // Disable GPEs for features granted native control.\r
+ If(And(CTRL,0x02))\r
+ {\r
+ NHPG()\r
+ }\r
+ If(And(CTRL,0x04)) // PME control granted?\r
+ {\r
+ NPME()\r
+ }\r
+ }\r
+\r
+ If(LNotEqual(Arg1,One))\r
+ {\r
+ // Unknown revision\r
+ Or(CDW1,0x08,CDW1)\r
+ }\r
+\r
+ If(LNotEqual(CDW3,CTRL))\r
+ {\r
+ // Capabilities bits were masked\r
+ Or(CDW1,0x10,CDW1)\r
+ }\r
+ // Update DWORD3 in the buffer\r
+ And(CTRL,0xfe,CTRL) \r
+ Store(CTRL,CDW3)\r
+ Store(CTRL,OSCC)\r
+ Return(Local0)\r
+ } Else\r
+ {\r
+ Or(CDW1,4,CDW1) // Unrecognized UUID\r
+ Return(Local0)\r
+ }\r
+} // End _OSC\r
--- /dev/null
+/*++\r
+\r
+Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved\r
+\r
+ This program and the accompanying materials are licensed and made available under\r
+ the terms and conditions of the BSD License that accompanies this distribution.\r
+ The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php.\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+\r
+Module Name:\r
+\r
+ Hpet.c\r
+\r
+Abstract:\r
+\r
+ This file contains a structure definition for the ACPI HPET Table.\r
+--*/\r
+\r
+//\r
+// Statements that include other files\r
+//\r
+#ifdef ECP_FLAG\r
+#include <Tiano.h>\r
+#endif\r
+#include <Hpet.h>\r
+#include "AcpiTablePlatform.h"\r
+\r
+// Hpet Table\r
+EFI_ACPI_HIGH_PRECISION_EVENT_TIMER_TABLE_HEADER HPET = {\r
+ {\r
+ EFI_ACPI_3_0_HIGH_PRECISION_EVENT_TIMER_TABLE_SIGNATURE,\r
+ sizeof (EFI_ACPI_HIGH_PRECISION_EVENT_TIMER_TABLE_HEADER),\r
+ EFI_ACPI_HIGH_PRECISION_EVENT_TIMER_TABLE_REVISION,\r
+ 0, // to make sum of entire table == 0\r
+ EFI_ACPI_OEM_ID, // OEMID is a 6 bytes long field\r
+ EFI_ACPI_OEM_TABLE_ID, // OEM table identification(8 bytes long)\r
+ EFI_ACPI_OEM_REVISION, // OEM revision\r
+ EFI_ACPI_CREATOR_ID, // ASL compiler vendor ID\r
+ EFI_ACPI_CREATOR_REVISION // ASL compiler revision number\r
+ },\r
+ 0x0, // EventTimerBlockId\r
+ {\r
+ 0x00, // Address_Space_ID = System Memory\r
+ 0x40, // Register_Bit_Width = 32 bits, mentioned about write failures when in 64bit in SCU HAS\r
+ 0x00, // Register_Bit_offset\r
+ 0x00, // Dword access\r
+ HPET_BASE_ADDRESS, // Base addresse of HPET\r
+ },\r
+ 0x0, // Only HPET's _UID in Namespace\r
+ MAIN_COUNTER_MIN_PERIODIC_CLOCK_TICKS,\r
+ 0x0\r
+};\r
+\r
+VOID*\r
+ReferenceAcpiTable (\r
+ VOID\r
+ )\r
+{\r
+ //\r
+ // Reference the table being generated to prevent the optimizer from\r
+ // removing the data structure from the executable\r
+ //\r
+ return (VOID*)&HPET;\r
+}\r
--- /dev/null
+/*++\r
+\r
+Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved\r
+\r
+ This program and the accompanying materials are licensed and made available under\r
+ the terms and conditions of the BSD License that accompanies this distribution.\r
+ The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php.\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+\r
+Module Name:\r
+\r
+ INTELGFX.ASL\r
+\r
+Abstract:\r
+\r
+ IGD OpRegion/Software ACPI Reference Code for the Baytrail Family.\r
+\r
+--*/\r
+\r
+// Enable/Disable Output Switching. In WIN2K/WINXP, _DOS = 0 will\r
+// get called during initialization to prepare for an ACPI Display\r
+// Switch Event. During an ACPI Display Switch, the OS will call\r
+// _DOS = 2 immediately after a Notify=0x80 to temporarily disable\r
+// all Display Switching. After ACPI Display Switching is complete,\r
+// the OS will call _DOS = 0 to re-enable ACPI Display Switching.\r
+\r
+Method(_DOS,1)\r
+{\r
+ // Store Display Switching and LCD brightness BIOS control bit\r
+ Store(And(Arg0,7),DSEN)\r
+}\r
+\r
+// Enumerate the Display Environment. This method will return\r
+// valid addresses for all display device encoders present in the\r
+// system. The Miniport Driver will reject the addresses for every\r
+// encoder that does not have an attached display device. After\r
+// enumeration is complete, the OS will call the _DGS methods\r
+// during a display switch only for the addresses accepted by the\r
+// Miniport Driver. For hot-insertion and removal of display\r
+// devices, a re-enumeration notification will be required so the\r
+// address of the newly present display device will be accepted by\r
+// the Miniport Driver.\r
+\r
+Method(_DOD, 0, Serialized)\r
+{\r
+ Store(0, NDID)\r
+ If(LNotEqual(DIDL, Zero))\r
+ {\r
+ Store(SDDL(DIDL),DID1)\r
+ }\r
+ If(LNotEqual(DDL2, Zero))\r
+ {\r
+ Store(SDDL(DDL2),DID2)\r
+ }\r
+ If(LNotEqual(DDL3, Zero))\r
+ {\r
+ Store(SDDL(DDL3),DID3)\r
+ }\r
+ If(LNotEqual(DDL4, Zero))\r
+ {\r
+ Store(SDDL(DDL4),DID4)\r
+ }\r
+ If(LNotEqual(DDL5, Zero))\r
+ {\r
+ Store(SDDL(DDL5),DID5)\r
+ }\r
+\r
+ // TODO - This level of flexibility is not needed for a true\r
+ // OEM design. Simply determine the greatest number of\r
+ // encoders the platform will suppport then remove all\r
+ // return packages beyond that value. Note that for\r
+ // current silicon, the maximum number of encoders\r
+ // possible is 5.\r
+\r
+ If(LEqual(NDID,1))\r
+ {\r
+ If (LNOTEqual (ISPD, 0))\r
+ {\r
+ Name(TMP0,Package() {0xFFFFFFFF,0xFFFFFFFF})\r
+ Store(Or(0x10000,DID1),Index(TMP0,0))\r
+ //Add ISP device to GFX0\r
+ Store(0x00020F38, Index(TMP0,1))\r
+ Return(TMP0)\r
+ } Else\r
+ {\r
+ Name(TMP1,Package() {0xFFFFFFFF})\r
+ Store(Or(0x10000,DID1),Index(TMP1,0))\r
+ Return(TMP1)\r
+ }\r
+ }\r
+\r
+ If(LEqual(NDID,2))\r
+ {\r
+ If (LNOTEqual (ISPD, 0))\r
+ {\r
+ Name(TMP2,Package() {0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF})\r
+ Store(Or(0x10000,DID1),Index(TMP2,0))\r
+ Store(Or(0x10000,DID2),Index(TMP2,1))\r
+ //Add ISP device to GFX0\r
+ Store(0x00020F38, Index(TMP2,2))\r
+ Return(TMP2)\r
+ } Else\r
+ {\r
+ Name(TMP3,Package() {0xFFFFFFFF, 0xFFFFFFFF})\r
+ Store(Or(0x10000,DID1),Index(TMP3,0))\r
+ Store(Or(0x10000,DID2),Index(TMP3,1))\r
+ Return(TMP3)\r
+ }\r
+ }\r
+\r
+ If(LEqual(NDID,3))\r
+ {\r
+ If (LNOTEqual (ISPD, 0))\r
+ {\r
+ Name(TMP4,Package() {0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,0xFFFFFFFF})\r
+ Store(Or(0x10000,DID1),Index(TMP4,0))\r
+ Store(Or(0x10000,DID2),Index(TMP4,1))\r
+ Store(Or(0x10000,DID3),Index(TMP4,2))\r
+ //Add ISP device to GFX0\r
+ Store(0x00020F38, Index(TMP4,3))\r
+ Return(TMP4)\r
+ } Else\r
+ {\r
+ Name(TMP5,Package() {0xFFFFFFFF, 0xFFFFFFFF,0xFFFFFFFF})\r
+ Store(Or(0x10000,DID1),Index(TMP5,0))\r
+ Store(Or(0x10000,DID2),Index(TMP5,1))\r
+ Store(Or(0x10000,DID3),Index(TMP5,2))\r
+ Return(TMP5)\r
+ }\r
+ }\r
+\r
+ If(LEqual(NDID,4))\r
+ {\r
+ If (LNOTEqual (ISPD, 0))\r
+ {\r
+ Name(TMP6,Package() {0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF})\r
+ Store(Or(0x10000,DID1),Index(TMP6,0))\r
+ Store(Or(0x10000,DID2),Index(TMP6,1))\r
+ Store(Or(0x10000,DID3),Index(TMP6,2))\r
+ Store(Or(0x10000,DID4),Index(TMP6,3))\r
+ //Add ISP device to GFX0\r
+ Store(0x00020F38, Index(TMP6,4))\r
+ Return(TMP6)\r
+ } Else\r
+ {\r
+ Name(TMP7,Package() {0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF})\r
+ Store(Or(0x10000,DID1),Index(TMP7,0))\r
+ Store(Or(0x10000,DID2),Index(TMP7,1))\r
+ Store(Or(0x10000,DID3),Index(TMP7,2))\r
+ Store(Or(0x10000,DID4),Index(TMP7,3))\r
+ Return(TMP7)\r
+ }\r
+ }\r
+\r
+ If(LGreater(NDID,4))\r
+ {\r
+ If (LNOTEqual (ISPD, 0))\r
+ {\r
+ Name(TMP8,Package() {0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF})\r
+ Store(Or(0x10000,DID1),Index(TMP8,0))\r
+ Store(Or(0x10000,DID2),Index(TMP8,1))\r
+ Store(Or(0x10000,DID3),Index(TMP8,2))\r
+ Store(Or(0x10000,DID4),Index(TMP8,3))\r
+ Store(Or(0x10000,DID5),Index(TMP8,4))\r
+ //Add ISP device to GFX0\r
+ Store(0x00020F38, Index(TMP8,5))\r
+ Return(TMP8)\r
+ } Else\r
+ {\r
+ Name(TMP9,Package() {0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF})\r
+ Store(Or(0x10000,DID1),Index(TMP9,0))\r
+ Store(Or(0x10000,DID2),Index(TMP9,1))\r
+ Store(Or(0x10000,DID3),Index(TMP9,2))\r
+ Store(Or(0x10000,DID4),Index(TMP9,3))\r
+ Store(Or(0x10000,DID5),Index(TMP9,4))\r
+ Return(TMP9)\r
+ }\r
+ }\r
+\r
+ // If nothing else, return Unknown LFP.\r
+ // (Prevents compiler warning.)\r
+\r
+ //Add ISP device to GFX0\r
+ If (LNOTEqual (ISPD, 0))\r
+ {\r
+ Return(Package() {0x00000400, 0x00020F38})\r
+ } Else\r
+ {\r
+ Return(Package() {0x00000400})\r
+ }\r
+}\r
+\r
+Device(DD01)\r
+{\r
+\r
+ // Return Unique ID.\r
+\r
+ Method(_ADR,0,Serialized)\r
+ {\r
+ If(LEqual(And(0x0F00,DID1),0x400))\r
+ {\r
+ Store(0x1, EDPV)\r
+ Store(DID1, DIDX)\r
+ Return(1)\r
+ }\r
+ If(LEqual(DID1,0))\r
+ {\r
+ Return(1)\r
+ }\r
+ Else\r
+ {\r
+ Return(And(0xFFFF,DID1))\r
+ }\r
+ }\r
+\r
+ // Return the Current Status.\r
+\r
+ Method(_DCS,0)\r
+ {\r
+ Return(CDDS(DID1))\r
+ }\r
+\r
+ // Query Graphics State (active or inactive).\r
+\r
+ Method(_DGS,0)\r
+ {\r
+ Return(NDDS(DID1))\r
+ }\r
+\r
+ // Device Set State.\r
+\r
+ // _DSS Table:\r
+ //\r
+ // BIT31 BIT30 Execution\r
+ // 0 0 Don't implement.\r
+ // 0 1 Cache change. Nothing to Implement.\r
+ // 1 0 Don't Implement.\r
+ // 1 1 Display Switch Complete. Implement.\r
+\r
+ Method(_DSS,1)\r
+ {\r
+ If(LEqual(And(Arg0,0xC0000000),0xC0000000))\r
+ {\r
+\r
+ // State change was performed by the\r
+ // Video Drivers. Simply update the\r
+ // New State.\r
+\r
+ Store(NSTE,CSTE)\r
+ }\r
+ }\r
+}\r
+\r
+Device(DD02)\r
+{\r
+\r
+ // Return Unique ID.\r
+\r
+ Method(_ADR,0,Serialized)\r
+ {\r
+ If(LEqual(And(0x0F00,DID2),0x400))\r
+ {\r
+ Store(0x2, EDPV)\r
+ Store(DID2, DIDX)\r
+ Return(2)\r
+ }\r
+ If(LEqual(DID2,0))\r
+ {\r
+ Return(2)\r
+ }\r
+ Else\r
+ {\r
+ Return(And(0xFFFF,DID2))\r
+ }\r
+ }\r
+\r
+ // Return the Current Status.\r
+\r
+ Method(_DCS,0)\r
+ {\r
+ Return(CDDS(DID2))\r
+ }\r
+\r
+ // Query Graphics State (active or inactive).\r
+\r
+ Method(_DGS,0)\r
+ {\r
+ // Return the Next State.\r
+ Return(NDDS(DID2))\r
+ }\r
+\r
+ // Device Set State. (See table above.)\r
+\r
+ Method(_DSS,1)\r
+ {\r
+ If(LEqual(And(Arg0,0xC0000000),0xC0000000))\r
+ {\r
+\r
+ // State change was performed by the\r
+ // Video Drivers. Simply update the\r
+ // New State.\r
+\r
+ Store(NSTE,CSTE)\r
+ }\r
+ }\r
+}\r
+\r
+Device(DD03)\r
+{\r
+\r
+ // Return Unique ID.\r
+\r
+ Method(_ADR,0,Serialized)\r
+ {\r
+ If(LEqual(And(0x0F00,DID3),0x400))\r
+ {\r
+ Store(0x3, EDPV)\r
+ Store(DID3, DIDX)\r
+ Return(3)\r
+ }\r
+ If(LEqual(DID3,0))\r
+ {\r
+ Return(3)\r
+ }\r
+ Else\r
+ {\r
+ Return(And(0xFFFF,DID3))\r
+ }\r
+ }\r
+\r
+ // Return the Current Status.\r
+\r
+ Method(_DCS,0)\r
+ {\r
+ If(LEqual(DID3,0))\r
+ {\r
+ Return(0x0B)\r
+ }\r
+ Else\r
+ {\r
+ Return(CDDS(DID3))\r
+ }\r
+ }\r
+\r
+ // Query Graphics State (active or inactive).\r
+\r
+ Method(_DGS,0)\r
+ {\r
+ Return(NDDS(DID3))\r
+ }\r
+\r
+ // Device Set State. (See table above.)\r
+\r
+ Method(_DSS,1)\r
+ {\r
+ If(LEqual(And(Arg0,0xC0000000),0xC0000000))\r
+ {\r
+ // State change was performed by the\r
+ // Video Drivers. Simply update the\r
+ // New State.\r
+\r
+ Store(NSTE,CSTE)\r
+ }\r
+ }\r
+}\r
+\r
+Device(DD04)\r
+{\r
+\r
+ // Return Unique ID.\r
+\r
+ Method(_ADR,0,Serialized)\r
+ {\r
+ If(LEqual(And(0x0F00,DID4),0x400))\r
+ {\r
+ Store(0x4, EDPV)\r
+ Store(DID4, DIDX)\r
+ Return(4)\r
+ }\r
+ If(LEqual(DID4,0))\r
+ {\r
+ Return(4)\r
+ }\r
+ Else\r
+ {\r
+ Return(And(0xFFFF,DID4))\r
+ }\r
+ }\r
+\r
+ // Return the Current Status.\r
+\r
+ Method(_DCS,0)\r
+ {\r
+ If(LEqual(DID4,0))\r
+ {\r
+ Return(0x0B)\r
+ }\r
+ Else\r
+ {\r
+ Return(CDDS(DID4))\r
+ }\r
+ }\r
+\r
+ // Query Graphics State (active or inactive).\r
+\r
+ Method(_DGS,0)\r
+ {\r
+ Return(NDDS(DID4))\r
+ }\r
+\r
+ // Device Set State. (See table above.)\r
+\r
+ Method(_DSS,1)\r
+ {\r
+ If(LEqual(And(Arg0,0xC0000000),0xC0000000))\r
+ {\r
+\r
+ // State change was performed by the\r
+ // Video Drivers. Simply update the\r
+ // New State.\r
+\r
+ Store(NSTE,CSTE)\r
+ }\r
+ }\r
+}\r
+\r
+\r
+Device(DD05)\r
+{\r
+\r
+ // Return Unique ID.\r
+\r
+ Method(_ADR,0,Serialized)\r
+ {\r
+ If(LEqual(And(0x0F00,DID5),0x400))\r
+ {\r
+ Store(0x5, EDPV)\r
+ Store(DID5, DIDX)\r
+ Return(5)\r
+ }\r
+ If(LEqual(DID5,0))\r
+ {\r
+ Return(5)\r
+ }\r
+ Else\r
+ {\r
+ Return(And(0xFFFF,DID5))\r
+ }\r
+ }\r
+\r
+ // Return the Current Status.\r
+\r
+ Method(_DCS,0)\r
+ {\r
+ If(LEqual(DID5,0))\r
+ {\r
+ Return(0x0B)\r
+ }\r
+ Else\r
+ {\r
+ Return(CDDS(DID5))\r
+ }\r
+ }\r
+\r
+ // Query Graphics State (active or inactive).\r
+\r
+ Method(_DGS,0)\r
+ {\r
+ Return(NDDS(DID5))\r
+ }\r
+\r
+ // Device Set State. (See table above.)\r
+\r
+ Method(_DSS,1)\r
+ {\r
+ If(LEqual(And(Arg0,0xC0000000),0xC0000000))\r
+ {\r
+ // State change was performed by the\r
+ // Video Drivers. Simply update the\r
+ // New State.\r
+\r
+ Store(NSTE,CSTE)\r
+ }\r
+ }\r
+}\r
+\r
+\r
+Device(DD06)\r
+{\r
+\r
+ // Return Unique ID.\r
+\r
+ Method(_ADR,0,Serialized)\r
+ {\r
+ If(LEqual(And(0x0F00,DID6),0x400))\r
+ {\r
+ Store(0x6, EDPV)\r
+ Store(DID6, DIDX)\r
+ Return(6)\r
+ }\r
+ If(LEqual(DID6,0))\r
+ {\r
+ Return(6)\r
+ }\r
+ Else\r
+ {\r
+ Return(And(0xFFFF,DID6))\r
+ }\r
+ }\r
+\r
+ // Return the Current Status.\r
+\r
+ Method(_DCS,0)\r
+ {\r
+ If(LEqual(DID6,0))\r
+ {\r
+ Return(0x0B)\r
+ }\r
+ Else\r
+ {\r
+ Return(CDDS(DID6))\r
+ }\r
+ }\r
+\r
+ // Query Graphics State (active or inactive).\r
+\r
+ Method(_DGS,0)\r
+ {\r
+ Return(NDDS(DID6))\r
+ }\r
+\r
+ // Device Set State. (See table above.)\r
+\r
+ Method(_DSS,1)\r
+ {\r
+ If(LEqual(And(Arg0,0xC0000000),0xC0000000))\r
+ {\r
+ // State change was performed by the\r
+ // Video Drivers. Simply update the\r
+ // New State.\r
+\r
+ Store(NSTE,CSTE)\r
+ }\r
+ }\r
+}\r
+\r
+\r
+Device(DD07)\r
+{\r
+\r
+ // Return Unique ID.\r
+\r
+ Method(_ADR,0,Serialized)\r
+ {\r
+ If(LEqual(And(0x0F00,DID7),0x400))\r
+ {\r
+ Store(0x7, EDPV)\r
+ Store(DID7, DIDX)\r
+ Return(7)\r
+ }\r
+ If(LEqual(DID7,0))\r
+ {\r
+ Return(7)\r
+ }\r
+ Else\r
+ {\r
+ Return(And(0xFFFF,DID7))\r
+ }\r
+ }\r
+\r
+ // Return the Current Status.\r
+\r
+ Method(_DCS,0)\r
+ {\r
+ If(LEqual(DID7,0))\r
+ {\r
+ Return(0x0B)\r
+ }\r
+ Else\r
+ {\r
+ Return(CDDS(DID7))\r
+ }\r
+ }\r
+\r
+ // Query Graphics State (active or inactive).\r
+\r
+ Method(_DGS,0)\r
+ {\r
+ Return(NDDS(DID7))\r
+ }\r
+\r
+ // Device Set State. (See table above.)\r
+\r
+ Method(_DSS,1)\r
+ {\r
+ If(LEqual(And(Arg0,0xC0000000),0xC0000000))\r
+ {\r
+ // State change was performed by the\r
+ // Video Drivers. Simply update the\r
+ // New State.\r
+\r
+ Store(NSTE,CSTE)\r
+ }\r
+ }\r
+}\r
+\r
+\r
+Device(DD08)\r
+{\r
+\r
+ // Return Unique ID.\r
+\r
+ Method(_ADR,0,Serialized)\r
+ {\r
+ If(LEqual(And(0x0F00,DID8),0x400))\r
+ {\r
+ Store(0x8, EDPV)\r
+ Store(DID8, DIDX)\r
+ Return(8)\r
+ }\r
+ If(LEqual(DID8,0))\r
+ {\r
+ Return(8)\r
+ }\r
+ Else\r
+ {\r
+ Return(And(0xFFFF,DID8))\r
+ }\r
+ }\r
+\r
+ // Return the Current Status.\r
+\r
+ Method(_DCS,0)\r
+ {\r
+ If(LEqual(DID8,0))\r
+ {\r
+ Return(0x0B)\r
+ }\r
+ Else\r
+ {\r
+ Return(CDDS(DID8))\r
+ }\r
+ }\r
+\r
+ // Query Graphics State (active or inactive).\r
+\r
+ Method(_DGS,0)\r
+ {\r
+ Return(NDDS(DID8))\r
+ }\r
+\r
+ // Device Set State. (See table above.)\r
+\r
+ Method(_DSS,1)\r
+ {\r
+ If(LEqual(And(Arg0,0xC0000000),0xC0000000))\r
+ {\r
+ // State change was performed by the\r
+ // Video Drivers. Simply update the\r
+ // New State.\r
+\r
+ Store(NSTE,CSTE)\r
+ }\r
+ }\r
+}\r
+\r
+//device for eDP\r
+Device(DD1F)\r
+{\r
+ // Return Unique ID.\r
+\r
+ Method(_ADR,0,Serialized)\r
+ {\r
+ If(LEqual(EDPV, 0x0))\r
+ {\r
+ Return(0x1F)\r
+ }\r
+ Else\r
+ {\r
+ Return(And(0xFFFF,DIDX))\r
+ }\r
+ }\r
+\r
+ // Return the Current Status.\r
+\r
+ Method(_DCS,0)\r
+ {\r
+ If(LEqual(EDPV, 0x0))\r
+ {\r
+ Return(0x00)\r
+ }\r
+ Else\r
+ {\r
+ Return(CDDS(DIDX))\r
+ }\r
+ }\r
+\r
+ // Query Graphics State (active or inactive).\r
+\r
+ Method(_DGS,0)\r
+ {\r
+ Return(NDDS(DIDX))\r
+ }\r
+\r
+ // Device Set State. (See table above.)\r
+\r
+ Method(_DSS,1)\r
+ {\r
+ If(LEqual(And(Arg0,0xC0000000),0xC0000000))\r
+ {\r
+ // State change was performed by the\r
+ // Video Drivers. Simply update the\r
+ // New State.\r
+ Store(NSTE,CSTE)\r
+ }\r
+ }\r
+ // Query List of Brightness Control Levels Supported.\r
+\r
+ Method(_BCL,0)\r
+ {\r
+ // List of supported brightness levels in the following sequence.\r
+\r
+ // Level when machine has full power.\r
+ // Level when machine is on batteries.\r
+ // Other supported levels.\r
+ Return(Package() {80, 50, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 100})\r
+ }\r
+\r
+ // Set the Brightness Level.\r
+\r
+ Method (_BCM,1)\r
+ {\r
+ // Set the requested level if it is between 0 and 100%.\r
+\r
+ If(LAnd(LGreaterEqual(Arg0,0),LLessEqual(Arg0,100)))\r
+ {\r
+ \_SB.PCI0.GFX0.AINT(1, Arg0)\r
+ Store(Arg0,BRTL) // Store Brightness Level.\r
+ }\r
+ }\r
+\r
+ // Brightness Query Current level.\r
+\r
+ Method (_BQC,0)\r
+ {\r
+ Return(BRTL)\r
+ }\r
+}\r
+\r
+Method(SDDL,1)\r
+{\r
+ Increment(NDID)\r
+ Store(And(Arg0,0xF0F),Local0)\r
+ Or(0x80000000,Local0, Local1)\r
+ If(LEqual(DIDL,Local0))\r
+ {\r
+ Return(Local1)\r
+ }\r
+ If(LEqual(DDL2,Local0))\r
+ {\r
+ Return(Local1)\r
+ }\r
+ If(LEqual(DDL3,Local0))\r
+ {\r
+ Return(Local1)\r
+ }\r
+ If(LEqual(DDL4,Local0))\r
+ {\r
+ Return(Local1)\r
+ }\r
+ If(LEqual(DDL5,Local0))\r
+ {\r
+ Return(Local1)\r
+ }\r
+ If(LEqual(DDL6,Local0))\r
+ {\r
+ Return(Local1)\r
+ }\r
+ If(LEqual(DDL7,Local0))\r
+ {\r
+ Return(Local1)\r
+ }\r
+ If(LEqual(DDL8,Local0))\r
+ {\r
+ Return(Local1)\r
+ }\r
+ Return(0)\r
+}\r
+\r
+Method(CDDS,1)\r
+{\r
+ Store(And(Arg0,0xF0F),Local0)\r
+\r
+ If(LEqual(0, Local0))\r
+ {\r
+ Return(0x1D)\r
+ }\r
+ If(LEqual(CADL, Local0))\r
+ {\r
+ Return(0x1F)\r
+ }\r
+ If(LEqual(CAL2, Local0))\r
+ {\r
+ Return(0x1F)\r
+ }\r
+ If(LEqual(CAL3, Local0))\r
+ {\r
+ Return(0x1F)\r
+ }\r
+ If(LEqual(CAL4, Local0))\r
+ {\r
+ Return(0x1F)\r
+ }\r
+ If(LEqual(CAL5, Local0))\r
+ {\r
+ Return(0x1F)\r
+ }\r
+ If(LEqual(CAL6, Local0))\r
+ {\r
+ Return(0x1F)\r
+ }\r
+ If(LEqual(CAL7, Local0))\r
+ {\r
+ Return(0x1F)\r
+ }\r
+ If(LEqual(CAL8, Local0))\r
+ {\r
+ Return(0x1F)\r
+ }\r
+ Return(0x1D)\r
+}\r
+\r
+Method(NDDS,1)\r
+{\r
+ Store(And(Arg0,0xF0F),Local0)\r
+\r
+ If(LEqual(0, Local0))\r
+ {\r
+ Return(0)\r
+ }\r
+ If(LEqual(NADL, Local0))\r
+ {\r
+ Return(1)\r
+ }\r
+ If(LEqual(NDL2, Local0))\r
+ {\r
+ Return(1)\r
+ }\r
+ If(LEqual(NDL3, Local0))\r
+ {\r
+ Return(1)\r
+ }\r
+ If(LEqual(NDL4, Local0))\r
+ {\r
+ Return(1)\r
+ }\r
+ If(LEqual(NDL5, Local0))\r
+ {\r
+ Return(1)\r
+ }\r
+ If(LEqual(NDL6, Local0))\r
+ {\r
+ Return(1)\r
+ }\r
+ If(LEqual(NDL7, Local0))\r
+ {\r
+ Return(1)\r
+ }\r
+ If(LEqual(NDL8, Local0))\r
+ {\r
+ Return(1)\r
+ }\r
+ Return(0)\r
+}\r
+\r
+//\r
+// Include IGD OpRegion/Software SCI interrupt handler which is use by\r
+// the graphics drivers to request data from system BIOS.\r
+//\r
+include("IgdOpRn.ASL")\r
--- /dev/null
+/*++\r
+\r
+Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved\r
+\r
+ This program and the accompanying materials are licensed and made available under\r
+ the terms and conditions of the BSD License that accompanies this distribution.\r
+ The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php.\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+\r
+Module Name:\r
+\r
+ INTELISPDev2.ASL\r
+\r
+Abstract:\r
+\r
+ ISP Exist as B0D2F0 Software ACPI Reference Code for the Baytrail Family.\r
+\r
+--*/\r
+////Device ISP0\r
+Device(ISP0)\r
+{\r
+ Name(_ADR, 0x0F38)\r
+ //Name (_HID, "80860F38")\r
+ //Name (_CID, "80860F38")\r
+ Name(_DDN, "VLV2 ISP - 80860F38")\r
+ Name(_UID, 0x01)\r
+\r
+ Method (_STA, 0, NotSerialized)\r
+ {\r
+ If(LEqual(ISPD,1)) //Dev2 need report ISP0 as GFX0 child\r
+ {\r
+ Return (0xF)\r
+ }\r
+ Else\r
+ {\r
+ Return (0x0)\r
+ }\r
+ }\r
+ Name(SBUF,ResourceTemplate ()\r
+ {\r
+ Memory32Fixed (ReadWrite, 0x00000000, 0x00400000, ISP0)\r
+ })\r
+ Method(_CRS, 0x0, NotSerialized)\r
+ {\r
+ Return (SBUF)\r
+ }\r
+ Method (_SRS, 0x1, NotSerialized)\r
+ {\r
+ }\r
+ Method (_DIS, 0x0, NotSerialized)\r
+ {\r
+ }\r
+ Method(_DSM, 0x4, NotSerialized)\r
+ {\r
+ If (LEqual (Arg0, 0x01))\r
+ {\r
+ ///Switch ISP to D3H\r
+ Return (0x01)\r
+ }\r
+ Elseif (LEqual (Arg0, 0x02))\r
+ {\r
+ //Switch ISP to D0\r
+ Return (0x02)\r
+ }\r
+ Else\r
+ {\r
+ //Do nothing\r
+ Return (0x0F)\r
+ }\r
+ }\r
+} ///End ISP0\r
+\r
--- /dev/null
+/*++\r
+\r
+Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved\r
+\r
+ This program and the accompanying materials are licensed and made available under\r
+ the terms and conditions of the BSD License that accompanies this distribution.\r
+ The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php.\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+\r
+Module Name:\r
+\r
+ IgdOGBDA.ASL\r
+\r
+Abstract:\r
+\r
+ IGD OpRegion/Software SCI Reference Code for the Baytrail Family.\r
+ This file contains Get BIOS Data Area funciton support for\r
+ the Integrated Graphics Device (IGD) OpRegion/Software SCI mechanism.\r
+\r
+--*/\r
+\r
+\r
+Method (GBDA, 0, Serialized)\r
+{\r
+\r
+ // Supported calls: Sub-function 0\r
+\r
+ If (LEqual(GESF, 0))\r
+ {\r
+ //<TODO> Update implementation specific supported calls. Reference\r
+ // code is set to Intel's validated implementation.\r
+\r
+ Store(0x0000279, PARM)\r
+\r
+ Store(Zero, GESF) // Clear the exit parameter\r
+ Return(SUCC) // Success\r
+ }\r
+\r
+ // Requested callbacks: Sub-function 1\r
+\r
+ If (LEqual(GESF, 1))\r
+ {\r
+\r
+ //<TODO> Update implementation specific system BIOS requested call\r
+ // back functions. Call back functions are where the driver calls the\r
+ // system BIOS at function indicated event.\r
+\r
+ Store(0x00000240, PARM)\r
+\r
+ Store(Zero, GESF) // Clear the exit parameter\r
+ Return(SUCC) // Success\r
+ }\r
+\r
+ // Get Boot display Preferences: Sub-function 4\r
+\r
+ If (LEqual(GESF, 4))\r
+ {\r
+\r
+ //<TODO> Update the implementation specific Get Boot Display\r
+ // Preferences function.\r
+\r
+ And(PARM, 0xEFFF0000, PARM) // PARM[30:16] = Boot device ports\r
+ And(PARM, ShiftLeft(DeRefOf(Index(DBTB, IBTT)), 16), PARM)\r
+ Or(IBTT, PARM, PARM) // PARM[7:0] = Boot device type\r
+\r
+ Store(Zero, GESF) // Clear the exit parameter\r
+ Return(SUCC) // Success\r
+ }\r
+\r
+ // Panel details: Sub-function 5\r
+\r
+ If (LEqual(GESF, 5))\r
+ {\r
+\r
+ //<TODO> Update the implementation specific Get Panel Details\r
+ // function.\r
+\r
+ Store(IPSC, PARM) // Report the scaling setting\r
+ Or(PARM, ShiftLeft(IPAT, 8), PARM)\r
+ Add(PARM, 0x100, PARM) // Adjust panel type, 0 = VBT default\r
+ Or(PARM, ShiftLeft(LIDS, 16), PARM) // Report the lid state\r
+ Add(PARM, 0x10000, PARM) // Adjust the lid state, 0 = Unknown\r
+ Or(PARM, ShiftLeft(IBLC, 18), PARM) // Report the BLC setting\r
+ Or(PARM, ShiftLeft(IBIA, 20), PARM) // Report the BIA setting\r
+ Store(Zero, GESF)\r
+ Return(SUCC)\r
+ }\r
+\r
+ // TV-standard/Video-connector: Sub-function 6\r
+\r
+ If (LEqual(GESF, 6))\r
+ {\r
+\r
+ //<TODO> Update the implementation specific Get\r
+ // TV-standard/Video-connectorPanel function.\r
+\r
+ Store(ITVF, PARM)\r
+ Or(PARM, ShiftLeft(ITVM, 4), PARM)\r
+ Store(Zero, GESF)\r
+ Return(SUCC)\r
+ }\r
+\r
+ // Internal graphics: Sub-function 7\r
+\r
+ If (LEqual(GESF, 7))\r
+ {\r
+ Store(GIVD, PARM) // PARM[0] - VGA mode(1=VGA)\r
+ Xor(PARM, 1, PARM) // Invert the VGA mode polarity\r
+ Or(PARM, ShiftLeft(GMFN, 1), PARM) // PARM[1] - # IGD PCI functions-1\r
+ // PARM[3:2] - Reserved\r
+ // PARM[4] - IGD D3 support(0=cold)\r
+ // PARM[10:5] - Reserved\r
+ Or(PARM, ShiftLeft(3, 11), PARM) // PARM[12:11] - DVMT mode(11b = 5.0)\r
+\r
+ //\r
+ // Report DVMT 5.0 Total Graphics memory size.\r
+ //\r
+ Or(PARM, ShiftLeft(IDMS, 17), PARM) // Bits 20:17 are for Gfx total memory size\r
+\r
+ // If the "Set Internal Graphics" call is supported, the modified\r
+ // settings flag must be programmed per the specification. This means\r
+ // that the flag must be set to indicate that system BIOS requests\r
+ // these settings. Once "Set Internal Graphics" is called, the\r
+ // modified settings flag must be cleared on all subsequent calls to\r
+ // this function.\r
+\r
+ // Report the graphics frequency based on DISPLAY_CLOCK_FREQUENCY_ENCODING [MMADR+0x20C8]\r
+\r
+ Or(ShiftLeft(Derefof(Index(CDCT, \_SB.PCI0.GFX0.MCHK.DCFE)), 21),PARM, PARM)\r
+\r
+ Store(1, GESF) // Set the modified settings flag\r
+ Return(SUCC)\r
+ }\r
+\r
+ // Spread spectrum clocks: Sub-function 10\r
+\r
+ If (LEqual(GESF, 10))\r
+ {\r
+\r
+ Store(0, PARM) // Assume SSC is disabled\r
+\r
+ If(ISSC)\r
+ {\r
+ Or(PARM, 3, PARM) // If SSC enabled, return SSC1+Enabled\r
+ }\r
+\r
+ Store(0, GESF) // Set the modified settings flag\r
+ Return(SUCC) // Success\r
+ }\r
+\r
+\r
+ // A call to a reserved "Get BIOS data" function was received.\r
+\r
+ Store(Zero, GESF) // Clear the exit parameter\r
+ Return(CRIT) // Reserved, "Critical failure"\r
+}\r
--- /dev/null
+/*++\r
+\r
+Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved\r
+\r
+ This program and the accompanying materials are licensed and made available under\r
+ the terms and conditions of the BSD License that accompanies this distribution.\r
+ The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php.\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+\r
+Module Name:\r
+\r
+ IgdOMOBF.ASL\r
+\r
+Abstract:\r
+\r
+ IGD OpRegion/Software SCI Reference Code for the Baytrail Family.\r
+ This file contains ASL code with the purpose of handling events\r
+ i.e. hotkeys and other system interrupts.\r
+\r
+--*/\r
+\r
+\r
+// Notes:\r
+// 1. The following routines are to be called from the appropriate event\r
+// handlers.\r
+// 2. This code cannot comprehend the exact implementation in the OEM's BIOS.\r
+// Therefore, an OEM must call these methods from the existing event\r
+// handler infrastructure. Details on when/why to call each method is\r
+// included in the method header under the "usage" section.\r
+\r
+\r
+/************************************************************************;\r
+;* ACPI Notification Methods\r
+;************************************************************************/\r
+\r
+\r
+/************************************************************************;\r
+;*\r
+;* Name: PDRD\r
+;*\r
+;* Description: Check if the graphics driver is ready to process\r
+;* notifications and video extensions.\r
+;*\r
+;* Usage: This method is to be called prior to performing any\r
+;* notifications or handling video extensions.\r
+;* Ex: If (PDRD()) {Return (FAIL)}\r
+;*\r
+;* Input: None\r
+;*\r
+;* Output: None\r
+;*\r
+;* References: DRDY (Driver ready status), ASLP (Driver recommended\r
+;* sleep timeout value).\r
+;*\r
+;************************************************************************/\r
+\r
+Method(PDRD)\r
+{\r
+ If(LNot(DRDY))\r
+ {\r
+\r
+ // Sleep for ASLP milliseconds if the driver is not ready.\r
+\r
+ Sleep(ASLP)\r
+ }\r
+\r
+ // If DRDY is clear, the driver is not ready. If the return value is\r
+ // !=0, do not perform any notifications or video extension handling.\r
+\r
+ Return(LNot(DRDY))\r
+}\r
+\r
+\r
+/************************************************************************;\r
+;*\r
+;* Name: PSTS\r
+;*\r
+;* Description: Check if the graphics driver has completed the previous\r
+;* "notify" command.\r
+;*\r
+;* Usage: This method is called before every "notify" command. A\r
+;* "notify" should only be set if the driver has completed the\r
+;* previous command. Else, ignore the event and exit the parent\r
+;* method.\r
+;* Ex: If (PSTS()) {Return (FAIL)}\r
+;*\r
+;* Input: None\r
+;*\r
+;* Output: None\r
+;*\r
+;* References: CSTS (Notification status), ASLP (Driver recommended sleep\r
+;* timeout value).\r
+;*\r
+;************************************************************************/\r
+\r
+Method(PSTS)\r
+{\r
+ If(LGreater(CSTS, 2))\r
+ {\r
+ // Sleep for ASLP milliseconds if the status is not "success,\r
+ // failure, or pending"\r
+ //\r
+ Sleep(ASLP)\r
+ }\r
+\r
+ Return(LEqual(CSTS, 3)) // Return True if still Dispatched\r
+}\r
+\r
+\r
+/************************************************************************;\r
+;*\r
+;* Name: GNOT\r
+;*\r
+;* Description: Call the appropriate methods to query the graphics driver\r
+;* status. If all methods return success, do a notification of\r
+;* the graphics device.\r
+;*\r
+;* Usage: This method is to be called when a graphics device\r
+;* notification is required (display switch hotkey, etc).\r
+;*\r
+;* Input: Arg0 = Current event type:\r
+;* 1 = display switch\r
+;* 2 = lid\r
+;* 3 = dock\r
+;* Arg1 = Notification type:\r
+;* 0 = Re-enumeration\r
+;* 0x80 = Display switch\r
+;*\r
+;* Output: Returns 0 = success, 1 = failure\r
+;*\r
+;* References: PDRD and PSTS methods. OSYS (OS version)\r
+;*\r
+;************************************************************************/\r
+\r
+Method(GNOT, 2)\r
+{\r
+ // Check for 1. Driver loaded, 2. Driver ready.\r
+ // If any of these cases is not met, skip this event and return failure.\r
+ //\r
+ If(PDRD())\r
+ {\r
+ Return(0x1) // Return failure if driver not loaded.\r
+ }\r
+\r
+ Store(Arg0, CEVT) // Set up the current event value\r
+ Store(3, CSTS) // CSTS=BIOS dispatched an event\r
+\r
+ If(LAnd(LEqual(CHPD, 0), LEqual(Arg1, 0))) // Do not re-enum if driver supports hotplug\r
+ {\r
+ If(LOr(LGreater(OSYS, 2000), LLess(OSYS, 2006)))\r
+ {\r
+ //\r
+ // WINXP requires that the entire PCI Bridge be re-enumerated.\r
+ //\r
+ Notify(\_SB.PCI0, Arg1)\r
+ }\r
+ Else\r
+ {\r
+ //\r
+ // Re-enumerate the Graphics Device for non-XP operating systems.\r
+ //\r
+ Notify(\_SB.PCI0.GFX0, Arg1)\r
+ }\r
+ }\r
+\r
+ Notify(\_SB.PCI0.GFX0,0x80)\r
+\r
+\r
+ Return(0x0) // Return success\r
+}\r
+\r
+\r
+/************************************************************************;\r
+;*\r
+;* Name: GHDS\r
+;*\r
+;* Description: Handle a hotkey display switching event (performs a\r
+;* Notify(GFX0, 0).\r
+;*\r
+;* Usage: This method must be called when a hotkey event occurs and the\r
+;* purpose of that hotkey is to do a display switch.\r
+;*\r
+;* Input: Arg0 = Toggle table number.\r
+;*\r
+;* Output: Returns 0 = success, 1 = failure.\r
+;* CEVT and TIDX are indirect outputs.\r
+;*\r
+;* References: TIDX, GNOT\r
+;*\r
+;************************************************************************/\r
+\r
+Method(GHDS, 1)\r
+{\r
+ Store(Arg0, TIDX) // Store the table number\r
+\r
+ // Call GNOT for CEVT = 1 = hotkey, notify value = 0\r
+\r
+ Return(GNOT(1, 0)) // Return stats from GNOT\r
+}\r
+\r
+\r
+/************************************************************************;\r
+;*\r
+;* Name: GLID\r
+;*\r
+;* Description: Handle a lid event (performs the Notify(GFX0, 0), but not the\r
+;* lid notify).\r
+;*\r
+;* Usage: This method must be called when a lid event occurs. A\r
+;* Notify(LID0, 0x80) must follow the call to this method.\r
+;*\r
+;* Input: Arg0 = Lid state:\r
+;* 0 = All closed\r
+;* 1 = internal LFP lid open\r
+;* 2 = external lid open\r
+;* 3 = both external and internal open\r
+;*\r
+;* Output: Returns 0=success, 1=failure.\r
+;* CLID and CEVT are indirect outputs.\r
+;*\r
+;* References: CLID, GNOT\r
+;*\r
+;************************************************************************/\r
+\r
+Method(GLID, 1)\r
+{\r
+ Store(Arg0, CLID) // Store the current lid state\r
+\r
+ // Call GNOT for CEVT=2=Lid, notify value = 0\r
+\r
+ Return(GNOT(2, 0)) // Return stats from GNOT\r
+}\r
+\r
+\r
+/************************************************************************;\r
+;*\r
+;* Name: GDCK\r
+;*\r
+;* Description: Handle a docking event by updating the current docking status\r
+;* and doing a notification.\r
+;*\r
+;* Usage: This method must be called when a docking event occurs.\r
+;*\r
+;* Input: Arg0 = Docking state:\r
+;* 0 = Undocked\r
+;* 1 = Docked\r
+;*\r
+;* Output: Returns 0=success, 1=failure.\r
+;* CDCK and CEVT are indirect outputs.\r
+;*\r
+;* References: CDCK, GNOT\r
+;*\r
+;************************************************************************/\r
+\r
+Method(GDCK, 1)\r
+{\r
+ Store(Arg0, CDCK) // Store the current dock state\r
+\r
+ // Call GNOT for CEVT=4=Dock, notify value = 0\r
+\r
+ Return(GNOT(4, 0)) // Return stats from GNOT\r
+}\r
+\r
+\r
+/************************************************************************;\r
+;* ASLE Interrupt Methods\r
+;************************************************************************/\r
+\r
+\r
+/************************************************************************;\r
+;*\r
+;* Name: PARD\r
+;*\r
+;* Description: Check if the driver is ready to handle ASLE interrupts\r
+;* generate by the system BIOS.\r
+;*\r
+;* Usage: This method must be called before generating each ASLE\r
+;* interrupt.\r
+;*\r
+;* Input: None\r
+;*\r
+;* Output: Returns 0 = success, 1 = failure.\r
+;*\r
+;* References: ARDY (Driver readiness), ASLP (Driver recommended sleep\r
+;* timeout value)\r
+;*\r
+;************************************************************************/\r
+\r
+Method(PARD)\r
+{\r
+ If(LNot(ARDY))\r
+ {\r
+\r
+ // Sleep for ASLP milliseconds if the driver is not ready.\r
+\r
+ Sleep(ASLP)\r
+ }\r
+\r
+ // If ARDY is clear, the driver is not ready. If the return value is\r
+ // !=0, do not generate the ASLE interrupt.\r
+\r
+ Return(LNot(ARDY))\r
+}\r
+\r
+\r
+/************************************************************************;\r
+;*\r
+;* Name: AINT\r
+;*\r
+;* Description: Call the appropriate methods to generate an ASLE interrupt.\r
+;* This process includes ensuring the graphics driver is ready\r
+;* to process the interrupt, ensuring the driver supports the\r
+;* interrupt of interest, and passing information about the event\r
+;* to the graphics driver.\r
+;*\r
+;* Usage: This method must called to generate an ASLE interrupt.\r
+;*\r
+;* Input: Arg0 = ASLE command function code:\r
+;* 0 = Set ALS illuminance\r
+;* 1 = Set backlight brightness\r
+;* 2 = Do Panel Fitting\r
+;* Arg1 = If Arg0 = 0, current ALS reading:\r
+;* 0 = Reading below sensor range\r
+;* 1-0xFFFE = Current sensor reading\r
+;* 0xFFFF = Reading above sensor range\r
+;* Arg1 = If Arg0 = 1, requested backlight percentage\r
+;*\r
+;* Output: Returns 0 = success, 1 = failure\r
+;*\r
+;* References: PARD method.\r
+;*\r
+;************************************************************************/\r
+\r
+Method(AINT, 2)\r
+{\r
+\r
+ // Return failure if the requested feature is not supported by the\r
+ // driver.\r
+\r
+ If(LNot(And(TCHE, ShiftLeft(1, Arg0))))\r
+ {\r
+ Return(0x1)\r
+ }\r
+\r
+ // Return failure if the driver is not ready to handle an ASLE\r
+ // interrupt.\r
+\r
+ If(PARD())\r
+ {\r
+ Return(0x1)\r
+ }\r
+\r
+ // Evaluate the first argument (Panel fitting, backlight brightness, or ALS).\r
+\r
+ If(LEqual(Arg0, 2)) // Arg0 = 2, so request a panel fitting mode change.\r
+ {\r
+ If(CPFM) // If current mode field is non-zero use it.\r
+ {\r
+ And(CPFM, 0x0F, Local0) // Create variables without reserved\r
+ And(EPFM, 0x0F, Local1) // or valid bits.\r
+\r
+ If(LEqual(Local0, 1)) // If current mode is centered,\r
+ {\r
+ If(And(Local1, 6)) // and if stretched is enabled,\r
+ {\r
+ Store(6, PFIT) // request stretched.\r
+ }\r
+ Else // Otherwise,\r
+ {\r
+ If(And(Local1, 8)) // if aspect ratio is enabled,\r
+ {\r
+ Store(8, PFIT) // request aspect ratio.\r
+ }\r
+ Else // Only centered mode is enabled\r
+ {\r
+ Store(1, PFIT) // so request centered. (No change.)\r
+ }\r
+ }\r
+ }\r
+ If(LEqual(Local0, 6)) // If current mode is stretched,\r
+ {\r
+ If(And(Local1, 8)) // and if aspect ratio is enabled,\r
+ {\r
+ Store(8, PFIT) // request aspect ratio.\r
+ }\r
+ Else // Otherwise,\r
+ {\r
+ If(And(Local1, 1)) // if centered is enabled,\r
+ {\r
+ Store(1, PFIT) // request centered.\r
+ }\r
+ Else // Only stretched mode is enabled\r
+ {\r
+ Store(6, PFIT) // so request stretched. (No change.)\r
+ }\r
+ }\r
+ }\r
+ If(LEqual(Local0, 8)) // If current mode is aspect ratio,\r
+ {\r
+ If(And(Local1, 1)) // and if centered is enabled,\r
+ {\r
+ Store(1, PFIT) // request centered.\r
+ }\r
+ Else // Otherwise,\r
+ {\r
+ If(And(Local1, 6)) // if stretched is enabled,\r
+ {\r
+ Store(6, PFIT) // request stretched.\r
+ }\r
+ Else // Only aspect ratio mode is enabled\r
+ {\r
+ Store(8, PFIT) // so request aspect ratio. (No change.)\r
+ }\r
+ }\r
+ }\r
+ }\r
+\r
+ // The following code for panel fitting (within the Else condition) is retained for backward compatiblity.\r
+\r
+ Else // If CFPM field is zero use PFIT and toggle the\r
+ {\r
+ Xor(PFIT,7,PFIT) // mode setting between stretched and centered only.\r
+ }\r
+\r
+ Or(PFIT,0x80000000,PFIT) // Set the valid bit for all cases.\r
+\r
+ Store(4, ASLC) // Store "Panel fitting event" to ASLC[31:1]\r
+ }\r
+ Else\r
+ {\r
+ If(LEqual(Arg0, 1)) // Arg0=1, so set the backlight brightness.\r
+ {\r
+ Store(Divide(Multiply(Arg1, 255), 100), BCLP) // Convert from percent to 0-255.\r
+\r
+ Or(BCLP, 0x80000000, BCLP) // Set the valid bit.\r
+\r
+ Store(2, ASLC) // Store "Backlight control event" to ASLC[31:1]\r
+ }\r
+ Else\r
+ {\r
+ If(LEqual(Arg0, 0)) // Arg0=0, so set the ALS illuminace\r
+ {\r
+ Store(Arg1, ALSI)\r
+\r
+ Store(1, ASLC) // Store "ALS event" to ASLC[31:1]\r
+ }\r
+ Else\r
+ {\r
+ Return(0x1) // Unsupported function\r
+ }\r
+ }\r
+ }\r
+\r
+ Store(0x01, ASLE) // Generate ASLE interrupt\r
+ Return(0x0) // Return success\r
+}\r
+\r
+\r
+/************************************************************************;\r
+;*\r
+;* Name: SCIP\r
+;*\r
+;* Description: Checks the presence of the OpRegion and SCI\r
+;*\r
+;* Usage: This method is called before other OpRegion methods. The\r
+;* former "GSMI True/False is not always valid. This method\r
+;* checks if the OpRegion Version is non-zero and if non-zero,\r
+;* (present and readable) then checks the GSMI flag.\r
+;*\r
+;* Input: None\r
+;*\r
+;* Output: Boolean True = SCI present.\r
+;*\r
+;* References: None\r
+;*\r
+;************************************************************************/\r
+\r
+Method(SCIP)\r
+{\r
+ If(LNotEqual(OVER,0)) // If OpRegion Version not 0.\r
+ {\r
+ Return(LNot(GSMI)) // Return True if SCI.\r
+ }\r
+\r
+ Return(0) // Else Return False.\r
+}\r
--- /dev/null
+/*++\r
+\r
+Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved\r
+\r
+ This program and the accompanying materials are licensed and made available under\r
+ the terms and conditions of the BSD License that accompanies this distribution.\r
+ The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php.\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+\r
+Module Name:\r
+\r
+ IgdOSBCB.ASL\r
+\r
+Abstract:\r
+\r
+ IGD OpRegion/Software SCI Reference Code for the Baytrail Family.\r
+ This file contains the system BIOS call back functionality for the\r
+ OpRegion/Software SCI mechanism.\r
+\r
+--*/\r
+\r
+\r
+Method (SBCB, 0, Serialized)\r
+{\r
+\r
+ // Supported Callbacks: Sub-function 0\r
+\r
+ If (LEqual(GESF, 0x0))\r
+ {\r
+\r
+ //<TODO> An OEM may support the driver->SBIOS status callbacks, but\r
+ // the supported callbacks value must be modified. The code that is\r
+ // executed upon reception of the callbacks must be also be updated\r
+ // to perform the desired functionality.\r
+\r
+ Store(0x00000000, PARM) // No callbacks supported\r
+\r
+ If(LEqual(PFLV,FMBL))\r
+ {\r
+ Store(0x000F87FD, PARM) // Mobile\r
+ }\r
+ If(LEqual(PFLV,FDTP))\r
+ {\r
+ Store(0x000F87BD, PARM) // Desktop\r
+ }\r
+\r
+ Store(Zero, GESF) // Clear the exit parameter\r
+ Return(SUCC) // "Success"\r
+ }\r
+\r
+ // BIOS POST Completion: Sub-function 1\r
+\r
+ If (LEqual(GESF, 1))\r
+ {\r
+ Store(Zero, GESF) // Clear the exit parameter\r
+ Store(Zero, PARM)\r
+ Return(SUCC) // Not supported, but no failure\r
+ }\r
+\r
+ // Pre-Hires Set Mode: Sub-function 3\r
+\r
+ If (LEqual(GESF, 3))\r
+ {\r
+ Store(Zero, GESF) // Clear the exit parameter\r
+ Store(Zero, PARM)\r
+ Return(SUCC) // Not supported, but no failure\r
+ }\r
+\r
+ // Post-Hires Set Mode: Sub-function 4\r
+\r
+ If (LEqual(GESF, 4))\r
+ {\r
+ Store(Zero, GESF) // Clear the exit parameter\r
+ Store(Zero, PARM)\r
+ Return(SUCC) // Not supported, but no failure\r
+ }\r
+\r
+ // Display Switch: Sub-function 5\r
+\r
+ If (LEqual(GESF, 5))\r
+ {\r
+ Store(Zero, GESF) // Clear the exit parameter\r
+ Store(Zero, PARM)\r
+ Return(SUCC) // Not supported, but no failure\r
+ }\r
+\r
+ // Set TV format: Sub-function 6\r
+\r
+ If (LEqual(GESF, 6))\r
+ {\r
+\r
+ //<TODO> If implemented, the input values must be saved into\r
+ // non-volatile storage for parsing during the next boot. The\r
+ // following Sample code is Intel validated implementation.\r
+\r
+ Store(And(PARM, 0x0F), ITVF)\r
+ Store(ShiftRight(And(PARM, 0xF0), 4), ITVM)\r
+ Store(Zero, GESF) // Clear the exit parameter\r
+ Store(Zero, PARM)\r
+ Return(SUCC)\r
+ }\r
+\r
+ // Adapter Power State: Sub-function 7\r
+\r
+ If (LEqual(GESF, 7))\r
+ {\r
+\r
+ // Upon notification from driver that the Adapter Power State = D0,\r
+ // check if previous lid event failed. If it did, retry the lid\r
+ // event here.\r
+ If(LEqual(PARM, 0))\r
+ {\r
+ Store(CLID, Local0)\r
+ If(And(0x80000000,Local0))\r
+ {\r
+ And(CLID, 0x0000000F, CLID)\r
+ GLID(CLID)\r
+ }\r
+ }\r
+ Store(Zero, GESF) // Clear the exit parameter\r
+ Store(Zero, PARM)\r
+ Return(SUCC) // Not supported, but no failure\r
+ }\r
+\r
+ // Display Power State: Sub-function 8\r
+\r
+ If (LEqual(GESF, 8))\r
+ {\r
+ Store(Zero, GESF) // Clear the exit parameter\r
+ Store(Zero, PARM)\r
+ Return(SUCC) // Not supported, but no failure\r
+ }\r
+\r
+ // Set Boot Display: Sub-function 9\r
+\r
+ If (LEqual(GESF, 9))\r
+ {\r
+\r
+ //<TODO> An OEM may elect to implement this method. In that case,\r
+ // the input values must be saved into non-volatile storage for\r
+ // parsing during the next boot. The following Sample code is Intel\r
+ // validated implementation.\r
+\r
+ And(PARM, 0xFF, IBTT) // Save the boot display to NVS\r
+ Store(Zero, GESF) // Clear the exit parameter\r
+ Store(Zero, PARM)\r
+ Return(SUCC) // Reserved, "Critical failure"\r
+ }\r
+\r
+ // Set Panel Details: Sub-function 10 (0Ah)\r
+\r
+ If (LEqual(GESF, 10))\r
+ {\r
+\r
+ //<TODO> An OEM may elect to implement this method. In that case,\r
+ // the input values must be saved into non-volatile storage for\r
+ // parsing during the next boot. The following Sample code is Intel\r
+ // validated implementation.\r
+\r
+ // Set the panel-related NVRAM variables based the input from the driver.\r
+\r
+ And(PARM, 0xFF, IPSC)\r
+\r
+ // Change panel type if a change is requested by the driver (Change if\r
+ // panel type input is non-zero). Zero=No change requested.\r
+\r
+ If(And(ShiftRight(PARM, 8), 0xFF))\r
+ {\r
+ And(ShiftRight(PARM, 8), 0xFF, IPAT)\r
+ Decrement(IPAT) // 0 = no change, so fit to CMOS map\r
+ }\r
+ And(ShiftRight(PARM, 18), 0x3, IBLC)\r
+ And(ShiftRight(PARM, 20), 0x7, IBIA)\r
+ Store(Zero, GESF) // Clear the exit parameter\r
+ Store(Zero, PARM)\r
+ Return(SUCC) // Success\r
+ }\r
+\r
+ // Set Internal Graphics: Sub-function 11 (0Bh)\r
+\r
+ If (LEqual(GESF, 11))\r
+ {\r
+\r
+ //<TODO> An OEM may elect to implement this method. In that case,\r
+ // the input values must be saved into non-volatile storage for\r
+ // parsing during the next boot. The following Sample code is Intel\r
+ // validated implementation.\r
+\r
+ And(ShiftRight(PARM, 1), 1, IF1E) // Program the function 1 option\r
+\r
+ // Fixed memory/DVMT memory\r
+\r
+ And(ShiftRight(PARM, 17), 0xF, IDMS) // Program DVMT/fixed memory size\r
+\r
+ Store(Zero, GESF) // Clear the exit parameter\r
+ Store(Zero, PARM)\r
+ Return(SUCC) // Success\r
+ }\r
+\r
+ // Post-Hires to DOS FS: Sub-function 16 (10h)\r
+\r
+ If (LEqual(GESF, 16))\r
+ {\r
+ Store(Zero, GESF) // Clear the exit parameter\r
+ Store(Zero, PARM)\r
+ Return(SUCC) // Not supported, but no failure\r
+ }\r
+\r
+ // APM Complete: Sub-function 17 (11h)\r
+\r
+ If (LEqual(GESF, 17))\r
+ {\r
+\r
+ Store(ShiftLeft(LIDS, 8), PARM) // Report the lid state\r
+ Add(PARM, 0x100, PARM) // Adjust the lid state, 0 = Unknown\r
+\r
+ Store(Zero, GESF) // Clear the exit parameter\r
+ Return(SUCC) // Not supported, but no failure\r
+ }\r
+\r
+ // Set Spread Spectrum Clocks: Sub-function 18 (12h)\r
+\r
+ If (LEqual(GESF, 18))\r
+ {\r
+\r
+ //<TODO> An OEM may elect to implement this method. In that case,\r
+ // the input values must be saved into non-volatile storage for\r
+ // parsing during the next boot. The following Sample code is Intel\r
+ // validated implementation.\r
+\r
+ If(And(PARM, 1))\r
+ {\r
+ If(LEqual(ShiftRight(PARM, 1), 1))\r
+ {\r
+ Store(1, ISSC) // Enable HW SSC, only for clock 1\r
+ }\r
+ Else\r
+ {\r
+ Store(Zero, GESF)\r
+ Return(CRIT) // Failure, as the SSC clock must be 1\r
+ }\r
+ }\r
+ Else\r
+ {\r
+ Store(0, ISSC) // Disable SSC\r
+ }\r
+ Store(Zero, GESF) // Clear the exit parameter\r
+ Store(Zero, PARM)\r
+ Return(SUCC) // Success\r
+ }\r
+\r
+ // Post VBE/PM Callback: Sub-function 19 (13h)\r
+\r
+ If (LEqual(GESF, 19))\r
+ {\r
+ Store(Zero, GESF) // Clear the exit parameter\r
+ Store(Zero, PARM)\r
+ Return(SUCC) // Not supported, but no failure\r
+ }\r
+\r
+ // Set PAVP Data: Sub-function 20 (14h)\r
+\r
+ If (LEqual(GESF, 20))\r
+ {\r
+ And(PARM, 0xF, PAVP) // Store PAVP info\r
+ Store(Zero, GESF) // Clear the exit parameter\r
+ Store(Zero, PARM)\r
+ Return(SUCC) // Success\r
+ }\r
+\r
+ // A call to a reserved "System BIOS callbacks" function was received\r
+\r
+ Store(Zero, GESF) // Clear the exit parameter\r
+ Return(SUCC) // Reserved, "Critical failure"\r
+}\r
--- /dev/null
+/*++\r
+\r
+Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved\r
+\r
+ This program and the accompanying materials are licensed and made available under\r
+ the terms and conditions of the BSD License that accompanies this distribution.\r
+ The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php.\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+\r
+Module Name:\r
+\r
+ IgdOpRn.ASL\r
+\r
+Abstract:\r
+\r
+ IGD OpRegion/Software SCI Reference Code for the Baytrail Family.\r
+ This file contains the interrupt handler code for the Integrated\r
+ Graphics Device (IGD) OpRegion/Software SCI mechanism.\r
+\r
+--*/\r
+\r
+\r
+//NOTES:\r
+//\r
+// (1) The code contained in this file inherits the scope in which it\r
+// was included. So BIOS developers must be sure to include this\r
+// file in the scope associated with the graphics device\r
+// (ex. \_SB.PCI0.GFX0).\r
+// (2) Create a _L06 method under the GPE scope to handle the event\r
+// generated by the graphics driver. The _L06 method must call\r
+// the GSCI method in this file.\r
+// (3) The MCHP operation region assumes that _ADR and _BBN names\r
+// corresponding to bus 0, device0, function 0 have been declared\r
+// under the PCI0 scope.\r
+// (4) Before the first execution of the GSCI method, the base address\r
+// of the GMCH SCI OpRegion must be programmed where the driver can\r
+// access it. A 32bit scratch register at 0xFC in the IGD PCI\r
+// configuration space (B0/D2/F0/R0FCh) is used for this purpose.\r
+\r
+// Define an OperationRegion to cover the GMCH PCI configuration space as\r
+// described in the IGD OpRegion specificiation.\r
+\r
+// Define an OperationRegion to cover the IGD PCI configuration space as\r
+// described in the IGD OpRegion specificiation.\r
+\r
+OperationRegion(IGDP, PCI_Config,0x00,0x100)\r
+Field(IGDP, AnyAcc, NoLock, Preserve)\r
+{\r
+ Offset(0x10), // GTTMMADR\r
+ MADR, 32,\r
+ Offset(0x50), // GMCH Graphics Control Register\r
+ , 1,\r
+ GIVD, 1, // IGD VGA disable bit\r
+ , 1,\r
+ GUMA, 5, // Stolen memory size\r
+ , 8,\r
+ Offset(0x54),\r
+ , 4,\r
+ GMFN, 1, // Gfx function 1 enable\r
+ , 27,\r
+ Offset(0x5C), // Stolen Memory Base Address\r
+ GSTM, 32,\r
+ Offset(0xE0), // Reg 0xE8, SWSCI control register\r
+ GSSE, 1, // Graphics SCI event (1=event pending)\r
+ GSSB, 14, // Graphics SCI scratchpad bits\r
+ GSES, 1, // Graphics event select (1=SCI)\r
+ Offset(0xE4),\r
+ ASLE, 8, // Reg 0xE4, ASLE interrupt register\r
+ , 24, // Only use first byte of ASLE reg\r
+ Offset(0xFC),\r
+ ASLS, 32, // Reg 0xFC, Address of the IGD OpRegion\r
+}\r
+\r
+Method (MCHK, 0, Serialized)\r
+{\r
+\r
+ If (LNotEqual (MADR, 0xFFFFFFFF))\r
+ {\r
+ OperationRegion(IGMM,SystemMemory,MADR,0x3000)\r
+ Field(IGMM,AnyAcc, NoLock, Preserve)\r
+ {\r
+ Offset(0X20C8),\r
+ , 4,\r
+ DCFE, 4, // DISPLAY_CLOCK_FREQUENCY_ENCODING\r
+ }\r
+ }\r
+}\r
+\r
+\r
+// Define an OperationRegion to cover the IGD OpRegion layout.\r
+\r
+OperationRegion(IGDM, SystemMemory, ASLB, 0x2000)\r
+Field(IGDM, AnyAcc, NoLock, Preserve)\r
+{\r
+\r
+ // OpRegion Header\r
+\r
+ SIGN, 128, // Signature-"IntelGraphicsMem"\r
+ SIZE, 32, // OpRegion Size\r
+ OVER, 32, // OpRegion Version\r
+ SVER, 256, // System BIOS Version\r
+ VVER, 128, // VBIOS Version\r
+ GVER, 128, // Driver version\r
+ MBOX, 32, // Mailboxes supported\r
+ DMOD, 32, // Driver Model\r
+ PCON, 32, // 96, Platform Configuration\r
+\r
+ // OpRegion Mailbox 1 (Public ACPI Methods)\r
+ // Note: Mailbox 1 is normally reserved for desktop platforms.\r
+\r
+ Offset(0x100),\r
+ DRDY, 32, // Driver readiness (ACPI notification)\r
+ CSTS, 32, // Notification status\r
+ CEVT, 32, // Current event\r
+ Offset(0x120),\r
+ DIDL, 32, // Supported display device ID list\r
+ DDL2, 32, // Allows for 8 devices\r
+ DDL3, 32,\r
+ DDL4, 32,\r
+ DDL5, 32,\r
+ DDL6, 32,\r
+ DDL7, 32,\r
+ DDL8, 32,\r
+ CPDL, 32, // Currently present display list\r
+ CPL2, 32, // Allows for 8 devices\r
+ CPL3, 32,\r
+ CPL4, 32,\r
+ CPL5, 32,\r
+ CPL6, 32,\r
+ CPL7, 32,\r
+ CPL8, 32,\r
+ CAD1, 32, // Currently active display list\r
+ CAL2, 32, // Allows for 8 devices\r
+ CAL3, 32,\r
+ CAL4, 32,\r
+ CAL5, 32,\r
+ CAL6, 32,\r
+ CAL7, 32,\r
+ CAL8, 32,\r
+ NADL, 32, // Next active display list\r
+ NDL2, 32, // Allows for 8 devices\r
+ NDL3, 32,\r
+ NDL4, 32,\r
+ NDL5, 32,\r
+ NDL6, 32,\r
+ NDL7, 32,\r
+ NDL8, 32,\r
+ ASLP, 32, // ASL sleep timeout\r
+ TIDX, 32, // Toggle table index\r
+ CHPD, 32, // Current hot plug enable indicator\r
+ CLID, 32, // Current lid state indicator\r
+ CDCK, 32, // Current docking state indicator\r
+ SXSW, 32, // Display switch notify on resume\r
+ EVTS, 32, // Events supported by ASL (diag only)\r
+ CNOT, 32, // Current OS notifications (diag only)\r
+ NRDY, 32,\r
+\r
+ // OpRegion Mailbox 2 (Software SCI Interface)\r
+\r
+ Offset(0x200), // SCIC\r
+ SCIE, 1, // SCI entry bit (1=call unserviced)\r
+ GEFC, 4, // Entry function code\r
+ GXFC, 3, // Exit result\r
+ GESF, 8, // Entry/exit sub-function/parameter\r
+ , 16, // SCIC[31:16] reserved\r
+ Offset(0x204), // PARM\r
+ PARM, 32, // PARM register (extra parameters)\r
+ DSLP, 32, // Driver sleep time out\r
+\r
+ // OpRegion Mailbox 3 (BIOS to Driver Notification)\r
+ // Note: Mailbox 3 is normally reserved for desktop platforms.\r
+\r
+ Offset(0x300),\r
+ ARDY, 32, // Driver readiness (power conservation)\r
+ ASLC, 32, // ASLE interrupt command/status\r
+ TCHE, 32, // Technology enabled indicator\r
+ ALSI, 32, // Current ALS illuminance reading\r
+ BCLP, 32, // Backlight brightness\r
+ PFIT, 32, // Panel fitting state or request\r
+ CBLV, 32, // Current brightness level\r
+ BCLM, 320, // Backlight brightness level duty cycle mapping table\r
+ CPFM, 32, // Current panel fitting mode\r
+ EPFM, 32, // Enabled panel fitting modes\r
+ PLUT, 592, // Optional. 74-byte Panel LUT Table\r
+ PFMB, 32, // Optional. PWM Frequency and Minimum Brightness\r
+ CCDV, 32, // Optional. Gamma, Brightness, Contrast values.\r
+ PCFT, 32, // Optional. Power Conservation Features\r
+\r
+ Offset(0x3B6),\r
+ STAT, 32, // Status register\r
+\r
+ // OpRegion Mailbox 4 (VBT)\r
+\r
+ Offset(0x400),\r
+ GVD1, 0xC000, // 6K bytes maximum VBT image\r
+\r
+ // OpRegion Mailbox 5 (BIOS to Driver Notification Extension)\r
+\r
+ Offset(0x1C00),\r
+ PHED, 32, // Panel Header\r
+ BDDC, 2048, // Panel EDID (Max 256 bytes)\r
+\r
+}\r
+\r
+\r
+\r
+// Convert boot display type into a port mask.\r
+\r
+Name (DBTB, Package()\r
+{\r
+ 0x0000, // Automatic\r
+ 0x0007, // Port-0 : Integrated CRT\r
+ 0x0038, // Port-1 : DVO-A, or Integrated LVDS\r
+ 0x01C0, // Port-2 : SDVO-B, or SDVO-B/C\r
+ 0x0E00, // Port-3 : SDVO-C\r
+ 0x003F, // [CRT + DVO-A / Integrated LVDS]\r
+ 0x01C7, // [CRT + SDVO-B] or [CRT + SDVO-B/C]\r
+ 0x0E07, // [CRT + SDVO-C]\r
+ 0x01F8, // [DVO-A / Integrated LVDS + SDVO-B]\r
+ 0x0E38, // [DVO-A / Integrated LVDS + SDVO-C]\r
+ 0x0FC0, // [SDVO-B + SDVO-C]\r
+ 0x0000, // Reserved\r
+ 0x0000, // Reserved\r
+ 0x0000, // Reserved\r
+ 0x0000, // Reserved\r
+ 0x0000, // Reserved\r
+ 0x7000, // Port-4: Integrated TV\r
+ 0x7007, // [Integrated TV + CRT]\r
+ 0x7038, // [Integrated TV + LVDS]\r
+ 0x71C0, // [Integrated TV + DVOB]\r
+ 0x7E00 // [Integrated TV + DVOC]\r
+})\r
+\r
+// Core display clock value table.\r
+\r
+Name (CDCT, Package()\r
+{\r
+ Package() {160},\r
+ Package() {200},\r
+ Package() {267},\r
+ Package() {320},\r
+ Package() {356},\r
+ Package() {400},\r
+})\r
+\r
+// Defined exit result values:\r
+\r
+Name (SUCC, 1) // Exit result: Success\r
+Name (NVLD, 2) // Exit result: Invalid parameter\r
+Name (CRIT, 4) // Exit result: Critical failure\r
+Name (NCRT, 6) // Exit result: Non-critical failure\r
+\r
+\r
+/************************************************************************;\r
+;*\r
+;* Name: GSCI\r
+;*\r
+;* Description: Handles an SCI generated by the graphics driver. The\r
+;* PARM and SCIC input fields are parsed to determine the\r
+;* functionality requested by the driver. GBDA or SBCB\r
+;* is called based on the input data in SCIC.\r
+;*\r
+;* Usage: The method must be called in response to a GPE 06 event\r
+;* which will be generated by the graphics driver.\r
+;* Ex: Method(\_GPE._L06) {Return(\_SB.PCI0.GFX0.GSCI())}\r
+;*\r
+;* Input: PARM and SCIC are indirect inputs\r
+;*\r
+;* Output: PARM and SIC are indirect outputs\r
+;*\r
+;* References: GBDA (Get BIOS Data method), SBCB (System BIOS Callback\r
+;* method)\r
+;*\r
+;************************************************************************/\r
+\r
+Method (GSCI, 0, Serialized)\r
+{\r
+ Include("IgdOGBDA.ASL") // "Get BIOS Data" Functions\r
+ Include("IgdOSBCB.ASL") // "System BIOS CallBacks"\r
+\r
+ If (LEqual(GEFC, 4))\r
+ {\r
+ Store(GBDA(), GXFC) // Process Get BIOS Data functions\r
+ }\r
+\r
+ If (LEqual(GEFC, 6))\r
+ {\r
+ Store(SBCB(), GXFC) // Process BIOS Callback functions\r
+ }\r
+\r
+ Store(0, GEFC) // Wipe out the entry function code\r
+ Store(1, SCIS) // Clear the GUNIT SCI status bit in PCH ACPI I/O space.\r
+ Store(0, GSSE) // Clear the SCI generation bit in PCI space.\r
+ Store(0, SCIE) // Clr SCI serviced bit to signal completion\r
+\r
+ Return(Zero)\r
+}\r
+\r
+// Include MOBLFEAT.ASL for mobile systems only. Remove for desktop.\r
+Include("IgdOMOBF.ASL") // IGD SCI mobile features\r
--- /dev/null
+/** @file\r
+Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+Device(IOTD) { \r
+ Name(_HID, "MSFT8000")\r
+ Name(_CID, "MSFT8000")\r
+ \r
+ Name(_CRS, ResourceTemplate() { \r
+ // Index 0 \r
+ SPISerialBus( // Pin 5, 7, 9 , 11 of JP1 for SIO_SPI\r
+ 1, // Device selection\r
+ PolarityLow, // Device selection polarity\r
+ FourWireMode, // wiremode\r
+ 8, // databit len\r
+ ControllerInitiated, // slave mode\r
+ 8000000, // Connection speed\r
+ ClockPolarityLow, // Clock polarity\r
+ ClockPhaseSecond, // clock phase\r
+ "\\_SB.SPI1", // ResourceSource: SPI bus controller name\r
+ 0, // ResourceSourceIndex\r
+ ResourceConsumer, // Resource usage\r
+ JSPI, // DescriptorName: creates name for offset of resource descriptor\r
+ ) // Vendor Data \r
+ \r
+ // Index 1 \r
+ I2CSerialBus( // Pin 13, 15 of JP1, for SIO_I2C5 (signal)\r
+ 0x00, // SlaveAddress: bus address (TBD)\r
+ , // SlaveMode: default to ControllerInitiated\r
+ 400000, // ConnectionSpeed: in Hz\r
+ , // Addressing Mode: default to 7 bit\r
+ "\\_SB.I2C6", // ResourceSource: I2C bus controller name (For MinnowBoard Max, hardware I2C5(0-based) is reported as ACPI I2C6(1-based))\r
+ ,\r
+ ,\r
+ JI2C, // Descriptor Name: creates name for offset of resource descriptor\r
+ ) // VendorData\r
+ \r
+ // Index 2\r
+ UARTSerialBus( // Pin 17, 19 of JP1, for SIO_UART2\r
+ 115200, // InitialBaudRate: in bits ber second\r
+ , // BitsPerByte: default to 8 bits\r
+ , // StopBits: Defaults to one bit\r
+ 0xfc, // LinesInUse: 8 1-bit flags to declare line enabled\r
+ , // IsBigEndian: default to LittleEndian\r
+ , // Parity: Defaults to no parity\r
+ , // FlowControl: Defaults to no flow control\r
+ 32, // ReceiveBufferSize\r
+ 32, // TransmitBufferSize\r
+ "\\_SB.URT2", // ResourceSource: UART bus controller name\r
+ ,\r
+ ,\r
+ UAR2, // DescriptorName: creates name for offset of resource descriptor\r
+ ) \r
+ \r
+ // Index 3\r
+ GpioIo (Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.GPO2",) {0} // Pin 21 of JP1 (GPIO_S5[00])\r
+ // Index 4\r
+ GpioInt(Edge, ActiveBoth, SharedAndWake, PullNone, 0,"\\_SB.GPO2",) {0} \r
+ \r
+ // Index 5\r
+ GpioIo (Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.GPO2",) {1} // Pin 23 of JP1 (GPIO_S5[01])\r
+ // Index 6\r
+ GpioInt(Edge, ActiveBoth, SharedAndWake, PullNone, 0,"\\_SB.GPO2",) {1}\r
+ \r
+ // Index 7\r
+ GpioIo (Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.GPO2",) {2} // Pin 25 of JP1 (GPIO_S5[02])\r
+ // Index 8\r
+ GpioInt(Edge, ActiveBoth, SharedAndWake, PullNone, 0,"\\_SB.GPO2",) {2} \r
+ \r
+ // Index 9\r
+ UARTSerialBus( // Pin 6, 8, 10, 12 of JP1, for SIO_UART1\r
+ 115200, // InitialBaudRate: in bits ber second\r
+ , // BitsPerByte: default to 8 bits\r
+ , // StopBits: Defaults to one bit\r
+ 0xfc, // LinesInUse: 8 1-bit flags to declare line enabled\r
+ , // IsBigEndian: default to LittleEndian\r
+ , // Parity: Defaults to no parity\r
+ FlowControlHardware, // FlowControl: Defaults to no flow control\r
+ 32, // ReceiveBufferSize\r
+ 32, // TransmitBufferSize\r
+ "\\_SB.URT1", // ResourceSource: UART bus controller name\r
+ ,\r
+ ,\r
+ UAR1, // DescriptorName: creates name for offset of resource descriptor\r
+ ) \r
+ \r
+ // Index 10\r
+ GpioIo (Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.GPO0",) {62} // Pin 14 of JP1 (GPIO_SC[62])\r
+ // Index 11\r
+ GpioInt(Edge, ActiveBoth, SharedAndWake, PullNone, 0,"\\_SB.GPO0",) {62} \r
+ \r
+ // Index 12\r
+ GpioIo (Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.GPO0",) {63} // Pin 16 of JP1 (GPIO_SC[63])\r
+ // Index 13\r
+ GpioInt(Edge, ActiveBoth, SharedAndWake, PullNone, 0,"\\_SB.GPO0",) {63} \r
+ \r
+ // Index 14\r
+ GpioIo (Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.GPO0",) {65} // Pin 18 of JP1 (GPIO_SC[65])\r
+ // Index 15\r
+ GpioInt(Edge, ActiveBoth, SharedAndWake, PullNone, 0,"\\_SB.GPO0",) {65} \r
+ \r
+ // Index 16\r
+ GpioIo (Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.GPO0",) {64} // Pin 20 of JP1 (GPIO_SC[64])\r
+ // Index 17\r
+ GpioInt(Edge, ActiveBoth, SharedAndWake, PullNone, 0,"\\_SB.GPO0",) {64} \r
+ \r
+ // Index 18\r
+ GpioIo (Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.GPO0",) {94} // Pin 22 of JP1 (GPIO_SC[94])\r
+ // Index 19\r
+ GpioInt(Edge, ActiveBoth, SharedAndWake, PullNone, 0,"\\_SB.GPO0",) {94} \r
+ \r
+ // Index 20\r
+ GpioIo (Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.GPO0",) {95} // Pin 24 of JP1 (GPIO_SC[95])\r
+ // Index 21\r
+ GpioInt(Edge, ActiveBoth, SharedAndWake, PullNone, 0,"\\_SB.GPO0",) {95} \r
+ \r
+ // Index 22\r
+ GpioIo (Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.GPO0",) {54} // Pin 26 of JP1 (GPIO_SC[54])\r
+ // Index 23\r
+ GpioInt(Edge, ActiveBoth, SharedAndWake, PullNone, 0,"\\_SB.GPO0",) {54}\r
+ })\r
+\r
+ Name(_DSD, Package() {\r
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),\r
+ Package(1) { // Just one Property for IOT (at this time) \r
+ Package(2) { //The \93symbolic-identifiers\94 property\r
+ "symbolic-identifiers", \r
+ Package() { //Contains all the <resource index, symbolic-identifier> pairs \r
+ 0, "SPI0", \r
+ 1, "I2C5", \r
+ 2, "UART2",\r
+ 3, 21, // Pin 21 of JP1 (GPIO_S5[00])\r
+ 4, 21, // Pin 21 for separate resource. \r
+ 5, 23, // Pin 23 of JP1 (GPIO_S5[01])\r
+ 6, 23,\r
+ 7, 25, // Pin 25 of JP1 (GPIO_S5[02])\r
+ 8, 25,\r
+ 9, "UART1",\r
+ 10, 14, // Pin 14 of JP1 (GPIO_SC[62])\r
+ 11, 14,\r
+ 12, 16, // Pin 16 of JP1 (GPIO_SC[63])\r
+ 13, 16,\r
+ 14, 18, // Pin 18 of JP1 (GPIO_SC[65])\r
+ 15, 18,\r
+ 16, 20, // Pin 20 of JP1 (GPIO_SC[64])\r
+ 17, 20,\r
+ 18, 22, // Pin 22 of JP1 (GPIO_SC[94])\r
+ 19, 22,\r
+ 20, 24, // Pin 24 of JP1 (GPIO_SC[95])\r
+ 21, 24,\r
+ 22, 26, // Pin 26 of JP1 (GPIO_SC[54])\r
+ 23, 26\r
+ }\r
+ } \r
+ }\r
+ })\r
+ \r
+ Method(_STA,0,Serialized) {\r
+ \r
+ //\r
+ // Only report IoT virtual device when all pins' configuration follows MSFT's datasheet.\r
+ //\r
+ If (LEqual(IOT, 1)) {\r
+ Return (0xF)\r
+ }\r
+ \r
+ Return (0x0)\r
+ }\r
+}\r
--- /dev/null
+/**************************************************************************;\r
+;* *;\r
+;* *;\r
+;* Intel Corporation - ACPI Reference Code for the Baytrail *;\r
+;* Family of Customer Reference Boards. *;\r
+;* *;\r
+;* *;\r
+;* Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved *;\r
+;\r
+; This program and the accompanying materials are licensed and made available under\r
+; the terms and conditions of the BSD License that accompanies this distribution.\r
+; The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php.\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+;* *;\r
+;* *;\r
+;**************************************************************************/\r
+\r
+Device(FWHD) // Firmware Hub Device\r
+{\r
+ Name(_HID,EISAID("INT0800"))\r
+\r
+ Name(_CRS,ResourceTemplate()\r
+ {\r
+ Memory32Fixed(ReadOnly,0xFF000000,0x1000000)\r
+ })\r
+}\r
+\r
+Device(IPIC) // 8259 PIC\r
+{\r
+ Name(_HID,EISAID("PNP0000"))\r
+\r
+ Name(_CRS,ResourceTemplate()\r
+ {\r
+ IO(Decode16,0x20,0x20,0x01,0x02)\r
+ IO(Decode16,0x24,0x24,0x01,0x02)\r
+ IO(Decode16,0x28,0x28,0x01,0x02)\r
+ IO(Decode16,0x2C,0x2C,0x01,0x02)\r
+ IO(Decode16,0x30,0x30,0x01,0x02)\r
+ IO(Decode16,0x34,0x34,0x01,0x02)\r
+ IO(Decode16,0x38,0x38,0x01,0x02)\r
+ IO(Decode16,0x3C,0x3C,0x01,0x02)\r
+ IO(Decode16,0xA0,0xA0,0x01,0x02)\r
+ IO(Decode16,0xA4,0xA4,0x01,0x02)\r
+ IO(Decode16,0xA8,0xA8,0x01,0x02)\r
+ IO(Decode16,0xAC,0xAC,0x01,0x02)\r
+ IO(Decode16,0xB0,0xB0,0x01,0x02)\r
+ IO(Decode16,0xB4,0xB4,0x01,0x02)\r
+ IO(Decode16,0xB8,0xB8,0x01,0x02)\r
+ IO(Decode16,0xBC,0xBC,0x01,0x02)\r
+ IO(Decode16,0x4D0,0x4D0,0x01,0x02)\r
+ IRQNoFlags() {2}\r
+ })\r
+}\r
+\r
+Device(LDRC) // LPC Device Resource Consumption\r
+{\r
+ Name(_HID,EISAID("PNP0C02"))\r
+\r
+ Name(_UID,2)\r
+\r
+ Name(_CRS,ResourceTemplate()\r
+ {\r
+ IO(Decode16,0x4E,0x4E,0x1,0x02) // LPC Slot Access.\r
+ IO(Decode16,0x61,0x61,0x1,0x1) // NMI Status.\r
+ IO(Decode16,0x63,0x63,0x1,0x1) // Processor I/F.\r
+ IO(Decode16,0x65,0x65,0x1,0x1) // Processor I/F.\r
+ IO(Decode16,0x67,0x67,0x1,0x1) // Processor I/F.\r
+ IO(Decode16,0x70,0x70,0x1,0x1) // NMI Enable.\r
+ IO(Decode16,0x80,0x80,0x1,0x10) // Postcode.\r
+ IO(Decode16,0x92,0x92,0x1,0x1) // Processor I/F.\r
+ IO(Decode16,0xB2,0xB2,0x01,0x02) // Software SMI.\r
+ IO(Decode16,0x680,0x680,0x1,0x20) // 32 Byte I/O.\r
+ IO(Decode16,0x400,0x400,0x1,0x80) // ACPI Base.\r
+ IO(Decode16,0x500,0x500,0x1,0xFF) // GPIO Base.\r
+ })\r
+}\r
+\r
+Device(TIMR) // 8254 Timer\r
+{\r
+ Name(_HID,EISAID("PNP0100"))\r
+\r
+ Name(_CRS,ResourceTemplate()\r
+ {\r
+ IO(Decode16,0x40,0x40,0x01,0x04)\r
+ IO(Decode16,0x50,0x50,0x10,0x04)\r
+ IRQNoFlags() {0}\r
+ })\r
+}\r
+\r
+Device(IUR3) // Internal UART\r
+{\r
+ Name(_HID, EISAID("PNP0501"))\r
+\r
+ Name(_UID,1)\r
+\r
+ // Status Method for internal UART\r
+\r
+ Method(_STA,0,Serialized)\r
+ {\r
+ // Only report resources to the OS if internal UART is\r
+ // not set to Disabled in BIOS Setup.\r
+\r
+ If(LEqual(USEL,0))\r
+ {\r
+ If(LEqual(PU1E,1))\r
+ {\r
+ Store(1,UI3E) // Enable IRQ3 for UART\r
+ Store(1,UI4E) // Enable IRQ4 for UART\r
+ Store(1,C1EN) // Enable UART\r
+ Return(0x000F)\r
+ }\r
+ }\r
+\r
+ Return(0x0000)\r
+ }\r
+\r
+ // Disable Method for internal UART\r
+\r
+ Method(_DIS,0,Serialized)\r
+ {\r
+ Store(0,UI3E)\r
+ Store(0,UI4E)\r
+ Store(0,C1EN)\r
+ }\r
+\r
+ // Current Resource Setting Method for internal UART\r
+\r
+ Method(_CRS,0,Serialized)\r
+ {\r
+ // Create the Buffer that stores the Resources to\r
+ // be returned.\r
+\r
+ Name(BUF0,ResourceTemplate()\r
+ {\r
+ IO(Decode16,0x03F8,0x03F8,0x01,0x08)\r
+ IRQNoFlags() {3}\r
+ })\r
+\r
+ Name(BUF1,ResourceTemplate()\r
+ {\r
+ IO(Decode16,0x03F8,0x03F8,0x01,0x08)\r
+ IRQNoFlags() {4}\r
+ })\r
+\r
+ If (LLessEqual(SRID, 0x04))\r
+ {\r
+ Return(BUF0)\r
+ } Else\r
+ {\r
+ Return(BUF1)\r
+ }\r
+ }\r
+}\r
--- /dev/null
+/**************************************************************************;\r
+;* *;\r
+;* *;\r
+;* Intel Corporation - ACPI Reference Code for the Baytrail *;\r
+;* Family of Customer Reference Boards. *;\r
+;* *;\r
+;* *;\r
+;* Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved *;\r
+;\r
+; This program and the accompanying materials are licensed and made available under\r
+; the terms and conditions of the BSD License that accompanies this distribution.\r
+; The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php.\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+;* *;\r
+;* *;\r
+;**************************************************************************/\r
+\r
+\r
+// LPC Bridge - Device 31, Function 0\r
+// Define the needed LPC registers used by ASL.\r
+\r
+scope(\_SB)\r
+{\r
+ OperationRegion(ILBR, SystemMemory, \IBAS, 0x8C)\r
+ Field(ILBR, AnyAcc, NoLock, Preserve)\r
+ {\r
+ Offset(0x08), // 0x08\r
+ PARC, 8,\r
+ PBRC, 8,\r
+ PCRC, 8,\r
+ PDRC, 8,\r
+ PERC, 8,\r
+ PFRC, 8,\r
+ PGRC, 8,\r
+ PHRC, 8,\r
+ Offset(0x88), // 0x88\r
+ , 3,\r
+ UI3E, 1,\r
+ UI4E, 1\r
+ }\r
+\r
+ Include ("98_LINK.ASL")\r
+}\r
+\r
+OperationRegion(LPC0, PCI_Config, 0x00, 0xC0)\r
+Field(LPC0, AnyAcc, NoLock, Preserve)\r
+{\r
+ Offset(0x08), // 0x08\r
+ SRID, 8, // Revision ID\r
+ Offset(0x080), // 0x80\r
+ C1EN, 1, // COM1 Enable\r
+ , 31\r
+}\r
+\r
+\r
+Include ("LPC_DEV.ASL")\r
+\r
+\r
+\r
+\r
+\r
--- /dev/null
+/*++\r
+\r
+Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved\r
+\r
+ This program and the accompanying materials are licensed and made available under\r
+ the terms and conditions of the BSD License that accompanies this distribution.\r
+ The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php.\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+\r
+--*/\r
+\r
+//\r
+// Include files\r
+//\r
+\r
+#include <PiDxe.h>\r
+#include <IndustryStandard/Acpi50.h>\r
+\r
+\r
+\r
+//\r
+// LPIT Definitions\r
+//\r
+\r
+#define EFI_ACPI_LOW_POWER_IDLE_TABLE_REVISION 0x1\r
+\r
+//\r
+// Ensure proper structure formats\r
+//\r
+#pragma pack(1)\r
+\r
+typedef union _EFI_ACPI_LPI_STATE_FLAGS {\r
+ struct {\r
+ UINT32 Disabled :1;\r
+ UINT32 CounterUnavailable :1;\r
+ UINT32 Reserved :30;\r
+ };\r
+ UINT32 AsUlong;\r
+} EFI_ACPI_LPI_STATE_FLAGS, *PEFI_ACPI_LPI_STATE_FLAGS;\r
+\r
+// Only Mwait LPI here:\r
+\r
+typedef struct _EFI_ACPI_MWAIT_LPI_STATE_DESCRIPTOR {\r
+ UINT32 Type; // offset: 0\r
+ UINT32 Length; // offset: 4\r
+ UINT16 UniqueId; // offset: 8\r
+ UINT8 Reserved[2]; // offset: 9\r
+ EFI_ACPI_LPI_STATE_FLAGS Flags; // offset: 12\r
+ EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE EntryTrigger; // offset: 16\r
+ UINT32 Residency; // offset: 28\r
+ UINT32 Latency; // offset: 32\r
+ EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE ResidencyCounter; // offset: 36\r
+ UINT64 ResidencyCounterFrequency; //offset: 48\r
+} EFI_ACPI_MWAIT_LPI_STATE_DESCRIPTOR;\r
+\r
+\r
+//\r
+// Defines for LPIT table, some are VLV specific\r
+//\r
+\r
+\r
+// signature "LPIT"\r
+#define EFI_ACPI_LOW_POWER_IDLE_TABLE_SIGNATURE 0x5449504c\r
+\r
+#define EFI_ACPI_OEM_LPIT_REVISION 0x00000000\r
+\r
+#define EFI_ACPI_LOW_POWER_IDLE_MWAIT_TYPE 0x0\r
+#define EFI_ACPI_LOW_POWER_IDLE_DEFAULT_FLAG 0x0\r
+#define EFI_ACPI_LOW_POWER_IDLE_RES_FREQ_8K 0x8000 // 32768\r
+\r
+//\r
+// LPI state count (4 on VLV: S0ir, S0i1, S0i2, S0i3)\r
+//\r
+\r
+#define EFI_ACPI_VLV_LPI_STATE_COUNT 0x4\r
+\r
+//\r
+// LPI TRIGGER (HW C7 on VLV),\r
+// TOFIX!!!\r
+//\r
+#define EFI_ACPI_VLV_LPI_TRIGGER {0x7F,0x1,0x2,0x0,0x64}\r
+\r
+//\r
+// LPI residency counter (MMIO)\r
+//\r
+#define EFI_ACPI_VLV_LPI_RES_COUNTER0 {0x0,32,0x0,0x03,0xFED03080}\r
+#define EFI_ACPI_VLV_LPI_RES_COUNTER1 {0x0,32,0x0,0x03,0xFED03084}\r
+#define EFI_ACPI_VLV_LPI_RES_COUNTER2 {0x0,32,0x0,0x03,0xFED03088}\r
+#define EFI_ACPI_VLV_LPI_RES_COUNTER3 {0x0,32,0x0,0x03,0xFED0308C}\r
+\r
+//\r
+// LPI break-even residency in us - all match S0i3 residency\r
+// Residency estimate: Latency x 3\r
+//\r
+#define EFI_ACPI_VLV_LPI_MIN_RES0 15000\r
+#define EFI_ACPI_VLV_LPI_MIN_RES1 15000\r
+#define EFI_ACPI_VLV_LPI_MIN_RES2 15000\r
+#define EFI_ACPI_VLV_LPI_MIN_RES3 15000\r
+\r
+//\r
+// LPI latency in us - all match S0i3 latency\r
+//\r
+#define EFI_ACPI_VLV_LPI_LATENCY0 5000\r
+#define EFI_ACPI_VLV_LPI_LATENCY1 5000\r
+#define EFI_ACPI_VLV_LPI_LATENCY2 5000\r
+#define EFI_ACPI_VLV_LPI_LATENCY3 5000\r
+\r
+\r
+//\r
+// LPI ID\r
+//\r
+#define EFI_ACPI_VLV_LPI_UNIQUE_ID0 0\r
+#define EFI_ACPI_VLV_LPI_UNIQUE_ID1 1\r
+#define EFI_ACPI_VLV_LPI_UNIQUE_ID2 2\r
+#define EFI_ACPI_VLV_LPI_UNIQUE_ID3 3\r
+\r
+//\r
+// LPI ACPI table header\r
+//\r
+\r
+\r
+typedef struct _EFI_ACPI_LOW_POWER_IDLE_TABLE {\r
+ EFI_ACPI_DESCRIPTION_HEADER Header;\r
+ EFI_ACPI_MWAIT_LPI_STATE_DESCRIPTOR LpiStates[EFI_ACPI_VLV_LPI_STATE_COUNT];\r
+} EFI_ACPI_LOW_POWER_IDLE_TABLE;\r
+\r
+#pragma pack()\r
+\r
+EFI_ACPI_LOW_POWER_IDLE_TABLE Lpit = {\r
+\r
+ //\r
+ // Header\r
+ //\r
+\r
+\r
+ EFI_ACPI_LOW_POWER_IDLE_TABLE_SIGNATURE,\r
+ sizeof (EFI_ACPI_LOW_POWER_IDLE_TABLE),\r
+ EFI_ACPI_LOW_POWER_IDLE_TABLE_REVISION ,\r
+\r
+ //\r
+ // Checksum will be updated at runtime\r
+ //\r
+ 0x00,\r
+\r
+ //\r
+ // It is expected that these values will be updated at runtime\r
+ //\r
+ ' ', ' ', ' ', ' ', ' ', ' ',\r
+\r
+ 0,\r
+ EFI_ACPI_OEM_LPIT_REVISION,\r
+ 0,\r
+ 0,\r
+\r
+\r
+\r
+ //\r
+ // Descriptor\r
+ //\r
+ {\r
+ {\r
+ EFI_ACPI_LOW_POWER_IDLE_MWAIT_TYPE,\r
+ sizeof(EFI_ACPI_MWAIT_LPI_STATE_DESCRIPTOR),\r
+ EFI_ACPI_VLV_LPI_UNIQUE_ID0,\r
+ {0,0},\r
+ {EFI_ACPI_LOW_POWER_IDLE_DEFAULT_FLAG}, // Flags\r
+ EFI_ACPI_VLV_LPI_TRIGGER, //EntryTrigger\r
+ EFI_ACPI_VLV_LPI_MIN_RES0, //Residency\r
+ EFI_ACPI_VLV_LPI_LATENCY0, //Latency\r
+ EFI_ACPI_VLV_LPI_RES_COUNTER0, //ResidencyCounter\r
+ EFI_ACPI_LOW_POWER_IDLE_RES_FREQ_8K //Residency counter frequency\r
+ },\r
+ {\r
+ EFI_ACPI_LOW_POWER_IDLE_MWAIT_TYPE,\r
+ sizeof(EFI_ACPI_MWAIT_LPI_STATE_DESCRIPTOR),\r
+ EFI_ACPI_VLV_LPI_UNIQUE_ID1,\r
+ {0,0},\r
+ {EFI_ACPI_LOW_POWER_IDLE_DEFAULT_FLAG}, // Flags\r
+ EFI_ACPI_VLV_LPI_TRIGGER, //EntryTrigger\r
+ EFI_ACPI_VLV_LPI_MIN_RES1, //Residency\r
+ EFI_ACPI_VLV_LPI_LATENCY1, //Latency\r
+ EFI_ACPI_VLV_LPI_RES_COUNTER1, //ResidencyCounter\r
+ EFI_ACPI_LOW_POWER_IDLE_RES_FREQ_8K //Residency counter frequency\r
+ },\r
+ {\r
+ EFI_ACPI_LOW_POWER_IDLE_MWAIT_TYPE,\r
+ sizeof(EFI_ACPI_MWAIT_LPI_STATE_DESCRIPTOR),\r
+ EFI_ACPI_VLV_LPI_UNIQUE_ID2,\r
+ {0,0},\r
+ {EFI_ACPI_LOW_POWER_IDLE_DEFAULT_FLAG}, // Flags\r
+ EFI_ACPI_VLV_LPI_TRIGGER, //EntryTrigger\r
+ EFI_ACPI_VLV_LPI_MIN_RES2, //Residency\r
+ EFI_ACPI_VLV_LPI_LATENCY2, //Latency\r
+ EFI_ACPI_VLV_LPI_RES_COUNTER2, //ResidencyCounter\r
+ EFI_ACPI_LOW_POWER_IDLE_RES_FREQ_8K //Residency counter frequency\r
+ },\r
+ {\r
+ EFI_ACPI_LOW_POWER_IDLE_MWAIT_TYPE,\r
+ sizeof(EFI_ACPI_MWAIT_LPI_STATE_DESCRIPTOR),\r
+ EFI_ACPI_VLV_LPI_UNIQUE_ID3,\r
+ {0,0},\r
+ {EFI_ACPI_LOW_POWER_IDLE_DEFAULT_FLAG}, // Flags\r
+ EFI_ACPI_VLV_LPI_TRIGGER, //EntryTrigger\r
+ EFI_ACPI_VLV_LPI_MIN_RES3, //Residency\r
+ EFI_ACPI_VLV_LPI_LATENCY3, //Latency\r
+ EFI_ACPI_VLV_LPI_RES_COUNTER3, //ResidencyCounter\r
+ EFI_ACPI_LOW_POWER_IDLE_RES_FREQ_8K //Residency counter frequency\r
+ }\r
+ }\r
+\r
+};\r
+\r
+\r
+VOID*\r
+ReferenceAcpiTable (\r
+ VOID\r
+ )\r
+{\r
+ //\r
+ // Reference the table being generated to prevent the optimizer from\r
+ // removing the data structure from the executable\r
+ //\r
+ return (VOID*)&Lpit;\r
+}\r
--- /dev/null
+/*++\r
+\r
+Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>\r
+\r
+ This program and the accompanying materials are licensed and made available under\r
+ the terms and conditions of the BSD License that accompanies this distribution.\r
+ The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php.\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+Module Name:\r
+\r
+ Madt.h\r
+\r
+Abstract:\r
+\r
+ This file describes the contents of the ACPI Multiple APIC Description\r
+ Table (MADT). Some additional ACPI values are defined in Acpi1_0.h and\r
+ Acpi2_0.h.\r
+ To make changes to the MADT, it is necessary to update the count for the\r
+ APIC structure being updated, and to modify table found in Madt.c.\r
+\r
+--*/\r
+\r
+#ifndef _MADT_H\r
+#define _MADT_H\r
+\r
+//\r
+// Statements that include other files\r
+//\r
+#include "AcpiTablePlatform.h"\r
+#include <IndustryStandard/Acpi10.h>\r
+#include <IndustryStandard/Acpi20.h>\r
+#include <IndustryStandard/Acpi30.h>\r
+#include "Platform.h"\r
+\r
+//\r
+// MADT Definitions\r
+//\r
+#define EFI_ACPI_OEM_MADT_REVISION 0x00000000\r
+//\r
+// Multiple APIC Flags are defined in AcpiX.0.h\r
+//\r
+#define EFI_ACPI_1_0_MULTIPLE_APIC_FLAGS (EFI_ACPI_1_0_PCAT_COMPAT)\r
+#define EFI_ACPI_2_0_MULTIPLE_APIC_FLAGS (EFI_ACPI_2_0_PCAT_COMPAT)\r
+#define EFI_ACPI_3_0_MULTIPLE_APIC_FLAGS (EFI_ACPI_3_0_PCAT_COMPAT)\r
+#define EFI_ACPI_4_0_MULTIPLE_APIC_FLAGS (EFI_ACPI_4_0_PCAT_COMPAT)\r
+\r
+//\r
+// Define the number of each table type.\r
+// This is where the table layout is modified.\r
+//\r
+#define EFI_ACPI_PROCESSOR_LOCAL_APIC_COUNT MAX_CPU_NUM\r
+#define EFI_ACPI_LOCAL_APIC_NMI_COUNT MAX_CPU_NUM\r
+#define EFI_ACPI_IO_APIC_COUNT 1\r
+#define EFI_ACPI_INTERRUPT_SOURCE_OVERRIDE_COUNT 2\r
+#define EFI_ACPI_NON_MASKABLE_INTERRUPT_SOURCE_COUNT 0\r
+#define EFI_ACPI_LOCAL_APIC_ADDRESS_OVERRIDE_COUNT 0\r
+#define EFI_ACPI_IO_SAPIC_COUNT 0\r
+#define EFI_ACPI_PROCESSOR_LOCAL_SAPIC_COUNT 0\r
+#define EFI_ACPI_PLATFORM_INTERRUPT_SOURCES_COUNT 0\r
+\r
+//\r
+// MADT structure\r
+//\r
+//\r
+// Ensure proper structure formats\r
+//\r
+#pragma pack(1)\r
+//\r
+// ACPI 1.0 Table structure\r
+//\r
+typedef struct {\r
+ EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header;\r
+\r
+#if EFI_ACPI_PROCESSOR_LOCAL_APIC_COUNT > 0\r
+ EFI_ACPI_1_0_PROCESSOR_LOCAL_APIC_STRUCTURE LocalApic[EFI_ACPI_PROCESSOR_LOCAL_APIC_COUNT];\r
+#endif\r
+\r
+#if EFI_ACPI_IO_APIC_COUNT > 0\r
+ EFI_ACPI_1_0_IO_APIC_STRUCTURE IoApic[EFI_ACPI_IO_APIC_COUNT];\r
+#endif\r
+\r
+#if EFI_ACPI_INTERRUPT_SOURCE_OVERRIDE_COUNT > 0\r
+ EFI_ACPI_1_0_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE Iso[EFI_ACPI_INTERRUPT_SOURCE_OVERRIDE_COUNT];\r
+#endif\r
+\r
+#if EFI_ACPI_NON_MASKABLE_INTERRUPT_SOURCE_COUNT > 0\r
+ EFI_ACPI_1_0_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE NmiSource[EFI_ACPI_NON_MASKABLE_INTERRUPT_SOURCE_COUNT];\r
+#endif\r
+\r
+#if EFI_ACPI_LOCAL_APIC_NMI_COUNT > 0\r
+ EFI_ACPI_1_0_LOCAL_APIC_NMI_STRUCTURE LocalApicNmi[EFI_ACPI_LOCAL_APIC_NMI_COUNT];\r
+#endif\r
+\r
+#if EFI_ACPI_LOCAL_APIC_ADDRESS_OVERRIDE_COUNT > 0\r
+ EFI_ACPI_1_0_LOCAL_APIC_ADDRESS_OVERRIDE_STRUCTURE LocalApicOverride[EFI_ACPI_LOCAL_APIC_ADDRESS_OVERRIDE_COUNT];\r
+#endif\r
+\r
+} EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE;\r
+\r
+//\r
+// ACPI 2.0 Table structure\r
+//\r
+typedef struct {\r
+ EFI_ACPI_2_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header;\r
+\r
+#if EFI_ACPI_PROCESSOR_LOCAL_APIC_COUNT > 0\r
+ EFI_ACPI_2_0_PROCESSOR_LOCAL_APIC_STRUCTURE LocalApic[EFI_ACPI_PROCESSOR_LOCAL_APIC_COUNT];\r
+#endif\r
+\r
+#if EFI_ACPI_IO_APIC_COUNT > 0\r
+ EFI_ACPI_2_0_IO_APIC_STRUCTURE IoApic[EFI_ACPI_IO_APIC_COUNT];\r
+#endif\r
+\r
+#if EFI_ACPI_INTERRUPT_SOURCE_OVERRIDE_COUNT > 0\r
+ EFI_ACPI_2_0_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE Iso[EFI_ACPI_INTERRUPT_SOURCE_OVERRIDE_COUNT];\r
+#endif\r
+\r
+#if EFI_ACPI_NON_MASKABLE_INTERRUPT_SOURCE_COUNT > 0\r
+ EFI_ACPI_2_0_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE NmiSource[EFI_ACPI_NON_MASKABLE_INTERRUPT_SOURCE_COUNT];\r
+#endif\r
+\r
+#if EFI_ACPI_LOCAL_APIC_NMI_COUNT > 0\r
+ EFI_ACPI_2_0_LOCAL_APIC_NMI_STRUCTURE LocalApicNmi[EFI_ACPI_LOCAL_APIC_NMI_COUNT];\r
+#endif\r
+\r
+#if EFI_ACPI_LOCAL_APIC_ADDRESS_OVERRIDE_COUNT > 0\r
+ EFI_ACPI_2_0_LOCAL_APIC_ADDRESS_OVERRIDE_STRUCTURE LocalApicOverride[EFI_ACPI_LOCAL_APIC_ADDRESS_OVERRIDE_COUNT];\r
+#endif\r
+\r
+#if EFI_ACPI_IO_SAPIC_COUNT > 0\r
+ EFI_ACPI_2_0_IO_SAPIC_STRUCTURE IoSapic[EFI_ACPI_IO_SAPIC_COUNT];\r
+#endif\r
+\r
+#if EFI_ACPI_PROCESSOR_LOCAL_SAPIC_COUNT > 0\r
+ EFI_ACPI_2_0_PROCESSOR_LOCAL_SAPIC_STRUCTURE LocalSapic[EFI_ACPI_PROCESSOR_LOCAL_SAPIC_COUNT];\r
+#endif\r
+\r
+#if EFI_ACPI_PLATFORM_INTERRUPT_SOURCES_COUNT > 0\r
+ EFI_ACPI_2_0_PLATFORM_INTERRUPT_SOURCES_STRUCTURE PlatformInterruptSources[EFI_ACPI_PLATFORM_INTERRUPT_SOURCES_COUNT];\r
+#endif\r
+\r
+} EFI_ACPI_2_0_MULTIPLE_APIC_DESCRIPTION_TABLE;\r
+\r
+//\r
+// ACPI 3.0 Table structure\r
+//\r
+typedef struct {\r
+ EFI_ACPI_3_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header;\r
+\r
+#if EFI_ACPI_PROCESSOR_LOCAL_APIC_COUNT > 0 // Type 0x00\r
+ EFI_ACPI_3_0_PROCESSOR_LOCAL_APIC_STRUCTURE LocalApic[EFI_ACPI_PROCESSOR_LOCAL_APIC_COUNT];\r
+#endif\r
+\r
+#if EFI_ACPI_IO_APIC_COUNT > 0 // Type 0x01\r
+ EFI_ACPI_3_0_IO_APIC_STRUCTURE IoApic[EFI_ACPI_IO_APIC_COUNT];\r
+#endif\r
+\r
+#if EFI_ACPI_INTERRUPT_SOURCE_OVERRIDE_COUNT > 0 // Type 0x02\r
+ EFI_ACPI_3_0_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE Iso[EFI_ACPI_INTERRUPT_SOURCE_OVERRIDE_COUNT];\r
+#endif\r
+\r
+#if EFI_ACPI_NON_MASKABLE_INTERRUPT_SOURCE_COUNT > 0 // Type 0x03\r
+ EFI_ACPI_3_0_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE NmiSource[EFI_ACPI_NON_MASKABLE_INTERRUPT_SOURCE_COUNT];\r
+#endif\r
+\r
+#if EFI_ACPI_LOCAL_APIC_NMI_COUNT > 0 // Type 0x04\r
+ EFI_ACPI_3_0_LOCAL_APIC_NMI_STRUCTURE LocalApicNmi[EFI_ACPI_LOCAL_APIC_NMI_COUNT];\r
+#endif\r
+\r
+#if EFI_ACPI_LOCAL_APIC_ADDRESS_OVERRIDE_COUNT > 0 // Type 0x05\r
+ EFI_ACPI_3_0_LOCAL_APIC_ADDRESS_OVERRIDE_STRUCTURE LocalApicOverride[EFI_ACPI_LOCAL_APIC_ADDRESS_OVERRIDE_COUNT];\r
+#endif\r
+\r
+#if EFI_ACPI_IO_SAPIC_COUNT > 0 // Type 0x06\r
+ EFI_ACPI_3_0_IO_SAPIC_STRUCTURE IoSapic[EFI_ACPI_IO_SAPIC_COUNT];\r
+#endif\r
+\r
+#if EFI_ACPI_PROCESSOR_LOCAL_SAPIC_COUNT > 0 // Type 0x07 : This table changes in madt 2.0\r
+ EFI_ACPI_3_0_PROCESSOR_LOCAL_SAPIC_STRUCTURE LocalSapic[EFI_ACPI_PROCESSOR_LOCAL_SAPIC_COUNT];\r
+#endif\r
+\r
+#if EFI_ACPI_PLATFORM_INTERRUPT_SOURCES_COUNT > 0 // Type 0x08\r
+ EFI_ACPI_3_0_PLATFORM_INTERRUPT_SOURCES_STRUCTURE PlatformInterruptSources[EFI_ACPI_PLATFORM_INTERRUPT_SOURCES_COUNT];\r
+#endif\r
+\r
+} EFI_ACPI_3_0_MULTIPLE_APIC_DESCRIPTION_TABLE;\r
+\r
+#pragma pack()\r
+\r
+#endif\r
--- /dev/null
+/*++\r
+\r
+ Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>\r
+\r
+ This program and the accompanying materials are licensed and made available under\r
+ the terms and conditions of the BSD License that accompanies this distribution.\r
+ The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php.\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+\r
+Module Name:\r
+\r
+ Madt3.0.c\r
+\r
+Abstract:\r
+\r
+ This file contains a structure definition for the ACPI 2.0 Multiple APIC\r
+ Description Table (MADT). Any changes to the MADT table require updating the\r
+ respective structure count in Madt.h and then adding the structure to the\r
+ MADT defined in this file. The table layout is defined in Madt.h and the\r
+ table contents are defined in Acpi3_0.h and Madt.h.\r
+\r
+--*/\r
+\r
+//\r
+// Statements that include other files\r
+//\r
+#include "Madt.h"\r
+#include <IndustryStandard/Acpi50.h>\r
+\r
+//\r
+// Multiple APIC Description Table\r
+//\r
+EFI_ACPI_3_0_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = {\r
+ EFI_ACPI_3_0_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE, // **Signatures are the same 1.0-3.0 because it says "APIC".\r
+ sizeof (EFI_ACPI_3_0_MULTIPLE_APIC_DESCRIPTION_TABLE), // **Length\r
+ EFI_ACPI_5_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION,\r
+ //\r
+ // EFI_ACPI_3_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION, // **Table Revision must be 2.0 for ACPI 3.0\r
+ // Checksum will be updated at runtime\r
+ //\r
+ 0x00, // **Check sum\r
+ //\r
+ // It is expected that these values will be programmed at runtime\r
+ //\r
+ ' ', // OEMID\r
+ ' ', // Creative way to\r
+ ' ', // make six bytes\r
+ ' ', // of space in\r
+ ' ', // a table for\r
+ ' ', // **OEMID\r
+ 0, // **OEM Table ID\r
+ EFI_ACPI_OEM_MADT_REVISION, // **OEM Revision\r
+ 0, // **Creator ID\r
+ 0, // **Creator Revision\r
+ //\r
+ // MADT specific fields\r
+ //\r
+ LOCAL_APIC_ADDRESS, // **Local APIC Address\r
+ EFI_ACPI_4_0_MULTIPLE_APIC_FLAGS, // **Flags\r
+ //\r
+ // Processor Local APIC Structure\r
+ // Correct processor order, Primary threads first then Hyper threads\r
+ // And correct APIC-ids\r
+ // This text below is included as a reference until Thurley is 100%:\r
+ // According to EDS the Local APIC ID is determined based of a bit structure\r
+ // Bit 24: Core ID Bit 25: Core Pair ID Bit 26-27: Reserved Bit 28-30: Socket ID Bit 31: Reserved\r
+ // 4 Sockets and 4 Cores per Socket.\r
+ // So possible LAPIC IDs 00, 01, 02, 03, 10, 11, 12, 13, 20, 21, 22, 23, 30, 31, 32, 33\r
+ // Static Entries 00, 10, 20, 30, 01, 11, 21, 31, 02, 12, 22, 32, 03, 13, 23, 33\r
+ // BSP needs to be first entry in table. Check before boot. If BSP non zero need to rotate the entries.\r
+ // Suppore BSP is LAPIC ID xy. Rotate the table by using formula [x + (y * 4)]\r
+ // So if BSP LAPIC ID is 21 then table rotated 6 times.\r
+ // End of Reference Text.\r
+ // Thurley is supposed to be 2 sockets, 4 cores, and hyperthreading available per each core.\r
+ // 2 (sockets) x 4 (cores) = 8 (processors non-HT), 8 (processors non-HT) x 2 (HT/proc) = 16 (HT procs)\r
+ // Rhyme & reason of the ordering below. This is a best guess ordering for now,\r
+ // Thurley EPS may give better info on LAPIC numbers.\r
+ // Ordering was established to help dissipate heat across two sockets evenly.\r
+ // Since logical processor number only has to be unique, I followed\r
+ // a similar approach to high end servers and have the first digit of the LAPIC\r
+ // id the socket number.\r
+ //\r
+ EFI_ACPI_3_0_PROCESSOR_LOCAL_APIC, // Type 0x00\r
+ sizeof (EFI_ACPI_3_0_PROCESSOR_LOCAL_APIC_STRUCTURE), // Length\r
+ 0x01, // Processor ID\r
+ 0x00, // Local APIC ID\r
+ 0x00000001, // Flags - Disabled (until initialized by platform driver)\r
+ EFI_ACPI_3_0_PROCESSOR_LOCAL_APIC, // Type\r
+ sizeof (EFI_ACPI_3_0_PROCESSOR_LOCAL_APIC_STRUCTURE), // Length\r
+ 0x02, // Processor ID\r
+ 0x02, // Local APIC ID //Todo: Temp change APIC ID order for fixing VLV X0 not enable 2 CPU in Windows.\r
+ 0x00000001, // Flags - Disabled (until initialized by platform driver)\r
+ EFI_ACPI_3_0_PROCESSOR_LOCAL_APIC, // Type\r
+ sizeof (EFI_ACPI_3_0_PROCESSOR_LOCAL_APIC_STRUCTURE), // Length\r
+ 0x03, // Processor ID\r
+ 0x04, // Local APIC ID\r
+ 0x00000001, // Flags - Disabled (until initialized by platform driver)\r
+ EFI_ACPI_3_0_PROCESSOR_LOCAL_APIC, // Type\r
+ sizeof (EFI_ACPI_3_0_PROCESSOR_LOCAL_APIC_STRUCTURE), // Length\r
+ 0x04, // Processor ID\r
+ 0x06, // Local APIC ID\r
+ 0x00000001, // Flags - Disabled (until initialized by platform driver)\r
+ //\r
+ // *************** IO APIC Structure ******************\r
+ //\r
+ //\r
+ //\r
+ // ************************** I/O APIC **************\r
+ //\r
+ EFI_ACPI_3_0_IO_APIC, // Type 0x01\r
+ sizeof (EFI_ACPI_3_0_IO_APIC_STRUCTURE), // Length\r
+ ICH_IOAPIC_ID, // IO APIC ID\r
+ EFI_ACPI_RESERVED_BYTE, // Reserved EFI_ACPI_RESERVED_BYTE\r
+ IO_APIC_ADDRESS, // IO APIC Address (physical) 0xFEC00000\r
+ 0x18 * 0, // Global System Interrupt Base\r
+\r
+ //\r
+ // Interrupt Source Override Structure: Sample\r
+ //\r
+ // EFI_ACPI_2_0_INTERRUPT_SOURCE_OVERRIDE, // Type 0x02\r
+ // sizeof (EFI_ACPI_2_0_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE),// Length\r
+ // 0x00, // Bus\r
+ // 0x00, // Source\r
+ // 0x00000000, // Global System Interrupt\r
+ // 0x0000,
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