Vlv2TbltDevicePkg/Include/Library/EfiRegTableLib.h

   1 /*++
   2
   3   Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>
   4
   5   This program and the accompanying materials are licensed and made available under
   6   the terms and conditions of the BSD License that accompanies this distribution.
   7   The full text of the license may be found at
   8   http://opensource.org/licenses/bsd-license.php.
   9
  10   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12
  13
  14
  15 Module Name:
  16
  17   EfiRegTableLib.h
  18
  19 Abstract:
  20
  21   Definitions and macros for building register tables for chipset
  22   initialization..
  23
  24   Components linking this lib must include CpuIo, PciRootBridgeIo, and
  25   BootScriptSave protocols in their DPX.
  26
  27
  28
  29 --*/
  30
  31 #ifndef EFI_REG_TABLE_H
  32 #define EFI_REG_TABLE_H
  33
  34
  35 #include <PiDxe.h>
  36 #include <Library/BaseLib.h>
  37 #include <Library/DebugLib.h>
  38 #include <Library/UefiLib.h>
  39 #include <Library/UefiDriverEntryPoint.h>
  40 #include <Protocol/CpuIo.h>
  41 #include <Protocol/BootScriptSave.h>
  42 #include <Framework/BootScript.h>
  43 #include <Protocol/PciRootBridgeIo.h>
  44
  45
  46 #define OPCODE_BASE(OpCode)       ((UINT8)((OpCode) & 0xFF))
  47 #define OPCODE_FLAGS(OpCode)      ((UINT8)(((OpCode) >> 8) & 0xFF))
  48 #define OPCODE_EXTRA_DATA(OpCode) ((UINT16)((OpCode) >> 16))
  49
  50 //
  51 // RegTable Base OpCodes
  52 //
  53 #define OP_TERMINATE_TABLE                0
  54 #define OP_MEM_WRITE                      1
  55 #define OP_MEM_READ_MODIFY_WRITE          2
  56 #define OP_IO_WRITE                       3
  57 #define OP_IO_READ_MODIFY_WRITE           4
  58 #define OP_PCI_WRITE                      5
  59 #define OP_PCI_READ_MODIFY_WRITE          6
  60 #define OP_STALL                          7
  61
  62 //
  63 // RegTable OpCode Flags
  64 //
  65 #define OPCODE_FLAG_S3SAVE                1
  66
  67
  68 #define TERMINATE_TABLE { (UINT32) OP_TERMINATE_TABLE, (UINT32) 0, (UINT32) 0 }
  69
  70
  71 //
  72 // REG_TABLE_ENTRY_PCI_WRITE encodes the width in the upper bits of the OpCode
  73 // as one of the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH values
  74 //
  75 typedef struct {
  76   UINT32                                OpCode;
  77   UINT32                                PciAddress;
  78   UINT32                                Data;
  79 } EFI_REG_TABLE_PCI_WRITE;
  80
  81 #define PCI_WRITE(Bus, Dev, Fnc, Reg, Width, Data, S3Flag)                    \
  82   {                                                                           \
  83     (UINT32) (OP_PCI_WRITE | ((S3Flag) << 8) | ((Width) << 16)),              \
  84     (UINT32) (EFI_PCI_ADDRESS ((Bus), (Dev), (Fnc), (Reg))),                  \
  85     (UINT32) (Data),                                                          \
  86     (UINT32) (0)                                                              \
  87   }
  88
  89 typedef struct {
  90   UINT32                                OpCode;
  91   UINT32                                MemAddress;
  92   UINT32                                Data;
  93 } EFI_REG_TABLE_MEM_WRITE;
  94
  95 typedef struct {
  96   UINT32                                OpCode;
  97   UINT32                                PciAddress;
  98   UINT32                                OrMask;
  99   UINT32                                AndMask;
 100 } EFI_REG_TABLE_PCI_READ_MODIFY_WRITE;
 101
 102 #define PCI_READ_MODIFY_WRITE(Bus, Dev, Fnc, Reg, Width, OrMask, AndMask, S3Flag)  \
 103   {                                                                           \
 104     (UINT32) (OP_PCI_READ_MODIFY_WRITE | ((S3Flag) << 8) | ((Width) << 16)),  \
 105     (UINT32) (EFI_PCI_ADDRESS ((Bus), (Dev), (Fnc), (Reg))),                  \
 106     (UINT32) (OrMask),                                                        \
 107     (UINT32) (AndMask)                                                        \
 108   }
 109
 110 typedef struct {
 111   UINT32                                OpCode;
 112   UINT32                                MemAddress;
 113   UINT32                                OrMask;
 114   UINT32                                AndMask;
 115 } EFI_REG_TABLE_MEM_READ_MODIFY_WRITE;
 116
 117 #define MEM_READ_MODIFY_WRITE(Address, Width, OrMask, AndMask, S3Flag)  \
 118   {                                                                           \
 119     (UINT32) (OP_MEM_READ_MODIFY_WRITE | ((S3Flag) << 8) | ((Width) << 16)),  \
 120     (UINT32) (Address),                  \
 121     (UINT32) (OrMask),                                                        \
 122     (UINT32) (AndMask)                                                        \
 123   }
 124
 125 typedef struct {
 126   UINT32                                OpCode;
 127   UINT32                                Field2;
 128   UINT32                                Field3;
 129   UINT32                                Field4;
 130 } EFI_REG_TABLE_GENERIC;
 131
 132 typedef union {
 133   EFI_REG_TABLE_GENERIC                 Generic;
 134   EFI_REG_TABLE_PCI_WRITE               PciWrite;
 135   EFI_REG_TABLE_PCI_READ_MODIFY_WRITE   PciReadModifyWrite;
 136   EFI_REG_TABLE_MEM_READ_MODIFY_WRITE   MemReadModifyWrite;
 137 } EFI_REG_TABLE;
 138
 139 /**
 140   Processes register table assuming which may contain PCI, IO, MEM, and STALL
 141   entries.
 142
 143   No parameter checking is done so the caller must be careful about omitting
 144   values for PciRootBridgeIo or CpuIo parameters.  If the regtable does
 145   not contain any PCI accesses, it is safe to omit the PciRootBridgeIo (supply
 146   NULL).  If the regtable does not contain any IO or Mem entries, it is safe to
 147   omit the CpuIo (supply NULL).
 148
 149   The RegTableEntry parameter is not checked, but is required.
 150
 151   gBS is assumed to have been defined and is used when processing stalls.
 152
 153   The function processes each entry sequentially until an OP_TERMINATE_TABLE
 154   entry is encountered.
 155
 156   @param[in] RegTableEntry    A pointer to the register table to process
 157
 158   @param[in] PciRootBridgeIo  A pointer to the instance of PciRootBridgeIo that is used
 159                               when processing PCI table entries
 160
 161   @param[in] CpuIo            A pointer to the instance of CpuIo that is used when processing IO and
 162                               MEM table entries
 163
 164   @retval Nothing.
 165
 166 **/
 167 VOID
 168 ProcessRegTablePci (
 169   EFI_REG_TABLE                   * RegTableEntry,
 170   EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL * PciRootBridgeIo,
 171   EFI_CPU_IO_PROTOCOL             * CpuIo
 172   );
 173
 174 /**
 175   Processes register table assuming which may contain IO, MEM, and STALL
 176   entries, but must NOT contain any PCI entries.  Any PCI entries cause an
 177   ASSERT in a DEBUG build and are skipped in a free build.
 178
 179   No parameter checking is done.  Both RegTableEntry and CpuIo parameters are
 180   required.
 181
 182   gBS is assumed to have been defined and is used when processing stalls.
 183
 184   The function processes each entry sequentially until an OP_TERMINATE_TABLE
 185   entry is encountered.
 186
 187   @param[in] RegTableEntry - A pointer to the register table to process
 188
 189   @param[in] CpuIo - A pointer to the instance of CpuIo that is used when processing IO and
 190                   MEM table entries
 191
 192   @retval Nothing.
 193
 194 **/
 195 VOID
 196 ProcessRegTableCpu (
 197   EFI_REG_TABLE                   * RegTableEntry,
 198   EFI_CPU_IO_PROTOCOL             * CpuIo
 199   );
 200
 201 #endif