3 Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
5 This program and the accompanying materials are licensed and made available under
6 the terms and conditions of the BSD License that accompanies this distribution.
7 The full text of the license may be found at
8 http://opensource.org/licenses/bsd-license.php.
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
21 Platform Initialization Driver.
26 #include "PlatformDxe.h"
28 #include "PchCommonDefinitions.h"
29 #include <Protocol/UsbPolicy.h>
30 #include <Protocol/PchPlatformPolicy.h>
31 #include <Protocol/TpmMp.h>
32 #include <Protocol/CpuIo2.h>
33 #include <Library/S3BootScriptLib.h>
34 #include <Guid/PciLanInfo.h>
35 #include <Guid/ItkData.h>
36 #include <Library/PciLib.h>
37 #include <PlatformBootMode.h>
38 #include <Guid/EventGroup.h>
39 #include <Guid/Vlv2Variable.h>
40 #include <Protocol/GlobalNvsArea.h>
41 #include <Protocol/IgdOpRegion.h>
42 #include <Library/PcdLib.h>
45 // VLV2 GPIO GROUP OFFSET
47 #define GPIO_SCORE_OFFSET 0x0000
48 #define GPIO_NCORE_OFFSET 0x1000
49 #define GPIO_SSUS_OFFSET 0x2000
56 GPIO_CONF_PAD_INIT mTB_BL_GpioInitData_SC_TRI_Exit_boot_Service
[] =
58 // Pad Name GPIO Number Used As GPO Default Function# INT Capable Interrupt Type PULL H/L MMIO Offset
59 GPIO_INIT_ITEM("LPC_CLKOUT0 GPIOC_47 " ,TRISTS
,NA
,F0
, , ,NONE
,0x47),
60 GPIO_INIT_ITEM("LPC_CLKOUT1 GPIOC_48 " ,TRISTS
,NA
,F0
, , ,NONE
,0x41),
64 EFI_GUID mSystemHiiExportDatabase
= EFI_HII_EXPORT_DATABASE_GUID
;
65 EFI_GUID mPlatformDriverGuid
= EFI_PLATFORM_DRIVER_GUID
;
66 SYSTEM_CONFIGURATION mSystemConfiguration
;
67 SYSTEM_PASSWORDS mSystemPassword
;
68 EFI_HANDLE mImageHandle
;
69 BOOLEAN mMfgMode
= FALSE
;
70 VOID
*mDxePlatformStringPack
;
71 UINT32 mPlatformBootMode
= PLATFORM_NORMAL_MODE
;
72 extern CHAR16 gItkDataVarName
[];
75 EFI_PLATFORM_INFO_HOB mPlatformInfo
;
76 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*mPciRootBridgeIo
;
77 EFI_EVENT mReadyToBootEvent
;
79 UINT8 mSmbusRsvdAddresses
[] = PLATFORM_SMBUS_RSVD_ADDRESSES
;
80 UINT8 mNumberSmbusAddress
= sizeof( mSmbusRsvdAddresses
) / sizeof( mSmbusRsvdAddresses
[0] );
81 UINT32 mSubsystemVidDid
;
82 UINT32 mSubsystemAudioVidDid
;
84 UINTN mPciLanCount
= 0;
85 VOID
*mPciLanInfo
= NULL
;
88 static EFI_SPEAKER_IF_PROTOCOL mSpeakerInterface
= {
93 EFI_USB_POLICY_PROTOCOL mUsbPolicyData
= {0};
96 CFIO_PNP_INIT mTB_BL_GpioInitData_SC_TRI_S0ix_Exit_boot_Service
[] =
98 {0x410 ,0x20038e10}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_clkout1_pconf0
99 {0x470 ,0x20038e10}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_clkout0_pconf0
100 {0x560 ,0x20038e10}, //vlv.gpio.gpscore.cfio_regs_pad_ilb_serirq_pconf0
101 {0x450 ,0x20038e10}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_frameb_pconf0
102 {0x480 ,0x20038e10}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_clkrunb_pconf0
103 {0x420 ,0x20038e10}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_ad3_pconf0
104 {0x430 ,0x20038e10}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_ad2_pconf0
105 {0x440 ,0x20038e10}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_ad1_pconf0
106 {0x460 ,0x20038e10}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_ad0_pconf0
107 {0x418 ,0x00000006}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_clkout1_pad_val
108 {0x478 ,0x00000006}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_clkout0_pad_val
109 {0x568 ,0x00000006}, //vlv.gpio.gpscore.cfio_regs_pad_ilb_serirq_pad_val
110 {0x458 ,0x00000006}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_frameb_pad_val
111 {0x488 ,0x00000006}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_clkrunb_pad_val
112 {0x428 ,0x00000006}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_ad3_pad_val
113 {0x438 ,0x00000006}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_ad2_pad_val
114 {0x448 ,0x00000006}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_ad1_pad_val
115 {0x468 ,0x00000006}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_ad0_pad_val
120 IN VOID
*Destination
,
125 #if defined(FIRMWARE_ID_BACKWARD_COMPATIBLE) && (FIRMWARE_ID_BACKWARD_COMPATIBLE != 0)
133 InitializeClockRouting(
140 #if defined(SENSOR_INFO_VAR_SUPPORT) && SENSOR_INFO_VAR_SUPPORT != 0
142 InitializeSensorInfoVariable (
157 InitPlatformBootMode();
160 InitMfgAndConfigModeStateVar();
163 InitPchPlatformPolicy (
164 IN EFI_PLATFORM_INFO_HOB
*PlatformInfo
168 InitVlvPlatformPolicy (
172 InitSioPlatformPolicy(
184 InitPlatformUsbPolicy (
195 TristateLpcGpioConfig (
196 IN UINT32 Gpio_Mmio_Offset
,
197 IN UINT32 Gpio_Pin_Num
,
198 GPIO_CONF_PAD_INIT
* Gpio_Conf_Data
209 // GPIO WELL -- Memory base registers
213 // A0 BIOS Spec doesn't mention it although X0 does. comment out now.
214 // GPIO write 0x01001002 to IOBASE + Gpio_Mmio_Offset + 0x0900
217 for(index
=0; index
< Gpio_Pin_Num
; index
++)
220 // Calculate the MMIO Address for specific GPIO pin CONF0 register pointed by index.
222 mmio_conf0
= IO_BASE_ADDRESS
+ Gpio_Mmio_Offset
+ R_PCH_CFIO_PAD_CONF0
+ Gpio_Conf_Data
[index
].offset
* 16;
223 mmio_padval
= IO_BASE_ADDRESS
+ Gpio_Mmio_Offset
+ R_PCH_CFIO_PAD_VAL
+ Gpio_Conf_Data
[index
].offset
* 16;
226 DEBUG ((EFI_D_INFO
, "%s, ", Gpio_Conf_Data
[index
].pad_name
));
229 DEBUG ((EFI_D_INFO
, "Usage = %d, Func# = %d, IntType = %d, Pull Up/Down = %d, MMIO Base = 0x%08x, ",
230 Gpio_Conf_Data
[index
].usage
,
231 Gpio_Conf_Data
[index
].func
,
232 Gpio_Conf_Data
[index
].int_type
,
233 Gpio_Conf_Data
[index
].pull
,
237 // Step 1: PadVal Programming
239 pad_val
.dw
= MmioRead32(mmio_padval
);
242 // Config PAD_VAL only for GPIO (Non-Native) Pin
244 if(Native
!= Gpio_Conf_Data
[index
].usage
)
246 pad_val
.dw
&= ~0x6; // Clear bits 1:2
247 pad_val
.dw
|= (Gpio_Conf_Data
[index
].usage
& 0x6); // Set bits 1:2 according to PadVal
250 // set GPO default value
252 if(Gpio_Conf_Data
[index
].usage
== GPO
&& Gpio_Conf_Data
[index
].gpod4
!= NA
)
254 pad_val
.r
.pad_val
= Gpio_Conf_Data
[index
].gpod4
;
259 DEBUG ((EFI_D_INFO
, "Set PAD_VAL = 0x%08x, ", pad_val
.dw
));
261 MmioWrite32(mmio_padval
, pad_val
.dw
);
264 // Step 2: CONF0 Programming
265 // Read GPIO default CONF0 value, which is assumed to be default value after reset.
267 conf0_val
.dw
= MmioRead32(mmio_conf0
);
272 conf0_val
.r
.Func_Pin_Mux
= Gpio_Conf_Data
[index
].func
;
274 if(GPO
== Gpio_Conf_Data
[index
].usage
)
277 // If used as GPO, then internal pull need to be disabled
279 conf0_val
.r
.Pull_assign
= 0; // Non-pull
284 // Set PullUp / PullDown
286 if(P_20K_H
== Gpio_Conf_Data
[index
].pull
)
288 conf0_val
.r
.Pull_assign
= 0x1; // PullUp
289 conf0_val
.r
.Pull_strength
= 0x2;// 20K
291 else if(P_20K_L
== Gpio_Conf_Data
[index
].pull
)
293 conf0_val
.r
.Pull_assign
= 0x2; // PullDown
294 conf0_val
.r
.Pull_strength
= 0x2;// 20K
296 else if(P_NONE
== Gpio_Conf_Data
[index
].pull
)
298 conf0_val
.r
.Pull_assign
= 0; // Non-pull
302 ASSERT(FALSE
); // Invalid value
307 // Set INT Trigger Type
309 conf0_val
.dw
&= ~0x0f000000; // Clear bits 27:24
312 // Set INT Trigger Type
314 if(TRIG_
== Gpio_Conf_Data
[index
].int_type
)
317 // Interrupt not capable, clear bits 27:24
322 conf0_val
.dw
|= (Gpio_Conf_Data
[index
].int_type
& 0x0f)<<24;
325 DEBUG ((EFI_D_INFO
, "Set CONF0 = 0x%08x\n", conf0_val
.dw
));
328 // Write back the targeted GPIO config value according to platform (board) GPIO setting
330 MmioWrite32 (mmio_conf0
, conf0_val
.dw
);
333 // A0 BIOS Spec doesn't mention it although X0 does. comment out now.
334 // GPIO SCORE write 0x01001002 to IOBASE + 0x0900
340 SpiBiosProtectionFunction(
346 UINTN mPciD31F0RegBase
;
347 UINTN BiosFlaLower
= 0;
348 UINTN BiosFlaLimit
= 0x7fffff;
350 BiosFlaLower
= PcdGet32(PcdFlashMicroCodeAddress
)-PcdGet32(PcdFlashAreaBaseAddress
);
353 mPciD31F0RegBase
= MmPciAddress (0,
354 DEFAULT_PCI_BUS_NUMBER_PCH
,
355 PCI_DEVICE_NUMBER_PCH_LPC
,
356 PCI_FUNCTION_NUMBER_PCH_LPC
,
359 SpiBase
= MmioRead32(mPciD31F0RegBase
+ R_PCH_LPC_SPI_BASE
) & B_PCH_LPC_SPI_BASE_BAR
;
362 //Set SMM_BWP, WPD and LE bit
364 MmioOr32 ((UINTN
) (SpiBase
+ R_PCH_SPI_BCR
), (UINT8
) B_PCH_SPI_BCR_SMM_BWP
);
365 MmioAnd32 ((UINTN
) (SpiBase
+ R_PCH_SPI_BCR
), (UINT8
)(~B_PCH_SPI_BCR_BIOSWE
));
366 MmioOr32 ((UINTN
) (SpiBase
+ R_PCH_SPI_BCR
), (UINT8
) B_PCH_SPI_BCR_BLE
);
369 //First check if FLOCKDN or PR0FLOCKDN is set. No action if either of them set already.
371 if( (MmioRead16(SpiBase
+ R_PCH_SPI_HSFS
) & B_PCH_SPI_HSFS_FLOCKDN
) != 0 ||
372 (MmioRead32(SpiBase
+ R_PCH_SPI_IND_LOCK
)& B_PCH_SPI_IND_LOCK_PR0
) != 0) {
374 //Already locked. we could take no action here
376 DEBUG((EFI_D_INFO
, "PR0 already locked down. Stop configuring PR0.\n"));
383 MmioOr32((UINTN
)(SpiBase
+ R_PCH_SPI_PR0
),
384 B_PCH_SPI_PR0_RPE
|B_PCH_SPI_PR0_WPE
|\
385 (B_PCH_SPI_PR0_PRB_MASK
&(BiosFlaLower
>>12))|(B_PCH_SPI_PR0_PRL_MASK
&(BiosFlaLimit
>>12)<<16));
390 MmioOr16 ((UINTN
) (SpiBase
+ R_PCH_SPI_HSFS
), (UINT16
) (B_PCH_SPI_HSFS_FLOCKDN
));
393 // Verify if it's really locked.
395 if ((MmioRead16 (SpiBase
+ R_PCH_SPI_HSFS
) & B_PCH_SPI_HSFS_FLOCKDN
) == 0) {
396 DEBUG((EFI_D_ERROR
, "Failed to lock down PR0.\n"));
413 VarSize
= sizeof(SYSTEM_CONFIGURATION
);
414 Status
= gRT
->GetVariable(
416 &gEfiNormalSetupGuid
,
419 &mSystemConfiguration
425 PchAzaliaPciCfg32Or (R_PCH_HDA_PCS
, B_PCH_HDA_PCS_PMEE
);
428 //Program SATA PME_EN
430 PchSataPciCfg32Or (R_PCH_SATA_PMCS
, B_PCH_SATA_PMCS_PMEE
);
432 DEBUG ((EFI_D_INFO
, "InitPciDevPME mSystemConfiguration.EhciPllCfgEnable = 0x%x \n",mSystemConfiguration
.EhciPllCfgEnable
));
433 if (mSystemConfiguration
.EhciPllCfgEnable
!= 1) {
435 //Program EHCI PME_EN
440 PCI_DEVICE_NUMBER_PCH_USB
,
441 PCI_FUNCTION_NUMBER_PCH_EHCI
,
442 R_PCH_EHCI_PWR_CNTL_STS
,
443 B_PCH_EHCI_PWR_CNTL_STS_PME_EN
450 EhciPciMmBase
= MmPciAddress (0,
452 PCI_DEVICE_NUMBER_PCH_USB
,
453 PCI_FUNCTION_NUMBER_PCH_EHCI
,
456 DEBUG ((EFI_D_INFO
, "ConfigureAdditionalPm() EhciPciMmBase = 0x%x \n",EhciPciMmBase
));
457 Buffer32
= MmioRead32(EhciPciMmBase
+ R_PCH_EHCI_PWR_CNTL_STS
);
458 DEBUG ((EFI_D_INFO
, "ConfigureAdditionalPm() R_PCH_EHCI_PWR_CNTL_STS = 0x%x \n",Buffer32
));
462 #if defined SUPPORT_LVDS_DISPLAY && SUPPORT_LVDS_DISPLAY
469 TristateLpcGpioS0i3Config (
470 UINT32 Gpio_Mmio_Offset
,
472 CFIO_PNP_INIT
* Gpio_Conf_Data
480 DEBUG ((DEBUG_INFO
, "TristateLpcGpioS0i3Config\n"));
482 for(index
=0; index
< Gpio_Pin_Num
; index
++)
484 mmio_reg
= IO_BASE_ADDRESS
+ Gpio_Mmio_Offset
+ Gpio_Conf_Data
[index
].offset
;
486 MmioWrite32(mmio_reg
, Gpio_Conf_Data
[index
].val
);
488 mmio_val
= MmioRead32(mmio_reg
);
490 DEBUG ((EFI_D_INFO
, "Set MMIO=0x%08x PAD_VAL = 0x%08x,\n", mmio_reg
, mmio_val
));
497 EFI_BOOT_SCRIPT_SAVE_PROTOCOL
*mBootScriptSave
;
500 Event Notification during exit boot service to enabel ACPI mode
502 Disable SW SMI Timer, SMI from USB & Intel Specific USB 2
504 Clear all ACPI event status and disable all ACPI events
505 Disable PM sources except power button
508 Guarantee day-of-month alarm is invalid (ACPI 5.0 Section 4.8.2.4 "Real Time Clock Alarm")
510 Update EC to disable SMI and enable SCI
514 Enable PME_B0_EN in GPE0a_EN
516 @param Event - EFI Event Handle
517 @param Context - Pointer to Notify Context
534 AcpiBase
= MmioRead16 (
535 PchPciDeviceMmBase (DEFAULT_PCI_BUS_NUMBER_PCH
,
536 PCI_DEVICE_NUMBER_PCH_LPC
,
537 PCI_FUNCTION_NUMBER_PCH_LPC
) + R_PCH_LPC_ACPI_BASE
538 ) & B_PCH_LPC_ACPI_BASE_BAR
;
540 DEBUG ((EFI_D_INFO
, "EnableAcpiCallback: AcpiBase = %x\n", AcpiBase
));
543 // Disable SW SMI Timer, SMI from USB & Intel Specific USB 2
545 RegData32
= IoRead32(AcpiBase
+ R_PCH_SMI_EN
);
546 RegData32
&= ~(B_PCH_SMI_EN_SWSMI_TMR
| B_PCH_SMI_EN_LEGACY_USB2
| B_PCH_SMI_EN_INTEL_USB2
);
547 IoWrite32(AcpiBase
+ R_PCH_SMI_EN
, RegData32
);
549 RegData32
= IoRead32(AcpiBase
+ R_PCH_SMI_STS
);
550 RegData32
|= B_PCH_SMI_STS_SWSMI_TMR
;
551 IoWrite32(AcpiBase
+ R_PCH_SMI_STS
, RegData32
);
554 // Disable PM sources except power button
555 // power button is enabled only for PCAT. Disabled it on Tablet platform
558 IoWrite16(AcpiBase
+ R_PCH_ACPI_PM1_EN
, B_PCH_ACPI_PM1_EN_PWRBTN
);
559 IoWrite16(AcpiBase
+ R_PCH_ACPI_PM1_STS
, 0xffff);
562 // Guarantee day-of-month alarm is invalid (ACPI 5.0 Section 4.8.2.4 "Real Time Clock Alarm")
563 // Clear Status D reg VM bit, Date of month Alarm to make Data in CMOS RAM is no longer Valid
565 IoWrite8 (PCAT_RTC_ADDRESS_REGISTER
, RTC_ADDRESS_REGISTER_D
);
566 IoWrite8 (PCAT_RTC_DATA_REGISTER
, 0x0);
568 RegData32
= IoRead32(AcpiBase
+ R_PCH_ALT_GP_SMI_EN
);
569 RegData32
&= ~(BIT7
);
570 IoWrite32((AcpiBase
+ R_PCH_ALT_GP_SMI_EN
), RegData32
);
575 Pm1Cnt
= IoRead16(AcpiBase
+ R_PCH_ACPI_PM1_CNT
);
576 Pm1Cnt
|= B_PCH_ACPI_PM1_CNT_SCI_EN
;
577 IoWrite16(AcpiBase
+ R_PCH_ACPI_PM1_CNT
, Pm1Cnt
);
579 IoWrite8(0x80, 0xA0); //SW_SMI_ACPI_ENABLE
582 // Enable PME_B0_EN in GPE0a_EN
583 // Caution: Enable PME_B0_EN must be placed after enabling SCI.
584 // Otherwise, USB PME could not be handled as SMI event since no handler is there.
586 Gpe0aEn
= IoRead32 (AcpiBase
+ R_PCH_ACPI_GPE0a_EN
);
587 Gpe0aEn
|= B_PCH_ACPI_GPE0a_EN_PME_B0
;
588 IoWrite32(AcpiBase
+ R_PCH_ACPI_GPE0a_EN
, Gpe0aEn
);
596 This is the standard EFI driver point for the Driver. This
597 driver is responsible for setting up any platform specific policy or
598 initialization information.
600 @param ImageHandle Handle for the image of this driver.
601 @param SystemTable Pointer to the EFI System Table.
603 @retval EFI_SUCCESS Policy decisions set.
609 IN EFI_HANDLE ImageHandle
,
610 IN EFI_SYSTEM_TABLE
*SystemTable
615 EFI_HANDLE Handle
= NULL
;
617 EFI_EVENT mEfiExitBootServicesEvent
;
620 mImageHandle
= ImageHandle
;
622 Status
= gBS
->InstallProtocolInterface (
624 &gEfiSpeakerInterfaceProtocolGuid
,
625 EFI_NATIVE_INTERFACE
,
629 Status
= gBS
->LocateProtocol (
630 &gEfiPciRootBridgeIoProtocolGuid
,
632 (VOID
**) &mPciRootBridgeIo
634 ASSERT_EFI_ERROR (Status
);
636 VarSize
= sizeof(EFI_PLATFORM_INFO_HOB
);
637 Status
= gRT
->GetVariable(
639 &gEfiVlv2VariableGuid
,
646 // Initialize Product Board ID variable
648 InitMfgAndConfigModeStateVar();
649 InitPlatformBootMode();
652 // Install Observable protocol
654 InitializeObservableProtocol();
657 VarSize
= sizeof(SYSTEM_CONFIGURATION
);
658 Status
= gRT
->GetVariable(
660 &gEfiNormalSetupGuid
,
663 &mSystemConfiguration
667 Status
= EfiCreateEventReadyToBootEx (
675 // Create a ReadyToBoot Event to run the PME init process
677 Status
= EfiCreateEventReadyToBootEx (
684 // Create a ReadyToBoot Event to run enable PR0 and lock down
686 if(mSystemConfiguration
.SpiRwProtect
==1) {
687 Status
= EfiCreateEventReadyToBootEx (
689 SpiBiosProtectionFunction
,
697 EFI_COMPUTING_UNIT_CHIPSET
| EFI_CU_PLATFORM_DXE_STEP1
,
705 #if defined(SENSOR_INFO_VAR_SUPPORT) && SENSOR_INFO_VAR_SUPPORT != 0
707 // Initialize Sensor Info variable
709 InitializeSensorInfoVariable();
711 InitPchPlatformPolicy(&mPlatformInfo
);
712 InitVlvPlatformPolicy();
717 InitPlatformUsbPolicy();
718 InitSioPlatformPolicy();
719 InitializeClockRouting();
720 InitializeSlotInfo();
730 EFI_COMPUTING_UNIT_CHIPSET
| EFI_CU_PLATFORM_DXE_STEP2
,
739 // Install PCI Bus Driver Hook
747 EFI_COMPUTING_UNIT_CHIPSET
| EFI_CU_PLATFORM_DXE_STEP3
,
757 // Initialize Password States and Callbacks
761 #if defined SUPPORT_LVDS_DISPLAY && SUPPORT_LVDS_DISPLAY
765 #if defined(FIRMWARE_ID_BACKWARD_COMPATIBLE) && (FIRMWARE_ID_BACKWARD_COMPATIBLE != 0)
767 // Re-write Firmware ID if it is changed
774 EFI_COMPUTING_UNIT_CHIPSET
| EFI_CU_PLATFORM_DXE_STEP4
,
783 Status
= gBS
->CreateEventEx (
788 &gEfiEventExitBootServicesGuid
,
789 &mEfiExitBootServicesEvent
794 // Tristae Lpc pins at last moment
796 if (mSystemConfiguration
.TristateLpc
== 1)
804 Source Or Destination with Length bytes.
806 @param[in] Destination Target memory
807 @param[in] Source Source memory
808 @param[in] Length Number of bytes
815 IN VOID
*Destination
,
823 if (Source
< Destination
) {
824 Destination8
= (CHAR8
*) Destination
+ Length
- 1;
825 Source8
= (CHAR8
*) Source
+ Length
- 1;
827 *(Destination8
--) |= *(Source8
--);
830 Destination8
= (CHAR8
*) Destination
;
831 Source8
= (CHAR8
*) Source
;
833 *(Destination8
++) |= *(Source8
++);
842 // Saved SPI Opcode menu to fix EFI variable unable to write after S3 resume.
844 S3BootScriptSaveMemWrite (
845 EfiBootScriptWidthUint32
,
846 (UINTN
)(SPI_BASE_ADDRESS
+ (R_PCH_SPI_OPMENU0
)),
848 (VOID
*)(UINTN
)(SPI_BASE_ADDRESS
+ (R_PCH_SPI_OPMENU0
)));
850 S3BootScriptSaveMemWrite (
851 EfiBootScriptWidthUint32
,
852 (UINTN
)(SPI_BASE_ADDRESS
+ (R_PCH_SPI_OPMENU1
)),
854 (VOID
*)(UINTN
)(SPI_BASE_ADDRESS
+ (R_PCH_SPI_OPMENU1
)));
856 S3BootScriptSaveMemWrite (
857 EfiBootScriptWidthUint16
,
858 (UINTN
)(SPI_BASE_ADDRESS
+ R_PCH_SPI_OPTYPE
),
860 (VOID
*)(UINTN
)(SPI_BASE_ADDRESS
+ R_PCH_SPI_OPTYPE
));
862 S3BootScriptSaveMemWrite (
863 EfiBootScriptWidthUint16
,
864 (UINTN
)(SPI_BASE_ADDRESS
+ R_PCH_SPI_PREOP
),
866 (VOID
*)(UINTN
)(SPI_BASE_ADDRESS
+ R_PCH_SPI_PREOP
));
869 // Saved MTPMC_1 for S3 resume.
871 S3BootScriptSaveMemWrite (
872 EfiBootScriptWidthUint32
,
873 (UINTN
)(PMC_BASE_ADDRESS
+ R_PCH_PMC_MTPMC1
),
875 (VOID
*)(UINTN
)(PMC_BASE_ADDRESS
+ R_PCH_PMC_MTPMC1
));
881 ReadyToBootFunction (
887 EFI_ISA_ACPI_PROTOCOL
*IsaAcpi
;
888 EFI_ISA_ACPI_DEVICE_ID IsaDevice
;
891 EFI_TPM_MP_DRIVER_PROTOCOL
*TpmMpDriver
;
892 EFI_CPU_IO_PROTOCOL
*CpuIo
;
894 UINT8 ReceiveBuffer
[64];
895 UINT32 ReceiveBufferSize
;
897 UINT8 TpmForceClearCommand
[] = {0x00, 0xC1,
898 0x00, 0x00, 0x00, 0x0A,
899 0x00, 0x00, 0x00, 0x5D};
900 UINT8 TpmPhysicalPresenceCommand
[] = {0x00, 0xC1,
901 0x00, 0x00, 0x00, 0x0C,
902 0x40, 0x00, 0x00, 0x0A,
904 UINT8 TpmPhysicalDisableCommand
[] = {0x00, 0xC1,
905 0x00, 0x00, 0x00, 0x0A,
906 0x00, 0x00, 0x00, 0x70};
907 UINT8 TpmPhysicalEnableCommand
[] = {0x00, 0xC1,
908 0x00, 0x00, 0x00, 0x0A,
909 0x00, 0x00, 0x00, 0x6F};
910 UINT8 TpmPhysicalSetDeactivatedCommand
[] = {0x00, 0xC1,
911 0x00, 0x00, 0x00, 0x0B,
912 0x00, 0x00, 0x00, 0x72,
914 UINT8 TpmSetOwnerInstallCommand
[] = {0x00, 0xC1,
915 0x00, 0x00, 0x00, 0x0B,
916 0x00, 0x00, 0x00, 0x71,
919 Size
= sizeof(UINT16
);
920 Status
= gRT
->GetVariable (
921 VAR_EQ_FLOPPY_MODE_DECIMAL_NAME
,
922 &gEfiNormalSetupGuid
,
929 // Disable Floppy Controller if needed
931 Status
= gBS
->LocateProtocol (&gEfiIsaAcpiProtocolGuid
, NULL
, (VOID
**) &IsaAcpi
);
932 if (!EFI_ERROR(Status
) && (State
== 0x00)) {
933 IsaDevice
.HID
= EISA_PNP_ID(0x604);
935 Status
= IsaAcpi
->EnableDevice(IsaAcpi
, &IsaDevice
, FALSE
);
939 // save LAN info to a variable
941 if (NULL
!= mPciLanInfo
) {
945 EFI_VARIABLE_NON_VOLATILE
| EFI_VARIABLE_BOOTSERVICE_ACCESS
| EFI_VARIABLE_RUNTIME_ACCESS
,
946 mPciLanCount
* sizeof(PCI_LAN_INFO
),
951 if (NULL
!= mPciLanInfo
) {
952 gBS
->FreePool (mPciLanInfo
);
958 // Handle ACPI OS TPM requests here
960 Status
= gBS
->LocateProtocol (
961 &gEfiCpuIoProtocolGuid
,
965 Status
= gBS
->LocateProtocol (
966 &gEfiTpmMpDriverProtocolGuid
,
968 (VOID
**)&TpmMpDriver
970 if (!EFI_ERROR (Status
))
972 Data
= ReadCmosBank1Byte (CpuIo
, ACPI_TPM_REQUEST
);
975 // Clear pending ACPI TPM request indicator
977 WriteCmosBank1Byte (CpuIo
, ACPI_TPM_REQUEST
, 0x00);
980 WriteCmosBank1Byte (CpuIo
, ACPI_TPM_LAST_REQUEST
, Data
);
983 // Assert Physical Presence for these commands
985 TpmPhysicalPresenceCommand
[11] = 0x20;
986 ReceiveBufferSize
= sizeof(ReceiveBuffer
);
987 Status
= TpmMpDriver
->Transmit (
988 TpmMpDriver
, TpmPhysicalPresenceCommand
,
989 sizeof (TpmPhysicalPresenceCommand
),
990 ReceiveBuffer
, &ReceiveBufferSize
993 // PF PhysicalPresence = TRUE
995 TpmPhysicalPresenceCommand
[11] = 0x08;
996 ReceiveBufferSize
= sizeof(ReceiveBuffer
);
997 Status
= TpmMpDriver
->Transmit (
998 TpmMpDriver
, TpmPhysicalPresenceCommand
,
999 sizeof (TpmPhysicalPresenceCommand
),
1006 // TPM_PhysicalEnable
1008 ReceiveBufferSize
= sizeof(ReceiveBuffer
);
1009 Status
= TpmMpDriver
->Transmit (
1010 TpmMpDriver
, TpmPhysicalEnableCommand
,
1011 sizeof (TpmPhysicalEnableCommand
),
1012 ReceiveBuffer
, &ReceiveBufferSize
1018 // TPM_PhysicalDisable
1020 ReceiveBufferSize
= sizeof(ReceiveBuffer
);
1021 Status
= TpmMpDriver
->Transmit (
1022 TpmMpDriver
, TpmPhysicalDisableCommand
,
1023 sizeof (TpmPhysicalDisableCommand
),
1031 // TPM_PhysicalSetDeactivated=FALSE
1033 ReceiveBufferSize
= sizeof(ReceiveBuffer
);
1034 TpmPhysicalSetDeactivatedCommand
[10] = 0x00;
1035 Status
= TpmMpDriver
->Transmit (
1037 TpmPhysicalSetDeactivatedCommand
,
1038 sizeof (TpmPhysicalSetDeactivatedCommand
),
1039 ReceiveBuffer
, &ReceiveBufferSize
1041 gRT
->ResetSystem (EfiResetWarm
, EFI_SUCCESS
, 0, NULL
);
1046 // TPM_PhysicalSetDeactivated=TRUE
1048 ReceiveBufferSize
= sizeof(ReceiveBuffer
);
1049 TpmPhysicalSetDeactivatedCommand
[10] = 0x01;
1050 Status
= TpmMpDriver
->Transmit (
1052 TpmPhysicalSetDeactivatedCommand
,
1053 sizeof (TpmPhysicalSetDeactivatedCommand
),
1069 ReceiveBufferSize
= sizeof(ReceiveBuffer
);
1070 Status
= TpmMpDriver
->Transmit (
1072 TpmForceClearCommand
,
1073 sizeof (TpmForceClearCommand
),
1087 // TPM_PhysicalEnable
1089 ReceiveBufferSize
= sizeof(ReceiveBuffer
);
1090 Status
= TpmMpDriver
->Transmit (
1092 TpmPhysicalEnableCommand
,
1093 sizeof (TpmPhysicalEnableCommand
),
1098 // TPM_PhysicalSetDeactivated=FALSE
1100 ReceiveBufferSize
= sizeof(ReceiveBuffer
);
1101 TpmPhysicalSetDeactivatedCommand
[10] = 0x00;
1102 Status
= TpmMpDriver
->Transmit (
1104 TpmPhysicalSetDeactivatedCommand
,
1105 sizeof (TpmPhysicalSetDeactivatedCommand
),
1119 // TPM_PhysicalSetDeactivated=TRUE
1121 ReceiveBufferSize
= sizeof(ReceiveBuffer
);
1122 TpmPhysicalSetDeactivatedCommand
[10] = 0x01;
1123 Status
= TpmMpDriver
->Transmit (
1125 TpmPhysicalSetDeactivatedCommand
,
1126 sizeof (TpmPhysicalSetDeactivatedCommand
),
1131 // TPM_PhysicalDisable
1133 ReceiveBufferSize
= sizeof(ReceiveBuffer
);
1134 Status
= TpmMpDriver
->Transmit (
1136 TpmPhysicalDisableCommand
,
1137 sizeof (TpmPhysicalDisableCommand
),
1151 // TPM_SetOwnerInstall=TRUE
1153 ReceiveBufferSize
= sizeof(ReceiveBuffer
);
1154 TpmSetOwnerInstallCommand
[10] = 0x01;
1155 Status
= TpmMpDriver
->Transmit (
1157 TpmSetOwnerInstallCommand
,
1158 sizeof (TpmSetOwnerInstallCommand
),
1166 // TPM_SetOwnerInstall=FALSE
1168 ReceiveBufferSize
= sizeof(ReceiveBuffer
);
1169 TpmSetOwnerInstallCommand
[10] = 0x00;
1170 Status
= TpmMpDriver
->Transmit (
1172 TpmSetOwnerInstallCommand
,
1173 sizeof (TpmSetOwnerInstallCommand
),
1181 // TPM_PhysicalEnable
1183 ReceiveBufferSize
= sizeof(ReceiveBuffer
);
1184 Status
= TpmMpDriver
->Transmit (
1186 TpmPhysicalEnableCommand
,
1187 sizeof (TpmPhysicalEnableCommand
),
1192 // TPM_PhysicalSetDeactivated=FALSE
1194 ReceiveBufferSize
= sizeof(ReceiveBuffer
);
1195 TpmPhysicalSetDeactivatedCommand
[10] = 0x00;
1196 Status
= TpmMpDriver
->Transmit (
1198 TpmPhysicalSetDeactivatedCommand
,
1199 sizeof (TpmPhysicalSetDeactivatedCommand
),
1204 // Do TPM_SetOwnerInstall=TRUE on next reboot
1207 WriteCmosBank1Byte (CpuIo
, ACPI_TPM_REQUEST
, 0xF0);
1219 // TPM_SetOwnerInstall=FALSE
1221 ReceiveBufferSize
= sizeof(ReceiveBuffer
);
1222 TpmSetOwnerInstallCommand
[10] = 0x00;
1223 Status
= TpmMpDriver
->Transmit (
1225 TpmSetOwnerInstallCommand
,
1226 sizeof (TpmSetOwnerInstallCommand
),
1231 // TPM_PhysicalSetDeactivated=TRUE
1233 ReceiveBufferSize
= sizeof(ReceiveBuffer
);
1234 TpmPhysicalSetDeactivatedCommand
[10] = 0x01;
1235 Status
= TpmMpDriver
->Transmit (
1237 TpmPhysicalSetDeactivatedCommand
,
1238 sizeof (TpmPhysicalSetDeactivatedCommand
),
1243 // TPM_PhysicalDisable
1245 ReceiveBufferSize
= sizeof(ReceiveBuffer
);
1246 Status
= TpmMpDriver
->Transmit (
1248 TpmPhysicalDisableCommand
,
1249 sizeof (TpmPhysicalDisableCommand
),
1265 ReceiveBufferSize
= sizeof(ReceiveBuffer
);
1266 Status
= TpmMpDriver
->Transmit (
1268 TpmForceClearCommand
,
1269 sizeof (TpmForceClearCommand
),
1274 // TPM_PhysicalEnable
1276 ReceiveBufferSize
= sizeof(ReceiveBuffer
);
1277 Status
= TpmMpDriver
->Transmit (
1279 TpmPhysicalEnableCommand
,
1280 sizeof (TpmPhysicalEnableCommand
),
1285 // TPM_PhysicalSetDeactivated=FALSE
1287 ReceiveBufferSize
= sizeof(ReceiveBuffer
);
1288 TpmPhysicalSetDeactivatedCommand
[10] = 0x00;
1289 Status
= TpmMpDriver
->Transmit (
1291 TpmPhysicalSetDeactivatedCommand
,
1292 sizeof (TpmPhysicalSetDeactivatedCommand
),
1306 // Second part of ACPI TPM request 0x0A: OEM custom TPM_SetOwnerInstall=TRUE
1308 ReceiveBufferSize
= sizeof(ReceiveBuffer
);
1309 TpmSetOwnerInstallCommand
[10] = 0x01;
1310 Status
= TpmMpDriver
->Transmit (
1312 TpmSetOwnerInstallCommand
,
1313 sizeof (TpmSetOwnerInstallCommand
),
1317 WriteCmosBank1Byte (CpuIo
, ACPI_TPM_LAST_REQUEST
, 0x0A);
1320 // Deassert Physical Presence
1322 TpmPhysicalPresenceCommand
[11] = 0x10;
1323 ReceiveBufferSize
= sizeof(ReceiveBuffer
);
1324 Status
= TpmMpDriver
->Transmit (
1326 TpmPhysicalPresenceCommand
,
1327 sizeof (TpmPhysicalPresenceCommand
),
1339 Initializes manufacturing and config mode setting.
1343 InitMfgAndConfigModeStateVar()
1345 EFI_PLATFORM_SETUP_ID
*BootModeBuffer
;
1350 // Variable initialization
1354 HobList
= GetFirstGuidHob(&gEfiPlatformBootModeGuid
);
1355 if (HobList
!= NULL
) {
1356 BootModeBuffer
= GET_GUID_HOB_DATA (HobList
);
1359 // Check if in Manufacturing mode
1362 &BootModeBuffer
->SetupName
,
1363 MANUFACTURE_SETUP_NAME
,
1364 StrSize (MANUFACTURE_SETUP_NAME
)
1370 // Check if in safe mode
1373 &BootModeBuffer
->SetupName
,
1375 StrSize (SAFE_SETUP_NAME
)
1385 Initializes manufacturing and config mode setting.
1389 InitPlatformBootMode()
1391 EFI_PLATFORM_SETUP_ID
*BootModeBuffer
;
1394 HobList
= GetFirstGuidHob(&gEfiPlatformBootModeGuid
);
1395 if (HobList
!= NULL
) {
1396 BootModeBuffer
= GET_GUID_HOB_DATA (HobList
);
1397 mPlatformBootMode
= BootModeBuffer
->PlatformBootMode
;
1411 UINT16 ItkModBiosState
;
1417 // Setup local variable according to ITK variable
1420 // Read ItkBiosModVar to determine if BIOS has been modified by ITK
1421 // If ItkBiosModVar = 0 or if variable hasn't been initialized then BIOS has not been modified by ITK modified
1422 // Set local variable VAR_EQ_ITK_BIOS_MOD_DECIMAL_NAME=0 if BIOS has not been modified by ITK
1424 DataSize
= sizeof (Value
);
1425 Status
= gRT
->GetVariable (
1426 ITK_BIOS_MOD_VAR_NAME
,
1432 if (Status
== EFI_NOT_FOUND
) {
1434 // Variable not found, hasn't been initialized, intialize to 0
1438 // Write variable to flash.
1441 ITK_BIOS_MOD_VAR_NAME
,
1443 EFI_VARIABLE_RUNTIME_ACCESS
|
1444 EFI_VARIABLE_NON_VOLATILE
|
1445 EFI_VARIABLE_BOOTSERVICE_ACCESS
,
1451 if ( (!EFI_ERROR (Status
)) || (Status
== EFI_NOT_FOUND
) ) {
1452 if (Value
== 0x00) {
1453 ItkModBiosState
= 0x00;
1455 ItkModBiosState
= 0x01;
1458 VAR_EQ_ITK_BIOS_MOD_DECIMAL_NAME
,
1459 &gEfiNormalSetupGuid
,
1460 EFI_VARIABLE_BOOTSERVICE_ACCESS
,
1462 (void *)&ItkModBiosState
1467 #if defined(FIRMWARE_ID_BACKWARD_COMPATIBLE) && (FIRMWARE_ID_BACKWARD_COMPATIBLE != 0)
1471 Initializes the BIOS FIRMWARE ID from the FIRMWARE_ID build variable.
1480 CHAR16 FirmwareIdNameWithPassword
[] = FIRMWARE_ID_NAME_WITH_PASSWORD
;
1483 // First try writing the variable without a password in case we are
1484 // upgrading from a BIOS without password protection on the FirmwareId
1486 Status
= gRT
->SetVariable(
1487 (CHAR16
*)&gFirmwareIdName
,
1489 EFI_VARIABLE_NON_VOLATILE
| EFI_VARIABLE_BOOTSERVICE_ACCESS
|
1490 EFI_VARIABLE_RUNTIME_ACCESS
,
1491 sizeof( FIRMWARE_ID
) - 1,
1495 if (Status
== EFI_INVALID_PARAMETER
) {
1498 // Since setting the firmware id without the password failed,
1499 // a password must be required.
1501 Status
= gRT
->SetVariable(
1502 (CHAR16
*)&FirmwareIdNameWithPassword
,
1504 EFI_VARIABLE_NON_VOLATILE
| EFI_VARIABLE_BOOTSERVICE_ACCESS
|
1505 EFI_VARIABLE_RUNTIME_ACCESS
,
1506 sizeof( FIRMWARE_ID
) - 1,
1518 // Workaround to support IIA bug.
1519 // IIA request to change option value to 4, 5 and 7 relatively
1520 // instead of 1, 2, and 3 which follow Lakeport Specs.
1521 // Check option value, temporary hardcode GraphicsDriverMemorySize
1522 // Option value to fulfill IIA requirment. So that user no need to
1523 // load default and update setupvariable after update BIOS.
1524 // Option value hardcoded as: 1 to 4, 2 to 5, 3 to 7.
1525 // *This is for broadwater and above product only.
1528 SYSTEM_CONFIGURATION SystemConfiguration
;
1532 VarSize
= sizeof(SYSTEM_CONFIGURATION
);
1533 Status
= gRT
->GetVariable(
1535 &gEfiNormalSetupGuid
,
1538 &SystemConfiguration
1541 if((SystemConfiguration
.GraphicsDriverMemorySize
< 4) && !EFI_ERROR(Status
) ) {
1542 switch (SystemConfiguration
.GraphicsDriverMemorySize
){
1544 SystemConfiguration
.GraphicsDriverMemorySize
= 4;
1547 SystemConfiguration
.GraphicsDriverMemorySize
= 5;
1550 SystemConfiguration
.GraphicsDriverMemorySize
= 7;
1556 Status
= gRT
->SetVariable (
1558 &gEfiNormalSetupGuid
,
1559 EFI_VARIABLE_NON_VOLATILE
| EFI_VARIABLE_BOOTSERVICE_ACCESS
,
1560 sizeof(SYSTEM_CONFIGURATION
),
1561 &SystemConfiguration
1567 InitPlatformUsbPolicy (
1577 mUsbPolicyData
.Version
= (UINT8
)USB_POLICY_PROTOCOL_REVISION_2
;
1578 mUsbPolicyData
.UsbMassStorageEmulationType
= mSystemConfiguration
.UsbBIOSINT13DeviceEmulation
;
1579 if(mUsbPolicyData
.UsbMassStorageEmulationType
== 3) {
1580 mUsbPolicyData
.UsbEmulationSize
= mSystemConfiguration
.UsbBIOSINT13DeviceEmulationSize
;
1582 mUsbPolicyData
.UsbEmulationSize
= 0;
1584 mUsbPolicyData
.UsbZipEmulationType
= mSystemConfiguration
.UsbZipEmulation
;
1585 mUsbPolicyData
.UsbOperationMode
= HIGH_SPEED
;
1588 // Some chipset need Period smi, 0 = LEGACY_PERIOD_UN_SUPP
1590 mUsbPolicyData
.USBPeriodSupport
= LEGACY_PERIOD_UN_SUPP
;
1593 // Some platform need legacyfree, 0 = LEGACY_FREE_UN_SUPP
1595 mUsbPolicyData
.LegacyFreeSupport
= LEGACY_FREE_UN_SUPP
;
1598 // Set Code base , TIANO_CODE_BASE =0x01, ICBD =0x00
1600 mUsbPolicyData
.CodeBase
= (UINT8
)ICBD_CODE_BASE
;
1603 // Some chispet 's LpcAcpibase are diffrent,set by platform or chipset,
1604 // default is Ich acpibase =0x040. acpitimerreg=0x08.
1605 mUsbPolicyData
.LpcAcpiBase
= 0x40;
1606 mUsbPolicyData
.AcpiTimerReg
= 0x08;
1609 // Set for reduce usb post time
1611 mUsbPolicyData
.UsbTimeTue
= 0x00;
1612 mUsbPolicyData
.InternelHubExist
= 0x00; //TigerPoint doesn't have RMH
1613 mUsbPolicyData
.EnumWaitPortStableStall
= 100;
1616 Status
= gBS
->InstallProtocolInterface (
1619 EFI_NATIVE_INTERFACE
,
1622 ASSERT_EFI_ERROR(Status
);
1628 IN EFI_CPU_IO_PROTOCOL
*CpuIo
,
1634 CpuIo
->Io
.Write (CpuIo
, EfiCpuIoWidthUint8
, 0x72, 1, &Index
);
1635 CpuIo
->Io
.Read (CpuIo
, EfiCpuIoWidthUint8
, 0x73, 1, &Data
);
1640 WriteCmosBank1Byte (
1641 IN EFI_CPU_IO_PROTOCOL
*CpuIo
,