Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/PchRegsSmbus.h

   1 /**
   2
   3 Copyright (c) 2011  - 2014, Intel Corporation. All rights reserved
   4
   5   This program and the accompanying materials are licensed and made available under
   6   the terms and conditions of the BSD License that accompanies this distribution.
   7   The full text of the license may be found at
   8   http://opensource.org/licenses/bsd-license.php.
   9
  10   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12
  13
  14
  15   @file
  16   PchRegsSmbus.h
  17
  18   @brief
  19   Register names for VLV Smbus Device.
  20
  21   Conventions:
  22
  23   - Prefixes:
  24     Definitions beginning with "R_" are registers
  25     Definitions beginning with "B_" are bits within registers
  26     Definitions beginning with "V_" are meaningful values of bits within the registers
  27     Definitions beginning with "S_" are register sizes
  28     Definitions beginning with "N_" are the bit position
  29   - In general, PCH registers are denoted by "_PCH_" in register names
  30   - Registers / bits that are different between PCH generations are denoted by
  31     "_PCH_<generation_name>_" in register/bit names. e.g., "_PCH_VLV_"
  32   - Registers / bits that are different between SKUs are denoted by "_<SKU_name>"
  33     at the end of the register/bit names
  34   - Registers / bits of new devices introduced in a PCH generation will be just named
  35     as "_PCH_" without <generation_name> inserted.
  36
  37 **/
  38 #ifndef _PCH_REGS_SMBUS_H_
  39 #define _PCH_REGS_SMBUS_H_
  40
  41 ///
  42 /// SMBus Controller Registers (D31:F3)
  43 ///
  44 #define PCI_DEVICE_NUMBER_PCH_SMBUS        31
  45 #define PCI_FUNCTION_NUMBER_PCH_SMBUS      3
  46
  47 #define R_PCH_SMBUS_VENDOR_ID              0x00  // Vendor ID
  48 #define V_PCH_SMBUS_VENDOR_ID              V_PCH_INTEL_VENDOR_ID // Intel Vendor ID
  49
  50 #define R_PCH_SMBUS_DEVICE_ID              0x02  // Device ID
  51 #define V_PCH_SMBUS_DEVICE_ID              0x0F12
  52
  53 #define R_PCH_SMBUS_PCICMD                 0x04  // CMD register enables/disables, Memory/IO space access and interrupt
  54 #define B_PCH_SMBUS_PCICMD_INTR_DIS        BIT10 // Interrupt Disable
  55 #define B_PCH_SMBUS_PCICMD_FBE             BIT9  // FBE - reserved as '0'
  56 #define B_PCH_SMBUS_PCICMD_SERR_EN         BIT8  // SERR Enable - reserved as '0'
  57 #define B_PCH_SMBUS_PCICMD_WCC             BIT7  // Wait Cycle Control - reserved as '0'
  58 #define B_PCH_SMBUS_PCICMD_PER             BIT6  // Parity Error - reserved as '0'
  59 #define B_PCH_SMBUS_PCICMD_VPS             BIT5  // VGA Palette Snoop - reserved as '0'
  60 #define B_PCH_SMBUS_PCICMD_PMWE            BIT4  // Postable Memory Write Enable - reserved as '0'
  61 #define B_PCH_SMBUS_PCICMD_SCE             BIT3  // Special Cycle Enable - reserved as '0'
  62 #define B_PCH_SMBUS_PCICMD_BME             BIT2  // Bus Master Enable - reserved as '0'
  63 #define B_PCH_SMBUS_PCICMD_MSE             BIT1  // Memory Space Enable
  64 #define B_PCH_SMBUS_PCICMD_IOSE            BIT0  // I/O Space Enable
  65
  66 #define R_PCH_SMBUS_BASE                   0x20  // The I/O memory bar
  67 #define B_PCH_SMBUS_BASE_BAR               0x0000FFE0 // Base Address
  68 #define B_PCH_SMBUS_BASE_IOSI              BIT0  // IO Space Indicator
  69
  70 #define R_PCH_SMBUS_SVID                   0x2C  // Subsystem Vendor ID
  71 #define B_PCH_SMBUS_SVID                   0xFFFF // Subsystem Vendor ID
  72
  73 //
  74 // SMBus I/O Registers
  75 //
  76 #define R_PCH_SMBUS_HSTS                   0x00  // Host Status Register R/W
  77 #define B_PCH_SMBUS_HSTS_ALL               0xFF
  78 #define B_PCH_SMBUS_BYTE_DONE_STS          BIT7  // Byte Done Status
  79 #define B_PCH_SMBUS_IUS                    BIT6  // In Use Status
  80 #define B_PCH_SMBUS_SMBALERT_STS           BIT5  // SMBUS Alert
  81 #define B_PCH_SMBUS_FAIL                   BIT4  // Failed
  82 #define B_PCH_SMBUS_BERR                   BIT3  // Bus Error
  83 #define B_PCH_SMBUS_DERR                   BIT2  // Device Error
  84 #define B_PCH_SMBUS_ERRORS                 (B_PCH_SMBUS_FAIL | B_PCH_SMBUS_BERR | B_PCH_SMBUS_DERR)
  85 #define B_PCH_SMBUS_INTR                   BIT1  // Interrupt
  86 #define B_PCH_SMBUS_HBSY                   BIT0  // Host Busy
  87
  88 #define R_PCH_SMBUS_HCTL                   0x02  // Host Control Register R/W
  89 #define B_PCH_SMBUS_PEC_EN                 BIT7  // Packet Error Checking Enable
  90 #define B_PCH_SMBUS_START                  BIT6  // Start
  91 #define B_PCH_SMBUS_LAST_BYTE              BIT5  // Last Byte
  92 #define B_PCH_SMBUS_SMB_CMD                0x1C  // SMB Command
  93 #define V_PCH_SMBUS_SMB_CMD_BLOCK_PROCESS  0x1C  // Block Process
  94 #define V_PCH_SMBUS_SMB_CMD_IIC_READ       0x18  // I2C Read
  95 #define V_PCH_SMBUS_SMB_CMD_BLOCK          0x14  // Block
  96 #define V_PCH_SMBUS_SMB_CMD_PROCESS_CALL   0x10  // Process Call
  97 #define V_PCH_SMBUS_SMB_CMD_WORD_DATA      0x0C  // Word Data
  98 #define V_PCH_SMBUS_SMB_CMD_BYTE_DATA      0x08  // Byte Data
  99 #define V_PCH_SMBUS_SMB_CMD_BYTE           0x04  // Byte
 100 #define V_PCH_SMBUS_SMB_CMD_QUICK          0x00  // Quick
 101 #define B_PCH_SMBUS_KILL                   BIT1  // Kill
 102 #define B_PCH_SMBUS_INTREN                 BIT0  // Interrupt Enable
 103
 104 #define R_PCH_SMBUS_HCMD                   0x03  // Host Command Register R/W
 105 #define B_PCH_SMBUS_HCMD                   0xFF  // Command to be transmitted
 106
 107 #define R_PCH_SMBUS_TSA                    0x04  // Transmit Slave Address Register R/W
 108 #define B_PCH_SMBUS_ADDRESS                0xFE  // 7-bit address of the targeted slave
 109 #define B_PCH_SMBUS_RW_SEL                 BIT0  // Direction of the host transfer, 1 = read, 0 = write
 110 #define B_PCH_SMBUS_RW_SEL_READ            0x01  // Read
 111 #define B_PCH_SMBUS_RW_SEL_WRITE           0x00  // Write
 112 //
 113 #define R_PCH_SMBUS_HD0                    0x05  // Data 0 Register R/W
 114 #define R_PCH_SMBUS_HD1                    0x06  // Data 1 Register R/W
 115 #define R_PCH_SMBUS_HBD                    0x07  // Host Block Data Register R/W
 116 #define R_PCH_SMBUS_PEC                    0x08  // Packet Error Check Data Register R/W
 117
 118 #define R_PCH_SMBUS_RSA                    0x09  // Receive Slave Address Register R/W
 119 #define B_PCH_SMBUS_SLAVE_ADDR             0x7F  // TCO slave address (Not used, reserved)
 120
 121 #define R_PCH_SMBUS_SD                     0x0A  // Receive Slave Data Register R/W
 122
 123 #define R_PCH_SMBUS_AUXS                   0x0C  // Auxiliary Status Register R/WC
 124 #define B_PCH_SMBUS_CRCE                   BIT0  // CRC Error
 125 //
 126 #define R_PCH_SMBUS_AUXC                   0x0D  // Auxiliary Control Register R/W
 127 #define B_PCH_SMBUS_E32B                   BIT1  // Enable 32-byte Buffer
 128 #define B_PCH_SMBUS_AAC                    BIT0  // Automatically Append CRC
 129
 130 #define R_PCH_SMBUS_SMLC                   0x0E  // SMLINK Pin Control Register R/W
 131 #define B_PCH_SMBUS_SMLINK_CLK_CTL         BIT2  // Not supported
 132 #define B_PCH_SMBUS_SMLINK1_CUR_STS        BIT1  // Not supported
 133 #define B_PCH_SMBUS_SMLINK0_CUR_STS        BIT0  // Not supported
 134
 135
 136 #define R_PCH_SMBUS_SMBC                   0x0F  // SMBus Pin Control Register R/W
 137 #define B_PCH_SMBUS_SMBCLK_CTL             BIT2  // SMBCLK Control
 138 #define B_PCH_SMBUS_SMBDATA_CUR_STS        BIT1  // SMBDATA Current Status
 139 #define B_PCH_SMBUS_SMBCLK_CUR_STS         BIT0  // SMBCLK Current Status
 140
 141 #define R_PCH_SMBUS_SSTS                   0x10  // Slave Status Register R/WC
 142 #define B_PCH_SMBUS_HOST_NOTIFY_STS        BIT0  // Host Notify Status
 143
 144 #define R_PCH_SMBUS_SCMD                   0x11  // Slave Command Register R/W
 145 #define B_PCH_SMBUS_SMBALERT_DIS           BIT2  // Not supported
 146 #define B_PCH_SMBUS_HOST_NOTIFY_WKEN       BIT1  // Host Notify Wake Enable
 147 #define B_PCH_SMBUS_HOST_NOTIFY_INTREN     BIT0  // Host Notify Interrupt Enable
 148
 149 #define R_PCH_SMBUS_NDA                    0x14  // Notify Device Address Register RO
 150 #define B_PCH_SMBUS_DEVICE_ADDRESS         0xFE  // Device Address
 151
 152 #define R_PCH_SMBUS_NDLB                   0x16  // Notify Data Low Byte Register RO
 153 #define R_PCH_SMBUS_NDHB                   0x17  // Notify Data High Byte Register RO
 154
 155 #endif