Upload BSD-licensed Vlv2TbltDevicePkg and Vlv2DeviceRefCodePkg to

https://svn.code.sf.net/p/edk2/code/trunk/edk2/,

which are for MinnowBoard MAX open source project.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: David Wei <david.wei@intel.com>
Reviewed-by: Mike Wu <mike.wu@intel.com>
Reviewed-by: Hot Tian <hot.tian@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16599 6f19259b-4bc3-4df7-8a09-765794883524

diff --git a/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/98_LINK.ASL b/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/98_LINK.ASL
new file mode 100644 (file)
index 0000000..ac13f36
--- /dev/null
+++ b/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/98_LINK.ASL
@@ -0,0 +1,623 @@
+/**************************************************************************;\r
+;*                                                                        *;\r
+;*                                                                        *;\r
+;*    Intel Corporation - ACPI Reference Code for the Baytrail            *;\r
+;*    Family of Customer Reference Boards.                                *;\r
+;*                                                                        *;\r
+;*                                                                        *;\r
+;*    Copyright (c)  2012  - 2014, Intel Corporation. All rights reserved   *;\r
+;\r
+; This program and the accompanying materials are licensed and made available under\r
+; the terms and conditions of the BSD License that accompanies this distribution.\r
+; The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php.\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+;*                                                                        *;\r
+;*                                                                        *;\r
+;**************************************************************************/\r
+\r
+\r
+\r
+// Use this information when determining the Possible IRQs that can be\r
+// used in a given system.\r
+//\r
+// The following IRQs are always in use by legacy devices:\r
+//              0  = System Timer\r
+//              2  = 8259 PIC\r
+//              8  = RTC\r
+//              9  = SCI Interrupt (It may be used, we choose not to)\r
+//              13 = Co-processor Error\r
+//\r
+// The following may be in use by legacy devices:\r
+//              1  = If using PS/2 Keyboard\r
+//              3  = If COMx Port Enabled and IRQ = 3\r
+//              4  = If COMx Port Enabled and IRQ = 4\r
+//              5  = If LPT Port Enabled and IRQ = 5\r
+//              6  = If FDC Enabled\r
+//              7  = If LPT Port Enabled and IRQ = 7\r
+//              12 = If using PS/2 Mouse\r
+//              14 = Primary IDE (If populated and in Compatibility Mode)\r
+//              15 = Secondary IDE (If populated and in Compatibility Mode)\r
+//\r
+// The following will never be in use by legacy devices:\r
+//              10 = Assign to PARC, PCRC, PERC, PGRC\r
+//              11 = Assign to PBRC, PDRC, PFRC, PHRC\r
+\r
+Device(LNKA)                            // PARC Routing Resource\r
+{\r
+  Name(_HID,EISAID("PNP0C0F"))    // PCI Interrupt Link Device\r
+\r
+  Name(_UID,1)                    // Unique to other Link Devices\r
+\r
+  // Disable the PCI IRQ.\r
+\r
+  Method(_DIS,0,Serialized)\r
+  {\r
+    Or(PARC,0x80,PARC)\r
+  }\r
+\r
+  // Possible IRQ Resource Setting.\r
+\r
+  Method (_PRS, 0, Serialized)\r
+  {\r
+    return (PRSA)\r
+  }\r
+\r
+  // Current IRQ Resource Setting.\r
+\r
+  Method(_CRS,0,Serialized)\r
+  {\r
+    Name(RTLA,ResourceTemplate()\r
+    {\r
+      IRQ(Level,ActiveLow,Shared) {}\r
+    })\r
+\r
+    // Point to specific byte.\r
+\r
+    CreateWordField(RTLA,1,IRQ0)\r
+\r
+    // Zero out IRQ mask bits 0-15\r
+\r
+    Store(Zero,IRQ0)\r
+\r
+    ShiftLeft(1,And(PARC,0x0F),IRQ0)\r
+\r
+    Return(RTLA)\r
+  }\r
+\r
+  // Set IRQ Resource Setting.\r
+\r
+  Method(_SRS,1,Serialized)\r
+  {\r
+    // Point to the specific byte passed in\r
+\r
+    CreateWordField(Arg0,1,IRQ0)\r
+\r
+    // Determine the IRQ bit to set and store it\r
+\r
+    FindSetRightBit(IRQ0,Local0)\r
+    Decrement(Local0)\r
+    Store(Local0,PARC)\r
+  }\r
+\r
+  // PCI IRQ Status.\r
+\r
+  Method(_STA,0,Serialized)\r
+  {\r
+    If(And(PARC,0x80))\r
+    {\r
+      Return(0x0009)\r
+    }\r
+    Else\r
+    {\r
+      Return(0x000B)\r
+    }\r
+  }\r
+}\r
+\r
+Device(LNKB)                            // PBRC Routing Resource\r
+{\r
+  Name(_HID,EISAID("PNP0C0F"))\r
+\r
+  Name(_UID,2)\r
+\r
+  // Disable the PCI IRQ.\r
+\r
+  Method(_DIS,0,Serialized)\r
+  {\r
+    Or(PBRC,0x80,PBRC)\r
+  }\r
+\r
+  // Possible IRQ Resource Setting.\r
+\r
+  Method (_PRS, 0, Serialized)\r
+  {\r
+    return (PRSB)\r
+  }\r
+\r
+  // Current IRQ Resource Setting.\r
+\r
+  Method(_CRS,0,Serialized)\r
+  {\r
+    Name(RTLB,ResourceTemplate()\r
+    {\r
+      IRQ(Level,ActiveLow,Shared) {}\r
+    })\r
+\r
+    // Point to specific byte.\r
+\r
+    CreateWordField(RTLB,1,IRQ0)\r
+\r
+    // Zero out IRQ mask bits 0-15\r
+\r
+    Store(Zero,IRQ0)\r
+\r
+    ShiftLeft(1,And(PBRC,0x0F),IRQ0)\r
+\r
+    Return(RTLB)\r
+  }\r
+\r
+  // Set IRQ Resource Setting.\r
+\r
+  Method(_SRS,1,Serialized)\r
+  {\r
+    // Point to the specific byte passed in.\r
+\r
+    CreateWordField(Arg0,1,IRQ0)\r
+\r
+    // Determine the IRQ bit to set and store it,\r
+\r
+    FindSetRightBit(IRQ0,Local0)\r
+    Decrement(Local0)\r
+    Store(Local0,PBRC)\r
+  }\r
+\r
+  // PCI IRQ Status.\r
+\r
+  Method(_STA,0,Serialized)\r
+  {\r
+    If(And(PBRC,0x80))\r
+    {\r
+      Return(0x0009)\r
+    }\r
+    Else\r
+    {\r
+      Return(0x000B)\r
+    }\r
+  }\r
+}\r
+\r
+Device(LNKC)                            // PCRC Routing Resource\r
+{\r
+  Name(_HID,EISAID("PNP0C0F"))\r
+\r
+  Name(_UID,3)\r
+\r
+  // Disable the PCI IRQ.\r
+\r
+  Method(_DIS,0,Serialized)\r
+  {\r
+    Or(PCRC,0x80,PCRC)\r
+  }\r
+\r
+  // Possible IRQ Resource Setting.\r
+\r
+  Method (_PRS, 0, Serialized)\r
+  {\r
+    return (PRSC)\r
+  }\r
+\r
+  // Current IRQ Resource Setting.\r
+\r
+  Method(_CRS,0,Serialized)\r
+  {\r
+    Name(RTLC,ResourceTemplate()\r
+    {\r
+      IRQ(Level,ActiveLow,Shared) {}\r
+    })\r
+\r
+    // Point to specific byte.\r
+\r
+    CreateWordField(RTLC,1,IRQ0)\r
+\r
+    // Zero out IRQ mask bits 0-15\r
+\r
+    Store(Zero,IRQ0)\r
+\r
+    ShiftLeft(1,And(PCRC,0x0F),IRQ0)\r
+\r
+    Return(RTLC)\r
+  }\r
+\r
+  // Set IRQ Resource Setting.\r
+\r
+  Method(_SRS,1,Serialized)\r
+  {\r
+    // Point to the specific byte passed in.\r
+\r
+    CreateWordField(Arg0,1,IRQ0)\r
+\r
+    // Determine the IRQ bit to set and store it,\r
+\r
+    FindSetRightBit(IRQ0,Local0)\r
+    Decrement(Local0)\r
+    Store(Local0,PCRC)\r
+  }\r
+\r
+  // PCI IRQ Status.\r
+\r
+  Method(_STA,0,Serialized)\r
+  {\r
+    If(And(PCRC,0x80))\r
+    {\r
+      Return(0x0009)\r
+    }\r
+    Else\r
+    {\r
+      Return(0x000B)\r
+    }\r
+  }\r
+}\r
+\r
+Device(LNKD)                            // PDRC Routing Resource\r
+{\r
+  Name(_HID,EISAID("PNP0C0F"))\r
+\r
+  Name(_UID,4)\r
+\r
+  // Disable the PCI IRQ.\r
+\r
+  Method(_DIS,0,Serialized)\r
+  {\r
+    Or(PDRC,0x80,PDRC)\r
+  }\r
+\r
+  // Possible IRQ Resource Setting.\r
+\r
+  Method (_PRS, 0, Serialized)\r
+  {\r
+    return (PRSD)\r
+  }\r
+\r
+  // Current IRQ Resource Setting.\r
+\r
+  Method(_CRS,0,Serialized)\r
+  {\r
+    Name(RTLD,ResourceTemplate()\r
+    {\r
+      IRQ(Level,ActiveLow,Shared) {}\r
+    })\r
+\r
+    // Point to specific byte.\r
+\r
+    CreateWordField(RTLD,1,IRQ0)\r
+\r
+    // Zero out IRQ mask bits 0-15\r
+\r
+    Store(Zero,IRQ0)\r
+\r
+    ShiftLeft(1,And(PDRC,0x0F),IRQ0)\r
+\r
+    Return(RTLD)\r
+  }\r
+\r
+  // Set IRQ Resource Setting.\r
+\r
+  Method(_SRS,1,Serialized)\r
+  {\r
+    // Point to the specific byte passed in.\r
+\r
+    CreateWordField(Arg0,1,IRQ0)\r
+\r
+    // Determine the IRQ bit to set and store it,\r
+\r
+    FindSetRightBit(IRQ0,Local0)\r
+    Decrement(Local0)\r
+    Store(Local0,PDRC)\r
+  }\r
+\r
+  // PCI IRQ Status.\r
+\r
+  Method(_STA,0,Serialized)\r
+  {\r
+    If(And(PDRC,0x80))\r
+    {\r
+      Return(0x0009)\r
+    }\r
+    Else\r
+    {\r
+      Return(0x000B)\r
+    }\r
+  }\r
+}\r
+\r
+Device(LNKE)                            // PERC Routing Resource\r
+{\r
+  Name(_HID,EISAID("PNP0C0F"))\r
+\r
+  Name(_UID,5)\r
+\r
+  // Disable the PCI IRQ.\r
+\r
+  Method(_DIS,0,Serialized)\r
+  {\r
+    Or(PERC,0x80,PERC)\r
+  }\r
+\r
+  // Possible IRQ Resource Setting.\r
+\r
+  Method (_PRS, 0, Serialized)\r
+  {\r
+    return (PRSE)\r
+  }\r
+\r
+  // Current IRQ Resource Setting.\r
+\r
+  Method(_CRS,0,Serialized)\r
+  {\r
+    Name(RTLE,ResourceTemplate()\r
+    {\r
+      IRQ(Level,ActiveLow,Shared) {}\r
+    })\r
+\r
+    // Point to specific byte.\r
+\r
+    CreateWordField(RTLE,1,IRQ0)\r
+\r
+    // Zero out IRQ mask bits 0-15\r
+\r
+    Store(Zero,IRQ0)\r
+\r
+    ShiftLeft(1,And(PERC,0x0F),IRQ0)\r
+\r
+    Return(RTLE)\r
+  }\r
+\r
+  // Set IRQ Resource Setting.\r
+\r
+  Method(_SRS,1,Serialized)\r
+  {\r
+    // Point to the specific byte passed in\r
+\r
+    CreateWordField(Arg0,1,IRQ0)\r
+\r
+    // Determine the IRQ bit to set and store it\r
+\r
+    FindSetRightBit(IRQ0,Local0)\r
+    Decrement(Local0)\r
+    Store(Local0,PERC)\r
+  }\r
+\r
+  // PCI IRQ Status.\r
+\r
+  Method(_STA,0,Serialized)\r
+  {\r
+    If(And(PERC,0x80))\r
+    {\r
+      Return(0x0009)\r
+    }\r
+    Else\r
+    {\r
+      Return(0x000B)\r
+    }\r
+  }\r
+}\r
+\r
+Device(LNKF)                            // PFRC Routing Resource\r
+{\r
+  Name(_HID,EISAID("PNP0C0F"))\r
+\r
+  Name(_UID,6)\r
+\r
+  // Disable the PCI IRQ.\r
+\r
+  Method(_DIS,0,Serialized)\r
+  {\r
+    Or(PFRC,0x80,PFRC)\r
+  }\r
+\r
+  // Possible IRQ Resource Setting.\r
+\r
+  Method (_PRS, 0, Serialized)\r
+  {\r
+    return (PRSF)\r
+  }\r
+\r
+  // Current IRQ Resource Setting.\r
+\r
+  Method(_CRS,0,Serialized)\r
+  {\r
+    Name(RTLF,ResourceTemplate()\r
+    {\r
+      IRQ(Level,ActiveLow,Shared) {}\r
+    })\r
+\r
+    // Point to specific byte.\r
+\r
+    CreateWordField(RTLF,1,IRQ0)\r
+\r
+    // Zero out IRQ mask bits 0-15\r
+\r
+    Store(Zero,IRQ0)\r
+\r
+    ShiftLeft(1,And(PFRC,0x0F),IRQ0)\r
+\r
+    Return(RTLF)\r
+  }\r
+\r
+  // Set IRQ Resource Setting.\r
+\r
+  Method(_SRS,1,Serialized)\r
+  {\r
+    // Point to the specific byte passed in.\r
+\r
+    CreateWordField(Arg0,1,IRQ0)\r
+\r
+    // Determine the IRQ bit to set and store it,\r
+\r
+    FindSetRightBit(IRQ0,Local0)\r
+    Decrement(Local0)\r
+    Store(Local0,PFRC)\r
+  }\r
+\r
+  // PCI IRQ Status.\r
+\r
+  Method(_STA,0,Serialized)\r
+  {\r
+    If(And(PFRC,0x80))\r
+    {\r
+      Return(0x0009)\r
+    }\r
+    Else\r
+    {\r
+      Return(0x000B)\r
+    }\r
+  }\r
+}\r
+\r
+Device(LNKG)                            // PGRC Routing Resource\r
+{\r
+  Name(_HID,EISAID("PNP0C0F"))\r
+\r
+  Name(_UID,7)\r
+\r
+  // Disable the PCI IRQ.\r
+\r
+  Method(_DIS,0,Serialized)\r
+  {\r
+    Or(PGRC,0x80,PGRC)\r
+  }\r
+\r
+  // Possible IRQ Resource Setting.\r
+\r
+  Method (_PRS, 0, Serialized)\r
+  {\r
+    return (PRSG)\r
+  }\r
+\r
+  // Current IRQ Resource Setting.\r
+\r
+  Method(_CRS,0,Serialized)\r
+  {\r
+    Name(RTLG,ResourceTemplate()\r
+    {\r
+      IRQ(Level,ActiveLow,Shared) {}\r
+    })\r
+\r
+    // Point to specific byte.\r
+\r
+    CreateWordField(RTLG,1,IRQ0)\r
+\r
+    // Zero out IRQ mask bits 0-15\r
+\r
+    Store(Zero,IRQ0)\r
+\r
+    ShiftLeft(1,And(PGRC,0x0F),IRQ0)\r
+\r
+    Return(RTLG)\r
+  }\r
+\r
+  // Set IRQ Resource Setting.\r
+\r
+  Method(_SRS,1,Serialized)\r
+  {\r
+    // Point to the specific byte passed in.\r
+\r
+    CreateWordField(Arg0,1,IRQ0)\r
+\r
+    // Determine the IRQ bit to set and store it,\r
+\r
+    FindSetRightBit(IRQ0,Local0)\r
+    Decrement(Local0)\r
+    Store(Local0,PGRC)\r
+  }\r
+\r
+  // PCI IRQ Status.\r
+\r
+  Method(_STA,0,Serialized)\r
+  {\r
+    If(And(PGRC,0x80))\r
+    {\r
+      Return(0x0009)\r
+    }\r
+    Else\r
+    {\r
+      Return(0x000B)\r
+    }\r
+  }\r
+}\r
+\r
+Device(LNKH)                            // PHRC Routing Resource\r
+{\r
+  Name(_HID,EISAID("PNP0C0F"))\r
+\r
+  Name(_UID,8)\r
+\r
+  // Disable the PCI IRQ.\r
+\r
+  Method(_DIS,0,Serialized)\r
+  {\r
+    Or(PHRC,0x80,PHRC)\r
+  }\r
+\r
+  // Possible IRQ Resource Setting.\r
+\r
+  Method (_PRS, 0, Serialized)\r
+  {\r
+    return (PRSH)\r
+  }\r
+\r
+  // Current IRQ Resource Setting.\r
+\r
+  Method(_CRS,0,Serialized)\r
+  {\r
+    Name(RTLH,ResourceTemplate()\r
+    {\r
+      IRQ(Level,ActiveLow,Shared) {}\r
+    })\r
+\r
+    // Point to specific byte.\r
+\r
+    CreateWordField(RTLH,1,IRQ0)\r
+\r
+    // Zero out IRQ mask bits 0-15\r
+\r
+    Store(Zero,IRQ0)\r
+\r
+    ShiftLeft(1,And(PHRC,0x0F),IRQ0)\r
+\r
+    Return(RTLH)\r
+  }\r
+\r
+  // Set IRQ Resource Setting.\r
+\r
+  Method(_SRS,1,Serialized)\r
+  {\r
+    // Point to the specific byte passed in.\r
+\r
+    CreateWordField(Arg0,1,IRQ0)\r
+\r
+    // Determine the IRQ bit to set and store it,\r
+\r
+    FindSetRightBit(IRQ0,Local0)\r
+    Decrement(Local0)\r
+    Store(Local0,PHRC)\r
+  }\r
+\r
+  // PCI IRQ Status.\r
+\r
+  Method(_STA,0,Serialized)\r
+  {\r
+    If(And(PHRC,0x80))\r
+    {\r
+      Return(0x0009)\r
+    }\r
+    Else\r
+    {\r
+      Return(0x000B)\r
+    }\r
+  }\r
+}\r

diff --git a/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/AcpiTablePlatform.h b/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/AcpiTablePlatform.h
new file mode 100644 (file)
index 0000000..1f81d25
--- /dev/null
+++ b/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/AcpiTablePlatform.h
@@ -0,0 +1,76 @@
+/*++\r
+\r
+Copyright (c)  1999  - 2014, Intel Corporation. All rights reserved\r
+\r
+  This program and the accompanying materials are licensed and made available under\r
+  the terms and conditions of the BSD License that accompanies this distribution.\r
+  The full text of the license may be found at\r
+  http://opensource.org/licenses/bsd-license.php.\r
+\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+\r
+Module Name:\r
+\r
+  AcpiTablePlatform.h\r
+\r
+\r
+Abstract: File contains platform specific ACPI defines for use in ACPI tables\r
+\r
+\r
+--*/\r
+#ifndef _Platform_h_INCLUDED_\r
+#define _Platform_h_INCLUDED_\r
+\r
+#ifdef ECP_FLAG\r
+#include "EdkIIGlueDxe.h"\r
+#endif\r
+#include <IndustryStandard/Acpi.h>\r
+//\r
+// ACPI table information used to initialize tables.\r
+//\r
+#define EFI_ACPI_OEM_ID           'O','E','M','I','D',' '   // OEMID 6 bytes long\r
+#define EFI_ACPI_OEM_TABLE_ID     SIGNATURE_64('O','E','M','T','A','B','L','E') // OEM table id 8 bytes long\r
+#define EFI_ACPI_OEM_REVISION     0x00000005\r
+#define EFI_ACPI_CREATOR_ID       SIGNATURE_32('C','R','E','A')\r
+#define EFI_ACPI_CREATOR_REVISION 0x0100000D\r
+#define INT_MODEL       0x01\r
+#define PM_PROFILE      EFI_ACPI_4_0_PM_PROFILE_MOBILE\r
+#define SCI_INT_VECTOR  0x0009\r
+#define SMI_CMD_IO_PORT 0x000000B2\r
+#define ACPI_ENABLE     0x0A0\r
+#define ACPI_DISABLE    0x0A1\r
+#define S4BIOS_REQ      0x00\r
+#define PSTATE_CNT      0x00\r
+#define PM1a_EVT_BLK    0x00000400\r
+#define PM1b_EVT_BLK    0x00000000\r
+#define PM1a_CNT_BLK    0x00000404\r
+#define PM1b_CNT_BLK    0x00000000\r
+#define PM2_CNT_BLK     0x00000450\r
+#define PM_TMR_BLK      0x00000408\r
+#define GPE0_BLK        0x00000420\r
+#define GPE1_BLK        0x00000000\r
+#define PM1_EVT_LEN     0x04\r
+#define PM1_CNT_LEN     0x02\r
+#define PM2_CNT_LEN     0x01\r
+#define PM_TM_LEN       0x04\r
+#define GPE0_BLK_LEN    0x10\r
+#define GPE1_BLK_LEN    0x00\r
+#define GPE1_BASE       0x00\r
+#define CST_CNT         0x00\r
+#define P_LVL2_LAT      0x0064\r
+#define P_LVL3_LAT      0x01F4\r
+#define FLUSH_SIZE      0x0400\r
+#define FLUSH_STRIDE    0x0010\r
+#define DUTY_OFFSET     0x01\r
+#define DUTY_WIDTH      0x03\r
+#define DAY_ALRM        0x0D\r
+#define MON_ALRM        0x00\r
+#define CENTURY         0x32\r
+#define FLAG            ( EFI_ACPI_4_0_WBINVD | EFI_ACPI_4_0_SLP_BUTTON | EFI_ACPI_4_0_RESET_REG_SUP | EFI_ACPI_4_0_RTC_S4)\r
+#define IAPC_BOOT_ARCH  ( EFI_ACPI_4_0_VGA_NOT_PRESENT | EFI_ACPI_4_0_8042 | EFI_ACPI_4_0_LEGACY_DEVICES)\r
+#define RESERVED        0x00\r
+\r
+#endif\r

diff --git a/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/AcpiTables.inf b/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/AcpiTables.inf
new file mode 100644 (file)
index 0000000..c857ab8
--- /dev/null
+++ b/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/AcpiTables.inf
@@ -0,0 +1,44 @@
+## @file\r
+# Component description file for PlatformAcpiTable module.\r
+#\r
+# Build acpi table data required by system boot.\r
+#  All .asi files tagged with "ToolCode="DUMMY"" in following file list are device description and are included\r
+#  by top level ASL file which will be dealed with by asl.exe application.\r
+#\r
+# Copyright (c)  1999  - 2014, Intel Corporation. All rights reserved\r
+#\r
+# This program and the accompanying materials are licensed and made available under\r
+# the terms and conditions of the BSD License that accompanies this distribution.\r
+# The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php.\r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+#\r
+#\r
+##\r
+\r
+[defines]\r
+  INF_VERSION                    = 0x00010005\r
+  BASE_NAME                      = AcpiTables\r
+  FILE_GUID                      = 7E374E25-8E01-4FEE-87F2-390C23C606CD\r
+  MODULE_TYPE                    = USER_DEFINED\r
+  VERSION_STRING                 = 1.0\r
+  EDK_RELEASE_VERSION            = 0x00020000\r
+  EFI_SPECIFICATION_VERSION      = 0x00020000\r
+\r
+[sources.common]\r
+  DSDT.ASL\r
+  Facs/Facs.aslc\r
+  Facp/Facp.aslc\r
+  Madt/Madt30.aslc\r
+  Mcfg/Mcfg.aslc\r
+  Hpet/Hpet.aslc\r
+  Lpit/Lpit.aslc\r
+\r
+\r
+[Packages]\r
+  MdePkg/MdePkg.dec\r
+  Vlv2TbltDevicePkg/PlatformPkg.dec\r
+  Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec\r

diff --git a/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/CPU.asl b/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/CPU.asl
new file mode 100644 (file)
index 0000000..9092ff8
--- /dev/null
+++ b/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/CPU.asl
@@ -0,0 +1,55 @@
+/**************************************************************************;\r
+;*                                                                        *;\r
+;*                                                                        *;\r
+;*    Intel Corporation - ACPI Reference Code for the Baytrail            *;\r
+;*    Family of Customer Reference Boards.                                *;\r
+;*                                                                        *;\r
+;*                                                                        *;\r
+;*    Copyright (c)  1999  - 2014, Intel Corporation. All rights reserved   *;\r
+;\r
+; This program and the accompanying materials are licensed and made available under\r
+; the terms and conditions of the BSD License that accompanies this distribution.\r
+; The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php.\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+;*                                                                        *;\r
+;*                                                                        *;\r
+;**************************************************************************/\r
+\r
+\r
+\r
+// NOTE:  The _PDC Implementation is out of the scope of this\r
+// reference code.  Please see the latest Hyper-Threading Technology\r
+// Reference Code for complete implementation details.\r
+\r
+Scope(\_PR)\r
+{\r
+  Processor(CPU0,         // Unique name for Processor 0.\r
+            1,                        // Unique ID for Processor 0.\r
+            0x00,                 // CPU0 ACPI P_BLK address = ACPIBASE + 10h.\r
+            0)                        // CPU0  P_BLK length = 6 bytes.\r
+  {}\r
+\r
+  Processor(CPU1,         // Unique name for Processor 1.\r
+            2,                        // Unique ID for Processor 1.\r
+            0x00,\r
+            0)                    // CPU1 P_BLK length = 6 bytes.\r
+  {}\r
+\r
+  Processor(CPU2,         // Unique name for Processor 2.\r
+            3,                        // Unique ID for Processor 2.\r
+            0x00,\r
+            0)                    // CPU2 P_BLK length = 6 bytes.\r
+  {}\r
+\r
+  Processor(CPU3,         // Unique name for Processor 3.\r
+            4,                        // Unique ID for Processor 3.\r
+            0x00,\r
+            0)                    // CPU3 P_BLK length = 6 bytes.\r
+  {}\r
+}     // End _PR\r
+\r
+\r

diff --git a/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/DSDT.ASL b/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/DSDT.ASL
new file mode 100644 (file)
index 0000000..56ed337
--- /dev/null
+++ b/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/DSDT.ASL
@@ -0,0 +1,81 @@
+/**************************************************************************;\r
+;*                                                                        *;\r
+;*                                                                        *;\r
+;*    Intel Corporation - ACPI Reference Code for the Sandy Bridge        *;\r
+;*    Family of Customer Reference Boards.                                *;\r
+;*                                                                        *;\r
+;*                                                                        *;\r
+;*    Copyright (c) 2012  - 2014, Intel Corporation. All rights reserved    *;\r
+;\r
+; This program and the accompanying materials are licensed and made available under\r
+; the terms and conditions of the BSD License that accompanies this distribution.\r
+; The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php.\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+;*                                                                        *;\r
+;*                                                                        *;\r
+;**************************************************************************/\r
+\r
+DefinitionBlock (\r
+  "DSDT.aml",\r
+  "DSDT",\r
+  0x02,  // DSDT revision.\r
+  "OEMID", // OEM ID (6 byte string)\r
+  "VLV-SOC", // OEM table ID  (8 byte string)\r
+  0x0 // OEM version of DSDT table (4 byte Integer)\r
+)\r
+\r
+// BEGIN OF ASL SCOPE\r
+{\r
+  External(MDBG, MethodObj)\r
+\r
+  Method(ADBG, 1, Serialized)\r
+  {\r
+\r
+    If(CondRefOf(MDBG))   //check if SSDT is loaded\r
+    {\r
+      Return(MDBG(Arg0))\r
+    }\r
+\r
+    Return(0)\r
+  }\r
+\r
+\r
+// Miscellaneous services enabled in Project\r
+  include ("token.asl")\r
+  include ("GloblNvs.asl")\r
+  include ("PciTree.asl")\r
+  include ("Pch.asl")\r
+  include ("Vlv.asl")\r
+  include ("CPU.asl")\r
+  include ("Platform.asl")\r
+  include ("THERMAL.ASL")\r
+  include ("PCI_DRC.ASL")\r
+  include ("Video.asl")\r
+  include ("Gpe.asl")\r
+  include ("IoTVirtualDevice.asl")\r
+\r
+  // Sleep states supported by Chipset/Board.\r
+  // SSx - BIOS setup controlled enabled _Sx Sleep state status\r
+  // Values to be written to SLP_TYPE register are provided by SBACPI.SDL (South Bridge ACPI ModulePart)\r
+\r
+  Name(\_S0, Package(4) {0x0,0x0,0,0}) // mandatory System state\r
+  Name(\_S1, Package(4) {0x1,0x0,0,0})\r
+  Name(\_S3, Package(4) {0x5,0x0,0,0})\r
+  Name(\_S4, Package(4) {0x6,0x0,0,0})\r
+  Name(\_S5, Package(4) {0x7,0x0,0,0}) // mandatory System state\r
+\r
+  Method(PTS, 1)          // METHOD CALLED FROM _PTS PRIOR TO ENTER ANY SLEEP STATE\r
+  {\r
+    If(Arg0)            // entering any sleep state\r
+    {\r
+    }\r
+  }\r
+  Method(WAK, 1)          // METHOD CALLED FROM _WAK RIGHT AFTER WAKE UP\r
+  {\r
+  }\r
+\r
+}// End of ASL File\r

diff --git a/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/Facp/Facp.aslc b/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/Facp/Facp.aslc
new file mode 100644 (file)
index 0000000..c9319d5
--- /dev/null
+++ b/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/Facp/Facp.aslc
@@ -0,0 +1,194 @@
+/*++\r
+\r
+Copyright (c)  1999  - 2014, Intel Corporation. All rights reserved\r
+\r
+  This program and the accompanying materials are licensed and made available under\r
+  the terms and conditions of the BSD License that accompanies this distribution.\r
+  The full text of the license may be found at\r
+  http://opensource.org/licenses/bsd-license.php.\r
+\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+\r
+Module Name:\r
+\r
+  Facp.c\r
+\r
+\r
+Abstract: The fixed ACPI description Table (FADT) Structure\r
+\r
+\r
+--*/\r
+#ifdef ECP_FLAG\r
+#include "EDKIIGlueDxe.h"\r
+#else\r
+#include <PiDxe.h>\r
+#endif\r
+#include <IndustryStandard/Acpi50.h>\r
+#include "AcpiTablePlatform.h"\r
+\r
+EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE FACP = {\r
+  {\r
+    EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE,\r
+    sizeof (EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE),\r
+    EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION,\r
+    0,                                                                                    // to make sum of entire table == 0\r
+    EFI_ACPI_OEM_ID,         // OEMID is a 6 bytes long field\r
+    EFI_ACPI_OEM_TABLE_ID,      // OEM table identification(8 bytes long)\r
+    EFI_ACPI_OEM_REVISION,      // OEM revision number\r
+    EFI_ACPI_CREATOR_ID,        // ASL compiler vendor ID\r
+    EFI_ACPI_CREATOR_REVISION   // ASL compiler revision number\r
+  },\r
+  0,                                                                                    // Physical addesss of FACS\r
+  0,                                                                                    // Physical address of DSDT\r
+  INT_MODEL,                                                                                    // System Interrupt Model (ignored in 2k and later, must be 0 for 98)\r
+  PM_PROFILE,                                                                                   // Preferred PM Profile\r
+  SCI_INT_VECTOR,                                                                       // System vector of SCI interrupt\r
+  SMI_CMD_IO_PORT,                                                                      // Port address of SMI command port\r
+  ACPI_ENABLE,                                                                          // value to write to port smi_cmd to enable ACPI\r
+  ACPI_DISABLE,                                                                         // value to write to port smi_cmd to disable ACPI\r
+  S4BIOS_REQ,                                                                           // Value to write to SMI CMD port to enter the S4BIOS state\r
+  PSTATE_CNT,       // PState control\r
+  PM1a_EVT_BLK,                                                                         // Port address of Power Mgt 1a Event Reg Blk\r
+  PM1b_EVT_BLK,                                                                         // Port address of Power Mgt 1b Event Reg Blk\r
+  PM1a_CNT_BLK,                                                                         // Port address of Power Mgt 1a Ctrl Reg Blk\r
+  PM1b_CNT_BLK,                                                                         // Port address of Power Mgt 1b Ctrl Reg Blk\r
+  PM2_CNT_BLK,                                                                          // Port address of Power Mgt 2  Ctrl Reg Blk\r
+  PM_TMR_BLK,                                                                           // Port address of Power Mgt Timer Ctrl Reg Blk\r
+  GPE0_BLK,                                                                             // Port addr of General Purpose Event 0 Reg Blk\r
+  GPE1_BLK,                                                                             // Port addr of General Purpose Event 1 Reg Blk\r
+  PM1_EVT_LEN,                                                                          // Byte Length of ports at pm1X_evt_blk\r
+  PM1_CNT_LEN,                                                                          // Byte Length of ports at pm1X_cnt_blk\r
+  PM2_CNT_LEN,                                                                          // Byte Length of ports at pm2_cnt_blk\r
+  PM_TM_LEN,                                                                            // Byte Length of ports at pm_tm_blk\r
+  GPE0_BLK_LEN,                                                                         // Byte Length of ports at gpe0_blk\r
+  GPE1_BLK_LEN,                                                                         // Byte Length of ports at gpe1_blk\r
+  GPE1_BASE,                                                                            // offset in gpe model where gpe1 events start\r
+  CST_CNT,          // _CST support\r
+  P_LVL2_LAT,                                                                           // worst case HW latency to enter/exit C2 state\r
+  P_LVL3_LAT,                                                                           // worst case HW latency to enter/exit C3 state\r
+  FLUSH_SIZE,                                                                           // Size of area read to flush caches\r
+  FLUSH_STRIDE,                                                                         // Stride used in flushing caches\r
+  DUTY_OFFSET,                                                                          // bit location of duty cycle field in p_cnt reg\r
+  DUTY_WIDTH,                                                                           // bit width of duty cycle field in p_cnt reg\r
+  DAY_ALRM,                                                                             // index to day-of-month alarm in RTC CMOS RAM\r
+  MON_ALRM,                                                                             // index to month-of-year alarm in RTC CMOS RAM\r
+  CENTURY,                                                                              // index to century in RTC CMOS RAM\r
+  IAPC_BOOT_ARCH,                                                                       // IA-PCI Boot Architecture Flag\r
+  RESERVED,                                                                             // reserved\r
+  FLAG,\r
+  {\r
+    EFI_ACPI_5_0_SYSTEM_IO,\r
+    8,\r
+    0,\r
+    0,\r
+    0xCF9\r
+  },\r
+  0x06,             // Hardware reset value\r
+  0, 0, 0,          // Reserved\r
+  0,                // XFirmwareCtrl\r
+  0,                // XDsdt\r
+  //\r
+  // X_PM1a Event Register Block\r
+  //\r
+  EFI_ACPI_5_0_SYSTEM_IO,\r
+  0x20,\r
+  0x00,\r
+  EFI_ACPI_3_0_DWORD,\r
+  PM1a_EVT_BLK,\r
+\r
+  //\r
+  // X_PM1b Event Register Block\r
+  //\r
+  EFI_ACPI_5_0_SYSTEM_IO,\r
+  0x00,\r
+  0x00,\r
+  EFI_ACPI_RESERVED_BYTE,\r
+  PM1b_EVT_BLK,\r
+\r
+  //\r
+  // X_PM1a Control Register Block\r
+  //\r
+  EFI_ACPI_5_0_SYSTEM_IO,\r
+  0x10,\r
+  0x00,\r
+  EFI_ACPI_3_0_WORD,\r
+  PM1a_CNT_BLK,\r
+\r
+  //\r
+  // X_PM1b Control Register Block\r
+  //\r
+  EFI_ACPI_5_0_SYSTEM_IO,\r
+  0x00,\r
+  0x00,\r
+  EFI_ACPI_RESERVED_BYTE,\r
+  PM1b_CNT_BLK,\r
+\r
+  //\r
+  // X_PM2 Control Register Block\r
+  //\r
+  EFI_ACPI_5_0_SYSTEM_IO,\r
+  0x08,\r
+  0x00,\r
+  EFI_ACPI_3_0_BYTE,\r
+  PM2_CNT_BLK,\r
+\r
+  //\r
+  // X_PM Timer Control Register Block\r
+  //\r
+  EFI_ACPI_5_0_SYSTEM_IO,\r
+  0x20,\r
+  0x00,\r
+  EFI_ACPI_3_0_DWORD,\r
+  PM_TMR_BLK,\r
+\r
+  //\r
+  // X_General Purpose Event 0 Register Block\r
+  //\r
+  EFI_ACPI_5_0_SYSTEM_IO,\r
+  0x80,\r
+  0x00,\r
+  EFI_ACPI_RESERVED_BYTE,\r
+  GPE0_BLK,\r
+\r
+  //\r
+  // X_General Purpose Event 1 Register Block\r
+  //\r
+  EFI_ACPI_5_0_SYSTEM_IO,\r
+  0x00,\r
+  0x00,\r
+  EFI_ACPI_RESERVED_BYTE,\r
+  GPE1_BLK,\r
+\r
+  //\r
+  // Sleep Control Register Block\r
+  //\r
+  EFI_ACPI_5_0_SYSTEM_IO,\r
+  0x08,\r
+  0x00,\r
+  EFI_ACPI_RESERVED_BYTE,\r
+  0,\r
+\r
+  //\r
+  // Sleep Status Register Block\r
+  //\r
+  EFI_ACPI_5_0_SYSTEM_IO,\r
+  0x08,\r
+  0x00,\r
+  EFI_ACPI_RESERVED_BYTE,\r
+  0,\r
+};\r
+\r
+VOID*\r
+ReferenceAcpiTable (\r
+  VOID\r
+  )\r
+{\r
+  //\r
+  // Reference the table being generated to prevent the optimizer from\r
+  // removing the data structure from the executable\r
+  //\r
+  return (VOID*)&FACP;\r
+}\r

diff --git a/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/Facs/Facs.aslc b/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/Facs/Facs.aslc
new file mode 100644 (file)
index 0000000..45050f0
--- /dev/null
+++ b/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/Facs/Facs.aslc
@@ -0,0 +1,90 @@
+/*++\r
+\r
+Copyright (c)  1999  - 2014, Intel Corporation. All rights reserved\r
+\r
+  This program and the accompanying materials are licensed and made available under\r
+  the terms and conditions of the BSD License that accompanies this distribution.\r
+  The full text of the license may be found at\r
+  http://opensource.org/licenses/bsd-license.php.\r
+\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+\r
+Module Name:\r
+\r
+  Ea815acpiFACS.c\r
+\r
+\r
+Abstract:\r
+\r
+  This file contains the FACS structure definition.\r
+\r
+--*/\r
+\r
+//\r
+// Statements that include other files\r
+//\r
+#ifdef ECP_FLAG\r
+#include "EDKIIGlueDxe.h"\r
+#else\r
+#include <PiDxe.h>\r
+#endif\r
+#include <IndustryStandard/Acpi50.h>\r
+#include "AcpiTablePlatform.h"\r
+\r
+EFI_ACPI_5_0_FIRMWARE_ACPI_CONTROL_STRUCTURE FACS = {\r
+  EFI_ACPI_5_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_SIGNATURE,\r
+  sizeof (EFI_ACPI_5_0_FIRMWARE_ACPI_CONTROL_STRUCTURE),\r
+\r
+  //\r
+  // Hardware Signature will be updated at runtime\r
+  //\r
+  0x00000000,                  //HardwareSignature\r
+  0x00000000,                  //FirmwareWakingVector\r
+  0x00000000,                  //GlobalLock\r
+  0x00000000,                  //Flags\r
+  0x0000000000000000,          //XFirmwareWakingVector\r
+  EFI_ACPI_5_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_VERSION,\r
+  EFI_ACPI_RESERVED_BYTE,      //Reserved0[3]\r
+  EFI_ACPI_RESERVED_BYTE,\r
+  EFI_ACPI_RESERVED_BYTE,\r
+  0x00000000,                  //OspmFlags\r
+  EFI_ACPI_RESERVED_BYTE,      //Reserved1[24]\r
+  EFI_ACPI_RESERVED_BYTE,\r
+  EFI_ACPI_RESERVED_BYTE,\r
+  EFI_ACPI_RESERVED_BYTE,\r
+  EFI_ACPI_RESERVED_BYTE,\r
+  EFI_ACPI_RESERVED_BYTE,\r
+  EFI_ACPI_RESERVED_BYTE,\r
+  EFI_ACPI_RESERVED_BYTE,\r
+  EFI_ACPI_RESERVED_BYTE,\r
+  EFI_ACPI_RESERVED_BYTE,\r
+  EFI_ACPI_RESERVED_BYTE,\r
+  EFI_ACPI_RESERVED_BYTE,\r
+  EFI_ACPI_RESERVED_BYTE,\r
+  EFI_ACPI_RESERVED_BYTE,\r
+  EFI_ACPI_RESERVED_BYTE,\r
+  EFI_ACPI_RESERVED_BYTE,\r
+  EFI_ACPI_RESERVED_BYTE,\r
+  EFI_ACPI_RESERVED_BYTE,\r
+  EFI_ACPI_RESERVED_BYTE,\r
+  EFI_ACPI_RESERVED_BYTE,\r
+  EFI_ACPI_RESERVED_BYTE,\r
+  EFI_ACPI_RESERVED_BYTE,\r
+  EFI_ACPI_RESERVED_BYTE,\r
+  EFI_ACPI_RESERVED_BYTE\r
+};\r
+\r
+VOID*\r
+ReferenceAcpiTable (\r
+  VOID\r
+  )\r
+{\r
+  //\r
+  // Reference the table being generated to prevent the optimizer from\r
+  // removing the data structure from the executable\r
+  //\r
+  return (VOID*)&FACS;\r
+}\r

diff --git a/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/GloblNvs.asl b/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/GloblNvs.asl
new file mode 100644 (file)
index 0000000..fffc829
--- /dev/null
+++ b/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/GloblNvs.asl
@@ -0,0 +1,352 @@
+/**************************************************************************;\r
+;*                                                                        *;\r
+;*                                                                        *;\r
+;*    Intel Corporation - ACPI Reference Code for the Baytrail            *;\r
+;*    Family of Customer Reference Boards.                                *;\r
+;*                                                                        *;\r
+;*                                                                        *;\r
+;*    Copyright (c)  1999  - 2014, Intel Corporation. All rights reserved   *;\r
+;\r
+; This program and the accompanying materials are licensed and made available under\r
+; the terms and conditions of the BSD License that accompanies this distribution.\r
+; The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php.\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+;*                                                                        *;\r
+;*                                                                        *;\r
+;**************************************************************************/\r
+\r
+\r
+\r
+// Define a Global region of ACPI NVS Region that may be used for any\r
+// type of implementation.  The starting offset and size will be fixed\r
+// up by the System BIOS during POST.  Note that the Size must be a word\r
+// in size to be fixed up correctly.\r
+\r
+OperationRegion(GNVS,SystemMemory,0xFFFF0000,0xAA55)\r
+Field(GNVS,AnyAcc,Lock,Preserve)\r
+{\r
+  Offset(0),       // Miscellaneous Dynamic Registers:\r
+  OSYS,   16,      //   (00) Operating System\r
+      ,   8,       //   (02)\r
+      ,   8,       //   (03)\r
+      ,   8,       //   (04)\r
+      ,   8,       //   (05)\r
+      ,   8,       //   (06)\r
+      ,   8,       //   (07)\r
+      ,   8,       //   (08)\r
+      ,   8,       //   (09)\r
+      ,   8,       //   (10)\r
+  P80D,   32,      //   (11) Port 80 Debug Port Value\r
+  LIDS,   8,       //   (15) Lid State (Lid Open = 1)\r
+      ,   8,       //   (16)\r
+      ,   8,       //   (17)\r
+  Offset(18),      // Thermal Policy Registers:\r
+      ,   8,       //   (18)\r
+      ,   8,       //   (19)\r
+  ACTT,   8,       //   (20) Active Trip Point\r
+  PSVT,   8,       //   (21) Passive Trip Point\r
+  TC1V,   8,       //   (22) Passive Trip Point TC1 Value\r
+  TC2V,   8,       //   (23) Passive Trip Point TC2 Value\r
+  TSPV,   8,       //   (24) Passive Trip Point TSP Value\r
+  CRTT,   8,       //   (25) Critical Trip Point\r
+  DTSE,   8,       //   (26) Digital Thermal Sensor Enable\r
+  DTS1,   8,       //   (27) Digital Thermal Sensor 1 Reading\r
+  DTS2,   8,       //   (28) Digital Thermal Sensor 2 Reading\r
+  DTSF,   8,       //   (29) DTS SMI Function Call\r
+  Offset(30),      // Battery Support Registers:\r
+      ,   8,       //   (30)\r
+      ,   8,       //   (31)\r
+      ,   8,       //   (32)\r
+      ,   8,       //   (33)\r
+      ,   8,       //   (34)\r
+      ,   8,       //   (35)\r
+      ,   8,       //   (36)\r
+  Offset(40),      // CPU Identification Registers:\r
+  APIC,   8,       //   (40) APIC Enabled by SBIOS (APIC Enabled = 1)\r
+  MPEN,   8,       //   (41) Number of Logical Processors if MP Enabled != 0\r
+      ,   8,       //   (42)\r
+      ,   8,       //   (43)\r
+      ,   8,       //   (44)\r
+      ,   32,      //   (45)\r
+  Offset(50),      // SIO CMOS Configuration Registers:\r
+      ,   8,       //   (50)\r
+      ,   8,       //   (51)\r
+      ,   8,       //   (52)\r
+      ,   8,       //   (53)\r
+      ,   8,       //   (54)\r
+      ,   8,       //   (55)\r
+      ,   8,       //   (56)\r
+      ,   8,       //   (57)\r
+      ,   8,       //   (58)\r
+  Offset(60),      // Internal Graphics Registers:\r
+      ,   8,       //   (60)\r
+      ,   8,       //   (61)\r
+  CADL,   8,       //   (62) Current Attached Device List\r
+      ,   8,       //   (63)\r
+  CSTE,   16,      //   (64) Current Display State\r
+  NSTE,   16,      //   (66) Next Display State\r
+      ,   16,      //   (68)\r
+  NDID,   8,       //   (70) Number of Valid Device IDs\r
+  DID1,   32,      //   (71) Device ID 1\r
+  DID2,   32,      //   (75) Device ID 2\r
+  DID3,   32,      //   (79) Device ID 3\r
+  DID4,   32,      //   (83) Device ID 4\r
+  DID5,   32,      //   (87) Device ID 5\r
+      ,   32,      //   (91)\r
+      ,   8,       //   (95) Fifth byte of AKSV (mannufacturing mode)\r
+  Offset(103),     // Backlight Control Registers:\r
+      ,   8,       //   (103)\r
+  BRTL,   8,       //   (104) Brightness Level Percentage\r
+  Offset(105),     // Ambiant Light Sensor Registers:\r
+      ,   8,       //   (105)\r
+      ,   8,       //   (106)\r
+  LLOW,   8,       //   (107) LUX Low Value\r
+      ,   8,       //   (108)\r
+  Offset(110),     // EMA Registers:\r
+      ,   8,       //   (110)\r
+      ,   16,      //   (111)\r
+      ,   16,      //   (113)\r
+  Offset(116),     // MEF Registers:\r
+      ,   8,       //   (116) MEF Enable\r
+  Offset(117),     // PCIe Dock:\r
+      ,   8,       //   (117)\r
+  Offset(120),     // TPM Registers:\r
+      ,   8,       //   (120)\r
+      ,   8,       //   (121)\r
+      ,   8,       //   (122)\r
+      ,   8,       //   (123)\r
+      ,   32,      //   (124)\r
+      ,   8,       //   (125)\r
+      ,   8,       //   (129)\r
+  Offset(130),     //\r
+      ,   56,      //   (130)\r
+      ,   56,      //   (137)\r
+      ,   8,       //   (144)\r
+      ,   56,      //   (145)\r
+  Offset(170),     // IGD OpRegion/Software SCI base address\r
+  ASLB,   32,      //   (170) IGD OpRegion base address\r
+  Offset(174),     // IGD OpRegion/Software SCI shared data\r
+  IBTT,   8,       //   (174) IGD Boot Display Device\r
+  IPAT,   8,       //   (175) IGD Panel Type CMOs option\r
+  ITVF,   8,       //   (176) IGD TV Format CMOS option\r
+  ITVM,   8,       //   (177) IGD TV Minor Format CMOS option\r
+  IPSC,   8,       //   (178) IGD Panel Scaling\r
+  IBLC,   8,       //   (179) IGD BLC Configuration\r
+  IBIA,   8,       //   (180) IGD BIA Configuration\r
+  ISSC,   8,       //   (181) IGD SSC Configuration\r
+  I409,   8,       //   (182) IGD 0409 Modified Settings Flag\r
+  I509,   8,       //   (183) IGD 0509 Modified Settings Flag\r
+  I609,   8,       //   (184) IGD 0609 Modified Settings Flag\r
+  I709,   8,       //   (185) IGD 0709 Modified Settings Flag\r
+  IDMM,   8,       //   (186) IGD DVMT Mode\r
+  IDMS,   8,       //   (187) IGD DVMT Memory Size\r
+  IF1E,   8,       //   (188) IGD Function 1 Enable\r
+  HVCO,   8,       //   (189) HPLL VCO\r
+  NXD1,   32,      //   (190) Next state DID1 for _DGS\r
+  NXD2,   32,      //   (194) Next state DID2 for _DGS\r
+  NXD3,   32,      //   (198) Next state DID3 for _DGS\r
+  NXD4,   32,      //   (202) Next state DID4 for _DGS\r
+  NXD5,   32,      //   (206) Next state DID5 for _DGS\r
+  NXD6,   32,      //   (210) Next state DID6 for _DGS\r
+  NXD7,   32,      //   (214) Next state DID7 for _DGS\r
+  NXD8,   32,      //   (218) Next state DID8 for _DGS\r
+  GSMI,   8,       //   (222) GMCH SMI/SCI mode (0=SCI)\r
+  PAVP,   8,       //   (223) IGD PAVP data\r
+  Offset(225),\r
+  OSCC,   8,       //   (225) PCIE OSC Control\r
+  NEXP,   8,       //   (226) Native PCIE Setup Value\r
+  Offset(235), // Global Variables\r
+  DSEN,   8,       //   (235) _DOS Display Support Flag.\r
+  ECON,   8,       //   (236) Embedded Controller Availability Flag.\r
+  GPIC,   8,       //   (237) Global IOAPIC/8259 Interrupt Mode Flag.\r
+  CTYP,   8,       //   (238) Global Cooling Type Flag.\r
+  L01C,   8,       //   (239) Global L01 Counter.\r
+  VFN0,   8,       //   (240) Virtual Fan0 Status.\r
+  VFN1,   8,       //   (241) Virtual Fan1 Status.\r
+  Offset(256),\r
+  NVGA,   32,  //   (256) NVIG opregion address\r
+  NVHA,   32,  //   (260) NVHM opregion address\r
+  AMDA,   32,  //   (264) AMDA opregion address\r
+  DID6,   32,  //   (268) Device ID 6\r
+  DID7,   32,  //   (272) Device ID 7\r
+  DID8,   32,  //   (276) Device ID 8\r
+  Offset(332),\r
+  USEL,   8,    // (332) UART Selection\r
+  PU1E,   8,    // (333) PCU UART 1 Enabled\r
+  PU2E,   8,    // (334) PCU UART 2 Enabled\r
+\r
+  LPE0, 32,     // (335) LPE Bar0\r
+  LPE1, 32,     // (339) LPE Bar1\r
+  LPE2, 32,     // (343) LPE Bar2\r
+\r
+  Offset(347),\r
+      ,   8,    // (347)\r
+      ,   8,    // (348)\r
+  PFLV,   8,    // (349) Platform Flavor\r
+\r
+  Offset(351),\r
+  ICNF,   8,   //   (351) ISCT / AOAC Configuration\r
+  XHCI,   8,   //   (352) xHCI controller mode\r
+  PMEN,   8,   //   (353) PMIC enable/disable\r
+\r
+  LPEE,   8,   //   (354) LPE enable/disable\r
+  ISPA,   32,  //   (355) ISP Base Addr\r
+  ISPD,   8,    //  (359) ISP Device Selection 0: Disabled; 1: PCI Device 2; 2: PCI Device 3\r
+\r
+  offset(360),  // ((4+8+6)*4+2)*4=296\r
+  //\r
+  // Lpss controllers\r
+  //\r
+  PCIB,     32,\r
+  PCIT,     32,\r
+  D10A,     32,  //DMA1\r
+  D10L,     32,\r
+  D11A,     32,\r
+  D11L,     32,\r
+  P10A,     32,  //  PWM1\r
+  P10L,     32,\r
+  P11A,     32,\r
+  P11L,     32,\r
+  P20A,     32,  //  PWM2\r
+  P20L,     32,\r
+  P21A,     32,\r
+  P21L,     32,\r
+  U10A,     32,  // UART1\r
+  U10L,     32,\r
+  U11A,     32,\r
+  U11L,     32,\r
+  U20A,     32,  // UART2\r
+  U20L,     32,\r
+  U21A,     32,\r
+  U21L,     32,\r
+  SP0A,     32,  // SPI\r
+  SP0L,     32,\r
+  SP1A,     32,\r
+  SP1L,     32,\r
+\r
+  D20A,     32,  //DMA2\r
+  D20L,     32,\r
+  D21A,     32,\r
+  D21L,     32,\r
+  I10A,     32,  //  I2C1\r
+  I10L,     32,\r
+  I11A,     32,\r
+  I11L,     32,\r
+  I20A,     32,  //  I2C2\r
+  I20L,     32,\r
+  I21A,     32,\r
+  I21L,     32,\r
+  I30A,     32,  //  I2C3\r
+  I30L,     32,\r
+  I31A,     32,\r
+  I31L,     32,\r
+  I40A,     32,  //  I2C4\r
+  I40L,     32,\r
+  I41A,     32,\r
+  I41L,     32,\r
+  I50A,     32,  //  I2C5\r
+  I50L,     32,\r
+  I51A,     32,\r
+  I51L,     32,\r
+  I60A,     32,  //  I2C6\r
+  I60L,     32,\r
+  I61A,     32,\r
+  I61L,     32,\r
+  I70A,     32,  //  I2C7\r
+  I70L,     32,\r
+  I71A,     32,\r
+  I71L,     32,\r
+  //\r
+  // Scc controllers\r
+  //\r
+  eM0A,     32,  //  EMMC\r
+  eM0L,     32,\r
+  eM1A,     32,\r
+  eM1L,     32,\r
+  SI0A,     32,  //  SDIO\r
+  SI0L,     32,\r
+  SI1A,     32,\r
+  SI1L,     32,\r
+  SD0A,     32,  //  SDCard\r
+  SD0L,     32,\r
+  SD1A,     32,\r
+  SD1L,     32,\r
+  MH0A,     32,  //\r
+  MH0L,     32,\r
+  MH1A,     32,\r
+  MH1L,     32,\r
+\r
+  offset(656),\r
+  SDRM,     8,\r
+  offset(657),\r
+  HLPS,     8,   //(657) Hide Devices\r
+  offset(658),\r
+  OSEL,     8,      //(658) OS Seletion - Windows/Android\r
+\r
+  offset(659),  // VLV1 DPTF\r
+  SDP1,     8,      //(659) An enumerated value corresponding to SKU\r
+  DPTE,     8,      //(660) DPTF Enable\r
+  THM0,     8,      //(661) System Thermal 0\r
+  THM1,     8,      //(662) System Thermal 1\r
+  THM2,     8,      //(663) System Thermal 2\r
+  THM3,     8,      //(664) System Thermal 3\r
+  THM4,     8,      //(665) System Thermal 3\r
+  CHGR,     8,      //(666) DPTF Changer Device\r
+  DDSP,     8,      //(667) DPTF Display Device\r
+  DSOC,     8,      //(668) DPTF SoC device\r
+  DPSR,     8,      //(669) DPTF Processor device\r
+  DPCT,     32,     //(670) DPTF Processor participant critical temperature\r
+  DPPT,     32,     //(674) DPTF Processor participant passive temperature\r
+  DGC0,     32,     //(678) DPTF Generic sensor0 participant critical temperature\r
+  DGP0,     32,     //(682) DPTF Generic sensor0 participant passive temperature\r
+  DGC1,     32,     //(686) DPTF Generic sensor1 participant critical temperature\r
+  DGP1,     32,     //(690) DPTF Generic sensor1 participant passive temperature\r
+  DGC2,     32,     //(694) DPTF Generic sensor2 participant critical temperature\r
+  DGP2,     32,     //(698) DPTF Generic sensor2 participant passive temperature\r
+  DGC3,     32,     //(702) DPTF Generic sensor3 participant critical temperature\r
+  DGP3,     32,     //(706) DPTF Generic sensor3 participant passive temperature\r
+  DGC4,     32,     //(710)DPTF Generic sensor3 participant critical temperature\r
+  DGP4,     32,     //(714)DPTF Generic sensor3 participant passive temperature\r
+  DLPM,     8,      //(718) DPTF Current low power mode setting\r
+  DSC0,     32,     //(719) DPTF Critical threshold0 for SCU\r
+  DSC1,     32,     //(723) DPTF Critical threshold1 for SCU\r
+  DSC2,     32,     //(727) DPTF Critical threshold2 for SCU\r
+  DSC3,     32,     //(731) DPTF Critical threshold3 for SCU\r
+  DSC4,     32,     //(735) DPTF Critical threshold3 for SCU\r
+  DDBG,     8,      //(739) DPTF Super Debug option. 0 - Disabled, 1 - Enabled\r
+  LPOE,     32,     //(740) DPTF LPO Enable\r
+  LPPS,     32,     //(744) P-State start index\r
+  LPST,     32,     //(748) Step size\r
+  LPPC,     32,     //(752) Power control setting\r
+  LPPF,     32,     //(756) Performance control setting\r
+  DPME,     8,      //(760) DPTF DPPM enable/disable\r
+  BCSL,     8,      //(761) Battery charging solution 0-CLV 1-ULPMC\r
+  NFCS,     8,      //(762) NFCx Select 1: NFC1    2:NFC2\r
+  PCIM,     8,      //(763) EMMC device 0-ACPI mode, 1-PCI mode\r
+  TPMA,     32,     //(764)\r
+  TPML,     32,     //(768)\r
+  ITSA,      8,     //(772) I2C Touch Screen Address\r
+  S0IX,     8,      //(773) S0ix status\r
+  SDMD,     8,      //(774) SDIO Mode\r
+  EMVR,     8,      //(775) eMMC controller version\r
+  BMBD,     32,     //(776) BM Bound\r
+  FSAS,     8,      //(780) FSA Status\r
+  BDID,     8,      //(781) Board ID\r
+  FBID,     8,      //(782) FAB ID\r
+  OTGM,     8,      //(783) OTG mode\r
+  STEP,     8,      //(784) Stepping ID\r
+  WITT,     8,      //(785) Enable Test Device connected to I2C for WHCK test.\r
+  SOCS,     8,      //(786) provide the SoC stepping infomation\r
+  AMTE,     8,      //(787) Ambient Trip point change\r
+  UTS,      8,      //(788) Enable Test Device connected to URT for WHCK test.\r
+  SCPE,     8,      //(789) Allow higher performance on AC/USB - Enable/Disable\r
+  Offset(792),\r
+  EDPV,     8,      //(792) Check for eDP display device\r
+  DIDX,     32,     //(793) Device ID for eDP device\r
+  IOT,      8,      //(794) MinnowBoard Max JP1 is configured for MSFT IOT project.   \r
+}\r
+\r

diff --git a/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/Gpe.asl b/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/Gpe.asl
new file mode 100644 (file)
index 0000000..1753540
--- /dev/null
+++ b/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/Gpe.asl
@@ -0,0 +1,105 @@
+/**************************************************************************;\r
+;*                                                                        *;\r
+;*                                                                        *;\r
+;*    Intel Corporation - ACPI Reference Code for the Baytrail            *;\r
+;*    Family of Customer Reference Boards.                                *;\r
+;*                                                                        *;\r
+;*                                                                        *;\r
+;*    Copyright (c) 2012  - 2014, Intel Corporation. All rights reserved    *;\r
+;\r
+; This program and the accompanying materials are licensed and made available under\r
+; the terms and conditions of the BSD License that accompanies this distribution.\r
+; The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php.\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+;*                                                                        *;\r
+;*                                                                        *;\r
+;**************************************************************************/\r
+\r
+\r
+// General Purpose Events.  This Scope handles the Run-time and\r
+// Wake-time SCIs.  The specific method called will be determined by\r
+// the _Lxx value, where xx equals the bit location in the General\r
+// Purpose Event register(s).\r
+\r
+Scope(\_GPE)\r
+{\r
+  //\r
+  // Software GPE caused the event.\r
+  //\r
+  Method(_L02)\r
+  {\r
+    // Clear GPE status bit.\r
+    Store(0,GPEC)\r
+    //\r
+    // Handle DTS Thermal Events.\r
+    //\r
+    External(DTSE, IntObj)\r
+    If(CondRefOf(DTSE))\r
+    {\r
+      If(LGreaterEqual(DTSE, 0x01))\r
+      {\r
+        Notify(\_TZ.TZ01,0x80)\r
+      }\r
+    }\r
+  }\r
+\r
+  //\r
+  // PUNIT SCI event.\r
+  //\r
+  Method(_L04)\r
+  {\r
+    // Clear the PUNIT Status Bit.\r
+    Store(1, PSCI)\r
+  }\r
+\r
+\r
+  //\r
+  // IGD OpRegion SCI event (see IGD OpRegion/Software SCI BIOS SPEC).\r
+  //\r
+  Method(_L05)\r
+  {\r
+    If(LAnd(\_SB.PCI0.GFX0.GSSE, LNot(GSMI)))   // Graphics software SCI event?\r
+    {\r
+      \_SB.PCI0.GFX0.GSCI()     // Handle the SWSCI\r
+    }\r
+  }\r
+\r
+  //\r
+  // This PME event (PCH's GPE #13) is received when any PCH internal device with PCI Power Management capabilities\r
+  // on bus 0 asserts the equivalent of the PME# signal.\r
+  //\r
+  Method(_L0D, 0)\r
+  {\r
+    If(LAnd(\_SB.PCI0.EHC1.PMEE, \_SB.PCI0.EHC1.PMES))\r
+    {\r
+      If(LNotEqual(OSEL, 1))\r
+      {\r
+        Store(1, \_SB.PCI0.EHC1.PMES) //Clear PME status\r
+        Store(0, \_SB.PCI0.EHC1.PMEE) //Disable PME\r
+      }\r
+      Notify(\_SB.PCI0.EHC1, 0x02)\r
+    }\r
+    If(LAnd(\_SB.PCI0.XHC1.PMEE, \_SB.PCI0.XHC1.PMES))\r
+    {\r
+      If(LNotEqual(OSEL, 1))\r
+      {\r
+        Store(1, \_SB.PCI0.XHC1.PMES) //Clear PME status\r
+        Store(0, \_SB.PCI0.XHC1.PMEE) //Disable PME\r
+      }\r
+      Notify(\_SB.PCI0.XHC1, 0x02)\r
+    }\r
+    If(LAnd(\_SB.PCI0.HDEF.PMEE, \_SB.PCI0.HDEF.PMES))\r
+    {\r
+      If(LNotEqual(OSEL, 1))\r
+      {\r
+        Store(1, \_SB.PCI0.HDEF.PMES) //Clear PME status\r
+        Store(0, \_SB.PCI0.HDEF.PMEE) //Disable PME\r
+      }\r
+      Notify(\_SB.PCI0.HDEF, 0x02)\r
+    }\r
+  }\r
+}\r

diff --git a/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/HOST_BUS.ASL b/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/HOST_BUS.ASL
new file mode 100644 (file)
index 0000000..587909b
--- /dev/null
+++ b/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/HOST_BUS.ASL
@@ -0,0 +1,353 @@
+/*++\r
+\r
+Copyright (c)  1999  - 2014, Intel Corporation. All rights reserved\r
+\r
+  This program and the accompanying materials are licensed and made available under\r
+  the terms and conditions of the BSD License that accompanies this distribution.\r
+  The full text of the license may be found at\r
+  http://opensource.org/licenses/bsd-license.php.\r
+\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+\r
+Module Name:\r
+\r
+  HOST_BUS.ASL\r
+\r
+Abstract:\r
+\r
+  Baytrail PCI configuration space definition.\r
+\r
+---*/\r
+Device(VLVC)\r
+{\r
+  Name(_ADR, 0x00000000)           // Device 0, Function 0\r
+\r
+  // Define various MCH Controller PCI Configuration Space\r
+  // registers which will be used to dynamically produce all\r
+  // resources in the Host Bus _CRS.\r
+  OperationRegion(HBUS, PCI_Config, 0x00, 0xFF)\r
+  Field(HBUS, DWordAcc, NoLock, Preserve)\r
+  {\r
+    Offset(0xD0),\r
+    SMCR,   32,             // VLV Message Control Register (0xD0)\r
+    Offset(0xD4),\r
+    SMDR,   32,             // VLV Message Data Register (0xD4)\r
+    Offset(0xD8),\r
+    MCRX,   32,             // VLV Message Control Register Extension (0xD8)\r
+  }\r
+\r
+  // Define a method to read a 32-bit register on the VLV Message bus.\r
+  //  Arg0 = Port\r
+  //  Arg1 = Register\r
+  //\r
+  //  Returns 32-bit register value\r
+\r
+  Method(RMBR, 2, Serialized)\r
+  {\r
+\r
+    // Initiate regsiter read message on VLV Message Bus MCR\r
+\r
+    Or(ShiftLeft(Arg0, 16), ShiftLeft(Arg1, 8), Local0)\r
+    Or(0x100000F0, Local0, SMCR)\r
+\r
+    // Read register value from Message Data Register\r
+\r
+    Return(SMDR)\r
+  }\r
+\r
+\r
+  // Define a method to write a 32-bit register on the VLV Message bus MDR.\r
+  //  Arg0 = Port\r
+  //  Arg1 = Register\r
+  //  Arg2 = 32-bit value\r
+\r
+  Method(WMBR, 3, Serialized)\r
+  {\r
+\r
+    // Write register value to Message Data Register\r
+\r
+    Store(Arg2, SMDR)\r
+\r
+    // Initiate register write message on VLV Message Bus\r
+\r
+    Or(ShiftLeft(Arg0, 16), ShiftLeft(Arg1, 8), Local0)\r
+    Or(0x110000F0, Local0, SMCR)\r
+  }\r
+}\r
+\r
+//\r
+// BUS, I/O, and MMIO resources\r
+//\r
+Method(_CRS,0,Serialized)\r
+{\r
+  //Update ISP0 reserved memory\r
+  CreateDwordField(RES0, ^ISP0._MIN,ISMN)\r
+  CreateDwordField(RES0, ^ISP0._MAX,ISMX)\r
+  CreateDwordField(RES0, ^ISP0._LEN,ISLN)\r
+  If (LEqual(ISPD,1))\r
+  {\r
+    Store (ISPA, ISMN)\r
+    Add (ISMN, ISLN, ISMX)\r
+    Subtract(ISMX, 1, ISMX)\r
+  } Else\r
+  {\r
+    Store (0, ISMN)\r
+    Store (0, ISMX)\r
+    Store (0, ISLN)\r
+  }\r
+\r
+  //PCI MMIO SPACE\r
+  CreateDwordField(RES0, ^PM01._MIN,M1MN)\r
+  CreateDwordField(RES0, ^PM01._MAX,M1MX)\r
+  CreateDwordField(RES0, ^PM01._LEN,M1LN)\r
+\r
+  //Get dBMBOUND Base\r
+  And(BMBD, 0xFF000000, M1MN)\r
+\r
+  //Get ECBASE\r
+  Store(PCIT, M1MX)\r
+  Add(Subtract(M1MX, M1MN), 1, M1LN)\r
+  Subtract(M1MX, 1, M1MX)\r
+\r
+  // Create pointers to Gfx Stolen Memory Sizing values.\r
+  CreateDwordField(RES0, ^STOM._MIN,GSMN)\r
+  CreateDwordField(RES0, ^STOM._MAX,GSMX)\r
+  CreateDwordField(RES0, ^STOM._LEN,GSLN)\r
+\r
+  If (LNotEqual (\_SB.PCI0.GFX0.GSTM, 0xFFFFFFFF))\r
+  {\r
+    Store(0x00, GSMN) //Read the Stolen memory base from B0:D2:F0:R5C\r
+  } else\r
+  {\r
+    Store(\_SB.PCI0.GFX0.GSTM, GSMN) //Read the Stolen memory base from B0:D2:F0:R5C\r
+  }\r
+  If (LNotEqual (\_SB.PCI0.GFX0.GUMA, 0xFFFFFFFF))\r
+  {\r
+    Store(0x00, GSLN) //Read the Stolen memory base from B0:D2:F0:R5C\r
+  } else\r
+  {\r
+    ShiftLeft(\_SB.PCI0.GFX0.GUMA, 25, GSLN) //Read Stolen memory base form B0:D2:F0:R50\r
+  }\r
+  Add(GSMN, GSLN, GSMX) //Store the Stolen Memory Size\r
+  Subtract(GSMX, 1, GSMX)\r
+\r
+  Return(RES0)\r
+}\r
+\r
+Name( RES0,ResourceTemplate()\r
+{\r
+  WORDBusNumber (          // Bus number resource (0); the bridge produces bus numbers for its subsequent buses\r
+    ResourceProducer,      // bit 0 of general flags is 1\r
+    MinFixed,              // Range is fixed\r
+    MaxFixed,              // Range is fixed\r
+    PosDecode,             // PosDecode\r
+    0x0000,                // Granularity\r
+    0x0000,                // Min\r
+    0x00FF,                // Max\r
+    0x0000,                // Translation\r
+    0x0100                 // Range Length = Max-Min+1\r
+  )\r
+\r
+  IO (Decode16, 0x70, 0x77, 0x01, 0x08)         //Consumed resource (0xCF8-0xCFF)\r
+  IO (Decode16, 0xCF8, 0xCF8, 0x01, 0x08)       //Consumed resource (0xCF8-0xCFF)\r
+\r
+  WORDIO (                 // Consumed-and-produced resource (all I/O below CF8)\r
+    ResourceProducer,      // bit 0 of general flags is 0\r
+    MinFixed,              // Range is fixed\r
+    MaxFixed,              // Range is fixed\r
+    PosDecode,\r
+    EntireRange,\r
+    0x0000,                // Granularity\r
+    0x0000,                // Min\r
+    0x006F,                // Max\r
+    0x0000,                // Translation\r
+    0x0070                 // Range Length\r
+  )\r
+\r
+  WORDIO (                 // Consumed-and-produced resource\r
+    ResourceProducer,      // bit 0 of general flags is 0\r
+    MinFixed,              // Range is fixed\r
+    MaxFixed,              // Range is fixed\r
+    PosDecode,\r
+    EntireRange,\r
+    0x0000,                // Granularity\r
+    0x0078,                // Min\r
+    0x0CF7,                // Max\r
+    0x0000,                // Translation\r
+    0x0C80                 // Range Length\r
+  )\r
+\r
+  WORDIO (                 // Consumed-and-produced resource (all I/O above CFF)\r
+    ResourceProducer,      // bit 0 of general flags is 0\r
+    MinFixed,              // Range is fixed\r
+    MaxFixed,              // Range is fixed\r
+    PosDecode,\r
+    EntireRange,\r
+    0x0000,                // Granularity\r
+    0x0D00,                // Min\r
+    0xFFFF,                // Max\r
+    0x0000,                // Translation\r
+    0xF300                 // Range Length\r
+  )\r
+\r
+  DWORDMEMORY (            // Descriptor for legacy VGA video RAM\r
+    ResourceProducer,      // bit 0 of general flags is 0\r
+    PosDecode,\r
+    MinFixed,              // Range is fixed\r
+    MaxFixed,              // Range is fixed\r
+    Cacheable,\r
+    ReadWrite,\r
+    0x00000000,            // Granularity\r
+    0x000A0000,            // Min\r
+    0x000BFFFF,            // Max\r
+    0x00000000,            // Translation\r
+    0x00020000             // Range Length\r
+  )\r
+\r
+  DWORDMEMORY (            // Descriptor for legacy OptionRom\r
+    ResourceProducer,      // bit 0 of general flags is 0\r
+    PosDecode,\r
+    MinFixed,              // Range is fixed\r
+    MaxFixed,              // Range is fixed\r
+    Cacheable,\r
+    ReadWrite,\r
+    0x00000000,            // Granularity\r
+    0x000C0000,            // Min\r
+    0x000DFFFF,            // Max\r
+    0x00000000,            // Translation\r
+    0x00020000             // Range Length\r
+  )\r
+\r
+  DWORDMEMORY (            // Descriptor for BIOS Area\r
+    ResourceProducer,      // bit 0 of general flags is 0\r
+    PosDecode,\r
+    MinFixed,              // Range is fixed\r
+    MaxFixed,              // Range is fixed\r
+    Cacheable,\r
+    ReadWrite,\r
+    0x00000000,            // Granularity\r
+    0x000E0000,            // Min\r
+    0x000FFFFF,            // Max\r
+    0x00000000,            // Translation\r
+    0x00020000             // Range Length\r
+  )\r
+\r
+  DWORDMEMORY (            // Descriptor for ISP0 reserved Mem\r
+    ResourceProducer,      // bit 0 of general flags is 0\r
+    PosDecode,\r
+    MinFixed,              // Range is fixed\r
+    MaxFixed,              // Range is fixed\r
+    Cacheable,\r
+    ReadWrite,\r
+    0x00000000,            // Granularity\r
+    0x7A000000,            // Min\r
+    0x7A3FFFFF,            // Max\r
+    0x00000000,            // Translation\r
+    0x00400000             // Range Length\r
+    ,,,\r
+    ISP0\r
+  )\r
+\r
+  DWORDMEMORY (            // Descriptor for VGA Stolen Mem\r
+    ResourceProducer,      // bit 0 of general flags is 0\r
+    PosDecode,\r
+    MinFixed,              // Range is fixed\r
+    MaxFixed,              // Range is fixed\r
+    Cacheable,\r
+    ReadWrite,\r
+    0x00000000,            // Granularity\r
+    0x7C000000,            // Min\r
+    0x7FFFFFFF,            // Max\r
+    0x00000000,            // Translation\r
+    0x04000000             // Range Length\r
+    ,,,\r
+    STOM\r
+  )\r
+\r
+  DWORDMEMORY (            // Descriptor for PCI MMIO\r
+    ResourceProducer,      // bit 0 of general flags is 0\r
+    PosDecode,\r
+    MinFixed,              // Range is fixed\r
+    MaxFixed,              // Range is fixed\r
+    Cacheable,\r
+    ReadWrite,\r
+    0x00000000,            // Granularity\r
+    0x80000000,            // Min\r
+    0xDFFFFFFF,            // Max\r
+    0x00000000,            // Translation\r
+    0x60000000             // Range Length\r
+    ,,,\r
+    PM01\r
+  )\r
+})\r
+\r
+//Name(GUID,UUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))\r
+Name(GUID,Buffer()\r
+{\r
+  0x5b, 0x4d, 0xdb, 0x33,\r
+  0xf7, 0x1f,\r
+  0x1c, 0x40,\r
+  0x96, 0x57,\r
+  0x74, 0x41, 0xc0, 0x3d, 0xd7, 0x66\r
+})\r
+\r
+\r
+Name(SUPP,0)    // PCI _OSC Support Field value\r
+Name(CTRL,0)    // PCI _OSC Control Field value\r
+\r
+Method(_OSC,4,Serialized)\r
+{\r
+  // Check for proper UUID\r
+  // Save the capabilities buffer\r
+  Store(Arg3,Local0)\r
+\r
+  // Create DWord-adressable fields from the Capabilties Buffer\r
+  CreateDWordField(Local0,0,CDW1)\r
+  CreateDWordField(Local0,4,CDW2)\r
+  CreateDWordField(Local0,8,CDW3)\r
+\r
+  // Check for proper UUID\r
+  If(LAnd(LEqual(Arg0,GUID),NEXP))\r
+  {\r
+    // Save Capabilities DWord2 & 3\r
+    Store(CDW2,SUPP)\r
+    Store(CDW3,CTRL)\r
+\r
+    If(Not(And(CDW1,1)))    // Query flag clear?\r
+    {\r
+      // Disable GPEs for features granted native control.\r
+      If(And(CTRL,0x02))\r
+      {\r
+        NHPG()\r
+      }\r
+      If(And(CTRL,0x04))      // PME control granted?\r
+      {\r
+        NPME()\r
+      }\r
+    }\r
+\r
+    If(LNotEqual(Arg1,One))\r
+    {\r
+      // Unknown revision\r
+      Or(CDW1,0x08,CDW1)\r
+    }\r
+\r
+    If(LNotEqual(CDW3,CTRL))\r
+    {\r
+      // Capabilities bits were masked\r
+      Or(CDW1,0x10,CDW1)\r
+    }\r
+    // Update DWORD3 in the buffer\r
+       And(CTRL,0xfe,CTRL)                \r
+    Store(CTRL,CDW3)\r
+    Store(CTRL,OSCC)\r
+    Return(Local0)\r
+  } Else\r
+  {\r
+    Or(CDW1,4,CDW1)         // Unrecognized UUID\r
+    Return(Local0)\r
+  }\r
+}       // End _OSC\r

diff --git a/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/Hpet/Hpet.aslc b/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/Hpet/Hpet.aslc
new file mode 100644 (file)
index 0000000..d3988ca
--- /dev/null
+++ b/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/Hpet/Hpet.aslc
@@ -0,0 +1,69 @@
+/*++\r
+\r
+Copyright (c)  1999  - 2014, Intel Corporation. All rights reserved\r
+\r
+  This program and the accompanying materials are licensed and made available under\r
+  the terms and conditions of the BSD License that accompanies this distribution.\r
+  The full text of the license may be found at\r
+  http://opensource.org/licenses/bsd-license.php.\r
+\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+\r
+Module Name:\r
+\r
+  Hpet.c\r
+\r
+Abstract:\r
+\r
+  This file contains a structure definition for the ACPI HPET Table.\r
+--*/\r
+\r
+//\r
+// Statements that include other files\r
+//\r
+#ifdef ECP_FLAG\r
+#include <Tiano.h>\r
+#endif\r
+#include <Hpet.h>\r
+#include "AcpiTablePlatform.h"\r
+\r
+// Hpet Table\r
+EFI_ACPI_HIGH_PRECISION_EVENT_TIMER_TABLE_HEADER HPET = {\r
+  {\r
+    EFI_ACPI_3_0_HIGH_PRECISION_EVENT_TIMER_TABLE_SIGNATURE,\r
+    sizeof (EFI_ACPI_HIGH_PRECISION_EVENT_TIMER_TABLE_HEADER),\r
+    EFI_ACPI_HIGH_PRECISION_EVENT_TIMER_TABLE_REVISION,\r
+    0,                          // to make sum of entire table == 0\r
+    EFI_ACPI_OEM_ID,            // OEMID is a 6 bytes long field\r
+    EFI_ACPI_OEM_TABLE_ID,      // OEM table identification(8 bytes long)\r
+    EFI_ACPI_OEM_REVISION,      // OEM revision\r
+    EFI_ACPI_CREATOR_ID,        // ASL compiler vendor ID\r
+    EFI_ACPI_CREATOR_REVISION   // ASL compiler revision number\r
+  },\r
+  0x0,                          // EventTimerBlockId\r
+  {\r
+    0x00,                     // Address_Space_ID = System Memory\r
+    0x40,                     // Register_Bit_Width = 32 bits, mentioned about write failures when in 64bit in SCU HAS\r
+    0x00,                     // Register_Bit_offset\r
+    0x00,                     // Dword access\r
+    HPET_BASE_ADDRESS,        // Base addresse of HPET\r
+  },\r
+  0x0,                          // Only HPET's _UID in Namespace\r
+  MAIN_COUNTER_MIN_PERIODIC_CLOCK_TICKS,\r
+  0x0\r
+};\r
+\r
+VOID*\r
+ReferenceAcpiTable (\r
+  VOID\r
+  )\r
+{\r
+  //\r
+  // Reference the table being generated to prevent the optimizer from\r
+  // removing the data structure from the executable\r
+  //\r
+  return (VOID*)&HPET;\r
+}\r

diff --git a/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/INTELGFX.ASL b/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/INTELGFX.ASL
new file mode 100644 (file)
index 0000000..c8f663a
--- /dev/null
+++ b/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/INTELGFX.ASL
@@ -0,0 +1,885 @@
+/*++\r
+\r
+Copyright (c)  1999  - 2014, Intel Corporation. All rights reserved\r
+\r
+  This program and the accompanying materials are licensed and made available under\r
+  the terms and conditions of the BSD License that accompanies this distribution.\r
+  The full text of the license may be found at\r
+  http://opensource.org/licenses/bsd-license.php.\r
+\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+\r
+Module Name:\r
+\r
+  INTELGFX.ASL\r
+\r
+Abstract:\r
+\r
+  IGD OpRegion/Software ACPI Reference Code for the Baytrail Family.\r
+\r
+--*/\r
+\r
+// Enable/Disable Output Switching.  In WIN2K/WINXP, _DOS = 0 will\r
+// get called during initialization to prepare for an ACPI Display\r
+// Switch Event.  During an ACPI Display Switch, the OS will call\r
+// _DOS = 2 immediately after a Notify=0x80 to temporarily disable\r
+// all Display Switching.  After ACPI Display Switching is complete,\r
+// the OS will call _DOS = 0 to re-enable ACPI Display Switching.\r
+\r
+Method(_DOS,1)\r
+{\r
+  // Store Display Switching and LCD brightness BIOS control bit\r
+  Store(And(Arg0,7),DSEN)\r
+}\r
+\r
+// Enumerate the Display Environment.  This method will return\r
+// valid addresses for all display device encoders present in the\r
+// system.  The Miniport Driver will reject the addresses for every\r
+// encoder that does not have an attached display device.  After\r
+// enumeration is complete, the OS will call the _DGS methods\r
+// during a display switch only for the addresses accepted by the\r
+// Miniport Driver.  For hot-insertion and removal of display\r
+// devices, a re-enumeration notification will be required so the\r
+// address of the newly present display device will be accepted by\r
+// the Miniport Driver.\r
+\r
+Method(_DOD, 0, Serialized)\r
+{\r
+  Store(0, NDID)\r
+  If(LNotEqual(DIDL, Zero))\r
+  {\r
+    Store(SDDL(DIDL),DID1)\r
+  }\r
+  If(LNotEqual(DDL2, Zero))\r
+  {\r
+    Store(SDDL(DDL2),DID2)\r
+  }\r
+  If(LNotEqual(DDL3, Zero))\r
+  {\r
+    Store(SDDL(DDL3),DID3)\r
+  }\r
+  If(LNotEqual(DDL4, Zero))\r
+  {\r
+    Store(SDDL(DDL4),DID4)\r
+  }\r
+  If(LNotEqual(DDL5, Zero))\r
+  {\r
+    Store(SDDL(DDL5),DID5)\r
+  }\r
+\r
+  // TODO - This level of flexibility is not needed for a true\r
+  //      OEM design.  Simply determine the greatest number of\r
+  //      encoders the platform will suppport then remove all\r
+  //      return packages beyond that value.  Note that for\r
+  //      current silicon, the maximum number of encoders\r
+  //      possible is 5.\r
+\r
+  If(LEqual(NDID,1))\r
+  {\r
+    If (LNOTEqual (ISPD, 0))\r
+    {\r
+      Name(TMP0,Package() {0xFFFFFFFF,0xFFFFFFFF})\r
+      Store(Or(0x10000,DID1),Index(TMP0,0))\r
+      //Add ISP device to GFX0\r
+      Store(0x00020F38, Index(TMP0,1))\r
+      Return(TMP0)\r
+    } Else\r
+    {\r
+      Name(TMP1,Package() {0xFFFFFFFF})\r
+      Store(Or(0x10000,DID1),Index(TMP1,0))\r
+      Return(TMP1)\r
+    }\r
+  }\r
+\r
+  If(LEqual(NDID,2))\r
+  {\r
+    If (LNOTEqual (ISPD, 0))\r
+    {\r
+      Name(TMP2,Package() {0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF})\r
+      Store(Or(0x10000,DID1),Index(TMP2,0))\r
+      Store(Or(0x10000,DID2),Index(TMP2,1))\r
+      //Add ISP device to GFX0\r
+      Store(0x00020F38, Index(TMP2,2))\r
+      Return(TMP2)\r
+    } Else\r
+    {\r
+      Name(TMP3,Package() {0xFFFFFFFF, 0xFFFFFFFF})\r
+      Store(Or(0x10000,DID1),Index(TMP3,0))\r
+      Store(Or(0x10000,DID2),Index(TMP3,1))\r
+      Return(TMP3)\r
+    }\r
+  }\r
+\r
+  If(LEqual(NDID,3))\r
+  {\r
+    If (LNOTEqual (ISPD, 0))\r
+    {\r
+      Name(TMP4,Package() {0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,0xFFFFFFFF})\r
+      Store(Or(0x10000,DID1),Index(TMP4,0))\r
+      Store(Or(0x10000,DID2),Index(TMP4,1))\r
+      Store(Or(0x10000,DID3),Index(TMP4,2))\r
+      //Add ISP device to GFX0\r
+      Store(0x00020F38, Index(TMP4,3))\r
+      Return(TMP4)\r
+    } Else\r
+    {\r
+      Name(TMP5,Package() {0xFFFFFFFF, 0xFFFFFFFF,0xFFFFFFFF})\r
+      Store(Or(0x10000,DID1),Index(TMP5,0))\r
+      Store(Or(0x10000,DID2),Index(TMP5,1))\r
+      Store(Or(0x10000,DID3),Index(TMP5,2))\r
+      Return(TMP5)\r
+    }\r
+  }\r
+\r
+  If(LEqual(NDID,4))\r
+  {\r
+    If (LNOTEqual (ISPD, 0))\r
+    {\r
+      Name(TMP6,Package() {0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF})\r
+      Store(Or(0x10000,DID1),Index(TMP6,0))\r
+      Store(Or(0x10000,DID2),Index(TMP6,1))\r
+      Store(Or(0x10000,DID3),Index(TMP6,2))\r
+      Store(Or(0x10000,DID4),Index(TMP6,3))\r
+      //Add ISP device to GFX0\r
+      Store(0x00020F38, Index(TMP6,4))\r
+      Return(TMP6)\r
+    } Else\r
+    {\r
+      Name(TMP7,Package() {0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF})\r
+      Store(Or(0x10000,DID1),Index(TMP7,0))\r
+      Store(Or(0x10000,DID2),Index(TMP7,1))\r
+      Store(Or(0x10000,DID3),Index(TMP7,2))\r
+      Store(Or(0x10000,DID4),Index(TMP7,3))\r
+      Return(TMP7)\r
+    }\r
+  }\r
+\r
+  If(LGreater(NDID,4))\r
+  {\r
+    If (LNOTEqual (ISPD, 0))\r
+    {\r
+      Name(TMP8,Package() {0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF})\r
+      Store(Or(0x10000,DID1),Index(TMP8,0))\r
+      Store(Or(0x10000,DID2),Index(TMP8,1))\r
+      Store(Or(0x10000,DID3),Index(TMP8,2))\r
+      Store(Or(0x10000,DID4),Index(TMP8,3))\r
+      Store(Or(0x10000,DID5),Index(TMP8,4))\r
+      //Add ISP device to GFX0\r
+      Store(0x00020F38, Index(TMP8,5))\r
+      Return(TMP8)\r
+    } Else\r
+    {\r
+      Name(TMP9,Package() {0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF})\r
+      Store(Or(0x10000,DID1),Index(TMP9,0))\r
+      Store(Or(0x10000,DID2),Index(TMP9,1))\r
+      Store(Or(0x10000,DID3),Index(TMP9,2))\r
+      Store(Or(0x10000,DID4),Index(TMP9,3))\r
+      Store(Or(0x10000,DID5),Index(TMP9,4))\r
+      Return(TMP9)\r
+    }\r
+  }\r
+\r
+  // If nothing else, return Unknown LFP.\r
+  // (Prevents compiler warning.)\r
+\r
+  //Add ISP device to GFX0\r
+  If (LNOTEqual (ISPD, 0))\r
+  {\r
+    Return(Package() {0x00000400, 0x00020F38})\r
+  } Else\r
+  {\r
+    Return(Package() {0x00000400})\r
+  }\r
+}\r
+\r
+Device(DD01)\r
+{\r
+\r
+  // Return Unique ID.\r
+\r
+  Method(_ADR,0,Serialized)\r
+  {\r
+    If(LEqual(And(0x0F00,DID1),0x400))\r
+    {\r
+      Store(0x1, EDPV)\r
+      Store(DID1, DIDX)\r
+      Return(1)\r
+    }\r
+    If(LEqual(DID1,0))\r
+    {\r
+      Return(1)\r
+    }\r
+    Else\r
+    {\r
+      Return(And(0xFFFF,DID1))\r
+    }\r
+  }\r
+\r
+  // Return the Current Status.\r
+\r
+  Method(_DCS,0)\r
+  {\r
+    Return(CDDS(DID1))\r
+  }\r
+\r
+  // Query Graphics State (active or inactive).\r
+\r
+  Method(_DGS,0)\r
+  {\r
+    Return(NDDS(DID1))\r
+  }\r
+\r
+  // Device Set State.\r
+\r
+  // _DSS Table:\r
+  //\r
+  //      BIT31   BIT30   Execution\r
+  //      0       0       Don't implement.\r
+  //      0       1       Cache change.  Nothing to Implement.\r
+  //      1       0       Don't Implement.\r
+  //      1       1       Display Switch Complete.  Implement.\r
+\r
+  Method(_DSS,1)\r
+  {\r
+    If(LEqual(And(Arg0,0xC0000000),0xC0000000))\r
+    {\r
+\r
+      // State change was performed by the\r
+      // Video Drivers.  Simply update the\r
+      // New State.\r
+\r
+      Store(NSTE,CSTE)\r
+    }\r
+  }\r
+}\r
+\r
+Device(DD02)\r
+{\r
+\r
+  // Return Unique ID.\r
+\r
+  Method(_ADR,0,Serialized)\r
+  {\r
+    If(LEqual(And(0x0F00,DID2),0x400))\r
+    {\r
+      Store(0x2, EDPV)\r
+      Store(DID2, DIDX)\r
+      Return(2)\r
+    }\r
+    If(LEqual(DID2,0))\r
+    {\r
+      Return(2)\r
+    }\r
+    Else\r
+    {\r
+      Return(And(0xFFFF,DID2))\r
+    }\r
+  }\r
+\r
+  // Return the Current Status.\r
+\r
+  Method(_DCS,0)\r
+  {\r
+    Return(CDDS(DID2))\r
+  }\r
+\r
+  // Query Graphics State (active or inactive).\r
+\r
+  Method(_DGS,0)\r
+  {\r
+    // Return the Next State.\r
+    Return(NDDS(DID2))\r
+  }\r
+\r
+  // Device Set State. (See table above.)\r
+\r
+  Method(_DSS,1)\r
+  {\r
+    If(LEqual(And(Arg0,0xC0000000),0xC0000000))\r
+    {\r
+\r
+      // State change was performed by the\r
+      // Video Drivers.  Simply update the\r
+      // New State.\r
+\r
+      Store(NSTE,CSTE)\r
+    }\r
+  }\r
+}\r
+\r
+Device(DD03)\r
+{\r
+\r
+  // Return Unique ID.\r
+\r
+  Method(_ADR,0,Serialized)\r
+  {\r
+    If(LEqual(And(0x0F00,DID3),0x400))\r
+    {\r
+      Store(0x3, EDPV)\r
+      Store(DID3, DIDX)\r
+      Return(3)\r
+    }\r
+    If(LEqual(DID3,0))\r
+    {\r
+      Return(3)\r
+    }\r
+    Else\r
+    {\r
+      Return(And(0xFFFF,DID3))\r
+    }\r
+  }\r
+\r
+  // Return the Current Status.\r
+\r
+  Method(_DCS,0)\r
+  {\r
+    If(LEqual(DID3,0))\r
+    {\r
+      Return(0x0B)\r
+    }\r
+    Else\r
+    {\r
+      Return(CDDS(DID3))\r
+    }\r
+  }\r
+\r
+  // Query Graphics State (active or inactive).\r
+\r
+  Method(_DGS,0)\r
+  {\r
+    Return(NDDS(DID3))\r
+  }\r
+\r
+  // Device Set State. (See table above.)\r
+\r
+  Method(_DSS,1)\r
+  {\r
+    If(LEqual(And(Arg0,0xC0000000),0xC0000000))\r
+    {\r
+      // State change was performed by the\r
+      // Video Drivers.  Simply update the\r
+      // New State.\r
+\r
+      Store(NSTE,CSTE)\r
+    }\r
+  }\r
+}\r
+\r
+Device(DD04)\r
+{\r
+\r
+  // Return Unique ID.\r
+\r
+  Method(_ADR,0,Serialized)\r
+  {\r
+    If(LEqual(And(0x0F00,DID4),0x400))\r
+    {\r
+      Store(0x4, EDPV)\r
+      Store(DID4, DIDX)\r
+      Return(4)\r
+    }\r
+    If(LEqual(DID4,0))\r
+    {\r
+      Return(4)\r
+    }\r
+    Else\r
+    {\r
+      Return(And(0xFFFF,DID4))\r
+    }\r
+  }\r
+\r
+  // Return the Current Status.\r
+\r
+  Method(_DCS,0)\r
+  {\r
+    If(LEqual(DID4,0))\r
+    {\r
+      Return(0x0B)\r
+    }\r
+    Else\r
+    {\r
+      Return(CDDS(DID4))\r
+    }\r
+  }\r
+\r
+  // Query Graphics State (active or inactive).\r
+\r
+  Method(_DGS,0)\r
+  {\r
+    Return(NDDS(DID4))\r
+  }\r
+\r
+  // Device Set State. (See table above.)\r
+\r
+  Method(_DSS,1)\r
+  {\r
+    If(LEqual(And(Arg0,0xC0000000),0xC0000000))\r
+    {\r
+\r
+      // State change was performed by the\r
+      // Video Drivers.  Simply update the\r
+      // New State.\r
+\r
+      Store(NSTE,CSTE)\r
+    }\r
+  }\r
+}\r
+\r
+\r
+Device(DD05)\r
+{\r
+\r
+  // Return Unique ID.\r
+\r
+  Method(_ADR,0,Serialized)\r
+  {\r
+    If(LEqual(And(0x0F00,DID5),0x400))\r
+    {\r
+      Store(0x5, EDPV)\r
+      Store(DID5, DIDX)\r
+      Return(5)\r
+    }\r
+    If(LEqual(DID5,0))\r
+    {\r
+      Return(5)\r
+    }\r
+    Else\r
+    {\r
+      Return(And(0xFFFF,DID5))\r
+    }\r
+  }\r
+\r
+  // Return the Current Status.\r
+\r
+  Method(_DCS,0)\r
+  {\r
+    If(LEqual(DID5,0))\r
+    {\r
+      Return(0x0B)\r
+    }\r
+    Else\r
+    {\r
+      Return(CDDS(DID5))\r
+    }\r
+  }\r
+\r
+  // Query Graphics State (active or inactive).\r
+\r
+  Method(_DGS,0)\r
+  {\r
+    Return(NDDS(DID5))\r
+  }\r
+\r
+  // Device Set State. (See table above.)\r
+\r
+  Method(_DSS,1)\r
+  {\r
+    If(LEqual(And(Arg0,0xC0000000),0xC0000000))\r
+    {\r
+      // State change was performed by the\r
+      // Video Drivers.  Simply update the\r
+      // New State.\r
+\r
+      Store(NSTE,CSTE)\r
+    }\r
+  }\r
+}\r
+\r
+\r
+Device(DD06)\r
+{\r
+\r
+  // Return Unique ID.\r
+\r
+  Method(_ADR,0,Serialized)\r
+  {\r
+    If(LEqual(And(0x0F00,DID6),0x400))\r
+    {\r
+      Store(0x6, EDPV)\r
+      Store(DID6, DIDX)\r
+      Return(6)\r
+    }\r
+    If(LEqual(DID6,0))\r
+    {\r
+      Return(6)\r
+    }\r
+    Else\r
+    {\r
+      Return(And(0xFFFF,DID6))\r
+    }\r
+  }\r
+\r
+  // Return the Current Status.\r
+\r
+  Method(_DCS,0)\r
+  {\r
+    If(LEqual(DID6,0))\r
+    {\r
+      Return(0x0B)\r
+    }\r
+    Else\r
+    {\r
+      Return(CDDS(DID6))\r
+    }\r
+  }\r
+\r
+  // Query Graphics State (active or inactive).\r
+\r
+  Method(_DGS,0)\r
+  {\r
+    Return(NDDS(DID6))\r
+  }\r
+\r
+  // Device Set State. (See table above.)\r
+\r
+  Method(_DSS,1)\r
+  {\r
+    If(LEqual(And(Arg0,0xC0000000),0xC0000000))\r
+    {\r
+      // State change was performed by the\r
+      // Video Drivers.  Simply update the\r
+      // New State.\r
+\r
+      Store(NSTE,CSTE)\r
+    }\r
+  }\r
+}\r
+\r
+\r
+Device(DD07)\r
+{\r
+\r
+  // Return Unique ID.\r
+\r
+  Method(_ADR,0,Serialized)\r
+  {\r
+    If(LEqual(And(0x0F00,DID7),0x400))\r
+    {\r
+      Store(0x7, EDPV)\r
+      Store(DID7, DIDX)\r
+      Return(7)\r
+    }\r
+    If(LEqual(DID7,0))\r
+    {\r
+      Return(7)\r
+    }\r
+    Else\r
+    {\r
+      Return(And(0xFFFF,DID7))\r
+    }\r
+  }\r
+\r
+  // Return the Current Status.\r
+\r
+  Method(_DCS,0)\r
+  {\r
+    If(LEqual(DID7,0))\r
+    {\r
+      Return(0x0B)\r
+    }\r
+    Else\r
+    {\r
+      Return(CDDS(DID7))\r
+    }\r
+  }\r
+\r
+  // Query Graphics State (active or inactive).\r
+\r
+  Method(_DGS,0)\r
+  {\r
+    Return(NDDS(DID7))\r
+  }\r
+\r
+  // Device Set State. (See table above.)\r
+\r
+  Method(_DSS,1)\r
+  {\r
+    If(LEqual(And(Arg0,0xC0000000),0xC0000000))\r
+    {\r
+      // State change was performed by the\r
+      // Video Drivers.  Simply update the\r
+      // New State.\r
+\r
+      Store(NSTE,CSTE)\r
+    }\r
+  }\r
+}\r
+\r
+\r
+Device(DD08)\r
+{\r
+\r
+  // Return Unique ID.\r
+\r
+  Method(_ADR,0,Serialized)\r
+  {\r
+    If(LEqual(And(0x0F00,DID8),0x400))\r
+    {\r
+      Store(0x8, EDPV)\r
+      Store(DID8, DIDX)\r
+      Return(8)\r
+    }\r
+    If(LEqual(DID8,0))\r
+    {\r
+      Return(8)\r
+    }\r
+    Else\r
+    {\r
+      Return(And(0xFFFF,DID8))\r
+    }\r
+  }\r
+\r
+  // Return the Current Status.\r
+\r
+  Method(_DCS,0)\r
+  {\r
+    If(LEqual(DID8,0))\r
+    {\r
+      Return(0x0B)\r
+    }\r
+    Else\r
+    {\r
+      Return(CDDS(DID8))\r
+    }\r
+  }\r
+\r
+  // Query Graphics State (active or inactive).\r
+\r
+  Method(_DGS,0)\r
+  {\r
+    Return(NDDS(DID8))\r
+  }\r
+\r
+  // Device Set State. (See table above.)\r
+\r
+  Method(_DSS,1)\r
+  {\r
+    If(LEqual(And(Arg0,0xC0000000),0xC0000000))\r
+    {\r
+      // State change was performed by the\r
+      // Video Drivers.  Simply update the\r
+      // New State.\r
+\r
+      Store(NSTE,CSTE)\r
+    }\r
+  }\r
+}\r
+\r
+//device for eDP\r
+Device(DD1F)\r
+{\r
+  // Return Unique ID.\r
+\r
+  Method(_ADR,0,Serialized)\r
+  {\r
+    If(LEqual(EDPV, 0x0))\r
+    {\r
+      Return(0x1F)\r
+    }\r
+    Else\r
+    {\r
+      Return(And(0xFFFF,DIDX))\r
+    }\r
+  }\r
+\r
+  // Return the Current Status.\r
+\r
+  Method(_DCS,0)\r
+  {\r
+    If(LEqual(EDPV, 0x0))\r
+    {\r
+      Return(0x00)\r
+    }\r
+    Else\r
+    {\r
+      Return(CDDS(DIDX))\r
+    }\r
+  }\r
+\r
+  // Query Graphics State (active or inactive).\r
+\r
+  Method(_DGS,0)\r
+  {\r
+    Return(NDDS(DIDX))\r
+  }\r
+\r
+  // Device Set State. (See table above.)\r
+\r
+  Method(_DSS,1)\r
+  {\r
+    If(LEqual(And(Arg0,0xC0000000),0xC0000000))\r
+    {\r
+      // State change was performed by the\r
+      // Video Drivers.  Simply update the\r
+      // New State.\r
+      Store(NSTE,CSTE)\r
+    }\r
+  }\r
+  // Query List of Brightness Control Levels Supported.\r
+\r
+  Method(_BCL,0)\r
+  {\r
+    // List of supported brightness levels in the following sequence.\r
+\r
+    // Level when machine has full power.\r
+    // Level when machine is on batteries.\r
+    // Other supported levels.\r
+    Return(Package() {80, 50, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 100})\r
+  }\r
+\r
+  // Set the Brightness Level.\r
+\r
+  Method (_BCM,1)\r
+  {\r
+    // Set the requested level if it is between 0 and 100%.\r
+\r
+    If(LAnd(LGreaterEqual(Arg0,0),LLessEqual(Arg0,100)))\r
+    {\r
+      \_SB.PCI0.GFX0.AINT(1, Arg0)\r
+      Store(Arg0,BRTL)  // Store Brightness Level.\r
+    }\r
+  }\r
+\r
+  // Brightness Query Current level.\r
+\r
+  Method (_BQC,0)\r
+  {\r
+    Return(BRTL)\r
+  }\r
+}\r
+\r
+Method(SDDL,1)\r
+{\r
+  Increment(NDID)\r
+  Store(And(Arg0,0xF0F),Local0)\r
+  Or(0x80000000,Local0, Local1)\r
+  If(LEqual(DIDL,Local0))\r
+  {\r
+    Return(Local1)\r
+  }\r
+  If(LEqual(DDL2,Local0))\r
+  {\r
+    Return(Local1)\r
+  }\r
+  If(LEqual(DDL3,Local0))\r
+  {\r
+    Return(Local1)\r
+  }\r
+  If(LEqual(DDL4,Local0))\r
+  {\r
+    Return(Local1)\r
+  }\r
+  If(LEqual(DDL5,Local0))\r
+  {\r
+    Return(Local1)\r
+  }\r
+  If(LEqual(DDL6,Local0))\r
+  {\r
+    Return(Local1)\r
+  }\r
+  If(LEqual(DDL7,Local0))\r
+  {\r
+    Return(Local1)\r
+  }\r
+  If(LEqual(DDL8,Local0))\r
+  {\r
+    Return(Local1)\r
+  }\r
+  Return(0)\r
+}\r
+\r
+Method(CDDS,1)\r
+{\r
+  Store(And(Arg0,0xF0F),Local0)\r
+\r
+  If(LEqual(0, Local0))\r
+  {\r
+    Return(0x1D)\r
+  }\r
+  If(LEqual(CADL, Local0))\r
+  {\r
+    Return(0x1F)\r
+  }\r
+  If(LEqual(CAL2, Local0))\r
+  {\r
+    Return(0x1F)\r
+  }\r
+  If(LEqual(CAL3, Local0))\r
+  {\r
+    Return(0x1F)\r
+  }\r
+  If(LEqual(CAL4, Local0))\r
+  {\r
+    Return(0x1F)\r
+  }\r
+  If(LEqual(CAL5, Local0))\r
+  {\r
+    Return(0x1F)\r
+  }\r
+  If(LEqual(CAL6, Local0))\r
+  {\r
+    Return(0x1F)\r
+  }\r
+  If(LEqual(CAL7, Local0))\r
+  {\r
+    Return(0x1F)\r
+  }\r
+  If(LEqual(CAL8, Local0))\r
+  {\r
+    Return(0x1F)\r
+  }\r
+  Return(0x1D)\r
+}\r
+\r
+Method(NDDS,1)\r
+{\r
+  Store(And(Arg0,0xF0F),Local0)\r
+\r
+  If(LEqual(0, Local0))\r
+  {\r
+    Return(0)\r
+  }\r
+  If(LEqual(NADL, Local0))\r
+  {\r
+    Return(1)\r
+  }\r
+  If(LEqual(NDL2, Local0))\r
+  {\r
+    Return(1)\r
+  }\r
+  If(LEqual(NDL3, Local0))\r
+  {\r
+    Return(1)\r
+  }\r
+  If(LEqual(NDL4, Local0))\r
+  {\r
+    Return(1)\r
+  }\r
+  If(LEqual(NDL5, Local0))\r
+  {\r
+    Return(1)\r
+  }\r
+  If(LEqual(NDL6, Local0))\r
+  {\r
+    Return(1)\r
+  }\r
+  If(LEqual(NDL7, Local0))\r
+  {\r
+    Return(1)\r
+  }\r
+  If(LEqual(NDL8, Local0))\r
+  {\r
+    Return(1)\r
+  }\r
+  Return(0)\r
+}\r
+\r
+//\r
+// Include IGD OpRegion/Software SCI interrupt handler which is use by\r
+// the graphics drivers to request data from system BIOS.\r
+//\r
+include("IgdOpRn.ASL")\r

diff --git a/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/INTELISPDev2.ASL b/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/INTELISPDev2.ASL
new file mode 100644 (file)
index 0000000..280d6cb
--- /dev/null
+++ b/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/INTELISPDev2.ASL
@@ -0,0 +1,77 @@
+/*++\r
+\r
+Copyright (c)  1999  - 2014, Intel Corporation. All rights reserved\r
+\r
+  This program and the accompanying materials are licensed and made available under\r
+  the terms and conditions of the BSD License that accompanies this distribution.\r
+  The full text of the license may be found at\r
+  http://opensource.org/licenses/bsd-license.php.\r
+\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+\r
+Module Name:\r
+\r
+  INTELISPDev2.ASL\r
+\r
+Abstract:\r
+\r
+  ISP Exist as B0D2F0 Software ACPI Reference Code for the Baytrail Family.\r
+\r
+--*/\r
+////Device ISP0\r
+Device(ISP0)\r
+{\r
+  Name(_ADR, 0x0F38)\r
+  //Name (_HID, "80860F38")\r
+  //Name (_CID, "80860F38")\r
+  Name(_DDN, "VLV2 ISP - 80860F38")\r
+  Name(_UID, 0x01)\r
+\r
+  Method (_STA, 0, NotSerialized)\r
+  {\r
+    If(LEqual(ISPD,1))   //Dev2 need report ISP0 as GFX0 child\r
+    {\r
+      Return (0xF)\r
+    }\r
+    Else\r
+    {\r
+      Return (0x0)\r
+    }\r
+  }\r
+  Name(SBUF,ResourceTemplate ()\r
+  {\r
+    Memory32Fixed (ReadWrite, 0x00000000, 0x00400000, ISP0)\r
+  })\r
+  Method(_CRS, 0x0, NotSerialized)\r
+  {\r
+    Return (SBUF)\r
+  }\r
+  Method (_SRS, 0x1, NotSerialized)\r
+  {\r
+  }\r
+  Method (_DIS, 0x0, NotSerialized)\r
+  {\r
+  }\r
+  Method(_DSM, 0x4, NotSerialized)\r
+  {\r
+    If (LEqual (Arg0, 0x01))\r
+    {\r
+      ///Switch ISP to D3H\r
+      Return (0x01)\r
+    }\r
+    Elseif (LEqual (Arg0, 0x02))\r
+    {\r
+      //Switch ISP to D0\r
+      Return (0x02)\r
+    }\r
+    Else\r
+    {\r
+      //Do nothing\r
+      Return (0x0F)\r
+    }\r
+  }\r
+} ///End ISP0\r
+\r

diff --git a/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/IgdOGBDA.ASL b/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/IgdOGBDA.ASL
new file mode 100644 (file)
index 0000000..d4e735e
--- /dev/null
+++ b/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/IgdOGBDA.ASL
@@ -0,0 +1,161 @@
+/*++\r
+\r
+Copyright (c)  1999  - 2014, Intel Corporation. All rights reserved\r
+\r
+  This program and the accompanying materials are licensed and made available under\r
+  the terms and conditions of the BSD License that accompanies this distribution.\r
+  The full text of the license may be found at\r
+  http://opensource.org/licenses/bsd-license.php.\r
+\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+\r
+Module Name:\r
+\r
+  IgdOGBDA.ASL\r
+\r
+Abstract:\r
+\r
+  IGD OpRegion/Software SCI Reference Code for the Baytrail Family.\r
+  This file contains Get BIOS Data Area funciton support for\r
+  the Integrated Graphics Device (IGD) OpRegion/Software SCI mechanism.\r
+\r
+--*/\r
+\r
+\r
+Method (GBDA, 0, Serialized)\r
+{\r
+\r
+  // Supported calls: Sub-function 0\r
+\r
+  If (LEqual(GESF, 0))\r
+  {\r
+    //<TODO> Update implementation specific supported calls.  Reference\r
+    // code is set to Intel's validated implementation.\r
+\r
+    Store(0x0000279, PARM)\r
+\r
+    Store(Zero, GESF)               // Clear the exit parameter\r
+    Return(SUCC)                    // Success\r
+  }\r
+\r
+  // Requested callbacks: Sub-function 1\r
+\r
+  If (LEqual(GESF, 1))\r
+  {\r
+\r
+    //<TODO> Update implementation specific system BIOS requested call\r
+    // back functions.  Call back functions are where the driver calls the\r
+    // system BIOS at function indicated event.\r
+\r
+    Store(0x00000240, PARM)\r
+\r
+    Store(Zero, GESF)               // Clear the exit parameter\r
+    Return(SUCC)                    // Success\r
+  }\r
+\r
+  // Get Boot display Preferences: Sub-function 4\r
+\r
+  If (LEqual(GESF, 4))\r
+  {\r
+\r
+    //<TODO> Update the implementation specific Get Boot Display\r
+    // Preferences function.\r
+\r
+    And(PARM, 0xEFFF0000, PARM)     // PARM[30:16] = Boot device ports\r
+    And(PARM, ShiftLeft(DeRefOf(Index(DBTB, IBTT)), 16), PARM)\r
+    Or(IBTT, PARM, PARM)            // PARM[7:0] = Boot device type\r
+\r
+    Store(Zero, GESF)               // Clear the exit parameter\r
+    Return(SUCC)                    // Success\r
+  }\r
+\r
+  // Panel details: Sub-function 5\r
+\r
+  If (LEqual(GESF, 5))\r
+  {\r
+\r
+    //<TODO> Update the implementation specific Get Panel Details\r
+    // function.\r
+\r
+    Store(IPSC, PARM)               // Report the scaling setting\r
+    Or(PARM, ShiftLeft(IPAT, 8), PARM)\r
+    Add(PARM, 0x100, PARM)          // Adjust panel type, 0 = VBT default\r
+    Or(PARM, ShiftLeft(LIDS, 16), PARM) // Report the lid state\r
+    Add(PARM, 0x10000, PARM)        // Adjust the lid state, 0 = Unknown\r
+    Or(PARM, ShiftLeft(IBLC, 18), PARM) // Report the BLC setting\r
+    Or(PARM, ShiftLeft(IBIA, 20), PARM) // Report the BIA setting\r
+    Store(Zero, GESF)\r
+    Return(SUCC)\r
+  }\r
+\r
+  // TV-standard/Video-connector: Sub-function 6\r
+\r
+  If (LEqual(GESF, 6))\r
+  {\r
+\r
+    //<TODO> Update the implementation specific Get\r
+    // TV-standard/Video-connectorPanel function.\r
+\r
+    Store(ITVF, PARM)\r
+    Or(PARM, ShiftLeft(ITVM, 4), PARM)\r
+    Store(Zero, GESF)\r
+    Return(SUCC)\r
+  }\r
+\r
+  // Internal graphics: Sub-function 7\r
+\r
+  If (LEqual(GESF, 7))\r
+  {\r
+    Store(GIVD, PARM)               // PARM[0]      - VGA mode(1=VGA)\r
+    Xor(PARM, 1, PARM)              // Invert the VGA mode polarity\r
+    Or(PARM, ShiftLeft(GMFN, 1), PARM) // PARM[1]   - # IGD PCI functions-1\r
+    // PARM[3:2]    - Reserved\r
+    // PARM[4]      - IGD D3 support(0=cold)\r
+    // PARM[10:5]   - Reserved\r
+    Or(PARM, ShiftLeft(3, 11), PARM) // PARM[12:11] - DVMT mode(11b = 5.0)\r
+\r
+    //\r
+    // Report DVMT 5.0 Total Graphics memory size.\r
+    //\r
+    Or(PARM, ShiftLeft(IDMS, 17), PARM)   // Bits 20:17 are for Gfx total memory size\r
+\r
+    // If the "Set Internal Graphics" call is supported, the modified\r
+    // settings flag must be programmed per the specification.  This means\r
+    // that the flag must be set to indicate that system BIOS requests\r
+    // these settings.  Once "Set Internal Graphics" is called, the\r
+    //  modified settings flag must be cleared on all subsequent calls to\r
+    // this function.\r
+\r
+    // Report the graphics frequency based on DISPLAY_CLOCK_FREQUENCY_ENCODING [MMADR+0x20C8]\r
+\r
+    Or(ShiftLeft(Derefof(Index(CDCT, \_SB.PCI0.GFX0.MCHK.DCFE)), 21),PARM, PARM)\r
+\r
+    Store(1, GESF)                  // Set the modified settings flag\r
+    Return(SUCC)\r
+  }\r
+\r
+  // Spread spectrum clocks: Sub-function 10\r
+\r
+  If (LEqual(GESF, 10))\r
+  {\r
+\r
+    Store(0, PARM)                  // Assume SSC is disabled\r
+\r
+    If(ISSC)\r
+    {\r
+      Or(PARM, 3, PARM)       // If SSC enabled, return SSC1+Enabled\r
+    }\r
+\r
+    Store(0, GESF)                  // Set the modified settings flag\r
+    Return(SUCC)                    // Success\r
+  }\r
+\r
+\r
+  // A call to a reserved "Get BIOS data" function was received.\r
+\r
+  Store(Zero, GESF)                     // Clear the exit parameter\r
+  Return(CRIT)                          // Reserved, "Critical failure"\r
+}\r

diff --git a/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/IgdOMOBF.ASL b/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/IgdOMOBF.ASL
new file mode 100644 (file)
index 0000000..927e43d
--- /dev/null
+++ b/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/IgdOMOBF.ASL
@@ -0,0 +1,491 @@
+/*++\r
+\r
+Copyright (c)  1999  - 2014, Intel Corporation. All rights reserved\r
+\r
+  This program and the accompanying materials are licensed and made available under\r
+  the terms and conditions of the BSD License that accompanies this distribution.\r
+  The full text of the license may be found at\r
+  http://opensource.org/licenses/bsd-license.php.\r
+\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+\r
+Module Name:\r
+\r
+  IgdOMOBF.ASL\r
+\r
+Abstract:\r
+\r
+  IGD OpRegion/Software SCI Reference Code for the Baytrail Family.\r
+  This file contains ASL code with the purpose of handling events\r
+  i.e. hotkeys and other system interrupts.\r
+\r
+--*/\r
+\r
+\r
+// Notes:\r
+// 1. The following routines are to be called from the appropriate event\r
+//    handlers.\r
+// 2. This code cannot comprehend the exact implementation in the OEM's BIOS.\r
+//    Therefore, an OEM must call these methods from the existing event\r
+//    handler infrastructure.  Details on when/why to call each method is\r
+//    included in the method header under the "usage" section.\r
+\r
+\r
+/************************************************************************;\r
+;* ACPI Notification Methods\r
+;************************************************************************/\r
+\r
+\r
+/************************************************************************;\r
+;*\r
+;* Name:        PDRD\r
+;*\r
+;* Description: Check if the graphics driver is ready to process\r
+;*              notifications and video extensions.\r
+;*\r
+;* Usage:       This method is to be called prior to performing any\r
+;*              notifications or handling video extensions.\r
+;*              Ex: If (PDRD()) {Return (FAIL)}\r
+;*\r
+;* Input:       None\r
+;*\r
+;* Output:      None\r
+;*\r
+;* References:  DRDY (Driver ready status), ASLP (Driver recommended\r
+;*              sleep timeout value).\r
+;*\r
+;************************************************************************/\r
+\r
+Method(PDRD)\r
+{\r
+  If(LNot(DRDY))\r
+  {\r
+\r
+    // Sleep for ASLP milliseconds if the driver is not ready.\r
+\r
+    Sleep(ASLP)\r
+  }\r
+\r
+  // If DRDY is clear, the driver is not ready.  If the return value is\r
+  // !=0, do not perform any notifications or video extension handling.\r
+\r
+  Return(LNot(DRDY))\r
+}\r
+\r
+\r
+/************************************************************************;\r
+;*\r
+;* Name:        PSTS\r
+;*\r
+;* Description: Check if the graphics driver has completed the previous\r
+;*              "notify" command.\r
+;*\r
+;* Usage:       This method is called before every "notify" command.  A\r
+;*              "notify" should only be set if the driver has completed the\r
+;*              previous command.  Else, ignore the event and exit the parent\r
+;*              method.\r
+;*              Ex: If (PSTS()) {Return (FAIL)}\r
+;*\r
+;* Input:       None\r
+;*\r
+;* Output:      None\r
+;*\r
+;* References:  CSTS (Notification status), ASLP (Driver recommended sleep\r
+;*              timeout value).\r
+;*\r
+;************************************************************************/\r
+\r
+Method(PSTS)\r
+{\r
+  If(LGreater(CSTS, 2))\r
+  {\r
+    // Sleep for ASLP milliseconds if the status is not "success,\r
+    // failure, or pending"\r
+    //\r
+    Sleep(ASLP)\r
+  }\r
+\r
+  Return(LEqual(CSTS, 3))         // Return True if still Dispatched\r
+}\r
+\r
+\r
+/************************************************************************;\r
+;*\r
+;* Name:        GNOT\r
+;*\r
+;* Description: Call the appropriate methods to query the graphics driver\r
+;*              status.  If all methods return success, do a notification of\r
+;*              the graphics device.\r
+;*\r
+;* Usage:       This method is to be called when a graphics device\r
+;*              notification is required (display switch hotkey, etc).\r
+;*\r
+;* Input:       Arg0 = Current event type:\r
+;*                      1 = display switch\r
+;*                      2 = lid\r
+;*                      3 = dock\r
+;*              Arg1 = Notification type:\r
+;*                      0 = Re-enumeration\r
+;*                      0x80 = Display switch\r
+;*\r
+;* Output:      Returns 0 = success, 1 = failure\r
+;*\r
+;* References:  PDRD and PSTS methods.  OSYS (OS version)\r
+;*\r
+;************************************************************************/\r
+\r
+Method(GNOT, 2)\r
+{\r
+  // Check for 1. Driver loaded, 2. Driver ready.\r
+  // If any of these cases is not met, skip this event and return failure.\r
+  //\r
+  If(PDRD())\r
+  {\r
+    Return(0x1)             // Return failure if driver not loaded.\r
+  }\r
+\r
+  Store(Arg0, CEVT)               // Set up the current event value\r
+  Store(3, CSTS)                  // CSTS=BIOS dispatched an event\r
+\r
+  If(LAnd(LEqual(CHPD, 0), LEqual(Arg1, 0)))      // Do not re-enum if driver supports hotplug\r
+  {\r
+    If(LOr(LGreater(OSYS, 2000), LLess(OSYS, 2006)))\r
+    {\r
+      //\r
+      // WINXP requires that the entire PCI Bridge be re-enumerated.\r
+      //\r
+      Notify(\_SB.PCI0, Arg1)\r
+    }\r
+    Else\r
+    {\r
+      //\r
+      // Re-enumerate the Graphics Device for non-XP operating systems.\r
+      //\r
+      Notify(\_SB.PCI0.GFX0, Arg1)\r
+    }\r
+  }\r
+\r
+  Notify(\_SB.PCI0.GFX0,0x80)\r
+\r
+\r
+  Return(0x0)                     // Return success\r
+}\r
+\r
+\r
+/************************************************************************;\r
+;*\r
+;* Name:        GHDS\r
+;*\r
+;* Description: Handle a hotkey display switching event (performs a\r
+;*              Notify(GFX0, 0).\r
+;*\r
+;* Usage:       This method must be called when a hotkey event occurs and the\r
+;*              purpose of that hotkey is to do a display switch.\r
+;*\r
+;* Input:       Arg0 = Toggle table number.\r
+;*\r
+;* Output:      Returns 0 = success, 1 = failure.\r
+;*              CEVT and TIDX are indirect outputs.\r
+;*\r
+;* References:  TIDX, GNOT\r
+;*\r
+;************************************************************************/\r
+\r
+Method(GHDS, 1)\r
+{\r
+  Store(Arg0, TIDX)               // Store the table number\r
+\r
+  // Call GNOT for CEVT = 1 = hotkey, notify value = 0\r
+\r
+  Return(GNOT(1, 0))              // Return stats from GNOT\r
+}\r
+\r
+\r
+/************************************************************************;\r
+;*\r
+;* Name:        GLID\r
+;*\r
+;* Description: Handle a lid event (performs the Notify(GFX0, 0), but not the\r
+;*              lid notify).\r
+;*\r
+;* Usage:       This method must be called when a lid event occurs.  A\r
+;*              Notify(LID0, 0x80) must follow the call to this method.\r
+;*\r
+;* Input:       Arg0 = Lid state:\r
+;*                      0 = All closed\r
+;*                      1 = internal LFP lid open\r
+;*                      2 = external lid open\r
+;*                      3 = both external and internal open\r
+;*\r
+;* Output:      Returns 0=success, 1=failure.\r
+;*              CLID and CEVT are indirect outputs.\r
+;*\r
+;* References:  CLID, GNOT\r
+;*\r
+;************************************************************************/\r
+\r
+Method(GLID, 1)\r
+{\r
+  Store(Arg0, CLID)               // Store the current lid state\r
+\r
+  // Call GNOT for CEVT=2=Lid, notify value = 0\r
+\r
+  Return(GNOT(2, 0))              // Return stats from GNOT\r
+}\r
+\r
+\r
+/************************************************************************;\r
+;*\r
+;* Name:        GDCK\r
+;*\r
+;* Description: Handle a docking event by updating the current docking status\r
+;*              and doing a notification.\r
+;*\r
+;* Usage:       This method must be called when a docking event occurs.\r
+;*\r
+;* Input:       Arg0 = Docking state:\r
+;*                      0 = Undocked\r
+;*                      1 = Docked\r
+;*\r
+;* Output:      Returns 0=success, 1=failure.\r
+;*              CDCK and CEVT are indirect outputs.\r
+;*\r
+;* References:  CDCK, GNOT\r
+;*\r
+;************************************************************************/\r
+\r
+Method(GDCK, 1)\r
+{\r
+  Store(Arg0, CDCK)               // Store the current dock state\r
+\r
+  // Call GNOT for CEVT=4=Dock, notify value = 0\r
+\r
+  Return(GNOT(4, 0))              // Return stats from GNOT\r
+}\r
+\r
+\r
+/************************************************************************;\r
+;* ASLE Interrupt Methods\r
+;************************************************************************/\r
+\r
+\r
+/************************************************************************;\r
+;*\r
+;* Name:        PARD\r
+;*\r
+;* Description: Check if the driver is ready to handle ASLE interrupts\r
+;*              generate by the system BIOS.\r
+;*\r
+;* Usage:       This method must be called before generating each ASLE\r
+;*              interrupt.\r
+;*\r
+;* Input:       None\r
+;*\r
+;* Output:      Returns 0 = success, 1 = failure.\r
+;*\r
+;* References:  ARDY (Driver readiness), ASLP (Driver recommended sleep\r
+;*              timeout value)\r
+;*\r
+;************************************************************************/\r
+\r
+Method(PARD)\r
+{\r
+  If(LNot(ARDY))\r
+  {\r
+\r
+    // Sleep for ASLP milliseconds if the driver is not ready.\r
+\r
+    Sleep(ASLP)\r
+  }\r
+\r
+  // If ARDY is clear, the driver is not ready.  If the return value is\r
+  // !=0, do not generate the ASLE interrupt.\r
+\r
+  Return(LNot(ARDY))\r
+}\r
+\r
+\r
+/************************************************************************;\r
+;*\r
+;* Name:        AINT\r
+;*\r
+;* Description: Call the appropriate methods to generate an ASLE interrupt.\r
+;*              This process includes ensuring the graphics driver is ready\r
+;*              to process the interrupt, ensuring the driver supports the\r
+;*              interrupt of interest, and passing information about the event\r
+;*              to the graphics driver.\r
+;*\r
+;* Usage:       This method must called to generate an ASLE interrupt.\r
+;*\r
+;* Input:       Arg0 = ASLE command function code:\r
+;*                      0 = Set ALS illuminance\r
+;*                      1 = Set backlight brightness\r
+;*                      2 = Do Panel Fitting\r
+;*              Arg1 = If Arg0 = 0, current ALS reading:\r
+;*                      0 = Reading below sensor range\r
+;*                      1-0xFFFE = Current sensor reading\r
+;*                      0xFFFF = Reading above sensor range\r
+;*              Arg1 = If Arg0 = 1, requested backlight percentage\r
+;*\r
+;* Output:      Returns 0 = success, 1 = failure\r
+;*\r
+;* References:  PARD method.\r
+;*\r
+;************************************************************************/\r
+\r
+Method(AINT, 2)\r
+{\r
+\r
+  // Return failure if the requested feature is not supported by the\r
+  // driver.\r
+\r
+  If(LNot(And(TCHE, ShiftLeft(1, Arg0))))\r
+  {\r
+    Return(0x1)\r
+  }\r
+\r
+  // Return failure if the driver is not ready to handle an ASLE\r
+  // interrupt.\r
+\r
+  If(PARD())\r
+  {\r
+    Return(0x1)\r
+  }\r
+\r
+  // Evaluate the first argument (Panel fitting, backlight brightness, or ALS).\r
+\r
+  If(LEqual(Arg0, 2))             // Arg0 = 2, so request a panel fitting mode change.\r
+  {\r
+    If(CPFM)                                        // If current mode field is non-zero use it.\r
+    {\r
+      And(CPFM, 0x0F, Local0)                 // Create variables without reserved\r
+      And(EPFM, 0x0F, Local1)                 // or valid bits.\r
+\r
+      If(LEqual(Local0, 1))                   // If current mode is centered,\r
+      {\r
+        If(And(Local1, 6))              // and if stretched is enabled,\r
+        {\r
+          Store(6, PFIT)          // request stretched.\r
+        }\r
+        Else                            // Otherwise,\r
+        {\r
+          If(And(Local1, 8))      // if aspect ratio is enabled,\r
+          {\r
+            Store(8, PFIT)  // request aspect ratio.\r
+          }\r
+          Else                    // Only centered mode is enabled\r
+          {\r
+            Store(1, PFIT)  // so request centered. (No change.)\r
+          }\r
+        }\r
+      }\r
+      If(LEqual(Local0, 6))                   // If current mode is stretched,\r
+      {\r
+        If(And(Local1, 8))              // and if aspect ratio is enabled,\r
+        {\r
+          Store(8, PFIT)          // request aspect ratio.\r
+        }\r
+        Else                            // Otherwise,\r
+        {\r
+          If(And(Local1, 1))      // if centered is enabled,\r
+          {\r
+            Store(1, PFIT)  // request centered.\r
+          }\r
+          Else                    // Only stretched mode is enabled\r
+          {\r
+            Store(6, PFIT)  // so request stretched. (No change.)\r
+          }\r
+        }\r
+      }\r
+      If(LEqual(Local0, 8))                   // If current mode is aspect ratio,\r
+      {\r
+        If(And(Local1, 1))              // and if centered is enabled,\r
+        {\r
+          Store(1, PFIT)          // request centered.\r
+        }\r
+        Else                            // Otherwise,\r
+        {\r
+          If(And(Local1, 6))      // if stretched is enabled,\r
+          {\r
+            Store(6, PFIT)  // request stretched.\r
+          }\r
+          Else                    // Only aspect ratio mode is enabled\r
+          {\r
+            Store(8, PFIT)  // so request aspect ratio. (No change.)\r
+          }\r
+        }\r
+      }\r
+    }\r
+\r
+    // The following code for panel fitting (within the Else condition) is retained for backward compatiblity.\r
+\r
+    Else                            // If CFPM field is zero use PFIT and toggle the\r
+    {\r
+      Xor(PFIT,7,PFIT)        // mode setting between stretched and centered only.\r
+    }\r
+\r
+    Or(PFIT,0x80000000,PFIT)        // Set the valid bit for all cases.\r
+\r
+    Store(4, ASLC)                  // Store "Panel fitting event" to ASLC[31:1]\r
+  }\r
+  Else\r
+  {\r
+    If(LEqual(Arg0, 1))             // Arg0=1, so set the backlight brightness.\r
+    {\r
+      Store(Divide(Multiply(Arg1, 255), 100), BCLP) // Convert from percent to 0-255.\r
+\r
+      Or(BCLP, 0x80000000, BCLP)      // Set the valid bit.\r
+\r
+      Store(2, ASLC)                  // Store "Backlight control event" to ASLC[31:1]\r
+    }\r
+    Else\r
+    {\r
+      If(LEqual(Arg0, 0))             // Arg0=0, so set the ALS illuminace\r
+      {\r
+        Store(Arg1, ALSI)\r
+\r
+        Store(1, ASLC)          // Store "ALS event" to ASLC[31:1]\r
+      }\r
+      Else\r
+      {\r
+        Return(0x1) // Unsupported function\r
+      }\r
+    }\r
+  }\r
+\r
+  Store(0x01, ASLE)               // Generate ASLE interrupt\r
+  Return(0x0)                     // Return success\r
+}\r
+\r
+\r
+/************************************************************************;\r
+;*\r
+;* Name:        SCIP\r
+;*\r
+;* Description: Checks the presence of the OpRegion and SCI\r
+;*\r
+;* Usage:       This method is called before other OpRegion methods. The\r
+;*              former "GSMI True/False is not always valid.  This method\r
+;*              checks if the OpRegion Version is non-zero and if non-zero,\r
+;*              (present and readable) then checks the GSMI flag.\r
+;*\r
+;* Input:       None\r
+;*\r
+;* Output:      Boolean True = SCI present.\r
+;*\r
+;* References:  None\r
+;*\r
+;************************************************************************/\r
+\r
+Method(SCIP)\r
+{\r
+  If(LNotEqual(OVER,0))           // If OpRegion Version not 0.\r
+  {\r
+    Return(LNot(GSMI))      // Return True if SCI.\r
+  }\r
+\r
+  Return(0)                       // Else Return False.\r
+}\r

diff --git a/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/IgdOSBCB.ASL b/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/IgdOSBCB.ASL
new file mode 100644 (file)
index 0000000..418329d
--- /dev/null
+++ b/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/IgdOSBCB.ASL
@@ -0,0 +1,280 @@
+/*++\r
+\r
+Copyright (c)  1999  - 2014, Intel Corporation. All rights reserved\r
+\r
+  This program and the accompanying materials are licensed and made available under\r
+  the terms and conditions of the BSD License that accompanies this distribution.\r
+  The full text of the license may be found at\r
+  http://opensource.org/licenses/bsd-license.php.\r
+\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+\r
+Module Name:\r
+\r
+  IgdOSBCB.ASL\r
+\r
+Abstract:\r
+\r
+  IGD OpRegion/Software SCI Reference Code for the Baytrail Family.\r
+  This file contains the system BIOS call back functionality for the\r
+  OpRegion/Software SCI mechanism.\r
+\r
+--*/\r
+\r
+\r
+Method (SBCB, 0, Serialized)\r
+{\r
+\r
+  // Supported Callbacks: Sub-function 0\r
+\r
+  If (LEqual(GESF, 0x0))\r
+  {\r
+\r
+    //<TODO> An OEM may support the driver->SBIOS status callbacks, but\r
+    // the supported callbacks value must be modified.  The code that is\r
+    // executed upon reception of the callbacks must be also be updated\r
+    // to perform the desired functionality.\r
+\r
+    Store(0x00000000, PARM)         // No callbacks supported\r
+\r
+    If(LEqual(PFLV,FMBL))\r
+    {\r
+      Store(0x000F87FD, PARM)         // Mobile\r
+    }\r
+    If(LEqual(PFLV,FDTP))\r
+    {\r
+      Store(0x000F87BD, PARM)         // Desktop\r
+    }\r
+\r
+    Store(Zero, GESF)               // Clear the exit parameter\r
+    Return(SUCC)                    // "Success"\r
+  }\r
+\r
+  // BIOS POST Completion: Sub-function 1\r
+\r
+  If (LEqual(GESF, 1))\r
+  {\r
+    Store(Zero, GESF)               // Clear the exit parameter\r
+    Store(Zero, PARM)\r
+    Return(SUCC)                    // Not supported, but no failure\r
+  }\r
+\r
+  // Pre-Hires Set Mode: Sub-function 3\r
+\r
+  If (LEqual(GESF, 3))\r
+  {\r
+    Store(Zero, GESF)               // Clear the exit parameter\r
+    Store(Zero, PARM)\r
+    Return(SUCC)                    // Not supported, but no failure\r
+  }\r
+\r
+  // Post-Hires Set Mode: Sub-function 4\r
+\r
+  If (LEqual(GESF, 4))\r
+  {\r
+    Store(Zero, GESF)               // Clear the exit parameter\r
+    Store(Zero, PARM)\r
+    Return(SUCC)                    // Not supported, but no failure\r
+  }\r
+\r
+  // Display Switch: Sub-function 5\r
+\r
+  If (LEqual(GESF, 5))\r
+  {\r
+    Store(Zero, GESF)               // Clear the exit parameter\r
+    Store(Zero, PARM)\r
+    Return(SUCC)                    // Not supported, but no failure\r
+  }\r
+\r
+  // Set TV format: Sub-function 6\r
+\r
+  If (LEqual(GESF, 6))\r
+  {\r
+\r
+    //<TODO> If implemented, the input values must be saved into\r
+    // non-volatile storage for parsing during the next boot.  The\r
+    // following Sample code is Intel validated implementation.\r
+\r
+    Store(And(PARM, 0x0F), ITVF)\r
+    Store(ShiftRight(And(PARM, 0xF0), 4), ITVM)\r
+    Store(Zero, GESF)               // Clear the exit parameter\r
+    Store(Zero, PARM)\r
+    Return(SUCC)\r
+  }\r
+\r
+  // Adapter Power State: Sub-function 7\r
+\r
+  If (LEqual(GESF, 7))\r
+  {\r
+\r
+    // Upon notification from driver that the Adapter Power State = D0,\r
+    // check if previous lid event failed.  If it did, retry the lid\r
+    // event here.\r
+    If(LEqual(PARM, 0))\r
+    {\r
+      Store(CLID, Local0)\r
+      If(And(0x80000000,Local0))\r
+      {\r
+        And(CLID, 0x0000000F, CLID)\r
+        GLID(CLID)\r
+      }\r
+    }\r
+    Store(Zero, GESF)               // Clear the exit parameter\r
+    Store(Zero, PARM)\r
+    Return(SUCC)                    // Not supported, but no failure\r
+  }\r
+\r
+  // Display Power State: Sub-function 8\r
+\r
+  If (LEqual(GESF, 8))\r
+  {\r
+    Store(Zero, GESF)               // Clear the exit parameter\r
+    Store(Zero, PARM)\r
+    Return(SUCC)                    // Not supported, but no failure\r
+  }\r
+\r
+  // Set Boot Display: Sub-function 9\r
+\r
+  If (LEqual(GESF, 9))\r
+  {\r
+\r
+    //<TODO> An OEM may elect to implement this method.  In that case,\r
+    // the input values must be saved into non-volatile storage for\r
+    // parsing during the next boot.  The following Sample code is Intel\r
+    // validated implementation.\r
+\r
+    And(PARM, 0xFF, IBTT)           // Save the boot display to NVS\r
+    Store(Zero, GESF)               // Clear the exit parameter\r
+    Store(Zero, PARM)\r
+    Return(SUCC)                    // Reserved, "Critical failure"\r
+  }\r
+\r
+  // Set Panel Details: Sub-function 10 (0Ah)\r
+\r
+  If (LEqual(GESF, 10))\r
+  {\r
+\r
+    //<TODO> An OEM may elect to implement this method.  In that case,\r
+    // the input values must be saved into non-volatile storage for\r
+    // parsing during the next boot.  The following Sample code is Intel\r
+    // validated implementation.\r
+\r
+    // Set the panel-related NVRAM variables based the input from the driver.\r
+\r
+    And(PARM, 0xFF, IPSC)\r
+\r
+    // Change panel type if a change is requested by the driver (Change if\r
+    // panel type input is non-zero).  Zero=No change requested.\r
+\r
+    If(And(ShiftRight(PARM, 8), 0xFF))\r
+    {\r
+      And(ShiftRight(PARM, 8), 0xFF, IPAT)\r
+      Decrement(IPAT)         // 0 = no change, so fit to CMOS map\r
+    }\r
+    And(ShiftRight(PARM, 18), 0x3, IBLC)\r
+    And(ShiftRight(PARM, 20), 0x7, IBIA)\r
+    Store(Zero, GESF)               // Clear the exit parameter\r
+    Store(Zero, PARM)\r
+    Return(SUCC)                    // Success\r
+  }\r
+\r
+  // Set Internal Graphics: Sub-function 11 (0Bh)\r
+\r
+  If (LEqual(GESF, 11))\r
+  {\r
+\r
+    //<TODO> An OEM may elect to implement this method.  In that case,\r
+    // the input values must be saved into non-volatile storage for\r
+    // parsing during the next boot.  The following Sample code is Intel\r
+    // validated implementation.\r
+\r
+    And(ShiftRight(PARM, 1), 1, IF1E) // Program the function 1 option\r
+\r
+    // Fixed memory/DVMT memory\r
+\r
+    And(ShiftRight(PARM, 17), 0xF, IDMS) // Program DVMT/fixed memory size\r
+\r
+    Store(Zero, GESF)               // Clear the exit parameter\r
+    Store(Zero, PARM)\r
+    Return(SUCC)                    // Success\r
+  }\r
+\r
+  // Post-Hires to DOS FS: Sub-function 16 (10h)\r
+\r
+  If (LEqual(GESF, 16))\r
+  {\r
+    Store(Zero, GESF)               // Clear the exit parameter\r
+    Store(Zero, PARM)\r
+    Return(SUCC)                    // Not supported, but no failure\r
+  }\r
+\r
+  // APM Complete:  Sub-function 17 (11h)\r
+\r
+  If (LEqual(GESF, 17))\r
+  {\r
+\r
+    Store(ShiftLeft(LIDS, 8), PARM) // Report the lid state\r
+    Add(PARM, 0x100, PARM)          // Adjust the lid state, 0 = Unknown\r
+\r
+    Store(Zero, GESF)               // Clear the exit parameter\r
+    Return(SUCC)                    // Not supported, but no failure\r
+  }\r
+\r
+  // Set Spread Spectrum Clocks: Sub-function 18 (12h)\r
+\r
+  If (LEqual(GESF, 18))\r
+  {\r
+\r
+    //<TODO> An OEM may elect to implement this method.  In that case,\r
+    // the input values must be saved into non-volatile storage for\r
+    // parsing during the next boot.  The following Sample code is Intel\r
+    // validated implementation.\r
+\r
+    If(And(PARM, 1))\r
+    {\r
+      If(LEqual(ShiftRight(PARM, 1), 1))\r
+      {\r
+        Store(1, ISSC)  // Enable HW SSC, only for clock 1\r
+      }\r
+      Else\r
+      {\r
+        Store(Zero, GESF)\r
+        Return(CRIT)    // Failure, as the SSC clock must be 1\r
+      }\r
+    }\r
+    Else\r
+    {\r
+      Store(0, ISSC)          // Disable SSC\r
+    }\r
+    Store(Zero, GESF)               // Clear the exit parameter\r
+    Store(Zero, PARM)\r
+    Return(SUCC)                    // Success\r
+  }\r
+\r
+  // Post VBE/PM Callback: Sub-function 19 (13h)\r
+\r
+  If (LEqual(GESF, 19))\r
+  {\r
+    Store(Zero, GESF)               // Clear the exit parameter\r
+    Store(Zero, PARM)\r
+    Return(SUCC)                    // Not supported, but no failure\r
+  }\r
+\r
+  // Set PAVP Data: Sub-function 20 (14h)\r
+\r
+  If (LEqual(GESF, 20))\r
+  {\r
+    And(PARM, 0xF, PAVP)    // Store PAVP info\r
+    Store(Zero, GESF)               // Clear the exit parameter\r
+    Store(Zero, PARM)\r
+    Return(SUCC)                    // Success\r
+  }\r
+\r
+  // A call to a reserved "System BIOS callbacks" function was received\r
+\r
+  Store(Zero, GESF)                     // Clear the exit parameter\r
+  Return(SUCC)                          // Reserved, "Critical failure"\r
+}\r

diff --git a/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/IgdOpRn.ASL b/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/IgdOpRn.ASL
new file mode 100644 (file)
index 0000000..65190af
--- /dev/null
+++ b/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/IgdOpRn.ASL
@@ -0,0 +1,305 @@
+/*++\r
+\r
+Copyright (c)  1999  - 2014, Intel Corporation. All rights reserved\r
+\r
+  This program and the accompanying materials are licensed and made available under\r
+  the terms and conditions of the BSD License that accompanies this distribution.\r
+  The full text of the license may be found at\r
+  http://opensource.org/licenses/bsd-license.php.\r
+\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+\r
+Module Name:\r
+\r
+  IgdOpRn.ASL\r
+\r
+Abstract:\r
+\r
+  IGD OpRegion/Software SCI Reference Code for the Baytrail Family.\r
+  This file contains the interrupt handler code for the Integrated\r
+  Graphics Device (IGD) OpRegion/Software SCI mechanism.\r
+\r
+--*/\r
+\r
+\r
+//NOTES:\r
+//\r
+// (1)  The code contained in this file inherits the scope in which it\r
+//      was included.  So BIOS developers must be sure to include this\r
+//      file in the scope associated with the graphics device\r
+//      (ex. \_SB.PCI0.GFX0).\r
+// (2)  Create a _L06 method under the GPE scope to handle the event\r
+//      generated by the graphics driver.  The _L06 method must call\r
+//      the GSCI method in this file.\r
+// (3)  The MCHP operation region assumes that _ADR and _BBN names\r
+//      corresponding to bus 0, device0, function 0 have been declared\r
+//      under the PCI0 scope.\r
+// (4)  Before the first execution of the GSCI method, the base address\r
+//      of the GMCH SCI OpRegion must be programmed where the driver can\r
+//      access it. A 32bit scratch register at 0xFC in the IGD PCI\r
+//      configuration space (B0/D2/F0/R0FCh) is used for this purpose.\r
+\r
+//  Define an OperationRegion to cover the GMCH PCI configuration space as\r
+//  described in the IGD OpRegion specificiation.\r
+\r
+//  Define an OperationRegion to cover the IGD PCI configuration space as\r
+//  described in the IGD OpRegion specificiation.\r
+\r
+OperationRegion(IGDP, PCI_Config,0x00,0x100)\r
+Field(IGDP, AnyAcc, NoLock, Preserve)\r
+{\r
+  Offset(0x10),  // GTTMMADR\r
+  MADR,   32,\r
+  Offset(0x50),  // GMCH Graphics Control Register\r
+  ,   1,\r
+  GIVD,   1,     // IGD VGA disable bit\r
+  ,   1,\r
+  GUMA,   5,     // Stolen memory size\r
+  ,   8,\r
+  Offset(0x54),\r
+  ,   4,\r
+  GMFN,   1,     // Gfx function 1 enable\r
+  ,   27,\r
+  Offset(0x5C),  // Stolen Memory Base Address\r
+  GSTM,   32,\r
+  Offset(0xE0),  // Reg 0xE8, SWSCI control register\r
+  GSSE,   1,     // Graphics SCI event (1=event pending)\r
+  GSSB,   14,    // Graphics SCI scratchpad bits\r
+  GSES,   1,     // Graphics event select (1=SCI)\r
+  Offset(0xE4),\r
+  ASLE,   8,     // Reg 0xE4, ASLE interrupt register\r
+  ,   24,    // Only use first byte of ASLE reg\r
+  Offset(0xFC),\r
+  ASLS,   32,    // Reg 0xFC, Address of the IGD OpRegion\r
+}\r
+\r
+Method (MCHK, 0, Serialized)\r
+{\r
+\r
+  If (LNotEqual (MADR, 0xFFFFFFFF))\r
+  {\r
+    OperationRegion(IGMM,SystemMemory,MADR,0x3000)\r
+    Field(IGMM,AnyAcc, NoLock, Preserve)\r
+    {\r
+      Offset(0X20C8),\r
+      ,    4,\r
+      DCFE,    4,                     // DISPLAY_CLOCK_FREQUENCY_ENCODING\r
+    }\r
+  }\r
+}\r
+\r
+\r
+//  Define an OperationRegion to cover the IGD OpRegion layout.\r
+\r
+OperationRegion(IGDM, SystemMemory, ASLB, 0x2000)\r
+Field(IGDM, AnyAcc, NoLock, Preserve)\r
+{\r
+\r
+  // OpRegion Header\r
+\r
+  SIGN,   128,                    // Signature-"IntelGraphicsMem"\r
+  SIZE,   32,                     // OpRegion Size\r
+  OVER,   32,                     // OpRegion Version\r
+  SVER,   256,                    // System BIOS Version\r
+  VVER,   128,                    // VBIOS Version\r
+  GVER,   128,                    // Driver version\r
+  MBOX,   32,                     // Mailboxes supported\r
+  DMOD,   32,                     // Driver Model\r
+  PCON,   32,                     // 96, Platform Configuration\r
+\r
+  // OpRegion Mailbox 1 (Public ACPI Methods)\r
+  // Note: Mailbox 1 is normally reserved for desktop platforms.\r
+\r
+  Offset(0x100),\r
+  DRDY,   32,                     // Driver readiness (ACPI notification)\r
+  CSTS,   32,                     // Notification status\r
+  CEVT,   32,                     // Current event\r
+  Offset(0x120),\r
+  DIDL,   32,                     // Supported display device ID list\r
+  DDL2,   32,                     // Allows for 8 devices\r
+  DDL3,   32,\r
+  DDL4,   32,\r
+  DDL5,   32,\r
+  DDL6,   32,\r
+  DDL7,   32,\r
+  DDL8,   32,\r
+  CPDL,   32,                     // Currently present display list\r
+  CPL2,   32,                     // Allows for 8 devices\r
+  CPL3,   32,\r
+  CPL4,   32,\r
+  CPL5,   32,\r
+  CPL6,   32,\r
+  CPL7,   32,\r
+  CPL8,   32,\r
+  CAD1,   32,                     // Currently active display list\r
+  CAL2,   32,                     // Allows for 8 devices\r
+  CAL3,   32,\r
+  CAL4,   32,\r
+  CAL5,   32,\r
+  CAL6,   32,\r
+  CAL7,   32,\r
+  CAL8,   32,\r
+  NADL,   32,                     // Next active display list\r
+  NDL2,   32,                     // Allows for 8 devices\r
+  NDL3,   32,\r
+  NDL4,   32,\r
+  NDL5,   32,\r
+  NDL6,   32,\r
+  NDL7,   32,\r
+  NDL8,   32,\r
+  ASLP,   32,                     // ASL sleep timeout\r
+  TIDX,   32,                     // Toggle table index\r
+  CHPD,   32,                     // Current hot plug enable indicator\r
+  CLID,   32,                     // Current lid state indicator\r
+  CDCK,   32,                     // Current docking state indicator\r
+  SXSW,   32,                     // Display switch notify on resume\r
+  EVTS,   32,                     // Events supported by ASL (diag only)\r
+  CNOT,   32,                     // Current OS notifications (diag only)\r
+  NRDY,   32,\r
+\r
+  // OpRegion Mailbox 2 (Software SCI Interface)\r
+\r
+  Offset(0x200),                  // SCIC\r
+  SCIE,   1,                      // SCI entry bit (1=call unserviced)\r
+  GEFC,   4,                      // Entry function code\r
+  GXFC,   3,                      // Exit result\r
+  GESF,   8,                      // Entry/exit sub-function/parameter\r
+  ,   16,                     // SCIC[31:16] reserved\r
+  Offset(0x204),                  // PARM\r
+  PARM,   32,                     // PARM register (extra parameters)\r
+  DSLP,   32,                     // Driver sleep time out\r
+\r
+  // OpRegion Mailbox 3 (BIOS to Driver Notification)\r
+  // Note: Mailbox 3 is normally reserved for desktop platforms.\r
+\r
+  Offset(0x300),\r
+  ARDY,   32,                     // Driver readiness (power conservation)\r
+  ASLC,   32,                     // ASLE interrupt command/status\r
+  TCHE,   32,                     // Technology enabled indicator\r
+  ALSI,   32,                     // Current ALS illuminance reading\r
+  BCLP,   32,                     // Backlight brightness\r
+  PFIT,   32,                     // Panel fitting state or request\r
+  CBLV,   32,                     // Current brightness level\r
+  BCLM,   320,                    // Backlight brightness level duty cycle mapping table\r
+  CPFM,   32,                     // Current panel fitting mode\r
+  EPFM,   32,                     // Enabled panel fitting modes\r
+  PLUT,   592,                    // Optional. 74-byte Panel LUT Table\r
+  PFMB,   32,                     // Optional. PWM Frequency and Minimum Brightness\r
+  CCDV,   32,                     // Optional. Gamma, Brightness, Contrast values.\r
+  PCFT,   32,                     // Optional. Power Conservation Features\r
+\r
+  Offset(0x3B6),\r
+  STAT,   32,                     // Status register\r
+\r
+  // OpRegion Mailbox 4 (VBT)\r
+\r
+  Offset(0x400),\r
+  GVD1,   0xC000,                 // 6K bytes maximum VBT image\r
+\r
+  // OpRegion Mailbox 5 (BIOS to Driver Notification Extension)\r
+\r
+  Offset(0x1C00),\r
+  PHED,   32,                     // Panel Header\r
+  BDDC,   2048,                   // Panel EDID (Max 256 bytes)\r
+\r
+}\r
+\r
+\r
+\r
+// Convert boot display type into a port mask.\r
+\r
+Name (DBTB, Package()\r
+{\r
+  0x0000,                         // Automatic\r
+  0x0007,                         // Port-0 : Integrated CRT\r
+  0x0038,                         // Port-1 : DVO-A, or Integrated LVDS\r
+  0x01C0,                         // Port-2 : SDVO-B, or SDVO-B/C\r
+  0x0E00,                         // Port-3 : SDVO-C\r
+  0x003F,                         // [CRT + DVO-A / Integrated LVDS]\r
+  0x01C7,                         // [CRT + SDVO-B] or [CRT + SDVO-B/C]\r
+  0x0E07,                         // [CRT + SDVO-C]\r
+  0x01F8,                         // [DVO-A / Integrated LVDS + SDVO-B]\r
+  0x0E38,                         // [DVO-A / Integrated LVDS + SDVO-C]\r
+  0x0FC0,                         // [SDVO-B + SDVO-C]\r
+  0x0000,                         // Reserved\r
+  0x0000,                         // Reserved\r
+  0x0000,                         // Reserved\r
+  0x0000,                         // Reserved\r
+  0x0000,                         // Reserved\r
+  0x7000,                         // Port-4: Integrated TV\r
+  0x7007,                         // [Integrated TV + CRT]\r
+  0x7038,                         // [Integrated TV + LVDS]\r
+  0x71C0,                         // [Integrated TV + DVOB]\r
+  0x7E00                          // [Integrated TV + DVOC]\r
+})\r
+\r
+// Core display clock value table.\r
+\r
+Name (CDCT, Package()\r
+{\r
+  Package() {160},\r
+  Package() {200},\r
+  Package() {267},\r
+  Package() {320},\r
+  Package() {356},\r
+  Package() {400},\r
+})\r
+\r
+// Defined exit result values:\r
+\r
+Name (SUCC, 1)                          // Exit result: Success\r
+Name (NVLD, 2)                          // Exit result: Invalid parameter\r
+Name (CRIT, 4)                          // Exit result: Critical failure\r
+Name (NCRT, 6)                          // Exit result: Non-critical failure\r
+\r
+\r
+/************************************************************************;\r
+;*\r
+;* Name: GSCI\r
+;*\r
+;* Description: Handles an SCI generated by the graphics driver.  The\r
+;*              PARM and SCIC input fields are parsed to determine the\r
+;*              functionality requested by the driver.  GBDA or SBCB\r
+;*              is called based on the input data in SCIC.\r
+;*\r
+;* Usage:       The method must be called in response to a GPE 06 event\r
+;*              which will be generated by the graphics driver.\r
+;*              Ex: Method(\_GPE._L06) {Return(\_SB.PCI0.GFX0.GSCI())}\r
+;*\r
+;* Input:       PARM and SCIC are indirect inputs\r
+;*\r
+;* Output:      PARM and SIC are indirect outputs\r
+;*\r
+;* References:  GBDA (Get BIOS Data method), SBCB (System BIOS Callback\r
+;*              method)\r
+;*\r
+;************************************************************************/\r
+\r
+Method (GSCI, 0, Serialized)\r
+{\r
+  Include("IgdOGBDA.ASL") // "Get BIOS Data" Functions\r
+  Include("IgdOSBCB.ASL") // "System BIOS CallBacks"\r
+\r
+  If (LEqual(GEFC, 4))\r
+  {\r
+    Store(GBDA(), GXFC)     // Process Get BIOS Data functions\r
+  }\r
+\r
+  If (LEqual(GEFC, 6))\r
+  {\r
+    Store(SBCB(), GXFC)     // Process BIOS Callback functions\r
+  }\r
+\r
+  Store(0, GEFC)                  // Wipe out the entry function code\r
+  Store(1, SCIS)                  // Clear the GUNIT SCI status bit in PCH ACPI I/O space.\r
+  Store(0, GSSE)                  // Clear the SCI generation bit in PCI space.\r
+  Store(0, SCIE)                  // Clr SCI serviced bit to signal completion\r
+\r
+  Return(Zero)\r
+}\r
+\r
+// Include MOBLFEAT.ASL for mobile systems only.  Remove for desktop.\r
+Include("IgdOMOBF.ASL")     // IGD SCI mobile features\r

diff --git a/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/IoTVirtualDevice.asl b/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/IoTVirtualDevice.asl
new file mode 100644 (file)
index 0000000..ef1383b
--- /dev/null
+++ b/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/IoTVirtualDevice.asl
@@ -0,0 +1,177 @@
+/** @file\r
+Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution.  The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+Device(IOTD) { \r
+  Name(_HID, "MSFT8000")\r
+  Name(_CID, "MSFT8000")\r
+  \r
+  Name(_CRS, ResourceTemplate() {  \r
+    // Index 0 \r
+    SPISerialBus(            // Pin 5, 7, 9 , 11 of JP1 for SIO_SPI\r
+      1,                     // Device selection\r
+      PolarityLow,           // Device selection polarity\r
+      FourWireMode,          // wiremode\r
+      8,                     // databit len\r
+      ControllerInitiated,   // slave mode\r
+      8000000,               // Connection speed\r
+      ClockPolarityLow,      // Clock polarity\r
+      ClockPhaseSecond,      // clock phase\r
+      "\\_SB.SPI1",          // ResourceSource: SPI bus controller name\r
+      0,                     // ResourceSourceIndex\r
+      ResourceConsumer,      // Resource usage\r
+      JSPI,                  // DescriptorName: creates name for offset of resource descriptor\r
+      )                      // Vendor Data  \r
+    \r
+    // Index 1     \r
+    I2CSerialBus(            // Pin 13, 15 of JP1, for SIO_I2C5 (signal)\r
+      0x00,                  // SlaveAddress: bus address (TBD)\r
+      ,                      // SlaveMode: default to ControllerInitiated\r
+      400000,                // ConnectionSpeed: in Hz\r
+      ,                      // Addressing Mode: default to 7 bit\r
+      "\\_SB.I2C6",          // ResourceSource: I2C bus controller name (For MinnowBoard Max, hardware I2C5(0-based) is reported as ACPI I2C6(1-based))\r
+      ,\r
+      ,\r
+      JI2C,                  // Descriptor Name: creates name for offset of resource descriptor\r
+      )                      // VendorData\r
+    \r
+    // Index 2\r
+    UARTSerialBus(           // Pin 17, 19 of JP1, for SIO_UART2\r
+      115200,                // InitialBaudRate: in bits ber second\r
+      ,                      // BitsPerByte: default to 8 bits\r
+      ,                      // StopBits: Defaults to one bit\r
+      0xfc,                  // LinesInUse: 8 1-bit flags to declare line enabled\r
+      ,                      // IsBigEndian: default to LittleEndian\r
+      ,                      // Parity: Defaults to no parity\r
+      ,                      // FlowControl: Defaults to no flow control\r
+      32,                    // ReceiveBufferSize\r
+      32,                    // TransmitBufferSize\r
+      "\\_SB.URT2",          // ResourceSource: UART bus controller name\r
+      ,\r
+      ,\r
+      UAR2,                  // DescriptorName: creates name for offset of resource descriptor\r
+      )                      \r
+    \r
+    // Index 3\r
+    GpioIo (Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.GPO2",) {0}  // Pin 21 of JP1 (GPIO_S5[00])\r
+    // Index 4\r
+    GpioInt(Edge, ActiveBoth, SharedAndWake, PullNone, 0,"\\_SB.GPO2",) {0} \r
+    \r
+    // Index 5\r
+    GpioIo (Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.GPO2",) {1}  // Pin 23 of JP1 (GPIO_S5[01])\r
+    // Index 6\r
+    GpioInt(Edge, ActiveBoth, SharedAndWake, PullNone, 0,"\\_SB.GPO2",) {1}\r
+    \r
+    // Index 7\r
+    GpioIo (Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.GPO2",) {2}  // Pin 25 of JP1 (GPIO_S5[02])\r
+    // Index 8\r
+    GpioInt(Edge, ActiveBoth, SharedAndWake, PullNone, 0,"\\_SB.GPO2",) {2} \r
+    \r
+    // Index 9\r
+    UARTSerialBus(           // Pin 6, 8, 10, 12 of JP1, for SIO_UART1\r
+      115200,                // InitialBaudRate: in bits ber second\r
+      ,                      // BitsPerByte: default to 8 bits\r
+      ,                      // StopBits: Defaults to one bit\r
+      0xfc,                  // LinesInUse: 8 1-bit flags to declare line enabled\r
+      ,                      // IsBigEndian: default to LittleEndian\r
+      ,                      // Parity: Defaults to no parity\r
+      FlowControlHardware,   // FlowControl: Defaults to no flow control\r
+      32,                    // ReceiveBufferSize\r
+      32,                    // TransmitBufferSize\r
+      "\\_SB.URT1",          // ResourceSource: UART bus controller name\r
+      ,\r
+      ,\r
+      UAR1,              // DescriptorName: creates name for offset of resource descriptor\r
+      )  \r
+    \r
+    // Index 10\r
+    GpioIo (Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.GPO0",) {62}  // Pin 14 of JP1 (GPIO_SC[62])\r
+    // Index 11\r
+    GpioInt(Edge, ActiveBoth, SharedAndWake, PullNone, 0,"\\_SB.GPO0",) {62} \r
+    \r
+    // Index 12\r
+    GpioIo (Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.GPO0",) {63}  // Pin 16 of JP1 (GPIO_SC[63])\r
+    // Index 13\r
+    GpioInt(Edge, ActiveBoth, SharedAndWake, PullNone, 0,"\\_SB.GPO0",) {63} \r
+    \r
+    // Index 14\r
+    GpioIo (Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.GPO0",) {65}  // Pin 18 of JP1 (GPIO_SC[65])\r
+    // Index 15\r
+    GpioInt(Edge, ActiveBoth, SharedAndWake, PullNone, 0,"\\_SB.GPO0",) {65} \r
+    \r
+    // Index 16\r
+    GpioIo (Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.GPO0",) {64}  // Pin 20 of JP1 (GPIO_SC[64])\r
+    // Index 17\r
+    GpioInt(Edge, ActiveBoth, SharedAndWake, PullNone, 0,"\\_SB.GPO0",) {64} \r
+    \r
+    // Index 18\r
+    GpioIo (Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.GPO0",) {94}  // Pin 22 of JP1 (GPIO_SC[94])\r
+    // Index 19\r
+    GpioInt(Edge, ActiveBoth, SharedAndWake, PullNone, 0,"\\_SB.GPO0",) {94} \r
+    \r
+    // Index 20\r
+    GpioIo (Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.GPO0",) {95}  // Pin 24 of JP1 (GPIO_SC[95])\r
+    // Index 21\r
+    GpioInt(Edge, ActiveBoth, SharedAndWake, PullNone, 0,"\\_SB.GPO0",) {95} \r
+    \r
+    // Index 22\r
+    GpioIo (Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.GPO0",) {54}  // Pin 26 of JP1 (GPIO_SC[54])\r
+    // Index 23\r
+    GpioInt(Edge, ActiveBoth, SharedAndWake, PullNone, 0,"\\_SB.GPO0",) {54}\r
+  })\r
+\r
+  Name(_DSD, Package() {\r
+    ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),\r
+    Package(1) {         // Just one Property for IOT (at this time) \r
+      Package(2) {     //The \93symbolic-identifiers\94 property\r
+        "symbolic-identifiers", \r
+        Package() {    //Contains all the <resource index, symbolic-identifier> pairs       \r
+          0, "SPI0",     \r
+          1, "I2C5",           \r
+          2, "UART2",\r
+          3, 21,       // Pin 21 of JP1 (GPIO_S5[00])\r
+          4, 21,       // Pin 21 for separate resource. \r
+          5, 23,       // Pin 23 of JP1 (GPIO_S5[01])\r
+          6, 23,\r
+          7, 25,       // Pin 25 of JP1 (GPIO_S5[02])\r
+          8, 25,\r
+          9, "UART1",\r
+          10, 14,      // Pin 14 of JP1 (GPIO_SC[62])\r
+          11, 14,\r
+          12, 16,      // Pin 16 of JP1 (GPIO_SC[63])\r
+          13, 16,\r
+          14, 18,      // Pin 18 of JP1 (GPIO_SC[65])\r
+          15, 18,\r
+          16, 20,      // Pin 20 of JP1 (GPIO_SC[64])\r
+          17, 20,\r
+          18, 22,      // Pin 22 of JP1 (GPIO_SC[94])\r
+          19, 22,\r
+          20, 24,      // Pin 24 of JP1 (GPIO_SC[95])\r
+          21, 24,\r
+          22, 26,      // Pin 26 of JP1 (GPIO_SC[54])\r
+          23, 26\r
+        }\r
+      } \r
+    }\r
+  })\r
+  \r
+  Method(_STA,0,Serialized) {\r
+    \r
+    //\r
+    // Only report IoT virtual device when all pins' configuration follows MSFT's datasheet.\r
+    //\r
+    If (LEqual(IOT, 1)) {\r
+      Return (0xF)\r
+    }\r
+    \r
+    Return (0x0)\r
+  }\r
+}\r

diff --git a/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/LPC_DEV.ASL b/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/LPC_DEV.ASL
new file mode 100644 (file)
index 0000000..31b4050
--- /dev/null
+++ b/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/LPC_DEV.ASL
@@ -0,0 +1,157 @@
+/**************************************************************************;\r
+;*                                                                        *;\r
+;*                                                                        *;\r
+;*    Intel Corporation - ACPI Reference Code for the Baytrail            *;\r
+;*    Family of Customer Reference Boards.                                *;\r
+;*                                                                        *;\r
+;*                                                                        *;\r
+;*    Copyright (c) 2012  - 2014, Intel Corporation. All rights reserved    *;\r
+;\r
+; This program and the accompanying materials are licensed and made available under\r
+; the terms and conditions of the BSD License that accompanies this distribution.\r
+; The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php.\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+;*                                                                        *;\r
+;*                                                                        *;\r
+;**************************************************************************/\r
+\r
+Device(FWHD) // Firmware Hub Device\r
+{\r
+  Name(_HID,EISAID("INT0800"))\r
+\r
+  Name(_CRS,ResourceTemplate()\r
+  {\r
+    Memory32Fixed(ReadOnly,0xFF000000,0x1000000)\r
+  })\r
+}\r
+\r
+Device(IPIC) // 8259 PIC\r
+{\r
+  Name(_HID,EISAID("PNP0000"))\r
+\r
+  Name(_CRS,ResourceTemplate()\r
+  {\r
+    IO(Decode16,0x20,0x20,0x01,0x02)\r
+    IO(Decode16,0x24,0x24,0x01,0x02)\r
+    IO(Decode16,0x28,0x28,0x01,0x02)\r
+    IO(Decode16,0x2C,0x2C,0x01,0x02)\r
+    IO(Decode16,0x30,0x30,0x01,0x02)\r
+    IO(Decode16,0x34,0x34,0x01,0x02)\r
+    IO(Decode16,0x38,0x38,0x01,0x02)\r
+    IO(Decode16,0x3C,0x3C,0x01,0x02)\r
+    IO(Decode16,0xA0,0xA0,0x01,0x02)\r
+    IO(Decode16,0xA4,0xA4,0x01,0x02)\r
+    IO(Decode16,0xA8,0xA8,0x01,0x02)\r
+    IO(Decode16,0xAC,0xAC,0x01,0x02)\r
+    IO(Decode16,0xB0,0xB0,0x01,0x02)\r
+    IO(Decode16,0xB4,0xB4,0x01,0x02)\r
+    IO(Decode16,0xB8,0xB8,0x01,0x02)\r
+    IO(Decode16,0xBC,0xBC,0x01,0x02)\r
+    IO(Decode16,0x4D0,0x4D0,0x01,0x02)\r
+    IRQNoFlags() {2}\r
+  })\r
+}\r
+\r
+Device(LDRC) // LPC Device Resource Consumption\r
+{\r
+  Name(_HID,EISAID("PNP0C02"))\r
+\r
+  Name(_UID,2)\r
+\r
+  Name(_CRS,ResourceTemplate()\r
+  {\r
+    IO(Decode16,0x4E,0x4E,0x1,0x02)         // LPC Slot Access.\r
+    IO(Decode16,0x61,0x61,0x1,0x1)          // NMI Status.\r
+    IO(Decode16,0x63,0x63,0x1,0x1)          // Processor I/F.\r
+    IO(Decode16,0x65,0x65,0x1,0x1)          // Processor I/F.\r
+    IO(Decode16,0x67,0x67,0x1,0x1)          // Processor I/F.\r
+    IO(Decode16,0x70,0x70,0x1,0x1)          // NMI Enable.\r
+    IO(Decode16,0x80,0x80,0x1,0x10)         // Postcode.\r
+    IO(Decode16,0x92,0x92,0x1,0x1)          // Processor I/F.\r
+    IO(Decode16,0xB2,0xB2,0x01,0x02)        // Software SMI.\r
+    IO(Decode16,0x680,0x680,0x1,0x20)       // 32 Byte I/O.\r
+    IO(Decode16,0x400,0x400,0x1,0x80)       // ACPI Base.\r
+    IO(Decode16,0x500,0x500,0x1,0xFF)       // GPIO Base.\r
+  })\r
+}\r
+\r
+Device(TIMR) // 8254 Timer\r
+{\r
+  Name(_HID,EISAID("PNP0100"))\r
+\r
+  Name(_CRS,ResourceTemplate()\r
+  {\r
+    IO(Decode16,0x40,0x40,0x01,0x04)\r
+    IO(Decode16,0x50,0x50,0x10,0x04)\r
+    IRQNoFlags() {0}\r
+  })\r
+}\r
+\r
+Device(IUR3) // Internal UART\r
+{\r
+  Name(_HID, EISAID("PNP0501"))\r
+\r
+  Name(_UID,1)\r
+\r
+  // Status Method for internal UART\r
+\r
+  Method(_STA,0,Serialized)\r
+  {\r
+    // Only report resources to the OS if internal UART is\r
+    // not set to Disabled in BIOS Setup.\r
+\r
+    If(LEqual(USEL,0))\r
+    {\r
+      If(LEqual(PU1E,1))\r
+      {\r
+        Store(1,UI3E) // Enable IRQ3 for UART\r
+        Store(1,UI4E) // Enable IRQ4 for UART\r
+        Store(1,C1EN) // Enable UART\r
+        Return(0x000F)\r
+      }\r
+    }\r
+\r
+    Return(0x0000)\r
+  }\r
+\r
+  // Disable Method for internal UART\r
+\r
+  Method(_DIS,0,Serialized)\r
+  {\r
+    Store(0,UI3E)\r
+    Store(0,UI4E)\r
+    Store(0,C1EN)\r
+  }\r
+\r
+  // Current Resource Setting Method for internal UART\r
+\r
+  Method(_CRS,0,Serialized)\r
+  {\r
+    // Create the Buffer that stores the Resources to\r
+    // be returned.\r
+\r
+    Name(BUF0,ResourceTemplate()\r
+    {\r
+      IO(Decode16,0x03F8,0x03F8,0x01,0x08)\r
+      IRQNoFlags() {3}\r
+    })\r
+\r
+    Name(BUF1,ResourceTemplate()\r
+    {\r
+      IO(Decode16,0x03F8,0x03F8,0x01,0x08)\r
+      IRQNoFlags() {4}\r
+    })\r
+\r
+    If (LLessEqual(SRID, 0x04))\r
+    {\r
+      Return(BUF0)\r
+    } Else\r
+    {\r
+      Return(BUF1)\r
+    }\r
+  }\r
+}\r

diff --git a/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/LpcB.asl b/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/LpcB.asl
new file mode 100644 (file)
index 0000000..afa6a53
--- /dev/null
+++ b/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/LpcB.asl
@@ -0,0 +1,65 @@
+/**************************************************************************;\r
+;*                                                                        *;\r
+;*                                                                        *;\r
+;*    Intel Corporation - ACPI Reference Code for the Baytrail            *;\r
+;*    Family of Customer Reference Boards.                                *;\r
+;*                                                                        *;\r
+;*                                                                        *;\r
+;*    Copyright (c) 2012  - 2014, Intel Corporation. All rights reserved    *;\r
+;\r
+; This program and the accompanying materials are licensed and made available under\r
+; the terms and conditions of the BSD License that accompanies this distribution.\r
+; The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php.\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+;*                                                                        *;\r
+;*                                                                        *;\r
+;**************************************************************************/\r
+\r
+\r
+// LPC Bridge - Device 31, Function 0\r
+// Define the needed LPC registers used by ASL.\r
+\r
+scope(\_SB)\r
+{\r
+  OperationRegion(ILBR, SystemMemory, \IBAS, 0x8C)\r
+  Field(ILBR, AnyAcc, NoLock, Preserve)\r
+  {\r
+    Offset(0x08), // 0x08\r
+    PARC,   8,\r
+    PBRC,   8,\r
+    PCRC,   8,\r
+    PDRC,   8,\r
+    PERC,   8,\r
+    PFRC,   8,\r
+    PGRC,   8,\r
+    PHRC,   8,\r
+    Offset(0x88), // 0x88\r
+    ,       3,\r
+    UI3E,   1,\r
+    UI4E,   1\r
+  }\r
+\r
+  Include ("98_LINK.ASL")\r
+}\r
+\r
+OperationRegion(LPC0, PCI_Config, 0x00, 0xC0)\r
+Field(LPC0, AnyAcc, NoLock, Preserve)\r
+{\r
+  Offset(0x08), // 0x08\r
+  SRID,   8,  // Revision ID\r
+  Offset(0x080), // 0x80\r
+  C1EN,   1, // COM1 Enable\r
+  ,      31\r
+}\r
+\r
+\r
+Include ("LPC_DEV.ASL")\r
+\r
+\r
+\r
+\r
+\r

diff --git a/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/Lpit/Lpit.aslc b/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/Lpit/Lpit.aslc
new file mode 100644 (file)
index 0000000..ae81b2f
--- /dev/null
+++ b/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/Lpit/Lpit.aslc
@@ -0,0 +1,229 @@
+/*++\r
+\r
+Copyright (c)  1999  - 2014, Intel Corporation. All rights reserved\r
+\r
+  This program and the accompanying materials are licensed and made available under\r
+  the terms and conditions of the BSD License that accompanies this distribution.\r
+  The full text of the license may be found at\r
+  http://opensource.org/licenses/bsd-license.php.\r
+\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+\r
+--*/\r
+\r
+//\r
+// Include files\r
+//\r
+\r
+#include <PiDxe.h>\r
+#include <IndustryStandard/Acpi50.h>\r
+\r
+\r
+\r
+//\r
+// LPIT Definitions\r
+//\r
+\r
+#define EFI_ACPI_LOW_POWER_IDLE_TABLE_REVISION 0x1\r
+\r
+//\r
+// Ensure proper structure formats\r
+//\r
+#pragma pack(1)\r
+\r
+typedef union _EFI_ACPI_LPI_STATE_FLAGS {\r
+  struct {\r
+    UINT32 Disabled           :1;\r
+    UINT32 CounterUnavailable :1;\r
+    UINT32 Reserved           :30;\r
+  };\r
+  UINT32 AsUlong;\r
+} EFI_ACPI_LPI_STATE_FLAGS, *PEFI_ACPI_LPI_STATE_FLAGS;\r
+\r
+// Only Mwait LPI here:\r
+\r
+typedef struct _EFI_ACPI_MWAIT_LPI_STATE_DESCRIPTOR {\r
+  UINT32 Type;        // offset: 0\r
+  UINT32 Length;      // offset: 4\r
+  UINT16 UniqueId;    // offset: 8\r
+  UINT8 Reserved[2];  // offset: 9\r
+  EFI_ACPI_LPI_STATE_FLAGS Flags; // offset: 12\r
+  EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE EntryTrigger; // offset: 16\r
+  UINT32 Residency;   // offset: 28\r
+  UINT32 Latency;     // offset: 32\r
+  EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE ResidencyCounter; // offset: 36\r
+  UINT64 ResidencyCounterFrequency; //offset: 48\r
+} EFI_ACPI_MWAIT_LPI_STATE_DESCRIPTOR;\r
+\r
+\r
+//\r
+// Defines for LPIT table, some are VLV specific\r
+//\r
+\r
+\r
+// signature "LPIT"\r
+#define EFI_ACPI_LOW_POWER_IDLE_TABLE_SIGNATURE  0x5449504c\r
+\r
+#define EFI_ACPI_OEM_LPIT_REVISION                      0x00000000\r
+\r
+#define EFI_ACPI_LOW_POWER_IDLE_MWAIT_TYPE    0x0\r
+#define EFI_ACPI_LOW_POWER_IDLE_DEFAULT_FLAG  0x0\r
+#define EFI_ACPI_LOW_POWER_IDLE_RES_FREQ_8K   0x8000    // 32768\r
+\r
+//\r
+// LPI state count (4 on VLV: S0ir, S0i1, S0i2, S0i3)\r
+//\r
+\r
+#define EFI_ACPI_VLV_LPI_STATE_COUNT          0x4\r
+\r
+//\r
+// LPI TRIGGER (HW C7 on VLV),\r
+// TOFIX!!!\r
+//\r
+#define EFI_ACPI_VLV_LPI_TRIGGER {0x7F,0x1,0x2,0x0,0x64}\r
+\r
+//\r
+// LPI residency counter (MMIO)\r
+//\r
+#define  EFI_ACPI_VLV_LPI_RES_COUNTER0   {0x0,32,0x0,0x03,0xFED03080}\r
+#define  EFI_ACPI_VLV_LPI_RES_COUNTER1   {0x0,32,0x0,0x03,0xFED03084}\r
+#define  EFI_ACPI_VLV_LPI_RES_COUNTER2   {0x0,32,0x0,0x03,0xFED03088}\r
+#define  EFI_ACPI_VLV_LPI_RES_COUNTER3   {0x0,32,0x0,0x03,0xFED0308C}\r
+\r
+//\r
+// LPI break-even residency in us - all match S0i3 residency\r
+// Residency estimate: Latency x 3\r
+//\r
+#define  EFI_ACPI_VLV_LPI_MIN_RES0   15000\r
+#define  EFI_ACPI_VLV_LPI_MIN_RES1   15000\r
+#define  EFI_ACPI_VLV_LPI_MIN_RES2   15000\r
+#define  EFI_ACPI_VLV_LPI_MIN_RES3   15000\r
+\r
+//\r
+// LPI latency in us - all match S0i3 latency\r
+//\r
+#define  EFI_ACPI_VLV_LPI_LATENCY0   5000\r
+#define  EFI_ACPI_VLV_LPI_LATENCY1   5000\r
+#define  EFI_ACPI_VLV_LPI_LATENCY2   5000\r
+#define  EFI_ACPI_VLV_LPI_LATENCY3   5000\r
+\r
+\r
+//\r
+// LPI ID\r
+//\r
+#define  EFI_ACPI_VLV_LPI_UNIQUE_ID0   0\r
+#define  EFI_ACPI_VLV_LPI_UNIQUE_ID1   1\r
+#define  EFI_ACPI_VLV_LPI_UNIQUE_ID2   2\r
+#define  EFI_ACPI_VLV_LPI_UNIQUE_ID3   3\r
+\r
+//\r
+//  LPI ACPI table header\r
+//\r
+\r
+\r
+typedef struct _EFI_ACPI_LOW_POWER_IDLE_TABLE {\r
+  EFI_ACPI_DESCRIPTION_HEADER             Header;\r
+  EFI_ACPI_MWAIT_LPI_STATE_DESCRIPTOR     LpiStates[EFI_ACPI_VLV_LPI_STATE_COUNT];\r
+} EFI_ACPI_LOW_POWER_IDLE_TABLE;\r
+\r
+#pragma pack()\r
+\r
+EFI_ACPI_LOW_POWER_IDLE_TABLE Lpit = {\r
+\r
+  //\r
+  // Header\r
+  //\r
+\r
+\r
+  EFI_ACPI_LOW_POWER_IDLE_TABLE_SIGNATURE,\r
+  sizeof (EFI_ACPI_LOW_POWER_IDLE_TABLE),\r
+  EFI_ACPI_LOW_POWER_IDLE_TABLE_REVISION ,\r
+\r
+  //\r
+  // Checksum will be updated at runtime\r
+  //\r
+  0x00,\r
+\r
+  //\r
+  // It is expected that these values will be updated at runtime\r
+  //\r
+  ' ', ' ', ' ', ' ', ' ', ' ',\r
+\r
+  0,\r
+  EFI_ACPI_OEM_LPIT_REVISION,\r
+  0,\r
+  0,\r
+\r
+\r
+\r
+  //\r
+  // Descriptor\r
+  //\r
+  {\r
+    {\r
+      EFI_ACPI_LOW_POWER_IDLE_MWAIT_TYPE,\r
+      sizeof(EFI_ACPI_MWAIT_LPI_STATE_DESCRIPTOR),\r
+      EFI_ACPI_VLV_LPI_UNIQUE_ID0,\r
+      {0,0},\r
+      {EFI_ACPI_LOW_POWER_IDLE_DEFAULT_FLAG},   // Flags\r
+      EFI_ACPI_VLV_LPI_TRIGGER,  //EntryTrigger\r
+      EFI_ACPI_VLV_LPI_MIN_RES0, //Residency\r
+      EFI_ACPI_VLV_LPI_LATENCY0, //Latency\r
+      EFI_ACPI_VLV_LPI_RES_COUNTER0, //ResidencyCounter\r
+      EFI_ACPI_LOW_POWER_IDLE_RES_FREQ_8K //Residency counter frequency\r
+    },\r
+    {\r
+      EFI_ACPI_LOW_POWER_IDLE_MWAIT_TYPE,\r
+      sizeof(EFI_ACPI_MWAIT_LPI_STATE_DESCRIPTOR),\r
+      EFI_ACPI_VLV_LPI_UNIQUE_ID1,\r
+      {0,0},\r
+      {EFI_ACPI_LOW_POWER_IDLE_DEFAULT_FLAG},   // Flags\r
+      EFI_ACPI_VLV_LPI_TRIGGER,  //EntryTrigger\r
+      EFI_ACPI_VLV_LPI_MIN_RES1, //Residency\r
+      EFI_ACPI_VLV_LPI_LATENCY1, //Latency\r
+      EFI_ACPI_VLV_LPI_RES_COUNTER1, //ResidencyCounter\r
+      EFI_ACPI_LOW_POWER_IDLE_RES_FREQ_8K //Residency counter frequency\r
+    },\r
+    {\r
+      EFI_ACPI_LOW_POWER_IDLE_MWAIT_TYPE,\r
+      sizeof(EFI_ACPI_MWAIT_LPI_STATE_DESCRIPTOR),\r
+      EFI_ACPI_VLV_LPI_UNIQUE_ID2,\r
+      {0,0},\r
+      {EFI_ACPI_LOW_POWER_IDLE_DEFAULT_FLAG},   // Flags\r
+      EFI_ACPI_VLV_LPI_TRIGGER,  //EntryTrigger\r
+      EFI_ACPI_VLV_LPI_MIN_RES2, //Residency\r
+      EFI_ACPI_VLV_LPI_LATENCY2, //Latency\r
+      EFI_ACPI_VLV_LPI_RES_COUNTER2, //ResidencyCounter\r
+      EFI_ACPI_LOW_POWER_IDLE_RES_FREQ_8K //Residency counter frequency\r
+    },\r
+    {\r
+      EFI_ACPI_LOW_POWER_IDLE_MWAIT_TYPE,\r
+      sizeof(EFI_ACPI_MWAIT_LPI_STATE_DESCRIPTOR),\r
+      EFI_ACPI_VLV_LPI_UNIQUE_ID3,\r
+      {0,0},\r
+      {EFI_ACPI_LOW_POWER_IDLE_DEFAULT_FLAG},   // Flags\r
+      EFI_ACPI_VLV_LPI_TRIGGER,  //EntryTrigger\r
+      EFI_ACPI_VLV_LPI_MIN_RES3, //Residency\r
+      EFI_ACPI_VLV_LPI_LATENCY3, //Latency\r
+      EFI_ACPI_VLV_LPI_RES_COUNTER3, //ResidencyCounter\r
+      EFI_ACPI_LOW_POWER_IDLE_RES_FREQ_8K //Residency counter frequency\r
+    }\r
+  }\r
+\r
+};\r
+\r
+\r
+VOID*\r
+ReferenceAcpiTable (\r
+  VOID\r
+  )\r
+{\r
+  //\r
+  // Reference the table being generated to prevent the optimizer from\r
+  // removing the data structure from the executable\r
+  //\r
+  return (VOID*)&Lpit;\r
+}\r

diff --git a/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/Madt/Madt.h b/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/Madt/Madt.h
new file mode 100644 (file)
index 0000000..7a01d64
--- /dev/null
+++ b/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/Madt/Madt.h
@@ -0,0 +1,195 @@
+/*++\r
+\r
+Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+\r
+  This program and the accompanying materials are licensed and made available under\r
+  the terms and conditions of the BSD License that accompanies this distribution.\r
+  The full text of the license may be found at\r
+  http://opensource.org/licenses/bsd-license.php.\r
+\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+Module Name:\r
+\r
+  Madt.h\r
+\r
+Abstract:\r
+\r
+  This file describes the contents of the ACPI Multiple APIC Description\r
+  Table (MADT).  Some additional ACPI values are defined in Acpi1_0.h and\r
+  Acpi2_0.h.\r
+  To make changes to the MADT, it is necessary to update the count for the\r
+  APIC structure being updated, and to modify table found in Madt.c.\r
+\r
+--*/\r
+\r
+#ifndef _MADT_H\r
+#define _MADT_H\r
+\r
+//\r
+// Statements that include other files\r
+//\r
+#include "AcpiTablePlatform.h"\r
+#include <IndustryStandard/Acpi10.h>\r
+#include <IndustryStandard/Acpi20.h>\r
+#include <IndustryStandard/Acpi30.h>\r
+#include "Platform.h"\r
+\r
+//\r
+// MADT Definitions\r
+//\r
+#define EFI_ACPI_OEM_MADT_REVISION                      0x00000000\r
+//\r
+// Multiple APIC Flags are defined in AcpiX.0.h\r
+//\r
+#define EFI_ACPI_1_0_MULTIPLE_APIC_FLAGS  (EFI_ACPI_1_0_PCAT_COMPAT)\r
+#define EFI_ACPI_2_0_MULTIPLE_APIC_FLAGS  (EFI_ACPI_2_0_PCAT_COMPAT)\r
+#define EFI_ACPI_3_0_MULTIPLE_APIC_FLAGS  (EFI_ACPI_3_0_PCAT_COMPAT)\r
+#define EFI_ACPI_4_0_MULTIPLE_APIC_FLAGS  (EFI_ACPI_4_0_PCAT_COMPAT)\r
+\r
+//\r
+// Define the number of each table type.\r
+// This is where the table layout is modified.\r
+//\r
+#define EFI_ACPI_PROCESSOR_LOCAL_APIC_COUNT             MAX_CPU_NUM\r
+#define EFI_ACPI_LOCAL_APIC_NMI_COUNT                   MAX_CPU_NUM\r
+#define EFI_ACPI_IO_APIC_COUNT                          1\r
+#define EFI_ACPI_INTERRUPT_SOURCE_OVERRIDE_COUNT        2\r
+#define EFI_ACPI_NON_MASKABLE_INTERRUPT_SOURCE_COUNT    0\r
+#define EFI_ACPI_LOCAL_APIC_ADDRESS_OVERRIDE_COUNT      0\r
+#define EFI_ACPI_IO_SAPIC_COUNT                         0\r
+#define EFI_ACPI_PROCESSOR_LOCAL_SAPIC_COUNT            0\r
+#define EFI_ACPI_PLATFORM_INTERRUPT_SOURCES_COUNT       0\r
+\r
+//\r
+// MADT structure\r
+//\r
+//\r
+// Ensure proper structure formats\r
+//\r
+#pragma pack(1)\r
+//\r
+// ACPI 1.0 Table structure\r
+//\r
+typedef struct {\r
+  EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER   Header;\r
+\r
+#if EFI_ACPI_PROCESSOR_LOCAL_APIC_COUNT > 0\r
+  EFI_ACPI_1_0_PROCESSOR_LOCAL_APIC_STRUCTURE           LocalApic[EFI_ACPI_PROCESSOR_LOCAL_APIC_COUNT];\r
+#endif\r
+\r
+#if EFI_ACPI_IO_APIC_COUNT > 0\r
+  EFI_ACPI_1_0_IO_APIC_STRUCTURE                        IoApic[EFI_ACPI_IO_APIC_COUNT];\r
+#endif\r
+\r
+#if EFI_ACPI_INTERRUPT_SOURCE_OVERRIDE_COUNT > 0\r
+  EFI_ACPI_1_0_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE      Iso[EFI_ACPI_INTERRUPT_SOURCE_OVERRIDE_COUNT];\r
+#endif\r
+\r
+#if EFI_ACPI_NON_MASKABLE_INTERRUPT_SOURCE_COUNT > 0\r
+  EFI_ACPI_1_0_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE  NmiSource[EFI_ACPI_NON_MASKABLE_INTERRUPT_SOURCE_COUNT];\r
+#endif\r
+\r
+#if EFI_ACPI_LOCAL_APIC_NMI_COUNT > 0\r
+  EFI_ACPI_1_0_LOCAL_APIC_NMI_STRUCTURE                 LocalApicNmi[EFI_ACPI_LOCAL_APIC_NMI_COUNT];\r
+#endif\r
+\r
+#if EFI_ACPI_LOCAL_APIC_ADDRESS_OVERRIDE_COUNT > 0\r
+  EFI_ACPI_1_0_LOCAL_APIC_ADDRESS_OVERRIDE_STRUCTURE    LocalApicOverride[EFI_ACPI_LOCAL_APIC_ADDRESS_OVERRIDE_COUNT];\r
+#endif\r
+\r
+} EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE;\r
+\r
+//\r
+// ACPI 2.0 Table structure\r
+//\r
+typedef struct {\r
+  EFI_ACPI_2_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER   Header;\r
+\r
+#if EFI_ACPI_PROCESSOR_LOCAL_APIC_COUNT > 0\r
+  EFI_ACPI_2_0_PROCESSOR_LOCAL_APIC_STRUCTURE           LocalApic[EFI_ACPI_PROCESSOR_LOCAL_APIC_COUNT];\r
+#endif\r
+\r
+#if EFI_ACPI_IO_APIC_COUNT > 0\r
+  EFI_ACPI_2_0_IO_APIC_STRUCTURE                        IoApic[EFI_ACPI_IO_APIC_COUNT];\r
+#endif\r
+\r
+#if EFI_ACPI_INTERRUPT_SOURCE_OVERRIDE_COUNT > 0\r
+  EFI_ACPI_2_0_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE      Iso[EFI_ACPI_INTERRUPT_SOURCE_OVERRIDE_COUNT];\r
+#endif\r
+\r
+#if EFI_ACPI_NON_MASKABLE_INTERRUPT_SOURCE_COUNT > 0\r
+  EFI_ACPI_2_0_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE  NmiSource[EFI_ACPI_NON_MASKABLE_INTERRUPT_SOURCE_COUNT];\r
+#endif\r
+\r
+#if EFI_ACPI_LOCAL_APIC_NMI_COUNT > 0\r
+  EFI_ACPI_2_0_LOCAL_APIC_NMI_STRUCTURE                 LocalApicNmi[EFI_ACPI_LOCAL_APIC_NMI_COUNT];\r
+#endif\r
+\r
+#if EFI_ACPI_LOCAL_APIC_ADDRESS_OVERRIDE_COUNT > 0\r
+  EFI_ACPI_2_0_LOCAL_APIC_ADDRESS_OVERRIDE_STRUCTURE    LocalApicOverride[EFI_ACPI_LOCAL_APIC_ADDRESS_OVERRIDE_COUNT];\r
+#endif\r
+\r
+#if EFI_ACPI_IO_SAPIC_COUNT > 0\r
+  EFI_ACPI_2_0_IO_SAPIC_STRUCTURE                       IoSapic[EFI_ACPI_IO_SAPIC_COUNT];\r
+#endif\r
+\r
+#if EFI_ACPI_PROCESSOR_LOCAL_SAPIC_COUNT > 0\r
+  EFI_ACPI_2_0_PROCESSOR_LOCAL_SAPIC_STRUCTURE          LocalSapic[EFI_ACPI_PROCESSOR_LOCAL_SAPIC_COUNT];\r
+#endif\r
+\r
+#if EFI_ACPI_PLATFORM_INTERRUPT_SOURCES_COUNT > 0\r
+  EFI_ACPI_2_0_PLATFORM_INTERRUPT_SOURCES_STRUCTURE     PlatformInterruptSources[EFI_ACPI_PLATFORM_INTERRUPT_SOURCES_COUNT];\r
+#endif\r
+\r
+} EFI_ACPI_2_0_MULTIPLE_APIC_DESCRIPTION_TABLE;\r
+\r
+//\r
+// ACPI 3.0 Table structure\r
+//\r
+typedef struct {\r
+  EFI_ACPI_3_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER   Header;\r
+\r
+#if EFI_ACPI_PROCESSOR_LOCAL_APIC_COUNT > 0           // Type 0x00\r
+  EFI_ACPI_3_0_PROCESSOR_LOCAL_APIC_STRUCTURE           LocalApic[EFI_ACPI_PROCESSOR_LOCAL_APIC_COUNT];\r
+#endif\r
+\r
+#if EFI_ACPI_IO_APIC_COUNT > 0                        // Type 0x01\r
+  EFI_ACPI_3_0_IO_APIC_STRUCTURE                        IoApic[EFI_ACPI_IO_APIC_COUNT];\r
+#endif\r
+\r
+#if EFI_ACPI_INTERRUPT_SOURCE_OVERRIDE_COUNT > 0      // Type 0x02\r
+  EFI_ACPI_3_0_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE      Iso[EFI_ACPI_INTERRUPT_SOURCE_OVERRIDE_COUNT];\r
+#endif\r
+\r
+#if EFI_ACPI_NON_MASKABLE_INTERRUPT_SOURCE_COUNT > 0  // Type 0x03\r
+  EFI_ACPI_3_0_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE  NmiSource[EFI_ACPI_NON_MASKABLE_INTERRUPT_SOURCE_COUNT];\r
+#endif\r
+\r
+#if EFI_ACPI_LOCAL_APIC_NMI_COUNT > 0                 // Type 0x04\r
+  EFI_ACPI_3_0_LOCAL_APIC_NMI_STRUCTURE                 LocalApicNmi[EFI_ACPI_LOCAL_APIC_NMI_COUNT];\r
+#endif\r
+\r
+#if EFI_ACPI_LOCAL_APIC_ADDRESS_OVERRIDE_COUNT > 0    // Type 0x05\r
+  EFI_ACPI_3_0_LOCAL_APIC_ADDRESS_OVERRIDE_STRUCTURE    LocalApicOverride[EFI_ACPI_LOCAL_APIC_ADDRESS_OVERRIDE_COUNT];\r
+#endif\r
+\r
+#if EFI_ACPI_IO_SAPIC_COUNT > 0                       // Type 0x06\r
+  EFI_ACPI_3_0_IO_SAPIC_STRUCTURE                       IoSapic[EFI_ACPI_IO_SAPIC_COUNT];\r
+#endif\r
+\r
+#if EFI_ACPI_PROCESSOR_LOCAL_SAPIC_COUNT > 0          // Type 0x07 : This table changes in madt 2.0\r
+  EFI_ACPI_3_0_PROCESSOR_LOCAL_SAPIC_STRUCTURE          LocalSapic[EFI_ACPI_PROCESSOR_LOCAL_SAPIC_COUNT];\r
+#endif\r
+\r
+#if EFI_ACPI_PLATFORM_INTERRUPT_SOURCES_COUNT > 0     // Type 0x08\r
+  EFI_ACPI_3_0_PLATFORM_INTERRUPT_SOURCES_STRUCTURE     PlatformInterruptSources[EFI_ACPI_PLATFORM_INTERRUPT_SOURCES_COUNT];\r
+#endif\r
+\r
+} EFI_ACPI_3_0_MULTIPLE_APIC_DESCRIPTION_TABLE;\r
+\r
+#pragma pack()\r
+\r
+#endif\r

diff --git a/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/Madt/Madt30.aslc b/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/Madt/Madt30.aslc
new file mode 100644 (file)
index 0000000..7b16120
--- /dev/null
+++ b/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/Madt/Madt30.aslc
@@ -0,0 +1,184 @@
+/*++\r
+\r
+  Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+\r
+  This program and the accompanying materials are licensed and made available under\r
+  the terms and conditions of the BSD License that accompanies this distribution.\r
+  The full text of the license may be found at\r
+  http://opensource.org/licenses/bsd-license.php.\r
+\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+\r
+Module Name:\r
+\r
+  Madt3.0.c\r
+\r
+Abstract:\r
+\r
+  This file contains a structure definition for the ACPI 2.0 Multiple APIC\r
+  Description Table (MADT).  Any changes to the MADT table require updating the\r
+  respective structure count in Madt.h and then adding the structure to the\r
+  MADT defined in this file.  The table layout is defined in Madt.h and the\r
+  table contents are defined in Acpi3_0.h and Madt.h.\r
+\r
+--*/\r
+\r
+//\r
+// Statements that include other files\r
+//\r
+#include "Madt.h"\r
+#include <IndustryStandard/Acpi50.h>\r
+\r
+//\r
+// Multiple APIC Description Table\r
+//\r
+EFI_ACPI_3_0_MULTIPLE_APIC_DESCRIPTION_TABLE  Madt = {\r
+  EFI_ACPI_3_0_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE, // **Signatures are the same 1.0-3.0 because it says "APIC".\r
+  sizeof (EFI_ACPI_3_0_MULTIPLE_APIC_DESCRIPTION_TABLE),  // **Length\r
+  EFI_ACPI_5_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION,\r
+  //\r
+  // EFI_ACPI_3_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION,  // **Table Revision must be 2.0 for ACPI 3.0\r
+  // Checksum will be updated at runtime\r
+  //\r
+  0x00, // **Check sum\r
+  //\r
+  // It is expected that these values will be programmed at runtime\r
+  //\r
+  ' ',                        // OEMID\r
+  ' ',                        // Creative way to\r
+  ' ',                        // make six bytes\r
+  ' ',                        // of space in\r
+  ' ',                        // a table for\r
+  ' ',                        // **OEMID\r
+  0,                          // **OEM Table ID\r
+  EFI_ACPI_OEM_MADT_REVISION, // **OEM Revision\r
+  0,                          // **Creator ID\r
+  0,                          // **Creator Revision\r
+  //\r
+  // MADT specific fields\r
+  //\r
+  LOCAL_APIC_ADDRESS,               // **Local APIC Address\r
+  EFI_ACPI_4_0_MULTIPLE_APIC_FLAGS, // **Flags\r
+  //\r
+  // Processor Local APIC Structure\r
+  // Correct processor order, Primary threads first then Hyper threads\r
+  // And correct APIC-ids\r
+  // This text below is included as a reference until Thurley is 100%:\r
+  // According to EDS the Local APIC ID is determined based of a bit structure\r
+  // Bit 24: Core ID Bit 25: Core Pair ID Bit 26-27: Reserved Bit 28-30: Socket ID Bit 31: Reserved\r
+  // 4 Sockets and 4 Cores per Socket.\r
+  // So possible LAPIC IDs 00, 01, 02, 03, 10, 11, 12, 13, 20, 21, 22, 23, 30, 31, 32, 33\r
+  // Static Entries 00, 10, 20, 30, 01, 11, 21, 31, 02, 12, 22, 32, 03, 13, 23, 33\r
+  // BSP needs to be first entry in table. Check before boot. If BSP non zero need to rotate the entries.\r
+  // Suppore BSP is LAPIC ID xy. Rotate the table by using formula [x + (y * 4)]\r
+  // So if BSP LAPIC ID is 21 then table rotated 6 times.\r
+  // End of Reference Text.\r
+  // Thurley is supposed to be 2 sockets, 4 cores, and hyperthreading available per each core.\r
+  // 2 (sockets) x 4 (cores) = 8 (processors non-HT), 8 (processors non-HT) x 2 (HT/proc) = 16 (HT procs)\r
+  // Rhyme & reason of the ordering below.  This is a best guess ordering for now,\r
+  // Thurley EPS may give better info on LAPIC numbers.\r
+  // Ordering was established to help dissipate heat across two sockets evenly.\r
+  // Since logical processor number only has to be unique, I followed\r
+  // a similar approach to high end servers and have the first digit of the LAPIC\r
+  // id the socket number.\r
+  //\r
+  EFI_ACPI_3_0_PROCESSOR_LOCAL_APIC,                    // Type 0x00\r
+  sizeof (EFI_ACPI_3_0_PROCESSOR_LOCAL_APIC_STRUCTURE), // Length\r
+  0x01,                                                 // Processor ID\r
+  0x00,                                                 // Local APIC ID\r
+  0x00000001,                                           // Flags - Disabled (until initialized by platform driver)\r
+  EFI_ACPI_3_0_PROCESSOR_LOCAL_APIC,                    // Type\r
+  sizeof (EFI_ACPI_3_0_PROCESSOR_LOCAL_APIC_STRUCTURE), // Length\r
+  0x02,                                                 // Processor ID\r
+  0x02,                                                 // Local APIC ID //Todo: Temp change APIC ID order for fixing VLV X0 not enable 2 CPU in Windows.\r
+  0x00000001,                                           // Flags - Disabled (until initialized by platform driver)\r
+  EFI_ACPI_3_0_PROCESSOR_LOCAL_APIC,                    // Type\r
+  sizeof (EFI_ACPI_3_0_PROCESSOR_LOCAL_APIC_STRUCTURE), // Length\r
+  0x03,                                                 // Processor ID\r
+  0x04,                                                 // Local APIC ID\r
+  0x00000001,                                           // Flags - Disabled (until initialized by platform driver)\r
+  EFI_ACPI_3_0_PROCESSOR_LOCAL_APIC,                    // Type\r
+  sizeof (EFI_ACPI_3_0_PROCESSOR_LOCAL_APIC_STRUCTURE), // Length\r
+  0x04,                                                 // Processor ID\r
+  0x06,                                                 // Local APIC ID\r
+  0x00000001,                                           // Flags - Disabled (until initialized by platform driver)\r
+  //\r
+  // ***************   IO APIC Structure ******************\r
+  //\r
+  //\r
+  //\r
+  // **************************  I/O APIC  **************\r
+  //\r
+  EFI_ACPI_3_0_IO_APIC,                     // Type 0x01\r
+  sizeof (EFI_ACPI_3_0_IO_APIC_STRUCTURE),  // Length\r
+  ICH_IOAPIC_ID,                            // IO APIC ID\r
+  EFI_ACPI_RESERVED_BYTE,                   // Reserved    EFI_ACPI_RESERVED_BYTE\r
+  IO_APIC_ADDRESS,                          // IO APIC Address (physical)   0xFEC00000\r
+  0x18 * 0,                                 // Global System Interrupt Base\r
+\r
+  //\r
+  // Interrupt Source Override Structure: Sample\r
+  //\r
+  // EFI_ACPI_2_0_INTERRUPT_SOURCE_OVERRIDE,                   // Type  0x02\r
+  // sizeof (EFI_ACPI_2_0_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE),// Length\r
+  // 0x00,                                                     // Bus\r
+  // 0x00,                                                     // Source\r
+  // 0x00000000,                                               // Global System Interrupt\r
+  // 0x0000,                                                   // Flags\r
+  //\r
+  // IRQ0=>IRQ2 Interrupt Source Override Structure\r
+  //\r
+  EFI_ACPI_3_0_INTERRUPT_SOURCE_OVERRIDE, // Type  0x02\r
+  sizeof (EFI_ACPI_3_0_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE),  // Length\r
+  0x00,       // Bus - ISA\r
+  0x00,       // Source - IRQ0\r
+  0x00000002, // Global System Interrupt - IRQ2\r
+  0x0000,     // Flags - Conforms to specifications of the bus\r
+  //\r
+  // ISO (SCI Active High) Interrupt Source Override Structure\r
+  //\r
+  EFI_ACPI_3_0_INTERRUPT_SOURCE_OVERRIDE, // Type  0x02\r
+  sizeof (EFI_ACPI_3_0_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE),  // Length\r
+  0x00,       // Bus - ISA\r
+  0x09,       // Source - IRQ0\r
+  0x00000009, // Global System Interrupt - IRQ2\r
+  0x000D,     // Flags - Level-tiggered, Active High\r
+\r
+\r
+\r
+  EFI_ACPI_3_0_LOCAL_APIC_NMI,                    // Type\r
+  sizeof (EFI_ACPI_3_0_LOCAL_APIC_NMI_STRUCTURE), // Length\r
+  0x01,                                           // ACPI Processor ID\r
+  0x000D,                                         // Flags - Level-tiggered, Active High\r
+  0x01,                                           // Local APIC LINT#\r
+  EFI_ACPI_3_0_LOCAL_APIC_NMI,                    // Type\r
+  sizeof (EFI_ACPI_3_0_LOCAL_APIC_NMI_STRUCTURE), // Length\r
+  0x02,                                           // ACPI Processor ID\r
+  0x000D,                                         // Flags - Level-tiggered, Active High\r
+  0x01,                                           // Local APIC LINT#\r
+  EFI_ACPI_3_0_LOCAL_APIC_NMI,                    // Type\r
+  sizeof (EFI_ACPI_3_0_LOCAL_APIC_NMI_STRUCTURE), // Length\r
+  0x03,                                           // ACPI Processor ID\r
+  0x000D,                                         // Flags - Level-tiggered, Active High\r
+  0x01,                                           // Local APIC LINT#\r
+  EFI_ACPI_3_0_LOCAL_APIC_NMI,                    // Type\r
+  sizeof (EFI_ACPI_3_0_LOCAL_APIC_NMI_STRUCTURE), // Length\r
+  0x04,                                           // ACPI Processor ID\r
+  0x000D,                                         // Flags - Level-tiggered, Active High\r
+  0x01,                                           // Local APIC LINT#\r
+};\r
+\r
+VOID*\r
+ReferenceAcpiTable (\r
+  VOID\r
+  )\r
+{\r
+  //\r
+  // Reference the table being generated to prevent the optimizer from\r
+  // removing the data structure from the executable\r
+  //\r
+  return (VOID*)&Madt;\r
+}\r

diff --git a/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/Mcfg/Mcfg.aslc b/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/Mcfg/Mcfg.aslc
new file mode 100644 (file)
index 0000000..0683ca4
--- /dev/null
+++ b/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/Mcfg/Mcfg.aslc
@@ -0,0 +1,92 @@
+/*++\r
+\r
+  Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+\r
+  This program and the accompanying materials are licensed and made available under\r
+  the terms and conditions of the BSD License that accompanies this distribution.\r
+  The full text of the license may be found at\r
+  http://opensource.org/licenses/bsd-license.php.\r
+\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+\r
+Module Name:\r
+\r
+  Mcfg.c\r
+\r
+Abstract:\r
+\r
+  This file contains a structure definition for the ACPI Memory mapped\r
+  configuration space base address Description Table (MCFG).  Any changes\r
+  to the MCFG table require updating the respective structure count in\r
+  Mcfg.h and then adding the structure to the MCFG defined in this file.\r
+  The table layout is defined in Mcfg.h and the table contents are defined\r
+  in McfgTable.h and Mcfg.h.\r
+\r
+--*/\r
+\r
+//\r
+// Statements that include other files\r
+//\r
+#include <Mcfg.h>\r
+\r
+//\r
+// MCFG Table definition\r
+//\r
+EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE MCFG = {\r
+  EFI_ACPI_3_0_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE_SIGNATURE,\r
+  sizeof (EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE),\r
+  EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE_REVISION,\r
+  //\r
+  // Checksum will be updated at runtime\r
+  //\r
+  0x00,\r
+  //\r
+  // It is expected that these values will be programmed at runtime\r
+  //\r
+  ' ',\r
+  ' ',\r
+  ' ',\r
+  ' ',\r
+  ' ',\r
+  ' ',\r
+\r
+  0,\r
+  EFI_ACPI_OEM_MCFG_REVISION,\r
+  0,\r
+  0,\r
+  //\r
+  // Beginning of MCFG specific fields\r
+  //\r
+  EFI_ACPI_RESERVED_QWORD,\r
+  //\r
+  // Sample Memory Mapped Configuration Space Base Address Structure\r
+  //\r
+  // 0x0,                                                              // Base Address\r
+  // 0x0,                                                              // PCI Segment Group Number\r
+  // 0x0,                                                              // Start Bus Number\r
+  // 0x0,                                                              // End Bus Number\r
+  // EFI_ACPI_RESERVED_DWORD,                                          // Reserved\r
+  //\r
+  // Memory Mapped Configuration Space Base Address Structure\r
+  //\r
+  0x0,                      // Base Address, will be updated by AcpiPlatform\r
+  0x0,                      // PCI Segment Group Number\r
+  0x0,                      // Start Bus Number\r
+  PLATFORM_MAX_BUS_NUM,     // End Bus Number\r
+  EFI_ACPI_RESERVED_DWORD,  // Reserved\r
+};\r
+\r
+VOID*\r
+ReferenceAcpiTable (\r
+  VOID\r
+  )\r
+{\r
+  //\r
+  // Reference the table being generated to prevent the optimizer from\r
+  // removing the data structure from the executable\r
+  //\r
+  return (VOID*)&MCFG;\r
+}\r

diff --git a/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/PCI_DRC.ASL b/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/PCI_DRC.ASL
new file mode 100644 (file)
index 0000000..73b3d4d
--- /dev/null
+++ b/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/PCI_DRC.ASL
@@ -0,0 +1,96 @@
+/**************************************************************************;\r
+;*                                                                        *;\r
+;*                                                                        *;\r
+;*    Intel Corporation - ACPI Reference Code for the Baytrail            *;\r
+;*    Family of Customer Reference Boards.                                *;\r
+;*                                                                        *;\r
+;*                                                                        *;\r
+;*    Copyright (c) 2012  - 2014, Intel Corporation. All rights reserved    *;\r
+;\r
+; This program and the accompanying materials are licensed and made available under\r
+; the terms and conditions of the BSD License that accompanies this distribution.\r
+; The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php.\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+;*                                                                        *;\r
+;*                                                                        *;\r
+;**************************************************************************/\r
+\r
+\r
+\r
+Scope (\_SB.PCI0)\r
+{\r
+\r
+  Device(PDRC)   // PCI Device Resource Consumption\r
+  {\r
+    Name(_HID,EISAID("PNP0C02"))\r
+\r
+    Name(_UID,1)\r
+\r
+    Name(BUF0,ResourceTemplate()\r
+    {\r
+      //\r
+      // PCI Express BAR _BAS and _LEN will be updated in _CRS below according to B0:D0:F0:Reg.60h\r
+      // Forced hard code at the moment.\r
+      //\r
+      //Memory32Fixed(ReadWrite,0,0,PCIX)       // PCIEX BAR\r
+      Memory32Fixed(ReadWrite,0x0E0000000,0x010000000,PCIX)\r
+\r
+      //\r
+      // SPI BAR. Check if the hard code meets the real configuration.\r
+      // If not, dynamically update it like the _CRS method below.\r
+      //\r
+      Memory32Fixed(ReadWrite,0x0FED01000,0x01000,SPIB) // SPI BAR\r
+\r
+      //\r
+      // PMC BAR. Check if the hard code meets the real configuration.\r
+      // If not, dynamically update it like the _CRS method below.\r
+      //\r
+      Memory32Fixed(ReadWrite,0x0FED03000,0x01000,PMCB) // PMC BAR\r
+\r
+      //\r
+      // SMB BAR. Check if the hard code meets the real configuration.\r
+      // If not, dynamically update it like the _CRS method below.\r
+      //\r
+      Memory32Fixed(ReadWrite,0x0FED04000,0x01000,SMBB) // SMB BAR\r
+\r
+      //\r
+      // IO BAR. Check if the hard code meets the real configuration.\r
+      // If not, dynamically update it like the _CRS method below.\r
+      //\r
+      Memory32Fixed(ReadWrite,0x0FED0C000,0x04000,IOBR) // IO BAR\r
+\r
+      //\r
+      // ILB BAR. Check if the hard code meets the real configuration.\r
+      // If not, dynamically update it like the _CRS method below.\r
+      //\r
+      Memory32Fixed(ReadWrite,0x0FED08000,0x01000,ILBB) // ILB BAR\r
+\r
+      //\r
+      // RCRB BAR _BAS will be updated in _CRS below according to B0:D31:F0:Reg.F0h\r
+      //\r
+      Memory32Fixed(ReadWrite,0x0FED1C000,0x01000,RCRB) // RCRB BAR\r
+\r
+      //\r
+      // Local APIC range(0xFEE0_0000 to 0xFEEF_FFFF)\r
+      //\r
+      Memory32Fixed (ReadOnly, 0x0FEE00000, 0x0100000, LIOH)\r
+\r
+      //\r
+      // MPHY BAR. Check if the hard code meets the real configuration.\r
+      // If not, dynamically update it like the _CRS method below.\r
+      //\r
+      Memory32Fixed(ReadWrite,0x0FEF00000,0x0100000,MPHB)       // MPHY BAR\r
+    })\r
+\r
+    Method(_CRS,0,Serialized)\r
+    {\r
+\r
+      Return(BUF0)\r
+    }\r
+\r
+  }\r
+}\r

diff --git a/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/Pch.asl b/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/Pch.asl
new file mode 100644 (file)
index 0000000..38dac87
--- /dev/null
+++ b/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/Pch.asl
@@ -0,0 +1,685 @@
+/**************************************************************************;\r
+;*                                                                        *;\r
+;*                                                                        *;\r
+;*    Intel Corporation - ACPI Reference Code for the Baytrail            *;\r
+;*    Family of Customer Reference Boards.                                *;\r
+;*                                                                        *;\r
+;*                                                                        *;\r
+;*    Copyright (c) 2012  - 2014, Intel Corporation. All rights reserved    *;\r
+;\r
+; This program and the accompanying materials are licensed and made available under\r
+; the terms and conditions of the BSD License that accompanies this distribution.\r
+; The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php.\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+;*                                                                        *;\r
+;*                                                                        *;\r
+;**************************************************************************/\r
+\r
+\r
+Scope(\)\r
+{\r
+  //\r
+  // Define VLV ABASE I/O as an ACPI operating region. The base address\r
+  // can be found in Device 31, Registers 40-43h.\r
+  //\r
+  OperationRegion(PMIO, SystemIo, \PMBS, 0x46)\r
+  Field(PMIO, ByteAcc, NoLock, Preserve)\r
+  {\r
+    ,      8,\r
+    PWBS,  1,       // Power Button Status\r
+    Offset(0x20),\r
+    ,      13,\r
+    PMEB,  1,     // PME_B0_STS\r
+    Offset(0x42),     // General Purpose Control\r
+    ,      1,\r
+    GPEC,  1\r
+  }\r
+  Field(PMIO, ByteAcc, NoLock, WriteAsZeros)\r
+  {\r
+    Offset(0x20),     // GPE0 Status\r
+    ,      4,\r
+    PSCI,  1,       // PUNIT SCI Status\r
+    SCIS,  1        // GUNIT SCI Status\r
+  }\r
+\r
+\r
+\r
+  //\r
+  // Define a Memory Region that will allow access to the PMC\r
+  // Register Block.  Note that in the Intel Reference Solution, the PMC\r
+  // will get fixed up dynamically during POST.\r
+  //\r
+  OperationRegion(PMCR, SystemMemory, \PFDR, 0x04)// PMC Function Disable Register\r
+  Field(PMCR,DWordAcc,Lock,Preserve)\r
+  {\r
+    Offset(0x00),   //  Function Disable Register\r
+    L10D,  1,         //  (0) LPIO1 DMA Disable\r
+    L11D,  1,         //  (1) LPIO1 PWM #1 Disable\r
+    L12D,  1,         //  (2) LPIO1 PWM #2 Disable\r
+    L13D,  1,         //  (3) LPIO1 HS-UART #1 Disable\r
+    L14D,  1,         //  (4) LPIO1 HS-UART #2 Disable\r
+    L15D,  1,         //  (5) LPIO1 SPI Disable\r
+    ,          2,     //  (6:7) Reserved\r
+    SD1D,  1,         //  (8) SCC SDIO #1 Disable\r
+    SD2D,  1,         //  (9) SCC SDIO #2 Disable\r
+    SD3D,  1,         //  (10) SCC SDIO #3 Disable\r
+    HSID,  1,         //  (11)\r
+    HDAD,  1,         //  (12) Azalia Disable\r
+    LPED,  1,         //  (13) LPE Disable\r
+    OTGD,  1,         //  (14) USB OTG Disable\r
+    ,          1,     //  (15) USH Disable\r
+    ,          1,     //  (16)\r
+    ,          1,     //  (17)\r
+    ,          1,     //  (18) USB Disable\r
+    ,          1,     //  (19) SEC Disable\r
+    RP1D,  1,         //  (20) Root Port 0 Disable\r
+    RP2D,  1,         //  (21) Root Port 1 Disable\r
+    RP3D,  1,         //  (22) Root Port 2 Disable\r
+    RP4D,  1,         //  (23) Root Port 3 Disable\r
+    L20D,  1,         //  (24) LPIO2 DMA Disable\r
+    L21D,  1,         //  (25) LPIO2 I2C #1 Disable\r
+    L22D,  1,         //  (26) LPIO2 I2C #2 Disable\r
+    L23D,  1,         //  (27) LPIO2 I2C #3 Disable\r
+    L24D,  1,         //  (28) LPIO2 I2C #4 Disable\r
+    L25D,  1,         //  (29) LPIO2 I2C #5 Disable\r
+    L26D,  1,         //  (30) LPIO2 I2C #6 Disable\r
+    L27D,  1          //  (31) LPIO2 I2C #7 Disable\r
+  }\r
+\r
+\r
+  OperationRegion(CLKC, SystemMemory, \PCLK, 0x18)// PMC CLK CTL Registers\r
+  Field(CLKC,DWordAcc,Lock,Preserve)\r
+  {\r
+    Offset(0x00),   //  PLT_CLK_CTL_0\r
+    CKC0, 2,\r
+    CKF0, 1,\r
+    ,     29,\r
+    Offset(0x04),   //  PLT_CLK_CTL_1\r
+    CKC1, 2,\r
+    CKF1, 1,\r
+    ,     29,\r
+    Offset(0x08),   //  PLT_CLK_CTL_2\r
+    CKC2,  2,\r
+    CKF2, 1,\r
+    ,     29,\r
+    Offset(0x0C),   //  PLT_CLK_CTL_3\r
+    CKC3,  2,\r
+    CKF3, 1,\r
+    ,     29,\r
+    Offset(0x10),   //  PLT_CLK_CTL_4\r
+    CKC4,  2,\r
+    CKF4, 1,\r
+    ,     29,\r
+    Offset(0x14),   //  PLT_CLK_CTL_5\r
+    CKC5,  2,\r
+    CKF5, 1,\r
+    ,     29,\r
+  }\r
+} //end Scope(\)\r
+\r
+scope (\_SB)\r
+{\r
+  Device(LPEA)\r
+  {\r
+    Name (_ADR, 0)\r
+    Name (_HID, "80860F28")\r
+    Name (_CID, "80860F28")\r
+    //Name (_CLS, Package (3) {0x04, 0x01, 0x00})\r
+    Name (_DDN, "Intel(R) Low Power Audio Controller - 80860F28")\r
+    Name (_SUB, "80867270")\r
+    Name (_UID, 1)\r
+    Name (_DEP, Package() {\_SB.I2C2.RTEK})\r
+    Name(_PR0,Package() {PLPE})\r
+\r
+    Method (_STA, 0x0, NotSerialized)\r
+    {\r
+      If (LAnd(LAnd(LEqual(LPEE, 2), LEqual(LPED, 0)), LEqual(OSEL, 0)))\r
+      {\r
+        Return (0xF)\r
+      }\r
+      Return (0x0)\r
+    }\r
+\r
+    Method (_DIS, 0x0, NotSerialized)\r
+    {\r
+      //Add a dummy disable function\r
+    }\r
+\r
+    Name (RBUF, ResourceTemplate ()\r
+      {\r
+        Memory32Fixed (ReadWrite, 0xFE400000, 0x00200000, BAR0)  // MMIO 1 - LPE MMIO\r
+        Memory32Fixed (ReadWrite, 0xFE830000, 0x00001000, BAR1)  // MMIO 2 - Shadowed PCI Config Space\r
+        Memory32Fixed (ReadWrite, 0x55AA55AA, 0x00100000, BAR2)  // LPE Memory Bar Allocate during post\r
+        Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , ) {24}\r
+        Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , ) {25}\r
+        Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , ) {26}\r
+        Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , ) {27}\r
+        Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , ) {28}\r
+        Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , ) {29}\r
+        GpioInt(Edge, ActiveBoth, ExclusiveAndWake, PullNone, 0,"\\_SB.GPO2") {28} //  Audio jack interrupt\r
+      }\r
+    )\r
+\r
+    Method (_CRS, 0x0, NotSerialized)\r
+    {\r
+      CreateDwordField(^RBUF, ^BAR0._BAS, B0BA)\r
+      Store(LPE0, B0BA)\r
+      CreateDwordField(^RBUF, ^BAR1._BAS, B1BA)\r
+      Store(LPE1, B1BA)\r
+      CreateDwordField(^RBUF, ^BAR2._BAS, B2BA)\r
+      Store(LPE2, B2BA)\r
+      Return (RBUF)\r
+    }\r
+\r
+    OperationRegion (KEYS, SystemMemory, LPE1, 0x100)\r
+    Field (KEYS, DWordAcc, NoLock, WriteAsZeros)\r
+    {\r
+      Offset (0x84),\r
+      PSAT,   32\r
+    }\r
+\r
+    PowerResource(PLPE, 0, 0)   // Power Resource for LPEA\r
+    {\r
+      Method (_STA)\r
+      {\r
+        Return (1)      // Power Resource is always available.\r
+      }\r
+\r
+      Method (_ON)\r
+      {\r
+        And(PSAT, 0xfffffffC, PSAT)\r
+        OR(PSAT, 0X00000000, PSAT)\r
+      }\r
+\r
+      Method (_OFF)\r
+      {\r
+        OR(PSAT, 0x00000003, PSAT)\r
+        OR(PSAT, 0X00000000, PSAT)\r
+      }\r
+    } // End PLPE\r
+  } // End "Low Power Engine Audio"\r
+\r
+  Device(LPA2)\r
+  {\r
+    Name (_ADR, 0)\r
+    Name (_HID, "LPE0F28")  // _HID: Hardware ID\r
+    Name (_CID, "LPE0F28")  // _CID: Compatible ID\r
+    Name (_DDN, "Intel(R) SST Audio - LPE0F28")  // _DDN: DOS Device Name\r
+    Name (_SUB, "80867270")\r
+    Name (_UID, 1)\r
+    Name (_DEP, Package() {\_SB.I2C2.RTEK})\r
+    Name(_PR0,Package() {PLPE})\r
+\r
+    Method (_STA, 0x0, NotSerialized)\r
+    {\r
+      If (LAnd(LAnd(LEqual(LPEE, 2), LEqual(LPED, 0)), LEqual(OSEL, 1)))\r
+      {\r
+        Return (0xF)\r
+      }\r
+      Return (0x0)\r
+    }\r
+\r
+    Method (_DIS, 0x0, NotSerialized)\r
+    {\r
+      //Add a dummy disable function\r
+    }\r
+\r
+    Name (RBUF, ResourceTemplate ()\r
+      {\r
+        Memory32Fixed (ReadWrite, 0x55AA55AA, 0x00100000, BAR2)  // LPE Memory Bar Allocate during post\r
+        Memory32Fixed (ReadWrite, 0x55AA55AA, 0x00000100, SHIM)\r
+        Memory32Fixed (ReadWrite, 0x55AA55AA, 0x00001000, MBOX)\r
+        Memory32Fixed (ReadWrite, 0x55AA55AA, 0x00014000, IRAM)\r
+        Memory32Fixed (ReadWrite, 0x55AA55AA, 0x00028000, DRAM)\r
+        Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , ) {29}\r
+        Memory32Fixed (ReadWrite, 0xFE830000, 0x00001000, BAR1)  // MMIO 2 - Shadowed PCI Config Space\r
+      }\r
+    )\r
+\r
+    Method (_CRS, 0x0, NotSerialized)\r
+    {\r
+      CreateDwordField(^RBUF, ^SHIM._BAS, SHBA)\r
+      Add(LPE0, 0x140000, SHBA)\r
+      CreateDwordField(^RBUF, ^MBOX._BAS, MBBA)\r
+      Add(LPE0, 0x144000, MBBA)\r
+      CreateDwordField(^RBUF, ^IRAM._BAS, IRBA)\r
+      Add(LPE0, 0xC0000, IRBA)\r
+      CreateDwordField(^RBUF, ^DRAM._BAS, DRBA)\r
+      Add(LPE0, 0x100000, DRBA)\r
+      CreateDwordField(^RBUF, ^BAR1._BAS, B1BA)\r
+      Store(LPE1, B1BA)\r
+      CreateDwordField(^RBUF, ^BAR2._BAS, B2BA)\r
+      Store(LPE2, B2BA)\r
+      Return (RBUF)\r
+    }\r
+\r
+    OperationRegion (KEYS, SystemMemory, LPE1, 0x100)\r
+    Field (KEYS, DWordAcc, NoLock, WriteAsZeros)\r
+    {\r
+      Offset (0x84),\r
+      PSAT,   32\r
+    }\r
+\r
+    PowerResource(PLPE, 0, 0)   // Power Resource for LPEA\r
+    {\r
+      Method (_STA)\r
+      {\r
+        Return (1)      // Power Resource is always available.\r
+      }\r
+\r
+      Method (_ON)\r
+      {\r
+        And(PSAT, 0xfffffffC, PSAT)\r
+        OR(PSAT, 0X00000000, PSAT)\r
+      }\r
+\r
+      Method (_OFF)\r
+      {\r
+        OR(PSAT, 0x00000003, PSAT)\r
+        OR(PSAT, 0X00000000, PSAT)\r
+      }\r
+    } // End PLPE\r
+\r
+    Device (ADMA)\r
+    {\r
+      Name (_ADR, Zero)  // _ADR: Address\r
+      Name (_HID, "DMA0F28")  // _HID: Hardware ID\r
+      Name (_CID, "DMA0F28")  // _CID: Compatible ID\r
+      Name (_DDN, "Intel(R) Audio  DMA0 - DMA0F28")  // _DDN: DOS Device Name\r
+      Name (_UID, One)  // _UID: Unique ID\r
+      Name (RBUF, ResourceTemplate ()\r
+      {\r
+        Memory32Fixed (ReadWrite, 0x55AA55AA, 0x00001000, DMA0)  // LPE BASE + LPE DMA0 offset\r
+        Memory32Fixed (ReadWrite, 0x55AA55AA, 0x00001000, SHIM)  // LPE BASE + LPE SHIM offset\r
+        Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , ) {24}\r
+      })\r
+\r
+      Method (_CRS, 0, NotSerialized)   // _CRS: Current Resource Settings\r
+      {\r
+        CreateDwordField(^RBUF, ^DMA0._BAS, D0BA)\r
+        Add(LPE0, 0x98000, D0BA)\r
+        CreateDwordField(^RBUF, ^SHIM._BAS, SHBA)\r
+        Add(LPE0, 0x140000, SHBA)\r
+        Return (RBUF)\r
+      }\r
+    }\r
+  } // End "Low Power Engine Audio" for Android\r
+}\r
+\r
+scope (\_SB.PCI0)\r
+{\r
+\r
+  //\r
+  // Serial ATA Host Controller - Device 19, Function 0\r
+  //\r
+\r
+  Device(SATA)\r
+  {\r
+    Name(_ADR,0x00130000)\r
+    //\r
+    // SATA Methods pulled in via SSDT.\r
+    //\r
+\r
+    OperationRegion(SATR, PCI_Config, 0x74,0x4)\r
+    Field(SATR,WordAcc,NoLock,Preserve)\r
+    {\r
+      Offset(0x00), // 0x74, PMCR\r
+      ,   8,\r
+      PMEE,   1,    //PME_EN\r
+      ,   6,\r
+      PMES,   1     //PME_STS\r
+    }\r
+\r
+    Method (_STA, 0x0, NotSerialized)\r
+    {\r
+      Return(0xf)\r
+    }\r
+\r
+    Method(_DSW, 3)\r
+    {\r
+    } // End _DSW\r
+  }\r
+\r
+  //\r
+  // For eMMC 4.41 PCI mode in order to present non-removable device under Windows environment\r
+  //\r
+  Device(EM41)\r
+  {\r
+    Name(_ADR,0x00100000)\r
+    OperationRegion(SDIO, PCI_Config, 0x84,0x4)\r
+    Field(SDIO,WordAcc,NoLock,Preserve)\r
+    {\r
+      Offset(0x00), // 0x84, PMCR\r
+      ,   8,\r
+      PMEE,   1,    //PME_EN\r
+      ,   6,\r
+      PMES,   1     //PME_STS\r
+    }\r
+\r
+    Method (_STA, 0x0, NotSerialized)\r
+    {\r
+      If (LAnd(LEqual(PCIM, 1), LEqual(SD1D, 0)))\r
+      {\r
+        Return(0xF)\r
+      }\r
+      Else\r
+      {\r
+        Return(0x0)\r
+      }\r
+    }\r
+\r
+    Method(_DSW, 3)\r
+    {\r
+    } // End _DSW\r
+\r
+    Device (CARD)\r
+    {\r
+      Name (_ADR, 0x00000008)\r
+      Method(_RMV, 0x0, NotSerialized)\r
+      {\r
+        Return (0)\r
+      } // End _DSW\r
+    }\r
+  }\r
+\r
+  //\r
+  // For eMMC 4.5 PCI mode in order to present non-removable device under Windows environment\r
+  //\r
+  Device(EM45)\r
+  {\r
+    Name(_ADR,0x00170000)\r
+    OperationRegion(SDIO, PCI_Config, 0x84,0x4)\r
+    Field(SDIO,WordAcc,NoLock,Preserve)\r
+    {\r
+      Offset(0x00), // 0x84, PMCR\r
+      ,   8,\r
+      PMEE,   1,    //PME_EN\r
+      ,   6,\r
+      PMES,   1     //PME_STS\r
+    }\r
+\r
+    Method (_STA, 0x0, NotSerialized)\r
+    {\r
+      If (LAnd(LEqual(PCIM, 1), LEqual(HSID, 0)))\r
+      {\r
+        Return(0xF)\r
+      }\r
+      Else\r
+      {\r
+        Return(0x0)\r
+      }\r
+    }\r
+\r
+    Method(_DSW, 3)\r
+    {\r
+    } // End _DSW\r
+\r
+    Device (CARD)\r
+    {\r
+      Name (_ADR, 0x00000008)\r
+      Method(_RMV, 0x0, NotSerialized)\r
+      {\r
+        Return (0)\r
+      } // End _DSW\r
+    }\r
+  }\r
+  //\r
+  // For SD Host Controller (Bus 0x00 : Dev 0x12 : Func 0x00) PCI mode in order to present non-removable device under Windows environment\r
+  //\r
+  Device(SD12)\r
+  {\r
+    Name(_ADR,0x00120000)\r
+\r
+    Method (_STA, 0x0, NotSerialized)\r
+    {\r
+      //\r
+      // PCIM>> 0:ACPI mode           1:PCI mode\r
+      //\r
+      If (LEqual(PCIM, 0)) {\r
+        Return (0x0)\r
+      }\r
+\r
+      //\r
+      // If device is disabled.\r
+      //\r
+      If (LEqual(SD3D, 1))\r
+      {\r
+        Return (0x0)\r
+      }\r
+\r
+      Return (0xF)\r
+    }\r
+\r
+    Device (CARD)\r
+    {\r
+      Name (_ADR, 0x00000008)\r
+      Method(_RMV, 0x0, NotSerialized)\r
+      {\r
+        // SDRM = 0 non-removable;\r
+        If (LEqual(SDRM, 0))\r
+        {\r
+          Return (0)\r
+        }\r
+\r
+        Return (1)\r
+      }\r
+    }\r
+  }\r
+\r
+  // xHCI Controller - Device 20, Function 0\r
+  include("PchXhci.asl")\r
+\r
+  //\r
+  // High Definition Audio Controller - Device 27, Function 0\r
+  //\r
+  Device(HDEF)\r
+  {\r
+    Name(_ADR, 0x001B0000)\r
+    include("PchAudio.asl")\r
+\r
+    Method (_STA, 0x0, NotSerialized)\r
+    {\r
+      If (LEqual(HDAD, 0))\r
+      {\r
+        Return(0xf)\r
+      }\r
+      Return(0x0)\r
+    }\r
+\r
+    Method(_DSW, 3)\r
+    {\r
+    } // End _DSW\r
+  } // end "High Definition Audio Controller"\r
+\r
+\r
+\r
+  //\r
+  // PCIE Root Port #1\r
+  //\r
+  Device(RP01)\r
+  {\r
+    Name(_ADR, 0x001C0000)\r
+    include("PchPcie.asl")\r
+    Name(_PRW, Package() {9, 4})\r
+\r
+    Method(_PRT,0)\r
+    {\r
+      If(PICM) { Return(AR04) }// APIC mode\r
+      Return (PR04) // PIC Mode\r
+    } // end _PRT\r
+  } // end "PCIE Root Port #1"\r
+\r
+  //\r
+  // PCIE Root Port #2\r
+  //\r
+  Device(RP02)\r
+  {\r
+    Name(_ADR, 0x001C0001)\r
+    include("PchPcie.asl")\r
+    Name(_PRW, Package() {9, 4})\r
+\r
+    Method(_PRT,0)\r
+    {\r
+      If(PICM) { Return(AR05) }// APIC mode\r
+      Return (PR05) // PIC Mode\r
+    } // end _PRT\r
+\r
+  } // end "PCIE Root Port #2"\r
+\r
+  //\r
+  // PCIE Root Port #3\r
+  //\r
+  Device(RP03)\r
+  {\r
+    Name(_ADR, 0x001C0002)\r
+    include("PchPcie.asl")\r
+    Name(_PRW, Package() {9, 4})\r
+    Method(_PRT,0)\r
+    {\r
+      If(PICM) { Return(AR06) }// APIC mode\r
+      Return (PR06) // PIC Mode\r
+    } // end _PRT\r
+\r
+  } // end "PCIE Root Port #3"\r
+\r
+  //\r
+  // PCIE Root Port #4\r
+  //\r
+  Device(RP04)\r
+  {\r
+    Name(_ADR, 0x001C0003)\r
+    include("PchPcie.asl")\r
+    Name(_PRW, Package() {9, 4})\r
+    Method(_PRT,0)\r
+    {\r
+      If(PICM) { Return(AR07) }// APIC mode\r
+      Return (PR07) // PIC Mode\r
+    } // end _PRT\r
+\r
+  } // end "PCIE Root Port #4"\r
+\r
+\r
+  Scope(\_SB)\r
+  {\r
+    //\r
+    // Dummy power resource for USB D3 cold support\r
+    //\r
+    PowerResource(USBC, 0, 0)\r
+    {\r
+      Method(_STA) { Return (0xF) }\r
+      Method(_ON) {}\r
+      Method(_OFF) {}\r
+    }\r
+  }\r
+  //\r
+  // EHCI Controller - Device 29, Function 0\r
+  //\r
+  Device(EHC1)\r
+  {\r
+    Name(_ADR, 0x001D0000)\r
+    Name(_DEP, Package(0x1)\r
+    {\r
+      PEPD\r
+    })\r
+    include("PchEhci.asl")\r
+    Name(_PRW, Package() {0x0D, 4})\r
+\r
+    OperationRegion(USBR, PCI_Config, 0x54,0x4)\r
+    Field(USBR,WordAcc,NoLock,Preserve)\r
+    {\r
+      Offset(0x00), // 0x54, PMCR\r
+      ,   8,\r
+      PMEE,   1,    //PME_EN\r
+      ,   6,\r
+      PMES,   1     //PME_STS\r
+    }\r
+\r
+    Method (_STA, 0x0, NotSerialized)\r
+    {\r
+      If(LEqual(XHCI, 0))      //XHCI is not present. It means EHCI is there\r
+      {\r
+        Return (0xF)\r
+      } Else\r
+      {\r
+        Return (0x0)\r
+      }\r
+    }\r
+\r
+    Method (_RMV, 0, NotSerialized)\r
+    {\r
+      Return (0x0)\r
+    }\r
+    //\r
+    // Create a dummy PR3 method to indicate to the PCI driver\r
+    // that the device is capable of D3 cold\r
+    //\r
+    Method(_PR3, 0x0, NotSerialized)\r
+    {\r
+      return (Package() {\_SB.USBC})\r
+    }\r
+\r
+  } // end "EHCI Controller"\r
+\r
+  //\r
+  // SMBus Controller - Device 31, Function 3\r
+  //\r
+  Device(SBUS)\r
+  {\r
+    Name(_ADR,0x001F0003)\r
+    Include("PchSmb.asl")\r
+  }\r
+\r
+  Device(SEC0)\r
+  {\r
+    Name (_ADR, 0x001a0000)                     // Device 0x1a, Function 0\r
+    Name(_DEP, Package(0x1)\r
+    {\r
+      PEPD\r
+    })\r
+\r
+\r
+    OperationRegion (PMEB, PCI_Config, 0x84, 0x04)  //PMECTRLSTATUS\r
+    Field (PMEB, WordAcc, NoLock, Preserve)\r
+    {\r
+      ,   8,\r
+      PMEE,   1,    //bit8 PMEENABLE\r
+      ,   6,\r
+      PMES,   1     //bit15 PMESTATUS\r
+    }\r
+\r
+    // Arg0 -- integer that contains the device wake capability control (0-disable 1- enable)\r
+    // Arg1 -- integer that contains target system state (0-4)\r
+    // Arg2 -- integer that contains the target device state\r
+    Method (_DSW, 3, NotSerialized)   // _DSW: Device Sleep Wake\r
+    {\r
+    }\r
+\r
+    Method (_CRS, 0, NotSerialized)\r
+    {\r
+      Name (RBUF, ResourceTemplate ()\r
+      {\r
+        Memory32Fixed (ReadWrite, 0x1e000000, 0x2000000)\r
+      })\r
+\r
+      If (LEqual(PAVP, 2))\r
+      {\r
+        Return (RBUF)\r
+      }\r
+      Return (ResourceTemplate() {})\r
+    }\r
+\r
+    Method (_STA)\r
+    {\r
+      If (LNotEqual(PAVP, 0))\r
+      {\r
+        Return (0xF)\r
+      }\r
+      Return (0x0)\r
+    }\r
+  }   // Device(SEC0)\r
+\r
+} // End scope (\_SB.PCI0)\r

diff --git a/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/PchAudio.asl b/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/PchAudio.asl
new file mode 100644 (file)
index 0000000..7c93c3a
--- /dev/null
+++ b/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/PchAudio.asl
@@ -0,0 +1,42 @@
+/**************************************************************************;\r
+;*                                                                        *;\r
+;*                                                                        *;\r
+;*    Intel Corporation - ACPI Reference Code for the Baytrail            *;\r
+;*    Family of Customer Reference Boards.                                *;\r
+;*                                                                        *;\r
+;*                                                                        *;\r
+;*    Copyright (c)  2011  - 2014, Intel Corporation. All rights reserved   *;\r
+;\r
+; This program and the accompanying materials are licensed and made available under\r
+; the terms and conditions of the BSD License that accompanies this distribution.\r
+; The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php.\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+;*                                                                        *;\r
+;*                                                                        *;\r
+;**************************************************************************/\r
+//\r
+// High Definition Audio - Device 27, Function 0\r
+//\r
+OperationRegion(HDAR, PCI_Config, 0x4C,0x10)\r
+Field(HDAR,WordAcc,NoLock,Preserve)\r
+{\r
+  Offset(0x00), // 0x4C, Dock Control Register\r
+  DCKA,    1,   // Dock Attach\r
+  ,    7,\r
+  Offset(0x01), // 04Dh, Dock Status Register\r
+  DCKM,    1,   // Dock Mated\r
+  ,    6,\r
+  DCKS,    1,   // Docking Supported\r
+  Offset(0x08), // 0x54, Power Management Control and Status Register\r
+  ,    8,\r
+  PMEE,    1,   // PME_EN\r
+  ,    6,\r
+  PMES,    1    // PME Status\r
+}\r
+\r
+\r
+\r

diff --git a/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/PchEhci.asl b/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/PchEhci.asl
new file mode 100644 (file)
index 0000000..84626e3
--- /dev/null
+++ b/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/PchEhci.asl
@@ -0,0 +1,275 @@
+/***************************************************************************************;\r
+;*                                                                                     *;\r
+;*                                                                                     *;\r
+;*    Intel Corporation - ACPI Reference Code for the Baytrail                         *;\r
+;*    Family of Customer Reference Boards.                                             *;\r
+;*                                                                                     *;\r
+;*                                                                                     *;\r
+;*    Copyright (c)  2011  - 2014, Intel Corporation. All rights reserved              *;\r
+;*                                                                                     *;\r
+;*   This program and the accompanying materials are licensed and made available under *;\r
+;*   the terms and conditions of the BSD License that accompanies this distribution.   *;\r
+;*   The full text of the license may be found at                                      *;\r
+;*   http://opensource.org/licenses/bsd-license.php.                                   *;\r
+;*                                                                                     *;\r
+;*   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,             *;\r
+;*   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.     *;\r
+;*                                                                                     *;\r
+;*                                                                                     *;\r
+;*                                                                                     *;\r
+;***************************************************************************************/\r
+\r
+OperationRegion(PWKE,PCI_Config,0x62,0x04)\r
+\r
+Field(PWKE,DWordAcc,NoLock,Preserve)\r
+{\r
+  , 1,\r
+  PWUC, 8 // Port Wake Up Capability Mask\r
+}\r
+\r
+Method(_PSW,1)\r
+{\r
+  If(Arg0)\r
+  {\r
+    Store(Ones,PWUC)\r
+  }\r
+  Else\r
+  {\r
+    Store(0,PWUC)\r
+  }\r
+}\r
+\r
+// Leaves the USB ports on in S3/S4 to allow\r
+// the ability to Wake from USB.  Therefore, define\r
+// the below control methods to state D2 entry during\r
+// the given S-State.\r
+\r
+Method(_S3D,0)\r
+{\r
+  Return(2)\r
+}\r
+\r
+Method(_S4D,0)\r
+{\r
+  Return(2)\r
+}\r
+\r
+Device(HUBN)\r
+{\r
+  Name(_ADR, Zero)\r
+  Device(PR01)\r
+  {\r
+    Name(_ADR, One)\r
+\r
+    //\r
+    // There will have "Generic USB Hub" existed at Port 1 of each EHCI controller\r
+    // in Windows "Device Manager" while RMH is enabled, so need to add _UPC\r
+    // and _PLD to report OS that it's not user visible to pass WHQL: Single Computer\r
+    // Display Object test in Win7\r
+    //\r
+    Name(_UPC, Package()\r
+    {\r
+      0xFF,                       // Port is connectable\r
+      0x00,                       // Connector type - Type "A"\r
+      0x00000000,                 // Reserved 0 - must be zero\r
+      0x00000000\r
+    })                // Reserved 1 - must be zero\r
+\r
+    Name(_PLD, Package()\r
+    {\r
+      Buffer (0x10)\r
+      {\r
+        0x81, 0x00, 0x00, 0x00,     // Revision 1, Ignore color\r
+        0x00, 0x00, 0x00, 0x00,\r
+        0x30, 0x1C, 0x00, 0x00,     // Panel Unknown, Shape Unknown\r
+        0x00, 0x00, 0x00, 0x00\r
+      }\r
+    })\r
+\r
+    Device(PR11)\r
+    {\r
+      Name(_ADR, One)\r
+      Name(_UPC, Package()\r
+      {\r
+        0xFF,                       // Port is connectable\r
+        0xFF,                       // Proprietary connector\r
+        0x00000000,                 // Reserved 0 - must be zero\r
+        0x00000000\r
+      })                // Reserved 1 - must be zero\r
+      Name(_PLD, Package()\r
+      {\r
+        Buffer (0x10)\r
+        {\r
+          0x81, 0x00, 0x00, 0x00,     // Revision 1, Ignore color\r
+          0x00, 0x00, 0x00, 0x00,\r
+          0xE1, 0x1C, 0x00, 0x00,     // Front Panel, Vertical Upper, Horz. Left, Shape Unknown\r
+          0x00, 0x00, 0x00, 0x00\r
+        }\r
+      })\r
+    }\r
+\r
+    Device(PR12)\r
+    {\r
+      Name(_ADR, 0x02)\r
+      Name(_UPC, Package()\r
+      {\r
+        0xFF,                       // Port is connectable\r
+        0xFF,                       // Proprietary connector\r
+        0x00000000,                 // Reserved 0 - must be zero\r
+        0x00000000\r
+      })                // Reserved 1 - must be zero\r
+      Name(_PLD, Package()\r
+      {\r
+        Buffer (0x10)\r
+        {\r
+          0x81, 0x00, 0x00, 0x00,     // Revision 1, Ignore color\r
+          0x00, 0x00, 0x00, 0x00,\r
+          0xE1, 0x1D, 0x00, 0x00,     // Front Panel, Vertical Center, Horz. Left, Shape Unknown\r
+          0x00, 0x00, 0x00, 0x00\r
+        }\r
+      })\r
+    }\r
+\r
+    Device(PR13)\r
+    {\r
+      Name(_ADR, 0x03)\r
+      Name(_UPC, Package()\r
+      {\r
+        0xFF,                       // Port is connectable\r
+        0xFF,                       // Proprietary connector\r
+        0x00000000,                 // Reserved 0 - must be zero\r
+        0x00000000\r
+      })                // Reserved 1 - must be zero\r
+      Name(_PLD, Package()\r
+      {\r
+        Buffer (0x10)\r
+        {\r
+          0x81, 0x00, 0x00, 0x00,     // Revision 1, Ignore color\r
+          0x00, 0x00, 0x00, 0x00,\r
+          0xE1, 0x1D, 0x00, 0x00,     // Front Panel, Vertical Center, Horz. Left, Shape Unknown\r
+          0x00, 0x00, 0x00, 0x00\r
+        }\r
+      })\r
+    }\r
+\r
+    Device(PR14)\r
+    {\r
+      Name(_ADR, 0x04)\r
+      Name(_UPC, Package()\r
+      {\r
+        0xFF,                       // Port is connectable\r
+        0xFF,                       // Proprietary connector\r
+        0x00000000,                 // Reserved 0 - must be zero\r
+        0x00000000\r
+      })                // Reserved 1 - must be zero\r
+\r
+      Name(_PLD, Package()\r
+      {\r
+        Buffer (0x10)\r
+        {\r
+          0x81, 0x00, 0x00, 0x00,     // Revision 1, Ignore color\r
+          0x00, 0x00, 0x00, 0x00,\r
+          0xE1, 0x1E, 0x00, 0x00,     // Front Panel, Vertical Lower, Horz. Left, Shape Unknown\r
+          0x00, 0x00, 0x00, 0x00\r
+        }\r
+      })\r
+\r
+      // copy USB Sideband Deferring GPE Vector (HOST_ALERT#1) to DSM method\r
+      Include("UsbSbd.asl")\r
+    }\r
+\r
+    Device(PR15)\r
+    {\r
+      Name(_ADR, 0x05)\r
+      Name(_UPC, Package()\r
+      {\r
+        0xFF,                       // Port is connectable\r
+        0xFF,                       // Proprietary connector\r
+        0x00000000,                 // Reserved 0 - must be zero\r
+        0x00000000\r
+      })                // Reserved 1 - must be zero\r
+      Name(_PLD, Package()\r
+      {\r
+        Buffer (0x10)\r
+        {\r
+          0x81, 0x00, 0x00, 0x00,     // Revision 1, Ignore color\r
+          0x00, 0x00, 0x00, 0x00,\r
+          0xB1, 0x1E, 0x00, 0x00,     // Panel Unknown, Shape Unknown\r
+          0x00, 0x00, 0x00, 0x00\r
+        }\r
+      })\r
+      // copy USB Sideband Deferring GPE Vector (HOST_ALERT#2) to DSM method\r
+      Include("UsbSbd.asl")\r
+    }\r
+\r
+    Device(PR16)\r
+    {\r
+      Name(_ADR, 0x06)\r
+      Name(_UPC, Package()\r
+      {\r
+        0xFF,                       // Port is connectable\r
+        0xFF,                       // Proprietary connector\r
+        0x00000000,                 // Reserved 0 - must be zero\r
+        0x00000000\r
+      })                // Reserved 1 - must be zero\r
+      Name(_PLD, Package()\r
+      {\r
+        Buffer (0x10)\r
+        {\r
+          0x81, 0x00, 0x00, 0x00,     // Revision 1, Ignore color\r
+          0x00, 0x00, 0x00, 0x00,\r
+          0xB1, 0x1E, 0x00, 0x00,     // Panel Unknown, Shape Unknown\r
+          0x00, 0x00, 0x00, 0x00\r
+        }\r
+      })\r
+      // copy USB Sideband Deferring GPE Vector (HOST_ALERT#1) to DSM method\r
+      Include("UsbSbd.asl")\r
+    }\r
+\r
+    Device(PR17)\r
+    {\r
+      Name(_ADR, 0x07)\r
+      Name(_UPC, Package()\r
+      {\r
+        0xFF,                       // Port is connectable\r
+        0xFF,                       // Proprietary connector\r
+        0x00000000,                 // Reserved 0 - must be zero\r
+        0x00000000\r
+      })                // Reserved 1 - must be zero\r
+      Name(_PLD, Package()\r
+      {\r
+        Buffer (0x10)\r
+        {\r
+          0x81, 0x00, 0x00, 0x00,     // Revision 1, Ignore color\r
+          0x00, 0x00, 0x00, 0x00,\r
+          0xB1, 0x1E, 0x00, 0x00,     // Panel Unknown, Shape Unknown\r
+          0x00, 0x00, 0x00, 0x00\r
+        }\r
+      })\r
+      // copy USB Sideband Deferring GPE Vector (HOST_ALERT#2) to DSM method\r
+      Include("UsbSbd.asl")\r
+    }\r
+\r
+    Device(PR18)\r
+    {\r
+      Name(_ADR, 0x08)\r
+      Name(_UPC, Package()\r
+      {\r
+        0xFF,                       // Port is connectable\r
+        0xFF,                       // Proprietary connector\r
+        0x00000000,                 // Reserved 0 - must be zero\r
+        0x00000000\r
+      })                // Reserved 1 - must be zero\r
+      Name(_PLD, Package()\r
+      {\r
+        Buffer (0x10)\r
+        {\r
+          0x81, 0x00, 0x00, 0x00,     // Revision 1, Ignore color\r
+          0x00, 0x00, 0x00, 0x00,\r
+          0xB1, 0x1E, 0x00, 0x00,     // Panel Unknown, Shape Unknown\r
+          0x00, 0x00, 0x00, 0x00\r
+        }\r
+      })\r
+    }\r
+  } // End of PR01\r
+} // End of HUBN\r

diff --git a/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/PchLpss.asl b/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/PchLpss.asl
new file mode 100644 (file)
index 0000000..3e61e79
--- /dev/null
+++ b/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/PchLpss.asl
@@ -0,0 +1,1096 @@
+/**************************************************************************;\r
+;*                                                                        *;\r
+;*                                                                        *;\r
+;*    Intel Corporation - ACPI Reference Code for the Baytrail            *;\r
+;*    Family of Customer Reference Boards.                                *;\r
+;*                                                                        *;\r
+;*                                                                        *;\r
+;*    Copyright (c) 2012  - 2014, Intel Corporation. All rights reserved    *;\r
+;\r
+; This program and the accompanying materials are licensed and made available under\r
+; the terms and conditions of the BSD License that accompanies this distribution.\r
+; The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php.\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+;*                                                                        *;\r
+;*                                                                        *;\r
+;**************************************************************************/\r
+//\r
+// LPIO1 DMA#1 (Synopsis GP DMA)\r
+//\r
+Device (GDM1)\r
+{\r
+  Name (_HID, "INTL9C60")\r
+  Name (_DDN, "Intel(R) DMA Controller #1 - INTL9C60")\r
+  Name (_UID, 1)\r
+\r
+  Name (RBUF, ResourceTemplate ()\r
+  {\r
+    Memory32Fixed (ReadWrite, 0x00000000, 0x00004000, BAR0)\r
+    Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , ) {42}  // DMA #1 IRQ\r
+  })\r
+  Method (_CRS, 0x0, NotSerialized)\r
+  {\r
+    CreateDwordField(^RBUF, ^BAR0._BAS, B0BA)\r
+    CreateDwordField(^RBUF, ^BAR0._LEN, B0LN)\r
+    Store(D10A, B0BA)\r
+    Store(D10L, B0LN)\r
+    Return (RBUF)\r
+  }\r
+  Method (_STA, 0x0, NotSerialized)\r
+  {\r
+    //\r
+    // PCIM>> 0:ACPI mode           1:PCI mode\r
+    //\r
+    If (LEqual(PCIM, 1)) {\r
+      Return (0x0)\r
+    }\r
+\r
+    If (LOr(LEqual(D10A, 0), LEqual(L10D, 1)))\r
+    {\r
+      Return (0x0)\r
+    }\r
+    Return (0xF)\r
+  }\r
+}\r
+\r
+//\r
+// LPIO1 DMA#2 (Synopsis GP DMA)\r
+//\r
+Device (GDM2)\r
+{\r
+  Name (_HID, "INTL9C60")\r
+  Name (_DDN, "Intel(R) DMA Controller #2 - INTL9C60")\r
+  Name (_UID, 2)\r
+\r
+  Name (RBUF, ResourceTemplate ()\r
+  {\r
+    Memory32Fixed (ReadWrite, 0x00000000, 0x00004000, BAR0)\r
+    Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , ) {43}  // DMA #2 IRQ\r
+  })\r
+  Method (_CRS, 0x0, NotSerialized)\r
+  {\r
+    CreateDwordField(^RBUF, ^BAR0._BAS, B0BA)\r
+    CreateDwordField(^RBUF, ^BAR0._LEN, B0LN)\r
+    Store(D20A, B0BA)\r
+    Store(D20L, B0LN)\r
+    Return (RBUF)\r
+  }\r
+  Method (_STA, 0x0, NotSerialized)\r
+  {\r
+    //\r
+    // PCIM>> 0:ACPI mode           1:PCI mode\r
+    //\r
+    If (LEqual(PCIM, 1)) {\r
+      Return (0x0)\r
+    }\r
+\r
+    If (LOr(LEqual(D20A, 0), LEqual(L20D, 1)))\r
+    {\r
+      Return (0x0)\r
+    }\r
+    Return (0xF)\r
+  }\r
+}\r
+\r
+//\r
+// LPIO1 PWM #1\r
+//\r
+Device(PWM1)\r
+{\r
+  Name (_ADR, 0)\r
+  Name (_HID, "80860F09")\r
+  Name (_CID, "80860F09")\r
+  Name (_DDN, "Intel(R) PWM Controller #1 - 80860F08")\r
+  Name (_UID, 1)\r
+\r
+  Name (RBUF, ResourceTemplate ()\r
+  {\r
+    Memory32Fixed (ReadWrite, 0x00000000, 0x00001000, BAR0)\r
+  })\r
+  Method (_CRS, 0x0, NotSerialized)\r
+  {\r
+    CreateDwordField(^RBUF, ^BAR0._BAS, B0BA)\r
+    CreateDwordField(^RBUF, ^BAR0._LEN, B0LN)\r
+    Store(P10A, B0BA)\r
+    Store(P10L, B0LN)\r
+    Return (RBUF)\r
+  }\r
+  Method (_STA, 0x0, NotSerialized)\r
+  {\r
+    //\r
+    // PCIM>> 0:ACPI mode           1:PCI mode\r
+    //\r
+    If (LEqual(PCIM, 1)) {\r
+      Return (0x0)\r
+    }\r
+\r
+    If (LOr(LEqual(P10A, 0), LEqual(L11D, 1)))\r
+    {\r
+      Return (0x0)\r
+    }\r
+    Return (0xF)\r
+  }\r
+}\r
+\r
+//\r
+// LPIO1 PWM #2\r
+//\r
+Device(PWM2)\r
+{\r
+  Name (_ADR, 0)\r
+  Name (_HID, "80860F09")\r
+  Name (_CID, "80860F09")\r
+  Name (_DDN, "Intel(R) PWM Controller #2 - 80860F09")\r
+  Name (_UID, 2)\r
+\r
+  Name (RBUF, ResourceTemplate ()\r
+  {\r
+    Memory32Fixed (ReadWrite, 0x00000000, 0x00001000, BAR0)\r
+  })\r
+  Method (_CRS, 0x0, NotSerialized)\r
+  {\r
+    CreateDwordField(^RBUF, ^BAR0._BAS, B0BA)\r
+    CreateDwordField(^RBUF, ^BAR0._LEN, B0LN)\r
+    Store(P20A, B0BA)\r
+    Store(P20L, B0LN)\r
+    Return (RBUF)\r
+  }\r
+  Method (_STA, 0x0, NotSerialized)\r
+  {\r
+    //\r
+    // PCIM>> 0:ACPI mode           1:PCI mode\r
+    //\r
+    If (LEqual(PCIM, 1)) {\r
+      Return (0x0)\r
+    }\r
+\r
+    If (LOr(LEqual(P20A, 0), LEqual(L12D, 1)))\r
+    {\r
+      Return (0x0)\r
+    }\r
+    Return (0xF)\r
+  }\r
+}\r
+\r
+//\r
+// LPIO1 HS-UART #1\r
+//\r
+Device(URT1)\r
+{\r
+  Name (_ADR, 0)\r
+  Name (_HID, "80860F0A")\r
+  Name (_CID, "80860F0A")\r
+  Name (_DDN, "Intel(R) HS-UART Controller #1 - 80860F0A")\r
+  Name (_UID, 1)\r
+  Name(_DEP, Package(0x1)\r
+  {\r
+    PEPD\r
+  })\r
+  Name (RBUF, ResourceTemplate ()\r
+  {\r
+    Memory32Fixed (ReadWrite, 0x00000000, 0x00001000, BAR0)\r
+    Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , ) {39}  // HS-UART #1 IRQ\r
+\r
+    FixedDMA(0x2, 0x2, Width32Bit, )\r
+    FixedDMA(0x3, 0x3, Width32Bit, )\r
+  })\r
+  Method (_HRV, 0x0, NotSerialized)\r
+  {\r
+    Return (SOCS)\r
+  }\r
+  Method (_CRS, 0x0, NotSerialized)\r
+  {\r
+    CreateDwordField(^RBUF, ^BAR0._BAS, B0BA)\r
+    CreateDwordField(^RBUF, ^BAR0._LEN, B0LN)\r
+    Store(U10A, B0BA)\r
+    Store(U10L, B0LN)\r
+    Return (RBUF)\r
+  }\r
+\r
+  Method (_STA, 0x0, NotSerialized)\r
+  {\r
+    //\r
+    // PCIM>> 0:ACPI mode           1:PCI mode\r
+    //\r
+    If (LEqual(PCIM, 1)) {\r
+      Return (0x0)\r
+    }\r
+\r
+    If (LOr(LEqual(U10A, 0), LEqual(L13D, 1)))\r
+    {\r
+      Return (0x0)\r
+    }\r
+    Return (0xF)\r
+  }\r
+\r
+  Method (_PS3, 0, NotSerialized)\r
+  {\r
+    OR(PSAT, 0x00000003, PSAT)\r
+    OR(PSAT, 0X00000000, PSAT)\r
+  }\r
+\r
+  Method (_PS0, 0, NotSerialized)\r
+  {\r
+    And(PSAT, 0xfffffffC, PSAT)\r
+    OR(PSAT, 0X00000000, PSAT)\r
+  }\r
+\r
+  OperationRegion (KEYS, SystemMemory, U11A, 0x100)\r
+  Field (KEYS, DWordAcc, NoLock, WriteAsZeros)\r
+  {\r
+    Offset (0x84),\r
+    PSAT,   32\r
+  }\r
+}//  Device (URT1)\r
+\r
+//\r
+// LPIO1 HS-UART #2\r
+//\r
+Device(URT2)\r
+{\r
+  Name (_ADR, 0)\r
+  Name (_HID, "80860F0A")\r
+  Name (_CID, "80860F0A")\r
+  Name (_DDN, "Intel(R) HS-UART Controller #2 - 80860F0C")\r
+  Name (_UID, 2)\r
+\r
+  Name(_DEP, Package(0x1)\r
+  {\r
+    PEPD\r
+  })\r
+\r
+  Name (RBUF, ResourceTemplate ()\r
+  {\r
+    Memory32Fixed (ReadWrite, 0x00000000, 0x00001000, BAR0)\r
+    Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , ) {40}  // HS-UART #2 IRQ\r
+\r
+    FixedDMA(0x4, 0x4, Width32Bit, )\r
+    FixedDMA(0x5, 0x5, Width32Bit, )\r
+  })\r
+\r
+  Method (_HRV, 0x0, NotSerialized)\r
+  {\r
+    Return (SOCS)\r
+  }\r
+\r
+  Method (_CRS, 0x0, NotSerialized)\r
+  {\r
+    CreateDwordField(^RBUF, ^BAR0._BAS, B0BA)\r
+    CreateDwordField(^RBUF, ^BAR0._LEN, B0LN)\r
+    Store(U20A, B0BA)\r
+    Store(U20L, B0LN)\r
+    Return (RBUF)\r
+  }\r
+\r
+  Method (_STA, 0x0, NotSerialized)\r
+  {\r
+    //\r
+    // PCIM>> 0:ACPI mode           1:PCI mode\r
+    //\r
+    If (LEqual(PCIM, 1)) {\r
+      Return (0x0)\r
+    }\r
+\r
+    If (LOr(LEqual(U20A, 0), LEqual(L14D, 1)))\r
+    {\r
+      Return (0x0)\r
+    }\r
+    Return (0xF)\r
+  }\r
+\r
+  Method (_PS3, 0, NotSerialized)\r
+  {\r
+    OR(PSAT, 0x00000003, PSAT)\r
+    OR(PSAT, 0X00000000, PSAT)\r
+  }\r
+\r
+  Method (_PS0, 0, NotSerialized)\r
+  {\r
+    And(PSAT, 0xfffffffC, PSAT)\r
+    OR(PSAT, 0X00000000, PSAT)\r
+  }\r
+\r
+  OperationRegion (KEYS, SystemMemory, U21A, 0x100)\r
+  Field (KEYS, DWordAcc, NoLock, WriteAsZeros)\r
+  {\r
+    Offset (0x84),\r
+    PSAT,   32\r
+  }\r
+}//  Device (URT2)\r
+\r
+//\r
+// LPIO1 SPI\r
+//\r
+Device(SPI1)\r
+{\r
+  Name (_ADR, 0)\r
+  Name (_HID, "80860F0E")\r
+  Name (_CID, "80860F0E")\r
+  Name (_UID, "0")  // Static bus number assignment\r
+  Name(_DEP, Package(0x1)\r
+  {\r
+    PEPD\r
+  })\r
+  Name (_DDN, "Intel(R) SPI Controller - 80860F0E")\r
+\r
+  Name (RBUF, ResourceTemplate ()\r
+  {\r
+    Memory32Fixed (ReadWrite, 0x00000000, 0x00001000, BAR0)\r
+    Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , ) {41}  // SPI IRQ\r
+\r
+    FixedDMA(0x0, 0x0, Width32Bit, )\r
+    FixedDMA(0x1, 0x1, Width32Bit, )\r
+  })\r
+\r
+  Method (_HRV, 0x0, NotSerialized)\r
+  {\r
+    Return (SOCS)\r
+  }\r
+\r
+  Method (_CRS, 0x0, NotSerialized)\r
+  {\r
+    CreateDwordField(^RBUF, ^BAR0._BAS, B0BA)\r
+    CreateDwordField(^RBUF, ^BAR0._LEN, B0LN)\r
+    Store(SP0A, B0BA)\r
+    Store(SP0L, B0LN)\r
+    Return (RBUF)\r
+  }\r
+\r
+  Method (_STA, 0x0, NotSerialized)\r
+  {\r
+    //\r
+    // PCIM>> 0:ACPI mode           1:PCI mode\r
+    //\r
+    If (LEqual(PCIM, 1)) {\r
+      Return (0x0)\r
+    }\r
+\r
+    If (LOr(LEqual(SP0A, 0), LEqual(L15D, 1)))\r
+    {\r
+      Return (0x0)\r
+    }\r
+    Return (0xF)\r
+  }\r
+\r
+  Method (_PS3, 0, NotSerialized)\r
+  {\r
+    OR(PSAT, 0x00000003, PSAT)\r
+    OR(PSAT, 0X00000000, PSAT)\r
+  }\r
+\r
+  Method (_PS0, 0, NotSerialized)\r
+  {\r
+    And(PSAT, 0xfffffffC, PSAT)\r
+    OR(PSAT, 0X00000000, PSAT)\r
+  }\r
+\r
+  OperationRegion (KEYS, SystemMemory, SP1A, 0x100)\r
+  Field (KEYS, DWordAcc, NoLock, WriteAsZeros)\r
+  {\r
+    Offset (0x84),\r
+           PSAT,   32\r
+  }\r
+}//  Device (SPI1)\r
+\r
+//\r
+// LPIO2 I2C #1\r
+//\r
+Device(I2C1)\r
+{\r
+  Name (_ADR, 0)\r
+  Name (_HID, "80860F41")\r
+  Name (_CID, "80860F41")\r
+  Name(_DEP, Package(0x1)\r
+  {\r
+    PEPD\r
+  })\r
+  Name (_DDN, "Intel(R) I2C Controller #1 - 80860F41")\r
+  Name (_UID, 1)\r
+\r
+  Name (RBUF, ResourceTemplate ()\r
+  {\r
+    Memory32Fixed (ReadWrite, 0x00000000, 0x00001000, BAR0)\r
+    Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , ) {32}  // I2C #1 IRQ\r
+\r
+    FixedDMA(0x10, 0x0, Width32Bit, )\r
+    FixedDMA(0x11, 0x1, Width32Bit, )\r
+  })\r
+\r
+  Method (SSCN, 0x0, NotSerialized)\r
+  {\r
+    Name (PKG, Package(3) { 0x200, 0x200, 0x06 })\r
+    Return (PKG)\r
+  }\r
+  Method (FMCN, 0x0, NotSerialized)\r
+  {\r
+    Name (PKG, Package(3) { 0x55, 0x99, 0x06 })\r
+    Return (PKG)\r
+  }\r
+  Method (FPCN, 0x0, NotSerialized)\r
+  {\r
+    Name (PKG, Package(3) { 0x1b, 0x3a, 0x06 })\r
+    Return (PKG)\r
+  }\r
+\r
+  Method (_HRV, 0x0, NotSerialized)\r
+  {\r
+    Return (SOCS)\r
+  }\r
+  Method (_CRS, 0x0, NotSerialized)\r
+  {\r
+    CreateDwordField(^RBUF, ^BAR0._BAS, B0BA)\r
+    CreateDwordField(^RBUF, ^BAR0._LEN, B0LN)\r
+    Store(I10A, B0BA)\r
+    Store(I10L, B0LN)\r
+    Return (RBUF)\r
+  }\r
+  Method (_STA, 0x0, NotSerialized)\r
+  {\r
+    //\r
+    // PCIM>> 0:ACPI mode           1:PCI mode\r
+    //\r
+    If (LEqual(PCIM, 1)) {\r
+      Return (0x0)\r
+    }\r
+\r
+    If (LOr(LEqual(I10A, 0), LEqual(L21D, 1)))\r
+    {\r
+      Return (0x0)\r
+    }\r
+    Return (0xF)\r
+\r
+  }\r
+\r
+  Method (_PS3, 0, NotSerialized)\r
+  {\r
+    OR(PSAT, 0x00000003, PSAT)\r
+    OR(PSAT, 0X00000000, PSAT)\r
+  }\r
+  Method (_PS0, 0, NotSerialized)\r
+  {\r
+    And(PSAT, 0xfffffffC, PSAT)\r
+    OR(PSAT, 0X00000000, PSAT)\r
+  }\r
+  OperationRegion (KEYS, SystemMemory, I11A, 0x100)\r
+  Field (KEYS, DWordAcc, NoLock, WriteAsZeros)\r
+  {\r
+    Offset (0x84),\r
+           PSAT,   32\r
+  }\r
+\r
+}\r
+\r
+//\r
+// LPIO2 I2C #2\r
+//\r
+Device(I2C2)\r
+{\r
+  Name (_ADR, 0)\r
+  Name (_HID, "80860F41")\r
+  Name (_CID, "80860F41")\r
+  Name(_DEP, Package(0x1)\r
+  {\r
+    PEPD\r
+  })\r
+  Name (_DDN, "Intel(R) I2C Controller #2 - 80860F42")\r
+  Name (_UID, 2)\r
+\r
+  Name (RBUF, ResourceTemplate ()\r
+  {\r
+    Memory32Fixed (ReadWrite, 0x00000000, 0x00001000, BAR0)\r
+    Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , ) {33}  // I2C #2 IRQ\r
+\r
+    FixedDMA(0x12, 0x2, Width32Bit, )\r
+    FixedDMA(0x13, 0x3, Width32Bit, )\r
+  })\r
+\r
+  Method (SSCN, 0x0, NotSerialized)\r
+  {\r
+    Name (PKG, Package(3) { 0x200, 0x200, 0x06 })\r
+    Return (PKG)\r
+  }\r
+  Method (FMCN, 0x0, NotSerialized)\r
+  {\r
+    Name (PKG, Package(3) { 0x55, 0x99, 0x06 })\r
+    Return (PKG)\r
+  }\r
+  Method (FPCN, 0x0, NotSerialized)\r
+  {\r
+    Name (PKG, Package(3) { 0x1b, 0x3a, 0x06 })\r
+    Return (PKG)\r
+  }\r
+\r
+  Method (_HRV, 0x0, NotSerialized)\r
+  {\r
+    Return (SOCS)\r
+  }\r
+  Method (_CRS, 0x0, NotSerialized)\r
+  {\r
+    CreateDwordField(^RBUF, ^BAR0._BAS, B0BA)\r
+    CreateDwordField(^RBUF, ^BAR0._LEN, B0LN)\r
+    Store(I20A, B0BA)\r
+    Store(I20L, B0LN)\r
+    Return (RBUF)\r
+  }\r
+  Method (_STA, 0x0, NotSerialized)\r
+  {\r
+    //\r
+    // PCIM>> 0:ACPI mode           1:PCI mode\r
+    //\r
+    If (LEqual(PCIM, 1)) {\r
+      Return (0x0)\r
+    }\r
+\r
+    If (LOr(LEqual(I20A, 0), LEqual(L22D, 1)))\r
+    {\r
+      Return (0x0)\r
+    }\r
+    Return (0xF)\r
+  }\r
+\r
+  Method (_PS3, 0, NotSerialized)\r
+  {\r
+    OR(PSAT, 0x00000003, PSAT)\r
+    OR(PSAT, 0X00000000, PSAT)\r
+\r
+  }\r
+  Method (_PS0, 0, NotSerialized)\r
+  {\r
+    And(PSAT, 0xfffffffC, PSAT)\r
+    OR(PSAT, 0X00000000, PSAT)\r
+  }\r
+  OperationRegion (KEYS, SystemMemory, I21A, 0x100)\r
+  Field (KEYS, DWordAcc, NoLock, WriteAsZeros)\r
+  {\r
+    Offset (0x84),\r
+           PSAT,   32\r
+  }\r
+\r
+\r
+  //\r
+  // Realtek Audio Codec\r
+  //\r
+  Device (RTEK)   //Audio Codec driver I2C\r
+  {\r
+    Name (_ADR, 0)\r
+    Name (_HID, "10EC5640")\r
+    Name (_CID, "10EC5640")\r
+    Name (_DDN, "RTEK Codec Controller " )\r
+    Name (_UID, 1)\r
+\r
+\r
+    Method(_CRS, 0x0, Serialized)\r
+    {\r
+      Name(SBUF,ResourceTemplate ()\r
+      {\r
+        I2CSerialBus(0x1C,          //SlaveAddress: bus address\r
+                     ,                         //SlaveMode: default to ControllerInitiated\r
+                     400000,                   //ConnectionSpeed: in Hz\r
+                     ,                         //Addressing Mode: default to 7 bit\r
+                     "\\_SB.I2C2",             //ResourceSource: I2C bus controller name\r
+                     ,                         //ResourceSourceIndex: defaults to 0\r
+                     ,                         //ResourceUsage: Defaults to ResourceConsumer\r
+                     ,                         //Descriptor Name: creates name for offset of resource descriptor\r
+                    )  //VendorData\r
+        GpioInt(Edge, ActiveHigh, ExclusiveAndWake, PullNone, 0,"\\_SB.GPO2") {4} //  AUD_INT\r
+      })\r
+      Return (SBUF)\r
+    }\r
+\r
+    Method (_STA, 0x0, NotSerialized)\r
+    {\r
+\r
+      If (LEqual(LPEE, 2)) { // LPE enable/disable\r
+        Return(0xF)\r
+      }\r
+      Return(0)\r
+    }\r
+\r
+    Method (_DIS, 0x0, NotSerialized)\r
+    {\r
+\r
+    }\r
+  } // Device (RTEK)\r
+} //  Device (I2C2)\r
+\r
+//\r
+// LPIO2 I2C #3\r
+//\r
+Device(I2C3)\r
+{\r
+  Name (_ADR, 0)\r
+  Name (_HID, "80860F41")\r
+  Name (_CID, "80860F41")\r
+  Name (_DDN, "Intel(R) I2C Controller #3 - 80860F43")\r
+  Name (_UID, 3)\r
+  Name(_DEP, Package(0x1)\r
+  {\r
+    PEPD\r
+  })\r
+  Name (RBUF, ResourceTemplate ()\r
+  {\r
+    Memory32Fixed (ReadWrite, 0x00000000, 0x00001000, BAR0)\r
+    Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , ) {34}  // I2C #3 IRQ\r
+\r
+    FixedDMA(0x14, 0x4, Width32Bit, )\r
+    FixedDMA(0x15, 0x5, Width32Bit, )\r
+  })\r
+\r
+  Method (SSCN, 0x0, NotSerialized)\r
+  {\r
+    Name (PKG, Package(3) { 0x200, 0x200, 0x06 })\r
+    Return (PKG)\r
+  }\r
+  Method (FMCN, 0x0, NotSerialized)\r
+  {\r
+    Name (PKG, Package(3) { 0x55, 0x99, 0x06 })\r
+    Return (PKG)\r
+  }\r
+  Method (FPCN, 0x0, NotSerialized)\r
+  {\r
+    Name (PKG, Package(3) { 0x1b, 0x3a, 0x06 })\r
+    Return (PKG)\r
+  }\r
+\r
+  Method (_HRV, 0x0, NotSerialized)\r
+  {\r
+    Return (SOCS)\r
+  }\r
+  Method (_CRS, 0x0, NotSerialized)\r
+  {\r
+    CreateDwordField(^RBUF, ^BAR0._BAS, B0BA)\r
+    CreateDwordField(^RBUF, ^BAR0._LEN, B0LN)\r
+    Store(I30A, B0BA)\r
+    Store(I30L, B0LN)\r
+    Return (RBUF)\r
+  }\r
+\r
+  Method (_STA, 0x0, NotSerialized)\r
+  {\r
+    //\r
+    // PCIM>> 0:ACPI mode           1:PCI mode\r
+    //\r
+    If (LEqual(PCIM, 1)) {\r
+      Return (0x0)\r
+    }\r
+\r
+    If (LOr(LEqual(I30A, 0), LEqual(L23D, 1)))\r
+    {\r
+      Return (0x0)\r
+    }\r
+    Return (0xF)\r
+  }\r
+\r
+  Method (_PS3, 0, NotSerialized)\r
+  {\r
+    OR(PSAT, 0x00000003, PSAT)\r
+    OR(PSAT, 0X00000000, PSAT)\r
+\r
+  }\r
+  Method (_PS0, 0, NotSerialized)\r
+  {\r
+    And(PSAT, 0xfffffffC, PSAT)\r
+    OR(PSAT, 0X00000000, PSAT)\r
+  }\r
+  OperationRegion (KEYS, SystemMemory, I31A, 0x100)\r
+  Field (KEYS, DWordAcc, NoLock, WriteAsZeros)\r
+  {\r
+    Offset (0x84),\r
+    PSAT,   32\r
+  }\r
+\r
+\r
+}\r
+\r
+//\r
+// LPIO2 I2C #4\r
+//\r
+Device(I2C4)\r
+{\r
+  Name (_ADR, 0)\r
+  Name (_HID, "80860F41")\r
+  Name (_CID, "80860F41")\r
+  Name (_DDN, "Intel(R) I2C Controller #4 - 80860F44")\r
+  Name (_UID, 4)\r
+  Name(_DEP, Package(0x1)\r
+  {\r
+    PEPD\r
+  })\r
+  Name (RBUF, ResourceTemplate ()\r
+  {\r
+    Memory32Fixed (ReadWrite, 0x00000000, 0x00001000, BAR0)\r
+    Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , ) {35}  // I2C #4 IRQ\r
+\r
+    FixedDMA(0x16, 0x6, Width32Bit, )\r
+    FixedDMA(0x17, 0x7, Width32Bit, )\r
+  })\r
+\r
+  Method (SSCN, 0x0, NotSerialized)\r
+  {\r
+    Name (PKG, Package(3) { 0x200, 0x200, 0x06 })\r
+    Return (PKG)\r
+  }\r
+  Method (FMCN, 0x0, NotSerialized)\r
+  {\r
+    Name (PKG, Package(3) { 0x55, 0x99, 0x06 })\r
+    Return (PKG)\r
+  }\r
+  Method (FPCN, 0x0, NotSerialized)\r
+  {\r
+    Name (PKG, Package(3) { 0x1b, 0x3a, 0x06 })\r
+    Return (PKG)\r
+  }\r
+\r
+\r
+  Method (_HRV, 0x0, NotSerialized)\r
+  {\r
+    Return (SOCS)\r
+  }\r
+  Method (_CRS, 0x0, NotSerialized)\r
+  {\r
+    CreateDwordField(^RBUF, ^BAR0._BAS, B0BA)\r
+    CreateDwordField(^RBUF, ^BAR0._LEN, B0LN)\r
+    Store(I40A, B0BA)\r
+    Store(I40L, B0LN)\r
+    Return (RBUF)\r
+  }\r
+\r
+  Method (_STA, 0x0, NotSerialized)\r
+  {\r
+    //\r
+    // PCIM>> 0:ACPI mode           1:PCI mode\r
+    //\r
+    If (LEqual(PCIM, 1)) {\r
+      Return (0x0)\r
+    }\r
+\r
+    If (LOr(LEqual(I40A, 0), LEqual(L24D, 1)))\r
+    {\r
+      Return (0x0)\r
+    }\r
+    Return (0xF)\r
+  }\r
+\r
+  Method (_PS3, 0, NotSerialized)\r
+  {\r
+    OR(PSAT, 0x00000003, PSAT)\r
+    OR(PSAT, 0X00000000, PSAT)\r
+\r
+  }\r
+  Method (_PS0, 0, NotSerialized)\r
+  {\r
+    And(PSAT, 0xfffffffC, PSAT)\r
+    OR(PSAT, 0X00000000, PSAT)\r
+  }\r
+  OperationRegion (KEYS, SystemMemory, I41A, 0x100)\r
+  Field (KEYS, DWordAcc, NoLock, WriteAsZeros)\r
+  {\r
+    Offset (0x84),\r
+    PSAT,   32\r
+  }\r
+\r
+  PowerResource (CLK0, 0x00, 0x0000)\r
+  {\r
+    Method (_STA, 0, NotSerialized)   // _STA: Status\r
+    {\r
+      Return (CKC0)\r
+    }\r
+\r
+    Method (_ON, 0, NotSerialized)   // _ON_: Power On\r
+    {\r
+      Store (One, CKC0)\r
+      Store (One, CKF0)\r
+      Sleep (0x20)\r
+    }\r
+\r
+    Method (_OFF, 0, NotSerialized)   // _OFF: Power Off\r
+    {\r
+      Store (0x02, CKC0)\r
+    }\r
+  }\r
+  PowerResource (CLK1, 0x00, 0x0000)\r
+  {\r
+    Method (_STA, 0, NotSerialized)   // _STA: Status\r
+    {\r
+      Return (CKC1)\r
+    }\r
+\r
+    Method (_ON, 0, NotSerialized)   // _ON_: Power On\r
+    {\r
+      Store (One, CKC1)\r
+      Store (One, CKF1)\r
+      Sleep (0x20)\r
+    }\r
+\r
+    Method (_OFF, 0, NotSerialized)   // _OFF: Power Off\r
+    {\r
+      Store (0x02, CKC1)\r
+    }\r
+  }\r
+}\r
+\r
+//\r
+// LPIO2 I2C #5\r
+//\r
+Device(I2C5)\r
+{\r
+  Name (_ADR, 0)\r
+  Name (_HID, "80860F41")\r
+  Name (_CID, "80860F41")\r
+  Name (_DDN, "Intel(R) I2C Controller #5 - 80860F45")\r
+  Name (_UID, 5)\r
+  Name(_DEP, Package(0x1)\r
+  {\r
+    PEPD\r
+  })\r
+  Name (RBUF, ResourceTemplate ()\r
+  {\r
+    Memory32Fixed (ReadWrite, 0x00000000, 0x00001000, BAR0)\r
+    Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , ) {36}  // I2C #5 IRQ\r
+\r
+    FixedDMA(0x18, 0x0, Width32Bit, )\r
+    FixedDMA(0x19, 0x1, Width32Bit, )\r
+  })\r
+\r
+  Method (SSCN, 0x0, NotSerialized)\r
+  {\r
+    Name (PKG, Package(3) { 0x200, 0x200, 0x06 })\r
+    Return (PKG)\r
+  }\r
+  Method (FMCN, 0x0, NotSerialized)\r
+  {\r
+    Name (PKG, Package(3) { 0x55, 0x99, 0x06 })\r
+    Return (PKG)\r
+  }\r
+  Method (FPCN, 0x0, NotSerialized)\r
+  {\r
+    Name (PKG, Package(3) { 0x1b, 0x3a, 0x06 })\r
+    Return (PKG)\r
+  }\r
+\r
+  Method (_HRV, 0x0, NotSerialized)\r
+  {\r
+    Return (SOCS)\r
+  }\r
+  Method (_CRS, 0x0, NotSerialized)\r
+  {\r
+    CreateDwordField(^RBUF, ^BAR0._BAS, B0BA)\r
+    CreateDwordField(^RBUF, ^BAR0._LEN, B0LN)\r
+    Store(I50A, B0BA)\r
+    Store(I50L, B0LN)\r
+    Return (RBUF)\r
+  }\r
+  Method (_STA, 0x0, NotSerialized)\r
+  {\r
+    //\r
+    // PCIM>> 0:ACPI mode           1:PCI mode\r
+    //\r
+    If (LEqual(PCIM, 1)) {\r
+      Return (0x0)\r
+    }\r
+\r
+    If (LOr(LEqual(I50A, 0), LEqual(L25D, 1)))\r
+    {\r
+      Return (0x0)\r
+    }\r
+    Return (0xF)\r
+  }\r
+\r
+  Method (_PS3, 0, NotSerialized)\r
+  {\r
+    OR(PSAT, 0x00000003, PSAT)\r
+    OR(PSAT, 0X00000000, PSAT)\r
+  }\r
+  Method (_PS0, 0, NotSerialized)\r
+  {\r
+    And(PSAT, 0xfffffffC, PSAT)\r
+    OR(PSAT, 0X00000000, PSAT)\r
+  }\r
+  OperationRegion (KEYS, SystemMemory, I51A, 0x100)\r
+  Field (KEYS, DWordAcc, NoLock, WriteAsZeros)\r
+  {\r
+    Offset (0x84),\r
+    PSAT,   32\r
+  }\r
+}\r
+\r
+//\r
+// LPIO2 I2C #6\r
+//\r
+Device(I2C6)\r
+{\r
+  Name (_ADR, 0)\r
+  Name (_HID, "80860F41")\r
+  Name (_CID, "80860F41")\r
+  Name (_DDN, "Intel(R) I2C Controller #6 - 80860F46")\r
+  Name (_UID, 6)\r
+  Name(_DEP, Package(0x1)\r
+  {\r
+    PEPD\r
+  })\r
+  Name (RBUF, ResourceTemplate ()\r
+  {\r
+    Memory32Fixed (ReadWrite, 0x00000000, 0x00001000, BAR0)\r
+    Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , ) {37}  // I2C #6 IRQ\r
+\r
+    FixedDMA(0x1A, 0x02, Width32Bit, )\r
+    FixedDMA(0x1B, 0x03, Width32Bit, )\r
+  })\r
+\r
+  Method (SSCN, 0x0, NotSerialized)\r
+  {\r
+    Name (PKG, Package(3) { 0x200, 0x200, 0x06 })\r
+    Return (PKG)\r
+  }\r
+  Method (FMCN, 0x0, NotSerialized)\r
+  {\r
+    Name (PKG, Package(3) { 0x55, 0x99, 0x06 })\r
+    Return (PKG)\r
+  }\r
+  Method (FPCN, 0x0, NotSerialized)\r
+  {\r
+    Name (PKG, Package(3) { 0x1b, 0x3a, 0x06 })\r
+    Return (PKG)\r
+  }\r
+\r
+  Method (_HRV, 0x0, NotSerialized)\r
+  {\r
+    Return (SOCS)\r
+  }\r
+  Method (_CRS, 0x0, NotSerialized)\r
+  {\r
+    CreateDwordField(^RBUF, ^BAR0._BAS, B0BA)\r
+    CreateDwordField(^RBUF, ^BAR0._LEN, B0LN)\r
+    Store(I60A, B0BA)\r
+    Store(I60L, B0LN)\r
+    Return (RBUF)\r
+  }\r
+  Method (_STA, 0x0, NotSerialized)\r
+  {\r
+    //\r
+    // PCIM>> 0:ACPI mode           1:PCI mode\r
+    //\r
+    If (LEqual(PCIM, 1)) {\r
+      Return (0x0)\r
+    }\r
+\r
+    If (LOr(LEqual(I60A, 0), LEqual(L26D, 1)))\r
+    {\r
+      Return (0x0)\r
+    }\r
+    Return (0xF)\r
+  }\r
+\r
+  Method (_PS3, 0, NotSerialized)\r
+  {\r
+    OR(PSAT, 0x00000003, PSAT)\r
+    OR(PSAT, 0X00000000, PSAT)\r
+  }\r
+  Method (_PS0, 0, NotSerialized)\r
+  {\r
+    And(PSAT, 0xfffffffC, PSAT)\r
+    OR(PSAT, 0X00000000, PSAT)\r
+  }\r
+  OperationRegion (KEYS, SystemMemory, I61A, 0x100)\r
+  Field (KEYS, DWordAcc, NoLock, WriteAsZeros)\r
+  {\r
+    Offset (0x84),\r
+           PSAT,   32\r
+  }\r
+}\r
+\r
+//\r
+// LPIO2 I2C #7\r
+//\r
+Device(I2C7)\r
+{\r
+  Name (_ADR, 0)\r
+  Name (_HID, "80860F41")\r
+  Name (_CID, "80860F41")\r
+  //Name (_CLS, Package (3) {0x0C, 0x80, 0x00})\r
+  Name (_DDN, "Intel(R) I2C Controller #7 - 80860F47")\r
+  Name (_UID, 7)\r
+  Name(_DEP, Package(0x1)\r
+  {\r
+    PEPD\r
+  })\r
+  Name (RBUF, ResourceTemplate ()\r
+  {\r
+    Memory32Fixed (ReadWrite, 0x00000000, 0x00001000, BAR0)\r
+    Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , ) {38}  // I2C #7 IRQ\r
+\r
+    FixedDMA(0x1C, 0x4, Width32Bit, )\r
+    FixedDMA(0x1D, 0x5, Width32Bit, )\r
+  })\r
+\r
+  Method (SSCN, 0x0, NotSerialized)\r
+  {\r
+    Name (PKG, Package(3) { 0x200, 0x200, 0x06 })\r
+    Return (PKG)\r
+  }\r
+  Method (FMCN, 0x0, NotSerialized)\r
+  {\r
+    Name (PKG, Package(3) { 0x55, 0x99, 0x06 })\r
+    Return (PKG)\r
+  }\r
+  Method (FPCN, 0x0, NotSerialized)\r
+  {\r
+    Name (PKG, Package(3) { 0x1b, 0x3a, 0x06 })\r
+    Return (PKG)\r
+  }\r
+\r
+  Method (_HRV, 0x0, NotSerialized)\r
+  {\r
+    Return (SOCS)\r
+  }\r
+\r
+  Method (_CRS, 0x0, NotSerialized)\r
+  {\r
+    CreateDwordField(^RBUF, ^BAR0._BAS, B0BA)\r
+    CreateDwordField(^RBUF, ^BAR0._LEN, B0LN)\r
+    Store(I70A, B0BA)\r
+    Store(I70L, B0LN)\r
+    Return (RBUF)\r
+  }\r
+\r
+  Method (_STA, 0x0, NotSerialized)\r
+  {\r
+    //\r
+    // PCIM>> 0:ACPI mode           1:PCI mode\r
+    //\r
+    If (LEqual(PCIM, 1)) {\r
+      Return (0x0)\r
+    }\r
+\r
+    If (LOr(LEqual(I70A, 0), LEqual(L27D, 1)))\r
+    {\r
+      Return (0x0)\r
+    }\r
+    Return (0xF)\r
+  }\r
+\r
+  Method (_PS3, 0, NotSerialized)\r
+  {\r
+    OR(PSAT, 0x00000003, PSAT)\r
+    OR(PSAT, 0X00000000, PSAT)\r
+  }\r
+\r
+  Method (_PS0, 0, NotSerialized)\r
+  {\r
+    And(PSAT, 0xfffffffC, PSAT)\r
+    OR(PSAT, 0X00000000, PSAT)\r
+  }\r
+\r
+  OperationRegion (KEYS, SystemMemory, I71A, 0x100)\r
+  Field (KEYS, DWordAcc, NoLock, WriteAsZeros)\r
+  {\r
+    Offset (0x84),\r
+    PSAT,   32\r
+  }\r
+\r
+}\r
+\r

diff --git a/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/PchPcie.asl b/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/PchPcie.asl
new file mode 100644 (file)
index 0000000..bfd73e4
--- /dev/null
+++ b/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/PchPcie.asl
@@ -0,0 +1,56 @@
+/**************************************************************************;\r
+;*                                                                        *;\r
+;*                                                                        *;\r
+;*    Intel Corporation - ACPI Reference Code for the Baytrail            *;\r
+;*    Family of Customer Reference Boards.                                *;\r
+;*                                                                        *;\r
+;*                                                                        *;\r
+;*    Copyright (c)  2011  - 2014, Intel Corporation. All rights reserved   *;\r
+;\r
+; This program and the accompanying materials are licensed and made available under\r
+; the terms and conditions of the BSD License that accompanies this distribution.\r
+; The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php.\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+;*                                                                        *;\r
+;*                                                                        *;\r
+;**************************************************************************/\r
+\r
+\r
+OperationRegion(PXCS,PCI_Config,0x40,0xC0)\r
+Field(PXCS,AnyAcc, NoLock, Preserve)\r
+{\r
+  Offset(0x10), // LCTL - Link Control Register\r
+  L0SE, 1,      // 0, L0s Entry Enabled\r
+  , 7,\r
+  Offset(0x12), // LSTS - Link Status Register\r
+  , 13,\r
+  LASX, 1,      // 0, Link Active Status\r
+  Offset(0x1A), // SLSTS[7:0] - Slot Status Register\r
+  ABPX, 1,      // 0, Attention Button Pressed\r
+  , 2,\r
+  PDCX, 1,      // 3, Presence Detect Changed\r
+  , 2,\r
+  PDSX, 1,      // 6, Presence Detect State\r
+  , 1,\r
+  Offset(0x20), // RSTS - Root Status Register\r
+  , 16,\r
+  PSPX, 1,      // 16,        PME Status\r
+}\r
+\r
+\r
+Device(PXSX)\r
+{\r
+  Name(_ADR, 0x00000000)\r
+\r
+  // NOTE:  Any PCIE Hot-Plug dependency for this port is\r
+  // specific to the CRB.  Please modify the code based on\r
+  // your platform requirements.\r
+\r
+  Name(_PRW, Package() {9,4})\r
+}\r
+\r
+\r

diff --git a/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/PchScc.asl b/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/PchScc.asl
new file mode 100644 (file)
index 0000000..60ff48d
--- /dev/null
+++ b/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/PchScc.asl
@@ -0,0 +1,616 @@
+/**************************************************************************;\r
+;*                                                                        *;\r
+;*                                                                        *;\r
+;*    Intel Corporation - ACPI Reference Code for the Baytrail            *;\r
+;*    Family of Customer Reference Boards.                                *;\r
+;*                                                                        *;\r
+;*                                                                        *;\r
+;*    Copyright (c) 2012  - 2014, Intel Corporation. All rights reserved    *;\r
+;\r
+; This program and the accompanying materials are licensed and made available under\r
+; the terms and conditions of the BSD License that accompanies this distribution.\r
+; The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php.\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+;*                                                                        *;\r
+;*                                                                        *;\r
+;**************************************************************************/\r
+Device (PEPD)\r
+{\r
+  Name (_HID, "INT3396")\r
+  Name(_CID, 0x800dd041)\r
+  Name (_UID, 0x1)\r
+\r
+  // Indicates if the platform PEP has loaded\r
+  Name(PEPP, Zero)\r
+\r
+  // Devices score-boarded by the PEP, Rev0 format\r
+  Name (DEVS, Package() {0})\r
+\r
+  // Devices score-boarded by the PEP, Rev1 format\r
+  Name(DEVX, Package()\r
+  {\r
+    Package () {"\\_SB.PCI0.XHC1", 0x1},\r
+    Package () {"\\_SB.PCI0.EHC1", 0x1},\r
+    Package () {"\\_SB.PCI0.GFX0", 0x1},\r
+    Package () {"\\_SB.PCI0.GFX0.ISP0", 0x1},\r
+    Package () {"\\_SB.PCI0.SEC0", 0x1},\r
+    Package () {"\\_SB.I2C1", 0x1},\r
+    Package () {"\\_SB.I2C2", 0x1},\r
+    Package () {"\\_SB.I2C3", 0x1},\r
+    Package () {"\\_SB.I2C4", 0x1},\r
+    Package () {"\\_SB.I2C5", 0x1},\r
+    Package () {"\\_SB.I2C6", 0x1},\r
+    Package () {"\\_SB.I2C7", 0x1},\r
+    Package () {"\\_SB.SDHA", 0x1},\r
+    Package () {"\\_SB.SDHB", 0x1},\r
+    Package () {"\\_SB.SDHC", 0x1},\r
+    Package () {"\\_SB.SPI1", 0x1},\r
+    Package () {"\\_SB.URT1", 0x1},\r
+    Package () {"\\_SB.URT2", 0x1},\r
+  })\r
+  // Crashdump device package\r
+  Name(CDMP, Package(2) {})\r
+  // Device dependency for uPEP\r
+  Name(DEVY, Package()\r
+  {\r
+    Package() {"\\_PR.CPU0", 0x1, Package() {Package() {0xFF, 0}}},\r
+    Package() {"\\_PR.CPU1", 0x1, Package() {Package() {0xFF, 0}}},\r
+    Package() {"\\_PR.CPU2", 0x1, Package() {Package() {0xFF, 0}}},\r
+    Package() {"\\_PR.CPU3", 0x1, Package() {Package() {0xFF, 0}}},\r
+    Package() {"\\_SB.I2C1", 0x1, Package() {Package() {0xFF,3}}},\r
+    Package() {"\\_SB.I2C2", 0x1, Package() {Package() {0xFF,3}}},\r
+    Package() {"\\_SB.I2C3", 0x1, Package() {Package() {0xFF,3}}},\r
+    Package() {"\\_SB.I2C4", 0x1, Package() {Package() {0xFF,3}}},\r
+    Package() {"\\_SB.I2C5", 0x1, Package() {Package() {0xFF,3}}},\r
+    Package() {"\\_SB.I2C6", 0x1, Package() {Package() {0xFF,3}}},\r
+    Package() {"\\_SB.I2C7", 0x1, Package() {Package() {0xFF,3}}},\r
+    Package() {"\\_SB.PCI0.GFX0", 0x1, Package() {Package() {0xFF,3}}},\r
+    Package() {"\\_SB.PCI0.SEC0", 0x1, Package() {Package() {0xFF,3}}},\r
+    Package() {"\\_SB.PCI0.XHC1", 0x1, Package() {Package() {0xFF,3}}},\r
+    Package() {"\\_SB.PCI0.GFX0.ISP0", 0x1, Package() {Package() {0xFF,3}}},\r
+    Package() {"\\_SB.LPEA", 0x1, Package() {Package() {0x0,3}, Package() {0x1,0}, Package() {0x2,3}, Package() {0x3,3}}},\r
+    Package() {"\\_SB.SDHA", 0x1, Package() {Package() {0xFF,3}}},\r
+    Package() {"\\_SB.SDHB", 0x1, Package() {Package() {0xFF,3}}},\r
+    Package() {"\\_SB.SDHC", 0x1, Package() {Package() {0xFF,3}}},\r
+    Package() {"\\_SB.SPI1", 0x1, Package() {Package() {0xFF,3}}},\r
+    Package() {"\\_SB.URT1", 0x1, Package() {Package() {0xFF,3}}},\r
+    Package() {"\\_SB.URT2", 0x1, Package() {Package() {0xFF,3}}}\r
+  })\r
+  // BCCD crashdump information\r
+  Name(BCCD, Package()\r
+  {\r
+    Package()\r
+    {\r
+      "\\_SB.SDHA",\r
+      Package()\r
+      {\r
+        Package() { Package() {0, 32, 0,  3, 0xFFFFFFFFFFFFFFFF}, Package() {0xFFFFFFFC, 0x0, 0x4}, 0}\r
+      }\r
+    }\r
+  })\r
+\r
+  Method(_STA, 0x0, NotSerialized)\r
+  {\r
+    Return(0xf)\r
+  }\r
+\r
+  Method(_DSM, 0x4, Serialized)\r
+  {\r
+    If(LEqual(Arg0,ToUUID("B8FEBFE0-BAF8-454b-AECD-49FB91137B21")))\r
+    {\r
+\r
+      // Number of fn IDs supported\r
+      If(LEqual(Arg2, Zero))\r
+      {\r
+        Return(Buffer(One)\r
+        {\r
+          0xf\r
+        })\r
+      }\r
+\r
+      // Pep presence\r
+      If(LEqual(Arg2, One))\r
+      {\r
+        Store(0x1, PEPP)\r
+        Return(0xf)\r
+      }\r
+\r
+      // Mitigation devices\r
+      If(LEqual(Arg2, 0x2))\r
+      {\r
+        If(LEqual(Arg1, 0x0))\r
+        {\r
+          // Rev0\r
+          Return(DEVS)\r
+        }\r
+        If(LEqual(Arg1, 0x1))\r
+        {\r
+          // Rev1\r
+          Return(DEVX)\r
+        }\r
+      }\r
+\r
+      // Crashdump device data\r
+      If(LEqual(Arg2, 0x3))\r
+      {\r
+        Store("\\_SB.SDHA", Index(CDMP,0))\r
+        Store(EM1A, Index(CDMP,1))\r
+        Return(CDMP)\r
+      }\r
+    }\r
+    // New UUID for built-in uPEP\r
+    If(LEqual(Arg0,ToUUID("C4EB40A0-6CD2-11E2-BCFD-0800200C9A66")))\r
+    {\r
+\r
+      // Number of fn IDs supported\r
+      If(LEqual(Arg2, Zero))\r
+      {\r
+        Return(Buffer(One)\r
+        {\r
+          0x7\r
+        })\r
+      }\r
+      // LPI device dependencies\r
+      If(LEqual(Arg2, 0x1))\r
+      {\r
+        Return(DEVY)\r
+      }\r
+      // Crashdump device data\r
+      If(LEqual(Arg2, 0x2))\r
+      {\r
+        Store(EM1A, Local0)\r
+        Add(Local0, 0x84, Local0)\r
+        Store(Local0, Index(DerefOf(Index(DerefOf(Index(DerefOf(Index(DerefOf(Index(BCCD, Zero, )), One, )), Zero, )), Zero, )), 0x4, ))\r
+        Return(BCCD)\r
+      }\r
+    }\r
+\r
+    Return(One)\r
+  }\r
+}\r
+\r
+//\r
+// eMMC 4.41\r
+//\r
+Device(SDHA)\r
+{\r
+  Name (_ADR, 0)\r
+  Name (_HID, "80860F14")\r
+  Name (_CID, "PNP0D40")\r
+  Name (_DDN, "Intel(R) eMMC Controller - 80860F14")\r
+  Name (_UID, 1)\r
+  Name(_DEP, Package(0x1)\r
+  {\r
+    PEPD\r
+  })\r
+\r
+  Name (RBF1, ResourceTemplate ()\r
+  {\r
+    Memory32Fixed (ReadWrite, 0x00000000, 0x00001000, BAR0)\r
+    Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , ) {45}  // eMMC 4.41 IRQ\r
+  })\r
+\r
+  Method (_CRS, 0x0, NotSerialized)\r
+  {\r
+    // Update the Base address for BAR0 of eMMC 4.41\r
+    CreateDwordField(^RBF1, ^BAR0._BAS, B0B1)\r
+    CreateDwordField(^RBF1, ^BAR0._LEN, B0L1)\r
+    Store(eM0A, B0B1)\r
+    Store(eM0L, B0L1)\r
+    Return (RBF1)\r
+  }\r
+  Method (_STA, 0x0, NotSerialized)\r
+  {\r
+    //\r
+    // PCIM>> 0:ACPI mode            1:PCI mode\r
+    // SD1D>> 0:eMMC 4.41 enable     1:eMMC 4.41 disable\r
+    //\r
+    If (LAnd(LEqual(PCIM, 0), LEqual(SD1D, 0)))\r
+    {\r
+      Return (0xF)\r
+    }\r
+    Else\r
+    {\r
+      Return (0x0)\r
+    }\r
+  }\r
+\r
+\r
+  Method (_PS3, 0, NotSerialized)\r
+  {\r
+    OR(PSAT, 0x00000003, PSAT)\r
+    OR(PSAT, 0X00000000, PSAT)\r
+    //\r
+    // If not B1, still keep 2 ms w/a\r
+    //\r
+    If(LLess(SOCS, 0x03))\r
+    {\r
+      Sleep(2)\r
+    }\r
+  }\r
+  Method (_PS0, 0, NotSerialized)\r
+  {\r
+    And(PSAT, 0xfffffffC, PSAT)\r
+    OR(PSAT, 0X00000000, PSAT)\r
+    //\r
+    // If not B1, still keep 2 ms w/a\r
+    //\r
+    If(LLess(SOCS, 0x03))\r
+    {\r
+      Sleep(2)\r
+    }\r
+  }\r
+\r
+  OperationRegion (KEYS, SystemMemory, eM1A, 0x100)\r
+  Field (KEYS, DWordAcc, NoLock, WriteAsZeros)\r
+  {\r
+    Offset (0x84),\r
+           PSAT,  32\r
+  }\r
+\r
+         Method (_DIS, 0x0, NotSerialized)\r
+  {\r
+    //Adding dummy disable methods for device EMM0\r
+  }\r
+\r
+  Device (EMMD)\r
+  {\r
+    Name (_ADR, 0x00000008) // Slot 0, Function 8\r
+    Method (_RMV, 0, NotSerialized)\r
+    {\r
+      Return (0x0)\r
+    }\r
+  }\r
+}\r
+\r
+\r
+//\r
+// eMMC 4.5\r
+//\r
+Device(SDHD)\r
+{\r
+  Name (_ADR, 0)\r
+  Name (_HID, "80860F14")\r
+  Name (_CID, "PNP0D40")\r
+  Name (_DDN, "Intel(R) eMMC Controller - 80860F14")\r
+  Name (_UID, 1)\r
+  Name(_DEP, Package(0x1)\r
+  {\r
+    PEPD\r
+  })\r
+\r
+  Name (RBF1, ResourceTemplate ()\r
+  {\r
+    Memory32Fixed (ReadWrite, 0x00000000, 0x00001000, BAR0)\r
+    Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , ) {44}  // eMMC 4.5 IRQ\r
+  })\r
+  Method (_CRS, 0x0, NotSerialized)\r
+  {\r
+    CreateDwordField(^RBF1, ^BAR0._BAS, B0B1)\r
+    CreateDwordField(^RBF1, ^BAR0._LEN, B0L1)\r
+    Store(eM0A, B0B1)\r
+    Store(eM0L, B0L1)\r
+    Return (RBF1)\r
+  }\r
+  Method (_STA, 0x0, NotSerialized)\r
+  {\r
+    //\r
+    // PCIM>> 0:ACPI mode           1:PCI mode\r
+    // HSID>> 0:eMMC 4.5 enable     1:eMMC 4.5 disable\r
+    //\r
+    If (LAnd(LEqual(PCIM, 0), LEqual(HSID, 0)))\r
+    {\r
+      Return (0xF)\r
+    }\r
+    Else\r
+    {\r
+      Return (0x0)\r
+    }\r
+  }\r
+\r
+\r
+  Method (_PS3, 0, NotSerialized)\r
+  {\r
+    OR(PSAT, 0x00000003, PSAT)\r
+    OR(PSAT, 0X00000000, PSAT)\r
+    //\r
+    // If not B1, still keep 2 ms w/a\r
+    //\r
+    If(LLess(SOCS, 0x03))\r
+    {\r
+      Sleep(2)\r
+    }\r
+  }\r
+  Method (_PS0, 0, NotSerialized)\r
+  {\r
+    And(PSAT, 0xfffffffC, PSAT)\r
+    OR(PSAT, 0X00000000, PSAT)\r
+    //\r
+    // If not B1, still keep 2 ms w/a\r
+    //\r
+    If(LLess(SOCS, 0x03))\r
+    {\r
+      Sleep(2)\r
+    }\r
+  }\r
+\r
+  OperationRegion (KEYS, SystemMemory, eM1A, 0x100)\r
+  Field (KEYS, DWordAcc, NoLock, WriteAsZeros)\r
+  {\r
+    Offset (0x84),\r
+           PSAT,  32\r
+  }\r
+\r
+         Method (_DIS, 0x0, NotSerialized)\r
+  {\r
+    //Adding dummy disable methods for device EMM0\r
+  }\r
+\r
+  Device (EM45)\r
+  {\r
+    Name (_ADR, 0x00000008) // Slot 0, Function 8\r
+    Method (_RMV, 0, NotSerialized)\r
+    {\r
+      Return (0x0)\r
+    }\r
+  }\r
+}\r
+\r
+\r
+//\r
+// SDIO\r
+//\r
+Device(SDHB)\r
+{\r
+  Name (_ADR, 0)\r
+  Name (_HID, "INT33BB")\r
+  Name (_CID, "PNP0D40")\r
+  Name (_DDN, "Intel(R) SDIO Controller - 80860F15")\r
+  Name (_UID, 2)\r
+  Name (_HRV, 2)\r
+  Name(_DEP, Package(0x01)\r
+  {\r
+    PEPD\r
+  })\r
+  Name (PSTS, 0x0)\r
+\r
+  Name (RBUF, ResourceTemplate ()\r
+  {\r
+    Memory32Fixed (ReadWrite, 0x00000000, 0x00001000, BAR0)\r
+    Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , ) {46}  // SDIO IRQ\r
+  })\r
+\r
+  Method (_CRS, 0x0, NotSerialized)\r
+  {\r
+\r
+    CreateDwordField(^RBUF, ^BAR0._BAS, B0BA)\r
+    CreateDwordField(^RBUF, ^BAR0._LEN, B0LN)\r
+    Store(SI0A, B0BA)\r
+    Store(SI0L, B0LN)\r
+    Return (RBUF)\r
+  }\r
+  Method (_STA, 0x0, NotSerialized)\r
+  {\r
+    If (LLessEqual(STEP, 0x04))\r
+    {\r
+      //A stepping\r
+      Store(SDMD, _HRV)\r
+    }\r
+\r
+    //\r
+    // PCIM>> 0:ACPI mode           1:PCI mode\r
+    //\r
+    If (LEqual(PCIM, 1)) {\r
+      Return (0x0)\r
+    }\r
+\r
+    If (LOr(LEqual(SI0A, 0), LEqual(SD2D, 1)))\r
+    {\r
+      Return (0x0)\r
+    }\r
+    Return (0xF)\r
+  }\r
+  Method (_DIS, 0x0, NotSerialized)\r
+  {\r
+    //Adding dummy disable methods for device EMM0\r
+  }\r
+\r
+  Method (_PS3, 0, NotSerialized)\r
+  {\r
+    OR(PSAT, 0x00000003, PSAT)\r
+    OR(PSAT, 0X00000000, PSAT)\r
+  }\r
+  Method (_PS0, 0, NotSerialized)\r
+  {\r
+    And(PSAT, 0xfffffffC, PSAT)\r
+    OR(PSAT, 0X00000000, PSAT)\r
+\r
+    if(LEqual(\_SB.SDHB.PSTS,0x0))\r
+    {\r
+      if(LEqual (\_SB.GPO2.AVBL, 1))\r
+      {\r
+        Store( 0x01, \_SB.GPO2.WFD3 ) // WL_WIFI_REQ_ON = 1 put the device to normal state\r
+        Store( 0x01, \_SB.SDHB.PSTS)  // indicates that the device powered ON\r
+      }\r
+    }\r
+\r
+\r
+  }\r
+  OperationRegion (KEYS, SystemMemory, SI1A, 0x100)\r
+  Field (KEYS, DWordAcc, NoLock, WriteAsZeros)\r
+  {\r
+    Offset (0x84),\r
+           PSAT,   32\r
+  }\r
+\r
+\r
+         Device (BRCM)\r
+  {\r
+    Name (_ADR, 0x01)                 //SlotNumber + Function\r
+    Name (_DEP, Package() {\_SB.GPO2})\r
+\r
+    Method (_RMV, 0, NotSerialized)\r
+    {\r
+      Return (0x0)\r
+    }\r
+    Name (_PRW, Package() {0, 0})\r
+    Name (_S4W, 2)\r
+\r
+    Method (_CRS, 0, Serialized)\r
+    {\r
+      Name (RBUF, ResourceTemplate ()\r
+      {\r
+        Interrupt (ResourceConsumer, Edge, ActiveHigh, ExclusiveAndWake, , , ) {73}\r
+      })\r
+      Return (RBUF)\r
+    }\r
+\r
+    Method (_PS3, 0, NotSerialized)\r
+    {\r
+      if(LEqual (\_SB.GPO2.AVBL, 1))\r
+      {\r
+        Store( 0x00, \_SB.GPO2.WFD3 ) // WL_WIFI_REQ_ON = 0 puts the device in reset state\r
+        Store( 0x00, \_SB.SDHB.PSTS) //Indicates that the device is powered off\r
+      }\r
+\r
+    }\r
+    Method (_PS0, 0, NotSerialized)\r
+    {\r
+      if(LEqual(\_SB.SDHB.PSTS,0x0))\r
+      {\r
+        if(LEqual (\_SB.GPO2.AVBL, 1))\r
+        {\r
+          Store( 0x01, \_SB.GPO2.WFD3 ) // WL_WIFI_REQ_ON = 1 put the device to normal state\r
+          Store( 0x01, \_SB.SDHB.PSTS)     // indicates that the device powered ON\r
+        }\r
+      }\r
+    }\r
+  } // Device (BRCM)\r
+  //\r
+  // Secondary Broadcom WIFI function\r
+  //\r
+  Device(BRC2)\r
+  {\r
+    Name(_ADR, 0x2) // function 2\r
+    Name(_STA, 0xf)\r
+    //\r
+    // The device is not removable. This must be a method.\r
+    //\r
+    Method(_RMV, 0x0, NotSerialized)\r
+    {\r
+      Return(0x0)\r
+    }\r
+\r
+    //\r
+    // Describe a vendor-defined connection between this device and the\r
+    // primary wifi device\r
+    //\r
+\r
+    Method(_CRS)\r
+    {\r
+      Name(NAM, Buffer() {"\\_SB.SDHB.BRCM"})\r
+      Name(SPB, Buffer()\r
+      {\r
+        0x8E,       // SPB Descriptor\r
+        0x18, 0x00, // Length including NAM above\r
+        0x01,       // +0x00 SPB Descriptor Revision\r
+        0x00,       // +0x01 Resource Source Index\r
+        0xc0,       // +0x02 Bus type - vendor defined\r
+        0x02,       // +0x03 Consumer + controller initiated\r
+        0x00, 0x00, // +0x04 Type specific flags\r
+        0x01,       // +0x06 Type specific revision\r
+        0x00, 0x00  // +0x07 type specific data length\r
+        // +0x09 - 0xf bytes for NULL-terminated NAM\r
+        // Length = 0x18\r
+      })\r
+\r
+      Name(END, Buffer() {0x79, 0x00})\r
+      Concatenate(SPB, NAM, Local0)\r
+      Concatenate(Local0, END, Local1)\r
+      Return(Local1)\r
+    }\r
+  }\r
+\r
+}\r
+\r
+//\r
+// SD Card\r
+//\r
+Device(SDHC)\r
+{\r
+  Name (_ADR, 0)\r
+  Name (_HID, "80860F16")\r
+  Name (_CID, "PNP0D40")\r
+  Name (_DDN, "Intel(R) SD Card Controller - 80860F16")\r
+  Name (_UID, 3)\r
+  Name(_DEP, Package(0x01)\r
+  {\r
+    PEPD\r
+  })\r
+  Name (RBUF, ResourceTemplate ()\r
+  {\r
+    Memory32Fixed (ReadWrite, 0x00000000, 0x00001000, BAR0)\r
+    Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , ) {47}  // SD Card IRQ\r
+  })\r
+  Method (_CRS, 0x0, NotSerialized)\r
+  {\r
+    CreateDwordField(^RBUF, ^BAR0._BAS, B0BA)\r
+    CreateDwordField(^RBUF, ^BAR0._LEN, B0LN)\r
+    Store(SD0A, B0BA)\r
+    Store(SD0L, B0LN)\r
+    Return (RBUF)\r
+  }\r
+  Method (_STA, 0x0, NotSerialized)\r
+  {\r
+    //\r
+    // PCIM>> 0:ACPI mode           1:PCI mode\r
+    //\r
+    If (LEqual(PCIM, 1)) {\r
+      Return (0x0)\r
+    }\r
+\r
+    If (LOr(LEqual(SD0A, 0), LEqual(SD3D, 1)))\r
+    {\r
+      Return (0x0)\r
+    }\r
+    Return (0xF)\r
+  }\r
+\r
+  Method (_PS3, 0, NotSerialized)\r
+  {\r
+    OR(PSAT, 0x00000003, PSAT)\r
+    OR(PSAT, 0X00000000, PSAT)\r
+  }\r
+  Method (_PS0, 0, NotSerialized)\r
+  {\r
+    And(PSAT, 0xfffffffC, PSAT)\r
+    OR(PSAT, 0X00000000, PSAT)\r
+  }\r
+  OperationRegion (KEYS, SystemMemory, SD1A, 0x100)\r
+  Field (KEYS, DWordAcc, NoLock, WriteAsZeros)\r
+  {\r
+    Offset (0x84),\r
+           PSAT,   32\r
+  }\r
+\r
+  Device (CARD)\r
+  {\r
+    Name (_ADR, 0x00000008)\r
+    Method(_RMV, 0x0, NotSerialized)\r
+    {\r
+      // SDRM = 0 non-removable;\r
+      If (LEqual(SDRM, 0))\r
+      {\r
+        Return (0)\r
+      }\r
+\r
+      Return (1)\r
+    }\r
+  }\r
+\r
+}\r
+\r

diff --git a/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/PchSmb.asl b/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/PchSmb.asl
new file mode 100644 (file)
index 0000000..42ecbe2
--- /dev/null
+++ b/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/PchSmb.asl
@@ -0,0 +1,839 @@
+/**************************************************************************;\r
+;*                                                                        *;\r
+;*                                                                        *;\r
+;*    Intel Corporation - ACPI Reference Code for the Baytrail            *;\r
+;*    Family of Customer Reference Boards.                                *;\r
+;*                                                                        *;\r
+;*                                                                        *;\r
+;*    Copyright (c)  1999  - 2014, Intel Corporation. All rights reserved   *;\r
+;\r
+; This program and the accompanying materials are licensed and made available under\r
+; the terms and conditions of the BSD License that accompanies this distribution.\r
+; The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php.\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+;*                                                                        *;\r
+;*                                                                        *;\r
+;**************************************************************************/\r
+\r
+\r
+// Define various SMBus PCI Configuration Space Registers.\r
+\r
+OperationRegion(SMBP,PCI_Config,0x40,0xC0)\r
+Field(SMBP,DWordAcc,NoLock,Preserve)\r
+{\r
+  ,     2,\r
+  I2CE, 1\r
+}\r
+\r
+// SMBus Send Byte - This function will write a single byte of\r
+// data to a specific Slave Device per SMBus Send Byte Protocol.\r
+//      Arg0 = Address\r
+//      Arg1 = Data\r
+//      Return: Success = 1\r
+//              Failure = 0\r
+\r
+      Method(SSXB,2,Serialized)\r
+{\r
+  OperationRegion(SMPB,PCI_Config,0x20,4)\r
+  Field(SMPB,DWordAcc,NoLock,Preserve)\r
+  {\r
+    ,     5,\r
+    SBAR, 11\r
+  }\r
+\r
+  // Define various SMBus IO Mapped Registers.\r
+\r
+  OperationRegion(SMBI,SystemIO,ShiftLeft(SBAR,5),0x10)\r
+  Field(SMBI,ByteAcc,NoLock,Preserve)\r
+  {\r
+    HSTS, 8,        // 0 - Host Status Register\r
+    Offset(0x02),\r
+    HCON, 8,        // 2 - Host Control\r
+    HCOM, 8,        // 3 - Host Command\r
+    TXSA, 8,        // 4 - Transmit Slave Address\r
+    DAT0, 8,        // 5 - Host Data 0\r
+    DAT1, 8,        // 6 - Host Data 1\r
+    HBDR, 8,        // 7 - Host Block Data\r
+    PECR, 8,        // 8 - Packer Error Check\r
+    RXSA, 8,        // 9 - Receive Slave Address\r
+    SDAT, 16,       // A - Slave Data\r
+  }\r
+\r
+  // Step 1:  Confirm the ICHx SMBus is ready to perform\r
+  // communication.\r
+\r
+  If(STRT())\r
+  {\r
+    Return(0)\r
+  }\r
+\r
+  // Step 2:  Initiate a Send Byte.\r
+\r
+  Store(0,I2CE)                           // Ensure SMbus Mode.\r
+  Store(0xBF,HSTS)                        // Clear all but INUSE_STS.\r
+  Store(Arg0,TXSA)                        // Write Address in TXSA.\r
+  Store(Arg1,HCOM)                        // Data in HCOM.\r
+\r
+  // Set the SMBus Host control register to 0x48.\r
+  //   Bit 7:    =  0  = reserved\r
+  //   Bit 6:    =  1  = start\r
+  //   Bit 5:    =  0  = disregard, I2C related bit\r
+  //   Bits 4:2: = 001 = Byte Protocol\r
+  //   Bit 1:    =  0  = Normal Function\r
+  //   Bit 0:    =  0  = Disable interrupt generation\r
+\r
+  Store(0x48,HCON)\r
+\r
+  // Step 3:  Exit the Method correctly.\r
+\r
+  If(COMP)\r
+  {\r
+    Or(HSTS,0xFF,HSTS)              // Clear INUSE_STS and others..\r
+    Return(1)                       // Return Success.\r
+  }\r
+\r
+  Return(0)\r
+}\r
+\r
+// SMBus Receive Byte - This function will write a single byte\r
+// of data to a specific Slave Device per SMBus Receive Byte\r
+// Protocol.\r
+//      Arg0 = Address\r
+//      Return: Success = Byte-Size Value\r
+//              Failure = Word-Size Value = FFFFh.\r
+\r
+Method(SRXB,1,Serialized)\r
+{\r
+  OperationRegion(SMPB,PCI_Config,0x20,4)\r
+  Field(SMPB,DWordAcc,NoLock,Preserve)\r
+  {\r
+    ,     5,\r
+    SBAR, 11\r
+  }\r
+\r
+  // Define various SMBus IO Mapped Registers.\r
+\r
+  OperationRegion(SMBI,SystemIO,ShiftLeft(SBAR,5),0x10)\r
+  Field(SMBI,ByteAcc,NoLock,Preserve)\r
+  {\r
+    HSTS, 8,        // 0 - Host Status Register\r
+    Offset(0x02),\r
+    HCON, 8,        // 2 - Host Control\r
+    HCOM, 8,        // 3 - Host Command\r
+    TXSA, 8,        // 4 - Transmit Slave Address\r
+    DAT0, 8,        // 5 - Host Data 0\r
+    DAT1, 8,        // 6 - Host Data 1\r
+    HBDR, 8,        // 7 - Host Block Data\r
+    PECR, 8,        // 8 - Packer Error Check\r
+    RXSA, 8,        // 9 - Receive Slave Address\r
+    SDAT, 16,       // A - Slave Data\r
+  }\r
+  // Step 1:  Confirm the ICHx SMBus is ready to perform\r
+  // communication.\r
+\r
+  If(STRT())\r
+  {\r
+    Return(0xFFFF)\r
+  }\r
+\r
+  // Step 2:  Initiate a Receive Byte.\r
+\r
+  Store(0,I2CE)                           // Ensure SMbus Mode.\r
+  Store(0xBF,HSTS)                        // Clear all but INUSE_STS.\r
+  Store(Or(Arg0,1),TXSA)                  // Read Address in TXSA.\r
+\r
+  // Set the SMBus Host control register to 0x48.\r
+  //   Bit 7:    =  0  = reserved\r
+  //   Bit 6:    =  1  = start\r
+  //   Bit 5:    =  0  = disregard, I2C related bit\r
+  //   Bits 4:2: = 001 = Byte Protocol\r
+  //   Bit 1:    =  0  = Normal Function\r
+  //   Bit 0:    =  0  = Disable interrupt generation\r
+\r
+  Store(0x44,HCON)\r
+\r
+  // Step 3:  Exit the Method correctly.\r
+\r
+  If(COMP)\r
+  {\r
+    Or(HSTS,0xFF,HSTS)              // Clear INUSE_STS and others..\r
+    Return(DAT0)                    // Return Success.\r
+  }\r
+\r
+  Return(0xFFFF)                          // Return Failure.\r
+}\r
+\r
+// SMBus Write Byte - This function will write a single byte\r
+// of data to a specific Slave Device per SMBus Write Byte\r
+// Protocol.\r
+//      Arg0 = Address\r
+//      Arg1 = Command\r
+//      Arg2 = Data\r
+//      Return: Success = 1\r
+//              Failure = 0\r
+\r
+Method(SWRB,3,Serialized)\r
+{\r
+  OperationRegion(SMPB,PCI_Config,0x20,4)\r
+  Field(SMPB,DWordAcc,NoLock,Preserve)\r
+  {\r
+    ,     5,\r
+    SBAR, 11\r
+  }\r
+\r
+  // Define various SMBus IO Mapped Registers.\r
+\r
+  OperationRegion(SMBI,SystemIO,ShiftLeft(SBAR,5),0x10)\r
+  Field(SMBI,ByteAcc,NoLock,Preserve)\r
+  {\r
+    HSTS, 8,        // 0 - Host Status Register\r
+    Offset(0x02),\r
+    HCON, 8,        // 2 - Host Control\r
+    HCOM, 8,        // 3 - Host Command\r
+    TXSA, 8,        // 4 - Transmit Slave Address\r
+    DAT0, 8,        // 5 - Host Data 0\r
+    DAT1, 8,        // 6 - Host Data 1\r
+    HBDR, 8,        // 7 - Host Block Data\r
+    PECR, 8,        // 8 - Packer Error Check\r
+    RXSA, 8,        // 9 - Receive Slave Address\r
+    SDAT, 16,       // A - Slave Data\r
+  }\r
+  // Step 1:  Confirm the ICHx SMBus is ready to perform communication.\r
+\r
+  If(STRT())\r
+  {\r
+    Return(0)\r
+  }\r
+\r
+  // Step 2:  Initiate a Write Byte.\r
+\r
+  Store(0,I2CE)                           // Ensure SMbus Mode.\r
+  Store(0xBF,HSTS)                        // Clear all but INUSE_STS.\r
+  Store(Arg0,TXSA)                        // Write Address in TXSA.\r
+  Store(Arg1,HCOM)                        // Command in HCOM.\r
+  Store(Arg2,DAT0)                        // Data in DAT0.\r
+\r
+  // Set the SMBus Host control register to 0x48.\r
+  //   Bit 7:    =  0  = reserved\r
+  //   Bit 6:    =  1  = start\r
+  //   Bit 5:    =  0  = disregard, I2C related bit\r
+  //   Bits 4:2: = 010 = Byte Data Protocol\r
+  //   Bit 1:    =  0  = Normal Function\r
+  //   Bit 0:    =  0  = Disable interrupt generation\r
+\r
+  Store(0x48,HCON)\r
+\r
+  // Step 3:  Exit the Method correctly.\r
+\r
+  If(COMP)\r
+  {\r
+    Or(HSTS,0xFF,HSTS)              // Clear INUSE_STS and others..\r
+    Return(1)                       // Return Success.\r
+  }\r
+\r
+  Return(0)                               // Return Failure.\r
+}\r
+\r
+// SMBus Read Byte - This function will read a single byte of data\r
+// from a specific slave device per SMBus Read Byte Protocol.\r
+//      Arg0 = Address\r
+//      Arg1 = Command\r
+//      Return: Success = Byte-Size Value\r
+//              Failure = Word-Size Value\r
+\r
+Method(SRDB,2,Serialized)\r
+{\r
+  OperationRegion(SMPB,PCI_Config,0x20,4)\r
+  Field(SMPB,DWordAcc,NoLock,Preserve)\r
+  {\r
+    ,     5,\r
+    SBAR, 11\r
+  }\r
+\r
+  // Define various SMBus IO Mapped Registers.\r
+\r
+  OperationRegion(SMBI,SystemIO,ShiftLeft(SBAR,5),0x10)\r
+  Field(SMBI,ByteAcc,NoLock,Preserve)\r
+  {\r
+    HSTS, 8,        // 0 - Host Status Register\r
+    Offset(0x02),\r
+    HCON, 8,        // 2 - Host Control\r
+    HCOM, 8,        // 3 - Host Command\r
+    TXSA, 8,        // 4 - Transmit Slave Address\r
+    DAT0, 8,        // 5 - Host Data 0\r
+    DAT1, 8,        // 6 - Host Data 1\r
+    HBDR, 8,        // 7 - Host Block Data\r
+    PECR, 8,        // 8 - Packer Error Check\r
+    RXSA, 8,        // 9 - Receive Slave Address\r
+    SDAT, 16,       // A - Slave Data\r
+  }\r
+  // Step 1:  Confirm the ICHx SMBus is ready to perform communication.\r
+\r
+  If(STRT())\r
+  {\r
+    Return(0xFFFF)\r
+  }\r
+\r
+  // Step 2:  Initiate a Read Byte.\r
+\r
+  Store(0,I2CE)                           // Ensure SMbus Mode.\r
+  Store(0xBF,HSTS)                        // Clear all but INUSE_STS.\r
+  Store(Or(Arg0,1),TXSA)                  // Read Address in TXSA.\r
+  Store(Arg1,HCOM)                        // Command in HCOM.\r
+\r
+  // Set the SMBus Host control register to 0x48.\r
+  //   Bit 7:    =  0  = reserved\r
+  //   Bit 6:    =  1  = start\r
+  //   Bit 5:    =  0  = disregard, I2C related bit\r
+  //   Bits 4:2: = 010 = Byte Data Protocol\r
+  //   Bit 1:    =  0  = Normal Function\r
+  //   Bit 0:    =  0  = Disable interrupt generation\r
+\r
+  Store(0x48,HCON)\r
+\r
+  // Step 3:  Exit the Method correctly.\r
+\r
+  If(COMP)\r
+  {\r
+    Or(HSTS,0xFF,HSTS)              // Clear INUSE_STS and others..\r
+    Return(DAT0)                    // Return Success.\r
+  }\r
+\r
+  Return(0xFFFF)                          // Return Failure.\r
+}\r
+\r
+// SMBus Write Word - This function will write a single word\r
+// of data to a specific Slave Device per SMBus Write Word\r
+// Protocol.\r
+//      Arg0 = Address\r
+//      Arg1 = Command\r
+//      Arg2 = Data (16 bits in size)\r
+//      Return: Success = 1\r
+//              Failure = 0\r
+\r
+Method(SWRW,3,Serialized)\r
+{\r
+  OperationRegion(SMPB,PCI_Config,0x20,4)\r
+  Field(SMPB,DWordAcc,NoLock,Preserve)\r
+  {\r
+    ,     5,\r
+    SBAR, 11\r
+  }\r
+\r
+  // Define various SMBus IO Mapped Registers.\r
+\r
+  OperationRegion(SMBI,SystemIO,ShiftLeft(SBAR,5),0x10)\r
+  Field(SMBI,ByteAcc,NoLock,Preserve)\r
+  {\r
+    HSTS, 8,        // 0 - Host Status Register\r
+    Offset(0x02),\r
+       HCON, 8,        // 2 - Host Control\r
+       HCOM, 8,        // 3 - Host Command\r
+       TXSA, 8,        // 4 - Transmit Slave Address\r
+       DAT0, 8,        // 5 - Host Data 0\r
+       DAT1, 8,        // 6 - Host Data 1\r
+       HBDR, 8,        // 7 - Host Block Data\r
+       PECR, 8,        // 8 - Packer Error Check\r
+       RXSA, 8,        // 9 - Receive Slave Address\r
+       SDAT, 16,       // A - Slave Data\r
+  }\r
+  // Step 1:  Confirm the ICHx SMBus is ready to perform communication.\r
+\r
+  If(STRT())\r
+  {\r
+    Return(0)\r
+  }\r
+\r
+  // Step 2:  Initiate a Write Word.\r
+\r
+  Store(0,I2CE)                           // Ensure SMbus Mode.\r
+  Store(0xBF,HSTS)                        // Clear all but INUSE_STS.\r
+  Store(Arg0,TXSA)                        // Write Address in TXSA.\r
+  Store(Arg1,HCOM)                        // Command in HCOM.\r
+  And(Arg2,0xFF,DAT1)                     // Low byte Data in DAT1.\r
+  And(ShiftRight(Arg2,8),0xFF,DAT0)       // High byte Data in DAT0.\r
+\r
+  // Set the SMBus Host control register to 0x4C.\r
+  //   Bit 7:    =  0  = reserved\r
+  //   Bit 6:    =  1  = start\r
+  //   Bit 5:    =  0  = disregard, I2C related bit\r
+  //   Bits 4:2: = 011 = Word Data Protocol\r
+  //   Bit 1:    =  0  = Normal Function\r
+  //   Bit 0:    =  0  = Disable interrupt generation\r
+\r
+  Store(0x4C,HCON)\r
+\r
+  // Step 3:  Exit the Method correctly.\r
+\r
+  If(COMP())\r
+  {\r
+    Or(HSTS,0xFF,HSTS)              // Clear INUSE_STS and others.\r
+    Return(1)                       // Return Success.\r
+  }\r
+\r
+  Return(0)                               // Return Failure.\r
+}\r
+\r
+// SMBus Read Word - This function will read a single byte of data\r
+// from a specific slave device per SMBus Read Word Protocol.\r
+//      Arg0 = Address\r
+//      Arg1 = Command\r
+//      Return: Success = Word-Size Value\r
+//              Failure = Dword-Size Value\r
+\r
+Method(SRDW,2,Serialized)\r
+{\r
+  OperationRegion(SMPB,PCI_Config,0x20,4)\r
+  Field(SMPB,DWordAcc,NoLock,Preserve)\r
+  {\r
+    ,     5,\r
+    SBAR, 11\r
+  }\r
+\r
+  // Define various SMBus IO Mapped Registers.\r
+\r
+  OperationRegion(SMBI,SystemIO,ShiftLeft(SBAR,5),0x10)\r
+  Field(SMBI,ByteAcc,NoLock,Preserve)\r
+  {\r
+    HSTS, 8,        // 0 - Host Status Register\r
+       Offset(0x02),\r
+       HCON, 8,        // 2 - Host Control\r
+       HCOM, 8,        // 3 - Host Command\r
+       TXSA, 8,        // 4 - Transmit Slave Address\r
+       DAT0, 8,        // 5 - Host Data 0\r
+       DAT1, 8,        // 6 - Host Data 1\r
+       HBDR, 8,        // 7 - Host Block Data\r
+       PECR, 8,        // 8 - Packer Error Check\r
+       RXSA, 8,        // 9 - Receive Slave Address\r
+       SDAT, 16,       // A - Slave Data\r
+  }\r
+  // Step 1:  Confirm the ICHx SMBus is ready to perform communication.\r
+\r
+  If(STRT())\r
+  {\r
+    Return(0xFFFF)\r
+  }\r
+\r
+  // Step 2:  Initiate a Read Word.\r
+\r
+  Store(0,I2CE)                           // Ensure SMbus Mode.\r
+  Store(0xBF,HSTS)                        // Clear all but INUSE_STS.\r
+  Store(Or(Arg0,1),TXSA)                  // Read Address in TXSA.\r
+  Store(Arg1,HCOM)                        // Command in HCOM.\r
+\r
+  // Set the SMBus Host control register to 0x4C.\r
+  //   Bit 7:    =  0  = reserved\r
+  //   Bit 6:    =  1  = start\r
+  //   Bit 5:    =  0  = disregard, I2C related bit\r
+  //   Bits 4:2: = 011 = Word Data Protocol\r
+  //   Bit 1:    =  0  = Normal Function\r
+  //   Bit 0:    =  0  = Disable interrupt generation\r
+\r
+  Store(0x4C,HCON)\r
+\r
+  // Step 3:  Exit the Method correctly.\r
+\r
+  If(COMP())\r
+  {\r
+    Or(HSTS,0xFF,HSTS)                      // Clear INUSE_STS and others.\r
+    Return(Or(ShiftLeft(DAT0,8),DAT1))      // Return Success.\r
+  }\r
+\r
+  Return(0xFFFFFFFF)                      // Return Failure.\r
+}\r
+\r
+// SMBus Block Write - This function will write an entire block of data\r
+// to a specific slave device per SMBus Block Write Protocol.\r
+//      Arg0 = Address\r
+//      Arg1 = Command\r
+//      Arg2 = Buffer of Data to Write\r
+//      Arg3 = 1 = I2C Block Write, 0 = SMBus Block Write\r
+//      Return: Success = 1\r
+//              Failure = 0\r
+\r
+Method(SBLW,4,Serialized)\r
+{\r
+  OperationRegion(SMPB,PCI_Config,0x20,4)\r
+  Field(SMPB,DWordAcc,NoLock,Preserve)\r
+  {\r
+    ,     5,\r
+    SBAR, 11\r
+  }\r
+\r
+  // Define various SMBus IO Mapped Registers.\r
+\r
+  OperationRegion(SMBI,SystemIO,ShiftLeft(SBAR,5),0x10)\r
+  Field(SMBI,ByteAcc,NoLock,Preserve)\r
+  {\r
+    HSTS, 8,        // 0 - Host Status Register\r
+       Offset(0x02),\r
+       HCON, 8,        // 2 - Host Control\r
+       HCOM, 8,        // 3 - Host Command\r
+       TXSA, 8,        // 4 - Transmit Slave Address\r
+       DAT0, 8,        // 5 - Host Data 0\r
+       DAT1, 8,        // 6 - Host Data 1\r
+       HBDR, 8,        // 7 - Host Block Data\r
+       PECR, 8,        // 8 - Packer Error Check\r
+       RXSA, 8,        // 9 - Receive Slave Address\r
+       SDAT, 16,       // A - Slave Data\r
+  }\r
+  // Step 1:  Confirm the ICHx SMBus is ready to perform communication.\r
+\r
+  If(STRT())\r
+  {\r
+    Return(0)\r
+  }\r
+\r
+  // Step 2:  Initiate a Block Write.\r
+\r
+  Store(Arg3,I2CE)                        // Select the proper protocol.\r
+  Store(0xBF,HSTS)                        // Clear all but INUSE_STS.\r
+  Store(Arg0,TXSA)                        // Write Address in TXSA.\r
+  Store(Arg1,HCOM)                        // Command in HCOM.\r
+  Store(Sizeof(Arg2),DAT0)                // Count in DAT0.\r
+  Store(0,Local1)                         // Init Pointer to Buffer.\r
+  Store(DerefOf(Index(Arg2,0)),HBDR)      // First Byte in HBD Register.\r
+\r
+  // Set the SMBus Host control register to 0x48.\r
+  //   Bit 7:    =  0  = reserved\r
+  //   Bit 6:    =  1  = start\r
+  //   Bit 5:    =  0  = disregard, I2C related bit\r
+  //   Bits 4:2: = 101 = Block Protocol\r
+  //   Bit 1:    =  0  = Normal Function\r
+  //   Bit 0:    =  0  = Disable interrupt generation\r
+\r
+  Store(0x54,HCON)\r
+\r
+  // Step 3:  Send the entire Block of Data.\r
+\r
+  While(LGreater(Sizeof(Arg2),Local1))\r
+  {\r
+    // Wait up to 200ms for Host Status to get set.\r
+\r
+    Store(4000,Local0)              // 4000 * 50us = 200ms.\r
+\r
+    While(LAnd(LNot(And(HSTS,0x80)),Local0))\r
+    {\r
+      Decrement(Local0)       // Decrement Count.\r
+      Stall(50)               // Delay = 50us.\r
+    }\r
+\r
+    If(LNot(Local0))                // Timeout?\r
+    {\r
+      KILL()                  // Yes.  Kill Communication.\r
+      Return(0)               // Return failure.\r
+    }\r
+\r
+    Store(0x80,HSTS)                // Clear Host Status.\r
+    Increment(Local1)               // Point to Next Byte.\r
+\r
+    // Place next byte in HBDR if last byte has not been sent.\r
+\r
+    If(LGreater(Sizeof(Arg2),Local1))\r
+    {\r
+      Store(DerefOf(Index(Arg2,Local1)),HBDR)\r
+    }\r
+  }\r
+\r
+  // Step 4:  Exit the Method correctly.\r
+\r
+  If(COMP())\r
+  {\r
+    Or(HSTS,0xFF,HSTS)              // Clear all status bits.\r
+    Return(1)                       // Return Success.\r
+  }\r
+\r
+  Return(0)                               // Return Failure.\r
+}\r
+\r
+// SMBus Block Read - This function will read a block of data from\r
+// a specific slave device per SMBus Block Read Protocol.\r
+//      Arg0 = Address\r
+//      Arg1 = Command\r
+//      Arg2 = 1 = I2C Block Write, 0 = SMBus Block Write\r
+//      Return: Success = Data Buffer (First Byte = length)\r
+//              Failure = 0\r
+\r
+Method(SBLR,3,Serialized)\r
+{\r
+  OperationRegion(SMPB,PCI_Config,0x20,4)\r
+  Field(SMPB,DWordAcc,NoLock,Preserve)\r
+  {\r
+    ,     5,\r
+    SBAR, 11\r
+  }\r
+\r
+  // Define various SMBus IO Mapped Registers.\r
+\r
+  OperationRegion(SMBI,SystemIO,ShiftLeft(SBAR,5),0x10)\r
+  Field(SMBI,ByteAcc,NoLock,Preserve)\r
+  {\r
+    HSTS, 8,        // 0 - Host Status Register\r
+       Offset(0x02),\r
+       HCON, 8,        // 2 - Host Control\r
+       HCOM, 8,        // 3 - Host Command\r
+       TXSA, 8,        // 4 - Transmit Slave Address\r
+       DAT0, 8,        // 5 - Host Data 0\r
+       DAT1, 8,        // 6 - Host Data 1\r
+       HBDR, 8,        // 7 - Host Block Data\r
+       PECR, 8,        // 8 - Packer Error Check\r
+       RXSA, 8,        // 9 - Receive Slave Address\r
+       SDAT, 16,       // A - Slave Data\r
+  }\r
+  Name(TBUF, Buffer(256) {})\r
+\r
+  // Step 1:  Confirm the ICHx SMBus is ready to perform communication.\r
+\r
+  If(STRT())\r
+  {\r
+    Return(0)\r
+  }\r
+\r
+  // Step 2:  Initiate a Block Read.\r
+\r
+  Store(Arg2,I2CE)                        // Select the proper protocol.\r
+  Store(0xBF,HSTS)                        // Clear all but INUSE_STS.\r
+  Store(Or(Arg0,1),TXSA)                  // Read Address in TXSA.\r
+  Store(Arg1,HCOM)                        // Command in HCOM.\r
+\r
+  // Set the SMBus Host control register to 0x48.\r
+  //   Bit 7:    =  0  = reserved\r
+  //   Bit 6:    =  1  = start\r
+  //   Bit 5:    =  0  = disregard, I2C related bit\r
+  //   Bits 4:2: = 101 = Block Protocol\r
+  //   Bit 1:    =  0  = Normal Function\r
+  //   Bit 0:    =  0  = Disable interrupt generation\r
+\r
+  Store(0x54,HCON)\r
+\r
+  // Step 3:  Wait up to 200ms to get the Data Count.\r
+\r
+  Store(4000,Local0)                      // 4000 * 50us = 200ms.\r
+\r
+  While(LAnd(LNot(And(HSTS,0x80)),Local0))\r
+  {\r
+    Decrement(Local0)               // Decrement Count.\r
+    Stall(50)                       // Delay = 50us.\r
+  }\r
+\r
+  If(LNot(Local0))                        // Timeout?\r
+  {\r
+    KILL()                          // Yes.  Kill Communication.\r
+    Return(0)                       // Return failure.\r
+  }\r
+\r
+  Store(DAT0,Index(TBUF,0))               // Get the Data Count.\r
+  Store(0x80,HSTS)                        // Clear Host Status.\r
+  Store(1,Local1)                         // Local1 = Buffer Pointer.\r
+\r
+  // Step 4:  Get the Block Data and store it.\r
+\r
+  While(LLess(Local1,DerefOf(Index(TBUF,0))))\r
+  {\r
+    // Wait up to 200ms for Host Status to get set.\r
+\r
+    Store(4000,Local0)              // 4000 * 50us = 200ms.\r
+\r
+    While(LAnd(LNot(And(HSTS,0x80)),Local0))\r
+    {\r
+      Decrement(Local0)       // Decrement Count.\r
+      Stall(50)               // Delay = 50us.\r
+    }\r
+\r
+    If(LNot(Local0))                // Timeout?\r
+    {\r
+      KILL()                  // Yes.  Kill Communication.\r
+      Return(0)               // Return failure.\r
+    }\r
+\r
+    Store(HBDR,Index(TBUF,Local1))  // Place into Buffer.\r
+    Store(0x80,HSTS)                // Clear Host Status.\r
+    Increment(Local1)\r
+  }\r
+\r
+  // Step 5:  Exit the Method correctly.\r
+\r
+  If(COMP())\r
+  {\r
+    Or(HSTS,0xFF,HSTS)              // Clear INUSE_STS and others.\r
+    Return(TBUF)                    // Return Success.\r
+  }\r
+\r
+  Return(0)                               // Return Failure.\r
+}\r
+\r
+\r
+// SMBus Start Check\r
+//      Return: Success = 0\r
+//              Failure = 1\r
+\r
+Method(STRT,0,Serialized)\r
+{\r
+  OperationRegion(SMPB,PCI_Config,0x20,4)\r
+  Field(SMPB,DWordAcc,NoLock,Preserve)\r
+  {\r
+    ,     5,\r
+    SBAR, 11\r
+  }\r
+\r
+  // Define various SMBus IO Mapped Registers.\r
+\r
+  OperationRegion(SMBI,SystemIO,ShiftLeft(SBAR,5),0x10)\r
+  Field(SMBI,ByteAcc,NoLock,Preserve)\r
+  {\r
+    HSTS, 8,        // 0 - Host Status Register\r
+       Offset(0x02),\r
+       HCON, 8,        // 2 - Host Control\r
+       HCOM, 8,        // 3 - Host Command\r
+       TXSA, 8,        // 4 - Transmit Slave Address\r
+       DAT0, 8,        // 5 - Host Data 0\r
+       DAT1, 8,        // 6 - Host Data 1\r
+       HBDR, 8,        // 7 - Host Block Data\r
+       PECR, 8,        // 8 - Packer Error Check\r
+       RXSA, 8,        // 9 - Receive Slave Address\r
+       SDAT, 16,       // A - Slave Data\r
+  }\r
+  // Wait up to 200ms to confirm the SMBus Semaphore has been\r
+  // released (In Use Status = 0).  Note that the Sleep time may take\r
+  // longer as the This function will yield the Processor such that it\r
+  // may perform different tasks during the delay.\r
+\r
+  Store(200,Local0)                       // 200 * 1ms = 200ms.\r
+\r
+  While(Local0)\r
+  {\r
+    If(And(HSTS,0x40))              // In Use Set?\r
+    {\r
+      Decrement(Local0)       // Yes.  Decrement Count.\r
+      Sleep(1)                // Delay = 1ms.\r
+      If(LEqual(Local0,0))    // Count = 0?\r
+      {\r
+        Return(1)       // Return failure.\r
+      }\r
+    }\r
+    Else\r
+    {\r
+      Store(0,Local0)         // In Use Clear.  Continue.\r
+    }\r
+  }\r
+\r
+  // In Use Status = 0 during last read, which will make subsequent\r
+  // reads return In Use Status = 1 until software clears it.  All\r
+  // software using ICHx SMBus should check this bit before initiating\r
+  // any SMBus communication.\r
+\r
+  // Wait up to 200ms to confirm the Host Interface is\r
+  // not processing a command.\r
+\r
+  Store(4000,Local0)                      // 4000 * 50us = 200ms.\r
+\r
+  While(Local0)\r
+  {\r
+    If(And(HSTS,0x01))              // Host Busy Set?\r
+    {\r
+      Decrement(Local0)       // Decrement Count.\r
+      Stall(50)               // Delay = 50us.\r
+      If(LEqual(Local0,0))    // Count = 0?\r
+      {\r
+        KILL()          // Yes.  Kill Communication.\r
+      }\r
+    }\r
+    Else\r
+    {\r
+      Return(0)\r
+    }\r
+  }\r
+\r
+  Return(1)                               // Timeout.  Return failure.\r
+}\r
+\r
+// SMBus Completion Check\r
+//      Return: Success = 1\r
+//              Failure = 0\r
+\r
+Method(COMP,0,Serialized)\r
+{\r
+  OperationRegion(SMPB,PCI_Config,0x20,4)\r
+  Field(SMPB,DWordAcc,NoLock,Preserve)\r
+  {\r
+    ,     5,\r
+    SBAR, 11\r
+  }\r
+\r
+  // Define various SMBus IO Mapped Registers.\r
+\r
+  OperationRegion(SMBI,SystemIO,ShiftLeft(SBAR,5),0x10)\r
+  Field(SMBI,ByteAcc,NoLock,Preserve)\r
+  {\r
+    HSTS, 8,        // 0 - Host Status Register\r
+       Offset(0x02),\r
+       HCON, 8,        // 2 - Host Control\r
+       HCOM, 8,        // 3 - Host Command\r
+       TXSA, 8,        // 4 - Transmit Slave Address\r
+       DAT0, 8,        // 5 - Host Data 0\r
+       DAT1, 8,        // 6 - Host Data 1\r
+       HBDR, 8,        // 7 - Host Block Data\r
+       PECR, 8,        // 8 - Packer Error Check\r
+       RXSA, 8,        // 9 - Receive Slave Address\r
+       SDAT, 16,       // A - Slave Data\r
+  }\r
+  // Wait for up to 200ms for the Completion Command\r
+  // Status to get set.\r
+\r
+  Store(4000,Local0)                      // 4000 * 50us = 200ms.\r
+\r
+  While(Local0)\r
+  {\r
+    If(And(HSTS,0x02))              // Completion Status Set?\r
+    {\r
+      Return(1)               // Yes.  We are done.\r
+    }\r
+    Else\r
+    {\r
+      Decrement(Local0)       // Decrement Count.\r
+      Stall(50)               // Delay 50us.\r
+      If(LEqual(Local0,0))    // Count = 0?\r
+      {\r
+        KILL()          // Yes.  Kill Communication.\r
+      }\r
+    }\r
+  }\r
+\r
+  Return(0)                               // Timeout.  Return Failure.\r
+}\r
+\r
+// SMBus Kill Command\r
+\r
+Method(KILL,0,Serialized)\r
+{\r
+  OperationRegion(SMPB,PCI_Config,0x20,4)\r
+  Field(SMPB,DWordAcc,NoLock,Preserve)\r
+  {\r
+    ,     5,\r
+    SBAR, 11\r
+  }\r
+\r
+  // Define various SMBus IO Mapped Registers.\r
+\r
+  OperationRegion(SMBI,SystemIO,ShiftLeft(SBAR,5),0x10)\r
+  Field(SMBI,ByteAcc,NoLock,Preserve)\r
+  {\r
+    HSTS, 8,        // 0 - Host Status Register\r
+       Offset(0x02),\r
+       HCON, 8,        // 2 - Host Control\r
+       HCOM, 8,        // 3 - Host Command\r
+       TXSA, 8,        // 4 - Transmit Slave Address\r
+       DAT0, 8,        // 5 - Host Data 0\r
+       DAT1, 8,        // 6 - Host Data 1\r
+       HBDR, 8,        // 7 - Host Block Data\r
+       PECR, 8,        // 8 - Packer Error Check\r
+       RXSA, 8,        // 9 - Receive Slave Address\r
+       SDAT, 16,       // A - Slave Data\r
+  }\r
+  Or(HCON,0x02,HCON)                      // Yes.  Send Kill command.\r
+  Or(HSTS,0xFF,HSTS)                      // Clear all status.\r
+}\r

diff --git a/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/PchXhci.asl b/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/PchXhci.asl
new file mode 100644 (file)
index 0000000..696a541
--- /dev/null
+++ b/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/PchXhci.asl
@@ -0,0 +1,385 @@
+/**************************************************************************;\r
+;*                                                                        *;\r
+;*                                                                        *;\r
+;*    Intel Corporation - ACPI Reference Code for the Haswell             *;\r
+;*    Family of Customer Reference Boards.                                *;\r
+;*                                                                        *;\r
+;*                                                                        *;\r
+;*    Copyright (c)  2010  - 2014, Intel Corporation. All rights reserved   *;\r
+;\r
+; This program and the accompanying materials are licensed and made available under\r
+; the terms and conditions of the BSD License that accompanies this distribution.\r
+; The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php.\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+;*                                                                        *;\r
+;*                                                                        *;\r
+;**************************************************************************/\r
+\r
+//scope is \_SB.PCI0.XHC\r
+Device(XHC1)\r
+{\r
+  Name(_ADR, 0x00140000)                     //Device 20, Function 0\r
+\r
+  //When it is in Host mode, USH core is connected to USB3 microAB(USB3 P1 and USB2 P0)\r
+  Name (_DDN, "Baytrail XHCI controller (CCG core/Host only)" )\r
+\r
+  Method(XDEP, 0)\r
+  {\r
+    If(LEqual(OSYS,2013))\r
+    {\r
+      Name(_DEP, Package(0x1)\r
+      {\r
+        PEPD\r
+      })\r
+    }\r
+  }\r
+\r
+  Name (_STR, Unicode ("Baytrail XHCI controller (CCG core/Host only)"))\r
+  Name(_PRW, Package() {0xD,4})\r
+\r
+  Method(_PSW,1)\r
+  {\r
+    If (LAnd (PMES, PMEE)) {\r
+       Store (0, PMEE)\r
+       Store (1, PMES)\r
+    }\r
+  }\r
+\r
+  OperationRegion (PMEB, PCI_Config, 0x74, 0x04)  // Power Management Control/Status\r
+  Field (PMEB, WordAcc, NoLock, Preserve)\r
+  {\r
+    ,   8,\r
+    PMEE,   1,   //bit8 PME_En\r
+    ,   6,\r
+    PMES,   1    //bit15 PME_Status\r
+  }\r
+\r
+  Method(_STA, 0)\r
+  {\r
+    If(LNotEqual(XHCI, 0))      //NVS variable controls present of XHCI controller\r
+    {\r
+      Return (0xF)\r
+    } Else\r
+    {\r
+      Return (0x0)\r
+    }\r
+  }\r
+\r
+  OperationRegion(XPRT,PCI_Config,0xD0,0x10)\r
+  Field(XPRT,DWordAcc,NoLock,Preserve)       //usbx_top.doc.xml\r
+  {\r
+    PR2,  32,                              //bit[8:0] USB2HCSEL\r
+    PR2M, 32,                              //bit[8:0] USB2HCSELM\r
+    PR3,  32,                              //bit[3:0] USB3SSEN\r
+    PR3M, 32                               //bit[3:0] USB3SSENM\r
+  }\r
+\r
+  Device(RHUB)\r
+  {\r
+    Name(_ADR, Zero)         //address 0 is reserved for root hub\r
+\r
+    //\r
+    // Super Speed Ports - must match _UPC declarations of the coresponding Full Speed Ports.\r
+    //   Paired with Port 1\r
+    Device(SSP1)\r
+    {\r
+      Name(_ADR, 0x07)\r
+\r
+      Method(_UPC,0,Serialized)\r
+      {\r
+        Name(UPCP, Package()\r
+        {\r
+          0xFF,                                      // Port is connectable if non-zero\r
+          0x06,                                      // USB3 uAB connector\r
+          0x00,\r
+          0x00\r
+        })\r
+        Return(UPCP)\r
+      }\r
+\r
+      Method(_PLD,0,Serialized)\r
+      {\r
+        Name(PLDP, Package()       //pls check ACPI 5.0 section 6.1.8\r
+        {\r
+          Buffer(0x14)\r
+          {\r
+            //31:0   - Bit[6:0]=2 revision is 0x2, Bit[7]=1 Ignore Color Bit[31:8]=0 RGB color is ignored\r
+            0x82, 0x00, 0x00, 0x00,\r
+            //63:32 - Bit[47:32]=0 width: 0x0000  Bit[63:48]=0 Height:0x0000\r
+            0x00, 0x00, 0x00, 0x00,\r
+            //95:64 - bit[66:64]=b'011 visiable/docking/no lid bit[69:67]=b'001 bottom panel bit[71:70]=b'01 Center  bit[73:72]=b'01 Center\r
+            //           bit[77:74]=6 Horizontal Trapezoid bit[78]=0 bit[86:79]=0 bit[94:87]='0 no group info' bit[95]=0 not a bay\r
+            0x4B, 0x19, 0x00, 0x00,\r
+            //127:96 -bit[96]=1 Ejectable bit[97]=1 OSPM Ejection required Bit[105:98]=0 no Cabinet Number\r
+            //            bit[113:106]=0 no Card cage Number bit[114]=0 no reference shape Bit[118:115]=0 no rotation Bit[123:119]=0 no order\r
+            0x03, 0x00, 0x00, 0x00,\r
+            //159:128  Vert. and Horiz. Offsets not supplied\r
+            0xFF, 0xFF, 0xFF, 0xFF\r
+          }\r
+        })\r
+        Return (PLDP)\r
+      }\r
+    }\r
+    //\r
+    // High Speed Ports\r
+    // pair port with port 7 (SS)\r
+    //    The UPC declarations for LS/FS/HS and SS ports that are paired to form a USB3.0 compatible connector.\r
+    //    A "pair" is defined by two ports that declare _PLDs with identical Panel, Vertical Position, Horizontal Postion, Shape, Group Orientation\r
+    //    and Group Token\r
+    Device(HS01)\r
+    {\r
+      Name(_ADR, 0x01)\r
+\r
+      Method(_UPC,0,Serialized)\r
+      {\r
+        Name(UPCP, Package() { 0xFF,0x06,0x00,0x00 })\r
+        Return(UPCP)\r
+      }\r
+\r
+      Method(_PLD,0,Serialized)\r
+      {\r
+        Name(PLDP, Package()       //pls check ACPI 5.0 section 6.1.8\r
+        {\r
+          Buffer(0x14)\r
+          {\r
+            //31:0   - Bit[6:0]=2 revision is 0x2, Bit[7]=1 Ignore Color Bit[31:8]=0 RGB color is ignored\r
+            0x82, 0x00, 0x00, 0x00,\r
+            //63:32 - Bit[47:32]=0 width: 0x0000  Bit[63:48]=0 Height:0x0000\r
+            0x00, 0x00, 0x00, 0x00,\r
+            //95:64 - bit[66:64]=b'011 visiable/docking/no lid bit[69:67]=b'001 bottom panel bit[71:70]=b'01 Center  bit[73:72]=b'01 Center\r
+            //           bit[77:74]=6 Horizontal Trapezoid bit[78]=0 bit[86:79]=0 bit[94:87]='0 no group info' bit[95]=0 not a bay\r
+            0x4B, 0x19, 0x00, 0x00,\r
+            //127:96 -bit[96]=1 Ejectable bit[97]=1 OSPM Ejection required Bit[105:98]=0 no Cabinet Number\r
+            //            bit[113:106]=0 no Card cage Number bit[114]=0 no reference shape Bit[118:115]=0 no rotation Bit[123:119]=0 no order\r
+            0x03, 0x00, 0x00, 0x00,\r
+            //159:128  Vert. and Horiz. Offsets not supplied\r
+            0xFF, 0xFF, 0xFF, 0xFF\r
+          }\r
+        })\r
+        Return (PLDP)\r
+      }\r
+    }//end of HS01\r
+\r
+    // USB2 Type-A/USB2 only\r
+    // EHCI debug capable\r
+    Device(HS02)\r
+    {\r
+      Name(_ADR, 0x02)                                   // 0 is for root hub so physical port index starts from 1 (it is port1 in schematic)\r
+\r
+      Method(_UPC,0,Serialized)\r
+      {\r
+        Name(UPCP, Package()\r
+        {\r
+          0xFF,                     // connectable\r
+          0xFF,                     //\r
+          0x00,\r
+          0x00\r
+        })\r
+\r
+        Return(UPCP)\r
+      }\r
+\r
+      Method(_PLD,0,Serialized)\r
+      {\r
+        Name(PLDP, Package()\r
+        {\r
+          Buffer(0x14)\r
+          {\r
+            //31:0   - Bit[6:0]=2 revision is 0x2, Bit[7]=1 Ignore Color Bit[31:8]=0 RGB color is ignored\r
+            0x82, 0x00, 0x00, 0x00,\r
+            //63:32 - Bit[47:32]=0 width: 0x0000  Bit[63:48]=0 Height:0x0000\r
+            0x00, 0x00, 0x00, 0x00,\r
+            //95:64 - bit[66:64]=b'000 not visiable/no docking/no lid bit[69:67]=b'000 top bit[71:70]=b'01 Center  bit[73:72]=b'00 Left\r
+            //           bit[77:74]=2 Square bit[78]=0 bit[86:79]=0 bit[94:87]='0 no group info' bit[95]=0 not a bay\r
+            0x40, 0x08, 0x00, 0x00,\r
+            //127:96 -bit[96]=0 not Ejectable bit[97]=0 no OSPM Ejection required Bit[105:98]=0 no Cabinet Number\r
+            //            bit[113:106]=0 no Card cage Number bit[114]=0 no reference shape Bit[118:115]=0 no rotation Bit[123:119]=0 no order\r
+            0x00, 0x00, 0x00, 0x00,\r
+            //159:128  Vert. and Horiz. Offsets not supplied\r
+            0xFF, 0xFF, 0xFF, 0xFF\r
+          }\r
+        })\r
+\r
+        Return (PLDP)\r
+      }\r
+    }//end of HS02\r
+    // high speed port 3\r
+    Device(HS03)\r
+    {\r
+      Name(_ADR, 0x03)\r
+\r
+      Method(_UPC,0,Serialized)\r
+      {\r
+        Name(UPCP, Package()\r
+        {\r
+          0xFF,                     //  connectable\r
+          0xFF,\r
+          0x00,\r
+          0x00\r
+        })\r
+\r
+        Return(UPCP)\r
+      }\r
+\r
+      Method(_RMV, 0)                                    // for XHCICV debug purpose\r
+      {\r
+        Return(0x0)\r
+      }\r
+\r
+      Method(_PLD,0,Serialized)\r
+      {\r
+        Name(PLDP, Package()\r
+        {\r
+          Buffer(0x14)\r
+          {\r
+            //31:0   - Bit[6:0]=2 revision is 0x2, Bit[7]=1 Ignore Color Bit[31:8]=0 RGB color is ignored\r
+            0x82, 0x00, 0x00, 0x00,\r
+            //63:32 - Bit[47:32]=0 width: 0x0000  Bit[63:48]=0 Height:0x0000\r
+            0x00, 0x00, 0x00, 0x00,\r
+            //95:64 - bit[66:64]=b'000 not Visible/no docking/no lid bit[69:67]=6 (b'110) unknown(Vertical Position and  Horizontal Position will be ignored)\r
+            //           bit[71:70]=b'00 Vertical Position ignore bit[73:72]=b'00 Horizontal Position ignore\r
+            //           bit[77:74]=2 Square bit[78]=0 bit[86:79]=0 bit[94:87]='0 no group info' bit[95]=0 not a bay\r
+            0x30, 0x08, 0x00, 0x00,\r
+            //127:96 -bit[96]=0 not Ejectable bit[97]=0 OSPM Ejection not required Bit[105:98]=0 no Cabinet Number\r
+            //            bit[113:106]=0 no Card cage Number bit[114]=0 no reference shape Bit[118:115]=0 no rotation Bit[123:119]=0 no order\r
+            0x00, 0x00, 0x00, 0x00,\r
+            //159:128  Vert. and Horiz. Offsets not supplied\r
+            0xFF, 0xFF, 0xFF, 0xFF\r
+          }\r
+        })\r
+        Return (PLDP)\r
+      }\r
+    }\r
+\r
+    Device(HS04)\r
+    {\r
+      Name(_ADR, 0x04)\r
+\r
+      Method(_UPC,0,Serialized)\r
+      {\r
+        Name(UPCP, Package()\r
+        {\r
+          0xFF,                     //connectable\r
+          0xFF,                     //Proprietary connector (FPC connector)\r
+          0x00,\r
+          0x00\r
+        })\r
+\r
+        Return(UPCP)\r
+      }\r
+      Method(_PLD,0,Serialized)\r
+      {\r
+        Name(PLDP, Package()\r
+        {\r
+          Buffer(0x14)\r
+          {\r
+            //31:0   - Bit[6:0]=2 revision is 0x2, Bit[7]=1 Ignore Color Bit[31:8]=0 RGB color is ignored\r
+            0x82, 0x00, 0x00, 0x00,\r
+            //63:32 - Bit[47:32]=0 width: 0x0000  Bit[63:48]=0 Height:0x0000\r
+            0x00, 0x00, 0x00, 0x00,\r
+            //95:64 - bit[66:64]=b'000 not Visible/no docking/no lid bit[69:67]=6 (b'110) unknown(Vertical Position and  Horizontal Position will be ignored)\r
+            //           bit[71:70]=b'00 Vertical Position ignore bit[73:72]=b'00 Horizontal Position ignore\r
+            //           bit[77:74]=2 Square bit[78]=0 bit[86:79]=0 bit[94:87]='0 no group info' bit[95]=0 not a bay\r
+            0x30, 0x08, 0x00, 0x00,\r
+            //127:96 -bit[96]=0 not Ejectable bit[97]=0 OSPM Ejection not required Bit[105:98]=0 no Cabinet Number\r
+            //            bit[113:106]=0 no Card cage Number bit[114]=0 no reference shape Bit[118:115]=0 no rotation Bit[123:119]=0 no order\r
+            0x00, 0x00, 0x00, 0x00,\r
+            //159:128  Vert. and Horiz. Offsets not supplied\r
+            0xFF, 0xFF, 0xFF, 0xFF\r
+          }\r
+        })\r
+\r
+        Return (PLDP)\r
+      }\r
+    }\r
+\r
+\r
+    Device(HSC1)                                           // USB2 HSIC 01\r
+    {\r
+      Name(_ADR, 0x05)\r
+\r
+      Method(_UPC,0,Serialized)\r
+      {\r
+        Name(UPCP, Package()\r
+        {\r
+          0xFF,                     //connectable\r
+          0xFF,                     //Proprietary connector (FPC connector)\r
+          0x00,\r
+          0x00\r
+        })\r
+\r
+        Return(UPCP)\r
+      }\r
+      Method(_PLD,0,Serialized)\r
+      {\r
+        Name(PLDP, Package()\r
+        {\r
+          Buffer(0x14)\r
+          {\r
+            //31:0   - Bit[6:0]=2 revision is 0x2, Bit[7]=1 Ignore Color Bit[31:8]=0 RGB color is ignored\r
+            0x82, 0x00, 0x00, 0x00,\r
+            //63:32 - Bit[47:32]=0 width: 0x0000  Bit[63:48]=0 Height:0x0000\r
+            0x00, 0x00, 0x00, 0x00,\r
+            //95:64 - bit[66:64]=b'000 not Visible/no docking/no lid bit[69:67]=6 (b'110) unknown(Vertical Position and  Horizontal Position will be ignored)\r
+            //           bit[71:70]=b'00 Vertical Position ignore bit[73:72]=b'00 Horizontal Position ignore\r
+            //           bit[77:74]=2 Square bit[78]=0 bit[86:79]=0 bit[94:87]='0 no group info' bit[95]=0 not a bay\r
+            0x30, 0x08, 0x00, 0x00,\r
+            //127:96 -bit[96]=0 not Ejectable bit[97]=0 OSPM Ejection not required Bit[105:98]=0 no Cabinet Number\r
+            //            bit[113:106]=0 no Card cage Number bit[114]=0 no reference shape Bit[118:115]=0 no rotation Bit[123:119]=0 no order\r
+            0x00, 0x00, 0x00, 0x00,\r
+            //159:128  Vert. and Horiz. Offsets not supplied\r
+            0xFF, 0xFF, 0xFF, 0xFF\r
+          }\r
+        })\r
+        Return (PLDP)\r
+      }\r
+    }\r
+\r
+    Device(HSC2)                                           // USB2 HSIC 02\r
+    {\r
+      Name(_ADR, 0x06)\r
+\r
+      Method(_UPC,0,Serialized)\r
+      {\r
+        Name(UPCP, Package()\r
+        {\r
+          0xFF,                     //connectable\r
+          0xFF,                     //Proprietary connector (FPC connector)\r
+          0x00,\r
+          0x00\r
+        })\r
+\r
+        Return(UPCP)\r
+      }\r
+      Method(_PLD,0,Serialized)\r
+      {\r
+        Name(PLDP, Package()\r
+        {\r
+          Buffer(0x14)\r
+          {\r
+            //31:0   - Bit[6:0]=2 revision is 0x2, Bit[7]=1 Ignore Color Bit[31:8]=0 RGB color is ignored\r
+            0x82, 0x00, 0x00, 0x00,\r
+            //63:32 - Bit[47:32]=0 width: 0x0000  Bit[63:48]=0 Height:0x0000\r
+            0x00, 0x00, 0x00, 0x00,\r
+            //95:64 - bit[66:64]=b'000 not Visible/no docking/no lid bit[69:67]=6 (b'110) unknown(Vertical Position and  Horizontal Position will be ignored)\r
+            //           bit[71:70]=b'00 Vertical Position ignore bit[73:72]=b'00 Horizontal Position ignore\r
+            //           bit[77:74]=2 Square bit[78]=0 bit[86:79]=0 bit[94:87]='0 no group info' bit[95]=0 not a bay\r
+            0x30, 0x08, 0x00, 0x00,\r
+            //127:96 -bit[96]=0 not Ejectable bit[97]=0 OSPM Ejection not required Bit[105:98]=0 no Cabinet Number\r
+            //            bit[113:106]=0 no Card cage Number bit[114]=0 no reference shape Bit[118:115]=0 no rotation Bit[123:119]=0 no order\r
+            0x00, 0x00, 0x00, 0x00,\r
+            //159:128  Vert. and Horiz. Offsets not supplied\r
+            0xFF, 0xFF, 0xFF, 0xFF\r
+          }\r
+        })\r
+        Return (PLDP)\r
+      }\r
+    }\r
+  }  //end of root hub\r
+\r
+} // end of XHC1\r
+\r

diff --git a/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/PciTree.asl b/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/PciTree.asl
new file mode 100644 (file)
index 0000000..84a7ee2
--- /dev/null
+++ b/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/PciTree.asl
@@ -0,0 +1,373 @@
+/**************************************************************************;\r
+;*                                                                        *;\r
+;*                                                                        *;\r
+;*    Intel Corporation - ACPI Reference Code for the Sandy Bridge        *;\r
+;*    Family of Customer Reference Boards.                                *;\r
+;*                                                                        *;\r
+;*                                                                        *;\r
+;*    Copyright (c) 2012  - 2014, Intel Corporation. All rights reserved    *;\r
+;\r
+; This program and the accompanying materials are licensed and made available under\r
+; the terms and conditions of the BSD License that accompanies this distribution.\r
+; The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php.\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+;*                                                                        *;\r
+;*                                                                        *;\r
+;**************************************************************************/\r
+\r
+Scope(\_SB)\r
+{\r
+\r
+//RTC\r
+  Device(RTC)    // RTC\r
+  {\r
+    Name(_HID,EISAID("PNP0B00"))\r
+\r
+    Name(_CRS,ResourceTemplate()\r
+    {\r
+      IO(Decode16,0x70,0x70,0x01,0x08)\r
+    })\r
+  }\r
+//RTC\r
+\r
+  Device(HPET)   // High Performance Event Timer\r
+  {\r
+    Name (_HID, EisaId ("PNP0103"))\r
+    Name (_UID, 0x00)\r
+    Method (_STA, 0, NotSerialized)\r
+    {\r
+      Return (0x0F)\r
+    }\r
+\r
+    Method (_CRS, 0, Serialized)\r
+    {\r
+      Name (RBUF, ResourceTemplate ()\r
+      {\r
+        Memory32Fixed (ReadWrite,\r
+                       0xFED00000,         // Address Base\r
+                       0x00000400,         // Address Length\r
+                      )\r
+        Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )\r
+        {\r
+          0x00000008,   //0xB HPET-2\r
+        }\r
+      })\r
+      Return (RBUF)\r
+    }\r
+  }\r
+//HPET\r
+\r
+  Name(PR00, Package()\r
+  {\r
+// SD Host #0 - eMMC\r
+    Package() {0x0010FFFF, 0, LNKA, 0 },\r
+// SD Host #1 - SDIO\r
+    Package() {0x0011FFFF, 0, LNKB, 0 },\r
+// SD Host #2 - SD Card\r
+    Package() {0x0012FFFF, 0, LNKC, 0 },\r
+// SATA Controller\r
+    Package() {0x0013FFFF, 0, LNKD, 0 },\r
+// xHCI Host\r
+    Package() {0x0014FFFF, 0, LNKE, 0 },\r
+// Low Power Audio Engine\r
+    Package() {0x0015FFFF, 0, LNKF, 0 },\r
+// USB OTG\r
+    Package() {0x0016FFFF, 0, LNKG, 0 },\r
+// MIPI-HSI/eMMC4.5\r
+    Package() {0x0017FFFF, 0, LNKH, 0 },\r
+// LPSS2 DMA\r
+// LPSS2 I2C #4\r
+    Package() {0x0018FFFF, 0, LNKB, 0 },\r
+// LPSS2 I2C #1\r
+// LPSS2 I2C #5\r
+    Package() {0x0018FFFF, 2, LNKD, 0 },\r
+// LPSS2 I2C #2\r
+// LPSS2 I2C #6\r
+    Package() {0x0018FFFF, 3, LNKC, 0 },\r
+// LPSS2 I2C #3\r
+// LPSS2 I2C #7\r
+    Package() {0x0018FFFF, 1, LNKA, 0 },\r
+// SeC\r
+    Package() {0x001AFFFF, 0, LNKF, 0 },\r
+//\r
+// High Definition Audio Controller\r
+    Package() {0x001BFFFF, 0, LNKG, 0 },\r
+//\r
+// EHCI Controller\r
+    Package() {0x001DFFFF, 0, LNKH, 0 },\r
+// LPSS DMA\r
+    Package() {0x001EFFFF, 0, LNKD, 0 },\r
+// LPSS I2C #0\r
+    Package() {0x001EFFFF, 3, LNKA, 0 },\r
+// LPSS I2C #1\r
+    Package() {0x001EFFFF, 1, LNKB, 0 },\r
+// LPSS PCM\r
+    Package() {0x001EFFFF, 2, LNKC, 0 },\r
+// LPSS I2S\r
+// LPSS HS-UART #0\r
+// LPSS HS-UART #1\r
+// LPSS SPI\r
+// LPC Bridge\r
+//\r
+// SMBus Controller\r
+    Package() {0x001FFFFF, 1, LNKC, 0 },\r
+//\r
+// PCIE Root Port #1\r
+    Package() {0x001CFFFF, 0, LNKA, 0 },\r
+// PCIE Root Port #2\r
+    Package() {0x001CFFFF, 1, LNKB, 0 },\r
+// PCIE Root Port #3\r
+    Package() {0x001CFFFF, 2, LNKC, 0 },\r
+// PCIE Root Port #4\r
+    Package() {0x001CFFFF, 3, LNKD, 0 },\r
+\r
+// Host Bridge\r
+// Mobile IGFX\r
+    Package() {0x0002FFFF, 0, LNKA, 0 },\r
+  })\r
+\r
+  Name(AR00, Package()\r
+  {\r
+// SD Host #0 - eMMC\r
+    Package() {0x0010FFFF, 0, 0, 16 },\r
+// SD Host #1 - SDIO\r
+    Package() {0x0011FFFF, 0, 0, 17 },\r
+// SD Host #2 - SD Card\r
+    Package() {0x0012FFFF, 0, 0, 18 },\r
+// SATA Controller\r
+    Package() {0x0013FFFF, 0, 0, 19 },\r
+// xHCI Host\r
+    Package() {0x0014FFFF, 0, 0, 20 },\r
+// Low Power Audio Engine\r
+    Package() {0x0015FFFF, 0, 0, 21 },\r
+// USB OTG\r
+    Package() {0x0016FFFF, 0, 0, 22 },\r
+//\r
+// MIPI-HSI\r
+    Package() {0x0017FFFF, 0, 0, 23 },\r
+//\r
+// LPSS2 DMA\r
+// LPSS2 I2C #4\r
+    Package() {0x0018FFFF, 0, 0, 17 },\r
+// LPSS2 I2C #1\r
+// LPSS2 I2C #5\r
+    Package() {0x0018FFFF, 2, 0, 19 },\r
+// LPSS2 I2C #2\r
+// LPSS2 I2C #6\r
+    Package() {0x0018FFFF, 3, 0, 18 },\r
+// LPSS2 I2C #3\r
+// LPSS2 I2C #7\r
+    Package() {0x0018FFFF, 1, 0, 16 },\r
+\r
+// SeC\r
+    Package() {0x001AFFFF, 0, 0, 21 },\r
+//\r
+// High Definition Audio Controller\r
+    Package() {0x001BFFFF, 0, 0, 22 },\r
+//\r
+// EHCI Controller\r
+    Package() {0x001DFFFF, 0, 0, 23 },\r
+// LPSS DMA\r
+    Package() {0x001EFFFF, 0, 0, 19 },\r
+// LPSS I2C #0\r
+    Package() {0x001EFFFF, 3, 0, 16 },\r
+// LPSS I2C #1\r
+    Package() {0x001EFFFF, 1, 0, 17 },\r
+// LPSS PCM\r
+    Package() {0x001EFFFF, 2, 0, 18 },\r
+// LPSS I2S\r
+// LPSS HS-UART #0\r
+// LPSS HS-UART #1\r
+// LPSS SPI\r
+// LPC Bridge\r
+//\r
+// SMBus Controller\r
+    Package() {0x001FFFFF, 1, 0, 18 },\r
+//\r
+// PCIE Root Port #1\r
+    Package() {0x001CFFFF, 0, 0, 16 },\r
+// PCIE Root Port #2\r
+    Package() {0x001CFFFF, 1, 0, 17 },\r
+// PCIE Root Port #3\r
+    Package() {0x001CFFFF, 2, 0, 18 },\r
+// PCIE Root Port #4\r
+    Package() {0x001CFFFF, 3, 0, 19 },\r
+// Host Bridge\r
+// Mobile IGFX\r
+    Package() {0x0002FFFF, 0, 0, 16 },\r
+  })\r
+\r
+  Name(PR04, Package()\r
+  {\r
+// PCIE Port #1 Slot\r
+    Package() {0x0000FFFF, 0, LNKA, 0 },\r
+    Package() {0x0000FFFF, 1, LNKB, 0 },\r
+    Package() {0x0000FFFF, 2, LNKC, 0 },\r
+    Package() {0x0000FFFF, 3, LNKD, 0 },\r
+  })\r
+\r
+  Name(AR04, Package()\r
+  {\r
+// PCIE Port #1 Slot\r
+    Package() {0x0000FFFF, 0, 0, 16 },\r
+    Package() {0x0000FFFF, 1, 0, 17 },\r
+    Package() {0x0000FFFF, 2, 0, 18 },\r
+    Package() {0x0000FFFF, 3, 0, 19 },\r
+  })\r
+\r
+  Name(PR05, Package()\r
+  {\r
+// PCIE Port #2 Slot\r
+    Package() {0x0000FFFF, 0, LNKB, 0 },\r
+    Package() {0x0000FFFF, 1, LNKC, 0 },\r
+    Package() {0x0000FFFF, 2, LNKD, 0 },\r
+    Package() {0x0000FFFF, 3, LNKA, 0 },\r
+  })\r
+\r
+  Name(AR05, Package()\r
+  {\r
+// PCIE Port #2 Slot\r
+    Package() {0x0000FFFF, 0, 0, 17 },\r
+    Package() {0x0000FFFF, 1, 0, 18 },\r
+    Package() {0x0000FFFF, 2, 0, 19 },\r
+    Package() {0x0000FFFF, 3, 0, 16 },\r
+  })\r
+\r
+  Name(PR06, Package()\r
+  {\r
+// PCIE Port #3 Slot\r
+    Package() {0x0000FFFF, 0, LNKC, 0 },\r
+    Package() {0x0000FFFF, 1, LNKD, 0 },\r
+    Package() {0x0000FFFF, 2, LNKA, 0 },\r
+    Package() {0x0000FFFF, 3, LNKB, 0 },\r
+  })\r
+\r
+  Name(AR06, Package()\r
+  {\r
+// PCIE Port #3 Slot\r
+    Package() {0x0000FFFF, 0, 0, 18 },\r
+    Package() {0x0000FFFF, 1, 0, 19 },\r
+    Package() {0x0000FFFF, 2, 0, 16 },\r
+    Package() {0x0000FFFF, 3, 0, 17 },\r
+  })\r
+\r
+  Name(PR07, Package()\r
+  {\r
+// PCIE Port #4 Slot\r
+    Package() {0x0000FFFF, 0, LNKD, 0 },\r
+    Package() {0x0000FFFF, 1, LNKA, 0 },\r
+    Package() {0x0000FFFF, 2, LNKB, 0 },\r
+    Package() {0x0000FFFF, 3, LNKC, 0 },\r
+  })\r
+\r
+  Name(AR07, Package()\r
+  {\r
+// PCIE Port #4 Slot\r
+    Package() {0x0000FFFF, 0, 0, 19 },\r
+    Package() {0x0000FFFF, 1, 0, 16 },\r
+    Package() {0x0000FFFF, 2, 0, 17 },\r
+    Package() {0x0000FFFF, 3, 0, 18 },\r
+  })\r
+\r
+  Name(PR01, Package()\r
+  {\r
+// PCI slot 1\r
+    Package() {0x0000FFFF, 0, LNKF, 0 },\r
+    Package() {0x0000FFFF, 1, LNKG, 0 },\r
+    Package() {0x0000FFFF, 2, LNKH, 0 },\r
+    Package() {0x0000FFFF, 3, LNKE, 0 },\r
+// PCI slot 2\r
+    Package() {0x0001FFFF, 0, LNKG, 0 },\r
+    Package() {0x0001FFFF, 1, LNKF, 0 },\r
+    Package() {0x0001FFFF, 2, LNKE, 0 },\r
+    Package() {0x0001FFFF, 3, LNKH, 0 },\r
+// PCI slot 3\r
+    Package() {0x0002FFFF, 0, LNKC, 0 },\r
+    Package() {0x0002FFFF, 1, LNKD, 0 },\r
+    Package() {0x0002FFFF, 2, LNKB, 0 },\r
+    Package() {0x0002FFFF, 3, LNKA, 0 },\r
+// PCI slot 4\r
+    Package() {0x0003FFFF, 0, LNKD, 0 },\r
+    Package() {0x0003FFFF, 1, LNKC, 0 },\r
+    Package() {0x0003FFFF, 2, LNKF, 0 },\r
+    Package() {0x0003FFFF, 3, LNKG, 0 },\r
+  })\r
+\r
+  Name(AR01, Package()\r
+  {\r
+// PCI slot 1\r
+    Package() {0x0000FFFF, 0, 0, 21 },\r
+    Package() {0x0000FFFF, 1, 0, 22 },\r
+    Package() {0x0000FFFF, 2, 0, 23 },\r
+    Package() {0x0000FFFF, 3, 0, 20 },\r
+// PCI slot 2\r
+    Package() {0x0001FFFF, 0, 0, 22 },\r
+    Package() {0x0001FFFF, 1, 0, 21 },\r
+    Package() {0x0001FFFF, 2, 0, 20 },\r
+    Package() {0x0001FFFF, 3, 0, 23 },\r
+// PCI slot 3\r
+    Package() {0x0002FFFF, 0, 0, 18 },\r
+    Package() {0x0002FFFF, 1, 0, 19 },\r
+    Package() {0x0002FFFF, 2, 0, 17 },\r
+    Package() {0x0002FFFF, 3, 0, 16 },\r
+// PCI slot 4\r
+    Package() {0x0003FFFF, 0, 0, 19 },\r
+    Package() {0x0003FFFF, 1, 0, 18 },\r
+    Package() {0x0003FFFF, 2, 0, 21 },\r
+    Package() {0x0003FFFF, 3, 0, 22 },\r
+  })\r
+//---------------------------------------------------------------------------\r
+// List of IRQ resource buffers compatible with _PRS return format.\r
+//---------------------------------------------------------------------------\r
+// Naming legend:\r
+// RSxy, PRSy - name of the IRQ resource buffer to be returned by _PRS, "xy" - last two characters of IRQ Link name.\r
+// Note. PRSy name is generated if IRQ Link name starts from "LNK".\r
+// HLxy , LLxy - reference names, can be used to access bit mask of available IRQs. HL and LL stand for active High(Low) Level triggered Irq model.\r
+//---------------------------------------------------------------------------\r
+  Name(PRSA, ResourceTemplate()         // Link name: LNKA\r
+  {\r
+    IRQ(Level, ActiveLow, Shared, LLKA) {3,4,5,6,10,11,12,14,15}\r
+  })\r
+  Alias(PRSA,PRSB)      // Link name: LNKB\r
+  Alias(PRSA,PRSC)      // Link name: LNKC\r
+  Alias(PRSA,PRSD)      // Link name: LNKD\r
+  Alias(PRSA,PRSE)      // Link name: LNKE\r
+  Alias(PRSA,PRSF)      // Link name: LNKF\r
+  Alias(PRSA,PRSG)      // Link name: LNKG\r
+  Alias(PRSA,PRSH)      // Link name: LNKH\r
+//---------------------------------------------------------------------------\r
+// Begin PCI tree object scope\r
+//---------------------------------------------------------------------------\r
+\r
+  Device(PCI0)   // PCI Bridge "Host Bridge"\r
+  {\r
+    Name(_HID, EISAID("PNP0A08"))       // Indicates PCI Express/PCI-X Mode2 host hierarchy\r
+    Name(_CID, EISAID("PNP0A03"))       // To support legacy OS that doesn't understand the new HID\r
+    Name(_ADR, 0x00000000)\r
+    Method(^BN00, 0) { return(0x0000) } // Returns default Bus number for Peer PCI busses. Name can be overriden with control method placed directly under Device scope\r
+    Method(_BBN, 0) { return(BN00()) }  // Bus number, optional for the Root PCI Bus\r
+    Name(_UID, 0x0000)  // Unique Bus ID, optional\r
+    Name(_DEP, Package(0x1)\r
+    {\r
+      PEPD\r
+    })\r
+\r
+                            Method(_PRT,0)\r
+    {\r
+      If(PICM) {Return(AR00)} // APIC mode\r
+      Return (PR00) // PIC Mode\r
+    } // end _PRT\r
+\r
+    include("HOST_BUS.ASL")\r
+    Device(LPCB)   // LPC Bridge\r
+    {\r
+      Name(_ADR, 0x001F0000)\r
+      include("LpcB.asl")\r
+    } // end "LPC Bridge"\r
+\r
+  } // end PCI0 Bridge "Host Bridge"\r
+} // end _SB scope\r

diff --git a/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/Platform.asl b/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/Platform.asl
new file mode 100644 (file)
index 0000000..5f269be
--- /dev/null
+++ b/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/Platform.asl
@@ -0,0 +1,830 @@
+/**************************************************************************;\r
+;*                                                                        *;\r
+;*                                                                        *;\r
+;*    Intel Corporation - ACPI Reference Code for the Baytrail            *;\r
+;*    Family of Customer Reference Boards.                                *;\r
+;*                                                                        *;\r
+;*                                                                        *;\r
+;*    Copyright (c) 2012  - 2014, Intel Corporation. All rights reserved    *;\r
+;\r
+; This program and the accompanying materials are licensed and made available under\r
+; the terms and conditions of the BSD License that accompanies this distribution.\r
+; The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php.\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+;*                                                                        *;\r
+;*                                                                        *;\r
+;**************************************************************************/\r
+\r
+\r
+// Define the following External variables to prevent a WARNING when\r
+// using ASL.EXE and an ERROR when using IASL.EXE.\r
+\r
+External(PDC0)\r
+External(PDC1)\r
+External(PDC2)\r
+External(PDC3)\r
+External(CFGD)\r
+External(\_PR.CPU0._PPC, IntObj)\r
+External(\_SB.PCI0.LPCB.TPM.PTS, MethodObj)\r
+External(\_SB.STR3, DeviceObj)\r
+External(\_SB.I2C1.BATC, DeviceObj)\r
+External(\_SB.DPTF, DeviceObj)\r
+External(\_SB.TCHG, DeviceObj)\r
+External(\_SB.IAOE.PTSL)\r
+External(\_SB.IAOE.WKRS)\r
+\r
+//\r
+// Create a Global MUTEX.\r
+//\r
+Mutex(MUTX,0)\r
+\r
+\r
+\r
+// Port 80h Update:\r
+//              Update 8 bits of the 32-bit Port 80h.\r
+//\r
+//      Arguments:\r
+//              Arg0:   0 = Write Port 80h, Bits 7:0 Only.\r
+//                      1 = Write Port 80h, Bits 15:8 Only.\r
+//                      2 = Write Port 80h, Bits 23:16 Only.\r
+//                      3 = Write Port 80h, Bits 31:24 Only.\r
+//              Arg1:   8-bit Value to write\r
+//\r
+//      Return Value:\r
+//              None\r
+\r
+Method(P8XH,2,Serialized)\r
+{\r
+  If(LEqual(Arg0,0))            // Write Port 80h, Bits 7:0.\r
+  {\r
+    Store(Or(And(P80D,0xFFFFFF00),Arg1),P80D)\r
+  }\r
+\r
+  If(LEqual(Arg0,1))            // Write Port 80h, Bits 15:8.\r
+  {\r
+    Store(Or(And(P80D,0xFFFF00FF),ShiftLeft(Arg1,8)),P80D)\r
+  }\r
+\r
+  If(LEqual(Arg0,2))            // Write Port 80h, Bits 23:16.\r
+  {\r
+    Store(Or(And(P80D,0xFF00FFFF),ShiftLeft(Arg1,16)),P80D)\r
+  }\r
+\r
+  If(LEqual(Arg0,3))            // Write Port 80h, Bits 31:24.\r
+  {\r
+    Store(Or(And(P80D,0x00FFFFFF),ShiftLeft(Arg1,24)),P80D)\r
+  }\r
+\r
+}\r
+\r
+//\r
+// Define SW SMI port as an ACPI Operating Region to use for generate SW SMI.\r
+//\r
+OperationRegion (SPRT, SystemIO, 0xB2, 2)\r
+Field (SPRT, ByteAcc, Lock, Preserve)\r
+{\r
+  SSMP, 8\r
+}\r
+\r
+// The _PIC Control Method is optional for ACPI design.  It allows the\r
+// OS to inform the ASL code which interrupt controller is being used,\r
+// the 8259 or APIC.  The reference code in this document will address\r
+// PCI IRQ Routing and resource allocation for both cases.\r
+//\r
+// The values passed into _PIC are:\r
+//       0 = 8259\r
+//       1 = IOAPIC\r
+\r
+Method(\_PIC,1)\r
+{\r
+  Store(Arg0,GPIC)\r
+  Store(Arg0,PICM)\r
+}\r
+\r
+OperationRegion(SWC0, SystemIO, 0x610, 0x0F)\r
+Field(SWC0, ByteAcc, NoLock, Preserve)\r
+{\r
+  G1S, 8,      //SWC GPE1_STS\r
+  Offset(0x4),\r
+  G1E, 8,\r
+  Offset(0xA),\r
+  G1S2, 8,     //SWC GPE1_STS_2\r
+  G1S3, 8      //SWC GPE1_STS_3\r
+}\r
+\r
+OperationRegion (SWC1, SystemIO, \PMBS, 0x2C)\r
+Field(SWC1, DWordAcc, NoLock, Preserve)\r
+{\r
+  Offset(0x20),\r
+  G0S, 32,      //GPE0_STS\r
+  Offset(0x28),\r
+  G0EN, 32      //GPE0_EN\r
+}\r
+\r
+// Prepare to Sleep.  The hook is called when the OS is about to\r
+// enter a sleep state.  The argument passed is the numeric value of\r
+// the Sx state.\r
+\r
+Method(_PTS,1)\r
+{\r
+  Store(0,P80D)         // Zero out the entire Port 80h DWord.\r
+  P8XH(0,Arg0)          // Output Sleep State to Port 80h, Byte 0.\r
+\r
+  //clear the 3 SWC status bits\r
+  Store(Ones, G1S3)\r
+  Store(Ones, G1S2)\r
+  Store(1, G1S)\r
+\r
+  //set SWC GPE1_EN\r
+  Store(1,G1E)\r
+\r
+  //clear GPE0_STS\r
+  Store(Ones, G0S)\r
+\r
+\r
+  If(LEqual(Arg0,3))   // If S3 Suspend\r
+  {\r
+    //\r
+    // Disable Digital Thermal Sensor function when doing S3 suspend\r
+    //\r
+    If(CondRefOf(DTSE))\r
+    {\r
+      If(LGreaterEqual(DTSE, 0x01))\r
+      {\r
+        Store(30, DTSF) // DISABLE_UPDATE_DTS_EVERY_SMI\r
+        Store(0xD0, SSMP) // DTS SW SMI\r
+      }\r
+    }\r
+  }\r
+}\r
+\r
+// Wake.  This hook is called when the OS is about to wake from a\r
+// sleep state.  The argument passed is the numeric value of the\r
+// sleep state the system is waking from.\r
+Method(_WAK,1,Serialized)\r
+{\r
+  P8XH(1,0xAB) // Beginning of _WAK.\r
+\r
+  Notify(\_SB.PWRB,0x02)\r
+\r
+  If(NEXP)\r
+  {\r
+    // Reinitialize the Native PCI Express after resume\r
+    If(And(OSCC,0x02))\r
+    {\r
+      \_SB.PCI0.NHPG()\r
+    }\r
+\r
+    If(And(OSCC,0x04))   // PME control granted?\r
+    {\r
+      \_SB.PCI0.NPME()\r
+    }\r
+  }\r
+\r
+  If(LOr(LEqual(Arg0,3), LEqual(Arg0,4)))   // If S3 or S4 Resume\r
+  {\r
+\r
+\r
+    // If CMP is enabled, we may need to restore the C-State and/or\r
+    // P-State configuration, as it may have been saved before the\r
+    // configuration was finalized based on OS/driver support.\r
+    //\r
+    //   CFGD[24]  = Two or more cores enabled\r
+    //\r
+    If(And(CFGD,0x01000000))\r
+    {\r
+      //\r
+      // If CMP and the OSYS is WinXP SP1, we will enable C1-SMI if\r
+      // C-States are enabled.\r
+      //\r
+      //   CFGD[7:4] = C4, C3, C2, C1 Capable/Enabled\r
+      //\r
+      //\r
+    }\r
+\r
+    // Windows XP SP2 does not properly restore the P-State\r
+    // upon resume from S4 or S3 with degrade modes enabled.\r
+    // Use the existing _PPC methods to cycle the available\r
+    // P-States such that the processor ends up running at\r
+    // the proper P-State.\r
+    //\r
+    // Note:  For S4, another possible W/A is to always boot\r
+    // the system in LFM.\r
+    //\r
+    If(LEqual(OSYS,2002))\r
+    {\r
+      If(And(CFGD,0x01))\r
+      {\r
+        If(LGreater(\_PR.CPU0._PPC,0))\r
+        {\r
+          Subtract(\_PR.CPU0._PPC,1,\_PR.CPU0._PPC)\r
+          PNOT()\r
+          Add(\_PR.CPU0._PPC,1,\_PR.CPU0._PPC)\r
+          PNOT()\r
+        }\r
+        Else\r
+        {\r
+          Add(\_PR.CPU0._PPC,1,\_PR.CPU0._PPC)\r
+          PNOT()\r
+          Subtract(\_PR.CPU0._PPC,1,\_PR.CPU0._PPC)\r
+          PNOT()\r
+        }\r
+      }\r
+    }\r
+  }\r
+  Return(Package() {0,0})\r
+}\r
+\r
+// Power Notification:\r
+//              Perform all needed OS notifications during a\r
+//              Power Switch.\r
+//\r
+//      Arguments:\r
+//              None\r
+//\r
+//      Return Value:\r
+//              None\r
+\r
+Method(PNOT,0,Serialized)\r
+{\r
+  // If MP enabled and driver support is present, notify all\r
+  // processors.\r
+\r
+  If(MPEN)\r
+  {\r
+    If(And(PDC0,0x0008))\r
+    {\r
+      Notify(\_PR.CPU0,0x80)    // Eval CPU0 _PPC.\r
+\r
+      If(And(PDC0,0x0010))\r
+      {\r
+        Sleep(100)\r
+        Notify(\_PR.CPU0,0x81)  // Eval _CST.\r
+      }\r
+    }\r
+\r
+    If(And(PDC1,0x0008))\r
+    {\r
+      Notify(\_PR.CPU1,0x80)    // Eval CPU1 _PPC.\r
+\r
+      If(And(PDC1,0x0010))\r
+      {\r
+        Sleep(100)\r
+        Notify(\_PR.CPU1,0x81)  // Eval _CST.\r
+      }\r
+    }\r
+\r
+    If(And(PDC2,0x0008))\r
+    {\r
+      Notify(\_PR.CPU2,0x80)    // Eval CPU2 _PPC.\r
+\r
+      If(And(PDC2,0x0010))\r
+      {\r
+        Sleep(100)\r
+        Notify(\_PR.CPU2,0x81)  // Eval _CST.\r
+      }\r
+    }\r
+\r
+    If(And(PDC3,0x0008))\r
+    {\r
+      Notify(\_PR.CPU3,0x80)    // Eval CPU3 _PPC.\r
+\r
+      If(And(PDC3,0x0010))\r
+      {\r
+        Sleep(100)\r
+        Notify(\_PR.CPU3,0x81)  // Eval _CST.\r
+      }\r
+    }\r
+  }\r
+  Else\r
+  {\r
+    Notify(\_PR.CPU0,0x80)      // Eval _PPC.\r
+    Sleep(100)\r
+    Notify(\_PR.CPU0,0x81)      // Eval _CST\r
+  }\r
+}\r
+\r
+//\r
+// System Bus\r
+//\r
+Scope(\_SB)\r
+{\r
+  Name(CRTT, 110) // Processor critical temperature\r
+  Name(ACTT, 77)  // Active temperature limit for processor participant\r
+  Name(GCR0, 70)  // Critical temperature for Generic participant 0 in degree celsius\r
+  Name(GCR1, 70)  // Critical temperature for Generic participant 1 in degree celsius\r
+  Name(GCR2, 70)  // Critical temperature for Generic participant 2 in degree celsius\r
+  Name(GCR3, 70)  // Critical temperature for Generic participant 3 in degree celsius\r
+  Name(GCR4, 70)  // Critical temperature for Generic participant 4 in degree celsius\r
+  Name(GCR5, 70)  // Critical temperature for Generic participant 5 in degree celsius\r
+  Name(GCR6, 70)  // Critical temperature for Generic participant 6 in degree celsius\r
+  Name(PST0, 60)  // Passive temperature limit for Generic Participant 0 in degree celsius\r
+  Name(PST1, 60)  // Passive temperature limit for Generic Participant 1 in degree celsius\r
+  Name(PST2, 60)  // Passive temperature limit for Generic Participant 2 in degree celsius\r
+  Name(PST3, 60)  // Passive temperature limit for Generic Participant 3 in degree celsius\r
+  Name(PST4, 60)  // Passive temperature limit for Generic Participant 4 in degree celsius\r
+  Name(PST5, 60)  // Passive temperature limit for Generic Participant 5 in degree celsius\r
+  Name(PST6, 60)  // Passive temperature limit for Generic Participant 6 in degree celsius\r
+  Name(LPMV, 3)\r
+  Name(PDBG, 0)   // DPTF Super debug option\r
+  Name(PDPM, 1)   // DPTF DPPM enable\r
+  Name(PDBP, 1)   // DPTF DBPT enable (dynamic battery protection technology)\r
+  Name(DLPO, Package()\r
+  {\r
+    0x1, // Revision\r
+    0x1, // LPO Enable\r
+    0x1, // LPO StartPState\r
+    25,  // LPO StepSize\r
+    0x1, //\r
+    0x1, //\r
+  })\r
+  Name(BRQD, 0x00) // This is used to determine if DPTF display participant requested Brightness level change\r
+  // or it is from Graphics driver. Value of 1 is for DPTF else it is 0\r
+\r
+  Method(_INI,0)\r
+  {\r
+    // NVS has stale DTS data.  Get and update the values\r
+    // with current temperatures.   Note that this will also\r
+    // re-arm any AP Thermal Interrupts.\r
+    // Read temperature settings from global NVS\r
+    Store(DPCT, CRTT)\r
+    Store(Subtract(DPPT, 8), ACTT)                      // Active Trip point = Passive trip point - 8\r
+    Store(DGC0, GCR0)\r
+    Store(DGC0, GCR1)\r
+    Store(DGC1, GCR2)\r
+    Store(DGC1, GCR3)\r
+    Store(DGC1, GCR4)\r
+    Store(DGC2, GCR5)\r
+    Store(DGC2, GCR6)\r
+    Store(DGP0, PST0)\r
+    Store(DGP0, PST1)\r
+    Store(DGP1, PST2)\r
+    Store(DGP1, PST3)\r
+    Store(DGP1, PST4)\r
+    Store(DGP2, PST5)\r
+    Store(DGP2, PST6)\r
+    // Read Current low power mode setting from global NVS\r
+    Store(DLPM, LPMV)\r
+\r
+\r
+    // Update DPTF Super Debug option\r
+    Store(DDBG, PDBG)\r
+\r
+\r
+    // Update DPTF LPO Options\r
+    Store(LPOE, Index(DLPO,1))\r
+    Store(LPPS, Index(DLPO,2))\r
+    Store(LPST, Index(DLPO,3))\r
+    Store(LPPC, Index(DLPO,4))\r
+    Store(LPPF, Index(DLPO,5))\r
+    Store(DPME, PDPM)\r
+  }\r
+\r
+  // Define a (Control Method) Power Button.\r
+  Device(PWRB)\r
+  {\r
+    Name(_HID,EISAID("PNP0C0C"))\r
+\r
+    // GPI_SUS0 = GPE16 = Waketime SCI.  The PRW isn't working when\r
+    // placed in any of the logical locations ( PS2K, PS2M),\r
+    // so a Power Button Device was created specifically\r
+    // for the WAKETIME_SCI PRW.\r
+\r
+    Name(_PRW, Package() {16,4})\r
+  }\r
+\r
+  Device(SLPB)\r
+  {\r
+    Name(_HID, EISAID("PNP0C0E"))\r
+  } // END SLPB\r
+\r
+  Scope(PCI0)\r
+  {\r
+    Method(_INI,0)\r
+    {\r
+      // Determine the OS and store the value, where:\r
+      //\r
+      //   OSYS = 2009 = Windows 7 and Windows Server 2008 R2.\r
+      //   OSYS = 2012 = Windows 8 and Windows Server 2012.\r
+      //\r
+      // Assume Windows 7 at a minimum.\r
+\r
+      Store(2009,OSYS)\r
+\r
+      // Check for a specific OS which supports _OSI.\r
+\r
+      If(CondRefOf(\_OSI,Local0))\r
+      {\r
+        // Linux returns _OSI = TRUE for numerous Windows\r
+        // strings so that it is fully compatible with\r
+        // BIOSes available in the market today.  There are\r
+        // currently 2 known exceptions to this model:\r
+        //      1) Video Repost - Linux supports S3 without\r
+        //              requireing a Driver, meaning a Video\r
+        //              Repost will be required.\r
+        //      2) On-Screen Branding - a full CMT Logo\r
+        //              is limited to the WIN2K and WINXP\r
+        //              Operating Systems only.\r
+\r
+        // Use OSYS for Windows Compatibility.\r
+        If(\_OSI("Windows 2009"))   // Windows 7 or Windows Server 2008 R2\r
+        {\r
+          Store(2009,OSYS)\r
+        }\r
+        If(\_OSI("Windows 2012"))   // Windows 8 or Windows Server 2012\r
+        {\r
+          Store(2012,OSYS)\r
+        }\r
+        If(\_OSI("Windows 2013"))   //Windows Blue\r
+        {\r
+          Store(2013,OSYS)\r
+        }\r
+\r
+        //\r
+        // If CMP is enabled, enable SMM C-State\r
+        // coordination.  SMM C-State coordination\r
+        // will be disabled in _PDC if driver support\r
+        // for independent C-States deeper than C1\r
+        // is indicated.\r
+      }\r
+    }\r
+\r
+    Method(NHPG,0,Serialized)\r
+    {\r
+\r
+    }\r
+\r
+    Method(NPME,0,Serialized)\r
+    {\r
+\r
+    }\r
+  } // end Scope(PCI0)\r
+\r
+  Device (GPED)   //virtual GPIO device for ASL based AC/Battery/Expection notification\r
+  {\r
+    Name (_ADR, 0)\r
+    Name (_HID, "INT0002")\r
+    Name (_CID, "INT0002")\r
+    Name (_DDN, "Virtual GPIO controller" )\r
+    Name (_UID, 1)\r
+\r
+    Method (_CRS, 0x0, Serialized)\r
+    {\r
+      Name (RBUF, ResourceTemplate ()\r
+      {\r
+        Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) {0x9} // Was 9\r
+      })\r
+      Return (RBUF)\r
+    }\r
+\r
+    Method (_STA, 0x0, NotSerialized)\r
+    {\r
+      Return(0x0)\r
+    }\r
+\r
+    Method (_AEI, 0x0, Serialized)\r
+    {\r
+      Name(RBUF, ResourceTemplate()\r
+      {\r
+        GpioInt(Edge, ActiveHigh, ExclusiveAndWake, PullDown,,"\\_SB.GPED",) {2} //pin 2\r
+      })\r
+      Return(RBUF)\r
+    }\r
+\r
+    Method(_E02)   // _Exx method will be called when interrupt is raised\r
+    {\r
+      If (LEqual (PWBS, 1))\r
+      {\r
+        Store (1, PWBS)      //Clear PowerButton Status\r
+      }\r
+      If (LEqual (PMEB, 1))\r
+      {\r
+        Store (1, PMEB)      //Clear PME_B0_STS\r
+      }\r
+      If (LEqual (\_SB.PCI0.SATA.PMES, 1))\r
+      {\r
+        Store (1, \_SB.PCI0.SATA.PMES)\r
+        Notify (\_SB.PCI0.SATA, 0x02)\r
+      }\r
+      //\r
+      // eMMC 4.41\r
+      //\r
+      If (LAnd(LEqual (\_SB.PCI0.EM41.PMES, 1), LEqual(PCIM, 1)))\r
+      {\r
+        Store (1, \_SB.PCI0.EM41.PMES)\r
+        Notify (\_SB.PCI0.EM41, 0x02)\r
+      }\r
+\r
+      //\r
+      // eMMC 4.5\r
+      //\r
+      If (LAnd(LEqual (\_SB.PCI0.EM45.PMES, 1), LEqual(PCIM, 1)))\r
+      {\r
+        Store (1, \_SB.PCI0.EM45.PMES)\r
+        Notify (\_SB.PCI0.EM45, 0x02)\r
+      }\r
+\r
+      If (LEqual(HDAD, 0))\r
+      {\r
+        If (LEqual (\_SB.PCI0.HDEF.PMES, 1))\r
+        {\r
+          Store (1, \_SB.PCI0.HDEF.PMES)\r
+          Notify (\_SB.PCI0.HDEF, 0x02)\r
+        }\r
+      }\r
+\r
+      If (LEqual (\_SB.PCI0.EHC1.PMES, 1))\r
+      {\r
+        Store (1, \_SB.PCI0.EHC1.PMES)\r
+        Notify (\_SB.PCI0.EHC1, 0x02)\r
+      }\r
+      If (LEqual (\_SB.PCI0.XHC1.PMES, 1))\r
+      {\r
+        Store (1, \_SB.PCI0.XHC1.PMES)\r
+        Notify (\_SB.PCI0.XHC1, 0x02)\r
+      }\r
+      If (LEqual (\_SB.PCI0.SEC0.PMES, 1))\r
+      {\r
+        Or (\_SB.PCI0.SEC0.PMES, Zero, \_SB.PCI0.SEC0.PMES)\r
+        Notify (\_SB.PCI0.SEC0, 0x02)\r
+      }\r
+    }\r
+  } //  Device (GPED)\r
+\r
+  //--------------------\r
+  //  GPIO\r
+  //--------------------\r
+  Device (GPO0)\r
+  {\r
+    Name (_ADR, 0)\r
+    Name (_HID, "INT33FC")\r
+    Name (_CID, "INT33B2")\r
+    Name (_DDN, "ValleyView2 General Purpose Input/Output (GPIO) controller" )\r
+    Name (_UID, 1)\r
+    Method (_CRS, 0x0, Serialized)\r
+    {\r
+      Name (RBUF, ResourceTemplate ()\r
+      {\r
+        Memory32Fixed (ReadWrite, 0x0FED0C000, 0x00001000)\r
+        Interrupt(ResourceConsumer, Level, ActiveLow, Shared, , , ) {49}\r
+\r
+      })\r
+      Return (RBUF)\r
+    }\r
+\r
+    Method (_STA, 0x0, NotSerialized)\r
+    {\r
+      //\r
+      // GPO driver will report present if any of below New IO bus exist\r
+      //\r
+      If (LOr(LEqual(L11D, 0), LEqual(L12D, 0))) // LPIO1 PWM #1 or #2 exist\r
+      { Return(0xF) }\r
+      If (LOr(LEqual(L13D, 0), LEqual(L14D, 0))) // LPIO1 HS-UART #1 or #2 exist\r
+      { Return(0xF) }\r
+      If (LOr(LEqual(L15D, 0), LEqual(SD1D, 0))) // LPIO1 SPI or SCC SDIO #1 exist\r
+      { Return(0xF) }\r
+      If (LOr(LEqual(SD2D, 0), LEqual(SD3D, 0))) // SCC SDIO #2 or #3 exist\r
+      { Return(0xF) }\r
+      If (LOr(LEqual(L21D, 0), LEqual(L22D, 0))) // LPIO2 I2C #1 or #2 exist\r
+      { Return(0xF) }\r
+      If (LOr(LEqual(L23D, 0), LEqual(L24D, 0))) // LPIO2 I2C #3 or #4 exist\r
+      { Return(0xF) }\r
+      If (LOr(LEqual(L25D, 0), LEqual(L26D, 0))) // LPIO2 I2C #5 or #6 exist\r
+      { Return(0xF) }\r
+      If (LEqual(L27D, 0))                       // LPIO2 I2C #7 exist\r
+      { Return(0xF) }\r
+\r
+      Return(0x0)\r
+    }\r
+\r
+    // Track status of GPIO OpRegion availability for this controller\r
+    Name(AVBL, 0)\r
+    Method(_REG,2)\r
+    {\r
+      If (Lequal(Arg0, 8))\r
+      {\r
+        Store(Arg1, ^AVBL)\r
+      }\r
+    }\r
+\r
+    OperationRegion(GPOP, SystemIo, \GPBS, 0x50)\r
+      Field(GPOP, ByteAcc, NoLock, Preserve) {\r
+      Offset(0x28), // cfio_ioreg_SC_GP_LVL_63_32_ - [GPIO_BASE_ADDRESS] + 28h\r
+          ,  21,\r
+      BTD3,  1,     //This field is not used. Pin not defined in schematics. Closest is GPIO_S5_35 - COMBO_BT_WAKEUP\r
+      Offset(0x48), // cfio_ioreg_SC_GP_LVL_95_64_ - [GPIO_BASE_ADDRESS] + 48h\r
+          ,  30,\r
+      SHD3,  1      //GPIO_S0_SC_95 - SENS_HUB_RST_N\r
+    }\r
+\r
+\r
+\r
+  }   //  Device (GPO0)\r
+\r
+  Device (GPO1)\r
+  {\r
+    Name (_ADR, 0)\r
+    Name (_HID, "INT33FC")\r
+    Name (_CID, "INT33B2")\r
+    Name (_DDN, "ValleyView2 GPNCORE controller" )\r
+    Name (_UID, 2)\r
+    Method (_CRS, 0x0, Serialized)\r
+    {\r
+      Name (RBUF, ResourceTemplate ()\r
+      {\r
+        Memory32Fixed (ReadWrite, 0x0FED0D000, 0x00001000)\r
+        Interrupt(ResourceConsumer, Level, ActiveLow, Shared, , , ) {48}\r
+      })\r
+      Return (RBUF)\r
+    }\r
+\r
+    Method (_STA, 0x0, NotSerialized)\r
+    {\r
+      Return(\_SB.GPO0._STA)\r
+    }\r
+  }   //  Device (GPO1)\r
+\r
+  Device (GPO2)\r
+  {\r
+    Name (_ADR, 0)\r
+    Name (_HID, "INT33FC")\r
+    Name (_CID, "INT33B2")\r
+    Name (_DDN, "ValleyView2 GPSUS controller" )\r
+    Name (_UID, 3)\r
+    Method (_CRS, 0x0, Serialized)\r
+    {\r
+      Name (RBUF, ResourceTemplate ()\r
+      {\r
+        Memory32Fixed (ReadWrite, 0x0FED0E000, 0x00001000)\r
+        Interrupt(ResourceConsumer, Level, ActiveLow, Shared, , , ) {50}\r
+      })\r
+      Return (RBUF)\r
+    }\r
+\r
+    Method (_STA, 0x0, NotSerialized)\r
+    {\r
+      Return(^^GPO0._STA)\r
+    }\r
+\r
+    // Track status of GPIO OpRegion availability for this controller\r
+    Name(AVBL, 0)\r
+    Method(_REG,2)\r
+    {\r
+      If (Lequal(Arg0, 8))\r
+      {\r
+        Store(Arg1, ^AVBL)\r
+      }\r
+    }\r
+    //Manipulate GPIO line using GPIO operation regions.\r
+    Name (GMOD, ResourceTemplate ()     //One method of creating a Connection for OpRegion accesses in Field definitions\r
+    {\r
+      //is creating a named object that refers to the connection attributes\r
+      GpioIo (Exclusive, PullDefault, 0, 0, IoRestrictionOutputOnly, "\\_SB.GPO2") {21}  //sus 21+128 BT+WLAN_ENABLE\r
+    })\r
+\r
+  OperationRegion(GPOP, SystemIo, \GPBS, 0x100)\r
+  Field(GPOP, ByteAcc, NoLock, Preserve) {\r
+      Offset(0x88),  // cfio_ioreg_SUS_GP_LVL_31_0_ - [GPIO_BASE_ADDRESS] + 88h\r
+          ,  20,\r
+      WFD3,  1\r
+    }\r
+\r
+\r
+  }   //  Device (GPO2)\r
+  include ("PchScc.asl")\r
+  include ("PchLpss.asl")\r
+\r
+         Scope(I2C7)\r
+  {\r
+\r
+  } //End Scope(I2C7)\r
+\r
+  //\r
+  // Device for Message Bus Interface\r
+  //\r
+  Device(MBID)\r
+  {\r
+    Name(_HID, "INT33BD")\r
+    Name(_CID, "INT33BD")\r
+    Name(_HRV, 2)//different from CLT's\r
+    Name(_UID, 1)\r
+\r
+    Method (_CRS, 0, Serialized)\r
+    {\r
+      Name (RBUF, ResourceTemplate ()\r
+      {\r
+        Memory32Fixed (\r
+          ReadWrite,\r
+          0xE00000D0, // Address Base\r
+          0xC,        // Address Length (MCR/MDR/MCRX)\r
+        )\r
+      })\r
+      Return (RBUF)\r
+    }\r
+\r
+\r
+    //\r
+    // custom opregion for MBI access\r
+    //\r
+    OperationRegion (REGS, 0x87, 0x0, 0x30)\r
+    Field (REGS, DWordAcc, NoLock, Preserve)\r
+    {\r
+      PORT, 32,    // Message Port\r
+      REG,  32,    // Message Target Register Address\r
+      DATA, 32,    // Message Data\r
+      MASK, 32,    // Mask bits for modify operation\r
+      BE,   32,    // Message Write Byte enables: 0 - BYTE; 1 - WORD; 2 - DWORD\r
+      OP,   32     // Operations: 0 - read; 1 - write; 2 - modify\r
+    }\r
+\r
+    //\r
+    // availability of the custom opregion\r
+    //\r
+    Name (AVBL, 0)\r
+    Method(_REG,2)\r
+    {\r
+      If (Lequal(Arg0, 0x87))\r
+      {\r
+        Store(Arg1, ^AVBL)\r
+      }\r
+    }\r
+\r
+    //\r
+    //  Method Name: READ\r
+    //  Arguments:\r
+    //    Arg0:   PORT\r
+    //    Arg1:   REG\r
+    //    Arg2:   BE\r
+    //  Return Value:\r
+    //  DATA\r
+    //\r
+    Method(READ, 3, Serialized)\r
+    {\r
+      Store(0xFFFFFFFF , Local0)\r
+      If (Lequal (AVBL, 1))\r
+      {\r
+        Store(0, OP)  // must be set at first, do not change!\r
+        Store(Arg0, PORT)\r
+        Store(Arg1, REG)\r
+        Store(Arg2, BE)\r
+        Store(DATA, Local0)\r
+      }\r
+      return(Local0)\r
+    }\r
+\r
+    //\r
+    //  Method Name: WRIT\r
+    //  Arguments:\r
+    //    Arg0:   PORT\r
+    //    Arg1:   REG\r
+    //    Arg2:   BE\r
+    //    Arg3:   DATA\r
+    //  Return Value:\r
+    //  NONE\r
+    //\r
+    Method(WRIT, 4, Serialized)\r
+    {\r
+      If (Lequal (AVBL, 1))\r
+      {\r
+        Store(1, OP)  // must be set at first, do not change!\r
+        Store(Arg0, PORT)\r
+        Store(Arg1, REG)\r
+        Store(Arg2, BE)\r
+        Store(Arg3, DATA)\r
+      }\r
+    }\r
+\r
+    //\r
+    //  Method Name: MODI\r
+    //  Arguments:\r
+    //    Arg0:   PORT\r
+    //    Arg1:   REG\r
+    //    Arg2:   BE\r
+    //    Arg3:   DATA\r
+    //    Arg4:   MASK\r
+    //  Return Value:\r
+    //  NONE\r
+    //\r
+    Method(MODI, 5, Serialized)\r
+    {\r
+      If (Lequal (AVBL, 1))\r
+      {\r
+        Store(2, OP)  // must be set at first, do not change!\r
+        Store(Arg0, PORT)\r
+        Store(Arg1, REG)\r
+        Store(Arg2, BE)\r
+        Store(Arg3, DATA)\r
+        Store(Arg4, MASK)\r
+      }\r
+    }\r
+  }\r
+\r
+\r
+} // end Scope(\_SB)\r
+\r
+Name(PICM, 0)   // Global Name, returns current Interrupt controller mode; updated from _PIC control method\r
+\r

diff --git a/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/RTD3.asl b/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/RTD3.asl
new file mode 100644 (file)
index 0000000..eb607c6
--- /dev/null
+++ b/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/RTD3.asl
@@ -0,0 +1,203 @@
+/**************************************************************************;\r
+;*                                                                        *;\r
+;*                                                                        *;\r
+;*    Intel Corporation - ACPI Reference Code for the Baytrail            *;\r
+;*    Family of Customer Reference Boards.                                *;\r
+;*                                                                        *;\r
+;*                                                                        *;\r
+;*    Copyright (c) 2012  - 2014, Intel Corporation. All rights reserved    *;\r
+;\r
+; This program and the accompanying materials are licensed and made available under\r
+; the terms and conditions of the BSD License that accompanies this distribution.\r
+; The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php.\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+;*                                                                        *;\r
+;*                                                                        *;\r
+;**************************************************************************/\r
+DefinitionBlock (\r
+  "Rtd3.aml",\r
+  "SSDT",\r
+  1,\r
+  "AcpiRef",\r
+  "Msg_Rtd3",\r
+  0x1000\r
+)\r
+{\r
+  External(RTD3)             //flag if RTD3 is enabled\r
+\r
+  If(LEqual(RTD3,1))\r
+  {\r
+    Scope (\_SB)\r
+    {\r
+      Name(OSCI, 0)  // \_SB._OSC DWORD2 input\r
+      Name(OSCO, 0)  // \_SB._OSC DWORD2 output\r
+\r
+      //Arg0 -- A buffer containing UUID\r
+      //Arg1 -- An Interger containing a Revision ID of the buffer format\r
+      //Arg2 -- An interger containing a count of entries in Arg3\r
+      //Arg3 -- A buffer containing a list of DWORD capacities\r
+      Method(_OSC, 4, NotSerialized)\r
+      {\r
+        // Check for proper UUID\r
+        If(LEqual(Arg0, ToUUID("0811B06E-4A27-44F9-8D60-3CBBC22E7B48")))\r
+        {\r
+          CreateDWordField(Arg3,0,CDW1)     //bit1,2 is always clear\r
+          CreateDWordField(Arg3,4,CDW2)     //Table 6-147 from ACPI spec\r
+\r
+          Store(CDW2, OSCI)                 // Save DWord2\r
+          Or(OSCI, 0x4, OSCO)               // Only allow _PR3 support\r
+\r
+          If(LNotEqual(Arg1,One))\r
+          {\r
+            Or(CDW1,0x08,CDW1)            // Unknown revision\r
+          }\r
+\r
+          If(LNotEqual(OSCI, OSCO))\r
+          {\r
+            Or(CDW1,0x10,CDW1)            // Capabilities bits were masked\r
+          }\r
+\r
+          Store(OSCO, CDW2)                 // Replace DWord2\r
+          Return(Arg3)\r
+        } Else\r
+        {\r
+          Or(CDW1,4,CDW1)                   // Unrecognized UUID\r
+          Return(Arg3)\r
+        }\r
+      }// End _OSC\r
+    }\r
+  }//end of RTD3 condition\r
+\r
+\r
+  //USB RTD3 code\r
+  If(LEqual(RTD3,1))\r
+  {\r
+    Scope(\_SB.PCI0.EHC1.HUBN.PR01.PR13)\r
+    {\r
+      Name(_PR0, Package() {\PR34})\r
+      Name(_PR3, Package() {\PR34})\r
+\r
+      Method(_S0W, 0)\r
+      {\r
+        If(And(\_SB.OSCO, 0x04))              // PMEs can be genrated from D3cold\r
+        {\r
+          Return(4)                         // OS comprehends D3cold, as described via \_SB._OSC\r
+        } Else\r
+        {\r
+          Return(3)\r
+        }\r
+      } // End _S0W\r
+    }\r
+\r
+    Scope(\_SB.PCI0.EHC1.HUBN.PR01.PR14)\r
+    {\r
+      Name(_PR0, Package() {\PR34})\r
+      Name(_PR3, Package() {\PR34})\r
+\r
+      Method(_S0W, 0)\r
+      {\r
+        If(And(\_SB.OSCO, 0x04))\r
+        {\r
+          Return(4)\r
+        } Else\r
+        {\r
+          Return(3)\r
+        }\r
+      } // End _S0W\r
+    }\r
+\r
+\r
+    Scope(\_SB.PCI0.EHC1.HUBN.PR01.PR15)\r
+    {\r
+      Name(_PR0, Package() {\PR56})\r
+      Name(_PR3, Package() {\PR56})\r
+\r
+      Method(_S0W, 0)\r
+      {\r
+        If(And(\_SB.OSCO, 0x04))\r
+        {\r
+          Return(4)\r
+        } Else\r
+        {\r
+          Return(3)\r
+        }\r
+      } // End _S0W\r
+    }\r
+\r
+    Scope(\_SB.PCI0.EHC1.HUBN.PR01.PR16)\r
+    {\r
+      Name(_PR0, Package() {\PR56})\r
+      Name(_PR3, Package() {\PR56})\r
+\r
+      Method(_S0W, 0)\r
+      {\r
+        If(And(\_SB.OSCO, 0x04))\r
+        {\r
+          Return(4)\r
+        } Else\r
+        {\r
+          Return(3)\r
+        }\r
+      } // End _S0W\r
+    }\r
+\r
+    Scope(\_SB.PCI0.XHC1)                              // XHCI host only controller\r
+    {\r
+\r
+      Method(_PS0,0,Serialized)                      // set device into D0 state\r
+      {\r
+      }\r
+\r
+      Method(_PS3,0,Serialized)                      // place device into D3H state\r
+      {\r
+        //write to PMCSR\r
+      }\r
+\r
+      Method(_DSW, 3,Serialized)                     // enable or disable the device’s ability to wake a sleeping system.\r
+      {\r
+      }\r
+    }\r
+\r
+    Scope(\_SB.PCI0.XHC1.RHUB.HS01)\r
+    {\r
+\r
+    }\r
+\r
+    Scope(\_SB.PCI0.XHC1.RHUB.SSP1)\r
+    {\r
+\r
+    }\r
+\r
+    Scope(\_SB.PCI0.XHC2)                              // OTG\r
+    {\r
+\r
+      Method(_PS0,0,Serialized)                      // set device into D0 state\r
+      {\r
+      }\r
+\r
+      Method(_PS3,0,Serialized)                      // place device into D3H state\r
+      {\r
+        //write to PMCSR\r
+      }\r
+\r
+      Method(_DSW, 3,Serialized)                      // enable or disable the device’s ability to wake a sleeping system.\r
+      {\r
+      }\r
+    }\r
+\r
+    Scope(\_SB.PCI0.XHC2.RHUB.HS01)\r
+    {\r
+\r
+    }\r
+\r
+    Scope(\_SB.PCI0.XHC2.RHUB.SSP1)\r
+    {\r
+\r
+    }\r
+  } //If(LEqual(RTD3,1)) USB\r
+\r
+}//end of SSDT\r

diff --git a/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/THERMAL.ASL b/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/THERMAL.ASL
new file mode 100644 (file)
index 0000000..e63f5bc
--- /dev/null
+++ b/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/THERMAL.ASL
@@ -0,0 +1,138 @@
+/**************************************************************************;\r
+;*                                                                        *;\r
+;*                                                                        *;\r
+;*    Intel Corporation - ACPI Reference Code for the Baytrail            *;\r
+;*    Family of Customer Reference Boards.                                *;\r
+;*                                                                        *;\r
+;*                                                                        *;\r
+;*    Copyright (c)  1999  - 2014, Intel Corporation. All rights reserved   *;\r
+;\r
+; This program and the accompanying materials are licensed and made available under\r
+; the terms and conditions of the BSD License that accompanies this distribution.\r
+; The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php.\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+;*                                                                        *;\r
+;*                                                                        *;\r
+;**************************************************************************/\r
+\r
+\r
+// THERMAL.ASL represents a Thermal Zone to be used for testing on the\r
+// Customer Reference Boards.\r
+\r
+External(\_SB.DPTF.CTOK, MethodObj)\r
+\r
+Scope(\_TZ)\r
+{\r
+\r
+  // Thermal Zone 1 = DTS Thermal Zone.\r
+\r
+  ThermalZone(TZ01)\r
+  {\r
+    // Return the temperature at which the OS must perform a Critcal\r
+    // Shutdown.\r
+\r
+    Method(_CRT,0,Serialized)\r
+    {\r
+      Return(Add(2732,Multiply(CRTT,10)))\r
+    }\r
+\r
+    // Notifies ASL Code the current cooling mode.\r
+    //      0 - Active cooling\r
+    //      1 - Passive cooling\r
+\r
+    Method(_SCP,1,Serialized)\r
+    {\r
+      Store(Arg0,CTYP)\r
+    }\r
+\r
+    // _TMP (Temperature)\r
+    //\r
+    // Return the highest of the CPU temperatures to the OS.\r
+    //\r
+    // Arguments: (0)\r
+    //   None\r
+    // Return Value:\r
+    //   An Integer containing the current temperature of the thermal zone (in tenths of degrees Kelvin)\r
+    //\r
+    Method(_TMP,0,Serialized)\r
+    {\r
+      If(DTSE)\r
+      {\r
+        If(LGreater(DTS2, DTS1))\r
+        {\r
+          Store(DTS2,Local0)\r
+        } else\r
+        {\r
+          Store(DTS1,Local0)\r
+        }\r
+        Return(Add(2732,Multiply(Local0,10)))\r
+        //\r
+        // Else return a static value if both EC and DTS are unavailable.\r
+        //\r
+      } Else\r
+      {\r
+        Return(3000) // (3000-2732)/10 = 26.8 degree C\r
+      }\r
+    }\r
+\r
+    // Return the Processor(s) used for Passive Cooling.\r
+\r
+    Method(_PSL,0,Serialized)\r
+    {\r
+      If(LEqual(MPEN, 4))\r
+      {\r
+        //  CMP - Throttling controls all four logical CPUs.\r
+        Return(Package() {\_PR.CPU0,\_PR.CPU1,\_PR.CPU2,\_PR.CPU3})\r
+      }\r
+\r
+      If(MPEN)\r
+      {\r
+        //  CMP - Throttling controls both CPUs.\r
+\r
+        Return(Package() {\_PR.CPU0,\_PR.CPU1})\r
+      }\r
+\r
+      Return(Package() {\_PR.CPU0})\r
+    }\r
+\r
+    // Returns the temperature at which the OS initiates CPU throttling.\r
+\r
+    Method(_PSV,0,Serialized)\r
+    {\r
+      Return(Add(2732,Multiply(PSVT,10)))\r
+    }\r
+\r
+    // Returns TC1 value used in the passive cooling formula.\r
+\r
+    Method(_TC1,0,Serialized)\r
+    {\r
+      Return(TC1V)\r
+    }\r
+\r
+    // Returns TC2 value used in the passive cooling formula.\r
+\r
+    Method(_TC2,0,Serialized)\r
+    {\r
+      Return(TC2V)\r
+    }\r
+\r
+    // Returns the sampling period used in the passive cooling formula.\r
+\r
+    Method(_TSP,0,Serialized)\r
+    {\r
+      Return(TSPV)\r
+    }\r
+\r
+    // Returns Hot Temperature\r
+\r
+    Method(_HOT,0,Serialized)\r
+    {\r
+      Subtract(CRTT, 5, Local0)\r
+      Return(Add(2732,Multiply(Local0,10)))\r
+    }\r
+  }\r
+}\r

diff --git a/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/UsbSbd.asl b/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/UsbSbd.asl
new file mode 100644 (file)
index 0000000..020bc97
--- /dev/null
+++ b/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/UsbSbd.asl
@@ -0,0 +1,99 @@
+/************************************************************************************;\r
+;*                                                                                  *;\r
+;*                                                                                  *;\r
+;*    Intel Corporation - ACPI Reference Code for the Baytrail                      *;\r
+;*    Family of Customer Reference Boards.                                          *;\r
+;*                                                                                  *;\r
+;*    MPG-MSAE                                                                      *;\r
+;*                                                                                  *;\r
+;*    Copyright (c) 1999 - 2014, Intel Corporation.                                 *;\r
+;*                                                                                  *;\r
+;* This program and the accompanying materials are licensed and made available under*;\r
+;* the terms and conditions of the BSD License that accompanies this distribution.  *;\r
+;* The full text of the license may be found at                                     *;\r
+;* http://opensource.org/licenses/bsd-license.php.                                  *;\r
+;*                                                                                  *;\r
+;* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            *;\r
+;* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    *;\r
+;*                                                                                  *;\r
+;*                                                                                  *;\r
+;*    This program has been developed by Intel Corporation.                         *;\r
+;*    Licensee has Intel's permission to incorporate this source code               *;\r
+;*    into their product, royalty free.  This source code may NOT be                *;\r
+;*    redistributed to anyone without Intel's written permission.                   *;\r
+;*                                                                                  *;\r
+;*    Intel specifically disclaims all warranties, express or                       *;\r
+;*    implied, and all liability, including consequential and other                 *;\r
+;*    indirect damages, for the use of this code, including liability               *;\r
+;*    for infringement of any proprietary rights, and including the                 *;\r
+;*    warranties of merchantability and fitness for a particular                    *;\r
+;*    purpose.  Intel does not assume any responsibility for any                    *;\r
+;*    errors which may appear in this code nor any responsibility to                *;\r
+;*    update it.                                                                    *;\r
+;*                                                                                  *;\r
+;*    Version:  See README.TXT                                                      *;\r
+;*                                                                                  *;\r
+;************************************************************************************/\r
+\r
+//\r
+// _DSM : Device Specific Method supporting USB Sideband Deferring function\r
+//\r
+// Arg0: UUID Unique function identifier\r
+// Arg1: Integer Revision Level\r
+// Arg2: Integer Function Index\r
+// Arg3: Package Parameters\r
+//\r
+Method (_DSM, 4, Serialized, 0, UnknownObj, {BuffObj, IntObj, IntObj, PkgObj})\r
+{\r
+\r
+  If (LEqual(Arg0, ToUUID ("A5FC708F-8775-4BA6-BD0C-BA90A1EC72F8")))\r
+  {\r
+    //\r
+    // Switch by function index\r
+    //\r
+    Switch (ToInteger(Arg2))\r
+    {\r
+      //\r
+      // Standard query - A bitmask of functions supported\r
+      // Supports function 0-2\r
+      //\r
+      Case (0)\r
+      {\r
+        if (LEqual(Arg1, 1))   // test Arg1 for the revision\r
+        {\r
+          Return (Buffer () {0x07})\r
+        }\r
+        else\r
+        {\r
+          Return (Buffer () {0})\r
+        }\r
+      }\r
+      //\r
+      // USB Sideband Deferring Support\r
+      //   0: USB Sideband Deferring not supported on this device\r
+      //   1: USB Sideband Deferring supported\r
+      //\r
+      Case (1)\r
+      {\r
+        if (LEqual(SDGV,0xFF))   // check for valid GPE vector\r
+        {\r
+          Return (0)\r
+        }\r
+        else\r
+        {\r
+          Return (1)\r
+        }\r
+      }\r
+      //\r
+      // GPE Vector\r
+      //  Return the bit offset within the GPE block of the GPIO (HOST_ALERT) driven by this device\r
+      //\r
+      Case (2)\r
+      {\r
+        Return (SDGV)\r
+      }\r
+    }\r
+  }\r
+\r
+  Return (0)\r
+}\r

diff --git a/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/Video.asl b/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/Video.asl
new file mode 100644 (file)
index 0000000..46d0aba
--- /dev/null
+++ b/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/Video.asl
@@ -0,0 +1,40 @@
+/**************************************************************************;\r
+;*                                                                        *;\r
+;*                                                                        *;\r
+;*    Intel Corporation - ACPI Reference Code for the Baytrail            *;\r
+;*    Family of Customer Reference Boards.                                *;\r
+;*                                                                        *;\r
+;*                                                                        *;\r
+;*    Copyright (c)  1999  - 2014, Intel Corporation. All rights reserved   *;\r
+;\r
+; This program and the accompanying materials are licensed and made available under\r
+; the terms and conditions of the BSD License that accompanies this distribution.\r
+; The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php.\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+;*                                                                        *;\r
+;*                                                                        *;\r
+;**************************************************************************/\r
+\r
+\r
+\r
+\r
+// Brightness Notification:\r
+//              Generate a brightness related notification\r
+//      to the LFP if its populated.\r
+//\r
+//      Arguments:\r
+//              Arg0:   Notification value.\r
+//\r
+//      Return Value:\r
+//              None\r
+Method(BRTN,1,Serialized)\r
+{\r
+  If(LEqual(And(DIDX,0x0F00),0x400))\r
+  {\r
+    Notify(\_SB.PCI0.GFX0.DD1F,Arg0)\r
+  }\r
+}\r

diff --git a/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/Vlv.asl b/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/Vlv.asl
new file mode 100644 (file)
index 0000000..66c741f
--- /dev/null
+++ b/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/Vlv.asl
@@ -0,0 +1,45 @@
+/*++\r
+\r
+Copyright (c)  1999  - 2014, Intel Corporation. All rights reserved\r
+\r
+  This program and the accompanying materials are licensed and made available under\r
+  the terms and conditions of the BSD License that accompanies this distribution.\r
+  The full text of the license may be found at\r
+  http://opensource.org/licenses/bsd-license.php.\r
+\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+\r
+Module Name:\r
+\r
+  VLV.ASL\r
+\r
+Abstract:\r
+\r
+  Baytrail PCI configuration space definition.\r
+\r
+--*/\r
+Scope (\_SB.PCI0)\r
+{\r
+\r
+  Device(GFX0)   // Mobile I.G.D\r
+  {\r
+    Name(_ADR, 0x00020000)\r
+\r
+    Method(GDEP, 0)\r
+    {\r
+      If(LEqual(OSYS,2013))\r
+      {\r
+        Name(_DEP, Package(0x1)\r
+        {\r
+          PEPD\r
+        })\r
+      }\r
+    }\r
+\r
+    include("INTELGFX.ASL")\r
+    include("INTELISPDev2.ASL")\r
+  } // end "Mobile I.G.D"\r
+}//end scope\r

diff --git a/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/token.asl b/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/token.asl
new file mode 100644 (file)
index 0000000..8df5b31
--- /dev/null
+++ b/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/token.asl
@@ -0,0 +1,45 @@
+/**************************************************************************;\r
+;*                                                                        *;\r
+;*                                                                        *;\r
+;*    Intel Corporation - ACPI Reference Code for the Sandy Bridge        *;\r
+;*    Family of Customer Reference Boards.                                *;\r
+;*                                                                        *;\r
+;*                                                                        *;\r
+;*    Copyright (c) 2012  - 2014, Intel Corporation. All rights reserved    *;\r
+;\r
+; This program and the accompanying materials are licensed and made available under\r
+; the terms and conditions of the BSD License that accompanies this distribution.\r
+; The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php.\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+;*                                                                        *;\r
+;*                                                                        *;\r
+;**************************************************************************/\r
+\r
+Name(PMBS, 0x400)       // ASL alias for ACPI I/O base address.\r
+Name(SMIP, 0xb2)        // I/O port to trigger SMI\r
+Name(GPBS, 0x500)       // GPIO Register Block address\r
+Name(APCB, 0xfec00000)  // Default I/O APIC(s) memory start address, 0x0FEC00000 - default, 0 - I/O APIC's disabled\r
+Name(APCL, 0x1000)      // I/O APIC(s) memory decoded range, 0x1000 - default, 0 - I/O APIC's not decoded\r
+Name(PFDR, 0xfed03034)  // PMC Function Disable Register\r
+Name(PMCB, 0xfed03000)  // PMC Base Address\r
+Name(PCLK, 0xfed03060)  // PMC Clock Control Register\r
+Name(PUNB, 0xfed05000)  // PUNIT Base Address\r
+Name(IBAS, 0xfed08000)  // ILB Base Address\r
+Name(SRCB, 0xfed1c000)  // RCBA (Root Complex Base Address)\r
+Name(SRCL, 0x1000)      // RCBA length\r
+Name(HPTB, 0xfed00000)  // Same as HPET_BASE_ADDRESS for ASL use\r
+Name(PEBS, 0xe0000000)  // PCIe Base\r
+Name(PELN, 0x10000000)  //\r
+Name(FMBL, 0x1) // Platform Flavor - Mobile flavor for ASL code.\r
+Name(FDTP, 0x2) // Platform Flavor - Desktop flavor for ASL code.\r
+Name(SDGV, 0x1c)        // UHCI Controller HOST_ALERT's bit offset within the GPE block. GPIO[0:15] corresponding to GPE[16:31]\r
+Name(PEHP, 0x1) // _OSC: Pci Express Native Hot Plug Control\r
+Name(SHPC, 0x0) // _OSC: Standard Hot Plug Controller (SHPC) Native Hot Plug control\r
+Name(PEPM, 0x1) // _OSC: Pci Express Native Power Management Events control\r
+Name(PEER, 0x1) // _OSC: Pci Express Advanced Error Reporting control\r
+Name(PECS, 0x1) // _OSC: Pci Express Capability Structure control\r
+\r

diff --git a/Vlv2DeviceRefCodePkg/Include/Guid/Vlv2DeviceRefCodePkgTokenSpace.h b/Vlv2DeviceRefCodePkg/Include/Guid/Vlv2DeviceRefCodePkgTokenSpace.h
new file mode 100644 (file)
index 0000000..24faf23
--- /dev/null
+++ b/Vlv2DeviceRefCodePkg/Include/Guid/Vlv2DeviceRefCodePkgTokenSpace.h
@@ -0,0 +1,30 @@
+/*++\r
+\r
+Copyright (c)  2010  - 2014, Intel Corporation. All rights reserved\r
+\r
+  This program and the accompanying materials are licensed and made available under\r
+  the terms and conditions of the BSD License that accompanies this distribution.\r
+  The full text of the license may be found at\r
+  http://opensource.org/licenses/bsd-license.php.\r
+\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+Module Name:\r
+\r
+  Vlv2DeviceRefCodeTokenSpace.h\r
+\r
+Abstract:\r
+\r
+  Interface definition details for GUID.\r
+\r
+--*/\r
+#ifndef __VLV2_REF_CODE__PKG_TOKEN_SPACE_GUID_H__\r
+#define __VLV2_REF_CODE__PKG_TOKEN_SPACE_GUID_H__\r
+\r
+#define EFI_VLV_TOKEN_SPACE_GUID \\r
+  { 0xca452c68, 0xdf0c, 0x45c9, {0x82, 0xfb, 0xea, 0xe4, 0x2b, 0x31, 0x29, 0x46}}\r
+extern EFI_GUID gEfiVLVTokenSpaceGuid;\r
+\r
+#endif\r

diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/Include/Guid/PowerManagementAcpiTableStorage.h b/Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/Include/Guid/PowerManagementAcpiTableStorage.h
new file mode 100644 (file)
index 0000000..535258f
--- /dev/null
+++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/Include/Guid/PowerManagementAcpiTableStorage.h
@@ -0,0 +1,33 @@
+\r
+/*++\r
+\r
+Copyright (c)  1999  - 2014, Intel Corporation. All rights reserved\r
+\r
+  This program and the accompanying materials are licensed and made available under\r
+  the terms and conditions of the BSD License that accompanies this distribution.\r
+  The full text of the license may be found at\r
+  http://opensource.org/licenses/bsd-license.php.\r
+\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+Module Name:\r
+\r
+  PowerManagementAcpiTableStorage.h\r
+\r
+Abstract:\r
+\r
+  GUID definition for the Power Management ACPI table storage file name\r
+\r
+--*/\r
+\r
+#ifndef _POWER_MANAGEMENT_ACPI_TABLE_STORAGE_H_\r
+#define _POWER_MANAGEMENT_ACPI_TABLE_STORAGE_H_\r
+\r
+#define POWER_MANAGEMENT_ACPI_TABLE_STORAGE_GUID \\r
+  { 0x161be597, 0xe9c5, 0x49db, 0xae, 0x50, 0xc4, 0x62, 0xab, 0x54, 0xee, 0xda }\r
+\r
+extern EFI_GUID gPowerManagementAcpiTableStorageGuid;\r
+\r
+#endif\r

diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/Include/Ppi/VlvPolicy.h b/Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/Include/Ppi/VlvPolicy.h
new file mode 100644 (file)
index 0000000..7b0c419
--- /dev/null
+++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/Include/Ppi/VlvPolicy.h
@@ -0,0 +1,110 @@
+\r
+/*++\r
+\r
+Copyright (c)  2010  - 2014, Intel Corporation. All rights reserved\r
+\r
+  This program and the accompanying materials are licensed and made available under\r
+  the terms and conditions of the BSD License that accompanies this distribution.\r
+  The full text of the license may be found at\r
+  http://opensource.org/licenses/bsd-license.php.\r
+\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+Module Name:\r
+\r
+  VlvPolicy.h\r
+\r
+Abstract:\r
+\r
+  Interface definition details between ValleyView MRC and platform drivers during PEI phase.\r
+\r
+--*/\r
+\r
+#ifndef _VLV_POLICY_PPI_H_\r
+#define _VLV_POLICY_PPI_H_\r
+\r
+//\r
+// MRC Policy provided by platform for PEI phase {7D84B2C2-22A1-4372-B12C-EBB232D3A6A3}\r
+//\r
+#define VLV_POLICY_PPI_GUID \\r
+  { \\r
+    0x7D84B2C2, 0x22A1, 0x4372, 0xB1, 0x2C, 0xEB, 0xB2, 0x32, 0xD3, 0xA6, 0xA3 \\r
+  }\r
+\r
+//\r
+// Extern the GUID for protocol users.\r
+//\r
+extern EFI_GUID gVlvPolicyPpiGuid;\r
+\r
+//\r
+// PPI revision number\r
+// Any backwards compatible changes to this PPI will result in an update in the revision number\r
+// Major changes will require publication of a new PPI\r
+//\r
+#define MRC_PLATFORM_POLICY_PPI_REVISION  1\r
+\r
+#ifndef MAX_SOCKETS\r
+#define MAX_SOCKETS 4\r
+#endif\r
+\r
+#define S3_TIMING_DATA_LEN          9\r
+#define S3_READ_TRAINING_DATA_LEN   16\r
+#define S3_WRITE_TRAINING_DATA_LEN  12\r
+\r
+#ifndef S3_RESTORE_DATA_LEN\r
+#define S3_RESTORE_DATA_LEN (S3_TIMING_DATA_LEN + S3_READ_TRAINING_DATA_LEN + S3_WRITE_TRAINING_DATA_LEN)\r
+#endif // S3_RESTORE_DATA_LEN\r
+#pragma pack(1)\r
+//\r
+// MRC Platform Data Structure\r
+//\r
+typedef struct {\r
+  UINT8   SpdAddressTable[MAX_SOCKETS];\r
+  UINT8   TSonDimmSmbusAddress[MAX_SOCKETS];\r
+\r
+  UINT16  SmbusBar;\r
+  UINT32  IchRcba;\r
+  UINT32  WdbBaseAddress; // Write Data Buffer area (WC caching mode)\r
+  UINT32  WdbRegionSize;\r
+  UINT32  SmBusAddress;\r
+  UINT8   UserBd;\r
+  UINT8   PlatformType;\r
+  UINT8   FastBoot;\r
+  UINT8   DynSR;\r
+} VLV_PLATFORM_DATA;\r
+\r
+\r
+typedef struct {\r
+  UINT16  MmioSize;\r
+  UINT16  GttSize;\r
+  UINT8   IgdDvmt50PreAlloc;\r
+  UINT8   PrimaryDisplay;\r
+  UINT8   PAVPMode;\r
+  UINT8   ApertureSize;\r
+} GT_CONFIGURATION;\r
+\r
+typedef struct {\r
+  UINT8   EccSupport;\r
+  UINT16  DdrFreqLimit;\r
+  UINT8   MaxTolud;\r
+} MEMORY_CONFIGURATION;\r
+\r
+\r
+//\r
+// MRC Platform Policiy PPI\r
+//\r
+typedef struct _VLV_POLICY_PPI {\r
+  UINT8                 Revision;\r
+  VLV_PLATFORM_DATA     PlatformData;\r
+  GT_CONFIGURATION      GtConfig;\r
+  MEMORY_CONFIGURATION  MemConfig;\r
+  VOID                  *S3DataPtr; // was called MRC_PARAMS_SAVE_RESTORE\r
+  UINT8                 ISPEn;            //ISP (IUNIT) Device Enabled\r
+  UINT8                 ISPPciDevConfig;  //ISP (IUNIT) Device Config: 0->B0/D2/F0 for Window OS, 1->B0D3/F0 for Linux OS\r
+} VLV_POLICY_PPI;\r
+\r
+#pragma pack()\r
+\r
+#endif // _VLV_POLICY_PPI_H_\r

diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/Include/Protocol/PpmPlatformPolicy.h b/Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/Include/Protocol/PpmPlatformPolicy.h
new file mode 100644 (file)
index 0000000..4b9f992
--- /dev/null
+++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/Include/Protocol/PpmPlatformPolicy.h
@@ -0,0 +1,138 @@
+/** \r
+  Copyright (c) 2009 - 2013, Intel Corporation. All rights reserved.<BR>\r
+  This program and the accompanying materials\r
+  are licensed and made available under the terms and conditions of the BSD License\r
+  which accompanies this distribution.  The full text of the license may be found at\r
+  http://opensource.org/licenses/bsd-license.php\r
+\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+/*++\r
+\r
+Module Name:\r
+\r
+  PpmPlatformPolicy.h\r
+\r
+Abstract:\r
+\r
+  Interface definition details between PPM and platform drivers during DXE phase.\r
+\r
+--*/\r
+#ifndef _PPM_PLATFORM_POLICY_H_\r
+#define _PPM_PLATFORM_POLICY_H_\r
+\r
+//\r
+//  PPM policy provided by platform for DXE phase {DDABFEAC-EF63-452c-8F39-ED7FAED8265E}\r
+//\r
+#define PPM_PLATFORM_POLICY_PROTOCOL_GUID \\r
+  {0xddabfeac, 0xef63, 0x452c, 0x8f, 0x39, 0xed, 0x7f, 0xae, 0xd8, 0x26, 0x5e}\r
+\r
+//\r
+// Extern the GUID for protocol users.\r
+//\r
+extern EFI_GUID gPpmPlatformPolicyProtocolGuid;\r
+\r
+//\r
+// Forward reference for ANSI C compatibility\r
+//\r
+typedef struct _PPM_PLATFORM_POLICY_PROTOCOL PPM_PLATFORM_POLICY_PROTOCOL;\r
+\r
+//\r
+// Protocol revision number\r
+// Any backwards compatible changes to this protocol will result in an update in the revision number\r
+// Major changes will require publication of a new protocol\r
+//\r
+// Revision 1: Original version\r
+// Revision 2: Added T-states field to the PPM_FUNCTION_ENABLES structure, Renamed unused fields - CxPopUpEnable, CxPopDownEnable, FastC4ExitEnable\r
+// Revision 3: Extended VidCpuid to 32 bits for extended CPUID support (Penryn)\r
+// Revision 4: Added support for extended C6 residency enabling\r
+//\r
+#define PPM_PLATFORM_POLICY_PROTOCOL_REVISION     1\r
+#define PPM_PLATFORM_POLICY_PROTOCOL_REVISION_2   2\r
+#define PPM_PLATFORM_POLICY_PROTOCOL_REVISION_3   3\r
+#define PPM_PLATFORM_POLICY_PROTOCOL_REVISION_4   4\r
+\r
+//\r
+// Define maximum number of custom VID states supported\r
+//\r
+#ifndef MAX_CUSTOM_VID_TABLE_STATES\r
+#define MAX_CUSTOM_VID_TABLE_STATES               6\r
+#endif\r
+//\r
+// Custom VID table\r
+//\r
+typedef struct {\r
+  UINT8   VidNumber;\r
+  UINT32  VidCpuid;\r
+  UINT16  VidMaxRatio;\r
+  UINT16  VidMaxVid;\r
+  UINT16  StateRatio[MAX_CUSTOM_VID_TABLE_STATES];\r
+  UINT16  StateVid[MAX_CUSTOM_VID_TABLE_STATES];\r
+} PPM_CUSTOM_VID_TABLE;\r
+\r
+//\r
+// PPM functional enables\r
+//\r
+typedef struct {\r
+  UINT8   EnableGv                   :1; // 0: Disabled; 1: Enabled\r
+  UINT8   EnableCx                   :1;\r
+  UINT8   EnableCxe                  :1;\r
+  UINT8   EnableC4                   :1;\r
+  UINT8   EnableC6                   :1;\r
+  UINT8   EnableC7                   :1;\r
+  UINT8   EnableTm                   :1;\r
+  UINT8   Reserve00                  :1;\r
+  UINT8   Reserve01                  :1;\r
+  UINT8   EnableTurboMode            :1;\r
+  UINT8   PowerLimit2                :1;\r
+  UINT8   EnableProcHot              :1;\r
+  UINT8   Reserve02                  :1;\r
+  UINT8   EnableCMP                  :1;\r
+  UINT8   TStatesEnable              :1;\r
+  UINT8   Reserve03                  :1;\r
+  UINT8   Reserve04                  ;\r
+\r
+} PPM_FUNCTION_ENABLES;\r
+\r
+\r
+//\r
+// PPM Turbo settings\r
+//\r
+typedef struct _PPM_TURBO_SETTINGS {\r
+  UINT16  PowerLimit1;\r
+  UINT32  PowerLimit1Time;\r
+  UINT16  PowerLimit2;\r
+  UINT8   TurboPowerLimitLock;\r
+} PPM_TURBO_SETTINGS;\r
+\r
+//\r
+// Platform Policy\r
+//\r
+typedef struct _PPM_PLATFORM_POLICY_PROTOCOL {\r
+  UINT8                                 Revision;\r
+  PPM_FUNCTION_ENABLES                  FunctionEnables;\r
+  PPM_CUSTOM_VID_TABLE                  CustomVidTable;\r
+  PPM_TURBO_SETTINGS                    TurboSettings;\r
+\r
+  UINT8                                 Reserve00;\r
+  UINT8                                 Reserve01;\r
+  UINT8                                 Reserve02;\r
+  UINT8                                 Reserve03;\r
+  UINT8                                 Reserve04;\r
+  UINT8                                 Reserve05;\r
+  UINT8                                 Reserve06;\r
+\r
+  UINT8                                 S3RestoreMsrSwSmiNumber;\r
+  UINT8                                 Reserve07;\r
+  UINT32                                Reserve08;\r
+  UINT8                                 Reserve09;\r
+  //\r
+  // Primary and Secondary Plane Current Limits\r
+  //\r
+  UINT16                                Reserve10;\r
+  UINT8                                 Reserve11;\r
+} PPM_PLATFORM_POLICY_PROTOCOL;\r
+\r
+#endif\r

diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/Include/Types.h b/Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/Include/Types.h
new file mode 100644 (file)
index 0000000..c808501
--- /dev/null
+++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/Include/Types.h
@@ -0,0 +1,61 @@
+/*++\r
+\r
+Copyright (c) 1999  - 2014, Intel Corporation. All rights reserved\r
+\r
+  This program and the accompanying materials are licensed and made available under\r
+  the terms and conditions of the BSD License that accompanies this distribution.\r
+  The full text of the license may be found at\r
+  http://opensource.org/licenses/bsd-license.php.\r
+\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+\r
+Module Name:\r
+\r
+    Types.h\r
+\r
+Abstract:\r
+\r
+    This file include all the external data types.\r
+\r
+--*/\r
+\r
+#ifndef _TYPES_H_\r
+#define _TYPES_H_\r
+\r
+\r
+\r
+//\r
+// Modifiers to abstract standard types to aid in debug of problems\r
+//\r
+#define CONST     const\r
+#define STATIC    static\r
+#define VOID      void\r
+#define VOLATILE  volatile\r
+\r
+//\r
+// Constants. They may exist in other build structures, so #ifndef them.\r
+//\r
+#ifndef TRUE\r
+#define TRUE  ((BOOLEAN) 1 == 1)\r
+#endif\r
+\r
+#ifndef FALSE\r
+#define FALSE ((BOOLEAN) 0 == 1)\r
+#endif\r
+\r
+#ifndef NULL\r
+#define NULL  ((VOID *) 0)\r
+#endif\r
+\r
+typedef UINT32 STATUS;\r
+#define SUCCESS 0\r
+#define FAILURE 0xFFFFFFFF\r
+\r
+#ifndef MRC_DEADLOOP\r
+#define MRC_DEADLOOP()    while (TRUE)\r
+#endif\r
+\r
+#endif\r

diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/PowerManagement/AcpiTables/PowerManagementAcpiTables.inf b/Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/PowerManagement/AcpiTables/PowerManagementAcpiTables.inf
new file mode 100644 (file)
index 0000000..72ed9c3
--- /dev/null
+++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/PowerManagement/AcpiTables/PowerManagementAcpiTables.inf
@@ -0,0 +1,45 @@
+#\r
+#/*++\r
+#\r
+#Copyright (c)  1999  - 2014, Intel Corporation. All rights reserved\r
+#\r
+# This program and the accompanying materials are licensed and made available under\r
+# the terms and conditions of the BSD License that accompanies this distribution.\r
+# The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php.\r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+#\r
+#Module Name:\r
+#\r
+#  PowerManagementAcpiTables.inf\r
+#\r
+#Abstract:\r
+#\r
+#  Component description file for the ACPI tables\r
+#\r
+#--*/\r
+\r
+[defines]\r
+  INF_VERSION                    = 0x00010005\r
+  BASE_NAME                      = PowerManagementAcpiTables2\r
+  FILE_GUID                      = 161BE597-E9C5-49DB-AE50-C462AB54EEDA\r
+  MODULE_TYPE                    = USER_DEFINED\r
+  VERSION_STRING                 = 1.0\r
+  EDK_RELEASE_VERSION            = 0x00020000\r
+  EFI_SPECIFICATION_VERSION      = 0x00020000\r
+\r
+\r
+[sources.common]\r
+  Ssdt/Cpu0Cst.asl\r
+  Ssdt/Cpu0Ist.asl\r
+  Ssdt/Cpu0Tst.asl\r
+  Ssdt/ApCst.asl\r
+  Ssdt/ApIst.asl\r
+  Ssdt/ApTst.asl\r
+  Ssdt/CpuPm.asl\r
+\r
+[Packages]\r
+  MdePkg/MdePkg.dec\r

diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/PowerManagement/AcpiTables/Ssdt/ApCst.asl b/Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/PowerManagement/AcpiTables/Ssdt/ApCst.asl
new file mode 100644 (file)
index 0000000..185750e
--- /dev/null
+++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/PowerManagement/AcpiTables/Ssdt/ApCst.asl
@@ -0,0 +1,116 @@
+/*-----------------------------------------------------------------------------\r
+-------------------------------------------------------------------------------\r
+\r
+\r
+ Intel Silvermont Processor Power Management BIOS Reference Code\r
+\r
+ Copyright (c) 2006 - 2014, Intel Corporation\r
+\r
+  This program and the accompanying materials are licensed and made available under\r
+  the terms and conditions of the BSD License that accompanies this distribution.\r
+  The full text of the license may be found at\r
+  http://opensource.org/licenses/bsd-license.php.\r
+\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+ Filename:      CPU1CST.ASL\r
+\r
+ Revision:      Refer to Readme\r
+\r
+ Date:          Refer to Readme\r
+\r
+--------------------------------------------------------------------------------\r
+-------------------------------------------------------------------------------\r
+\r
+ This Processor Power Management BIOS Source Code is furnished under license\r
+ and may only be used or copied in accordance with the terms of the license.\r
+ The information in this document is furnished for informational use only, is\r
+ subject to change without notice, and should not be construed as a commitment\r
+ by Intel Corporation. Intel Corporation assumes no responsibility or liability\r
+ for any errors or inaccuracies that may appear in this document or any\r
+ software that may be provided in association with this document.\r
+\r
+ Except as permitted by such license, no part of this document may be\r
+ reproduced, stored in a retrieval system, or transmitted in any form or by\r
+ any means without the express written consent of Intel Corporation.\r
+\r
+ WARNING: You are authorized and licensed to install and use this BIOS code\r
+ ONLY on an IST PC. This utility may damage any system that does not\r
+ meet these requirements.\r
+\r
+        An IST PC is a computer which\r
+        (1) Is capable of seamlessly and automatically transitioning among\r
+        multiple performance states (potentially operating at different\r
+        efficiency ratings) based upon power source changes, END user\r
+        preference, processor performance demand, and thermal conditions; and\r
+        (2) Includes an Intel Pentium II processors, Intel Pentium III\r
+        processor, Mobile Intel Pentium III Processor-M, Mobile Intel Pentium 4\r
+        Processor-M, Intel Pentium M Processor, or any other future Intel\r
+        processors that incorporates the capability to transition between\r
+        different performance states by altering some, or any combination of,\r
+        the following processor attributes: core voltage, core frequency, bus\r
+        frequency, number of processor cores available, or any other attribute\r
+        that changes the efficiency (instructions/unit time-power) at which the\r
+        processor operates.\r
+\r
+-------------------------------------------------------------------------------\r
+-------------------------------------------------------------------------------\r
+\r
+NOTES:\r
+        (1) <TODO> - IF the trap range and port definitions do not match those\r
+        specified by this reference code, this file must be modified IAW the\r
+        individual implmentation.\r
+\r
+--------------------------------------------------------------------------------\r
+------------------------------------------------------------------------------*/\r
+\r
+\r
+DefinitionBlock (\r
+        "APCST.aml",\r
+        "SSDT",\r
+        1,\r
+        "PmRef",\r
+        "ApCst",\r
+        0x3000\r
+        )\r
+{\r
+External(\_PR.CPU1, DeviceObj)\r
+External(\_PR.CPU2, DeviceObj)\r
+External(\_PR.CPU3, DeviceObj)\r
+External(\_PR.CPU0._CST)\r
+\r
+        Scope(\_PR.CPU1)\r
+        {\r
+                Method(_CST,0)\r
+                {\r
+                        //\r
+                        // Return P0's _CST object.\r
+                        //\r
+                        Return(\_PR.CPU0._CST)\r
+                }\r
+        }\r
+\r
+        Scope(\_PR.CPU2)\r
+        {\r
+                Method(_CST,0)\r
+                {\r
+                        //\r
+                        // Return P0's _CST object.\r
+                        //\r
+                        Return(\_PR.CPU0._CST)\r
+                }\r
+        }\r
+\r
+        Scope(\_PR.CPU3)\r
+        {\r
+                Method(_CST,0)\r
+                {\r
+                        //\r
+                        // Return P0's _CST object.\r
+                        //\r
+                        Return(\_PR.CPU0._CST)\r
+                }\r
+        }\r
+}  // End of Definition Block\r

diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/PowerManagement/AcpiTables/Ssdt/ApIst.asl b/Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/PowerManagement/AcpiTables/Ssdt/ApIst.asl
new file mode 100644 (file)
index 0000000..1c894c2
--- /dev/null
+++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/PowerManagement/AcpiTables/Ssdt/ApIst.asl
@@ -0,0 +1,172 @@
+/*-----------------------------------------------------------------------------\r
+-------------------------------------------------------------------------------\r
+\r
+\r
+ Intel Silvermont Processor Power Management BIOS Reference Code\r
+\r
+ Copyright (c) 2006 - 2014, Intel Corporation\r
+\r
+  This program and the accompanying materials are licensed and made available under\r
+  the terms and conditions of the BSD License that accompanies this distribution.\r
+  The full text of the license may be found at\r
+  http://opensource.org/licenses/bsd-license.php.\r
+\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+ Filename:      APIST.ASL\r
+\r
+ Revision:      Refer to Readme\r
+\r
+ Date:          Refer to Readme\r
+\r
+--------------------------------------------------------------------------------\r
+-------------------------------------------------------------------------------\r
+\r
+ This Processor Power Management BIOS Source Code is furnished under license\r
+ and may only be used or copied in accordance with the terms of the license.\r
+ The information in this document is furnished for informational use only, is\r
+ subject to change without notice, and should not be construed as a commitment\r
+ by Intel Corporation. Intel Corporation assumes no responsibility or liability\r
+ for any errors or inaccuracies that may appear in this document or any\r
+ software that may be provided in association with this document.\r
+\r
+ Except as permitted by such license, no part of this document may be\r
+ reproduced, stored in a retrieval system, or transmitted in any form or by\r
+ any means without the express written consent of Intel Corporation.\r
+\r
+ WARNING: You are authorized and licensed to install and use this BIOS code\r
+ ONLY on an IST PC. This utility may damage any system that does not\r
+ meet these requirements.\r
+\r
+        An IST PC is a computer which\r
+        (1) Is capable of seamlessly and automatically transitioning among\r
+        multiple performance states (potentially operating at different\r
+        efficiency ratings) based upon power source changes, END user\r
+        preference, processor performance demand, and thermal conditions; and\r
+        (2) Includes an Intel Pentium II processors, Intel Pentium III\r
+        processor, Mobile Intel Pentium III Processor-M, Mobile Intel Pentium 4\r
+        Processor-M, Intel Pentium M Processor, or any other future Intel\r
+        processors that incorporates the capability to transition between\r
+        different performance states by altering some, or any combination of,\r
+        the following processor attributes: core voltage, core frequency, bus\r
+        frequency, number of processor cores available, or any other attribute\r
+        that changes the efficiency (instructions/unit time-power) at which the\r
+        processor operates.\r
+\r
+-------------------------------------------------------------------------------\r
+-------------------------------------------------------------------------------\r
+\r
+NOTES:\r
+        (1) <TODO> - IF the trap range and port definitions do not match those\r
+        specified by this reference code, this file must be modified IAW the\r
+        individual implmentation.\r
+\r
+--------------------------------------------------------------------------------\r
+------------------------------------------------------------------------------*/\r
+\r
+\r
+DefinitionBlock (\r
+        "APIST.aml",\r
+        "SSDT",\r
+        1,\r
+        "PmRef",\r
+        "ApIst",\r
+        0x3000\r
+        )\r
+{\r
+        External(\_PR.CPU0._PSS, MethodObj)\r
+        External(\_PR.CPU0._PCT, MethodObj)\r
+        External(\_PR.CPU0._PPC, IntObj)\r
+        External(\_PR.CPU0._PSD, MethodObj)\r
+        External(\_PR.CPU1, DeviceObj)\r
+        External(\_PR.CPU2, DeviceObj)\r
+        External(\_PR.CPU3, DeviceObj)\r
+        External (CFGD)\r
+        External (PDC0)\r
+\r
+        Scope(\_PR.CPU1)\r
+        {\r
+                Method(_PPC,0)\r
+                {\r
+                        Return(\_PR.CPU0._PPC)  // Return P0 _PPC value.\r
+                }\r
+\r
+                Method(_PCT,0)\r
+                {\r
+                        Return(\_PR.CPU0._PCT)  // Return P0 _PCT.\r
+                }\r
+\r
+                Method(_PSS,0)\r
+                {\r
+                        //Return the same table as CPU0 for CMP cases.\r
+                        Return(\_PR.CPU0._PSS)\r
+                }\r
+\r
+                // The _PSD object provides information to the OSPM related\r
+                // to P-State coordination between processors in a multi-processor\r
+                // configurations.\r
+                //\r
+                Method(_PSD,0)\r
+                {\r
+                        Return(\_PR.CPU0._PSD)  // Return P0 _PSD.\r
+                }\r
+        }\r
+\r
+        Scope(\_PR.CPU2)\r
+        {\r
+                Method(_PPC,0)\r
+                {\r
+                        Return(\_PR.CPU0._PPC)  // Return P0 _PPC value.\r
+                }\r
+\r
+                Method(_PCT,0)\r
+                {\r
+                        Return(\_PR.CPU0._PCT)  // Return P0 _PCT.\r
+                }\r
+\r
+                Method(_PSS,0)\r
+                {\r
+                        //Return the same table as CPU0 for CMP cases.\r
+                        Return(\_PR.CPU0._PSS)\r
+                }\r
+\r
+                // The _PSD object provides information to the OSPM related\r
+                // to P-State coordination between processors in a multi-processor\r
+                // configurations.\r
+                //\r
+                Method(_PSD,0)\r
+                {\r
+                        Return(\_PR.CPU0._PSD)  // Return P0 _PSD.\r
+                }\r
+        }\r
+\r
+        Scope(\_PR.CPU3)\r
+        {\r
+                Method(_PPC,0)\r
+                {\r
+                        Return(\_PR.CPU0._PPC)  // Return P0 _PPC value.\r
+                }\r
+\r
+                Method(_PCT,0)\r
+                {\r
+                        Return(\_PR.CPU0._PCT)  // Return P0 _PCT.\r
+                }\r
+\r
+                Method(_PSS,0)\r
+                {\r
+                        //Return the same table as CPU0 for CMP cases.\r
+                        Return(\_PR.CPU0._PSS)\r
+                }\r
+\r
+                // The _PSD object provides information to the OSPM related\r
+                // to P-State coordination between processors in a multi-processor\r
+                // configurations.\r
+                //\r
+                Method(_PSD,0)\r
+                {\r
+                        Return(\_PR.CPU0._PSD)  // Return P0 _PSD.\r
+                }\r
+        }\r
+} // End of Definition Block\r

diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/PowerManagement/AcpiTables/Ssdt/ApTst.asl b/Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/PowerManagement/AcpiTables/Ssdt/ApTst.asl
new file mode 100644 (file)
index 0000000..266f846
--- /dev/null
+++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/PowerManagement/AcpiTables/Ssdt/ApTst.asl
@@ -0,0 +1,268 @@
+/*-----------------------------------------------------------------------------\r
+-------------------------------------------------------------------------------\r
+\r
+\r
+ Intel Platform Processor Power Management BIOS Reference Code\r
+\r
+ Copyright (c) 2007  - 2014, Intel Corporation\r
+\r
+  This program and the accompanying materials are licensed and made available under\r
+  the terms and conditions of the BSD License that accompanies this distribution.\r
+  The full text of the license may be found at\r
+  http://opensource.org/licenses/bsd-license.php.\r
+\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+ Filename:      APTST.ASL\r
+\r
+ Revision:      Refer to Readme\r
+\r
+ Date:          Refer to Readme\r
+\r
+--------------------------------------------------------------------------------\r
+-------------------------------------------------------------------------------\r
+\r
+ This Processor Power Management BIOS Source Code is furnished under license\r
+ and may only be used or copied in accordance with the terms of the license.\r
+ The information in this document is furnished for informational use only, is\r
+ subject to change without notice, and should not be construed as a commitment\r
+ by Intel Corporation. Intel Corporation assumes no responsibility or liability\r
+ for any errors or inaccuracies that may appear in this document or any\r
+ software that may be provided in association with this document.\r
+\r
+ Except as permitted by such license, no part of this document may be\r
+ reproduced, stored in a retrieval system, or transmitted in any form or by\r
+ any means without the express written consent of Intel Corporation.\r
+\r
+ WARNING: You are authorized and licensed to install and use this BIOS code\r
+ ONLY on an IST PC. This utility may damage any system that does not\r
+ meet these requirements.\r
+\r
+        An IST PC is a computer which\r
+        (1) Is capable of seamlessly and automatically transitioning among\r
+        multiple performance states (potentially operating at different\r
+        efficiency ratings) based upon power source changes, END user\r
+        preference, processor performance demand, and thermal conditions; and\r
+        (2) Includes an Intel Pentium II processors, Intel Pentium III\r
+        processor, Mobile Intel Pentium III Processor-M, Mobile Intel Pentium 4\r
+        Processor-M, Intel Pentium M Processor, or any other future Intel\r
+        processors that incorporates the capability to transition between\r
+        different performance states by altering some, or any combination of,\r
+        the following processor attributes: core voltage, core frequency, bus\r
+        frequency, number of processor cores available, or any other attribute\r
+        that changes the efficiency (instructions/unit time-power) at which the\r
+        processor operates.\r
+\r
+-------------------------------------------------------------------------------\r
+-------------------------------------------------------------------------------\r
+\r
+NOTES:\r
+        (1) <TODO> - IF the trap range and port definitions do not match those\r
+        specified by this reference code, this file must be modified IAW the\r
+        individual implmentation.\r
+\r
+--------------------------------------------------------------------------------\r
+------------------------------------------------------------------------------*/\r
+\r
+\r
+DefinitionBlock(\r
+        "APTST.aml",\r
+        "SSDT",\r
+        0x01,\r
+        "PmRef",\r
+        "ApTst",\r
+        0x3000\r
+        )\r
+{\r
+        External(\_PR.CPU1, DeviceObj)\r
+        External(\_PR.CPU2, DeviceObj)\r
+        External(\_PR.CPU3, DeviceObj)\r
+        External(\_PR.CPU0._PTC)\r
+        External(\_PR.CPU0._TSS)\r
+        External(PDC0)\r
+        External(CFGD)\r
+        External(MPEN)\r
+\r
+        Scope(\_PR.CPU1)\r
+        {\r
+                Name(_TPC, 0)   // All T-States are available\r
+\r
+                //\r
+                // T-State Control/Status interface\r
+                //\r
+                Method(_PTC, 0)\r
+                {\r
+                        Return(\_PR.CPU0._PTC)\r
+                }\r
+\r
+                Method(_TSS, 0)\r
+                {\r
+                        Return(\_PR.CPU0._TSS)\r
+                }\r
+\r
+                //\r
+                // T-State Dependency\r
+                //\r
+                Method(_TSD, 0)\r
+                {\r
+                        //\r
+                        // IF four cores are supported/enabled && !(direct access to MSR)\r
+                        //    Report 4 processors and SW_ANY as the coordination\r
+                        // IF two cores are supported/enabled && !(direct access to MSR)\r
+                        //    Report 2 processors and SW_ANY as the coordination type\r
+                        //  ELSE\r
+                        //    Report 1 processor and SW_ALL as the coordination type (domain 1)\r
+                        //\r
+                        //  CFGD[23] = Four cores enabled\r
+                        //  CFGD[24] = Two or more cores enabled\r
+                        //  PDCx[2] = OSPM is capable of direct access to On\r
+                        //              Demand throttling MSR\r
+                        //\r
+\r
+                If(LNot(And(PDC0,4)))\r
+                {\r
+                                Return(Package(){       // SW_ANY\r
+                                        Package(){\r
+                                                5,                // # entries.\r
+                                                0,                // Revision.\r
+                                                0,                // Domain #.\r
+                                                0xFD,           // Coord Type- SW_ANY\r
+                                                MPEN          // # processors.\r
+                                        }\r
+                                })\r
+                }\r
+                Return(Package(){               // SW_ALL\r
+                        Package(){\r
+                                5,                        // # entries.\r
+                                0,                        // Revision.\r
+                                1,                        // Domain #.\r
+                                0xFC,                   // Coord Type- SW_ALL\r
+                                1               // # processors.\r
+                        }\r
+                })\r
+                }\r
+        }  // End of CPU1\r
+\r
+        Scope(\_PR.CPU2)\r
+        {\r
+                Name(_TPC, 0)   // All T-States are available\r
+\r
+                //\r
+                // T-State Control/Status interface\r
+                //\r
+                Method(_PTC, 0)\r
+                {\r
+                        Return(\_PR.CPU0._PTC)\r
+                }\r
+\r
+                Method(_TSS, 0)\r
+                {\r
+                        Return(\_PR.CPU0._TSS)\r
+                }\r
+\r
+                //\r
+                // T-State Dependency\r
+                //\r
+                Method(_TSD, 0)\r
+                {\r
+                        //\r
+                        // IF four cores are supported/enabled && !(direct access to MSR)\r
+                        //    Report 4 processors and SW_ANY as the coordination\r
+                        // IF two cores are supported/enabled && !(direct access to MSR)\r
+                        //    Report 2 processors and SW_ANY as the coordination type\r
+                        //  ELSE\r
+                        //    Report 1 processor and SW_ALL as the coordination type (domain 1)\r
+                        //\r
+                        //  CFGD[23] = Four cores enabled\r
+                        //  CFGD[24] = Two or more cores enabled\r
+                        //  PDCx[2] = OSPM is capable of direct access to On\r
+                        //              Demand throttling MSR\r
+                        //\r
+\r
+                If(LNot(And(PDC0,4)))\r
+                {\r
+                                Return(Package(){       // SW_ANY\r
+                                        Package(){\r
+                                                5,                // # entries.\r
+                                                0,                // Revision.\r
+                                                0,                // Domain #.\r
+                                                0xFD,           // Coord Type- SW_ANY\r
+                                                MPEN          // # processors.\r
+                                        }\r
+                                })\r
+                }\r
+                Return(Package(){               // SW_ALL\r
+                        Package(){\r
+                                5,                        // # entries.\r
+                                0,                        // Revision.\r
+                                1,                        // Domain #.\r
+                                0xFC,                   // Coord Type- SW_ALL\r
+                                1                // # processors.\r
+                        }\r
+                })\r
+                }\r
+        }  // End of CPU2\r
+\r
+        Scope(\_PR.CPU3)\r
+        {\r
+                Name(_TPC, 0)   // All T-States are available\r
+\r
+                //\r
+                // T-State Control/Status interface\r
+                //\r
+                Method(_PTC, 0)\r
+                {\r
+                        Return(\_PR.CPU0._PTC)\r
+                }\r
+\r
+                Method(_TSS, 0)\r
+                {\r
+                        Return(\_PR.CPU0._TSS)\r
+                }\r
+\r
+                //\r
+                // T-State Dependency\r
+                //\r
+                Method(_TSD, 0)\r
+                {\r
+                        //\r
+                        // IF four cores are supported/enabled && !(direct access to MSR)\r
+                        //    Report 4 processors and SW_ANY as the coordination\r
+                        // IF two cores are supported/enabled && !(direct access to MSR)\r
+                        //    Report 2 processors and SW_ANY as the coordination type\r
+                        //  ELSE\r
+                        //    Report 1 processor and SW_ALL as the coordination type (domain 1)\r
+                        //\r
+                        //  CFGD[23] = Four cores enabled\r
+                        //  CFGD[24] = Two or more cores enabled\r
+                        //  PDCx[2] = OSPM is capable of direct access to On\r
+                        //              Demand throttling MSR\r
+                        //\r
+\r
+                If(LNot(And(PDC0,4)))\r
+                {\r
+                                Return(Package(){       // SW_ANY\r
+                                        Package(){\r
+                                                5,                // # entries.\r
+                                                0,                // Revision.\r
+                                                0,                // Domain #.\r
+                                                0xFD,           // Coord Type- SW_ANY\r
+                                                MPEN          // # processors.\r
+                                        }\r
+                                })\r
+                }\r
+                Return(Package(){               // SW_ALL\r
+                        Package(){\r
+                                5,                        // # entries.\r
+                                0,                        // Revision.\r
+                                1,                        // Domain #.\r
+                                0xFC,                   // Coord Type- SW_ALL\r
+                                1                // # processors.\r
+                        }\r
+                })\r
+                }\r
+        }  // End of CPU3\r
+} // End of Definition Block\r
+\r

diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/PowerManagement/AcpiTables/Ssdt/Cpu0Cst.asl b/Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/PowerManagement/AcpiTables/Ssdt/Cpu0Cst.asl
new file mode 100644 (file)
index 0000000..1267d98
--- /dev/null
+++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/PowerManagement/AcpiTables/Ssdt/Cpu0Cst.asl
@@ -0,0 +1,280 @@
+\r
+/*-----------------------------------------------------------------------------\r
+-------------------------------------------------------------------------------\r
+\r
+\r
+ Intel Silvermont Processor Power Management BIOS Reference Code\r
+\r
+ Copyright (c) 2006 - 2014, Intel Corporation\r
+\r
+  This program and the accompanying materials are licensed and made available under\r
+  the terms and conditions of the BSD License that accompanies this distribution.\r
+  The full text of the license may be found at\r
+  http://opensource.org/licenses/bsd-license.php.\r
+\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+ Filename:    CPU0CST.ASL\r
+\r
+ Revision:    Refer to Readme\r
+\r
+ Date:        Refer to Readme\r
+\r
+--------------------------------------------------------------------------------\r
+-------------------------------------------------------------------------------\r
+\r
+ This Processor Power Management BIOS Source Code is furnished under license\r
+ and may only be used or copied in accordance with the terms of the license.\r
+ The information in this document is furnished for informational use only, is\r
+ subject to change without notice, and should not be construed as a commitment\r
+ by Intel Corporation. Intel Corporation assumes no responsibility or liability\r
+ for any errors or inaccuracies that may appear in this document or any\r
+ software that may be provided in association with this document.\r
+\r
+ Except as permitted by such license, no part of this document may be\r
+ reproduced, stored in a retrieval system, or transmitted in any form or by\r
+ any means without the express written consent of Intel Corporation.\r
+\r
+ WARNING: You are authorized and licensed to install and use this BIOS code\r
+ ONLY on an IST PC. This utility may damage any system that does not\r
+ meet these requirements.\r
+\r
+    An IST PC is a computer which\r
+    (1) Is capable of seamlessly and automatically transitioning among\r
+    multiple performance states (potentially operating at different\r
+    efficiency ratings) based upon power source changes, END user\r
+    preference, processor performance demand, and thermal conditions; and\r
+    (2) Includes an Intel Pentium II processors, Intel Pentium III\r
+    processor, Mobile Intel Pentium III Processor-M, Mobile Intel Pentium 4\r
+    Processor-M, Intel Pentium M Processor, or any other future Intel\r
+    processors that incorporates the capability to transition between\r
+    different performance states by altering some, or any combination of,\r
+    the following processor attributes: core voltage, core frequency, bus\r
+    frequency, number of processor cores available, or any other attribute\r
+    that changes the efficiency (instructions/unit time-power) at which the\r
+    processor operates.\r
+\r
+-------------------------------------------------------------------------------\r
+-------------------------------------------------------------------------------\r
+\r
+NOTES:\r
+    (1) <TODO> - IF the trap range and port definitions do not match those\r
+    specified by this reference code, this file must be modified IAW the\r
+    individual implmentation.\r
+\r
+--------------------------------------------------------------------------------\r
+------------------------------------------------------------------------------*/\r
+\r
+\r
+DefinitionBlock (\r
+    "CPU0CST.aml",\r
+    "SSDT",\r
+    1,\r
+    "PmRef",\r
+    "Cpu0Cst",\r
+    0x3001\r
+    )\r
+{\r
+    External(\_PR.CPU0, DeviceObj)\r
+    External(PWRS)\r
+    External(CFGD)\r
+    External(PDC0)\r
+\r
+    Scope(\_PR.CPU0)\r
+    {\r
+        OperationRegion (DEB0, SystemIO, 0x80, 1)    //DBG\r
+        Field (DEB0, ByteAcc,NoLock,Preserve)        //DBG\r
+        { DBG8, 8,}                    //DBG\r
+\r
+        Method (_CST, 0)\r
+        {\r
+            Store(0x60,DBG8) //DBG\r
+\r
+            // IF CMP is supported, but independent C-States beyond C1 are\r
+            // not supported; return C1 Halt and rely on BIOS based software\r
+            // coordination\r
+            //\r
+            //   CFGD[24] = CMP support\r
+            //   PDCx[4]  = 0 - OS does not support ind. C2/C3 in MP systems\r
+            //\r
+            // Note:  SMI will be generated when both processor enter the\r
+            // Halt state.\r
+            //\r
+            If(LAnd(And(CFGD,0x01000000), LNot(And(PDC0,0x10))))\r
+            {\r
+                Store(0x61,DBG8) //DBG\r
+                Return(Package() {\r
+                    1,\r
+                    Package()\r
+                    {   // C1 halt, but with BIOS coordination\r
+                        ResourceTemplate(){Register(FFixedHW, 0, 0, 0)},\r
+                        1,\r
+                        157,\r
+                        1000\r
+                    }\r
+                })\r
+            }\r
+\r
+            // IF MWAIT extensions are supported, use them.\r
+            //\r
+            //  IF C6 capable/enabled AND Battery\r
+            //        Report MWAIT C1, C2, C6 w/ BM_STS avoidance\r
+            //  ELSE IF C4 capable/enabled AND Battery\r
+            //        Report MWAIT C1, C2, C4 w/ BM_STS avoidance\r
+            //  ELSE IF C3 capable/enabled\r
+            //      Report MWAIT C1, C2, C3 w/ BM_STS avoidance\r
+            //  ELSE IF C2 capable/enabled\r
+            //        Report MWAIT C1, C2\r
+            //  ELSE\r
+            //        Report MWAIT C1\r
+            //\r
+            //   CFGD[21] = 1 - MWAIT extensions supported\r
+            //   CFGD[13] = 1 - C7  Capable/Enabled\r
+            //   CFGD[12] = 1 - C6S Capable/Enabled\r
+            //   CFGD[11] = 1 - C6  Capable/Enabled\r
+            //   CFGD[7]  = 1 - C4  Capable/Enabled\r
+            //   CFGD[5]  = 1 - C3  Capable/Enabled\r
+            //   PDCx[9]  = 1 - OS  supports MWAIT extensions\r
+            //   PDCx[8]  = 1 - OS  supports MWAIT for C1\r
+            //            (Inferred from PDCx[9] = 1.)\r
+            //   PDCx[4]  = 1 - OS supports independent C2/C3 in MP systems\r
+            //    or\r
+            //   NOT CMP  (Inferred from previous check.)\r
+            //\r
+            If(LAnd(And(CFGD, 0x200000), And(PDC0,0x200)))\r
+            {\r
+                //\r
+                // <TODO> The implementor may wish to only report C1-C2\r
+                // when on AC power.  In this case, the IF clause below can\r
+                // be modified to something like:\r
+                //\r
+                // "If(LAnd(And(CFGD,0x200), LNot(PWRS)))"\r
+                //\r
+                // Which uses the power state of the system (PWRS) to\r
+                // determine whether to allow deepers states.\r
+                //\r
+                //   IF C7 supported AND on battery\r
+                //    report MWAIT C1, C6, C7\r
+                //\r
+                //   CFGD[13] = C7  Capable/Enabled\r
+                //   CFGD[11] = C6  Capable/Enabled\r
+                //\r
+              If(LAnd(And(CFGD,0x2000),And(CFGD,0x40000000)))\r
+                {\r
+                    Store(0x77,DBG8) //DBG\r
+                    Return( Package()\r
+                    {\r
+                        3,\r
+                        Package()\r
+                        {   // C1, MWAIT\r
+                            ResourceTemplate(){Register(FFixedHW, 1, 2, 0x00, 1)},\r
+                            1,\r
+                            1,\r
+                            1000\r
+                        },\r
+                        Package()\r
+                        {\r
+                            // C6, MWAIT Extension with Incremental L2 Shrink\r
+                            // ResourceTemplate(){Register(FFixedHW, 1, 2, 0x50, 1)},\r
+                            // C6, MWAIT Extension with No L2 Shrink\r
+                            ResourceTemplate(){Register(FFixedHW, 1, 2, 0x51, 1)},\r
+                            2,\r
+                            500,\r
+                            10\r
+                        },\r
+                        Package()\r
+                        {\r
+                            // C7, MWAIT Extension with Full L2 Shrink\r
+                            ResourceTemplate(){Register(FFixedHW, 1, 2, 0x64, 1)},\r
+                            3,\r
+                            1500,   //PnP setting, 1.5 ms for worst-case exit latency\r
+                            10\r
+                        }\r
+                    })\r
+                }\r
+\r
+\r
+             If(LAnd(And(CFGD,0x2000),LNot(And(CFGD,0x40000000))))\r
+                {\r
+                    Store(0x67,DBG8) //DBG\r
+                    Return( Package()\r
+                    {\r
+                        3,\r
+                        Package()\r
+                        {   // C1, MWAIT\r
+                            ResourceTemplate(){Register(FFixedHW, 1, 2, 0x00, 1)},\r
+                            1,\r
+                            1,\r
+                            1000\r
+                        },\r
+                        Package()\r
+                        {\r
+                            // C6, MWAIT Extension with Incremental L2 Shrink\r
+                            // ResourceTemplate(){Register(FFixedHW, 1, 2, 0x50, 1)},\r
+                            // C6 = C6NS, MWAIT Extension with No L2 Shrink\r
+                            ResourceTemplate(){Register(FFixedHW, 1, 2, 0x51, 1)},\r
+                            2,\r
+                            500,\r
+                            10\r
+                        },\r
+                        Package()\r
+                        {\r
+\r
+                            ResourceTemplate(){Register(FFixedHW, 1, 2, 0x52, 1)},\r
+                            3,\r
+                            1500,   //PnP setting, 1.5 ms for worst-case exit latency\r
+                            10\r
+                        }\r
+                    })\r
+                }\r
+\r
+                If(And(CFGD,0x800)) // Setup Max C-State = C6\r
+                {\r
+                    Store(0x76,DBG8) //DBG\r
+                    Return( Package()\r
+                    {\r
+                        2,\r
+                        Package()\r
+                        {   // C1, MWAIT\r
+                            ResourceTemplate(){Register(FFixedHW, 1, 2, 0x00, 1)},\r
+                            1,\r
+                            1,\r
+                            1000\r
+                        },\r
+                        Package()\r
+                        {\r
+                            // C6, MWAIT Extension with Incremental L2 Shrink\r
+                            // ResourceTemplate(){Register(FFixedHW, 1, 2, 0x50, 1)},\r
+                            // C6, MWAIT Extension with No L2 Shrink\r
+                            ResourceTemplate(){Register(FFixedHW, 1, 2, 0x51, 1)},\r
+                            2,\r
+                            500,\r
+                            10\r
+                        }\r
+                    })\r
+                }\r
+                //\r
+                // IF no deeper C-States are supported; report MWAIT C1.\r
+                //\r
+                Store(0x71,DBG8) //DBG\r
+                Return(Package()\r
+                {\r
+                    1,\r
+                    Package()\r
+                    {   // C1, MWAIT\r
+                        ResourceTemplate () {Register(FFixedHW, 1, 2, 0x00, 1)},\r
+                        1,\r
+                        1,\r
+                        1000\r
+                    }\r
+                })\r
+            }\r
+\r
+\r
+        }\r
+    }\r
+}\r
+\r
+\r

diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/PowerManagement/AcpiTables/Ssdt/Cpu0Ist.asl b/Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/PowerManagement/AcpiTables/Ssdt/Cpu0Ist.asl
new file mode 100644 (file)
index 0000000..8bb4512
--- /dev/null
+++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/PowerManagement/AcpiTables/Ssdt/Cpu0Ist.asl
@@ -0,0 +1,266 @@
+/*-----------------------------------------------------------------------------\r
+-------------------------------------------------------------------------------\r
+\r
+\r
+ Intel Silvermont Processor Power Management BIOS Reference Code\r
+\r
+ Copyright (c) 2006 - 2014, Intel Corporation\r
+\r
+  This program and the accompanying materials are licensed and made available under\r
+  the terms and conditions of the BSD License that accompanies this distribution.\r
+  The full text of the license may be found at\r
+  http://opensource.org/licenses/bsd-license.php.\r
+\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+ Filename:    CPU0IST.ASL\r
+\r
+ Revision:    Refer to Readme\r
+\r
+ Date:        Refer to Readme\r
+\r
+--------------------------------------------------------------------------------\r
+-------------------------------------------------------------------------------\r
+\r
+ This Processor Power Management BIOS Source Code is furnished under license\r
+ and may only be used or copied in accordance with the terms of the license.\r
+ The information in this document is furnished for informational use only, is\r
+ subject to change without notice, and should not be construed as a commitment\r
+ by Intel Corporation. Intel Corporation assumes no responsibility or liability\r
+ for any errors or inaccuracies that may appear in this document or any\r
+ software that may be provided in association with this document.\r
+\r
+ Except as permitted by such license, no part of this document may be\r
+ reproduced, stored in a retrieval system, or transmitted in any form or by\r
+ any means without the express written consent of Intel Corporation.\r
+\r
+ WARNING: You are authorized and licensed to install and use this BIOS code\r
+ ONLY on an IST PC. This utility may damage any system that does not\r
+ meet these requirements.\r
+\r
+    An IST PC is a computer which\r
+    (1) Is capable of seamlessly and automatically transitioning among\r
+    multiple performance states (potentially operating at different\r
+    efficiency ratings) based upon power source changes, END user\r
+    preference, processor performance demand, and thermal conditions; and\r
+    (2) Includes an Intel Pentium II processors, Intel Pentium III\r
+    processor, Mobile Intel Pentium III Processor-M, Mobile Intel Pentium 4\r
+    Processor-M, Intel Pentium M Processor, or any other future Intel\r
+    processors that incorporates the capability to transition between\r
+    different performance states by altering some, or any combination of,\r
+    the following processor attributes: core voltage, core frequency, bus\r
+    frequency, number of processor cores available, or any other attribute\r
+    that changes the efficiency (instructions/unit time-power) at which the\r
+    processor operates.\r
+\r
+-------------------------------------------------------------------------------\r
+-------------------------------------------------------------------------------\r
+\r
+NOTES:\r
+    (1) <TODO> - IF the trap range and port definitions do not match those\r
+    specified by this reference code, this file must be modified IAW the\r
+    individual implmentation.\r
+\r
+--------------------------------------------------------------------------------\r
+------------------------------------------------------------------------------*/\r
+\r
+\r
+DefinitionBlock (\r
+    "CPU0IST.aml",\r
+    "SSDT",\r
+    0x01,\r
+    "PmRef",\r
+    "Cpu0Ist",\r
+    0x3000\r
+    )\r
+{\r
+    External (\_PR.CPU0, DeviceObj)\r
+    External (PDC0)\r
+    External (CFGD)\r
+\r
+    Scope(\_PR.CPU0)\r
+    {\r
+        //OperationRegion (DEB0, SystemIO, 0x80, 1)    //DBG\r
+        //Field (DEB0, ByteAcc,NoLock,Preserve)        //DBG\r
+        //{ DBG8, 8,}                                  //DBG\r
+\r
+        Name(_PPC, 0)        // Initialize as All States Available.\r
+\r
+        // NOTE:  For CMP systems; this table is not loaded unless\r
+        //      the required driver support is present.\r
+        //      So, we do not check for those cases here.\r
+        //\r
+        //   CFGD[0] = GV3 Capable/Enabled\r
+        //   PDCx[0]  = OS Capable of Hardware P-State control\r
+        //\r
+        Method(_PCT,0)\r
+        {\r
+            If(LAnd(And(CFGD,0x0001), And(PDC0,0x0001)))\r
+            {\r
+                //Store(0xA0,DBG8) //DBG\r
+                Return(Package()    // Native Mode\r
+                {\r
+                    ResourceTemplate(){Register(FfixedHW, 0, 0, 0)},\r
+                    ResourceTemplate(){Register(FfixedHW, 0, 0, 0)}\r
+                })\r
+            }\r
+            // @NOTE: IO Trap is not supported. Therefore should not expose any IO interface for _PCT\r
+            // For all other cases, report control through the\r
+            // SMI interface.  (The port used for SMM control is fixed up\r
+            // by the initialization code.)\r
+            //\r
+            Return(Package()        // SMM Mode\r
+            {\r
+               ResourceTemplate(){Register(FfixedHW, 0, 0, 0)},\r
+               ResourceTemplate(){Register(FfixedHW, 0, 0, 0)}\r
+            })\r
+        }\r
+\r
+\r
+        // NOTE:  For CMP systems; this table is not loaded if MP\r
+        //      driver support is not present or P-State are disabled.\r
+        //\r
+        Method(_PSS,0)\r
+        {\r
+            //\r
+            // Report NSPP if:\r
+            //   (1) GV3 capable (Not checked, see above.)\r
+            //   (2) Driver support direct hardware control\r
+            //   (3) MP driver support present (Not checked, see above.)\r
+            // else;\r
+            //   Report SPSS\r
+            //\r
+            //   PDCx[0]  = OS Capable of Hardware P-State control\r
+            //\r
+            If(And(PDC0,0x0001)){\r
+                //Store(0xB0,DBG8) //DBG\r
+                Return(NPSS)\r
+            }\r
+            //Store(0xBF,DBG8) //DBG\r
+            // Otherwise, report SMM mode\r
+            //\r
+            Return(SPSS)\r
+\r
+        }\r
+\r
+        Name(SPSS,Package()\r
+        {\r
+            Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r
+            Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r
+            Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r
+            Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r
+            Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r
+            Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r
+            Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r
+            Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r
+            Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r
+            Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r
+            Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r
+            Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r
+            Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r
+            Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r
+            Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r
+            Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000}\r
+        })\r
+\r
+        Name(NPSS,Package()\r
+        {\r
+            Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r
+            Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r
+            Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r
+            Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r
+            Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r
+            Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r
+            Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r
+            Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r
+            Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r
+            Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r
+            Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r
+            Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r
+            Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r
+            Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r
+            Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r
+            Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000}\r
+        })\r
+\r
+        // The _PSD object provides information to the OSPM related\r
+        // to P-State coordination between processors in a multi-processor\r
+        // configurations.\r
+        //\r
+        Method(_PSD,0)\r
+        {\r
+            //\r
+            // IF CMP is supported/enabled\r
+            //   IF quad core processor\r
+            //     IF PDC[11]\r
+            //         Report 4 processors and HW_ALL as the coordination type\r
+            //     ELSE\r
+            //         Report 4 processors and SW_ALL as the coordination type\r
+            //   ELSE\r
+            //     IF PDC[11]\r
+            //         Report 2 processors and HW_ALL as the coordination type\r
+            //     ELSE\r
+            //         Report 2 processors and SW_ALL as the coordination type\r
+            // ELSE\r
+            //    Report 1 processor and SW_ALL as the coordination type\r
+            //    (Domain 0)\r
+            //\r
+            //   CFGD[24] = Two or more cores enabled\r
+            //   CFGD[23] = Four cores enabled\r
+            //   PDCx[11] = Hardware coordination with hardware feedback\r
+            //\r
+\r
+            If(And(CFGD,0x1000000))    // CMP Enabled.\r
+            {\r
+              If(And(CFGD,0x800000))    // 2 or 4 process.\r
+                {\r
+                  If(And(PDC0,0x0800))\r
+                  {\r
+                      Return(Package(){    // HW_ALL\r
+                        Package(){\r
+                            5,              // # entries.\r
+                            0,              // Revision.\r
+                            0,              // Domain #.\r
+                            0xFE,           // Coord Type- HW_ALL.\r
+                            4               // # processors.\r
+                        }\r
+                      })\r
+                  } // If(And(PDC0,0x0800))\r
+                   Return(Package(){        // SW_ALL\r
+                     Package(){\r
+                        5,                  // # entries.\r
+                        0,                  // Revision.\r
+                        0,                  // Domain #.\r
+                        0xFC,               // Coord Type- SW_ALL.\r
+                        4                   // # processors.\r
+                     }\r
+                    })\r
+                } else {\r
+                  Return(Package(){        // HW_ALL\r
+                      Package(){\r
+                          5,                  // # entries.\r
+                          0,                  // Revision.\r
+                          0,                  // Domain #.\r
+                          0xFE,               // Coord Type- HW_ALL.\r
+                          2                   // # processors.\r
+                      }\r
+                  })\r
+                }\r
+            }    // If(And(CFGD,0x1000000))    // CMP Enabled.\r
+\r
+            Return(Package(){              // SW_ALL\r
+                Package(){\r
+                    5,                        // # entries.\r
+                    0,                        // Revision.\r
+                    0,                        // Domain #.\r
+                    0xFC,                     // Coord Type- SW_ALL.\r
+                    1                         // # processors.\r
+                }\r
+            })\r
+        } // Method(_PSD,0)\r
+    } // Scope(\_PR.CPU0)\r
+} // End of Definition Block\r
+\r
+\r

diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/PowerManagement/AcpiTables/Ssdt/Cpu0Tst.asl b/Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/PowerManagement/AcpiTables/Ssdt/Cpu0Tst.asl
new file mode 100644 (file)
index 0000000..e535c93
--- /dev/null
+++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/PowerManagement/AcpiTables/Ssdt/Cpu0Tst.asl
@@ -0,0 +1,241 @@
+/*-----------------------------------------------------------------------------\r
+-------------------------------------------------------------------------------\r
+\r
+\r
+ Intel Silvermont Processor Power Management BIOS Reference Code\r
+\r
+ Copyright (c) 2006 - 2014, Intel Corporation\r
+\r
+  This program and the accompanying materials are licensed and made available under\r
+  the terms and conditions of the BSD License that accompanies this distribution.\r
+  The full text of the license may be found at\r
+  http://opensource.org/licenses/bsd-license.php.\r
+\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+ Filename:      CPU0TST.ASL\r
+\r
+ Revision:      Refer to Readme\r
+\r
+ Date:          Refer to Readme\r
+\r
+--------------------------------------------------------------------------------\r
+-------------------------------------------------------------------------------\r
+\r
+ This Processor Power Management BIOS Source Code is furnished under license\r
+ and may only be used or copied in accordance with the terms of the license.\r
+ The information in this document is furnished for informational use only, is\r
+ subject to change without notice, and should not be construed as a commitment\r
+ by Intel Corporation. Intel Corporation assumes no responsibility or liability\r
+ for any errors or inaccuracies that may appear in this document or any\r
+ software that may be provided in association with this document.\r
+\r
+ Except as permitted by such license, no part of this document may be\r
+ reproduced, stored in a retrieval system, or transmitted in any form or by\r
+ any means without the express written consent of Intel Corporation.\r
+\r
+ WARNING: You are authorized and licensed to install and use this BIOS code\r
+ ONLY on an IST PC. This utility may damage any system that does not\r
+ meet these requirements.\r
+\r
+        An IST PC is a computer which\r
+        (1) Is capable of seamlessly and automatically transitioning among\r
+        multiple performance states (potentially operating at different\r
+        efficiency ratings) based upon power source changes, end user\r
+        preference, processor performance demand, and thermal conditions; and\r
+        (2) Includes an Intel Pentium II processors, Intel Pentium III\r
+        processor, Mobile Intel Pentium III Processor-M, Mobile Intel Pentium 4\r
+        Processor-M, Intel Pentium M Processor, or any other future Intel\r
+        processors that incorporates the capability to transition between\r
+        different performance states by altering some, or any combination of,\r
+        the following processor attributes: core voltage, core frequency, bus\r
+        frequency, number of processor cores available, or any other attribute\r
+        that changes the efficiency (instructions/unit time-power) at which the\r
+        processor operates.\r
+\r
+-------------------------------------------------------------------------------\r
+-------------------------------------------------------------------------------\r
+\r
+NOTES:\r
+        (1) <TODO> - IF the trap range and port definitions do not match those\r
+        specified by this reference code, this file must be modified IAW the\r
+        individual implmentation.\r
+\r
+--------------------------------------------------------------------------------\r
+------------------------------------------------------------------------------*/\r
+\r
+DefinitionBlock(\r
+        "CPU0TST.aml",\r
+        "SSDT",\r
+        0x01,\r
+        "PmRef",\r
+        "Cpu0Tst",\r
+        0x3000\r
+        )\r
+{\r
+        External(\_PR.CPU0, DeviceObj)\r
+        External(PDC0)\r
+        External(CFGD)\r
+        External(_PSS)\r
+\r
+        Scope(\_PR.CPU0)\r
+        {\r
+                Name(_TPC, 0)   // All T-States are available\r
+\r
+                //\r
+                // T-State Control/Status interface\r
+                //\r
+                Method(_PTC, 0)\r
+                {\r
+                        //\r
+                        // IF OSPM is capable of direct access to MSR\r
+                        //    Report MSR interface\r
+                        // ELSE\r
+                        //    Report I/O interface\r
+                        //\r
+                        //  PDCx[2] = OSPM is capable of direct access to On\r
+                        //              Demand throttling MSR\r
+                        //\r
+                        If(And(PDC0, 0x0004)) {\r
+                                Return(Package() {\r
+                                        ResourceTemplate(){Register(FFixedHW, 0, 0, 0)},\r
+                                        ResourceTemplate(){Register(FFixedHW, 0, 0, 0)}\r
+                                })\r
+                        }\r
+\r
+                }\r
+\r
+                // _TSS package for I/O port based T-State control\r
+                // "Power" fields are replaced with real values by the first\r
+                // call of _TSS method.\r
+                //\r
+                Name(TSSI, Package() {\r
+                                Package(){100, 1000, 0, 0x00, 0},\r
+                                Package(){ 88,  875, 0, 0x0F, 0},\r
+                                Package(){ 75,  750, 0, 0x0E, 0},\r
+                                Package(){ 63,  625, 0, 0x0D, 0},\r
+                                Package(){ 50,  500, 0, 0x0C, 0},\r
+                                Package(){ 38,  375, 0, 0x0B, 0},\r
+                                Package(){ 25,  250, 0, 0x0A, 0},\r
+                                Package(){ 13,  125, 0, 0x09, 0}\r
+                })\r
+\r
+                // _TSS package for MSR based T-State control\r
+                // "Power" fields are replaced with real values by the first\r
+                // call of _TSS method.\r
+                //\r
+                Name(TSSM, Package() {\r
+                                Package(){100, 1000, 0, 0x00, 0},\r
+                                Package(){ 88,  875, 0, 0x1E, 0},\r
+                                Package(){ 75,  750, 0, 0x1C, 0},\r
+                                Package(){ 63,  625, 0, 0x1A, 0},\r
+                                Package(){ 50,  500, 0, 0x18, 0},\r
+                                Package(){ 38,  375, 0, 0x16, 0},\r
+                                Package(){ 25,  250, 0, 0x14, 0},\r
+                                Package(){ 13,  125, 0, 0x12, 0}\r
+                })\r
+\r
+                Name(TSSF, 0)   // Flag for TSSI/TSSM initialization\r
+\r
+                Method(_TSS, 0)\r
+                {\r
+                        // Update "Power" fields of TSSI/TSSM with the LFM\r
+                        // power data IF _PSS is available\r
+                        //\r
+                        IF (LAnd(LNot(TSSF),CondRefOf(_PSS)))\r
+                        {\r
+                                Store(_PSS, Local0)\r
+                                Store(SizeOf(Local0), Local1)   // _PSS size\r
+                                Decrement(Local1)               // Index of LFM\r
+                                Store(DerefOf(Index(DerefOf(Index(Local0,Local1)),1)), Local2)  // LFM Power\r
+\r
+                                Store(0, Local3)\r
+                                While(LLess(Local3, SizeOf(TSSI)))\r
+                                {\r
+                                        Store(Divide(Multiply(Local2, Subtract(8, Local3)), 8),\r
+                                              Local4)           // Power for this TSSI/TSSM entry\r
+                                        Store(Local4,Index(DerefOf(Index(TSSI,Local3)),1))\r
+                                        Store(Local4,Index(DerefOf(Index(TSSM,Local3)),1))\r
+                                        Increment(Local3)\r
+                                }\r
+                                Store(Ones, TSSF)               // TSSI/TSSM are updated\r
+                        }\r
+                        //\r
+                        // IF OSPM is capable of direct access to MSR\r
+                        //    Report TSSM\r
+                        // ELSE\r
+                        //    Report TSSI\r
+                        //\r
+                        If(And(PDC0, 0x0004))\r
+                        {\r
+                                Return(TSSM)\r
+                        }\r
+                        Return(TSSI)\r
+                }\r
+\r
+              Method(_TDL, 0)\r
+              {\r
+                Store ("Cpu0: _TDL Called", Debug)\r
+                Name ( LFMI, 0)\r
+                Store (SizeOf(TSSM), LFMI)\r
+                Decrement(LFMI)    // Index of LFM entry in TSSM\r
+                Return(LFMI)\r
+              }\r
+\r
+                //\r
+                // T-State Dependency\r
+                //\r
+                Method(_TSD, 0)\r
+                {\r
+                        //\r
+      // IF four cores are supported/enabled && !(direct access to MSR)\r
+                        //    Report 4 processors and SW_ANY as the coordination type\r
+      // ELSE IF two cores are supported/enabled && !(direct access to MSR)\r
+                        //    Report 2 processors and SW_ANY as the coordination type\r
+                        // ELSE\r
+                        //   Report 1 processor and SW_ALL as the coordination type\r
+                        //\r
+                        //  CFGD[23] = Four cores enabled\r
+                        //  CFGD[24] = Two or more cores enabled\r
+                        //  PDCx[2] = OSPM is capable of direct access to On\r
+                        //              Demand throttling MSR\r
+                        //\r
+                        If(LAnd(And(CFGD,0x0800000),LNot(And(PDC0,4))))\r
+                        {\r
+                                Return(Package(){       // SW_ANY\r
+                                        Package(){\r
+                                                5,                // # entries.\r
+                                                0,                // Revision.\r
+                                                0,                // Domain #.\r
+                                                0xFD,           // Coord Type- SW_ANY\r
+                                                4                   // # processors.\r
+                                        }\r
+                                })\r
+                        }\r
+                        If(LAnd(And(CFGD,0x1000000),LNot(And(PDC0,4))))\r
+                        {\r
+                                Return(Package(){       // SW_ANY\r
+                                        Package(){\r
+                                                5,                // # entries.\r
+                                                0,                // Revision.\r
+                                                0,                // Domain #.\r
+                                                0xFD,           // Coord Type- SW_ANY\r
+                                                2                   // # processors.\r
+                                        }\r
+                                })\r
+                        }\r
+                        Return(Package(){               // SW_ALL\r
+                                Package(){\r
+                                        5,                        // # entries.\r
+                                        0,                        // Revision.\r
+                                        0,                        // Domain #.\r
+                                        0xFC,                   // Coord Type- SW_ALL\r
+                                        1                           // # processors.\r
+                                }\r
+                        })\r
+                }\r
+        }\r
+} // End of Definition Block\r
+\r

diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/PowerManagement/AcpiTables/Ssdt/CpuPm.asl b/Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/PowerManagement/AcpiTables/Ssdt/CpuPm.asl
new file mode 100644 (file)
index 0000000..32cdcd3
--- /dev/null
+++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/PowerManagement/AcpiTables/Ssdt/CpuPm.asl
@@ -0,0 +1,799 @@
+/*-----------------------------------------------------------------------------\r
+\r
+\r
+ Intel Silvermont Processor Power Management BIOS Reference Code\r
+\r
+ Copyright (c) 2006 - 2014, Intel Corporation\r
+\r
+  This program and the accompanying materials are licensed and made available under\r
+  the terms and conditions of the BSD License that accompanies this distribution.\r
+  The full text of the license may be found at\r
+  http://opensource.org/licenses/bsd-license.php.\r
+\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+ Filename:    CPUPM.ASL\r
+\r
+ Revision:    Refer to Readme\r
+\r
+ Date:        Refer to Readme\r
+-------------------------------------------------------------------------------\r
+\r
+ This Processor Power Management BIOS Source Code is furnished under license\r
+ and may only be used or copied in accordance with the terms of the license.\r
+ The information in this document is furnished for informational use only, is\r
+ subject to change without notice, and should not be construed as a commitment\r
+ by Intel Corporation. Intel Corporation assumes no responsibility or liability\r
+ for any errors or inaccuracies that may appear in this document or any\r
+ software that may be provided in association with this document.\r
+\r
+ Except as permitted by such license, no part of this document may be\r
+ reproduced, stored in a retrieval system, or transmitted in any form or by\r
+ any means without the express written consent of Intel Corporation.\r
+\r
+ WARNING: You are authorized and licensed to install and use this BIOS code\r
+ ONLY on an IST PC. This utility may damage any system that does not\r
+ meet these requirements.\r
+\r
+    An IST PC is a computer which\r
+    (1) Is capable of seamlessly and automatically transitioning among\r
+    multiple performance states (potentially operating at different\r
+    efficiency ratings) based upon power source changes, END user\r
+    preference, processor performance demand, and thermal conditions; and\r
+    (2) Includes an Intel Pentium II processors, Intel Pentium III\r
+    processor, Mobile Intel Pentium III Processor-M, Mobile Intel Pentium 4\r
+    Processor-M, Intel Pentium M Processor, or any other future Intel\r
+    processors that incorporates the capability to transition between\r
+    different performance states by altering some, or any combination of,\r
+    the following processor attributes: core voltage, core frequency, bus\r
+    frequency, number of processor cores available, or any other attribute\r
+    that changes the efficiency (instructions/unit time-power) at which the\r
+    processor operates.\r
+-------------------------------------------------------------------------------\r
+\r
+NOTES:\r
+    (1) <TODO> - Except for the SSDT package, the objects in this ASL code\r
+    may be moved to the DSDT. It is kept separate in this reference package\r
+    for ease of distribution only.\r
+------------------------------------------------------------------------------*/\r
+\r
+DefinitionBlock (\r
+    "CPUPM.aml",\r
+    "SSDT",\r
+    0x01,\r
+    "PmRef",\r
+    "CpuPm",\r
+    0x3000\r
+    )\r
+{\r
+    External(\_PR.CPU0, DeviceObj)\r
+    External(\_PR.CPU1, DeviceObj)\r
+    External(\_PR.CPU2, DeviceObj)\r
+    External(\_PR.CPU3, DeviceObj)\r
+    External(SMIF)\r
+\r
+  Scope(\)\r
+  {\r
+\r
+      // Package of pointers to SSDT's\r
+      //\r
+      // First column is SSDT name, used for debug only.\r
+      // (First column must be EXACTLY eight characters.)\r
+      // Second column is physical address.\r
+      // Third column is table length.\r
+      //\r
+      // IF modifying this file, see warnings listed in ppminit.asm.\r
+      //\r
+      Name(SSDT,Package()\r
+      {\r
+          "CPU0IST ", 0x80000000, 0x80000000,\r
+          "APIST   ", 0x80000000, 0x80000000,\r
+          "CPU0CST ", 0x80000000, 0x80000000,\r
+          "APCST   ", 0x80000000, 0x80000000\r
+      })\r
+\r
+      //\r
+      // Note:  See PpmBiosInit in PPMINIT.ASM for a definition of\r
+      // the PpmFlags mirrored in CFGD.\r
+      //\r
+      Name(CFGD, 0x80000000)\r
+\r
+      Name(\PDC0,0x80000000)    // CPU0 _PDC Flags.\r
+      Name(\PDC1,0x80000000)    // CPU1 _PDC Flags.\r
+      Name(\PDC2,0x80000000)    // CPU2 _PDC Flags.\r
+      Name(\PDC3,0x80000000)    // CPU3 _PDC Flags.\r
+      Name(\SDTL,0x00)          // Loaded SSDT Flags.\r
+  }\r
+\r
+  Scope(\_PR.CPU0)\r
+  {\r
+      //\r
+      // Define handles for opregions (used by load.)\r
+      //\r
+      Name(HI0,0)        // Handle to CPU0IST\r
+      Name(HC0,0)        // Handle to CPU0CST\r
+\r
+      Method(_PDC,1)\r
+      {\r
+          //\r
+          // Check and extract the _PDC information.\r
+          //\r
+          Store(CPDC(Arg0), Local0)\r
+          //\r
+          // Save the capability information and load tables as needed.\r
+          //\r
+          GCAP(Local0)\r
+          //\r
+          // Return status.\r
+          //\r
+          //Return (Local0)\r
+      }\r
+\r
+      Method(_OSC, 4)\r
+      {\r
+          //\r
+          // Check and extract the _OSC information.\r
+          //\r
+          Store(COSC(Arg0, Arg1, Arg2, Arg3), Local0)\r
+          //\r
+          // Save the capability information and load tables as needed.\r
+          //\r
+          GCAP(Local0)\r
+          //\r
+          // Return status.\r
+          //\r
+          Return (Local0)\r
+      }\r
+\r
+      //\r
+      // Implement a generic Method to check _PDC information which may be called\r
+      // by any of the processor scopes.  (The use of _PDC is deprecated in ACPI 3.\r
+      // in favor of _OSC. However, for backwards compatibility, _PDC may be\r
+      // implemented using _OSC as follows:)\r
+      //\r
+      Method(CPDC,1)\r
+      {\r
+          CreateDwordField (Arg0, 0, REVS)\r
+          CreateDwordField (Arg0, 4, SIZE)\r
+\r
+          //\r
+          // Local0 = Number of bytes for Arg0\r
+          //\r
+          Store (SizeOf (Arg0), Local0)\r
+\r
+          //\r
+          // Local1 = Number of Capabilities bytes in Arg0\r
+          //\r
+          Store (Subtract (Local0, 8), Local1)\r
+\r
+          //\r
+          // TEMP = Temporary field holding Capability DWORDs\r
+          //\r
+          CreateField (Arg0, 64, Multiply (Local1, 8), TEMP)\r
+\r
+          //\r
+          // Create the Status (STAT) buffer with the first DWORD = 0\r
+          // This is required as per ACPI 3.0 Spec which says the\r
+          // first DWORD is used to return errors defined by _OSC.\r
+          //\r
+          Name (STS0, Buffer () {0x00, 0x00, 0x00, 0x00})\r
+\r
+          //\r
+          // Concatenate the _PDC capabilities bytes to the STS0 Buffer\r
+          // and store them in a local variable for calling OSC\r
+          //\r
+          Concatenate (STS0, TEMP, Local2)\r
+\r
+          Return(COSC (ToUUID("4077A616-290C-47BE-9EBD-D87058713953"), REVS, SIZE, Local2))\r
+      }\r
+\r
+      //\r
+      // Implement a generic Method to check _OSC information which may be called\r
+      // by any of the processor scopes.\r
+      //\r
+      Method(COSC, 4)\r
+      {\r
+          //\r
+          // Point to Status DWORD in the Arg3 buffer (STATUS)\r
+          //\r
+          CreateDWordField(Arg3, 0, STS0)\r
+          //\r
+          // Point to Caps DWORDs of the Arg3 buffer (CAPABILITIES)\r
+          //\r
+          CreateDwordField(Arg3, 4, CAP0)\r
+\r
+          //\r
+          // _OSC needs to validate the UUID and Revision.\r
+          //\r
+          // IF Unrecognized UUID\r
+          //    Return Unrecognized UUID _OSC Failure\r
+          // IF Unsupported Revision\r
+          //    Return Unsupported Revision _OSC Failure\r
+          //\r
+          //    STS0[0] = Reserved\r
+          //    STS0[1] = _OSC Failure\r
+          //    STS0[2] = Unrecognized UUID\r
+          //    STS0[3] = Unsupported Revision\r
+          //    STS0[4] = Capabilities masked\r
+          //\r
+          // Note:  The comparison method used is necessary due to\r
+          // limitations of certain OSes which cannot perform direct\r
+          // buffer comparisons.\r
+          //\r
+          // Create a set of "Input" UUID fields.\r
+          //\r
+          CreateDwordField(Arg0, 0x0, IID0)\r
+          CreateDwordField(Arg0, 0x4, IID1)\r
+          CreateDwordField(Arg0, 0x8, IID2)\r
+          CreateDwordField(Arg0, 0xC, IID3)\r
+          //\r
+          // Create a set of "Expected" UUID fields.\r
+          //\r
+          Name(UID0, ToUUID("4077A616-290C-47BE-9EBD-D87058713953"))\r
+          CreateDwordField(UID0, 0x0, EID0)\r
+          CreateDwordField(UID0, 0x4, EID1)\r
+          CreateDwordField(UID0, 0x8, EID2)\r
+          CreateDwordField(UID0, 0xC, EID3)\r
+          //\r
+          // Verify the input UUID matches the expected UUID.\r
+          //\r
+          If(LNot(LAnd(LAnd(LEqual(IID0, EID0),LEqual(IID1, EID1)),LAnd(LEqual(IID2, EID2),LEqual(IID3, EID3)))))\r
+          {\r
+              //\r
+              // Return Unrecognized UUID _OSC Failure\r
+              //\r
+              Store (0x6, STS0)\r
+              Return (Arg3)\r
+          }\r
+\r
+          If(LNot(LEqual(Arg1,1)))\r
+          {\r
+              //\r
+              // Return Unsupported Revision _OSC Failure\r
+              //\r
+              Store (0xA, STS0)\r
+              Return (Arg3)\r
+          }\r
+\r
+          Return (Arg3)\r
+      }\r
+\r
+      //\r
+      // Get the capability information and load appropriate tables as needed.\r
+      //\r
+      Method(GCAP, 1)\r
+      {\r
+\r
+          // Point to Status DWORD in the Arg0 buffer (STATUS)\r
+          CreateDWordField(Arg0, 0, STS0)\r
+\r
+          // Point to Caps DWORDs of the Arg0 buffer (CAPABILITIES)\r
+          CreateDwordField(Arg0, 4, CAP0)\r
+\r
+          //\r
+          // If the UUID was unrecognized or the _OSC revision was unsupported,\r
+          // return without updating capabilities.\r
+          //\r
+          If(LOr(LEqual(STS0,0x6),LEqual(STS0,0xA)))\r
+          {\r
+              Return()\r
+          }\r
+\r
+          //\r
+          // Check if this is a query (BIT0 of Status = 1).\r
+          // If so, mask off the bits we support and return.\r
+          //\r
+          if (And(STS0, 1))\r
+          {\r
+              And(CAP0, 0xBFF, CAP0)\r
+              Return()\r
+          }\r
+\r
+          //\r
+          // Store result of PDC. (We clear out the MSB, which was just\r
+          // used as a placeholder for the compiler; and then "OR" the\r
+          // value in case we get multiple calls, each of which only\r
+          // reports partial support.)\r
+          //\r
+          Or(And(PDC0, 0x7FFFFFFF), CAP0, PDC0)\r
+\r
+          //\r
+          // Check IF the IST SSDTs should be loaded.\r
+          //\r
+          //   CFGD[0] = GV3 Capable/Enabled\r
+          //\r
+          If(And(CFGD,0x01))\r
+          {\r
+              //\r
+              // Load the IST SSDTs if:\r
+              //   (1) CMP capable and enabled.\r
+              //   (2) Driver supports P-States in MP configurations\r
+              //   (3) Driver supports direct HW P-State control\r
+              //   (4) SSDT is not already loaded\r
+              //\r
+              //   CFGD[24] = Two or more cores enabled\r
+              //   PDCx[3]  = OS supports C1 and P-states in MP systems\r
+              //   PDCx[0]  = OS supports direct access of the perf MSR\r
+              //   SDTL[0]  = CPU0 IST SSDT Loaded\r
+              //\r
+              If(LAnd(LAnd(And(CFGD,0x01000000),LEqual(And(PDC0, 0x0009), 0x0009)),LNot(And(SDTL,0x01))))\r
+              {\r
+                  //\r
+                  // Flag the IST SSDT as loaded for CPU0\r
+                  //\r
+                  Or(SDTL, 0x01, SDTL)\r
+\r
+                  OperationRegion(IST0,SystemMemory,DeRefOf(Index(SSDT,1)),DeRefOf(Index(SSDT,2)))\r
+                  Load(IST0, HI0)    // Dynamically load the CPU0IST SSDT\r
+              }\r
+          }\r
+\r
+          //\r
+          // Check IF the CST SSDTs should be loaded.\r
+          //\r
+          //   CFGD[11,7,2,1] = C6, C4, C1E, C1 Capable/Enabled\r
+          //\r
+          If(And(CFGD,0x82))\r
+          {\r
+              //\r
+              // Load the CST SSDTs if:\r
+              //   (1) CMP capable/enabled\r
+              //   (2) Driver supports multi-processor configurations\r
+              //   (3) CPU0 CST ISDT is not already loaded\r
+              //\r
+              //   CFGD[24] = Two or more cores enabled\r
+              //   PDCx[3]  = OS supports C1 and P-states in MP systems\r
+              //   PDCx[4]  = OS supports ind. C2/C3 in MP systems\r
+              //   SDTL[1]  = CPU0 CST SSDT Loaded\r
+              //\r
+              If(LAnd(LAnd(And(CFGD,0x01000000),And(PDC0,0x0018)),LNot(And(SDTL,0x02))))\r
+              {\r
+                  //\r
+                  // Flag the CST SSDT as loaded for CPU0\r
+                  //\r
+                  Or(SDTL, 0x02, SDTL)\r
+\r
+                  OperationRegion(CST0,SystemMemory,DeRefOf(Index(SSDT,7)),DeRefOf(Index(SSDT,8)))\r
+                  Load(CST0, HC0)    // Dynamically load the CPU0CST SSDT\r
+              }\r
+          }\r
+\r
+          Return ()\r
+      }\r
+  }\r
+\r
+\r
+  Scope(\_PR.CPU1)\r
+  {\r
+      //\r
+      // Define handles for opregions (used by load.)\r
+      //\r
+      Name(HI1,0)        // Handle to APIST\r
+      Name(HC1,0)        // Handle to APCST\r
+\r
+      Method(_PDC,1)\r
+      {\r
+          //\r
+          // Refer to \_PR.CPU0._PDC for description.\r
+          //\r
+          Store(\_PR.CPU0.CPDC(Arg0), Local0)\r
+          GCAP(Local0)\r
+          //Return (Local0)\r
+      }\r
+\r
+      Method(_OSC, 4)\r
+      {\r
+          //\r
+          // Refer to \_PR.CPU0._OSC for description.\r
+          //\r
+          Store(\_PR.CPU0.COSC(Arg0, Arg1, Arg2, Arg3), Local0)\r
+          GCAP(Local0)\r
+          Return (Local0)\r
+      }\r
+\r
+      //\r
+      // Get the capability information and load appropriate tables as needed.\r
+      //\r
+      Method(GCAP, 1)\r
+      {\r
+          //\r
+          // Point to Status DWORD in the Arg0 buffer (STATUS)\r
+          //\r
+          CreateDWordField(Arg0, 0, STS1)\r
+          //\r
+          // Point to Caps DWORDs of the Arg0 buffer (CAPABILITIES)\r
+          //\r
+          CreateDwordField(Arg0, 4, CAP1)\r
+          //\r
+          // If the UUID was unrecognized or the _OSC revision was unsupported,\r
+          // return without updating capabilities.\r
+          //\r
+          If(LOr(LEqual(STS1,0x6),LEqual(STS1,0xA)))\r
+          {\r
+              Return()\r
+          }\r
+\r
+          //\r
+          // Check if this is a query (BIT0 of Status = 1).\r
+          // If so, mask off the bits we support and return.\r
+          //\r
+          if (And(STS1, 1))\r
+          {\r
+              And(CAP1, 0xBFF, CAP1)\r
+              Return()\r
+          }\r
+\r
+          //\r
+          // Store result of PDC. (We clear out the MSB, which was just\r
+          // used as a placeholder for the compiler; and then "OR" the\r
+          // value in case we get multiple calls, each of which only\r
+          // reports partial support.)\r
+          //\r
+          Or(And(PDC1, 0x7FFFFFFF), CAP1, PDC1)\r
+\r
+          //\r
+          // Attempt to dynamically load the IST SSDTs if:\r
+          //   (1) Driver supports P-States in MP configurations\r
+          //   (2) Driver supports direct HW P-State control\r
+          //\r
+          //   PDCx[3]  = OS supports C1 and P-states in MP systems\r
+          //   PDCx[0]  = OS supports direct access of the perf MSR\r
+          //\r
+          If(LEqual(And(PDC0, 0x0009), 0x0009))\r
+          {\r
+              APPT()\r
+          }\r
+\r
+          //\r
+          // Load the CST SSDTs if:\r
+          //   (1) Driver supports multi-processor configurations\r
+          //\r
+          //   PDCx[3]  = OS supports C1 and P-states in MP systems\r
+          //   PDCx[4]  = OS supports ind. C2/C3 in MP systems\r
+          //\r
+          If(And(PDC0,0x0018))\r
+          {\r
+              APCT()\r
+          }\r
+\r
+          Return()\r
+      }\r
+\r
+      //\r
+      // Dynamically load the CST SSDTs if:\r
+      //   (1) C-States are enabled\r
+      //   (2) SSDT is not already loaded\r
+      //\r
+      //   CFGD[11,7,2,1] = C6, C4, C1E, C1 Capable/Enabled\r
+      //   SDTL[5]   = AP CST SSDT Loaded\r
+      //\r
+      Method(APCT,0)\r
+      {\r
+          If(LAnd(And(CFGD,0x82),LNot(And(SDTL,0x20))))\r
+          {\r
+              //\r
+              // Flag the CST SSDT as loaded for the AP's\r
+              //\r
+              Or(SDTL, 0x20, SDTL)\r
+              //\r
+              // Dynamically load the APCST SSDT\r
+              //\r
+              OperationRegion(CST1,SystemMemory,DeRefOf(Index(SSDT,10)),DeRefOf(Index(SSDT,11)))\r
+              Load(CST1, HC1)\r
+          }\r
+      }\r
+\r
+      //\r
+      // Dynamically load the IST SSDTs if:\r
+      //   (1) If GV3 capable and enabled\r
+      //   (2) SSDT is not already loaded\r
+      //\r
+      //   CFGD[0] = GV3 Capable/Enabled\r
+      //   SDTL[4] = AP IST SSDT Loaded\r
+      //\r
+      Method(APPT,0)\r
+      {\r
+          If(LAnd(And(CFGD,0x01),LNot(And(SDTL,0x10))))\r
+          {\r
+              //\r
+              // Flag the IST SSDT as loaded for CPU0\r
+              //\r
+              Or(SDTL, 0x10, SDTL)\r
+\r
+              OperationRegion(IST1,SystemMemory,DeRefOf(Index(SSDT,4)),DeRefOf(Index(SSDT,5)))\r
+              Load(IST1, HI1)    // Dynamically load the CPU1IST SSDT\r
+          }\r
+      }\r
+  }    // End CPU1\r
+\r
+  Scope(\_PR.CPU2)\r
+  {\r
+      //\r
+      // Define handles for opregions (used by load.)\r
+      //\r
+      Name(HI1,0)        // Handle to APIST\r
+      Name(HC1,0)        // Handle to APCST\r
+\r
+      Method(_PDC,1)\r
+      {\r
+          //\r
+          // Refer to \_PR.CPU0._PDC for description.\r
+          //\r
+          Store(\_PR.CPU0.CPDC(Arg0), Local0)\r
+          GCAP(Local0)\r
+          //Return (Local0)\r
+      }\r
+\r
+      Method(_OSC, 4)\r
+      {\r
+          //\r
+          // Refer to \_PR.CPU0._OSC for description.\r
+          //\r
+          Store(\_PR.CPU0.COSC(Arg0, Arg1, Arg2, Arg3), Local0)\r
+          GCAP(Local0)\r
+          Return (Local0)\r
+      }\r
+\r
+      //\r
+      // Get the capability information and load appropriate tables as needed.\r
+      //\r
+      Method(GCAP, 1)\r
+      {\r
+          //\r
+          // Point to Status DWORD in the Arg0 buffer (STATUS)\r
+          //\r
+          CreateDWordField(Arg0, 0, STS1)\r
+          //\r
+          // Point to Caps DWORDs of the Arg0 buffer (CAPABILITIES)\r
+          //\r
+          CreateDwordField(Arg0, 4, CAP1)\r
+          //\r
+          // If the UUID was unrecognized or the _OSC revision was unsupported,\r
+          // return without updating capabilities.\r
+          //\r
+          If(LOr(LEqual(STS1,0x6),LEqual(STS1,0xA)))\r
+          {\r
+              Return()\r
+          }\r
+\r
+          //\r
+          // Check if this is a query (BIT0 of Status = 1).\r
+          // If so, mask off the bits we support and return.\r
+          //\r
+          if (And(STS1, 1))\r
+          {\r
+              And(CAP1, 0xBFF, CAP1)\r
+              Return()\r
+          }\r
+\r
+          //\r
+          // Store result of PDC. (We clear out the MSB, which was just\r
+          // used as a placeholder for the compiler; and then "OR" the\r
+          // value in case we get multiple calls, each of which only\r
+          // reports partial support.)\r
+          //\r
+          Or(And(PDC1, 0x7FFFFFFF), CAP1, PDC1)\r
+\r
+          //\r
+          // Attempt to dynamically load the IST SSDTs if:\r
+          //   (1) Driver supports P-States in MP configurations\r
+          //   (2) Driver supports direct HW P-State control\r
+          //\r
+          //   PDCx[3]  = OS supports C1 and P-states in MP systems\r
+          //   PDCx[0]  = OS supports direct access of the perf MSR\r
+          //\r
+          If(LEqual(And(PDC0, 0x0009), 0x0009))\r
+          {\r
+              APPT()\r
+          }\r
+\r
+          //\r
+          // Load the CST SSDTs if:\r
+          //   (1) Driver supports multi-processor configurations\r
+          //\r
+          //   PDCx[3]  = OS supports C1 and P-states in MP systems\r
+          //   PDCx[4]  = OS supports ind. C2/C3 in MP systems\r
+          //\r
+          If(And(PDC0,0x0018))\r
+          {\r
+              APCT()\r
+          }\r
+\r
+          Return()\r
+      }\r
+\r
+      //\r
+      // Dynamically load the CST SSDTs if:\r
+      //   (1) C-States are enabled\r
+      //   (2) SSDT is not already loaded\r
+      //\r
+      //   CFGD[11,7,2,1] = C6, C4, C1E, C1 Capable/Enabled\r
+      //   SDTL[5]   = AP CST SSDT Loaded\r
+      //\r
+      Method(APCT,0)\r
+      {\r
+          If(LAnd(And(CFGD,0x82),LNot(And(SDTL,0x20))))\r
+          {\r
+              //\r
+              // Flag the CST SSDT as loaded for the AP's\r
+              //\r
+              Or(SDTL, 0x20, SDTL)\r
+              //\r
+              // Dynamically load the APCST SSDT\r
+              //\r
+              OperationRegion(CST1,SystemMemory,DeRefOf(Index(SSDT,10)),DeRefOf(Index(SSDT,11)))\r
+              Load(CST1, HC1)\r
+          }\r
+      }\r
+\r
+      //\r
+      // Dynamically load the IST SSDTs if:\r
+      //   (1) If GV3 capable and enabled\r
+      //   (2) SSDT is not already loaded\r
+      //\r
+      //   CFGD[0] = GV3 Capable/Enabled\r
+      //   SDTL[4] = AP IST SSDT Loaded\r
+      //\r
+      Method(APPT,0)\r
+      {\r
+          If(LAnd(And(CFGD,0x01),LNot(And(SDTL,0x10))))\r
+          {\r
+              //\r
+              // Flag the IST SSDT as loaded for CPU0\r
+              //\r
+              Or(SDTL, 0x10, SDTL)\r
+\r
+              OperationRegion(IST1,SystemMemory,DeRefOf(Index(SSDT,4)),DeRefOf(Index(SSDT,5)))\r
+              Load(IST1, HI1)    // Dynamically load the CPU1IST SSDT\r
+          }\r
+      }\r
+  }    // End CPU1\r
+\r
+  Scope(\_PR.CPU3)\r
+  {\r
+      //\r
+      // Define handles for opregions (used by load.)\r
+      //\r
+      Name(HI1,0)        // Handle to APIST\r
+      Name(HC1,0)        // Handle to APCST\r
+\r
+      Method(_PDC,1)\r
+      {\r
+          //\r
+          // Refer to \_PR.CPU0._PDC for description.\r
+          //\r
+          Store(\_PR.CPU0.CPDC(Arg0), Local0)\r
+          GCAP(Local0)\r
+          //Return (Local0)\r
+      }\r
+\r
+      Method(_OSC, 4)\r
+      {\r
+          //\r
+          // Refer to \_PR.CPU0._OSC for description.\r
+          //\r
+          Store(\_PR.CPU0.COSC(Arg0, Arg1, Arg2, Arg3), Local0)\r
+          GCAP(Local0)\r
+          Return (Local0)\r
+      }\r
+\r
+      //\r
+      // Get the capability information and load appropriate tables as needed.\r
+      //\r
+      Method(GCAP, 1)\r
+      {\r
+          //\r
+          // Point to Status DWORD in the Arg0 buffer (STATUS)\r
+          //\r
+          CreateDWordField(Arg0, 0, STS1)\r
+          //\r
+          // Point to Caps DWORDs of the Arg0 buffer (CAPABILITIES)\r
+          //\r
+          CreateDwordField(Arg0, 4, CAP1)\r
+          //\r
+          // If the UUID was unrecognized or the _OSC revision was unsupported,\r
+          // return without updating capabilities.\r
+          //\r
+          If(LOr(LEqual(STS1,0x6),LEqual(STS1,0xA)))\r
+          {\r
+              Return()\r
+          }\r
+\r
+          //\r
+          // Check if this is a query (BIT0 of Status = 1).\r
+          // If so, mask off the bits we support and return.\r
+          //\r
+          if (And(STS1, 1))\r
+          {\r
+              And(CAP1, 0xBFF, CAP1)\r
+              Return()\r
+          }\r
+\r
+          //\r
+          // Store result of PDC. (We clear out the MSB, which was just\r
+          // used as a placeholder for the compiler; and then "OR" the\r
+          // value in case we get multiple calls, each of which only\r
+          // reports partial support.)\r
+          //\r
+          Or(And(PDC1, 0x7FFFFFFF), CAP1, PDC1)\r
+\r
+          //\r
+          // Attempt to dynamically load the IST SSDTs if:\r
+          //   (1) Driver supports P-States in MP configurations\r
+          //   (2) Driver supports direct HW P-State control\r
+          //\r
+          //   PDCx[3]  = OS supports C1 and P-states in MP systems\r
+          //   PDCx[0]  = OS supports direct access of the perf MSR\r
+          //\r
+          If(LEqual(And(PDC0, 0x0009), 0x0009))\r
+          {\r
+              APPT()\r
+          }\r
+\r
+          //\r
+          // Load the CST SSDTs if:\r
+          //   (1) Driver supports multi-processor configurations\r
+          //\r
+          //   PDCx[3]  = OS supports C1 and P-states in MP systems\r
+          //   PDCx[4]  = OS supports ind. C2/C3 in MP systems\r
+          //\r
+          If(And(PDC0,0x0018))\r
+          {\r
+              APCT()\r
+          }\r
+\r
+          Return()\r
+      }\r
+\r
+      //\r
+      // Dynamically load the CST SSDTs if:\r
+      //   (1) C-States are enabled\r
+      //   (2) SSDT is not already loaded\r
+      //\r
+      //   CFGD[11,7,2,1] = C6, C4, C1E, C1 Capable/Enabled\r
+      //   SDTL[5]   = AP CST SSDT Loaded\r
+      //\r
+      Method(APCT,0)\r
+      {\r
+          If(LAnd(And(CFGD,0x82),LNot(And(SDTL,0x20))))\r
+          {\r
+              //\r
+              // Flag the CST SSDT as loaded for the AP's\r
+              //\r
+              Or(SDTL, 0x20, SDTL)\r
+              //\r
+              // Dynamically load the APCST SSDT\r
+              //\r
+              OperationRegion(CST1,SystemMemory,DeRefOf(Index(SSDT,10)),DeRefOf(Index(SSDT,11)))\r
+              Load(CST1, HC1)\r
+          }\r
+      }\r
+\r
+      //\r
+      // Dynamically load the IST SSDTs if:\r
+      //   (1) If GV3 capable and enabled\r
+      //   (2) SSDT is not already loaded\r
+      //\r
+      //   CFGD[0] = GV3 Capable/Enabled\r
+      //   SDTL[4] = AP IST SSDT Loaded\r
+      //\r
+      Method(APPT,0)\r
+      {\r
+          If(LAnd(And(CFGD,0x01),LNot(And(SDTL,0x10))))\r
+          {\r
+              //\r
+              // Flag the IST SSDT as loaded for CPU0\r
+              //\r
+              Or(SDTL, 0x10, SDTL)\r
+\r
+              OperationRegion(IST1,SystemMemory,DeRefOf(Index(SSDT,4)),DeRefOf(Index(SSDT,5)))\r
+              Load(IST1, HI1)    // Dynamically load the CPU1IST SSDT\r
+          }\r
+      }\r
+  }    // End CPU3\r
+} // End of Definition Block\r
+\r
+\r
+\r

diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/NorthCluster/Include/PlatformBaseAddresses.h b/Vlv2DeviceRefCodePkg/ValleyView2Soc/NorthCluster/Include/PlatformBaseAddresses.h
new file mode 100644 (file)
index 0000000..43119b8
--- /dev/null
+++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/NorthCluster/Include/PlatformBaseAddresses.h
@@ -0,0 +1,98 @@
+/*++\r
+\r
+  Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+\r
+  This program and the accompanying materials are licensed and made available under\r
+  the terms and conditions of the BSD License that accompanies this distribution.\r
+  The full text of the license may be found at\r
+  http://opensource.org/licenses/bsd-license.php.\r
+\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+\r
+\r
+\r
+Module Name:\r
+\r
+  PlatformBaseAddresses.h\r
+\r
+Abstract:\r
+\r
+\r
+\r
+Revision History\r
+\r
+++*/\r
+\r
+\r
+#ifndef _PLATFORM_BASE_ADDRESSES_H\r
+#define _PLATFORM_BASE_ADDRESSES_H\r
+\r
+//\r
+// Define some fixed platform device location information\r
+//\r
+\r
+//\r
+// Define platform base\r
+//\r
+\r
+//\r
+// SIO\r
+//\r
+#define SIO_BASE_ADDRESS                  0x0680\r
+#define SIO_MONITORING_BASE_ADDRESS       0x0290\r
+#define SIO_BASE_MASK                     0xFFF0\r
+#define WINDBOND_ECIR_BASE_ADDRESS        0x0810\r
+#define SIO_MAILBOX_BASE_ADDRESS          0x0360    // Used by EC controller\r
+#define SIO_EC_CHANNEL2                   0x62      // Used by EC controller for offset 0x62 and 0x66\r
+\r
+\r
+//\r
+// South Cluster\r
+//\r
+#define ACPI_BASE_ADDRESS                 0x0400\r
+#define GPIO_BASE_ADDRESS                 0x0500\r
+#define SMBUS_BUS_DEV_FUNC                0x1F0300\r
+#define SMBUS_BASE_ADDRESS                0xEFA0     // SMBus IO Base Address\r
+#define SPI_BASE_ADDRESS                  0xFED01000 // SPI Memory Base Address\r
+#define PMC_BASE_ADDRESS                  0xFED03000 // PMC Memory Base Address\r
+#define SMBM_BASE_ADDRESS                 0xFED04000 // SMBus Memory Base Address\r
+#define IO_BASE_ADDRESS                   0xFED0C000 // IO Memory Base Address\r
+#define ILB_BASE_ADDRESS                  0xFED08000 // ILB Memory Base Address\r
+#define HPET_BASE_ADDRESS                 0xFED00000 // HPET Base Address\r
+#define RCBA_BASE_ADDRESS                 0xFED1C000 // Root Complex Base Address\r
+#define MPHY_BASE_ADDRESS                 0xFEF00000 // MPHY Memory Base Address\r
+#define PUNIT_BASE_ADDRESS                0xFED05000 // PUnit Memory Base Address\r
+\r
+//\r
+// GPIO GROUP OFFSET\r
+//\r
+#define GPIO_SCORE_OFFSET                 0x0000\r
+#define GPIO_NCORE_OFFSET                 0x1000\r
+#define GPIO_SSUS_OFFSET                  0x2000\r
+\r
+//\r
+// MCH/CPU\r
+//\r
+#define DMI_BASE_ADDRESS                  0xFED18000 // 4K, similar to IIO_RCBA // modify from bearlake -- cchew10\r
+#define EP_BASE_ADDRESS                   0xFED19000\r
+#define MC_MMIO_BASE                      0xFED14000 // Base Address for MMIO registers\r
+\r
+//\r
+// TPM\r
+//\r
+#define TPM_BASE_ADDRESS                  0xFED40000  // Base address for TPM\r
+\r
+//\r
+// Local and I/O APIC addresses.\r
+//\r
+#define IO_APIC_ADDRESS                   0xFEC00000\r
+#define IIO_IOAPIC_ADDRESS                0xFEC90000\r
+#define LOCAL_APIC_ADDRESS                0xFEE00000\r
+\r
+\r
+#endif\r
+\r
+\r

diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/NorthCluster/Include/Ppi/Capsule.h b/Vlv2DeviceRefCodePkg/ValleyView2Soc/NorthCluster/Include/Ppi/Capsule.h
new file mode 100644 (file)
index 0000000..618e3d3
--- /dev/null
+++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/NorthCluster/Include/Ppi/Capsule.h
@@ -0,0 +1,66 @@
+/*++\r
+\r
+Copyright (c)  1999  - 2014, Intel Corporation. All rights reserved\r
+\r
+  This program and the accompanying materials are licensed and made available under\r
+  the terms and conditions of the BSD License that accompanies this distribution.\r
+  The full text of the license may be found at\r
+  http://opensource.org/licenses/bsd-license.php.\r
+\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+\r
+Module Name:\r
+\r
+  Capsule.h\r
+\r
+Abstract:\r
+\r
+  Capsule PPI definitions.\r
+\r
+--*/\r
+//\r
+//\r
+#ifndef _PEI_CAPSULE_PPI_H_\r
+#define _PEI_CAPSULE_PPI_H_\r
+\r
+#define PEI_CAPSULE_PPI_GUID \\r
+  { \\r
+    0x3acf33ee, 0xd892, 0x40f4, 0xa2, 0xfc, 0x38, 0x54, 0xd2, 0xe1, 0x32, 0x3d \\r
+  }\r
+\r
+EFI_FORWARD_DECLARATION (PEI_CAPSULE_PPI);\r
+\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *PEI_CAPSULE_COALESCE) (\r
+  IN EFI_PEI_SERVICES                **PeiServices,\r
+  IN OUT VOID                        **MemoryBase,\r
+  IN OUT UINTN                       *MemSize\r
+  );\r
+\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *PEI_CAPSULE_CREATE_STATE) (\r
+  IN EFI_PEI_SERVICES                                   **PeiServices,\r
+  IN VOID                                               *CapsuleBase, // returned from coalesce\r
+  IN UINTN                              CapsuleSize                   // returned from coalesce\r
+  );\r
+\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *PEI_CAPSULE_CHECK_CAPSULE_UPDATE) (\r
+  IN EFI_PEI_SERVICES           **PeiServices\r
+  );\r
+\r
+typedef struct _PEI_CAPSULE_PPI {\r
+  PEI_CAPSULE_COALESCE              Coalesce;\r
+  PEI_CAPSULE_CHECK_CAPSULE_UPDATE  CheckCapsuleUpdate;\r
+  PEI_CAPSULE_CREATE_STATE          CreateState;\r
+} PEI_CAPSULE_PPI;\r
+\r
+extern EFI_GUID gPeiCapsulePpiGuid;\r
+\r
+#endif // #ifndef _PEI_CAPSULE_PPI_H_\r

diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/NorthCluster/Include/Ppi/PlatformMemoryRange.h b/Vlv2DeviceRefCodePkg/ValleyView2Soc/NorthCluster/Include/Ppi/PlatformMemoryRange.h
new file mode 100644 (file)
index 0000000..b2faf4c
--- /dev/null
+++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/NorthCluster/Include/Ppi/PlatformMemoryRange.h
@@ -0,0 +1,150 @@
+/*++\r
+\r
+Copyright (c)  1999  - 2014, Intel Corporation. All rights reserved\r
+\r
+  This program and the accompanying materials are licensed and made available under\r
+  the terms and conditions of the BSD License that accompanies this distribution.\r
+  The full text of the license may be found at\r
+  http://opensource.org/licenses/bsd-license.php.\r
+\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+\r
+Module Name:\r
+\r
+  PlatformMemoryRange.h\r
+\r
+Abstract:\r
+\r
+  Platform Memory Range PPI as defined in EFI 2.0\r
+\r
+  PPI for reserving special purpose memory ranges.\r
+\r
+--*/\r
+//\r
+//\r
+#ifndef _PEI_PLATFORM_MEMORY_RANGE_H_\r
+#define _PEI_PLATFORM_MEMORY_RANGE_H_\r
+\r
+#define PEI_PLATFORM_MEMORY_RANGE_PPI_GUID \\r
+  { \\r
+    0x30eb2979, 0xb0f7, 0x4d60, 0xb2, 0xdc, 0x1a, 0x2c, 0x96, 0xce, 0xb1, 0xf4 \\r
+  }\r
+\r
+typedef struct _PEI_PLATFORM_MEMORY_RANGE_PPI  PEI_PLATFORM_MEMORY_RANGE_PPI ;\r
+\r
+#define PEI_MEMORY_RANGE_OPTION_ROM UINT32\r
+\r
+#define PEI_MR_OPTION_ROM_ALL       0xFFFFFFFF\r
+#define PEI_MR_OPTION_ROM_NONE      0x00000000\r
+#define PEI_MR_OPTION_ROM_C0000_16K 0x00000001\r
+#define PEI_MR_OPTION_ROM_C4000_16K 0x00000002\r
+#define PEI_MR_OPTION_ROM_C8000_16K 0x00000004\r
+#define PEI_MR_OPTION_ROM_CC000_16K 0x00000008\r
+#define PEI_MR_OPTION_ROM_D0000_16K 0x00000010\r
+#define PEI_MR_OPTION_ROM_D4000_16K 0x00000020\r
+#define PEI_MR_OPTION_ROM_D8000_16K 0x00000040\r
+#define PEI_MR_OPTION_ROM_DC000_16K 0x00000080\r
+#define PEI_MR_OPTION_ROM_E0000_16K 0x00000100\r
+#define PEI_MR_OPTION_ROM_E4000_16K 0x00000200\r
+#define PEI_MR_OPTION_ROM_E8000_16K 0x00000400\r
+#define PEI_MR_OPTION_ROM_EC000_16K 0x00000800\r
+#define PEI_MR_OPTION_ROM_F0000_16K 0x00001000\r
+#define PEI_MR_OPTION_ROM_F4000_16K 0x00002000\r
+#define PEI_MR_OPTION_ROM_F8000_16K 0x00004000\r
+#define PEI_MR_OPTION_ROM_FC000_16K 0x00008000\r
+\r
+//\r
+// SMRAM Memory Range\r
+//\r
+#define PEI_MEMORY_RANGE_SMRAM      UINT32\r
+#define PEI_MR_SMRAM_ALL            0xFFFFFFFF\r
+#define PEI_MR_SMRAM_NONE           0x00000000\r
+#define PEI_MR_SMRAM_CACHEABLE_MASK 0x80000000\r
+#define PEI_MR_SMRAM_SEGTYPE_MASK   0x00FF0000\r
+#define PEI_MR_SMRAM_ABSEG_MASK     0x00010000\r
+#define PEI_MR_SMRAM_HSEG_MASK      0x00020000\r
+#define PEI_MR_SMRAM_TSEG_MASK      0x00040000\r
+//\r
+// If adding additional entries, SMRAM Size\r
+// is a multiple of 128KB.\r
+//\r
+#define PEI_MR_SMRAM_SIZE_MASK          0x0000FFFF\r
+#define PEI_MR_SMRAM_SIZE_128K_MASK     0x00000001\r
+#define PEI_MR_SMRAM_SIZE_256K_MASK     0x00000002\r
+#define PEI_MR_SMRAM_SIZE_512K_MASK     0x00000004\r
+#define PEI_MR_SMRAM_SIZE_1024K_MASK    0x00000008\r
+#define PEI_MR_SMRAM_SIZE_2048K_MASK    0x00000010\r
+#define PEI_MR_SMRAM_SIZE_4096K_MASK    0x00000020\r
+#define PEI_MR_SMRAM_SIZE_8192K_MASK    0x00000040\r
+\r
+#define PEI_MR_SMRAM_ABSEG_128K_NOCACHE 0x00010001\r
+#define PEI_MR_SMRAM_HSEG_128K_CACHE    0x80020001\r
+#define PEI_MR_SMRAM_HSEG_128K_NOCACHE  0x00020001\r
+#define PEI_MR_SMRAM_TSEG_128K_CACHE    0x80040001\r
+#define PEI_MR_SMRAM_TSEG_128K_NOCACHE  0x00040001\r
+#define PEI_MR_SMRAM_TSEG_256K_CACHE    0x80040002\r
+#define PEI_MR_SMRAM_TSEG_256K_NOCACHE  0x00040002\r
+#define PEI_MR_SMRAM_TSEG_512K_CACHE    0x80040004\r
+#define PEI_MR_SMRAM_TSEG_512K_NOCACHE  0x00040004\r
+#define PEI_MR_SMRAM_TSEG_1024K_CACHE   0x80040008\r
+#define PEI_MR_SMRAM_TSEG_1024K_NOCACHE 0x00040008\r
+\r
+//\r
+// Graphics Memory Range\r
+//\r
+#define PEI_MEMORY_RANGE_GRAPHICS_MEMORY  UINT32\r
+#define PEI_MR_GRAPHICS_MEMORY_ALL        0xFFFFFFFF\r
+#define PEI_MR_GRAPHICS_MEMORY_NONE       0x00000000\r
+#define PEI_MR_GRAPHICS_MEMORY_CACHEABLE  0x80000000\r
+//\r
+// If adding additional entries, Graphics Memory Size\r
+// is a multiple of 512KB.\r
+//\r
+#define PEI_MR_GRAPHICS_MEMORY_SIZE_MASK    0x0000FFFF\r
+#define PEI_MR_GRAPHICS_MEMORY_512K_NOCACHE 0x00000001\r
+#define PEI_MR_GRAPHICS_MEMORY_512K_CACHE   0x80000001\r
+#define PEI_MR_GRAPHICS_MEMORY_1M_NOCACHE   0x00000002\r
+#define PEI_MR_GRAPHICS_MEMORY_1M_CACHE     0x80000002\r
+#define PEI_MR_GRAPHICS_MEMORY_4M_NOCACHE   0x00000008\r
+#define PEI_MR_GRAPHICS_MEMORY_4M_CACHE     0x80000008\r
+#define PEI_MR_GRAPHICS_MEMORY_8M_NOCACHE   0x00000010\r
+#define PEI_MR_GRAPHICS_MEMORY_8M_CACHE     0x80000010\r
+#define PEI_MR_GRAPHICS_MEMORY_16M_NOCACHE  0x00000020\r
+#define PEI_MR_GRAPHICS_MEMORY_16M_CACHE    0x80000020\r
+#define PEI_MR_GRAPHICS_MEMORY_32M_NOCACHE  0x00000040\r
+#define PEI_MR_GRAPHICS_MEMORY_32M_CACHE    0x80000040\r
+#define PEI_MR_GRAPHICS_MEMORY_48M_NOCACHE  0x00000060\r
+#define PEI_MR_GRAPHICS_MEMORY_48M_CACHE    0x80000060\r
+#define PEI_MR_GRAPHICS_MEMORY_64M_NOCACHE  0x00000080\r
+#define PEI_MR_GRAPHICS_MEMORY_64M_CACHE    0x80000080\r
+#define PEI_MR_GRAPHICS_MEMORY_128M_NOCACHE 0x00000100\r
+#define PEI_MR_GRAPHICS_MEMORY_128M_CACHE   0x80000100\r
+#define PEI_MR_GRAPHICS_MEMORY_256M_NOCACHE 0x00000200\r
+#define PEI_MR_GRAPHICS_MEMORY_256M_CACHE   0x80000200\r
+//\r
+// Pci Memory Hole\r
+//\r
+#define PEI_MEMORY_RANGE_PCI_MEMORY       UINT32\r
+#define PEI_MR_PCI_MEMORY_SIZE_512M_MASK  0x00000001\r
+\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *PEI_CHOOSE_RANGES) (\r
+  IN      EFI_PEI_SERVICES                      **PeiServices,\r
+  IN PEI_PLATFORM_MEMORY_RANGE_PPI              * This,\r
+  IN OUT  PEI_MEMORY_RANGE_OPTION_ROM           * OptionRomMask,\r
+  IN OUT  PEI_MEMORY_RANGE_SMRAM                * SmramMask,\r
+  IN OUT  PEI_MEMORY_RANGE_GRAPHICS_MEMORY      * GraphicsMemoryMask,\r
+  IN OUT  PEI_MEMORY_RANGE_PCI_MEMORY           * PciMemoryMask\r
+  );\r
+\r
+struct _PEI_PLATFORM_MEMORY_RANGE_PPI {\r
+  PEI_CHOOSE_RANGES ChooseRanges;\r
+};\r
+\r
+extern EFI_GUID gPeiPlatformMemoryRangePpiGuid;\r
+\r
+#endif\r

diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/NorthCluster/Include/Ppi/PlatformMemorySize.h b/Vlv2DeviceRefCodePkg/ValleyView2Soc/NorthCluster/Include/Ppi/PlatformMemorySize.h
new file mode 100644 (file)
index 0000000..6aa66b5
--- /dev/null
+++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/NorthCluster/Include/Ppi/PlatformMemorySize.h
@@ -0,0 +1,52 @@
+/*++\r
+\r
+Copyright (c)  1999  - 2014, Intel Corporation. All rights reserved\r
+\r
+  This program and the accompanying materials are licensed and made available under\r
+  the terms and conditions of the BSD License that accompanies this distribution.\r
+  The full text of the license may be found at\r
+  http://opensource.org/licenses/bsd-license.php.\r
+\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+Module Name:\r
+\r
+  PlatformMemorySize.h\r
+\r
+Abstract:\r
+\r
+  Platform Memory Size PPI as defined in Tiano\r
+\r
+  PPI for describing the minimum platform memory size in order to successfully\r
+  pass control into DXE\r
+\r
+--*/\r
+//\r
+//\r
+#ifndef _PEI_PLATFORM_MEMORY_SIZE_H_\r
+#define _PEI_PLATFORM_MEMORY_SIZE_H_\r
+\r
+#define PEI_PLATFORM_MEMORY_SIZE_PPI_GUID \\r
+  { \\r
+    0x9a7ef41e, 0xc140, 0x4bd1, 0xb8, 0x84, 0x1e, 0x11, 0x24, 0xb, 0x4c, 0xe6 \\r
+  }\r
+\r
+EFI_FORWARD_DECLARATION (PEI_PLATFORM_MEMORY_SIZE_PPI);\r
+\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *PEI_GET_MINIMUM_PLATFORM_MEMORY_SIZE) (\r
+  IN      EFI_PEI_SERVICES                       **PeiServices,\r
+  IN PEI_PLATFORM_MEMORY_SIZE_PPI                * This,\r
+  IN OUT  UINT64                                 *MemorySize\r
+  );\r
+\r
+typedef struct _PEI_PLATFORM_MEMORY_SIZE_PPI {\r
+  PEI_GET_MINIMUM_PLATFORM_MEMORY_SIZE  GetPlatformMemorySize;\r
+} PEI_PLATFORM_MEMORY_SIZE_PPI;\r
+\r
+extern EFI_GUID gPeiPlatformMemorySizePpiGuid;\r
+\r
+#endif\r

diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/NorthCluster/Include/Ppi/SmmAccess.h b/Vlv2DeviceRefCodePkg/ValleyView2Soc/NorthCluster/Include/Ppi/SmmAccess.h
new file mode 100644 (file)
index 0000000..674d566
--- /dev/null
+++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/NorthCluster/Include/Ppi/SmmAccess.h
@@ -0,0 +1,171 @@
+//\r
+//\r
+/*++\r
+\r
+Copyright (c)  2009  - 2014, Intel Corporation. All rights reserved\r
+\r
+  This program and the accompanying materials are licensed and made available under\r
+  the terms and conditions of the BSD License that accompanies this distribution.\r
+  The full text of the license may be found at\r
+  http://opensource.org/licenses/bsd-license.php.\r
+\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+\r
+Module Name:\r
+\r
+  SmmAccess.h\r
+\r
+Abstract:\r
+\r
+  SmmAccess PPI\r
+\r
+  This code abstracts the PEI core to provide SmmAccess services.\r
+\r
+--*/\r
+\r
+#ifndef _PEI_SMM_ACCESS_PPI_H_\r
+#define _PEI_SMM_ACCESS_PPI_H_\r
+\r
+#ifdef ECP_FLAG\r
+#include "Guid/SmramMemoryReserve/SmramMemoryReserve.h"\r
+#else\r
+#include "Guid/SmramMemoryReserve.h"\r
+#endif\r
+\r
+#define PEI_SMM_ACCESS_PPI_GUID \\r
+  { \\r
+    0x268f33a9, 0xcccd, 0x48be, 0x88, 0x17, 0x86, 0x5, 0x3a, 0xc3, 0x2e, 0xd6 \\r
+  }\r
+\r
+typedef struct _PEI_SMM_ACCESS_PPI PEI_SMM_ACCESS_PPI;\r
+\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *PEI_SMM_OPEN) (\r
+  IN EFI_PEI_SERVICES                **PeiServices,\r
+  IN PEI_SMM_ACCESS_PPI              *This,\r
+  IN UINTN                           DescriptorIndex\r
+  )\r
+/*++\r
+\r
+  Routine Description:\r
+    This routine accepts a request to "open" a region of SMRAM.  The\r
+    region could be legacy ABSEG, HSEG, or TSEG near top of physical memory.\r
+    The use of "open" means that the memory is visible from all PEIM\r
+    and SMM agents.\r
+\r
+  Arguments:\r
+    PeiServices           - General purpose services available to every PEIM.\r
+    This                  - Pointer to the SMM Access Interface.\r
+    DescriptorIndex       - Region of SMRAM to Open.\r
+\r
+  Returns:\r
+    EFI_SUCCESS           - The region was successfully opened.\r
+    EFI_DEVICE_ERROR      - The region could not be opened because locked by\r
+                            chipset.\r
+    EFI_INVALID_PARAMETER - The descriptor index was out of bounds.\r
+--*/\r
+;\r
+\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *PEI_SMM_CLOSE) (\r
+  IN EFI_PEI_SERVICES                **PeiServices,\r
+  IN PEI_SMM_ACCESS_PPI              *This,\r
+  IN UINTN                           DescriptorIndex\r
+  )\r
+/*++\r
+\r
+  Routine Description:\r
+    This routine accepts a request to "close" a region of SMRAM.  The\r
+    region could be legacy AB or TSEG near top of physical memory.\r
+    The use of "close" means that the memory is only visible from SMM agents,\r
+    not from PEIM.\r
+\r
+  Arguments:\r
+    PeiServices           - General purpose services available to every PEIM.\r
+    This                  - Pointer to the SMM Access Interface.\r
+    DescriptorIndex       - Region of SMRAM to Close.\r
+\r
+  Returns:\r
+    EFI_SUCCESS           - The region was successfully closed.\r
+    EFI_DEVICE_ERROR      - The region could not be closed because locked by\r
+                              chipset.\r
+    EFI_INVALID_PARAMETER - The descriptor index was out of bounds.\r
+\r
+--*/\r
+;\r
+\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *PEI_SMM_LOCK) (\r
+  IN EFI_PEI_SERVICES                **PeiServices,\r
+  IN PEI_SMM_ACCESS_PPI              *This,\r
+  IN UINTN                           DescriptorIndex\r
+  )\r
+/*++\r
+\r
+  Routine Description:\r
+    This routine accepts a request to "lock" SMRAM.  The\r
+    region could be legacy AB or TSEG near top of physical memory.\r
+    The use of "lock" means that the memory can no longer be opened\r
+    to PEIM.\r
+\r
+  Arguments:\r
+    PeiServices           - General purpose services available to every PEIM.\r
+    This                  - Pointer to the SMM Access Interface.\r
+    DescriptorIndex       - Region of SMRAM to Lock.\r
+\r
+  Returns:\r
+    EFI_SUCCESS           - The region was successfully locked.\r
+    EFI_DEVICE_ERROR      - The region could not be locked because at least\r
+                            one range is still open.\r
+    EFI_INVALID_PARAMETER - The descriptor index was out of bounds.\r
+\r
+--*/\r
+;\r
+\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *PEI_SMM_CAPABILITIES) (\r
+  IN EFI_PEI_SERVICES                **PeiServices,\r
+  IN PEI_SMM_ACCESS_PPI              *This,\r
+  IN OUT UINTN                       *SmramMapSize,\r
+  IN OUT EFI_SMRAM_DESCRIPTOR        *SmramMap\r
+  )\r
+/*++\r
+\r
+  Routine Description:\r
+    This routine services a user request to discover the SMRAM\r
+    capabilities of this platform.  This will report the possible\r
+    ranges that are possible for SMRAM access, based upon the\r
+    memory controller capabilities.\r
+\r
+  Arguments:\r
+    PeiServices           - General purpose services available to every PEIM.\r
+    This                  - Pointer to the SMRAM Access Interface.\r
+    SmramMapSize          - Pointer to the variable containing size of the\r
+                              buffer to contain the description information.\r
+    SmramMap              - Buffer containing the data describing the Smram\r
+                              region descriptors.\r
+  Returns:\r
+    EFI_BUFFER_TOO_SMALL  - The user did not provide a sufficient buffer.\r
+    EFI_SUCCESS           - The user provided a sufficiently-sized buffer.\r
+--*/\r
+;\r
+\r
+struct _PEI_SMM_ACCESS_PPI {\r
+  PEI_SMM_OPEN          Open;\r
+  PEI_SMM_CLOSE         Close;\r
+  PEI_SMM_LOCK          Lock;\r
+  PEI_SMM_CAPABILITIES  GetCapabilities;\r
+  BOOLEAN               LockState;\r
+  BOOLEAN               OpenState;\r
+};\r
+\r
+extern EFI_GUID gPeiSmmAccessPpiGuid;\r
+\r
+#endif\r

diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/NorthCluster/Include/Ppi/VlvMmioPolicy.h b/Vlv2DeviceRefCodePkg/ValleyView2Soc/NorthCluster/Include/Ppi/VlvMmioPolicy.h
new file mode 100644 (file)
index 0000000..53a5c12
--- /dev/null
+++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/NorthCluster/Include/Ppi/VlvMmioPolicy.h
@@ -0,0 +1,45 @@
+\r
+/*++\r
+\r
+Copyright (c)  2010  - 2014, Intel Corporation. All rights reserved\r
+\r
+  This program and the accompanying materials are licensed and made available under\r
+  the terms and conditions of the BSD License that accompanies this distribution.\r
+  The full text of the license may be found at\r
+  http://opensource.org/licenses/bsd-license.php.\r
+\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+Module Name:\r
+\r
+  VlvMmioPolicy.h\r
+\r
+Abstract:\r
+\r
+  Interface definition details between ValleyView platform drivers during PEI phase.\r
+\r
+--*/\r
+\r
+#ifndef _VLV_MMIO_POLICY_PPI_H_\r
+#define _VLV_MMIO_POLICY_PPI_H_\r
+\r
+#define VLV_MMIO_POLICY_PPI_GUID \\r
+  { \\r
+    0xE767BF7F, 0x4DB6, 0x5B34, 0x10, 0x11, 0x4F, 0xBE, 0x4C, 0xA7, 0xAF, 0xD2 \\r
+  }\r
+\r
+extern EFI_GUID gVlvMmioPolicyPpiGuid;\r
+\r
+\r
+//\r
+// MRC Platform Policiy PPI\r
+//\r
+typedef struct _VLV_MMIO_POLICY_PPI {\r
+  UINT16                 MmioSize;\r
+} VLV_MMIO_POLICY_PPI;\r
+\r
+#pragma pack()\r
+\r
+#endif // _VLV_MMIO_POLICY_PPI_H_\r

diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/NorthCluster/Include/Ppi/VlvPeiInit.h b/Vlv2DeviceRefCodePkg/ValleyView2Soc/NorthCluster/Include/Ppi/VlvPeiInit.h
new file mode 100644 (file)
index 0000000..9ad30cc
--- /dev/null
+++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/NorthCluster/Include/Ppi/VlvPeiInit.h
@@ -0,0 +1,41 @@
+\r
+/*++\r
+\r
+Copyright (c)  1999  - 2014, Intel Corporation. All rights reserved\r
+\r
+  This program and the accompanying materials are licensed and made available under\r
+  the terms and conditions of the BSD License that accompanies this distribution.\r
+  The full text of the license may be found at\r
+  http://opensource.org/licenses/bsd-license.php.\r
+\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+Module Name:\r
+\r
+  VlvPeiInit.h\r
+\r
+Abstract:\r
+\r
+  Interface definition between ValleyView MRC and VlvInitPeim driver..\r
+\r
+--*/\r
+\r
+#ifndef _VLV_PEI_INIT_H_\r
+#define _VLV_PEI_INIT_H_\r
+\r
+//\r
+// Define the VLV PEI Init PPI GUID\r
+//\r
+#define VLV_PEI_INIT_PPI_GUID \\r
+  { \\r
+    0x9ea8911, 0xbe0d, 0x4230, 0xa0, 0x3, 0xed, 0xc6, 0x93, 0xb4, 0x8e, 0x11 \\r
+  }\r
+\r
+//\r
+// Extern the GUID for PPI users.\r
+//\r
+extern EFI_GUID     gVlvPeiInitPpiGuid;\r
+\r
+#endif\r

diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/NorthCluster/Include/Ppi/VlvPolicy.h b/Vlv2DeviceRefCodePkg/ValleyView2Soc/NorthCluster/Include/Ppi/VlvPolicy.h
new file mode 100644 (file)
index 0000000..19061f7
--- /dev/null
+++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/NorthCluster/Include/Ppi/VlvPolicy.h
@@ -0,0 +1,112 @@
+\r
+/*++\r
+\r
+Copyright (c)  2010  - 2014, Intel Corporation. All rights reserved\r
+\r
+  This program and the accompanying materials are licensed and made available under\r
+  the terms and conditions of the BSD License that accompanies this distribution.\r
+  The full text of the license may be found at\r
+  http://opensource.org/licenses/bsd-license.php.\r
+\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+Module Name:\r
+\r
+  VlvPolicy.h\r
+\r
+Abstract:\r
+\r
+  Interface definition details between ValleyView MRC and platform drivers during PEI phase.\r
+\r
+--*/\r
+\r
+#ifndef _VLV_POLICY_PPI_H_\r
+#define _VLV_POLICY_PPI_H_\r
+\r
+//\r
+// MRC Policy provided by platform for PEI phase {7D84B2C2-22A1-4372-B12C-EBB232D3A6A3}\r
+//\r
+#define VLV_POLICY_PPI_GUID \\r
+  { \\r
+    0x7D84B2C2, 0x22A1, 0x4372, 0xB1, 0x2C, 0xEB, 0xB2, 0x32, 0xD3, 0xA6, 0xA3 \\r
+  }\r
+\r
+//\r
+// Extern the GUID for protocol users.\r
+//\r
+extern EFI_GUID gVlvPolicyPpiGuid;\r
+\r
+//\r
+// PPI revision number\r
+// Any backwards compatible changes to this PPI will result in an update in the revision number\r
+// Major changes will require publication of a new PPI\r
+//\r
+#define MRC_PLATFORM_POLICY_PPI_REVISION  1\r
+\r
+#ifndef MAX_SOCKETS\r
+#define MAX_SOCKETS 4\r
+#endif\r
+\r
+#define S3_TIMING_DATA_LEN          9\r
+#define S3_READ_TRAINING_DATA_LEN   16\r
+#define S3_WRITE_TRAINING_DATA_LEN  12\r
+\r
+#ifndef S3_RESTORE_DATA_LEN\r
+#define S3_RESTORE_DATA_LEN (S3_TIMING_DATA_LEN + S3_READ_TRAINING_DATA_LEN + S3_WRITE_TRAINING_DATA_LEN)\r
+#endif // S3_RESTORE_DATA_LEN\r
+#pragma pack(1)\r
+//\r
+// MRC Platform Data Structure\r
+//\r
+typedef struct {\r
+  UINT8   SpdAddressTable[MAX_SOCKETS];\r
+  UINT8   TSonDimmSmbusAddress[MAX_SOCKETS];\r
+\r
+  UINT16  SmbusBar;\r
+  UINT32  IchRcba;\r
+  UINT32  WdbBaseAddress; // Write Data Buffer area (WC caching mode)\r
+  UINT32  WdbRegionSize;\r
+  UINT32  SmBusAddress;\r
+  UINT8   UserBd;\r
+  UINT8   PlatformType;\r
+  UINT8   FastBoot;\r
+  UINT8   DynSR;\r
+} VLV_PLATFORM_DATA;\r
+\r
+\r
+typedef struct {\r
+  UINT16  MmioSize;\r
+  UINT16  GttSize;\r
+  UINT8   IgdDvmt50PreAlloc;\r
+  UINT8   PrimaryDisplay;\r
+  UINT8   PAVPMode;\r
+  UINT8   ApertureSize;\r
+  UINT8   InternalGraphics;\r
+  UINT8   IgdTurboEn;\r
+} GT_CONFIGURATION;\r
+\r
+typedef struct {\r
+  UINT8   EccSupport;\r
+  UINT16  DdrFreqLimit;\r
+  UINT8   MaxTolud;\r
+} MEMORY_CONFIGURATION;\r
+\r
+\r
+//\r
+// MRC Platform Policiy PPI\r
+//\r
+typedef struct _VLV_POLICY_PPI {\r
+  UINT8                 Revision;\r
+  VLV_PLATFORM_DATA      PlatformData;\r
+  GT_CONFIGURATION      GtConfig;\r
+  MEMORY_CONFIGURATION  MemConfig;\r
+  VOID                  *S3DataPtr; // was called MRC_PARAMS_SAVE_RESTORE\r
+  UINT8                 ISPEn;            //ISP (IUNIT) Device Enabled\r
+  UINT8                 ISPPciDevConfig;  //ISP (IUNIT) Device Config: 0->B0/D2/F0 for Window OS, 1->B0D3/F0 for Linux OS\r
+} VLV_POLICY_PPI;\r
+\r
+#pragma pack()\r
+\r
+#endif // _VLV_POLICY_PPI_H_\r

diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/NorthCluster/Include/Protocol/IgdOpRegion.h b/Vlv2DeviceRefCodePkg/ValleyView2Soc/NorthCluster/Include/Protocol/IgdOpRegion.h
new file mode 100644 (file)
index 0000000..8aa7c7b
--- /dev/null
+++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/NorthCluster/Include/Protocol/IgdOpRegion.h
@@ -0,0 +1,219 @@
+\r
+/*++\r
+\r
+Copyright (c)  1999  - 2014, Intel Corporation. All rights reserved\r
+\r
+  This program and the accompanying materials are licensed and made available under\r
+  the terms and conditions of the BSD License that accompanies this distribution.\r
+  The full text of the license may be found at\r
+  http://opensource.org/licenses/bsd-license.php.\r
+\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+Module Name:\r
+\r
+  IgdOpRegion.h\r
+\r
+Abstract:\r
+\r
+  This file is part of the IGD OpRegion Implementation.  The IGD OpRegion is\r
+  an interface between system BIOS, ASL code, and Graphics drivers.\r
+\r
+  Supporting Specifiction: IGD OpRegion/Software SCI SPEC\r
+\r
+  Note:  Data structures defined in this protocol are packed not naturally\r
+    aligned.\r
+\r
+  GUID forms:\r
+    {CDC5DDDF-E79D-41ec-A9B0-6565490DB9D3}\r
+    (0xcdc5dddf, 0xe79d, 0x41ec, 0xa9, 0xb0, 0x65, 0x65, 0x49, 0xd, 0xb9, 0xd3);\r
+\r
+  Acronyms:\r
+    NVS:        ACPI Non Volatile Storage\r
+    OpRegion:   ACPI Operational Region\r
+    VBT:        Video BIOS Table (OEM customizable data)\r
+\r
+--*/\r
+\r
+#ifndef _IGD_OPREGION_PROTOCOL_H_\r
+#define _IGD_OPREGION_PROTOCOL_H_\r
+\r
+//\r
+// OpRegion / Software SCI protocol GUID\r
+//\r
+#define IGD_OPREGION_PROTOCOL_GUID \\r
+  { \\r
+    0xcdc5dddf, 0xe79d, 0x41ec, 0xa9, 0xb0, 0x65, 0x65, 0x49, 0xd, 0xb9, 0xd3 \\r
+  }\r
+\r
+//\r
+// Extern the GUID for protocol users.\r
+//\r
+extern EFI_GUID gIgdOpRegionProtocolGuid;\r
+\r
+//\r
+// Forward reference for pure ANSI compatability\r
+//\r
+typedef struct _IGD_OPREGION_PROTOCOL IGD_OPREGION_PROTOCOL;\r
+\r
+//\r
+// Protocol data definitions\r
+//\r
+\r
+//\r
+// OpRegion structures:\r
+// Sub-structures define the different parts of the OpRegion followed by the\r
+// main structure representing the entire OpRegion.\r
+//\r
+// Note: These structures are packed to 1 byte offsets because the exact\r
+// data location is requred by the supporting design specification due to\r
+// the fact that the data is used by ASL and Graphics driver code compiled\r
+// separatly.\r
+//\r
+\r
+//\r
+// OpRegion header (mailbox 0) structure and #defines.\r
+//\r
+#pragma pack (1)\r
+typedef struct {\r
+  CHAR8   SIGN[0x10]; // 0      OpRegion signature\r
+  UINT32  SIZE;       // 0x10   OpRegion size\r
+  UINT32  OVER;       // 0x14   OpRegion structure version\r
+  UINT8   SVER[0x20]; // 0x18   System BIOS build version\r
+  UINT8   VVER[0x10]; // 0x38   Video BIOS build version\r
+  UINT8   GVER[0x10]; // 0x48   Graphic driver build version\r
+  UINT32  MBOX;       // 0x58   Mailboxes supported\r
+  UINT32  DMOD;       // 0x5C   Driver Model\r
+  UINT32  PCON;       // 0x60   Platform Configuration Info\r
+  CHAR8   GOPV[0x20]; // 0X64   GOP build version\r
+  UINT8   RSV[0x7C];  //        Reserved\r
+} OPREGION_HEADER;\r
+#pragma pack ()\r
+\r
+//\r
+// OpRegion mailbox 1 (public ACPI Methods).\r
+//\r
+#pragma pack (1)\r
+typedef struct {\r
+  UINT32  DRDY;     // 0    Driver readiness\r
+  UINT32  CSTS;     // 4    Status\r
+  UINT32  CEVT;     // 8    Current event\r
+  UINT8   RM11[0x14]; // 12   Reserved\r
+  UINT32  DIDL;       // 32   Supported display devices list\r
+  UINT32  DDL2;       //  8 Devices.\r
+  UINT32  DDL3;\r
+  UINT32  DDL4;\r
+  UINT32  DDL5;\r
+  UINT32  DDL6;\r
+  UINT32  DDL7;\r
+  UINT32  DDL8;\r
+  UINT32  CPDL;       // 64   Currently present display devices list\r
+  UINT32  CPL2;       //  8 Devices.\r
+  UINT32  CPL3;\r
+  UINT32  CPL4;\r
+  UINT32  CPL5;\r
+  UINT32  CPL6;\r
+  UINT32  CPL7;\r
+  UINT32  CPL8;\r
+  UINT32  CADL;       // 96   Currently active display devices list\r
+  UINT32  CAL2;       //  8 Devices.\r
+  UINT32  CAL3;\r
+  UINT32  CAL4;\r
+  UINT32  CAL5;\r
+  UINT32  CAL6;\r
+  UINT32  CAL7;\r
+  UINT32  CAL8;\r
+  UINT32  NADL;       // 128  Next active device list\r
+  UINT32  NDL2;       //   8 Devices.\r
+  UINT32  NDL3;\r
+  UINT32  NDL4;\r
+  UINT32  NDL5;\r
+  UINT32  NDL6;\r
+  UINT32  NDL7;\r
+  UINT32  NDL8;\r
+  UINT32  ASLP;     // 160  ASL sleep timeout\r
+  UINT32  TIDX;     // 164  Toggle table index\r
+  UINT32  CHPD;     // 168  Current hot plug enable indicator\r
+  UINT32  CLID;     // 172  Current lid state indicator\r
+  UINT32  CDCK;     // 176  Current docking state indicator\r
+  UINT32  SXSW;     // 180  Display Switch notification on Sx State resume\r
+  UINT32  EVTS;     // 184  Events supported by ASL\r
+  UINT32  CNOT;     // 188  Current OS Notification\r
+  UINT32  NRDY;     // 192  Reasons for DRDY = 0\r
+  UINT8   RM12[0x3C]; // 196  Reserved\r
+} OPREGION_MBOX1;\r
+#pragma pack ()\r
+\r
+//\r
+// OpRegion mailbox 2 (Software SCI Interface).\r
+//\r
+#pragma pack (1)\r
+typedef struct {\r
+  UINT32  SCIC;       // 0    Software SCI function number parameters\r
+  UINT32  PARM;       // 4    Software SCI additional parameters\r
+  UINT32  DSLP;       // 8    Driver sleep timeout\r
+  UINT8   RM21[0xF4]; // 12   Reserved\r
+} OPREGION_MBOX2;\r
+#pragma pack ()\r
+\r
+//\r
+// OpRegion mailbox 3 (Power Conservation).\r
+//\r
+#pragma pack (1)\r
+typedef struct {\r
+  UINT32  ARDY;       // 0    Driver readiness\r
+  UINT32  ASLC;       // 4    ASLE interrupt command / status\r
+  UINT32  TCHE;       // 8    Technology enabled indicator\r
+  UINT32  ALSI;       // 12   Current ALS illuminance reading\r
+  UINT32  BCLP;       // 16   Backlight britness to set\r
+  UINT32  PFIT;       // 20   Panel fitting Current State or Request\r
+  UINT32  CBLV;       // 24   Brightness Current State\r
+  UINT16  BCLM[0x14]; // 28   Backlight Brightness Level Duty Cycle Mapping Table\r
+  UINT32  CPFM;       // 68   Panel Fitting Current Mode\r
+  UINT32  EPFM;       // 72   Enabled Panel Fitting Mode\r
+  UINT8   PLUT[0x4A]; // 76   Panel Look Up Table\r
+  UINT32  PFMB;       // 150  PWM Frequency and Minimum Brightness\r
+  UINT32  CCDV;       // 154  Color Correction Default Values\r
+  UINT32  PCFT;       // 158  Power Conservation Features\r
+  UINT8   RM31[0x5E]; // 162  Reserved\r
+} OPREGION_MBOX3;\r
+#pragma pack ()\r
+\r
+//\r
+// OpRegion mailbox 4 (VBT).\r
+//\r
+#pragma pack (1)\r
+typedef struct {\r
+  UINT8 GVD1[0x1800]; // 6K Reserved\r
+} OPREGION_VBT;\r
+#pragma pack ()\r
+\r
+#pragma pack (1)\r
+typedef struct {\r
+  UINT8 EDIDOVRD[0x400]; // 6K Edid overriding data\r
+} OPREGION_MBOX5;\r
+#pragma pack ()\r
+//\r
+// Entire OpRegion\r
+//\r
+#pragma pack (1)\r
+typedef struct {\r
+  OPREGION_HEADER  Header; // OpRegion header\r
+  OPREGION_MBOX1   MBox1;  // Mailbox 1: Public ACPI Methods\r
+  OPREGION_MBOX2   MBox2;  // Mailbox 2: Software SCI Inteface\r
+  OPREGION_MBOX3   MBox3;  // Mailbox 3: Power Conservation\r
+  OPREGION_VBT        VBT;    // VBT: Video BIOS Table (OEM customizable data)\r
+  OPREGION_MBOX5   MBox5;\r
+} IGD_OPREGION_STRUC;\r
+#pragma pack ()\r
+\r
+//\r
+// Protocol data structure definition\r
+//\r
+struct _IGD_OPREGION_PROTOCOL {\r
+  IGD_OPREGION_STRUC    *OpRegion;\r
+};\r
+\r
+#endif\r

diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/NorthCluster/Include/Protocol/MemInfo.h b/Vlv2DeviceRefCodePkg/ValleyView2Soc/NorthCluster/Include/Protocol/MemInfo.h
new file mode 100644 (file)
index 0000000..74e31d4
--- /dev/null
+++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/NorthCluster/Include/Protocol/MemInfo.h
@@ -0,0 +1,89 @@
+\r
+/*++\r
+\r
+Copyright (c)  1999  - 2014, Intel Corporation. All rights reserved\r
+\r
+  This program and the accompanying materials are licensed and made available under\r
+  the terms and conditions of the BSD License that accompanies this distribution.\r
+  The full text of the license may be found at\r
+  http://opensource.org/licenses/bsd-license.php.\r
+\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+Module Name:\r
+\r
+  MemInfo.h\r
+\r
+Abstract:\r
+\r
+  This protocol provides the memory information data, such as\r
+  total physical memory size, memory frequency, memory size\r
+  of each dimm and rank.\r
+\r
+  This protocol is EFI compatible.\r
+\r
+--*/\r
+\r
+#ifndef _MEM_INFO_PROTOCOL_H_\r
+#define _MEM_INFO_PROTOCOL_H_\r
+\r
+//\r
+// Define the  protocol GUID\r
+//\r
+#define MEM_INFO_PROTOCOL_GUID \\r
+  { \\r
+    0x6f20f7c8, 0xe5ef, 0x4f21, 0x8d, 0x19, 0xed, 0xc5, 0xf0, 0xc4, 0x96, 0xae \\r
+  }\r
+\r
+//\r
+// Extern the GUID for protocol users.\r
+//\r
+extern EFI_GUID                   gMemInfoProtocolGuid;\r
+\r
+//\r
+// Forward reference for ANSI C compatibility\r
+//\r
+typedef struct _MEM_INFO_PROTOCOL MEM_INFO_PROTOCOL;\r
+\r
+//\r
+// Protocol definitions\r
+//\r
+\r
+#define CH_NUM    2\r
+#define DIMM_NUM  1\r
+#define RANK_NUM  2\r
+\r
+#pragma pack(1)\r
+typedef struct {\r
+  UINT32  memSize;\r
+  UINT8   ddrFreq;\r
+  UINT8   ddrType;\r
+  BOOLEAN EccSupport;\r
+  UINT16  dimmSize[CH_NUM * DIMM_NUM];\r
+  UINT8   reserved;\r
+  UINT16   reserved2;\r
+} MEMORY_INFO_DATA;\r
+#pragma pack()\r
+\r
+/*++\r
+Data definition:\r
+\r
+  memSize         Total physical memory size\r
+  ddrFreq         DDR Frequency\r
+  EccSupport      ECC Support\r
+  dimmSize        Dimm Size\r
+  DimmExist       Dimm Present or not\r
+  RankInDimm      No. of ranks in a dimm\r
+\r
+--*/\r
+\r
+//\r
+// Protocol definition\r
+//\r
+struct _MEM_INFO_PROTOCOL {\r
+  MEMORY_INFO_DATA  MemInfoData;\r
+};\r
+\r
+#endif\r

diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/NorthCluster/Include/Protocol/PlatformGopPolicy.h b/Vlv2DeviceRefCodePkg/ValleyView2Soc/NorthCluster/Include/Protocol/PlatformGopPolicy.h
new file mode 100644 (file)
index 0000000..7e948c7
--- /dev/null
+++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/NorthCluster/Include/Protocol/PlatformGopPolicy.h
@@ -0,0 +1,73 @@
+/*++\r
+\r
+Copyright (c)  1999  - 2014, Intel Corporation. All rights reserved\r
+\r
+  This program and the accompanying materials are licensed and made available under\r
+  the terms and conditions of the BSD License that accompanies this distribution.\r
+  The full text of the license may be found at\r
+  http://opensource.org/licenses/bsd-license.php.\r
+\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+--*/\r
+\r
+/** @file\r
+**/\r
+\r
+#ifndef _PLATFORM_GOP_POLICY_PROTOCOL_H_\r
+#define _PLATFORM_GOP_POLICY_PROTOCOL_H_\r
+\r
+#define EFI_PLATFORM_GOP_POLICY_PROTOCOL_GUID \\r
+  { 0xec2e931b, 0x3281, 0x48a5, 0x81, 0x7, 0xdf, 0x8a, 0x8b, 0xed, 0x3c, 0x5d }\r
+\r
+#define EFI_BMP_IMAGE_GUID \\r
+  { 0x878AC2CC, 0x5343, 0x46F2, 0xB5, 0x63, 0x51, 0xF8, 0x9D, 0xAF, 0x56, 0xBA }\r
+\r
+#define PLATFORM_GOP_POLICY_PROTOCOL_REVISION_01 0x01\r
+#define PLATFORM_GOP_POLICY_PROTOCOL_REVISION_02 x0222\r
+\r
+#pragma pack(1)\r
+\r
+typedef enum {\r
+  LidClosed,\r
+  LidOpen,\r
+  LidStatusMax\r
+} LID_STATUS;\r
+\r
+typedef enum {\r
+  Docked,\r
+  UnDocked,\r
+  DockStatusMax\r
+} DOCK_STATUS;\r
+\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *GET_PLATFORM_LID_STATUS) (\r
+  OUT LID_STATUS *CurrentLidStatus\r
+  );\r
+\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *GET_VBT_DATA) (\r
+  OUT EFI_PHYSICAL_ADDRESS *VbtAddress,\r
+  OUT UINT32 *VbtSize\r
+  );\r
+\r
+#pragma pack()\r
+\r
+typedef struct _PLATFORM_GOP_POLICY_PROTOCOL {\r
+  UINT32                             Revision;\r
+  GET_PLATFORM_LID_STATUS            GetPlatformLidStatus;\r
+  GET_VBT_DATA                       GetVbtData;\r
+} PLATFORM_GOP_POLICY_PROTOCOL;\r
+\r
+//\r
+// Extern the GUID for protocol users.\r
+//\r
+extern EFI_GUID  gPlatformGOPPolicyGuid;\r
+\r
+extern EFI_GUID  gBmpImageGuid;\r
+\r
+#endif\r

diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/NorthCluster/Include/Protocol/VlvPlatformPolicy.h b/Vlv2DeviceRefCodePkg/ValleyView2Soc/NorthCluster/Include/Protocol/VlvPlatformPolicy.h
new file mode 100644 (file)
index 0000000..de98c59
--- /dev/null
+++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/NorthCluster/Include/Protocol/VlvPlatformPolicy.h
@@ -0,0 +1,111 @@
+\r
+/*++\r
+\r
+Copyright (c)  1999  - 2014, Intel Corporation. All rights reserved\r
+\r
+  This program and the accompanying materials are licensed and made available under\r
+  the terms and conditions of the BSD License that accompanies this distribution.\r
+  The full text of the license may be found at\r
+  http://opensource.org/licenses/bsd-license.php.\r
+\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+Module Name:\r
+\r
+  VlvPlatformPolicy.h\r
+\r
+Abstract:\r
+\r
+  Interface definition details between MCH and platform drivers during DXE phase.\r
+\r
+--*/\r
+\r
+#ifndef _VLV_PLATFORM_POLICY_H_\r
+#define _VLV_PLATFORM_POLICY_H_\r
+\r
+//\r
+// VLV Policy provided by platform for DXE phase {5BAB88BA-E0E2-4674-B6AD-B812F6881CD6}\r
+//\r
+#define DXE_VLV_PLATFORM_POLICY_GUID \\r
+  {0x5bab88ba, 0xe0e2, 0x4674, 0xb6, 0xad, 0xb8, 0x12, 0xf6, 0x88, 0x1c, 0xd6}\r
+\r
+//\r
+// Extern the GUID for protocol users.\r
+//\r
+extern EFI_GUID gDxeVlvPlatformPolicyGuid;\r
+\r
+//\r
+// Protocol revision number\r
+// Any backwards compatible changes to this protocol will result in an update in the revision number\r
+// Major changes will require publication of a new protocol\r
+//\r
+#define DXE_VLV_PLATFORM_POLICY_PROTOCOL_REVISION 0\r
+\r
+\r
+typedef struct {\r
+  UINT8  PFITStatus;\r
+  UINT8  IgdTheramlSupport;\r
+  UINT8  ALSEnabled;\r
+  UINT8  LidStatus;\r
+} IGD_PANEL_FEATURES;\r
+\r
+typedef struct {\r
+  UINT8   Reserved00;                     \r
+  UINT8   Reserved01;                     \r
+  UINT16  Reserved02;  \r
+  UINT16  Reserved03; \r
+  UINT16  Reserved04; \r
+  UINT16  Reserved05;  \r
+  UINT16  Reserved06;  \r
+  UINT16  Reserved07; \r
+  UINT16  Reserved08; \r
+  UINT16  Reserved09;  \r
+  UINT16  Reserved0A; \r
+  UINT16  Reserved0B;\r
+  UINT16  Reserved0C;\r
+  UINT16  Reserved0D;\r
+  UINT8   Reserved0E;\r
+  UINT8   Reserved0F;\r
+  UINT32  Reserved10;\r
+  UINT32  Reserved11;\r
+  UINT32  Reserved12;\r
+  UINT32  Reserved13;\r
+  UINT32  Reserved14;\r
+  UINT8   Reserved15;\r
+  UINT8   Reserved16;\r
+} DPTF_SETTINGS;\r
+\r
+//\r
+// MCH DXE Platform Policiy ==================================================\r
+//\r
+\r
+#define NO_AUDIO   0\r
+#define HD_AUDIO   1\r
+#define LPE_AUDIO  2\r
+\r
+typedef struct _DXE_VLV_PLATFORM_POLICY_PROTOCOL {\r
+  UINT8                   Revision;\r
+  IGD_PANEL_FEATURES      IgdPanelFeatures;\r
+  DPTF_SETTINGS           Reserved;\r
+  UINT8                   GraphicReserve00;\r
+  UINT8                   GraphicsPerfAnalyzers;\r
+  UINT8                   PwmReserved00;\r
+  UINT8                   PwmReserved01;  \r
+  UINT8                   PmSupport;\r
+  UINT8                   GraphicReserve01;\r
+  UINT8                   GfxPause;\r
+  UINT8                   GraphicsFreqReq;\r
+  UINT8                   GraphicReserve03;\r
+  UINT8                   GraphicReserve02;\r
+  UINT8                   GraphicReserve04;\r
+  UINT8                   PavpMode;\r
+  UINT8                   GraphicReserve05;\r
+  UINT8                   UlClockGating;\r
+  UINT8                   IdleReserve;\r
+  UINT8                   AudioTypeSupport;\r
+  UINT8                   GraphicReserve06;\r
+} DXE_VLV_PLATFORM_POLICY_PROTOCOL;\r
+\r
+#endif\r

diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/NorthCluster/Include/Valleyview.h b/Vlv2DeviceRefCodePkg/ValleyView2Soc/NorthCluster/Include/Valleyview.h
new file mode 100644 (file)
index 0000000..ccb4eb3
--- /dev/null
+++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/NorthCluster/Include/Valleyview.h
@@ -0,0 +1,61 @@
+\r
+/*++\r
+\r
+Copyright (c)  1999  - 2014, Intel Corporation. All rights reserved\r
+\r
+  This program and the accompanying materials are licensed and made available under\r
+  the terms and conditions of the BSD License that accompanies this distribution.\r
+  The full text of the license may be found at\r
+  http://opensource.org/licenses/bsd-license.php.\r
+\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+\r
+Module Name:\r
+\r
+  Valleyview.h\r
+\r
+Abstract:\r
+\r
+  This header file provides common definitions just for Valleyview-SOC using to avoid including extra module's file.\r
+--*/\r
+\r
+#ifndef _MC_H_INCLUDED_\r
+#define _MC_H_INCLUDED_\r
+/*\r
+< Extended Configuration Base Address.*/\r
+#define EC_BASE             0xE0000000\r
+\r
+//\r
+// DEVICE 0 (Memroy Controller Hub)\r
+//\r
+#define MC_BUS          0x00\r
+#define MC_DEV          0x00\r
+#define MC_DEV2         0x02\r
+#define MC_FUN          0x00\r
+// NC DEV 0 Vendor and Device IDs\r
+#define MC_VID          0x8086\r
+#define MC_DID_OFFSET   0x2         //Device Identification\r
+#define MC_GGC_OFFSET   0x50        //GMCH Graphics Control Register\r
+\r
+//\r
+// Device 2 Register Equates\r
+//\r
+#define IGD_BUS             0x00\r
+#define IGD_DEV             0x02\r
+#define IGD_FUN_0           0x00\r
+#define IGD_FUN_1           0x01\r
+#define IGD_DEV_FUN         (IGD_DEV << 3)\r
+#define IGD_BUS_DEV_FUN     (MC_BUS << 8) + IGD_DEV_FUN\r
+#define IGD_VID             0x8086\r
+#define IGD_DID             0xA001\r
+#define IGD_MGGC_OFFSET     0x0050      //GMCH Graphics Control Register 0x50\r
+#define IGD_BSM_OFFSET      0x005C      //Base of Stolen Memory\r
+#define IGD_SWSCI_OFFSET    0x00E0      //Software SCI 0xE0 2\r
+#define IGD_ASLE_OFFSET     0x00E4      //System Display Event Register 0xE4 4\r
+#define IGD_ASLS_OFFSET     0x00FC      // ASL Storage\r
+#define IGD_DID_QS          0x0BE2      //RCOverride -a: Fix the DID error\r
+\r
+#endif\r

diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/NorthCluster/Include/VlvAccess.h b/Vlv2DeviceRefCodePkg/ValleyView2Soc/NorthCluster/Include/VlvAccess.h
new file mode 100644 (file)
index 0000000..1a1326c
--- /dev/null
+++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/NorthCluster/Include/VlvAccess.h
@@ -0,0 +1,260 @@
+\r
+/*++\r
+\r
+Copyright (c)  1999  - 2014, Intel Corporation. All rights reserved\r
+\r
+  This program and the accompanying materials are licensed and made available under\r
+  the terms and conditions of the BSD License that accompanies this distribution.\r
+  The full text of the license may be found at\r
+  http://opensource.org/licenses/bsd-license.php.\r
+\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+\r
+Module Name:\r
+\r
+  vlvAccess.h\r
+\r
+Abstract:\r
+\r
+  Macros to simplify and abstract the interface to PCI configuration.\r
+\r
+--*/\r
+\r
+#ifndef _VLVACCESS_H_INCLUDED_\r
+#define _VLVACCESS_H_INCLUDED_\r
+\r
+#include "Valleyview.h"\r
+#include "VlvCommonDefinitions.h"\r
+#include <Library/IoLib.h>\r
+\r
+//\r
+// Memory Mapped IO access macros used by MSG BUS LIBRARY\r
+//\r
+#define MmioAddress( BaseAddr, Register ) \\r
+  ( (UINTN)BaseAddr + \\r
+    (UINTN)(Register) \\r
+  )\r
+\r
+\r
+//\r
+// UINT32\r
+//\r
+\r
+#define Mmio32Ptr( BaseAddr, Register ) \\r
+  ( (volatile UINT32 *)MmioAddress( BaseAddr, Register ) )\r
+\r
+#define Mmio32( BaseAddr, Register ) \\r
+  *Mmio32Ptr( BaseAddr, Register )\r
+\r
+#define Mmio32Or( BaseAddr, Register, OrData ) \\r
+  Mmio32( BaseAddr, Register ) = \\r
+    (UINT32) ( \\r
+      Mmio32( BaseAddr, Register ) | \\r
+      (UINT32)(OrData) \\r
+    )\r
+\r
+#define Mmio32And( BaseAddr, Register, AndData ) \\r
+  Mmio32( BaseAddr, Register ) = \\r
+    (UINT32) ( \\r
+      Mmio32( BaseAddr, Register ) & \\r
+      (UINT32)(AndData) \\r
+    )\r
+\r
+#define Mmio32AndThenOr( BaseAddr, Register, AndData, OrData ) \\r
+  Mmio32( BaseAddr, Register ) = \\r
+    (UINT32) ( \\r
+      ( Mmio32( BaseAddr, Register ) & \\r
+          (UINT32)(AndData) \\r
+      ) | \\r
+      (UINT32)(OrData) \\r
+    )\r
+\r
+//\r
+// UINT16\r
+//\r
+\r
+#define Mmio16Ptr( BaseAddr, Register ) \\r
+  ( (volatile UINT16 *)MmioAddress( BaseAddr, Register ) )\r
+\r
+#define Mmio16( BaseAddr, Register ) \\r
+  *Mmio16Ptr( BaseAddr, Register )\r
+\r
+#define Mmio16Or( BaseAddr, Register, OrData ) \\r
+  Mmio16( BaseAddr, Register ) = \\r
+    (UINT16) ( \\r
+      Mmio16( BaseAddr, Register ) | \\r
+      (UINT16)(OrData) \\r
+    )\r
+\r
+#define Mmio16And( BaseAddr, Register, AndData ) \\r
+  Mmio16( BaseAddr, Register ) = \\r
+    (UINT16) ( \\r
+      Mmio16( BaseAddr, Register ) & \\r
+      (UINT16)(AndData) \\r
+    )\r
+\r
+#define Mmio16AndThenOr( BaseAddr, Register, AndData, OrData ) \\r
+  Mmio16( BaseAddr, Register ) = \\r
+    (UINT16) ( \\r
+      ( Mmio16( BaseAddr, Register ) & \\r
+          (UINT16)(AndData) \\r
+      ) | \\r
+      (UINT16)(OrData) \\r
+    )\r
+\r
+//\r
+// UINT8\r
+//\r
+\r
+#define Mmio8Ptr( BaseAddr, Register ) \\r
+  ( (volatile UINT8 *)MmioAddress( BaseAddr, Register ) )\r
+\r
+#define Mmio8( BaseAddr, Register ) \\r
+  *Mmio8Ptr( BaseAddr, Register )\r
+\r
+#define Mmio8Or( BaseAddr, Register, OrData ) \\r
+  Mmio8( BaseAddr, Register ) = \\r
+    (UINT8) ( \\r
+      Mmio8( BaseAddr, Register ) | \\r
+      (UINT8)(OrData) \\r
+    )\r
+\r
+#define Mmio8And( BaseAddr, Register, AndData ) \\r
+  Mmio8( BaseAddr, Register ) = \\r
+    (UINT8) ( \\r
+      Mmio8( BaseAddr, Register ) & \\r
+      (UINT8)(AndData) \\r
+    )\r
+\r
+#define Mmio8AndThenOr( BaseAddr, Register, AndData, OrData ) \\r
+  Mmio8( BaseAddr, Register ) = \\r
+    (UINT8) ( \\r
+      ( Mmio8( BaseAddr, Register ) & \\r
+          (UINT8)(AndData) \\r
+        ) | \\r
+      (UINT8)(OrData) \\r
+    )\r
+\r
+//\r
+// MSG BUS API\r
+//\r
+\r
+#define MSG_BUS_ENABLED     0x000000F0\r
+#define MSGBUS_MASKHI       0xFFFFFF00\r
+#define MSGBUS_MASKLO       0x000000FF\r
+\r
+#define MESSAGE_BYTE_EN          BIT4\r
+#define MESSAGE_WORD_EN          BIT4 | BIT5\r
+#define MESSAGE_DWORD_EN         BIT4 | BIT5 | BIT6 | BIT7\r
+\r
+#define SIDEBAND_OPCODE          0x78\r
+#define MEMREAD_OPCODE           0x00000000\r
+#define MEMWRITE_OPCODE          0x01000000\r
+\r
+\r
+\r
+/***************************/\r
+//\r
+// Memory mapped PCI IO\r
+//\r
+\r
+#define PciCfgPtr(Bus, Device, Function, Register )\\r
+    (UINTN)(Bus << 20) + \\r
+    (UINTN)(Device << 15) + \\r
+    (UINTN)(Function << 12) + \\r
+    (UINTN)(Register)\r
+\r
+#define PciCfg32Read_CF8CFC(B,D,F,R) \\r
+  (UINT32)(IoOut32(0xCF8,(0x80000000|(B<<16)|(D<<11)|(F<<8)|(R))),IoIn32(0xCFC))\r
+\r
+#define PciCfg32Write_CF8CFC(B,D,F,R,Data) \\r
+  (IoOut32(0xCF8,(0x80000000|(B<<16)|(D<<11)|(F<<8)|(R))),IoOut32(0xCFC,Data))\r
+\r
+#define PciCfg32Or_CF8CFC(B,D,F,R,O) \\r
+  PciCfg32Write_CF8CFC(B,D,F,R, \\r
+    (PciCfg32Read_CF8CFC(B,D,F,R) | (O)))\r
+\r
+#define PciCfg32And_CF8CFC(B,D,F,R,A) \\r
+  PciCfg32Write_CF8CFC(B,D,F,R, \\r
+    (PciCfg32Read_CF8CFC(B,D,F,R) & (A)))\r
+\r
+#define PciCfg32AndThenOr_CF8CFC(B,D,F,R,A,O) \\r
+  PciCfg32Write_CF8CFC(B,D,F,R, \\r
+    (PciCfg32Read_CF8CFC(B,D,F,R) & (A)) | (O))\r
+\r
+//\r
+// Device 0, Function 0\r
+//\r
+#define McD0PciCfg64(Register)                              MmPci64           (0, MC_BUS, 0, 0, Register)\r
+#define McD0PciCfg64Or(Register, OrData)                    MmPci64Or         (0, MC_BUS, 0, 0, Register, OrData)\r
+#define McD0PciCfg64And(Register, AndData)                  MmPci64And        (0, MC_BUS, 0, 0, Register, AndData)\r
+#define McD0PciCfg64AndThenOr(Register, AndData, OrData)    MmPci64AndThenOr  (0, MC_BUS, 0, 0, Register, AndData, OrData)\r
+\r
+#define McD0PciCfg32(Register)                              MmPci32           (0, MC_BUS, 0, 0, Register)\r
+#define McD0PciCfg32Or(Register, OrData)                    MmPci32Or         (0, MC_BUS, 0, 0, Register, OrData)\r
+#define McD0PciCfg32And(Register, AndData)                  MmPci32And        (0, MC_BUS, 0, 0, Register, AndData)\r
+#define McD0PciCfg32AndThenOr(Register, AndData, OrData)    MmPci32AndThenOr  (0, MC_BUS, 0, 0, Register, AndData, OrData)\r
+\r
+#define McD0PciCfg16(Register)                              MmPci16           (0, MC_BUS, 0, 0, Register)\r
+#define McD0PciCfg16Or(Register, OrData)                    MmPci16Or         (0, MC_BUS, 0, 0, Register, OrData)\r
+#define McD0PciCfg16And(Register, AndData)                  MmPci16And        (0, MC_BUS, 0, 0, Register, AndData)\r
+#define McD0PciCfg16AndThenOr(Register, AndData, OrData)    MmPci16AndThenOr  (0, MC_BUS, 0, 0, Register, AndData, OrData)\r
+\r
+#define McD0PciCfg8(Register)                               MmPci8            (0, MC_BUS, 0, 0, Register)\r
+#define McD0PciCfg8Or(Register, OrData)                     MmPci8Or          (0, MC_BUS, 0, 0, Register, OrData)\r
+#define McD0PciCfg8And(Register, AndData)                   MmPci8And         (0, MC_BUS, 0, 0, Register, AndData)\r
+#define McD0PciCfg8AndThenOr( Register, AndData, OrData )   MmPci8AndThenOr   (0, MC_BUS, 0, 0, Register, AndData, OrData)\r
+\r
+\r
+//\r
+// Device 2, Function 0\r
+//\r
+#define McD2PciCfg64(Register)                              MmPci64           (0, MC_BUS, 2, 0, Register)\r
+#define McD2PciCfg64Or(Register, OrData)                    MmPci64Or         (0, MC_BUS, 2, 0, Register, OrData)\r
+#define McD2PciCfg64And(Register, AndData)                  MmPci64And        (0, MC_BUS, 2, 0, Register, AndData)\r
+#define McD2PciCfg64AndThenOr(Register, AndData, OrData)    MmPci64AndThenOr  (0, MC_BUS, 2, 0, Register, AndData, OrData)\r
+\r
+#define McD2PciCfg32(Register)                              MmPci32           (0, MC_BUS, 2, 0, Register)\r
+#define McD2PciCfg32Or(Register, OrData)                    MmPci32Or         (0, MC_BUS, 2, 0, Register, OrData)\r
+#define McD2PciCfg32And(Register, AndData)                  MmPci32And        (0, MC_BUS, 2, 0, Register, AndData)\r
+#define McD2PciCfg32AndThenOr(Register, AndData, OrData)    MmPci32AndThenOr  (0, MC_BUS, 2, 0, Register, AndData, OrData)\r
+\r
+#define McD2PciCfg16(Register)                              MmPci16           (0, MC_BUS, 2, 0, Register)\r
+#define McD2PciCfg16Or(Register, OrData)                    MmPci16Or         (0, MC_BUS, 2, 0, Register, OrData)\r
+#define McD2PciCfg16And(Register, AndData)                  MmPci16And        (0, MC_BUS, 2, 0, Register, AndData)\r
+#define McD2PciCfg16AndThenOr(Register, AndData, OrData)    MmPci16AndThenOr  (0, MC_BUS, 2, 0, Register, AndData, OrData)\r
+\r
+#define McD2PciCfg8(Register)                               MmPci8            (0, MC_BUS, 2, 0, Register)\r
+#define McD2PciCfg8Or(Register, OrData)                     MmPci8Or          (0, MC_BUS, 2, 0, Register, OrData)\r
+#define McD2PciCfg8And(Register, AndData)                   MmPci8And         (0, MC_BUS, 2, 0, Register, AndData)\r
+\r
+//\r
+// IO\r
+//\r
+\r
+#ifndef IoIn8\r
+\r
+#define IoIn8(Port) \\r
+  IoRead8(Port)\r
+\r
+#define IoIn16(Port) \\r
+  IoRead16(Port)\r
+\r
+#define IoIn32(Port) \\r
+  IoRead32(Port)\r
+\r
+#define IoOut8(Port, Data) \\r
+  IoWrite8(Port, Data)\r
+\r
+#define IoOut16(Port, Data) \\r
+  IoWrite16(Port, Data)\r
+\r
+#define IoOut32(Port, Data) \\r
+  IoWrite32(Port, Data)\r
+\r
+#endif\r
+\r
+#endif\r

diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/NorthCluster/Include/VlvCommonDefinitions.h b/Vlv2DeviceRefCodePkg/ValleyView2Soc/NorthCluster/Include/VlvCommonDefinitions.h
new file mode 100644 (file)
index 0000000..3203fc6
--- /dev/null
+++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/NorthCluster/Include/VlvCommonDefinitions.h
@@ -0,0 +1,258 @@
+\r
+/*++\r
+\r
+Copyright (c)  1999  - 2014, Intel Corporation. All rights reserved\r
+\r
+  This program and the accompanying materials are licensed and made available under\r
+  the terms and conditions of the BSD License that accompanies this distribution.\r
+  The full text of the license may be found at\r
+  http://opensource.org/licenses/bsd-license.php.\r
+\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+\r
+Module Name:\r
+\r
+  VlvCommonDefinitions.h\r
+\r
+Abstract:\r
+\r
+  Macros to simplify and abstract the interface to PCI configuration.\r
+\r
+--*/\r
+\r
+///\r
+/// PCI CONFIGURATION MAP REGISTER OFFSETS\r
+///\r
+#ifndef PCI_VID\r
+#define PCI_VID             0x0000  ///< Vendor ID Register\r
+#define PCI_DID             0x0002  ///< Device ID Register\r
+#define PCI_CMD             0x0004  ///< PCI Command Register\r
+#define PCI_STS             0x0006  ///< PCI Status Register\r
+#define PCI_RID             0x0008  ///< Revision ID Register\r
+#define PCI_IFT             0x0009  ///< Interface Type\r
+#define PCI_SCC             0x000A  ///< Sub Class Code Register\r
+#define PCI_BCC             0x000B  ///< Base Class Code Register\r
+#define PCI_CLS             0x000C  ///< Cache Line Size\r
+#define PCI_PMLT            0x000D  ///< Primary Master Latency Timer\r
+#define PCI_HDR             0x000E  ///< Header Type Register\r
+#define PCI_BIST            0x000F  ///< Built in Self Test Register\r
+#define PCI_BAR0            0x0010  ///< Base Address Register 0\r
+#define PCI_BAR1            0x0014  ///< Base Address Register 1\r
+#define PCI_BAR2            0x0018  ///< Base Address Register 2\r
+#define PCI_PBUS            0x0018  ///< Primary Bus Number Register\r
+#define PCI_SBUS            0x0019  ///< Secondary Bus Number Register\r
+#define PCI_SUBUS           0x001A  ///< Subordinate Bus Number Register\r
+#define PCI_SMLT            0x001B  ///< Secondary Master Latency Timer\r
+#define PCI_BAR3            0x001C  ///< Base Address Register 3\r
+#define PCI_IOBASE          0x001C  ///< I/O base Register\r
+#define PCI_IOLIMIT         0x001D  ///< I/O Limit Register\r
+#define PCI_SECSTATUS       0x001E  ///< Secondary Status Register\r
+#define PCI_BAR4            0x0020  ///< Base Address Register 4\r
+#define PCI_MEMBASE         0x0020  ///< Memory Base Register\r
+#define PCI_MEMLIMIT        0x0022  ///< Memory Limit Register\r
+#define PCI_BAR5            0x0024  ///< Base Address Register 5\r
+#define PCI_PRE_MEMBASE     0x0024  ///< Prefetchable memory Base register\r
+#define PCI_PRE_MEMLIMIT    0x0026  ///< Prefetchable memory Limit register\r
+#define PCI_PRE_MEMBASE_U   0x0028  ///< Prefetchable memory base upper 32 bits\r
+#define PCI_PRE_MEMLIMIT_U  0x002C  ///< Prefetchable memory limit upper 32 bits\r
+#define PCI_SVID            0x002C  ///< Subsystem Vendor ID\r
+#define PCI_SID             0x002E  ///< Subsystem ID\r
+#define PCI_IOBASE_U        0x0030  ///< I/O base Upper Register\r
+#define PCI_IOLIMIT_U       0x0032  ///< I/O Limit Upper Register\r
+#define PCI_CAPP            0x0034  ///< Capabilities Pointer\r
+#define PCI_EROM            0x0038  ///< Expansion ROM Base Address\r
+#define PCI_INTLINE         0x003C  ///< Interrupt Line Register\r
+#define PCI_INTPIN          0x003D  ///< Interrupt Pin Register\r
+#define PCI_MAXGNT          0x003E  ///< Max Grant Register\r
+#define PCI_BRIDGE_CNTL     0x003E  ///< Bridge Control Register\r
+#define PCI_MAXLAT          0x003F  ///< Max Latency Register\r
+#endif\r
+//\r
+// Bit Difinitions\r
+//\r
+#ifndef BIT0\r
+#define BIT0                     0x0001\r
+#define BIT1                     0x0002\r
+#define BIT2                     0x0004\r
+#define BIT3                     0x0008\r
+#define BIT4                     0x0010\r
+#define BIT5                     0x0020\r
+#define BIT6                     0x0040\r
+#define BIT7                     0x0080\r
+#define BIT8                     0x0100\r
+#define BIT9                     0x0200\r
+#define BIT10                    0x0400\r
+#define BIT11                    0x0800\r
+#define BIT12                    0x1000\r
+#define BIT13                    0x2000\r
+#define BIT14                    0x4000\r
+#define BIT15                    0x8000\r
+#define BIT16                    0x00010000\r
+#define BIT17                    0x00020000\r
+#define BIT18                    0x00040000\r
+#define BIT19                    0x00080000\r
+#define BIT20                    0x00100000\r
+#define BIT21                    0x00200000\r
+#define BIT22                    0x00400000\r
+#define BIT23                    0x00800000\r
+#define BIT24                    0x01000000\r
+#define BIT25                    0x02000000\r
+#define BIT26                    0x04000000\r
+#define BIT27                    0x08000000\r
+#define BIT28                    0x10000000\r
+#define BIT29                    0x20000000\r
+#define BIT30                    0x40000000\r
+#define BIT31                    0x80000000\r
+#endif\r
+\r
+#ifndef _PCIACCESS_H_INCLUDED_\r
+#define _PCIACCESS_H_INCLUDED_\r
+#ifndef PCI_EXPRESS_BASE_ADDRESS\r
+ #define PCI_EXPRESS_BASE_ADDRESS 0xE0000000\r
+#endif\r
+\r
+#ifndef MmPciAddress\r
+#define MmPciAddress( Segment, Bus, Device, Function, Register ) \\r
+  ( (UINTN)PCI_EXPRESS_BASE_ADDRESS + \\r
+    (UINTN)(Bus << 20) + \\r
+    (UINTN)(Device << 15) + \\r
+    (UINTN)(Function << 12) + \\r
+    (UINTN)(Register) \\r
+  )\r
+#endif\r
+\r
+//\r
+// UINT64\r
+//\r
+#define MmPci64Ptr( Segment, Bus, Device, Function, Register ) \\r
+  ( (volatile UINT64 *)MmPciAddress( Segment, Bus, Device, Function, Register ) )\r
+\r
+#define MmPci64( Segment, Bus, Device, Function, Register ) \\r
+  *MmPci64Ptr( Segment, Bus, Device, Function, Register )\r
+\r
+#define MmPci64Or( Segment, Bus, Device, Function, Register, OrData ) \\r
+  MmPci64( Segment, Bus, Device, Function, Register ) = \\r
+    (UINT64) ( \\r
+      MmPci64( Segment, Bus, Device, Function, Register ) | \\r
+      (UINT64)(OrData) \\r
+    )\r
+\r
+#define MmPci64And( Segment, Bus, Device, Function, Register, AndData ) \\r
+  MmPci64( Segment, Bus, Device, Function, Register ) = \\r
+    (UINT64) ( \\r
+      MmPci64( Segment, Bus, Device, Function, Register ) & \\r
+      (UINT64)(AndData) \\r
+    )\r
+\r
+#define MmPci64AndThenOr( Segment, Bus, Device, Function, Register, AndData, OrData ) \\r
+  MmPci64( Segment, Bus, Device, Function, Register ) = \\r
+    (UINT64) ( \\r
+      ( MmPci64( Segment, Bus, Device, Function, Register ) & \\r
+          (UINT64)(AndData) \\r
+      ) | \\r
+      (UINT64)(OrData) \\r
+    )\r
+\r
+//\r
+// UINT32\r
+//\r
+\r
+#define MmPci32Ptr( Segment, Bus, Device, Function, Register ) \\r
+  ( (volatile UINT32 *) MmPciAddress( Segment, Bus, Device, Function, Register ) )\r
+\r
+#define MmPci32( Segment, Bus, Device, Function, Register ) \\r
+  *MmPci32Ptr( Segment, Bus, Device, Function, Register )\r
+\r
+#define MmPci32Or( Segment, Bus, Device, Function, Register, OrData ) \\r
+  MmPci32( Segment, Bus, Device, Function, Register ) = \\r
+    (UINT32) ( \\r
+      MmPci32( Segment, Bus, Device, Function, Register ) | \\r
+      (UINT32)(OrData) \\r
+    )\r
+\r
+#define MmPci32And( Segment, Bus, Device, Function, Register, AndData ) \\r
+  MmPci32( Segment, Bus, Device, Function, Register ) = \\r
+    (UINT32) ( \\r
+      MmPci32( Segment, Bus, Device, Function, Register ) & \\r
+      (UINT32)(AndData) \\r
+    )\r
+\r
+#define MmPci32AndThenOr( Segment, Bus, Device, Function, Register, AndData, OrData ) \\r
+  MmPci32( Segment, Bus, Device, Function, Register ) = \\r
+    (UINT32) ( \\r
+      ( MmPci32( Segment, Bus, Device, Function, Register ) & \\r
+          (UINT32)(AndData) \\r
+      ) | \\r
+      (UINT32)(OrData) \\r
+    )\r
+\r
+//\r
+// UINT16\r
+//\r
+\r
+#define MmPci16Ptr( Segment, Bus, Device, Function, Register ) \\r
+  ( (volatile UINT16 *)MmPciAddress( Segment, Bus, Device, Function, Register ) )\r
+\r
+#define MmPci16( Segment, Bus, Device, Function, Register ) \\r
+  *MmPci16Ptr( Segment, Bus, Device, Function, Register )\r
+\r
+#define MmPci16Or( Segment, Bus, Device, Function, Register, OrData ) \\r
+  MmPci16( Segment, Bus, Device, Function, Register ) = \\r
+    (UINT16) ( \\r
+      MmPci16( Segment, Bus, Device, Function, Register ) | \\r
+      (UINT16)(OrData) \\r
+    )\r
+\r
+#define MmPci16And( Segment, Bus, Device, Function, Register, AndData ) \\r
+  MmPci16( Segment, Bus, Device, Function, Register ) = \\r
+    (UINT16) ( \\r
+      MmPci16( Segment, Bus, Device, Function, Register ) & \\r
+      (UINT16)(AndData) \\r
+    )\r
+\r
+#define MmPci16AndThenOr( Segment, Bus, Device, Function, Register, AndData, OrData ) \\r
+  MmPci16( Segment, Bus, Device, Function, Register ) = \\r
+    (UINT16) ( \\r
+      ( MmPci16( Segment, Bus, Device, Function, Register ) & \\r
+          (UINT16)(AndData) \\r
+      ) | \\r
+      (UINT16)(OrData) \\r
+    )\r
+\r
+//\r
+// UINT8\r
+//\r
+\r
+#define MmPci8Ptr( Segment, Bus, Device, Function, Register ) \\r
+  ( (volatile UINT8 *)MmPciAddress( Segment, Bus, Device, Function, Register ) )\r
+\r
+#define MmPci8( Segment, Bus, Device, Function, Register ) \\r
+  *MmPci8Ptr( Segment, Bus, Device, Function, Register )\r
+\r
+#define MmPci8Or( Segment, Bus, Device, Function, Register, OrData ) \\r
+  MmPci8( Segment, Bus, Device, Function, Register ) = \\r
+    (UINT8) ( \\r
+      MmPci8( Segment, Bus, Device, Function, Register ) | \\r
+      (UINT8)(OrData) \\r
+    )\r
+\r
+#define MmPci8And( Segment, Bus, Device, Function, Register, AndData ) \\r
+  MmPci8( Segment, Bus, Device, Function, Register ) = \\r
+    (UINT8) ( \\r
+      MmPci8( Segment, Bus, Device, Function, Register ) & \\r
+      (UINT8)(AndData) \\r
+    )\r
+\r
+#define MmPci8AndThenOr( Segment, Bus, Device, Function, Register, AndData, OrData ) \\r
+  MmPci8( Segment, Bus, Device, Function, Register ) = \\r
+    (UINT8) ( \\r
+      ( MmPci8( Segment, Bus, Device, Function, Register ) & \\r
+          (UINT8)(AndData) \\r
+        ) | \\r
+      (UINT8)(OrData) \\r
+    )\r
+\r
+#endif\r

diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Guid/PchInitVar.h b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Guid/PchInitVar.h
new file mode 100644 (file)
index 0000000..e6d2321
--- /dev/null
+++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Guid/PchInitVar.h
@@ -0,0 +1,54 @@
+/*++\r
+\r
+Copyright (c) 2011  - 2014, Intel Corporation. All rights reserved\r
+\r
+  This program and the accompanying materials are licensed and made available under\r
+  the terms and conditions of the BSD License that accompanies this distribution.\r
+  The full text of the license may be found at\r
+  http://opensource.org/licenses/bsd-license.php.\r
+\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+\r
+Module Name:\r
+\r
+  PchInitVar.h\r
+\r
+Abstract:\r
+\r
+  This file defines variable shared between PCH Init DXE driver and PCH\r
+  Init S3 Resume PEIM.\r
+\r
+--*/\r
+#ifndef _PCH_INIT_VAR_H_\r
+#define _PCH_INIT_VAR_H_\r
+\r
+#include <Protocol/PchPlatformPolicy.h>\r
+//\r
+// Define the PCH Init Var GUID\r
+//\r
+#define PCH_INIT_VARIABLE_GUID {0xe6c2f70a, 0xb604, 0x4877,{0x85, 0xba, 0xde, 0xec, 0x89, 0xe1, 0x17, 0xeb}}\r
+//\r
+// Extern the GUID for PPI users.\r
+//\r
+extern EFI_GUID gPchInitVariableGuid;\r
+\r
+#define PCH_INIT_VARIABLE_NAME  L"PchInit"\r
+\r
+//\r
+// Define the Pch Init Variable structure\r
+//\r
+typedef struct {\r
+  UINT32  StorePosition;\r
+  UINT32  ExecutePosition;\r
+} PCH_S3_PARAMETER_HEADER;\r
+\r
+#pragma pack(1)\r
+typedef struct _PCH_INIT_VARIABLE {\r
+  PCH_S3_PARAMETER_HEADER *PchS3Parameter;\r
+} PCH_INIT_VARIABLE;\r
+#pragma pack()\r
+\r
+#endif\r

diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Guid/SataControllerGuid.h b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Guid/SataControllerGuid.h
new file mode 100644 (file)
index 0000000..52ce58e
--- /dev/null
+++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Guid/SataControllerGuid.h
@@ -0,0 +1,40 @@
+/*++\r
+\r
+Copyright (c)  2009  - 2014, Intel Corporation. All rights reserved\r
+\r
+  This program and the accompanying materials are licensed and made available under\r
+  the terms and conditions of the BSD License that accompanies this distribution.\r
+  The full text of the license may be found at\r
+  http://opensource.org/licenses/bsd-license.php.\r
+\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+\r
+Module Name:\r
+\r
+  SataControllerGuid.h\r
+\r
+Abstract:\r
+\r
+  GUID for use in describing SataController\r
+\r
+--*/\r
+#ifndef _SERIAL_ATA_CONTROLLER_GUID_H_\r
+#define _SERIAL_ATA_CONTROLLER_GUID_H_\r
+\r
+#ifdef ECP_FLAG\r
+#define PCH_SATA_CONTROLLER_DRIVER_GUID \\r
+  { \\r
+    0xbb929da9, 0x68f7, 0x4035, 0xb2, 0x2c, 0xa3, 0xbb, 0x3f, 0x23, 0xda, 0x55 \\r
+  }\r
+#else\r
+#define PCH_SATA_CONTROLLER_DRIVER_GUID \\r
+  {\\r
+    0xbb929da9, 0x68f7, 0x4035, 0xb2, 0x2c, 0xa3, 0xbb, 0x3f, 0x23, 0xda, 0x55 \}\r
+\r
+#endif\r
+\r
+extern EFI_GUID gSataControllerDriverGuid;\r
+#endif\r

diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Guid/SmbusArpMap.h b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Guid/SmbusArpMap.h
new file mode 100644 (file)
index 0000000..4e69679
--- /dev/null
+++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Guid/SmbusArpMap.h
@@ -0,0 +1,36 @@
+//\r
+//\r
+/*++\r
+\r
+Copyright (c)  2009  - 2014, Intel Corporation. All rights reserved\r
+\r
+  This program and the accompanying materials are licensed and made available under\r
+  the terms and conditions of the BSD License that accompanies this distribution.\r
+  The full text of the license may be found at\r
+  http://opensource.org/licenses/bsd-license.php.\r
+\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+\r
+Module Name:\r
+\r
+  SmbusArpMap.h\r
+\r
+Abstract:\r
+\r
+  GUID for use in describing SMBus devices that were ARPed during PEI.\r
+\r
+--*/\r
+#ifndef _EFI_SMBUS_ARP_MAP_GUID_H_\r
+#define _EFI_SMBUS_ARP_MAP_GUID_H_\r
+\r
+#define EFI_SMBUS_ARP_MAP_GUID \\r
+  { \\r
+    0x707be83e, 0x0bf6, 0x40a5, 0xbe, 0x64, 0x34, 0xc0, 0x3a, 0xa0, 0xb8, 0xe2 \\r
+  }\r
+\r
+extern EFI_GUID gEfiSmbusArpMapGuid;\r
+\r
+#endif\r

diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Guid/Vlv2Variable.h b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Guid/Vlv2Variable.h
new file mode 100644 (file)
index 0000000..64d91f0
--- /dev/null
+++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Guid/Vlv2Variable.h
@@ -0,0 +1,34 @@
+/*++\r
+\r
+Copyright (c)  1999  - 2014, Intel Corporation. All rights reserved\r
+\r
+  This program and the accompanying materials are licensed and made available under\r
+  the terms and conditions of the BSD License that accompanies this distribution.\r
+  The full text of the license may be found at\r
+  http://opensource.org/licenses/bsd-license.php.\r
+\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+\r
+Module Name:\r
+\r
+  Vlv2Variable.h\r
+\r
+Abstract:\r
+\r
+  GUID used to define ValleyView2 variable.\r
+\r
+--*/\r
+\r
+#ifndef _VLV2_VARIABLE_GUID_H_\r
+#define _VLV2_VARIABLE_GUID_H_\r
+\r
+#define EFI_VLV2_VARIABLE \\r
+  { \\r
+    0x10ba6bbe, 0xa97e, 0x41c3, {0x9a, 0x07, 0x60, 0x7a, 0xd9, 0xbd, 0x60, 0xe5 } \\r
+  }\r
+extern EFI_GUID gEfiVlv2VariableGuid;\r
+\r
+#endif\r

diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/IndustryStandard/CeAta.h b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/IndustryStandard/CeAta.h
new file mode 100644 (file)
index 0000000..b641ccb
--- /dev/null
+++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/IndustryStandard/CeAta.h
@@ -0,0 +1,132 @@
+/*++\r
+\r
+Copyright (c)  1999  - 2014, Intel Corporation. All rights reserved\r
+\r
+  This program and the accompanying materials are licensed and made available under\r
+  the terms and conditions of the BSD License that accompanies this distribution.\r
+  The full text of the license may be found at\r
+  http://opensource.org/licenses/bsd-license.php.\r
+\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+--*/\r
+\r
+\r
+/*++\r
+\r
+Module Name:\r
+\r
+  CEATA.h\r
+\r
+Abstract:\r
+\r
+  Header file for chipset CE-AT spec.\r
+\r
+--*/\r
+\r
+#ifndef _CE_ATA_H\r
+#define _CE_ATA_H\r
+\r
+#pragma pack(1)\r
+\r
+\r
+#define  DATA_UNIT_SIZE       512\r
+\r
+\r
+#define  CMD60                60\r
+#define  CMD61                61\r
+\r
+\r
+#define RW_MULTIPLE_REGISTER  CMD60\r
+#define RW_MULTIPLE_BLOCK     CMD61\r
+\r
+\r
+#define CE_ATA_SIG_CE         0xCE\r
+#define CE_ATA_SIG_AA         0xAA\r
+\r
+\r
+#define Reg_Features_Exp      01\r
+#define Reg_SectorCount_Exp   02\r
+#define Reg_LBALow_Exp        03\r
+#define Reg_LBAMid_Exp        04\r
+#define Reg_LBAHigh_Exp       05\r
+#define Reg_Control           06\r
+#define Reg_Features_Error    09\r
+#define Reg_SectorCount       10\r
+#define Reg_LBALow            11\r
+#define Reg_LBAMid            12\r
+#define Reg_LBAHigh           13\r
+#define Reg_Device_Head       14\r
+#define Reg_Command_Status    15\r
+\r
+#define Reg_scrTempC          0x80\r
+#define Reg_scrTempMaxP       0x84\r
+#define Reg_scrTempMinP       0x88\r
+#define Reg_scrStatus         0x8C\r
+#define Reg_scrReallocsA      0x90\r
+#define Reg_scrERetractsA     0x94\r
+#define Reg_scrCapabilities   0x98\r
+#define Reg_scrControl        0xC0\r
+\r
+\r
+\r
+typedef struct {\r
+  UINT8  Reserved0;\r
+  UINT8  Features_Exp;\r
+  UINT8  SectorCount_Exp;\r
+  UINT8  LBALow_Exp;\r
+  UINT8  LBAMid_Exp;\r
+  UINT8  LBAHigh_Exp;\r
+  UINT8  Control;\r
+  UINT8  Reserved1[2];\r
+  UINT8  Features_Error;\r
+  UINT8  SectorCount;\r
+  UINT8  LBALow;\r
+  UINT8  LBAMid;\r
+  UINT8  LBAHigh;\r
+  UINT8  Device_Head;\r
+  UINT8  Command_Status;\r
+} TASK_FILE;\r
+\r
+\r
+//\r
+//Reduced ATA command set\r
+//\r
+#define IDENTIFY_DEVICE       0xEC\r
+#define READ_DMA_EXT          0x25\r
+#define WRITE_DMA_EXT         0x35\r
+#define STANDBY_IMMEDIATE     0xE0\r
+#define FLUSH_CACHE_EXT       0xEA\r
+\r
+\r
+\r
+typedef struct {\r
+  UINT16  Reserved0[10];\r
+  UINT16  SerialNumber[10];\r
+  UINT16  Reserved1[3];\r
+  UINT16  FirmwareRevision[4];\r
+  UINT16  ModelNumber[20];\r
+  UINT16  Reserved2[33];\r
+  UINT16  MajorVersion;\r
+  UINT16  Reserved3[19];\r
+  UINT16  MaximumLBA[4];\r
+  UINT16  Reserved4[2];\r
+  UINT16  Sectorsize;\r
+  UINT16  Reserved5;\r
+  UINT16  DeviceGUID[4];\r
+  UINT16  Reserved6[94];\r
+  UINT16  Features;\r
+  UINT16  MaxWritesPerAddress;\r
+  UINT16  Reserved7[47];\r
+  UINT16  IntegrityWord;\r
+} IDENTIFY_DEVICE_DATA;\r
+\r
+\r
+\r
+\r
+\r
+#pragma pack()\r
+\r
+#endif\r

diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/IndustryStandard/Mmc.h b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/IndustryStandard/Mmc.h
new file mode 100644 (file)
index 0000000..2d5427a
--- /dev/null
+++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/IndustryStandard/Mmc.h
@@ -0,0 +1,355 @@
+/*++\r
+\r
+Copyright (c)  1999  - 2014, Intel Corporation. All rights reserved\r
+\r
+  This program and the accompanying materials are licensed and made available under\r
+  the terms and conditions of the BSD License that accompanies this distribution.\r
+  The full text of the license may be found at\r
+  http://opensource.org/licenses/bsd-license.php.\r
+\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+--*/\r
+\r
+\r
+/*++\r
+\r
+Module Name:\r
+\r
+  MMC.h\r
+\r
+Abstract:\r
+\r
+  Header file for Industry MMC 4.2 spec.\r
+\r
+--*/\r
+\r
+#ifndef _MMC_H\r
+#define _MMC_H\r
+\r
+#pragma pack(1)\r
+//\r
+//Command definition\r
+//\r
+\r
+#define  CMD0              0\r
+#define  CMD1              1\r
+#define  CMD2              2\r
+#define  CMD3              3\r
+#define  CMD4              4\r
+#define  CMD6              6\r
+#define  CMD7              7\r
+#define  CMD8              8\r
+#define  CMD9              9\r
+#define  CMD10             10\r
+#define  CMD11             11\r
+#define  CMD12             12\r
+#define  CMD13             13\r
+#define  CMD14             14\r
+#define  CMD15             15\r
+#define  CMD16             16\r
+#define  CMD17             17\r
+#define  CMD18             18\r
+#define  CMD19             19\r
+#define  CMD20             20\r
+#define  CMD23             23\r
+#define  CMD24             24\r
+#define  CMD25             25\r
+#define  CMD26             26\r
+#define  CMD27             27\r
+#define  CMD28             28\r
+#define  CMD29             29\r
+#define  CMD30             30\r
+#define  CMD35             35\r
+#define  CMD36             36\r
+#define  CMD38             38\r
+#define  CMD39             39\r
+#define  CMD40             40\r
+#define  CMD42             42\r
+#define  CMD55             55\r
+#define  CMD56             56\r
+\r
+\r
+\r
+#define  GO_IDLE_STATE           CMD0\r
+#define  SEND_OP_COND            CMD1\r
+#define  ALL_SEND_CID            CMD2\r
+#define  SET_RELATIVE_ADDR       CMD3\r
+#define  SET_DSR                 CMD4\r
+#define  SWITCH                  CMD6\r
+#define  SELECT_DESELECT_CARD    CMD7\r
+#define  SEND_EXT_CSD            CMD8\r
+#define  SEND_CSD                CMD9\r
+#define  SEND_CID                CMD10\r
+#define  READ_DAT_UNTIL_STOP     CMD11\r
+#define  STOP_TRANSMISSION       CMD12\r
+#define  SEND_STATUS             CMD13\r
+#define  BUSTEST_R               CMD14\r
+#define  GO_INACTIVE_STATE       CMD15\r
+#define  SET_BLOCKLEN            CMD16\r
+#define  READ_SINGLE_BLOCK       CMD17\r
+#define  READ_MULTIPLE_BLOCK     CMD18\r
+#define  BUSTEST_W               CMD19\r
+#define  WRITE_DAT_UNTIL_STOP    CMD20\r
+#define  SET_BLOCK_COUNT         CMD23\r
+#define  WRITE_BLOCK             CMD24\r
+#define  WRITE_MULTIPLE_BLOCK    CMD25\r
+#define  PROGRAM_CID             CMD26\r
+#define  PROGRAM_CSD             CMD27\r
+#define  SET_WRITE_PROT          CMD28\r
+#define  CLR_WRITE_PROT          CMD29\r
+#define  SEND_WRITE_PROT         CMD30\r
+#define  ERASE_GROUP_START       CMD35\r
+#define  ERASE_GROUP_END         CMD36\r
+#define  ERASE                   CMD38\r
+#define  FAST_IO                 CMD39\r
+#define  GO_IRQ_STATE            CMD40\r
+#define  LOCK_UNLOCK             CMD42\r
+#define  APP_CMD                 CMD55\r
+#define  GEN_CMD                 CMD56\r
+\r
+#define B_PERM_WP_DIS            0x10\r
+#define B_PWR_WP_EN              0x01\r
+#define US_PERM_WP_DIS           0x10\r
+#define US_PWR_WP_EN             0x01\r
+\r
+#define FREQUENCY_OD            (400 * 1000)\r
+#define FREQUENCY_MMC_PP        (26 * 1000 * 1000)\r
+#define FREQUENCY_MMC_PP_HIGH   (52 * 1000 * 1000)\r
+\r
+#define DEFAULT_DSR_VALUE        0x404\r
+\r
+//\r
+//Registers definition\r
+//\r
+\r
+typedef struct {\r
+  UINT32  Reserved0:   7;  // 0\r
+  UINT32  V170_V195:   1;  // 1.70V - 1.95V\r
+  UINT32  V200_V260:   7;  // 2.00V - 2.60V\r
+  UINT32  V270_V360:   9;  // 2.70V - 3.60V\r
+  UINT32  Reserved1:   5;  // 0\r
+  UINT32  AccessMode:  2;  // 00b (byte mode), 10b (sector mode)\r
+  UINT32  Busy:        1;  // This bit is set to LOW if the card has not finished the power up routine\r
+} OCR;\r
+\r
+\r
+typedef struct {\r
+  UINT8   NotUsed:     1; //  1\r
+  UINT8   CRC:         7; //  CRC7 checksum\r
+  UINT8   MDT;            //  Manufacturing date\r
+  UINT32  PSN;            //  Product serial number\r
+  UINT8   PRV;            //  Product revision\r
+  UINT8   PNM[6];         //  Product name\r
+  UINT16  OID;            //  OEM/Application ID\r
+  UINT8   MID;            //  Manufacturer ID\r
+} CID;\r
+\r
+\r
+typedef struct {\r
+  UINT8   NotUsed:            1; //  1 [0:0]\r
+  UINT8   CRC:                7; //  CRC [7:1]\r
+  UINT8   ECC:                2; //  ECC code [9:8]\r
+  UINT8   FILE_FORMAT:        2; //  File format [11:10]\r
+  UINT8   TMP_WRITE_PROTECT:  1; //  Temporary write protection [12:12]\r
+  UINT8   PERM_WRITE_PROTECT: 1; //  Permanent write protection [13:13]\r
+  UINT8   COPY:               1; //  Copy flag (OTP) [14:14]\r
+  UINT8   FILE_FORMAT_GRP:    1; //  File format group [15:15]\r
+  UINT16  CONTENT_PROT_APP:   1; //  Content protection application [16:16]\r
+  UINT16  Reserved0:          4; //  0 [20:17]\r
+  UINT16  WRITE_BL_PARTIAL:   1; //  Partial blocks for write allowed [21:21]\r
+  UINT16  WRITE_BL_LEN:       4; //  Max. write data block length [25:22]\r
+  UINT16  R2W_FACTOR:         3; //  Write speed factor [28:26]\r
+  UINT16  DEFAULT_ECC:        2; //  Manufacturer default ECC [30:29]\r
+  UINT16  WP_GRP_ENABLE:      1; //  Write protect group enable [31:31]\r
+  UINT32  WP_GRP_SIZE:        5; //  Write protect group size [36:32]\r
+  UINT32  ERASE_GRP_MULT:     5; //  Erase group size multiplier [41:37]\r
+  UINT32  ERASE_GRP_SIZE:     5; //  Erase group size [46:42]\r
+  UINT32  C_SIZE_MULT:        3; //  Device size multiplier [49:47]\r
+  UINT32  VDD_W_CURR_MAX:     3; //  Max. write current @ VDD max [52:50]\r
+  UINT32  VDD_W_CURR_MIN:     3; //  Max. write current @ VDD min [55:53]\r
+  UINT32  VDD_R_CURR_MAX:     3; //  Max. read current @ VDD max [58:56]\r
+  UINT32  VDD_R_CURR_MIN:     3; //  Max. read current @ VDD min [61:59]\r
+  UINT32  C_SIZELow2:         2;//  Device size [73:62]\r
+  UINT32  C_SIZEHigh10:       10;//  Device size [73:62]\r
+  UINT32  Reserved1:          2; //  0 [75:74]\r
+  UINT32  DSR_IMP:            1; //  DSR implemented [76:76]\r
+  UINT32  READ_BLK_MISALIGN:  1; //  Read block misalignment [77:77]\r
+  UINT32  WRITE_BLK_MISALIGN: 1; //  Write block misalignment [78:78]\r
+  UINT32  READ_BL_PARTIAL:    1; //  Partial blocks for read allowed [79:79]\r
+  UINT32  READ_BL_LEN:        4; //  Max. read data block length [83:80]\r
+  UINT32  CCC:                12;//  Card command classes [95:84]\r
+  UINT8   TRAN_SPEED          ; //  Max. bus clock frequency [103:96]\r
+  UINT8   NSAC                ; //  Data read access-time 2 in CLK cycles (NSAC*100) [111:104]\r
+  UINT8   TAAC                ; //  Data read access-time 1 [119:112]\r
+  UINT8   Reserved2:          2; //  0 [121:120]\r
+  UINT8   SPEC_VERS:          4; //  System specification version [125:122]\r
+  UINT8   CSD_STRUCTURE:      2; //  CSD structure [127:126]\r
+} CSD;\r
+\r
+typedef struct {\r
+  UINT8  Reserved133_0[134];     // [133:0] 0\r
+  UINT8  SEC_BAD_BLOCK_MGMNT;    // [134] Bad Block Management mode\r
+  UINT8  Reserved135;            // [135] 0\r
+  UINT8  ENH_START_ADDR[4];      // [139:136] Enhanced User Data Start Address\r
+  UINT8  ENH_SIZE_MULT[3];       // [142:140] Enhanced User Data Start Size\r
+  UINT8  GP_SIZE_MULT_1[3];      // [145:143] GPP1 Size\r
+  UINT8  GP_SIZE_MULT_2[3];      // [148:146] GPP2 Size\r
+  UINT8  GP_SIZE_MULT_3[3];      // [151:149] GPP3 Size\r
+  UINT8  GP_SIZE_MULT_4[3];      // [154:152] GPP4 Size\r
+  UINT8  PARTITION_SETTING_COMPLETED; // [155] Partitioning Setting\r
+  UINT8  PARTITIONS_ATTRIBUTES;  // [156] Partitions attributes\r
+  UINT8  MAX_ENH_SIZE_MULT[3];   // [159:157] GPP4 Start Size\r
+  UINT8  PARTITIONING_SUPPORT;   // [160] Partitioning Support\r
+  UINT8  HPI_MGMT;               // [161] HPI management\r
+  UINT8  RST_n_FUNCTION;         // [162] H/W reset function\r
+  UINT8  BKOPS_EN;               // [163] Enable background operations handshake\r
+  UINT8  BKOPS_START;            // [164] Manually start background operations\r
+  UINT8  Reserved165;            // [165] 0\r
+  UINT8  WR_REL_PARAM;           // [166] Write reliability parameter register\r
+  UINT8  WR_REL_SET;             // [167] Write reliability setting register\r
+  UINT8  RPMB_SIZE_MULT;         // [168] RPMB Size\r
+  UINT8  FW_CONFIG;              // [169] FW configuration\r
+  UINT8  Reserved170;            // [170] 0\r
+  UINT8  USER_WP;                // [171] User area write protection\r
+  UINT8  Reserved172;            // [172] 0\r
+  UINT8  BOOT_WP;                // [173] Boot area write protection\r
+  UINT8  Reserved174;            // [174] 0\r
+  UINT8  ERASE_GROUP_DEF;        // [175] High density erase group definition\r
+  UINT8  Reserved176;            // [176] 0\r
+  UINT8  BOOT_BUS_WIDTH;         // [177] Boot bus width\r
+  UINT8  BOOT_CONFIG_PROT;       // [178] Boot config protection\r
+  UINT8  PARTITION_CONFIG;       // [179] Partition config\r
+  UINT8  Reserved180;            // [180] 0\r
+  UINT8  ERASED_MEM_CONT;        // [181] Erased Memory Content\r
+  UINT8  Reserved182;            // [182] 0\r
+  UINT8  BUS_WIDTH;              // [183] Bus Width Mode\r
+  UINT8  Reserved184;            // [184] 0\r
+  UINT8  HS_TIMING;              // [185] High Speed Interface Timing\r
+  UINT8  Reserved186;            // [186] 0\r
+  UINT8  POWER_CLASS;            // [187] Power Class\r
+  UINT8  Reserved188;            // [188] 0\r
+  UINT8  CMD_SET_REV;            // [189] Command Set Revision\r
+  UINT8  Reserved190;            // [190] 0\r
+  UINT8  CMD_SET;                // [191] Command Set\r
+  UINT8  EXT_CSD_REV;            // [192] Extended CSD Revision\r
+  UINT8  Reserved193;            // [193] 0\r
+  UINT8  CSD_STRUCTURE;          // [194] CSD Structure Version\r
+  UINT8  Reserved195;            // [195] 0\r
+  UINT8  CARD_TYPE;              // [196] Card Type\r
+  UINT8  Reserved197;            // [197] 0\r
+  UINT8  OUT_OF_INTERRUPT_TIME;  // [198] Out-of-interrupt busy timing\r
+  UINT8  PARTITION_SWITCH_TIME;  // [199] Partition switching timing\r
+  UINT8  PWR_CL_52_195;          // [200] Power Class for 52MHz @ 1.95V\r
+  UINT8  PWR_CL_26_195;          // [201] Power Class for 26MHz @ 1.95V\r
+  UINT8  PWR_CL_52_360;          // [202] Power Class for 52MHz @ 3.6V\r
+  UINT8  PWR_CL_26_360;          // [203] Power Class for 26MHz @ 3.6V\r
+  UINT8  Reserved204;            // [204] 0\r
+  UINT8  MIN_PERF_R_4_26;        // [205] Minimum Read Performance for 4bit @26MHz\r
+  UINT8  MIN_PERF_W_4_26;        // [206] Minimum Write Performance for 4bit @26MHz\r
+  UINT8  MIN_PERF_R_8_26_4_52;   // [207] Minimum Read Performance for 8bit @26MHz/4bit @52MHz\r
+  UINT8  MIN_PERF_W_8_26_4_52;   // [208] Minimum Write Performance for 8bit @26MHz/4bit @52MHz\r
+  UINT8  MIN_PERF_R_8_52;        // [209] Minimum Read Performance for 8bit @52MHz\r
+  UINT8  MIN_PERF_W_8_52;        // [210] Minimum Write Performance for 8bit @52MHz\r
+  UINT8  Reserved211;            // [211] 0\r
+  UINT8  SEC_COUNT[4];           // [215:212] Sector Count\r
+  UINT8  Reserved216;            // [216] 0\r
+  UINT8  S_A_TIMEOUT;            // [217] Sleep/awake timeout\r
+  UINT8  Reserved218;            // [218] 0\r
+  UINT8  S_C_VCCQ;               // [219] Sleep current (VCCQ)\r
+  UINT8  S_C_VCC;                // [220] Sleep current (VCC)\r
+  UINT8  HC_WP_GRP_SIZE;         // [221] High-capacity write protect group size\r
+  UINT8  REL_WR_SEC_C;           // [222] Reliable write sector count\r
+  UINT8  ERASE_TIMEOUT_MULT;     // [223] High-capacity erase timeout\r
+  UINT8  HC_ERASE_GRP_SIZE;      // [224] High-capacity erase unit size\r
+  UINT8  ACC_SIZE;               // [225] Access size\r
+  UINT8  BOOT_SIZE_MULTI;        // [226] Boot partition size\r
+  UINT8  Reserved227;            // [227] 0\r
+  UINT8  BOOT_INFO;              // [228] Boot information\r
+  UINT8  SEC_TRIM_MULT;          // [229] Secure TRIM Multiplier\r
+  UINT8  SEC_ERASE_MULT;         // [230] Secure Erase Multiplier\r
+  UINT8  SEC_FEATURE_SUPPORT;    // [231] Secure Feature support\r
+  UINT8  TRIM_MULT;              // [232] TRIM Multiplier\r
+  UINT8  Reserved233;            // [233] 0\r
+  UINT8  MIN_PERF_DDR_R_8_52;    // [234] Min Read Performance for 8-bit @ 52MHz\r
+  UINT8  MIN_PERF_DDR_W_8_52;    // [235] Min Write Performance for 8-bit @ 52MHz\r
+  UINT8  Reserved237_236[2];     // [237:236] 0\r
+  UINT8  PWR_CL_DDR_52_195;      // [238] Power class for 52MHz, DDR at 1.95V\r
+  UINT8  PWR_CL_DDR_52_360;      // [239] Power class for 52MHz, DDR at 3.6V\r
+  UINT8  Reserved240;            // [240] 0\r
+  UINT8  INI_TIMEOUT_AP;         // [241] 1st initialization time after partitioning\r
+  UINT8  CORRECTLY_PRG_SECTORS_NUM[4]; // [245:242] Number of correctly programmed sectors\r
+  UINT8  BKOPS_STATUS;           // [246] Background operations status\r
+  UINT8  Reserved501_247[255];   // [501:247] 0\r
+  UINT8  BKOPS_SUPPORT;          // [502] Background operations support\r
+  UINT8  HPI_FEATURES;           // [503] HPI features\r
+  UINT8  S_CMD_SET;              // [504] Sector Count\r
+  UINT8  Reserved511_505[7];     // [511:505] Sector Count\r
+} EXT_CSD;\r
+\r
+\r
+//\r
+//Card Status definition\r
+//\r
+typedef struct {\r
+  UINT32  Reserved0:           2; //Reserved for Manufacturer Test Mode\r
+  UINT32  Reserved1:           2; //Reserved for Application Specific commands\r
+  UINT32  Reserved2:           1; //\r
+  UINT32  SAPP_CMD:            1; //\r
+  UINT32  Reserved3:           1; //Reserved\r
+  UINT32  SWITCH_ERROR:        1; //\r
+  UINT32  READY_FOR_DATA:      1; //\r
+  UINT32  CURRENT_STATE:       4; //\r
+  UINT32  ERASE_RESET:         1; //\r
+  UINT32  Reserved4:           1; //Reserved\r
+  UINT32  WP_ERASE_SKIP:       1; //\r
+  UINT32  CID_CSD_OVERWRITE:   1; //\r
+  UINT32  OVERRUN:             1; //\r
+  UINT32  UNDERRUN:            1; //\r
+  UINT32  ERROR:               1; //\r
+  UINT32  CC_ERROR:            1; //\r
+  UINT32  CARD_ECC_FAILED:     1; //\r
+  UINT32  ILLEGAL_COMMAND:     1; //\r
+  UINT32  COM_CRC_ERROR:       1; //\r
+  UINT32  LOCK_UNLOCK_FAILED:  1; //\r
+  UINT32  CARD_IS_LOCKED:      1; //\r
+  UINT32  WP_VIOLATION:        1; //\r
+  UINT32  ERASE_PARAM:         1; //\r
+  UINT32  ERASE_SEQ_ERROR:     1; //\r
+  UINT32  BLOCK_LEN_ERROR:     1; //\r
+  UINT32  ADDRESS_MISALIGN:    1; //\r
+  UINT32  ADDRESS_OUT_OF_RANGE:1; //\r
+} CARD_STATUS;\r
+\r
+typedef struct {\r
+  UINT32  CmdSet:              3;\r
+  UINT32  Reserved0:           5;\r
+  UINT32  Value:               8;\r
+  UINT32  Index:               8;\r
+  UINT32  Access:              2;\r
+  UINT32  Reserved1:           6;\r
+} SWITCH_ARGUMENT;\r
+\r
+#define CommandSet_Mode          0\r
+#define SetBits_Mode             1\r
+#define ClearBits_Mode           2\r
+#define WriteByte_Mode           3\r
+\r
+\r
+#define  Idle_STATE              0\r
+#define  Ready_STATE             1\r
+#define  Ident_STATE             2\r
+#define  Stby_STATE              3\r
+#define  Tran_STATE              4\r
+#define  Data_STATE              5\r
+#define  Rcv_STATE               6\r
+#define  Prg_STATE               7\r
+#define  Dis_STATE               8\r
+#define  Btst_STATE              9\r
+\r
+\r
+\r
+#pragma pack()\r
+#endif\r

diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/IndustryStandard/SdCard.h b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/IndustryStandard/SdCard.h
new file mode 100644 (file)
index 0000000..835800d
--- /dev/null
+++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/IndustryStandard/SdCard.h
@@ -0,0 +1,163 @@
+/*++\r
+\r
+Copyright (c)  1999  - 2014, Intel Corporation. All rights reserved\r
+\r
+  This program and the accompanying materials are licensed and made available under\r
+  the terms and conditions of the BSD License that accompanies this distribution.\r
+  The full text of the license may be found at\r
+  http://opensource.org/licenses/bsd-license.php.\r
+\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+--*/\r
+\r
+\r
+/*++\r
+Module Name:\r
+\r
+  SDCard.h\r
+\r
+Abstract:\r
+\r
+  Header file for Industry SD Card 2.0 spec.\r
+\r
+--*/\r
+\r
+#ifndef _SD_CARD_H\r
+#define _SD_CARD_H\r
+\r
+#include "Mmc.h"\r
+\r
+#pragma pack(1)\r
+\r
+#define CHECK_PATTERN     0xAA\r
+\r
+#define ACMD6             6\r
+#define ACMD13            13\r
+#define ACMD23            23\r
+#define ACMD41            41\r
+#define ACMD42            42\r
+#define ACMD51            51\r
+\r
+\r
+#define SWITCH_FUNC              CMD6\r
+#define SEND_IF_COND             CMD8\r
+\r
+\r
+#define SET_BUS_WIDTH            ACMD6\r
+#define SD_STATUS                ACMD13\r
+#define SET_WR_BLK_ERASE_COUNT   ACMD23\r
+#define SD_SEND_OP_COND          ACMD41\r
+#define SET_CLR_CARD_DETECT      ACMD42\r
+#define SEND_SCR                 ACMD51\r
+\r
+\r
+\r
+#define SD_BUS_WIDTH_1              0\r
+#define SD_BUS_WIDTH_4              2\r
+\r
+\r
+\r
+#define FREQUENCY_SD_PP        (25 * 1000 * 1000)\r
+#define FREQUENCY_SD_PP_HIGH   (50 * 1000 * 1000)\r
+\r
+\r
+#define SD_SPEC_10                  0\r
+#define SD_SPEC_11                  1\r
+#define SD_SPEC_20                  2\r
+\r
+\r
+#define VOLTAGE_27_36               0x1\r
+\r
+typedef struct {\r
+  UINT8   NotUsed:            1; //  1 [0:0]\r
+  UINT8   CRC:                7; //  CRC [7:1]\r
+  UINT8   ECC:                2; //  ECC code [9:8]\r
+  UINT8   FILE_FORMAT:        2; //  File format [11:10]\r
+  UINT8   TMP_WRITE_PROTECT:  1; //  Temporary write protection [12:12]\r
+  UINT8   PERM_WRITE_PROTECT: 1; //  Permanent write protection [13:13]\r
+  UINT8   COPY:               1; //  Copy flag (OTP) [14:14]\r
+  UINT8   FILE_FORMAT_GRP:    1; //  File format group [15:15]\r
+  UINT16  Reserved0:          5; //  0 [20:16]\r
+  UINT16  WRITE_BL_PARTIAL:   1; //  Partial blocks for write allowed [21:21]\r
+  UINT16  WRITE_BL_LEN:       4; //  Max. write data block length [25:22]\r
+  UINT16  R2W_FACTOR:         3; //  Write speed factor [28:26]\r
+  UINT16  DEFAULT_ECC:        2; //  Manufacturer default ECC [30:29]\r
+  UINT16  WP_GRP_ENABLE:      1; //  Write protect group enable [31:31]\r
+  UINT16  WP_GRP_SIZE:        7; //  Write protect group size [38:32]\r
+  UINT16  SECTOR_SIZE:        7; //  Erase sector size [45:39]\r
+  UINT16  ERASE_BLK_EN:       1; //  Erase single block enable [46:46]\r
+  UINT16  Reserved1:          1; //  0 [47:47]\r
+\r
+  UINT32  C_SIZE:             22; //  Device size [69:48]\r
+  UINT32  Reserved2:          6;  //  0 [75:70]\r
+  UINT32  DSR_IMP:            1;  //  DSR implemented [76:76]\r
+  UINT32  READ_BLK_MISALIGN:  1;  //  Read block misalignment [77:77]\r
+  UINT32  WRITE_BLK_MISALIGN: 1;  //  Write block misalignment [78:78]\r
+  UINT32  READ_BL_PARTIAL:    1;  //  Partial blocks for read allowed [79:79]\r
+\r
+  UINT16  READ_BL_LEN:        4;  //  Max. read data block length [83:80]\r
+  UINT16  CCC:                12; //  Card command classes [95:84]\r
+  UINT8   TRAN_SPEED          ;   //  Max. bus clock frequency [103:96]\r
+  UINT8   NSAC                ;   //  Data read access-time 2 in CLK cycles (NSAC*100) [111:104]\r
+  UINT8   TAAC                ;   //  Data read access-time 1 [119:112]\r
+  UINT8   Reserved3:          6;  //  0 [125:120]\r
+  UINT8   CSD_STRUCTURE:      2;  //  CSD structure [127:126]\r
+} CSD_SDV2;\r
+\r
+typedef struct {\r
+  UINT32  Reserved0;\r
+  UINT32  Reserved1:               16;\r
+  UINT32  SD_BUS_WIDTH:            4;\r
+  UINT32  SD_SECURITY:             3;\r
+  UINT32  DATA_STAT_AFTER_ERASE:   1;\r
+  UINT32  SD_SPEC:                 4;\r
+  UINT32  SCR_STRUCT:              4;\r
+} SCR;\r
+\r
+\r
+typedef struct {\r
+  UINT8   Reserved0[50];\r
+  UINT8   ERASE_OFFSET:               2;\r
+  UINT8   ERASE_TIMEOUT:              6;\r
+  UINT16  ERASE_SIZE;\r
+  UINT8   Reserved1:                  4;\r
+  UINT8   AU_SIZE:                    4;\r
+  UINT8   PERFORMANCE_MOVE;\r
+  UINT8   SPEED_CLASS;\r
+  UINT32  SIZE_OF_PROTECTED_AREA;\r
+  UINT32  SD_CARD_TYPE:              16;\r
+  UINT32  Reserved2:                 13;\r
+  UINT32  SECURED_MODE:               1;\r
+  UINT32  DAT_BUS_WIDTH:              2;\r
+} SD_STATUS_REG;\r
+\r
+\r
+\r
+typedef struct {\r
+  UINT8   Reserved0[34];\r
+  UINT16  Group1BusyStatus;\r
+  UINT16  Group2BusyStatus;\r
+  UINT16  Group3BusyStatus;\r
+  UINT16  Group4BusyStatus;\r
+  UINT16  Group5BusyStatus;\r
+  UINT16  Group6BusyStatus;\r
+  UINT8   DataStructureVersion;\r
+  UINT8   Group21Status;\r
+  UINT8   Group43Status;\r
+  UINT8   Group65Status;\r
+  UINT16  Group1Function;\r
+  UINT16  Group2Function;\r
+  UINT16  Group3Function;\r
+  UINT16  Group4Function;\r
+  UINT16  Group5Function;\r
+  UINT16  Group6Function;\r
+  UINT16  MaxCurrent;\r
+} SWITCH_STATUS;\r
+\r
+\r
+#pragma pack()\r
+#endif\r
+\r

diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Library/I2CLib.h b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Library/I2CLib.h
new file mode 100644 (file)
index 0000000..9173364
--- /dev/null
+++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Library/I2CLib.h
@@ -0,0 +1,175 @@
+/*++\r
+\r
+Copyright (c)  1999  - 2014, Intel Corporation. All rights reserved\r
+\r
+  This program and the accompanying materials are licensed and made available under\r
+  the terms and conditions of the BSD License that accompanies this distribution.\r
+  The full text of the license may be found at\r
+  http://opensource.org/licenses/bsd-license.php.\r
+\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+\r
+Module Name:\r
+\r
+  I2CRegs.h\r
+\r
+Abstract:\r
+\r
+  Register Definitions for I2C Driver/PEIM.\r
+\r
+--*/\r
+#include <Uefi.h>\r
+#include <Library/IoLib.h>\r
+\r
+#ifndef I2C_REGS_A0_H\r
+#define I2C_REGS_A0_H\r
+\r
+//\r
+// FIFO write workaround value.\r
+//\r
+#define FIFO_WRITE_DELAY    2\r
+\r
+//\r
+// MMIO Register Definitions\r
+//\r
+#define    R_IC_CON                          ( 0x00) // I2C Control\r
+#define     B_IC_RESTART_EN                  BIT5\r
+#define     B_IC_SLAVE_DISABLE               BIT6\r
+#define     V_SPEED_STANDARD                 0x02\r
+#define     V_SPEED_FAST                     0x04\r
+#define     V_SPEED_HIGH                     0x06\r
+#define     B_MASTER_MODE                    BIT0\r
+\r
+#define    R_IC_TAR                          ( 0x04) // I2C Target Address\r
+#define     IC_TAR_10BITADDR_MASTER           BIT12\r
+\r
+#define    R_IC_SAR                          ( 0x08) // I2C Slave Address\r
+#define    R_IC_HS_MADDR                     ( 0x0C) // I2C HS MasterMode Code Address\r
+#define    R_IC_DATA_CMD                     ( 0x10) // I2C Rx/Tx Data Buffer and Command\r
+\r
+#define    B_READ_CMD                         BIT8    // 1 = read, 0 = write\r
+#define    B_CMD_STOP                         BIT9    // 1 = STOP\r
+#define    B_CMD_RESTART                      BIT10   // 1 = IC_RESTART_EN\r
+\r
+#define    V_WRITE_CMD_MASK                  ( 0xFF)\r
+\r
+#define    R_IC_SS_SCL_HCNT                  ( 0x14) // Standard Speed I2C Clock SCL High Count\r
+#define    R_IC_SS_SCL_LCNT                  ( 0x18) // Standard Speed I2C Clock SCL Low Count\r
+#define    R_IC_FS_SCL_HCNT                  ( 0x1C) // Full Speed I2C Clock SCL High Count\r
+#define    R_IC_FS_SCL_LCNT                  ( 0x20) // Full Speed I2C Clock SCL Low Count\r
+#define    R_IC_HS_SCL_HCNT                  ( 0x24) // High Speed I2C Clock SCL High Count\r
+#define    R_IC_HS_SCL_LCNT                  ( 0x28) // High Speed I2C Clock SCL Low Count\r
+#define    R_IC_INTR_STAT                    ( 0x2C) // I2C Inetrrupt Status\r
+#define    R_IC_INTR_MASK                    ( 0x30) // I2C Interrupt Mask\r
+#define     I2C_INTR_GEN_CALL                 BIT11  // General call received\r
+#define     I2C_INTR_START_DET                BIT10\r
+#define     I2C_INTR_STOP_DET                 BIT9\r
+#define     I2C_INTR_ACTIVITY                 BIT8\r
+#define     I2C_INTR_TX_ABRT                  BIT6   // Set on NACK\r
+#define     I2C_INTR_TX_EMPTY                 BIT4\r
+#define     I2C_INTR_TX_OVER                  BIT3\r
+#define     I2C_INTR_RX_FULL                  BIT2   // Data bytes in RX FIFO over threshold\r
+#define     I2C_INTR_RX_OVER                  BIT1\r
+#define     I2C_INTR_RX_UNDER                 BIT0\r
+#define    R_IC_RAW_INTR_STAT                ( 0x34) // I2C Raw Interrupt Status\r
+#define    R_IC_RX_TL                        ( 0x38) // I2C Receive FIFO Threshold\r
+#define    R_IC_TX_TL                        ( 0x3C) // I2C Transmit FIFO Threshold\r
+#define    R_IC_CLR_INTR                     ( 0x40) // Clear Combined and Individual Interrupts\r
+#define    R_IC_CLR_RX_UNDER                 ( 0x44) // Clear RX_UNDER Interrupt\r
+#define    R_IC_CLR_RX_OVER                  ( 0x48) // Clear RX_OVERinterrupt\r
+#define    R_IC_CLR_TX_OVER                  ( 0x4C) // Clear TX_OVER interrupt\r
+#define    R_IC_CLR_RD_REQ                   ( 0x50) // Clear RD_REQ interrupt\r
+#define    R_IC_CLR_TX_ABRT                  ( 0x54) // Clear TX_ABRT interrupt\r
+#define    R_IC_CLR_RX_DONE                  ( 0x58) // Clear RX_DONE interrupt\r
+#define    R_IC_CLR_ACTIVITY                 ( 0x5C) // Clear ACTIVITY interrupt\r
+#define    R_IC_CLR_STOP_DET                 ( 0x60) // Clear STOP_DET interrupt\r
+#define    R_IC_CLR_START_DET                ( 0x64) // Clear START_DET interrupt\r
+#define    R_IC_CLR_GEN_CALL                 ( 0x68) // Clear GEN_CALL interrupt\r
+#define    R_IC_ENABLE                       ( 0x6C) // I2C Enable\r
+#define    R_IC_STATUS                       ( 0x70) // I2C Status\r
+\r
+#define    R_IC_SDA_HOLD                     ( 0x7C) // I2C IC_DEFAULT_SDA_HOLD//16bits\r
+\r
+#define     STAT_MST_ACTIVITY                 BIT5   // Master FSM Activity Status.\r
+#define     STAT_RFF                          BIT4   // RX FIFO is completely full\r
+#define     STAT_RFNE                         BIT3   // RX FIFO is not empty\r
+#define     STAT_TFE                          BIT2   // TX FIFO is completely empty\r
+#define     STAT_TFNF                         BIT1   // TX FIFO is not full\r
+\r
+#define    R_IC_TXFLR                        ( 0x74) // Transmit FIFO Level Register\r
+#define    R_IC_RXFLR                        ( 0x78) // Receive FIFO Level Register\r
+#define    R_IC_TX_ABRT_SOURCE               ( 0x80) // I2C Transmit Abort Status Register\r
+#define    R_IC_SLV_DATA_NACK_ONLY           ( 0x84) // Generate SLV_DATA_NACK Register\r
+#define    R_IC_DMA_CR                       ( 0x88) // DMA Control Register\r
+#define    R_IC_DMA_TDLR                     ( 0x8C) // DMA Transmit Data Level\r
+#define    R_IC_DMA_RDLR                     ( 0x90) // DMA Receive Data Level\r
+#define    R_IC_SDA_SETUP                    ( 0x94) // I2C SDA Setup Register\r
+#define    R_IC_ACK_GENERAL_CALL             ( 0x98) // I2C ACK General Call Register\r
+#define    R_IC_ENABLE_STATUS                ( 0x9C) // I2C Enable Status Register\r
+#define    R_IC_COMP_PARAM                   ( 0xF4) // Component Parameter Register\r
+#define    R_IC_COMP_VERSION                 ( 0xF8) // Component Version ID\r
+#define    R_IC_COMP_TYPE                    ( 0xFC) // Component Type\r
+\r
+#define    R_IC_CLK_GATE                     ( 0xC0) // Clock Gate\r
+\r
+#define    I2C_SS_SCL_HCNT_VALUE_100M        0x1DD\r
+#define    I2C_SS_SCL_LCNT_VALUE_100M        0x1E4\r
+#define    I2C_FS_SCL_HCNT_VALUE_100M        0x54\r
+#define    I2C_FS_SCL_LCNT_VALUE_100M        0x9a\r
+#define    I2C_HS_SCL_HCNT_VALUE_100M        0x7\r
+#define    I2C_HS_SCL_LCNT_VALUE_100M        0xE\r
+\r
+#define     IC_TAR_10BITADDR_MASTER           BIT12\r
+#define     FIFO_SIZE                         32\r
+#define     R_IC_INTR_STAT                    ( 0x2C) // I2c Inetrrupt Status\r
+#define     R_IC_INTR_MASK                    ( 0x30) // I2c Interrupt Mask\r
+#define     I2C_INTR_GEN_CALL                 BIT11  // General call received\r
+#define     I2C_INTR_START_DET                BIT10\r
+#define     I2C_INTR_STOP_DET                 BIT9\r
+#define     I2C_INTR_ACTIVITY                 BIT8\r
+#define     I2C_INTR_TX_ABRT                  BIT6   // Set on NACK\r
+#define     I2C_INTR_TX_EMPTY                 BIT4\r
+#define     I2C_INTR_TX_OVER                  BIT3\r
+#define     I2C_INTR_RX_FULL                  BIT2   // Data bytes in RX FIFO over threshold\r
+#define     I2C_INTR_RX_OVER                  BIT1\r
+#define     I2C_INTR_RX_UNDER                 BIT0\r
+\r
+EFI_STATUS ProgramPciLpssI2C (\r
+  IN  UINT8 BusNo\r
+  );\r
+EFI_STATUS ByteReadI2C_Basic(\r
+  IN  UINT8 BusNo,\r
+  IN  UINT8 SlaveAddress,\r
+  IN  UINTN ReadBytes,\r
+  OUT UINT8 *ReadBuffer,\r
+  IN  UINT8 Start,\r
+  IN  UINT8 End\r
+  );\r
+EFI_STATUS ByteWriteI2C_Basic(\r
+  IN  UINT8 BusNo,\r
+  IN  UINT8 SlaveAddress,\r
+  IN  UINTN WriteBytes,\r
+  IN  UINT8 *WriteBuffer,\r
+  IN  UINT8 Start,\r
+  IN  UINT8 End\r
+  );\r
+\r
+EFI_STATUS ByteReadI2C(\r
+  IN  UINT8 BusNo,\r
+  IN  UINT8 SlaveAddress,\r
+  IN  UINT8 Offset,\r
+  IN  UINTN ReadBytes,\r
+  OUT UINT8 *ReadBuffer\r
+  );\r
+EFI_STATUS ByteWriteI2C(\r
+  IN  UINT8 BusNo,\r
+  IN  UINT8 SlaveAddress,\r
+  IN  UINT8 Offset,\r
+  IN  UINTN WriteBytes,\r
+  IN  UINT8 *WriteBuffer\r
+  );\r
+\r
+#endif  // I2C_REGS_A0_H\r

diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Library/PchPlatformLib.h b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Library/PchPlatformLib.h
new file mode 100644 (file)
index 0000000..8f0ca02
--- /dev/null
+++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Library/PchPlatformLib.h
@@ -0,0 +1,121 @@
+/**\r
+**/\r
+/**\r
+\r
+Copyright (c) 2012  - 2014, Intel Corporation. All rights reserved\r
+\r
+  This program and the accompanying materials are licensed and made available under\r
+  the terms and conditions of the BSD License that accompanies this distribution.\r
+  The full text of the license may be found at\r
+  http://opensource.org/licenses/bsd-license.php.\r
+\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+  @file\r
+  PchPlatformLib.h\r
+\r
+  @brief\r
+  Header file for PchPlatform Lib.\r
+\r
+**/\r
+#ifndef _PCH_PLATFORM_LIB_H_\r
+#define _PCH_PLATFORM_LIB_H_\r
+\r
+///\r
+/// Timeout value used when Sending / Receiving messages.\r
+/// NOTE: this must cover the longest possible wait time\r
+/// between message being sent and response being available.\r
+/// e.g. Virtual function readiness might take some time.\r
+///\r
+VOID\r
+EFIAPI\r
+PchPmTimerStall (\r
+  IN  UINTN   Microseconds\r
+  )\r
+/**\r
+\r
+  @brief\r
+  Delay for at least the request number of microseconds.\r
+  This function would be called by runtime driver, please do not use any MMIO marco here.\r
+\r
+  @param[in] Microseconds         Number of microseconds to delay.\r
+\r
+  @retval NONE\r
+\r
+**/\r
+;\r
+\r
+BOOLEAN\r
+EFIAPI\r
+PchIsSpiDescriptorMode (\r
+  IN  UINTN   SpiBase\r
+  )\r
+/**\r
+\r
+  @brief\r
+  Check whether SPI is in descriptor mode\r
+\r
+  @param[in] SpiBase              The PCH Spi Base Address\r
+\r
+  @retval TRUE                    SPI is in descriptor mode\r
+  @retval FALSE                   SPI is not in descriptor mode\r
+\r
+**/\r
+;\r
+\r
+PCH_STEPPING\r
+EFIAPI\r
+PchStepping (\r
+  VOID\r
+  )\r
+/**\r
+\r
+  @brief\r
+  Return Pch stepping type\r
+\r
+  @param[in] None\r
+\r
+  @retval PCH_STEPPING            Pch stepping type\r
+\r
+**/\r
+;\r
+\r
+BOOLEAN\r
+IsPchSupported (\r
+  VOID\r
+  )\r
+/**\r
+\r
+  @brief\r
+  Determine if PCH is supported\r
+\r
+  @param[in] None\r
+\r
+  @retval TRUE                    PCH is supported\r
+  @retval FALSE                   PCH is not supported\r
+\r
+**/\r
+;\r
+\r
+VOID\r
+EFIAPI\r
+PchAlternateAccessMode (\r
+  IN  UINTN         IlbBase,\r
+  IN  BOOLEAN       AmeCtrl\r
+  )\r
+/**\r
+\r
+  This function can be called to enable/disable Alternate Access Mode\r
+\r
+  @param[in] IlbBase              The PCH ILB Base Address\r
+  @param[in] AmeCtrl              If TRUE, enable Alternate Access Mode.\r
+                                  If FALSE, disable Alternate Access Mode.\r
+\r
+  @retval NONE\r
+\r
+**/\r
+;\r
+\r
+#endif\r

diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchAccess.h b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchAccess.h
new file mode 100644 (file)
index 0000000..3f44d2b
--- /dev/null
+++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchAccess.h
@@ -0,0 +1,526 @@
+/**\r
+\r
+Copyright (c) 2012  - 2014, Intel Corporation. All rights reserved\r
+\r
+  This program and the accompanying materials are licensed and made available under\r
+  the terms and conditions of the BSD License that accompanies this distribution.\r
+  The full text of the license may be found at\r
+  http://opensource.org/licenses/bsd-license.php.\r
+\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+\r
+  @file\r
+  PchAccess.h\r
+\r
+  @brief\r
+  Macros that simplify accessing PCH devices's PCI registers.\r
+\r
+  ** NOTE ** these macros assume the PCH device is on BUS 0\r
+\r
+**/\r
+#ifndef _PCH_ACCESS_H_\r
+#define _PCH_ACCESS_H_\r
+\r
+#include "PchRegs.h"\r
+#include "PchCommonDefinitions.h"\r
+\r
+#ifndef STALL_ONE_MICRO_SECOND\r
+#define STALL_ONE_MICRO_SECOND 1\r
+#endif\r
+#ifndef STALL_ONE_SECOND\r
+#define STALL_ONE_SECOND 1000000\r
+#endif\r
+\r
+///\r
+/// Memory Mapped PCI Access macros\r
+///\r
+///\r
+/// PCI Device MM Base\r
+///\r
+#ifndef MmPciAddress\r
+#define MmPciAddress(Segment, Bus, Device, Function, Register) \\r
+  ((UINTN) PatchPcdGet64 (PcdPciExpressBaseAddress) + \\r
+   (UINTN) (Bus << 20) + \\r
+   (UINTN) (Device << 15) + \\r
+   (UINTN) (Function << 12) + \\r
+   (UINTN) (Register) \\r
+  )\r
+#endif\r
+///\r
+/// Pch Controller PCI access macros\r
+///\r
+#define PCH_RCRB_BASE ( \\r
+  MmioRead32 (MmPciAddress (0, \\r
+  DEFAULT_PCI_BUS_NUMBER_PCH, \\r
+  PCI_DEVICE_NUMBER_PCH_LPC, \\r
+  PCI_FUNCTION_NUMBER_PCH_LPC), \\r
+  R_PCH_LPC_RCBA)) & B_PCH_LPC_RCBA_BAR \\r
+  )\r
+\r
+///\r
+/// Device 0x1b, Function 0\r
+///\r
+#define PchAzaliaPciCfg32(Register) \\r
+  MmioRead32 ( \\r
+  MmPciAddress (0, \\r
+  DEFAULT_PCI_BUS_NUMBER_PCH, \\r
+  PCI_DEVICE_NUMBER_PCH_AZALIA, \\r
+  0, \\r
+  Register) \\r
+  )\r
+\r
+#define PchAzaliaPciCfg32Or(Register, OrData) \\r
+  MmioOr32 ( \\r
+  MmPciAddress (0, \\r
+  DEFAULT_PCI_BUS_NUMBER_PCH, \\r
+  PCI_DEVICE_NUMBER_PCH_AZALIA, \\r
+  0, \\r
+  Register), \\r
+  OrData \\r
+  )\r
+\r
+#define PchAzaliaPciCfg32And(Register, AndData) \\r
+  MmioAnd32 ( \\r
+  MmPciAddress (0, \\r
+  DEFAULT_PCI_BUS_NUMBER_PCH, \\r
+  PCI_DEVICE_NUMBER_PCH_AZALIA, \\r
+  0, \\r
+  Register), \\r
+  AndData \\r
+  )\r
+\r
+#define PchAzaliaPciCfg32AndThenOr(Register, AndData, OrData) \\r
+  MmioAndThenOr32 ( \\r
+  MmPciAddress (0, \\r
+  DEFAULT_PCI_BUS_NUMBER_PCH, \\r
+  PCI_DEVICE_NUMBER_PCH_AZALIA, \\r
+  0, \\r
+  Register), \\r
+  OrData \\r
+  )\r
+\r
+#define PchAzaliaPciCfg16(Register) \\r
+  MmioRead16 ( \\r
+  MmPciAddress (0, \\r
+  DEFAULT_PCI_BUS_NUMBER_PCH, \\r
+  PCI_DEVICE_NUMBER_PCH_AZALIA, \\r
+  0, \\r
+  Register) \\r
+  )\r
+\r
+#define PchAzaliaPciCfg16Or(Register, OrData) \\r
+  MmioOr16 ( \\r
+  MmPciAddress (0, \\r
+  DEFAULT_PCI_BUS_NUMBER_PCH, \\r
+  PCI_DEVICE_NUMBER_PCH_AZALIA, \\r
+  0, \\r
+  Register), \\r
+  OrData \\r
+  )\r
+\r
+#define PchAzaliaPciCfg16And(Register, AndData) \\r
+  MmioAnd16 ( \\r
+  MmPciAddress (0, \\r
+  DEFAULT_PCI_BUS_NUMBER_PCH, \\r
+  PCI_DEVICE_NUMBER_PCH_AZALIA, \\r
+  0, \\r
+  Register), \\r
+  AndData \\r
+  )\r
+\r
+#define PchAzaliaPciCfg16AndThenOr(Register, AndData, OrData) \\r
+  MmioAndThenOr16 ( \\r
+  MmPciAddress (0, \\r
+  DEFAULT_PCI_BUS_NUMBER_PCH, \\r
+  PCI_DEVICE_NUMBER_PCH_AZALIA, \\r
+  0, \\r
+  Register), \\r
+  AndData, \\r
+  OrData \\r
+  )\r
+\r
+#define PchAzaliaPciCfg8(Register)  MmioRead8 (MmPciAddress (0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_AZALIA, 0, Register))\r
+\r
+#define PchAzaliaPciCfg8Or(Register, OrData) \\r
+  MmioOr8 ( \\r
+  MmPciAddress (0, \\r
+  DEFAULT_PCI_BUS_NUMBER_PCH, \\r
+  PCI_DEVICE_NUMBER_PCH_AZALIA, \\r
+  0, \\r
+  Register), \\r
+  OrData \\r
+  )\r
+\r
+#define PchAzaliaPciCfg8And(Register, AndData) \\r
+  MmioAnd8 ( \\r
+  MmPciAddress (0, \\r
+  DEFAULT_PCI_BUS_NUMBER_PCH, \\r
+  PCI_DEVICE_NUMBER_PCH_AZALIA, \\r
+  0, \\r
+  Register), \\r
+  AndData \\r
+  )\r
+\r
+#define PchAzaliaPciCfg8AndThenOr(Register, AndData, OrData) \\r
+  MmioAndThenOr8 ( \\r
+  MmPciAddress (0, \\r
+  DEFAULT_PCI_BUS_NUMBER_PCH, \\r
+  PCI_DEVICE_NUMBER_PCH_AZALIA, \\r
+  0, \\r
+  Register), \\r
+  AndData, \\r
+  OrData \\r
+  )\r
+\r
+///\r
+/// Device 0x1f, Function 0\r
+///\r
+#define PchLpcPciCfg32(Register)  MmioRead32 (MmPciAddress (0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_LPC, 0, Register))\r
+\r
+#define PchLpcMmioOr32 (Register, OrData) \\r
+  MmioOr32 ( \\r
+  MmPciAddress (0, \\r
+  DEFAULT_PCI_BUS_NUMBER_PCH, \\r
+  PCI_DEVICE_NUMBER_PCH_LPC, \\r
+  0, \\r
+  Register), \\r
+  OrData \\r
+  )\r
+\r
+#define PchLpcPciCfg32And(Register, AndData) \\r
+  MmioAnd32 ( \\r
+  MmPciAddress (0, \\r
+  DEFAULT_PCI_BUS_NUMBER_PCH, \\r
+  PCI_DEVICE_NUMBER_PCH_LPC, \\r
+  0, \\r
+  Register), \\r
+  AndData \\r
+  )\r
+\r
+#define PchLpcPciCfg32AndThenOr(Register, AndData, OrData) \\r
+  MmioAndThenOr32 ( \\r
+  MmPciAddress (0, \\r
+  DEFAULT_PCI_BUS_NUMBER_PCH, \\r
+  PCI_DEVICE_NUMBER_PCH_LPC, \\r
+  0, \\r
+  Register), \\r
+  AndData, \\r
+  OrData \\r
+  )\r
+\r
+#define PchLpcPciCfg16(Register)  MmioRead16 (MmPciAddress (0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_LPC, 0, Register))\r
+\r
+#define PchLpcPciCfg16Or(Register, OrData) \\r
+  MmioOr16 ( \\r
+  MmPciAddress (0, \\r
+  DEFAULT_PCI_BUS_NUMBER_PCH, \\r
+  PCI_DEVICE_NUMBER_PCH_LPC, \\r
+  0, \\r
+  Register), \\r
+  OrData \\r
+  )\r
+\r
+#define PchLpcPciCfg16And(Register, AndData) \\r
+  MmioAndThenOr16 ( \\r
+  MmPciAddress (0, \\r
+  DEFAULT_PCI_BUS_NUMBER_PCH, \\r
+  PCI_DEVICE_NUMBER_PCH_LPC, \\r
+  0, \\r
+  Register), \\r
+  AndData \\r
+  )\r
+\r
+#define PchLpcPciCfg16AndThenOr(Register, AndData, OrData) \\r
+  MmioAndThenOr16 ( \\r
+  MmPciAddress (0, \\r
+  DEFAULT_PCI_BUS_NUMBER_PCH, \\r
+  PCI_DEVICE_NUMBER_PCH_LPC, \\r
+  0, \\r
+  Register), \\r
+  AndData, \\r
+  OrData \\r
+  )\r
+\r
+#define PchLpcPciCfg8(Register) MmioRead8 (MmPciAddress (0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_LPC, 0, Register))\r
+\r
+#define PchLpcPciCfg8Or(Register, OrData) \\r
+  MmioOr8 ( \\r
+  MmPciAddress (0, \\r
+  DEFAULT_PCI_BUS_NUMBER_PCH, \\r
+  PCI_DEVICE_NUMBER_PCH_LPC, \\r
+  0, \\r
+  Register), \\r
+  OrData \\r
+  )\r
+\r
+#define PchLpcPciCfg8And(Register, AndData) \\r
+  MmioAnd8 ( \\r
+  MmPciAddress (0, \\r
+  DEFAULT_PCI_BUS_NUMBER_PCH, \\r
+  PCI_DEVICE_NUMBER_PCH_LPC, \\r
+  0, \\r
+  Register), \\r
+  AndData \\r
+  )\r
+\r
+#define PchLpcPciCfg8AndThenOr(Register, AndData, OrData) \\r
+  MmioAndThenOr8 ( \\r
+  MmPciAddress (0, \\r
+  DEFAULT_PCI_BUS_NUMBER_PCH, \\r
+  PCI_DEVICE_NUMBER_PCH_LPC, \\r
+  0, \\r
+  Register), \\r
+  AndData, \\r
+  OrData \\r
+  )\r
+\r
+\r
+///\r
+/// SATA device 0x13, Function 0\r
+///\r
+#define PchSataPciCfg32(Register) MmioRead32 (MmPciAddress (0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_SATA, PCI_FUNCTION_NUMBER_PCH_SATA, Register))\r
+\r
+#define PchSataPciCfg32Or(Register, OrData) \\r
+  MmioOr32 ( \\r
+  MmPciAddress (0, \\r
+  DEFAULT_PCI_BUS_NUMBER_PCH, \\r
+  PCI_DEVICE_NUMBER_PCH_SATA, \\r
+  PCI_FUNCTION_NUMBER_PCH_SATA, \\r
+  Register), \\r
+  OrData \\r
+  )\r
+\r
+#define PchSataPciCfg32And(Register, AndData) \\r
+  MmioAnd32 ( \\r
+  MmPciAddress (0, \\r
+  DEFAULT_PCI_BUS_NUMBER_PCH, \\r
+  PCI_DEVICE_NUMBER_PCH_SATA, \\r
+  PCI_FUNCTION_NUMBER_PCH_SATA, \\r
+  Register), \\r
+  AndData \\r
+  )\r
+\r
+#define PchSataPciCfg32AndThenOr(Register, AndData, OrData) \\r
+  MmioAndThenOr32 ( \\r
+  MmPciAddress (0, \\r
+  DEFAULT_PCI_BUS_NUMBER_PCH, \\r
+  PCI_DEVICE_NUMBER_PCH_SATA, \\r
+  PCI_FUNCTION_NUMBER_PCH_SATA, \\r
+  Register), \\r
+  AndData, \\r
+  OrData \\r
+  )\r
+\r
+#define PchSataPciCfg16(Register) MmioRead16 (MmPciAddress (0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_SATA, PCI_FUNCTION_NUMBER_PCH_SATA, Register))\r
+\r
+#define PchSataPciCfg16Or(Register, OrData) \\r
+  MmioOr16 ( \\r
+  MmPciAddress (0, \\r
+  DEFAULT_PCI_BUS_NUMBER_PCH, \\r
+  PCI_DEVICE_NUMBER_PCH_SATA, \\r
+  PCI_FUNCTION_NUMBER_PCH_SATA, \\r
+  Register), \\r
+  OrData \\r
+  )\r
+\r
+#define PchSataPciCfg16And(Register, AndData) \\r
+  MmioAndThenOr16 ( \\r
+  MmPciAddress (0, \\r
+  DEFAULT_PCI_BUS_NUMBER_PCH, \\r
+  PCI_DEVICE_NUMBER_PCH_SATA, \\r
+  PCI_FUNCTION_NUMBER_PCH_SATA, \\r
+  Register), \\r
+  AndData \\r
+  )\r
+\r
+#define PchSataPciCfg16AndThenOr(Register, AndData, OrData) \\r
+  MmioAndThenOr16 ( \\r
+  MmPciAddress (0, \\r
+  DEFAULT_PCI_BUS_NUMBER_PCH, \\r
+  PCI_DEVICE_NUMBER_PCH_SATA, \\r
+  PCI_FUNCTION_NUMBER_PCH_SATA, \\r
+  Register), \\r
+  AndData, \\r
+  OrData \\r
+  )\r
+\r
+#define PchSataPciCfg8(Register)  MmioRead8 (MmPciAddress (0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_SATA, PCI_FUNCTION_NUMBER_PCH_SATA, Register))\r
+\r
+#define PchSataPciCfg8Or(Register, OrData) \\r
+  MmioOr8 ( \\r
+  MmPciAddress (0, \\r
+  DEFAULT_PCI_BUS_NUMBER_PCH, \\r
+  PCI_DEVICE_NUMBER_PCH_SATA, \\r
+  PCI_FUNCTION_NUMBER_PCH_SATA, \\r
+  Register), \\r
+  OrData \\r
+  )\r
+\r
+#define PchSataPciCfg8And(Register, AndData) \\r
+  MmioAnd8 ( \\r
+  MmPciAddress (0, \\r
+  DEFAULT_PCI_BUS_NUMBER_PCH, \\r
+  PCI_DEVICE_NUMBER_PCH_SATA, \\r
+  PCI_FUNCTION_NUMBER_PCH_SATA, \\r
+  Register), \\r
+  AndData \\r
+  )\r
+\r
+#define PchSataPciCfg8AndThenOr(Register, AndData, OrData) \\r
+  MmioAndThenOr8 ( \\r
+  MmPciAddress (0, \\r
+  DEFAULT_PCI_BUS_NUMBER_PCH, \\r
+  PCI_DEVICE_NUMBER_PCH_SATA, \\r
+  PCI_FUNCTION_NUMBER_PCH_SATA, \\r
+  Register), \\r
+  AndData, \\r
+  OrData \\r
+  )\r
+\r
+\r
+///\r
+/// Root Complex Register Block\r
+///\r
+#define PchMmRcrb32(Register)                           MmioRead32 (PCH_RCRB_BASE + Register)\r
+\r
+#define PchMmRcrb32Or(Register, OrData)                 MmioOr32 (PCH_RCRB_BASE + Register, OrData)\r
+\r
+#define PchMmRcrb32And(Register, AndData)               MmioAnd32 (PCH_RCRB_BASE + Register, AndData)\r
+\r
+#define PchMmRcrb32AndThenOr(Register, AndData, OrData) MmioAndThenOr32 (PCH_RCRB_BASE + Register, AndData, OrData)\r
+\r
+#define PchMmRcrb16(Register)                           MmioRead16 (PCH_RCRB_BASE + Register)\r
+\r
+#define PchMmRcrb16Or(Register, OrData)                 MmioOr16 (PCH_RCRB_BASE + Register, OrData)\r
+\r
+#define PchMmRcrb16And(Register, AndData)               MmioAnd16 (PCH_RCRB_BASE + Register, AndData)\r
+\r
+#define PchMmRcrb16AndThenOr(Register, AndData, OrData) MmioAndThenOr16 (PCH_RCRB_BASE + Register, AndData, OrData)\r
+\r
+#define PchMmRcrb8(Register)                            MmioRead8 (PCH_RCRB_BASE + Register)\r
+\r
+#define PchMmRcrb8Or(Register, OrData)                  MmioOr8 (PCH_RCRB_BASE + Register, OrData)\r
+\r
+#define PchMmRcrb8And(Register, AndData)                MmioAnd8 (PCH_RCRB_BASE + Register, AndData)\r
+\r
+#define PchMmRcrb8AndThenOr(Register, AndData, OrData)  MmioAndThenOr8 (PCH_RCRB_BASE + Register, AndData, OrData)\r
+\r
+\r
+///\r
+/// Message Bus\r
+///\r
+\r
+///\r
+/// Message Bus Registers\r
+///\r
+#define MC_MCR            0x000000D0 // Cunit Message Control Register\r
+#define MC_MDR            0x000000D4 // Cunit Message Data Register\r
+#define MC_MCRX           0x000000D8 // Cunit Message Control Register Extension\r
+\r
+///\r
+/// Message Bus API\r
+///\r
+#define MSG_BUS_ENABLED   0x000000F0\r
+#define MSGBUS_MASKHI     0xFFFFFF00\r
+#define MSGBUS_MASKLO     0x000000FF\r
+#define MESSAGE_DWORD_EN  BIT4 | BIT5 | BIT6 | BIT7\r
+\r
+#define PchMsgBusRead32(PortId, Register, Dbuff, ReadOpCode, WriteOpCode) \\r
+{ \\r
+  MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCRX), (UINT32) (Register & MSGBUS_MASKHI)); \\r
+  MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCR ), (UINT32) ((ReadOpCode << 24) | (PortId << 16) | ((Register & MSGBUS_MASKLO) << 8) | MESSAGE_DWORD_EN)); \\r
+  (Dbuff) = MmioRead32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MDR)); \\r
+}\r
+\r
+#define PchMsgBusAnd32(PortId, Register, Dbuff, AndData, ReadOpCode, WriteOpCode) \\r
+{ \\r
+  MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCRX), (UINT32) (Register & MSGBUS_MASKHI)); \\r
+  MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCR ), (UINT32) ((ReadOpCode << 24) | (PortId << 16) | ((Register & MSGBUS_MASKLO) << 8) | MESSAGE_DWORD_EN)); \\r
+  (Dbuff) = MmioRead32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MDR)); \\r
+  MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCRX), (UINT32) (Register & MSGBUS_MASKHI)); \\r
+  MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MDR ), (UINT32) (Dbuff & AndData)); \\r
+  MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCR ), (UINT32) ((WriteOpCode << 24) | (PortId << 16) | ((Register & MSGBUS_MASKLO) << 8) | MESSAGE_DWORD_EN)); \\r
+}\r
+\r
+#define PchMsgBusOr32(PortId, Register, Dbuff, OrData, ReadOpCode, WriteOpCode) \\r
+{ \\r
+  MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCRX), (UINT32) (Register & MSGBUS_MASKHI)); \\r
+  MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCR ), (UINT32) ((ReadOpCode << 24) | (PortId << 16) | ((Register & MSGBUS_MASKLO) << 8) | MESSAGE_DWORD_EN)); \\r
+  (Dbuff) = MmioRead32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MDR)); \\r
+  MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCRX), (UINT32) (Register & MSGBUS_MASKHI)); \\r
+  MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MDR ), (UINT32) (Dbuff | OrData)); \\r
+  MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCR ), (UINT32) ((WriteOpCode << 24) | (PortId << 16) | ((Register & MSGBUS_MASKLO) << 8) | MESSAGE_DWORD_EN)); \\r
+}\r
+\r
+#define PchMsgBusAndThenOr32(PortId, Register, Dbuff, AndData, OrData, ReadOpCode, WriteOpCode) \\r
+{ \\r
+  MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCRX), (UINT32) (Register & MSGBUS_MASKHI)); \\r
+  MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCR ), (UINT32) ((ReadOpCode << 24) | (PortId << 16) | ((Register & MSGBUS_MASKLO) << 8) | MESSAGE_DWORD_EN)); \\r
+  (Dbuff) = MmioRead32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MDR)); \\r
+  MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCRX), (UINT32) (Register & MSGBUS_MASKHI)); \\r
+  MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MDR ), (UINT32) ((Dbuff & AndData) | OrData)); \\r
+  MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCR ), (UINT32) ((WriteOpCode << 24) | (PortId << 16) | ((Register & MSGBUS_MASKLO) << 8) | MESSAGE_DWORD_EN)); \\r
+}\r
+\r
+typedef struct _PCH_MSG_BUS_TABLE_STRUCT {\r
+  UINT32      PortId;\r
+  UINT32      Address;\r
+  UINT32      AndMask;\r
+  UINT32      OrMask;\r
+  UINT32      ReadOpCode;\r
+  UINT32      WriteOpCode;\r
+} PCH_MSG_BUS_TABLE_STRUCT_TABLE_STRUCT;\r
+\r
+#ifndef _S3SUPPORT_\r
+#define _S3SUPPORT_\r
+UINTN MCRX;\r
+UINTN MCR;\r
+//\r
+// In S3 execute, we should follow the MSG BUS access procedure to restore the saving data.\r
+// To do so, we adopt READ ->> SAVE\r
+// Indirect IO access: (According BayTrail-M EDS chapter 3.6)\r
+// 1. Write Index port into MSG BUS_MCRX first.\r
+// 2. Write content to data register which is called MSG BUS_MDR.\r
+// 3. Send "message bus control" to complete the procedure.\r
+//\r
+#define S3BootScriptSaveMsgBusToMemWrite(PortId, Register, Dbuff, ReadOpCode, WriteOpCode) \\r
+{ \\r
+  MCRX = (UINTN) Register & MSGBUS_MASKHI; \\r
+  MCR = (UINTN) ((ReadOpCode << 24) | (PortId << 16) | ((Register & MSGBUS_MASKLO) << 8) | MESSAGE_DWORD_EN); \\r
+  MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCRX), (UINT32) MCRX); \\r
+  S3BootScriptSaveMemWrite(EfiBootScriptWidthUint32, (UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCRX),1, (VOID *) (UINTN) &MCRX); \\r
+  MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCR ), (UINT32) MCR); \\r
+  (Dbuff) = (UINT32) MmioRead32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MDR)); \\r
+  S3BootScriptSaveMemWrite(EfiBootScriptWidthUint32, (UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MDR),1, (VOID *) &Dbuff); \\r
+  MCR = (UINTN) ((WriteOpCode << 24) | (PortId << 16) | ((Register & MSGBUS_MASKLO) << 8) | MESSAGE_DWORD_EN); \\r
+  S3BootScriptSaveMemWrite(EfiBootScriptWidthUint32, (UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCR),1, (VOID *) (UINTN) &MCR); \\r
+}\r
+\r
+//\r
+// This macro combines two function:  1. PchMsgBusAndThenOr32 ()  2. S3 boot script save\r
+//\r
+#define PchMsgBusAndThenOr32AddToS3Save(PortId, Register, Dbuff, AndData, OrData, ReadOpCode, WriteOpCode) \\r
+{ \\r
+  MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCRX), (UINT32) (Register & MSGBUS_MASKHI)); \\r
+  MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCR ), (UINT32) ((ReadOpCode << 24) | (PortId << 16) | ((Register & MSGBUS_MASKLO) << 8) | MESSAGE_DWORD_EN)); \\r
+  (Dbuff) = (UINT32) MmioRead32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MDR)); \\r
+  MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCRX), (UINT32) (Register & MSGBUS_MASKHI)); \\r
+  MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MDR ), (UINT32) ((Dbuff & AndData) | OrData)); \\r
+  MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCR ), (UINT32) ((WriteOpCode << 24) | (PortId << 16) | ((Register & MSGBUS_MASKLO) << 8) | MESSAGE_DWORD_EN)); \\r
+  MCRX = (UINTN) Register & MSGBUS_MASKHI; \\r
+  MCR = (UINTN) ((ReadOpCode << 24) | (PortId << 16) | ((Register & MSGBUS_MASKLO) << 8) | MESSAGE_DWORD_EN); \\r
+  MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCRX), (UINT32) MCRX); \\r
+  S3BootScriptSaveMemWrite(EfiBootScriptWidthUint32, (UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCRX),1,(VOID *) (UINTN) &MCRX); \\r
+  MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCR ), (UINT32) MCR); \\r
+  (Dbuff) = (UINT32) MmioRead32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MDR)); \\r
+  S3BootScriptSaveMemWrite(EfiBootScriptWidthUint32, (UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MDR),1,(VOID *) &Dbuff); \\r
+  MCR = (UINTN) ((WriteOpCode << 24) | (PortId << 16) | ((Register & MSGBUS_MASKLO) << 8) | MESSAGE_DWORD_EN); \\r
+  S3BootScriptSaveMemWrite(EfiBootScriptWidthUint32, (UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCR),1,(VOID *) (UINTN) &MCR); \\r
+}\r
+\r
+#endif\r
+\r
+#endif\r

diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchCommonDefinitions.h b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchCommonDefinitions.h
new file mode 100644 (file)
index 0000000..29002cc
--- /dev/null
+++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchCommonDefinitions.h
@@ -0,0 +1,216 @@
+/*++\r
+\r
+Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved\r
+\r
+  This program and the accompanying materials are licensed and made available under\r
+  the terms and conditions of the BSD License that accompanies this distribution.\r
+  The full text of the license may be found at\r
+  http://opensource.org/licenses/bsd-license.php.\r
+\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+\r
+Module Name:\r
+\r
+  PchCommonDefinitions.h\r
+\r
+Abstract:\r
+\r
+  This header file provides common definitions for PCH\r
+\r
+--*/\r
+#ifndef _PCH_COMMON_DEFINITIONS_H_\r
+#define _PCH_COMMON_DEFINITIONS_H_\r
+\r
+//\r
+//  MMIO access macros\r
+//\r
+#define PchMmioAddress(BaseAddr, Register)  ((UINTN) BaseAddr + (UINTN) (Register))\r
+\r
+//\r
+// 32 bit MMIO access\r
+//\r
+#define PchMmio32Ptr(BaseAddr, Register)  ((volatile UINT32 *) PchMmioAddress (BaseAddr, Register))\r
+\r
+#define PchMmio32(BaseAddr, Register)     *PchMmio32Ptr (BaseAddr, Register)\r
+\r
+#define PchMmio32Or(BaseAddr, Register, OrData) \\r
+  PchMmio32 (BaseAddr, Register) = (UINT32) \\r
+    (PchMmio32 (BaseAddr, Register) | (UINT32) (OrData))\r
+\r
+#define PchMmio32And(BaseAddr, Register, AndData) \\r
+  PchMmio32 (BaseAddr, Register) = (UINT32) \\r
+    (PchMmio32 (BaseAddr, Register) & (UINT32) (AndData))\r
+\r
+#define PchMmio32AndThenOr(BaseAddr, Register, AndData, OrData) \\r
+  PchMmio32 (BaseAddr, Register) = (UINT32) \\r
+    ((PchMmio32 (BaseAddr, Register) & (UINT32) (AndData)) | (UINT32) (OrData))\r
+\r
+//\r
+// 16 bit MMIO access\r
+//\r
+#define PchMmio16Ptr(BaseAddr, Register)  ((volatile UINT16 *) PchMmioAddress (BaseAddr, Register))\r
+\r
+#define PchMmio16(BaseAddr, Register)     *PchMmio16Ptr (BaseAddr, Register)\r
+\r
+#define PchMmio16Or(BaseAddr, Register, OrData) \\r
+  PchMmio16 (BaseAddr, Register) = (UINT16) \\r
+    (PchMmio16 (BaseAddr, Register) | (UINT16) (OrData))\r
+\r
+#define PchMmio16And(BaseAddr, Register, AndData) \\r
+  PchMmio16 (BaseAddr, Register) = (UINT16) \\r
+    (PchMmio16 (BaseAddr, Register) & (UINT16) (AndData))\r
+\r
+#define PchMmio16AndThenOr(BaseAddr, Register, AndData, OrData) \\r
+  PchMmio16 (BaseAddr, Register) = (UINT16) \\r
+    ((PchMmio16 (BaseAddr, Register) & (UINT16) (AndData)) | (UINT16) (OrData))\r
+\r
+//\r
+// 8 bit MMIO access\r
+//\r
+#define PchMmio8Ptr(BaseAddr, Register) ((volatile UINT8 *) PchMmioAddress (BaseAddr, Register))\r
+\r
+#define PchMmio8(BaseAddr, Register)    *PchMmio8Ptr (BaseAddr, Register)\r
+\r
+#define PchMmio8Or(BaseAddr, Register, OrData) \\r
+  PchMmio8 (BaseAddr, Register) = (UINT8) \\r
+    (PchMmio8 (BaseAddr, Register) | (UINT8) (OrData))\r
+\r
+#define PchMmio8And(BaseAddr, Register, AndData) \\r
+  PchMmio8 (BaseAddr, Register) = (UINT8) \\r
+    (PchMmio8 (BaseAddr, Register) & (UINT8) (AndData))\r
+\r
+#define PchMmio8AndThenOr(BaseAddr, Register, AndData, OrData) \\r
+  PchMmio8 (BaseAddr, Register) = (UINT8) \\r
+    ((PchMmio8 (BaseAddr, Register) & (UINT8) (AndData)) | (UINT8) (OrData))\r
+\r
+//\r
+// Memory Mapped PCI Access macros\r
+//\r
+#define PCH_PCI_EXPRESS_BASE_ADDRESS  0xE0000000\r
+//\r
+// PCI Device MM Base\r
+//\r
+#define PchPciDeviceMmBase(Bus, Device, Function) \\r
+    ( \\r
+      (UINTN) PCH_PCI_EXPRESS_BASE_ADDRESS + (UINTN) (Bus << 20) + (UINTN) (Device << 15) + (UINTN) \\r
+        (Function << 12) \\r
+    )\r
+\r
+//\r
+// PCI Device MM Address\r
+//\r
+#define PchPciDeviceMmAddress(Segment, Bus, Device, Function, Register) \\r
+    ( \\r
+      (UINTN) PCH_PCI_EXPRESS_BASE_ADDRESS + (UINTN) (Bus << 20) + (UINTN) (Device << 15) + (UINTN) \\r
+        (Function << 12) + (UINTN) (Register) \\r
+    )\r
+\r
+//\r
+// 32 bit PCI access\r
+//\r
+#define PchMmPci32Ptr(Segment, Bus, Device, Function, Register) \\r
+    ((volatile UINT32 *) PchPciDeviceMmAddress (Segment, Bus, Device, Function, Register))\r
+\r
+#define PchMmPci32(Segment, Bus, Device, Function, Register)  *PchMmPci32Ptr (Segment, Bus, Device, Function, Register)\r
+\r
+#define PchMmPci32Or(Segment, Bus, Device, Function, Register, OrData) \\r
+  PchMmPci32 ( \\r
+  Segment, \\r
+  Bus, \\r
+  Device, \\r
+  Function, \\r
+  Register \\r
+  ) = (UINT32) (PchMmPci32 (Segment, Bus, Device, Function, Register) | (UINT32) (OrData))\r
+\r
+#define PchMmPci32And(Segment, Bus, Device, Function, Register, AndData) \\r
+  PchMmPci32 ( \\r
+  Segment, \\r
+  Bus, \\r
+  Device, \\r
+  Function, \\r
+  Register \\r
+  ) = (UINT32) (PchMmPci32 (Segment, Bus, Device, Function, Register) & (UINT32) (AndData))\r
+\r
+#define PchMmPci32AndThenOr(Segment, Bus, Device, Function, Register, AndData, OrData) \\r
+  PchMmPci32 ( \\r
+  Segment, \\r
+  Bus, \\r
+  Device, \\r
+  Function, \\r
+  Register \\r
+  ) = (UINT32) ((PchMmPci32 (Segment, Bus, Device, Function, Register) & (UINT32) (AndData)) | (UINT32) (OrData))\r
+\r
+//\r
+// 16 bit PCI access\r
+//\r
+#define PchMmPci16Ptr(Segment, Bus, Device, Function, Register) \\r
+    ((volatile UINT16 *) PchPciDeviceMmAddress (Segment, Bus, Device, Function, Register))\r
+\r
+#define PchMmPci16(Segment, Bus, Device, Function, Register)  *PchMmPci16Ptr (Segment, Bus, Device, Function, Register)\r
+\r
+#define PchMmPci16Or(Segment, Bus, Device, Function, Register, OrData) \\r
+  PchMmPci16 ( \\r
+  Segment, \\r
+  Bus, \\r
+  Device, \\r
+  Function, \\r
+  Register \\r
+  ) = (UINT16) (PchMmPci16 (Segment, Bus, Device, Function, Register) | (UINT16) (OrData))\r
+\r
+#define PchMmPci16And(Segment, Bus, Device, Function, Register, AndData) \\r
+  PchMmPci16 ( \\r
+  Segment, \\r
+  Bus, \\r
+  Device, \\r
+  Function, \\r
+  Register \\r
+  ) = (UINT16) (PchMmPci16 (Segment, Bus, Device, Function, Register) & (UINT16) (AndData))\r
+\r
+#define PchMmPci16AndThenOr(Segment, Bus, Device, Function, Register, AndData, OrData) \\r
+  PchMmPci16 ( \\r
+  Segment, \\r
+  Bus, \\r
+  Device, \\r
+  Function, \\r
+  Register \\r
+  ) = (UINT16) ((PchMmPci16 (Segment, Bus, Device, Function, Register) & (UINT16) (AndData)) | (UINT16) (OrData))\r
+\r
+//\r
+// 8 bit PCI access\r
+//\r
+#define PchMmPci8Ptr(Segment, Bus, Device, Function, Register) \\r
+    ((volatile UINT8 *) PchPciDeviceMmAddress (Segment, Bus, Device, Function, Register))\r
+\r
+#define PchMmPci8(Segment, Bus, Device, Function, Register) *PchMmPci8Ptr (Segment, Bus, Device, Function, Register)\r
+\r
+#define PchMmPci8Or(Segment, Bus, Device, Function, Register, OrData) \\r
+  PchMmPci8 ( \\r
+  Segment, \\r
+  Bus, \\r
+  Device, \\r
+  Function, \\r
+  Register \\r
+  ) = (UINT8) (PchMmPci8 (Segment, Bus, Device, Function, Register) | (UINT8) (OrData))\r
+\r
+#define PchMmPci8And(Segment, Bus, Device, Function, Register, AndData) \\r
+  PchMmPci8 ( \\r
+  Segment, \\r
+  Bus, \\r
+  Device, \\r
+  Function, \\r
+  Register \\r
+  ) = (UINT8) (PchMmPci8 (Segment, Bus, Device, Function, Register) & (UINT8) (AndData))\r
+\r
+#define PchMmPci8AndThenOr(Segment, Bus, Device, Function, Register, AndData, OrData) \\r
+  PchMmPci8 ( \\r
+  Segment, \\r
+  Bus, \\r
+  Device, \\r
+  Function, \\r
+  Register \\r
+  ) = (UINT8) ((PchMmPci8 (Segment, Bus, Device, Function, Register) & (UINT8) (AndData)) | (UINT8) (OrData))\r
+\r
+#endif\r

diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs.h b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs.h
new file mode 100644 (file)
index 0000000..21ca877
--- /dev/null
+++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs.h
@@ -0,0 +1,211 @@
+/**\r
+\r
+Copyright (c) 2011  - 2014, Intel Corporation. All rights reserved\r
+\r
+  This program and the accompanying materials are licensed and made available under\r
+  the terms and conditions of the BSD License that accompanies this distribution.\r
+  The full text of the license may be found at\r
+  http://opensource.org/licenses/bsd-license.php.\r
+\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+\r
+  @file\r
+  PchRegs.h\r
+\r
+  @brief\r
+  Register names for VLV SC.\r
+\r
+  Conventions:\r
+\r
+  - Prefixes:\r
+    Definitions beginning with "R_" are registers\r
+    Definitions beginning with "B_" are bits within registers\r
+    Definitions beginning with "V_" are meaningful values of bits within the registers\r
+    Definitions beginning with "S_" are register sizes\r
+    Definitions beginning with "N_" are the bit position\r
+  - In general, PCH registers are denoted by "_PCH_" in register names\r
+  - Registers / bits that are different between PCH generations are denoted by\r
+    "_PCH_<generation_name>_" in register/bit names. e.g., "_PCH_VLV_"\r
+  - Registers / bits that are different between SKUs are denoted by "_<SKU_name>"\r
+    at the end of the register/bit names\r
+  - Registers / bits of new devices introduced in a PCH generation will be just named\r
+    as "_PCH_" without <generation_name> inserted.\r
+\r
+**/\r
+#ifndef _PCH_REGS_H_\r
+#define _PCH_REGS_H_\r
+\r
+///\r
+/// Bit Definitions. BUGBUG: drive these definitions to code base. Should not need\r
+/// to be part of chipset modules\r
+///\r
+#ifndef BIT0\r
+#define BIT0  0x0001\r
+#define BIT1  0x0002\r
+#define BIT2  0x0004\r
+#define BIT3  0x0008\r
+#define BIT4  0x0010\r
+#define BIT5  0x0020\r
+#define BIT6  0x0040\r
+#define BIT7  0x0080\r
+#define BIT8  0x0100\r
+#define BIT9  0x0200\r
+#define BIT10 0x0400\r
+#define BIT11 0x0800\r
+#define BIT12 0x1000\r
+#define BIT13 0x2000\r
+#define BIT14 0x4000\r
+#define BIT15 0x8000\r
+#define BIT16 0x00010000\r
+#define BIT17 0x00020000\r
+#define BIT18 0x00040000\r
+#define BIT19 0x00080000\r
+#define BIT20 0x00100000\r
+#define BIT21 0x00200000\r
+#define BIT22 0x00400000\r
+#define BIT23 0x00800000\r
+#define BIT24 0x01000000\r
+#define BIT25 0x02000000\r
+#define BIT26 0x04000000\r
+#define BIT27 0x08000000\r
+#define BIT28 0x10000000\r
+#define BIT29 0x20000000\r
+#define BIT30 0x40000000\r
+#define BIT31 0x80000000\r
+#define BIT32 0x100000000\r
+#define BIT33 0x200000000\r
+#define BIT34 0x400000000\r
+#define BIT35 0x800000000\r
+#define BIT36 0x1000000000\r
+#define BIT37 0x2000000000\r
+#define BIT38 0x4000000000\r
+#define BIT39 0x8000000000\r
+#define BIT40 0x10000000000\r
+#define BIT41 0x20000000000\r
+#define BIT42 0x40000000000\r
+#define BIT43 0x80000000000\r
+#define BIT44 0x100000000000\r
+#define BIT45 0x200000000000\r
+#define BIT46 0x400000000000\r
+#define BIT47 0x800000000000\r
+#define BIT48 0x1000000000000\r
+#define BIT49 0x2000000000000\r
+#define BIT50 0x4000000000000\r
+#define BIT51 0x8000000000000\r
+#define BIT52 0x10000000000000\r
+#define BIT53 0x20000000000000\r
+#define BIT54 0x40000000000000\r
+#define BIT55 0x80000000000000\r
+#define BIT56 0x100000000000000\r
+#define BIT57 0x200000000000000\r
+#define BIT58 0x400000000000000\r
+#define BIT59 0x800000000000000\r
+#define BIT60 0x1000000000000000\r
+#define BIT61 0x2000000000000000\r
+#define BIT62 0x4000000000000000\r
+#define BIT63 0x8000000000000000\r
+#endif\r
+///\r
+/// The default PCH PCI bus number\r
+///\r
+#define DEFAULT_PCI_BUS_NUMBER_PCH  0\r
+\r
+///\r
+/// Default Vendor ID and Subsystem ID\r
+///\r
+#define V_PCH_INTEL_VENDOR_ID   0x8086\r
+#define V_PCH_DEFAULT_SID       0x7270\r
+#define V_PCH_DEFAULT_SVID_SID  (V_PCH_INTEL_VENDOR_ID + (V_PCH_DEFAULT_SID << 16))\r
+\r
+///\r
+/// Include device register definitions\r
+///\r
+#include "PchRegs/PchRegsHda.h"\r
+#include "PchRegs/PchRegsLpss.h"\r
+#include "PchRegs/PchRegsPcie.h"\r
+#include "PchRegs/PchRegsPcu.h"\r
+#include "PchRegs/PchRegsRcrb.h"\r
+#include "PchRegs/PchRegsSata.h"\r
+#include "PchRegs/PchRegsScc.h"\r
+#include "PchRegs/PchRegsSmbus.h"\r
+#include "PchRegs/PchRegsSpi.h"\r
+#include "PchRegs/PchRegsUsb.h"\r
+//#include "PchRegs/PchRegsLpe.h"\r
+\r
+///\r
+/// Device IDS that are PCH Server specific\r
+///\r
+#define IS_PCH_DEVICE_ID(DeviceId) \\r
+    ( \\r
+      (DeviceId == V_PCH_LPC_DEVICE_ID_0) || \\r
+      (DeviceId == V_PCH_LPC_DEVICE_ID_1) || \\r
+      (DeviceId == V_PCH_LPC_DEVICE_ID_2) || \\r
+      (DeviceId == V_PCH_LPC_DEVICE_ID_3) \\r
+    )\r
+\r
+#define IS_PCH_VLV_LPC_DEVICE_ID(DeviceId) \\r
+    ( \\r
+      IS_PCH_DEVICE_ID (DeviceId) \\r
+    )\r
+\r
+#define IS_PCH_VLV_SATA_DEVICE_ID(DeviceId) \\r
+    ( \\r
+      IS_PCH_VLV_SATA_AHCI_DEVICE_ID (DeviceId) || \\r
+      IS_PCH_VLV_SATA_MODE_DEVICE_ID (DeviceId) || \\r
+      IS_PCH_VLV_SATA_RAID_DEVICE_ID (DeviceId) \\r
+    )\r
+\r
+#define IS_PCH_VLV_SATA_AHCI_DEVICE_ID(DeviceId) \\r
+    ( \\r
+      (DeviceId == V_PCH_SATA_DEVICE_ID_D_AHCI) || \\r
+      (DeviceId == V_PCH_SATA_DEVICE_ID_M_AHCI) \\r
+    )\r
+\r
+#define IS_PCH_VLV_SATA_RAID_DEVICE_ID(DeviceId) \\r
+    ( \\r
+      (DeviceId == V_PCH_SATA_DEVICE_ID_D_RAID) || \\r
+      (DeviceId == V_PCH_SATA_DEVICE_ID_M_RAID) \\r
+    )\r
+\r
+#define IS_PCH_VLV_SATA_MODE_DEVICE_ID(DeviceId) \\r
+    ( \\r
+      (DeviceId == V_PCH_SATA_DEVICE_ID_D_IDE) || \\r
+      (DeviceId == V_PCH_SATA_DEVICE_ID_M_IDE) \\r
+    )\r
+#define IS_PCH_VLV_USB_DEVICE_ID(DeviceId) \\r
+    ( \\r
+      (DeviceId == V_PCH_USB_DEVICE_ID_0) || \\r
+      (DeviceId == V_PCH_USB_DEVICE_ID_1) \\r
+    )\r
+#define IS_PCH_VLV_PCIE_DEVICE_ID(DeviceId) \\r
+    ( \\r
+      (DeviceId == V_PCH_PCIE_DEVICE_ID_0) || \\r
+      (DeviceId == V_PCH_PCIE_DEVICE_ID_1) || \\r
+      (DeviceId == V_PCH_PCIE_DEVICE_ID_2) || \\r
+      (DeviceId == V_PCH_PCIE_DEVICE_ID_3) || \\r
+      (DeviceId == V_PCH_PCIE_DEVICE_ID_4) || \\r
+      (DeviceId == V_PCH_PCIE_DEVICE_ID_5) || \\r
+      (DeviceId == V_PCH_PCIE_DEVICE_ID_6) || \\r
+      (DeviceId == V_PCH_PCIE_DEVICE_ID_7) \\r
+    )\r
+\r
+///\r
+/// Any device ID that is Valleyview SC\r
+///\r
+#define IS_PCH_VLV_DEVICE_ID(DeviceId) \\r
+    ( \\r
+      IS_PCH_VLV_LPC_DEVICE_ID (DeviceId) || \\r
+      IS_PCH_VLV_SATA_DEVICE_ID (DeviceId) || \\r
+      IS_PCH_VLV_USB_DEVICE_ID (DeviceId) || \\r
+      IS_PCH_VLV_PCIE_DEVICE_ID (DeviceId) || \\r
+      (DeviceId) == V_PCH_SMBUS_DEVICE_ID || \\r
+      (DeviceId) == V_PCH_HDA_DEVICE_ID_0 || \\r
+      (DeviceId) == V_PCH_HDA_DEVICE_ID_1 \\r
+    )\r
+\r
+#define IS_SUPPORTED_DEVICE_ID(DeviceId)  IS_PCH_VLV_DEVICE_ID (DeviceId)\r
+\r
+#endif\r

diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/PchRegsHda.h b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/PchRegsHda.h
new file mode 100644 (file)
index 0000000..5d68925
--- /dev/null
+++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/PchRegsHda.h
@@ -0,0 +1,56 @@
+/**\r
+\r
+Copyright (c) 2012  - 2014, Intel Corporation. All rights reserved\r
+\r
+  This program and the accompanying materials are licensed and made available under\r
+  the terms and conditions of the BSD License that accompanies this distribution.\r
+  The full text of the license may be found at\r
+  http://opensource.org/licenses/bsd-license.php.\r
+\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+\r
+  @file\r
+  PchRegsHda.h\r
+\r
+  @brief\r
+  Register names for PCH High Definition Audio device.\r
+\r
+  Conventions:\r
+\r
+  - Prefixes:\r
+    Definitions beginning with "R_" are registers\r
+    Definitions beginning with "B_" are bits within registers\r
+    Definitions beginning with "V_" are meaningful values of bits within the registers\r
+    Definitions beginning with "S_" are register sizes\r
+    Definitions beginning with "N_" are the bit position\r
+  - In general, PCH registers are denoted by "_PCH_" in register names\r
+  - Registers / bits that are different between PCH generations are denoted by\r
+    "_PCH_<generation_name>_" in register/bit names. e.g., "_PCH_VLV_"\r
+  - Registers / bits that are different between SKUs are denoted by "_<SKU_name>"\r
+    at the end of the register/bit names\r
+  - Registers / bits of new devices introduced in a PCH generation will be just named\r
+    as "_PCH_" without <generation_name> inserted.\r
+\r
+**/\r
+#ifndef _PCH_REGS_HDA_H_\r
+#define _PCH_REGS_HDA_H_\r
+\r
+///\r
+/// Azalia Controller Registers (D27:F0)\r
+///\r
+#define PCI_DEVICE_NUMBER_PCH_AZALIA       27\r
+#define PCI_FUNCTION_NUMBER_PCH_AZALIA     0\r
+\r
+#define R_PCH_HDA_PCS                      0x54  // Power Management Control and Status\r
+#define B_PCH_HDA_PCS_DATA                 0xFF000000 // Data, does not apply\r
+#define B_PCH_HDA_PCS_CCE                  BIT23 // Bus Power Control Enable, does not apply\r
+#define B_PCH_HDA_PCS_PMES                 BIT15 // PME Status\r
+#define B_PCH_HDA_PCS_PMEE                 BIT8  // PME Enable\r
+#define B_PCH_HDA_PCS_PS                   (BIT1 | BIT0) // Power State - D0/D3 Hot\r
+#define V_PCH_HDA_PCS_PS0                  0x00\r
+#define V_PCH_HDA_PCS_PS3                  0x03\r
+\r
+#endif\r

diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/PchRegsLpss.h b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/PchRegsLpss.h
new file mode 100644 (file)
index 0000000..4e3cd6c
--- /dev/null
+++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/PchRegsLpss.h
@@ -0,0 +1,492 @@
+/*++\r
+\r
+Copyright (c) 2012  - 2014, Intel Corporation. All rights reserved\r
+\r
+  This program and the accompanying materials are licensed and made available under\r
+  the terms and conditions of the BSD License that accompanies this distribution.\r
+  The full text of the license may be found at\r
+  http://opensource.org/licenses/bsd-license.php.\r
+\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+\r
+Module Name:\r
+\r
+  PchRegsLpss.h\r
+\r
+Abstract:\r
+\r
+  Register names for VLV Low Input Output (LPSS) module.\r
+\r
+  Conventions:\r
+\r
+  - Prefixes:\r
+    Definitions beginning with "R_" are registers\r
+    Definitions beginning with "B_" are bits within registers\r
+    Definitions beginning with "V_" are meaningful values of bits within the registers\r
+    Definitions beginning with "S_" are register sizes\r
+    Definitions beginning with "N_" are the bit position\r
+  - In general, PCH registers are denoted by "_PCH_" in register names\r
+  - Registers / bits that are different between PCH generations are denoted by\r
+    "_PCH_<generation_name>_" in register/bit names. e.g., "_PCH_VLV_"\r
+  - Registers / bits that are different between SKUs are denoted by "_<SKU_name>"\r
+    at the end of the register/bit names\r
+  - Registers / bits of new devices introduced in a PCH generation will be just named\r
+    as "_PCH_" without <generation_name> inserted.\r
+\r
+--*/\r
+#ifndef _PCH_REGS_LPSS_H_\r
+#define _PCH_REGS_LPSS_H_\r
+\r
+\r
+//\r
+// Low Power Input Output (LPSS) Module Registers\r
+//\r
+\r
+//\r
+// LPSS DMAC Modules\r
+// PCI Config Space Registers\r
+//\r
+#define PCI_DEVICE_NUMBER_PCH_LPSS_DMAC0          30\r
+#define PCI_DEVICE_NUMBER_PCH_LPSS_DMAC1          24\r
+#define PCI_FUNCTION_NUMBER_PCH_LPSS_DMAC         0\r
+\r
+#define R_PCH_LPSS_DMAC_DEVVENDID                 0x00  // Device ID & Vendor ID\r
+#define B_PCH_LPSS_DMAC_DEVVENDID_DID             0xFFFF0000 // Device ID\r
+#define B_PCH_LPSS_DMAC_DEVVENDID_VID             0x0000FFFF // Vendor ID\r
+\r
+#define R_PCH_LPSS_DMAC_STSCMD                    0x04  // Status & Command\r
+#define B_PCH_LPSS_DMAC_STSCMD_RMA                BIT29 // RMA\r
+#define B_PCH_LPSS_DMAC_STSCMD_RCA                BIT28 // RCA\r
+#define B_PCH_LPSS_DMAC_STSCMD_CAPLIST            BIT20 // Capability List\r
+#define B_PCH_LPSS_DMAC_STSCMD_INTRSTS            BIT19 // Interrupt Status\r
+#define B_PCH_LPSS_DMAC_STSCMD_INTRDIS            BIT10 // Interrupt Disable\r
+#define B_PCH_LPSS_DMAC_STSCMD_SERREN             BIT8  // SERR# Enable\r
+#define B_PCH_LPSS_DMAC_STSCMD_BME                BIT2  // Bus Master Enable\r
+#define B_PCH_LPSS_DMAC_STSCMD_MSE                BIT1  // Memory Space Enable\r
+\r
+#define R_PCH_LPSS_DMAC_REVCC                     0x08  // Revision ID & Class Code\r
+#define B_PCH_LPSS_DMAC_REVCC_CC                  0xFFFFFF00 // Class Code\r
+#define B_PCH_LPSS_DMAC_REVCC_RID                 0x000000FF // Revision ID\r
+\r
+#define R_PCH_LPSS_DMAC_CLHB                      0x0C\r
+#define B_PCH_LPSS_DMAC_CLHB_MULFNDEV             BIT23\r
+#define B_PCH_LPSS_DMAC_CLHB_HT                   0x007F0000 // Header Type\r
+#define B_PCH_LPSS_DMAC_CLHB_LT                   0x0000FF00 // Latency Timer\r
+#define B_PCH_LPSS_DMAC_CLHB_CLS                  0x000000FF // Cache Line Size\r
+\r
+#define R_PCH_LPSS_DMAC_BAR                       0x10  // BAR\r
+#define B_PCH_LPSS_DMAC_BAR_BA                    0xFFFFC000 // Base Address\r
+#define V_PCH_LPSS_DMAC_BAR_SIZE                  0x4000\r
+#define N_PCH_LPSS_DMAC_BAR_ALIGNMENT             14\r
+#define B_PCH_LPSS_DMAC_BAR_SI                    0x00000FF0 // Size Indicator\r
+#define B_PCH_LPSS_DMAC_BAR_PF                    BIT3  // Prefetchable\r
+#define B_PCH_LPSS_DMAC_BAR_TYPE                  (BIT2 | BIT1) // Type\r
+#define B_PCH_LPSS_DMAC_BAR_MS                    BIT0  // Message Space\r
+\r
+#define R_PCH_LPSS_DMAC_BAR1                      0x14  // BAR 1\r
+#define B_PCH_LPSS_DMAC_BAR1_BA                   0xFFFFF000 // Base Address\r
+#define B_PCH_LPSS_DMAC_BAR1_SI                   0x00000FF0 // Size Indicator\r
+#define B_PCH_LPSS_DMAC_BAR1_PF                   BIT3  // Prefetchable\r
+#define B_PCH_LPSS_DMAC_BAR1_TYPE                 (BIT2 | BIT1) // Type\r
+#define B_PCH_LPSS_DMAC_BAR1_MS                   BIT0  // Message Space\r
+\r
+#define R_PCH_LPSS_DMAC_SSID                      0x2C  // Sub System ID\r
+#define B_PCH_LPSS_DMAC_SSID_SID                  0xFFFF0000 // Sub System ID\r
+#define B_PCH_LPSS_DMAC_SSID_SVID                 0x0000FFFF // Sub System Vendor ID\r
+\r
+#define R_PCH_LPSS_DMAC_ERBAR                     0x30  // Expansion ROM BAR\r
+#define B_PCH_LPSS_DMAC_ERBAR_BA                  0xFFFFFFFF // Expansion ROM Base Address\r
+\r
+#define R_PCH_LPSS_DMAC_CAPPTR                    0x34  // Capability Pointer\r
+#define B_PCH_LPSS_DMAC_CAPPTR_CPPWR              0xFF  // Capability Pointer Power\r
+\r
+#define R_PCH_LPSS_DMAC_INTR                      0x3C  // Interrupt\r
+#define B_PCH_LPSS_DMAC_INTR_ML                   0xFF000000 // Max Latency\r
+#define B_PCH_LPSS_DMAC_INTR_MG                   0x00FF0000\r
+#define B_PCH_LPSS_DMAC_INTR_IP                   0x00000F00 // Interrupt Pin\r
+#define B_PCH_LPSS_DMAC_INTR_IL                   0x000000FF // Interrupt Line\r
+\r
+#define R_PCH_LPSS_DMAC_PCAPID                    0x80  // Power Capability ID\r
+#define B_PCH_LPSS_DMAC_PCAPID_PS                 0xF8000000 // PME Support\r
+#define B_PCH_LPSS_DMAC_PCAPID_VS                 0x00070000 // Version\r
+#define B_PCH_LPSS_DMAC_PCAPID_NC                 0x0000FF00 // Next Capability\r
+#define B_PCH_LPSS_DMAC_PCAPID_PC                 0x000000FF // Power Capability\r
+\r
+#define R_PCH_LPSS_DMAC_PCS                       0x84  // PME Control Status\r
+#define B_PCH_LPSS_DMAC_PCS_PMESTS                BIT15 // PME Status\r
+#define B_PCH_LPSS_DMAC_PCS_PMEEN                 BIT8  // PME Enable\r
+#define B_PCH_LPSS_DMAC_PCS_NSS                   BIT3  // No Soft Reset\r
+#define B_PCH_LPSS_DMAC_PCS_PS                    (BIT1 | BIT0) // Power State\r
+\r
+#define R_PCH_LPSS_DMAC_MANID                     0xF8  // Manufacturer ID\r
+#define B_PCH_LPSS_DMAC_MANID_MANID               0xFFFFFFFF // Manufacturer ID\r
+\r
+\r
+//\r
+// LPSS I2C Module\r
+// PCI Config Space Registers\r
+//\r
+#define PCI_DEVICE_NUMBER_PCH_LPSS_I2C            24\r
+#define PCI_FUNCTION_NUMBER_PCH_LPSS_I2C0         1\r
+#define PCI_FUNCTION_NUMBER_PCH_LPSS_I2C1         2\r
+#define PCI_FUNCTION_NUMBER_PCH_LPSS_I2C2         3\r
+#define PCI_FUNCTION_NUMBER_PCH_LPSS_I2C3         4\r
+#define PCI_FUNCTION_NUMBER_PCH_LPSS_I2C4         5\r
+#define PCI_FUNCTION_NUMBER_PCH_LPSS_I2C5         6\r
+#define PCI_FUNCTION_NUMBER_PCH_LPSS_I2C6         7\r
+\r
+#define R_PCH_LPSS_I2C_DEVVENDID                  0x00  // Device ID & Vendor ID\r
+#define B_PCH_LPSS_I2C_DEVVENDID_DID              0xFFFF0000 // Device ID\r
+#define B_PCH_LPSS_I2C_DEVVENDID_VID              0x0000FFFF // Vendor ID\r
+\r
+#define R_PCH_LPSS_I2C_STSCMD                     0x04  // Status & Command\r
+#define B_PCH_LPSS_I2C_STSCMD_RMA                 BIT29 // RMA\r
+#define B_PCH_LPSS_I2C_STSCMD_RCA                 BIT28 // RCA\r
+#define B_PCH_LPSS_I2C_STSCMD_CAPLIST             BIT20 // Capability List\r
+#define B_PCH_LPSS_I2C_STSCMD_INTRSTS             BIT19 // Interrupt Status\r
+#define B_PCH_LPSS_I2C_STSCMD_INTRDIS             BIT10 // Interrupt Disable\r
+#define B_PCH_LPSS_I2C_STSCMD_SERREN              BIT8  // SERR# Enable\r
+#define B_PCH_LPSS_I2C_STSCMD_BME                 BIT2  // Bus Master Enable\r
+#define B_PCH_LPSS_I2C_STSCMD_MSE                 BIT1  // Memory Space Enable\r
+\r
+#define R_PCH_LPSS_I2C_REVCC                      0x08  // Revision ID & Class Code\r
+#define B_PCH_LPSS_I2C_REVCC_CC                   0xFFFFFF00 // Class Code\r
+#define B_PCH_LPSS_I2C_REVCC_RID                  0x000000FF // Revision ID\r
+\r
+#define R_PCH_LPSS_I2C_CLHB                       0x0C\r
+#define B_PCH_LPSS_I2C_CLHB_MULFNDEV              BIT23\r
+#define B_PCH_LPSS_I2C_CLHB_HT                    0x007F0000 // Header Type\r
+#define B_PCH_LPSS_I2C_CLHB_LT                    0x0000FF00 // Latency Timer\r
+#define B_PCH_LPSS_I2C_CLHB_CLS                   0x000000FF // Cache Line Size\r
+\r
+#define R_PCH_LPSS_I2C_BAR                        0x10  // BAR\r
+#define B_PCH_LPSS_I2C_BAR_BA                     0xFFFFF000 // Base Address\r
+#define V_PCH_LPSS_I2C_BAR_SIZE                   0x1000\r
+#define N_PCH_LPSS_I2C_BAR_ALIGNMENT              12\r
+#define B_PCH_LPSS_I2C_BAR_SI                     0x00000FF0 // Size Indicator\r
+#define B_PCH_LPSS_I2C_BAR_PF                     BIT3  // Prefetchable\r
+#define B_PCH_LPSS_I2C_BAR_TYPE                   (BIT2 | BIT1) // Type\r
+#define B_PCH_LPSS_I2C_BAR_MS                     BIT0  // Message Space\r
+\r
+#define R_PCH_LPSS_I2C_BAR1                       0x14  // BAR 1\r
+#define B_PCH_LPSS_I2C_BAR1_BA                    0xFFFFF000 // Base Address\r
+#define B_PCH_LPSS_I2C_BAR1_SI                    0x00000FF0 // Size Indicator\r
+#define B_PCH_LPSS_I2C_BAR1_PF                    BIT3  // Prefetchable\r
+#define B_PCH_LPSS_I2C_BAR1_TYPE                  (BIT2 | BIT1) // Type\r
+#define B_PCH_LPSS_I2C_BAR1_MS                    BIT0  // Message Space\r
+\r
+#define R_PCH_LPSS_I2C_SSID                       0x2C  // Sub System ID\r
+#define B_PCH_LPSS_I2C_SSID_SID                   0xFFFF0000 // Sub System ID\r
+#define B_PCH_LPSS_I2C_SSID_SVID                  0x0000FFFF // Sub System Vendor ID\r
+\r
+#define R_PCH_LPSS_I2C_ERBAR                      0x30  // Expansion ROM BAR\r
+#define B_PCH_LPSS_I2C_ERBAR_BA                   0xFFFFFFFF // Expansion ROM Base Address\r
+\r
+#define R_PCH_LPSS_I2C_CAPPTR                     0x34  // Capability Pointer\r
+#define B_PCH_LPSS_I2C_CAPPTR_CPPWR               0xFF  // Capability Pointer Power\r
+\r
+#define R_PCH_LPSS_I2C_INTR                       0x3C  // Interrupt\r
+#define B_PCH_LPSS_I2C_INTR_ML                    0xFF000000 // Max Latency\r
+#define B_PCH_LPSS_I2C_INTR_MG                    0x00FF0000\r
+#define B_PCH_LPSS_I2C_INTR_IP                    0x00000F00 // Interrupt Pin\r
+#define B_PCH_LPSS_I2C_INTR_IL                    0x000000FF // Interrupt Line\r
+\r
+#define R_PCH_LPSS_I2C_PCAPID                     0x80  // Power Capability ID\r
+#define B_PCH_LPSS_I2C_PCAPID_PS                  0xF8000000 // PME Support\r
+#define B_PCH_LPSS_I2C_PCAPID_VS                  0x00070000 // Version\r
+#define B_PCH_LPSS_I2C_PCAPID_NC                  0x0000FF00 // Next Capability\r
+#define B_PCH_LPSS_I2C_PCAPID_PC                  0x000000FF // Power Capability\r
+\r
+#define R_PCH_LPSS_I2C_PCS                        0x84  // PME Control Status\r
+#define B_PCH_LPSS_I2C_PCS_PMESTS                 BIT15 // PME Status\r
+#define B_PCH_LPSS_I2C_PCS_PMEEN                  BIT8  // PME Enable\r
+#define B_PCH_LPSS_I2C_PCS_NSS                    BIT3  // No Soft Reset\r
+#define B_PCH_LPSS_I2C_PCS_PS                     (BIT1 | BIT0) // Power State\r
+\r
+#define R_PCH_LPSS_I2C_MANID                      0xF8  // Manufacturer ID\r
+#define B_PCH_LPSS_I2C_MANID_MANID                0xFFFFFFFF // Manufacturer ID\r
+\r
+//\r
+// LPSS I2C Module\r
+// Memory Space Registers\r
+//\r
+#define R_PCH_LPSS_I2C_MEM_RESETS                 0x804 // Software Reset\r
+#define B_PCH_LPSS_I2C_MEM_RESETS_FUNC            BIT1  // Function Clock Domain Reset\r
+#define B_PCH_LPSS_I2C_MEM_RESETS_APB             BIT0  // APB Domain Reset\r
+\r
+//\r
+// LPSS PWM Modules\r
+// PCI Config Space Registers\r
+//\r
+#define PCI_DEVICE_NUMBER_PCH_LPSS_PWM            30\r
+#define PCI_FUNCTION_NUMBER_PCH_LPSS_PWM0         1\r
+#define PCI_FUNCTION_NUMBER_PCH_LPSS_PWM1         2\r
+\r
+#define R_PCH_LPSS_PWM_DEVVENDID                  0x00  // Device ID & Vendor ID\r
+#define B_PCH_LPSS_PWM_DEVVENDID_DID              0xFFFF0000 // Device ID\r
+#define B_PCH_LPSS_PWM_DEVVENDID_VID              0x0000FFFF // Vendor ID\r
+\r
+#define R_PCH_LPSS_PWM_STSCMD                     0x04  // Status & Command\r
+#define B_PCH_LPSS_PWM_STSCMD_RMA                 BIT29 // RMA\r
+#define B_PCH_LPSS_PWM_STSCMD_RCA                 BIT28 // RCA\r
+#define B_PCH_LPSS_PWM_STSCMD_CAPLIST             BIT20 // Capability List\r
+#define B_PCH_LPSS_PWM_STSCMD_INTRSTS             BIT19 // Interrupt Status\r
+#define B_PCH_LPSS_PWM_STSCMD_INTRDIS             BIT10 // Interrupt Disable\r
+#define B_PCH_LPSS_PWM_STSCMD_SERREN              BIT8  // SERR# Enable\r
+#define B_PCH_LPSS_PWM_STSCMD_BME                 BIT2  // Bus Master Enable\r
+#define B_PCH_LPSS_PWM_STSCMD_MSE                 BIT1  // Memory Space Enable\r
+\r
+#define R_PCH_LPSS_PWM_REVCC                      0x08  // Revision ID & Class Code\r
+#define B_PCH_LPSS_PWM_REVCC_CC                   0xFFFFFF00 // Class Code\r
+#define B_PCH_LPSS_PWM_REVCC_RID                  0x000000FF // Revision ID\r
+\r
+#define R_PCH_LPSS_PWM_CLHB                       0x0C\r
+#define B_PCH_LPSS_PWM_CLHB_MULFNDEV              BIT23\r
+#define B_PCH_LPSS_PWM_CLHB_HT                    0x007F0000 // Header Type\r
+#define B_PCH_LPSS_PWM_CLHB_LT                    0x0000FF00 // Latency Timer\r
+#define B_PCH_LPSS_PWM_CLHB_CLS                   0x000000FF // Cache Line Size\r
+\r
+#define R_PCH_LPSS_PWM_BAR                        0x10  // BAR\r
+#define B_PCH_LPSS_PWM_BAR_BA                     0xFFFFF000 // Base Address\r
+#define V_PCH_LPSS_PWM_BAR_SIZE                   0x1000\r
+#define N_PCH_LPSS_PWM_BAR_ALIGNMENT              12\r
+#define B_PCH_LPSS_PWM_BAR_SI                     0x00000FF0 // Size Indicator\r
+#define B_PCH_LPSS_PWM_BAR_PF                     BIT3  // Prefetchable\r
+#define B_PCH_LPSS_PWM_BAR_TYPE                   (BIT2 | BIT1) // Type\r
+#define B_PCH_LPSS_PWM_BAR_MS                     BIT0  // Message Space\r
+\r
+#define R_PCH_LPSS_PWM_BAR1                       0x14  // BAR 1\r
+#define B_PCH_LPSS_PWM_BAR1_BA                    0xFFFFF000 // Base Address\r
+#define B_PCH_LPSS_PWM_BAR1_SI                    0x00000FF0 // Size Indicator\r
+#define B_PCH_LPSS_PWM_BAR1_PF                    BIT3  // Prefetchable\r
+#define B_PCH_LPSS_PWM_BAR1_TYPE                  (BIT2 | BIT1) // Type\r
+#define B_PCH_LPSS_PWM_BAR1_MS                    BIT0  // Message Space\r
+\r
+#define R_PCH_LPSS_PWM_SSID                       0x2C  // Sub System ID\r
+#define B_PCH_LPSS_PWM_SSID_SID                   0xFFFF0000 // Sub System ID\r
+#define B_PCH_LPSS_PWM_SSID_SVID                  0x0000FFFF // Sub System Vendor ID\r
+\r
+#define R_PCH_LPSS_PWM_ERBAR                      0x30  // Expansion ROM BAR\r
+#define B_PCH_LPSS_PWM_ERBAR_BA                   0xFFFFFFFF // Expansion ROM Base Address\r
+\r
+#define R_PCH_LPSS_PWM_CAPPTR                     0x34  // Capability Pointer\r
+#define B_PCH_LPSS_PWM_CAPPTR_CPPWR               0xFF  // Capability Pointer Power\r
+\r
+#define R_PCH_LPSS_PWM_INTR                       0x3C  // Interrupt\r
+#define B_PCH_LPSS_PWM_INTR_ML                    0xFF000000 // Max Latency\r
+#define B_PCH_LPSS_PWM_INTR_MG                    0x00FF0000\r
+#define B_PCH_LPSS_PWM_INTR_IP                    0x00000F00 // Interrupt Pin\r
+#define B_PCH_LPSS_PWM_INTR_IL                    0x000000FF // Interrupt Line\r
+\r
+#define R_PCH_LPSS_PWM_PCAPID                     0x80  // Power Capability ID\r
+#define B_PCH_LPSS_PWM_PCAPID_PS                  0xF8000000 // PME Support\r
+#define B_PCH_LPSS_PWM_PCAPID_VS                  0x00070000 // Version\r
+#define B_PCH_LPSS_PWM_PCAPID_NC                  0x0000FF00 // Next Capability\r
+#define B_PCH_LPSS_PWM_PCAPID_PC                  0x000000FF // Power Capability\r
+\r
+#define R_PCH_LPSS_PWM_PCS                        0x84  // PME Control Status\r
+#define B_PCH_LPSS_PWM_PCS_PMESTS                 BIT15 // PME Status\r
+#define B_PCH_LPSS_PWM_PCS_PMEEN                  BIT8  // PME Enable\r
+#define B_PCH_LPSS_PWM_PCS_NSS                    BIT3  // No Soft Reset\r
+#define B_PCH_LPSS_PWM_PCS_PS                     (BIT1 | BIT0) // Power State\r
+\r
+#define R_PCH_LPSS_PWM_MANID                      0xF8  // Manufacturer ID\r
+#define B_PCH_LPSS_PWM_MANID_MANID                0xFFFFFFFF // Manufacturer ID\r
+\r
+//\r
+// LPSS PWM Module\r
+// Memory Space Registers\r
+//\r
+#define R_PCH_LPSS_PWM_MEM_RESETS                 0x804 // Software Reset\r
+#define B_PCH_LPSS_PWM_MEM_RESETS_FUNC            BIT1  // Function Clock Domain Reset\r
+#define B_PCH_LPSS_PWM_MEM_RESETS_APB             BIT0  // APB Domain Reset\r
+\r
+//\r
+// LPSS HSUART Modules\r
+// PCI Config Space Registers\r
+//\r
+#define PCI_DEVICE_NUMBER_PCH_LPSS_HSUART         30\r
+#define PCI_FUNCTION_NUMBER_PCH_LPSS_HSUART0      3\r
+#define PCI_FUNCTION_NUMBER_PCH_LPSS_HSUART1      4\r
+\r
+#define R_PCH_LPSS_HSUART_DEVVENDID               0x00  // Device ID & Vendor ID\r
+#define B_PCH_LPSS_HSUART_DEVVENDID_DID           0xFFFF0000 // Device ID\r
+#define B_PCH_LPSS_HSUART_DEVVENDID_VID           0x0000FFFF // Vendor ID\r
+\r
+#define R_PCH_LPSS_HSUART_STSCMD                  0x04  // Status & Command\r
+#define B_PCH_LPSS_HSUART_STSCMD_RMA              BIT29 // RMA\r
+#define B_PCH_LPSS_HSUART_STSCMD_RCA              BIT28 // RCA\r
+#define B_PCH_LPSS_HSUART_STSCMD_CAPLIST          BIT20 // Capability List\r
+#define B_PCH_LPSS_HSUART_STSCMD_INTRSTS          BIT19 // Interrupt Status\r
+#define B_PCH_LPSS_HSUART_STSCMD_INTRDIS          BIT10 // Interrupt Disable\r
+#define B_PCH_LPSS_HSUART_STSCMD_SERREN           BIT8  // SERR# Enable\r
+#define B_PCH_LPSS_HSUART_STSCMD_BME              BIT2  // Bus Master Enable\r
+#define B_PCH_LPSS_HSUART_STSCMD_MSE              BIT1  // Memory Space Enable\r
+\r
+#define R_PCH_LPSS_HSUART_REVCC                   0x08  // Revision ID & Class Code\r
+#define B_PCH_LPSS_HSUART_REVCC_CC                0xFFFFFF00 // Class Code\r
+#define B_PCH_LPSS_HSUART_REVCC_RID               0x000000FF // Revision ID\r
+\r
+#define R_PCH_LPSS_HSUART_CLHB                    0x0C\r
+#define B_PCH_LPSS_HSUART_CLHB_MULFNDEV           BIT23\r
+#define B_PCH_LPSS_HSUART_CLHB_HT                 0x007F0000 // Header Type\r
+#define B_PCH_LPSS_HSUART_CLHB_LT                 0x0000FF00 // Latency Timer\r
+#define B_PCH_LPSS_HSUART_CLHB_CLS                0x000000FF // Cache Line Size\r
+\r
+#define R_PCH_LPSS_HSUART_BAR                     0x10  // BAR\r
+#define B_PCH_LPSS_HSUART_BAR_BA                  0xFFFFF000 // Base Address\r
+#define V_PCH_LPSS_HSUART_BAR_SIZE                0x1000\r
+#define N_PCH_LPSS_HSUART_BAR_ALIGNMENT           12\r
+#define B_PCH_LPSS_HSUART_BAR_SI                  0x00000FF0 // Size Indicator\r
+#define B_PCH_LPSS_HSUART_BAR_PF                  BIT3  // Prefetchable\r
+#define B_PCH_LPSS_HSUART_BAR_TYPE                (BIT2 | BIT1) // Type\r
+#define B_PCH_LPSS_HSUART_BAR_MS                  BIT0  // Message Space\r
+\r
+#define R_PCH_LPSS_HSUART_BAR1                    0x14  // BAR 1\r
+#define B_PCH_LPSS_HSUART_BAR1_BA                 0xFFFFF000 // Base Address\r
+#define B_PCH_LPSS_HSUART_BAR1_SI                 0x00000FF0 // Size Indicator\r
+#define B_PCH_LPSS_HSUART_BAR1_PF                 BIT3  // Prefetchable\r
+#define B_PCH_LPSS_HSUART_BAR1_TYPE               (BIT2 | BIT1) // Type\r
+#define B_PCH_LPSS_HSUART_BAR1_MS                 BIT0  // Message Space\r
+\r
+#define R_PCH_LPSS_HSUART_SSID                    0x2C  // Sub System ID\r
+#define B_PCH_LPSS_HSUART_SSID_SID                0xFFFF0000 // Sub System ID\r
+#define B_PCH_LPSS_HSUART_SSID_SVID               0x0000FFFF // Sub System Vendor ID\r
+\r
+#define R_PCH_LPSS_HSUART_ERBAR                   0x30  // Expansion ROM BAR\r
+#define B_PCH_LPSS_HSUART_ERBAR_BA                0xFFFFFFFF // Expansion ROM Base Address\r
+\r
+#define R_PCH_LPSS_HSUART_CAPPTR                  0x34  // Capability Pointer\r
+#define B_PCH_LPSS_HSUART_CAPPTR_CPPWR            0xFF  // Capability Pointer Power\r
+\r
+#define R_PCH_LPSS_HSUART_INTR                    0x3C  // Interrupt\r
+#define B_PCH_LPSS_HSUART_INTR_ML                 0xFF000000 // Max Latency\r
+#define B_PCH_LPSS_HSUART_INTR_MG                 0x00FF0000\r
+#define B_PCH_LPSS_HSUART_INTR_IP                 0x00000F00 // Interrupt Pin\r
+#define B_PCH_LPSS_HSUART_INTR_IL                 0x000000FF // Interrupt Line\r
+\r
+#define R_PCH_LPSS_HSUART_PCAPID                  0x80  // Power Capability ID\r
+#define B_PCH_LPSS_HSUART_PCAPID_PS               0xF8000000 // PME Support\r
+#define B_PCH_LPSS_HSUART_PCAPID_VS               0x00070000 // Version\r
+#define B_PCH_LPSS_HSUART_PCAPID_NC               0x0000FF00 // Next Capability\r
+#define B_PCH_LPSS_HSUART_PCAPID_PC               0x000000FF // Power Capability\r
+\r
+#define R_PCH_LPSS_HSUART_PCS                     0x84  // PME Control Status\r
+#define B_PCH_LPSS_HSUART_PCS_PMESTS              BIT15 // PME Status\r
+#define B_PCH_LPSS_HSUART_PCS_PMEEN               BIT8  // PME Enable\r
+#define B_PCH_LPSS_HSUART_PCS_NSS                 BIT3  // No Soft Reset\r
+#define B_PCH_LPSS_HSUART_PCS_PS                  (BIT1 | BIT0) // Power State\r
+\r
+#define R_PCH_LPSS_HSUART_MANID                   0xF8  // Manufacturer ID\r
+#define B_PCH_LPSS_HSUART_MANID_MANID             0xFFFFFFFF // Manufacturer ID\r
+\r
+//\r
+// LPSS HSUART Module\r
+// Memory Space Registers\r
+//\r
+#define R_PCH_LPSS_HSUART_MEM_PCP                 0x800 // Private Clock Parameters\r
+#define B_PCH_LPSS_HSUART_MEM_PCP_CLKUPDATE       BIT31 // Clock Divider Update\r
+#define B_PCH_LPSS_HSUART_MEM_PCP_NVAL            0x7FFF0000 // N value for the M over N divider\r
+#define B_PCH_LPSS_HSUART_MEM_PCP_MVAL            0x0000FFFE // M value for the M over N divider\r
+#define B_PCH_LPSS_HSUART_MEM_PCP_CLKEN           BIT0  // Clock Enable\r
+\r
+#define R_PCH_LPSS_HSUART_MEM_RESETS              0x804 // Software Reset\r
+#define B_PCH_LPSS_HSUART_MEM_RESETS_FUNC         BIT1  // Function Clock Domain Reset\r
+#define B_PCH_LPSS_HSUART_MEM_RESETS_APB          BIT0  // APB Domain Reset\r
+\r
+//\r
+// LPSS SPI Module\r
+// PCI Config Space Registers\r
+//\r
+#define PCI_DEVICE_NUMBER_PCH_LPSS_SPI            30\r
+#define PCI_FUNCTION_NUMBER_PCH_LPSS_SPI          5\r
+\r
+#define R_PCH_LPSS_SPI_DEVVENDID                  0x00  // Device ID & Vendor ID\r
+#define B_PCH_LPSS_SPI_DEVVENDID_DID              0xFFFF0000 // Device ID\r
+#define B_PCH_LPSS_SPI_DEVVENDID_VID              0x0000FFFF // Vendor ID\r
+\r
+#define R_PCH_LPSS_SPI_STSCMD                     0x04  // Status & Command\r
+#define B_PCH_LPSS_SPI_STSCMD_RMA                 BIT29 // RMA\r
+#define B_PCH_LPSS_SPI_STSCMD_RCA                 BIT28 // RCA\r
+#define B_PCH_LPSS_SPI_STSCMD_CAPLIST             BIT20 // Capability List\r
+#define B_PCH_LPSS_SPI_STSCMD_INTRSTS             BIT19 // Interrupt Status\r
+#define B_PCH_LPSS_SPI_STSCMD_INTRDIS             BIT10 // Interrupt Disable\r
+#define B_PCH_LPSS_SPI_STSCMD_SERREN              BIT8  // SERR# Enable\r
+#define B_PCH_LPSS_SPI_STSCMD_BME                 BIT2  // Bus Master Enable\r
+#define B_PCH_LPSS_SPI_STSCMD_MSE                 BIT1  // Memory Space Enable\r
+\r
+#define R_PCH_LPSS_SPI_REVCC                      0x08  // Revision ID & Class Code\r
+#define B_PCH_LPSS_SPI_REVCC_CC                   0xFFFFFF00 // Class Code\r
+#define B_PCH_LPSS_SPI_REVCC_RID                  0x000000FF // Revision ID\r
+\r
+#define R_PCH_LPSS_SPI_CLHB                       0x0C\r
+#define B_PCH_LPSS_SPI_CLHB_MULFNDEV              BIT23\r
+#define B_PCH_LPSS_SPI_CLHB_HT                    0x007F0000 // Header Type\r
+#define B_PCH_LPSS_SPI_CLHB_LT                    0x0000FF00 // Latency Timer\r
+#define B_PCH_LPSS_SPI_CLHB_CLS                   0x000000FF // Cache Line Size\r
+\r
+#define R_PCH_LPSS_SPI_BAR                        0x10  // BAR\r
+#define B_PCH_LPSS_SPI_BAR_BA                     0xFFFFF000 // Base Address\r
+#define V_PCH_LPSS_SPI_BAR_SIZE                   0x1000\r
+#define N_PCH_LPSS_SPI_BAR_ALIGNMENT              12\r
+#define B_PCH_LPSS_SPI_BAR_SI                     0x00000FF0 // Size Indicator\r
+#define B_PCH_LPSS_SPI_BAR_PF                     BIT3  // Prefetchable\r
+#define B_PCH_LPSS_SPI_BAR_TYPE                   (BIT2 | BIT1) // Type\r
+#define B_PCH_LPSS_SPI_BAR_MS                     BIT0  // Message Space\r
+\r
+#define R_PCH_LPSS_SPI_BAR1                       0x14  // BAR 1\r
+#define B_PCH_LPSS_SPI_BAR1_BA                    0xFFFFF000 // Base Address\r
+#define B_PCH_LPSS_SPI_BAR1_SI                    0x00000FF0 // Size Indicator\r
+#define B_PCH_LPSS_SPI_BAR1_PF                    BIT3  // Prefetchable\r
+#define B_PCH_LPSS_SPI_BAR1_TYPE                  (BIT2 | BIT1) // Type\r
+#define B_PCH_LPSS_SPI_BAR1_MS                    BIT0  // Message Space\r
+\r
+#define R_PCH_LPSS_SPI_SSID                       0x2C  // Sub System ID\r
+#define B_PCH_LPSS_SPI_SSID_SID                   0xFFFF0000 // Sub System ID\r
+#define B_PCH_LPSS_SPI_SSID_SVID                  0x0000FFFF // Sub System Vendor ID\r
+\r
+#define R_PCH_LPSS_SPI_ERBAR                      0x30  // Expansion ROM BAR\r
+#define B_PCH_LPSS_SPI_ERBAR_BA                   0xFFFFFFFF // Expansion ROM Base Address\r
+\r
+#define R_PCH_LPSS_SPI_CAPPTR                     0x34  // Capability Pointer\r
+#define B_PCH_LPSS_SPI_CAPPTR_CPPWR               0xFF  // Capability Pointer Power\r
+\r
+#define R_PCH_LPSS_SPI_INTR                       0x3C  // Interrupt\r
+#define B_PCH_LPSS_SPI_INTR_ML                    0xFF000000 // Max Latency\r
+#define B_PCH_LPSS_SPI_INTR_MG                    0x00FF0000\r
+#define B_PCH_LPSS_SPI_INTR_IP                    0x00000F00 // Interrupt Pin\r
+#define B_PCH_LPSS_SPI_INTR_IL                    0x000000FF // Interrupt Line\r
+\r
+#define R_PCH_LPSS_SPI_PCAPID                     0x80  // Power Capability ID\r
+#define B_PCH_LPSS_SPI_PCAPID_PS                  0xF8000000 // PME Support\r
+#define B_PCH_LPSS_SPI_PCAPID_VS                  0x00070000 // Version\r
+#define B_PCH_LPSS_SPI_PCAPID_NC                  0x0000FF00 // Next Capability\r
+#define B_PCH_LPSS_SPI_PCAPID_PC                  0x000000FF // Power Capability\r
+\r
+#define R_PCH_LPSS_SPI_PCS                        0x84  // PME Control Status\r
+#define B_PCH_LPSS_SPI_PCS_PMESTS                 BIT15 // PME Status\r
+#define B_PCH_LPSS_SPI_PCS_PMEEN                  BIT8  // PME Enable\r
+#define B_PCH_LPSS_SPI_PCS_NSS                    BIT3  // No Soft Reset\r
+#define B_PCH_LPSS_SPI_PCS_PS                     (BIT1 | BIT0) // Power State\r
+\r
+#define R_PCH_LPSS_SPI_MANID                      0xF8  // Manufacturer ID\r
+#define B_PCH_LPSS_SPI_MANID_MANID                0xFFFFFFFF // Manufacturer ID\r
+\r
+//\r
+// LPSS SPI Module\r
+// Memory Space Registers\r
+//\r
+#define R_PCH_LPSS_SPI_MEM_PCP                    0x400 // Private Clock Parameters\r
+#define B_PCH_LPSS_SPI_MEM_PCP_CLKUPDATE          BIT31 // Clock Divider Update\r
+#define B_PCH_LPSS_SPI_MEM_PCP_NVAL               0x7FFF0000 // N value for the M over N divider\r
+#define B_PCH_LPSS_SPI_MEM_PCP_MVAL               0x0000FFFE // M value for the M over N divider\r
+#define B_PCH_LPSS_SPI_MEM_PCP_CLKEN              BIT0  // Clock Enable\r
+\r
+#define R_PCH_LPSS_SPI_MEM_RESETS                 0x404 // Software Reset\r
+#define B_PCH_LPSS_SPI_MEM_RESETS_FUNC            BIT1  // Function Clock Domain Reset\r
+#define B_PCH_LPSS_SPI_MEM_RESETS_APB             BIT0  // APB Domain Reset\r
+\r
+#endif\r

diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/PchRegsPcie.h b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/PchRegsPcie.h
new file mode 100644 (file)
index 0000000..bb50709
--- /dev/null
+++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/PchRegsPcie.h
@@ -0,0 +1,89 @@
+/**\r
+\r
+Copyright (c) 2012  - 2014, Intel Corporation. All rights reserved\r
+\r
+  This program and the accompanying materials are licensed and made available under\r
+  the terms and conditions of the BSD License that accompanies this distribution.\r
+  The full text of the license may be found at\r
+  http://opensource.org/licenses/bsd-license.php.\r
+\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+\r
+  @file\r
+  PchRegsPcie.h\r
+\r
+  @brief\r
+  Register names for VLV PCI-E root port devices\r
+\r
+  Conventions:\r
+\r
+  - Prefixes:\r
+    Definitions beginning with "R_" are registers\r
+    Definitions beginning with "B_" are bits within registers\r
+    Definitions beginning with "V_" are meaningful values of bits within the registers\r
+    Definitions beginning with "S_" are register sizes\r
+    Definitions beginning with "N_" are the bit position\r
+  - In general, PCH registers are denoted by "_PCH_" in register names\r
+  - Registers / bits that are different between PCH generations are denoted by\r
+    "_PCH_<generation_name>_" in register/bit names. e.g., "_PCH_VLV_"\r
+  - Registers / bits that are different between SKUs are denoted by "_<SKU_name>"\r
+    at the end of the register/bit names\r
+  - Registers / bits of new devices introduced in a PCH generation will be just named\r
+    as "_PCH_" without <generation_name> inserted.\r
+\r
+--*/\r
+#ifndef _PCH_REGS_PCIE_H_\r
+#define _PCH_REGS_PCIE_H_\r
+\r
+#define PCH_PCIE_MAX_ROOT_PORTS                            4\r
+\r
+///\r
+/// VLV PCI Express Root Ports (D28:F0~F3)\r
+///\r
+#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORTS              28\r
+#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_1           0\r
+#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_2           1\r
+#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_3           2\r
+#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_4           3\r
+\r
+#define R_PCH_PCIE_ID                                      0x00  // Identifiers\r
+#define B_PCH_PCIE_ID_DID                                  0xFFFF0000 // Device ID\r
+#define V_PCH_PCIE_DEVICE_ID_0                             0x0F48  // PCIE Root Port #1\r
+#define V_PCH_PCIE_DEVICE_ID_1                             0x0F4A  // PCIE Root Port #2\r
+#define V_PCH_PCIE_DEVICE_ID_2                             0x0F4C  // PCIE Root Port #3\r
+#define V_PCH_PCIE_DEVICE_ID_3                             0x0F4E  // PCIE Root Port #4\r
+#define B_PCH_PCIE_ID_VID                                  0x0000FFFF // Vendor ID\r
+#define V_PCH_PCIE_VENDOR_ID                               V_PCH_INTEL_VENDOR_ID\r
+\r
+\r
+#define R_PCH_PCIE_BNUM_SLT                                0x18  // Bus Numbers; Secondary Latency Timer\r
+#define B_PCH_PCIE_BNUM_SLT_SLT                            0xFF000000 // Secondary Latency Timer\r
+#define B_PCH_PCIE_BNUM_SLT_SBBN                           0x00FF0000 // Subordinate Bus Number\r
+#define B_PCH_PCIE_BNUM_SLT_SCBN                           0x0000FF00 // Secondary Bus Number\r
+#define B_PCH_PCIE_BNUM_SLT_PBN                            0x000000FF // Primary Bus Number\r
+#define R_PCH_PCIE_CAPP                                    0x34  // Capabilities List Pointer\r
+#define B_PCH_PCIE_CAPP                                    0xFF  // Capabilities Pointer\r
+\r
+#define R_PCH_PCIE_SLCTL_SLSTS                             0x58  // Slot Control; Slot Status\r
+#define S_PCH_PCIE_SLCTL_SLSTS                             4\r
+#define B_PCH_PCIE_SLCTL_SLSTS_DLLSC                       BIT24 // Data Link Layer State Changed\r
+#define B_PCH_PCIE_SLCTL_SLSTS_PDS                         BIT22 // Presence Detect State\r
+#define B_PCH_PCIE_SLCTL_SLSTS_MS                          BIT21 // MRL Sensor State\r
+#define B_PCH_PCIE_SLCTL_SLSTS_PDC                         BIT19 // Presence Detect Changed\r
+#define B_PCH_PCIE_SLCTL_SLSTS_MSC                         BIT18 // MRL Sensor Changed\r
+#define B_PCH_PCIE_SLCTL_SLSTS_PFD                         BIT17 // Power Fault Detected\r
+#define B_PCH_PCIE_SLCTL_SLSTS_DLLSCE                      BIT12 // Data Link Layer State Changed Enable\r
+#define B_PCH_PCIE_SLCTL_SLSTS_PCC                         BIT10 // Power Controller Control\r
+#define B_PCH_PCIE_SLCTL_SLSTS_HPE                         BIT5  // Hot Plug Interrupt Enable\r
+#define B_PCH_PCIE_SLCTL_SLSTS_CCE                         BIT4  // Command Completed Interrupt Enable\r
+#define B_PCH_PCIE_SLCTL_SLSTS_PDE                         BIT3  // Presence Detect Changed Enable\r
+\r
+#define R_PCH_PCIE_SVID                                    0x94  // Subsystem Vendor IDs\r
+#define S_PCH_PCIE_SVID                                    4\r
+#define B_PCH_PCIE_SVID_SID                                0xFFFF0000 // Subsystem Identifier\r
+#define B_PCH_PCIE_SVID_SVID                               0x0000FFFF // Subsystem Vendor Identifier\r
+\r
+#endif\r

diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/PchRegsPcu.h b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/PchRegsPcu.h
new file mode 100644 (file)
index 0000000..2962989
--- /dev/null
+++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/PchRegsPcu.h
@@ -0,0 +1,1205 @@
+/*++\r
+\r
+Copyright (c) 2012  - 2014, Intel Corporation. All rights reserved\r
+\r
+  This program and the accompanying materials are licensed and made available under\r
+  the terms and conditions of the BSD License that accompanies this distribution.\r
+  The full text of the license may be found at\r
+  http://opensource.org/licenses/bsd-license.php.\r
+\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+\r
+Module Name:\r
+\r
+  PchRegsPcu.h\r
+\r
+Abstract:\r
+\r
+  Register names for VLV PCU device.\r
+\r
+  Conventions:\r
+\r
+  - Prefixes:\r
+    Definitions beginning with "R_" are registers\r
+    Definitions beginning with "B_" are bits within registers\r
+    Definitions beginning with "V_" are meaningful values of bits within the registers\r
+    Definitions beginning with "S_" are register sizes\r
+    Definitions beginning with "N_" are the bit position\r
+  - In general, PCH registers are denoted by "_PCH_" in register names\r
+  - Registers / bits that are different between PCH generations are denoted by\r
+    "_PCH_<generation_name>_" in register/bit names. e.g., "_PCH_VLV_"\r
+  - Registers / bits that are different between SKUs are denoted by "_<SKU_name>"\r
+    at the end of the register/bit names\r
+  - Registers / bits of new devices introduced in a PCH generation will be just named\r
+    as "_PCH_" without <generation_name> inserted.\r
+\r
+--*/\r
+#ifndef _PCH_REGS_LPC_H_\r
+#define _PCH_REGS_LPC_H_\r
+\r
+//\r
+// VLV PCU Registers (D31:F0)\r
+//\r
+#define PCI_DEVICE_NUMBER_PCH_LPC                 31\r
+#define PCI_FUNCTION_NUMBER_PCH_LPC               0\r
+\r
+// Silicon Steppings\r
+typedef enum {\r
+  PchA0         = 0,\r
+  PchA1         = 1,\r
+  PchB0         = 2,\r
+  PchB1         = 3,\r
+  PchB2         = 4,\r
+  PchB3         = 5,\r
+  PchC0         = 6,\r
+  PchD0         = 7,\r
+  PchSteppingMax\r
+} PCH_STEPPING;\r
+\r
+#define R_PCH_LPC_REG_ID                          0x00  // Identifiers Register\r
+#define B_PCH_LPC_DEVICE_ID                       0xFFFF0000 // Device Identification\r
+#define B_PCH_LPC_VENDOR_ID                       0x0000FFFF // Vendor Identification\r
+#define V_PCH_LPC_VENDOR_ID                       V_PCH_INTEL_VENDOR_ID // Vendor ID for Intel\r
+//\r
+// General VLV PCU Device ID\r
+//\r
+#define V_PCH_LPC_DEVICE_ID_0                     0x0F1C\r
+#define V_PCH_LPC_DEVICE_ID_1                     0x0F1D\r
+#define V_PCH_LPC_DEVICE_ID_2                     0x0F1E\r
+#define V_PCH_LPC_DEVICE_ID_3                     0x0F1F\r
+\r
+#define R_PCH_LPC_COMMAND                         0x04  // Command\r
+#define B_PCH_LPC_COMMAND_ID                      BIT10 // Interrupt Disable\r
+#define B_PCH_LPC_COMMAND_FBE                     BIT9  // Fast Back to Back Enable\r
+#define B_PCH_LPC_COMMAND_SERR_EN                 BIT8  // SERR# Enable\r
+#define B_PCH_LPC_COMMAND_WCC                     BIT7  // Wait Cycle Control\r
+#define B_PCH_LPC_COMMAND_PER                     BIT6  // Parity Error Response Enable\r
+#define B_PCH_LPC_COMMAND_VPS                     BIT5  // VGA Palette Snoop\r
+#define B_PCH_LPC_COMMAND_MWIE                    BIT4  // Memory Write and Invalidate Enable\r
+#define B_PCH_LPC_COMMAND_SCE                     BIT3  // Special Cycle Enable\r
+#define B_PCH_LPC_COMMAND_BME                     BIT2  // Bus Master Enable\r
+#define B_PCH_LPC_COMMAND_MSE                     BIT1  // Memory Space Enable\r
+#define B_PCH_LPC_COMMAND_IOSE                    BIT0  // I/O Space Enable\r
+\r
+#define R_PCH_LPC_DEV_STS                         0x06  // Status\r
+#define B_PCH_LPC_DEV_STS_DPE                     BIT15 // Detected Parity Error\r
+#define B_PCH_LPC_DEV_STS_SSE                     BIT14 // Signaled System Error\r
+#define B_PCH_LPC_DEV_STS_RMA                     BIT13 // Received Master Abort\r
+#define B_PCH_LPC_DEV_STS_RTA                     BIT12 // Received Target Abort\r
+#define B_PCH_LPC_DEV_STS_STA                     BIT11 // Signaled Target Abort\r
+#define B_PCH_LPC_DEV_STS_DEVT_STS                (BIT10 | BIT9) // DEVSEL# Timing Status\r
+#define B_PCH_LPC_DEV_STS_MDPED                   BIT8  // Data Parity Error\r
+#define B_PCH_LPC_DEV_STS_FB2B                    BIT7  // Fast Back to Back Capable\r
+#define B_PCH_LPC_DEV_STS_66MHZ_CAP               BIT5  // 66 MHz capable\r
+#define B_PCH_LPC_DEV_STS_CAP_LIST                BIT4  // Capabilities List\r
+#define B_PCH_LPC_DEV_STS_INT_STS                 BIT3  // Interrupt Status\r
+\r
+#define R_PCH_LPC_RID_CC                          0x08  // Revision ID & Class Code\r
+#define B_PCH_LPC_RID_CC_BCC                      0xFF000000 // Base Class Code\r
+#define B_PCH_LPC_RID_CC_SCC                      0x00FF0000 // Sub-Class Code\r
+#define B_PCH_LPC_RID_CC_PI                       0x0000FF00 // Programming Interface\r
+#define B_PCH_LPC_RID_CC_RID                      0x000000FF // Revision ID\r
+\r
+// Silicon Steppings\r
+\r
+#define V_PCH_LPC_RID_0                           0x01  // A0 Stepping (17 x 17)\r
+#define V_PCH_LPC_RID_1                           0x02  // A0 Stepping (25 x 27)\r
+#define V_PCH_LPC_RID_2                           0x03  // A1 Stepping (17 x 17)\r
+#define V_PCH_LPC_RID_3                           0x04  // A1 Stepping (25 x 27)\r
+#define V_PCH_LPC_RID_4                           0x05  // B0 Stepping (17 x 17)\r
+#define V_PCH_LPC_RID_5                           0x06  // B0 Stepping (25 x 27)\r
+#define V_PCH_LPC_RID_6                           0x07  // B1 Stepping (17 x 17)\r
+#define V_PCH_LPC_RID_7                           0x08  // B1 Stepping (25 x 27)\r
+#define V_PCH_LPC_RID_8                           0x09  // B2 Stepping (17 x 17)\r
+#define V_PCH_LPC_RID_9                           0x0A  // B2 Stepping (25 x 27)\r
+#define V_PCH_LPC_RID_A                           0x0B  // B3 Stepping (17 x 17)\r
+#define V_PCH_LPC_RID_B                           0x0C  // B3 Stepping (25 x 27)\r
+#define V_PCH_LPC_RID_C                           0x0D  // C0 Stepping (17 x 17)\r
+#define V_PCH_LPC_RID_D                           0x0E  // C0 Stepping (25 x 27)\r
+\r
+#define R_PCH_LPC_MLT                             0x0D  // Master Latency Timer\r
+#define B_PCH_LPC_MLT_MLC                         0xF8  // Master Latency Count\r
+\r
+#define R_PCH_LPC_HEADTYP                         0x0E  // Header Type\r
+#define B_PCH_LPC_HEADTYP_MFD                     BIT7  // Multi-function Device\r
+#define B_PCH_LPC_HEADTYP_HT                      0x7F  // Header Type\r
+\r
+#define R_PCH_LPC_SS                              0x2C  // Subsystem ID & Vendor ID\r
+#define B_PCH_LPC_SS_SSID                         0xFFFF0000 // Subsystem ID\r
+#define B_PCH_LPC_SS_SSVID                        0x0000FFFF // Subsystem Vendor ID\r
+\r
+#define R_PCH_LPC_CAP_LIST                        0x34  // Capability List\r
+#define B_PCH_LPC_CAP_LIST_CP                     0xFF  // Capability Pointer\r
+\r
+#define R_PCH_LPC_ACPI_BASE                       0x40 // ABASE, 16bit\r
+#define B_PCH_LPC_ACPI_BASE_BAR                   0x0000FF80 // Base Address, 128 Bytes\r
+#define B_PCH_LPC_ACPI_BASE_EN                    BIT1 // Enable Bit\r
+#define B_PCH_LPC_ACPI_BASE_MEMI                  BIT0 // Memory Space Indication\r
+\r
+#define R_PCH_LPC_PMC_BASE                        0x44  // PBASE, 32bit, 512 Bytes\r
+#define B_PCH_LPC_PMC_BASE_BAR                    0xFFFFFE00 // Base Address\r
+#define B_PCH_LPC_PMC_BASE_PREF                   BIT3  // Prefetchable\r
+#define B_PCH_LPC_PMC_BASE_ADDRNG                 BIT2  // Address Range\r
+#define B_PCH_LPC_PMC_BASE_EN                     BIT1  // Enable Bit\r
+#define B_PCH_LPC_PMC_BASE_MEMI                   BIT0  // Memory Space Indication\r
+\r
+#define R_PCH_LPC_GPIO_BASE                       0x48  // GBASE, 16bit\r
+#define B_PCH_LPC_GPIO_BASE_BAR                   0xFF00 // Base Address, 256 Bytes\r
+#define B_PCH_LPC_GPIO_BASE_EN                    BIT1  // Enable Bit\r
+#define B_PCH_LPC_GPIO_BASE_MEMI                  BIT0  // Memory Space Indication\r
+\r
+#define R_PCH_LPC_IO_BASE                         0x4C  // IOBASE, 32bit\r
+#define B_PCH_LPC_IO_BASE_BAR                     0xFFFFC000 // Base Address, 16 KiloBytes\r
+#define B_PCH_LPC_IO_BASE_PREF                    BIT3  // Prefetchable\r
+#define B_PCH_LPC_IO_BASE_ADDRNG                  BIT2  // Address Range\r
+#define B_PCH_LPC_IO_BASE_EN                      BIT1  // Enable Bit\r
+#define B_PCH_LPC_IO_BASE_MEMI                    BIT0  // Memory Space Indication\r
+\r
+#define R_PCH_LPC_ILB_BASE                        0x50  // IBASE, 32bit\r
+#define B_PCH_LPC_ILB_BASE_BAR                    0xFFFFFE00 // Base Address, 512 bytes\r
+#define B_PCH_LPC_ILB_BASE_PREF                   BIT3  // Prefetchable\r
+#define B_PCH_LPC_ILB_BASE_ADDRNG                 BIT2  // Address Range\r
+#define B_PCH_LPC_ILB_BASE_EN                     BIT1  // Enable Bit\r
+#define B_PCH_LPC_ILB_BASE_MEMI                   BIT0  // Memory Space Indication\r
+\r
+#define R_PCH_LPC_SPI_BASE                        0x54  // SBASE, 32bit\r
+#define B_PCH_LPC_SPI_BASE_BAR                    0xFFFFFE00 // Base Address, 512 bytes\r
+#define B_PCH_LPC_SPI_BASE_PREF                   BIT3  // Prefetchable\r
+#define B_PCH_LPC_SPI_BASE_ADDRNG                 BIT2  // Address Range\r
+#define B_PCH_LPC_SPI_BASE_EN                     BIT1  // Enable Bit\r
+#define B_PCH_LPC_SPI_BASE_MEMI                   BIT0  // Memory Space Indicator\r
+\r
+#define R_PCH_LPC_MPHY_BASE                       0x58 // MPBASE, 32bit\r
+#define B_PCH_LPC_MPHY_BASE_BAR                   0xFFF00000 // Base Address, 1 MegaByte\r
+#define B_PCH_LPC_MPHY_BASE_PREF                  BIT3  // Prefetchable\r
+#define B_PCH_LPC_MPHY_BASE_ADDRNG                BIT2  // Address Range\r
+#define B_PCH_LPC_MPHY_BASE_EN                    BIT1  // Enable Bit\r
+#define B_PCH_LPC_MPHY_BASE_MEMI                  BIT0  // Memory Space Indicator\r
+\r
+#define R_PCH_LPC_PUNIT_BASE                      0x5C  // PUBASE, 32bit\r
+#define B_PCH_LPC_PUNIT_BASE_BAR                  0xFFFFF800 // Base Address, 2K bytes\r
+#define B_PCH_LPC_PUNIT_BASE_PREF                 BIT3  // Prefetchable\r
+#define B_PCH_LPC_PUNIT_BASE_ADDRNG               BIT2  // Address Range\r
+#define B_PCH_LPC_PUNIT_BASE_EN                   BIT1  // Enable Bit\r
+#define B_PCH_LPC_PUNIT_BASE_MEMI                 BIT0  // Memory Space Indicator\r
+\r
+#define R_PCH_LPC_UART_CTRL                       0x80  // UART Control\r
+#define B_PCH_LPC_UART_CTRL_COM1_EN               BIT0  // COM1 Enable\r
+\r
+#define R_PCH_LPC_FWH_BIOS_DEC                    0xD8  // BIOS Decode Enable\r
+#define B_PCH_LPC_FWH_BIOS_DEC_EF8                BIT15 // F8-FF Enable\r
+#define B_PCH_LPC_FWH_BIOS_DEC_EF0                BIT14 // F0-F8 Enable\r
+#define B_PCH_LPC_FWH_BIOS_DEC_EE8                BIT13 // E8-EF Enable\r
+#define B_PCH_LPC_FWH_BIOS_DEC_EE0                BIT12 // E0-E8 Enable\r
+#define B_PCH_LPC_FWH_BIOS_DEC_ED8                BIT11 // D8-DF Enable\r
+#define B_PCH_LPC_FWH_BIOS_DEC_ED0                BIT10 // D0-D8 Enable\r
+#define B_PCH_LPC_FWH_BIOS_DEC_EC8                BIT9  // C8-CF Enable\r
+#define B_PCH_LPC_FWH_BIOS_DEC_EC0                BIT8  // C0-C8 Enable\r
+#define B_PCH_LPC_FWH_BIOS_DEC_LFE                BIT7  // Legacy F Segment Enable\r
+#define B_PCH_LPC_FWH_BIOS_DEC_LEE                BIT6  // Legacy E Segment Enable\r
+#define B_PCH_LPC_FWH_BIOS_DEC_E70                BIT3  // 70-7F Enable\r
+#define B_PCH_LPC_FWH_BIOS_DEC_E60                BIT2  // 60-6F Enable\r
+#define B_PCH_LPC_FWH_BIOS_DEC_E50                BIT1  // 50-5F Enable\r
+#define B_PCH_LPC_FWH_BIOS_DEC_E40                BIT0  // 40-4F Enable\r
+\r
+#define R_PCH_LPC_FDCAP                           0xE0  // Feature Detection Capability ID\r
+#define B_PCH_LPC_FDCAP_NEXT                      0xFF00 // Next Capability\r
+#define B_PCH_LPC_FDCAP_CAPID                     0x00FF // Capability ID\r
+\r
+#define R_PCH_LPC_FDLEN                           0xE2  // Feature Detection Capability Length\r
+#define B_PCH_LPC_FDLEN_CAPLEN                    0xFF  // Capability Length\r
+\r
+#define R_PCH_LPC_FDVER                           0xE3  // Feature Detection Capability Version\r
+#define B_PCH_LPC_FDVER_VSCID                     0xF0  // Vendor Specific Capability ID\r
+#define B_PCH_LPC_FDVER_CAPVER                    0x0F  // Capability Version\r
+\r
+#define R_PCH_LPC_FVECTIDX                        0xE4  // Feature Vector Index\r
+\r
+#define R_PCH_LPC_FVECTD                          0xE8  // Feature Vector Data\r
+\r
+#define R_PCH_LPC_RCBA                            0xF0  // RCBA, 32bit\r
+#define B_PCH_LPC_RCBA_BAR                        0xFFFFFC00 // Base Address, 1 KiloByte\r
+#define B_PCH_LPC_RCBA_EN                         BIT0  // Enable Bit\r
+\r
+#define R_PCH_LPC_ULT_OBS                         0xF4  // ULT Observability\r
+#define B_PCH_LPC_ULT_OBS_WNUM                    0x3FF000 // Reserved Wafer Number\r
+#define B_PCH_LPC_ULT_OBS_XLOC                    0xFC0 // Reserved X Loc\r
+#define B_PCH_LPC_ULT_OBS_YLOC                    0x3F  // Reserved Y Loc\r
+\r
+#define R_PCH_LPC_MAN_ID                          0xF8  // Manufacturer ID\r
+#define B_PCH_LPC_MAN_ID_DPID                     0xF000000 // Dot Portion of Process ID\r
+#define B_PCH_LPC_MAN_ID_MSID                     0xFF0000 // Manufacturing Stepping Identifier\r
+#define B_PCH_LPC_MAN_ID_MID                      0xFF00 // Manufacturing Identifier\r
+#define B_PCH_LPC_MAN_ID_PPID                     0xFF  // Process Portion of Process ID\r
+\r
+#define R_PCH_LPC_CGC                             0xFC  // Clock Gating Control\r
+#define B_PCH_LPC_CGC_SBLCG                       BIT9  // IOSF-SB Local Clock Gating Disable\r
+#define B_PCH_LPC_CGC_SBTCG                       BIT8  // IOSF-SB Trunk Clock Gating (Request) Disable\r
+#define B_PCH_LPC_CGC_PRILCG                      BIT1  // IOSF-PRI Local Clock Gating Disable\r
+#define B_PCH_LPC_CGC_PRITCG                      BIT0  // IOSF-PRI Trunk Clock Gating (Request) Disable\r
+\r
+//\r
+// iLB Memory Space Registers (IBASE)\r
+//\r
+#define R_PCH_ILB_ACPI_CNT                        0x00  // ACPI Control\r
+#define B_PCH_ILB_ACPI_CNT_SCI_IRQ_SEL            (BIT2 | BIT1 | BIT0) // SCI IRQ Select\r
+#define V_PCH_ILB_ACPI_CNT_SCI_IRQ_9              0     // IRQ9\r
+#define V_PCH_ILB_ACPI_CNT_SCI_IRQ_10             BIT0  // IRQ10\r
+#define V_PCH_ILB_ACPI_CNT_SCI_IRQ_11             BIT1  // IRQ11\r
+#define V_PCH_ILB_ACPI_CNT_SCI_IRQ_20             BIT2  // IRQ20 (Only if APIC enabled)\r
+#define V_PCH_ILB_ACPI_CNT_SCI_IRQ_21             (BIT2 | BIT0) // IRQ21 (Only if APIC enabled)\r
+#define V_PCH_ILB_ACPI_CNT_SCI_IRQ_22             (BIT2 | BIT1) // IRQ22 (Only if APIC enabled)\r
+#define V_PCH_ILB_ACPI_CNT_SCI_IRQ_23             (BIT2 | BIT1 | BIT0) // IRQ23 (Only if APIC enabled)\r
+\r
+#define R_PCH_ILB_MC                              0x04  // Miscellaneous Control\r
+#define B_PCH_ILB_MC_DRTC                         BIT3  // Disable RTC\r
+#define B_PCH_ILB_MC_D8259                        BIT2  // Disable 8259\r
+#define B_PCH_ILB_MC_D8254                        BIT1  // Disable 8254\r
+#define B_PCH_ILB_MC_AME                          BIT0  // Alternate Access Mode Enable\r
+\r
+#define R_PCH_ILB_PIRQA_ROUT                      0x08  // PIRQA Routing Control\r
+#define R_PCH_ILB_PIRQB_ROUT                      0x09  // PIRQB Routing Control\r
+#define R_PCH_ILB_PIRQC_ROUT                      0x0A  // PIRQC Routing Control\r
+#define R_PCH_ILB_PIRQD_ROUT                      0x0B  // PIRQD Routing Control\r
+#define R_PCH_ILB_PIRQE_ROUT                      0x0C  // PIRQE Routing Control\r
+#define R_PCH_ILB_PIRQF_ROUT                      0x0D  // PIRQF Routing Control\r
+#define R_PCH_ILB_PIRQG_ROUT                      0x0E  // PIRQG Routing Control\r
+#define R_PCH_ILB_PIRQH_ROUT                      0x0F  // PIRQH Routing Control\r
+//\r
+// Bit values are the same for R_PCH_ILB_PIRQA_ROUT to R_PCH_ILB_PIRQH_ROUT\r
+//\r
+#define B_PCH_ILB_PIRQX_ROUT_IRQEN                BIT7  // Interrupt Routing Enable\r
+#define B_PCH_ILB_PIRQX_ROUT                      0x0F  // IRQ Routing\r
+#define V_PCH_ILB_PIRQX_ROUT_IRQ_3                0x03  // Route to IRQ3\r
+#define V_PCH_ILB_PIRQX_ROUT_IRQ_4                0x04  // Route to IRQ4\r
+#define V_PCH_ILB_PIRQX_ROUT_IRQ_5                0x05  // Route to IRQ5\r
+#define V_PCH_ILB_PIRQX_ROUT_IRQ_6                0x06  // Route to IRQ6\r
+#define V_PCH_ILB_PIRQX_ROUT_IRQ_7                0x07  // Route to IRQ7\r
+#define V_PCH_ILB_PIRQX_ROUT_IRQ_9                0x09  // Route to IRQ9\r
+#define V_PCH_ILB_PIRQX_ROUT_IRQ_10               0x0A  // Route to IRQ10\r
+#define V_PCH_ILB_PIRQX_ROUT_IRQ_11               0x0B  // Route to IRQ11\r
+#define V_PCH_ILB_PIRQX_ROUT_IRQ_12               0x0C  // Route to IRQ12\r
+#define V_PCH_ILB_PIRQX_ROUT_IRQ_14               0x0E  // Route to IRQ14\r
+#define V_PCH_ILB_PIRQX_ROUT_IRQ_15               0x0F  // Route to IRQ15\r
+\r
+#define R_PCH_ILB_SERIRQ_CNT                      0x10  // Serial IRQ Control\r
+#define B_PCH_ILB_SERIRQ_CNT_SIRQMD               BIT7  // Mode\r
+\r
+#define R_PCH_ILB_ULKMC                           0x14  // USB Legacy Keyboard / Mouse Control\r
+#define B_PCH_ILB_ULKMC_TRAPBY64W                 BIT11 // SMI Caused by Port 64 Write\r
+#define B_PCH_ILB_ULKMC_TRAPBY64R                 BIT10 // SMI Caused by Port 64 Read\r
+#define B_PCH_ILB_ULKMC_TRAPBY60W                 BIT9  // SMI Caused by Port 60 Write\r
+#define B_PCH_ILB_ULKMC_TRAPBY60R                 BIT8  // SMI Caused by Port 60 Read\r
+#define B_PCH_ILB_ULKMC_64WEN                     BIT3  // SMI on Port 64 Writes Enable\r
+#define B_PCH_ILB_ULKMC_64REN                     BIT2  // SMI on Port 64 Reads Enable\r
+#define B_PCH_ILB_ULKMC_60WEN                     BIT1  // SMI on Port 60 Writes Enable\r
+#define B_PCH_ILB_ULKMC_60REN                     BIT0  // SMI on Port 60 Reads Enable\r
+\r
+#define R_PCH_ILB_FWH_BIOS_SEL                    0x18  // FWH ID Select\r
+#define B_PCH_ILB_FWH_BIOS_SEL_F8                 0xF0000000 // F8-FF ID Select\r
+#define B_PCH_ILB_FWH_BIOS_SEL_F0                 0x0F000000 // F0-F7 ID Select\r
+#define B_PCH_ILB_FWH_BIOS_SEL_E8                 0x00F00000 // E8-EF ID Select\r
+#define B_PCH_ILB_FWH_BIOS_SEL_E0                 0x000F0000 // E0-E7 ID Select\r
+#define B_PCH_ILB_FWH_BIOS_SEL_D8                 0x0000F000 // D8-DF ID Select\r
+#define B_PCH_ILB_FWH_BIOS_SEL_D0                 0x00000F00 // D0-D7 ID Select\r
+#define B_PCH_ILB_FWH_BIOS_SEL_C8                 0x000000F0 // C8-CF ID Select\r
+#define B_PCH_ILB_FWH_BIOS_SEL_C0                 0x0000000F // C0-C7 ID Select\r
+\r
+#define R_PCH_ILB_BIOS_CNTL                       0x1C  // BIOS Control\r
+#define S_PCH_ILB_BIOS_CNTL                       4\r
+#define B_PCH_ILB_BIOS_CNTL_PFE                   BIT8  // Prefetch Enable\r
+#define B_PCH_ILB_BIOS_CNTL_LE                    BIT1  // Lock Enable\r
+#define N_PCH_ILB_BIOS_CNTL_LE                    1\r
+#define B_PCH_ILB_BIOS_CNTL_WP                    BIT0  // Write Protect\r
+\r
+#define R_PCH_ILB_D0IR                            0x20  // Device 0 Interrupt Route\r
+#define R_PCH_ILB_D1IR                            0x22  // Device 1 Interrupt Route\r
+#define R_PCH_ILB_D2IR                            0x24  // Device 2 Interrupt Route\r
+#define R_PCH_ILB_D3IR                            0x26  // Device 3 Interrupt Route\r
+#define R_PCH_ILB_D4IR                            0x28  // Device 4 Interrupt Route\r
+#define R_PCH_ILB_D5IR                            0x2A  // Device 5 Interrupt Route\r
+#define R_PCH_ILB_D6IR                            0x2C  // Device 6 Interrupt Route\r
+#define R_PCH_ILB_D7IR                            0x2E  // Device 7 Interrupt Route\r
+#define R_PCH_ILB_D8IR                            0x30  // Device 8 Interrupt Route\r
+#define R_PCH_ILB_D9IR                            0x32  // Device 9 Interrupt Route\r
+#define R_PCH_ILB_D10IR                           0x34  // Device 10 Interrupt Route\r
+#define R_PCH_ILB_D11IR                           0x36  // Device 11 Interrupt Route\r
+#define R_PCH_ILB_D12IR                           0x38  // Device 12 Interrupt Route\r
+#define R_PCH_ILB_D13IR                           0x3A  // Device 13 Interrupt Route\r
+#define R_PCH_ILB_D14IR                           0x3C  // Device 14 Interrupt Route\r
+#define R_PCH_ILB_D15IR                           0x3E  // Device 15 Interrupt Route\r
+#define R_PCH_ILB_D16IR                           0x40  // Device 16 Interrupt Route\r
+#define R_PCH_ILB_D17IR                           0x42  // Device 17 Interrupt Route\r
+#define R_PCH_ILB_D18IR                           0x44  // Device 18 Interrupt Route\r
+#define R_PCH_ILB_D19IR                           0x46  // Device 19 Interrupt Route\r
+#define R_PCH_ILB_D20IR                           0x48  // Device 20 Interrupt Route\r
+#define R_PCH_ILB_D21IR                           0x4A  // Device 21 Interrupt Route\r
+#define R_PCH_ILB_D22IR                           0x4C  // Device 22 Interrupt Route\r
+#define R_PCH_ILB_D23IR                           0x4E  // Device 23 Interrupt Route\r
+#define R_PCH_ILB_D24IR                           0x50  // Device 24 Interrupt Route\r
+#define R_PCH_ILB_D25IR                           0x52  // Device 25 Interrupt Route\r
+#define R_PCH_ILB_D26IR                           0x54  // Device 26 Interrupt Route\r
+#define R_PCH_ILB_D27IR                           0x56  // Device 27 Interrupt Route\r
+#define R_PCH_ILB_D28IR                           0x58  // Device 28 Interrupt Route\r
+#define R_PCH_ILB_D29IR                           0x5A  // Device 29 Interrupt Route\r
+#define R_PCH_ILB_D30IR                           0x5C  // Device 30 Interrupt Route\r
+#define R_PCH_ILB_D31IR                           0x5E  // Device 31 Interrupt Route\r
+\r
+#define B_PCH_ILB_DXXIR_IDR_MASK                  (BIT14 | BIT13 | BIT12) // INTD Mask\r
+#define V_PCH_ILB_DXXIR_IDR_PIRQA                 0                       // INTD Mapping to IRQ A\r
+#define V_PCH_ILB_DXXIR_IDR_PIRQB                 BIT12                   // INTD Mapping to IRQ B\r
+#define V_PCH_ILB_DXXIR_IDR_PIRQC                 BIT13                   // INTD Mapping to IRQ C\r
+#define V_PCH_ILB_DXXIR_IDR_PIRQD                 (BIT13 | BIT12)         // INTD Mapping to IRQ D\r
+#define V_PCH_ILB_DXXIR_IDR_PIRQE                 BIT14                   // INTD Mapping to IRQ E\r
+#define V_PCH_ILB_DXXIR_IDR_PIRQF                 (BIT14 | BIT12)         // INTD Mapping to IRQ F\r
+#define V_PCH_ILB_DXXIR_IDR_PIRQG                 (BIT14 | BIT13)         // INTD Mapping to IRQ G\r
+#define V_PCH_ILB_DXXIR_IDR_PIRQH                 (BIT14 | BIT13 | BIT12) // INTD Mapping to IRQ H\r
+\r
+#define B_PCH_ILB_DXXIR_ICR_MASK                  (BIT10 | BIT9 | BIT8) // INTC Mask\r
+#define V_PCH_ILB_DXXIR_ICR_PIRQA                 0                     // INTC Mapping to IRQ A\r
+#define V_PCH_ILB_DXXIR_ICR_PIRQB                 BIT8                  // INTC Mapping to IRQ B\r
+#define V_PCH_ILB_DXXIR_ICR_PIRQC                 BIT9                  // INTC Mapping to IRQ C\r
+#define V_PCH_ILB_DXXIR_ICR_PIRQD                 (BIT9 | BIT8)         // INTC Mapping to IRQ D\r
+#define V_PCH_ILB_DXXIR_ICR_PIRQE                 BIT10                 // INTC Mapping to IRQ E\r
+#define V_PCH_ILB_DXXIR_ICR_PIRQF                 (BIT10 | BIT8)        // INTC Mapping to IRQ F\r
+#define V_PCH_ILB_DXXIR_ICR_PIRQG                 (BIT10 | BIT9)        // INTC Mapping to IRQ G\r
+#define V_PCH_ILB_DXXIR_ICR_PIRQH                 (BIT10 | BIT9 | BIT8) // INTC Mapping to IRQ H\r
+\r
+#define B_PCH_ILB_DXXIR_IBR_MASK                  (BIT6 | BIT5 | BIT4) // INTB Mask\r
+#define V_PCH_ILB_DXXIR_IBR_PIRQA                 0                    // INTB Mapping to IRQ A\r
+#define V_PCH_ILB_DXXIR_IBR_PIRQB                 BIT4                 // INTB Mapping to IRQ B\r
+#define V_PCH_ILB_DXXIR_IBR_PIRQC                 BIT5                 // INTB Mapping to IRQ C\r
+#define V_PCH_ILB_DXXIR_IBR_PIRQD                 (BIT5 | BIT4)        // INTB Mapping to IRQ D\r
+#define V_PCH_ILB_DXXIR_IBR_PIRQE                 BIT6                 // INTB Mapping to IRQ E\r
+#define V_PCH_ILB_DXXIR_IBR_PIRQF                 (BIT6 | BIT4)        // INTB Mapping to IRQ F\r
+#define V_PCH_ILB_DXXIR_IBR_PIRQG                 (BIT6 | BIT5)        // INTB Mapping to IRQ G\r
+#define V_PCH_ILB_DXXIR_IBR_PIRQH                 (BIT6 | BIT5 | BIT4) // INTB Mapping to IRQ H\r
+\r
+#define B_PCH_ILB_DXXIR_IAR_MASK                  (BIT2 | BIT1 | BIT0) // INTA Mask\r
+#define V_PCH_ILB_DXXIR_IAR_PIRQA                 0                    // INTA Mapping to IRQ A\r
+#define V_PCH_ILB_DXXIR_IAR_PIRQB                 BIT0                 // INTA Mapping to IRQ B\r
+#define V_PCH_ILB_DXXIR_IAR_PIRQC                 BIT1                 // INTA Mapping to IRQ C\r
+#define V_PCH_ILB_DXXIR_IAR_PIRQD                 (BIT1 | BIT0)        // INTA Mapping to IRQ D\r
+#define V_PCH_ILB_DXXIR_IAR_PIRQE                 BIT2                 // INTA Mapping to IRQ E\r
+#define V_PCH_ILB_DXXIR_IAR_PIRQF                 (BIT2 | BIT0)        // INTA Mapping to IRQ F\r
+#define V_PCH_ILB_DXXIR_IAR_PIRQG                 (BIT2 | BIT1)        // INTA Mapping to IRQ G\r
+#define V_PCH_ILB_DXXIR_IAR_PIRQH                 (BIT2 | BIT1 | BIT0) // INTA Mapping to IRQ H\r
+\r
+#define R_PCH_ILB_OIC                             0x60  // Other Interrupt Controller\r
+#define B_PCH_ILB_OIC_SIRQEN                      BIT12 // Serial IRQ Enable\r
+#define B_PCH_ILB_OIC_AEN                         BIT8  // APIC Enable\r
+\r
+#define R_PCH_ILB_RTC_CONF                        0x64  // RTC Control\r
+#define B_PCH_ILB_RTC_CONF_UCMOS_LOCK             BIT1  // Upper 128 Byte Lock\r
+#define B_PCH_ILB_RTC_CONF_LCMOS_LOCK             BIT0  // Lower 128 Byte Lock\r
+\r
+#define R_PCH_ILB_RTM                             0x68  // RTC Test Mode\r
+#define B_PCH_ILB_RTM_RTM1                        (BIT2 | BIT1 | BIT0)\r
+\r
+#define R_PCH_ILB_BCS                             0x6C  // BIOS Control Status\r
+#define B_PCH_ILB_BCS_SMIWPEN                     BIT1  // SMI WPD Enable\r
+#define B_PCH_ILB_BCS_SMIWPST                     BIT0  // SMI WPD Status\r
+\r
+#define R_PCH_ILB_LE                              0x70  // LE\r
+#define B_PCH_ILB_LE_IRQ12C                       BIT1  // IRQ12 Cause\r
+#define B_PCH_ILB_LE_IRQ1C                        BIT0  // IRQ1 Cause\r
+\r
+#define R_PCH_ILB_RTCC                            0x74  // RTC HIP Configuration\r
+#define B_PCH_ILB_RTCC_RTCB4                      BIT6  // RTC Bias Resistor 4, Adds 480 Kohm\r
+#define B_PCH_ILB_RTCC_RTCB3                      BIT5  // RTC Bias Resistor 3, Adds 240 Kohm\r
+#define B_PCH_ILB_RTCC_RTCB2                      BIT4  // RTC Bias Resistor 2, Adds 120 Kohm\r
+#define B_PCH_ILB_RTCC_RTCB1                      BIT3  // RTC Bias Resistor 1, Adds 60 Kohm\r
+#define B_PCH_ILB_RTCC_RTCB0                      BIT2  // RTC Bias Resistor 0, Adds 30 Kohm\r
+#define B_PCH_ILB_RTCC_DSWEN                      BIT1  // Deep Sleep Well Enable\r
+#define B_PCH_ILB_RTCC_FEN                        BIT0  // Enable the Fast Oscillator Bypass Mode\r
+\r
+#define R_PCH_ILB_DEF0                            0x78  // Defeature Register 0\r
+#define B_PCH_ILB_DEF0_SHRTSYNC                   BIT22 // Short Sync Abort Defeature\r
+#define B_PCH_ILB_DEF0_SDD                        BIT21 // Sub Decode Disable\r
+\r
+#define R_PCH_ILB_DEF1                            0x7C  // Defeature Register 1\r
+#define B_PCH_ILB_DEF1_TPMPF                      BIT10 // usb2leg_chknbit_TPM_PF\r
+#define B_PCH_ILB_DEF1_HPETDEF                    BIT8  // usb2leg_chknbit_hpet\r
+#define B_PCH_ILB_DEF1_ECWS                       BIT6  // 8254 Early CW Select\r
+#define B_PCH_ILB_DEF1_FOF                        BIT5  // 8254 Freeze on first on 1st rd wr11\r
+#define B_PCH_ILB_DEF1_FOAR                       BIT4  // 8254 Freeze_On_AnyRead\r
+#define B_PCH_ILB_DEF1_LMOO                       BIT3  // 8259 L2L0_Match_On_OCW2\r
+#define B_PCH_ILB_DEF1_DFP                        BIT2  // 8259 Disable_Freeze_Priority\r
+#define B_PCH_ILB_DEF1_EETI                       BIT1  // 8259 Extend_EdgeTrig_IRQ\r
+#define B_PCH_ILB_DEF1_DSAEOI                     BIT0  // 8259 Disable_Slave_AEOI\r
+\r
+#define R_PCH_ILB_GNMI                            0x80  // NMI Register\r
+#define S_PCH_ILB_GNMI                            4\r
+#define B_PCH_ILB_GNMI_NMI2SMIEN                  BIT6  // NMI to SMI Enable\r
+#define N_PCH_ILB_GNMI_NMI2SMIEN                  6\r
+#define B_PCH_ILB_GNMI_NMI2SMIST                  BIT5  // NMI to SMI Status\r
+#define N_PCH_ILB_GNMI_NMI2SMIST                  5\r
+#define B_PCH_ILB_GNMI_NMIN                       BIT4  // NMI NOW\r
+#define B_PCH_ILB_GNMI_NMINS                      BIT3  // NMI NOW Status\r
+#define B_PCH_ILB_GNMI_GNMIED                     BIT2  // GPIO NMI Edge Detection\r
+#define B_PCH_ILB_GNMI_GNMIE                      BIT1  // GPIO NMI Enable\r
+#define B_PCH_ILB_GNMI_GNMIS                      BIT0  // GPIO NMI Status\r
+\r
+#define R_PCH_ILB_LPCC                            0x84  // LPC Control\r
+#define B_PCH_ILB_LPCC_LPCCLK_SLC                 BIT8  // iLPCCLK Mux Select\r
+#define B_PCH_ILB_LPCC_LPCCLK_FORCE_OFF           BIT3\r
+#define B_PCH_ILB_LPCC_CLKRUN_EN                  BIT2  // LPC CLKRUN Protocol Enable\r
+#define B_PCH_ILB_LPCC_LPCCLK1EN                  BIT1  // Clock 1 Enable\r
+#define B_PCH_ILB_LPCC_LPCCLK0EN                  BIT0  // Clock 0 Enable\r
+\r
+#define R_PCH_ILB_IRQE                            0x88  // IRQ Enable Control\r
+#define B_PCH_ILB_IRQE_IRQ4TO7EN                  (BIT7 | BIT6 | BIT5 | BIT4) // IRQ4 - IRQ7 Enable\r
+#define B_PCH_ILB_IRQE_UARTIRQEN_IRQ3             BIT3  // UART IRQ3 Enable\r
+\r
+//\r
+// ACPI and Legacy I/O Registers (ABASE)\r
+//\r
+#define R_PCH_ACPI_PM1_STS                        0x00  // Power Management 1 Status\r
+#define S_PCH_ACPI_PM1_STS                        2\r
+#define B_PCH_ACPI_PM1_STS_WAK                    BIT15 // Wake Status\r
+#define B_PCH_ACPI_PM1_STS_WAK_PCIE0              BIT14 // PCI Express 0 Wake Status\r
+#define B_PCH_ACPI_PM1_STS_USB_CLKLESS            BIT13 // USB Clockless Status\r
+#define B_PCH_ACPI_PM1_STS_PRBTNOR                BIT11 // Power Button Override Status\r
+#define B_PCH_ACPI_PM1_STS_RTC                    BIT10 // RTC Status\r
+#define B_PCH_ACPI_PM1_STS_PWRBTN                 BIT8  // Power Button Status\r
+#define B_PCH_ACPI_PM1_STS_GBL                    BIT5  // Global Status\r
+#define B_PCH_ACPI_PM1_STS_WAK_PCIE3              BIT4  // PCI Express 3 Wake Status\r
+#define B_PCH_ACPI_PM1_STS_WAK_PCIE2              BIT3  // PCI Express 2 Wake Status\r
+#define B_PCH_ACPI_PM1_STS_WAK_PCIE1              BIT2  // PCI Express 1 Wake Status\r
+#define B_PCH_ACPI_PM1_STS_TMROF                  BIT0  // Timer Overflow Status\r
+#define N_PCH_ACPI_PM1_STS_WAK                    15\r
+#define N_PCH_ACPI_PM1_STS_PRBTNOR                11\r
+#define N_PCH_ACPI_PM1_STS_RTC                    10\r
+#define N_PCH_ACPI_PM1_STS_PWRBTN                 8\r
+#define N_PCH_ACPI_PM1_STS_GBL                    5\r
+#define N_PCH_ACPI_PM1_STS_TMROF                  0\r
+\r
+#define R_PCH_ACPI_PM1_EN                         0x02  // Power Management 1 Enables\r
+#define S_PCH_ACPI_PM1_EN                         2\r
+#define B_PCH_ACPI_PM1_WAK_DIS_PCIE0              BIT14 // PCI Express 0 Disable\r
+#define B_PCH_ACPI_PM1_EN_USB_CLKLESS             BIT13 // USB Clockless Enable Bit\r
+#define B_PCH_ACPI_PM1_EN_RTC                     BIT10 // RTC Alarm Enable Bit\r
+#define B_PCH_ACPI_PM1_EN_PWRBTN                  BIT8  // Power Button Enable Bit\r
+#define B_PCH_ACPI_PM1_EN_GBL                     BIT5  // Global Enable Bit\r
+#define B_PCH_ACPI_PM1_WAK_DIS_PCIE3              BIT4  // PCI Express 3 Disable\r
+#define B_PCH_ACPI_PM1_WAK_DIS_PCIE2              BIT3  // PCI Express 2 Disable\r
+#define B_PCH_ACPI_PM1_WAK_DIS_PCIE1              BIT2  // PCI Express 1 Disable\r
+#define B_PCH_ACPI_PM1_EN_TMROF                   BIT0  // Timer Overflow Interrupt Enable Bit\r
+#define N_PCH_ACPI_PM1_EN_RTC                     10\r
+#define N_PCH_ACPI_PM1_EN_PWRBTN                  8\r
+#define N_PCH_ACPI_PM1_EN_GBL                     5\r
+#define N_PCH_ACPI_PM1_EN_TMROF                   0\r
+\r
+#define R_PCH_ACPI_PM1_CNT                        0x04  // Power Management 1 Control\r
+#define S_PCH_ACPI_PM1_CNT                        4\r
+#define B_PCH_ACPI_PM1_CNT_SLP_EN                 BIT13 // Sleep enable\r
+#define B_PCH_ACPI_PM1_CNT_SLP_TYP                (BIT12 | BIT11 | BIT10) // Sleep Type\r
+#define V_PCH_ACPI_PM1_CNT_S0                     0x00000000 // ON (S0)\r
+#define V_PCH_ACPI_PM1_CNT_S1                     0x00000400 // Puts CPU in S1 state (S1)\r
+#define V_PCH_ACPI_PM1_CNT_S3                     0x00001400 // Suspend-to-RAM (S3)\r
+#define V_PCH_ACPI_PM1_CNT_S4                     0x00001800 // Suspend-to-Disk (S4)\r
+#define V_PCH_ACPI_PM1_CNT_S5                     0x00001C00 // Soft Off (S5)\r
+#define B_PCH_ACPI_PM1_CNT_GBL_RLS                BIT2\r
+#define B_PCH_ACPI_PM1_CNT_BM_RLD                 BIT1  // Treated as Scratchpad Bit\r
+#define B_PCH_ACPI_PM1_CNT_SCI_EN                 BIT0  // SCI Enable\r
+\r
+#define R_PCH_ACPI_PM1_TMR                        0x08  // Power Management 1 Timer\r
+#define B_PCH_ACPI_PM1_TMR_VAL                    0xFFFFFF // The timer value mask\r
+#define V_PCH_ACPI_PM1_TMR_MAX_VAL                0x1000000 // The timer is 24 bit overflow\r
+#define V_PCH_ACPI_PM1_TMR_FREQUENCY              3579545 // Timer Frequency\r
+#define V_PCH_ACPI_PM1_TMR_NUM_BITS               24    // Programmed to 24 not 32\r
+#define V_PCH_ACPI_PM1_TMR_MAX_BITS               32\r
+\r
+#define R_PCH_ACPI_GPE0a_STS                      0x20  // General Purpose Event 0a Status\r
+#define S_PCH_ACPI_GPE0a_STS                      4\r
+#define B_PCH_ACPI_GPE0a_STS_CORE_GPIO            0xFF000000 // CORE GPIO Status\r
+#define B_PCH_ACPI_GPE0a_STS_SUS_GPIO             0x00FF0000 // SUS GPIO Status\r
+#define B_PCH_ACPI_GPE0a_STS_PME_B0               BIT13 // Power Management Event Bus 0 Status\r
+#define B_PCH_ACPI_GPE0a_STS_BATLOW               BIT10 // Battery Low Status\r
+#define B_PCH_ACPI_GPE0a_STS_PCI_EXP              BIT9  // PCI Express Status\r
+#define B_PCH_ACPI_GPE0a_STS_GUNIT_SCI            BIT5  // GUNIT SCI Status\r
+#define B_PCH_ACPI_GPE0a_STS_PUNIT_SCI            BIT4  // PUNIT SCI Status\r
+#define B_PCH_ACPI_GPE0a_STS_SWGPE                BIT2  // Software GPE Status\r
+#define B_PCH_ACPI_GPE0a_STS_HOT_PLUG             BIT1  // Hot Plug Status\r
+#define N_PCH_ACPI_GPE0a_STS_PME_B0               13\r
+#define N_PCH_ACPI_GPE0a_STS_BATLOW               10\r
+#define N_PCH_ACPI_GPE0a_STS_PCI_EXP              9\r
+#define N_PCH_ACPI_GPE0a_STS_GUNIT_SCI            5\r
+#define N_PCH_ACPI_GPE0a_STS_PUNIT_SCI            4\r
+#define N_PCH_ACPI_GPE0a_STS_SWGPE                2\r
+#define N_PCH_ACPI_GPE0a_STS_HOT_PLUG             1\r
+\r
+#define R_PCH_ACPI_GPE0a_EN                       0x28  // General Purpose Event 0a Enables\r
+#define S_PCH_ACPI_GPE0a_EN                       4\r
+#define B_PCH_ACPI_GPE0a_EN_CORE_GPIO             0xFF000000 // CORE GPIO Enable\r
+#define B_PCH_ACPI_GPE0a_EN_SUS_GPIO              0x00FF0000 // SUS GPIO Enable\r
+#define B_PCH_ACPI_GPE0a_EN_PME_B0                BIT13 // Power Management Event Bus 0 Enable\r
+#define B_PCH_ACPI_GPE0a_EN_BATLOW                BIT10 // Battery Low Enable\r
+#define B_PCH_ACPI_GPE0a_EN_PCI_EXP               BIT9  // PCI Express Enable\r
+#define B_PCH_ACPI_GPE0a_EN_SWGPE                 BIT2  // Software GPE Enable\r
+#define B_PCH_ACPI_GPE0a_EN_HOT_PLUG              BIT1  // Hot Plug Enable\r
+#define N_PCH_ACPI_GPE0a_EN_PME_B0                13\r
+#define N_PCH_ACPI_GPE0a_EN_BATLOW                10\r
+#define N_PCH_ACPI_GPE0a_EN_PCI_EXP               9\r
+#define N_PCH_ACPI_GPE0a_EN_SWGPE                 2\r
+#define N_PCH_ACPI_GPE0a_EN_HOT_PLUG              1\r
+\r
+#define R_PCH_SMI_EN                              0x30  // SMI Control and Enable\r
+#define S_PCH_SMI_EN                              4\r
+#define B_PCH_SMI_EN_LEGACY_USB3                  BIT31 // Legacy USB 3 Enable\r
+#define B_PCH_SMI_EN_INTEL_USB2                   BIT18 // Intel USB 2 Enable\r
+#define B_PCH_SMI_EN_LEGACY_USB2                  BIT17 // Legacy USB 2 Enable\r
+#define B_PCH_SMI_EN_PERIODIC                     BIT14 // Periodic Enable\r
+#define B_PCH_SMI_EN_TCO                          BIT13 // TCO Enable\r
+#define B_PCH_SMI_EN_BIOS_RLS                     BIT7  // BIOS RLS\r
+#define B_PCH_SMI_EN_SWSMI_TMR                    BIT6  // Software SMI Timer Enable\r
+#define B_PCH_SMI_EN_APMC                         BIT5  // APMC Enable\r
+#define B_PCH_SMI_EN_ON_SLP_EN                    BIT4  // SMI On Sleep Enable\r
+#define B_PCH_SMI_EN_BIOS                         BIT2  // BIOS Enable\r
+#define B_PCH_SMI_EN_EOS                          BIT1  // End of SMI\r
+#define B_PCH_SMI_EN_GBL_SMI                      BIT0  // Global SMI Enable\r
+#define N_PCH_SMI_EN_LEGACY_USB3                  31\r
+#define N_PCH_SMI_EN_GPIO_UNLOCK                  27\r
+#define N_PCH_SMI_EN_INTEL_USB2                   18\r
+#define N_PCH_SMI_EN_LEGACY_USB2                  17\r
+#define N_PCH_SMI_EN_PERIODIC                     14\r
+#define N_PCH_SMI_EN_TCO                          13\r
+#define N_PCH_SMI_EN_BIOS_RLS                     7\r
+#define N_PCH_SMI_EN_SWSMI_TMR                    6\r
+#define N_PCH_SMI_EN_APMC                         5\r
+#define N_PCH_SMI_EN_ON_SLP_EN                    4\r
+#define N_PCH_SMI_EN_BIOS                         2\r
+#define N_PCH_SMI_EN_EOS                          1\r
+#define N_PCH_SMI_EN_GBL_SMI                      0\r
+\r
+#define R_PCH_SMI_STS                             0x34  // SMI Status Register\r
+#define S_PCH_SMI_STS                             4\r
+#define B_PCH_SMI_STS_LEGACY_USB3                 BIT31 // Legacy USB 3 Status\r
+#define B_PCH_SMI_STS_GUNIT_SMI                   BIT29 // GUNIT SMI Status\r
+#define B_PCH_SMI_STS_PUNIT_SMI                   BIT28 // PUNIT SMI Status\r
+#define B_PCH_SMI_STS_SPI                         BIT26 // SPI SMI Status\r
+#define B_PCH_SMI_STS_PCI_EXP                     BIT20 // PCI Express SMI Status\r
+#define B_PCH_SMI_STS_INTEL_USB2                  BIT18 // Intel USB 2 Status\r
+#define B_PCH_SMI_STS_LEGACY_USB2                 BIT17 // Legacy USB 2 Status\r
+#define N_PCH_SMI_STS_TCO                         13\r
+#define B_PCH_SMI_STS_SMBUS                       BIT16 // SMBUS SMI Status\r
+#define B_PCH_SMI_STS_ILB                         BIT15 // ILB SMI Status\r
+#define B_PCH_SMI_STS_PERIODIC                    BIT14 // Periodic Status\r
+#define B_PCH_SMI_STS_TCO                         BIT13 // TCO Status\r
+#define B_PCH_SMI_STS_GPE0                        BIT9  // GPE0 Status\r
+#define B_PCH_SMI_STS_PM1_STS_REG                 BIT8  // PM1 Status Register\r
+#define B_PCH_SMI_STS_SWSMI_TMR                   BIT6  // Software SMI Timer Status\r
+#define B_PCH_SMI_STS_APM                         BIT5  // APM Status\r
+#define B_PCH_SMI_STS_ON_SLP_EN                   BIT4  // SMI On Sleep Enable Status\r
+#define B_PCH_SMI_STS_BIOS                        BIT2  // BIOS Status\r
+#define N_PCH_SMI_STS_LEGACY_USB3                 31\r
+#define N_PCH_SMI_STS_SPI                         26\r
+#define N_PCH_SMI_STS_PCI_EXP                     20\r
+#define N_PCH_SMI_STS_INTEL_USB2                  18\r
+#define N_PCH_SMI_STS_LEGACY_USB2                 17\r
+#define N_PCH_SMI_STS_SMBUS                       16\r
+#define N_PCH_SMI_STS_ILB                         15\r
+#define N_PCH_SMI_STS_PERIODIC                    14\r
+#define N_PCH_SMI_STS_TCO                         13\r
+#define N_PCH_SMI_STS_GPE0                        9\r
+#define N_PCH_SMI_STS_PM1_STS_REG                 8\r
+#define N_PCH_SMI_STS_SWSMI_TMR                   6\r
+#define N_PCH_SMI_STS_APM                         5\r
+#define N_PCH_SMI_STS_ON_SLP_EN                   4\r
+#define N_PCH_SMI_STS_BIOS                        2\r
+\r
+#define R_PCH_ALT_GP_SMI_EN                       0x38  // Alternate GPI SMI Enable\r
+#define S_PCH_ALT_GP_SMI_EN                       2\r
+#define B_PCH_ALT_GP_SMI_EN_CORE_GPIO             0xFF00 // SUS GPIO SMI Enable\r
+#define B_PCH_ALT_GP_SMI_EN_SUS_GPIO              0x00FF // CORE GPIO SMI Enable\r
+\r
+#define R_PCH_ALT_GP_SMI_STS                      0x3A  // Alternate GPI SMI Status\r
+#define S_PCH_ALT_GP_SMI_STS                      2\r
+#define B_PCH_ALT_GP_SMI_STS_CORE_GPIO            0xFF00 // SUS GPIO SMI Status\r
+#define B_PCH_ALT_GP_SMI_STS_SUS_GPIO             0x00FF // CORE GPIO SMI Status\r
+\r
+#define R_PCH_UPRWC                               0x3C  // USB Per-Port Registers Write Control\r
+#define S_PCH_UPRWC                               2\r
+#define B_PCH_UPRWC_WR_EN_SMI_STS                 BIT8 // Write Enable Status\r
+#define B_PCH_UPRWC_WR_EN                         BIT1 // USB Per-Port Registers Write Enable\r
+#define B_PCH_UPRWC_WR_EN_SMI_EN                  BIT0 // Write Enable SMI Enable\r
+\r
+#define R_PCH_ACPI_GPE_CNTL                       0x40  // General Purpose Event Control\r
+#define B_PCH_ACPI_GPE_CNTL_SWGPE_CTRL            BIT17 // Software GPE Control\r
+#define B_PCH_ACPI_GPE_CNTL_PCIE3_SCI_EN          BIT3\r
+#define B_PCH_ACPI_GPE_CNTL_PCIE2_SCI_EN          BIT2\r
+#define B_PCH_ACPI_GPE_CNTL_PCIE1_SCI_EN          BIT1\r
+#define B_PCH_ACPI_GPE_CNTL_PCIE0_SCI_EN          BIT0\r
+\r
+#define R_PCH_ACPI_PM2_CNT                        0x50  // PM2a Control Block\r
+#define B_PCH_ACPI_PM2_CNT_ARB_DIS                BIT0  // Scratchpad Bit\r
+\r
+#define R_PCH_TCO_RLD                             0x60  // TCO Reload\r
+#define B_PCH_TCO_RLD_VAL                         0x3FF // TCO Timer Count Value\r
+\r
+#define R_PCH_TCO_STS                             0x64  // TCO Timer Status\r
+#define S_PCH_TCO_STS                             4\r
+#define B_PCH_TCO_STS_SECOND_TO                   BIT17 // Second Timeout Status\r
+#define B_PCH_TCO_STS_TIMEOUT                     BIT3  // Timeout\r
+#define N_PCH_TCO_STS_TIMEOUT                     3\r
+\r
+#define R_PCH_TCO_CNT                             0x68  // TCO Control\r
+#define S_PCH_TCO_CNT                             2\r
+#define B_PCH_TCO_CNT_OS_POLICY                   (BIT21 | BIT20) // OS Policy\r
+#define B_PCH_TCO_CNT_LOCK                        BIT12 // TCO Enable Lock\r
+#define B_PCH_TCO_CNT_TMR_HLT                     BIT11 // TCO Timer Halt\r
+\r
+#define R_PCH_TCO_TMR                             0x70  // TCO Timer\r
+#define B_PCH_TCO_TMR_TCO_TRLD                    0x3FF0000\r
+\r
+//\r
+// PMC Memory Space Registers (PBASE)\r
+//\r
+#define R_PCH_PMC_PRSTS                           0x00  // Power and Reset Status\r
+#define B_PCH_PMC_PRSTS_PRODID                    0xFF000000 // Power Management Controller Product ID\r
+#define B_PCH_PMC_PRSTS_REVID                     0x00FF0000 // Power Management Controller Revision ID\r
+#define B_PCH_PMC_PRSTS_PM_WD_TMR                 BIT15 // PMC Watchdog Timer Status\r
+#define B_PCH_PMC_PRSTS_CODE_COPIED_STS           BIT11 // Patch Copied Over Status\r
+#define B_PCH_PMC_PRSTS_CODE_LOAD_TO              BIT9  // Patch Load Timeout Status\r
+#define B_PCH_PMC_PRSTS_OP_STS                    BIT8  // PMC Operational Status\r
+#define B_PCH_PMC_PRSTS_SEC_GBLRST_STS            BIT7  // SEC Global Reset Status\r
+#define B_PCH_PMC_PRSTS_SEC_WD_TMR_STS            BIT6  // SEC Watchdog Timer Status\r
+#define B_PCH_PMC_PRSTS_WOL_OVR_WK_STS            BIT5  // Wake On LAN Override Wake Status\r
+#define B_PCH_PMC_PRSTS_HOST_WAKE_STS             BIT4  // PMC Host Wake Status\r
+\r
+#define R_PCH_PMC_PM_CFG                          0x08  // Power Management Configuration\r
+#define B_PCH_PMC_PM_CFG_SPS                      BIT5  // Shutdown Policy Select\r
+#define B_PCH_PMC_PM_CFG_NO_REBOOT                BIT4  // No Reboot Strap\r
+#define B_PCH_PMC_PM_CFG_SX_ENT_TO_EN             BIT3  // S1 / 3 / 4 / 5 Entry Timeout Enable\r
+#define B_PCH_PMC_PM_CFG_TIMING_T581              (BIT1 | BIT0) // Timing t581\r
+\r
+#define R_PCH_PMC_PM_STS                          0x0C  // Power Management Status\r
+#define B_PCH_PMC_PM_STS_PMC_MSG_FULL             BIT24 // PMC Message Full Status\r
+#define B_PCH_PMC_PM_STS_PMC_MSG_4_FULL           BIT23 // PMC 4 Message Full Status\r
+#define B_PCH_PMC_PM_STS_PMC_MSG_3_FULL           BIT22 // PMC 3 Message Full Status\r
+#define B_PCH_PMC_PM_STS_PMC_MSG_2_FULL           BIT21 // PMC 2 Message Full Status\r
+#define B_PCH_PMC_PM_STS_PMC_MSG_1_FULL           BIT20 // PMC 1 Message Full Status\r
+#define B_PCH_PMC_PM_STS_CODE_REQ                 BIT8  // Patch Request Status\r
+#define B_PCH_PMC_PM_STS_HPR_ENT_TO               BIT2  // Host partition Reset Entry Timeout Status\r
+#define B_PCH_PMC_PM_STS_SX_ENT_TO                BIT1  // S3 / 4 / 5 Entry Timeout Status\r
+\r
+#define R_PCH_PMC_MTPMC                           0x10  // Message to PMC\r
+\r
+#define R_PCH_PMC_GEN_PMCON_1                     0x20  // General PM Configuration 1\r
+#define B_PCH_PMC_GEN_PMCON_UART_EN               BIT24 // UART Debug Port Enable\r
+#define B_PCH_PMC_GEN_PMCON_DRAM_INIT             BIT23 // DRAM Initialization Scratchpad Bit\r
+#define B_PCH_PMC_GEN_PMCON_MEM_SR                BIT21 // Memory Placed in Self-Refresh\r
+#define B_PCH_PMC_GEN_PMCON_SRS                   BIT20 // System Reset Status\r
+#define B_PCH_PMC_GEN_PMCON_CTS                   BIT19 // CPU Thermal Trip Status\r
+#define B_PCH_PMC_GEN_PMCON_MIN_SLP_S4            BIT18 // Minimum SLP_S4# Assertion Width Violation Status\r
+#define B_PCH_PMC_GEN_PMCON_PWROK_FLR             BIT16 // PWROK Failure\r
+#define B_PCH_PMC_GEN_PMCON_PME_B0_S5_DIS         BIT15 // PME B0 S5 Disable\r
+#define B_PCH_PMC_GEN_PMCON_SUS_PWR_FLR           BIT14 // SUS Well Power Failure\r
+#define B_PCH_PMC_GEN_PMCON_WOL_ENABLE_OVERRIDE   BIT13 // WOL Enable Override\r
+#define B_PCH_PMC_GEN_PMCON_DISABLE_SX_STRETCH    BIT12 // Disable SLP_X Scretching After SUS Well Power Up\r
+#define B_PCH_PMC_GEN_PMCON_SLP_S3_MAW            (BIT11 | BIT10) // SLP_S3# Minimum Assertion Width\r
+#define V_PCH_PMC_GEN_PMCON_SLP_S3_MAW_60US       0x000 // 60 micro seconds\r
+#define V_PCH_PMC_GEN_PMCON_SLP_S3_MAW_1MS        0x400 // 1 milli second\r
+#define V_PCH_PMC_GEN_PMCON_SLP_S3_MAW_50MS       0x800 // 50 milli seconds\r
+#define V_PCH_PMC_GEN_PMCON_SLP_S3_MAW_2S         0xC00 // 2 seconds\r
+#define B_PCH_PMC_GEN_PMCON_GEN_RST_STS           BIT9  // General Reset Status\r
+#define B_PCH_PMC_GEN_PMCON_RTC_RESERVED          BIT8  // RTC Reserved\r
+#define B_PCH_PMC_GEN_PMCON_SWSMI_RTSL            (BIT7 | BIT6)  // SWSMI Rate Select\r
+#define V_PCH_PMC_GEN_PMCON_SWSMI_RTSL_64MS       0xC0  // 64ms +/- 4ms\r
+#define V_PCH_PMC_GEN_PMCON_SWSMI_RTSL_32MS       0x80  // 32ms +/- 4ms\r
+#define V_PCH_PMC_GEN_PMCON_SWSMI_RTSL_16MS       0x40  // 16ms +/- 4ms\r
+#define V_PCH_PMC_GEN_PMCON_SWSMI_RTSL_1_5MS      0x00  // 1.5ms +/- 0.6ms\r
+#define B_PCH_PMC_GEN_PMCON_SLP_S4_MAW            (BIT5 | BIT4) // SLP_S4# Minimum Assertion Width\r
+#define V_PCH_PMC_GEN_PMCON_SLP_S4_MAW_1S         0x30  // 1 second\r
+#define V_PCH_PMC_GEN_PMCON_SLP_S4_MAW_2S         0x20  // 2 seconds\r
+#define V_PCH_PMC_GEN_PMCON_SLP_S4_MAW_3S         0x10  // 3 seconds\r
+#define V_PCH_PMC_GEN_PMCON_SLP_S4_MAW_4S         0x00  // 4 seconds\r
+#define B_PCH_PMC_GEN_PMCON_SLP_S4_ASE            BIT3  // SLP_S4# Assertion Scretch Enable\r
+#define B_PCH_PMC_GEN_PMCON_RTC_PWR_STS           BIT2  // RTC Power Status\r
+#define B_PCH_PMC_GEN_PMCON_AFTERG3_EN            BIT0  // After G3 State Enable\r
+\r
+#define R_PCH_PMC_GEN_PMCON_2                     0x24  // General PM Configuration 2\r
+#define B_PCH_PMC_GEN_PMCON_LOCK_S4_STRET_LD      BIT18 // SLP_S3 / SLP_S4 Stretching Policy Lock-Down\r
+#define B_PCH_PMC_GEN_PMCON_BIOS_PCI_EXP_EN       BIT10 // BIOS PCI Express Enable\r
+#define B_PCH_PMC_GEN_PMCON_PWRBTN_LVL            BIT9  // Power Button Level\r
+#define B_PCH_PMC_GEN_PMCON_SMI_LOCK              BIT4  // SMI Lock\r
+#define B_PCH_PMC_GEN_PMCON_PER_SMI_SEL           (BIT1 | BIT0) // Period SMI Select\r
+#define V_PCH_PMC_GEN_PMCON_PER_SMI_64S           0x0000 // 64 seconds\r
+#define V_PCH_PMC_GEN_PMCON_PER_SMI_32S           0x0001 // 32 seconds\r
+#define V_PCH_PMC_GEN_PMCON_PER_SMI_16S           0x0002 // 16 seconds\r
+#define V_PCH_PMC_GEN_PMCON_PER_SMI_8S            0x0003 //  8 seconds\r
+\r
+#define R_PCH_PMC_MFPMC                           0x28  // Message from PMC\r
+\r
+#define R_PCH_PMC_SEC_STS                         0x2C  // SEC Status\r
+#define B_PCH_PMC_SEC_STS_SEC                     (BIT3 | BIT2 | BIT1 | BIT0) // SEC Exclusion Cause\r
+\r
+#define R_PCH_PMC_CRID                            0x30  // Configured Revision ID\r
+#define B_PCH_PMC_CRID_RID_SEL                    (BIT1 | BIT0) // Revision ID Select\r
+\r
+#define R_PCH_PMC_FUNC_DIS                        0x34  // Function Disable Register\r
+#define B_PCH_PMC_FUNC_DIS_LPSS2_FUNC7            BIT31 // LPSS2 I2C #7\r
+#define B_PCH_PMC_FUNC_DIS_LPSS2_FUNC6            BIT30 // LPSS2 I2C #6\r
+#define B_PCH_PMC_FUNC_DIS_LPSS2_FUNC5            BIT29 // LPSS2 I2C #5\r
+#define B_PCH_PMC_FUNC_DIS_LPSS2_FUNC4            BIT28 // LPSS2 I2C #4\r
+#define B_PCH_PMC_FUNC_DIS_LPSS2_FUNC3            BIT27 // LPSS2 I2C #3\r
+#define B_PCH_PMC_FUNC_DIS_LPSS2_FUNC2            BIT26 // LPSS2 I2C #2\r
+#define B_PCH_PMC_FUNC_DIS_LPSS2_FUNC1            BIT25 // LPSS2 I2C #1\r
+#define B_PCH_PMC_FUNC_DIS_LPSS2_FUNC0            BIT24 // LPSS2 DMA Disable\r
+#define B_PCH_PMC_FUNC_DIS_PCI_EX_FUNC3           BIT23 // PCI Express Function 3 Disable\r
+#define B_PCH_PMC_FUNC_DIS_PCI_EX_FUNC2           BIT22 // PCI Express Function 2 Disable\r
+#define B_PCH_PMC_FUNC_DIS_PCI_EX_FUNC1           BIT21 // PCI Express Function 1 Disable\r
+#define B_PCH_PMC_FUNC_DIS_PCI_EX_FUNC0           BIT20 // PCI Express Function 0 Disable\r
+#define N_PCH_PMC_FUNC_DIS_PCI_EX_FUNC0           20\r
+#define B_PCH_PMC_FUNC_DIS_SEC                    BIT19 // SEC Disable\r
+#define B_PCH_PMC_FUNC_DIS_USB                    BIT18 // USB Disable\r
+#define B_PCH_PMC_FUNC_DIS_SATA                   BIT17 // SATA Disable\r
+#define B_PCH_PMC_FUNC_DIS_USH                    BIT15 // USH (USB3) Disable\r
+#define B_PCH_PMC_FUNC_DIS_OTG                    BIT14 // USB OTG Disable\r
+#define B_PCH_PMC_FUNC_DIS_LPE                    BIT13 // LPE Disable\r
+#define B_PCH_PMC_FUNC_DIS_AZALIA                 BIT12 // Azalia Disable\r
+#define B_PCH_PMC_FUNC_DIS_MIPI                   BIT11 // MIPI-HSI Disable\r
+#define B_PCH_PMC_FUNC_DIS_SDIO4                  BIT11 // SCC SDIO #4 (Device 23, eMMC4.5) Disable\r
+#define B_PCH_PMC_FUNC_DIS_SDIO3                  BIT10 // SCC SDIO #3 (Device 18, SD Card) Disable\r
+#define B_PCH_PMC_FUNC_DIS_SDIO2                  BIT9  // SCC SDIO #2 (Device 17, SDIO) Disable\r
+#define B_PCH_PMC_FUNC_DIS_SDIO1                  BIT8  // SCC SDIO #1 (Device 16, eMMC) Disable\r
+#define B_PCH_PMC_FUNC_DIS_LPSS1_FUNC7            BIT7  // LPSS1 Spare #2 Disable\r
+#define B_PCH_PMC_FUNC_DIS_LPSS1_FUNC6            BIT6  // LPSS1 Spare #1 Disable\r
+#define B_PCH_PMC_FUNC_DIS_LPSS1_FUNC5            BIT5  // LPSS1 SPI Disable\r
+#define B_PCH_PMC_FUNC_DIS_LPSS1_FUNC4            BIT4  // LPSS1 HS-UART #2 Disable\r
+#define B_PCH_PMC_FUNC_DIS_LPSS1_FUNC3            BIT3  // LPSS1 HS-UART #1 Disable\r
+#define B_PCH_PMC_FUNC_DIS_LPSS1_FUNC2            BIT2  // LPSS1 PWM #2 Disable\r
+#define B_PCH_PMC_FUNC_DIS_LPSS1_FUNC1            BIT1  // LPSS1 PWM #1 Disable\r
+#define B_PCH_PMC_FUNC_DIS_LPSS1_FUNC0            BIT0  // LPSS1 DMA Disable\r
+\r
+#define R_PCH_PMC_FUNC_DIS2                       0x38  // Function Disable 2 Register\r
+#define B_PCH_PMC_FUNC_DIS2_USH_SS_PHY            BIT2  // USH Super Speed PHY Disable\r
+#define B_PCH_PMC_FUNC_DIS2_OTG_SS_PHY            BIT1  // OTG Super Speed PHY Disable\r
+#define B_PCH_PMC_FUNC_DIS2_SMBUS                 BIT0  // SMBus Disable\r
+\r
+#define R_PCH_PMC_PMIR                            0x48  // Extended Test Mode Register (ETR)\r
+#define B_PCH_PMC_PMIR_CF9LOCK                    BIT31 // CF9h Lockdown\r
+#define B_PCH_PMC_PMIR_LTR_DEF                    BIT22 // LTR Default\r
+#define B_PCH_PMC_PMIR_IGNORE_HPET                BIT21 // Ignore HPET Disable Check Before Going to S0i2\r
+#define B_PCH_PMC_PMIR_CF9GR                      BIT20 // CF9h Global Reset\r
+\r
+#define R_PCH_PMC_VLT                             0x50  // Voltage Detect Register\r
+#define B_PCH_PMC_VLT_FUSES                       0xFF  // Voltage Detect Fuses\r
+\r
+#define R_PCH_PMC_GPI_ROUT                        0x58  // GPI Rout\r
+#define B_PCH_PMC_GPI_ROUT_0                      (BIT1 | BIT0)\r
+#define B_PCH_PMC_GPI_ROUT_1                      (BIT3 | BIT2)\r
+#define B_PCH_PMC_GPI_ROUT_2                      (BIT5 | BIT4)\r
+#define B_PCH_PMC_GPI_ROUT_3                      (BIT7 | BIT6)\r
+#define B_PCH_PMC_GPI_ROUT_4                      (BIT9 | BIT8)\r
+#define B_PCH_PMC_GPI_ROUT_5                      (BIT11 | BIT10)\r
+#define B_PCH_PMC_GPI_ROUT_6                      (BIT13 | BIT12)\r
+#define B_PCH_PMC_GPI_ROUT_7                      (BIT15 | BIT14)\r
+#define B_PCH_PMC_GPI_ROUT_8                      (BIT17 | BIT16)\r
+#define B_PCH_PMC_GPI_ROUT_9                      (BIT19 | BIT18)\r
+#define B_PCH_PMC_GPI_ROUT_10                     (BIT21 | BIT20)\r
+#define B_PCH_PMC_GPI_ROUT_11                     (BIT23 | BIT22)\r
+#define B_PCH_PMC_GPI_ROUT_12                     (BIT25 | BIT24)\r
+#define B_PCH_PMC_GPI_ROUT_13                     (BIT27 | BIT26)\r
+#define B_PCH_PMC_GPI_ROUT_14                     (BIT29 | BIT28)\r
+#define B_PCH_PMC_GPI_ROUT_15                     (BIT31 | BIT30)\r
+\r
+#define R_PCH_PMC_PCC0                            0x60  // Platform Clock Control 0\r
+#define B_PCH_PMC_PCC0_CLK_FREQ                   BIT2  // Clock Frequency\r
+#define B_PCH_PMC_PCC0_CLK_CTL                    (BIT1 | BIT0) // Clock Gating\r
+\r
+#define R_PCH_PMC_PCC1                            0x64  // Platform Clock Control 1\r
+#define B_PCH_PMC_PCC1_CLK_FREQ                   BIT2  // Clock Frequency\r
+#define B_PCH_PMC_PCC1_CLK_CTL                    (BIT1 | BIT0) // Clock Gating\r
+\r
+#define R_PCH_PMC_PCC2                            0x68  // Platform Clock Control 2\r
+#define B_PCH_PMC_PCC2_CLK_FREQ                   BIT2  // Clock Frequency\r
+#define B_PCH_PMC_PCC2_CLK_CTL                    (BIT1 | BIT0) // Clock Gating\r
+\r
+#define R_PCH_PMC_PCC3                            0x6C  // Platform Clock Control 3\r
+#define B_PCH_PMC_PCC3_CLK_FREQ                   BIT2  // Clock Frequency\r
+#define B_PCH_PMC_PCC3_CLK_CTL                    (BIT1 | BIT0) // Clock Gating\r
+\r
+#define R_PCH_PMC_PCC4                            0x70  // Platform Clock Control 4\r
+#define B_PCH_PMC_PCC4_CLK_FREQ                   BIT2  // Clock Frequency\r
+#define B_PCH_PMC_PCC4_CLK_CTL                    (BIT1 | BIT0) // Clock Gating\r
+\r
+#define R_PCH_PMC_PCC5                            0x74  // Platform Clock Control 5\r
+#define B_PCH_PMC_PCC5_CLK_FREQ                   BIT2  // Clock Frequency\r
+#define B_PCH_PMC_PCC5_CLK_CTL                    (BIT1 | BIT0) // Clock Gating\r
+\r
+#define R_PCH_PMC_S0IR_TMR                        0x80  // S0I Ready Residency Timer\r
+#define B_PCH_PMC_S0IR_TMR_RTIME                  0xFFFFFFFF // Time Spent in S0I Ready State\r
+\r
+#define R_PCH_PMC_S0I1_TMR                        0x84  // S0I1 Ready Residency Timer\r
+#define B_PCH_PMC_S0I1_TMR_RTIME                  0xFFFFFFFF // Time Spent in S0I1 Ready State\r
+\r
+#define R_PCH_PMC_S0I2_TMR                        0x88  // S0I2 Ready Residency Timer\r
+#define B_PCH_PMC_S0I2_TMR_RTIME                  0xFFFFFFFF // Time Spent in S0I2 Ready State\r
+\r
+#define R_PCH_PMC_S0I3_TMR                        0x8C  // S0I3 Ready Residency Timer\r
+#define B_PCH_PMC_S0I3_TMR_RTIME                  0xFFFFFFFF // Time Spent in S0I3 Ready State\r
+\r
+#define R_PCH_PMC_S0_TMR                          0x90  // S0 Residency Timer\r
+#define B_PCH_PMC_S0_TMR_RTIME                    0xFFFFFFFF // Time Spent in S0 State\r
+\r
+#define R_PCH_PMC_PSS                             0x98  // Power Island Power Status\r
+#define B_PCH_PMC_PSS_PG_STS                      0x3FFFF // Power Gate Status of All Power Islands\r
+#define B_PCH_PMC_PSS_PG_STS_USB_SUS              BIT17 // USB SUS\r
+#define B_PCH_PMC_PSS_PG_STS_USB                  BIT16 // USB\r
+#define B_PCH_PMC_PSS_PG_STS_OTG_VCCACLK          BIT15 // OTG VCCACLK\r
+#define B_PCH_PMC_PSS_PG_STS_OTG VCCA             BIT14 // OTG VCCA\r
+#define B_PCH_PMC_PSS_PG_STS_OTG_VCCS             BIT13 // OTG VCCS\r
+#define B_PCH_PMC_PSS_PG_STS_OTG_CTL              BIT12 // OTG Control\r
+#define B_PCH_PMC_PSS_PG_STS_USH_VCCA             BIT11 // USH VCCA\r
+#define B_PCH_PMC_PSS_PG_STS_USH_VCCS             BIT10 // USH VCCS\r
+#define B_PCH_PMC_PSS_PG_STS_USH_SUS              BIT9  // USH SUS\r
+#define B_PCH_PMC_PSS_PG_STS_USH_CTL              BIT8  // USH Control\r
+#define B_PCH_PMC_PSS_PG_STS_DFX                  BIT7  // DFX\r
+#define B_PCH_PMC_PSS_PG_STS_LPE                  BIT6  // LPE Audio\r
+#define B_PCH_PMC_PSS_PG_STS_LPSS                 BIT5  // LPSS\r
+#define B_PCH_PMC_PSS_PG_STS_PCIE                 BIT4  // PCIe\r
+#define B_PCH_PMC_PSS_PG_STS_HDA                  BIT2  // HDA\r
+#define B_PCH_PMC_PSS_PG_STS_SATA                 BIT1  // SATA\r
+\r
+#define R_PCH_PMC_D3_STS_0                        0xA0  // D3 Status 0\r
+#define B_PCH_PMC_D3_STS_0_LPSS1F7                BIT31 // LPSS 1 Function 7\r
+#define B_PCH_PMC_D3_STS_0_LPSS1F6                BIT30 // LPSS 1 Function 6\r
+#define B_PCH_PMC_D3_STS_0_LPSS1F5                BIT29 // LPSS 1 Function 5\r
+#define B_PCH_PMC_D3_STS_0_LPSS1F4                BIT28 // LPSS 1 Function 4\r
+#define B_PCH_PMC_D3_STS_0_LPSS1F3                BIT27 // LPSS 1 Function 3\r
+#define B_PCH_PMC_D3_STS_0_LPSS1F2                BIT26 // LPSS 1 Function 2\r
+#define B_PCH_PMC_D3_STS_0_LPSS1F1                BIT25 // LPSS 1 Function 1\r
+#define B_PCH_PMC_D3_STS_0_LPSS1F0                BIT24 // LPSS 1 Function 0\r
+#define B_PCH_PMC_D3_STS_0_PCIEF3                 BIT23 // PCIe Function 3\r
+#define B_PCH_PMC_D3_STS_0_PCIEF2                 BIT22 // PCIe Function 2\r
+#define B_PCH_PMC_D3_STS_0_PCIEF1                 BIT21 // PCIe Function 1\r
+#define B_PCH_PMC_D3_STS_0_PCIEF0                 BIT20 // PCIe Function 0\r
+#define B_PCH_PMC_D3_STS_0_USB                    BIT18 // USB\r
+#define B_PCH_PMC_D3_STS_0_SATA                   BIT17 // SATA\r
+#define B_PCH_PMC_D3_STS_0_USH                    BIT15 // USH\r
+#define B_PCH_PMC_D3_STS_0_OTG                    BIT14 // OTG\r
+#define B_PCH_PMC_D3_STS_0_LPE                    BIT13 // LPE\r
+#define B_PCH_PMC_D3_STS_0_HDA                    BIT12 // HDA\r
+#define B_PCH_PMC_D3_STS_0_MIPI                   BIT11 // MIPI-HSI\r
+#define B_PCH_PMC_D3_STS_0_SCCF2                  BIT10 // SCC Function 2\r
+#define B_PCH_PMC_D3_STS_0_SCCF1                  BIT9  // SCC Function 1\r
+#define B_PCH_PMC_D3_STS_0_SCCF0                  BIT8  // SCC Function 0\r
+#define B_PCH_PMC_D3_STS_0_LPSS0F7                BIT7  // LPSS 0 Function 7\r
+#define B_PCH_PMC_D3_STS_0_LPSS0F6                BIT6  // LPSS 0 Function 6\r
+#define B_PCH_PMC_D3_STS_0_LPSS0F5                BIT5  // LPSS 0 Function 5\r
+#define B_PCH_PMC_D3_STS_0_LPSS0F4                BIT4  // LPSS 0 Function 4\r
+#define B_PCH_PMC_D3_STS_0_LPSS0F3                BIT3  // LPSS 0 Function 3\r
+#define B_PCH_PMC_D3_STS_0_LPSS0F2                BIT2  // LPSS 0 Function 2\r
+#define B_PCH_PMC_D3_STS_0_LPSS0F1                BIT1  // LPSS 0 Function 1\r
+#define B_PCH_PMC_D3_STS_0_LPSS0F0                BIT0  // LPSS 0 Function 0\r
+\r
+#define R_PCH_PMC_D3_STS_1                        0xA4  // D3 Status 1\r
+#define B_PCH_PMC_D3_STS_1_DFX                    BIT3  // DFX\r
+#define B_PCH_PMC_D3_STS_1_OTG_SS                 BIT2  // OTG SS\r
+#define B_PCH_PMC_D3_STS_1_USH_SS                 BIT1  // USH SS\r
+#define B_PCH_PMC_D3_STS_1_SMB                    BIT0  // SMBus\r
+#define R_PCH_PMC_D3_STDBY_STS_0                  0xA8  // D3 Standby Status 0\r
+#define B_PCH_PMC_D3_STDBY_STS_0_LPSS1F7          BIT31 // LPSS 1 Function 7\r
+#define B_PCH_PMC_D3_STDBY_STS_0_LPSS1F6          BIT30 // LPSS 1 Function 6\r
+#define B_PCH_PMC_D3_STDBY_STS_0_LPSS1F5          BIT29 // LPSS 1 Function 5\r
+#define B_PCH_PMC_D3_STDBY_STS_0_LPSS1F4          BIT28 // LPSS 1 Function 4\r
+#define B_PCH_PMC_D3_STDBY_STS_0_LPSS1F3          BIT27 // LPSS 1 Function 3\r
+#define B_PCH_PMC_D3_STDBY_STS_0_LPSS1F2          BIT26 // LPSS 1 Function 2\r
+#define B_PCH_PMC_D3_STDBY_STS_0_LPSS1F1          BIT25 // LPSS 1 Function 1\r
+#define B_PCH_PMC_D3_STDBY_STS_0_LPSS1F0          BIT24 // LPSS 1 Function 0\r
+#define B_PCH_PMC_D3_STDBY_STS_0_PCIEF3           BIT23 // PCIe Function 3\r
+#define B_PCH_PMC_D3_STDBY_STS_0_PCIEF2           BIT22 // PCIe Function 2\r
+#define B_PCH_PMC_D3_STDBY_STS_0_PCIEF1           BIT21 // PCIe Function 1\r
+#define B_PCH_PMC_D3_STDBY_STS_0_PCIEF0           BIT20 // PCIe Function 0\r
+#define B_PCH_PMC_D3_STDBY_STS_0_USB              BIT18 // USB\r
+#define B_PCH_PMC_D3_STDBY_STS_0_SATA             BIT17 // SATA\r
+#define B_PCH_PMC_D3_STDBY_STS_0_USH              BIT15 // USH\r
+#define B_PCH_PMC_D3_STDBY_STS_0_OTG              BIT14 // OTG\r
+#define B_PCH_PMC_D3_STDBY_STS_0_LPE              BIT13 // LPE\r
+#define B_PCH_PMC_D3_STDBY_STS_0_HDA              BIT12 // HDA\r
+#define B_PCH_PMC_D3_STDBY_STS_0_MIPI             BIT11 // MIPI-HSI\r
+#define B_PCH_PMC_D3_STDBY_STS_0_SCCF2            BIT10 // SCC Function 2\r
+#define B_PCH_PMC_D3_STDBY_STS_0_SCCF1            BIT9  // SCC Function 1\r
+#define B_PCH_PMC_D3_STDBY_STS_0_SCCF0            BIT8  // SCC Function 0\r
+#define B_PCH_PMC_D3_STDBY_STS_0_LPSS0F7          BIT7  // LPSS 0 Function 7\r
+#define B_PCH_PMC_D3_STDBY_STS_0_LPSS0F6          BIT6  // LPSS 0 Function 6\r
+#define B_PCH_PMC_D3_STDBY_STS_0_LPSS0F5          BIT5  // LPSS 0 Function 5\r
+#define B_PCH_PMC_D3_STDBY_STS_0_LPSS0F4          BIT4  // LPSS 0 Function 4\r
+#define B_PCH_PMC_D3_STDBY_STS_0_LPSS0F3          BIT3  // LPSS 0 Function 3\r
+#define B_PCH_PMC_D3_STDBY_STS_0_LPSS0F2          BIT2  // LPSS 0 Function 2\r
+#define B_PCH_PMC_D3_STDBY_STS_0_LPSS0F1          BIT1  // LPSS 0 Function 1\r
+#define B_PCH_PMC_D3_STDBY_STS_0_LPSS0F0          BIT0  // LPSS 0 Function 0\r
+\r
+#define R_PCH_PMC_D3_STDBY_STS_1                  0xAC  // D3 Standby Status 1\r
+#define B_PCH_PMC_D3_STDBY_STS_1_DFX              BIT3  // DFX\r
+#define B_PCH_PMC_D3_STDBY_STS_1_OTG_SS           BIT2  // OTG SS\r
+#define B_PCH_PMC_D3_STDBY_STS_1_USH_SS           BIT1  // USH SS\r
+#define B_PCH_PMC_D3_STDBY_STS_1_SMB              BIT0  // SMBus\r
+\r
+#define R_PCH_PMC_MTPMC1                          0xB0  // Message to PMC 1\r
+\r
+#define R_PCH_PMC_MTPMC2                          0xB4  // Message to PMC 2\r
+\r
+#define R_PCH_PMC_MTPMC3                          0xB8  // Message to PMC 3\r
+\r
+#define R_PCH_PMC_MTPMC4                          0xBC  // Message to PMC 4\r
+\r
+//\r
+// IO Memory Space Registers (IOBASE)\r
+//\r
+#define R_PCH_CFIO_PAD_CONF0                      0x00  // CFIO PAD_CONF0\r
+#define R_PCH_CFIO_PAD_CONF1                      0x04  // CFIO PAD_CONF1\r
+#define R_PCH_CFIO_PAD_VAL                        0x08  // CFIO PAD_VAL\r
+#define R_PCH_CFIO_PAD_DFT                        0x0C  // CFIO PAD_CFT\r
+\r
+//\r
+// GPIO Register Offsets from GBASE\r
+//\r
+#define R_PCH_GPIO_SC_USE_SEL                     0x00  // GPIO South Usage Select [31:0]\r
+#define R_PCH_GPIO_SC_IO_SEL                      0x04  // GPIO South Input / Output Select [31:0]\r
+#define R_PCH_GPIO_SC_LVL                         0x08  // GPIO South Level for Input or Output [31:0]\r
+\r
+#define R_PCH_GPIO_SC_TPE                         0x0C  // GPIO South Trigger Positive Edge Enable [31:0]\r
+#define R_PCH_GPIO_SC_TNE                         0x10  // GPIO South Trigger Negative Edge Enable [31:0]\r
+#define R_PCH_GPIO_SC_TS                          0x14  // GPIO South Trigger Status [31:0]\r
+\r
+#define R_PCH_GPIO_SC_USE_SEL2                    0x20  // GPIO South Usage Select 2 [63:32]\r
+#define R_PCH_GPIO_SC_IO_SEL2                     0x24  // GPIO South Input / Output Select 2 [63:32]\r
+#define R_PCH_GPIO_SC_LVL2                        0x28  // GPIO South Level for Input or Output 2 [63:32]\r
+\r
+#define R_PCH_GPIO_SC_TPE2                        0x2C  // GPIO South Trigger Positive Edge Enable 2 [63:32]\r
+#define R_PCH_GPIO_SC_TNE2                        0x30  // GPIO South Trigger Negative Edge Enable 2 [63:32]\r
+#define R_PCH_GPIO_SC_TS2                         0x34  // GPIO South Trigger Status 2 [63:32]\r
+\r
+#define R_PCH_GPIO_SC_USE_SEL3                    0x40  // GPIO South Usage Select 3 [95:64]\r
+#define R_PCH_GPIO_SC_IO_SEL3                     0x44  // GPIO South Input / Output Select 3 [95:64]\r
+#define R_PCH_GPIO_SC_LVL3                        0x48  // GPIO South Level for Input or Output 3 [95:64]\r
+\r
+#define R_PCH_GPIO_SC_TPE3                        0x4C  // GPIO South Trigger Positive Edge Enable 3 [95:64]\r
+#define R_PCH_GPIO_SC_TNE3                        0x50  // GPIO South Trigger Negative Edge Enable 3 [95:64]\r
+#define R_PCH_GPIO_SC_TS3                         0x54  // GPIO South Trigger Status 3 [95:64]\r
+\r
+#define R_PCH_GPIO_SC_USE_SEL4                    0x60  // GPIO South Usage Select 4 [127:96]\r
+#define R_PCH_GPIO_SC_IO_SEL4                     0x64  // GPIO South Input / Output Select 4 [127:96]\r
+#define R_PCH_GPIO_SC_LVL4                        0x68  // GPIO South Level for Input or Output 4 [127:96]\r
+\r
+#define R_PCH_GPIO_SC_TPE4                        0x6C  // GPIO South Trigger Positive Edge Enable 4 [127:96]\r
+#define R_PCH_GPIO_SC_TNE4                        0x70  // GPIO South Trigger Negative Edge Enable 4 [127:96]\r
+#define R_PCH_GPIO_SC_TS4                         0x74  // GPIO South Trigger Status 4 [127:96]\r
+\r
+#define R_PCH_GPIO_SUS_USE_SEL                    0x80  // GPIO Suspend Use Select [31:0]\r
+#define R_PCH_GPIO_SUS_IO_SEL                     0x84  // GPIO Suspend Input / Output Select [31:0]\r
+#define R_PCH_GPIO_SUS_LVL                        0x88  // GPIO Suspend Level for Input or Output [31:0]\r
+\r
+#define R_PCH_GPIO_SUS_TPE                        0x8C  // GPIO Suspend Trigger Positive Edge Enable [31:0]\r
+#define R_PCH_GPIO_SUS_TNE                        0x90  // GPIO Suspend Trigger Negative Edge Enable [31:0]\r
+#define R_PCH_GPIO_SUS_TS                         0x94  // GPIO Suspend Trigger Status [31:0]\r
+\r
+#define R_PCH_GPIO_SUS_WAKE_EN                    0x98  // GPIO Suspend Wake Enable [31:0]\r
+\r
+#define R_PCH_GPIO_SUS_USE_SEL2                   0x100 // GPIO Suspend Use Select 2 [42:32]\r
+#define R_PCH_GPIO_SUS_IO_SEL2                    0x104 // GPIO Suspend Input / Output Select 2 [42:32]\r
+#define R_PCH_GPIO_SUS_LVL2                       0x108 // GPIO Suspend Level for Input or Output 2 [42:32]\r
+\r
+#define R_PCH_GPIO_SUS_TPE2                       0x10C // GPIO Suspend Trigger Positive Edge Enable [42:32]\r
+#define R_PCH_GPIO_SUS_TNE2                       0x110 // GPIO Suspend Trigger Negative Edge Enable [42:32]\r
+#define R_PCH_GPIO_SUS_TS2                        0x114 // GPIO Suspend Trigger Status [42:32]\r
+\r
+#define R_PCH_GPIO_SUS_WAKE_EN2                   0x118 // GPIO Suspend Wake Enable 2 [42:32]\r
+\r
+//\r
+// Fixed IO Space\r
+//\r
+\r
+//\r
+// Processor Interface Registers\r
+//\r
+#define R_PCH_NMI_SC                              0x61  // NMI Status and Control\r
+#define B_PCH_NMI_SC_SERR_NMI_STS                 BIT7  // SERR# NMI Status\r
+#define B_PCH_NMI_SC_IOCHK_NMI_STS                BIT6  // IOCHK NMI Status\r
+#define B_PCH_NMI_SC_TMR2_OUT_STS                 BIT5  // Timer Counter 2 Status\r
+#define B_PCH_NMI_SC_REF_TOGGLE                   BIT4  // Refresh Cycle toggle Status\r
+#define B_PCH_NMI_SC_IOCHK_NMI_EN                 BIT3  // IOCHK NMI Enable\r
+#define B_PCH_NMI_SC_PCI_SERR_EN                  BIT2  // SERR# NMI Enable\r
+#define B_PCH_NMI_SC_SPKR_DAT_EN                  BIT1  // Speaker Data Enable\r
+#define B_PCH_NMI_SC_TIM_CNT2_EN                  BIT0  // Timer Counter 2 Enable\r
+\r
+#define R_PCH_NMI_EN                              0x70  // NMI Enable and Real Time Clock Index, Co-function with R_PCH_RTC_INDEX\r
+#define B_PCH_NMI_EN_NMI_EN                       BIT7  // NMI Enable, must preserve this bit first before writing to IO port 0x70\r
+\r
+//\r
+// RTC Registers\r
+//\r
+#define R_PCH_RTC_INDEX                           0x70  // NMI Enable and Real Time Clock Index, Co-function with R_PCH_NMI_EN\r
+#define R_PCH_RTC_TARGET                          0x71  // Real-Time Clock Target Register\r
+#define R_PCH_RTC_EXT_INDEX                       0x72  // Extended RAM Index Register\r
+#define R_PCH_RTC_EXT_TARGET                      0x73  // Extended RAM Target Register\r
+#define R_PCH_RTC_INDEX2                          0x74  // Real-Time Clock Index Register\r
+#define R_PCH_RTC_TARGET2                         0x75  // Real-Time Clock Target Register\r
+#define R_PCH_RTC_EXT_INDEX2                      0x76  // Extended RAM Index Register\r
+#define R_PCH_RTC_EXT_TARGET2                     0x77  // Extended RAM Target Register\r
+\r
+#define R_PCH_RTC_SECONDS                         0x00  // Seconds, Range 0..59\r
+#define R_PCH_RTC_SECONDSALARM                    0x01  // Seconds Alarm, Range 0..59\r
+#define R_PCH_RTC_MINUTES                         0x02  // Minutes, Range 0..59\r
+#define R_PCH_RTC_MINUTESALARM                    0x03  // Minutes Alarm, Range 0..59\r
+#define R_PCH_RTC_HOURS                           0x04  // Hours, Range 1..12 or 0..23 Bit 7 is AM/PM\r
+#define R_PCH_RTC_HOURSALARM                      0x05  // Hours Alarm, Range 1..12 or 0..23 Bit 7 is AM/PM\r
+#define R_PCH_RTC_DAYOFWEEK                       0x06  // Day of Week, Range 1..7\r
+#define R_PCH_RTC_DAYOFMONTH                      0x07  // Day of Month, Range 1..31\r
+#define R_PCH_RTC_MONTH                           0x08  // Month, Range 1..12\r
+#define R_PCH_RTC_YEAR                            0x09  // Year, Range 0..99\r
+\r
+#define R_PCH_RTC_REGISTERA                       0x0A  // RTC Register A\r
+#define B_PCH_RTC_REGISTERA_UIP                   BIT7  // Update In Progress\r
+#define B_PCH_RTC_REGISTERA_DV                    (BIT6 | BIT5 | BIT4) // Division Chain Select\r
+#define V_PCH_RTC_REGISTERA_DV_NORM_OP            0x20  // Normal Operation\r
+#define V_PCH_RTC_REGISTERA_DV_BYP_5              0x30  // Bypass 5 Stages (Test mode only)\r
+#define V_PCH_RTC_REGISTERA_DV_BYP_10             0x40  // Bypass 10 Stages (Test mode only)\r
+#define V_PCH_RTC_REGISTERA_DV_BYP_15             0x50  // Bypass 15 Stages (Test mode only)\r
+#define V_PCH_RTC_REGISTERA_DV_DIV_RST1           0x60  // Divider Reset\r
+#define V_PCH_RTC_REGISTERA_DV_DIV_RST2           0x70  // Divider Reset\r
+#define B_PCH_RTC_REGISTERA_RS                    (BIT3 | BIT2 | BIT1 | BIT0) // Rate Select\r
+#define V_PCH_RTC_REGISTERA_RS_INT_NV_TGL         0x00  // Interrupt Never Toggles\r
+#define V_PCH_RTC_REGISTERA_RS_3P906MS1           0x01  // 3.90625 ms\r
+#define V_PCH_RTC_REGISTERA_RS_7P812MS1           0x02  // 7.8125 ms\r
+#define V_PCH_RTC_REGISTERA_RS_122P0US            0x03  // 122.070 us\r
+#define V_PCH_RTC_REGISTERA_RS_244P1US            0x04  // 244.141 us\r
+#define V_PCH_RTC_REGISTERA_RS_488P2US            0x05  // 488.281 us\r
+#define V_PCH_RTC_REGISTERA_RS_976P5US            0x06  // 976.5625 us\r
+#define V_PCH_RTC_REGISTERA_RS_1P953MS            0x07  // 1.953125 ms\r
+#define V_PCH_RTC_REGISTERA_RS_3P906MS            0x08  // 3.90625 ms\r
+#define V_PCH_RTC_REGISTERA_RS_7P812MS            0x09  // 7.8125 ms\r
+#define V_PCH_RTC_REGISTERA_RS_15P62MS            0x0A  // 15.625 ms\r
+#define V_PCH_RTC_REGISTERA_RS_31P25MS            0x0B  // 31.25 ms\r
+#define V_PCH_RTC_REGISTERA_RS_62P5MS             0x0C  // 62.5 ms\r
+#define V_PCH_RTC_REGISTERA_RS_125MS              0x0D  // 125 ms\r
+#define V_PCH_RTC_REGISTERA_RS_250MS              0x0E  // 250 ms\r
+#define V_PCH_RTC_REGISTERA_RS_500MS              0x0F  // 500 ms\r
+\r
+#define R_PCH_RTC_REGISTERB                       0x0B  // RTC Register B\r
+#define B_PCH_RTC_REGISTERB_SET                   BIT7  // Update Cycle Inhibit 1: Stop auto update, begin set value; 0: Update cycle occurs\r
+#define B_PCH_RTC_REGISTERB_PIE                   BIT6  // Periodic Interrupt Enable\r
+#define B_PCH_RTC_REGISTERB_AIE                   BIT5  // Alarm Interrupt Enable\r
+#define B_PCH_RTC_REGISTERB_UIE                   BIT4  // Update-ended Interrupt Enable\r
+#define B_PCH_RTC_REGISTERB_SQWE                  BIT3  // Square Wave Enable (Not implemented)\r
+#define B_PCH_RTC_REGISTERB_DM                    BIT2  // Data Mode 1: Binary; 0:BCD\r
+#define B_PCH_RTC_REGISTERB_HF                    BIT1  // Hour Format 1: 24 mode; 0: 12 mode.\r
+#define B_PCH_RTC_REGISTERB_DSE                   BIT0  // Daylight Savings Enable (Not Implemented)\r
+\r
+#define R_PCH_RTC_REGISTERC                       0x0C  // RTC Register C\r
+#define B_PCH_RTC_REGISTERC_IRQF                  BIT7  // Interrupt Request Flag\r
+#define B_PCH_RTC_REGISTERC_PF                    BIT6  // Periodic Interrupt Flag\r
+#define B_PCH_RTC_REGISTERC_AF                    BIT5  // Alarm Flag\r
+#define B_PCH_RTC_REGISTERC_UF                    BIT4  // Update-ended Flag\r
+#define B_PCH_RTC_REGISTERC_RESERVED              (BIT3 | BIT2 | BIT1 | BIT0)\r
+\r
+#define R_PCH_RTC_REGISTERD                       0x0D  // RTC Register D\r
+#define B_PCH_RTC_REGISTERD_VRT                   BIT7  // Valid RAM and Time Bit\r
+#define B_PCH_RTC_REGISTERD_RESERVED              BIT6\r
+#define B_PCH_RTC_REGISTERD_DA                    0x3F  // Date Alarm\r
+\r
+#define B_PCH_RTC_CENTURY                         0x32  // Century Data\r
+\r
+//\r
+// APM Registers\r
+//\r
+#define R_PCH_APM_CNT                             0xB2  // Advanced Power Management Control Port\r
+#define R_PCH_APM_STS                             0xB3  // Advanced Power Management Status Port\r
+\r
+//\r
+// INIT Register\r
+//\r
+#define R_PCH_PORT92                              0x92\r
+#define B_PCH_PORT92_ALT_A20_GATE                 BIT1  // Alternate A20 Gate\r
+#define B_PCH_PORT92_INIT_NOW                     BIT0  // Init Now\r
+\r
+//\r
+// PCU UART\r
+//\r
+#define R_PCH_COM1_BASE                           0x3F8 // COM1 IO BASE\r
+\r
+//\r
+// Reset Control Register\r
+//\r
+#define R_PCH_RST_CNT                             0xCF9 // Reset Control\r
+#define B_PCH_RST_CNT_FULL_RST                    BIT3\r
+#define B_PCH_RST_CNT_RST_CPU                     BIT2\r
+#define B_PCH_RST_CNT_SYS_RST                     BIT1\r
+#define V_PCH_RST_CNT_FULLRESET                   0x0E\r
+#define V_PCH_RST_CNT_HARDRESET                   0x06\r
+#define V_PCH_RST_CNT_SOFTRESET                   0x04  // Not supported by VLV\r
+#define V_PCH_RST_CNT_HARDSTARTSTATE              0x02\r
+#define V_PCH_RST_CNT_SOFTSTARTSTATE              0x00\r
+\r
+//\r
+// Fixed Memory Region\r
+//\r
+\r
+//\r
+// IO APIC Registers\r
+//\r
+#define R_PCH_IO_APIC_INDEX                       0xFEC00000 // IOAPIC Index Register, 8bit\r
+#define R_PCH_IO_APIC_WINDOW                      0xFEC00010 // IOAPIC Window Register, 32bit\r
+#define R_PCH_IO_APIC_EOI                         0xFEC00040 // IOAPIC EOI Register, 8bit\r
+\r
+#define R_PCH_IO_APIC_ID                          0x00  // Identification\r
+#define B_PCH_IO_APIC_ID_AID                      (BIT27 | BIT26 | BIT25 | BIT24) // APIC Identification\r
+\r
+#define R_PCH_IO_APIC_VS                          0x01  // Version\r
+#define B_PCH_IO_APIC_VS_MRE                      0xFF0000 // Maximum Redirection Entries\r
+#define B_PCH_IO_APIC_VS_PRQ                      BIT15 // Pin Assertion Register Supported\r
+#define B_PCH_IO_APIC_VS_VS                       0xFF  // Version\r
+\r
+//\r
+// HPET Registers\r
+//\r
+#define R_PCH_PCH_HPET                            0xFED00000 // HPET Base Address\r
+\r
+#define R_PCH_PCH_HPET_GCID                       0x00  // HPET General Capabilities and ID, 64bit\r
+#define B_PCH_PCH_HPET_GCID_CTP                   0xFFFFFFFF00000000 // Counter Tick Period\r
+#define B_PCH_PCH_HPET_GCID_VID                   0xFFFF0000 // Vendor ID\r
+#define B_PCH_PCH_HPET_GCID_LRC                   BIT15 // Legacy Rout Capable\r
+#define B_PCH_PCH_HPET_GCID_CS                    BIT13 // Counter Size\r
+#define B_PCH_PCH_HPET_GCID_NT                    0x1F00 // Number of Timers\r
+#define B_PCH_PCH_HPET_GCID_RID                   0xFF  // Revision ID\r
+#define N_PCH_HPET_ADDR_ASEL                      12\r
+\r
+#define R_PCH_PCH_HPET_GCFG                       0x10  // HPET General Configuration\r
+#define B_PCH_PCH_HPET_GCFG_LRE                   BIT1  // Legacy Rout Enable\r
+#define B_PCH_PCH_HPET_GCFG_EN                    BIT0  // Overall Enable\r
+\r
+#define R_PCH_PCH_HPET_GIS                        0x20  // HPET General Interrupt Status\r
+#define B_PCH_PCH_HPET_GIS_T2                     BIT2  // Timer 2 Status\r
+#define B_PCH_PCH_HPET_GIS_T1                     BIT1  // Timer 1 Status\r
+#define B_PCH_PCH_HPET_GIS_T0                     BIT0  // Timer 0 Status\r
+\r
+#define R_PCH_PCH_HPET_MCV                        0xF0  // HPET Main Counter Value, 64bit\r
+\r
+#define R_PCH_PCH_HPET_T0C                        0x100 // HPET Timer 0 Config and Capabilities\r
+#define R_PCH_PCH_HPET_T0CV_L                     0x108 // HPET Timer 0 Lower Comparator Value\r
+#define R_PCH_PCH_HPET_T0CV_H                     0x10C // HPET Timer 0 Upper Comparator Value\r
+\r
+#define R_PCH_PCH_HPET_T1C                        0x120 // HPET Timer 1 Config and Capabilities\r
+#define R_PCH_PCH_HPET_T1CV                       0x128 // HPET Timer 1 Comparator Value\r
+\r
+#define R_PCH_PCH_HPET_T2C                        0x140 // HPET Timer 2 Config and Capabilities\r
+#define R_PCH_PCH_HPET_T2CV                       0x148 // HPET Timer 2 Comparator Value\r
+\r
+#define B_PCH_PCH_HPET_TXC_IRC                    0xFFFFFFFF00000000 // Interrupt Rout Capability\r
+#define B_PCH_PCH_HPET_TXC_FID                    BIT15 // FSB Interrupt Delivery\r
+#define B_PCH_PCH_HPET_TXC_FE                     BIT14 // FSB Enable\r
+#define B_PCH_PCH_HPET_TXC_IR                     0x3E00 // Interrupt Rout\r
+#define B_PCH_PCH_HPET_TXC_T32M                   BIT8  // Timer 32-bit Mode\r
+#define B_PCH_PCH_HPET_TXC_TVS                    BIT6  // Timer Value Set\r
+#define B_PCH_PCH_HPET_TXC_TS                     BIT5  // Timer Size\r
+#define B_PCH_PCH_HPET_TXC_PIC                    BIT4  // Periodic Interrupt Capable\r
+#define B_PCH_PCH_HPET_TXC_TYP                    BIT3  // Timer Type\r
+#define B_PCH_PCH_HPET_TXC_IE                     BIT2  // Interrupt Enable\r
+#define B_PCH_PCH_HPET_TXC_IT                     BIT1  // Timer Interrupt Type\r
+\r
+#endif\r

diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/PchRegsRcrb.h b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/PchRegsRcrb.h
new file mode 100644 (file)
index 0000000..32f3645
--- /dev/null
+++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/PchRegsRcrb.h
@@ -0,0 +1,54 @@
+/**\r
+\r
+Copyright (c) 2012  - 2014, Intel Corporation. All rights reserved\r
+\r
+  This program and the accompanying materials are licensed and made available under\r
+  the terms and conditions of the BSD License that accompanies this distribution.\r
+  The full text of the license may be found at\r
+  http://opensource.org/licenses/bsd-license.php.\r
+\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+\r
+  @file\r
+  PchRegsRcrb.h\r
+\r
+  @brief\r
+  Register names for VLV Chipset Configuration Registers\r
+\r
+  Conventions:\r
+\r
+  - Prefixes:\r
+    Definitions beginning with "R_" are registers\r
+    Definitions beginning with "B_" are bits within registers\r
+    Definitions beginning with "V_" are meaningful values of bits within the registers\r
+    Definitions beginning with "S_" are register sizes\r
+    Definitions beginning with "N_" are the bit position\r
+  - In general, PCH registers are denoted by "_PCH_" in register names\r
+  - Registers / bits that are different between PCH generations are denoted by\r
+    "_PCH_<generation_name>_" in register/bit names. e.g., "_PCH_VLV_"\r
+  - Registers / bits that are different between SKUs are denoted by "_<SKU_name>"\r
+    at the end of the register/bit names\r
+  - Registers / bits of new devices introduced in a PCH generation will be just named\r
+    as "_PCH_" without <generation_name> inserted.\r
+\r
+**/\r
+#ifndef _PCH_REGS_RCRB_H_\r
+#define _PCH_REGS_RCRB_H_\r
+\r
+///\r
+/// Chipset Configuration Registers (Memory space)\r
+/// RCBA\r
+///\r
+#define R_PCH_RCRB_GCS                    0x00  // General Control and Status\r
+#define B_PCH_RCRB_GCS_BBSIZE             (BIT30 | BIT29) // Boot Block Size\r
+#define B_PCH_RCRB_GCS_BBS                (BIT11 | BIT10) // Boot BIOS Straps\r
+#define V_PCH_RCRB_GCS_BBS_SPI            (3 << 10) // Boot BIOS strapped to SPI\r
+#define V_PCH_RCRB_GCS_BBS_LPC            (0 << 10) // Boot BIOS strapped to LPC\r
+#define B_PCH_RCRB_GCS_TS                 BIT1 // Top Swap\r
+#define B_PCH_RCRB_GCS_BILD               BIT0 // BIOS Interface Lock-Down\r
+\r
+\r
+#endif\r

diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/PchRegsSata.h b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/PchRegsSata.h
new file mode 100644 (file)
index 0000000..7b86de3
--- /dev/null
+++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/PchRegsSata.h
@@ -0,0 +1,251 @@
+/**\r
+\r
+Copyright (c) 2012  - 2014, Intel Corporation. All rights reserved\r
+\r
+  This program and the accompanying materials are licensed and made available under\r
+  the terms and conditions of the BSD License that accompanies this distribution.\r
+  The full text of the license may be found at\r
+  http://opensource.org/licenses/bsd-license.php.\r
+\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+\r
+  @file\r
+  PchRegsSata.h\r
+\r
+  @brief\r
+  Register names for VLV SATA controllers\r
+\r
+  Conventions:\r
+\r
+  - Prefixes:\r
+    Definitions beginning with "R_" are registers\r
+    Definitions beginning with "B_" are bits within registers\r
+    Definitions beginning with "V_" are meaningful values of bits within the registers\r
+    Definitions beginning with "S_" are register sizes\r
+    Definitions beginning with "N_" are the bit position\r
+  - In general, PCH registers are denoted by "_PCH_" in register names\r
+  - Registers / bits that are different between PCH generations are denoted by\r
+    "_PCH_<generation_name>_" in register/bit names. e.g., "_PCH_VLV_"\r
+  - Registers / bits that are different between SKUs are denoted by "_<SKU_name>"\r
+    at the end of the register/bit names\r
+  - Registers / bits of new devices introduced in a PCH generation will be just named\r
+    as "_PCH_" without <generation_name> inserted.\r
+\r
+**/\r
+#ifndef _PCH_REGS_SATA_H_\r
+#define _PCH_REGS_SATA_H_\r
+\r
+///\r
+/// VLV SATA Message Bus\r
+///\r
+#define PCH_SATA_PHY_PORT_ID                0xA3  // SATA PHY Port ID\r
+#define PCH_SATA_PHY_MMIO_READ_OPCODE       0x00  // CUnit to SATA PHY MMIO Read Opcode\r
+#define PCH_SATA_PHY_MMIO_WRITE_OPCODE      0x01  // CUnit to SATA PHY MMIO Write Opcode\r
+\r
+///\r
+///  SATA Controller Registers (D19:F0)\r
+///\r
+#define PCI_DEVICE_NUMBER_PCH_SATA          19\r
+#define PCI_FUNCTION_NUMBER_PCH_SATA        0\r
+\r
+#define R_PCH_SATA_ID                       0x00  // Identifiers\r
+#define B_PCH_SATA_ID_DID                   0xFFFF0000 // Device ID\r
+#define B_PCH_SATA_ID_VID                   0x0000FFFF // Vendor ID\r
+#define V_PCH_SATA_VENDOR_ID                V_PCH_INTEL_VENDOR_ID\r
+#define V_PCH_SATA_DEVICE_ID_D_IDE          0x0F20  // Desktop IDE Mode (Ports 0 and 1)\r
+#define V_PCH_SATA_DEVICE_ID_D_AHCI         0x0F22  // Desktop AHCI Mode (Ports 0 and 1)\r
+#define V_PCH_SATA_DEVICE_ID_D_RAID         0x2822  // Desktop RAID 0/1/5/10 Mode, based on D19:F0:9Ch[7]\r
+\r
+#define V_PCH_SATA_DEVICE_ID_M_IDE          0x0F21  // Mobile IDE Mode (Ports 0 and 1)\r
+#define V_PCH_SATA_DEVICE_ID_M_AHCI         0x0F23  // Mobile AHCI Mode (Ports 0 and 1)\r
+#define V_PCH_SATA_DEVICE_ID_M_RAID         0x282A  // Mobile RAID 0/1/5/10 Mode, based on D19:F0:9Ch[7]\r
+\r
+#define R_PCH_SATA_COMMAND                  0x04  // Command\r
+#define B_PCH_SATA_COMMAND_INT_DIS          BIT10 // Interrupt Disable\r
+#define B_PCH_SATA_COMMAND_FBE              BIT9  // Fast Back-to-back Enable\r
+#define B_PCH_SATA_COMMAND_SERR_EN          BIT8  // SERR# Enable\r
+#define B_PCH_SATA_COMMAND_WCC              BIT7  // Wait Cycle Enable\r
+#define B_PCH_SATA_COMMAND_PER              BIT6  // Parity Error Response Enable\r
+#define B_PCH_SATA_COMMAND_VPS              BIT5  // VGA Palette Snooping Enable\r
+#define B_PCH_SATA_COMMAND_PMWE             BIT4  // Memory Write and Invalidate Enable\r
+#define B_PCH_SATA_COMMAND_SCE              BIT3  // Special Cycle Enable\r
+#define B_PCH_SATA_COMMAND_BME              BIT2  // Bus Master Enable\r
+#define B_PCH_SATA_COMMAND_MSE              BIT1  // Memory Space Enable\r
+#define B_PCH_SATA_COMMAND_IOSE             BIT0  // I/O Space Enable\r
+\r
+#define R_PCH_SATA_PCISTS                   0x06  // Device Status\r
+#define B_PCH_SATA_PCISTS_DPE               BIT15 // Detected Parity Error\r
+#define B_PCH_SATA_PCISTS_SSE               BIT14 // Signaled System Error\r
+#define B_PCH_SATA_PCISTS_RMA               BIT13 // Received Master-Abort Status\r
+#define B_PCH_SATA_PCISTS_RTA               BIT12 // Received Target-Abort Status\r
+#define B_PCH_SATA_PCISTS_STA               BIT11 // Signaled Target-Abort Status\r
+#define B_PCH_SATA_PCISTS_DEV_STS_MASK      (BIT10 | BIT9) // DEVSEL# Timing Status\r
+#define B_PCH_SATA_PCISTS_DPED              BIT8  // Master Data Parity Error Detected\r
+#define B_PCH_SATA_PCISTS_CAP_LIST          BIT4  // Capabilities List\r
+#define B_PCH_SATA_PCISTS_ITNS              BIT3  // Interrupt Status\r
+\r
+#define R_PCH_SATA_RID                      0x08  // Revision ID (8 bits)\r
+\r
+#define R_PCH_SATA_PI_REGISTER              0x09  // Programming Interface (8 bits)\r
+#define B_PCH_SATA_PI_REGISTER_SNC          BIT3  // Secondary Mode Native Capable\r
+#define B_PCH_SATA_PI_REGISTER_SNE          BIT2  // Secondary Mode Native Enable\r
+#define B_PCH_SATA_PI_REGISTER_PNC          BIT1  // Primary Mode Native Capable\r
+#define B_PCH_SATA_PI_REGISTER_PNE          BIT0  // Primary Mode Native Enable\r
+\r
+#define R_PCH_SATA_CC                       0x0A  // Class Code\r
+#define B_PCH_SATA_CC_BCC                   0xFF00 // Base Class Code\r
+#define B_PCH_SATA_CC_SCC                   0x00FF // Sub Class Code\r
+#define V_PCH_SATA_CC_SCC_IDE               0x01\r
+#define V_PCH_SATA_CC_SCC_AHCI              0x06\r
+#define V_PCH_SATA_CC_SCC_RAID              0x04\r
+\r
+#define R_PCH_SATA_CLS                      0x0C  // Cache Line Size (8 bits)\r
+#define B_PCH_SATA_CLS                      0xFF\r
+\r
+#define R_PCH_SATA_MLT                      0x0D  // Master Latency Timer (8 bits)\r
+#define B_PCH_SATA_MLT                      0xFF\r
+\r
+#define R_PCH_SATA_HTYPE                    0x0E  // Header Type\r
+#define B_PCH_SATA_HTYPE_MFD                BIT7  // Multi-function Device\r
+#define B_PCH_SATA_HTYPE_HL                 0x7F  // Header Layout\r
+\r
+#define R_PCH_SATA_PCMD_BAR                 0x10  // Primary Command Block Base Address\r
+#define B_PCH_SATA_PCMD_BAR_BA              0x0000FFF8 // Base Address\r
+#define B_PCH_SATA_PCMD_BAR_RTE             BIT0  // Resource Type Indicator\r
+\r
+#define R_PCH_SATA_PCTL_BAR                 0x14  // Primary Control Block Base Address\r
+#define B_PCH_SATA_PCTL_BAR_BA              0x0000FFFC // Base Address\r
+#define B_PCH_SATA_PCTL_BAR_RTE             BIT0  // Resource Type Indicator\r
+\r
+#define R_PCH_SATA_SCMD_BAR                 0x18  // Secondary Command Block Base Address\r
+#define B_PCH_SATA_SCMD_BAR_BA              0x0000FFF8 // Base Address\r
+#define B_PCH_SATA_SCMD_BAR_RTE             BIT0  // Resource Type Indicator\r
+\r
+#define R_PCH_SATA_SCTL_BAR                 0x1C  // Secondary Control Block Base Address\r
+#define B_PCH_SATA_SCTL_BAR_BA              0x0000FFFC // Base Address\r
+#define B_PCH_SATA_SCTL_BAR_RTE             BIT0  // Resource Type Indicator\r
+\r
+#define R_PCH_SATA_LBAR                     0x20  // Legacy IDE Base Address / AHCI Index Data Pair Base Address\r
+#define B_PCH_SATA_LBAR_BA                  0x0000FFE0 // Base Address\r
+#define B_PCH_SATA_LBAR_BA4                 BIT4  // Base Address 4\r
+#define B_PCH_SATA_LBAR_RTE                 BIT0  // Resource Type Indicator\r
+\r
+#define R_PCH_SATA_SIDPBA                   0x24  // Serial ATA Index Data Pair Base Address\r
+#define R_PCH_SATA_ABAR                     0x24  // AHCI Base Address\r
+#define B_PCH_SATA_ABAR_BA                  0xFFFFF800 // AHCI Memory Base Address (When CC.SCC not equal 0x01)\r
+#define V_PCH_SATA_ABAR_LENGTH              0x800 // AHCI Memory Length (When CC.SCC not equal 0x01)\r
+#define N_PCH_SATA_ABAR_ALIGNMENT           11    // AHCI Base Address Alignment (When CC.SCC not equal 0x01)\r
+#define B_PCH_SATA_SIDPBA_BA                0x0000FFF0 // Serial ATA Index Data Pair IO Base Address (When CC.SCC equal 0x01)\r
+#define V_PCH_SATA_SIDPBA_LENGTH            0x10  // Serial ATA Index Data Pair IO Length (When CC.SCC equal 0x01)\r
+#define N_PCH_SATA_SIDPBA_ALIGNMENT         4     // Serial ATA Index Data Pair Base Address Alignment (When CC.SCC not equal 0x01)\r
+#define B_PCH_SATA_ABAR_PF                  BIT3  // Prefetchable\r
+#define B_PCH_SATA_ABAR_TP                  (BIT2 | BIT1) // Type\r
+#define B_PCH_SATA_ABAR_RTE                 BIT0  // Resource Type Indicator\r
+\r
+#define R_PCH_SATA_SS                       0x2C  // Sub System Identifiers\r
+#define B_PCH_SATA_SS_SSID                  0xFFFF0000 // Subsystem ID\r
+#define B_PCH_SATA_SS_SSVID                 0x0000FFFF // Subsystem Vendor ID\r
+\r
+#define R_PCH_SATA_AHCI_CAP_PTR             0x34  // Capabilities Pointer (8 bits)\r
+#define B_PCH_SATA_AHCI_CAP_PTR             0xFF\r
+\r
+#define R_PCH_SATA_INTR                     0x3C  // Interrupt Information\r
+#define B_PCH_SATA_INTR_IPIN                0xFFFF0000 // Interrupt Pin\r
+#define B_PCH_SATA_INTR_ILINE               0x0000FFFF // Interrupt Line\r
+\r
+#define R_PCH_SATA_PMCS                     0x74  // PCI Power Management Control and Status\r
+#define B_PCH_SATA_PMCS_PMES                BIT15 // PME Status\r
+#define B_PCH_SATA_PMCS_PMEE                BIT8  // PME Enable\r
+#define B_PCH_SATA_PMCS_NSFRST              BIT3  // No Soft Reset\r
+#define V_PCH_SATA_PMCS_NSFRST_1            0x01\r
+#define V_PCH_SATA_PMCS_NSFRST_0            0x00\r
+#define B_PCH_SATA_PMCS_PS                  (BIT1 | BIT0) // Power State\r
+#define V_PCH_SATA_PMCS_PS_3                0x03\r
+#define V_PCH_SATA_PMCS_PS_0                0x00\r
+\r
+#define R_PCH_SATA_MAP                      0x90  // Port Mapping Register\r
+#define B_PCH_SATA_MAP_SPD                  (BIT14 | BIT13 | BIT12 | BIT11 | BIT10 | BIT9 | BIT8) // SATA Port Disable\r
+#define B_PCH_SATA_PORT6_DISABLED           BIT14\r
+#define B_PCH_SATA_PORT5_DISABLED           BIT13\r
+#define B_PCH_SATA_PORT4_DISABLED           BIT12\r
+#define B_PCH_SATA_PORT3_DISABLED           BIT11\r
+#define B_PCH_SATA_PORT2_DISABLED           BIT10\r
+#define B_PCH_SATA_PORT1_DISABLED           BIT9\r
+#define B_PCH_SATA_PORT0_DISABLED           BIT8\r
+#define B_PCH_SATA_MAP_SMS_MASK             (BIT7 | BIT6) // SATA Mode Select\r
+#define V_PCH_SATA_MAP_SMS_IDE              0x00\r
+#define V_PCH_SATA_MAP_SMS_AHCI             0x40\r
+#define V_PCH_SATA_MAP_SMS_RAID             0x80\r
+#define B_PCH_SATA_PORT_TO_CONTROLLER_CFG   BIT5  // SATA Port-to-Controller Configuration\r
+\r
+#define R_PCH_SATA_PCS                      0x92  // Port Control and Status\r
+#define S_PCH_SATA_PCS                      0x2\r
+#define B_PCH_SATA_PCS_OOB_RETRY            BIT15 // OOB Retry Mode\r
+#define B_PCH_SATA_PCS_PORT6_DET            BIT14 // Port 6 Present\r
+#define B_PCH_SATA_PCS_PORT5_DET            BIT13 // Port 5 Present\r
+#define B_PCH_SATA_PCS_PORT4_DET            BIT12 // Port 4 Present\r
+#define B_PCH_SATA_PCS_PORT3_DET            BIT11 // Port 3 Present\r
+#define B_PCH_SATA_PCS_PORT2_DET            BIT10 // Port 2 Present\r
+#define B_PCH_SATA_PCS_PORT1_DET            BIT9  // Port 1 Present\r
+#define B_PCH_SATA_PCS_PORT0_DET            BIT8  // Port 0 Present\r
+#define B_PCH_SATA_PCS_PORT5_EN             BIT5  // Port 5 Enabled\r
+#define B_PCH_SATA_PCS_PORT4_EN             BIT4  // Port 4 Enabled\r
+#define B_PCH_SATA_PCS_PORT3_EN             BIT3  // Port 3 Enabled\r
+#define B_PCH_SATA_PCS_PORT2_EN             BIT2  // Port 2 Enabled\r
+#define B_PCH_SATA_PCS_PORT1_EN             BIT1  // Port 1 Enabled\r
+#define B_PCH_SATA_PCS_PORT0_EN             BIT0  // Port 0 Enabled\r
+\r
+#define R_PCH_SATA_AHCI_PI                  0x0C  // Ports Implemented\r
+#define B_PCH_SATA_PORT_MASK                0x3F\r
+#define B_PCH_SATA_PORT5_IMPLEMENTED        BIT5  // Port 5 Implemented\r
+#define B_PCH_SATA_PORT4_IMPLEMENTED        BIT4  // Port 4 Implemented\r
+#define B_PCH_SATA_PORT3_IMPLEMENTED        BIT3  // Port 3 Implemented\r
+#define B_PCH_SATA_PORT2_IMPLEMENTED        BIT2  // Port 2 Implemented\r
+#define B_PCH_SATA_PORT1_IMPLEMENTED        BIT1  // Port 1 Implemented\r
+#define B_PCH_SATA_PORT0_IMPLEMENTED        BIT0  // Port 0 Implemented\r
+\r
+#define R_PCH_SATA_AHCI_P0SSTS              0x128 // Port 0 Serial ATA Status\r
+#define R_PCH_SATA_AHCI_P1SSTS              0x1A8 // Port 1 Serial ATA Status\r
+#define B_PCH_SATA_AHCI_PXSSTS_IPM          0x00000F00 // Interface Power Management\r
+#define B_PCH_SATA_AHCI_PXSSTS_IPM_0        0x00000000\r
+#define B_PCH_SATA_AHCI_PXSSTS_IPM_1        0x00000100\r
+#define B_PCH_SATA_AHCI_PXSSTS_IPM_2        0x00000200\r
+#define B_PCH_SATA_AHCI_PXSSTS_IPM_6        0x00000600\r
+#define B_PCH_SATA_AHCI_PXSSTS_SPD          0x000000F0 // Current Interface Speed\r
+#define B_PCH_SATA_AHCI_PXSSTS_SPD_0        0x00000000\r
+#define B_PCH_SATA_AHCI_PXSSTS_SPD_1        0x00000010\r
+#define B_PCH_SATA_AHCI_PXSSTS_SPD_2        0x00000020\r
+#define B_PCH_SATA_AHCI_PXSSTS_SPD_3        0x00000030\r
+#define B_PCH_SATA_AHCI_PXSSTS_DET          0x0000000F // Device Detection\r
+#define B_PCH_SATA_AHCI_PXSSTS_DET_0        0x00000000\r
+#define B_PCH_SATA_AHCI_PXSSTS_DET_1        0x00000001\r
+#define B_PCH_SATA_AHCI_PXSSTS_DET_3        0x00000003\r
+#define B_PCH_SATA_AHCI_PXSSTS_DET_4        0x00000004\r
+\r
+//\r
+// Macros of VLV capabilities for SATA controller which are used by SATA controller driver\r
+//\r
+//\r
+//\r
+// Define the individual capabilities of each SATA controller\r
+//\r
+#define PCH_SATA_MAX_CONTROLLERS            1     // Max SATA controllers number supported\r
+#define PCH_SATA_MAX_DEVICES                2     // Max SATA devices number of single SATA channel\r
+#define PCH_IDE_MAX_CHANNELS                2     // Max IDE channels number of single SATA controller\r
+#define PCH_IDE_MAX_DEVICES                 2     // Max IDE devices number of single SATA channel\r
+#define PCH_AHCI_MAX_PORTS                  2     // Max number of SATA ports in VLV\r
+#define PCH_IDE_MAX_PORTS                   2     // Max number of IDE ports in VLV\r
+\r
+//\r
+// GPIOS_14 SATA0GP is the SATA port 0 reset pin.\r
+//\r
+#define PCH_GPIO_SATA_PORT0_RESET           14\r
+//\r
+// GPIOS_15 SATA1GP is the SATA port 1 reset pin.\r
+//\r
+#define PCH_GPIO_SATA_PORT1_RESET           15\r
+\r
+#endif\r

diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/PchRegsScc.h b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/PchRegsScc.h
new file mode 100644 (file)
index 0000000..7b1af9c
--- /dev/null
+++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/PchRegsScc.h
@@ -0,0 +1,59 @@
+/*++\r
+\r
+Copyright (c) 2012  - 2014, Intel Corporation. All rights reserved\r
+\r
+  This program and the accompanying materials are licensed and made available under\r
+  the terms and conditions of the BSD License that accompanies this distribution.\r
+  The full text of the license may be found at\r
+  http://opensource.org/licenses/bsd-license.php.\r
+\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+\r
+Module Name:\r
+\r
+  PchRegsScc.h\r
+\r
+Abstract:\r
+\r
+  Register names for VLV SCC module.\r
+\r
+  Conventions:\r
+\r
+  - Prefixes:\r
+    Definitions beginning with "R_" are registers\r
+    Definitions beginning with "B_" are bits within registers\r
+    Definitions beginning with "V_" are meaningful values of bits within the registers\r
+    Definitions beginning with "S_" are register sizes\r
+    Definitions beginning with "N_" are the bit position\r
+  - In general, PCH registers are denoted by "_PCH_" in register names\r
+  - Registers / bits that are different between PCH generations are denoted by\r
+    "_PCH_<generation_name>_" in register/bit names. e.g., "_PCH_VLV_"\r
+  - Registers / bits that are different between SKUs are denoted by "_<SKU_name>"\r
+    at the end of the register/bit names\r
+  - Registers / bits of new devices introduced in a PCH generation will be just named\r
+    as "_PCH_" without <generation_name> inserted.\r
+\r
+--*/\r
+#ifndef _PCH_REGS_SCC_H_\r
+#define _PCH_REGS_SCC_H_\r
+\r
+\r
+//\r
+// SCC Modules Registers\r
+//\r
+\r
+//\r
+// SCC SDIO Modules\r
+// PCI Config Space Registers\r
+//\r
+#define PCI_DEVICE_NUMBER_PCH_SCC_SDIO_0         16\r
+#define PCI_DEVICE_NUMBER_PCH_SCC_SDIO_1         17\r
+#define PCI_DEVICE_NUMBER_PCH_SCC_SDIO_2         18\r
+#define PCI_DEVICE_NUMBER_PCH_SCC_SDIO_3         23\r
+\r
+#define PCI_FUNCTION_NUMBER_PCH_SCC_SDIO         0\r
+\r
+#endif\r

diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/PchRegsSmbus.h b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/PchRegsSmbus.h
new file mode 100644 (file)
index 0000000..075974a
--- /dev/null
+++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/PchRegsSmbus.h
@@ -0,0 +1,155 @@
+/**\r
+\r
+Copyright (c) 2011  - 2014, Intel Corporation. All rights reserved\r
+\r
+  This program and the accompanying materials are licensed and made available under\r
+  the terms and conditions of the BSD License that accompanies this distribution.\r
+  The full text of the license may be found at\r
+  http://opensource.org/licenses/bsd-license.php.\r
+\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+\r
+  @file\r
+  PchRegsSmbus.h\r
+\r
+  @brief\r
+  Register names for VLV Smbus Device.\r
+\r
+  Conventions:\r
+\r
+  - Prefixes:\r
+    Definitions beginning with "R_" are registers\r
+    Definitions beginning with "B_" are bits within registers\r
+    Definitions beginning with "V_" are meaningful values of bits within the registers\r
+    Definitions beginning with "S_" are register sizes\r
+    Definitions beginning with "N_" are the bit position\r
+  - In general, PCH registers are denoted by "_PCH_" in register names\r
+  - Registers / bits that are different between PCH generations are denoted by\r
+    "_PCH_<generation_name>_" in register/bit names. e.g., "_PCH_VLV_"\r
+  - Registers / bits that are different between SKUs are denoted by "_<SKU_name>"\r
+    at the end of the register/bit names\r
+  - Registers / bits of new devices introduced in a PCH generation will be just named\r
+    as "_PCH_" without <generation_name> inserted.\r
+\r
+**/\r
+#ifndef _PCH_REGS_SMBUS_H_\r
+#define _PCH_REGS_SMBUS_H_\r
+\r
+///\r
+/// SMBus Controller Registers (D31:F3)\r
+///\r
+#define PCI_DEVICE_NUMBER_PCH_SMBUS        31\r
+#define PCI_FUNCTION_NUMBER_PCH_SMBUS      3\r
+\r
+#define R_PCH_SMBUS_VENDOR_ID              0x00  // Vendor ID\r
+#define V_PCH_SMBUS_VENDOR_ID              V_PCH_INTEL_VENDOR_ID // Intel Vendor ID\r
+\r
+#define R_PCH_SMBUS_DEVICE_ID              0x02  // Device ID\r
+#define V_PCH_SMBUS_DEVICE_ID              0x0F12\r
+\r
+#define R_PCH_SMBUS_PCICMD                 0x04  // CMD register enables/disables, Memory/IO space access and interrupt\r
+#define B_PCH_SMBUS_PCICMD_INTR_DIS        BIT10 // Interrupt Disable\r
+#define B_PCH_SMBUS_PCICMD_FBE             BIT9  // FBE - reserved as '0'\r
+#define B_PCH_SMBUS_PCICMD_SERR_EN         BIT8  // SERR Enable - reserved as '0'\r
+#define B_PCH_SMBUS_PCICMD_WCC             BIT7  // Wait Cycle Control - reserved as '0'\r
+#define B_PCH_SMBUS_PCICMD_PER             BIT6  // Parity Error - reserved as '0'\r
+#define B_PCH_SMBUS_PCICMD_VPS             BIT5  // VGA Palette Snoop - reserved as '0'\r
+#define B_PCH_SMBUS_PCICMD_PMWE            BIT4  // Postable Memory Write Enable - reserved as '0'\r
+#define B_PCH_SMBUS_PCICMD_SCE             BIT3  // Special Cycle Enable - reserved as '0'\r
+#define B_PCH_SMBUS_PCICMD_BME             BIT2  // Bus Master Enable - reserved as '0'\r
+#define B_PCH_SMBUS_PCICMD_MSE             BIT1  // Memory Space Enable\r
+#define B_PCH_SMBUS_PCICMD_IOSE            BIT0  // I/O Space Enable\r
+\r
+#define R_PCH_SMBUS_BASE                   0x20  // The I/O memory bar\r
+#define B_PCH_SMBUS_BASE_BAR               0x0000FFE0 // Base Address\r
+#define B_PCH_SMBUS_BASE_IOSI              BIT0  // IO Space Indicator\r
+\r
+#define R_PCH_SMBUS_SVID                   0x2C  // Subsystem Vendor ID\r
+#define B_PCH_SMBUS_SVID                   0xFFFF // Subsystem Vendor ID\r
+\r
+//\r
+// SMBus I/O Registers\r
+//\r
+#define R_PCH_SMBUS_HSTS                   0x00  // Host Status Register R/W\r
+#define B_PCH_SMBUS_HSTS_ALL               0xFF\r
+#define B_PCH_SMBUS_BYTE_DONE_STS          BIT7  // Byte Done Status\r
+#define B_PCH_SMBUS_IUS                    BIT6  // In Use Status\r
+#define B_PCH_SMBUS_SMBALERT_STS           BIT5  // SMBUS Alert\r
+#define B_PCH_SMBUS_FAIL                   BIT4  // Failed\r
+#define B_PCH_SMBUS_BERR                   BIT3  // Bus Error\r
+#define B_PCH_SMBUS_DERR                   BIT2  // Device Error\r
+#define B_PCH_SMBUS_ERRORS                 (B_PCH_SMBUS_FAIL | B_PCH_SMBUS_BERR | B_PCH_SMBUS_DERR)\r
+#define B_PCH_SMBUS_INTR                   BIT1  // Interrupt\r
+#define B_PCH_SMBUS_HBSY                   BIT0  // Host Busy\r
+\r
+#define R_PCH_SMBUS_HCTL                   0x02  // Host Control Register R/W\r
+#define B_PCH_SMBUS_PEC_EN                 BIT7  // Packet Error Checking Enable\r
+#define B_PCH_SMBUS_START                  BIT6  // Start\r
+#define B_PCH_SMBUS_LAST_BYTE              BIT5  // Last Byte\r
+#define B_PCH_SMBUS_SMB_CMD                0x1C  // SMB Command\r
+#define V_PCH_SMBUS_SMB_CMD_BLOCK_PROCESS  0x1C  // Block Process\r
+#define V_PCH_SMBUS_SMB_CMD_IIC_READ       0x18  // I2C Read\r
+#define V_PCH_SMBUS_SMB_CMD_BLOCK          0x14  // Block\r
+#define V_PCH_SMBUS_SMB_CMD_PROCESS_CALL   0x10  // Process Call\r
+#define V_PCH_SMBUS_SMB_CMD_WORD_DATA      0x0C  // Word Data\r
+#define V_PCH_SMBUS_SMB_CMD_BYTE_DATA      0x08  // Byte Data\r
+#define V_PCH_SMBUS_SMB_CMD_BYTE           0x04  // Byte\r
+#define V_PCH_SMBUS_SMB_CMD_QUICK          0x00  // Quick\r
+#define B_PCH_SMBUS_KILL                   BIT1  // Kill\r
+#define B_PCH_SMBUS_INTREN                 BIT0  // Interrupt Enable\r
+\r
+#define R_PCH_SMBUS_HCMD                   0x03  // Host Command Register R/W\r
+#define B_PCH_SMBUS_HCMD                   0xFF  // Command to be transmitted\r
+\r
+#define R_PCH_SMBUS_TSA                    0x04  // Transmit Slave Address Register R/W\r
+#define B_PCH_SMBUS_ADDRESS                0xFE  // 7-bit address of the targeted slave\r
+#define B_PCH_SMBUS_RW_SEL                 BIT0  // Direction of the host transfer, 1 = read, 0 = write\r
+#define B_PCH_SMBUS_RW_SEL_READ            0x01  // Read\r
+#define B_PCH_SMBUS_RW_SEL_WRITE           0x00  // Write\r
+//\r
+#define R_PCH_SMBUS_HD0                    0x05  // Data 0 Register R/W\r
+#define R_PCH_SMBUS_HD1                    0x06  // Data 1 Register R/W\r
+#define R_PCH_SMBUS_HBD                    0x07  // Host Block Data Register R/W\r
+#define R_PCH_SMBUS_PEC                    0x08  // Packet Error Check Data Register R/W\r
+\r
+#define R_PCH_SMBUS_RSA                    0x09  // Receive Slave Address Register R/W\r
+#define B_PCH_SMBUS_SLAVE_ADDR             0x7F  // TCO slave address (Not used, reserved)\r
+\r
+#define R_PCH_SMBUS_SD                     0x0A  // Receive Slave Data Register R/W\r
+\r
+#define R_PCH_SMBUS_AUXS                   0x0C  // Auxiliary Status Register R/WC\r
+#define B_PCH_SMBUS_CRCE                   BIT0  // CRC Error\r
+//\r
+#define R_PCH_SMBUS_AUXC                   0x0D  // Auxiliary Control Register R/W\r
+#define B_PCH_SMBUS_E32B                   BIT1  // Enable 32-byte Buffer\r
+#define B_PCH_SMBUS_AAC                    BIT0  // Automatically Append CRC\r
+\r
+#define R_PCH_SMBUS_SMLC                   0x0E  // SMLINK Pin Control Register R/W\r
+#define B_PCH_SMBUS_SMLINK_CLK_CTL         BIT2  // Not supported\r
+#define B_PCH_SMBUS_SMLINK1_CUR_STS        BIT1  // Not supported\r
+#define B_PCH_SMBUS_SMLINK0_CUR_STS        BIT0  // Not supported\r
+\r
+\r
+#define R_PCH_SMBUS_SMBC                   0x0F  // SMBus Pin Control Register R/W\r
+#define B_PCH_SMBUS_SMBCLK_CTL             BIT2  // SMBCLK Control\r
+#define B_PCH_SMBUS_SMBDATA_CUR_STS        BIT1  // SMBDATA Current Status\r
+#define B_PCH_SMBUS_SMBCLK_CUR_STS         BIT0  // SMBCLK Current Status\r
+\r
+#define R_PCH_SMBUS_SSTS                   0x10  // Slave Status Register R/WC\r
+#define B_PCH_SMBUS_HOST_NOTIFY_STS        BIT0  // Host Notify Status\r
+\r
+#define R_PCH_SMBUS_SCMD                   0x11  // Slave Command Register R/W\r
+#define B_PCH_SMBUS_SMBALERT_DIS           BIT2  // Not supported\r
+#define B_PCH_SMBUS_HOST_NOTIFY_WKEN       BIT1  // Host Notify Wake Enable\r
+#define B_PCH_SMBUS_HOST_NOTIFY_INTREN     BIT0  // Host Notify Interrupt Enable\r
+\r
+#define R_PCH_SMBUS_NDA                    0x14  // Notify Device Address Register RO\r
+#define B_PCH_SMBUS_DEVICE_ADDRESS         0xFE  // Device Address\r
+\r
+#define R_PCH_SMBUS_NDLB                   0x16  // Notify Data Low Byte Register RO\r
+#define R_PCH_SMBUS_NDHB                   0x17  // Notify Data High Byte Register RO\r
+\r
+#endif\r

diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/PchRegsSpi.h b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/PchRegsSpi.h
new file mode 100644 (file)
index 0000000..132c64b
--- /dev/null
+++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/PchRegsSpi.h
@@ -0,0 +1,119 @@
+/**\r
+\r
+Copyright (c) 2011  - 2014, Intel Corporation. All rights reserved\r
+\r
+  This program and the accompanying materials are licensed and made available under\r
+  the terms and conditions of the BSD License that accompanies this distribution.\r
+  The full text of the license may be found at\r
+  http://opensource.org/licenses/bsd-license.php.\r
+\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+\r
+  @file\r
+  PchRegsSpi.h\r
+\r
+  @brief\r
+  Register names for PCH SPI device.\r
+\r
+  Conventions:\r
+\r
+  - Prefixes:\r
+    Definitions beginning with "R_" are registers\r
+    Definitions beginning with "B_" are bits within registers\r
+    Definitions beginning with "V_" are meaningful values of bits within the registers\r
+    Definitions beginning with "S_" are register sizes\r
+    Definitions beginning with "N_" are the bit position\r
+  - In general, PCH registers are denoted by "_PCH_" in register names\r
+  - Registers / bits that are different between PCH generations are denoted by\r
+    "_PCH_<generation_name>_" in register/bit names. e.g., "_PCH_VLV_"\r
+  - Registers / bits that are different between SKUs are denoted by "_<SKU_name>"\r
+    at the end of the register/bit names\r
+  - Registers / bits of new devices introduced in a PCH generation will be just named\r
+    as "_PCH_" without <generation_name> inserted.\r
+\r
+**/\r
+#ifndef _PCH_REGS_SPI_H_\r
+#define _PCH_REGS_SPI_H_\r
+\r
+///\r
+/// SPI Host Interface Registers\r
+///\r
+\r
+#define R_PCH_SPI_HSFS                       0x04  // Hardware Sequencing Flash Status Register (16bits)\r
+#define B_PCH_SPI_HSFS_FLOCKDN               BIT15 // Flash Configuration Lock-Down\r
+#define B_PCH_SPI_HSFS_FDV                   BIT14 // Flash Descriptor Valid\r
+#define B_PCH_SPI_HSFS_FDOPSS                BIT13 // Flash Descriptor Override Pin-Strap Status\r
+#define B_PCH_SPI_HSFS_SCIP                  BIT5  // SPI Cycle in Progress\r
+#define B_PCH_SPI_HSFS_BERASE_MASK           (BIT4 | BIT3) // Block / Sector Erase Size\r
+#define V_PCH_SPI_HSFS_BERASE_256B           0x00  // Block/Sector = 256 Bytes\r
+#define V_PCH_SPI_HSFS_BERASE_4K             0x01  // Block/Sector = 4K Bytes\r
+#define V_PCH_SPI_HSFS_BERASE_8K             0x10  // Block/Sector = 8K Bytes\r
+#define V_PCH_SPI_HSFS_BERASE_64K            0x11  // Block/Sector = 64K Bytes\r
+#define B_PCH_SPI_HSFS_AEL                   BIT2  // Access Error Log\r
+#define B_PCH_SPI_HSFS_FCERR                 BIT1  // Flash Cycle Error\r
+#define B_PCH_SPI_HSFS_FDONE                 BIT0  // Flash Cycle Done\r
+\r
+#define R_PCH_SPI_PR0                        0x74  // Protected Region 0 Register\r
+#define B_PCH_SPI_PR0_WPE                    BIT31 // Write Protection Enable\r
+#define B_PCH_SPI_PR0_PRL_MASK               0x1FFF0000 // Protected Range Limit Mask, [28:16] here represents upper limit of address [24:12]\r
+#define B_PCH_SPI_PR0_RPE                    BIT15 // Read Protection Enable\r
+#define B_PCH_SPI_PR0_PRB_MASK               0x00001FFF // Protected Range Base Mask, [12:0] here represents base limit of address [24:12]\r
+\r
+#define R_PCH_SPI_PREOP                      0x94  // Prefix Opcode Configuration Register (16 bits)\r
+#define B_PCH_SPI_PREOP1_MASK                0xFF00 // Prefix Opcode 1 Mask\r
+#define B_PCH_SPI_PREOP0_MASK                0x00FF // Prefix Opcode 0 Mask\r
+\r
+#define R_PCH_SPI_OPTYPE                     0x96  // Opcode Type Configuration\r
+#define B_PCH_SPI_OPTYPE7_MASK               (BIT15 | BIT14) // Opcode Type 7 Mask\r
+#define B_PCH_SPI_OPTYPE6_MASK               (BIT13 | BIT12) // Opcode Type 6 Mask\r
+#define B_PCH_SPI_OPTYPE5_MASK               (BIT11 | BIT10) // Opcode Type 5 Mask\r
+#define B_PCH_SPI_OPTYPE4_MASK               (BIT9 | BIT8) // Opcode Type 4 Mask\r
+#define B_PCH_SPI_OPTYPE3_MASK               (BIT7 | BIT6) // Opcode Type 3 Mask\r
+#define B_PCH_SPI_OPTYPE2_MASK               (BIT5 | BIT4) // Opcode Type 2 Mask\r
+#define B_PCH_SPI_OPTYPE1_MASK               (BIT3 | BIT2) // Opcode Type 1 Mask\r
+#define B_PCH_SPI_OPTYPE0_MASK               (BIT1 | BIT0) // Opcode Type 0 Mask\r
+#define V_PCH_SPI_OPTYPE_RDNOADDR            0x00  // Read cycle type without address\r
+#define V_PCH_SPI_OPTYPE_WRNOADDR            0x01  // Write cycle type without address\r
+#define V_PCH_SPI_OPTYPE_RDADDR              0x02  // Address required; Read cycle type\r
+#define V_PCH_SPI_OPTYPE_WRADDR              0x03  // Address required; Write cycle type\r
+\r
+#define R_PCH_SPI_OPMENU0                    0x98  // Opcode Menu Configuration 0 (32bits)\r
+#define R_PCH_SPI_OPMENU1                    0x9C  // Opcode Menu Configuration 1 (32bits)\r
+\r
+#define R_PCH_SPI_IND_LOCK                   0xA4  // Indvidual Lock\r
+#define B_PCH_SPI_IND_LOCK_PR0               BIT2  // PR0 LockDown\r
+\r
+\r
+#define R_PCH_SPI_FDOC                       0xB0  // Flash Descriptor Observability Control Register (32 bits)\r
+#define B_PCH_SPI_FDOC_FDSS_MASK             (BIT14 | BIT13 | BIT12) // Flash Descriptor Section Select\r
+#define V_PCH_SPI_FDOC_FDSS_FSDM             0x0000 // Flash Signature and Descriptor Map\r
+#define V_PCH_SPI_FDOC_FDSS_COMP             0x1000 // Component\r
+#define V_PCH_SPI_FDOC_FDSS_REGN             0x2000 // Region\r
+#define V_PCH_SPI_FDOC_FDSS_MSTR             0x3000 // Master\r
+#define V_PCH_SPI_FDOC_FDSS_VLVS             0x4000 // Soft Straps\r
+#define B_PCH_SPI_FDOC_FDSI_MASK             0x0FFC // Flash Descriptor Section Index\r
+\r
+#define R_PCH_SPI_FDOD                       0xB4  // Flash Descriptor Observability Data Register (32 bits)\r
+\r
+#define R_PCH_SPI_BCR                        0xFC  // BIOS Control Register\r
+#define S_PCH_SPI_BCR                        1\r
+#define B_PCH_SPI_BCR_SMM_BWP                BIT5  // SMM BIOS Write Protect Disable\r
+#define B_PCH_SPI_BCR_SRC                    (BIT3 | BIT2) // SPI Read Configuration (SRC)\r
+#define V_PCH_SPI_BCR_SRC_PREF_EN_CACHE_EN   0x08  // Prefetch Enable, Cache Enable\r
+#define V_PCH_SPI_BCR_SRC_PREF_DIS_CACHE_DIS 0x04  // Prefetch Disable, Cache Disable\r
+#define V_PCH_SPI_BCR_SRC_PREF_DIS_CACHE_EN  0x00  // Prefetch Disable, Cache Enable\r
+#define B_PCH_SPI_BCR_BLE                    BIT1  // Lock Enable (LE)\r
+#define B_PCH_SPI_BCR_BIOSWE                 BIT0  // Write Protect Disable (WPD)\r
+#define N_PCH_SPI_BCR_BLE                    1\r
+#define N_PCH_SPI_BCR_BIOSWE                 0\r
+\r
+//\r
+// Flash Descriptor Base Address Region (FDBAR) from Flash Region 0\r
+//\r
+#define R_PCH_SPI_FDBAR_FLVALSIG             0x00  // Flash Valid Signature\r
+#define V_PCH_SPI_FDBAR_FLVALSIG             0x0FF0A55A\r
+\r
+#endif\r

diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/PchRegsUsb.h b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/PchRegsUsb.h
new file mode 100644 (file)
index 0000000..ccc41a5
--- /dev/null
+++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/PchRegsUsb.h
@@ -0,0 +1,98 @@
+/**\r
+\r
+Copyright (c) 2012  - 2014, Intel Corporation. All rights reserved\r
+\r
+  This program and the accompanying materials are licensed and made available under\r
+  the terms and conditions of the BSD License that accompanies this distribution.\r
+  The full text of the license may be found at\r
+  http://opensource.org/licenses/bsd-license.php.\r
+\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+\r
+  @file\r
+  PchRegsUsb.h\r
+\r
+  @brief\r
+  Register names for PCH USB devices.\r
+\r
+  Conventions:\r
+\r
+  - Prefixes:\r
+    Definitions beginning with "R_" are registers\r
+    Definitions beginning with "B_" are bits within registers\r
+    Definitions beginning with "V_" are meaningful values of bits within the registers\r
+    Definitions beginning with "S_" are register sizes\r
+    Definitions beginning with "N_" are the bit position\r
+  - In general, PCH registers are denoted by "_PCH_" in register names\r
+  - Registers / bits that are different between PCH generations are denoted by\r
+    "_PCH_<generation_name>_" in register/bit names. e.g., "_PCH_VLV_"\r
+  - Registers / bits that are different between SKUs are denoted by "_<SKU_name>"\r
+    at the end of the register/bit names\r
+  - Registers / bits of new devices introduced in a PCH generation will be just named\r
+    as "_PCH_" without <generation_name> inserted.\r
+\r
+**/\r
+#ifndef _PCH_REGS_USB_H_\r
+#define _PCH_REGS_USB_H_\r
+\r
+///\r
+/// USB Definitions\r
+///\r
+\r
+typedef enum {\r
+  PchEhci1 = 0,\r
+  PchEhciControllerMax\r
+} PCH_USB20_CONTROLLER_TYPE;\r
+\r
+#define PCH_USB_MAX_PHYSICAL_PORTS          4      /// Max Physical Connector EHCI + XHCI, not counting virtual ports like USB-R.\r
+#define PCH_EHCI_MAX_PORTS                  4      /// Counting ports behind RMHs 8 from EHCI-1 and 6 from EHCI-2, not counting EHCI USB-R virtual ports.\r
+#define PCH_HSIC_MAX_PORTS                  2\r
+#define PCH_XHCI_MAX_USB3_PORTS             1\r
+\r
+#define PCI_DEVICE_NUMBER_PCH_USB           29\r
+#define PCI_FUNCTION_NUMBER_PCH_EHCI        0\r
+\r
+#define R_PCH_USB_VENDOR_ID                 0x00  // Vendor ID\r
+#define V_PCH_USB_VENDOR_ID                 V_PCH_INTEL_VENDOR_ID\r
+\r
+#define R_PCH_USB_DEVICE_ID                 0x02  // Device ID\r
+#define V_PCH_USB_DEVICE_ID_0               0x0F34  // EHCI#1\r
+\r
+#define R_PCH_EHCI_SVID                     0x2C  // USB2 Subsystem Vendor ID\r
+#define B_PCH_EHCI_SVID                     0xFFFF // USB2 Subsystem Vendor ID Mask\r
+\r
+#define R_PCH_EHCI_PWR_CNTL_STS             0x54  // Power Management Control / Status\r
+#define B_PCH_EHCI_PWR_CNTL_STS_PME_STS     BIT15 // PME Status\r
+#define B_PCH_EHCI_PWR_CNTL_STS_DATASCL     (BIT14 | BIT13) // Data Scale\r
+#define B_PCH_EHCI_PWR_CNTL_STS_DATASEL     (BIT12 | BIT11 | BIT10 | BIT9) // Data Select\r
+#define B_PCH_EHCI_PWR_CNTL_STS_PME_EN      BIT8  // Power Enable\r
+#define B_PCH_EHCI_PWR_CNTL_STS_PWR_STS     (BIT1 | BIT0) // Power State\r
+#define V_PCH_EHCI_PWR_CNTL_STS_PWR_STS_D0  0     // D0 State\r
+#define V_PCH_EHCI_PWR_CNTL_STS_PWR_STS_D3  (BIT1 | BIT0) // D3 Hot State\r
+\r
+///\r
+/// USB3 (XHCI) related definitions\r
+///\r
+#define PCI_DEVICE_NUMBER_PCH_XHCI          20\r
+#define PCI_FUNCTION_NUMBER_PCH_XHCI        0\r
+//\r
+/////\r
+///// XHCI PCI Config Space registers\r
+/////\r
+\r
+#define R_PCH_XHCI_SVID                     0x2C\r
+#define B_PCH_XHCI_SVID                     0xFFFF\r
+\r
+\r
+#define R_PCH_XHCI_PWR_CNTL_STS             0x74\r
+#define B_PCH_XHCI_PWR_CNTL_STS_PME_STS     BIT15\r
+#define B_PCH_XHCI_PWR_CNTL_STS_DATASCL     (BIT14 | BIT13)\r
+#define B_PCH_XHCI_PWR_CNTL_STS_DATASEL     (BIT12 | BIT11 | BIT10 | BIT9)\r
+#define B_PCH_XHCI_PWR_CNTL_STS_PME_EN      BIT8\r
+#define B_PCH_XHCI_PWR_CNTL_STS_PWR_STS     (BIT1 | BIT0)\r
+#define V_PCH_XHCI_PWR_CNTL_STS_PWR_STS_D3  (BIT1 | BIT0)\r
+\r
+#endif\r

diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Ppi/PchInit.h b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Ppi/PchInit.h
new file mode 100644 (file)
index 0000000..3e90a12
--- /dev/null
+++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Ppi/PchInit.h
@@ -0,0 +1,81 @@
+/**\r
+**/\r
+/**\r
+\r
+Copyright (c) 2012  - 2014, Intel Corporation. All rights reserved\r
+\r
+  This program and the accompanying materials are licensed and made available under\r
+  the terms and conditions of the BSD License that accompanies this distribution.\r
+  The full text of the license may be found at\r
+  http://opensource.org/licenses/bsd-license.php.\r
+\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+\r
+  @file\r
+  PchInit.h\r
+\r
+  @brief\r
+  This file defines the PCH Init PPI\r
+\r
+**/\r
+#ifndef _PCH_INIT_H_\r
+#define _PCH_INIT_H_\r
+\r
+//\r
+// Define the PCH Init PPI GUID\r
+//\r
+\r
+\r
+#include <Protocol/PchPlatformPolicy.h>\r
+#define PCH_INIT_PPI_GUID \\r
+  { \\r
+    0x9ea894a, 0xbe0d, 0x4230, 0xa0, 0x3, 0xed, 0xc6, 0x93, 0xb4, 0x8e, 0x95 \\r
+  }\r
+extern EFI_GUID               gPchInitPpiGuid;\r
+\r
+///\r
+/// Forward reference for ANSI C compatibility\r
+///\r
+typedef struct _PCH_INIT_PPI  PCH_INIT_PPI;\r
+\r
+///\r
+/// Data structure definitions\r
+///\r
+typedef enum _CPU_STRAP_OPERATION {\r
+  GetCpuStrapSetData,\r
+  SetCpuStrapSetData,\r
+  LockCpuStrapSetData\r
+} CPU_STRAP_OPERATION;\r
+\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *PCH_USB_INIT) (\r
+  IN  EFI_PEI_SERVICES            **PeiServices\r
+  )\r
+/**\r
+\r
+  @brief\r
+  The function performing USB init in PEI phase. This could be used by USB recovery\r
+  or debug features that need USB initialization during PEI phase.\r
+  Note: Before executing this function, please be sure that PCH_INIT_PPI.Initialize\r
+  has been done and PchUsbPolicyPpi has been installed.\r
+\r
+  @param[in] PeiServices    General purpose services available to every PEIM\r
+\r
+  @retval EFI_SUCCESS       The function completed successfully\r
+  @retval Others            All other error conditions encountered result in an ASSERT.\r
+\r
+**/\r
+;\r
+\r
+///\r
+/// PCH_INIT_PPI Structure Definition\r
+///\r
+struct _PCH_INIT_PPI {\r
+  PCH_USB_INIT          UsbInit;\r
+};\r
+\r
+#endif\r

diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Ppi/PchPeiInit.h b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Ppi/PchPeiInit.h
new file mode 100644 (file)
index 0000000..81995cf
--- /dev/null
+++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Ppi/PchPeiInit.h
@@ -0,0 +1,40 @@
+\r
+/*++\r
+\r
+Copyright (c)  2013  - 2014, Intel Corporation. All rights reserved\r
+\r
+  This program and the accompanying materials are licensed and made available under\r
+  the terms and conditions of the BSD License that accompanies this distribution.\r
+  The full text of the license may be found at\r
+  http://opensource.org/licenses/bsd-license.php.\r
+\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+Module Name:\r
+\r
+  PchPeiInit.h\r
+\r
+Abstract:\r
+\r
+\r
+--*/\r
+\r
+#ifndef _PCH_PEI_INIT_H_\r
+#define _PCH_PEI_INIT_H_\r
+\r
+//\r
+// Define the PCH PEI Init PPI GUID\r
+//\r
+#define PCH_PEI_INIT_PPI_GUID \\r
+  { \\r
+    0xACB93B08, 0x5CDC, 0x4A8F, 0x93, 0xD4, 0x6, 0xE3, 0x42, 0xDF, 0x18, 0x2E \\r
+  }\r
+\r
+//\r
+// Extern the GUID for PPI users.\r
+//\r
+extern EFI_GUID     gPchPeiInitPpiGuid;\r
+\r
+#endif\r

diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Ppi/PchPlatformPolicy.h b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Ppi/PchPlatformPolicy.h
new file mode 100644 (file)
index 0000000..f2f444c
--- /dev/null
+++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Ppi/PchPlatformPolicy.h
@@ -0,0 +1,167 @@
+/**\r
+**/\r
+/**\r
+\r
+Copyright (c) 2012  - 2014, Intel Corporation. All rights reserved\r
+\r
+  This program and the accompanying materials are licensed and made available under\r
+  the terms and conditions of the BSD License that accompanies this distribution.\r
+  The full text of the license may be found at\r
+  http://opensource.org/licenses/bsd-license.php.\r
+\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+\r
+  @file\r
+  PchPlatformPolicy.h\r
+\r
+  @brief\r
+  PCH policy PPI produced by a platform driver specifying various\r
+  expected PCH settings. This PPI is consumed by the PCH PEI modules.\r
+\r
+**/\r
+#ifndef PCH_PLATFORM_POLICY_H_\r
+#define PCH_PLATFORM_POLICY_H_\r
+//\r
+// External include files do NOT need to be explicitly specified in real EDKII\r
+// environment\r
+//\r
+\r
+\r
+#include "PchRegs.h"\r
+\r
+//\r
+#define PCH_PLATFORM_POLICY_PPI_GUID \\r
+  { \\r
+    0x15344673, 0xd365, 0x4be2, 0x85, 0x13, 0x14, 0x97, 0xcc, 0x7, 0x61, 0x1d \\r
+  }\r
+\r
+extern EFI_GUID                         gPchPlatformPolicyPpiGuid;\r
+\r
+///\r
+/// Forward reference for ANSI C compatibility\r
+///\r
+typedef struct _PCH_PLATFORM_POLICY_PPI PCH_PLATFORM_POLICY_PPI;\r
+\r
+///\r
+/// PPI revision number\r
+/// Any backwards compatible changes to this PPI will result in an update in the revision number\r
+/// Major changes will require publication of a new PPI\r
+///\r
+/// Revision 1:    Original version\r
+///\r
+#define PCH_PLATFORM_POLICY_PPI_REVISION_1  1\r
+#define PCH_PLATFORM_POLICY_PPI_REVISION_2  2\r
+#define PCH_PLATFORM_POLICY_PPI_REVISION_3  3\r
+#define PCH_PLATFORM_POLICY_PPI_REVISION_4  4\r
+#define PCH_PLATFORM_POLICY_PPI_REVISION_5  5\r
+//\r
+// Generic definitions for device enabling/disabling used by PCH code.\r
+//\r
+#define PCH_DEVICE_ENABLE   1\r
+#define PCH_DEVICE_DISABLE  0\r
+\r
+typedef struct {\r
+  UINT8  ThermalDataReportEnable  : 1;   // OBSOLETE from Revision 5 !!! DO NOT USE !!!\r
+  UINT8  MchTempReadEnable        : 1;\r
+  UINT8  PchTempReadEnable        : 1;\r
+  UINT8  CpuEnergyReadEnable      : 1;\r
+  UINT8  CpuTempReadEnable        : 1;\r
+  UINT8  Cpu2TempReadEnable       : 1;\r
+  UINT8  TsOnDimmEnable           : 1;\r
+  UINT8  Dimm1TempReadEnable      : 1;\r
+\r
+  UINT8  Dimm2TempReadEnable      : 1;\r
+  UINT8  Dimm3TempReadEnable      : 1;\r
+  UINT8  Dimm4TempReadEnable      : 1;\r
+  UINT8  Rsvdbits                 : 5;\r
+} PCH_THERMAL_REPORT_CONTROL;\r
+//\r
+// ---------------------------- HPET Config -----------------------------\r
+//\r
+typedef struct {\r
+  BOOLEAN Enable; /// Determines if enable HPET function\r
+  UINT32  Base;   /// The HPET base address\r
+} PCH_HPET_CONFIG;\r
+\r
+\r
+///\r
+/// ---------------------------- SATA Config -----------------------------\r
+///\r
+typedef enum {\r
+  PchSataModeIde,\r
+  PchSataModeAhci,\r
+  PchSataModeRaid,\r
+  PchSataModeMax\r
+} PCH_SATA_MODE;\r
+\r
+///\r
+/// ---------------------------- PCI Express Config -----------------------------\r
+///\r
+typedef enum {\r
+  PchPcieAuto,\r
+  PchPcieGen1,\r
+  PchPcieGen2\r
+} PCH_PCIE_SPEED;\r
+\r
+typedef struct {\r
+  PCH_PCIE_SPEED  PcieSpeed[PCH_PCIE_MAX_ROOT_PORTS];\r
+} PCH_PCIE_CONFIG;\r
+\r
+///\r
+/// ---------------------------- IO APIC Config -----------------------------\r
+///\r
+typedef struct {\r
+  UINT8 IoApicId;\r
+} PCH_IOAPIC_CONFIG;\r
+\r
+///\r
+/// --------------------- Low Power Input Output Config ------------------------\r
+///\r
+typedef struct {\r
+  UINT8                   LpssPciModeEnabled    : 1;    /// Determines if LPSS PCI Mode enabled\r
+  UINT8                   Dma0Enabled           : 1;     /// Determines if LPSS DMA1 enabled\r
+  UINT8                   Dma1Enabled           : 1;     /// Determines if LPSS DMA2 enabled\r
+  UINT8                   I2C0Enabled           : 1;     /// Determines if LPSS I2C #1 enabled\r
+  UINT8                   I2C1Enabled           : 1;     /// Determines if LPSS I2C #2 enabled\r
+  UINT8                   I2C2Enabled           : 1;     /// Determines if LPSS I2C #3 enabled\r
+  UINT8                   I2C3Enabled           : 1;     /// Determines if LPSS I2C #4 enabled\r
+  UINT8                   I2C4Enabled           : 1;     /// Determines if LPSS I2C #5 enabled\r
+  UINT8                   I2C5Enabled           : 1;     /// Determines if LPSS I2C #6 enabled\r
+  UINT8                   I2C6Enabled           : 1;     /// Determines if LPSS I2C #7 enabled\r
+  UINT8                   Pwm0Enabled           : 1;     /// Determines if LPSS PWM #1 enabled\r
+  UINT8                   Pwm1Enabled           : 1;     /// Determines if LPSS PWM #2 enabled\r
+  UINT8                   Hsuart0Enabled        : 1;     /// Determines if LPSS HSUART #1 enabled\r
+  UINT8                   Hsuart1Enabled        : 1;     /// Determines if LPSS HSUART #2 enabled\r
+  UINT8                   SpiEnabled            : 1;     /// Determines if LPSS SPI enabled\r
+  UINT8                   Rsvdbits              : 2;\r
+} PEI_PCH_LPSS_CONFIG;\r
+\r
+///\r
+/// ------------ General PCH Platform Policy PPI definition ------------\r
+///\r
+struct _PCH_PLATFORM_POLICY_PPI {\r
+  UINT8                         Revision;\r
+  UINT8                         BusNumber;  // Bus Number of the PCH device\r
+  UINT32                        SpiBase;    // SPI Base Address.\r
+  UINT32                        PmcBase;    // PMC Base Address.\r
+  UINT32                        SmbmBase;   // SMB Memory Base Address.\r
+  UINT32                        IoBase;     // IO Base Address.\r
+  UINT32                        IlbBase;    // Intel Legacy Block Base Address.\r
+  UINT32                        PUnitBase;  // PUnit Base Address.\r
+  UINT32                        Rcba;       // Root Complex Base Address.\r
+  UINT32                        MphyBase;   // MPHY Base Address.\r
+  UINT16                        AcpiBase;   // ACPI I/O Base address.\r
+  UINT16                        GpioBase;   // GPIO Base address\r
+  PCH_HPET_CONFIG               *HpetConfig;\r
+  PCH_SATA_MODE                 SataMode;\r
+  PCH_PCIE_CONFIG               *PcieConfig;\r
+  PCH_IOAPIC_CONFIG             *IoApicConfig;\r
+  PEI_PCH_LPSS_CONFIG           *LpssConfig;\r
+  BOOLEAN                       EnableRmh;      // Determines if enable USB RMH function\r
+  BOOLEAN                       EhciPllCfgEnable;\r
+};\r
+\r
+#endif\r

diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Ppi/PchUsbPolicy.h b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Ppi/PchUsbPolicy.h
new file mode 100644 (file)
index 0000000..41c2b48
--- /dev/null
+++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Ppi/PchUsbPolicy.h
@@ -0,0 +1,75 @@
+/**\r
+**/\r
+/**\r
+\r
+Copyright (c) 2012  - 2014, Intel Corporation. All rights reserved\r
+\r
+  This program and the accompanying materials are licensed and made available under\r
+  the terms and conditions of the BSD License that accompanies this distribution.\r
+  The full text of the license may be found at\r
+  http://opensource.org/licenses/bsd-license.php.\r
+\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+\r
+  @file\r
+  PchUsbPolicy.h\r
+\r
+  @brief\r
+  PCH Usb policy PPI produced by a platform driver specifying\r
+  various expected PCH Usb settings. This PPI is consumed by the\r
+  PCH PEI drivers.\r
+\r
+**/\r
+#ifndef _PCH_USB_POLICY_H_\r
+#define _PCH_USB_POLICY_H_\r
+\r
+//\r
+// PCH Usb policy provided by platform for PEI phase\r
+//\r
+\r
+#ifndef ECP_FLAG\r
+#include <PiPei.h>\r
+#endif\r
+\r
+#include "PchRegs.h"\r
+#include <Protocol/PchPlatformPolicy.h>\r
+\r
+#define PCH_USB_POLICY_PPI_GUID \\r
+  { \\r
+    0xc02b0573, 0x2b4e, 0x4a31, 0xa3, 0x1a, 0x94, 0x56, 0x7b, 0x50, 0x44, 0x2c \\r
+  }\r
+\r
+extern EFI_GUID                     gPchUsbPolicyPpiGuid;\r
+\r
+typedef struct _PCH_USB_POLICY_PPI  PCH_USB_POLICY_PPI;\r
+\r
+///\r
+/// PPI revision number\r
+/// Any backwards compatible changes to this PPI will result in an update in the revision number\r
+/// Major changes will require publication of a new PPI\r
+///\r
+/// Revision 1: Original version\r
+///\r
+#define PCH_USB_POLICY_PPI_REVISION_1 1\r
+\r
+///\r
+/// Generic definitions for device enabling/disabling used by PCH code.\r
+///\r
+#define PCH_DEVICE_ENABLE   1\r
+#define PCH_DEVICE_DISABLE  0\r
+\r
+#define EHCI_MODE           1\r
+\r
+struct _PCH_USB_POLICY_PPI {\r
+  UINT8           Revision;\r
+  PCH_USB_CONFIG  *UsbConfig;\r
+  UINT8           Mode;\r
+  UINTN           EhciMemBaseAddr;\r
+  UINT32          EhciMemLength;\r
+  UINTN           XhciMemBaseAddr;\r
+};\r
+\r
+#endif\r

diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Ppi/PeiBlockIo.h b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Ppi/PeiBlockIo.h
new file mode 100644 (file)
index 0000000..16a137f
--- /dev/null
+++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Ppi/PeiBlockIo.h
@@ -0,0 +1,236 @@
+/** @file\r
+  Block IO protocol as defined in the UEFI 2.0 specification.\r
+\r
+  The Block IO protocol is used to abstract block devices like hard drives,\r
+  DVD-ROMs and floppy drives.\r
+\r
+  Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.<BR>\r
+  This program and the accompanying materials\r
+  are licensed and made available under the terms and conditions of the BSD License\r
+  which accompanies this distribution.  The full text of the license may be found at\r
+  http://opensource.org/licenses/bsd-license.php\r
+\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#ifndef __PEI_BLOCK_IO_H__\r
+#define __PEI_BLOCK_IO_H__\r
+// {BC5FA650-EDBB-4d0d-B3A3-D98907F847DF}\r
+#ifndef ECP_FLAG\r
+#define PEI_BLOCK_IO_PPI_GUID \\r
+  {  \\r
+    0xbc5fa650, 0xedbb, 0x4d0d, { 0xb3, 0xa3, 0xd9, 0x89, 0x7, 0xf8, 0x47, 0xdf }  \\r
+  }\r
+#endif\r
+typedef struct _PEI_BLOCK_IO_PPI  PEI_BLOCK_IO_PPI;\r
+\r
+\r
+/**\r
+  Reset the Block Device.\r
+\r
+  @param  This                 Indicates a pointer to the calling context.\r
+  @param  ExtendedVerification Driver may perform diagnostics on reset.\r
+\r
+  @retval EFI_SUCCESS          The device was reset.\r
+  @retval EFI_DEVICE_ERROR     The device is not functioning properly and could\r
+                               not be reset.\r
+\r
+**/\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *PEI_BLOCK_RESET)(\r
+  IN PEI_BLOCK_IO_PPI               *This,\r
+  IN BOOLEAN                        ExtendedVerification\r
+  );\r
+\r
+/**\r
+  Read BufferSize bytes from Lba into Buffer.\r
+\r
+  @param  This       Indicates a pointer to the calling context.\r
+  @param  MediaId    Id of the media, changes every time the media is replaced.\r
+  @param  Lba        The starting Logical Block Address to read from\r
+  @param  BufferSize Size of Buffer, must be a multiple of device block size.\r
+  @param  Buffer     A pointer to the destination buffer for the data. The caller is\r
+                     responsible for either having implicit or explicit ownership of the buffer.\r
+\r
+  @retval EFI_SUCCESS           The data was read correctly from the device.\r
+  @retval EFI_DEVICE_ERROR      The device reported an error while performing the read.\r
+  @retval EFI_NO_MEDIA          There is no media in the device.\r
+  @retval EFI_MEDIA_CHANGED     The MediaId does not matched the current device.\r
+  @retval EFI_BAD_BUFFER_SIZE   The Buffer was not a multiple of the block size of the device.\r
+  @retval EFI_INVALID_PARAMETER The read request contains LBAs that are not valid,\r
+                                or the buffer is not on proper alignment.\r
+\r
+**/\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *PEI_BLOCK_READ)(\r
+  IN  EFI_PEI_SERVICES              **PeiServices,\r
+  IN PEI_BLOCK_IO_PPI               *This,\r
+  IN UINT32                         MediaId,\r
+  IN EFI_LBA                        Lba,\r
+  IN UINTN                          BufferSize,\r
+  OUT VOID                          *Buffer\r
+  );\r
+\r
+/**\r
+  Write BufferSize bytes from Lba into Buffer.\r
+\r
+  @param  This       Indicates a pointer to the calling context.\r
+  @param  MediaId    The media ID that the write request is for.\r
+  @param  Lba        The starting logical block address to be written. The caller is\r
+                     responsible for writing to only legitimate locations.\r
+  @param  BufferSize Size of Buffer, must be a multiple of device block size.\r
+  @param  Buffer     A pointer to the source buffer for the data.\r
+\r
+  @retval EFI_SUCCESS           The data was written correctly to the device.\r
+  @retval EFI_WRITE_PROTECTED   The device can not be written to.\r
+  @retval EFI_DEVICE_ERROR      The device reported an error while performing the write.\r
+  @retval EFI_NO_MEDIA          There is no media in the device.\r
+  @retval EFI_MEDIA_CHNAGED     The MediaId does not matched the current device.\r
+  @retval EFI_BAD_BUFFER_SIZE   The Buffer was not a multiple of the block size of the device.\r
+  @retval EFI_INVALID_PARAMETER The write request contains LBAs that are not valid,\r
+                                or the buffer is not on proper alignment.\r
+\r
+**/\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *PEI_BLOCK_WRITE)(\r
+  IN  EFI_PEI_SERVICES              **PeiServices,\r
+  IN PEI_BLOCK_IO_PPI               *This,\r
+  IN UINT32                         MediaId,\r
+  IN EFI_LBA                        Lba,\r
+  IN UINTN                          BufferSize,\r
+  IN VOID                           *Buffer\r
+  );\r
+\r
+/**\r
+  Flush the Block Device.\r
+\r
+  @param  This              Indicates a pointer to the calling context.\r
+\r
+  @retval EFI_SUCCESS       All outstanding data was written to the device\r
+  @retval EFI_DEVICE_ERROR  The device reported an error while writting back the data\r
+  @retval EFI_NO_MEDIA      There is no media in the device.\r
+\r
+**/\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *PEI_BLOCK_FLUSH)(\r
+  IN  PEI_BLOCK_IO_PPI           *This\r
+  );\r
+\r
+/**\r
+  Block IO read only mode data and updated only via members of BlockIO\r
+**/\r
+typedef struct {\r
+  ///\r
+  /// The curent media Id. If the media changes, this value is changed.\r
+  ///\r
+  UINT32  MediaId;\r
+\r
+  ///\r
+  /// TRUE if the media is removable; otherwise, FALSE.\r
+  ///\r
+  BOOLEAN RemovableMedia;\r
+\r
+  ///\r
+  /// TRUE if there is a media currently present in the device;\r
+  /// othersise, FALSE. THis field shows the media present status\r
+  /// as of the most recent ReadBlocks() or WriteBlocks() call.\r
+  ///\r
+  BOOLEAN MediaPresent;\r
+\r
+  ///\r
+  /// TRUE if LBA 0 is the first block of a partition; otherwise\r
+  /// FALSE. For media with only one partition this would be TRUE.\r
+  ///\r
+  BOOLEAN LogicalPartition;\r
+\r
+  ///\r
+  /// TRUE if the media is marked read-only otherwise, FALSE.\r
+  /// This field shows the read-only status as of the most recent WriteBlocks () call.\r
+  ///\r
+  BOOLEAN ReadOnly;\r
+\r
+  ///\r
+  /// TRUE if the WriteBlock () function caches write data.\r
+  ///\r
+  BOOLEAN WriteCaching;\r
+\r
+  ///\r
+  /// The intrinsic block size of the device. If the media changes, then\r
+  /// this field is updated.\r
+  ///\r
+  UINT32  BlockSize;\r
+\r
+  ///\r
+  /// Supplies the alignment requirement for any buffer to read or write block(s).\r
+  ///\r
+  UINT32  IoAlign;\r
+\r
+  ///\r
+  /// The last logical block address on the device.\r
+  /// If the media changes, then this field is updated.\r
+  ///\r
+  EFI_LBA LastBlock;\r
+\r
+  ///\r
+  /// Only present if EFI_BLOCK_IO_PROTOCOL.Revision is greater than or equal to\r
+  /// EFI_BLOCK_IO_PROTOCOL_REVISION2. Returns the first LBA is aligned to\r
+  /// a physical block boundary.\r
+  ///\r
+  EFI_LBA LowestAlignedLba;\r
+\r
+  ///\r
+  /// Only present if EFI_BLOCK_IO_PROTOCOL.Revision is greater than or equal to\r
+  /// EFI_BLOCK_IO_PROTOCOL_REVISION2. Returns the number of logical blocks\r
+  /// per physical block.\r
+  ///\r
+  UINT32 LogicalBlocksPerPhysicalBlock;\r
+\r
+  ///\r
+  /// Only present if EFI_BLOCK_IO_PROTOCOL.Revision is greater than or equal to\r
+  /// EFI_BLOCK_IO_PROTOCOL_REVISION3. Returns the optimal transfer length\r
+  /// granularity as a number of logical blocks.\r
+  ///\r
+  UINT32 OptimalTransferLengthGranularity;\r
+#ifdef ECP_FLAG\r
+} PEI_BLOCK_IO_MEDIA2;\r
+#else\r
+} PEI_BLOCK_IO_MEDIA;\r
+#endif\r
+#define EFI_BLOCK_IO_PROTOCOL_REVISION  0x00010000\r
+#define EFI_BLOCK_IO_PROTOCOL_REVISION2 0x00020001\r
+#define EFI_BLOCK_IO_PROTOCOL_REVISION3 0x00020031\r
+\r
+///\r
+/// Revision defined in EFI1.1.\r
+///\r
+#define EFI_BLOCK_IO_INTERFACE_REVISION   EFI_BLOCK_IO_PROTOCOL_REVISION\r
+\r
+///\r
+///  This protocol provides control over block devices.\r
+///\r
+struct _PEI_BLOCK_IO_PPI {\r
+  ///\r
+  /// The revision to which the block IO interface adheres. All future\r
+  /// revisions must be backwards compatible. If a future version is not\r
+  /// back wards compatible, it is not the same GUID.\r
+  ///\r
+  UINT64              Revision;\r
+  ///\r
+  /// Pointer to the EFI_BLOCK_IO_MEDIA data for this device.\r
+  ///\r
+  PEI_BLOCK_IO_MEDIA  *Media;\r
+  PEI_BLOCK_RESET     Reset;\r
+  PEI_BLOCK_READ      ReadBlocks;\r
+  PEI_BLOCK_WRITE     WriteBlocks;\r
+  PEI_BLOCK_FLUSH     FlushBlocks;\r
+};\r
+\r
+//extern EFI_GUID gEfiBlockIoProtocolGuid;\r
+extern EFI_GUID gPeiBlockIoPpiGuid;\r
+#endif\r

diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Ppi/Sdhc.h b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Ppi/Sdhc.h
new file mode 100644 (file)
index 0000000..2239959
--- /dev/null
+++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Ppi/Sdhc.h
@@ -0,0 +1,365 @@
+/**\r
+**/\r
+/**\r
+\r
+Copyright (c) 2012  - 2014, Intel Corporation. All rights reserved\r
+\r
+  This program and the accompanying materials are licensed and made available under\r
+  the terms and conditions of the BSD License that accompanies this distribution.\r
+  The full text of the license may be found at\r
+  http://opensource.org/licenses/bsd-license.php.\r
+\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+\r
+  @file\r
+  Spi.h\r
+\r
+  @brief\r
+  This file defines the EFI SPI PPI which implements the\r
+  Intel(R) PCH SPI Host Controller Compatibility Interface.\r
+\r
+**/\r
+#ifndef _PEI_SDHC_H_\r
+#define _PEI_SDHC_H_\r
+\r
+\r
+\r
+//\r
+#define PEI_SDHC_PPI_GUID \\r
+  {  \\r
+    0xf4ef9d7a, 0x98c5, 0x4c1a, 0xb4, 0xd9, 0xd8, 0xd8, 0x72, 0x65, 0xbe, 0xc \\r
+  }\r
+typedef struct _PEI_SD_CONTROLLER_PPI PEI_SD_CONTROLLER_PPI;\r
+\r
+#define EFI_SD_HOST_IO_PROTOCOL_REVISION_01          0x01\r
+\r
+typedef enum {\r
+  ResponseNo = 0,\r
+  ResponseR1,\r
+  ResponseR1b,\r
+  ResponseR2,\r
+  ResponseR3,\r
+  ResponseR4,\r
+  ResponseR5,\r
+  ResponseR5b,\r
+  ResponseR6,\r
+  ResponseR7\r
+} RESPONSE_TYPE;\r
+\r
+typedef enum {\r
+  NoData = 0,\r
+  InData,\r
+  OutData\r
+} TRANSFER_TYPE;\r
+\r
+typedef enum {\r
+  Reset_Auto = 0,\r
+  Reset_DAT,\r
+  Reset_CMD,\r
+  Reset_DAT_CMD,\r
+  Reset_All\r
+} RESET_TYPE;\r
+\r
+\r
+\r
+typedef enum {\r
+  SDMA = 0,\r
+  ADMA2,\r
+  PIO\r
+} DMA_MOD;\r
+\r
+typedef struct {\r
+  UINT32  HighSpeedSupport:    1;  //High speed supported\r
+  UINT32  V18Support:          1;  //1.8V supported\r
+  UINT32  V30Support:          1;  //3.0V supported\r
+  UINT32  V33Support:          1;  //3.3V supported\r
+  UINT32  Reserved0:           4;\r
+  UINT32  BusWidth4:           1;  // 4 bit width\r
+  UINT32  BusWidth8:           1;  // 8 bit width\r
+  UINT32  Reserved1:           6;\r
+  UINT32  SDMASupport:         1;\r
+  UINT32  ADMA2Support:        1;\r
+  UINT32  DmaMode:             2;\r
+  UINT32  Reserved2:           12;\r
+  UINT32  BoundarySize;\r
+}HOST_CAPABILITY;\r
+\r
+\r
+#define PCI_SUBCLASS_SD_HOST_CONTROLLER   0x05\r
+#define PCI_IF_STANDARD_HOST_NO_DMA       0x00\r
+#define PCI_IF_STANDARD_HOST_SUPPORT_DMA  0x01\r
+\r
+//\r
+//MMIO Registers definition for MMC/SDIO controller\r
+//\r
+#define  MMIO_DMAADR                     0x00\r
+#define  MMIO_BLKSZ                      0x04\r
+#define  MMIO_BLKCNT                     0x06\r
+#define  MMIO_CMDARG                     0x08\r
+#define  MMIO_XFRMODE                    0x0C\r
+#define  MMIO_SDCMD                      0x0E\r
+#define  MMIO_RESP                       0x10\r
+#define  MMIO_BUFDATA                    0x20\r
+#define  MMIO_PSTATE                     0x24\r
+#define  MMIO_HOSTCTL                    0x28\r
+#define  MMIO_PWRCTL                     0x29\r
+#define  MMIO_BLKGAPCTL                  0x2A\r
+#define  MMIO_WAKECTL                    0x2B\r
+#define  MMIO_CLKCTL                     0x2C\r
+#define  MMIO_TOCTL                      0x2E\r
+#define  MMIO_SWRST                      0x2F\r
+#define  MMIO_NINTSTS                    0x30\r
+#define  MMIO_ERINTSTS                   0x32\r
+#define  MMIO_NINTEN                     0x34\r
+#define  MMIO_ERINTEN                    0x36\r
+#define  MMIO_NINTSIGEN                  0x38\r
+#define  MMIO_ERINTSIGEN                 0x3A\r
+#define  MMIO_AC12ERRSTS                 0x3C\r
+#define  MMIO_HOST_CTL2                  0x3E //hphang <- New in VLV2\r
+#define  MMIO_CAP                        0x40\r
+#define  MMIO_CAP2                       0x44 //hphang <- New in VLV2\r
+#define  MMIO_MCCAP                      0x48\r
+#define  MMIO_FORCEEVENTCMD12ERRSTAT     0x50 //hphang <- New in VLV2\r
+#define  MMIO_FORCEEVENTERRINTSTAT       0x52 //hphang <- New in VLV2\r
+#define  MMIO_ADMAERRSTAT                0x54 //hphang <- New in VLV2\r
+#define  MMIO_ADMASYSADDR                0x58 //hphang <- New in VLV2\r
+#define  MMIO_PRESETVALUE0               0x60 //hphang <- New in VLV2\r
+#define  MMIO_PRESETVALUE1               0x64 //hphang <- New in VLV2\r
+#define  MMIO_PRESETVALUE2               0x68 //hphang <- New in VLV2\r
+#define  MMIO_PRESETVALUE3               0x6C //hphang <- New in VLV2\r
+#define  MMIO_BOOTTIMEOUTCTRL            0x70 //hphang <- New in VLV2\r
+#define  MMIO_DEBUGSEL                   0x74 //hphang <- New in VLV2\r
+#define  MMIO_SHAREDBUS                  0xE0 //hphang <- New in VLV2\r
+#define  MMIO_SPIINTSUP                  0xF0 //hphang <- New in VLV2\r
+#define  MMIO_SLTINTSTS                  0xFC\r
+#define  MMIO_CTRLRVER                   0xFE\r
+#define  MMIO_SRST                       0x1FC\r
+\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *EFI_SD_CONTROLLER_PPI_SEND_COMMAND) (\r
+  IN  PEI_SD_CONTROLLER_PPI       *This,\r
+  IN   UINT16                     CommandIndex,\r
+  IN   UINT32                     Argument,\r
+  IN   TRANSFER_TYPE              DataType,\r
+  IN   UINT8                      *Buffer, OPTIONAL\r
+  IN   UINT32                     BufferSize,\r
+  IN   RESPONSE_TYPE              ResponseType,\r
+  IN   UINT32                     TimeOut,\r
+  OUT  UINT32                     *ResponseData OPTIONAL\r
+  );\r
+\r
+/*++\r
+\r
+  Routine Description:\r
+    Set max clock frequency of the host, the actual frequency\r
+    may not be the same as MaxFrequency. It depends on\r
+    the max frequency the host can support, divider, and host\r
+    speed mode.\r
+\r
+  Arguments:\r
+    This           - Pointer to EFI_SD_HOST_IO_PROTOCOL\r
+    MaxFrequency   - Max frequency in HZ\r
+\r
+  Returns:\r
+    EFI_SUCCESS\r
+    EFI_TIMEOUT\r
+--*/\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *EFI_SD_CONTROLLER_PPI_SET_CLOCK_FREQUENCY) (\r
+  IN  PEI_SD_CONTROLLER_PPI      *This,\r
+  IN  UINT32                     MaxFrequency\r
+  );\r
+\r
+/*++\r
+\r
+  Routine Description:\r
+    Set bus width of the host\r
+\r
+  Arguments:\r
+    This       - Pointer to EFI_SD_HOST_IO_PROTOCOL\r
+    BusWidth   - Bus width in 1, 4, 8 bits\r
+\r
+  Returns:\r
+    EFI_SUCCESS\r
+    EFI_INVALID_PARAMETER\r
+\r
+--*/\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *EFI_SD_CONTROLLER_PPI_SET_BUS_WIDTH) (\r
+  IN  PEI_SD_CONTROLLER_PPI      *This,\r
+  IN  UINT32                     BusWidth\r
+  );\r
+\r
+/*++\r
+\r
+  Routine Description:\r
+    Set Host mode in DDR\r
+  Arguments:\r
+    This      - Pointer to EFI_SD_HOST_IO_PROTOCOL\r
+    SetHostDdrMode   - True for DDR Mode set, false for normal mode\r
+\r
+  Returns:\r
+    EFI_SUCCESS\r
+    EFI_INVALID_PARAMETER\r
+\r
+--*/\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *EFI_SD_HOST_IO_PROTOCOL_SET_HOST_DDR_MODE) (\r
+  IN  PEI_SD_CONTROLLER_PPI    *This,\r
+  IN  UINT32                     DdrMode\r
+  );\r
+\r
+/*++\r
+\r
+  Routine Description:\r
+    Set voltage which could supported by the host.\r
+    Support 0(Power off the host), 1.8V, 3.0V, 3.3V\r
+  Arguments:\r
+    This      - Pointer to EFI_SD_HOST_IO_PROTOCOL\r
+    Voltage   - Units in 0.1 V\r
+\r
+  Returns:\r
+    EFI_SUCCESS\r
+    EFI_INVALID_PARAMETER\r
+\r
+--*/\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *EFI_SD_CONTROLLER_PPI_SET_HOST_VOLTAGE) (\r
+  IN  PEI_SD_CONTROLLER_PPI      *This,\r
+  IN  UINT32                     Voltage\r
+  );\r
+\r
+/*++\r
+\r
+  Routine Description:\r
+   Reset the host\r
+\r
+  Arguments:\r
+    This      - Pointer to EFI_SD_HOST_IO_PROTOCOL\r
+    ResetAll  - TRUE to reset all\r
+\r
+  Returns:\r
+    EFI_SUCCESS\r
+    EFI_TIMEOUT\r
+\r
+--*/\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *EFI_SD_CONTROLLER_PPI_RESET_SD_HOST) (\r
+  IN  PEI_SD_CONTROLLER_PPI      *This,\r
+  IN  RESET_TYPE                 ResetType\r
+  );\r
+\r
+/*++\r
+\r
+  Routine Description:\r
+   Reset the host\r
+\r
+  Arguments:\r
+    This    - Pointer to EFI_SD_HOST_IO_PROTOCOL\r
+    Enable  - TRUE to enable, FALSE to disable\r
+\r
+  Returns:\r
+    EFI_SUCCESS\r
+    EFI_TIMEOUT\r
+\r
+--*/\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *EFI_SD_CONTROLLER_PPI_ENABLE_AUTO_STOP_CMD) (\r
+  IN  PEI_SD_CONTROLLER_PPI      *This,\r
+  IN  BOOLEAN                    Enable\r
+  );\r
+\r
+/*++\r
+\r
+  Routine Description:\r
+    Find whether these is a card inserted into the slot. If so\r
+    init the host. If not, return EFI_NOT_FOUND.\r
+\r
+  Arguments:\r
+    This      - Pointer to EFI_SD_HOST_IO_PROTOCOL\r
+\r
+  Returns:\r
+    EFI_SUCCESS\r
+    EFI_NOT_FOUND\r
+\r
+--*/\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *EFI_SD_CONTROLLER_PPI_DETECT_CARD_AND_INIT_HOST) (\r
+  IN  PEI_SD_CONTROLLER_PPI      *This\r
+  );\r
+\r
+/*++\r
+\r
+  Routine Description:\r
+   Set the Block length\r
+\r
+  Arguments:\r
+    This        - Pointer to EFI_SD_HOST_IO_PROTOCOL\r
+    BlockLength - card supportes block length\r
+\r
+  Returns:\r
+    EFI_SUCCESS\r
+    EFI_TIMEOUT\r
+\r
+--*/\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *EFI_SD_CONTROLLER_PPI_SET_BLOCK_LENGTH) (\r
+  IN  PEI_SD_CONTROLLER_PPI      *This,\r
+  IN  UINT32                     BlockLength\r
+  );\r
+\r
+/*++\r
+\r
+  Routine Description:\r
+   Set the Block length\r
+\r
+  Arguments:\r
+    This        - Pointer to EFI_SD_HOST_IO_PROTOCOL\r
+    BlockLength - card supportes block length\r
+\r
+  Returns:\r
+    EFI_SUCCESS\r
+    EFI_TIMEOUT\r
+\r
+--*/\r
+\r
+typedef EFI_STATUS\r
+(EFIAPI *EFI_SD_CONTROLLER_PPI_SETUP_DEVICE)(\r
+  IN  PEI_SD_CONTROLLER_PPI    *This\r
+  );\r
+\r
+//\r
+// Interface structure for the EFI SD Host I/O Protocol\r
+//\r
+struct _PEI_SD_CONTROLLER_PPI {\r
+  UINT32                                           Revision;\r
+  HOST_CAPABILITY                                  HostCapability;\r
+  EFI_SD_CONTROLLER_PPI_SEND_COMMAND               SendCommand;\r
+  EFI_SD_CONTROLLER_PPI_SET_CLOCK_FREQUENCY        SetClockFrequency;\r
+  EFI_SD_CONTROLLER_PPI_SET_BUS_WIDTH              SetBusWidth;\r
+  EFI_SD_CONTROLLER_PPI_SET_HOST_VOLTAGE           SetHostVoltage;\r
+  EFI_SD_HOST_IO_PROTOCOL_SET_HOST_DDR_MODE        SetHostDdrMode;\r
+  EFI_SD_CONTROLLER_PPI_RESET_SD_HOST              ResetSdHost;\r
+  EFI_SD_CONTROLLER_PPI_ENABLE_AUTO_STOP_CMD       EnableAutoStopCmd;\r
+  EFI_SD_CONTROLLER_PPI_DETECT_CARD_AND_INIT_HOST  DetectCardAndInitHost;\r
+  EFI_SD_CONTROLLER_PPI_SET_BLOCK_LENGTH           SetBlockLength;\r
+  EFI_SD_CONTROLLER_PPI_SETUP_DEVICE               SetupDevice;\r
+};\r
+// Extern the GUID for PPI users.\r
+//\r
+extern EFI_GUID           gPeiSdhcPpiGuid;\r
+\r
+\r
+#endif\r

diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Ppi/SmbusPolicy.h b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Ppi/SmbusPolicy.h
new file mode 100644 (file)
index 0000000..c4eba99
--- /dev/null
+++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Ppi/SmbusPolicy.h
@@ -0,0 +1,46 @@
+//\r
+//\r
+\r
+/*++\r
+\r
+Copyright (c)  1999  - 2014, Intel Corporation. All rights reserved\r
+\r
+  This program and the accompanying materials are licensed and made available under\r
+  the terms and conditions of the BSD License that accompanies this distribution.\r
+  The full text of the license may be found at\r
+  http://opensource.org/licenses/bsd-license.php.\r
+\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+\r
+Module Name:\r
+\r
+  SmbusPolicy.h\r
+\r
+Abstract:\r
+\r
+  Smbus Policy PPI as defined in EFI 2.0\r
+\r
+--*/\r
+#ifndef _PEI_SMBUS_POLICY_PPI_H\r
+#define _PEI_SMBUS_POLICY_PPI_H\r
+\r
+#define PEI_SMBUS_POLICY_PPI_GUID \\r
+  { \\r
+    0x63b6e435, 0x32bc, 0x49c6, 0x81, 0xbd, 0xb7, 0xa1, 0xa0, 0xfe, 0x1a, 0x6c \\r
+  }\r
+\r
+typedef struct _PEI_SMBUS_POLICY_PPI PEI_SMBUS_POLICY_PPI;\r
+\r
+typedef struct _PEI_SMBUS_POLICY_PPI {\r
+  UINTN   BaseAddress;\r
+  UINT32  PciAddress;\r
+  UINT8   NumRsvdAddress;\r
+  UINT8   *RsvdAddress;\r
+} PEI_SMBUS_POLICY_PPI;\r
+\r
+extern EFI_GUID gPeiSmbusPolicyPpiGuid;\r
+\r
+#endif\r

diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Ppi/Spi.h b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Ppi/Spi.h
new file mode 100644 (file)
index 0000000..7c8afec
--- /dev/null
+++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Ppi/Spi.h
@@ -0,0 +1,48 @@
+/**\r
+**/\r
+/**\r
+\r
+Copyright (c) 2012  - 2014, Intel Corporation. All rights reserved\r
+\r
+  This program and the accompanying materials are licensed and made available under\r
+  the terms and conditions of the BSD License that accompanies this distribution.\r
+  The full text of the license may be found at\r
+  http://opensource.org/licenses/bsd-license.php.\r
+\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+\r
+  @file\r
+  Spi.h\r
+\r
+  @brief\r
+  This file defines the EFI SPI PPI which implements the\r
+  Intel(R) PCH SPI Host Controller Compatibility Interface.\r
+\r
+**/\r
+#ifndef _PEI_SPI_H_\r
+#define _PEI_SPI_H_\r
+\r
+\r
+#include <Protocol/Spi.h>\r
+\r
+\r
+//\r
+#define PEI_SPI_PPI_GUID \\r
+  { \\r
+    0xa38c6898, 0x2b5c, 0x4ff6, 0x93, 0x26, 0x2e, 0x63, 0x21, 0x2e, 0x56, 0xc2 \\r
+  }\r
+// Extern the GUID for PPI users.\r
+//\r
+extern EFI_GUID           gPeiSpiPpiGuid;\r
+\r
+///\r
+/// Reuse the EFI_SPI_PROTOCOL definitions\r
+/// This is possible becaues the PPI implementation does not rely on a PeiService pointer,\r
+/// as it uses EDKII Glue Lib to do IO accesses\r
+///\r
+typedef EFI_SPI_PROTOCOL  PEI_SPI_PPI;\r
+\r
+#endif\r

diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/ActiveBios.h b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/ActiveBios.h
new file mode 100644 (file)
index 0000000..4f45d8b
--- /dev/null
+++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/ActiveBios.h
@@ -0,0 +1,129 @@
+/**\r
+**/\r
+/**\r
+\r
+Copyright (c) 2012  - 2014, Intel Corporation. All rights reserved\r
+\r
+  This program and the accompanying materials are licensed and made available under\r
+  the terms and conditions of the BSD License that accompanies this distribution.\r
+  The full text of the license may be found at\r
+  http://opensource.org/licenses/bsd-license.php.\r
+\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+\r
+  @file\r
+  ActiveBios.h\r
+\r
+  @brief\r
+  This protocol is used to report and control what BIOS is mapped to the\r
+  BIOS address space anchored at 4GB boundary.\r
+\r
+  This protocol is EFI compatible.\r
+\r
+  E.G. For current generation ICH, the 4GB-16MB to 4GB range can be mapped\r
+  to PCI, SPI, or FWH.\r
+\r
+**/\r
+#ifndef _EFI_ACTIVE_BIOS_PROTOCOL_H_\r
+#define _EFI_ACTIVE_BIOS_PROTOCOL_H_\r
+\r
+\r
+\r
+\r
+//\r
+#define EFI_ACTIVE_BIOS_PROTOCOL_GUID \\r
+  { \\r
+    0xebbe2d1b, 0x1647, 0x4bda, 0xab, 0x9a, 0x78, 0x63, 0xe3, 0x96, 0xd4, 0x1a \\r
+  }\r
+extern EFI_GUID                           gEfiActiveBiosProtocolGuid;\r
+\r
+///\r
+/// Forward reference for ANSI C compatibility\r
+///\r
+typedef struct _EFI_ACTIVE_BIOS_PROTOCOL  EFI_ACTIVE_BIOS_PROTOCOL;\r
+\r
+///\r
+/// Protocol definitions\r
+///\r
+typedef enum {\r
+  ActiveBiosStateSpi,\r
+  ActiveBiosStatePci,   /// Obsolete since VLV\r
+  ActiveBiosStateLpc,\r
+  ActiveBiosStateMax\r
+} EFI_ACTIVE_BIOS_STATE;\r
+\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *EFI_ACTIVE_BIOS_SET_ACTIVE_BIOS_STATE) (\r
+  IN EFI_ACTIVE_BIOS_PROTOCOL     * This,\r
+  IN EFI_ACTIVE_BIOS_STATE        DesiredState,\r
+  IN UINTN                        Key\r
+  )\r
+/**\r
+\r
+  @brief\r
+  Change the current active BIOS settings to the requested state.\r
+  The caller is responsible for requesting a supported state from\r
+  the EFI_ACTIVE_BIOS_STATE selections.\r
+  This will fail if someone has locked the interface and the correct key is\r
+  not provided.\r
+\r
+  @param[in] This                 Pointer to the EFI_ACTIVE_BIOS_PROTOCOL instance.\r
+  @param[in] DesiredState         The requested state to configure the system for.\r
+  @param[in] Key                  If the interface is locked, Key must be the Key\r
+                                  returned from the LockState function call.\r
+\r
+  @retval EFI_SUCCESS             The function completed successfully\r
+  @retval EFI_ACCESS_DENIED       The interface is currently locked.\r
+\r
+**/\r
+;\r
+\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *EFI_ACTIVE_BIOS_LOCK_ACTIVE_BIOS_STATE) (\r
+  IN     EFI_ACTIVE_BIOS_PROTOCOL   * This,\r
+  IN     BOOLEAN                    Lock,\r
+  IN OUT UINTN                      *Key\r
+  );\r
+\r
+/**\r
+\r
+  @brief\r
+  Lock the current active BIOS state from further changes.  This allows a\r
+  caller to implement a critical section.  This is optionally supported\r
+  functionality.  Size conscious implementations may choose to require\r
+  callers cooperate without support from this protocol.\r
+\r
+  @param[in] This                 Pointer to the EFI_ACTIVE_BIOS_PROTOCOL instance.\r
+  @param[in] Lock                 TRUE to lock the current state, FALSE to unlock.\r
+  @param[in] Key                  If Lock is TRUE, then a key will be returned.  If\r
+                                  Lock is FALSE, the key returned from the prior call\r
+                                  to lock the protocol must be provided to unlock the\r
+                                  protocol.  The value of Key is undefined except that\r
+                                  it cannot be 0.\r
+\r
+  @retval EFI_SUCCESS             Command succeed.\r
+  @exception EFI_UNSUPPORTED      The function is not supported.\r
+  @retval EFI_ACCESS_DENIED       The interface is currently locked.\r
+  @retval EFI_DEVICE_ERROR        Device error, command aborts abnormally.\r
+\r
+**/\r
+\r
+///\r
+/// Protocol definition\r
+///\r
+/// Note that some functions are optional.  This means that they may be NULL.\r
+/// Caller is required to verify that an optional function is defined by checking\r
+/// that the value is not NULL.\r
+///\r
+struct _EFI_ACTIVE_BIOS_PROTOCOL {\r
+  EFI_ACTIVE_BIOS_STATE                   State;\r
+  EFI_ACTIVE_BIOS_SET_ACTIVE_BIOS_STATE   SetState;\r
+  EFI_ACTIVE_BIOS_LOCK_ACTIVE_BIOS_STATE  LockState;\r
+};\r
+\r
+#endif\r

diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/ActiveBiosProtocol.h b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/ActiveBiosProtocol.h
new file mode 100644 (file)
index 0000000..e59cfc0
--- /dev/null
+++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/ActiveBiosProtocol.h
@@ -0,0 +1,131 @@
+/**\r
+  This protocol is used to report and control what BIOS is mapped to the\r
+  BIOS address space anchored at 4GB boundary.\r
+\r
+  This protocol is EFI compatible.\r
+\r
+  E.G. For current generation ICH, the 4GB-16MB to 4GB range can be mapped\r
+  to PCI, SPI, or FWH.\r
+\r
+Copyright (c) 2011 - 2014, Intel Corporation. All rights reserved.<BR>\r
+\r
+  This program and the accompanying materials are licensed and made available under\r
+  the terms and conditions of the BSD License that accompanies this distribution.\r
+  The full text of the license may be found at\r
+  http://opensource.org/licenses/bsd-license.php.\r
+\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+**/\r
+\r
+\r
+#ifndef _EFI_ACTIVE_BIOS_PROTOCOL_H_\r
+#define _EFI_ACTIVE_BIOS_PROTOCOL_H_\r
+\r
+//\r
+// Define the  protocol GUID\r
+//\r
+#define EFI_ACTIVE_BIOS_PROTOCOL_GUID  \\r
+  { 0xebbe2d1b, 0x1647, 0x4bda, {0xab, 0x9a, 0x78, 0x63, 0xe3, 0x96, 0xd4, 0x1a} }\r
+\r
+typedef struct _EFI_ACTIVE_BIOS_PROTOCOL EFI_ACTIVE_BIOS_PROTOCOL;\r
+\r
+//\r
+// Protocol definitions\r
+//\r
+typedef enum {\r
+  ActiveBiosStateSpi,\r
+  ActiveBiosStatePci,\r
+  ActiveBiosStateLpc,\r
+  ActiveBiosStateMax\r
+} EFI_ACTIVE_BIOS_STATE;\r
+\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *EFI_ACTIVE_BIOS_SET_ACTIVE_BIOS_STATE) (\r
+  IN EFI_ACTIVE_BIOS_PROTOCOL     *This,\r
+  IN EFI_ACTIVE_BIOS_STATE        DesiredState,\r
+  IN UINTN                        Key\r
+  );\r
+/*++\r
+\r
+Routine Description:\r
+\r
+  Change the current active BIOS settings to the requested state.\r
+  The caller is responsible for requesting a supported state from\r
+  the EFI_ACTIVE_BIOS_STATE selections.\r
+\r
+  This will fail if someone has locked the interface and the correct key is\r
+  not provided.\r
+\r
+Arguments:\r
+\r
+  This                    Pointer to the EFI_ACTIVE_BIOS_PROTOCOL instance.\r
+  DesiredState            The requested state to configure the system for.\r
+  Key                     If the interface is locked, Key must be the Key\r
+                          returned from the LockState function call.\r
+\r
+Returns:\r
+\r
+  EFI_SUCCESS             Command succeed.\r
+  EFI_ACCESS_DENIED       The interface is currently locked.\r
+  EFI_DEVICE_ERROR        Device error, command aborts abnormally.\r
+\r
+--*/\r
+\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *EFI_ACTIVE_BIOS_LOCK_ACTIVE_BIOS_STATE) (\r
+  IN     EFI_ACTIVE_BIOS_PROTOCOL   *This,\r
+  IN     BOOLEAN                    Lock,\r
+  IN OUT UINTN                      *Key\r
+  );\r
+/*++\r
+\r
+Routine Description:\r
+\r
+  Lock the current active BIOS state from further changes.  This allows a\r
+  caller to implement a critical section.  This is optionally supported\r
+  functionality.  Size conscious implementations may choose to require\r
+  callers cooperate without support from this protocol.\r
+\r
+Arguments:\r
+\r
+  This                    Pointer to the EFI_ACTIVE_BIOS_PROTOCOL instance.\r
+  Lock                    TRUE to lock the current state, FALSE to unlock.\r
+  Key                     If Lock is TRUE, then a key will be returned.  If\r
+                          Lock is FALSE, the key returned from the prior call\r
+                          to lock the protocol must be provided to unlock the\r
+                          protocol.  The value of Key is undefined except that it\r
+                          will never be 0.\r
+\r
+Returns:\r
+\r
+  EFI_SUCCESS             Command succeed.\r
+  EFI_UNSUPPORTED         The function is not supported.\r
+  EFI_ACCESS_DENIED       The interface is currently locked.\r
+  EFI_DEVICE_ERROR        Device error, command aborts abnormally.\r
+\r
+--*/\r
+\r
+//\r
+// Protocol definition\r
+//\r
+// Note that some functions are optional.  This means that they may be NULL.\r
+// Caller is required to verify that an optional function is defined by checking\r
+// that the value is not NULL.\r
+//\r
+struct _EFI_ACTIVE_BIOS_PROTOCOL {\r
+  EFI_ACTIVE_BIOS_STATE                       State;\r
+  EFI_ACTIVE_BIOS_SET_ACTIVE_BIOS_STATE       SetState;\r
+  EFI_ACTIVE_BIOS_LOCK_ACTIVE_BIOS_STATE      LockState;\r
+};\r
+\r
+//\r
+// Extern the GUID for protocol users.\r
+//\r
+extern EFI_GUID gEfiActiveBiosProtocolGuid;\r
+\r
+#endif\r

diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/DxePchPolicyUpdateProtocol.h b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/DxePchPolicyUpdateProtocol.h
new file mode 100644 (file)
index 0000000..25dbb50
--- /dev/null
+++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/DxePchPolicyUpdateProtocol.h
@@ -0,0 +1,57 @@
+/*++\r
+\r
+Copyright (c)  1999  - 2014, Intel Corporation. All rights reserved\r
+\r
+  This program and the accompanying materials are licensed and made available under\r
+  the terms and conditions of the BSD License that accompanies this distribution.\r
+  The full text of the license may be found at\r
+  http://opensource.org/licenses/bsd-license.php.\r
+\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+\r
+Module Name:\r
+\r
+  DxePchPolicyUpdateProtocol.h\r
+\r
+Abstract:\r
+\r
+  PCH policy update protocol. This protocol is consumed by the PchDxePolicyInit driver\r
+\r
+--*/\r
+#ifndef _DXE_PCH_POLICY_UPDATE_PROTOCOL_H_\r
+#define _DXE_PCH_POLICY_UPDATE_PROTOCOL_H_\r
+\r
+#include "PchRegs.h"\r
+\r
+\r
+#ifdef ECP_FLAG\r
+#define DXE_PCH_POLICY_UPDATE_PROTOCOL_GUID \\r
+  { \\r
+    0x1a819e49, 0xd8ee, 0x48cb, 0x9a, 0x9c, 0xa, 0xa0, 0xd2, 0x81, 0xa, 0x38 \\r
+  }\r
+#else\r
+#define DXE_PCH_POLICY_UPDATE_PROTOCOL_GUID \\r
+  { \\r
+    0x1a819e49, 0xd8ee, 0x48cb, \\r
+    { \\r
+        0x9a, 0x9c, 0xa, 0xa0, 0xd2, 0x81, 0xa, 0x38 \\r
+    } \\r
+  }\r
+#endif\r
+\r
+extern EFI_GUID                                   gDxePchPolicyUpdateProtocolGuid;\r
+#define DXE_PCH_POLICY_UPDATE_PROTOCOL_REVISION_1 1\r
+\r
+//\r
+// ------------ General PCH policy Update protocol definition ------------\r
+//\r
+struct _DXE_PCH_POLICY_UPDATE_PROTOCOL {\r
+  UINT8                   Revision;\r
+};\r
+\r
+typedef struct _DXE_PCH_POLICY_UPDATE_PROTOCOL  DXE_PCH_POLICY_UPDATE_PROTOCOL;\r
+\r
+#endif\r

diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/EmmcCardInfoProtocol.h b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/EmmcCardInfoProtocol.h
new file mode 100644 (file)
index 0000000..718ddbc
--- /dev/null
+++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/EmmcCardInfoProtocol.h
@@ -0,0 +1,48 @@
+/*++\r
+\r
+Copyright (c)  2013  - 2014, Intel Corporation. All rights reserved\r
+\r
+  This program and the accompanying materials are licensed and made available under\r
+  the terms and conditions of the BSD License that accompanies this distribution.\r
+  The full text of the license may be found at\r
+  http://opensource.org/licenses/bsd-license.php.\r
+\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+--*/\r
+\r
+\r
+/*++\r
+Module Name:\r
+\r
+  EmmcCardInfoProtocol.h\r
+\r
+Abstract:\r
+\r
+  Interface definition for EFI_EMMC_CARD_INFO_PROTOCOL\r
+\r
+--*/\r
+\r
+\r
+#ifndef _EMMC_CARD_INFO_H_\r
+#define _EMMC_CARD_INFO_H_\r
+\r
+#define EFI_EMMC_CARD_INFO_PROTOCOL_GUID \\r
+  { \\r
+    0x1ebe5ab9, 0x2129, 0x49e7, {0x84, 0xd7, 0xee, 0xb9, 0xfc, 0xe5, 0xde, 0xdd } \\r
+  }\r
+\r
+typedef struct _EFI_EMMC_CARD_INFO_PROTOCOL  EFI_EMMC_CARD_INFO_PROTOCOL;\r
+\r
+\r
+//\r
+// EMMC Card info Structures\r
+//\r
+struct _EFI_EMMC_CARD_INFO_PROTOCOL {\r
+  CARD_DATA *CardData;\r
+};\r
+\r
+extern EFI_GUID gEfiEmmcCardInfoProtocolGuid;\r
+#endif\r

diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/Gpio.h b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/Gpio.h
new file mode 100644 (file)
index 0000000..030fb83
--- /dev/null
+++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/Gpio.h
@@ -0,0 +1,167 @@
+/*++\r
+\r
+Copyright (c)  1999  - 2014, Intel Corporation. All rights reserved\r
+\r
+  This program and the accompanying materials are licensed and made available under\r
+  the terms and conditions of the BSD License that accompanies this distribution.\r
+  The full text of the license may be found at\r
+  http://opensource.org/licenses/bsd-license.php.\r
+\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+\r
+Module Name:\r
+\r
+  Gpio.h\r
+\r
+Abstract:\r
+\r
+EFI 2.0 PEIM to provide platform specific information to other\r
+modules and to do some platform specific initialization.\r
+\r
+--*/\r
+\r
+#ifndef _PEI_GPIO_H\r
+#define _PEI_GPIO_H\r
+\r
+//#include "Efi.h"\r
+//#include "EfiCommonLib.h"\r
+//#include "Pei.h"\r
+//#include "Numbers.h"\r
+\r
+////\r
+//// GPIO Register Settings for BeaverBridge (FFVS) (Cedarview/Tigerpoint)\r
+////\r
+//// Field Descriptions:\r
+////    USE: Defines the pin's usage model:  GPIO (G) or Native (N) mode.\r
+////    I/O: Defines whether GPIOs are inputs (I) or outputs (O).\r
+////         (Note:  Only meaningful for pins used as GPIOs.)\r
+////    LVL: This field gives you the initial value for "output" GPIO's.\r
+////         (Note: The output level is dependent upon whether the pin is inverted.)\r
+////    INV: Defines whether Input GPIOs activation level is inverted.\r
+////         (Note:  Only affects the level sent to the GPE logic and does not\r
+////         affect the level read through the GPIO registers.)\r
+////\r
+//// Notes:\r
+////    1. BoardID is GPIO [8:38:34]\r
+////\r
+////Signal         UsedAs               USE     I/O      LVL     INV\r
+////--------------------------------------------------------------------------\r
+////GPIO0           Nonfunction       G     O            H       -\r
+////GPIO1           SMC_RUNTIME_SCI#    G        I           -       I\r
+////PIRQE#/GPIO2    Nonfunction G   O   H   -\r
+////PIRQF#/GPIO3    Nonfunction G   O   H   -\r
+////PIRQG#/GPIO4    Nonfunction G   O   H   -\r
+////PIRQH#/GPIO5    Nonfunction G   O   H   -\r
+////GPIO6   unused  G   O   L   -\r
+////GPIO7   unused  G   O   L   -\r
+////GPIO8          BOARD ID2    G   I   -   -\r
+////GPIO9   unused  G   O   L   -\r
+////GPIO10  SMC_EXTSMI# G   I   -   I\r
+////GPIO11  Nonfunction G   O   H   -\r
+////GPIO12  unused  G   O   L   -\r
+////GPIO13  SMC_WAKE_SCI#   G   I   -   I\r
+////GPIO14  unused  G   O   L   -\r
+////GPIO15  unused  G   O   L   -\r
+////GPIO16  PM_DPRSLPVR N   -   -   -\r
+////GNT5#/GPIO17    GNT5#   N   -   -   -\r
+////STPPCI#/GPIO18  PM_STPPCI#  N   -   -   -\r
+////STPCPU#/GPIO20  PM_STPCPU#  N   -   -   -\r
+////GPIO22  CRT_RefClk  G   I   -   -\r
+////GPIO23  unused  G   O   L   -\r
+////GPIO24  unused  G   O   L   -\r
+////GPIO25  DMI strap   G   O   L   -\r
+////GPIO26  unused  G   O   L   -\r
+////GPIO27  unused  G   O   L   -\r
+////GPIO28  RF_KILL#    G   O   H   -\r
+////OC5#/GPIO29 OC  N   -   -   -\r
+////OC6#/GPIO30 OC  N   -   -   -\r
+////OC7#/GPIO31 OC  N   -   -   -\r
+////CLKRUN#/GPIO32  PM_CLKRUN#  N   -   -   -\r
+////GPIO33  NC  G   O   L   -\r
+////GPIO34  BOARD ID0   G   I   -   -\r
+////GPIO36  unused  G   O   L   -\r
+////GPIO38  BOARD ID1   G   I   -   -\r
+////GPIO39  unused  G   O   L   -\r
+////GPIO48  unused  G   O   L   -\r
+////CPUPWRGD/GPIO49 H_PWRGD N   -   -   -\r
+//\r
+//#define   GPIO_USE_SEL_VAL              0x1FC0FFFF       //GPIO1, 10, 13 is EC signal\r
+//#define   GPIO_USE_SEL2_VAL             0x000100D6\r
+//#define   GPIO_IO_SEL_VAL               0x00402502\r
+//#define   GPIO_IO_SEL2_VAL              0x00000044\r
+//#define   GPIO_LVL_VAL                  0x1800083D\r
+//#define   GPIO_LVL2_VAL                 0x00000000\r
+//#define   GPIO_INV_VAL                  0x00002402\r
+//#define   GPIO_BLNK_VAL                 0x00000000\r
+//#define   ICH_GPI_ROUTE (ICH_GPI_ROUTE_SCI(13) | ICH_GPI_ROUTE_SCI(1))\r
+\r
+//\r
+// GPIO Register Settings for CedarRock and CedarFalls platforms\r
+//\r
+//      GPIO Register Settings for NB10_CRB\r
+//---------------------------------------------------------------------------------\r
+//Signal        Used As         USE         I/O     LVL\r
+//---------------------------------------------------------------------------------\r
+//\r
+// GPIO0    FP_AUDIO_DETECT     G       I\r
+// GPIO1    SMC_RUNTIME_SCI#    G       I\r
+// GPIO2        INT_PIRQE_N     N       I\r
+// GPIO3    INT_PIRQF_N     N       I\r
+// GPIO4        INT_PIRQG_N     N       I\r
+// GPIO5        INT_PIRQH_N     N       I\r
+// GPIO6\r
+// GPIO7\r
+// GPIO8\r
+// GPIO9    LPC_SIO_PME     G       I\r
+// GPIO10   SMC_EXTSMI_N        G       I\r
+// GPIO11   SMBALERT- pullup    N\r
+// GPIO12   ICH_GP12        G       I\r
+// GPIO13   SMC_WAKE_SCI_N      G       I\r
+// GPIO14   LCD_PID0        G       O       H\r
+// GPIO15   CONFIG_MODE_N       G       I\r
+// GPIO16       PM_DPRSLPVR     N\r
+// GPIO17   SPI_SELECT_STRAP1\r
+//          /L_BKLTSEL0_N   G       I\r
+// GPIO18   PM_STPPCI_N     N\r
+// GPIO19\r
+// GPIO20   PM_STPCPU_N     N\r
+// GPIO21\r
+// GPIO22   REQ4B           G       I\r
+// GPIO23   L_DRQ1_N        N\r
+// GPIO24   CRB_SV_DET_N        G       O       H\r
+// GPIO25   DMI strap\r
+//          / L_BKLTSEL1_N  G       O       H\r
+// GPIO26   LCD_PID1        G       O       H\r
+// GPIO27   TPEV_DDR3L_DETECT   G       O       H\r
+// GPIO28   RF_KILL         G       O       H:enable\r
+// GPIO29   OC          N\r
+// GPIO30   OC          N\r
+// GPIO31   OC          N\r
+// GPIO32   PM_CLKRUN_N     Native\r
+// GPIO33   MFG_MODE_N      G       I\r
+// GPIO34   BOARD ID0       G       I\r
+// GPIO35\r
+// GPIO36   SV_SET_UP       G       O       H\r
+// GPIO37\r
+// GPIO38   BOARD ID1       G       I\r
+// GPIO39   BOARD ID2       G       I\r
+// GPIO48   FLASH_SEL0      N\r
+// GPIO49   H_PWRGD         N\r
+\r
+#define ICH_GPI_ROUTE_SMI(Gpio)          ((( 0 << ((Gpio * 2) + 1)) | (1 << (Gpio * 2))))\r
+#define ICH_GPI_ROUTE_SCI(Gpio)          ((( 1 << ((Gpio * 2) + 1)) | (0 << (Gpio * 2))))\r
+\r
+#define   GPIO_USE_SEL_VAL              0X1F42F7C3\r
+#define   GPIO_USE_SEL2_VAL             0X000000D6\r
+#define   GPIO_IO_SEL_VAL               0X1042B73F\r
+#define   GPIO_IO_SEL2_VAL              0X000100C6\r
+#define   GPIO_LVL_VAL                  0X1F15F601\r
+#define   GPIO_LVL2_VAL                 0X000200D7\r
+#define   GPIO_INV_VAL                  0x00002602\r
+#define   GPIO_BLNK_VAL                 0x00040000\r
+#define   ICH_GPI_ROUTE (ICH_GPI_ROUTE_SCI(13) | ICH_GPI_ROUTE_SCI(1))\r
+\r
+#endif\r

diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/HwWatchdogTimer.h b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/HwWatchdogTimer.h
new file mode 100644 (file)
index 0000000..61cde2f
--- /dev/null
+++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/HwWatchdogTimer.h
@@ -0,0 +1,300 @@
+/*++\r
+\r
+Copyright (c)  1999  - 2014, Intel Corporation. All rights reserved\r
+\r
+  This program and the accompanying materials are licensed and made available under\r
+  the terms and conditions of the BSD License that accompanies this distribution.\r
+  The full text of the license may be found at\r
+  http://opensource.org/licenses/bsd-license.php.\r
+\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+\r
+Module Name:\r
+\r
+  HwWatchdogTimer.h\r
+\r
+Abstract:\r
+\r
+\r
+--*/\r
+\r
+#ifndef __EFI_WATCHDOG_TIMER_DRIVER_PROTOCOL_H__\r
+#define __EFI_WATCHDOG_TIMER_DRIVER_PROTOCOL_H__\r
+\r
+#define EFI_WATCHDOG_TIMER_DRIVER_PROTOCOL_GUID \\r
+  { 0xd5b06d16, 0x2ea1, 0x4def, 0x98, 0xd0, 0xa0, 0x5d, 0x40, 0x72, 0x84, 0x17 }\r
+\r
+#define EFI_WATCHDOG_TIMER_NOT_SUPPORTED_PROTOCOL_GUID \\r
+  { 0xe9e156ac, 0x3203, 0x4572, 0xac, 0xdf, 0x84, 0x4f, 0xdc, 0xdb, 0x6, 0xbf }\r
+\r
+\r
+#include <Guid/HwWatchdogTimerHob.h>\r
+\r
+//\r
+// General Purpose Constants\r
+//\r
+#define ICH_INSTAFLUSH_GPIO      BIT16 // BIT 16 in GPIO Level 2 is GPIO 48.\r
+#define B_INSTAFLUSH             BIT4\r
+//\r
+// Other Watchdog timer values\r
+//\r
+#define WDT_COUNTDOWN_VALUE                 0x14\r
+#define BDS_WDT_COUNTDOWN_VALUE             0x35\r
+\r
+\r
+//\r
+// Prototypes for the Watchdog Timer Driver Protocol\r
+//\r
+\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *EFI_WATCHDOG_START_TIMER) (\r
+  VOID\r
+  );\r
+/*++\r
+\r
+  Routine Description:\r
+    This service begins the Watchdog Timer countdown.  If the countdown completes prior to\r
+    Stop Timer or Restart Timer the system will reset.\r
+\r
+  Arguments:\r
+    None\r
+\r
+  Returns:\r
+    EFI_SUCCESS       - Operation completed successfully\r
+    EFI_DEVICE_ERROR  - The command was unsuccessful\r
+\r
+--*/\r
+\r
+\r
+\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *PEI_WATCHDOG_RESET_TIMER) (\r
+  VOID\r
+  );\r
+/*++\r
+\r
+  Routine Description:\r
+    This service resets the Watchdog Timer countdown and should only be called after the\r
+    Start Timer function.\r
+\r
+  Arguments:\r
+    None\r
+\r
+  Returns:\r
+    EFI_SUCCESS       - Operation completed successfully\r
+    EFI_DEVICE_ERROR  - The command was unsuccessful\r
+\r
+--*/\r
+\r
+\r
+\r
+\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *EFI_WATCHDOG_RESTART_TIMER) (\r
+  VOID\r
+  );\r
+/*++\r
+\r
+  Routine Description:\r
+    This service restarts the Watchdog Timer countdown and should only be called after the\r
+    Start Timer function.\r
+\r
+  Arguments:\r
+    None\r
+\r
+  Returns:\r
+    EFI_SUCCESS       - Operation completed successfully\r
+    EFI_DEVICE_ERROR  - The command was unsuccessful\r
+\r
+--*/\r
+\r
+\r
+\r
+\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *EFI_WATCHDOG_STOP_TIMER) (\r
+  VOID\r
+  );\r
+/*++\r
+\r
+  Routine Description:\r
+    This service disables the Watchdog Timer countdown.\r
+\r
+  Arguments:\r
+    None\r
+\r
+  Returns:\r
+    EFI_SUCCESS       - Operation completed successfully\r
+    EFI_DEVICE_ERROR  - The command was unsuccessful\r
+\r
+--*/\r
+\r
+\r
+\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *EFI_WATCHDOG_CHECK_TIMEOUT) (\r
+  OUT HW_WATCHDOG_TIMEOUT       *WatchdogTimeout\r
+  );\r
+/*++\r
+\r
+  Routine Description:\r
+    This service disables the Watchdog Timer countdown.\r
+\r
+  Arguments:\r
+    None\r
+\r
+  Returns:\r
+    EFI_SUCCESS       - Operation completed successfully\r
+    EFI_DEVICE_ERROR  - The command was unsuccessful\r
+\r
+--*/\r
+\r
+\r
+\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *EFI_WATCHDOG_FORCE_REBOOT) (\r
+  IN BOOLEAN                    ForceTimeout,\r
+  IN UINT8                      ResetType\r
+  );\r
+/*++\r
+\r
+  Routine Description:\r
+    This service forces a reboot of the system due to a reset of the POWERGOOD_PS,\r
+    POWERGOOD_CLK, and the BSEL Override\r
+\r
+  Arguments:\r
+    None\r
+\r
+  Returns:\r
+    This function should not return!\r
+\r
+    EFI_DEVICE_ERROR  - The command was unsuccessful and a reboot did not occur\r
+\r
+--*/\r
+\r
+\r
+\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *EFI_WATCHDOG_KNOWN_RESET) (\r
+  IN BOOLEAN                    AllowReset\r
+  );\r
+/*++\r
+\r
+  Routine Description:\r
+    This service notifies the Watchdog Timer of the fact that a known reset is occuring.\r
+\r
+  Arguments:\r
+    AllowReset -  TRUE if a Reset is currently expected\r
+                  FALSE if a Reset is not currently expected\r
+\r
+  Returns:\r
+    This function should not return!\r
+\r
+    EFI_DEVICE_ERROR  - The command was unsuccessful and a reboot did not occur\r
+\r
+--*/\r
+\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *EFI_GET_TIMER_COUNT_DOWN_PERIOD)(\r
+  OUT UINT32      *CountdownValue\r
+  );\r
+/*++\r
+\r
+  Routine Description:\r
+    This service reads the current Watchdog Timer countdown reload value.\r
+\r
+  Arguments:\r
+    CountdownValue - pointer to UINT32 to return the value of the reload register.\r
+\r
+  Returns:\r
+    EFI_SUCCESS       - Operation completed successfully\r
+    EFI_DEVICE_ERROR  - The command was unsuccessful\r
+\r
+--*/\r
+\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *EFI_SET_TIMER_COUNT_DOWN_PERIOD)(\r
+  OUT UINT32      CountdownValue\r
+  );\r
+/*++\r
+\r
+  Routine Description:\r
+    This service reads the current Watchdog Timer countdown reload value.\r
+\r
+  Arguments:\r
+    CountdownValue - Value to set the reload register.\r
+\r
+  Returns:\r
+    EFI_SUCCESS       - Operation completed successfully\r
+    EFI_DEVICE_ERROR  - The command was unsuccessful\r
+\r
+--*/\r
+\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *PEI_WATCHDOG_CLEAR_TIMER_STATE) (\r
+  );\r
+/*++\r
+\r
+  Routine Description:\r
+    This service clears the state that indicates the Watchdog Timer fired.\r
+\r
+  Arguments:\r
+\r
+  Returns:\r
+    EFI_SUCCESS       - Operation completed successfully\r
+    EFI_DEVICE_ERROR  - The command was unsuccessful\r
+\r
+--*/\r
+\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *EFI_STALL_WATCHDOG_COUNTDOWN) (\r
+  IN BOOLEAN Stall\r
+  );\r
+/*++\r
+\r
+  Routine Description:\r
+    This service disables the Watchdog Timer countdown.  It also closes the recurring restart event\r
+    if the event exists.\r
+\r
+  Arguments:\r
+    Stall - TRUE = Stop the timer countdown\r
+            FALSE = Start the timer countdown\r
+\r
+  Returns:\r
+    EFI_SUCCESS       - Operation completed successfully\r
+    EFI_DEVICE_ERROR  - The command was unsuccessful\r
+\r
+--*/\r
+\r
+typedef struct _EFI_WATCHDOG_TIMER_DRIVER_PROTOCOL {\r
+  EFI_WATCHDOG_START_TIMER                      StartWatchdogTimer;\r
+  PEI_WATCHDOG_RESET_TIMER                      ResetWatchdogTimeout;\r
+  EFI_WATCHDOG_RESTART_TIMER                    RestartWatchdogTimer;\r
+  EFI_WATCHDOG_STOP_TIMER                       StopWatchdogTimer;\r
+  EFI_WATCHDOG_CHECK_TIMEOUT                    CheckWatchdogTimeout;\r
+  EFI_WATCHDOG_FORCE_REBOOT                     ForceReboot;\r
+  EFI_WATCHDOG_KNOWN_RESET                      AllowKnownReset;\r
+  EFI_GET_TIMER_COUNT_DOWN_PERIOD               GetCountdownPeriod;\r
+  EFI_SET_TIMER_COUNT_DOWN_PERIOD               SetCountdownPeriod;\r
+  PEI_WATCHDOG_CLEAR_TIMER_STATE                ClearTimerState;\r
+  EFI_STALL_WATCHDOG_COUNTDOWN                  StallWatchdogCountdown;\r
+} EFI_WATCHDOG_TIMER_DRIVER_PROTOCOL;\r
+\r
+extern EFI_GUID gEfiWatchdogTimerDriverProtocolGuid;\r
+extern EFI_GUID gEfiWatchdogTimerNotSupportedProtocolGuid;\r
+\r
+#endif\r

diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/I2cBus.h b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/I2cBus.h
new file mode 100644 (file)
index 0000000..685e563
--- /dev/null
+++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/I2cBus.h
@@ -0,0 +1,170 @@
+/** @file\r
+  I2C bus interface\r
+\r
+  This layer provides I/O access to an I2C device.\r
+\r
+  Copyright (c) 2012, Intel Corporation\r
+  All rights reserved. This program and the accompanying materials\r
+  are licensed and made available under the terms and conditions of the BSD License\r
+  which accompanies this distribution.  The full text of the license may be found at\r
+  http://opensource.org/licenses/bsd-license.php\r
+\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#ifndef __I2C_BUS_H__\r
+#define __I2C_BUS_H__\r
+\r
+#include <Protocol/I2cHostMcg.h>\r
+\r
+///\r
+/// I2C bus protocol\r
+///\r
+typedef struct _EFI_I2C_BUS_PROTOCOL  EFI_I2C_BUS_PROTOCOL;\r
+\r
+\r
+/**\r
+  Perform an I2C operation on the device\r
+\r
+  This routine must be called at or below TPL_NOTIFY.  For synchronous\r
+  requests this routine must be called at or below TPL_CALLBACK.\r
+\r
+  N.B. The typical consumers of this API are the third party I2C\r
+  drivers.  Extreme care must be taken by other consumers of this\r
+  API to prevent confusing the third party I2C drivers due to a\r
+  state change at the I2C device which the third party I2C drivers\r
+  did not initiate.  I2C platform drivers may use this API within\r
+  these guidelines.\r
+\r
+  This routine queues an operation to the I2C controller for execution\r
+  on the I2C bus.\r
+\r
+  As an upper layer driver writer, the following need to be provided\r
+  to the platform vendor:\r
+\r
+  1.  ACPI CID value or string - this is used to connect the upper layer\r
+      driver to the device.\r
+  2.  Slave address array guidance when the I2C device uses more than one\r
+      slave address.  This is used to access the blocks of hardware within\r
+      the I2C device.\r
+\r
+  @param[in] This               Address of an EFI_I2C_BUS_PROTOCOL\r
+                                structure\r
+  @param[in] SlaveAddressIndex  Index into an array of slave addresses for\r
+                                the I2C device.  The values in the array are\r
+                                specified by the board designer, with the\r
+                                I2C device driver writer providing the slave\r
+                                address order.\r
+\r
+                                For devices that have a single slave address,\r
+                                this value must be zero.  If the I2C device\r
+                                uses more than one slave address then the third\r
+                                party (upper level) I2C driver writer needs to\r
+                                specify the order of entries in the slave address\r
+                                array.\r
+\r
+                                \ref ThirdPartyI2cDrivers "Third Party I2C Drivers"\r
+                                section in I2cMaster.h.\r
+  @param[in] Event              Event to set for asynchronous operations,\r
+                                NULL for synchronous operations\r
+  @param[in] RequestPacket      Address of an EFI_I2C_REQUEST_PACKET\r
+                                structure describing the I2C operation\r
+  @param[out] I2cStatus         Optional buffer to receive the I2C operation\r
+                                completion status\r
+\r
+  @retval EFI_SUCCESS           The operation completed successfully.\r
+  @retval EFI_ABORTED           The request did not complete because the driver\r
+                                was shutdown.\r
+  @retval EFI_ACCESS_DENIED     Invalid SlaveAddressIndex value\r
+  @retval EFI_BAD_BUFFER_SIZE   The WriteBytes or ReadBytes buffer size is too large.\r
+  @retval EFI_DEVICE_ERROR      There was an I2C error (NACK) during the operation.\r
+                                This could indicate the slave device is not present.\r
+  @retval EFI_INVALID_PARAMETER RequestPacket is NULL\r
+  @retval EFI_INVALID_PARAMETER TPL is too high\r
+  @retval EFI_NO_RESPONSE       The I2C device is not responding to the\r
+                                slave address.  EFI_DEVICE_ERROR may also be\r
+                                returned if the controller can not distinguish\r
+                                when the NACK occurred.\r
+  @retval EFI_NOT_FOUND         I2C slave address exceeds maximum address\r
+  @retval EFI_NOT_READY         I2C bus is busy or operation pending, wait for\r
+                                the event and then read status pointed to by\r
+                                the request packet.\r
+  @retval EFI_OUT_OF_RESOURCES  Insufficient memory for I2C operation\r
+  @retval EFI_TIMEOUT           The transaction did not complete within an internally\r
+                                specified timeout period.\r
+\r
+**/\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *EFI_I2C_BUS_START_REQUEST) (\r
+  IN CONST EFI_I2C_BUS_PROTOCOL *This,\r
+  IN UINTN SlaveAddressIndex,\r
+  IN EFI_EVENT Event OPTIONAL,\r
+  IN CONST EFI_I2C_REQUEST_PACKET *RequestPacket,\r
+  OUT EFI_STATUS *I2cStatus OPTIONAL\r
+  );\r
+\r
+///\r
+/// The I2C bus protocol enables access to a specific device on the I2C bus.\r
+///\r
+/// Each I2C device is described as an ACPI node (HID, UID and CID) within the\r
+/// platform layer.  The I2C bus protocol enumerates the I2C devices in the\r
+/// platform and creates a unique handle and device path for each I2C device.\r
+///\r
+/// I2C slave addressing is abstracted to validate addresses and limit operation\r
+/// to the specified I2C device.  The third party providing the I2C device support\r
+/// provides an ordered list of slave addresses for the I2C device to the team\r
+/// building the platform layer.  The platform team must preserve the order of the\r
+/// supplied list.  SlaveAddressCount is the number of entries in this list or\r
+/// array within the platform layer.  The third party device support references\r
+/// a slave address using an index into the list or array in the range of zero\r
+/// to SlaveAddressCount - 1.\r
+///\r
+struct _EFI_I2C_BUS_PROTOCOL {\r
+  ///\r
+  /// Start an I2C operation on the bus\r
+  ///\r
+  EFI_I2C_BUS_START_REQUEST StartRequest;\r
+\r
+  ///\r
+  /// The maximum number of slave addresses for the I2C device.  The caller may\r
+  /// validate this value as a check on the platform layer's configuration.  Slave\r
+  /// address selection uses an index value in the range of zero to SlaveAddressCount - 1.\r
+  ///\r
+  UINTN SlaveAddressCount;\r
+\r
+  ///\r
+  /// Hardware revision - Matches the ACPI _HRV value\r
+  ///\r
+  /// The HardwareRevision value allows a single driver to support multiple hardware\r
+  /// revisions and implement the necessary workarounds for limitations within the\r
+  /// hardware.\r
+  ///\r
+  UINT32 HardwareRevision;\r
+\r
+  ///\r
+  /// The maximum number of bytes the I2C host controller\r
+  /// is able to receive from the I2C bus.\r
+  ///\r
+  UINT32 MaximumReceiveBytes;\r
+\r
+  ///\r
+  /// The maximum number of bytes the I2C host controller\r
+  /// is able to send on the I2C bus.\r
+  ///\r
+  UINT32 MaximumTransmitBytes;\r
+\r
+  ///\r
+  /// The maximum number of bytes in the I2C bus transaction.\r
+  ///\r
+  UINT32 MaximumTotalBytes;\r
+};\r
+\r
+///\r
+/// GUID for the I2C bus protocol\r
+///\r
+extern EFI_GUID gEfiI2cBusProtocolGuid;\r
+\r
+#endif  //  __I2C_BUS_H__\r

diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/PchExtendedReset.h b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/PchExtendedReset.h
new file mode 100644 (file)
index 0000000..574fc3e
--- /dev/null
+++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/PchExtendedReset.h
@@ -0,0 +1,90 @@
+/*++\r
+\r
+Copyright (c) 2008  - 2014, Intel Corporation. All rights reserved\r
+\r
+  This program and the accompanying materials are licensed and made available under\r
+  the terms and conditions of the BSD License that accompanies this distribution.\r
+  The full text of the license may be found at\r
+  http://opensource.org/licenses/bsd-license.php.\r
+\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+\r
+Module Name:\r
+\r
+  PchExtendedReset.h\r
+\r
+Abstract:\r
+\r
+  PCH Extended Reset Protocol\r
+\r
+--*/\r
+#ifndef _EFI_PCH_EXTENDED_RESET_H_\r
+#define _EFI_PCH_EXTENDED_RESET_H_\r
+\r
+\r
+\r
+//\r
+#define EFI_PCH_EXTENDED_RESET_PROTOCOL_GUID \\r
+  { \\r
+    0xf0bbfca0, 0x684e, 0x48b3, 0xba, 0xe2, 0x6c, 0x84, 0xb8, 0x9e, 0x53, 0x39 \\r
+  }\r
+extern EFI_GUID                                 gEfiPchExtendedResetProtocolGuid;\r
+\r
+//\r
+// Forward reference for ANSI C compatibility\r
+//\r
+typedef struct _EFI_PCH_EXTENDED_RESET_PROTOCOL EFI_PCH_EXTENDED_RESET_PROTOCOL;\r
+\r
+//\r
+// Related Definitions\r
+//\r
+//\r
+// PCH Extended Reset Types\r
+//\r
+typedef struct {\r
+  UINT8 PowerCycle  : 1;  // 0: Disabled*; 1: Enabled\r
+  UINT8 GlobalReset : 1;  // 0: Disabled*; 1: Enabled\r
+  UINT8 SusPwrDnAck : 1;  // 0: Do Nothing;\r
+  // 1: GPIO[30](SUS_PWR_DN_ACK) level is set low prior to Global Reset(for systems with an embedded controller)\r
+  UINT8 RsvdBits : 5;     // Reserved fields for future expansion w/o protocol change\r
+} PCH_EXTENDED_RESET_TYPES;\r
+\r
+//\r
+// Member functions\r
+//\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *EFI_PCH_EXTENDED_RESET) (\r
+  IN     EFI_PCH_EXTENDED_RESET_PROTOCOL   * This,\r
+  IN     PCH_EXTENDED_RESET_TYPES          PchExtendedResetTypes\r
+  );\r
+\r
+/*++\r
+\r
+Routine Description:\r
+\r
+  Execute Pch Extended Reset from the host controller.\r
+\r
+Arguments:\r
+\r
+  This                    - Pointer to the EFI_PCH_EXTENDED_RESET_PROTOCOL instance.\r
+  PchExtendedResetTypes   - Pch Extended Reset Types which includes PowerCycle, Globalreset.\r
+\r
+Returns:\r
+\r
+  Does not return if the reset takes place.\r
+  EFI_INVALID_PARAMETER   - If ResetType is invalid.\r
+\r
+--*/\r
+\r
+//\r
+// Interface structure for the Pch Extended Reset Protocol\r
+//\r
+struct _EFI_PCH_EXTENDED_RESET_PROTOCOL {\r
+  EFI_PCH_EXTENDED_RESET  Reset;\r
+};\r
+\r
+#endif\r

diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/PchInfo.h b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/PchInfo.h
new file mode 100644 (file)
index 0000000..2a3e2b2
--- /dev/null
+++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/PchInfo.h
@@ -0,0 +1,66 @@
+/**\r
+**/\r
+/**\r
+\r
+Copyright (c) 2012  - 2014, Intel Corporation. All rights reserved\r
+\r
+  This program and the accompanying materials are licensed and made available under\r
+  the terms and conditions of the BSD License that accompanies this distribution.\r
+  The full text of the license may be found at\r
+  http://opensource.org/licenses/bsd-license.php.\r
+\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+\r
+  @file\r
+  PchInfo.h\r
+\r
+  @brief\r
+  This file defines the PCH Info Protocol.\r
+\r
+**/\r
+#ifndef _PCH_INFO_H_\r
+#define _PCH_INFO_H_\r
+\r
+\r
+#define EFI_PCH_INFO_PROTOCOL_GUID \\r
+  { \\r
+    0xd31f0400, 0x7d16, 0x4316, 0xbf, 0x88, 0x60, 0x65, 0x88, 0x3b, 0x40, 0x2b \\r
+  }\r
+extern EFI_GUID                       gEfiPchInfoProtocolGuid;\r
+\r
+///\r
+/// Forward reference for ANSI C compatibility\r
+///\r
+typedef struct _EFI_PCH_INFO_PROTOCOL EFI_PCH_INFO_PROTOCOL;\r
+\r
+///\r
+/// Protocol revision number\r
+/// Any backwards compatible changes to this protocol will result in an update in the revision number\r
+/// Major changes will require publication of a new protocol\r
+///\r
+/// Revision 1:  Original version\r
+///\r
+#define PCH_INFO_PROTOCOL_REVISION_1  1\r
+#define PCH_INFO_PROTOCOL_REVISION_2  2\r
+\r
+///\r
+/// RCVersion[7:0] is the release number.\r
+/// For example:\r
+/// VlvFramework 0.6.0-01 should be 00 06 00 01 (0x00060001)\r
+/// VlvFramework 0.6.2    should be 00 06 02 00 (0x00060200)\r
+///\r
+#define PCH_RC_VERSION                0x01000000\r
+\r
+///\r
+/// Protocol definition\r
+///\r
+struct _EFI_PCH_INFO_PROTOCOL {\r
+  UINT8   Revision;\r
+  UINT8   BusNumber;\r
+  UINT32  RCVersion;\r
+};\r
+\r
+#endif\r

diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/PchPlatformPolicy.h b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/PchPlatformPolicy.h
new file mode 100644 (file)
index 0000000..0205c01
--- /dev/null
+++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/PchPlatformPolicy.h
@@ -0,0 +1,556 @@
+/**\r
+**/\r
+/**\r
+\r
+Copyright (c) 2013  - 2014, Intel Corporation. All rights reserved\r
+\r
+  This program and the accompanying materials are licensed and made available under\r
+  the terms and conditions of the BSD License that accompanies this distribution.\r
+  The full text of the license may be found at\r
+  http://opensource.org/licenses/bsd-license.php.\r
+\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+\r
+  @file\r
+  PchPlatformPolicy.h\r
+\r
+  @brief\r
+  PCH policy protocol produced by a platform driver specifying various\r
+  expected PCH settings. This protocol is consumed by the PCH drivers.\r
+\r
+**/\r
+#ifndef _PCH_PLATFORM_POLICY_H_\r
+#define _PCH_PLATFORM_POLICY_H_\r
+\r
+\r
+//\r
+#include "PchRegs.h"\r
+#ifndef ECP_FLAG\r
+#include "Uefi.h"\r
+#endif\r
+\r
+#define DXE_PCH_PLATFORM_POLICY_PROTOCOL_GUID \\r
+  { \\r
+    0x4b0165a9, 0x61d6, 0x4e23, 0xa0, 0xb5, 0x3e, 0xc7, 0x9c, 0x2e, 0x30, 0xd5 \\r
+  }\r
+extern EFI_GUID                                   gDxePchPlatformPolicyProtocolGuid;\r
+\r
+///\r
+/// Forward reference for ANSI C compatibility\r
+///\r
+typedef struct _DXE_PCH_PLATFORM_POLICY_PROTOCOL  DXE_PCH_PLATFORM_POLICY_PROTOCOL;\r
+\r
+///\r
+/// Protocol revision number\r
+/// Any backwards compatible changes to this protocol will result in an update in the revision number\r
+/// Major changes will require publication of a new protocol\r
+///\r
+/// Revision 1: Original version\r
+///\r
+#define DXE_PCH_PLATFORM_POLICY_PROTOCOL_REVISION_1 1\r
+#define DXE_PCH_PLATFORM_POLICY_PROTOCOL_REVISION_2 2\r
+#define DXE_PCH_PLATFORM_POLICY_PROTOCOL_REVISION_3 3\r
+#define DXE_PCH_PLATFORM_POLICY_PROTOCOL_REVISION_4 4\r
+#define DXE_PCH_PLATFORM_POLICY_PROTOCOL_REVISION_5 5\r
+#define DXE_PCH_PLATFORM_POLICY_PROTOCOL_REVISION_6 6\r
+#define DXE_PCH_PLATFORM_POLICY_PROTOCOL_REVISION_7 7\r
+#define DXE_PCH_PLATFORM_POLICY_PROTOCOL_REVISION_8 8\r
+#define DXE_PCH_PLATFORM_POLICY_PROTOCOL_REVISION_9 9\r
+#define DXE_PCH_PLATFORM_POLICY_PROTOCOL_REVISION_10 10\r
+#define DXE_PCH_PLATFORM_POLICY_PROTOCOL_REVISION_11 11\r
+#define DXE_PCH_PLATFORM_POLICY_PROTOCOL_REVISION_12 12\r
+\r
+///\r
+/// Generic definitions for device enabling/disabling used by PCH code.\r
+///\r
+#define PCH_DEVICE_ENABLE   1\r
+#define PCH_DEVICE_DISABLE  0\r
+\r
+///\r
+/// ---------------------------- Device Enabling ------------------------------\r
+///\r
+/// PCH Device enablings\r
+///\r
+typedef struct {\r
+  UINT8 Lan               : 1;    /// 0: Disable; 1: Enable\r
+  UINT8 Azalia            : 2;    /// 0: Disable; 1: Enable; 2: Auto\r
+  UINT8 Sata              : 1;    /// 0: Disable; 1: Enable\r
+  UINT8 Smbus             : 1;    /// 0: Disable; 1: Enable\r
+  UINT8 LpeEnabled        : 2;    /// 0: Disabled; 1: PCI Mode 2: ACPI Mode\r
+  UINT8 Reserved[1];              /// Reserved fields for future expansion w/o protocol change\r
+} PCH_DEVICE_ENABLING;\r
+\r
+///\r
+/// ---------------------------- USB Config -----------------------------\r
+///\r
+///\r
+/// Overcurrent pins\r
+///\r
+typedef enum {\r
+  PchUsbOverCurrentPin0 = 0,\r
+  PchUsbOverCurrentPin1,\r
+  PchUsbOverCurrentPin2,\r
+  PchUsbOverCurrentPin3,\r
+  PchUsbOverCurrentPin4,\r
+  PchUsbOverCurrentPin5,\r
+  PchUsbOverCurrentPin6,\r
+  PchUsbOverCurrentPin7,\r
+  PchUsbOverCurrentPinSkip,\r
+  PchUsbOverCurrentPinMax\r
+} PCH_USB_OVERCURRENT_PIN;\r
+\r
+typedef struct {\r
+  UINT8   Enable            : 1;    /// 0: Disable; 1: Enable. This would take effect while UsbPerPortCtl is enabled\r
+  UINT8   Panel             : 1;    /// 0: Back Panel Port; 1: Front Panel Port.\r
+  UINT8   Dock              : 1;    /// 0: Not docking port; 1: Docking Port.\r
+  UINT8   Rsvdbits          : 5;\r
+} PCH_USB_PORT_SETTINGS;\r
+\r
+typedef struct {\r
+  UINT8 Enable              : 1;    /// 0: Disable; 1: Enable\r
+  UINT8 Rsvdbits            : 7;\r
+} PCH_USB20_CONTROLLER_SETTINGS;\r
+\r
+typedef struct {\r
+  UINT8 Enable              : 2;    /// 0: 0: Disabled; 1: PCI Mode 2: ACPI Mode\r
+  UINT8 Rsvdbits            : 6;\r
+} PCH_USBOTG_CONTROLLER_SETTINGS;\r
+\r
+#define PCH_XHCI_MODE_OFF         0\r
+#define PCH_XHCI_MODE_ON          1\r
+#define PCH_XHCI_MODE_AUTO        2\r
+#define PCH_XHCI_MODE_SMARTAUTO   3\r
+\r
+#define PCH_EHCI_DEBUG_OFF        0\r
+#define PCH_EHCI_DEBUG_ON         1\r
+\r
+#define PCH_USB_FRONT_PANEL       1\r
+#define PCH_USB_BACK_PANEL        0\r
+\r
+typedef struct {\r
+  UINT8 Mode               : 2;    /// 0: Disable; 1: Enable, 2: Auto, 3: Smart Auto\r
+  UINT8 PreBootSupport     : 1;    /// 0: No xHCI driver available; 1: xHCI driver available\r
+  UINT8 XhciStreams        : 1;    /// 0: Disable; 1: Enable\r
+  UINT8 Rsvdbits           : 4;\r
+} PCH_USB30_CONTROLLER_SETTINGS;\r
+\r
+typedef struct {\r
+  UINT8 UsbPerPortCtl       : 1;    /// 0: Disable; 1: Enable Per-port enable control\r
+  UINT8 Ehci1Usbr           : 1;    /// 0: Disable; 1: Enable EHCI 1 USBR\r
+  UINT8 RsvdBits            : 6;\r
+  PCH_USB_PORT_SETTINGS          PortSettings[PCH_USB_MAX_PHYSICAL_PORTS];\r
+  PCH_USB20_CONTROLLER_SETTINGS  Usb20Settings[PchEhciControllerMax];\r
+  PCH_USB30_CONTROLLER_SETTINGS  Usb30Settings;\r
+  PCH_USBOTG_CONTROLLER_SETTINGS UsbOtgSettings;\r
+  PCH_USB_OVERCURRENT_PIN        Usb20OverCurrentPins[PCH_USB_MAX_PHYSICAL_PORTS];\r
+  PCH_USB_OVERCURRENT_PIN        Usb30OverCurrentPins[PCH_XHCI_MAX_USB3_PORTS];\r
+  ///\r
+  /// The length of Usb Port to configure the USB transmitter,\r
+  /// Bits [16:4] represents length of Usb Port in inches using octal format and [3:0] is for the decimal Point.\r
+  ///\r
+  UINT16                        Usb20PortLength[PCH_EHCI_MAX_PORTS];\r
+  UINT16                        EhciDebug;\r
+  UINT16                        UsbXhciLpmSupport;\r
+\r
+} PCH_USB_CONFIG;\r
+\r
+///\r
+/// ---------------------------- PCI Express Config ----------------------\r
+///\r
+/// The values before AutoConfig match the setting of PCI Express Base Specification 1.1, please be careful for adding new feature\r
+///\r
+typedef enum {\r
+  PchPcieAspmDisabled,\r
+  PchPcieAspmL0s,\r
+  PchPcieAspmL1,\r
+  PchPcieAspmL0sL1,\r
+  PchPcieAspmAutoConfig,\r
+  PchPcieAspmMax\r
+} PCH_PCI_EXPRESS_ASPM_CONTROL;\r
+\r
+///\r
+/// Refer to PCH EDS for the PCH implementation values corresponding\r
+/// to below PCI-E spec defined ranges\r
+///\r
+typedef enum {\r
+  PchPciECompletionTO_Default,\r
+  PchPciECompletionTO_50_100us,\r
+  PchPciECompletionTO_1_10ms,\r
+  PchPciECompletionTO_16_55ms,\r
+  PchPciECompletionTO_65_210ms,\r
+  PchPciECompletionTO_260_900ms,\r
+  PchPciECompletionTO_1_3P5s,\r
+  PchPciECompletionTO_4_13s,\r
+  PchPciECompletionTO_17_64s,\r
+  PchPciECompletionTO_Disabled\r
+} PCH_PCIE_COMPLETION_TIMEOUT;\r
+\r
+typedef struct {\r
+  UINT8 Enable                          : 1;    /// Root Port enabling, 0: Disable; 1: Enable.\r
+  UINT8 Hide                            : 1;    /// Whether or not to hide the configuration space of this port\r
+  UINT8 SlotImplemented                 : 1;\r
+  UINT8 HotPlug                         : 1;\r
+  UINT8 PmSci                           : 1;\r
+  UINT8 ExtSync                         : 1;    /// Extended Synch\r
+  UINT8 Rsvdbits                        : 2;\r
+  ///\r
+  /// Error handlings\r
+  ///\r
+  UINT8 UnsupportedRequestReport        : 1;\r
+  UINT8 FatalErrorReport                : 1;\r
+  UINT8 NoFatalErrorReport              : 1;\r
+  UINT8 CorrectableErrorReport          : 1;\r
+  UINT8 PmeInterrupt                    : 1;\r
+  UINT8 SystemErrorOnFatalError         : 1;\r
+  UINT8 SystemErrorOnNonFatalError      : 1;\r
+  UINT8 SystemErrorOnCorrectableError   : 1;\r
+\r
+  UINT8 AdvancedErrorReporting          : 1;\r
+  UINT8 TransmitterHalfSwing            : 1;\r
+  UINT8 Reserved                        : 6;    /// Reserved fields for future expansion w/o protocol change\r
+\r
+  UINT8 FunctionNumber;                         /// The function number this root port is mapped to.\r
+  UINT8 PhysicalSlotNumber;\r
+  PCH_PCIE_COMPLETION_TIMEOUT   CompletionTimeout;\r
+  PCH_PCI_EXPRESS_ASPM_CONTROL  Aspm;\r
+} PCH_PCI_EXPRESS_ROOT_PORT_CONFIG;\r
+\r
+typedef struct {\r
+  /**\r
+    VendorId\r
+\r
+      The vendor Id of Pci Express card ASPM setting override, 0xFFFF means any Vendor ID\r
+\r
+    DeviceId\r
+\r
+      The Device Id of Pci Express card ASPM setting override, 0xFFFF means any Device ID\r
+\r
+    RevId\r
+\r
+      The Rev Id of Pci Express card ASPM setting override, 0xFF means all steppings\r
+\r
+    BaseClassCode\r
+\r
+      The Base Class Code of Pci Express card ASPM setting override, 0xFF means all base class\r
+\r
+    SubClassCode\r
+\r
+      The Sub Class Code of Pci Express card ASPM setting override, 0xFF means all sub class\r
+\r
+\r
+    EndPointAspm\r
+\r
+      The override ASPM setting from End point\r
+  **/\r
+  UINT16                        VendorId;\r
+  UINT16                        DeviceId;\r
+  UINT8                         RevId;\r
+  UINT8                         BaseClassCode;\r
+  UINT8                         SubClassCode;\r
+  PCH_PCI_EXPRESS_ASPM_CONTROL  EndPointAspm;\r
+} PCH_PCIE_DEVICE_ASPM_OVERRIDE;\r
+\r
+typedef struct {\r
+  UINT16  VendorId; ///< PCI configuration space offset 0\r
+  UINT16  DeviceId; ///< PCI configuration space offset 2\r
+  UINT8   RevId;    ///< PCI configuration space offset 8; 0xFF means all steppings\r
+  /**\r
+    SnoopLatency bit definition\r
+    Note: All Reserved bits must be set to 0\r
+\r
+    BIT[15]     - When set to 1b, indicates that the values in bits 9:0 are valid\r
+                  When clear values in bits 9:0 will be ignored\r
+    BITS[14:13] - Reserved\r
+    BITS[12:10] - Value in bits 9:0 will be multiplied with the scale in these bits\r
+                  000b - 1 ns\r
+                  001b - 32 ns\r
+                  010b - 1024 ns\r
+                  011b - 32,768 ns\r
+                  100b - 1,048,576 ns\r
+                  101b - 33,554,432 ns\r
+                  110b - Reserved\r
+                  111b - Reserved\r
+    BITS[9:0]   - Snoop Latency Value. The value in these bits will be multiplied with\r
+                  the scale in bits 12:10\r
+  **/\r
+  UINT16  SnoopLatency;\r
+  /**\r
+    NonSnoopLatency bit definition\r
+    Note: All Reserved bits must be set to 0\r
+\r
+    BIT[15]     - When set to 1b, indicates that the values in bits 9:0 are valid\r
+                  When clear values in bits 9:0 will be ignored\r
+    BITS[14:13] - Reserved\r
+    BITS[12:10] - Value in bits 9:0 will be multiplied with the scale in these bits\r
+                  000b - 1 ns\r
+                  001b - 32 ns\r
+                  010b - 1024 ns\r
+                  011b - 32,768 ns\r
+                  100b - 1,048,576 ns\r
+                  101b - 33,554,432 ns\r
+                  110b - Reserved\r
+                  111b - Reserved\r
+    BITS[9:0]   - Non Snoop Latency Value. The value in these bits will be multiplied with\r
+                  the scale in bits 12:10\r
+  **/\r
+  UINT16  NonSnoopLatency;\r
+} PCH_PCIE_DEVICE_LTR_OVERRIDE;\r
+\r
+typedef struct {\r
+  ///\r
+  /// Temp Bus Number range available to be assigned to\r
+  /// each root port and its downstream devices for initialization\r
+  /// of these devices before PCI Bus enumeration\r
+  ///\r
+  UINT8                             TempRootPortBusNumMin;\r
+  UINT8                             TempRootPortBusNumMax;\r
+  PCH_PCI_EXPRESS_ROOT_PORT_CONFIG  RootPort[PCH_PCIE_MAX_ROOT_PORTS];\r
+  BOOLEAN                           RootPortClockGating;\r
+  UINT8                             NumOfDevAspmOverride;     /// Number of PCI Express card Aspm setting override\r
+  PCH_PCIE_DEVICE_ASPM_OVERRIDE     *DevAspmOverride;         /// The Pointer which is point to Pci Express card Aspm setting override\r
+  UINT8                             PcieDynamicGating;        /// Need PMC enable it first from PMC 0x3_12 MCU 318.\r
+} PCH_PCI_EXPRESS_CONFIG;\r
+\r
+\r
+///\r
+/// ---------------------------- SATA Config -----------------------------\r
+///\r
+typedef enum {\r
+  PchSataSpeedSupportGen1 = 1,\r
+  PchSataSpeedSupportGen2\r
+} PCH_SATA_SPEED_SUPPORT;\r
+\r
+typedef struct {\r
+  UINT8 Enable          : 1;    /// 0: Disable; 1: Enable\r
+  UINT8 HotPlug         : 1;    /// 0: Disable; 1: Enable\r
+  UINT8 MechSw          : 1;    /// 0: Disable; 1: Enable\r
+  UINT8 External        : 1;    /// 0: Disable; 1: Enable\r
+  UINT8 SpinUp          : 1;    /// 0: Disable; 1: Enable the COMRESET initialization Sequence to the device\r
+  UINT8 Rsvdbits        : 3;    /// Reserved fields for future expansion w/o protocol change\r
+} PCH_SATA_PORT_SETTINGS;\r
+\r
+typedef struct {\r
+  PCH_SATA_PORT_SETTINGS  PortSettings[PCH_AHCI_MAX_PORTS];\r
+  UINT8 RaidAlternateId : 1;    /// 0: Disable; 1: Enable\r
+  UINT8 Raid0           : 1;    /// 0: Disable; 1: Enable RAID0\r
+  UINT8 Raid1           : 1;    /// 0: Disable; 1: Enable RAID1\r
+  UINT8 Raid10          : 1;    /// 0: Disable; 1: Enable RAID10\r
+  UINT8 Raid5           : 1;    /// 0: Disable; 1: Enable RAID5\r
+  UINT8 Irrt            : 1;    /// 0: Disable; 1: Enable Intel Rapid Recovery Technology\r
+  UINT8 OromUiBanner    : 1;    /// 0: Disable; 1: Enable OROM UI and BANNER\r
+  UINT8 HddUnlock       : 1;    /// 0: Disable; 1: Indicates that the HDD password unlock in the OS is enabled\r
+\r
+  UINT8 LedLocate       : 1;    /// 0: Disable; 1: Indicates that the LED/SGPIO hardware is attached and ping to locate feature is enabled on the OS\r
+  UINT8 IrrtOnly        : 1;    /// 0: Disable; 1: Allow only IRRT drives to span internal and external ports\r
+  UINT8 TestMode        : 1;    /// 0: Disable; 1: Allow entrance to the PCH SATA test modes\r
+  UINT8 SalpSupport     : 1;    /// 0: Disable; 1: Enable Aggressive Link Power Management\r
+  UINT8 LegacyMode      : 1;    /// 0: Native PCI mode; 1: Legacy mode, when SATA controller is operating in IDE mode\r
+  UINT8 SpeedSupport    : 4;    /// Indicates the maximum speed the SATA controller can support\r
+  /// 1h: 1.5 Gb/s (Gen 1); 2h: 3 Gb/s(Gen 2)\r
+\r
+  UINT8 Rsvdbits        : 7;    // Reserved fields for future expansion w/o protocol change\r
+} PCH_SATA_CONFIG;\r
+///\r
+/// --------------------------- AZALIA Config ------------------------------\r
+///\r
+typedef struct {\r
+  UINT32  VendorDeviceId;\r
+  UINT16  SubSystemId;\r
+  UINT8   RevisionId;                       /// 0xFF applies to all steppings\r
+  UINT8   FrontPanelSupport;\r
+  UINT16  NumberOfRearJacks;\r
+  UINT16  NumberOfFrontJacks;\r
+} PCH_AZALIA_VERB_TABLE_HEADER;\r
+\r
+typedef struct {\r
+  PCH_AZALIA_VERB_TABLE_HEADER  VerbTableHeader;\r
+  UINT32                        *VerbTableData;\r
+} PCH_AZALIA_VERB_TABLE;\r
+\r
+typedef struct {\r
+  UINT8                 Pme       : 1;      /// 0: Disable; 1: Enable\r
+  UINT8                 DS        : 1;      /// 0: Docking is not supported; 1:Docking is supported\r
+  UINT8                 DA        : 1;      /// 0: Docking is not attached; 1:Docking is attached\r
+  UINT8                 HdmiCodec : 1;      /// 0: Disable; 1: Enable\r
+  UINT8                 AzaliaVCi : 1;      /// 0: Disable; 1: Enable\r
+  UINT8                 Rsvdbits  : 3;\r
+  UINT8                 AzaliaVerbTableNum; /// Number of verb tables provided by platform\r
+  PCH_AZALIA_VERB_TABLE *AzaliaVerbTable;   /// Pointer to the actual verb table(s)\r
+  UINT16                ResetWaitTimer;     /// The delay timer after Azalia reset, the value is number of microseconds\r
+} PCH_AZALIA_CONFIG;\r
+\r
+///\r
+/// --------------------------- Smbus Config ------------------------------\r
+///\r
+typedef struct {\r
+  UINT8 NumRsvdSmbusAddresses;\r
+  UINT8 *RsvdSmbusAddressTable;\r
+} PCH_SMBUS_CONFIG;\r
+\r
+///\r
+/// --------------------------- Miscellaneous PM Config ------------------------------\r
+///\r
+typedef struct {\r
+  UINT8 MeWakeSts           : 1;\r
+  UINT8 MeHrstColdSts       : 1;\r
+  UINT8 MeHrstWarmSts       : 1;\r
+  UINT8 MeHostPowerDn       : 1;\r
+  UINT8 WolOvrWkSts         : 1;\r
+  UINT8 Rsvdbits            : 3;\r
+} PCH_POWER_RESET_STATUS;\r
+\r
+typedef struct {\r
+  UINT8  PmeB0S5Dis         : 1;\r
+  UINT8  WolEnableOverride  : 1;\r
+  UINT8  Rsvdbits           : 6;\r
+} PCH_WAKE_CONFIG;\r
+\r
+typedef enum {\r
+  PchSlpS360us,\r
+  PchSlpS31ms,\r
+  PchSlpS350ms,\r
+  PchSlpS32s\r
+} PCH_SLP_S3_MIN_ASSERT;\r
+\r
+typedef enum {\r
+  PchSlpS4PchTime,   /// The time defined in EDS Power Sequencing and Reset Signal Timings table\r
+  PchSlpS41s,\r
+  PchSlpS42s,\r
+  PchSlpS43s,\r
+  PchSlpS44s\r
+} PCH_SLP_S4_MIN_ASSERT;\r
+\r
+typedef struct {\r
+  ///\r
+  /// Specify which Power/Reset bits need to be cleared by\r
+  /// the PCH Init Driver.\r
+  /// Usually platform drivers take care of these bits, but if\r
+  /// not, let PCH Init driver clear the bits.\r
+  ///\r
+  PCH_POWER_RESET_STATUS  PowerResetStatusClear;\r
+  ///\r
+  /// Specify Wake Policy\r
+  ///\r
+  PCH_WAKE_CONFIG         WakeConfig;\r
+  ///\r
+  /// SLP_XX Minimum Assertion Width Policy\r
+  ///\r
+  PCH_SLP_S3_MIN_ASSERT   PchSlpS3MinAssert;\r
+  PCH_SLP_S4_MIN_ASSERT   PchSlpS4MinAssert;\r
+  UINT8                   SlpStrchSusUp : 1;  /// Enable/Disable SLP_X Stretching After SUS Well Power Up\r
+  UINT8                   SlpLanLowDc   : 1;\r
+  UINT8                   Rsvdbits      : 6;\r
+} PCH_MISC_PM_CONFIG;\r
+\r
+///\r
+/// --------------------------- Subsystem Vendor ID / Subsystem ID Config -----\r
+///\r
+typedef struct {\r
+  UINT16  SubSystemVendorId;\r
+  UINT16  SubSystemId;\r
+} PCH_DEFAULT_SVID_SID;\r
+\r
+///\r
+/// --------------------------- Lock Down Config ------------------------------\r
+///\r
+typedef struct {\r
+  UINT8  GlobalSmi      : 1;\r
+  UINT8  BiosInterface  : 1;\r
+  UINT8  RtcLock        : 1;\r
+  UINT8  BiosLock       : 1;\r
+  UINT8  Rsvdbits       : 4;\r
+  UINT8  PchBiosLockSwSmiNumber;\r
+} PCH_LOCK_DOWN_CONFIG;\r
+//\r
+// --------------------------- Serial IRQ Config ------------------------------\r
+//\r
+typedef enum {\r
+  PchQuietMode,\r
+  PchContinuousMode\r
+} PCH_SIRQ_MODE;\r
+///\r
+/// Refer to SoC EDS for the details of Start Frame Pulse Width in Continuous and Quiet mode\r
+///\r
+\r
+typedef struct {\r
+  BOOLEAN                 SirqEnable;       /// Determines if enable Serial IRQ\r
+  PCH_SIRQ_MODE           SirqMode;         /// Serial IRQ Mode Select\r
+} PCH_LPC_SIRQ_CONFIG;\r
+\r
+///\r
+/// --------------------------- Power Optimizer Config ------------------------------\r
+///\r
+typedef struct {\r
+  UINT8  NumOfDevLtrOverride;                            /// Number of Pci Express card listed in LTR override table\r
+  PCH_PCIE_DEVICE_LTR_OVERRIDE *DevLtrOverride;          /// Pointer to Pci Express devices LTR override table\r
+} PCH_PWR_OPT_CONFIG;\r
+\r
+///\r
+/// --------------------- Low Power Input Output Config ------------------------\r
+///\r
+typedef struct {\r
+  UINT8                   LpssPciModeEnabled    : 1;    /// Determines if LPSS PCI Mode enabled\r
+  UINT8                   Dma0Enabled           : 1;     /// Determines if LPSS DMA1 enabled\r
+  UINT8                   Dma1Enabled           : 1;     /// Determines if LPSS DMA2 enabled\r
+  UINT8                   I2C0Enabled           : 1;     /// Determines if LPSS I2C #1 enabled\r
+  UINT8                   I2C1Enabled           : 1;     /// Determines if LPSS I2C #2 enabled\r
+  UINT8                   I2C2Enabled           : 1;     /// Determines if LPSS I2C #3 enabled\r
+  UINT8                   I2C3Enabled           : 1;     /// Determines if LPSS I2C #4 enabled\r
+  UINT8                   I2C4Enabled           : 1;     /// Determines if LPSS I2C #5 enabled\r
+  UINT8                   I2C5Enabled           : 1;     /// Determines if LPSS I2C #6 enabled\r
+  UINT8                   I2C6Enabled           : 1;     /// Determines if LPSS I2C #7 enabled\r
+  UINT8                   Pwm0Enabled           : 1;     /// Determines if LPSS PWM #1 enabled\r
+  UINT8                   Pwm1Enabled           : 1;     /// Determines if LPSS PWM #2 enabled\r
+  UINT8                   Hsuart0Enabled        : 1;     /// Determines if LPSS HSUART #1 enabled\r
+  UINT8                   Hsuart1Enabled        : 1;     /// Determines if LPSS HSUART #2 enabled\r
+  UINT8                   SpiEnabled            : 1;     /// Determines if LPSS SPI enabled\r
+  UINT8                   Rsvdbits              : 2;\r
+} PCH_LPSS_CONFIG;\r
+\r
+///\r
+/// ----------------------------- SCC Config --------------------------------\r
+///\r
+typedef struct {\r
+  UINT8                   eMMCEnabled           : 1;      /// Determines if SCC eMMC enabled\r
+  UINT8                   SdioEnabled           : 1;      /// Determines if SCC SDIO enabled\r
+  UINT8                   SdcardEnabled         : 1;      /// Determines if SCC SD Card enabled\r
+  UINT8                   HsiEnabled            : 1;      /// Determines if SCC HSI enabled\r
+  UINT8                   eMMC45Enabled         : 1;      /// Determines if SCC eMMC 4.5 enabled\r
+  UINT8                   eMMC45DDR50Enabled    : 1;  /// Determines if DDR50 enabled for eMMC 4.5\r
+  UINT8                   eMMC45HS200Enabled    : 1;  /// Determines if HS200nabled for eMMC 4.5\r
+  UINT8                   Rsvdbits              : 1;\r
+  UINT8                   SdCardSDR25Enabled    : 1;    /// Determines if SDR25 for SD Card\r
+  UINT8                   SdCardDDR50Enabled    : 1;    /// Determines if DDR50 for SD Card\r
+  UINT8                   Rsvdbits1             : 6;\r
+  UINT8                   eMMC45RetuneTimerValue;  /// Determines retune timer value.\r
+} PCH_SCC_CONFIG;\r
+\r
+///\r
+/// ------------ General PCH Platform Policy protocol definition ------------\r
+///\r
+struct _DXE_PCH_PLATFORM_POLICY_PROTOCOL {\r
+  UINT8                   Revision;\r
+  UINT8                   BusNumber;  /// PCI Bus Number of the PCH device\r
+  PCH_DEVICE_ENABLING     *DeviceEnabling;\r
+  PCH_USB_CONFIG          *UsbConfig;\r
+  PCH_PCI_EXPRESS_CONFIG  *PciExpressConfig;\r
+\r
+  PCH_SATA_CONFIG         *SataConfig;\r
+  PCH_AZALIA_CONFIG       *AzaliaConfig;\r
+  PCH_SMBUS_CONFIG        *SmbusConfig;\r
+  PCH_MISC_PM_CONFIG      *MiscPmConfig;\r
+  PCH_DEFAULT_SVID_SID    *DefaultSvidSid;\r
+  PCH_LOCK_DOWN_CONFIG    *LockDownConfig;\r
+  PCH_LPC_SIRQ_CONFIG     *SerialIrqConfig;\r
+  PCH_PWR_OPT_CONFIG      *PwrOptConfig;\r
+  PCH_LPSS_CONFIG         *LpssConfig;\r
+  PCH_SCC_CONFIG          *SccConfig;\r
+  UINT8                   IdleReserve;\r
+  UINT8                   EhciPllCfgEnable;\r
+  UINT8                   AcpiHWRed; //Hardware Reduced Mode\r
+};\r
+\r
+#endif\r

diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/PchReset.h b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/PchReset.h
new file mode 100644 (file)
index 0000000..45e2860
--- /dev/null
+++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/PchReset.h
@@ -0,0 +1,120 @@
+/**\r
+**/\r
+/**\r
+\r
+Copyright (c) 2011  - 2014, Intel Corporation. All rights reserved\r
+\r
+  This program and the accompanying materials are licensed and made available under\r
+  the terms and conditions of the BSD License that accompanies this distribution.\r
+  The full text of the license may be found at\r
+  http://opensource.org/licenses/bsd-license.php.\r
+\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+\r
+  @file\r
+  PchReset.h\r
+\r
+  @brief\r
+  PCH Reset Protocol\r
+\r
+**/\r
+#ifndef _PCH_RESET_H_\r
+#define _PCH_RESET_H_\r
+\r
+\r
+//\r
+#define PCH_RESET_PROTOCOL_GUID \\r
+  { \\r
+    0xdb63592c, 0xb8cc, 0x44c8, 0x91, 0x8c, 0x51, 0xf5, 0x34, 0x59, 0x8a, 0x5a \\r
+  }\r
+#define PCH_RESET_CALLBACK_PROTOCOL_GUID \\r
+  { \\r
+    0x3a3300ab, 0xc929, 0x487d, 0xab, 0x34, 0x15, 0x9b, 0xc1, 0x35, 0x62, 0xc0 \\r
+  }\r
+extern EFI_GUID                             gPchResetProtocolGuid;\r
+extern EFI_GUID                             gPchResetCallbackProtocolGuid;\r
+\r
+///\r
+/// Forward reference for ANSI C compatibility\r
+///\r
+typedef struct _PCH_RESET_PROTOCOL          PCH_RESET_PROTOCOL;\r
+\r
+typedef struct _PCH_RESET_CALLBACK_PROTOCOL PCH_RESET_CALLBACK_PROTOCOL;\r
+\r
+///\r
+/// Related Definitions\r
+///\r
+///\r
+/// PCH Reset Types\r
+///\r
+typedef enum {\r
+  ColdReset,\r
+  WarmReset,\r
+  ShutdownReset,\r
+  PowerCycleReset,\r
+  GlobalReset,\r
+  GlobalResetWithEc\r
+} PCH_RESET_TYPE;\r
+\r
+///\r
+/// Member functions\r
+///\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *PCH_RESET) (\r
+  IN     PCH_RESET_PROTOCOL       * This,\r
+  IN     PCH_RESET_TYPE           PchResetType\r
+  )\r
+/**\r
+\r
+  @brief\r
+  Execute Pch Reset from the host controller.\r
+\r
+  @param[in] This                 Pointer to the PCH_RESET_PROTOCOL instance.\r
+  @param[in] PchResetType         Pch Reset Types which includes ColdReset, WarmReset, ShutdownReset,\r
+                                  PowerCycleReset, GlobalReset, GlobalResetWithEc\r
+\r
+  @retval EFI_SUCCESS             Successfully completed.\r
+  @retval EFI_INVALID_PARAMETER   If ResetType is invalid.\r
+\r
+**/\r
+;\r
+\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *PCH_RESET_CALLBACK) (\r
+  IN     PCH_RESET_TYPE           PchResetType\r
+  )\r
+/**\r
+\r
+  @brief\r
+  Execute call back function for Pch Reset.\r
+\r
+  @param[in] PchResetType         Pch Reset Types which includes PowerCycle, Globalreset.\r
+\r
+  @retval EFI_SUCCESS             The callback function has been done successfully\r
+  @retval EFI_NOT_FOUND           Failed to find Pch Reset Callback protocol. Or, none of\r
+                                  callback protocol is installed.\r
+  @retval Others                  Do not do any reset from PCH\r
+\r
+**/\r
+;\r
+\r
+///\r
+/// Interface structure for the Pch Reset Protocol\r
+///\r
+struct _PCH_RESET_PROTOCOL {\r
+  PCH_RESET Reset;\r
+};\r
+\r
+///\r
+/// PCH_RESET_CALLBACK_PROTOCOL Structure Definition\r
+///\r
+struct _PCH_RESET_CALLBACK_PROTOCOL {\r
+  PCH_RESET_CALLBACK  ResetCallback;\r
+};\r
+\r
+#endif\r

diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/PchS3Support.h b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/PchS3Support.h
new file mode 100644 (file)
index 0000000..ca263c6
--- /dev/null
+++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/PchS3Support.h
@@ -0,0 +1,138 @@
+/**\r
+**/\r
+/**\r
+\r
+Copyright (c) 2012  - 2014, Intel Corporation. All rights reserved\r
+\r
+  This program and the accompanying materials are licensed and made available under\r
+  the terms and conditions of the BSD License that accompanies this distribution.\r
+  The full text of the license may be found at\r
+  http://opensource.org/licenses/bsd-license.php.\r
+\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+\r
+  @file\r
+  PchS3Support.h\r
+\r
+  @brief\r
+  This file defines the PCH S3 support Protocol.\r
+\r
+**/\r
+#ifndef _PCH_S3_SUPPORT_PROTOCOL_H_\r
+#define _PCH_S3_SUPPORT_PROTOCOL_H_\r
+\r
+#ifndef ECP_FLAG\r
+#include <Pi/PiS3BootScript.h>\r
+#endif\r
+\r
+#define EFI_PCH_S3_SUPPORT_PROTOCOL_GUID \\r
+  { \\r
+    0xe287d20b, 0xd897, 0x4e1e, 0xa5, 0xd9, 0x97, 0x77, 0x63, 0x93, 0x6a, 0x4 \\r
+  }\r
+\r
+#include <Protocol/PchPlatformPolicy.h>\r
+\r
+///\r
+/// Extern the GUID for protocol users.\r
+///\r
+extern EFI_GUID                             gEfiPchS3SupportProtocolGuid;\r
+\r
+///\r
+/// Forward reference for ANSI C compatibility\r
+///\r
+typedef struct _EFI_PCH_S3_SUPPORT_PROTOCOL EFI_PCH_S3_SUPPORT_PROTOCOL;\r
+\r
+typedef enum {\r
+  PchS3ItemTypeSendCodecCommand,\r
+  PchS3ItemTypePollStatus,\r
+  PchS3ItemTypeInitPcieRootPortDownstream,\r
+  PchS3ItemTypePcieSetPm,\r
+  PchS3ItemTypePmTimerStall,\r
+  PchS3ItemTypeMax\r
+} EFI_PCH_S3_DISPATCH_ITEM_TYPE;\r
+\r
+///\r
+/// It's better not to use pointer here because the size of pointer in DXE is 8, but it's 4 in PEI\r
+/// plug 4 to ParameterSize in PEIM if you really need it\r
+///\r
+typedef struct {\r
+  UINT32                        HdaBar;\r
+  UINT32                        CodecCmdData;\r
+} EFI_PCH_S3_PARAMETER_SEND_CODEC_COMMAND;\r
+\r
+typedef struct {\r
+  UINT64                        MmioAddress;\r
+  EFI_BOOT_SCRIPT_WIDTH         Width;\r
+  UINT64                        Mask;\r
+  UINT64                        Value;\r
+  UINT32                        Timeout;  // us\r
+} EFI_PCH_S3_PARAMETER_POLL_STATUS;\r
+\r
+typedef struct {\r
+  UINT8                         RootPortBus;\r
+  UINT8                         RootPortDevice;\r
+  UINT8                         RootPortFunc;\r
+  UINT8                         TempBusNumberMin;\r
+  UINT8                         TempBusNumberMax;\r
+} EFI_PCH_S3_PARAMETER_INIT_PCIE_ROOT_PORT_DOWNSTREAM;\r
+\r
+typedef struct {\r
+  UINT8                         RootPortBus;\r
+  UINT8                         RootPortDevice;\r
+  UINT8                         RootPortFunc;\r
+  PCH_PCI_EXPRESS_ASPM_CONTROL  RootPortAspm;\r
+  UINT8                         NumOfDevAspmOverride;\r
+  UINT32                        DevAspmOverrideAddr;\r
+  UINT8                         TempBusNumberMin;\r
+  UINT8                         TempBusNumberMax;\r
+  UINT8                         NumOfDevLtrOverride;\r
+  UINT32                        DevLtrOverrideAddr;\r
+} EFI_PCH_S3_PARAMETER_PCIE_SET_PM;\r
+\r
+typedef struct {\r
+  UINT32                        DelayTime;  // us\r
+} EFI_PCH_S3_PARAMETER_PM_TIMER_STALL;\r
+\r
+typedef struct {\r
+  EFI_PCH_S3_DISPATCH_ITEM_TYPE Type;\r
+  VOID                          *Parameter;\r
+} EFI_PCH_S3_DISPATCH_ITEM;\r
+\r
+///\r
+/// Member functions\r
+///\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *EFI_PCH_S3_SUPPORT_SET_S3_DISPATCH_ITEM) (\r
+  IN     EFI_PCH_S3_SUPPORT_PROTOCOL   * This,\r
+  IN     EFI_PCH_S3_DISPATCH_ITEM      * DispatchItem,\r
+  OUT    EFI_PHYSICAL_ADDRESS          * S3DispatchEntryPoint\r
+  );\r
+\r
+/**\r
+\r
+  @brief\r
+  Set an item to be dispatched at S3 resume time. At the same time, the entry point\r
+  of the PCH S3 support image is returned to be used in subsequent boot script save\r
+  call\r
+\r
+  @param[in] This                 Pointer to the protocol instance.\r
+  @param[in] DispatchItem         The item to be dispatched.\r
+  @param[in] S3DispatchEntryPoint The entry point of the PCH S3 support image.\r
+\r
+  @retval EFI_STATUS              Successfully completed.\r
+  @retval EFI_OUT_OF_RESOURCES    Out of resources.\r
+\r
+**/\r
+\r
+///\r
+/// Protocol definition\r
+///\r
+struct _EFI_PCH_S3_SUPPORT_PROTOCOL {\r
+  EFI_PCH_S3_SUPPORT_SET_S3_DISPATCH_ITEM SetDispatchItem;\r
+};\r
+\r
+#endif\r

diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/SdHostIo.h b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/SdHostIo.h
new file mode 100644 (file)
index 0000000..6f6dd34
--- /dev/null
+++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/SdHostIo.h
@@ -0,0 +1,415 @@
+/*++\r
+\r
+Copyright (c)  1999  - 2014, Intel Corporation. All rights reserved\r
+\r
+  This program and the accompanying materials are licensed and made available under\r
+  the terms and conditions of the BSD License that accompanies this distribution.\r
+  The full text of the license may be found at\r
+  http://opensource.org/licenses/bsd-license.php.\r
+\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+--*/\r
+\r
+\r
+/*++\r
+Module Name:\r
+\r
+  SdHostIo.h\r
+\r
+Abstract:\r
+\r
+  Interface definition for EFI_SD_HOST_IO_PROTOCOL\r
+\r
+--*/\r
+\r
+#ifndef _SD_HOST_IO_H\r
+#define _SD_HOST_IO_H\r
+\r
+\r
+// Global ID for the EFI_SD_HOST_IO_PROTOCOL\r
+// {B63F8EC7-A9C9-4472-A4C0-4D8BF365CC51}\r
+//\r
+#define EFI_SD_HOST_IO_PROTOCOL_GUID \\r
+  { 0xb63f8ec7, 0xa9c9, 0x4472, { 0xa4, 0xc0, 0x4d, 0x8b, 0xf3, 0x65, 0xcc, 0x51 } }\r
+\r
+typedef struct _EFI_SD_HOST_IO_PROTOCOL EFI_SD_HOST_IO_PROTOCOL;\r
+\r
+//\r
+// TODO: Move to Pci22.h\r
+//\r
+#define PCI_SUBCLASS_SD_HOST_CONTROLLER   0x05\r
+#define PCI_IF_STANDARD_HOST_NO_DMA       0x00\r
+#define PCI_IF_STANDARD_HOST_SUPPORT_DMA  0x01\r
+\r
+//\r
+// TODO: Retire\r
+//\r
+#define EFI_SD_HOST_IO_PROTOCOL_REVISION_01          0x01\r
+\r
+//\r
+// TODO: Do these belong in an Industry Standard include file?\r
+//\r
+// MMIO Registers definition for MMC/SDIO controller\r
+//\r
+#define  MMIO_DMAADR                     0x00\r
+#define  MMIO_BLKSZ                      0x04\r
+#define  MMIO_BLKCNT                     0x06\r
+#define  MMIO_CMDARG                     0x08\r
+#define  MMIO_XFRMODE                    0x0C\r
+#define  MMIO_SDCMD                      0x0E\r
+#define  MMIO_RESP                       0x10\r
+#define  MMIO_BUFDATA                    0x20\r
+#define  MMIO_PSTATE                     0x24\r
+#define  MMIO_HOSTCTL                    0x28\r
+#define  MMIO_PWRCTL                     0x29\r
+#define  MMIO_BLKGAPCTL                  0x2A\r
+#define  MMIO_WAKECTL                    0x2B\r
+#define  MMIO_CLKCTL                     0x2C\r
+#define  MMIO_TOCTL                      0x2E\r
+#define  MMIO_SWRST                      0x2F\r
+#define  MMIO_NINTSTS                    0x30\r
+#define  MMIO_ERINTSTS                   0x32\r
+#define  MMIO_NINTEN                     0x34\r
+#define  MMIO_ERINTEN                    0x36\r
+#define  MMIO_NINTSIGEN                  0x38\r
+#define  MMIO_ERINTSIGEN                 0x3A\r
+#define  MMIO_AC12ERRSTS                 0x3C\r
+#define  MMIO_HOST_CTL2                  0x3E //hphang <- New in VLV2\r
+#define  MMIO_CAP                        0x40\r
+#define  MMIO_CAP2                       0x44 //hphang <- New in VLV2\r
+#define  MMIO_MCCAP                      0x48\r
+#define  MMIO_FORCEEVENTCMD12ERRSTAT     0x50 //hphang <- New in VLV2\r
+#define  MMIO_FORCEEVENTERRINTSTAT       0x52 //hphang <- New in VLV2\r
+#define  MMIO_ADMAERRSTAT                0x54 //hphang <- New in VLV2\r
+#define  MMIO_ADMASYSADDR                0x58 //hphang <- New in VLV2\r
+#define  MMIO_PRESETVALUE0               0x60 //hphang <- New in VLV2\r
+#define  MMIO_PRESETVALUE1               0x64 //hphang <- New in VLV2\r
+#define  MMIO_PRESETVALUE2               0x68 //hphang <- New in VLV2\r
+#define  MMIO_PRESETVALUE3               0x6C //hphang <- New in VLV2\r
+#define  MMIO_BOOTTIMEOUTCTRL            0x70 //hphang <- New in VLV2\r
+#define  MMIO_DEBUGSEL                   0x74 //hphang <- New in VLV2\r
+#define  MMIO_SHAREDBUS                  0xE0 //hphang <- New in VLV2\r
+#define  MMIO_SPIINTSUP                  0xF0 //hphang <- New in VLV2\r
+#define  MMIO_SLTINTSTS                  0xFC\r
+#define  MMIO_CTRLRVER                   0xFE\r
+\r
+typedef enum {\r
+  ResponseNo = 0,\r
+  ResponseR1,\r
+  ResponseR1b,\r
+  ResponseR2,\r
+  ResponseR3,\r
+  ResponseR4,\r
+  ResponseR5,\r
+  ResponseR5b,\r
+  ResponseR6,\r
+  ResponseR7\r
+} RESPONSE_TYPE;\r
+\r
+typedef enum {\r
+  NoData = 0,\r
+  InData,\r
+  OutData\r
+} TRANSFER_TYPE;\r
+\r
+typedef enum {\r
+  Reset_Auto = 0,\r
+  Reset_DAT,\r
+  Reset_CMD,\r
+  Reset_DAT_CMD,\r
+  Reset_All,\r
+  Reset_HW\r
+} RESET_TYPE;\r
+\r
+\r
+typedef enum {\r
+  SDMA = 0,\r
+  ADMA2,\r
+  PIO\r
+} DMA_MOD;\r
+\r
+typedef struct {\r
+  UINT32  HighSpeedSupport:    1;  //High speed supported\r
+  UINT32  V18Support:          1;  //1.8V supported\r
+  UINT32  V30Support:          1;  //3.0V supported\r
+  UINT32  V33Support:          1;  //3.3V supported\r
+  UINT32  SDR50Support:        1;\r
+  UINT32  SDR104Support:       1;\r
+  UINT32  DDR50Support:        1;\r
+  UINT32  Reserved0:           1;\r
+  UINT32  BusWidth4:           1;  // 4 bit width\r
+  UINT32  BusWidth8:           1;  // 8 bit width\r
+  UINT32  Reserved1:           6;\r
+  UINT32  SDMASupport:         1;\r
+  UINT32  ADMA2Support:        1;\r
+  UINT32  DmaMode:             2;\r
+  UINT32  ReTuneTimer:         4;\r
+  UINT32  ReTuneMode:          2;\r
+  UINT32  Reserved2:           6;\r
+  UINT32  BoundarySize;\r
+} HOST_CAPABILITY;\r
+\r
+/*++\r
+\r
+  Routine Description:\r
+    The main function used to send the command to the card inserted into the SD host\r
+    slot.\r
+    It will assemble the arguments to set the command register and wait for the command\r
+    and transfer completed until timeout. Then it will read the response register to fill\r
+    the ResponseData\r
+\r
+  Arguments:\r
+    This           - Pointer to EFI_SD_HOST_IO_PROTOCOL\r
+    CommandIndex   - The command index to set the command index field of command register\r
+    Argument       - Command argument to set the argument field of command register\r
+    DataType       - TRANSFER_TYPE, indicates no data, data in or data out\r
+    Buffer         - Contains the data read from / write to the device\r
+    BufferSize     - The size of the buffer\r
+    ResponseType   - RESPONSE_TYPE\r
+    TimeOut        - Time out value in 1 ms unit\r
+    ResponseData   - Depending on the ResponseType, such as CSD or card status\r
+\r
+  Returns:\r
+    EFI_SUCCESS\r
+    EFI_INVALID_PARAMETER\r
+    EFI_OUT_OF_RESOURCES\r
+    EFI_TIMEOUT\r
+    EFI_DEVICE_ERROR\r
+\r
+--*/\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *EFI_SD_HOST_IO_PROTOCOL_SEND_COMMAND) (\r
+  IN   EFI_SD_HOST_IO_PROTOCOL    *This,\r
+  IN   UINT16                     CommandIndex,\r
+  IN   UINT32                     Argument,\r
+  IN   TRANSFER_TYPE              DataType,\r
+  IN   UINT8                      *Buffer, OPTIONAL\r
+  IN   UINT32                     BufferSize,\r
+  IN   RESPONSE_TYPE              ResponseType,\r
+  IN   UINT32                     TimeOut,\r
+  OUT  UINT32                     *ResponseData OPTIONAL\r
+  );\r
+\r
+/*++\r
+\r
+  Routine Description:\r
+    Set max clock frequency of the host, the actual frequency\r
+    may not be the same as MaxFrequency. It depends on\r
+    the max frequency the host can support, divider, and host\r
+    speed mode.\r
+\r
+  Arguments:\r
+    This           - Pointer to EFI_SD_HOST_IO_PROTOCOL\r
+    MaxFrequency   - Max frequency in HZ\r
+\r
+  Returns:\r
+    EFI_SUCCESS\r
+    EFI_TIMEOUT\r
+--*/\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *EFI_SD_HOST_IO_PROTOCOL_SET_CLOCK_FREQUENCY) (\r
+  IN  EFI_SD_HOST_IO_PROTOCOL    *This,\r
+  IN  UINT32                     MaxFrequency\r
+  );\r
+\r
+/*++\r
+\r
+  Routine Description:\r
+    Set bus width of the host\r
+\r
+  Arguments:\r
+    This       - Pointer to EFI_SD_HOST_IO_PROTOCOL\r
+    BusWidth   - Bus width in 1, 4, 8 bits\r
+\r
+  Returns:\r
+    EFI_SUCCESS\r
+    EFI_INVALID_PARAMETER\r
+\r
+--*/\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *EFI_SD_HOST_IO_PROTOCOL_SET_BUS_WIDTH) (\r
+  IN  EFI_SD_HOST_IO_PROTOCOL    *This,\r
+  IN  UINT32                     BusWidth\r
+  );\r
+\r
+/*++\r
+\r
+  Routine Description:\r
+    Set voltage which could supported by the host.\r
+    Support 0(Power off the host), 1.8V, 3.0V, 3.3V\r
+  Arguments:\r
+    This      - Pointer to EFI_SD_HOST_IO_PROTOCOL\r
+    Voltage   - Units in 0.1 V\r
+\r
+  Returns:\r
+    EFI_SUCCESS\r
+    EFI_INVALID_PARAMETER\r
+\r
+--*/\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *EFI_SD_HOST_IO_PROTOCOL_SET_HOST_VOLTAGE) (\r
+  IN  EFI_SD_HOST_IO_PROTOCOL    *This,\r
+  IN  UINT32                     Voltage\r
+  );\r
+\r
+/*++\r
+\r
+  Routine Description:\r
+    Set Host High Speed\r
+  Arguments:\r
+    This      - Pointer to EFI_SD_HOST_IO_PROTOCOL\r
+    HighSpeed   - True for High Speed Mode set, false for normal mode\r
+\r
+  Returns:\r
+    EFI_SUCCESS\r
+    EFI_INVALID_PARAMETER\r
+\r
+--*/\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *EFI_SD_HOST_IO_PROTOCOL_SET_HOST_SPEED_MODE) (\r
+  IN  EFI_SD_HOST_IO_PROTOCOL    *This,\r
+  IN  UINT32                     HighSpeed\r
+  );\r
+\r
+/*++\r
+\r
+  Routine Description:\r
+    Set High Speed Mode\r
+  Arguments:\r
+    This      - Pointer to EFI_SD_HOST_IO_PROTOCOL\r
+    SetHostDdrMode   - True for DDR Mode set, false for normal mode\r
+\r
+  Returns:\r
+    EFI_SUCCESS\r
+    EFI_INVALID_PARAMETER\r
+\r
+--*/\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *EFI_SD_HOST_IO_PROTOCOL_SET_HOST_DDR_MODE) (\r
+  IN  EFI_SD_HOST_IO_PROTOCOL    *This,\r
+  IN  UINT32                     DdrMode\r
+  );\r
+\r
+\r
+/*++\r
+\r
+  Routine Description:\r
+   Reset the host\r
+\r
+  Arguments:\r
+    This      - Pointer to EFI_SD_HOST_IO_PROTOCOL\r
+    ResetAll  - TRUE to reset all\r
+\r
+  Returns:\r
+    EFI_SUCCESS\r
+    EFI_TIMEOUT\r
+\r
+--*/\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *EFI_SD_HOST_IO_PROTOCOL_RESET_SD_HOST) (\r
+  IN  EFI_SD_HOST_IO_PROTOCOL    *This,\r
+  IN  RESET_TYPE                 ResetType\r
+  );\r
+\r
+/*++\r
+\r
+  Routine Description:\r
+   Reset the host\r
+\r
+  Arguments:\r
+    This    - Pointer to EFI_SD_HOST_IO_PROTOCOL\r
+    Enable  - TRUE to enable, FALSE to disable\r
+\r
+  Returns:\r
+    EFI_SUCCESS\r
+    EFI_TIMEOUT\r
+\r
+--*/\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *EFI_SD_HOST_IO_PROTOCOL_ENABLE_AUTO_STOP_CMD) (\r
+  IN  EFI_SD_HOST_IO_PROTOCOL    *This,\r
+  IN  BOOLEAN                    Enable\r
+  );\r
+\r
+/*++\r
+\r
+  Routine Description:\r
+    Find whether these is a card inserted into the slot. If so\r
+    init the host. If not, return EFI_NOT_FOUND.\r
+\r
+  Arguments:\r
+    This      - Pointer to EFI_SD_HOST_IO_PROTOCOL\r
+\r
+  Returns:\r
+    EFI_SUCCESS\r
+    EFI_NOT_FOUND\r
+\r
+--*/\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *EFI_SD_HOST_IO_PROTOCOL_DETECT_CARD_AND_INIT_HOST) (\r
+  IN  EFI_SD_HOST_IO_PROTOCOL    *This\r
+  );\r
+\r
+/*++\r
+\r
+  Routine Description:\r
+   Set the Block length\r
+\r
+  Arguments:\r
+    This        - Pointer to EFI_SD_HOST_IO_PROTOCOL\r
+    BlockLength - card supportes block length\r
+\r
+  Returns:\r
+    EFI_SUCCESS\r
+    EFI_TIMEOUT\r
+\r
+--*/\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *EFI_SD_HOST_IO_PROTOCOL_SET_BLOCK_LENGTH) (\r
+  IN  EFI_SD_HOST_IO_PROTOCOL    *This,\r
+  IN  UINT32                     BlockLength\r
+  );\r
+\r
+typedef EFI_STATUS\r
+(EFIAPI *EFI_SD_HOST_IO_PROTOCOL_SETUP_DEVICE)(\r
+  IN  EFI_SD_HOST_IO_PROTOCOL    *This\r
+  );\r
+\r
+\r
+\r
+//\r
+// Interface structure for the EFI SD Host I/O Protocol\r
+//\r
+struct _EFI_SD_HOST_IO_PROTOCOL {\r
+  UINT32                                             Revision;\r
+  HOST_CAPABILITY                                    HostCapability;\r
+  EFI_SD_HOST_IO_PROTOCOL_SEND_COMMAND               SendCommand;\r
+  EFI_SD_HOST_IO_PROTOCOL_SET_CLOCK_FREQUENCY        SetClockFrequency;\r
+  EFI_SD_HOST_IO_PROTOCOL_SET_BUS_WIDTH              SetBusWidth;\r
+  EFI_SD_HOST_IO_PROTOCOL_SET_HOST_VOLTAGE           SetHostVoltage;\r
+  EFI_SD_HOST_IO_PROTOCOL_SET_HOST_DDR_MODE          SetHostDdrMode;\r
+  EFI_SD_HOST_IO_PROTOCOL_RESET_SD_HOST              ResetSdHost;\r
+  EFI_SD_HOST_IO_PROTOCOL_ENABLE_AUTO_STOP_CMD       EnableAutoStopCmd;\r
+  EFI_SD_HOST_IO_PROTOCOL_DETECT_CARD_AND_INIT_HOST  DetectCardAndInitHost;\r
+  EFI_SD_HOST_IO_PROTOCOL_SET_BLOCK_LENGTH           SetBlockLength;\r
+  EFI_SD_HOST_IO_PROTOCOL_SETUP_DEVICE               SetupDevice;\r
+  EFI_SD_HOST_IO_PROTOCOL_SET_HOST_SPEED_MODE        SetHostSpeedMode;\r
+};\r
+\r
+extern EFI_GUID gEfiSdHostIoProtocolGuid;\r
+\r
+#endif\r
+\r

diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/SmbiosSlotPopulation.h b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/SmbiosSlotPopulation.h
new file mode 100644 (file)
index 0000000..7ba9ea3
--- /dev/null
+++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/SmbiosSlotPopulation.h
@@ -0,0 +1,53 @@
+/*++\r
+\r
+Copyright (c)  1999  - 2014, Intel Corporation. All rights reserved\r
+\r
+  This program and the accompanying materials are licensed and made available under\r
+  the terms and conditions of the BSD License that accompanies this distribution.\r
+  The full text of the license may be found at\r
+  http://opensource.org/licenses/bsd-license.php.\r
+\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+\r
+Module Name:\r
+\r
+    SmbiosSlotPopulation.h\r
+\r
+Abstract:\r
+\r
+    EFI SMBIOS slot structure control code.\r
+\r
+GUID:\r
+    {EF7BF7D6-F8FF-4a76-8247-C0D0D1CC49C0}\r
+    0xef7bf7d6, 0xf8ff, 0x4a76, 0x82, 0x47, 0xc0, 0xd0, 0xd1, 0xcc, 0x49, 0xc0\r
+\r
+Revision History\r
+\r
+--*/\r
+\r
+#ifndef _EFI_SMBIOS_SLOT_POPULATION_H_\r
+#define _EFI_SMBIOS_SLOT_POPULATION_H_\r
+\r
+//\r
+// Slot Population Protocol GUID\r
+//\r
+#define EFI_SMBIOS_SLOT_POPULATION_GUID \\r
+  { 0xef7bf7d6, 0xf8ff, 0x4a76, 0x82, 0x47, 0xc0, 0xd0, 0xd1, 0xcc, 0x49, 0xc0 }\r
+\r
+typedef struct {\r
+  UINT16      SmbiosSlotId;   // SMBIOS Slot ID\r
+  BOOLEAN     InUse;          // Does the slot have a card in it\r
+  BOOLEAN     Disabled;       // Should the slot information be in SMBIOS\r
+} EFI_SMBIOS_SLOT_ENTRY;\r
+\r
+typedef struct {\r
+  UINT32                NumberOfEntries;\r
+  EFI_SMBIOS_SLOT_ENTRY *SlotEntries;\r
+} EFI_SMBIOS_SLOT_POPULATION_INFO;\r
+\r
+extern EFI_GUID gEfiSmbiosSlotPopulationGuid;\r
+\r
+#endif\r

diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/SmmIchnDispatchEx.h b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/SmmIchnDispatchEx.h
new file mode 100644 (file)
index 0000000..8400156
--- /dev/null
+++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/SmmIchnDispatchEx.h
@@ -0,0 +1,165 @@
+/**\r
+**/\r
+/**\r
+\r
+Copyright (c) 2012  - 2014, Intel Corporation. All rights reserved\r
+\r
+  This program and the accompanying materials are licensed and made available under\r
+  the terms and conditions of the BSD License that accompanies this distribution.\r
+  The full text of the license may be found at\r
+  http://opensource.org/licenses/bsd-license.php.\r
+\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+\r
+  @file\r
+  SmmIchnDispatchEx.h\r
+\r
+  @brief\r
+  SmmIchnDispatch Extended Protocol\r
+\r
+**/\r
+#ifndef _EFI_SMM_ICHN_DISPATCH_EX_H_\r
+#define _EFI_SMM_ICHN_DISPATCH_EX_H_\r
+\r
+#ifdef ECP_FLAG\r
+#include <Protocol/SmmIchnDispatch/SmmIchnDispatch.h>\r
+#else\r
+#include <Protocol/SmmIchnDispatch.h>\r
+#endif\r
+\r
+#define EFI_SMM_ICHN_DISPATCH_EX_PROTOCOL_GUID \\r
+  { \\r
+    0x3920405b, 0xc897, 0x44da, 0x88, 0xf3, 0x4c, 0x49, 0x8a, 0x6f, 0xf7, 0x36 \\r
+  }\r
+extern EFI_GUID                                   gEfiSmmIchnDispatchExProtocolGuid;\r
+\r
+///\r
+/// Forward reference for ANSI C compatibility\r
+///\r
+typedef struct _EFI_SMM_ICHN_DISPATCH_EX_PROTOCOL EFI_SMM_ICHN_DISPATCH_EX_PROTOCOL;\r
+\r
+///\r
+/// Related Definitions\r
+///\r
+///\r
+/// Ichn Dispatch Extended Types\r
+///\r
+typedef enum {\r
+  IchnExPciExpress = NUM_ICHN_TYPES + 1,\r
+  IchnExMonitor,\r
+  IchnExSpi,\r
+  IchnExQRT,\r
+  IchnExGpioUnlock,\r
+  IchnExTmrOverflow,\r
+  IchnExPcie0Hotplug,\r
+  IchnExPcie1Hotplug,\r
+  IchnExPcie2Hotplug,\r
+  IchnExPcie3Hotplug,\r
+  IchnExPcie0LinkActive,\r
+  IchnExPcie1LinkActive,\r
+  IchnExPcie2LinkActive,\r
+  IchnExPcie3LinkActive,\r
+  ///\r
+  /// INSERT NEW ITEMS JUST BEFORE THIS LINE\r
+  ///\r
+  IchnExTypeMAX /// the maximum number of items in this enumeration\r
+} EFI_SMM_ICHN_EX_SMI_TYPE;\r
+\r
+typedef struct {\r
+  EFI_SMM_ICHN_EX_SMI_TYPE  Type;\r
+} EFI_SMM_ICHN_DISPATCH_EX_CONTEXT;\r
+\r
+///\r
+/// Member functions\r
+///\r
+typedef\r
+VOID\r
+(EFIAPI *EFI_SMM_ICHN_DISPATCH_EX) (\r
+  IN  EFI_HANDLE                                DispatchHandle,\r
+  IN  EFI_SMM_ICHN_DISPATCH_EX_CONTEXT          * DispatchContext\r
+  );\r
+\r
+/**\r
+\r
+  @brief\r
+  Dispatch function for a ICH n Extended specific SMI handler.\r
+\r
+  @param[in] DispatchHandle       Handle of this dispatch function.\r
+  @param[in] DispatchContext      Pointer to the dispatch function's context.\r
+                                  The DispatchContext fields are filled in\r
+                                  by the dispatching driver prior to\r
+                                  invoking this dispatch function.\r
+\r
+    @retval None\r
+\r
+**/\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *EFI_SMM_ICHN_EX_REGISTER) (\r
+  IN  EFI_SMM_ICHN_DISPATCH_EX_PROTOCOL   * This,\r
+  IN  EFI_SMM_ICHN_DISPATCH_EX            DispatchFunction,\r
+  IN  EFI_SMM_ICHN_DISPATCH_EX_CONTEXT    * DispatchContext,\r
+  OUT EFI_HANDLE                          * DispatchHandle\r
+  );\r
+\r
+/**\r
+\r
+  @brief\r
+  Register a child SMI source dispatch function with a parent SMM driver\r
+\r
+  @param[in] This                 Protocol instance pointer.\r
+  @param[in] DispatchFunction     Pointer to dispatch function to be invoked for\r
+                                  this SMI source\r
+  @param[in] DispatchContext      Pointer to the dispatch function's context.\r
+                                  The caller fills this context in before calling\r
+                                  the register function to indicate to the register\r
+                                  function the ICHN SMI source for which the dispatch\r
+                                  function should be invoked.\r
+  @param[in] DispatchHandle       Handle of dispatch function, for when interfacing\r
+                                  with the parent SMM driver.\r
+\r
+  @retval EFI_SUCCESS             The dispatch function has been successfully\r
+                                  registered and the SMI source has been enabled.\r
+  @retval EFI_DEVICE_ERROR        The driver was unable to enable the SMI source.\r
+  @retval EFI_OUT_OF_RESOURCES    Not enough memory (system or SMM) to manage this\r
+                                  child.\r
+  @retval EFI_INVALID_PARAMETER   DispatchContext is invalid. The ICHN input value\r
+                                  is not within valid range.\r
+\r
+**/\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *EFI_SMM_ICHN_EX_UNREGISTER) (\r
+  IN  EFI_SMM_ICHN_DISPATCH_EX_PROTOCOL         * This,\r
+  IN  EFI_HANDLE                                DispatchHandle\r
+  );\r
+\r
+/**\r
+\r
+  @brief\r
+  Unregister a child SMI source dispatch function with a parent SMM driver\r
+\r
+  @param[in] This                 Protocol instance pointer.\r
+  @param[in] DispatchHandle       Handle of dispatch function to deregister.\r
+\r
+  @retval EFI_SUCCESS             The dispatch function has been successfully\r
+                                  unregistered and the SMI source has been disabled\r
+                                  if there are no other registered child dispatch\r
+                                  functions for this SMI source.\r
+  @retval EFI_INVALID_PARAMETER   Handle is invalid.\r
+  @retval Others                  TBD\r
+\r
+**/\r
+\r
+///\r
+/// Interface structure for the SMM Ich n specific SMI Dispatch Protocol\r
+///\r
+typedef struct _EFI_SMM_ICHN_DISPATCH_EX_PROTOCOL {\r
+  EFI_SMM_ICHN_EX_REGISTER    Register;\r
+  EFI_SMM_ICHN_EX_UNREGISTER  UnRegister;\r
+};\r
+\r
+#endif\r

diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/SmmSmbus.h b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/SmmSmbus.h
new file mode 100644 (file)
index 0000000..3ee6a3a
--- /dev/null
+++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/SmmSmbus.h
@@ -0,0 +1,45 @@
+/*++\r
+\r
+Copyright (c)  2009  - 2014, Intel Corporation. All rights reserved\r
+\r
+  This program and the accompanying materials are licensed and made available under\r
+  the terms and conditions of the BSD License that accompanies this distribution.\r
+  The full text of the license may be found at\r
+  http://opensource.org/licenses/bsd-license.php.\r
+\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+\r
+Module Name:\r
+\r
+  SmmSmbus.h\r
+\r
+Abstract:\r
+\r
+  SmmSmbus Protocol\r
+\r
+--*/\r
+#ifndef __EFI_SMM_SMBUS_PROTOCOL_H__\r
+#define __EFI_SMM_SMBUS_PROTOCOL_H__\r
+\r
+//\r
+// GUID for the SmmSmbus Protocol\r
+//\r
+// EDK and EDKII have different GUID formats\r
+//\r
+\r
+#define EFI_SMM_SMBUS_PROTOCOL_GUID  \\r
+  { \\r
+    0x72e40094, 0x2ee1, 0x497a, 0x8f, 0x33, 0x4c, 0x93, 0x4a, 0x9e, 0x9c, 0xc \\r
+  }\r
+\r
+//\r
+// Resuse the DXE definition, and use another GUID.\r
+//\r
+typedef EFI_SMBUS_HC_PROTOCOL  SMM_SMBUS_HC_PROTOCOL;\r
+\r
+extern EFI_GUID  gEfiSmmSmbusProtocolGuid;\r
+\r
+#endif\r

diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/Spi.h b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/Spi.h
new file mode 100644 (file)
index 0000000..f73ef65
--- /dev/null
+++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/Spi.h
@@ -0,0 +1,266 @@
+/**\r
+**/\r
+/**\r
+\r
+Copyright (c) 2012  - 2014, Intel Corporation. All rights reserved\r
+\r
+  This program and the accompanying materials are licensed and made available under\r
+  the terms and conditions of the BSD License that accompanies this distribution.\r
+  The full text of the license may be found at\r
+  http://opensource.org/licenses/bsd-license.php.\r
+\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+\r
+  @file\r
+  Spi.h\r
+\r
+  @brief\r
+  This file defines the EFI SPI Protocol which implements the\r
+  Intel(R) ICH SPI Host Controller Compatibility Interface.\r
+\r
+**/\r
+#ifndef _EFI_SPI_H_\r
+#define _EFI_SPI_H_\r
+\r
+\r
+//\r
+#define EFI_SPI_PROTOCOL_GUID \\r
+  { \\r
+    0x1156efc6, 0xea32, 0x4396, 0xb5, 0xd5, 0x26, 0x93, 0x2e, 0x83, 0xc3, 0x13 \\r
+  }\r
+#define EFI_SMM_SPI_PROTOCOL_GUID \\r
+  { \\r
+    0xD9072C35, 0xEB8F, 0x43ad, 0xA2, 0x20, 0x34, 0xD4, 0x0E, 0x2A, 0x82, 0x85 \\r
+  }\r
+extern EFI_GUID                   gEfiSpiProtocolGuid;\r
+extern EFI_GUID                   gEfiSmmSpiProtocolGuid;\r
+\r
+///\r
+/// Forward reference for ANSI C compatibility\r
+///\r
+typedef struct _EFI_SPI_PROTOCOL  EFI_SPI_PROTOCOL;\r
+\r
+///\r
+/// SPI protocol data structures and definitions\r
+///\r
+///\r
+/// Number of Prefix Opcodes allowed on the SPI interface\r
+///\r
+#define SPI_NUM_PREFIX_OPCODE 2\r
+\r
+///\r
+/// Number of Opcodes in the Opcode Menu\r
+///\r
+#define SPI_NUM_OPCODE  8\r
+\r
+///\r
+/// Opcode Type\r
+///    EnumSpiOpcodeCommand: Command without address\r
+///    EnumSpiOpcodeRead: Read with address\r
+///    EnumSpiOpcodeWrite: Write with address\r
+///\r
+typedef enum {\r
+  EnumSpiOpcodeReadNoAddr,\r
+  EnumSpiOpcodeWriteNoAddr,\r
+  EnumSpiOpcodeRead,\r
+  EnumSpiOpcodeWrite,\r
+  EnumSpiOpcodeMax\r
+} SPI_OPCODE_TYPE;\r
+\r
+typedef enum {\r
+  EnumSpiCycle20MHz,\r
+  EnumSpiCycle33MHz,\r
+  EnumSpiCycle66MHz,  /// Not supported by VLV\r
+  EnumSpiCycle50MHz,\r
+  EnumSpiCycleMax\r
+} SPI_CYCLE_FREQUENCY;\r
+\r
+typedef enum {\r
+  EnumSpiRegionAll,\r
+  EnumSpiRegionBios,\r
+  EnumSpiRegionSeC,\r
+  EnumSpiRegionDescriptor,\r
+  EnumSpiRegionPlatformData,\r
+  EnumSpiRegionMax\r
+} SPI_REGION_TYPE;\r
+\r
+///\r
+/// Hardware Sequencing required operations (as listed in Valleyview EDS "Hardware\r
+/// Sequencing Commands and Opcode Requirements"\r
+///\r
+typedef enum {\r
+  EnumSpiOperationWriteStatus,\r
+  EnumSpiOperationProgramData_1_Byte,\r
+  EnumSpiOperationProgramData_64_Byte,\r
+  EnumSpiOperationReadData,\r
+  EnumSpiOperationWriteDisable,\r
+  EnumSpiOperationReadStatus,\r
+  EnumSpiOperationWriteEnable,\r
+  EnumSpiOperationFastRead,\r
+  EnumSpiOperationEnableWriteStatus,\r
+  EnumSpiOperationErase_256_Byte,\r
+  EnumSpiOperationErase_4K_Byte,\r
+  EnumSpiOperationErase_8K_Byte,\r
+  EnumSpiOperationErase_64K_Byte,\r
+  EnumSpiOperationFullChipErase,\r
+  EnumSpiOperationJedecId,\r
+  EnumSpiOperationDualOutputFastRead,\r
+  EnumSpiOperationDiscoveryParameters,\r
+  EnumSpiOperationOther,\r
+  EnumSpiOperationMax\r
+} SPI_OPERATION;\r
+\r
+///\r
+/// SPI Command Configuration\r
+///   Frequency       The expected frequency to be used (value to be programmed to the SSFC\r
+///                   Register)\r
+///   Operation       Which Hardware Sequencing required operation this opcode respoinds to.\r
+///                   The required operations are listed in EDS Table 5-55: "Hardware\r
+///                   Sequencing Commands and Opcode Requirements"\r
+///                   If the opcode does not corresponds to any operation listed, use\r
+///                   EnumSpiOperationOther, and provides TYPE and Code for it in\r
+///                   SpecialOpcodeEntry.\r
+///\r
+typedef struct _SPI_OPCODE_MENU_ENTRY {\r
+  SPI_OPCODE_TYPE     Type;\r
+  UINT8               Code;\r
+  SPI_CYCLE_FREQUENCY Frequency;\r
+  SPI_OPERATION       Operation;\r
+} SPI_OPCODE_MENU_ENTRY;\r
+\r
+//\r
+// Initialization data table loaded to the SPI host controller\r
+//    VendorId        Vendor ID of the SPI device\r
+//    DeviceId0       Device ID0 of the SPI device\r
+//    DeviceId1       Device ID1 of the SPI device\r
+//    PrefixOpcode    Prefix opcodes which are loaded into the SPI host controller\r
+//    OpcodeMenu      Opcodes which are loaded into the SPI host controller Opcode Menu\r
+//    BiosStartOffset The offset of the start of the BIOS image relative to the flash device.\r
+//                    Please note this is a Flash Linear Address, NOT a memory space address.\r
+//                    This value is platform specific and depends on the system flash map.\r
+//                    This value is only used on non Descriptor mode.\r
+//    BiosSize        The the BIOS Image size in flash. This value is platform specific\r
+//                    and depends on the system flash map. Please note BIOS Image size may\r
+//                    be smaller than BIOS Region size (in Descriptor Mode) or the flash size\r
+//                    (in Non Descriptor Mode), and in this case, BIOS Image is supposed to be\r
+//                    placed at the top end of the BIOS Region (in Descriptor Mode) or the flash\r
+//                    (in Non Descriptor Mode)\r
+//\r
+typedef struct _SPI_INIT_TABLE {\r
+  UINT8                 VendorId;\r
+  UINT8                 DeviceId0;\r
+  UINT8                 DeviceId1;\r
+  UINT8                 PrefixOpcode[SPI_NUM_PREFIX_OPCODE];\r
+  SPI_OPCODE_MENU_ENTRY OpcodeMenu[SPI_NUM_OPCODE];\r
+  UINTN                 BiosStartOffset;\r
+  UINTN                 BiosSize;\r
+} SPI_INIT_TABLE;\r
+\r
+//\r
+// Protocol member functions\r
+//\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *EFI_SPI_INIT) (\r
+  IN EFI_SPI_PROTOCOL     * This,\r
+  IN SPI_INIT_TABLE       * InitTable\r
+  );\r
+\r
+/**\r
+\r
+  @brief\r
+  Initializes the host controller to execute SPI commands.\r
+\r
+  @param[in] This                 Pointer to the EFI_SPI_PROTOCOL instance.\r
+  @param[in] InitData             Pointer to caller-allocated buffer containing the SPI\r
+                                  interface initialization table.\r
+\r
+  @retval EFI_SUCCESS             Opcode initialization on the SPI host controller completed.\r
+  @retval EFI_ACCESS_DENIED       The SPI configuration interface is locked.\r
+  @retval EFI_OUT_OF_RESOURCES    Not enough resource available to initialize the device.\r
+  @retval EFI_DEVICE_ERROR        Device error, operation failed.\r
+\r
+**/\r
+\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *EFI_SPI_LOCK) (\r
+  IN EFI_SPI_PROTOCOL     * This\r
+  );\r
+/**\r
+\r
+  @brief\r
+  Initializes the host controller to execute SPI commands.\r
+\r
+  @param[in] This                 Pointer to the EFI_SPI_PROTOCOL instance.\r
+  @param[in] InitData             Pointer to caller-allocated buffer containing the SPI\r
+                                  interface initialization table.\r
+\r
+  @retval EFI_SUCCESS             Opcode initialization on the SPI host controller completed.\r
+  @retval EFI_ACCESS_DENIED       The SPI configuration interface is locked.\r
+  @retval EFI_OUT_OF_RESOURCES    Not enough resource available to initialize the device.\r
+  @retval EFI_DEVICE_ERROR        Device error, operation failed.\r
+\r
+**/\r
+\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *EFI_SPI_EXECUTE) (\r
+  IN     EFI_SPI_PROTOCOL   * This,\r
+  IN     UINT8              OpcodeIndex,\r
+  IN     UINT8              PrefixOpcodeIndex,\r
+  IN     BOOLEAN            DataCycle,\r
+  IN     BOOLEAN            Atomic,\r
+  IN     BOOLEAN            ShiftOut,\r
+  IN     UINTN              Address,\r
+  IN     UINT32             DataByteCount,\r
+  IN OUT UINT8              *Buffer,\r
+  IN     SPI_REGION_TYPE    SpiRegionType\r
+  );\r
+/**\r
+\r
+  @brief\r
+  Execute SPI commands from the host controller.\r
+\r
+  @param[in] This                 Pointer to the EFI_SPI_PROTOCOL instance.\r
+  @param[in] OpcodeIndex          Index of the command in the OpCode Menu.\r
+  @param[in] PrefixOpcodeIndex    Index of the first command to run when in an atomic cycle sequence.\r
+  @param[in] DataCycle            TRUE if the SPI cycle contains data\r
+  @param[in] Atomic               TRUE if the SPI cycle is atomic and interleave cycles are not allowed.\r
+  @param[in] ShiftOut             If DataByteCount is not zero, TRUE to shift data out and FALSE to shift data in.\r
+  @param[in] Address              In Descriptor Mode, for Descriptor Region, GbE Region, ME Region and Platform\r
+                                  Region, this value specifies the offset from the Region Base; for BIOS Region,\r
+                                  this value specifies the offset from the start of the BIOS Image. In Non\r
+                                  Descriptor Mode, this value specifies the offset from the start of the BIOS Image.\r
+                                  Please note BIOS Image size may be smaller than BIOS Region size (in Descriptor\r
+                                  Mode) or the flash size (in Non Descriptor Mode), and in this case, BIOS Image is\r
+                                  supposed to be placed at the top end of the BIOS Region (in Descriptor Mode) or\r
+                                  the flash (in Non Descriptor Mode)\r
+  @param[in] DataByteCount        Number of bytes in the data portion of the SPI cycle.\r
+  @param[in] Buffer               Pointer to caller-allocated buffer containing the dada received or sent during the SPI cycle.\r
+  @param[in] SpiRegionType        SPI Region type. Values EnumSpiRegionBios, EnumSpiRegionGbE, EnumSpiRegionMe,\r
+                                  EnumSpiRegionDescriptor, and EnumSpiRegionPlatformData are only applicable in\r
+                                  Descriptor mode. Value EnumSpiRegionAll is applicable to both Descriptor Mode\r
+                                  and Non Descriptor Mode, which indicates "SpiRegionOffset" is actually relative\r
+                                  to base of the 1st flash device (i.e., it is a Flash Linear Address).\r
+\r
+  @retval EFI_SUCCESS             Command succeed.\r
+  @retval EFI_INVALID_PARAMETER   The parameters specified are not valid.\r
+  @exception EFI_UNSUPPORTED      Command not supported.\r
+  @retval EFI_DEVICE_ERROR        Device error, command aborts abnormally.\r
+\r
+**/\r
+\r
+///\r
+/// Protocol definition\r
+///\r
+struct _EFI_SPI_PROTOCOL {\r
+  EFI_SPI_INIT    Init;\r
+  EFI_SPI_LOCK    Lock;\r
+  EFI_SPI_EXECUTE Execute;\r
+};\r
+\r
+#endif\r

diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/TcoReset.h b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/TcoReset.h
new file mode 100644 (file)
index 0000000..4cb7dba
--- /dev/null
+++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/TcoReset.h
@@ -0,0 +1,94 @@
+/*++\r
+\r
+Copyright (c)  1999  - 2014, Intel Corporation. All rights reserved\r
+\r
+  This program and the accompanying materials are licensed and made available under\r
+  the terms and conditions of the BSD License that accompanies this distribution.\r
+  The full text of the license may be found at\r
+  http://opensource.org/licenses/bsd-license.php.\r
+\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+\r
+Module Name:\r
+\r
+  TcoReset.h\r
+\r
+Abstract:\r
+\r
+  Protocol to communicate with ICH TCO.\r
+\r
+GUID Info:\r
+ {A6A79162-E325-4c30-BCC3-59373064EFB3}\r
+ 0xa6a79162, 0xe325, 0x4c30, 0xbc, 0xc3, 0x59, 0x37, 0x30, 0x64, 0xef, 0xb3);\r
+\r
+\r
+--*/\r
+\r
+#ifndef _TCO_RESET_H_\r
+#define _TCO_RESET_H_\r
+\r
+\r
+#define EFI_TCO_RESET_PROTOCOL_GUID  \\r
+  {0xa6a79162, 0xe325, 0x4c30, 0xbc, 0xc3, 0x59, 0x37, 0x30, 0x64, 0xef, 0xb3}\r
+\r
+typedef struct _EFI_TCO_RESET_PROTOCOL EFI_TCO_RESET_PROTOCOL;\r
+\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *EFI_TCO_RESET_PROTOCOL_ENABLE_TCO_RESET) (\r
+  IN      UINT32            *RcrbGcsSaveValue\r
+  )\r
+/*++\r
+\r
+Routine Description:\r
+\r
+  Enables the TCO timer to reset the system in case of a system hang.  This is\r
+  used when writing the clock registers.\r
+\r
+Arguments:\r
+\r
+  RcrbGcsSaveValue  - This is the value of the RCRB GCS register before it is\r
+                      changed by this procedure.  This will be used to restore\r
+                      the settings of this register in PpiDisableTcoReset.\r
+\r
+Returns:\r
+\r
+  EFI_STATUS\r
+\r
+--*/\r
+;\r
+\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *EFI_TCO_RESET_PROTOCOL_DISABLE_TCO_RESET) (\r
+  OUT     UINT32    RcrbGcsRestoreValue\r
+  )\r
+/*++\r
+\r
+Routine Description:\r
+\r
+  Disables the TCO timer.  This is used after writing the clock registers.\r
+\r
+Arguments:\r
+\r
+  RcrbGcsRestoreValue - Value saved in PpiEnableTcoReset so that it can\r
+                        restored.\r
+\r
+Returns:\r
+\r
+  EFI_STATUS\r
+\r
+--*/\r
+;\r
+\r
+typedef struct _EFI_TCO_RESET_PROTOCOL {\r
+  EFI_TCO_RESET_PROTOCOL_ENABLE_TCO_RESET       EnableTcoReset;\r
+  EFI_TCO_RESET_PROTOCOL_DISABLE_TCO_RESET      DisableTcoReset;\r
+} EFI_TCO_RESET_PROTOCOL;\r
+\r
+extern EFI_GUID gEfiTcoResetProtocolGuid;\r
+\r
+#endif\r

diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Rsci.h b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Rsci.h
new file mode 100644 (file)
index 0000000..f914233
--- /dev/null
+++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Rsci.h
@@ -0,0 +1,34 @@
+/*++\r
+Copyright (c) 1996  - 2014, Intel Corporation.\r
+\r
+  This program and the accompanying materials are licensed and made available under\r
+  the terms and conditions of the BSD License that accompanies this distribution.\r
+  The full text of the license may be found at\r
+  http://opensource.org/licenses/bsd-license.php.\r
+\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+\r
+Module Name:\r
+\r
+\r
+\r
+Abstract:\r
+\r
+\r
+\r
+--*/\r
+\r
+#ifndef _RSCI_H\r
+#define _RSCI_H\r
+\r
+typedef enum {\r
+  NOT_APPLICABLE_RESET = 0,\r
+  WARM_RESET = 1,\r
+  COLD_RESET = 2,\r
+  GLOBAL_RESET = 7,\r
+}ANDROID_RESET_TYPE;\r
+\r
+#endif\r

diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/TianoApi.h b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/TianoApi.h
new file mode 100644 (file)
index 0000000..c73c68d
--- /dev/null
+++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/TianoApi.h
@@ -0,0 +1,67 @@
+/*++\r
+\r
+Copyright (c) 2004, Intel Corporation\r
+All rights reserved. This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution.  The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+Module Name:\r
+\r
+  TianoApi.h\r
+\r
+Abstract:\r
+\r
+  Tiano intrinsic definitions.\r
+\r
+\r
+--*/\r
+\r
+#ifndef _TIANO_API_H_\r
+#define _TIANO_API_H_\r
+\r
+//\r
+// Pointer to internal runtime function\r
+//\r
+#define EFI_INTERNAL_FUNCTION 0x00000002\r
+\r
+//\r
+// Pointer to internal runtime pointer\r
+//\r
+#define EFI_INTERNAL_POINTER  0x00000004\r
+\r
+//\r
+// Pointer to internal runtime pointer\r
+//\r
+#define EFI_IPF_GP_POINTER  0x00000008\r
+\r
+#define EFI_TPL_DRIVER      6\r
+\r
+//\r
+// EFI Event Types\r
+//\r
+#define EFI_EVENT_TIMER                         0x80000000\r
+#define EFI_EVENT_RUNTIME                       0x40000000\r
+#define EFI_EVENT_RUNTIME_CONTEXT               0x20000000\r
+\r
+#define EFI_EVENT_NOTIFY_WAIT                   0x00000100\r
+#define EFI_EVENT_NOTIFY_SIGNAL                 0x00000200\r
+\r
+#define EFI_EVENT_SIGNAL_EXIT_BOOT_SERVICES     0x00000201\r
+#define EFI_EVENT_SIGNAL_VIRTUAL_ADDRESS_CHANGE 0x60000202\r
+\r
+#define EFI_EVENT_EFI_SIGNAL_MASK               0x000000FF\r
+#define EFI_EVENT_EFI_SIGNAL_MAX                4\r
+\r
+//\r
+// Task priority level\r
+//\r
+#define EFI_TPL_APPLICATION 4\r
+#define EFI_TPL_CALLBACK    8\r
+#define EFI_TPL_NOTIFY      16\r
+#define EFI_TPL_HIGH_LEVEL  31\r
+\r
+#endif\r

diff --git a/Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec b/Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec
new file mode 100644 (file)
index 0000000..38b9754
--- /dev/null
+++ b/Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec
@@ -0,0 +1,121 @@
+##  @file  Vlv2DeviceRefCodePkg.dec\r
+#\r
+# Copyright (c) 2012  - 2014, Intel Corporation. All rights reserved\r
+#\r
+# This program and the accompanying materials are licensed and made available under\r
+# the terms and conditions of the BSD License that accompanies this distribution.\r
+# The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php.\r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+#\r
+##\r
+\r
+[Defines]\r
+  DEC_SPECIFICATION              = 0x00010005\r
+  PACKAGE_NAME                   = Vlv2DeviceRefCodePkg\r
+  PACKAGE_GUID                   = E4FA0DCA-91A3-4957-9344-C10BAA0BFE5F\r
+  PACKAGE_VERSION                = 0.1\r
+\r
+[Ppis]\r
+  gVlvPolicyPpiGuid                                           = { 0x7D84B2C2, 0x22A1, 0x4372, {0xB1, 0x2C, 0xEB, 0xB2, 0x32, 0xD3, 0xA6, 0xA3}}\r
+  gVlvMmioPolicyPpiGuid                                       = { 0xE767BF7F, 0x4DB6, 0x5B34, {0x10, 0x11, 0x4F, 0xBE, 0x4C, 0xA7, 0xAF, 0xD2}}\r
+  gPeiSmbusPolicyPpiGuid                            = { 0x63b6e435, 0x32bc, 0x49c6, {0x81, 0xbd, 0xb7, 0xa1, 0xa0, 0xfe, 0x1a, 0x6c}}\r
+  gSeCfTPMPpiGuid                       = { 0x10e26df1, 0x8775, 0x4ee1, {0xb5, 0x0a, 0x3a, 0xe8, 0x28, 0x93, 0x70, 0x3a}}\r
+  gPchUsbPolicyPpiGuid                  = { 0xc02b0573, 0x2b4e, 0x4a31, {0xa3, 0x1a, 0x94, 0x56, 0x7b, 0x50, 0x44, 0x2c}}\r
+  gPchInitPpiGuid                       = { 0x09ea894a, 0xbe0d, 0x4230, {0xa0, 0x03, 0xed, 0xc6, 0x93, 0xb4, 0x8e, 0x95}}\r
+  gPchPlatformPolicyPpiGuid             = { 0x15344673, 0xD365, 0x4BE2, {0x85, 0x13, 0x14, 0x97, 0xCC, 0x07, 0x61, 0x1D}}\r
+  gPeiSpiPpiGuid                        = { 0xA38C6898, 0x2B5C, 0x4FF6, {0x93, 0x26, 0x2E, 0x63, 0x21, 0x2E, 0x56, 0xC2}}\r
+  gVlvPeiInitPpiGuid                    = { 0x09ea8911, 0xbe0d, 0x4230, {0xa0, 0x03, 0xed, 0xc6, 0x93, 0xb4, 0x8e, 0x11}}\r
+  gSeCUmaPpiGuid                        = { 0xcbd86677, 0x362f, 0x4c04, {0x94, 0x59, 0xa7, 0x41, 0x32, 0x6e, 0x05, 0xcf}}\r
+  gPeiSeCPlatformPolicyPpiGuid          = { 0x7ae3ceb7, 0x2ee2, 0x48fa, {0xaa, 0x49, 0x35, 0x10, 0xbc, 0x83, 0xca, 0xbf}}\r
+  gPeiHeciPpiGuid                       = { 0xEE0EA811, 0xFBD9, 0x4777, {0xB9, 0x5A, 0xBA, 0x4F, 0x71, 0x10, 0x1F, 0x74}}\r
+  gPeiSdhcPpiGuid                       = { 0xf4ef9d7a, 0x98c5, 0x4c1a, {0xb4, 0xd9, 0xd8, 0xd8, 0x72, 0x65, 0xbe, 0x0c}}\r
+  gPeiBlockIoPpiGuid                    = { 0xbc5fa650, 0xedbb, 0x4d0d, {0xb3, 0xa3, 0xd9, 0x89, 0x07, 0xf8, 0x47, 0xdf}}\r
+  gSeCfTPMPolicyPpiGuid                 = { 0x4fd1ba49, 0x8f90, 0x471a, {0xa2, 0xc9, 0x17, 0x3c, 0x7a, 0x73, 0x2f, 0xd0}}\r
+  gEfiPeiReadOnlyVariable2PpiGuid       = { 0x2ab86ef5, 0xecb5, 0x4134, {0xb5, 0x56, 0x38, 0x54, 0xca, 0x1f, 0xe1, 0xb4}}\r
+  gPchPeiInitPpiGuid                    = { 0xACB93B08, 0x5CDC, 0x4A8F, {0x93, 0xD4, 0x6, 0xE3, 0x42, 0xDF, 0x18, 0x2E}}\r
+\r
+[Protocols]\r
+  gEfiGlobalNvsAreaProtocolGuid         = { 0x074e1e48, 0x8132, 0x47a1, {0x8c, 0x2c, 0x3f, 0x14, 0xad, 0x9a, 0x66, 0xdc}}\r
+  gPpmPlatformPolicyProtocolGuid        = { 0xddabfeac, 0xef63, 0x452c, {0x8f, 0x39, 0xed, 0x7f, 0xae, 0xd8, 0x26, 0x5e}}\r
+  gEfiSpiProtocolGuid                   = { 0x1156efc6, 0xea32, 0x4396, {0xb5, 0xd5, 0x26, 0x93, 0x2e, 0x83, 0xc3, 0x13}}\r
+  gMemInfoProtocolGuid                  = { 0x6f20f7c8, 0xe5ef, 0x4f21, {0x8d, 0x19, 0xed, 0xc5, 0xf0, 0xc4, 0x96, 0xae}}\r
+  gEfiSdHostIoProtocolGuid              = { 0xb63f8ec7, 0xa9c9, 0x4472, {0xa4, 0xc0, 0x4d, 0x8b, 0xf3, 0x65, 0xcc, 0x51}}\r
+  gEfiSpiProtocolGuid                   = { 0x1156efc6, 0xea32, 0x4396, {0xb5, 0xd5, 0x26, 0x93, 0x2e, 0x83, 0xc3, 0x13}}\r
+  gEfiSmmSpiProtocolGuid                = { 0xD9072C35, 0xEB8F, 0x43AD, {0xA2, 0x20, 0x34, 0xD4, 0x0E, 0x2A, 0x82, 0x85}}\r
+  gEfiSmmIchnDispatchExProtocolGuid     = { 0x3920405B, 0xC897, 0x44DA, {0x88, 0xF3, 0x4C, 0x49, 0x8A, 0x6F, 0xF7, 0x36}}\r
+  gEfiPchS3SupportProtocolGuid          = { 0xE287D20B, 0xD897, 0x4E1E, {0xA5, 0xD9, 0x97, 0x77, 0x63, 0x93, 0x6A, 0x04}}\r
+  gPchResetProtocolGuid                 = { 0xDB63592C, 0xB8CC, 0x44C8, {0x91, 0x8C, 0x51, 0xF5, 0x34, 0x59, 0x8A, 0x5A}}\r
+  gPchResetCallbackProtocolGuid         = { 0x3A3300AB, 0xC929, 0x487D, {0xAB, 0x34, 0x15, 0x9B, 0xC1, 0x35, 0x62, 0xC0}}\r
+  gDxePchPlatformPolicyProtocolGuid     = { 0x4b0165a9, 0x61d6, 0x4e23, {0xa0, 0xb5, 0x3e, 0xc7, 0x9c, 0x2e, 0x30, 0xd5}}\r
+  gEfiPchInfoProtocolGuid               = { 0xD31F0400, 0x7D16, 0x4316, {0xBF, 0x88, 0x60, 0x65, 0x88, 0x3B, 0x40, 0x2B}}\r
+  gEfiPchExtendedResetProtocolGuid      = { 0xF0BBFCA0, 0x684E, 0x48B3, {0xBA, 0xE2, 0x6C, 0x84, 0xB8, 0x9E, 0x53, 0x39}}\r
+  gEfiActiveBiosProtocolGuid            = { 0xEBBE2D1B, 0x1647, 0x4BDA, {0xAB, 0x9A, 0x78, 0x63, 0xE3, 0x96, 0xD4, 0x1A}}\r
+  gDxeIchPlatformPolicyProtocolGuid     = { 0xf617b358, 0x12cf, 0x414a, {0xa0, 0x69, 0x60, 0x67, 0x7b, 0xda, 0x13, 0xb3}}\r
+  gEfiIchInfoProtocolGuid               = { 0xd31f0400, 0x7d16, 0x4316, {0xbf, 0x88, 0x60, 0x65, 0x88, 0x3b, 0x40, 0x2b}}\r
+  gEfiSmmIoTrapDispatchProtocolGuid     = { 0x58dc368d, 0x7bfa, 0x4e77, {0xab, 0xbc, 0x0e, 0x29, 0x41, 0x8d, 0xf9, 0x30}}\r
+  gEfiSmmSmbusProtocolGuid              = { 0x72e40094, 0x2ee1, 0x497a, {0x8f, 0x33, 0x4c, 0x93, 0x4a, 0x9e, 0x9c, 0x0c}}\r
+  gDxeVlvPlatformPolicyGuid             = { 0x5bab88ba, 0xe0e2, 0x4674, {0xb6, 0xad, 0xb8, 0x12, 0xf6, 0x88, 0x1c, 0xd6}}\r
+  gIgdOpRegionProtocolGuid              = { 0xcdc5dddf, 0xe79d, 0x41ec, {0xa9, 0xb0, 0x65, 0x65, 0x49, 0x0d, 0xb9, 0xd3}}\r
+  gEfiHeciProtocolGuid                  = { 0xcfb33810, 0x6e87, 0x4284, {0xb2, 0x03, 0xa6, 0x6a, 0xbe, 0x07, 0xf6, 0xe8}}\r
+  gPlatformSeCHookProtocolGuid          = { 0xbc52476e, 0xf67e, 0x4301, {0xb2, 0x62, 0x36, 0x9c, 0x48, 0x78, 0xaa, 0xc2}}\r
+  gEfiSeCRcInfoProtocolGuid             = { 0x11fbfdfb, 0x10d2, 0x43e6, {0xb5, 0xb1, 0xb4, 0x38, 0x6e, 0xdc, 0xcb, 0x9a}}\r
+  gEfiTdtProtocolGuid                   = { 0x0bf70067, 0xd53b, 0x42df, {0xb7, 0x70, 0xe9, 0x2c, 0x91, 0xc6, 0x14, 0x11}}\r
+  gDxePlatformSeCPolicyGuid             = { 0xf8bff014, 0x18fb, 0x4ef9, {0xb1, 0x0c, 0xae, 0x22, 0x73, 0x8d, 0xbe, 0xed}}\r
+  gLpssDummyProtocolGuid                = { 0xaf4cc162, 0xd41c, 0x455a, {0xab, 0x45, 0x6d, 0xbc, 0xc1, 0xcd, 0x32, 0xf3}}\r
+  gEfiEmmcCardInfoProtocolGuid          = { 0x1ebe5ab9, 0x2129, 0x49e7, {0x84, 0xd7, 0xee, 0xb9, 0xfc, 0xe5, 0xde, 0xdd}}\r
+  gEfiTdtOperationProtocolGuid          = {0xfd301ba4, 0x5e62, 0x4679,{ 0xa0, 0x6f, 0xe0, 0x9a, 0xab, 0xdd, 0x2a, 0x91}}\r
+  gEfiConfigFileNameGuid            = { 0x98B8D59B, 0xE8BA, 0x48EE, { 0x98, 0xDD, 0xC2, 0x95, 0x39, 0x2F, 0x1E, 0xDB }}\r
+  gEfiDFUResultGuid                 = { 0x14a7c46f, 0xbc02, 0x4047, { 0x9f, 0x18, 0xa5, 0xd7, 0x25, 0xd8, 0xbd, 0x19 }}\r
+\r
+[Guids]\r
+  gEfiCPTokenSpaceGuid                  = { 0x918211ce, 0xa1d2, 0x43a0, {0xa0, 0x4e, 0x75, 0xb5, 0xbf, 0x44, 0x50, 0x0E}}\r
+  gEfiSmbusArpMapGuid                   = { 0x707BE83E, 0x0BF6, 0x40A5, {0xBE, 0x64, 0x34, 0xC0, 0x3A, 0xA0, 0xB8, 0xE2}}\r
+  gEfiMemoryConfigDataGuid              = { 0x80dbd530, 0xb74c, 0x4f11, {0x8c, 0x03, 0x41, 0x86, 0x65, 0x53, 0x28, 0x31}}\r
+  gEfiVLVTokenSpaceGuid                 = { 0xca452c68, 0xdf0c, 0x45c9, {0x82, 0xfb, 0xea, 0xe4, 0x2b, 0x31, 0x29, 0x46}}\r
+  gSataControllerDriverGuid             = { 0xbb929da9, 0x68f7, 0x4035, {0xb2, 0x2c, 0xa3, 0xbb, 0x3f, 0x23, 0xda, 0x55}}\r
+  gDxePchPolicyUpdateProtocolGuid       = { 0x1a819e49, 0xd8ee, 0x48cb, {0x9a, 0x9c, 0x0a, 0xa0, 0xd2, 0x81, 0x0a, 0x38}}\r
+  gPowerManagementAcpiTableStorageGuid  = { 0x161be597, 0xe9c5, 0x49db, {0xae, 0x50, 0xc4, 0x62, 0xab, 0x54, 0xee, 0xda}}\r
+  gEfiSetupVariableGuid                 = { 0xec87d643, 0xeba4, 0x4bb5, {0xa1, 0xe5, 0x3f, 0x3e, 0x36, 0xb2, 0x0d, 0xa9}}\r
+  gBmpImageGuid                         = { 0x878AC2CC, 0x5343, 0x46F2, {0xB5, 0x63, 0x51, 0xF8, 0x9D, 0xAF, 0x56, 0xBA}}\r
+  gPchInitVariableGuid                  = { 0xe6c2f70a, 0xb604, 0x4877, {0x85, 0xba, 0xde, 0xec, 0x89, 0xe1, 0x17, 0xeb}}\r
+  gEfiMemoryConfigDataGuid              = { 0x80dbd530, 0xb74c, 0x4f11, {0x8c, 0x03, 0x41, 0x86, 0x65, 0x53, 0x28, 0x31}}\r
+  gVlvRefCodePkgTokenSpaceGuid          = { 0x85768E4A, 0x6CDC, 0x444E, {0x93, 0xDF, 0x93, 0x66, 0x85, 0xB5, 0xDF, 0xCC}}\r
+  gSeCPlatformReadyToBootGuid           = { 0x03fdf171, 0x1d67, 0x4ace, {0xa9, 0x04, 0x3e, 0x36, 0xd3, 0x38, 0xfa, 0x74}}\r
+  gAmtReadyToBootGuid                   = { 0x40b09b5a, 0xf0ef, 0x4627, {0x93, 0xd5, 0x27, 0xf0, 0x4b, 0x75, 0x4d, 0x05}}\r
+  #\r
+  # According to UEFI 2.3.1 Errata C, 3.2 Globally Defined Variables.\r
+  # To prevent name collisions with possible future globally defined variables,\r
+  # other internal firmware data variables that are not defined in Table.10 must be saved with a unique VendorGuid other than EFI_GLOBAL_VARIABLE.\r
+  #\r
+  gEfiVlv2VariableGuid                  = { 0x10ba6bbe, 0xa97e, 0x41c3, {0x9a, 0x07, 0x60, 0x7a, 0xd9, 0xbd, 0x60, 0xe5}}\r
+\r
+[Includes.common]\r
+  .\r
+  ValleyView2Soc/NorthCluster/Include\r
+  ValleyView2Soc/SouthCluster/Include\r
+  ValleyView2Soc/CPU/Include\r
+  Include\r
+\r
+[PcdsFixedAtBuild]\r
+  gEfiVLVTokenSpaceGuid.PcdTCSmbaIoBaseAddress|0x1040|UINT16|0x10000207\r
+\r
+[PcdsDynamic, PcdsDynamicEx]\r
+  gEfiVLVTokenSpaceGuid.PcdTCSmbaIoBaseAddress|0x1040|UINT16|0x10000207\r
+  gEfiVLVTokenSpaceGuid.PcdEmmcManufacturerId|0|UINT8|0x10000208\r
+  gEfiVLVTokenSpaceGuid.PcdProductSerialNumber|0|UINT32|0x10000209\r
+  gEfiVLVTokenSpaceGuid.PcdMeasuredBootEnable|TRUE|BOOLEAN|0x1000020A\r
+  gEfiVLVTokenSpaceGuid.PcdFTPMErrorOccur|FALSE|BOOLEAN|0x1000020B\r
+  gEfiVLVTokenSpaceGuid.PcdFTPMErrorSkip|FALSE|BOOLEAN|0x1000020C\r
+  gEfiVLVTokenSpaceGuid.PcdFTPMCommand|0|UINT32|0x1000020D\r
+  gEfiVLVTokenSpaceGuid.PcdFTPMResponse|0|UINT32|0x1000020E\r
+  gEfiVLVTokenSpaceGuid.PcdFTPMNotRespond|FALSE|BOOLEAN|0x1000020F\r
+  gEfiVLVTokenSpaceGuid.PcdFTPMStatus|0|UINT32|0x10000210\r
+\r
+[PcdsFeatureFlag]\r
+  gVlvRefCodePkgTokenSpaceGuid.PcdCeAtaSupport|FALSE|BOOLEAN|0x12\r
+  gVlvRefCodePkgTokenSpaceGuid.PcdMmcSdMultiBlockSupport|TRUE|BOOLEAN|0x13\r
+\r

diff --git a/Vlv2TbltDevicePkg/AcpiPlatform/AcpiPlatform.c b/Vlv2TbltDevicePkg/AcpiPlatform/AcpiPlatform.c
new file mode 100644 (file)
index 0000000..824f237
--- /dev/null
+++ b/Vlv2TbltDevicePkg/AcpiPlatform/AcpiPlatform.c
@@ -0,0 +1,1307 @@
+/** @file\r
+\r
+  Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r
+\r
+  This program and the accompanying materials are licensed and made available under\r
+\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r
+\r
+  The full text of the license may be found at                                     \r
+\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r
+\r
+                                                                                   \r
+\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r
+\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r
+\r
+                                                                                   \r
+\r
+\r
+\r
+\r
+Module Name:\r
+\r
+  AcpiPlatform.c\r
+\r
+Abstract:\r
+\r
+  ACPI Platform Driver\r
+\r
+\r
+--*/\r
+\r
+#include <PiDxe.h>\r
+#include <Protocol/TcgService.h>\r
+#include <Protocol/FirmwareVolume.h>\r
+#include "AcpiPlatform.h"\r
+#include "AcpiPlatformHooks.h"\r
+#include "AcpiPlatformHooksLib.h"\r
+#include "Platform.h"\r
+#include <Hpet.h>\r
+#include <Mcfg.h>\r
+#include "Osfr.h"\r
+#include <Guid/GlobalVariable.h>\r
+#include <Guid/SetupVariable.h>\r
+#include <Guid/PlatformInfo.h>\r
+#include <Protocol/CpuIo.h>\r
+#include <Guid/BoardFeatures.h>\r
+#include <Protocol/AcpiSupport.h>\r
+#include <Protocol/AcpiS3Save.h>\r
+#include <Protocol/Ps2Policy.h>\r
+#include <Library/CpuIA32.h>\r
+#include <SetupMode.h>\r
+#include <Guid/AcpiTableStorage.h>\r
+#include <Guid/EfiVpdData.h>\r
+#include <PchAccess.h>\r
+#include <Guid/Vlv2Variable.h>\r
+#include <Guid/PlatformCpuInfo.h>\r
+\r
+\r
+CHAR16    EfiPlatformCpuInfoVariable[] = L"PlatformCpuInfo";\r
+CHAR16    gACPIOSFRModelStringVariableName[] = ACPI_OSFR_MODEL_STRING_VARIABLE_NAME;\r
+CHAR16    gACPIOSFRRefDataBlockVariableName[] = ACPI_OSFR_REF_DATA_BLOCK_VARIABLE_NAME;\r
+CHAR16    gACPIOSFRMfgStringVariableName[] = ACPI_OSFR_MFG_STRING_VARIABLE_NAME;\r
+\r
+EFI_CPU_IO_PROTOCOL                    *mCpuIo;\r
+#ifndef __GNUC__\r
+#pragma optimize("", off)\r
+#endif\r
+BOOLEAN                   mFirstNotify;\r
+EFI_PLATFORM_INFO_HOB     *mPlatformInfo;\r
+EFI_GUID                  mSystemConfigurationGuid = SYSTEM_CONFIGURATION_GUID;\r
+SYSTEM_CONFIGURATION      mSystemConfiguration;\r
+SYSTEM_CONFIGURATION      mSystemConfig;\r
+\r
+UINT8 mSmbusRsvdAddresses[] = PLATFORM_SMBUS_RSVD_ADDRESSES;\r
+UINT8 mNumberSmbusAddress = sizeof( mSmbusRsvdAddresses ) / sizeof( mSmbusRsvdAddresses[0] );\r
+\r
+/**\r
+  Locate the first instance of a protocol.  If the protocol requested is an\r
+  FV protocol, then it will return the first FV that contains the ACPI table\r
+  storage file.\r
+\r
+  @param[in]  Protocol            The protocol to find.\r
+  @param[in]  Instance            Return pointer to the first instance of the protocol.\r
+  @param[in]  Type                The type of protocol to locate.\r
+\r
+  @retval  EFI_SUCCESS            The function completed successfully.\r
+  @retval  EFI_NOT_FOUND          The protocol could not be located.\r
+  @retval  EFI_OUT_OF_RESOURCES   There are not enough resources to find the protocol.\r
+\r
+**/\r
+EFI_STATUS\r
+LocateSupportProtocol (\r
+  IN   EFI_GUID       *Protocol,\r
+  OUT  VOID           **Instance,\r
+  IN   UINT32         Type\r
+  )\r
+{\r
+  EFI_STATUS              Status;\r
+  EFI_HANDLE              *HandleBuffer;\r
+  UINTN                   NumberOfHandles;\r
+  EFI_FV_FILETYPE         FileType;\r
+  UINT32                  FvStatus;\r
+  EFI_FV_FILE_ATTRIBUTES  Attributes;\r
+  UINTN                   Size;\r
+  UINTN                   Index;\r
+\r
+  FvStatus = 0;\r
+\r
+  //\r
+  // Locate protocol.\r
+  //\r
+  Status = gBS->LocateHandleBuffer (\r
+                  ByProtocol,\r
+                  Protocol,\r
+                  NULL,\r
+                  &NumberOfHandles,\r
+                  &HandleBuffer\r
+                  );\r
+  if (EFI_ERROR (Status)) {\r
+    //\r
+    // Defined errors at this time are not found and out of resources.\r
+    //\r
+    return Status;\r
+  }\r
+\r
+  //\r
+  // Looking for FV with ACPI storage file.\r
+  //\r
+  for (Index = 0; Index < NumberOfHandles; Index++) {\r
+    //\r
+    // Get the protocol on this handle.\r
+    // This should not fail because of LocateHandleBuffer.\r
+    //\r
+    Status = gBS->HandleProtocol (\r
+                    HandleBuffer[Index],\r
+                    Protocol,\r
+                    Instance\r
+                    );\r
+    ASSERT (!EFI_ERROR (Status));\r
+\r
+    if (!Type) {\r
+      //\r
+      // Not looking for the FV protocol, so find the first instance of the\r
+      // protocol.  There should not be any errors because our handle buffer\r
+      // should always contain at least one or LocateHandleBuffer would have\r
+      // returned not found.\r
+      //\r
+      break;\r
+    }\r
+\r
+    //\r
+    // See if it has the ACPI storage file.\r
+    //\r
+    Status = ((EFI_FIRMWARE_VOLUME_PROTOCOL *) (*Instance))->ReadFile (\r
+                                                              *Instance,\r
+                                                              &gEfiAcpiTableStorageGuid,\r
+                                                              NULL,\r
+                                                              &Size,\r
+                                                              &FileType,\r
+                                                              &Attributes,\r
+                                                              &FvStatus\r
+                                                              );\r
+\r
+    //\r
+    // If we found it, then we are done.\r
+    //\r
+    if (!EFI_ERROR (Status)) {\r
+      break;\r
+    }\r
+  }\r
+\r
+  //\r
+  // Our exit status is determined by the success of the previous operations.\r
+  // If the protocol was found, Instance already points to it.\r
+  //\r
+  //\r
+  // Free any allocated buffers.\r
+  //\r
+  gBS->FreePool (HandleBuffer);\r
+\r
+  return Status;\r
+}\r
+\r
+/**\r
+  This function will update any runtime platform specific information.\r
+  This currently includes:\r
+    Setting OEM table values, ID, table ID, creator ID and creator revision.\r
+    Enabling the proper processor entries in the APIC tables.\r
+\r
+  @param[in]  Table       The table to update.\r
+\r
+  @retval  EFI_SUCCESS    The function completed successfully.\r
+\r
+**/\r
+EFI_STATUS\r
+PlatformUpdateTables (\r
+  IN OUT EFI_ACPI_COMMON_HEADER  *Table\r
+  )\r
+{\r
+  EFI_ACPI_DESCRIPTION_HEADER                                 *TableHeader;\r
+  UINT8                                                       *CurrPtr;\r
+  UINT8                                                       *EndPtr;\r
+  ACPI_APIC_STRUCTURE_PTR                                     *ApicPtr;\r
+  UINT8                                                       CurrProcessor;\r
+  EFI_STATUS                                                  Status;\r
+  EFI_MP_SERVICES_PROTOCOL                                    *MpService;\r
+  UINTN                                                       MaximumNumberOfCPUs;\r
+  UINTN                                                       NumberOfEnabledCPUs;\r
+  UINTN                                                       BufferSize;\r
+  ACPI_APIC_STRUCTURE_PTR                                     *ProcessorLocalApicEntry;\r
+  UINTN                                                       BspIndex;\r
+  EFI_ACPI_1_0_ASF_DESCRIPTION_TABLE                          *AsfEntry;\r
+  EFI_ACPI_HIGH_PRECISION_EVENT_TIMER_TABLE_HEADER            *HpetTbl;\r
+  UINT64                                                      OemIdValue;\r
+  UINT8                                                       Index;\r
+  EFI_ACPI_3_0_FIXED_ACPI_DESCRIPTION_TABLE                   *Facp;\r
+  EFI_ACPI_OSFR_TABLE                                         *OsfrTable;\r
+  EFI_ACPI_OSFR_OCUR_OBJECT                                   *pOcurObject;\r
+  EFI_ACPI_OSFR_OCUR_OBJECT                                   OcurObject = {{0xB46F133D, 0x235F, 0x4634, 0x9F, 0x03, 0xB1, 0xC0, 0x1C, 0x54, 0x78, 0x5B}, 0, 0, 0, 0, 0};\r
+  CHAR16                                                      *OcurMfgStringBuffer = NULL;\r
+  CHAR16                                                      *OcurModelStringBuffer = NULL;\r
+  UINT8                                                       *OcurRefDataBlockBuffer = NULL;\r
+  UINTN                                                       OcurMfgStringBufferSize;\r
+  UINTN                                                       OcurModelStringBufferSize;\r
+  UINTN                                                       OcurRefDataBlockBufferSize;\r
+#if defined (IDCC2_SUPPORTED) && IDCC2_SUPPORTED\r
+  EFI_ACPI_ASPT_TABLE                                         *pSpttTable;\r
+#endif\r
+  UINT16                                                      NumberOfHpets;\r
+  UINT16                                                      HpetCapIdValue;\r
+  UINT32                                                      HpetBlockID;\r
+  UINTN                                                       LocalApicCounter;\r
+  EFI_PROCESSOR_INFORMATION                                   ProcessorInfoBuffer;\r
+  UINT8                                                       TempVal;\r
+  EFI_ACPI_3_0_IO_APIC_STRUCTURE                              *IOApicType;\r
+  EFI_ACPI_3_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER         *APICTableHeader;\r
+\r
+  CurrPtr                 = NULL;\r
+  EndPtr                  = NULL;\r
+  ApicPtr                 = NULL;\r
+  LocalApicCounter        = 0;\r
+  CurrProcessor           = 0;\r
+  ProcessorLocalApicEntry = NULL;\r
+\r
+\r
+ if (Table->Signature != EFI_ACPI_1_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_SIGNATURE) {\r
+    TableHeader = (EFI_ACPI_DESCRIPTION_HEADER *) Table;\r
+    //\r
+    // Update the OEMID.\r
+    //\r
+    OemIdValue = mPlatformInfo->AcpiOemId;\r
+\r
+    *(UINT32 *)(TableHeader->OemId)     = (UINT32)OemIdValue;\r
+    *(UINT16 *)(TableHeader->OemId + 4) = *(UINT16*)(((UINT8 *)&OemIdValue) + 4);\r
+\r
+    if ((Table->Signature != EFI_ACPI_2_0_SECONDARY_SYSTEM_DESCRIPTION_TABLE_SIGNATURE)) {\r
+    //\r
+    // Update the OEM Table ID.\r
+    //\r
+      TableHeader->OemTableId = mPlatformInfo->AcpiOemTableId;\r
+    }\r
+\r
+    //\r
+    // Update the OEM Table ID.\r
+    //\r
+    TableHeader->OemRevision = EFI_ACPI_OEM_REVISION;\r
+\r
+    //\r
+    // Update the creator ID.\r
+    //\r
+    TableHeader->CreatorId = EFI_ACPI_CREATOR_ID;\r
+\r
+    //\r
+    // Update the creator revision.\r
+    //\r
+    TableHeader->CreatorRevision = EFI_ACPI_CREATOR_REVISION;\r
+  }\r
+\r
+  //\r
+  // Complete this function.\r
+  //\r
+  //\r
+  // Locate the MP services protocol.\r
+  //\r
+  //\r
+  // Find the MP Protocol. This is an MP platform, so MP protocol must be\r
+  // there.\r
+  //\r
+  Status = gBS->LocateProtocol (\r
+                  &gEfiMpServiceProtocolGuid,\r
+                  NULL,\r
+                  (VOID **) &MpService\r
+                  );\r
+  if (EFI_ERROR (Status)) {\r
+    return Status;\r
+  }\r
+\r
+  //\r
+  // Determine the number of processors.\r
+  //\r
+  MpService->GetNumberOfProcessors (\r
+              MpService,\r
+              &MaximumNumberOfCPUs,\r
+              &NumberOfEnabledCPUs\r
+              );\r
+\r
+  ASSERT (MaximumNumberOfCPUs <= MAX_CPU_NUM && NumberOfEnabledCPUs >= 1);\r
+\r
+\r
+  //\r
+  // Assign a invalid intial value for update.\r
+  //\r
+  //\r
+  // Update the processors in the APIC table.\r
+  //\r
+  switch (Table->Signature) {\r
+    case EFI_ACPI_1_0_ASF_DESCRIPTION_TABLE_SIGNATURE:\r
+      //\r
+      // Update the table if ASF is enabled. Otherwise, return error so caller will not install.\r
+      //\r
+      if (mSystemConfig.Asf == 1) {\r
+        return  EFI_UNSUPPORTED;\r
+      }\r
+      AsfEntry = (EFI_ACPI_1_0_ASF_DESCRIPTION_TABLE *) Table;\r
+      TempVal = (mNumberSmbusAddress < ASF_ADDR_DEVICE_ARRAY_LENGTH)? mNumberSmbusAddress : ASF_ADDR_DEVICE_ARRAY_LENGTH;\r
+      for (Index = 0; Index < TempVal; Index++) {\r
+        AsfEntry->AsfAddr.FixedSmbusAddresses[Index] = mSmbusRsvdAddresses[Index];\r
+      }\r
+      break;\r
+\r
+    case EFI_ACPI_3_0_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE:\r
+\r
+      Status = MpService->WhoAmI (\r
+                            MpService,\r
+                            &BspIndex\r
+                            );\r
+\r
+      //\r
+      // PCAT_COMPAT Set to 1 indicate 8259 vectors should be disabled.\r
+      //\r
+      APICTableHeader = (EFI_ACPI_3_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER *)Table;\r
+      APICTableHeader->Flags |= EFI_ACPI_3_0_PCAT_COMPAT;\r
+\r
+      CurrPtr = (UINT8 *) &((EFI_ACPI_DESCRIPTION_HEADER *) Table)[1];\r
+      CurrPtr = CurrPtr + 8;\r
+\r
+      //\r
+      // Size of Local APIC Address & Flag.\r
+      //\r
+      EndPtr  = (UINT8 *) Table;\r
+      EndPtr  = EndPtr + Table->Length;\r
+      while (CurrPtr < EndPtr) {\r
+        ApicPtr = (ACPI_APIC_STRUCTURE_PTR *) CurrPtr;\r
+        switch (ApicPtr->AcpiApicCommon.Type) {\r
+          case EFI_ACPI_3_0_PROCESSOR_LOCAL_APIC:\r
+            //\r
+            // ESS override\r
+            // Fix for Ordering of MADT to be maintained as it is in MADT table.\r
+            //\r
+            // Update processor enabled or disabled and keep the local APIC\r
+            // order in MADT intact.\r
+            //\r
+            // Sanity check to make sure proc-id is not arbitrary.\r
+            //\r
+            DEBUG ((EFI_D_ERROR, "ApicPtr->AcpiLocalApic.AcpiProcessorId = %x, MaximumNumberOfCPUs = %x\n", \\r
+            ApicPtr->AcpiLocalApic.AcpiProcessorId, MaximumNumberOfCPUs));\r
+            if(ApicPtr->AcpiLocalApic.AcpiProcessorId > MaximumNumberOfCPUs) {\r
+              ApicPtr->AcpiLocalApic.AcpiProcessorId = (UINT8)MaximumNumberOfCPUs;\r
+            }\r
+\r
+            BufferSize                    = 0;\r
+            ApicPtr->AcpiLocalApic.Flags  = 0;\r
+\r
+            for (CurrProcessor = 0; CurrProcessor < MaximumNumberOfCPUs; CurrProcessor++) {\r
+              Status = MpService->GetProcessorInfo (\r
+                                    MpService,\r
+                                    CurrProcessor,\r
+                                    &ProcessorInfoBuffer\r
+                                    );\r
+\r
+              if (Status == EFI_SUCCESS && ProcessorInfoBuffer.ProcessorId == ApicPtr->AcpiLocalApic.ApicId) {\r
+                //\r
+                // Check to see whether or not a processor (or thread) is enabled.\r
+                //\r
+                if ((BspIndex == CurrProcessor) || ((ProcessorInfoBuffer.StatusFlag & PROCESSOR_ENABLED_BIT) != 0)) {\r
+                  //\r
+                  // Go on and check if Hyper Threading is enabled. If HT not enabled\r
+                  // hide this thread from OS by not setting the flag to 1.  This is the\r
+                  // software way to disable Hyper Threading.  Basically we just hide it\r
+                  // from the OS.\r
+                  //\r
+                  ApicPtr->AcpiLocalApic.Flags = EFI_ACPI_1_0_LOCAL_APIC_ENABLED;\r
+\r
+\r
+                  if(ProcessorInfoBuffer.Location.Thread != 0) {\r
+                    ApicPtr->AcpiLocalApic.Flags = 0;\r
+                  }\r
+\r
+                  AppendCpuMapTableEntry (&(ApicPtr->AcpiLocalApic));\r
+                }\r
+                break;\r
+              }\r
+            }\r
+\r
+            //\r
+            // If no APIC-ID match, the cpu may not be populated.\r
+            //\r
+            break;\r
+\r
+          case EFI_ACPI_3_0_IO_APIC:\r
+\r
+            IOApicType = (EFI_ACPI_3_0_IO_APIC_STRUCTURE *)CurrPtr;\r
+            IOApicType->IoApicId = 0x02;\r
+            //\r
+            // IO APIC entries can be patched here.\r
+            //\r
+            break;\r
+        }\r
+\r
+        CurrPtr = CurrPtr + ApicPtr->AcpiApicCommon.Length;\r
+      }\r
+      break;\r
+\r
+    case EFI_ACPI_3_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE:\r
+\r
+       Facp = (EFI_ACPI_3_0_FIXED_ACPI_DESCRIPTION_TABLE *) Table;\r
+       Facp->Flags &= (UINT32)(~(3<<2));\r
+\r
+      break;\r
+\r
+    case EFI_ACPI_3_0_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE:\r
+      //\r
+      // Patch the memory resource.\r
+      //\r
+      PatchDsdtTable ((EFI_ACPI_DESCRIPTION_HEADER *) Table);\r
+      break;\r
+\r
+    case EFI_ACPI_3_0_SECONDARY_SYSTEM_DESCRIPTION_TABLE_SIGNATURE:\r
+      //\r
+      // Gv3 support\r
+      //\r
+      // TBD: Need re-design based on the ValleyTrail platform.\r
+      //\r
+      break;\r
+\r
+    case EFI_ACPI_3_0_HIGH_PRECISION_EVENT_TIMER_TABLE_SIGNATURE:\r
+      //\r
+      // Adjust HPET Table to correct the Base Address.\r
+      //\r
+      // Enable HPET always as Hpet.asi always indicates that Hpet is enabled.\r
+      //\r
+      MmioOr8 (R_PCH_PCH_HPET + R_PCH_PCH_HPET_GCFG, B_PCH_PCH_HPET_GCFG_EN);\r
+\r
+\r
+      HpetTbl = (EFI_ACPI_HIGH_PRECISION_EVENT_TIMER_TABLE_HEADER *) Table;\r
+      HpetTbl->BaseAddressLower32Bit.Address = HPET_BASE_ADDRESS;\r
+      HpetTbl->EventTimerBlockId = *((UINT32*)(UINTN)HPET_BASE_ADDRESS);\r
+\r
+      HpetCapIdValue = *(UINT16 *)(UINTN)(HPET_BASE_ADDRESS);\r
+      NumberOfHpets = HpetCapIdValue & B_PCH_PCH_HPET_GCID_NT;  // Bits [8:12] contains the number of Hpets\r
+      HpetBlockID = EFI_ACPI_EVENT_TIMER_BLOCK_ID;\r
+\r
+      if((NumberOfHpets) && (NumberOfHpets & B_PCH_PCH_HPET_GCID_NT)) {\r
+        HpetBlockID |= (NumberOfHpets);\r
+      }\r
+      HpetTbl->EventTimerBlockId = HpetBlockID;\r
+\r
+      break;\r
+\r
+    case EFI_ACPI_3_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE:\r
+      //\r
+      // Update MCFG base and end bus number.\r
+      //\r
+      ((EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE *) Table)->Segment[0].BaseAddress\r
+        = mPlatformInfo->PciData.PciExpressBase;\r
+      ((EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE *) Table)->Segment[0].EndBusNumber\r
+        = (UINT8)RShiftU64 (mPlatformInfo->PciData.PciExpressSize, 20) - 1;\r
+      break;\r
+\r
+\r
+    case EFI_ACPI_OSFR_TABLE_SIGNATURE:\r
+      //\r
+      // Get size of OSFR variable.\r
+      //\r
+      OcurMfgStringBufferSize = 0;\r
+      Status = gRT->GetVariable (\r
+                      gACPIOSFRMfgStringVariableName,\r
+                      &gACPIOSFRMfgStringVariableGuid,\r
+                      NULL,\r
+                      &OcurMfgStringBufferSize,\r
+                      NULL\r
+                      );\r
+      if (Status != EFI_BUFFER_TOO_SMALL) {\r
+        //\r
+        // Variable must not be present on the system.\r
+        //\r
+        return EFI_UNSUPPORTED;\r
+      }\r
+\r
+      //\r
+      // Allocate memory for variable data.\r
+      //\r
+      OcurMfgStringBuffer = AllocatePool (OcurMfgStringBufferSize);\r
+      Status = gRT->GetVariable (\r
+                      gACPIOSFRMfgStringVariableName,\r
+                      &gACPIOSFRMfgStringVariableGuid,\r
+                      NULL,\r
+                      &OcurMfgStringBufferSize,\r
+                      OcurMfgStringBuffer\r
+                      );\r
+      if (!EFI_ERROR (Status)) {\r
+        OcurModelStringBufferSize = 0;\r
+        Status = gRT->GetVariable (\r
+                        gACPIOSFRModelStringVariableName,\r
+                        &gACPIOSFRModelStringVariableGuid,\r
+                        NULL,\r
+                        &OcurModelStringBufferSize,\r
+                        NULL\r
+                        );\r
+        if (Status != EFI_BUFFER_TOO_SMALL) {\r
+          //\r
+          // Variable must not be present on the system.\r
+          //\r
+          return EFI_UNSUPPORTED;\r
+        }\r
+\r
+        //\r
+        // Allocate memory for variable data.\r
+        //\r
+        OcurModelStringBuffer = AllocatePool (OcurModelStringBufferSize);\r
+        Status = gRT->GetVariable (\r
+                        gACPIOSFRModelStringVariableName,\r
+                        &gACPIOSFRModelStringVariableGuid,\r
+                        NULL,\r
+                        &OcurModelStringBufferSize,\r
+                        OcurModelStringBuffer\r
+                        );\r
+        if (!EFI_ERROR (Status)) {\r
+          OcurRefDataBlockBufferSize = 0;\r
+          Status = gRT->GetVariable (\r
+                          gACPIOSFRRefDataBlockVariableName,\r
+                          &gACPIOSFRRefDataBlockVariableGuid,\r
+                          NULL,\r
+                          &OcurRefDataBlockBufferSize,\r
+                          NULL\r
+                          );\r
+          if (Status == EFI_BUFFER_TOO_SMALL) {\r
+            //\r
+            // Allocate memory for variable data.\r
+            //\r
+            OcurRefDataBlockBuffer = AllocatePool (OcurRefDataBlockBufferSize);\r
+            Status = gRT->GetVariable (\r
+                            gACPIOSFRRefDataBlockVariableName,\r
+                            &gACPIOSFRRefDataBlockVariableGuid,\r
+                            NULL,\r
+                            &OcurRefDataBlockBufferSize,\r
+                            OcurRefDataBlockBuffer\r
+                            );\r
+          }\r
+          OsfrTable = (EFI_ACPI_OSFR_TABLE *) Table;\r
+          //\r
+          // Currently only one object is defined: OCUR_OSFR_TABLE.\r
+          //\r
+          OsfrTable->ObjectCount = 1;\r
+          //\r
+          // Initialize table length to fixed portion of the ACPI OSFR table.\r
+          //\r
+          OsfrTable->Header.Length = sizeof (EFI_ACPI_OSFR_TABLE_FIXED_PORTION);\r
+          *(UINT32 *)((UINTN) OsfrTable + sizeof (EFI_ACPI_OSFR_TABLE_FIXED_PORTION)) = \\r
+            (UINT32) (sizeof (EFI_ACPI_OSFR_TABLE_FIXED_PORTION) + sizeof (UINT32));\r
+          pOcurObject = (EFI_ACPI_OSFR_OCUR_OBJECT *)((UINTN) OsfrTable + sizeof (EFI_ACPI_OSFR_TABLE_FIXED_PORTION) + \\r
+            sizeof (UINT32));\r
+          CopyMem (pOcurObject, &OcurObject, sizeof (EFI_ACPI_OSFR_OCUR_OBJECT));\r
+          pOcurObject->ManufacturerNameStringOffset = (UINT32)((UINTN) pOcurObject - (UINTN) OsfrTable + \\r
+            sizeof (EFI_ACPI_OSFR_OCUR_OBJECT));\r
+          pOcurObject->ModelNameStringOffset = (UINT32)((UINTN) pOcurObject - (UINTN) OsfrTable + \\r
+            sizeof (EFI_ACPI_OSFR_OCUR_OBJECT) + OcurMfgStringBufferSize);\r
+          if (OcurRefDataBlockBufferSize > 0) {\r
+            pOcurObject->MicrosoftReferenceOffset = (UINT32)((UINTN) pOcurObject - (UINTN) OsfrTable + \\r
+              sizeof (EFI_ACPI_OSFR_OCUR_OBJECT) + OcurMfgStringBufferSize + OcurModelStringBufferSize);\r
+          }\r
+          CopyMem ((UINTN *)((UINTN) pOcurObject + sizeof (EFI_ACPI_OSFR_OCUR_OBJECT)), OcurMfgStringBuffer, \\r
+            OcurMfgStringBufferSize);\r
+          CopyMem ((UINTN *)((UINTN) pOcurObject + sizeof (EFI_ACPI_OSFR_OCUR_OBJECT) + OcurMfgStringBufferSize), \\r
+            OcurModelStringBuffer, OcurModelStringBufferSize);\r
+          if (OcurRefDataBlockBufferSize > 0) {\r
+            CopyMem ((UINTN *)((UINTN) pOcurObject + sizeof (EFI_ACPI_OSFR_OCUR_OBJECT) + OcurMfgStringBufferSize + \\r
+            OcurModelStringBufferSize),OcurRefDataBlockBuffer, OcurRefDataBlockBufferSize);\r
+          }\r
+          OsfrTable->Header.Length += (UINT32)(OcurMfgStringBufferSize + OcurModelStringBufferSize + OcurRefDataBlockBufferSize);\r
+          OsfrTable->Header.Length += sizeof (EFI_ACPI_OSFR_OCUR_OBJECT) + sizeof (UINT32);\r
+        }\r
+      }\r
+      gBS->FreePool (OcurMfgStringBuffer);\r
+      gBS->FreePool (OcurModelStringBuffer);\r
+      gBS->FreePool (OcurRefDataBlockBuffer);\r
+      break;\r
+    default:\r
+      break;\r
+  }\r
+\r
+  //\r
+  //\r
+  // Update the hardware signature in the FACS structure.\r
+  //\r
+  //\r
+  // Locate the SPCR table and update based on current settings.\r
+  // The user may change CR settings via setup or other methods.\r
+  // The SPCR table must match.\r
+  //\r
+  return EFI_SUCCESS;\r
+}\r
+\r
+/**\r
+\r
+Routine Description:\r
+\r
+  GC_TODO: Add function description.\r
+\r
+Arguments:\r
+\r
+  Event   - GC_TODO: add argument description\r
+  Context - GC_TODO: add argument description\r
+\r
+Returns:\r
+\r
+  GC_TODO: add return values\r
+\r
+**/\r
+STATIC\r
+VOID\r
+EFIAPI\r
+OnReadyToBoot (\r
+  IN      EFI_EVENT                 Event,\r
+  IN      VOID                      *Context\r
+  )\r
+{\r
+  EFI_STATUS                  Status;\r
+  EFI_ACPI_TABLE_VERSION      TableVersion;\r
+  EFI_ACPI_SUPPORT_PROTOCOL   *AcpiSupport;\r
+  EFI_ACPI_S3_SAVE_PROTOCOL   *AcpiS3Save;\r
+  SYSTEM_CONFIGURATION        SetupVarBuffer;\r
+  UINTN                       VariableSize;\r
+  EFI_PLATFORM_CPU_INFO       *PlatformCpuInfoPtr = NULL;\r
+  EFI_PLATFORM_CPU_INFO       PlatformCpuInfo;\r
+  EFI_PEI_HOB_POINTERS          GuidHob;\r
+\r
+  if (mFirstNotify) {\r
+    return;\r
+  }\r
+\r
+  mFirstNotify = TRUE;\r
+\r
+  //\r
+  // To avoid compiler warning of "C4701: potentially uninitialized local variable 'PlatformCpuInfo' used".\r
+  //\r
+  PlatformCpuInfo.CpuVersion.FullCpuId = 0;\r
+\r
+  //\r
+  // Get Platform CPU Info HOB.\r
+  //\r
+  PlatformCpuInfoPtr = NULL;\r
+  ZeroMem (&PlatformCpuInfo, sizeof(EFI_PLATFORM_CPU_INFO));\r
+  VariableSize = sizeof(EFI_PLATFORM_CPU_INFO);\r
+  Status = gRT->GetVariable(\r
+                  EfiPlatformCpuInfoVariable,\r
+                  &gEfiVlv2VariableGuid,\r
+                  NULL,\r
+                  &VariableSize,\r
+                  PlatformCpuInfoPtr\r
+                  );\r
+  if (EFI_ERROR(Status)) {\r
+    GuidHob.Raw = GetHobList ();\r
+    if (GuidHob.Raw != NULL) {\r
+      if ((GuidHob.Raw = GetNextGuidHob (&gEfiPlatformCpuInfoGuid, GuidHob.Raw)) != NULL) {\r
+        PlatformCpuInfoPtr = GET_GUID_HOB_DATA (GuidHob.Guid);\r
+      }\r
+    }\r
+  }\r
+\r
+  if ((PlatformCpuInfoPtr != NULL)) {\r
+    CopyMem(&PlatformCpuInfo, PlatformCpuInfoPtr, sizeof(EFI_PLATFORM_CPU_INFO));\r
+  }\r
+\r
+  //\r
+  // Update the ACPI parameter blocks finally.\r
+  //\r
+  VariableSize = sizeof (SYSTEM_CONFIGURATION);\r
+  Status = gRT->GetVariable (\r
+                  L"Setup",\r
+                  &mSystemConfigurationGuid,\r
+                  NULL,\r
+                  &VariableSize,\r
+                  &SetupVarBuffer\r
+                  );\r
+  ASSERT_EFI_ERROR (Status);\r
+\r
+  //\r
+  // Find the AcpiSupport protocol.\r
+  //\r
+  Status = LocateSupportProtocol (&gEfiAcpiSupportProtocolGuid, (VOID **) &AcpiSupport, 0);\r
+  ASSERT_EFI_ERROR (Status);\r
+\r
+  TableVersion = EFI_ACPI_TABLE_VERSION_2_0;\r
+\r
+  //\r
+  // Publish ACPI 1.0 or 2.0 Tables.\r
+  //\r
+  Status = AcpiSupport->PublishTables (\r
+                          AcpiSupport,\r
+                          TableVersion\r
+                          );\r
+  ASSERT_EFI_ERROR (Status);\r
+\r
+  //\r
+  // S3 script save.\r
+  //\r
+  Status = gBS->LocateProtocol (&gEfiAcpiS3SaveProtocolGuid, NULL, (VOID **) &AcpiS3Save);\r
+  if (!EFI_ERROR (Status)) {\r
+    AcpiS3Save->S3Save (AcpiS3Save, NULL);\r
+  }\r
+\r
+}\r
+\r
+VOID\r
+PR1FSASetting (\r
+  IN VOID\r
+  )\r
+{\r
+  //\r
+  // for FSA on  PR1.\r
+  //\r
+  if (mPlatformInfo->BoardId == BOARD_ID_BL_FFRD && mPlatformInfo->BoardRev >= PR1) {\r
+    DEBUG((EFI_D_ERROR, "Set FSA status = 1 for FFRD PR1\n"));\r
+    mGlobalNvsArea.Area->FsaStatus  = mSystemConfiguration.PchFSAOn;\r
+  }\r
+  if (mPlatformInfo->BoardId == BOARD_ID_BL_FFRD8) {\r
+    DEBUG((EFI_D_ERROR, "Set FSA status = 1 for FFRD8\n"));\r
+    mGlobalNvsArea.Area->FsaStatus  = mSystemConfiguration.PchFSAOn;\r
+  }\r
+\r
+}\r
+\r
+/**\r
+  Entry point for Acpi platform driver.\r
+\r
+  @param[in]  ImageHandle        A handle for the image that is initializing this driver.\r
+  @param[in]  SystemTable        A pointer to the EFI system table.\r
+\r
+  @retval  EFI_SUCCESS           Driver initialized successfully.\r
+  @retval  EFI_LOAD_ERROR        Failed to Initialize or has been loaded.\r
+  @retval  EFI_OUT_OF_RESOURCES  Could not allocate needed resources.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+AcpiPlatformEntryPoint (\r
+  IN EFI_HANDLE         ImageHandle,\r
+  IN EFI_SYSTEM_TABLE   *SystemTable\r
+  )\r
+{\r
+  EFI_STATUS                    Status;\r
+  EFI_STATUS                    AcpiStatus;\r
+  EFI_ACPI_SUPPORT_PROTOCOL     *AcpiSupport;\r
+  EFI_FIRMWARE_VOLUME_PROTOCOL  *FwVol;\r
+  INTN                          Instance;\r
+  EFI_ACPI_COMMON_HEADER        *CurrentTable;\r
+  UINTN                         TableHandle;\r
+  UINT32                        FvStatus;\r
+  UINT32                        Size;\r
+  EFI_EVENT                     Event;\r
+  EFI_ACPI_TABLE_VERSION        TableVersion;\r
+  UINTN                         VarSize;\r
+  UINTN                         SysCfgSize;\r
+  EFI_HANDLE                    Handle;\r
+  EFI_PS2_POLICY_PROTOCOL       *Ps2Policy;\r
+  EFI_PEI_HOB_POINTERS          GuidHob;\r
+  UINT8                         PortData;\r
+  EFI_MP_SERVICES_PROTOCOL      *MpService;\r
+  UINTN                         MaximumNumberOfCPUs;\r
+  UINTN                         NumberOfEnabledCPUs;\r
+  UINT32                        Data32;\r
+  PCH_STEPPING                  pchStepping;\r
+\r
+  mFirstNotify      = FALSE;\r
+\r
+  TableVersion      = EFI_ACPI_TABLE_VERSION_2_0;\r
+  Instance          = 0;\r
+  CurrentTable      = NULL;\r
+  TableHandle       = 0;\r
+  Data32            = 0;\r
+\r
+  //\r
+  // Update HOB variable for PCI resource information.\r
+  // Get the HOB list.  If it is not present, then ASSERT.\r
+  //\r
+  GuidHob.Raw = GetHobList ();\r
+  if (GuidHob.Raw != NULL) {\r
+    if ((GuidHob.Raw = GetNextGuidHob (&gEfiPlatformInfoGuid, GuidHob.Raw)) != NULL) {\r
+      mPlatformInfo = GET_GUID_HOB_DATA (GuidHob.Guid);\r
+    }\r
+  }\r
+\r
+  //\r
+  // Search for the Memory Configuration GUID HOB.  If it is not present, then\r
+  // there's nothing we can do. It may not exist on the update path.\r
+  //\r
+  VarSize = sizeof(SYSTEM_CONFIGURATION);\r
+  Status = gRT->GetVariable(\r
+                  L"Setup",\r
+                  &mSystemConfigurationGuid,\r
+                  NULL,\r
+                  &VarSize,\r
+                  &mSystemConfiguration\r
+                  );\r
+  ASSERT_EFI_ERROR (Status);\r
+\r
+  //\r
+  // Find the AcpiSupport protocol.\r
+  //\r
+  Status = LocateSupportProtocol (&gEfiAcpiSupportProtocolGuid, (VOID **) &AcpiSupport, 0);\r
+  ASSERT_EFI_ERROR (Status);\r
+\r
+  //\r
+  // Locate the firmware volume protocol.\r
+  //\r
+  Status = LocateSupportProtocol (&gEfiFirmwareVolumeProtocolGuid, (VOID **) &FwVol, 1);\r
+  ASSERT_EFI_ERROR (Status);\r
+\r
+  //\r
+  // Read the current system configuration variable store.\r
+  //\r
+  SysCfgSize = sizeof(SYSTEM_CONFIGURATION);\r
+  Status = gRT->GetVariable (\r
+                  L"Setup",\r
+                  &gEfiNormalSetupGuid,\r
+                  NULL,\r
+                  &SysCfgSize,\r
+                  &mSystemConfig\r
+                  );\r
+\r
+  Status    = EFI_SUCCESS;\r
+  Instance  = 0;\r
+\r
+  //\r
+  // TBD: Need re-design based on the ValleyTrail platform.\r
+  //\r
+  Status = gBS->LocateProtocol (\r
+                  &gEfiMpServiceProtocolGuid,\r
+                  NULL,\r
+                  (VOID **) &MpService\r
+                  );\r
+  if (EFI_ERROR (Status)) {\r
+    return Status;\r
+  }\r
+\r
+  //\r
+  // Determine the number of processors.\r
+  //\r
+  MpService->GetNumberOfProcessors (\r
+               MpService,\r
+               &MaximumNumberOfCPUs,\r
+               &NumberOfEnabledCPUs\r
+               );\r
+\r
+  //\r
+  // Allocate and initialize the NVS area for SMM and ASL communication.\r
+  //\r
+  Status = gBS->AllocatePool (\r
+                  EfiACPIMemoryNVS,\r
+                  sizeof (EFI_GLOBAL_NVS_AREA),\r
+                  (void **)&mGlobalNvsArea.Area\r
+                  );\r
+  ASSERT_EFI_ERROR (Status);\r
+  gBS->SetMem (\r
+         mGlobalNvsArea.Area,\r
+         sizeof (EFI_GLOBAL_NVS_AREA),\r
+         0\r
+         );\r
+  DEBUG((EFI_D_ERROR, "mGlobalNvsArea.Area is at 0x%X\n", mGlobalNvsArea.Area));\r
+\r
+  //\r
+  // Update global NVS area for ASL and SMM init code to use.\r
+  //\r
+  mGlobalNvsArea.Area->ApicEnable                 = 1;\r
+  mGlobalNvsArea.Area->EmaEnable                  = 0;\r
+\r
+  mGlobalNvsArea.Area->NumberOfBatteries          = 1;\r
+  mGlobalNvsArea.Area->BatteryCapacity0           = 100;\r
+  mGlobalNvsArea.Area->BatteryStatus0             = 84;\r
+  mGlobalNvsArea.Area->OnboardCom                 = 1;\r
+  mGlobalNvsArea.Area->IdeMode                    = 0;\r
+  mGlobalNvsArea.Area->PowerState                 = 0;\r
+\r
+  mGlobalNvsArea.Area->LogicalProcessorCount    = (UINT8)NumberOfEnabledCPUs;\r
+\r
+  mGlobalNvsArea.Area->PassiveThermalTripPoint  = mSystemConfiguration.PassiveThermalTripPoint;\r
+  mGlobalNvsArea.Area->PassiveTc1Value          = mSystemConfiguration.PassiveTc1Value;\r
+  mGlobalNvsArea.Area->PassiveTc2Value          = mSystemConfiguration.PassiveTc2Value;\r
+  mGlobalNvsArea.Area->PassiveTspValue          = mSystemConfiguration.PassiveTspValue;\r
+  mGlobalNvsArea.Area->CriticalThermalTripPoint = mSystemConfiguration.CriticalThermalTripPoint;\r
+\r
+  mGlobalNvsArea.Area->IgdPanelType             = mSystemConfiguration.IgdFlatPanel;\r
+  mGlobalNvsArea.Area->IgdPanelScaling          = mSystemConfiguration.PanelScaling;\r
+  mGlobalNvsArea.Area->IgdSciSmiMode            = 0;\r
+  mGlobalNvsArea.Area->IgdTvFormat              = 0;\r
+  mGlobalNvsArea.Area->IgdTvMinor               = 0;\r
+  mGlobalNvsArea.Area->IgdSscConfig             = 1;\r
+  mGlobalNvsArea.Area->IgdBiaConfig             = mSystemConfiguration.IgdLcdIBia;\r
+  mGlobalNvsArea.Area->IgdBlcConfig             = mSystemConfiguration.IgdLcdIGmchBlc;\r
+  mGlobalNvsArea.Area->IgdDvmtMemSize           =  mSystemConfiguration.IgdDvmt50TotalAlloc;\r
+  mGlobalNvsArea.Area->IgdPAVP                  = mSystemConfiguration.PavpMode;\r
+\r
+  mGlobalNvsArea.Area->AlsEnable                = mSystemConfiguration.AlsEnable;\r
+  mGlobalNvsArea.Area->BacklightControlSupport  = 2;\r
+  mGlobalNvsArea.Area->BrightnessPercentage    = 100;\r
+  mGlobalNvsArea.Area->IgdState = 1;\r
+  mGlobalNvsArea.Area->LidState = 1;\r
+\r
+  mGlobalNvsArea.Area->DeviceId1 = 0x80000100 ;\r
+  mGlobalNvsArea.Area->DeviceId2 = 0x80000400 ;\r
+  mGlobalNvsArea.Area->DeviceId3 = 0x80000200 ;\r
+  mGlobalNvsArea.Area->DeviceId4 = 0x04;\r
+  mGlobalNvsArea.Area->DeviceId5 = 0x05;\r
+  mGlobalNvsArea.Area->NumberOfValidDeviceId = 4 ;\r
+  mGlobalNvsArea.Area->CurrentDeviceList = 0x0F ;\r
+  mGlobalNvsArea.Area->PreviousDeviceList = 0x0F ;\r
+\r
+  mGlobalNvsArea.Area->UartSelection = mSystemConfiguration.UartInterface;\r
+  mGlobalNvsArea.Area->PcuUart1Enable = mSystemConfiguration.PcuUart1;\r
+  mGlobalNvsArea.Area->NativePCIESupport = 1;\r
+\r
+\r
+\r
+\r
+\r
+  //\r
+  // Update BootMode: 0:ACPI mode; 1:PCI mode\r
+  //\r
+  mGlobalNvsArea.Area->LpssSccMode = mSystemConfiguration.LpssPciModeEnabled;\r
+  if (mSystemConfiguration.LpssMipiHsi == 0) {\r
+    mGlobalNvsArea.Area->MipiHsiAddr  = 0;\r
+    mGlobalNvsArea.Area->MipiHsiLen   = 0;\r
+    mGlobalNvsArea.Area->MipiHsi1Addr = 0;\r
+    mGlobalNvsArea.Area->MipiHsi1Len  = 0;\r
+  }\r
+\r
+  //\r
+  // Platform Flavor\r
+  //\r
+  mGlobalNvsArea.Area->PlatformFlavor = mPlatformInfo->PlatformFlavor;\r
+\r
+  //\r
+  // Update the Platform id\r
+  //\r
+  mGlobalNvsArea.Area->BoardID = mPlatformInfo->BoardId;\r
+\r
+  //\r
+  // Update the  Board Revision\r
+  //\r
+  mGlobalNvsArea.Area->FabID = mPlatformInfo->BoardRev;\r
+\r
+  //\r
+  // Update SOC Stepping\r
+  //\r
+  mGlobalNvsArea.Area->SocStepping = (UINT8)(PchStepping());\r
+\r
+  mGlobalNvsArea.Area->OtgMode = mSystemConfiguration.PchUsbOtg;\r
+\r
+  pchStepping = PchStepping();\r
+  if (mSystemConfiguration.UsbAutoMode == 1) {\r
+    //\r
+    // Auto mode is enabled.\r
+    //\r
+    if (PchA0 == pchStepping) {\r
+      //\r
+      //  For A0, EHCI is enabled as default.\r
+      //\r
+      mSystemConfiguration.PchUsb20       = 1;\r
+      mSystemConfiguration.PchUsb30Mode   = 0;\r
+      mSystemConfiguration.UsbXhciSupport = 0;\r
+      DEBUG ((EFI_D_INFO, "EHCI is enabled as default. SOC 0x%x\n", pchStepping));\r
+    } else {\r
+      //\r
+      //  For A1 and later, XHCI is enabled as default.\r
+      //\r
+      mSystemConfiguration.PchUsb20       = 0;\r
+      mSystemConfiguration.PchUsb30Mode   = 1;\r
+      mSystemConfiguration.UsbXhciSupport = 1;\r
+      DEBUG ((EFI_D_INFO, "XHCI is enabled as default. SOC 0x%x\n", pchStepping));\r
+    }\r
+  }\r
+\r
+  mGlobalNvsArea.Area->XhciMode = mSystemConfiguration.PchUsb30Mode;\r
+\r
+  mGlobalNvsArea.Area->Stepping = mPlatformInfo->IchRevision;\r
+\r
+  //\r
+  // Override invalid Pre-Boot Driver and XhciMode combination.\r
+  //\r
+  if ((mSystemConfiguration.UsbXhciSupport == 0) && (mSystemConfiguration.PchUsb30Mode == 3)) {\r
+    mGlobalNvsArea.Area->XhciMode = 2;\r
+  }\r
+  if ((mSystemConfiguration.UsbXhciSupport == 1) && (mSystemConfiguration.PchUsb30Mode == 2)) {\r
+    mGlobalNvsArea.Area->XhciMode = 3;\r
+  }\r
+\r
+  DEBUG ((EFI_D_ERROR, "ACPI NVS XHCI:0x%x\n", mGlobalNvsArea.Area->XhciMode));\r
+\r
+  mGlobalNvsArea.Area->PmicEnable                       = GLOBAL_NVS_DEVICE_DISABLE;\r
+  mGlobalNvsArea.Area->BatteryChargingSolution          = GLOBAL_NVS_DEVICE_DISABLE;\r
+  mGlobalNvsArea.Area->ISPDevSel                        = mSystemConfiguration.ISPDevSel;\r
+  mGlobalNvsArea.Area->LpeEnable                        = mSystemConfiguration.Lpe;\r
+\r
+  if (mSystemConfiguration.ISPEn == 0) {\r
+    mGlobalNvsArea.Area->ISPDevSel                      = GLOBAL_NVS_DEVICE_DISABLE;\r
+  }\r
+\r
+  mGlobalNvsArea.Area->WittEnable                       = mSystemConfiguration.WittEnable;\r
+  mGlobalNvsArea.Area->UtsEnable                        = mSystemConfiguration.UtsEnable;\r
+  mGlobalNvsArea.Area->SarEnable                        = mSystemConfiguration.SAR1;\r
+\r
+\r
+  mGlobalNvsArea.Area->ReservedO                        = 1;\r
+\r
+  SettingI2CTouchAddress();\r
+  mGlobalNvsArea.Area->IdleReserve= mSystemConfiguration.IdleReserve;\r
+  //\r
+  // Read BMBOUND and store it in GlobalNVS to pass into ASL.\r
+  //\r
+  // BUGBUG: code was moved into silicon reference code.\r
+  //\r
+  if (mSystemConfiguration.eMMCBootMode== 1) {\r
+    //\r
+    // Auto detect mode.\r
+    //\r
+    DEBUG ((EFI_D_ERROR, "Auto detect mode------------start\n"));\r
+\r
+    //\r
+    // Silicon Steppings.\r
+    //\r
+    switch (PchStepping()) {\r
+      case PchA0: // A0/A1\r
+      case PchA1:\r
+        DEBUG ((EFI_D_ERROR, "SOC A0/A1: eMMC 4.41 Configuration\n"));\r
+        mSystemConfiguration.LpsseMMCEnabled            = 1;\r
+        mSystemConfiguration.LpsseMMC45Enabled          = 0;\r
+        break;\r
+\r
+      case PchB0: // B0 and later.\r
+      default:\r
+        DEBUG ((EFI_D_ERROR, "SOC B0 and later: eMMC 4.5 Configuration\n"));\r
+        mSystemConfiguration.LpsseMMCEnabled            = 0;\r
+        mSystemConfiguration.LpsseMMC45Enabled          = 1;\r
+        break;\r
+   }\r
+  } else if (mSystemConfiguration.eMMCBootMode == 2) {\r
+      //\r
+      // eMMC 4.41\r
+      //\r
+      DEBUG ((EFI_D_ERROR, "Force to eMMC 4.41 Configuration\n"));\r
+      mSystemConfiguration.LpsseMMCEnabled            = 1;\r
+      mSystemConfiguration.LpsseMMC45Enabled          = 0;\r
+  } else if (mSystemConfiguration.eMMCBootMode == 3) {\r
+      //\r
+      // eMMC 4.5\r
+      //\r
+      DEBUG ((EFI_D_ERROR, "Force to eMMC 4.5 Configuration\n"));\r
+      mSystemConfiguration.LpsseMMCEnabled            = 0;\r
+      mSystemConfiguration.LpsseMMC45Enabled          = 1;\r
+\r
+  } else {\r
+      //\r
+      // Disable eMMC controllers.\r
+      //\r
+      DEBUG ((EFI_D_ERROR, "Disable eMMC controllers\n"));\r
+      mSystemConfiguration.LpsseMMCEnabled            = 0;\r
+      mSystemConfiguration.LpsseMMC45Enabled          = 0;\r
+  }\r
+\r
+  mGlobalNvsArea.Area->emmcVersion = 0;\r
+  if (mSystemConfiguration.LpsseMMCEnabled) {\r
+     DEBUG ((EFI_D_ERROR, "mGlobalNvsArea.Area->emmcVersion = 0\n"));\r
+     mGlobalNvsArea.Area->emmcVersion = 0;\r
+  }\r
+\r
+  if (mSystemConfiguration.LpsseMMC45Enabled) {\r
+     DEBUG ((EFI_D_ERROR, "mGlobalNvsArea.Area->emmcVersion = 1\n"));\r
+     mGlobalNvsArea.Area->emmcVersion = 1;\r
+  }\r
+\r
+  mGlobalNvsArea.Area->SdCardRemovable = mSystemConfiguration.SdCardRemovable;\r
+  \r
+  //\r
+  // Microsoft IOT\r
+  //\r
+  if ((mSystemConfiguration.LpssHsuart0FlowControlEnabled == 1) && \\r
+      (mSystemConfiguration.LpssPwm0Enabled == 0) && \\r
+      (mSystemConfiguration.LpssPwm1Enabled == 0)) {\r
+    mGlobalNvsArea.Area->MicrosoftIoT = GLOBAL_NVS_DEVICE_ENABLE;\r
+    DEBUG ((EFI_D_ERROR, "JP1 is set to be MSFT IOT configuration.\n"));\r
+  } else {\r
+    mGlobalNvsArea.Area->MicrosoftIoT = GLOBAL_NVS_DEVICE_DISABLE;\r
+    DEBUG ((EFI_D_ERROR, "JP1 is not set to be MSFT IOT configuration.\n"));\r
+  }\r
+  \r
+  //\r
+  // SIO related option.\r
+  //\r
+  Status = gBS->LocateProtocol (&gEfiCpuIoProtocolGuid, NULL, (void **)&mCpuIo);\r
+  ASSERT_EFI_ERROR (Status);\r
+\r
+  mGlobalNvsArea.Area->WPCN381U = GLOBAL_NVS_DEVICE_DISABLE;\r
+\r
+  mGlobalNvsArea.Area->DockedSioPresent = GLOBAL_NVS_DEVICE_DISABLE;\r
+\r
+  if (mGlobalNvsArea.Area->DockedSioPresent != GLOBAL_NVS_DEVICE_ENABLE) {\r
+    //\r
+    // Check ID for SIO WPCN381U.\r
+    //\r
+    Status = mCpuIo->Io.Read (\r
+                          mCpuIo,\r
+                          EfiCpuIoWidthUint8,\r
+                          WPCN381U_CONFIG_INDEX,\r
+                          1,\r
+                          &PortData\r
+                          );\r
+    ASSERT_EFI_ERROR (Status);\r
+    if (PortData != 0xFF) {\r
+      PortData = 0x20;\r
+      Status = mCpuIo->Io.Write (\r
+                            mCpuIo,\r
+                            EfiCpuIoWidthUint8,\r
+                            WPCN381U_CONFIG_INDEX,\r
+                            1,\r
+                            &PortData\r
+                            );\r
+      ASSERT_EFI_ERROR (Status);\r
+      Status = mCpuIo->Io.Read (\r
+                            mCpuIo,\r
+                            EfiCpuIoWidthUint8,\r
+                            WPCN381U_CONFIG_DATA,\r
+                            1,\r
+                            &PortData\r
+                            );\r
+      ASSERT_EFI_ERROR (Status);\r
+      if ((PortData == WPCN381U_CHIP_ID) || (PortData == WDCP376_CHIP_ID)) {\r
+        mGlobalNvsArea.Area->WPCN381U = GLOBAL_NVS_DEVICE_ENABLE;\r
+        mGlobalNvsArea.Area->OnboardCom = GLOBAL_NVS_DEVICE_ENABLE;\r
+        mGlobalNvsArea.Area->OnboardComCir = GLOBAL_NVS_DEVICE_DISABLE;\r
+      }\r
+    }\r
+  }\r
+\r
+\r
+\r
+  //\r
+  // Get Ps2 policy to set. Will be use if present.\r
+  //\r
+  Status =  gBS->LocateProtocol (\r
+                   &gEfiPs2PolicyProtocolGuid,\r
+                   NULL,\r
+                   (VOID **)&Ps2Policy\r
+                   );\r
+  if (!EFI_ERROR (Status)) {\r
+          Status = Ps2Policy->Ps2InitHardware (ImageHandle);\r
+  }\r
+\r
+  mGlobalNvsArea.Area->SDIOMode = mSystemConfiguration.LpssSdioMode;\r
+\r
+  Handle = NULL;\r
+  Status = gBS->InstallMultipleProtocolInterfaces (\r
+                  &Handle,\r
+                  &gEfiGlobalNvsAreaProtocolGuid,\r
+                  &mGlobalNvsArea,\r
+                  NULL\r
+                  );\r
+\r
+  //\r
+  // Read tables from the storage file.\r
+  //\r
+  while (!EFI_ERROR (Status)) {\r
+    CurrentTable = NULL;\r
+\r
+    Status = FwVol->ReadSection (\r
+                      FwVol,\r
+                      &gEfiAcpiTableStorageGuid,\r
+                      EFI_SECTION_RAW,\r
+                      Instance,\r
+                      (VOID **) &CurrentTable,\r
+                      (UINTN *) &Size,\r
+                      &FvStatus\r
+                      );\r
+\r
+    if (!EFI_ERROR (Status)) {\r
+      //\r
+      // Allow platform specific code to reject the table or update it.\r
+      //\r
+      AcpiStatus = AcpiPlatformHooksIsActiveTable (CurrentTable);\r
+\r
+      if (!EFI_ERROR (AcpiStatus)) {\r
+        //\r
+        // Perform any table specific updates.\r
+        //\r
+        AcpiStatus = PlatformUpdateTables (CurrentTable);\r
+        if (!EFI_ERROR (AcpiStatus)) {\r
+          //\r
+          // Add the table.\r
+          //\r
+          TableHandle = 0;\r
+          AcpiStatus = AcpiSupport->SetAcpiTable (\r
+                                      AcpiSupport,\r
+                                      CurrentTable,\r
+                                      TRUE,\r
+                                      TableVersion,\r
+                                      &TableHandle\r
+                                      );\r
+          ASSERT_EFI_ERROR (AcpiStatus);\r
+        }\r
+      }\r
+\r
+      //\r
+      // Increment the instance.\r
+      //\r
+      Instance++;\r
+    }\r
+  }\r
+\r
+  Status = EfiCreateEventReadyToBootEx (\r
+             TPL_NOTIFY,\r
+             OnReadyToBoot,\r
+             NULL,\r
+             &Event\r
+             );\r
+\r
+  //\r
+  // Finished.\r
+  //\r
+  return EFI_SUCCESS;\r
+}\r
+\r
+UINT8\r
+ReadCmosBank1Byte (\r
+  IN  UINT8                           Index\r
+  )\r
+{\r
+  UINT8                               Data;\r
+\r
+  IoWrite8(0x72, Index);\r
+  Data = IoRead8 (0x73);\r
+  return Data;\r
+}\r
+\r
+VOID\r
+WriteCmosBank1Byte (\r
+  IN  UINT8                           Index,\r
+  IN  UINT8                           Data\r
+  )\r
+{\r
+  IoWrite8 (0x72, Index);\r
+  IoWrite8 (0x73, Data);\r
+}\r
+\r
+\r
+\r
+VOID\r
+SettingI2CTouchAddress (\r
+  IN VOID\r
+  )\r
+{\r
+  if (mSystemConfiguration.I2CTouchAd == 0) {\r
+    //\r
+    // If setup menu select auto set I2C Touch Address base on board id.\r
+    //\r
+    if (mPlatformInfo->BoardId == BOARD_ID_BL_RVP ||\r
+        mPlatformInfo->BoardId == BOARD_ID_BL_STHI ||\r
+        mPlatformInfo->BoardId == BOARD_ID_BL_RVP_DDR3L ) {\r
+      //\r
+      //RVP\r
+      //\r
+      mGlobalNvsArea.Area->I2CTouchAddress = 0x4B;\r
+    } else if (mPlatformInfo->BoardId == BOARD_ID_BL_FFRD) {\r
+      //\r
+      //FFRD\r
+      //\r
+      mGlobalNvsArea.Area->I2CTouchAddress = 0x4A;\r
+    } else if (mPlatformInfo->BoardId == BOARD_ID_BB_RVP) {\r
+      mGlobalNvsArea.Area->I2CTouchAddress = 0x4C;\r
+    } else if (mPlatformInfo->BoardId == BOARD_ID_CVH) {\r
+      mGlobalNvsArea.Area->I2CTouchAddress = 0x4C;\r
+    } else if (mPlatformInfo->BoardId == BOARD_ID_BL_FFRD8) {\r
+      //\r
+      //FFRD8 uses 0x4A.\r
+      //\r
+      mGlobalNvsArea.Area->I2CTouchAddress = 0x4A;\r
+    }\r
+  } else {\r
+    mGlobalNvsArea.Area->I2CTouchAddress = mSystemConfiguration.I2CTouchAd;\r
+  }\r
+  DEBUG((EFI_D_ERROR, "GlobalNvsArea.Area->I2CTouchAddress: [%02x]\n", mGlobalNvsArea.Area->I2CTouchAddress));\r
+}\r
+\r
+\r

diff --git a/Vlv2TbltDevicePkg/AcpiPlatform/AcpiPlatform.h b/Vlv2TbltDevicePkg/AcpiPlatform/AcpiPlatform.h
new file mode 100644 (file)
index 0000000..fbc9272
--- /dev/null
+++ b/Vlv2TbltDevicePkg/AcpiPlatform/AcpiPlatform.h
@@ -0,0 +1,224 @@
+/*++\r
+\r
+  Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+\r
+Module Name:\r
+\r
+  AcpiPlatform.h\r
+\r
+Abstract:\r
+\r
+  This is an implementation of the ACPI platform driver.  Requirements for\r
+  this driver are defined in the Tiano ACPI External Product Specification,\r
+  revision 0.3.6.\r
+\r
+\r
+--*/\r
+\r
+#ifndef _ACPI_PLATFORM_H_\r
+#define _ACPI_PLATFORM_H_\r
+\r
+//\r
+// Statements that include other header files.\r
+//\r
+#include <FrameworkDxe.h>\r
+#include <PiDxe.h>\r
+#include <Base.h>\r
+#include <Library/UefiLib.h>\r
+#include <Library/BaseLib.h>\r
+#include <Library/UefiBootServicesTableLib.h>\r
+#include <Library/UefiRuntimeServicesTableLib.h>\r
+#include <Library/DebugLib.h>\r
+#include <Protocol/FirmwareVolume.h>\r
+#include <Library/PcdLib.h>\r
+#include <IndustryStandard/HighPrecisionEventTimerTable.h>\r
+#include <IndustryStandard/Acpi.h>\r
+#include <Protocol/AcpiSystemDescriptionTable.h>\r
+#include <Protocol/MpService.h>\r
+#include <Protocol/CpuIo.h>\r
+#include <IndustryStandard/Acpi30.h>\r
+#include <IndustryStandard/Acpi20.h>\r
+#include <Library/HobLib.h>\r
+#include <AlertStandardFormatTable.h>\r
+#include <Guid/SetupVariable.h>\r
+#include <Protocol/GlobalNvsArea.h>\r
+#include <Library/BaseMemoryLib.h>\r
+#include <Library/MemoryAllocationLib.h>\r
+#include <PchRegs.h>\r
+#include <Library/PchPlatformLib.h>\r
+//\r
+// Global variables.\r
+//\r
+EFI_GLOBAL_NVS_AREA_PROTOCOL  mGlobalNvsArea;\r
+\r
+//\r
+// ACPI table information used to initialize tables.\r
+#define EFI_ACPI_OEM_REVISION     0x00000003\r
+#define EFI_ACPI_CREATOR_ID       SIGNATURE_32 ('V', 'L', 'V', '2')\r
+#define EFI_ACPI_CREATOR_REVISION 0x0100000D\r
+\r
+#define WPCN381U_CONFIG_INDEX     0x2E\r
+#define WPCN381U_CONFIG_DATA      0x2F\r
+#define WPCN381U_CHIP_ID          0xF4\r
+#define WDCP376_CHIP_ID           0xF1\r
+\r
+#define MOBILE_PLATFORM 1\r
+#define DESKTOP_PLATFORM 2\r
+\r
+//\r
+// Define macros to build data structure signatures from characters.\r
+//\r
+#ifndef EFI_SIGNATURE_16\r
+#define EFI_SIGNATURE_16(A, B)        ((A) | (B << 8))\r
+#endif\r
+#ifndef EFI_SIGNATURE_32\r
+#define EFI_SIGNATURE_32(A, B, C, D)  (EFI_SIGNATURE_16 (A, B) | (EFI_SIGNATURE_16 (C, D) << 16))\r
+#endif\r
+#ifndef EFI_SIGNATURE_64\r
+#define EFI_SIGNATURE_64(A, B, C, D, E, F, G, H) \\r
+    (EFI_SIGNATURE_32 (A, B, C, D) | ((UINT64) (EFI_SIGNATURE_32 (E, F, G, H)) << 32))\r
+#endif\r
+\r
+\r
+#define GV3_SSDT_OEM_TABLE_IDBASE 0x4000\r
+\r
+//\r
+// Private Driver Data.\r
+//\r
+//\r
+// Define Union of IO APIC & Local APIC structure.\r
+//\r
+typedef union {\r
+  EFI_ACPI_2_0_PROCESSOR_LOCAL_APIC_STRUCTURE AcpiLocalApic;\r
+  EFI_ACPI_2_0_IO_APIC_STRUCTURE              AcpiIoApic;\r
+  struct {\r
+    UINT8 Type;\r
+    UINT8 Length;\r
+  } AcpiApicCommon;\r
+} ACPI_APIC_STRUCTURE_PTR;\r
+\r
+//\r
+// Protocol private structure definition.\r
+//\r
+\r
+/**\r
+  Entry point of the ACPI platform driver.\r
+\r
+  @param[in]  ImageHandle        EFI_HANDLE: A handle for the image that is initializing this driver.\r
+  @param[in]  SystemTable        EFI_SYSTEM_TABLE: A pointer to the EFI system table.\r
+\r
+  @retval  EFI_SUCCESS           Driver initialized successfully.\r
+  @retval  EFI_LOAD_ERROR        Failed to Initialize or has been loaded.\r
+  @retval  EFI_OUT_OF_RESOURCES  Could not allocate needed resources.\r
+\r
+**/\r
+EFI_STATUS\r
+InstallAcpiPlatform (\r
+  IN EFI_HANDLE           ImageHandle,\r
+  IN EFI_SYSTEM_TABLE     *SystemTable\r
+  );\r
+\r
+/**\r
+  Get Acpi Table Version.\r
+\r
+  @param[in]  ImageHandle          EFI_HANDLE: A handle for the image that is initializing this driver.\r
+  @param[in]  SystemTable          EFI_SYSTEM_TABLE: A pointer to the EFI system table.\r
+\r
+  @retval  EFI_SUCCESS:            Driver initialized successfully.\r
+  @retval  EFI_LOAD_ERROR:         Failed to Initialize or has been loaded.\r
+  @retval  EFI_OUT_OF_RESOURCES:   Could not allocate needed resources.\r
+\r
+--*/\r
+EFI_ACPI_TABLE_VERSION\r
+GetAcpiTableVersion (\r
+  VOID\r
+  );\r
+\r
+/**\r
+  The funtion returns Oem specific information of Acpi Platform.\r
+\r
+  @param[in]  OemId          OemId returned.\r
+  @param[in]  OemTableId     OemTableId returned.\r
+  @param[in]  OemRevision    OemRevision returned.\r
+\r
+  @retval  EFI_STATUS        Status of function execution.\r
+\r
+**/\r
+EFI_STATUS\r
+AcpiPlatformGetOemFields (\r
+  OUT UINT8   *OemId,\r
+  OUT UINT64  *OemTableId,\r
+  OUT UINT32  *OemRevision\r
+  );\r
+\r
+/**\r
+  The function returns Acpi table version.\r
+\r
+  @param[in]\r
+\r
+  @retval  EFI_ACPI_TABLE_VERSION   Acpi table version encoded as a UINT32.\r
+\r
+**/\r
+EFI_ACPI_TABLE_VERSION\r
+AcpiPlatformGetAcpiSetting (\r
+  VOID\r
+  );\r
+\r
+/**\r
+  Entry point for Acpi platform driver.\r
+\r
+  @param[in]  ImageHandle        A handle for the image that is initializing this driver.\r
+  @param[in]  SystemTable        A pointer to the EFI system table.\r
+\r
+  @retval  EFI_SUCCESS           Driver initialized successfully.\r
+  @retval  EFI_LOAD_ERROR        Failed to Initialize or has been loaded.\r
+  @retval  EFI_OUT_OF_RESOURCES  Could not allocate needed resources.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+AcpiPlatformEntryPoint (\r
+  IN EFI_HANDLE         ImageHandle,\r
+  IN EFI_SYSTEM_TABLE   *SystemTable\r
+  );\r
+\r
+UINT8\r
+ReadCmosBank1Byte (\r
+  IN  UINT8                           Index\r
+  );\r
+\r
+VOID\r
+WriteCmosBank1Byte (\r
+  IN  UINT8                           Index,\r
+  IN  UINT8                           Data\r
+  );\r
+\r
+VOID\r
+SelectNFCDevice (\r
+  IN VOID\r
+  );\r
+\r
+VOID\r
+SettingI2CTouchAddress (\r
+  IN VOID\r
+  );\r
+\r
+extern \r
+EFI_STATUS \r
+EFIAPI\r
+IsctDxeEntryPoint (\r
+  IN EFI_HANDLE       ImageHandle,\r
+  IN EFI_SYSTEM_TABLE *SystemTable\r
+  );\r
+\r
+#endif\r

diff --git a/Vlv2TbltDevicePkg/AcpiPlatform/AcpiPlatform.inf b/Vlv2TbltDevicePkg/AcpiPlatform/AcpiPlatform.inf
new file mode 100644 (file)
index 0000000..24fa913
--- /dev/null
+++ b/Vlv2TbltDevicePkg/AcpiPlatform/AcpiPlatform.inf
@@ -0,0 +1,90 @@
+#\r
+#\r
+# Copyright (c)  1999  - 2014, Intel Corporation. All rights reserved\r
+#                                                                                  \r\r
+# This program and the accompanying materials are licensed and made available under\r\r
+# the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+# The full text of the license may be found at                                     \r\r
+# http://opensource.org/licenses/bsd-license.php.                                  \r\r
+#                                                                                  \r\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+#                                                                                  \r\r
+#\r
+#\r
+#  Module Name:\r
+#\r
+#   AcpiPlatformBB.inf\r
+#\r
+#  Abstract:\r
+#\r
+#\r
+\r
+\r
+\r
+[defines]\r
+  INF_VERSION                    = 0x00010005\r
+  BASE_NAME                      = AcpiPlatform\r
+  FILE_GUID                      = F0F6F006-DAB4-44b2-A7A1-0F72EEDCA716\r
+  MODULE_TYPE                    = DXE_DRIVER\r
+  VERSION_STRING                 = 1.0\r
+  ENTRY_POINT                    = AcpiPlatformEntryPoint\r
+\r
+[sources.common]\r
+  AcpiPlatformHooks.c\r
+  AcpiPlatform.c\r
+\r
+[Packages]\r
+  Vlv2TbltDevicePkg/PlatformPkg.dec\r
+  MdePkg/MdePkg.dec\r
+  IntelFrameworkPkg/IntelFrameworkPkg.dec\r
+  MdeModulePkg/MdeModulePkg.dec\r
+  Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec\r
+  IntelFrameworkModulePkg/IntelFrameworkModulePkg.dec\r
+  Vlv2TbltDevicePkg/PlatformPkg.dec\r
+\r
+[LibraryClasses]\r
+  HobLib\r
+  UefiRuntimeServicesTableLib\r
+  UefiDriverEntryPoint\r
+  BaseMemoryLib\r
+  DebugLib\r
+  HobLib\r
+  IoLib\r
+  PchPlatformLib\r
+\r
+[Guids]\r
+  gACPIOSFRMfgStringVariableGuid\r
+  gEfiAcpiTableStorageGuid\r
+  gACPIOSFRMfgStringVariableGuid\r
+  gEfiBoardFeaturesGuid\r
+  gEfiPlatformInfoGuid\r
+  gEfiNormalSetupGuid\r
+  gACPIOSFRRefDataBlockVariableGuid\r
+  gACPIOSFRModelStringVariableGuid\r
+  gEfiPlatformCpuInfoGuid\r
+  gEfiVlv2VariableGuid\r
+\r
+[Protocols]\r
+  gEfiAcpiTableProtocolGuid                     # PROTOCOL ALWAYS_CONSUMED\r
+  gEnhancedSpeedstepProtocolGuid\r
+  gEfiPlatformCpuProtocolGuid\r
+  gEfiAcpiSupportProtocolGuid\r
+  gEfiAcpiS3SaveProtocolGuid\r
+  gEfiCpuIoProtocolGuid\r
+  gEfiPs2PolicyProtocolGuid\r
+  gEfiFirmwareVolume2ProtocolGuid\r
+  gEfiMpServiceProtocolGuid\r
+  gEfiGlobalNvsAreaProtocolGuid\r
+  gEfiTcgProtocolGuid\r
+  gEfiFirmwareVolumeProtocolGuid\r
+  gIgdOpRegionProtocolGuid\r
+\r
+[Pcd]\r
+  gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiTableStorageFile\r
+\r
+[Depex]\r
+  gEfiAcpiSupportProtocolGuid AND\r
+  gEfiMpServiceProtocolGuid AND\r
+  gEfiCpuIoProtocolGuid\r
+\r

diff --git a/Vlv2TbltDevicePkg/AcpiPlatform/AcpiPlatformHooks.c b/Vlv2TbltDevicePkg/AcpiPlatform/AcpiPlatformHooks.c
new file mode 100644 (file)
index 0000000..3489650
--- /dev/null
+++ b/Vlv2TbltDevicePkg/AcpiPlatform/AcpiPlatformHooks.c
@@ -0,0 +1,500 @@
+/** @file\r
+\r
+  Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+Module Name:\r
+\r
+  AcpiPlatformHooks.c\r
+\r
+Abstract:\r
+\r
+  ACPI Platform Driver Hooks\r
+\r
+--*/\r
+\r
+//\r
+// Statements that include other files.\r
+//\r
+#include "AcpiPlatform.h"\r
+#include "AcpiPlatformHooks.h"\r
+#include "Platform.h"\r
+\r
+//\r
+// Prototypes of the various hook functions.\r
+//\r
+#include "AcpiPlatformHooksLib.h"\r
+\r
+extern EFI_GLOBAL_NVS_AREA_PROTOCOL  mGlobalNvsArea;\r
+extern SYSTEM_CONFIGURATION             mSystemConfiguration;\r
+\r
+ENHANCED_SPEEDSTEP_PROTOCOL             *mEistProtocol  = NULL;\r
+\r
+EFI_CPU_ID_MAP              mCpuApicIdAcpiIdMapTable[MAX_CPU_NUM];\r
+\r
+EFI_STATUS\r
+AppendCpuMapTableEntry (\r
+  IN EFI_ACPI_2_0_PROCESSOR_LOCAL_APIC_STRUCTURE   *AcpiLocalApic\r
+  )\r
+{\r
+  BOOLEAN Added;\r
+  UINTN   Index;\r
+\r
+  for (Index = 0; Index < MAX_CPU_NUM; Index++) {\r
+    if ((mCpuApicIdAcpiIdMapTable[Index].ApicId == AcpiLocalApic->ApicId) && mCpuApicIdAcpiIdMapTable[Index].Flags) {\r
+      return EFI_SUCCESS;\r
+    }\r
+  }\r
+\r
+  Added = FALSE;\r
+  for (Index = 0; Index < MAX_CPU_NUM; Index++) {\r
+      if (!mCpuApicIdAcpiIdMapTable[Index].Flags) {\r
+        mCpuApicIdAcpiIdMapTable[Index].Flags           = 1;\r
+        mCpuApicIdAcpiIdMapTable[Index].ApicId          = AcpiLocalApic->ApicId;\r
+        mCpuApicIdAcpiIdMapTable[Index].AcpiProcessorId = AcpiLocalApic->AcpiProcessorId;\r
+      Added = TRUE;\r
+      break;\r
+    }\r
+  }\r
+\r
+  ASSERT (Added);\r
+  return EFI_SUCCESS;\r
+}\r
+\r
+UINT32\r
+ProcessorId2ApicId (\r
+  UINT32  AcpiProcessorId\r
+  )\r
+{\r
+  UINTN Index;\r
+\r
+  ASSERT (AcpiProcessorId < MAX_CPU_NUM);\r
+  for (Index = 0; Index < MAX_CPU_NUM; Index++) {\r
+    if (mCpuApicIdAcpiIdMapTable[Index].Flags && (mCpuApicIdAcpiIdMapTable[Index].AcpiProcessorId == AcpiProcessorId)) {\r
+      return mCpuApicIdAcpiIdMapTable[Index].ApicId;\r
+    }\r
+  }\r
+\r
+  return (UINT32) -1;\r
+}\r
+\r
+UINT8\r
+GetProcNumberInPackage (\r
+  IN UINT8  Package\r
+  )\r
+{\r
+  UINTN Index;\r
+  UINT8 Number;\r
+\r
+  Number = 0;\r
+  for (Index = 0; Index < MAX_CPU_NUM; Index++) {\r
+    if (mCpuApicIdAcpiIdMapTable[Index].Flags && (((mCpuApicIdAcpiIdMapTable[Index].ApicId >> 0x04) & 0x01) == Package)) {\r
+      Number++;\r
+    }\r
+  }\r
+\r
+  return Number;\r
+}\r
+\r
+EFI_STATUS\r
+LocateCpuEistProtocol (\r
+  IN UINT32                           CpuIndex,\r
+  OUT ENHANCED_SPEEDSTEP_PROTOCOL     **EistProtocol\r
+  )\r
+{\r
+  UINTN                       HandleCount;\r
+  EFI_HANDLE                  *HandleBuffer;\r
+  ENHANCED_SPEEDSTEP_PROTOCOL *EistProt;\r
+  UINTN                       Index;\r
+  UINT32                      ApicId;\r
+  EFI_STATUS                  Status;\r
+\r
+  HandleCount = 0;\r
+  gBS->LocateHandleBuffer (\r
+         ByProtocol,\r
+         &gEnhancedSpeedstepProtocolGuid,\r
+         NULL,\r
+         &HandleCount,\r
+         &HandleBuffer\r
+         );\r
+\r
+  Index     = 0;\r
+  EistProt  = NULL;\r
+  Status    = EFI_NOT_FOUND;\r
+  while (Index < HandleCount) {\r
+    gBS->HandleProtocol (\r
+           HandleBuffer[Index],\r
+           &gEnhancedSpeedstepProtocolGuid,\r
+          (VOID **) &EistProt\r
+           );\r
+    //\r
+    // Adjust the CpuIndex by +1 due to the AcpiProcessorId is 1 based.\r
+    //\r
+    ApicId = ProcessorId2ApicId (CpuIndex+1);\r
+    if (ApicId == (UINT32) -1) {\r
+      break;\r
+    }\r
+\r
+    if (EistProt->ProcApicId == ApicId) {\r
+      Status = EFI_SUCCESS;\r
+      break;\r
+    }\r
+\r
+    Index++;\r
+  }\r
+\r
+  if (HandleBuffer != NULL) {\r
+    gBS->FreePool (HandleBuffer);\r
+  }\r
+\r
+  if (!EFI_ERROR (Status)) {\r
+    *EistProtocol = EistProt;\r
+  } else {\r
+    *EistProtocol = NULL;\r
+  }\r
+\r
+  return Status;\r
+}\r
+\r
+EFI_STATUS\r
+PlatformHookInit (\r
+  VOID\r
+  )\r
+{\r
+  EFI_STATUS  Status;\r
+\r
+  Status = gBS->LocateProtocol (\r
+                  &gEnhancedSpeedstepProtocolGuid,\r
+                  NULL,\r
+                  (VOID **) &mEistProtocol\r
+                  );\r
+\r
+  ASSERT_EFI_ERROR (Status);\r
+\r
+  return Status;\r
+}\r
+\r
+/**\r
+  Called for every ACPI table found in the BIOS flash.\r
+  Returns whether a table is active or not. Inactive tables\r
+  are not published in the ACPI table list.\r
+\r
+  This hook can be used to implement optional SSDT tables or\r
+  enabling/disabling specific functionality (e.g. SPCR table)\r
+  based on a setup switch or platform preference. In case of\r
+  optional SSDT tables,the platform flash will include all the\r
+  SSDT tables but will return EFI_SUCCESS only for those tables\r
+  that need to be published.\r
+\r
+  @param[in]  *Table         Pointer to the active table.\r
+\r
+  @retval  EFI_SUCCESS       if the table is active.\r
+  @retval  EFI_UNSUPPORTED   if the table is not active.\r
+\r
+**/\r
+EFI_STATUS\r
+AcpiPlatformHooksIsActiveTable (\r
+  IN OUT EFI_ACPI_COMMON_HEADER     *Table\r
+  )\r
+{\r
+  EFI_ACPI_DESCRIPTION_HEADER *TableHeader;\r
+\r
+  TableHeader = (EFI_ACPI_DESCRIPTION_HEADER *) Table;\r
+\r
+  if (TableHeader->Signature == EFI_ACPI_2_0_STATIC_RESOURCE_AFFINITY_TABLE_SIGNATURE) {\r
+\r
+  }\r
+\r
+  if ((mSystemConfiguration.ENDBG2 == 0) && (CompareMem (&TableHeader->OemTableId, "INTLDBG2", 8) == 0)) {\r
+    return EFI_UNSUPPORTED;\r
+  }\r
+  return EFI_SUCCESS;\r
+}\r
+\r
+/**\r
+    Update the GV3 SSDT table.\r
+\r
+    @param[in][out]  *TableHeader   The table to be set.\r
+\r
+    @retval  EFI_SUCCESS            Returns Success.\r
+\r
+**/\r
+EFI_STATUS\r
+PatchGv3SsdtTable (\r
+  IN OUT   EFI_ACPI_DESCRIPTION_HEADER  *TableHeader\r
+  )\r
+{\r
+  EFI_STATUS                  Status;\r
+  UINT8                       *CurrPtr;\r
+  UINT8                       *SsdtPointer;\r
+  UINT32                      Signature;\r
+  UINT32                      CpuFixes;\r
+  UINT32                      NpssFixes;\r
+  UINT32                      SpssFixes;\r
+  UINT32                      CpuIndex;\r
+  UINT32                      PackageSize;\r
+  UINT32                      NewPackageSize;\r
+  UINT32                      AdjustSize;\r
+  UINTN                       EntryIndex;\r
+  UINTN                       TableIndex;\r
+  EFI_ACPI_NAME_COMMAND       *PssTable;\r
+  EFI_PSS_PACKAGE             *PssTableItemPtr;\r
+  ENHANCED_SPEEDSTEP_PROTOCOL *EistProt;\r
+  EIST_INFORMATION            *EistInfo;\r
+  EFI_ACPI_CPU_PSS_STATE      *PssState;\r
+  EFI_ACPI_NAMEPACK_DWORD     *NamePtr;\r
+  //\r
+  // Loop through the ASL looking for values that we must fix up.\r
+  //\r
+  NpssFixes = 0;\r
+  SpssFixes = 0;\r
+  CpuFixes  = 0;\r
+  CpuIndex  = 0;\r
+  CurrPtr   = (UINT8 *) TableHeader;\r
+\r
+  EistProt  = NULL;\r
+  for (SsdtPointer = CurrPtr; SsdtPointer <= (CurrPtr + ((EFI_ACPI_COMMON_HEADER *) CurrPtr)->Length); SsdtPointer++) {\r
+    Signature = *(UINT32 *) SsdtPointer;\r
+    switch (Signature) {\r
+\r
+    case SIGNATURE_32 ('_', 'P', 'R', '_'):\r
+      //\r
+      // _CPUX ('0' to '0xF')\r
+      //\r
+      CpuIndex = *(SsdtPointer + 7);\r
+      if (CpuIndex >= '0' && CpuIndex <= '9') {\r
+        CpuIndex -= '0';\r
+      } else {\r
+        if (CpuIndex > '9') {\r
+          CpuIndex -= '7';\r
+        }\r
+      }\r
+\r
+      CpuFixes++;\r
+      LocateCpuEistProtocol (CpuIndex, &EistProt);\r
+      break;\r
+\r
+    case SIGNATURE_32 ('D', 'O', 'M', 'N'):\r
+\r
+      NamePtr = ACPI_NAME_COMMAND_FROM_NAMEPACK_STR (SsdtPointer);\r
+      if (NamePtr->StartByte != AML_NAME_OP) {\r
+        continue;\r
+      }\r
+\r
+      if (NamePtr->Size != AML_NAME_DWORD_SIZE) {\r
+        continue;\r
+      }\r
+\r
+      NamePtr->Value = 0;\r
+\r
+        if (mCpuApicIdAcpiIdMapTable[CpuIndex].Flags) {\r
+          NamePtr->Value = (mCpuApicIdAcpiIdMapTable[CpuIndex].ApicId >> 0x04) & 0x01;\r
+      }\r
+      break;\r
+\r
+    case SIGNATURE_32 ('N', 'C', 'P', 'U'):\r
+\r
+      NamePtr = ACPI_NAME_COMMAND_FROM_NAMEPACK_STR (SsdtPointer);\r
+      if (NamePtr->StartByte != AML_NAME_OP) {\r
+        continue;\r
+      }\r
+\r
+      if (NamePtr->Size != AML_NAME_DWORD_SIZE) {\r
+        continue;\r
+      }\r
+\r
+        NamePtr->Value = 0;\r
+        if (mCpuApicIdAcpiIdMapTable[CpuIndex].Flags) {\r
+          NamePtr->Value = GetProcNumberInPackage ((mCpuApicIdAcpiIdMapTable[CpuIndex].ApicId >> 0x04) & 0x01);\r
+      }\r
+      break;\r
+\r
+    case SIGNATURE_32 ('N', 'P', 'S', 'S'):\r
+    case SIGNATURE_32 ('S', 'P', 'S', 'S'):\r
+      if (EistProt == NULL) {\r
+        continue;\r
+      }\r
+\r
+      PssTable = ACPI_NAME_COMMAND_FROM_NAME_STR (SsdtPointer);\r
+      if (PssTable->StartByte != AML_NAME_OP) {\r
+        continue;\r
+      }\r
+\r
+      Status      = EistProt->GetEistTable (EistProt, &EistInfo, (VOID **) &PssState);\r
+\r
+      AdjustSize  = PssTable->NumEntries * sizeof (EFI_PSS_PACKAGE);\r
+      AdjustSize -= EistInfo->NumStates * sizeof (EFI_PSS_PACKAGE);\r
+      PackageSize     = (PssTable->Size & 0xF) + ((PssTable->Size & 0xFF00) >> 4);\r
+      NewPackageSize  = PackageSize - AdjustSize;\r
+      PssTable->Size  = (UINT16) ((NewPackageSize & 0xF) + ((NewPackageSize & 0x0FF0) << 4));\r
+\r
+      //\r
+      // Set most significant two bits of byte zero to 01, meaning two bytes used.\r
+      //\r
+      PssTable->Size |= 0x40;\r
+\r
+      //\r
+      // Set unused table to Noop Code.\r
+      //\r
+      SetMem( (UINT8 *) PssTable + NewPackageSize + AML_NAME_PREFIX_SIZE, AdjustSize, AML_NOOP_OP);\r
+      PssTable->NumEntries  = (UINT8) EistInfo->NumStates;\r
+      PssTableItemPtr       = (EFI_PSS_PACKAGE *) ((UINT8 *) PssTable + sizeof (EFI_ACPI_NAME_COMMAND));\r
+\r
+      //\r
+      // Update the size.\r
+      //\r
+      for (TableIndex = 0; TableIndex < EistInfo->NumStates; TableIndex++) {\r
+        EntryIndex                = EistInfo->NumStates - TableIndex - 1;\r
+        PssTableItemPtr->CoreFreq = PssState[EntryIndex].CoreFrequency * PssState[EntryIndex].Control;\r
+        PssTableItemPtr->Power    = PssState[EntryIndex].Power * 1000;\r
+        if (PssTable->NameStr == SIGNATURE_32 ('N', 'P', 'S', 'S')) {\r
+          PssTableItemPtr->BMLatency    = PssState[EntryIndex].BusMasterLatency;\r
+          PssTableItemPtr->TransLatency = PssState[EntryIndex].TransitionLatency;\r
+        } else {\r
+          //\r
+          // This method should be supported by SMM PPM Handler.\r
+          //\r
+          PssTableItemPtr->BMLatency    = PssState[EntryIndex].BusMasterLatency * 2;\r
+          PssTableItemPtr->TransLatency = PssState[EntryIndex].TransitionLatency * 10;\r
+        }\r
+\r
+        PssTableItemPtr->Control  = PssState[EntryIndex].Control;\r
+        PssTableItemPtr->Status   = PssState[EntryIndex].Status;\r
+        PssTableItemPtr++;\r
+      }\r
+\r
+      if (PssTable->NameStr == SIGNATURE_32 ('N', 'P', 'S', 'S')) {\r
+        NpssFixes++;\r
+      } else {\r
+        SpssFixes++;\r
+      }\r
+\r
+      SsdtPointer = (UINT8 *) PssTable + PackageSize;\r
+      break;\r
+    }\r
+  }\r
+\r
+  //\r
+  // N fixes together currently.\r
+  //\r
+  ASSERT (CpuFixes == (UINT32) MAX_CPU_NUM);\r
+  ASSERT (SpssFixes == NpssFixes);\r
+  ASSERT (CpuFixes >= SpssFixes);\r
+\r
+  return EFI_SUCCESS;\r
+}\r
+\r
+/**\r
+    Update the DSDT table.\r
+\r
+    @param[in][out]  *TableHeader   The table to be set.\r
+\r
+    @retval  EFI_SUCCESS            Returns EFI_SUCCESS.\r
+\r
+**/\r
+EFI_STATUS\r
+PatchDsdtTable (\r
+  IN OUT   EFI_ACPI_DESCRIPTION_HEADER  *TableHeader\r
+  )\r
+{\r
+\r
+  UINT8                              *CurrPtr;\r
+  UINT8                              *DsdtPointer;\r
+  UINT32                             *Signature;\r
+  UINT8                              *EndPtr;\r
+  UINT8   *Operation;\r
+  UINT32  *Address;\r
+  UINT16  *Size;\r
+\r
+  //\r
+  // Fix PCI32 resource "FIX0" -- PSYS system status area\r
+  //\r
+  CurrPtr = (UINT8*) &((EFI_ACPI_DESCRIPTION_HEADER*) TableHeader)[0];\r
+  EndPtr = (UINT8*) TableHeader;\r
+  EndPtr = EndPtr + TableHeader->Length;\r
+  while (CurrPtr < (EndPtr-2)) {\r
+    //\r
+    // Removed the _S3 tag to indicate that we do not support S3. The 4th byte is blank space\r
+    // since there are only 3 char "_S3".\r
+    //\r
+    if (mSystemConfiguration.AcpiSuspendState == 0) {\r
+      //\r
+      // For iasl compiler version 20061109.\r
+      //\r
+      if ((CurrPtr[0] == '_') && (CurrPtr[1] == 'S') && (CurrPtr[2] == '3') && (CurrPtr[3] == '_')) {\r
+        break;\r
+      }\r
+      //\r
+      // For iasl compiler version 20040527.\r
+      //\r
+      if ((CurrPtr[0] == '\\') && (CurrPtr[1] == '_') && (CurrPtr[2] == 'S') && (CurrPtr[3] == '3')) {\r
+        break;\r
+      }\r
+    }\r
+    CurrPtr++;\r
+  }\r
+  CurrPtr = (UINT8*) &((EFI_ACPI_DESCRIPTION_HEADER*) TableHeader)[0];\r
+  EndPtr = (UINT8*) TableHeader;\r
+  EndPtr = EndPtr + TableHeader->Length;\r
+  while (CurrPtr < (EndPtr-2)) {\r
+    //\r
+    // For mipi dsi port select _DEP.\r
+    //\r
+    if (mSystemConfiguration.MipiDsi== 1) {\r
+      //\r
+      // For iasl compiler version 20061109.\r
+      //\r
+      if ((CurrPtr[0] == 'N') && (CurrPtr[1] == 'D') && (CurrPtr[2] == 'E') && (CurrPtr[3] == 'P')) {\r
+        CurrPtr[0] = '_';\r
+        break;\r
+      }\r
+\r
+    } else {\r
+      if ((CurrPtr[0] == 'P') && (CurrPtr[1] == 'D') && (CurrPtr[2] == 'E') && (CurrPtr[3] == 'P')) {\r
+        CurrPtr[0] = '_';\r
+        break;\r
+      }\r
+\r
+    }\r
+    CurrPtr++;\r
+  }\r
+  //\r
+  // Loop through the ASL looking for values that we must fix up.\r
+  //\r
+  CurrPtr = (UINT8 *) TableHeader;\r
+  for (DsdtPointer = CurrPtr; DsdtPointer <= (CurrPtr + ((EFI_ACPI_COMMON_HEADER *) CurrPtr)->Length); DsdtPointer++) {\r
+    Signature = (UINT32 *) DsdtPointer;\r
+\r
+    switch (*Signature) {\r
+    //\r
+    // GNVS operation region.\r
+    //\r
+    case (SIGNATURE_32 ('G', 'N', 'V', 'S')):\r
+      //\r
+      // Conditional match.  For Region Objects, the Operator will always be the\r
+      // byte immediately before the specific name.  Therefore, subtract 1 to check\r
+      // the Operator.\r
+      //\r
+      Operation = DsdtPointer - 1;\r
+      if (*Operation == AML_OPREGION_OP) {\r
+        Address   = (UINT32 *) (DsdtPointer + 6);\r
+        *Address  = (UINT32) (UINTN) mGlobalNvsArea.Area;\r
+        Size      = (UINT16 *) (DsdtPointer + 11);\r
+        *Size     = sizeof (EFI_GLOBAL_NVS_AREA);\r
+      }\r
+      break;\r
+    default:\r
+      break;\r
+    }\r
+  }\r
+  return EFI_SUCCESS;\r
+}\r
+\r

diff --git a/Vlv2TbltDevicePkg/AcpiPlatform/AcpiPlatformHooks.h b/Vlv2TbltDevicePkg/AcpiPlatform/AcpiPlatformHooks.h
new file mode 100644 (file)
index 0000000..164f45e
--- /dev/null
+++ b/Vlv2TbltDevicePkg/AcpiPlatform/AcpiPlatformHooks.h
@@ -0,0 +1,132 @@
+/*++\r
+\r
+  Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+Module Name:\r
+\r
+  AcpiPlatformHooks.h\r
+\r
+Abstract:\r
+\r
+  This is an implementation of the ACPI platform driver.  Requirements for\r
+  this driver are defined in the Tiano ACPI External Product Specification,\r
+  revision 0.3.6.\r
+\r
+--*/\r
+\r
+#ifndef _ACPI_PLATFORM_HOOKS_H_\r
+#define _ACPI_PLATFORM_HOOKS_H_\r
+\r
+//\r
+// Statements that include other header files\r
+//\r
+\r
+#include <IndustryStandard/Acpi.h>\r
+#include "Platform.h"\r
+#include <Protocol/EnhancedSpeedstep.h>\r
+\r
+#define AML_NAME_OP           0x08\r
+#define AML_METHOD_OP         0x14\r
+#define AML_OPREGION_OP       0x80\r
+#define AML_PACKAGE_OP        0x12  // Package operator.\r
+#define AML_NAME_PREFIX_SIZE  0x06\r
+#define AML_NAME_DWORD_SIZE   0x0C\r
+\r
+#pragma pack(1)\r
+\r
+typedef struct {\r
+  UINT8   AcpiProcessorId;\r
+  UINT8   ApicId;\r
+  UINT16  Flags;\r
+} EFI_CPU_ID_MAP;\r
+\r
+typedef struct {\r
+  UINT8   StartByte;\r
+  UINT32  NameStr;\r
+  UINT8   Size;\r
+  UINT32  Value;\r
+} EFI_ACPI_NAMEPACK_DWORD;\r
+\r
+typedef struct {\r
+  UINT8   StartByte;\r
+  UINT32  NameStr;\r
+  UINT8   OpCode;\r
+  UINT16  Size;                     // Hardcode to 16bit width because the table we use is fixed size\r
+  UINT8   NumEntries;\r
+} EFI_ACPI_NAME_COMMAND;\r
+\r
+typedef struct {\r
+  UINT8   PackageOp;\r
+  UINT8   PkgLeadByte;\r
+  UINT8   NumEntries;\r
+  UINT8   DwordPrefix0;\r
+  UINT32  CoreFreq;\r
+  UINT8   DwordPrefix1;\r
+  UINT32  Power;\r
+  UINT8   DwordPrefix2;\r
+  UINT32  TransLatency;\r
+  UINT8   DwordPrefix3;\r
+  UINT32  BMLatency;\r
+  UINT8   DwordPrefix4;\r
+  UINT32  Control;\r
+  UINT8   DwordPrefix5;\r
+  UINT32  Status;\r
+} EFI_PSS_PACKAGE;\r
+\r
+typedef struct {\r
+  UINT8 PackageOp;\r
+  UINT8 PkgLeadByte;\r
+  UINT8 NumEntries;\r
+  UINT8 BytePrefix0;\r
+  UINT8 Entries;\r
+  UINT8 BytePrefix1;\r
+  UINT8 Revision;\r
+  UINT8 BytePrefix2;\r
+  UINT8 Domain;\r
+  UINT8 BytePrefix3;\r
+  UINT8 Coordinate;\r
+  UINT8 BytePrefix4;\r
+  UINT8 ProcNumber;\r
+} EFI_PSD_PACKAGE;\r
+\r
+#pragma pack()\r
+\r
+#define ACPI_NAME_COMMAND_FROM_NAME_STR(a)  BASE_CR (a, EFI_ACPI_NAME_COMMAND, NameStr)\r
+#define ACPI_NAME_COMMAND_FROM_NAMEPACK_STR(a)  BASE_CR (a, EFI_ACPI_NAMEPACK_DWORD, NameStr)\r
+\r
+EFI_STATUS\r
+PlatformHookInit (\r
+  VOID\r
+  );\r
+\r
+\r
+EFI_STATUS\r
+PatchDsdtTable (\r
+  IN OUT   EFI_ACPI_DESCRIPTION_HEADER  *TableHeader\r
+  );\r
+\r
+EFI_STATUS\r
+PatchGv3SsdtTable (\r
+  IN OUT  EFI_ACPI_DESCRIPTION_HEADER *Table\r
+  );\r
+\r
+EFI_STATUS\r
+PatchErstTable (\r
+  IN OUT  EFI_ACPI_DESCRIPTION_HEADER *Table\r
+  );\r
+\r
+EFI_STATUS\r
+AppendCpuMapTableEntry (\r
+  IN EFI_ACPI_2_0_PROCESSOR_LOCAL_APIC_STRUCTURE   *AcpiLocalApic\r
+  );\r
+\r
+#endif\r

diff --git a/Vlv2TbltDevicePkg/AcpiPlatform/AcpiPlatformHooksLib.h b/Vlv2TbltDevicePkg/AcpiPlatform/AcpiPlatformHooksLib.h
new file mode 100644 (file)
index 0000000..f6a4b3b
--- /dev/null
+++ b/Vlv2TbltDevicePkg/AcpiPlatform/AcpiPlatformHooksLib.h
@@ -0,0 +1,96 @@
+/*++\r
+\r
+  Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+Module Name:\r
+\r
+  AcpiPlatformHooksLib.h\r
+\r
+Abstract:\r
+\r
+  This is an implementation of the ACPI platform driver.  Requirements for\r
+  this driver are defined in the Tiano ACPI External Product Specification,\r
+  revision 0.3.6.\r
+\r
+--*/\r
+\r
+#ifndef _ACPI_PLATFORM_HOOKS_LIB_H_\r
+#define _ACPI_PLATFORM_HOOKS_LIB_H_\r
+\r
+//\r
+// Statements that include other header files.\r
+//\r
+#include <IndustryStandard/Acpi.h>\r
+\r
+/**\r
+  Returns the ACPI table version that the platform wants.\r
+\r
+  @param[in]  None\r
+\r
+  @retval  EFI_ACPI_TABLE_VERSION_NONE  if ACPI is to be disabled.\r
+  @retval  EFI_ACPI_TABLE_VERSION_1_0B  if 1.0b.\r
+  @retval  EFI_ACPI_TABLE_VERSION_2_00  if 2.00.\r
+**/\r
+EFI_ACPI_TABLE_VERSION\r
+AcpiPlatformHooksGetAcpiTableVersion (\r
+  VOID\r
+  );\r
+\r
+/**\r
+  Returns the OEMID, OEM Table ID, OEM Revision.\r
+\r
+  @param[in]  None\r
+\r
+  @retval  OemId        OEM ID string for ACPI tables, maximum 6 ASCII characters.\r
+                        This is an OEM-supplied string that identifies the OEM.\r
+  @retval  OemTableId   An OEM-supplied string that the OEM uses to identify\r
+                        the particular data table. This field is particularly useful\r
+                        when defining a definition block to distinguish definition block\r
+                        functions. The OEM assigns each dissimilar table a new OEM Table ID.\r
+  @retval  OemRevision  An OEM-supplied revision number for ACPI tables.\r
+                        Larger numbers are assumed to be newer revisions.\r
+\r
+**/\r
+EFI_STATUS\r
+AcpiPlatformHooksGetOemFields (\r
+  OUT UINT8   *OemId,\r
+  OUT UINT64  *OemTableId,\r
+  OUT UINT32  *OemRevision\r
+  );\r
+\r
+ /**\r
+  Called for every ACPI table found in the BIOS flash.\r
+  Returns whether a table is active or not. Inactive tables\r
+  are not published in the ACPI table list. This hook can be\r
+  used to implement optional SSDT tables or enabling/disabling\r
+  specific functionality (e.g. SPCR table) based on a setup\r
+  switch or platform preference. In case of optional SSDT tables,\r
+  the platform flash will include all the SSDT tables but will\r
+  return EFI_SUCCESS only for those tables that need to be\r
+  published.\r
+  This hook can also be used to update the table data. The header\r
+  is updated by the common code. For example, if a platform wants\r
+  to use an SSDT table to export some platform settings to the\r
+  ACPI code, it needs to update the data inside that SSDT based\r
+  on platform preferences in this hook.\r
+\r
+  @param[in]  None\r
+\r
+  @retval  EFI_SUCCESS      if the table is active.\r
+  @retval  EFI_UNSUPPORTED  if the table is not active.\r
+**/\r
+EFI_STATUS\r
+AcpiPlatformHooksIsActiveTable (\r
+  IN OUT EFI_ACPI_COMMON_HEADER     *Table\r
+  );\r
+\r
+#endif\r

diff --git a/Vlv2TbltDevicePkg/AcpiPlatform/Osfr.h b/Vlv2TbltDevicePkg/AcpiPlatform/Osfr.h
new file mode 100644 (file)
index 0000000..1bef1af
--- /dev/null
+++ b/Vlv2TbltDevicePkg/AcpiPlatform/Osfr.h
@@ -0,0 +1,61 @@
+/*++\r
+\r
+  Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+Module Name:\r
+\r
+  Osfr.h\r
+\r
+Abstract:\r
+\r
+  This file describes the contents of the ACPI OSFR Table.\r
+\r
+--*/\r
+\r
+#ifndef _OSFR_H\r
+#define _OSFR_H\r
+\r
+//\r
+// Statements that include other files.\r
+//\r
+#include <IndustryStandard/Acpi10.h>\r
+#include <IndustryStandard/Acpi20.h>\r
+\r
+#pragma pack (1)\r
+\r
+#define EFI_ACPI_OSFR_TABLE_REVISION            0x1\r
+//#define EFI_ACPI_OSFR_TABLE_SIGNATURE           'RFSO'\r
+#define EFI_ACPI_OSFR_TABLE_SIGNATURE           SIGNATURE_32('O', 'S', 'F', 'R')  //'RFSO'\r
+\r
+typedef struct {\r
+  EFI_ACPI_DESCRIPTION_HEADER          Header;\r
+  UINT32                               ObjectCount;\r
+  UINT32                               TableDWORDs [64];\r
+} EFI_ACPI_OSFR_TABLE;\r
+\r
+typedef struct {\r
+  EFI_ACPI_DESCRIPTION_HEADER          Header;\r
+  UINT32                               ObjectCount;\r
+} EFI_ACPI_OSFR_TABLE_FIXED_PORTION;\r
+\r
+typedef struct {\r
+  EFI_GUID  ObjectUUID;\r
+  UINT32    Reserved1;\r
+  UINT32    ManufacturerNameStringOffset;\r
+  UINT32    ModelNameStringOffset;\r
+  UINT32    Reserved2;\r
+  UINT32    MicrosoftReferenceOffset;\r
+} EFI_ACPI_OSFR_OCUR_OBJECT;\r
+\r
+#pragma pack ()\r
+\r
+#endif\r

diff --git a/Vlv2TbltDevicePkg/Application/FirmwareUpdate/FirmwareUpdate.c b/Vlv2TbltDevicePkg/Application/FirmwareUpdate/FirmwareUpdate.c
new file mode 100644 (file)
index 0000000..709cdc7
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Application/FirmwareUpdate/FirmwareUpdate.c
@@ -0,0 +1,927 @@
+/** @file\r
+\r
+Copyright (c) 2007  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+**/\r
+\r
+#include "FirmwareUpdate.h"\r
+\r
+EFI_HII_HANDLE  HiiHandle;\r
+\r
+//\r
+// MinnowMax Flash Layout\r
+//\r
+//Start (hex)  End (hex)       Length (hex)    Area Name\r
+//-----------  ---------       ------------    ---------\r
+//00000000     007FFFFF        00800000        Flash Image\r
+//\r
+//00000000     00000FFF        00001000        Descriptor Region\r
+//00001000     004FFFFF        004FF000        TXE Region\r
+//00500000     007FFFFF        00300000        BIOS Region\r
+//\r
+FV_REGION_INFO mRegionInfo[] = {\r
+  {FixedPcdGet32 (PcdFlashDescriptorBase), FixedPcdGet32 (PcdFlashDescriptorSize), TRUE},\r
+  {FixedPcdGet32 (PcdTxeRomBase), FixedPcdGet32 (PcdTxeRomSize), TRUE},\r
+  {FixedPcdGet32 (PcdBiosRomBase), FixedPcdGet32 (PcdBiosRomSize), TRUE}\r
+};\r
+\r
+UINTN mRegionInfoCount = sizeof (mRegionInfo) / sizeof (mRegionInfo[0]);\r
+\r
+FV_INPUT_DATA mInputData = {0};\r
+\r
+EFI_SPI_PROTOCOL  *mSpiProtocol;\r
+\r
+EFI_STATUS\r
+GetRegionIndex (\r
+  IN  EFI_PHYSICAL_ADDRESS  Address,\r
+  OUT UINTN                 *RegionIndex\r
+  )\r
+{\r
+  UINTN Index;\r
+\r
+  for (Index = 0; Index < mRegionInfoCount; Index++) {\r
+    if (Address >= mRegionInfo[Index].Base &&\r
+        Address < (mRegionInfo[Index].Base + mRegionInfo[Index].Size)\r
+        ) {\r
+      break;\r
+    }\r
+  }\r
+\r
+  *RegionIndex = Index;\r
+  if (Index >= mRegionInfoCount) {\r
+    return EFI_NOT_FOUND;\r
+  }\r
+  return EFI_SUCCESS;\r
+}\r
+\r
+BOOLEAN\r
+UpdateBlock (\r
+  IN  EFI_PHYSICAL_ADDRESS  Address\r
+  )\r
+{\r
+  EFI_STATUS  Status;\r
+  UINTN       Index;\r
+\r
+  if (mInputData.FullFlashUpdate) {\r
+    return TRUE;\r
+  }\r
+\r
+  Status = GetRegionIndex (Address, &Index);\r
+  if ((!EFI_ERROR(Status)) && mRegionInfo[Index].Update) {\r
+    return TRUE;\r
+  }\r
+\r
+  return FALSE;\r
+}\r
+\r
+EFI_STATUS\r
+MarkRegionState (\r
+  IN  EFI_PHYSICAL_ADDRESS  Address,\r
+  IN  BOOLEAN               Update\r
+  )\r
+{\r
+  EFI_STATUS  Status;\r
+  UINTN       Index;\r
+\r
+  Status = GetRegionIndex (Address, &Index);\r
+  if (!EFI_ERROR(Status)) {\r
+    mRegionInfo[Index].Update = Update;\r
+  }\r
+\r
+  return Status;\r
+}\r
+\r
+UINTN\r
+InternalPrintToken (\r
+  IN  CONST CHAR16                     *Format,\r
+  IN  EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL  *Console,\r
+  IN  VA_LIST                          Marker\r
+  )\r
+{\r
+  EFI_STATUS  Status;\r
+  UINTN       Return;\r
+  CHAR16      *Buffer;\r
+  UINTN       BufferSize;\r
+\r
+  ASSERT (Format != NULL);\r
+  ASSERT (((UINTN) Format & BIT0) == 0);\r
+  ASSERT (Console != NULL);\r
+\r
+  BufferSize = (PcdGet32 (PcdUefiLibMaxPrintBufferSize) + 1) * sizeof (CHAR16);\r
+\r
+  Buffer = (CHAR16 *) AllocatePool(BufferSize);\r
+  ASSERT (Buffer != NULL);\r
+\r
+  Return = UnicodeVSPrint (Buffer, BufferSize, Format, Marker);\r
+\r
+  if (Console != NULL && Return > 0) {\r
+    //\r
+    // To be extra safe make sure Console has been initialized.\r
+    //\r
+    Status = Console->OutputString (Console, Buffer);\r
+    if (EFI_ERROR (Status)) {\r
+      Return = 0;\r
+    }\r
+  }\r
+\r
+  FreePool (Buffer);\r
+\r
+  return Return;\r
+}\r
+\r
+UINTN\r
+EFIAPI\r
+PrintToken (\r
+  IN UINT16             Token,\r
+  IN EFI_HII_HANDLE     Handle,\r
+  ...\r
+  )\r
+{\r
+  VA_LIST Marker;\r
+  UINTN   Return;\r
+  CHAR16  *Format;\r
+\r
+  VA_START (Marker, Handle);\r
+\r
+  Format = HiiGetString (Handle, Token, NULL);\r
+  ASSERT (Format != NULL);\r
+\r
+  Return = InternalPrintToken (Format, gST->ConOut, Marker);\r
+\r
+  FreePool (Format);\r
+\r
+  VA_END (Marker);\r
+\r
+  return Return;\r
+}\r
+\r
+EFI_STATUS\r
+ParseCommandLine (\r
+  IN  UINTN   Argc,\r
+  IN  CHAR16  **Argv\r
+  )\r
+{\r
+  EFI_STATUS  Status;\r
+  UINTN       Index;\r
+\r
+  //\r
+  // Check to make sure that the command line has enough arguments for minimal\r
+  // operation.  The minimum is just the file name.\r
+  //\r
+  if (Argc < 2 || Argc > 4) {\r
+    return EFI_INVALID_PARAMETER;\r
+  }\r
+\r
+  //\r
+  // Loop through command line arguments.\r
+  //\r
+  for (Index = 1; Index < Argc; Index++) {\r
+    //\r
+    // Make sure the string is valid.\r
+    //\r
+    if (StrLen (Argv[Index]) == 0) {;\r
+      PrintToken (STRING_TOKEN (STR_FWUPDATE_ZEROLENGTH_ARG), HiiHandle);\r
+      return EFI_INVALID_PARAMETER;\r
+    }\r
+\r
+    //\r
+    // Check to see if this is an option or the file name.\r
+    //\r
+    if ((Argv[Index])[0] == L'-' || (Argv[Index])[0] == L'/') {\r
+      //\r
+      // Parse the arguments.\r
+      //\r
+      if ((StrCmp (Argv[Index], L"-h") == 0) ||\r
+          (StrCmp (Argv[Index], L"--help") == 0) ||\r
+          (StrCmp (Argv[Index], L"/?") == 0) ||\r
+          (StrCmp (Argv[Index], L"/h") == 0)) {\r
+        //\r
+        // Print Help Information.\r
+        //\r
+        return EFI_INVALID_PARAMETER;\r
+      } else if (StrCmp (Argv[Index], L"-m") == 0) {\r
+        //\r
+        // Parse the MAC address here.\r
+        //\r
+        Status = ConvertMac(Argv[Index+1]);\r
+        if (EFI_ERROR(Status)) {\r
+          PrintToken (STRING_TOKEN (STR_FWUPDATE_INVAILD_MAC), HiiHandle);\r
+          return Status;\r
+        }\r
+\r
+        //\r
+        // Save the MAC address to mInputData.MacValue.\r
+        //\r
+        mInputData.UpdateMac= TRUE;\r
+        Index++;\r
+        } else {\r
+        //\r
+        // Invalid option was provided.\r
+        //\r
+        return EFI_INVALID_PARAMETER;\r
+      }\r
+    }\r
+    if ((Index == Argc - 1) && (StrCmp (Argv[Index - 1], L"-m") != 0)) {\r
+      //\r
+      // The only parameter that is not an option is the firmware image.  Check\r
+      // to make sure that the file exists.\r
+      //\r
+      Status = ShellIsFile (Argv[Index]);\r
+      if (EFI_ERROR (Status)) {\r
+        PrintToken (STRING_TOKEN (STR_FWUPDATE_FILE_NOT_FOUND_ERROR), HiiHandle, Argv[Index]);\r
+        return EFI_INVALID_PARAMETER;\r
+      }\r
+      if (StrLen (Argv[Index]) > INPUT_STRING_LEN) {\r
+        PrintToken (STRING_TOKEN (STR_FWUPDATE_PATH_ERROR), HiiHandle, Argv[Index]);\r
+        return EFI_INVALID_PARAMETER;\r
+      }\r
+      StrCpy (mInputData.FileName, Argv[Index]);\r
+      mInputData.UpdateFromFile = TRUE;\r
+    }\r
+  }\r
+\r
+  return EFI_SUCCESS;\r
+}\r
+\r
+INTN\r
+EFIAPI\r
+ShellAppMain (\r
+  IN UINTN Argc,\r
+  IN CHAR16 **Argv\r
+  )\r
+{\r
+  EFI_STATUS            Status;\r
+  UINTN                 Index;\r
+  UINT32                FileSize;\r
+  UINT32                BufferSize;\r
+  UINT8                 *FileBuffer;\r
+  UINT8                 *Buffer;\r
+  EFI_PHYSICAL_ADDRESS  Address;\r
+  UINTN                 CountOfBlocks;\r
+  EFI_TPL               OldTpl;\r
+  BOOLEAN               ResetRequired;\r
+  BOOLEAN               FlashError;\r
+\r
+  Index             = 0;\r
+  FileSize          = 0;\r
+  BufferSize        = 0;\r
+  FileBuffer        = NULL;\r
+  Buffer            = NULL;\r
+  Address           = 0;\r
+  CountOfBlocks     = 0;\r
+  ResetRequired     = FALSE;\r
+  FlashError        = FALSE;\r
+\r
+  Status = EFI_SUCCESS;\r
+\r
+  mInputData.FullFlashUpdate = TRUE;\r
+\r
+  //\r
+  // Publish our HII data.\r
+  //\r
+  HiiHandle = HiiAddPackages (\r
+                &gEfiCallerIdGuid,\r
+                NULL,\r
+                FirmwareUpdateStrings,\r
+                NULL\r
+                );\r
+  if (HiiHandle == NULL) {\r
+    Status = EFI_OUT_OF_RESOURCES;\r
+    goto Done;\r
+  }\r
+\r
+  //\r
+  // Locate the SPI protocol.\r
+  //\r
+  Status = gBS->LocateProtocol (\r
+                  &gEfiSpiProtocolGuid,\r
+                  NULL,\r
+                  (VOID **)&mSpiProtocol\r
+                  );\r
+  if (EFI_ERROR (Status)) {\r
+    PrintToken (STRING_TOKEN (STR_SPI_NOT_FOUND), HiiHandle);\r
+    return EFI_DEVICE_ERROR;\r
+  }\r
+\r
+  //\r
+  // Parse the command line.\r
+  //\r
+  Status = ParseCommandLine (Argc, Argv);\r
+  if (EFI_ERROR (Status)) {\r
+    PrintHelpInfo ();\r
+    Status = EFI_SUCCESS;\r
+    goto Done;\r
+  }\r
+\r
+  //\r
+  // Display sign-on information.\r
+  //\r
+  PrintToken (STRING_TOKEN (STR_FWUPDATE_FIRMWARE_VOL_UPDATE), HiiHandle);\r
+  PrintToken (STRING_TOKEN (STR_FWUPDATE_VERSION), HiiHandle);\r
+  PrintToken (STRING_TOKEN (STR_FWUPDATE_COPYRIGHT), HiiHandle);\r
+\r
+  //\r
+  // Test to see if the firmware needs to be updated.\r
+  //\r
+  if (mInputData.UpdateFromFile) {\r
+    //\r
+    // Get the file to use in the update.\r
+    //\r
+    PrintToken (STRING_TOKEN (STR_FWUPDATE_READ_FILE), HiiHandle, mInputData.FileName);\r
+    Status = ReadFileData (mInputData.FileName, &FileBuffer, &FileSize);\r
+    if (EFI_ERROR (Status)) {\r
+      PrintToken (STRING_TOKEN (STR_FWUPDATE_READ_FILE_ERROR), HiiHandle, mInputData.FileName);\r
+      goto Done;\r
+    }\r
+\r
+    //\r
+    // Check that the file and flash sizes match.\r
+    //\r
+    if (FileSize != PcdGet32 (PcdFlashChipSize)) {\r
+      PrintToken (STRING_TOKEN (STR_FWUPDATE_SIZE), HiiHandle);\r
+      Status = EFI_UNSUPPORTED;\r
+      goto Done;\r
+    }\r
+\r
+    //\r
+    // Display flash update information.\r
+    //\r
+    PrintToken (STRING_TOKEN (STR_FWUPDATE_UPDATING_FIRMWARE), HiiHandle);\r
+\r
+    //\r
+    // Update it.\r
+    //\r
+    Buffer        = FileBuffer;\r
+    BufferSize    = FileSize;\r
+    Address       = PcdGet32 (PcdFlashChipBase);\r
+    CountOfBlocks = (UINTN) (BufferSize / BLOCK_SIZE);\r
+\r
+    //\r
+    // Raise TPL to TPL_NOTIFY to block any event handler,\r
+    // while still allowing RaiseTPL(TPL_NOTIFY) within\r
+    // output driver during Print().\r
+    //\r
+    OldTpl = gBS->RaiseTPL (TPL_NOTIFY);\r
+    for (Index = 0; Index < CountOfBlocks; Index++) {\r
+      //\r
+      // Handle block based on address and contents.\r
+      //\r
+      if (!UpdateBlock (Address)) {\r
+        DEBUG((EFI_D_INFO, "Skipping block at 0x%lx\n", Address));\r
+      } else if (!EFI_ERROR (InternalCompareBlock (Address, Buffer))) {\r
+        DEBUG((EFI_D_INFO, "Skipping block at 0x%lx (already programmed)\n", Address));\r
+      } else {\r
+        //\r
+        // Display a dot for each block being updated.\r
+        //\r
+        Print (L".");\r
+\r
+        //\r
+        // Flag that the flash image will be changed and the system must be rebooted\r
+        // to use the change.\r
+        //\r
+        ResetRequired = TRUE;\r
+\r
+        //\r
+        // Make updating process uninterruptable,\r
+        // so that the flash memory area is not accessed by other entities\r
+        // which may interfere with the updating process.\r
+        //\r
+        Status  = InternalEraseBlock (Address);\r
+        ASSERT_EFI_ERROR(Status);\r
+        if (EFI_ERROR (Status)) {\r
+          gBS->RestoreTPL (OldTpl);\r
+          FlashError = TRUE;\r
+          goto Done;\r
+        }\r
+        Status = InternalWriteBlock (\r
+                  Address,\r
+                  Buffer,\r
+                  (BufferSize > BLOCK_SIZE ? BLOCK_SIZE : BufferSize)\r
+                  );\r
+        if (EFI_ERROR (Status)) {\r
+          gBS->RestoreTPL (OldTpl);\r
+          FlashError = TRUE;\r
+          goto Done;\r
+        }\r
+      }\r
+\r
+      //\r
+      // Move to next block to update.\r
+      //\r
+      Address += BLOCK_SIZE;\r
+      Buffer += BLOCK_SIZE;\r
+      if (BufferSize > BLOCK_SIZE) {\r
+        BufferSize -= BLOCK_SIZE;\r
+      } else {\r
+        BufferSize = 0;\r
+      }\r
+    }\r
+    gBS->RestoreTPL (OldTpl);\r
+\r
+    //\r
+    // Print result of update.\r
+    //\r
+    if (!FlashError) {\r
+      if (ResetRequired) {\r
+        Print (L"\n");\r
+        PrintToken (STRING_TOKEN (STR_FWUPDATE_UPDATE_SUCCESS), HiiHandle);\r
+      } else {\r
+        PrintToken (STRING_TOKEN (STR_FWUPDATE_NO_RESET), HiiHandle);\r
+      }\r
+    } else {\r
+      goto Done;\r
+    }\r
+  }\r
+\r
+  //\r
+  // All flash updates are done so see if the system needs to be reset.\r
+  //\r
+  if (ResetRequired && !FlashError) {\r
+    //\r
+    // Update successful.\r
+    //\r
+    for (Index = 5; Index > 0; Index--) {\r
+      PrintToken (STRING_TOKEN (STR_FWUPDATE_SHUTDOWN), HiiHandle, Index);\r
+      gBS->Stall (1000000);\r
+    }\r
+\r
+    gRT->ResetSystem (EfiResetShutdown, EFI_SUCCESS, 0, NULL);\r
+    PrintToken (STRING_TOKEN (STR_FWUPDATE_MANUAL_RESET), HiiHandle);\r
+    CpuDeadLoop ();\r
+  }\r
+\r
+Done:\r
+  //\r
+  // Print flash update failure message if error detected.\r
+  //\r
+  if (FlashError) {\r
+    PrintToken (STRING_TOKEN (STR_FWUPDATE_UPDATE_FAILED), HiiHandle, Index);\r
+  }\r
+\r
+  //\r
+  // Do cleanup.\r
+  //\r
+  if (HiiHandle != NULL) {\r
+    HiiRemovePackages (HiiHandle);\r
+  }\r
+  if (FileBuffer) {\r
+    gBS->FreePool (FileBuffer);\r
+  }\r
+\r
+  return Status;\r
+}\r
+\r
+STATIC\r
+EFI_STATUS\r
+InternalEraseBlock (\r
+  IN  EFI_PHYSICAL_ADDRESS BaseAddress\r
+  )\r
+/*++\r
+\r
+Routine Description:\r
+\r
+  Erase the whole block.\r
+\r
+Arguments:\r
+\r
+  BaseAddress  - Base address of the block to be erased.\r
+\r
+Returns:\r
+\r
+  EFI_SUCCESS - The command completed successfully.\r
+  Other       - Device error or wirte-locked, operation failed.\r
+\r
+--*/\r
+{\r
+  EFI_STATUS                              Status;\r
+  UINTN                                   NumBytes;\r
+\r
+  NumBytes = BLOCK_SIZE;\r
+\r
+  Status = SpiFlashBlockErase ((UINTN) BaseAddress, &NumBytes);\r
+\r
+  return Status;\r
+}\r
+\r
+#if 0\r
+STATIC\r
+EFI_STATUS\r
+InternalReadBlock (\r
+  IN  EFI_PHYSICAL_ADDRESS  BaseAddress,\r
+  OUT VOID                  *ReadBuffer\r
+  )\r
+{\r
+  EFI_STATUS    Status;\r
+  UINT32        BlockSize;\r
+\r
+  BlockSize = BLOCK_SIZE;\r
+\r
+  Status = SpiFlashRead ((UINTN) BaseAddress, &BlockSize, ReadBuffer);\r
+\r
+  return Status;\r
+}\r
+#endif\r
+\r
+STATIC\r
+EFI_STATUS\r
+InternalCompareBlock (\r
+  IN  EFI_PHYSICAL_ADDRESS        BaseAddress,\r
+  IN  UINT8                       *Buffer\r
+  )\r
+{\r
+  EFI_STATUS                              Status;\r
+  VOID                                    *CompareBuffer;\r
+  UINT32                                  NumBytes;\r
+  INTN                                    CompareResult;\r
+\r
+  NumBytes = BLOCK_SIZE;\r
+  CompareBuffer = AllocatePool (NumBytes);\r
+  if (CompareBuffer == NULL) {\r
+    Status = EFI_OUT_OF_RESOURCES;\r
+    goto Done;\r
+  }\r
+\r
+  Status = SpiFlashRead ((UINTN) BaseAddress, &NumBytes, CompareBuffer);\r
+  if (EFI_ERROR (Status)) {\r
+    goto Done;\r
+  }\r
+  CompareResult = CompareMem (CompareBuffer, Buffer, BLOCK_SIZE);\r
+  if (CompareResult != 0) {\r
+    Status = EFI_VOLUME_CORRUPTED;\r
+  }\r
+\r
+Done:\r
+  if (CompareBuffer != NULL) {\r
+    FreePool (CompareBuffer);\r
+  }\r
+\r
+  return Status;\r
+}\r
+\r
+STATIC\r
+EFI_STATUS\r
+InternalWriteBlock (\r
+  IN  EFI_PHYSICAL_ADDRESS        BaseAddress,\r
+  IN  UINT8                       *Buffer,\r
+  IN  UINT32                      BufferSize\r
+  )\r
+/*++\r
+\r
+Routine Description:\r
+\r
+  Write a block of data.\r
+\r
+Arguments:\r
+\r
+  BaseAddress  - Base address of the block.\r
+  Buffer       - Data buffer.\r
+  BufferSize   - Size of the buffer.\r
+\r
+Returns:\r
+\r
+  EFI_SUCCESS           - The command completed successfully.\r
+  EFI_INVALID_PARAMETER - Invalid parameter, can not proceed.\r
+  Other                 - Device error or wirte-locked, operation failed.\r
+\r
+--*/\r
+{\r
+  EFI_STATUS                              Status;\r
+\r
+  Status = SpiFlashWrite ((UINTN) BaseAddress, &BufferSize, Buffer);\r
+  ASSERT_EFI_ERROR(Status);\r
+  if (EFI_ERROR (Status)) {\r
+    DEBUG((EFI_D_ERROR, "\nFlash write error."));\r
+    return Status;\r
+  }\r
+\r
+  WriteBackInvalidateDataCacheRange ((VOID *) (UINTN) BaseAddress, BLOCK_SIZE);\r
+\r
+  Status = InternalCompareBlock (BaseAddress, Buffer);\r
+  if (EFI_ERROR (Status)) {\r
+    DEBUG((EFI_D_ERROR, "\nError when writing to BaseAddress %lx with different at offset %x.", BaseAddress, Status));\r
+  } else {\r
+    DEBUG((EFI_D_INFO, "\nVerified data written to Block at %lx is correct.", BaseAddress));\r
+  }\r
+\r
+  return Status;\r
+\r
+}\r
+\r
+STATIC\r
+EFI_STATUS\r
+ReadFileData (\r
+  IN  CHAR16   *FileName,\r
+  OUT UINT8    **Buffer,\r
+  OUT UINT32   *BufferSize\r
+  )\r
+{\r
+  EFI_STATUS             Status;\r
+  SHELL_FILE_HANDLE      FileHandle;\r
+  UINT64                 Size;\r
+  VOID                   *NewBuffer;\r
+  UINTN                  ReadSize;\r
+\r
+  FileHandle = NULL;\r
+  NewBuffer = NULL;\r
+  Size = 0;\r
+\r
+  Status = ShellOpenFileByName (FileName, &FileHandle, EFI_FILE_MODE_READ, 0);\r
+  if (EFI_ERROR (Status)) {\r
+    goto Done;\r
+  }\r
+\r
+  Status = FileHandleIsDirectory (FileHandle);\r
+  if (!EFI_ERROR (Status)) {\r
+    Status = EFI_NOT_FOUND;\r
+    goto Done;\r
+  }\r
+\r
+  Status = FileHandleGetSize (FileHandle, &Size);\r
+  if (EFI_ERROR (Status)) {\r
+    goto Done;\r
+  }\r
+\r
+  NewBuffer = AllocatePool ((UINTN) Size);\r
+\r
+  ReadSize = (UINTN) Size;\r
+  Status = FileHandleRead (FileHandle, &ReadSize, NewBuffer);\r
+  if (EFI_ERROR (Status)) {\r
+    goto Done;\r
+  } else if (ReadSize != (UINTN) Size) {\r
+    Status = EFI_INVALID_PARAMETER;\r
+    goto Done;\r
+  }\r
+\r
+Done:\r
+  if (FileHandle != NULL) {\r
+    ShellCloseFile (&FileHandle);\r
+  }\r
+\r
+  if (EFI_ERROR (Status)) {\r
+    if (NewBuffer != NULL) {\r
+      FreePool (NewBuffer);\r
+    }\r
+  } else {\r
+    *Buffer = NewBuffer;\r
+    *BufferSize = (UINT32) Size;\r
+  }\r
+\r
+  return Status;\r
+}\r
+\r
+STATIC\r
+VOID\r
+PrintHelpInfo (\r
+  VOID\r
+  )\r
+/*++\r
+\r
+Routine Description:\r
+\r
+  Print out help information.\r
+\r
+Arguments:\r
+\r
+  None.\r
+\r
+Returns:\r
+\r
+  None.\r
+\r
+--*/\r
+{\r
+  PrintToken (STRING_TOKEN (STR_FWUPDATE_FIRMWARE_VOL_UPDATE), HiiHandle);\r
+  PrintToken (STRING_TOKEN (STR_FWUPDATE_VERSION), HiiHandle);\r
+  PrintToken (STRING_TOKEN (STR_FWUPDATE_COPYRIGHT), HiiHandle);\r
+\r
+  Print (L"\n");\r
+  PrintToken (STRING_TOKEN (STR_FWUPDATE_USAGE), HiiHandle);\r
+  PrintToken (STRING_TOKEN (STR_FWUPDATE_USAGE_1), HiiHandle);\r
+  PrintToken (STRING_TOKEN (STR_FWUPDATE_USAGE_2), HiiHandle);\r
+  PrintToken (STRING_TOKEN (STR_FWUPDATE_USAGE_3), HiiHandle);\r
+  PrintToken (STRING_TOKEN (STR_FWUPDATE_USAGE_4), HiiHandle);\r
+\r
+  Print (L"\n");\r
+}\r
+\r
+/**\r
+  Read NumBytes bytes of data from the address specified by\r
+  PAddress into Buffer.\r
+\r
+  @param[in]      Address       The starting physical address of the read.\r
+  @param[in,out]  NumBytes      On input, the number of bytes to read. On output, the number\r
+                                of bytes actually read.\r
+  @param[out]     Buffer        The destination data buffer for the read.\r
+\r
+  @retval         EFI_SUCCESS       Opertion is successful.\r
+  @retval         EFI_DEVICE_ERROR  If there is any device errors.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+SpiFlashRead (\r
+  IN     UINTN     Address,\r
+  IN OUT UINT32    *NumBytes,\r
+     OUT UINT8     *Buffer\r
+  )\r
+{\r
+  EFI_STATUS    Status = EFI_SUCCESS;\r
+  UINTN         Offset = 0;\r
+\r
+  ASSERT ((NumBytes != NULL) && (Buffer != NULL));\r
+\r
+    Offset = Address - (UINTN)PcdGet32 (PcdFlashChipBase);\r
+\r
+    Status = mSpiProtocol->Execute (\r
+                             mSpiProtocol,\r
+                             1, //SPI_READ,\r
+                             0, //SPI_WREN,\r
+                             TRUE,\r
+                             TRUE,\r
+                             FALSE,\r
+                             Offset,\r
+                             BLOCK_SIZE,\r
+                             Buffer,\r
+                             EnumSpiRegionAll\r
+                             );\r
+    return Status;\r
+\r
+}\r
+\r
+/**\r
+  Write NumBytes bytes of data from Buffer to the address specified by\r
+  PAddresss.\r
+\r
+  @param[in]      Address         The starting physical address of the write.\r
+  @param[in,out]  NumBytes        On input, the number of bytes to write. On output,\r
+                                  the actual number of bytes written.\r
+  @param[in]      Buffer          The source data buffer for the write.\r
+\r
+  @retval         EFI_SUCCESS       Opertion is successful.\r
+  @retval         EFI_DEVICE_ERROR  If there is any device errors.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+SpiFlashWrite (\r
+  IN     UINTN     Address,\r
+  IN OUT UINT32    *NumBytes,\r
+  IN     UINT8     *Buffer\r
+  )\r
+{\r
+  EFI_STATUS                Status;\r
+  UINTN                     Offset;\r
+  UINT32                    Length;\r
+  UINT32                    RemainingBytes;\r
+\r
+  ASSERT ((NumBytes != NULL) && (Buffer != NULL));\r
+  ASSERT (Address >= (UINTN)PcdGet32 (PcdFlashChipBase));\r
+\r
+  Offset    = Address - (UINTN)PcdGet32 (PcdFlashChipBase);\r
+\r
+  ASSERT ((*NumBytes + Offset) <= (UINTN)PcdGet32 (PcdFlashChipSize));\r
+\r
+  Status = EFI_SUCCESS;\r
+  RemainingBytes = *NumBytes;\r
+\r
+  while (RemainingBytes > 0) {\r
+    if (RemainingBytes > SIZE_4KB) {\r
+      Length = SIZE_4KB;\r
+    } else {\r
+      Length = RemainingBytes;\r
+    }\r
+    Status = mSpiProtocol->Execute (\r
+                             mSpiProtocol,\r
+                             SPI_PROG,\r
+                             SPI_WREN,\r
+                             TRUE,\r
+                             TRUE,\r
+                             TRUE,\r
+                             (UINT32) Offset,\r
+                             Length,\r
+                             Buffer,\r
+                             EnumSpiRegionAll\r
+                             );\r
+    if (EFI_ERROR (Status)) {\r
+      break;\r
+    }\r
+    RemainingBytes -= Length;\r
+    Offset += Length;\r
+    Buffer += Length;\r
+  }\r
+\r
+  //\r
+  // Actual number of bytes written.\r
+  //\r
+  *NumBytes -= RemainingBytes;\r
+\r
+  return Status;\r
+}\r
+\r
+/**\r
+  Erase the block starting at Address.\r
+\r
+  @param[in]  Address         The starting physical address of the block to be erased.\r
+                              This library assume that caller garantee that the PAddress\r
+                              is at the starting address of this block.\r
+  @param[in]  NumBytes        On input, the number of bytes of the logical block to be erased.\r
+                              On output, the actual number of bytes erased.\r
+\r
+  @retval     EFI_SUCCESS.      Opertion is successful.\r
+  @retval     EFI_DEVICE_ERROR  If there is any device errors.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+SpiFlashBlockErase (\r
+  IN UINTN    Address,\r
+  IN UINTN    *NumBytes\r
+  )\r
+{\r
+  EFI_STATUS          Status;\r
+  UINTN               Offset;\r
+  UINTN               RemainingBytes;\r
+\r
+  ASSERT (NumBytes != NULL);\r
+  ASSERT (Address >= (UINTN)PcdGet32 (PcdFlashChipBase));\r
+\r
+  Offset    = Address - (UINTN)PcdGet32 (PcdFlashChipBase);\r
+\r
+  ASSERT ((*NumBytes % SIZE_4KB) == 0);\r
+  ASSERT ((*NumBytes + Offset) <= (UINTN)PcdGet32 (PcdFlashChipSize));\r
+\r
+  Status = EFI_SUCCESS;\r
+  RemainingBytes = *NumBytes;\r
+\r
+    while (RemainingBytes > 0) {\r
+      Status = mSpiProtocol->Execute (\r
+                               mSpiProtocol,\r
+                               SPI_SERASE,\r
+                               SPI_WREN,\r
+                               FALSE,\r
+                               TRUE,\r
+                               FALSE,\r
+                               (UINT32) Offset,\r
+                               0,\r
+                               NULL,\r
+                               EnumSpiRegionAll\r
+                               );\r
+      if (EFI_ERROR (Status)) {\r
+        break;\r
+      }\r
+      RemainingBytes -= SIZE_4KB;\r
+      Offset         += SIZE_4KB;\r
+    }\r
+\r
+  //\r
+  // Actual number of bytes erased.\r
+  //\r
+  *NumBytes -= RemainingBytes;\r
+\r
+  return Status;\r
+}\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+ConvertMac (\r
+  CHAR16 *Str\r
+  )\r
+{\r
+  UINTN Index;\r
+  UINT8 Temp[MAC_ADD_STR_LEN];\r
+\r
+  if (Str == NULL)\r
+    return EFI_INVALID_PARAMETER;\r
+\r
+  if (StrLen(Str) != MAC_ADD_STR_LEN)\r
+    return EFI_INVALID_PARAMETER;\r
+\r
+  for (Index = 0; Index < MAC_ADD_STR_LEN; Index++) {\r
+    if (Str[Index] >= 0x30 && Str[Index] <= 0x39) {\r
+      Temp[Index] = (UINT8)Str[Index] - 0x30;\r
+    } else if (Str[Index] >= 0x41 && Str[Index] <= 0x46) {\r
+      Temp[Index] = (UINT8)Str[Index] - 0x37;\r
+    } else if (Str[Index] >= 0x61 && Str[Index] <= 0x66) {\r
+      Temp[Index] = (UINT8)Str[Index] - 0x57;\r
+    } else {\r
+      return EFI_INVALID_PARAMETER;\r
+    }\r
+  }\r
+\r
+  for (Index = 0; Index < MAC_ADD_BYTE_COUNT; Index++) {\r
+    mInputData.MacValue[Index] = (Temp[2 * Index] << 4) + Temp[2 * Index + 1];\r
+  }\r
+\r
+  return EFI_SUCCESS;\r
+}\r
+\r

diff --git a/Vlv2TbltDevicePkg/Application/FirmwareUpdate/FirmwareUpdate.h b/Vlv2TbltDevicePkg/Application/FirmwareUpdate/FirmwareUpdate.h
new file mode 100644 (file)
index 0000000..6c1c4b6
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Application/FirmwareUpdate/FirmwareUpdate.h
@@ -0,0 +1,190 @@
+/** @file\r
+\r
+Copyright (c) 1999  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+**/\r
+\r
+#ifndef _FIRMWARE_UPDATE_H_\r
+#define _FIRMWARE_UPDATE_H_\r
+\r
+#include <Uefi.h>\r
+\r
+#include <PiDxe.h>\r
+\r
+#include <Guid/FileInfo.h>\r
+\r
+#include <Protocol/FirmwareVolumeBlock.h>\r
+#include <Protocol/LoadedImage.h>\r
+#include <Protocol/SimpleFileSystem.h>\r
+#include <Protocol/Spi.h>\r
+\r
+#include <Library/BaseLib.h>\r
+#include <Library/BaseMemoryLib.h>\r
+#include <Library/CacheMaintenanceLib.h>\r
+#include <Library/DebugLib.h>\r
+#include <Library/FileHandleLib.h>\r
+#include <Library/HiiLib.h>\r
+#include <Library/MemoryAllocationLib.h>\r
+#include <Library/PcdLib.h>\r
+#include <Library/PrintLib.h>\r
+#include <Library/ShellLib.h>\r
+#include <Library/UefiApplicationEntryPoint.h>\r
+#include <Library/UefiBootServicesTableLib.h>\r
+#include <Library/UefiLib.h>\r
+#include <Library/UefiRuntimeServicesTableLib.h>\r
+\r
+//\r
+// Function Prototypes.\r
+//\r
+STATIC\r
+EFI_STATUS\r
+ReadFileData (\r
+  IN  CHAR16   *FileName,\r
+  OUT UINT8    **Buffer,\r
+  OUT UINT32   *BufferSize\r
+  );\r
+\r
+STATIC\r
+EFI_STATUS\r
+InternalEraseBlock (\r
+  IN  EFI_PHYSICAL_ADDRESS    BaseAddress\r
+  );\r
+\r
+#if 0\r
+STATIC\r
+EFI_STATUS\r
+InternalReadBlock (\r
+  IN  EFI_PHYSICAL_ADDRESS    BaseAddress,\r
+  OUT VOID                    *ReadBuffer\r
+  );\r
+#endif\r
+\r
+STATIC\r
+EFI_STATUS\r
+InternalCompareBlock (\r
+  IN  EFI_PHYSICAL_ADDRESS    BaseAddress,\r
+  IN  UINT8                   *Buffer\r
+  );\r
+\r
+STATIC\r
+EFI_STATUS\r
+InternalWriteBlock (\r
+  IN  EFI_PHYSICAL_ADDRESS    BaseAddress,\r
+  IN  UINT8                   *Buffer,\r
+  IN  UINT32                  BufferSize\r
+  );\r
+\r
+STATIC\r
+VOID\r
+PrintHelpInfo (\r
+  VOID\r
+  );\r
+\r
+STATIC\r
+EFI_STATUS\r
+EFIAPI\r
+SpiFlashRead (\r
+  IN     UINTN     Address,\r
+  IN OUT UINT32    *NumBytes,\r
+     OUT UINT8     *Buffer\r
+  );\r
+\r
+STATIC\r
+EFI_STATUS\r
+EFIAPI\r
+SpiFlashWrite (\r
+  IN     UINTN     Address,\r
+  IN OUT UINT32    *NumBytes,\r
+  IN     UINT8     *Buffer\r
+  );\r
+\r
+STATIC\r
+EFI_STATUS\r
+EFIAPI\r
+SpiFlashBlockErase (\r
+  IN    UINTN    Address,\r
+  IN    UINTN    *NumBytes\r
+  );\r
+\r
+STATIC\r
+EFI_STATUS\r
+EFIAPI\r
+ConvertMac (\r
+  CHAR16 *Str\r
+  );\r
+\r
+EFI_STATUS\r
+InitializeFVUPDATE (\r
+  IN EFI_HANDLE           ImageHandle,\r
+  IN EFI_SYSTEM_TABLE     *SystemTable\r
+  );\r
+\r
+//\r
+// Flash specific definitions.\r
+// - Should we use a PCD for this information?\r
+//\r
+#define BLOCK_SIZE          SIZE_4KB\r
+\r
+//\r
+// Flash region layout and update information.\r
+//\r
+typedef struct {\r
+  EFI_PHYSICAL_ADDRESS  Base;\r
+  UINTN                 Size;\r
+  BOOLEAN               Update;\r
+} FV_REGION_INFO;\r
+\r
+//\r
+// MAC Address information.\r
+//\r
+#define MAC_ADD_STR_LEN       12\r
+#define MAC_ADD_STR_SIZE      (MAC_ADD_STR_LEN + 1)\r
+#define MAC_ADD_BYTE_COUNT    6\r
+#define MAC_ADD_TMP_STR_LEN   2\r
+#define MAC_ADD_TMP_STR_SIZE  (MAC_ADD_TMP_STR_LEN + 1)\r
+\r
+//\r
+// Command Line Data.\r
+//\r
+#define INPUT_STRING_LEN    255\r
+#define INPUT_STRING_SIZE   (INPUT_STRING_LEN + 1)\r
+typedef struct {\r
+  BOOLEAN   UpdateFromFile;\r
+  CHAR16    FileName[INPUT_STRING_SIZE];\r
+  BOOLEAN   UpdateMac;\r
+  UINT8     MacValue[MAC_ADD_BYTE_COUNT];\r
+  BOOLEAN   FullFlashUpdate;\r
+} FV_INPUT_DATA;\r
+\r
+//\r
+// Prefix Opcode Index on the host SPI controller.\r
+//\r
+typedef enum {\r
+  SPI_WREN,             // Prefix Opcode 0: Write Enable.\r
+  SPI_EWSR,             // Prefix Opcode 1: Enable Write Status Register.\r
+} PREFIX_OPCODE_INDEX;\r
+\r
+//\r
+// Opcode Menu Index on the host SPI controller.\r
+//\r
+typedef enum {\r
+  SPI_READ_ID,        // Opcode 0: READ ID, Read cycle with address.\r
+  SPI_READ,           // Opcode 1: READ, Read cycle with address.\r
+  SPI_RDSR,           // Opcode 2: Read Status Register, No address.\r
+  SPI_WRDI_SFDP,      // Opcode 3: Write Disable or Discovery Parameters, No address.\r
+  SPI_SERASE,         // Opcode 4: Sector Erase (4KB), Write cycle with address.\r
+  SPI_BERASE,         // Opcode 5: Block Erase (32KB), Write cycle with address.\r
+  SPI_PROG,           // Opcode 6: Byte Program, Write cycle with address.\r
+  SPI_WRSR,           // Opcode 7: Write Status Register, No address.\r
+} SPI_OPCODE_INDEX;\r
+\r
+#endif\r

diff --git a/Vlv2TbltDevicePkg/Application/FirmwareUpdate/FirmwareUpdate.inf b/Vlv2TbltDevicePkg/Application/FirmwareUpdate/FirmwareUpdate.inf
new file mode 100644 (file)
index 0000000..4e2ec32
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Application/FirmwareUpdate/FirmwareUpdate.inf
@@ -0,0 +1,90 @@
+## @file\r
+# Implements a Tunnel Mountain specific flash update program.  This will allow\r
+# users to update all regions of the flash as needed in a given update.\r
+#\r
+# Copyright (c) 2006  - 2014, Intel Corporation. All rights reserved.<BR>\r
+#                                                                                  \r\r
+# This program and the accompanying materials are licensed and made available under\r\r
+# the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+# The full text of the license may be found at                                     \r\r
+# http://opensource.org/licenses/bsd-license.php.                                  \r\r
+#                                                                                  \r\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+#                                                                                  \r\r
+#\r
+#\r
+##\r
+\r
+[Defines]\r
+  INF_VERSION                    = 0x00010005\r
+  BASE_NAME                      = FirmwareUpdate\r
+  FILE_GUID                      = AEFAF26C-FB6D-4fef-AF7A-9D78FF201FCA\r
+  MODULE_TYPE                    = UEFI_APPLICATION\r
+  VERSION_STRING                 = 1.0\r
+  ENTRY_POINT                    = ShellCEntryLib\r
+\r
+#\r
+# The following information is for reference only and not required by the build tools.\r
+#\r
+#  VALID_ARCHITECTURES           = X64\r
+#\r
+\r
+[Sources]\r
+  FirmwareUpdateStrings.uni\r
+  FirmwareUpdate.c\r
+  FirmwareUpdate.h\r
+\r
+[Packages]\r
+  MdeModulePkg/MdeModulePkg.dec\r
+  MdePkg/MdePkg.dec\r
+  IA32FamilyCpuPkg/IA32FamilyCpuPkg.dec\r
+  Vlv2TbltDevicePkg/PlatformPkg.dec\r
+  Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec\r
+  ShellPkg/ShellPkg.dec\r
+\r
+[LibraryClasses]\r
+  BaseLib\r
+  BaseMemoryLib\r
+  CacheMaintenanceLib\r
+  DebugLib\r
+  FileHandleLib\r
+  #FlashDeviceLib\r
+  #SpiFlashCommonLib\r
+  MemoryAllocationLib\r
+  PcdLib\r
+  ShellCEntryLib\r
+  ShellLib\r
+  UefiApplicationEntryPoint\r
+  UefiBootServicesTableLib\r
+  UefiLib\r
+  UefiRuntimeServicesTableLib\r
+\r
+[Protocols]\r
+  gEfiLoadedImageProtocolGuid                   # PROTOCOL ALWAYS_CONSUMED\r
+  gEfiFirmwareVolumeBlockProtocolGuid           # PROTOCOL ALWAYS_CONSUMED\r
+  gEfiSpiProtocolGuid\r
+\r
+[Pcd]\r
+  gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize   ## CONSUMES\r
+\r
+[FixedPcd]\r
+#  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize\r
+#  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase\r
+#  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize\r
+#  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase\r
+#  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize\r
+#  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase\r
+\r
+  gPlatformModuleTokenSpaceGuid.PcdFlashChipBase\r
+  gPlatformModuleTokenSpaceGuid.PcdFlashChipSize\r
+  gPlatformModuleTokenSpaceGuid.PcdFlashDescriptorBase\r
+  gPlatformModuleTokenSpaceGuid.PcdFlashDescriptorSize\r
+  gPlatformModuleTokenSpaceGuid.PcdTxeRomBase\r
+  gPlatformModuleTokenSpaceGuid.PcdTxeRomSize\r
+  gPlatformModuleTokenSpaceGuid.PcdBiosRomBase\r
+  gPlatformModuleTokenSpaceGuid.PcdBiosRomSize\r
+\r
+[BuildOptions]\r
+  MSFT:*_*_X64_CC_FLAGS       = /Od \r
+  INTEL:*_*_X64_CC_FLAGS       = /Od 
\ No newline at end of file

diff --git a/Vlv2TbltDevicePkg/Application/FirmwareUpdate/FirmwareUpdateStrings.uni b/Vlv2TbltDevicePkg/Application/FirmwareUpdate/FirmwareUpdateStrings.uni
new file mode 100644 (file)
index 0000000..bbf497f
Binary files /dev/null and b/Vlv2TbltDevicePkg/Application/FirmwareUpdate/FirmwareUpdateStrings.uni differ

diff --git a/Vlv2TbltDevicePkg/BfmLib.exe b/Vlv2TbltDevicePkg/BfmLib.exe
new file mode 100644 (file)
index 0000000..4402a78
Binary files /dev/null and b/Vlv2TbltDevicePkg/BfmLib.exe differ

diff --git a/Vlv2TbltDevicePkg/BiosIdD.env b/Vlv2TbltDevicePkg/BiosIdD.env
new file mode 100644 (file)
index 0000000..a2631e1
--- /dev/null
+++ b/Vlv2TbltDevicePkg/BiosIdD.env
@@ -0,0 +1,30 @@
+#/** @file\r
+#  This file is used to define the BIOS ID parameters of the build.\r
+#  This file is processed by GenBiosId.\r
+#  The BIOS ID format conforms to "BIOS Revision Identification Specification", Rev. 0.7, 6/27/2001.\r
+#\r
+#  BIOS ID string format:\r
+#    $(BOARD_ID)$(BOARD_REV).$(OEM_ID).$(VERSION_MAJOR).$(BUILD_TYPE)$(VERSION_MINOR).YYMMDDHHMM\r
+#  All fields must have a fixed length.\r
+#    Example: "TRFTCRB1.86C.0008.D03.0506081529"\r
+#\r
+#  Copyright (c) 2008  - 2014, Intel Corporation. All rights reserved.<BR>\r
+#                                                                                  \r\r
+# This program and the accompanying materials are licensed and made available under\r\r
+# the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+# The full text of the license may be found at                                     \r\r
+# http://opensource.org/licenses/bsd-license.php.                                  \r\r
+#                                                                                  \r\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+#                                                                                  \r\r
+#\r
+#**/\r
+\r
+BOARD_REV     = 1\r
+OEM_ID        = I32\r
+BUILD_TYPE    = D\r
+\r
+BOARD_ID = BLAKCRB\r
+VERSION_MAJOR = 0076\r
+VERSION_MINOR = 01\r

diff --git a/Vlv2TbltDevicePkg/BiosIdR.env b/Vlv2TbltDevicePkg/BiosIdR.env
new file mode 100644 (file)
index 0000000..051df7a
--- /dev/null
+++ b/Vlv2TbltDevicePkg/BiosIdR.env
@@ -0,0 +1,30 @@
+#/** @file\r
+#  This file is used to define the BIOS ID parameters of the build.\r
+#  This file is processed by GenBiosId.\r
+#  The BIOS ID format conforms to "BIOS Revision Identification Specification", Rev. 0.7, 6/27/2001.\r
+#\r
+#  BIOS ID string format:\r
+#    $(BOARD_ID)$(BOARD_REV).$(OEM_ID).$(VERSION_MAJOR).$(BUILD_TYPE)$(VERSION_MINOR).YYMMDDHHMM\r
+#  All fields must have a fixed length.\r
+#    Example: "TRFTCRB1.86C.0008.D03.0506081529"\r
+#\r
+#  Copyright (c) 2008  - 2014, Intel Corporation. All rights reserved.<BR>\r
+#                                                                                  \r\r
+# This program and the accompanying materials are licensed and made available under\r\r
+# the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+# The full text of the license may be found at                                     \r\r
+# http://opensource.org/licenses/bsd-license.php.                                  \r\r
+#                                                                                  \r\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+#                                                                                  \r\r
+#\r
+#**/\r
+\r
+BOARD_REV     = 1\r
+OEM_ID        = I32\r
+BUILD_TYPE    = R\r
+\r
+BOARD_ID = BLAKCRB\r
+VERSION_MAJOR = 0076\r
+VERSION_MINOR = 01\r

diff --git a/Vlv2TbltDevicePkg/BiosIdx64D.env b/Vlv2TbltDevicePkg/BiosIdx64D.env
new file mode 100644 (file)
index 0000000..585ba61
--- /dev/null
+++ b/Vlv2TbltDevicePkg/BiosIdx64D.env
@@ -0,0 +1,30 @@
+#/** @file\r
+#  This file is used to define the BIOS ID parameters of the build.\r
+#  This file is processed by GenBiosId.\r
+#  The BIOS ID format conforms to "BIOS Revision Identification Specification", Rev. 0.7, 6/27/2001.\r
+#\r
+#  BIOS ID string format:\r
+#    $(BOARD_ID)$(BOARD_REV).$(OEM_ID).$(VERSION_MAJOR).$(BUILD_TYPE)$(VERSION_MINOR).YYMMDDHHMM\r
+#  All fields must have a fixed length.\r
+#    Example: "TRFTCRB1.86C.0008.D03.0506081529"\r
+#\r
+#  Copyright (c) 2008  - 2014, Intel Corporation. All rights reserved.<BR>\r
+#                                                                                  \r\r
+# This program and the accompanying materials are licensed and made available under\r\r
+# the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+# The full text of the license may be found at                                     \r\r
+# http://opensource.org/licenses/bsd-license.php.                                  \r\r
+#                                                                                  \r\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+#                                                                                  \r\r
+#\r
+#**/\r
+\r
+BOARD_REV     = 1\r
+OEM_ID        = X64\r
+BUILD_TYPE    = D\r
+\r
+VERSION_MAJOR = 0076\r
+VERSION_MINOR = 01\r
+BOARD_ID = BBAYCRB \r

diff --git a/Vlv2TbltDevicePkg/BiosIdx64R.env b/Vlv2TbltDevicePkg/BiosIdx64R.env
new file mode 100644 (file)
index 0000000..961550f
--- /dev/null
+++ b/Vlv2TbltDevicePkg/BiosIdx64R.env
@@ -0,0 +1,30 @@
+#/** @file\r
+#  This file is used to define the BIOS ID parameters of the build.\r
+#  This file is processed by GenBiosId.\r
+#  The BIOS ID format conforms to "BIOS Revision Identification Specification", Rev. 0.7, 6/27/2001.\r
+#\r
+#  BIOS ID string format:\r
+#    $(BOARD_ID)$(BOARD_REV).$(OEM_ID).$(VERSION_MAJOR).$(BUILD_TYPE)$(VERSION_MINOR).YYMMDDHHMM\r
+#  All fields must have a fixed length.\r
+#    Example: "TRFTCRB1.86C.0008.D03.0506081529"\r
+#\r
+#  Copyright (c) 2008  - 2014, Intel Corporation. All rights reserved.<BR>\r
+#                                                                                  \r\r
+# This program and the accompanying materials are licensed and made available under\r\r
+# the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+# The full text of the license may be found at                                     \r\r
+# http://opensource.org/licenses/bsd-license.php.                                  \r\r
+#                                                                                  \r\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+#                                                                                  \r\r
+#\r
+#**/\r
+\r
+BOARD_REV     = 1\r
+OEM_ID        = X64\r
+BUILD_TYPE    = R\r
+\r
+VERSION_MAJOR = 0076\r
+VERSION_MINOR = 01\r
+BOARD_ID = BBAYCRB \r

diff --git a/Vlv2TbltDevicePkg/BootScriptSaveDxe/BootScriptSaveDxe.inf b/Vlv2TbltDevicePkg/BootScriptSaveDxe/BootScriptSaveDxe.inf
new file mode 100644 (file)
index 0000000..94f8b0e
--- /dev/null
+++ b/Vlv2TbltDevicePkg/BootScriptSaveDxe/BootScriptSaveDxe.inf
@@ -0,0 +1,65 @@
+#\r
+#\r
+## @file\r
+# Component description file for ScriptSave Lite module.\r
+#\r
+# This is an implementation of the Boot Script Save protocol.\r
+# Copyright (c) 2006  - 2014, Intel Corporation. All rights reserved.<BR>\r
+#                                                                                  \r\r
+# This program and the accompanying materials are licensed and made available under\r\r
+# the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+# The full text of the license may be found at                                     \r\r
+# http://opensource.org/licenses/bsd-license.php.                                  \r\r
+#                                                                                  \r\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+#                                                                                  \r\r
+#\r
+#\r
+#\r
+##\r
+\r
+[Defines]\r
+  INF_VERSION                    = 0x00010005\r
+  BASE_NAME                      = BootScriptSaveDxe\r
+  FILE_GUID                      = 42BB673D-09F3-4e2e-9FEE-D081131DED5B\r
+  MODULE_TYPE                    = DXE_DRIVER\r
+  VERSION_STRING                 = 1.0\r
+\r
+  ENTRY_POINT                    = InitializeScriptSave\r
+\r
+#\r
+# The following information is for reference only and not required by the build tools.\r
+#\r
+#  VALID_ARCHITECTURES           = IA32 X64 IPF EBC\r
+#\r
+\r
+[Sources]\r
+  ScriptSave.c\r
+  InternalBootScriptSave.h\r
+\r
+\r
+[Packages]\r
+  MdePkg/MdePkg.dec\r
+  IntelFrameworkPkg/IntelFrameworkPkg.dec\r
+  MdeModulePkg/MdeModulePkg.dec\r
+\r
+\r
+[LibraryClasses]\r
+  PcdLib\r
+  UefiRuntimeServicesTableLib\r
+  UefiBootServicesTableLib\r
+  MemoryAllocationLib\r
+  UefiDriverEntryPoint\r
+  BaseMemoryLib\r
+  DebugLib\r
+  BaseLib\r
+  S3BootScriptLib\r
+\r
+[Protocols]\r
+  gEfiBootScriptSaveProtocolGuid                # PROTOCOL ALWAYS_PRODUCED\r
+\r
+\r
+[Depex]\r
+  TRUE\r
+\r

diff --git a/Vlv2TbltDevicePkg/BootScriptSaveDxe/InternalBootScriptSave.h b/Vlv2TbltDevicePkg/BootScriptSaveDxe/InternalBootScriptSave.h
new file mode 100644 (file)
index 0000000..d76f4e4
--- /dev/null
+++ b/Vlv2TbltDevicePkg/BootScriptSaveDxe/InternalBootScriptSave.h
@@ -0,0 +1,107 @@
+/** @file\r
+//\r
+//\r
+  Internal header file for S3 Boot Script Saver driver.\r
+\r
+  Copyright (c) 2006  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+**/\r
+\r
+#ifndef _INTERNAL_BOOT_SCRIPT_SAVE_H_\r
+#define _INTERNAL_BOOT_SCRIPT_SAVE_H_\r
+#include <FrameworkDxe.h>\r
+\r
+#include <Protocol/BootScriptSave.h>\r
+#include <Protocol/FirmwareVolume.h>\r
+\r
+#include <Library/BaseLib.h>\r
+#include <Library/DebugLib.h>\r
+#include <Library/UefiDriverEntryPoint.h>\r
+#include <Library/UefiBootServicesTableLib.h>\r
+#include <Library/UefiRuntimeServicesTableLib.h>\r
+#include <Library/S3BootScriptLib.h>\r
+#include <Library/PcdLib.h>\r
+#include <Library/SmbusLib.h>\r
+#include <IndustryStandard/SmBus.h>\r
+\r
+/**\r
+  Adds a record into a specified Framework boot script table.\r
+\r
+  This function is used to store a boot script record into a given boot\r
+  script table. If the table specified by TableName is nonexistent in the\r
+  system, a new table will automatically be created and then the script record\r
+  will be added into the new table. A boot script table can add new script records\r
+  until EFI_BOOT_SCRIPT_SAVE_PROTOCOL.CloseTable() is called. Currently, the only\r
+  meaningful table name is EFI_ACPI_S3_RESUME_SCRIPT_TABLE. This function is\r
+  responsible for allocating necessary memory for the script.\r
+\r
+  This function has a variable parameter list. The exact parameter list depends on\r
+  the OpCode that is passed into the function. If an unsupported OpCode or illegal\r
+  parameter list is passed in, this function returns EFI_INVALID_PARAMETER.\r
+  If there are not enough resources available for storing more scripts, this function returns\r
+  EFI_OUT_OF_RESOURCES.\r
+\r
+  @param[in]  This                 A pointer to the EFI_BOOT_SCRIPT_SAVE_PROTOCOL instance.\r
+  @param[in]  TableName            Name of the script table. Currently, the only meaningful value is\r
+                                   EFI_ACPI_S3_RESUME_SCRIPT_TABLE.\r
+  @param[in]  OpCode               The operation code (opcode) number.\r
+  @param[in]  ...                  Argument list that is specific to each opcode.\r
+\r
+  @retval EFI_SUCCESS              The operation succeeded. A record was added into the\r
+                                   specified script table.\r
+  @retval EFI_INVALID_PARAMETER    The parameter is illegal or the given boot script is not supported.\r
+                                   If the opcode is unknow or not supported because of the PCD\r
+                                   Feature Flags.\r
+  @retval EFI_OUT_OF_RESOURCES     There is insufficient memory to store the boot script.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+BootScriptWrite (\r
+  IN EFI_BOOT_SCRIPT_SAVE_PROTOCOL    *This,\r
+  IN UINT16                           TableName,\r
+  IN UINT16                           OpCode,\r
+  ...\r
+  );\r
+\r
+/**\r
+  Closes the specified script table.\r
+\r
+  This function closes the specified boot script table and returns the base address\r
+  of the table. It allocates a new pool to duplicate all the boot scripts in the specified\r
+  table. Once this function is called, the specified table will be destroyed after it is\r
+  copied into the allocated pool. As a result, any attempts to add a script record into a\r
+  closed table will cause a new table to be created. The base address of the allocated pool\r
+  will be returned in Address. After using the boot script table, the caller is responsible\r
+  for freeing the pool that is allocated by this function. If the boot script table,\r
+  such as EFI_ACPI_S3_RESUME_SCRIPT_TABLE, is required to be stored in a nonperturbed\r
+  memory region, the caller should copy the table into the nonperturbed memory region by itself.\r
+\r
+  @param[in]  This              A pointer to the EFI_BOOT_SCRIPT_SAVE_PROTOCOL instance.\r
+  @param[in]  TableName         Name of the script table. Currently, the only meaningful value is\r
+                                EFI_ACPI_S3_RESUME_SCRIPT_TABLE.\r
+  @param[in]  Address           A pointer to the physical address where the table begins.\r
+\r
+  @retval EFI_SUCCESS           The table was successfully returned.\r
+  @retval EFI_NOT_FOUND         The specified table was not created previously.\r
+  @retval EFI_OUT_OF_RESOURCE   Memory is insufficient to hold the reorganized boot script table.\r
+  @retval EFI_UNSUPPORTED       The table type is not EFI_ACPI_S3_RESUME_SCRIPT_TABLE.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+BootScriptCloseTable (\r
+  IN EFI_BOOT_SCRIPT_SAVE_PROTOCOL    *This,\r
+  IN UINT16                           TableName,\r
+  OUT EFI_PHYSICAL_ADDRESS            *Address\r
+  );\r
+#endif //_INTERNAL_BOOT_SCRIPT_SAVE_H_\r

diff --git a/Vlv2TbltDevicePkg/BootScriptSaveDxe/ScriptSave.c b/Vlv2TbltDevicePkg/BootScriptSaveDxe/ScriptSave.c
new file mode 100644 (file)
index 0000000..55f758c
--- /dev/null
+++ b/Vlv2TbltDevicePkg/BootScriptSaveDxe/ScriptSave.c
@@ -0,0 +1,631 @@
+/** @file\r
+  Implementation for S3 Boot Script Saver driver.\r
+\r
+Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+**/\r
+\r
+#include "InternalBootScriptSave.h"\r
+\r
+EFI_HANDLE                    mHandle = NULL;\r
+EFI_BOOT_SCRIPT_SAVE_PROTOCOL mS3ScriptSave = {\r
+  BootScriptWrite,\r
+  BootScriptCloseTable\r
+  };\r
+\r
+/**\r
+  Internal function to add IO write opcode to the table.\r
+\r
+  @param  Marker                The variable argument list to get the opcode\r
+                                and associated attributes.\r
+\r
+  @retval EFI_OUT_OF_RESOURCES  Not enough resource to do operation.\r
+  @retval EFI_SUCCESS           Opcode is added.\r
+\r
+**/\r
+EFI_STATUS\r
+BootScriptIoWrite (\r
+  IN VA_LIST                       Marker\r
+  )\r
+{\r
+  S3_BOOT_SCRIPT_LIB_WIDTH Width;\r
+  UINT64                Address;\r
+  UINTN                 Count;\r
+  UINT8                 *Buffer;\r
+\r
+  Width       = VA_ARG (Marker, S3_BOOT_SCRIPT_LIB_WIDTH);\r
+  Address     = VA_ARG (Marker, UINT64);\r
+  Count       = VA_ARG (Marker, UINTN);\r
+  Buffer      = VA_ARG (Marker, UINT8 *);\r
+\r
+  return S3BootScriptSaveIoWrite (Width, Address, Count, Buffer);\r
+}\r
+\r
+/**\r
+  Internal function to add IO read/write opcode to the table.\r
+\r
+  @param  Marker                The variable argument list to get the opcode\r
+                                and associated attributes.\r
+\r
+  @retval EFI_OUT_OF_RESOURCES  Not enough resource to do operation.\r
+  @retval EFI_SUCCESS           Opcode is added.\r
+\r
+**/\r
+EFI_STATUS\r
+BootScriptIoReadWrite (\r
+  IN VA_LIST                       Marker\r
+  )\r
+{\r
+  S3_BOOT_SCRIPT_LIB_WIDTH Width;\r
+  UINT64                Address;\r
+  UINT8                 *Data;\r
+  UINT8                 *DataMask;\r
+\r
+  Width       = VA_ARG (Marker, S3_BOOT_SCRIPT_LIB_WIDTH);\r
+  Address     = VA_ARG (Marker, UINT64);\r
+  Data        = VA_ARG (Marker, UINT8 *);\r
+  DataMask    = VA_ARG (Marker, UINT8 *);\r
+\r
+  return S3BootScriptSaveIoReadWrite (Width, Address, Data, DataMask);\r
+}\r
+\r
+/**\r
+  Internal function to add memory write opcode to the table.\r
+\r
+  @param  Marker                The variable argument list to get the opcode\r
+                                and associated attributes.\r
+\r
+  @retval EFI_OUT_OF_RESOURCES  Not enough resource to do operation.\r
+  @retval EFI_SUCCESS           Opcode is added.\r
+\r
+**/\r
+EFI_STATUS\r
+BootScriptMemWrite (\r
+  IN VA_LIST                       Marker\r
+  )\r
+{\r
+  S3_BOOT_SCRIPT_LIB_WIDTH Width;\r
+  UINT64                Address;\r
+  UINTN                 Count;\r
+  UINT8                 *Buffer;\r
+\r
+  Width       = VA_ARG (Marker, S3_BOOT_SCRIPT_LIB_WIDTH);\r
+  Address     = VA_ARG (Marker, UINT64);\r
+  Count       = VA_ARG (Marker, UINTN);\r
+  Buffer      = VA_ARG (Marker, UINT8 *);\r
+\r
+  return S3BootScriptSaveMemWrite (Width, Address, Count, Buffer);\r
+}\r
+\r
+/**\r
+  Internal function to add memory read/write opcode to the table.\r
+\r
+  @param  Marker                The variable argument list to get the opcode\r
+                                and associated attributes.\r
+\r
+  @retval EFI_OUT_OF_RESOURCES  Not enough resource to do operation.\r
+  @retval EFI_SUCCESS           Opcode is added.\r
+\r
+**/\r
+EFI_STATUS\r
+BootScriptMemReadWrite (\r
+  IN VA_LIST                       Marker\r
+  )\r
+{\r
+  S3_BOOT_SCRIPT_LIB_WIDTH Width;\r
+  UINT64                Address;\r
+  UINT8                 *Data;\r
+  UINT8                 *DataMask;\r
+\r
+  Width       = VA_ARG (Marker, S3_BOOT_SCRIPT_LIB_WIDTH);\r
+  Address     = VA_ARG (Marker, UINT64);\r
+  Data        = VA_ARG (Marker, UINT8 *);\r
+  DataMask    = VA_ARG (Marker, UINT8 *);\r
+\r
+  return S3BootScriptSaveMemReadWrite (Width, Address, Data, DataMask);\r
+}\r
+\r
+/**\r
+  Internal function to add PciCfg write opcode to the table.\r
+\r
+  @param  Marker                The variable argument list to get the opcode\r
+                                and associated attributes.\r
+\r
+  @retval EFI_OUT_OF_RESOURCES  Not enough resource to do operation.\r
+  @retval EFI_SUCCESS           Opcode is added.\r
+\r
+**/\r
+EFI_STATUS\r
+BootScriptPciCfgWrite (\r
+  IN VA_LIST                       Marker\r
+  )\r
+{\r
+  S3_BOOT_SCRIPT_LIB_WIDTH Width;\r
+  UINT64                Address;\r
+  UINTN                 Count;\r
+  UINT8                 *Buffer;\r
+\r
+  Width       = VA_ARG (Marker, S3_BOOT_SCRIPT_LIB_WIDTH);\r
+  Address     = VA_ARG (Marker, UINT64);\r
+  Count       = VA_ARG (Marker, UINTN);\r
+  Buffer      = VA_ARG (Marker, UINT8 *);\r
+\r
+  return S3BootScriptSavePciCfgWrite (Width, Address, Count, Buffer);\r
+}\r
+\r
+/**\r
+  Internal function to PciCfg read/write opcode to the table.\r
+\r
+  @param  Marker                The variable argument list to get the opcode\r
+                                and associated attributes.\r
+\r
+  @retval EFI_OUT_OF_RESOURCES  Not enough resource to do operation.\r
+  @retval EFI_SUCCESS           Opcode is added.\r
+\r
+**/\r
+EFI_STATUS\r
+BootScriptPciCfgReadWrite (\r
+  IN VA_LIST                       Marker\r
+  )\r
+{\r
+  S3_BOOT_SCRIPT_LIB_WIDTH Width;\r
+  UINT64                Address;\r
+  UINT8                 *Data;\r
+  UINT8                 *DataMask;\r
+\r
+  Width       = VA_ARG (Marker, S3_BOOT_SCRIPT_LIB_WIDTH);\r
+  Address     = VA_ARG (Marker, UINT64);\r
+  Data        = VA_ARG (Marker, UINT8 *);\r
+  DataMask    = VA_ARG (Marker, UINT8 *);\r
+\r
+  return S3BootScriptSavePciCfgReadWrite (Width, Address, Data, DataMask);\r
+}\r
+\r
+/**\r
+  Internal function to add PciCfg2 write opcode to the table.\r
+\r
+  @param  Marker                The variable argument list to get the opcode\r
+                                and associated attributes.\r
+\r
+  @retval EFI_OUT_OF_RESOURCES  Not enough resource to do operation.\r
+  @retval EFI_SUCCESS           Opcode is added.\r
+\r
+**/\r
+EFI_STATUS\r
+BootScriptPciCfg2Write (\r
+  IN VA_LIST                       Marker\r
+  )\r
+{\r
+  S3_BOOT_SCRIPT_LIB_WIDTH Width;\r
+  UINT64                Address;\r
+  UINTN                 Count;\r
+  UINT8                 *Buffer;\r
+  UINT16                Segment;\r
+\r
+  Width       = VA_ARG (Marker, S3_BOOT_SCRIPT_LIB_WIDTH);\r
+  Address     = VA_ARG (Marker, UINT64);\r
+  Count       = VA_ARG (Marker, UINTN);\r
+  Buffer      = VA_ARG (Marker, UINT8 *);\r
+  Segment     = VA_ARG (Marker, UINT16);\r
+\r
+  return S3BootScriptSavePciCfg2Write (Width, Segment, Address, Count, Buffer);\r
+}\r
+\r
+/**\r
+  Internal function to PciCfg2 read/write opcode to the table.\r
+\r
+  @param  Marker                The variable argument list to get the opcode\r
+                                and associated attributes.\r
+\r
+  @retval EFI_OUT_OF_RESOURCES  Not enough resource to do operation.\r
+  @retval EFI_SUCCESS           Opcode is added.\r
+\r
+**/\r
+EFI_STATUS\r
+BootScriptPciCfg2ReadWrite (\r
+  IN VA_LIST                       Marker\r
+  )\r
+{\r
+  S3_BOOT_SCRIPT_LIB_WIDTH Width;\r
+  UINT16                Segment;\r
+  UINT64                Address;\r
+  UINT8                 *Data;\r
+  UINT8                 *DataMask;\r
+\r
+  Width       = VA_ARG (Marker, S3_BOOT_SCRIPT_LIB_WIDTH);\r
+  Address     = VA_ARG (Marker, UINT64);\r
+  Segment     = VA_ARG (Marker, UINT16);\r
+  Data        = VA_ARG (Marker, UINT8 *);\r
+  DataMask    = VA_ARG (Marker, UINT8 *);\r
+\r
+  return S3BootScriptSavePciCfg2ReadWrite (Width, Segment, Address, Data, DataMask);\r
+}\r
+\r
+/**\r
+  Internal function to add smbus excute opcode to the table.\r
+\r
+  @param  Marker                The variable argument list to get the opcode\r
+                                and associated attributes.\r
+\r
+  @retval EFI_OUT_OF_RESOURCES  Not enough resource to do operation.\r
+  @retval EFI_SUCCESS           Opcode is added.\r
+\r
+**/\r
+EFI_STATUS\r
+BootScriptSmbusExecute (\r
+  IN VA_LIST                       Marker\r
+  )\r
+{\r
+  EFI_SMBUS_DEVICE_ADDRESS  SlaveAddress;\r
+  EFI_SMBUS_DEVICE_COMMAND  Command;\r
+  EFI_SMBUS_OPERATION       Operation;\r
+  BOOLEAN                   PecCheck;\r
+  VOID                     *Buffer;\r
+  UINTN                    *DataSize;\r
+  UINTN                     SmBusAddress;\r
+\r
+  SlaveAddress.SmbusDeviceAddress = VA_ARG (Marker, UINTN);\r
+  Command                         = VA_ARG (Marker, EFI_SMBUS_DEVICE_COMMAND);\r
+  Operation                       = VA_ARG (Marker, EFI_SMBUS_OPERATION);\r
+  PecCheck                        = VA_ARG (Marker, BOOLEAN);\r
+  SmBusAddress                    = SMBUS_LIB_ADDRESS (SlaveAddress.SmbusDeviceAddress,Command,0,PecCheck);\r
+  DataSize                        = VA_ARG (Marker, UINTN *);\r
+  Buffer                          = VA_ARG (Marker, VOID *);\r
+\r
+  return S3BootScriptSaveSmbusExecute (SmBusAddress, Operation, DataSize, Buffer);\r
+}\r
+\r
+/**\r
+  Internal function to add stall opcode to the table.\r
+\r
+  @param  Marker                The variable argument list to get the opcode\r
+                                and associated attributes.\r
+\r
+  @retval EFI_OUT_OF_RESOURCES  Not enough resource to do operation.\r
+  @retval EFI_SUCCESS           Opcode is added.\r
+\r
+**/\r
+EFI_STATUS\r
+BootScriptStall (\r
+  IN VA_LIST                       Marker\r
+  )\r
+{\r
+  UINT32                Duration;\r
+\r
+  Duration    = VA_ARG (Marker, UINT32);\r
+\r
+  return S3BootScriptSaveStall (Duration);\r
+}\r
+\r
+/**\r
+  Internal function to add Save jmp address according to DISPATCH_OPCODE.\r
+  We ignore "Context" parameter.\r
+\r
+  @param  Marker                The variable argument list to get the opcode\r
+                                and associated attributes.\r
+\r
+  @retval EFI_OUT_OF_RESOURCES  Not enough resource to do operation.\r
+  @retval EFI_SUCCESS           Opcode is added.\r
+\r
+**/\r
+EFI_STATUS\r
+BootScriptDispatch (\r
+  IN VA_LIST                       Marker\r
+  )\r
+{\r
+  VOID        *EntryPoint;\r
+\r
+  EntryPoint = (VOID*)(UINTN)VA_ARG (Marker, EFI_PHYSICAL_ADDRESS);\r
+  return S3BootScriptSaveDispatch (EntryPoint);\r
+}\r
+\r
+/**\r
+  Internal function to add memory pool operation to the table.\r
+\r
+  @param  Marker                The variable argument list to get the opcode\r
+                                and associated attributes.\r
+\r
+  @retval EFI_OUT_OF_RESOURCES  Not enough resource to do operation.\r
+  @retval EFI_SUCCESS           Opcode is added.\r
+\r
+**/\r
+EFI_STATUS\r
+BootScriptMemPoll (\r
+  IN VA_LIST                       Marker\r
+  )\r
+{\r
+  S3_BOOT_SCRIPT_LIB_WIDTH Width;\r
+  UINT64                Address;\r
+  UINT8                 *BitMask;\r
+  UINT8                 *BitValue;\r
+  UINTN                Duration;\r
+  UINTN                LoopTimes;\r
+\r
+  Width       = VA_ARG (Marker, S3_BOOT_SCRIPT_LIB_WIDTH);\r
+  Address     = VA_ARG (Marker, UINT64);\r
+  BitMask     = VA_ARG (Marker, UINT8 *);\r
+  BitValue    = VA_ARG (Marker, UINT8 *);\r
+  Duration    = (UINTN)VA_ARG (Marker, UINT64);\r
+  LoopTimes   = (UINTN)VA_ARG (Marker, UINT64);\r
+\r
+  return S3BootScriptSaveMemPoll (Width, Address, BitMask, BitValue, Duration, LoopTimes);\r
+}\r
+\r
+/**\r
+  Internal function to add Save jmp address according to DISPATCH_OPCODE2.\r
+  The "Context" parameter is not ignored.\r
+\r
+  @param  Marker                The variable argument list to get the opcode\r
+                                and associated attributes.\r
+\r
+  @retval EFI_OUT_OF_RESOURCES  Not enough resource to do operation.\r
+  @retval EFI_SUCCESS           Opcode is added.\r
+\r
+**/\r
+EFI_STATUS\r
+BootScriptDispatch2 (\r
+  IN VA_LIST                       Marker\r
+  )\r
+{\r
+  VOID                  *EntryPoint;\r
+  VOID                  *Context;\r
+\r
+  EntryPoint = (VOID*)(UINTN)VA_ARG (Marker, EFI_PHYSICAL_ADDRESS);\r
+  Context    = (VOID*)(UINTN)VA_ARG (Marker, EFI_PHYSICAL_ADDRESS);\r
+\r
+  return S3BootScriptSaveDispatch2 (EntryPoint, Context);\r
+}\r
+\r
+/**\r
+  Internal function to add the opcode link node to the link list.\r
+\r
+  @param  Marker                The variable argument list to get the opcode\r
+                                and associated attributes.\r
+\r
+  @retval EFI_OUT_OF_RESOURCES  Not enought resource to complete the operations.\r
+  @retval EFI_SUCCESS           The opcode entry is added to the link list\r
+                                successfully.\r
+**/\r
+EFI_STATUS\r
+BootScriptInformation (\r
+  IN VA_LIST                       Marker\r
+  )\r
+{\r
+  UINT32                InformationLength;\r
+  EFI_PHYSICAL_ADDRESS  Information;\r
+\r
+  InformationLength = VA_ARG (Marker, UINT32);\r
+  Information = VA_ARG (Marker, EFI_PHYSICAL_ADDRESS);\r
+  return S3BootScriptSaveInformation (InformationLength, (VOID*)(UINTN)Information);\r
+}\r
+\r
+/**\r
+  Adds a record into a specified Framework boot script table.\r
+\r
+  This function is used to store a boot script record into a given boot\r
+  script table. If the table specified by TableName is nonexistent in the\r
+  system, a new table will automatically be created and then the script record\r
+  will be added into the new table. A boot script table can add new script records\r
+  until EFI_BOOT_SCRIPT_SAVE_PROTOCOL.CloseTable() is called. Currently, the only\r
+  meaningful table name is EFI_ACPI_S3_RESUME_SCRIPT_TABLE. This function is\r
+  responsible for allocating necessary memory for the script.\r
+\r
+  This function has a variable parameter list. The exact parameter list depends on\r
+  the OpCode that is passed into the function. If an unsupported OpCode or illegal\r
+  parameter list is passed in, this function returns EFI_INVALID_PARAMETER.\r
+  If there are not enough resources available for storing more scripts, this function returns\r
+  EFI_OUT_OF_RESOURCES.\r
+\r
+  @param  This                  A pointer to the EFI_BOOT_SCRIPT_SAVE_PROTOCOL instance.\r
+  @param  TableName             Name of the script table. Currently, the only meaningful value is\r
+                                EFI_ACPI_S3_RESUME_SCRIPT_TABLE.\r
+  @param  OpCode                The operation code (opcode) number.\r
+  @param  ...                   Argument list that is specific to each opcode.\r
+\r
+  @retval EFI_SUCCESS           The operation succeeded. A record was added into the\r
+                                specified script table.\r
+  @retval EFI_INVALID_PARAMETER The parameter is illegal or the given boot script is not supported.\r
+                                If the opcode is unknow or not supported because of the PCD\r
+                                Feature Flags.\r
+  @retval EFI_OUT_OF_RESOURCES  There is insufficient memory to store the boot script.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+BootScriptWrite (\r
+  IN EFI_BOOT_SCRIPT_SAVE_PROTOCOL    *This,\r
+  IN UINT16                           TableName,\r
+  IN UINT16                           OpCode,\r
+  ...\r
+  )\r
+{\r
+  EFI_STATUS                Status;\r
+  VA_LIST                   Marker;\r
+\r
+  if (TableName != FRAMEWORK_EFI_ACPI_S3_RESUME_SCRIPT_TABLE) {\r
+    //\r
+    // Only S3 boot script is supported for now.\r
+    //\r
+    return EFI_OUT_OF_RESOURCES;\r
+  }\r
+\r
+  //\r
+  // Build script according to opcode.\r
+  //\r
+  switch (OpCode) {\r
+\r
+  case EFI_BOOT_SCRIPT_IO_WRITE_OPCODE:\r
+    VA_START (Marker, OpCode);\r
+    Status = BootScriptIoWrite (Marker);\r
+    VA_END (Marker);\r
+    break;\r
+\r
+  case EFI_BOOT_SCRIPT_IO_READ_WRITE_OPCODE:\r
+    VA_START (Marker, OpCode);\r
+    Status = BootScriptIoReadWrite (Marker);\r
+    VA_END (Marker);\r
+    break;\r
+\r
+  case EFI_BOOT_SCRIPT_MEM_WRITE_OPCODE:\r
+    VA_START (Marker, OpCode);\r
+    Status = BootScriptMemWrite (Marker);\r
+    VA_END (Marker);\r
+    break;\r
+\r
+  case EFI_BOOT_SCRIPT_MEM_READ_WRITE_OPCODE:\r
+    VA_START (Marker, OpCode);\r
+    Status = BootScriptMemReadWrite (Marker);\r
+    VA_END (Marker);\r
+    break;\r
+\r
+  case EFI_BOOT_SCRIPT_PCI_CONFIG_WRITE_OPCODE:\r
+    VA_START (Marker, OpCode);\r
+    Status = BootScriptPciCfgWrite (Marker);\r
+    VA_END (Marker);\r
+    break;\r
+\r
+  case EFI_BOOT_SCRIPT_PCI_CONFIG_READ_WRITE_OPCODE:\r
+    VA_START (Marker, OpCode);\r
+    Status = BootScriptPciCfgReadWrite (Marker);\r
+    VA_END (Marker);\r
+    break;\r
+\r
+  case EFI_BOOT_SCRIPT_SMBUS_EXECUTE_OPCODE:\r
+    VA_START (Marker, OpCode);\r
+    Status = BootScriptSmbusExecute (Marker);\r
+    VA_END (Marker);\r
+    break;\r
+\r
+  case EFI_BOOT_SCRIPT_STALL_OPCODE:\r
+    VA_START (Marker, OpCode);\r
+    Status = BootScriptStall (Marker);\r
+    VA_END (Marker);\r
+\r
+    break;\r
+\r
+  case EFI_BOOT_SCRIPT_DISPATCH_OPCODE:\r
+    VA_START (Marker, OpCode);\r
+    Status = BootScriptDispatch (Marker);\r
+    VA_END (Marker);\r
+    break;\r
+\r
+  case EFI_BOOT_SCRIPT_DISPATCH_2_OPCODE:\r
+    VA_START (Marker, OpCode);\r
+    Status = BootScriptDispatch2 (Marker);\r
+    VA_END (Marker);\r
+    break;\r
+\r
+  case EFI_BOOT_SCRIPT_INFORMATION_OPCODE:\r
+    VA_START (Marker, OpCode);\r
+    Status = BootScriptInformation (Marker);\r
+    VA_END (Marker);\r
+    break;\r
+\r
+  case EFI_BOOT_SCRIPT_MEM_POLL_OPCODE:\r
+    VA_START (Marker, OpCode);\r
+    Status = BootScriptMemPoll (Marker);\r
+    VA_END (Marker);\r
+    break;\r
+\r
+  case EFI_BOOT_SCRIPT_PCI_CONFIG2_WRITE_OPCODE:\r
+    VA_START (Marker, OpCode);\r
+    Status = BootScriptPciCfg2Write (Marker);\r
+    VA_END (Marker);\r
+    break;\r
+\r
+  case EFI_BOOT_SCRIPT_PCI_CONFIG2_READ_WRITE_OPCODE:\r
+    VA_START (Marker, OpCode);\r
+    Status = BootScriptPciCfg2ReadWrite (Marker);\r
+    VA_END (Marker);\r
+    break;\r
+\r
+  default:\r
+    Status = EFI_INVALID_PARAMETER;\r
+    break;\r
+  }\r
+\r
+  return Status;\r
+}\r
+\r
+/**\r
+  Closes the specified script table.\r
+\r
+  This function closes the specified boot script table and returns the base address\r
+  of the table. It allocates a new pool to duplicate all the boot scripts in the specified\r
+  table. Once this function is called, the specified table will be destroyed after it is\r
+  copied into the allocated pool. As a result, any attempts to add a script record into a\r
+  closed table will cause a new table to be created. The base address of the allocated pool\r
+  will be returned in Address. After using the boot script table, the caller is responsible\r
+  for freeing the pool that is allocated by this function. If the boot script table,\r
+  such as EFI_ACPI_S3_RESUME_SCRIPT_TABLE, is required to be stored in a nonperturbed\r
+  memory region, the caller should copy the table into the nonperturbed memory region by itself.\r
+\r
+  @param  This                  A pointer to the EFI_BOOT_SCRIPT_SAVE_PROTOCOL instance.\r
+  @param  TableName             Name of the script table. Currently, the only meaningful value is\r
+                                 EFI_ACPI_S3_RESUME_SCRIPT_TABLE.\r
+  @param  Address               A pointer to the physical address where the table begins.\r
+\r
+  @retval EFI_SUCCESS           The table was successfully returned.\r
+  @retval EFI_NOT_FOUND         The specified table was not created previously.\r
+  @retval EFI_OUT_OF_RESOURCE   Memory is insufficient to hold the reorganized boot script table.\r
+  @retval EFI_UNSUPPORTED       The table type is not EFI_ACPI_S3_RESUME_SCRIPT_TABLE.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+BootScriptCloseTable (\r
+  IN EFI_BOOT_SCRIPT_SAVE_PROTOCOL    *This,\r
+  IN UINT16                           TableName,\r
+  OUT EFI_PHYSICAL_ADDRESS            *Address\r
+  )\r
+{\r
+  if (TableName != FRAMEWORK_EFI_ACPI_S3_RESUME_SCRIPT_TABLE) {\r
+    //\r
+    // Only S3 boot script is supported for now.\r
+    //\r
+    return EFI_NOT_FOUND;\r
+  }\r
+  *Address = (EFI_PHYSICAL_ADDRESS)(UINTN)S3BootScriptCloseTable ();\r
+\r
+  if (*Address == 0) {\r
+    return  EFI_NOT_FOUND;\r
+  }\r
+  return EFI_SUCCESS;\r
+}\r
+\r
+/**\r
+  This routine is entry point of ScriptSave driver.\r
+\r
+  @param  ImageHandle           Handle for this drivers loaded image protocol.\r
+  @param  SystemTable           EFI system table.\r
+\r
+  @retval EFI_OUT_OF_RESOURCES  No enough resource.\r
+  @retval EFI_SUCCESS           Succesfully installed the ScriptSave driver.\r
+  @retval other                 Errors occured.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+InitializeScriptSave (\r
+  IN EFI_HANDLE           ImageHandle,\r
+  IN EFI_SYSTEM_TABLE     *SystemTable\r
+  )\r
+{\r
+  return  gBS->InstallProtocolInterface (\r
+                  &mHandle,\r
+                  &gEfiBootScriptSaveProtocolGuid,\r
+                  EFI_NATIVE_INTERFACE,\r
+                  &mS3ScriptSave\r
+                  );\r
+\r
+}\r
+\r

diff --git a/Vlv2TbltDevicePkg/Build_IFWI.bat b/Vlv2TbltDevicePkg/Build_IFWI.bat
new file mode 100644 (file)
index 0000000..a07a826
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Build_IFWI.bat
@@ -0,0 +1,178 @@
+@REM @file\r
+@REM   Windows batch file to build BIOS ROM\r
+@REM\r
+@REM Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>\r
+@REM This program and the accompanying materials\r
+@REM are licensed and made available under the terms and conditions of the BSD License\r
+@REM which accompanies this distribution.  The full text of the license may be found at\r
+@REM http://opensource.org/licenses/bsd-license.php\r
+@REM\r
+@REM THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+@REM WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+@REM\r
+\r
+@echo off\r
+\r
+SetLocal EnableDelayedExpansion EnableExtensions\r
+\r
+@REM Go to root directory of the codebase.\r
+cd ..\r
+\r
+:: Assign initial values\r
+set exitCode=0\r
+set "Build_Flags= "\r
+set "Stitch_Flags= "\r
+set Arch=X64\r
+set PLATFORM_PACKAGE=Vlv2TbltDevicePkg\r
+set ROOT_DIR=%CD%\r
+\r
+:: Parse Optional arguments\r
+:OptLoop\r
+if /i "%~1"=="/?" goto Usage\r
+\r
+if /i "%~1"=="/q" (\r
+    set Build_Flags=%Build_Flags% /q\r
+    shift\r
+    goto OptLoop\r
+)\r
+if /i "%~1"=="/l" (\r
+    set Build_Flags=%Build_Flags% /l\r
+    shift\r
+    goto OptLoop\r
+)\r
+if /i "%~1" == "/c" (\r
+    set Build_Flags=%Build_Flags% /c\r
+    shift\r
+    goto OptLoop\r
+)\r
+if /i "%~1" == "/ECP" (\r
+    set Build_Flags=%Build_Flags% /ecp\r
+    shift\r
+    goto OptLoop\r
+)\r
+\r
+if /i "%~1"=="/s" (\r
+    set Build_Flags=%Build_Flags% /s\r
+    shift\r
+    goto OptLoop\r
+)\r
+\r
+if /i "%~1"=="/x64" (\r
+    set Arch=X64\r
+    set Build_Flags=%Build_Flags% /x64\r
+    shift\r
+    goto OptLoop\r
+)\r
+\r
+if /i "%~1"=="/IA32" (\r
+    set Arch=IA32\r
+    set Build_Flags=%Build_Flags% /IA32\r
+    shift\r
+    goto OptLoop\r
+)\r
+\r
+if /i "%~1"=="/nG" (\r
+    set Stitch_Flags=%Stitch_Flags% /nG\r
+    shift\r
+    goto OptLoop\r
+)\r
+if /i "%~1"=="/nM" (\r
+    set Stitch_Flags=%Stitch_Flags% /nM\r
+    shift\r
+    goto OptLoop\r
+)\r
+if /i "%~1"=="/nB" (\r
+    set Stitch_Flags=%Stitch_Flags% /nB\r
+    shift\r
+    goto OptLoop\r
+)\r
+\r
+:: Require 2 input parameters\r
+if "%~2"=="" goto Usage\r
+\r
+:: Assign required arguments\r
+set Platform_Type=%~1\r
+set Build_Target=%~2\r
+if "%~3"=="" (\r
+    set "IFWI_Suffix= "\r
+) else set "IFWI_Suffix=/S %~3"\r
+\r
+:: Build BIOS\r
+echo ======================================================================\r
+echo Build_IFWI:  Calling BIOS build Script...\r
+if "%Platform_Type%" == "BYTC" (\r
+    call %PLATFORM_PACKAGE%\bld_vlv_cr.bat %Build_Flags%  %Platform_Type% %Build_Target%\r
+ \r
+) else (\r
+    call %PLATFORM_PACKAGE%\bld_vlv.bat %Build_Flags%  %Platform_Type% %Build_Target%\r
+)\r
+if %ERRORLEVEL% NEQ 0 (\r
+    echo echo  -- Error Building BIOS  & echo.\r
+    set exitCode=1\r
+    goto exit\r
+)\r
+echo.\r
+echo Finished Building BIOS.\r
+@REM Set BIOS_ID environment variable here.\r
+call Conf\BiosId.bat\r
+echo BIOS_ID=%BIOS_ID%\r
+\r
+:: Set the Board_Id, Build_Type, Version_Major, and Version_Minor environment variables\r
+find /v "#" Conf\BiosId.env > ver_strings\r
+for /f "tokens=1,3" %%i in (ver_strings) do set %%i=%%j\r
+del /f/q ver_strings >nul\r
+set BIOS_Name=%BOARD_ID%_%Arch%_%BUILD_TYPE%_%VERSION_MAJOR%_%VERSION_MINOR%.ROM\r
+\r
+:: Start Integration process\r
+echo ======================================================================\r
+echo Build_IFWI:  Calling IFWI Stitching Script...\r
+if "%Platform_Type%" == "BYTC" (\r
+    pushd %PLATFORM_PACKAGE%\Stitch_CR\r
+) else (\r
+    pushd %PLATFORM_PACKAGE%\Stitch\r
+)\r
+   :: IFWIStitch.bat [/nG] [/nM] [/nB] [/B BIOS.rom] [/C StitchConfig] [/S IFWISuffix]\r
+   call IFWIStitch.bat %Stitch_Flags% /B ..\..\%BIOS_Name% %IFWI_Suffix%\r
+   \r
+   @echo off\r
+popd\r
+if %ERRORLEVEL% NEQ 0 (\r
+    echo echo  -- Error Stitching %BIOS_Nam% & echo.\r
+    set exitCode=1\r
+)\r
+echo.\r
+echo Build_IFWI is finished.\r
+echo The final IFWI file is located in %ROOT_DIR%\Vlv2TbltDevicePkg\Stitch\\r
+echo ======================================================================\r
+goto Exit\r
+\r
+:Usage\r
+echo Script to build BIOS firmware and stitch the entire IFWI.\r
+echo.\r
+echo Usage: Build_IFWI.bat [options]  PlatformType  BuildTarget  [IFWI Suffix]\r
+echo.\r
+echo        /q     Quiet mode. Only display Fatal Errors (slightly faster)\r
+echo        /l     Log a copy of the build output to EDK2.log\r
+echo        /c     CleanAll before building\r
+echo        /ecp   ECP build enable\r
+echo        /src   Build silicon source code (default binary)\r
+echo        /x64   Set Arch to X64  (default: X64)\r
+echo        /IA32  Set Arch to IA32 (default: X64)\r
+echo        /nG    Do NOT update the GOP driver when stitching (ie keep src version)\r
+echo        /nM    Do NOT update the Microcode when stitching  (ie keep src version)\r
+echo        /nB    Do NOT create a backup of BIOS.ROM before modifying it for Stitch\r
+echo. \r
+echo        Platform Types:   MNW2\r
+echo        Build Targets:    Release, Debug\r
+echo        IFWI Suffix:      Suffix to append to end of IFWI filename (default: MM_DD_YYYY)\r
+echo.\r
+echo        See  Stitch/Stitch_Config.txt  for additional stitching settings.\r
+echo.\r
+set exitCode=1\r
+\r
+:Exit\r
+@REM  CD to platform package.\r
+cd %ROOT_DIR%\Vlv2TbltDevicePkg\r
+exit /b %exitCode%\r
+\r
+EndLocal\r

diff --git a/Vlv2TbltDevicePkg/Build_IFWI.sh b/Vlv2TbltDevicePkg/Build_IFWI.sh
new file mode 100644 (file)
index 0000000..9bde502
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Build_IFWI.sh
@@ -0,0 +1,101 @@
+##**********************************************************************
+## Function define
+##**********************************************************************
+function Usage ( ) {
+  echo
+  echo "Script to build BIOS firmware and stitch the entire IFWI."
+  echo
+  echo "Usage: Build_IFWI.bat   PlatformType  BuildTarget  "
+  echo
+  echo 
+  echo "       Platform Types:   MNW2"
+  echo "       Build Targets:    Release, Debug"
+  echo
+  echo "       See  Stitch/Stitch_Config.txt  for additional stitching settings."
+  echo
+  echo
+  echo "Press any key......"
+  read
+  exit 0
+}
+
+## Assign initial values
+exitCode=0
+Build_Flags=
+Stitch_Flags=
+Arch=X64
+PLATFORM_PACKAGE=Vlv2TbltDevicePkg
+
+## Parse Optional arguments
+if [ "$1" == "/?" ]; then
+  Usage
+fi
+
+for (( i=1; i<=$#; ))
+  do
+    if [ "$(echo $1 | tr 'a-z' 'A-Z')" == "/Q" ]; then
+      Build_Flags="$Build_Flags /q"
+      shift
+    elif [ "$(echo $1 | tr 'a-z' 'A-Z')" == "/L" ]; then
+      Build_Flags="$Build_Flags /l"
+      shift
+    elif [ "$(echo $1 | tr 'a-z' 'A-Z')" == "/C" ]; then
+      Build_Flags="$Build_Flags /c"
+      shift
+    elif [ "$(echo $1 | tr 'a-z' 'A-Z')" == "/ECP" ]; then
+      Build_Flags="$Build_Flags /ecp"
+      shift
+    elif [ "$(echo $1 | tr 'a-z' 'A-Z')" == "/X64" ]; then
+      Arch=X64
+      Build_Flags="$Build_Flags /x64"
+      shift
+    elif [ "$1" == "/nG" ]; then
+      Stitch_Flags="$Stitch_Flags /nG"
+      shift
+    elif [ "$1" == "/nM" ]; then
+      Stitch_Flags="$Stitch_Flags /nM"
+      shift
+    elif [ "$1" == "/nB" ]; then
+      Stitch_Flags="$Stitch_Flags /nB"
+      shift
+    elif [ "$1" == "/nV" ]; then
+      Stitch_Flags="$Stitch_Flags /nV"
+      shift
+    else
+      break
+    fi
+  done
+
+## Require 2 input parameters
+if [ "$2" == "" ]; then
+  Usage
+fi
+
+## Assign required arguments
+Platform_Type=$1
+Build_Target=$2
+if [ "$3" == "" ]; then
+  IFWI_Suffix=
+else
+  IFWI_Suffix="/S $3"
+fi
+
+## Go to root directory
+cd ..
+
+## Build BIOS
+echo "======================================================================"
+echo "Build_IFWI:  Calling BIOS build Script..."
+./$PLATFORM_PACKAGE/bld_vlv.sh $Build_Flags $Platform_Type $Build_Target
+
+echo
+echo Finished Building BIOS.
+
+## Start Integration process
+echo ======================================================================
+echo Skip "Build_IFWI:  Calling IFWI Stitching Script..."
+
+echo
+echo Build_IFWI is finished.
+echo The final IFWI file is located in Stitch
+echo ======================================================================

diff --git a/Vlv2TbltDevicePkg/FCE.exe b/Vlv2TbltDevicePkg/FCE.exe
new file mode 100644 (file)
index 0000000..2b787be
Binary files /dev/null and b/Vlv2TbltDevicePkg/FCE.exe differ

diff --git a/Vlv2TbltDevicePkg/FspAzaliaConfigData/AzaliaConfig.bin b/Vlv2TbltDevicePkg/FspAzaliaConfigData/AzaliaConfig.bin
new file mode 100644 (file)
index 0000000..da24c02
Binary files /dev/null and b/Vlv2TbltDevicePkg/FspAzaliaConfigData/AzaliaConfig.bin differ

diff --git a/Vlv2TbltDevicePkg/FspSupport/BootModePei/BootModePei.c b/Vlv2TbltDevicePkg/FspSupport/BootModePei/BootModePei.c
new file mode 100644 (file)
index 0000000..9fd3cb7
--- /dev/null
+++ b/Vlv2TbltDevicePkg/FspSupport/BootModePei/BootModePei.c
@@ -0,0 +1,48 @@
+/** @file\r
+  This PEIM will parse the hoblist from fsp and report them into pei core.\r
+  This file contains the main entrypoint of the PEIM.\r
+\r
+  Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>\r
+  This program and the accompanying materials\r
+  are licensed and made available under the terms and conditions of the BSD License\r
+  which accompanies this distribution.  The full text of the license may be found at\r
+  http://opensource.org/licenses/bsd-license.php.\r
+\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+\r
+#include <PiPei.h>\r
+#include <Ppi/MasterBootMode.h>\r
+\r
+static EFI_PEI_PPI_DESCRIPTOR       mPpiList[] = {\r
+  {\r
+    EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,\r
+    &gEfiPeiMasterBootModePpiGuid,\r
+    NULL\r
+  },\r
+};\r
+\r
+/**\r
+  This is the entrypoint of PEIM\r
+\r
+  @param  FileHandle  Handle of the file being invoked.\r
+  @param  PeiServices Describes the list of possible PEI Services.\r
+\r
+  @retval EFI_SUCCESS if it completed successfully.\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+BootModePeiEntryPoint (\r
+  IN       EFI_PEI_FILE_HANDLE  FileHandle,\r
+  IN CONST EFI_PEI_SERVICES     **PeiServices\r
+  )\r
+{\r
+  (*PeiServices)->SetBootMode(PeiServices, BOOT_WITH_FULL_CONFIGURATION);\r
+\r
+  (*PeiServices)->InstallPpi (PeiServices, &mPpiList[0]);\r
+\r
+  return EFI_SUCCESS;\r
+}\r

diff --git a/Vlv2TbltDevicePkg/FspSupport/BootModePei/BootModePei.inf b/Vlv2TbltDevicePkg/FspSupport/BootModePei/BootModePei.inf
new file mode 100644 (file)
index 0000000..40dbba7
--- /dev/null
+++ b/Vlv2TbltDevicePkg/FspSupport/BootModePei/BootModePei.inf
@@ -0,0 +1,45 @@
+## @file\r
+# FSP PEI Module\r
+#\r
+# Parses the hoblist from fsp and report them into pei core. It will install\r
+# the memory as required.\r
+#\r
+#  Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>\r
+#\r
+#  This program and the accompanying materials\r
+#  are licensed and made available under the terms and conditions of the BSD License\r
+#  which accompanies this distribution. The full text of the license may be found at\r
+#  http://opensource.org/licenses/bsd-license.php.\r
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+##\r
+\r
+[Defines]\r
+  INF_VERSION                    = 0x00010005\r
+  BASE_NAME                      = BootModePeim\r
+  FILE_GUID                      = 2B1D0832-2184-4C8F-A90D-8E4AF9DE5BCD\r
+  MODULE_TYPE                    = PEIM\r
+  VERSION_STRING                 = 1.0\r
+  ENTRY_POINT                    = BootModePeiEntryPoint\r
+\r
+#\r
+# The following information is for reference only and not required by the build tools.\r
+#\r
+#  VALID_ARCHITECTURES           = IA32\r
+#\r
+\r
+[Sources]\r
+  BootModePei.c\r
+\r
+[Packages]\r
+  MdePkg/MdePkg.dec\r
+\r
+[LibraryClasses]\r
+  PeimEntryPoint\r
+\r
+[Ppis]\r
+  gEfiPeiMasterBootModePpiGuid\r
+\r
+[Depex]\r
+  TRUE\r

diff --git a/Vlv2TbltDevicePkg/FspSupport/Library/PeiFspHobProcessLibVlv2/FspHobProcessLibVlv2.c b/Vlv2TbltDevicePkg/FspSupport/Library/PeiFspHobProcessLibVlv2/FspHobProcessLibVlv2.c
new file mode 100644 (file)
index 0000000..9442553
--- /dev/null
+++ b/Vlv2TbltDevicePkg/FspSupport/Library/PeiFspHobProcessLibVlv2/FspHobProcessLibVlv2.c
@@ -0,0 +1,387 @@
+/** @file\r
+  Null instance of Platform Sec Lib.\r
+\r
+  Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>\r
+  This program and the accompanying materials\r
+  are licensed and made available under the terms and conditions of the BSD License\r
+  which accompanies this distribution.  The full text of the license may be found at\r
+  http://opensource.org/licenses/bsd-license.php.\r
+\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#include <PiPei.h>\r
+\r
+#include <Library/PeiServicesLib.h>\r
+#include <Library/PeiServicesTablePointerLib.h>\r
+#include <Library/BaseLib.h>\r
+#include <Library/DebugLib.h>\r
+#include <Library/BaseMemoryLib.h>\r
+#include <Library/HobLib.h>\r
+#include <Library/PcdLib.h>\r
+#include <Library/FspPlatformInfoLib.h>\r
+\r
+#include <Guid/GuidHobFsp.h>\r
+#include <Guid/MemoryTypeInformation.h>\r
+#include <Ppi/Capsule.h>\r
+\r
+#include <PlatformFspLib.h>\r
+#include <Guid/SmramMemoryReserve.h>\r
+EFI_GUID gFspReservedMemoryResourceHobTsegGuid = {0xd038747c, 0xd00c, 0x4980, {0xb3, 0x19, 0x49, 0x01, 0x99, 0xa4, 0x7d, 0x55}};\r
+\r
+//\r
+// Additional pages are used by DXE memory manager.\r
+// It should be consistent between RetrieveRequiredMemorySize() and GetPeiMemSize()\r
+//\r
+#define PEI_ADDITIONAL_MEMORY_SIZE    (16 * EFI_PAGE_SIZE)\r
+\r
+/**\r
+  Get the mem size in memory type infromation table.\r
+\r
+  @param PeiServices  PEI Services table.\r
+\r
+  @return the mem size in memory type infromation table.\r
+**/\r
+UINT64\r
+GetMemorySizeInMemoryTypeInformation (\r
+  IN EFI_PEI_SERVICES **PeiServices\r
+  )\r
+{\r
+  EFI_STATUS                  Status;\r
+  EFI_PEI_HOB_POINTERS        Hob;\r
+  EFI_MEMORY_TYPE_INFORMATION *MemoryData;\r
+  UINT8                       Index;\r
+  UINTN                       TempPageNum;\r
+\r
+  MemoryData = NULL;\r
+  Status     = (*PeiServices)->GetHobList (PeiServices, (VOID **) &Hob.Raw);\r
+  while (!END_OF_HOB_LIST (Hob)) {\r
+    if (Hob.Header->HobType == EFI_HOB_TYPE_GUID_EXTENSION &&\r
+      CompareGuid (&Hob.Guid->Name, &gEfiMemoryTypeInformationGuid)) {\r
+      MemoryData = (EFI_MEMORY_TYPE_INFORMATION *) (Hob.Raw + sizeof (EFI_HOB_GENERIC_HEADER) + sizeof (EFI_GUID));\r
+      break;\r
+    }\r
+\r
+    Hob.Raw = GET_NEXT_HOB (Hob);\r
+  }\r
+\r
+  if (MemoryData == NULL) {\r
+    return 0;\r
+  }\r
+\r
+  TempPageNum = 0;\r
+  for (Index = 0; MemoryData[Index].Type != EfiMaxMemoryType; Index++) {\r
+    //\r
+    // Accumulate default memory size requirements\r
+    //\r
+    TempPageNum += MemoryData[Index].NumberOfPages;\r
+  }\r
+\r
+  return TempPageNum * EFI_PAGE_SIZE;\r
+}\r
+\r
+/**\r
+  Get the mem size need to be reserved in PEI phase.\r
+\r
+  @param PeiServices  PEI Services table.\r
+\r
+  @return the mem size need to be reserved in PEI phase.\r
+**/\r
+UINT64\r
+RetrieveRequiredMemorySize (\r
+  IN EFI_PEI_SERVICES **PeiServices\r
+  )\r
+{\r
+  UINT64                      Size;\r
+\r
+  Size = GetMemorySizeInMemoryTypeInformation (PeiServices);\r
+  return Size + PEI_ADDITIONAL_MEMORY_SIZE;\r
+}\r
+\r
+/**\r
+  Get the mem size need to be consumed and reserved in PEI phase.\r
+\r
+  @param PeiServices  PEI Services table.\r
+  @param BootMode     Current boot mode.\r
+\r
+  @return the mem size need to be consumed and reserved in PEI phase.\r
+**/\r
+UINT64\r
+GetPeiMemSize (\r
+  IN EFI_PEI_SERVICES **PeiServices,\r
+  IN UINT32           BootMode\r
+  )\r
+{\r
+  UINT64                      Size;\r
+  UINT64                      MinSize;\r
+\r
+  if (BootMode == BOOT_IN_RECOVERY_MODE) {\r
+    return PcdGet32 (PcdPeiRecoveryMinMemSize);\r
+  }\r
+\r
+  Size = GetMemorySizeInMemoryTypeInformation (PeiServices);\r
+\r
+  if (BootMode == BOOT_ON_FLASH_UPDATE) {\r
+    //\r
+    // Maybe more size when in CapsuleUpdate phase ?\r
+    //\r
+    MinSize = PcdGet32 (PcdPeiMinMemSize);\r
+  } else {\r
+    MinSize = PcdGet32 (PcdPeiMinMemSize);\r
+  }\r
+\r
+  return MinSize + Size + PEI_ADDITIONAL_MEMORY_SIZE;\r
+}\r
+\r
+/**\r
+  BIOS process FspBobList.\r
+\r
+  @param FspHobList  Pointer to the HOB data structure produced by FSP.\r
+\r
+  @return If platform process the FSP hob list successfully.\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+FspHobProcess (\r
+  IN VOID                 *FspHobList\r
+  )\r
+{\r
+  EFI_PEI_HOB_POINTERS Hob;\r
+  UINT64               LowMemorySize;\r
+  UINT64               FspMemorySize;\r
+  EFI_PHYSICAL_ADDRESS FspMemoryBase;\r
+  UINT64               PeiMemSize;\r
+  EFI_PHYSICAL_ADDRESS PeiMemBase;\r
+  UINT64               S3PeiMemSize;\r
+  EFI_PHYSICAL_ADDRESS S3PeiMemBase;\r
+  BOOLEAN              FoundFspMemHob;\r
+  EFI_STATUS           Status;\r
+  EFI_BOOT_MODE        BootMode;\r
+  PEI_CAPSULE_PPI      *Capsule;\r
+  VOID                 *CapsuleBuffer;\r
+  UINTN                CapsuleBufferLength;\r
+  UINT64               RequiredMemSize;\r
+  EFI_PEI_SERVICES     **PeiServices;\r
+  UINT64               TsegSize;\r
+  EFI_PHYSICAL_ADDRESS TsegBase;\r
+  BOOLEAN              FoundTsegHob;\r
+\r
+  PeiServices = (EFI_PEI_SERVICES **)GetPeiServicesTablePointer ();\r
+\r
+  PeiServicesGetBootMode (&BootMode);\r
+\r
+  PeiMemBase = 0;\r
+  LowMemorySize = 0;\r
+  FspMemorySize = 0;\r
+  FspMemoryBase = 0;\r
+  FoundFspMemHob = FALSE;\r
+  TsegSize      = 0;\r
+  TsegBase      = 0;\r
+  FoundTsegHob   = FALSE;\r
+\r
+  //\r
+  // Parse the hob list from fsp\r
+  // Report all the resource hob except the memory between 1M and 4G\r
+  //\r
+  Hob.Raw = (UINT8 *)(UINTN)FspHobList;\r
+  DEBUG((DEBUG_INFO, "FspHobList - 0x%x\n", FspHobList));\r
+\r
+  while ((Hob.Raw = GetNextHob (EFI_HOB_TYPE_RESOURCE_DESCRIPTOR, Hob.Raw)) != NULL) {\r
+    DEBUG((DEBUG_INFO, "\nResourceType: 0x%x\n", Hob.ResourceDescriptor->ResourceType));\r
+    if ((Hob.ResourceDescriptor->ResourceType == EFI_RESOURCE_SYSTEM_MEMORY) ||\r
+        (Hob.ResourceDescriptor->ResourceType == EFI_RESOURCE_MEMORY_RESERVED)) {\r
+      DEBUG((DEBUG_INFO, "ResourceAttribute: 0x%x\n", Hob.ResourceDescriptor->ResourceAttribute));\r
+      DEBUG((DEBUG_INFO, "PhysicalStart: 0x%x\n", Hob.ResourceDescriptor->PhysicalStart));\r
+      DEBUG((DEBUG_INFO, "ResourceLength: 0x%x\n", Hob.ResourceDescriptor->ResourceLength));\r
+      DEBUG((DEBUG_INFO, "Owner: %g\n\n", &Hob.ResourceDescriptor->Owner));\r
+    }\r
+\r
+    if ((Hob.ResourceDescriptor->ResourceType == EFI_RESOURCE_SYSTEM_MEMORY)  // Found the low memory length below 4G\r
+        && (Hob.ResourceDescriptor->PhysicalStart >= BASE_1MB)\r
+        && (Hob.ResourceDescriptor->PhysicalStart + Hob.ResourceDescriptor->ResourceLength <= BASE_4GB)) {\r
+        LowMemorySize += Hob.ResourceDescriptor->ResourceLength;\r
+      Hob.Raw = GET_NEXT_HOB (Hob);\r
+      continue;\r
+    }\r
+\r
+    if ((Hob.ResourceDescriptor->ResourceType == EFI_RESOURCE_MEMORY_RESERVED)  // Found the low memory length below 4G\r
+        && (Hob.ResourceDescriptor->PhysicalStart >= BASE_1MB)\r
+        && (Hob.ResourceDescriptor->PhysicalStart + Hob.ResourceDescriptor->ResourceLength <= BASE_4GB)\r
+        && (CompareGuid (&Hob.ResourceDescriptor->Owner, &gFspReservedMemoryResourceHobGuid))) {\r
+      FoundFspMemHob = TRUE;\r
+      FspMemoryBase = Hob.ResourceDescriptor->PhysicalStart;\r
+      FspMemorySize = Hob.ResourceDescriptor->ResourceLength;\r
+      DEBUG((DEBUG_INFO, "Find fsp mem hob, base 0x%x, len 0x%x\n", FspMemoryBase, FspMemorySize));\r
+    }\r
+\r
+    if ((Hob.ResourceDescriptor->ResourceType == EFI_RESOURCE_MEMORY_RESERVED)  // Found the low memory length below 4G\r
+      && (Hob.ResourceDescriptor->PhysicalStart >= 0x100000)\r
+      && (Hob.ResourceDescriptor->PhysicalStart + Hob.ResourceDescriptor->ResourceLength <= 0x100000000)\r
+      && (CompareGuid (&Hob.ResourceDescriptor->Owner, &gFspReservedMemoryResourceHobTsegGuid))) {\r
+        FoundTsegHob = TRUE;\r
+        TsegBase = Hob.ResourceDescriptor->PhysicalStart;\r
+\r
+\r
+        if ((Hob.ResourceDescriptor->ResourceLength == 0  ) || (Hob.ResourceDescriptor->ResourceLength > 0x800000)){\r
+          Hob.ResourceDescriptor->ResourceLength = 0x800000;\r
+        }\r
+\r
+\r
+        TsegSize = Hob.ResourceDescriptor->ResourceLength;\r
+        DEBUG((EFI_D_ERROR, "Find Tseg mem hob, base 0x%lx, len 0x%lx\n", TsegBase, TsegSize));\r
+      }\r
+\r
+    //\r
+    // Report the resource hob\r
+    //\r
+    BuildResourceDescriptorHob (\r
+      Hob.ResourceDescriptor->ResourceType,\r
+      Hob.ResourceDescriptor->ResourceAttribute,\r
+      Hob.ResourceDescriptor->PhysicalStart,\r
+      Hob.ResourceDescriptor->ResourceLength\r
+      );\r
+\r
+    Hob.Raw = GET_NEXT_HOB (Hob);\r
+  }\r
+\r
+  if (!FoundFspMemHob) {\r
+    DEBUG((DEBUG_INFO, "Didn't find the fsp used memory information.\n"));\r
+    //ASSERT(FALSE);\r
+  }\r
+\r
+  DEBUG((DEBUG_INFO, "LowMemorySize: 0x%x.\n", LowMemorySize));\r
+  DEBUG((DEBUG_INFO, "FspMemoryBase: 0x%x.\n", FspMemoryBase));\r
+  DEBUG((DEBUG_INFO, "FspMemorySize: 0x%x.\n", FspMemorySize));\r
+\r
+  if (BootMode == BOOT_ON_S3_RESUME) {\r
+    BuildResourceDescriptorHob (\r
+      EFI_RESOURCE_SYSTEM_MEMORY,\r
+      (\r
+         EFI_RESOURCE_ATTRIBUTE_PRESENT |\r
+         EFI_RESOURCE_ATTRIBUTE_INITIALIZED |\r
+         // EFI_RESOURCE_ATTRIBUTE_TESTED |\r
+         EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |\r
+         EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |\r
+         EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |\r
+         EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE\r
+      ),\r
+      BASE_1MB,\r
+      LowMemorySize\r
+      );\r
+\r
+    Status = GetS3MemoryInfo (&S3PeiMemBase, &S3PeiMemSize);\r
+    ASSERT_EFI_ERROR (Status);\r
+    DEBUG((DEBUG_INFO, "S3 memory %Xh - %Xh bytes\n", S3PeiMemBase, S3PeiMemSize));\r
+\r
+    //\r
+    // Make sure Stack and PeiMemory are not overlap - JYAO1\r
+    //\r
+\r
+    Status = PeiServicesInstallPeiMemory (\r
+               S3PeiMemBase,\r
+               S3PeiMemSize\r
+               );\r
+    ASSERT_EFI_ERROR (Status);\r
+  } else {\r
+    PeiMemSize = GetPeiMemSize (PeiServices, BootMode);\r
+    DEBUG((DEBUG_INFO, "PEI memory size = %Xh bytes\n", PeiMemSize));\r
+\r
+    //\r
+    // Capsule mode\r
+    //\r
+    Capsule = NULL;\r
+    CapsuleBuffer = NULL;\r
+    CapsuleBufferLength = 0;\r
+    if (BootMode == BOOT_ON_FLASH_UPDATE) {\r
+      Status = PeiServicesLocatePpi (\r
+                 &gPeiCapsulePpiGuid,\r
+                 0,\r
+                 NULL,\r
+                 (VOID **) &Capsule\r
+                 );\r
+      ASSERT_EFI_ERROR (Status);\r
+\r
+      if (Status == EFI_SUCCESS) {\r
+        //\r
+        // Make sure Stack and CapsuleBuffer are not overlap - JYAO1\r
+        //\r
+        CapsuleBuffer = (VOID *)(UINTN)BASE_1MB;\r
+        CapsuleBufferLength = (UINTN)(LowMemorySize - PeiMemSize);\r
+        //\r
+        // Call the Capsule PPI Coalesce function to coalesce the capsule data.\r
+        //\r
+        Status = Capsule->Coalesce (PeiServices, &CapsuleBuffer, &CapsuleBufferLength);\r
+      }\r
+    }\r
+\r
+    RequiredMemSize = RetrieveRequiredMemorySize (PeiServices);\r
+    DEBUG((DEBUG_INFO, "Required memory size = %Xh bytes\n", RequiredMemSize));\r
+\r
+    //\r
+    // Report the main memory\r
+    //\r
+    BuildResourceDescriptorHob (\r
+      EFI_RESOURCE_SYSTEM_MEMORY,\r
+      (\r
+         EFI_RESOURCE_ATTRIBUTE_PRESENT |\r
+         EFI_RESOURCE_ATTRIBUTE_INITIALIZED |\r
+         EFI_RESOURCE_ATTRIBUTE_TESTED |\r
+         EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |\r
+         EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |\r
+         EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |\r
+         EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE\r
+      ),\r
+      BASE_1MB,\r
+      LowMemorySize\r
+      );\r
+\r
+    //\r
+    // Make sure Stack and CapsuleBuffer are not overlap - JYAO1\r
+    //\r
+\r
+    //\r
+    // Install efi memory\r
+    //\r
+    PeiMemBase = BASE_1MB + LowMemorySize - PeiMemSize;\r
+    Status = PeiServicesInstallPeiMemory (\r
+               PeiMemBase,\r
+               PeiMemSize - RequiredMemSize\r
+               );\r
+    ASSERT_EFI_ERROR (Status);\r
+\r
+    if (Capsule != NULL) {\r
+      Status = Capsule->CreateState (PeiServices, CapsuleBuffer, CapsuleBufferLength);\r
+    }\r
+  }\r
+\r
+  //\r
+  // Report GUIDed HOB for reserving SMRAM regions\r
+  //\r
+  if (FoundTsegHob) {\r
+    EFI_SMRAM_HOB_DESCRIPTOR_BLOCK  *SmramHobDescriptorBlock;\r
+\r
+    SmramHobDescriptorBlock = BuildGuidHob (\r
+             &gEfiSmmPeiSmramMemoryReserveGuid,\r
+             sizeof (EFI_SMRAM_HOB_DESCRIPTOR_BLOCK)\r
+             );\r
+    ASSERT (SmramHobDescriptorBlock != NULL);\r
+\r
+    SmramHobDescriptorBlock->NumberOfSmmReservedRegions = 1;\r
+\r
+    SmramHobDescriptorBlock->Descriptor[0].PhysicalStart = TsegBase;\r
+    SmramHobDescriptorBlock->Descriptor[0].CpuStart      = TsegBase;\r
+    SmramHobDescriptorBlock->Descriptor[0].PhysicalSize  = TsegSize;\r
+    SmramHobDescriptorBlock->Descriptor[0].RegionState   = EFI_SMRAM_CLOSED;\r
+  }\r
+  //\r
+  // NV Storage Hob\r
+  //\r
+  //\r
+  // Other hob for platform\r
+  //\r
+  PlatformHobCreateFromFsp ( PeiServices,  FspHobList);\r
+\r
+  return EFI_SUCCESS;\r
+}\r

diff --git a/Vlv2TbltDevicePkg/FspSupport/Library/PeiFspHobProcessLibVlv2/FspHobProcessLibVlv2.inf b/Vlv2TbltDevicePkg/FspSupport/Library/PeiFspHobProcessLibVlv2/FspHobProcessLibVlv2.inf
new file mode 100644 (file)
index 0000000..909285f
--- /dev/null
+++ b/Vlv2TbltDevicePkg/FspSupport/Library/PeiFspHobProcessLibVlv2/FspHobProcessLibVlv2.inf
@@ -0,0 +1,79 @@
+## @file\r
+#\r
+#  Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>\r
+#\r
+#  This program and the accompanying materials\r
+#  are licensed and made available under the terms and conditions of the BSD License\r
+#  which accompanies this distribution. The full text of the license may be found at\r
+#  http://opensource.org/licenses/bsd-license.php.\r
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+##\r
+\r
+################################################################################\r
+#\r
+# Defines Section - statements that will be processed to create a Makefile.\r
+#\r
+################################################################################\r
+[Defines]\r
+  INF_VERSION                    = 0x00010005\r
+  BASE_NAME                      = PeiFspHobProcessLibVlv2\r
+  FILE_GUID                      = C7B7070B-E5A8-4b86-9110-BDCA1095F496\r
+  MODULE_TYPE                    = SEC\r
+  VERSION_STRING                 = 1.0\r
+  LIBRARY_CLASS                  = FspHobProcessLib\r
+\r
+#\r
+# The following information is for reference only and not required by the build tools.\r
+#\r
+#  VALID_ARCHITECTURES           = IA32 X64\r
+#\r
+\r
+################################################################################\r
+#\r
+# Sources Section - list of files that are required for the build to succeed.\r
+#\r
+################################################################################\r
+\r
+[Sources]\r
+  FspHobProcessLibVlv2.c\r
+\r
+\r
+################################################################################\r
+#\r
+# Package Dependency Section - list of Package files that are required for\r
+#                              this module.\r
+#\r
+################################################################################\r
+\r
+[Packages]\r
+  MdePkg/MdePkg.dec\r
+  MdeModulePkg/MdeModulePkg.dec\r
+  IntelFrameworkPkg/IntelFrameworkPkg.dec\r
+  IntelFrameworkModulePkg/IntelFrameworkModulePkg.dec\r
+  IntelFspPkg/IntelFspPkg.dec\r
+  IntelFspWrapperPkg/IntelFspWrapperPkg.dec\r
+  Vlv2TbltDevicePkg/PlatformPkg.dec\r
+\r
+[LibraryClasses]\r
+  BaseLib\r
+  BaseMemoryLib\r
+  HobLib\r
+  DebugLib\r
+  FspPlatformInfoLib\r
+  PeiServicesLib\r
+  PeiServicesTablePointerLib\r
+  PlatformFspLib\r
+\r
+[Pcd]\r
+  gFspWrapperTokenSpaceGuid.PcdPeiMinMemSize\r
+  gFspWrapperTokenSpaceGuid.PcdPeiRecoveryMinMemSize\r
+\r
+[Guids]\r
+  gFspReservedMemoryResourceHobGuid\r
+  gEfiMemoryTypeInformationGuid\r
+  gEfiSmmPeiSmramMemoryReserveGuid\r
+\r
+[Ppis]\r
+  gPeiCapsulePpiGuid\r

diff --git a/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecLibVlv2/FspPlatformSecLibVlv2.c b/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecLibVlv2/FspPlatformSecLibVlv2.c
new file mode 100644 (file)
index 0000000..7a7931b
--- /dev/null
+++ b/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecLibVlv2/FspPlatformSecLibVlv2.c
@@ -0,0 +1,150 @@
+/** @file\r
+\r
+  Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>\r
+  This program and the accompanying materials\r
+  are licensed and made available under the terms and conditions of the BSD License\r
+  which accompanies this distribution.  The full text of the license may be found at\r
+  http://opensource.org/licenses/bsd-license.php.\r
+\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#include <PiPei.h>\r
+\r
+#include <Ppi/SecPlatformInformation.h>\r
+#include <Ppi/SecPerformance.h>\r
+#include <Ppi/TemporaryRamSupport.h>\r
+\r
+#include <Library/LocalApicLib.h>\r
+\r
+/**\r
+  This interface conveys state information out of the Security (SEC) phase into PEI.\r
+\r
+  @param  PeiServices               Pointer to the PEI Services Table.\r
+  @param  StructureSize             Pointer to the variable describing size of the input buffer.\r
+  @param  PlatformInformationRecord Pointer to the EFI_SEC_PLATFORM_INFORMATION_RECORD.\r
+\r
+  @retval EFI_SUCCESS               The data was successfully returned.\r
+  @retval EFI_BUFFER_TOO_SMALL      The buffer was too small.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+SecPlatformInformation (\r
+  IN CONST EFI_PEI_SERVICES                     **PeiServices,\r
+  IN OUT   UINT64                               *StructureSize,\r
+     OUT   EFI_SEC_PLATFORM_INFORMATION_RECORD  *PlatformInformationRecord\r
+  );\r
+\r
+/**\r
+  This interface conveys performance information out of the Security (SEC) phase into PEI.\r
+\r
+  This service is published by the SEC phase. The SEC phase handoff has an optional\r
+  EFI_PEI_PPI_DESCRIPTOR list as its final argument when control is passed from SEC into the\r
+  PEI Foundation. As such, if the platform supports collecting performance data in SEC,\r
+  this information is encapsulated into the data structure abstracted by this service.\r
+  This information is collected for the boot-strap processor (BSP) on IA-32.\r
+\r
+  @param[in]  PeiServices  The pointer to the PEI Services Table.\r
+  @param[in]  This         The pointer to this instance of the PEI_SEC_PERFORMANCE_PPI.\r
+  @param[out] Performance  The pointer to performance data collected in SEC phase.\r
+\r
+  @retval EFI_SUCCESS      The data was successfully returned.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+SecGetPerformance (\r
+  IN CONST EFI_PEI_SERVICES          **PeiServices,\r
+  IN       PEI_SEC_PERFORMANCE_PPI   *This,\r
+  OUT      FIRMWARE_SEC_PERFORMANCE  *Performance\r
+  );\r
+\r
+/**\r
+  This service of the TEMPORARY_RAM_SUPPORT_PPI that migrates temporary RAM into\r
+  permanent memory.\r
+\r
+  @param PeiServices            Pointer to the PEI Services Table.\r
+  @param TemporaryMemoryBase    Source Address in temporary memory from which the SEC or PEIM will copy the\r
+                                Temporary RAM contents.\r
+  @param PermanentMemoryBase    Destination Address in permanent memory into which the SEC or PEIM will copy the\r
+                                Temporary RAM contents.\r
+  @param CopySize               Amount of memory to migrate from temporary to permanent memory.\r
+\r
+  @retval EFI_SUCCESS           The data was successfully returned.\r
+  @retval EFI_INVALID_PARAMETER PermanentMemoryBase + CopySize > TemporaryMemoryBase when\r
+                                TemporaryMemoryBase > PermanentMemoryBase.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+SecTemporaryRamSupport (\r
+  IN CONST EFI_PEI_SERVICES   **PeiServices,\r
+  IN EFI_PHYSICAL_ADDRESS     TemporaryMemoryBase,\r
+  IN EFI_PHYSICAL_ADDRESS     PermanentMemoryBase,\r
+  IN UINTN                    CopySize\r
+  );\r
+\r
+EFI_SEC_PLATFORM_INFORMATION_PPI  mSecPlatformInformationPpi = {\r
+  SecPlatformInformation\r
+};\r
+\r
+PEI_SEC_PERFORMANCE_PPI  mSecPerformancePpi = {\r
+  SecGetPerformance\r
+};\r
+\r
+EFI_PEI_TEMPORARY_RAM_SUPPORT_PPI gSecTemporaryRamSupportPpi = {\r
+  SecTemporaryRamSupport\r
+};\r
+\r
+EFI_PEI_PPI_DESCRIPTOR  mPeiSecPlatformPpi[] = {\r
+  {\r
+    EFI_PEI_PPI_DESCRIPTOR_PPI,\r
+    &gEfiSecPlatformInformationPpiGuid,\r
+    &mSecPlatformInformationPpi\r
+  },\r
+  {\r
+    EFI_PEI_PPI_DESCRIPTOR_PPI,\r
+    &gPeiSecPerformancePpiGuid,\r
+    &mSecPerformancePpi\r
+  },\r
+  {\r
+    EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,\r
+    &gEfiTemporaryRamSupportPpiGuid,\r
+    &gSecTemporaryRamSupportPpi\r
+  },\r
+};\r
+\r
+/**\r
+  A developer supplied function to perform platform specific operations.\r
+\r
+  It's a developer supplied function to perform any operations appropriate to a\r
+  given platform. It's invoked just before passing control to PEI core by SEC\r
+  core. Platform developer may modify the SecCoreData passed to PEI Core.\r
+  It returns a platform specific PPI list that platform wishes to pass to PEI core.\r
+  The Generic SEC core module will merge this list to join the final list passed to\r
+  PEI core.\r
+\r
+  @param  SecCoreData           The same parameter as passing to PEI core. It\r
+                                could be overridden by this function.\r
+\r
+  @return The platform specific PPI list to be passed to PEI core or\r
+          NULL if there is no need of such platform specific PPI list.\r
+\r
+**/\r
+EFI_PEI_PPI_DESCRIPTOR *\r
+EFIAPI\r
+SecPlatformMain (\r
+  IN OUT   EFI_SEC_PEI_HAND_OFF        *SecCoreData\r
+  )\r
+{\r
+  EFI_PEI_PPI_DESCRIPTOR      *PpiList;\r
+\r
+  InitializeApicTimer (0, (UINT32) -1, TRUE, 5);\r
+\r
+  PpiList = &mPeiSecPlatformPpi[0];\r
+\r
+  return PpiList;\r
+}\r

diff --git a/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecLibVlv2/FspPlatformSecLibVlv2.inf b/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecLibVlv2/FspPlatformSecLibVlv2.inf
new file mode 100644 (file)
index 0000000..3d9b135
--- /dev/null
+++ b/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecLibVlv2/FspPlatformSecLibVlv2.inf
@@ -0,0 +1,87 @@
+## @file\r
+#\r
+#  Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>\r
+#\r
+#  This program and the accompanying materials\r
+#  are licensed and made available under the terms and conditions of the BSD License\r
+#  which accompanies this distribution. The full text of the license may be found at\r
+#  http://opensource.org/licenses/bsd-license.php.\r
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+##\r
+\r
+################################################################################\r
+#\r
+# Defines Section - statements that will be processed to create a Makefile.\r
+#\r
+################################################################################\r
+[Defines]\r
+  INF_VERSION                    = 0x00010005\r
+  BASE_NAME                      = SecPeiFspPlatformSecLibVlv2\r
+  FILE_GUID                      = 6653876C-F6A1-45BB-A027-20455093BC6D\r
+  MODULE_TYPE                    = SEC\r
+  VERSION_STRING                 = 1.0\r
+  LIBRARY_CLASS                  = FspPlatformSecLib\r
+\r
+#\r
+# The following information is for reference only and not required by the build tools.\r
+#\r
+#  VALID_ARCHITECTURES           = IA32 X64\r
+#\r
+\r
+################################################################################\r
+#\r
+# Sources Section - list of files that are required for the build to succeed.\r
+#\r
+################################################################################\r
+\r
+[Sources]\r
+  FspPlatformSecLibVlv2.c\r
+  SecRamInitData.c\r
+  SaveSecContext.c\r
+  SecPlatformInformation.c\r
+  SecGetPerformance.c\r
+  SecTempRamSupport.c\r
+  PlatformInit.c\r
+  UartInit.c\r
+\r
+[Sources.IA32]\r
+  Ia32/SecEntry.asm\r
+  Ia32/PeiCoreEntry.asm\r
+  Ia32/AsmSaveSecContext.asm\r
+  Ia32/Stack.asm\r
+\r
+################################################################################\r
+#\r
+# Package Dependency Section - list of Package files that are required for\r
+#                              this module.\r
+#\r
+################################################################################\r
+\r
+[Packages]\r
+  MdePkg/MdePkg.dec\r
+  MdeModulePkg/MdeModulePkg.dec\r
+  UefiCpuPkg/UefiCpuPkg.dec\r
+  IntelFspWrapperPkg/IntelFspWrapperPkg.dec\r
+\r
+[LibraryClasses]\r
+  LocalApicLib\r
+  SerialPortLib\r
+\r
+[Ppis]\r
+  gEfiSecPlatformInformationPpiGuid\r
+  gPeiSecPerformancePpiGuid\r
+  gEfiTemporaryRamSupportPpiGuid\r
+\r
+[Pcd]\r
+  gFspWrapperTokenSpaceGuid.PcdPeiTemporaryRamStackSize\r
+  gFspWrapperTokenSpaceGuid.PcdFlashFvFspBase\r
+  gFspWrapperTokenSpaceGuid.PcdFlashFvFspSize\r
+\r
+[FixedPcd]\r
+  gFspWrapperTokenSpaceGuid.PcdCpuMicrocodePatchAddress\r
+  gFspWrapperTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize\r
+  gFspWrapperTokenSpaceGuid.PcdFlashMicroCodeOffset\r
+  gFspWrapperTokenSpaceGuid.PcdFlashCodeCacheAddress\r
+  gFspWrapperTokenSpaceGuid.PcdFlashCodeCacheSize\r

diff --git a/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecLibVlv2/Ia32/AsmSaveSecContext.asm b/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecLibVlv2/Ia32/AsmSaveSecContext.asm
new file mode 100644 (file)
index 0000000..703b38b
--- /dev/null
+++ b/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecLibVlv2/Ia32/AsmSaveSecContext.asm
@@ -0,0 +1,51 @@
+;------------------------------------------------------------------------------\r
+;\r
+; Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>\r
+; This program and the accompanying materials\r
+; are licensed and made available under the terms and conditions of the BSD License\r
+; which accompanies this distribution.  The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php.\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+; Module Name:\r
+;\r
+;  SecEntry.asm\r
+;\r
+; Abstract:\r
+;\r
+;  This is the code that goes from real-mode to protected mode.\r
+;  It consumes the reset vector, calls two basic APIs from FSP binary.\r
+;\r
+;------------------------------------------------------------------------------\r
+\r
+.686p\r
+.xmm\r
+.model flat,c\r
+.code\r
+\r
+;----------------------------------------------------------------------------\r
+;  MMX Usage:\r
+;              MM0 = BIST State\r
+;              MM5 = Save time-stamp counter value high32bit\r
+;              MM6 = Save time-stamp counter value low32bit.\r
+;\r
+;  It should be same as SecEntry.asm and PeiCoreEntry.asm.\r
+;----------------------------------------------------------------------------\r
+\r
+AsmSaveBistValue   PROC PUBLIC\r
+  mov     eax, [esp+4]\r
+  movd    mm0, eax\r
+  ret\r
+AsmSaveBistValue   ENDP\r
+\r
+AsmSaveTickerValue   PROC PUBLIC\r
+  mov     eax, [esp+4]\r
+  movd    mm6, eax\r
+  mov     eax, [esp+8]\r
+  movd    mm5, eax\r
+  ret\r
+AsmSaveTickerValue   ENDP\r
+\r
+END\r

diff --git a/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecLibVlv2/Ia32/Fsp.inc b/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecLibVlv2/Ia32/Fsp.inc
new file mode 100644 (file)
index 0000000..296c47e
--- /dev/null
+++ b/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecLibVlv2/Ia32/Fsp.inc
@@ -0,0 +1,51 @@
+;------------------------------------------------------------------------------\r
+;\r
+; Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>\r
+; This program and the accompanying materials\r
+; are licensed and made available under the terms and conditions of the BSD License\r
+; which accompanies this distribution.  The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php.\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+; Module Name:\r
+;\r
+;   Fsp.inc\r
+;\r
+; Abstract:\r
+;\r
+;   Fsp related definitions\r
+;\r
+;------------------------------------------------------------------------------\r
+\r
+\r
+;\r
+; Fv Header\r
+;\r
+FVH_SIGINATURE_OFFSET       EQU  028h\r
+FVH_SIGINATURE_VALID_VALUE  EQU  04856465Fh    ; valid signature:_FVH\r
+FVH_HEADER_LENGTH_OFFSET    EQU  030h\r
+FVH_EXTHEADER_OFFSET_OFFSET EQU  034h\r
+FVH_EXTHEADER_SIZE_OFFSET   EQU  010h\r
+\r
+;\r
+; Ffs Header\r
+;\r
+FSP_HEADER_GUID_DWORD1      EQU  0912740BEh\r
+FSP_HEADER_GUID_DWORD2      EQU  047342284h\r
+FSP_HEADER_GUID_DWORD3      EQU  0B08471B9h\r
+FSP_HEADER_GUID_DWORD4      EQU  00C3F3527h\r
+FFS_HEADER_SIZE_VALUE       EQU  018h\r
+\r
+;\r
+; Section Header\r
+;\r
+SECTION_HEADER_TYPE_OFFSET  EQU  03h\r
+RAW_SECTION_HEADER_SIZE_VALUE  EQU  04h\r
+\r
+;\r
+; Fsp Header\r
+;\r
+FSP_HEADER_IMAGEBASE_OFFSET   EQU  01Ch\r
+FSP_HEADER_TEMPRAMINIT_OFFSET EQU  030h\r

diff --git a/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecLibVlv2/Ia32/PeiCoreEntry.asm b/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecLibVlv2/Ia32/PeiCoreEntry.asm
new file mode 100644 (file)
index 0000000..5935034
--- /dev/null
+++ b/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecLibVlv2/Ia32/PeiCoreEntry.asm
@@ -0,0 +1,141 @@
+;------------------------------------------------------------------------------\r
+;\r
+; Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>\r
+; This program and the accompanying materials\r
+; are licensed and made available under the terms and conditions of the BSD License\r
+; which accompanies this distribution.  The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php.\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+; Module Name:\r
+;\r
+;  SecEntry.asm\r
+;\r
+; Abstract:\r
+;\r
+;  This is the code that goes from real-mode to protected mode.\r
+;  It consumes the reset vector, calls two basic APIs from FSP binary.\r
+;\r
+;------------------------------------------------------------------------------\r
+\r
+.686p\r
+.xmm\r
+.model flat, c\r
+.code\r
+\r
+EXTRN   SecStartup:NEAR\r
+EXTRN   PlatformInit:NEAR\r
+\r
+CallPeiCoreEntryPoint   PROC PUBLIC\r
+  ;\r
+  ; Obtain the hob list pointer\r
+  ;\r
+  mov     eax, [esp+4]\r
+  ;\r
+  ; Obtain the stack information\r
+  ;   ECX: start of range\r
+  ;   EDX: end of range\r
+  ;\r
+  mov     ecx, [esp+8]\r
+  mov     edx, [esp+0Ch]\r
+\r
+  ;\r
+  ; Platform init\r
+  ;\r
+  pushad\r
+  push edx\r
+  push ecx\r
+  push eax\r
+  call PlatformInit\r
+  pop  eax\r
+  pop  eax\r
+  pop  eax\r
+  popad\r
+\r
+  ;\r
+  ; Set stack top pointer\r
+  ;\r
+  mov     esp, edx\r
+\r
+  ;\r
+  ; Push the hob list pointer\r
+  ;\r
+  push    eax\r
+\r
+  ;\r
+  ; Save the value\r
+  ;   ECX: start of range\r
+  ;   EDX: end of range\r
+  ;\r
+  mov     ebp, esp\r
+  push    ecx\r
+  push    edx\r
+\r
+  ;\r
+  ; Push processor count to stack first, then BIST status (AP then BSP)\r
+  ;\r
+  mov     eax, 1\r
+  cpuid\r
+  shr     ebx, 16\r
+  and     ebx, 0000000FFh\r
+  cmp     bl, 1\r
+  jae     PushProcessorCount\r
+\r
+  ;\r
+  ; Some processors report 0 logical processors.  Effectively 0 = 1.\r
+  ; So we fix up the processor count\r
+  ;\r
+  inc     ebx\r
+\r
+PushProcessorCount:\r
+  push    ebx\r
+\r
+  ;\r
+  ; We need to implement a long-term solution for BIST capture.  For now, we just copy BSP BIST\r
+  ; for all processor threads\r
+  ;\r
+  xor     ecx, ecx\r
+  mov     cl, bl\r
+PushBist:\r
+  movd    eax, mm0\r
+  push    eax\r
+  loop    PushBist\r
+\r
+  ; Save Time-Stamp Counter\r
+  movd eax, mm5\r
+  push eax\r
+\r
+  movd eax, mm6\r
+  push eax\r
+\r
+  ;\r
+  ; Pass entry point of the PEI core\r
+  ;\r
+  mov     edi, 0FFFFFFE0h\r
+  push    DWORD PTR ds:[edi]\r
+\r
+  ;\r
+  ; Pass BFV into the PEI Core\r
+  ;\r
+  mov     edi, 0FFFFFFFCh\r
+  push    DWORD PTR ds:[edi]\r
+\r
+  ;\r
+  ; Pass stack size into the PEI Core\r
+  ;\r
+  mov     ecx, [ebp - 4]\r
+  mov     edx, [ebp - 8]\r
+  push    ecx       ; RamBase\r
+\r
+  sub     edx, ecx\r
+  push    edx       ; RamSize\r
+\r
+  ;\r
+  ; Pass Control into the PEI Core\r
+  ;\r
+  call SecStartup\r
+CallPeiCoreEntryPoint   ENDP\r
+\r
+END\r

diff --git a/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecLibVlv2/Ia32/SecEntry.asm b/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecLibVlv2/Ia32/SecEntry.asm
new file mode 100644 (file)
index 0000000..f8a3182
--- /dev/null
+++ b/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecLibVlv2/Ia32/SecEntry.asm
@@ -0,0 +1,344 @@
+;------------------------------------------------------------------------------\r
+;\r
+; Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>\r
+; This program and the accompanying materials\r
+; are licensed and made available under the terms and conditions of the BSD License\r
+; which accompanies this distribution.  The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php.\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+; Module Name:\r
+;\r
+;  SecEntry.asm\r
+;\r
+; Abstract:\r
+;\r
+;  This is the code that goes from real-mode to protected mode.\r
+;  It consumes the reset vector, calls two basic APIs from FSP binary.\r
+;\r
+;------------------------------------------------------------------------------\r
+  INCLUDE Fsp.inc\r
+\r
+.686p\r
+.xmm\r
+.model small, c\r
+\r
+EXTRN   CallPeiCoreEntryPoint:NEAR\r
+EXTRN   TempRamInitParams:FAR\r
+\r
+; Pcds\r
+EXTRN   PcdGet32 (PcdFlashFvFspBase):DWORD\r
+EXTRN   PcdGet32 (PcdFlashFvFspSize):DWORD\r
+\r
+_TEXT_REALMODE      SEGMENT PARA PUBLIC USE16 'CODE'\r
+                    ASSUME  CS:_TEXT_REALMODE, DS:_TEXT_REALMODE\r
+\r
+;----------------------------------------------------------------------------\r
+;\r
+; Procedure:    _ModuleEntryPoint\r
+;\r
+; Input:        None\r
+;\r
+; Output:       None\r
+;\r
+; Destroys:     Assume all registers\r
+;\r
+; Description:\r
+;\r
+;   Transition to non-paged flat-model protected mode from a\r
+;   hard-coded GDT that provides exactly two descriptors.\r
+;   This is a bare bones transition to protected mode only\r
+;   used for a while in PEI and possibly DXE.\r
+;\r
+;   After enabling protected mode, a far jump is executed to\r
+;   transfer to PEI using the newly loaded GDT.\r
+;\r
+; Return:       None\r
+;\r
+;  MMX Usage:\r
+;              MM0 = BIST State\r
+;              MM5 = Save time-stamp counter value high32bit\r
+;              MM6 = Save time-stamp counter value low32bit.\r
+;\r
+;----------------------------------------------------------------------------\r
+\r
+align 4\r
+_ModuleEntryPoint PROC NEAR C PUBLIC\r
+  fninit                                ; clear any pending Floating point exceptions\r
+  ;\r
+  ; Store the BIST value in mm0\r
+  ;\r
+  movd    mm0, eax\r
+\r
+  ;\r
+  ; Save time-stamp counter value\r
+  ; rdtsc load 64bit time-stamp counter to EDX:EAX\r
+  ;\r
+  rdtsc\r
+  movd    mm5, edx\r
+  movd    mm6, eax\r
+\r
+  ;\r
+  ; Load the GDT table in GdtDesc\r
+  ;\r
+  mov     esi,  OFFSET GdtDesc\r
+  DB      66h\r
+  lgdt    fword ptr cs:[si]\r
+\r
+  ;\r
+  ; Transition to 16 bit protected mode\r
+  ;\r
+  mov     eax, cr0                   ; Get control register 0\r
+  or      eax, 00000003h             ; Set PE bit (bit #0) & MP bit (bit #1)\r
+  mov     cr0, eax                   ; Activate protected mode\r
+\r
+  mov     eax, cr4                   ; Get control register 4\r
+  or      eax, 00000600h             ; Set OSFXSR bit (bit #9) & OSXMMEXCPT bit (bit #10)\r
+  mov     cr4, eax\r
+\r
+  ;\r
+  ; Now we're in 16 bit protected mode\r
+  ; Set up the selectors for 32 bit protected mode entry\r
+  ;\r
+  mov     ax, SYS_DATA_SEL\r
+  mov     ds, ax\r
+  mov     es, ax\r
+  mov     fs, ax\r
+  mov     gs, ax\r
+  mov     ss, ax\r
+\r
+  ;\r
+  ; Transition to Flat 32 bit protected mode\r
+  ; The jump to a far pointer causes the transition to 32 bit mode\r
+  ;\r
+  mov esi, offset ProtectedModeEntryLinearAddress\r
+  jmp     fword ptr cs:[si]\r
+\r
+_ModuleEntryPoint   ENDP\r
+_TEXT_REALMODE      ENDS\r
+\r
+_TEXT_PROTECTED_MODE      SEGMENT PARA PUBLIC USE32 'CODE'\r
+                          ASSUME  CS:_TEXT_PROTECTED_MODE, DS:_TEXT_PROTECTED_MODE\r
+\r
+;----------------------------------------------------------------------------\r
+;\r
+; Procedure:    ProtectedModeEntryPoint\r
+;\r
+; Input:        None\r
+;\r
+; Output:       None\r
+;\r
+; Destroys:     Assume all registers\r
+;\r
+; Description:\r
+;\r
+; This function handles:\r
+;   Call two basic APIs from FSP binary\r
+;   Initializes stack with some early data (BIST, PEI entry, etc)\r
+;\r
+; Return:       None\r
+;\r
+;----------------------------------------------------------------------------\r
+\r
+align 4\r
+ProtectedModeEntryPoint PROC NEAR PUBLIC\r
+\r
+  ; Find the fsp info header\r
+  mov  edi, PcdGet32 (PcdFlashFvFspBase)\r
+  mov  ecx, PcdGet32 (PcdFlashFvFspSize)\r
+\r
+  mov  eax, dword ptr [edi + FVH_SIGINATURE_OFFSET]\r
+  cmp  eax, FVH_SIGINATURE_VALID_VALUE\r
+  jnz  FspHeaderNotFound\r
+\r
+  xor  eax, eax\r
+  mov  ax, word ptr [edi + FVH_EXTHEADER_OFFSET_OFFSET]\r
+  cmp  ax, 0\r
+  jnz  FspFvExtHeaderExist\r
+\r
+  xor  eax, eax\r
+  mov  ax, word ptr [edi + FVH_HEADER_LENGTH_OFFSET]   ; Bypass Fv Header\r
+  add  edi, eax\r
+  jmp  FspCheckFfsHeader\r
+\r
+FspFvExtHeaderExist:\r
+  add  edi, eax\r
+  mov  eax, dword ptr [edi + FVH_EXTHEADER_SIZE_OFFSET]  ; Bypass Ext Fv Header\r
+  add  edi, eax\r
+\r
+  ; Round up to 8 byte alignment\r
+  mov  eax, edi\r
+  and  al,  07h\r
+  jz FspCheckFfsHeader\r
+\r
+  and  edi, 0FFFFFFF8h\r
+  add  edi, 08h\r
+\r
+FspCheckFfsHeader:\r
+  ; Check the ffs guid\r
+  mov  eax, dword ptr [edi]\r
+  cmp  eax, FSP_HEADER_GUID_DWORD1\r
+  jnz FspHeaderNotFound\r
+\r
+  mov  eax, dword ptr [edi + 4]\r
+  cmp  eax, FSP_HEADER_GUID_DWORD2\r
+  jnz FspHeaderNotFound\r
+\r
+  mov  eax, dword ptr [edi + 8]\r
+  cmp  eax, FSP_HEADER_GUID_DWORD3\r
+  jnz FspHeaderNotFound\r
+\r
+  mov  eax, dword ptr [edi + 0Ch]\r
+  cmp  eax, FSP_HEADER_GUID_DWORD4\r
+  jnz FspHeaderNotFound\r
+\r
+  add  edi, FFS_HEADER_SIZE_VALUE       ; Bypass the ffs header\r
+\r
+  ; Check the section type as raw section\r
+  mov  al, byte ptr [edi + SECTION_HEADER_TYPE_OFFSET]\r
+  cmp  al, 019h\r
+  jnz FspHeaderNotFound\r
+\r
+  add  edi, RAW_SECTION_HEADER_SIZE_VALUE ; Bypass the section header\r
+  jmp FspHeaderFound\r
+\r
+FspHeaderNotFound:\r
+  jmp  $\r
+\r
+FspHeaderFound:\r
+  ; Get the fsp TempRamInit Api address\r
+  mov eax, dword ptr [edi + FSP_HEADER_IMAGEBASE_OFFSET]\r
+  add eax, dword ptr [edi + FSP_HEADER_TEMPRAMINIT_OFFSET]\r
+\r
+  ; Setup the hardcode stack\r
+  mov esp, OFFSET TempRamInitStack\r
+\r
+  ; Call the fsp TempRamInit Api\r
+  jmp eax\r
+\r
+TempRamInitDone:\r
+  cmp eax, 0\r
+  jnz FspApiFailed\r
+\r
+  ;   ECX: start of range\r
+  ;   EDX: end of range\r
+  mov     esp, edx\r
+  push    edx\r
+  push    ecx\r
+  push    eax ; zero - no hob list yet\r
+  call CallPeiCoreEntryPoint\r
+\r
+FspApiFailed:\r
+  jmp $\r
+\r
+align 10h\r
+TempRamInitStack:\r
+    DD  OFFSET TempRamInitDone\r
+    DD  OFFSET TempRamInitParams\r
+\r
+ProtectedModeEntryPoint ENDP\r
+\r
+;\r
+; ROM-based Global-Descriptor Table for the Tiano PEI Phase\r
+;\r
+align 16\r
+PUBLIC  BootGdtTable\r
+\r
+;\r
+; GDT[0]: 0x00: Null entry, never used.\r
+;\r
+NULL_SEL            EQU $ - GDT_BASE    ; Selector [0]\r
+GDT_BASE:\r
+BootGdtTable        DD  0\r
+                    DD  0\r
+;\r
+; Linear data segment descriptor\r
+;\r
+LINEAR_SEL          EQU $ - GDT_BASE    ; Selector [0x8]\r
+    DW  0FFFFh                          ; limit 0xFFFFF\r
+    DW  0                               ; base 0\r
+    DB  0\r
+    DB  092h                            ; present, ring 0, data, expand-up, writable\r
+    DB  0CFh                            ; page-granular, 32-bit\r
+    DB  0\r
+;\r
+; Linear code segment descriptor\r
+;\r
+LINEAR_CODE_SEL     EQU $ - GDT_BASE    ; Selector [0x10]\r
+    DW  0FFFFh                          ; limit 0xFFFFF\r
+    DW  0                               ; base 0\r
+    DB  0\r
+    DB  09Bh                            ; present, ring 0, data, expand-up, not-writable\r
+    DB  0CFh                            ; page-granular, 32-bit\r
+    DB  0\r
+;\r
+; System data segment descriptor\r
+;\r
+SYS_DATA_SEL        EQU $ - GDT_BASE    ; Selector [0x18]\r
+    DW  0FFFFh                          ; limit 0xFFFFF\r
+    DW  0                               ; base 0\r
+    DB  0\r
+    DB  093h                            ; present, ring 0, data, expand-up, not-writable\r
+    DB  0CFh                            ; page-granular, 32-bit\r
+    DB  0\r
+\r
+;\r
+; System code segment descriptor\r
+;\r
+SYS_CODE_SEL        EQU $ - GDT_BASE    ; Selector [0x20]\r
+    DW  0FFFFh                          ; limit 0xFFFFF\r
+    DW  0                               ; base 0\r
+    DB  0\r
+    DB  09Ah                            ; present, ring 0, data, expand-up, writable\r
+    DB  0CFh                            ; page-granular, 32-bit\r
+    DB  0\r
+;\r
+; Spare segment descriptor\r
+;\r
+SYS16_CODE_SEL      EQU $ - GDT_BASE    ; Selector [0x28]\r
+    DW  0FFFFh                          ; limit 0xFFFFF\r
+    DW  0                               ; base 0\r
+    DB  0Eh                             ; Changed from F000 to E000.\r
+    DB  09Bh                            ; present, ring 0, code, expand-up, writable\r
+    DB  00h                             ; byte-granular, 16-bit\r
+    DB  0\r
+;\r
+; Spare segment descriptor\r
+;\r
+SYS16_DATA_SEL      EQU $ - GDT_BASE    ; Selector [0x30]\r
+    DW  0FFFFh                          ; limit 0xFFFF\r
+    DW  0                               ; base 0\r
+    DB  0\r
+    DB  093h                            ; present, ring 0, data, expand-up, not-writable\r
+    DB  00h                             ; byte-granular, 16-bit\r
+    DB  0\r
+\r
+;\r
+; Spare segment descriptor\r
+;\r
+SPARE5_SEL          EQU $ - GDT_BASE    ; Selector [0x38]\r
+    DW  0                               ; limit 0\r
+    DW  0                               ; base 0\r
+    DB  0\r
+    DB  0                               ; present, ring 0, data, expand-up, writable\r
+    DB  0                               ; page-granular, 32-bit\r
+    DB  0\r
+GDT_SIZE            EQU $ - BootGdtTable    ; Size, in bytes\r
+\r
+;\r
+; GDT Descriptor\r
+;\r
+GdtDesc:                                ; GDT descriptor\r
+    DW  GDT_SIZE - 1                    ; GDT limit\r
+    DD  OFFSET BootGdtTable             ; GDT base address\r
+\r
+\r
+ProtectedModeEntryLinearAddress   LABEL   FWORD\r
+ProtectedModeEntryLinearOffset    LABEL   DWORD\r
+  DD      OFFSET ProtectedModeEntryPoint  ; Offset of our 32 bit code\r
+  DW      LINEAR_CODE_SEL\r
+\r
+_TEXT_PROTECTED_MODE    ENDS\r
+END\r

diff --git a/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecLibVlv2/Ia32/Stack.S b/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecLibVlv2/Ia32/Stack.S
new file mode 100644 (file)
index 0000000..950b3a1
--- /dev/null
+++ b/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecLibVlv2/Ia32/Stack.S
@@ -0,0 +1,77 @@
+#------------------------------------------------------------------------------\r
+#\r
+# Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>\r
+# This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution.  The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php.\r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+# Abstract:\r
+#\r
+#   Switch the stack from temporary memory to permenent memory.\r
+#\r
+#------------------------------------------------------------------------------\r
+\r
+\r
+#------------------------------------------------------------------------------\r
+# VOID\r
+# EFIAPI\r
+# SecSwitchStack (\r
+#   UINT32   TemporaryMemoryBase,\r
+#   UINT32   PermenentMemoryBase\r
+#   )#\r
+#------------------------------------------------------------------------------\r
+ASM_GLOBAL ASM_PFX (SecSwitchStack)\r
+ASM_PFX(SecSwitchStack):\r
+    #\r
+    # Save standard registers so they can be used to change stack\r
+    #\r
+    pushl %eax\r
+    pushl %ebx\r
+    pushl %ecx\r
+    pushl %edx\r
+\r
+    #\r
+    # !!CAUTION!! this function address's is pushed into stack after\r
+    # migration of whole temporary memory, so need save it to permenent\r
+    # memory at first!\r
+    #\r
+    movl  20(%esp), %ebx         # Save the first parameter\r
+    movl  24(%esp), %ecx         # Save the second parameter\r
+\r
+    #\r
+    # Save this function's return address into permenent memory at first.\r
+    # Then, Fixup the esp point to permenent memory\r
+    #\r
+    movl  %esp, %eax\r
+    subl  %ebx, %eax\r
+    addl  %ecx, %eax\r
+    movl  0(%esp), %edx          # copy pushed register's value to permenent memory\r
+    movl  %edx, 0(%eax)\r
+    movl  4(%esp), %edx\r
+    movl  %edx, 4(%eax)\r
+    movl  8(%esp), %edx\r
+    movl  %edx, 8(%eax)\r
+    movl  12(%esp), %edx\r
+    movl  %edx, 12(%eax)\r
+    movl  16(%esp), %edx        # Update this function's return address into permenent memory\r
+    movl  %edx, 16(%eax)\r
+    movl  %eax, %esp            # From now, esp is pointed to permenent memory\r
+\r
+    #\r
+    # Fixup the ebp point to permenent memory\r
+    #\r
+    movl  %ebp, %eax\r
+    subl  %ebx, %eax\r
+    addl  %ecx, %eax\r
+    movl  %eax, %ebp            # From now, ebp is pointed to permenent memory\r
+\r
+    popl  %edx\r
+    popl  %ecx\r
+    popl  %ebx\r
+    popl  %eax\r
+    ret\r
+\r

diff --git a/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecLibVlv2/Ia32/Stack.asm b/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecLibVlv2/Ia32/Stack.asm
new file mode 100644 (file)
index 0000000..f96a55f
--- /dev/null
+++ b/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecLibVlv2/Ia32/Stack.asm
@@ -0,0 +1,82 @@
+;------------------------------------------------------------------------------\r
+;\r
+; Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>\r
+; This program and the accompanying materials\r
+; are licensed and made available under the terms and conditions of the BSD License\r
+; which accompanies this distribution.  The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php.\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+; Abstract:\r
+;\r
+;   Switch the stack from temporary memory to permenent memory.\r
+;\r
+;------------------------------------------------------------------------------\r
+\r
+    .586p\r
+    .model  flat,C\r
+    .code\r
+\r
+;------------------------------------------------------------------------------\r
+; VOID\r
+; EFIAPI\r
+; SecSwitchStack (\r
+;   UINT32   TemporaryMemoryBase,\r
+;   UINT32   PermenentMemoryBase\r
+;   );\r
+;------------------------------------------------------------------------------\r
+SecSwitchStack   PROC\r
+    ;\r
+    ; Save three register: eax, ebx, ecx\r
+    ;\r
+    push  eax\r
+    push  ebx\r
+    push  ecx\r
+    push  edx\r
+\r
+    ;\r
+    ; !!CAUTION!! this function address's is pushed into stack after\r
+    ; migration of whole temporary memory, so need save it to permenent\r
+    ; memory at first!\r
+    ;\r
+\r
+    mov   ebx, [esp + 20]          ; Save the first parameter\r
+    mov   ecx, [esp + 24]          ; Save the second parameter\r
+\r
+    ;\r
+    ; Save this function's return address into permenent memory at first.\r
+    ; Then, Fixup the esp point to permenent memory\r
+    ;\r
+    mov   eax, esp\r
+    sub   eax, ebx\r
+    add   eax, ecx\r
+    mov   edx, dword ptr [esp]         ; copy pushed register's value to permenent memory\r
+    mov   dword ptr [eax], edx\r
+    mov   edx, dword ptr [esp + 4]\r
+    mov   dword ptr [eax + 4], edx\r
+    mov   edx, dword ptr [esp + 8]\r
+    mov   dword ptr [eax + 8], edx\r
+    mov   edx, dword ptr [esp + 12]\r
+    mov   dword ptr [eax + 12], edx\r
+    mov   edx, dword ptr [esp + 16]    ; Update this function's return address into permenent memory\r
+    mov   dword ptr [eax + 16], edx\r
+    mov   esp, eax                     ; From now, esp is pointed to permenent memory\r
+\r
+    ;\r
+    ; Fixup the ebp point to permenent memory\r
+    ;\r
+    mov   eax, ebp\r
+    sub   eax, ebx\r
+    add   eax, ecx\r
+    mov   ebp, eax                ; From now, ebp is pointed to permenent memory\r
+\r
+    pop   edx\r
+    pop   ecx\r
+    pop   ebx\r
+    pop   eax\r
+    ret\r
+SecSwitchStack   ENDP\r
+\r
+    END\r

diff --git a/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecLibVlv2/PlatformInit.c b/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecLibVlv2/PlatformInit.c
new file mode 100644 (file)
index 0000000..2e181ac
--- /dev/null
+++ b/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecLibVlv2/PlatformInit.c
@@ -0,0 +1,42 @@
+/** @file\r
+  This PEIM will parse the hoblist from fsp and report them into pei core.\r
+  This file contains the main entrypoint of the PEIM.\r
+\r
+  Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>\r
+  This program and the accompanying materials\r
+  are licensed and made available under the terms and conditions of the BSD License\r
+  which accompanies this distribution.  The full text of the license may be found at\r
+  http://opensource.org/licenses/bsd-license.php.\r
+\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+\r
+#include <PiPei.h>\r
+#include <Library\DebugLib.h>\r
+#include <Library\SerialPortLib.h>\r
+\r
+VOID EnableInternalUart ();\r
+\r
+VOID\r
+EFIAPI\r
+PlatformInit (\r
+  IN VOID                 *FspHobList,\r
+  IN VOID                 *StartOfRange,\r
+  IN VOID                 *EndOfRange\r
+  )\r
+{\r
+  //\r
+  // Platform initialization\r
+  // Enable Serial port here\r
+  //\r
+  EnableInternalUart ();\r
+  SerialPortInitialize ();\r
+\r
+  DEBUG ((DEBUG_INFO, "PlatformInit\n"));\r
+  DEBUG ((DEBUG_INFO, "FspHobList - 0x%x\n", FspHobList));\r
+  DEBUG ((DEBUG_INFO, "StartOfRange - 0x%x\n", StartOfRange));\r
+  DEBUG ((DEBUG_INFO, "EndOfRange - 0x%x\n", EndOfRange));\r
+}\r

diff --git a/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecLibVlv2/SaveSecContext.c b/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecLibVlv2/SaveSecContext.c
new file mode 100644 (file)
index 0000000..6f84f50
--- /dev/null
+++ b/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecLibVlv2/SaveSecContext.c
@@ -0,0 +1,114 @@
+/** @file\r
+  This PEIM will parse the hoblist from fsp and report them into pei core.\r
+  This file contains the main entrypoint of the PEIM.\r
+\r
+  Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>\r
+  This program and the accompanying materials\r
+  are licensed and made available under the terms and conditions of the BSD License\r
+  which accompanies this distribution.  The full text of the license may be found at\r
+  http://opensource.org/licenses/bsd-license.php.\r
+\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+\r
+#include <PiPei.h>\r
+#include <Library/DebugLib.h>\r
+\r
+#include <Ppi/TopOfTemporaryRam.h>\r
+#include <Ppi/SecPlatformInformation.h>\r
+\r
+/**\r
+  Save BIST value before call FspInit.\r
+\r
+  @param Bist   BIST value.\r
+**/\r
+VOID\r
+AsmSaveBistValue (\r
+  IN UINT32  Bist\r
+  );\r
+\r
+/**\r
+  Save Ticker value before call FspInit.\r
+\r
+  @param Ticker   Ticker value.\r
+**/\r
+VOID\r
+AsmSaveTickerValue (\r
+  IN UINT64  Ticker\r
+  );\r
+\r
+/**\r
+  Save SEC context before call FspInit.\r
+\r
+  @param PeiServices  Pointer to PEI Services Table.\r
+**/\r
+VOID\r
+EFIAPI\r
+SaveSecContext (\r
+  IN CONST EFI_PEI_SERVICES                     **PeiServices\r
+  )\r
+{\r
+  UINT32      *Bist;\r
+  UINT64      *Ticker;\r
+  UINT32      Size;\r
+  UINT32      Count;\r
+  UINT32      TopOfTemporaryRam;\r
+  VOID        *TopOfTemporaryRamPpi;\r
+  EFI_STATUS  Status;\r
+\r
+  DEBUG ((DEBUG_INFO, "SaveSecContext - 0x%x\n", PeiServices));\r
+\r
+  Status = (*PeiServices)->LocatePpi (\r
+                             PeiServices,\r
+                             &gTopOfTemporaryRamPpiGuid,\r
+                             0,\r
+                             NULL,\r
+                             (VOID **) &TopOfTemporaryRamPpi\r
+                             );\r
+  if (EFI_ERROR (Status)) {\r
+    return ;\r
+  }\r
+\r
+  DEBUG ((DEBUG_INFO, "TopOfTemporaryRamPpi - 0x%x\n", TopOfTemporaryRamPpi));\r
+\r
+  //\r
+  // The entries of BIST information, together with the number of them,\r
+  // reside in the bottom of stack, left untouched by normal stack operation.\r
+  // This routine copies the BIST information to the buffer pointed by\r
+  // PlatformInformationRecord for output.\r
+  //\r
+  // |--------------| <- TopOfTemporaryRam\r
+  // |Number of BSPs|\r
+  // |--------------|\r
+  // |     BIST     |\r
+  // |--------------|\r
+  // |     ....     |\r
+  // |--------------|\r
+  // |  TSC[63:32]  |\r
+  // |--------------|\r
+  // |  TSC[31:00]  |\r
+  // |--------------|\r
+  //\r
+\r
+  TopOfTemporaryRam = (UINT32)(UINTN)TopOfTemporaryRamPpi - sizeof(UINT32);\r
+  TopOfTemporaryRam -= sizeof(UINT32) * 2;\r
+  DEBUG ((DEBUG_INFO, "TopOfTemporaryRam - 0x%x\n", TopOfTemporaryRam));\r
+  Count             = *(UINT32 *)(UINTN)(TopOfTemporaryRam - sizeof(UINT32));\r
+  DEBUG ((DEBUG_INFO, "Count - 0x%x\n", Count));\r
+  Size              = Count * sizeof (IA32_HANDOFF_STATUS);\r
+  DEBUG ((DEBUG_INFO, "Size - 0x%x\n", Size));\r
+\r
+  Bist   = (UINT32 *)(UINTN)(TopOfTemporaryRam - sizeof(UINT32) - Size);\r
+  DEBUG ((DEBUG_INFO, "Bist - 0x%x\n", *Bist));\r
+  Ticker = (UINT64 *)(UINTN)(TopOfTemporaryRam - sizeof(UINT32) - Size - sizeof(UINT64));\r
+  DEBUG ((DEBUG_INFO, "Ticker - 0x%lx\n", *Ticker));\r
+\r
+  //\r
+  // Just need record BSP\r
+  //\r
+  AsmSaveBistValue (*Bist);\r
+  AsmSaveTickerValue (*Ticker);\r
+}\r

diff --git a/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecLibVlv2/SecGetPerformance.c b/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecLibVlv2/SecGetPerformance.c
new file mode 100644 (file)
index 0000000..ce7a959
--- /dev/null
+++ b/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecLibVlv2/SecGetPerformance.c
@@ -0,0 +1,89 @@
+/** @file\r
+\r
+  Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>\r
+  This program and the accompanying materials\r
+  are licensed and made available under the terms and conditions of the BSD License\r
+  which accompanies this distribution.  The full text of the license may be found at\r
+  http://opensource.org/licenses/bsd-license.php.\r
+\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#include <PiPei.h>\r
+\r
+#include <Ppi/SecPerformance.h>\r
+#include <Ppi/TopOfTemporaryRam.h>\r
+\r
+#include <Library/BaseMemoryLib.h>\r
+#include <Library/TimerLib.h>\r
+#include <Library/DebugLib.h>\r
+\r
+/**\r
+  This interface conveys performance information out of the Security (SEC) phase into PEI.\r
+\r
+  This service is published by the SEC phase. The SEC phase handoff has an optional\r
+  EFI_PEI_PPI_DESCRIPTOR list as its final argument when control is passed from SEC into the\r
+  PEI Foundation. As such, if the platform supports collecting performance data in SEC,\r
+  this information is encapsulated into the data structure abstracted by this service.\r
+  This information is collected for the boot-strap processor (BSP) on IA-32.\r
+\r
+  @param[in]  PeiServices  The pointer to the PEI Services Table.\r
+  @param[in]  This         The pointer to this instance of the PEI_SEC_PERFORMANCE_PPI.\r
+  @param[out] Performance  The pointer to performance data collected in SEC phase.\r
+\r
+  @retval EFI_SUCCESS  The data was successfully returned.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+SecGetPerformance (\r
+  IN CONST EFI_PEI_SERVICES          **PeiServices,\r
+  IN       PEI_SEC_PERFORMANCE_PPI   *This,\r
+  OUT      FIRMWARE_SEC_PERFORMANCE  *Performance\r
+  )\r
+{\r
+  UINT32      Size;\r
+  UINT32      Count;\r
+  UINT32      TopOfTemporaryRam;\r
+  UINT64      Ticker;\r
+  VOID        *TopOfTemporaryRamPpi;\r
+  EFI_STATUS  Status;\r
+\r
+  DEBUG ((DEBUG_INFO, "SecGetPerformance\n"));\r
+\r
+  Status = (*PeiServices)->LocatePpi (\r
+                             PeiServices,\r
+                             &gTopOfTemporaryRamPpiGuid,\r
+                             0,\r
+                             NULL,\r
+                             (VOID **) &TopOfTemporaryRamPpi\r
+                             );\r
+  if (EFI_ERROR (Status)) {\r
+    return EFI_NOT_FOUND;\r
+  }\r
+\r
+  //\r
+  // |--------------| <- TopOfTemporaryRam\r
+  // |Number of BSPs|\r
+  // |--------------|\r
+  // |     BIST     |\r
+  // |--------------|\r
+  // |     ....     |\r
+  // |--------------|\r
+  // |  TSC[63:32]  |\r
+  // |--------------|\r
+  // |  TSC[31:00]  |\r
+  // |--------------|\r
+  //\r
+  TopOfTemporaryRam = (UINT32)(UINTN)TopOfTemporaryRamPpi - sizeof(UINT32);\r
+  TopOfTemporaryRam -= sizeof(UINT32) * 2;\r
+  Count             = *(UINT32 *) (UINTN) (TopOfTemporaryRam - sizeof (UINT32));\r
+  Size              = Count * sizeof (UINT64);\r
+\r
+  Ticker = *(UINT64 *) (UINTN) (TopOfTemporaryRam - sizeof (UINT32) - Size - sizeof (UINT32) * 2);\r
+  Performance->ResetEnd = GetTimeInNanoSecond (Ticker);\r
+\r
+  return EFI_SUCCESS;\r
+}\r

diff --git a/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecLibVlv2/SecPlatformInformation.c b/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecLibVlv2/SecPlatformInformation.c
new file mode 100644 (file)
index 0000000..50e5cb2
--- /dev/null
+++ b/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecLibVlv2/SecPlatformInformation.c
@@ -0,0 +1,83 @@
+/** @file\r
+\r
+  Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>\r
+  This program and the accompanying materials are licensed and\r
+  made available under the terms and conditions of the BSD License\r
+  which accompanies this distribution.  The full text of the license may be found at\r
+  http://opensource.org/licenses/bsd-license.php.\r
+\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#include <PiPei.h>\r
+\r
+#include <Ppi/SecPlatformInformation.h>\r
+#include <Ppi/TopOfTemporaryRam.h>\r
+\r
+#include <Library/BaseMemoryLib.h>\r
+#include <Library/DebugLib.h>\r
+\r
+/**\r
+  This interface conveys state information out of the Security (SEC) phase into PEI.\r
+\r
+  @param  PeiServices               Pointer to the PEI Services Table.\r
+  @param  StructureSize             Pointer to the variable describing size of the input buffer.\r
+  @param  PlatformInformationRecord Pointer to the EFI_SEC_PLATFORM_INFORMATION_RECORD.\r
+\r
+  @retval EFI_SUCCESS           The data was successfully returned.\r
+  @retval EFI_BUFFER_TOO_SMALL  The buffer was too small.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+SecPlatformInformation (\r
+  IN CONST EFI_PEI_SERVICES                     **PeiServices,\r
+  IN OUT   UINT64                               *StructureSize,\r
+     OUT   EFI_SEC_PLATFORM_INFORMATION_RECORD  *PlatformInformationRecord\r
+  )\r
+{\r
+  UINT32      *Bist;\r
+  UINT32      Size;\r
+  UINT32      Count;\r
+  UINT32      TopOfTemporaryRam;\r
+  VOID        *TopOfTemporaryRamPpi;\r
+  EFI_STATUS  Status;\r
+\r
+  DEBUG ((DEBUG_INFO, "SecPlatformInformation\n"));\r
+\r
+  Status = (*PeiServices)->LocatePpi (\r
+                             PeiServices,\r
+                             &gTopOfTemporaryRamPpiGuid,\r
+                             0,\r
+                             NULL,\r
+                             (VOID **) &TopOfTemporaryRamPpi\r
+                             );\r
+  if (EFI_ERROR (Status)) {\r
+    return EFI_NOT_FOUND;\r
+  }\r
+\r
+  //\r
+  // The entries of BIST information, together with the number of them,\r
+  // reside in the bottom of stack, left untouched by normal stack operation.\r
+  // This routine copies the BIST information to the buffer pointed by\r
+  // PlatformInformationRecord for output.\r
+  //\r
+  TopOfTemporaryRam = (UINT32)(UINTN)TopOfTemporaryRamPpi - sizeof (UINT32);\r
+  TopOfTemporaryRam -= sizeof(UINT32) * 2;\r
+  Count             = *((UINT32 *)(UINTN) (TopOfTemporaryRam - sizeof (UINT32)));\r
+  Size              = Count * sizeof (IA32_HANDOFF_STATUS);\r
+\r
+  if ((*StructureSize) < (UINT64) Size) {\r
+    *StructureSize = Size;\r
+    return EFI_BUFFER_TOO_SMALL;\r
+  }\r
+\r
+  *StructureSize  = Size;\r
+  Bist            = (UINT32 *) (TopOfTemporaryRam - sizeof (UINT32) - Size);\r
+\r
+  CopyMem (PlatformInformationRecord, Bist, Size);\r
+\r
+  return EFI_SUCCESS;\r
+}\r

diff --git a/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecLibVlv2/SecRamInitData.c b/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecLibVlv2/SecRamInitData.c
new file mode 100644 (file)
index 0000000..392bd21
--- /dev/null
+++ b/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecLibVlv2/SecRamInitData.c
@@ -0,0 +1,22 @@
+/** @file\r
+  Calling Fsp Apis in SEC\r
+\r
+  Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>\r
+  This program and the accompanying materials are licensed and made\r
+  available under the terms and conditions of the BSD License\r
+  which accompanies this distribution.  The full text of the license may be found at\r
+  http://opensource.org/licenses/bsd-license.php.\r
+\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#include <Library/PcdLib.h>\r
+\r
+GLOBAL_REMOVE_IF_UNREFERENCED CONST UINT32 TempRamInitParams[4] = {\r
+  ((UINT32)FixedPcdGet64 (PcdCpuMicrocodePatchAddress) + FixedPcdGet32 (PcdFlashMicroCodeOffset)),\r
+  ((UINT32)FixedPcdGet64 (PcdCpuMicrocodePatchRegionSize) - FixedPcdGet32 (PcdFlashMicroCodeOffset)),\r
+  FixedPcdGet32 (PcdFlashCodeCacheAddress),\r
+  FixedPcdGet32 (PcdFlashCodeCacheSize)\r
+};\r

diff --git a/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecLibVlv2/SecTempRamSupport.c b/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecLibVlv2/SecTempRamSupport.c
new file mode 100644 (file)
index 0000000..e505d71
--- /dev/null
+++ b/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecLibVlv2/SecTempRamSupport.c
@@ -0,0 +1,155 @@
+/** @file\r
+  C functions in SEC\r
+\r
+  Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>\r
+  This program and the accompanying materials are licensed and made\r
+  available under the terms and conditions of the BSD License\r
+  which accompanies this distribution.  The full text of the license may be found at\r
+  http://opensource.org/licenses/bsd-license.php.\r
+\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#include <PiPei.h>\r
+\r
+#include <Ppi/TemporaryRamSupport.h>\r
+\r
+#include <Library/BaseMemoryLib.h>\r
+#include <Library/DebugLib.h>\r
+#include <Library/PcdLib.h>\r
+#include <Library/DebugAgentLib.h>\r
+\r
+/**\r
+  Switch the stack in the temporary memory to the one in the permanent memory.\r
+\r
+  This function must be invoked after the memory migration immediately. The relative\r
+  position of the stack in the temporary and permanent memory is same.\r
+\r
+  @param TemporaryMemoryBase  Base address of the temporary memory.\r
+  @param PermenentMemoryBase  Base address of the permanent memory.\r
+**/\r
+VOID\r
+EFIAPI\r
+SecSwitchStack (\r
+  UINT32   TemporaryMemoryBase,\r
+  UINT32   PermenentMemoryBase\r
+  );\r
+\r
+/**\r
+  This service of the TEMPORARY_RAM_SUPPORT_PPI that migrates temporary RAM into\r
+  permanent memory.\r
+\r
+  @param PeiServices            Pointer to the PEI Services Table.\r
+  @param TemporaryMemoryBase    Source Address in temporary memory from which the SEC or PEIM will copy the\r
+                                Temporary RAM contents.\r
+  @param PermanentMemoryBase    Destination Address in permanent memory into which the SEC or PEIM will copy the\r
+                                Temporary RAM contents.\r
+  @param CopySize               Amount of memory to migrate from temporary to permanent memory.\r
+\r
+  @retval EFI_SUCCESS           The data was successfully returned.\r
+  @retval EFI_INVALID_PARAMETER PermanentMemoryBase + CopySize > TemporaryMemoryBase when\r
+                                TemporaryMemoryBase > PermanentMemoryBase.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+SecTemporaryRamSupport (\r
+  IN CONST EFI_PEI_SERVICES   **PeiServices,\r
+  IN EFI_PHYSICAL_ADDRESS     TemporaryMemoryBase,\r
+  IN EFI_PHYSICAL_ADDRESS     PermanentMemoryBase,\r
+  IN UINTN                    CopySize\r
+  )\r
+{\r
+  IA32_DESCRIPTOR   IdtDescriptor;\r
+  VOID*             OldHeap;\r
+  VOID*             NewHeap;\r
+  VOID*             OldStack;\r
+  VOID*             NewStack;\r
+  DEBUG_AGENT_CONTEXT_POSTMEM_SEC  DebugAgentContext;\r
+  BOOLEAN           OldStatus;\r
+  UINTN             PeiStackSize;\r
+\r
+  PeiStackSize = (UINTN)PcdGet32 (PcdPeiTemporaryRamStackSize);\r
+  if (PeiStackSize == 0) {\r
+    PeiStackSize = (CopySize >> 1);\r
+  }\r
+\r
+  ASSERT (PeiStackSize < CopySize);\r
+\r
+  //\r
+  // |-------------------|---->\r
+  // |      Stack        |    PeiStackSize\r
+  // |-------------------|---->\r
+  // |      Heap         |    PeiTemporayRamSize\r
+  // |-------------------|---->  TempRamBase\r
+  //\r
+  // |-------------------|---->\r
+  // |      Heap         |    PeiTemporayRamSize\r
+  // |-------------------|---->\r
+  // |      Stack        |    PeiStackSize\r
+  // |-------------------|---->  PermanentMemoryBase\r
+  //\r
+\r
+  OldHeap = (VOID*)(UINTN)TemporaryMemoryBase;\r
+  NewHeap = (VOID*)((UINTN)PermanentMemoryBase + PeiStackSize);\r
+\r
+  OldStack = (VOID*)((UINTN)TemporaryMemoryBase + CopySize - PeiStackSize);\r
+  NewStack = (VOID*)(UINTN)PermanentMemoryBase;\r
+\r
+  DebugAgentContext.HeapMigrateOffset = (UINTN)NewHeap - (UINTN)OldHeap;\r
+  DebugAgentContext.StackMigrateOffset = (UINTN)NewStack - (UINTN)OldStack;\r
+\r
+  OldStatus = SaveAndSetDebugTimerInterrupt (FALSE);\r
+\r
+  //\r
+  // Initialize Debug Agent to support source level debug in PEI phase after memory ready.\r
+  // It will build HOB and fix up the pointer in IDT table.\r
+  //\r
+  InitializeDebugAgent (DEBUG_AGENT_INIT_POSTMEM_SEC, (VOID *) &DebugAgentContext, NULL);\r
+\r
+  //\r
+  // Migrate Heap\r
+  //\r
+  CopyMem (NewHeap, OldHeap, CopySize - PeiStackSize);\r
+\r
+  //\r
+  // Migrate Stack\r
+  //\r
+  CopyMem (NewStack, OldStack, PeiStackSize);\r
+\r
+\r
+  //\r
+  // We need *not* fix the return address because currently,\r
+  // The PeiCore is executed in flash.\r
+  //\r
+\r
+  //\r
+  // Rebase IDT table in permanent memory\r
+  //\r
+  AsmReadIdtr (&IdtDescriptor);\r
+  IdtDescriptor.Base = IdtDescriptor.Base - (UINTN)OldStack + (UINTN)NewStack;\r
+\r
+  AsmWriteIdtr (&IdtDescriptor);\r
+\r
+\r
+  //\r
+  // Program MTRR\r
+  //\r
+\r
+  //\r
+  // SecSwitchStack function must be invoked after the memory migration\r
+  // immediatly, also we need fixup the stack change caused by new call into\r
+  // permenent memory.\r
+  //\r
+  SecSwitchStack (\r
+    (UINT32) (UINTN) OldStack,\r
+    (UINT32) (UINTN) NewStack\r
+    );\r
+\r
+  SaveAndSetDebugTimerInterrupt (OldStatus);\r
+\r
+  return EFI_SUCCESS;\r
+}\r
+\r

diff --git a/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecLibVlv2/UartInit.c b/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecLibVlv2/UartInit.c
new file mode 100644 (file)
index 0000000..4255ad3
--- /dev/null
+++ b/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecLibVlv2/UartInit.c
@@ -0,0 +1,198 @@
+/** @file\r
+  This PEIM will parse the hoblist from fsp and report them into pei core.\r
+  This file contains the main entrypoint of the PEIM.\r
+\r
+  Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>\r
+  This program and the accompanying materials\r
+  are licensed and made available under the terms and conditions of the BSD License\r
+  which accompanies this distribution.  The full text of the license may be found at\r
+  http://opensource.org/licenses/bsd-license.php.\r
+\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+\r
+#include <PiPei.h>\r
+#include <Library\IoLib.h>\r
+#include <Library\SerialPortLib.h>\r
+\r
+#define PCI_IDX        0xCF8\r
+#define PCI_DAT        0xCFC\r
+\r
+#define PCI_LPC_BASE    (0x8000F800)\r
+#define PCI_LPC_REG(x)  (PCI_LPC_BASE + (x))\r
+\r
+#define PMC_BASE_ADDRESS                  0xFED03000    // PMC Memory Base Address\r
+#define R_PCH_LPC_PMC_BASE                        0x44  // PBASE, 32bit, 512 Bytes\r
+#define B_PCH_LPC_PMC_BASE_EN                     BIT1  // Enable Bit\r
+#define R_PCH_PMC_GEN_PMCON_1                     0x20  // General PM Configuration 1\r
+#define B_PCH_PMC_GEN_PMCON_SUS_PWR_FLR           BIT14 // SUS Well Power Failure\r
+#define B_PCH_PMC_GEN_PMCON_PWROK_FLR             BIT16 // PWROK Failure\r
+\r
+#define R_PCH_LPC_UART_CTRL                       0x80  // UART Control\r
+#define B_PCH_LPC_UART_CTRL_COM1_EN               BIT0  // COM1 Enable\r
+\r
+#define ILB_BASE_ADDRESS                  0xFED08000    // ILB Memory Base Address\r
+#define R_PCH_ILB_IRQE                            0x88  // IRQ Enable Control\r
+\r
+#define IO_BASE_ADDRESS                   0xFED0C000    // IO Memory Base Address\r
+\r
+#define V_PCH_ILB_IRQE_UARTIRQEN_IRQ3             BIT3  // UART IRQ3 Enable\r
+#define V_PCH_ILB_IRQE_UARTIRQEN_IRQ4             BIT4  // UART IRQ4 Enable\r
+#define PCIEX_BASE_ADDRESS                        0xE0000000\r
+#define PCI_EXPRESS_BASE_ADDRESS                  PCIEX_BASE_ADDRESS\r
+#define PciD31F0RegBase                           PCIEX_BASE_ADDRESS + (UINT32) (31 << 15)\r
+#define SB_RCBA                                   0xfed1c000\r
+\r
+typedef enum {\r
+  PchA0         = 0,\r
+  PchA1         = 1,\r
+  PchB0         = 2,\r
+  PchB1         = 3,\r
+  PchB2         = 4,\r
+  PchB3         = 5,\r
+  PchC0         = 6,\r
+  PchSteppingMax\r
+} PCH_STEPPING;\r
+\r
+#define MmPciAddress( Segment, Bus, Device, Function, Register ) \\r
+  ( (UINTN)PCI_EXPRESS_BASE_ADDRESS + \\r
+    (UINTN)(Bus << 20) + \\r
+    (UINTN)(Device << 15) + \\r
+    (UINTN)(Function << 12) + \\r
+    (UINTN)(Register) \\r
+  )\r
+\r
+#define DEFAULT_PCI_BUS_NUMBER_PCH  0\r
+#define PCI_DEVICE_NUMBER_PCH_LPC                 31\r
+#define PCI_FUNCTION_NUMBER_PCH_LPC               0\r
+\r
+#define R_PCH_LPC_RID_CC                          0x08  // Revision ID & Class Code\r
+\r
+#define V_PCH_LPC_RID_0                           0x01  // A0 Stepping (17 x 17)\r
+#define V_PCH_LPC_RID_1                           0x02  // A0 Stepping (25 x 27)\r
+#define V_PCH_LPC_RID_2                           0x03  // A1 Stepping (17 x 17)\r
+#define V_PCH_LPC_RID_3                           0x04  // A1 Stepping (25 x 27)\r
+#define V_PCH_LPC_RID_4                           0x05  // B0 Stepping (17 x 17)\r
+#define V_PCH_LPC_RID_5                           0x06  // B0 Stepping (25 x 27)\r
+#define V_PCH_LPC_RID_6                           0x07  // B1 Stepping (17 x 17)\r
+#define V_PCH_LPC_RID_7                           0x08  // B1 Stepping (25 x 27)\r
+#define V_PCH_LPC_RID_8                           0x09  // B2 Stepping (17 x 17)\r
+#define V_PCH_LPC_RID_9                           0x0A  // B2 Stepping (25 x 27)\r
+#define V_PCH_LPC_RID_A                           0x0B  // B3 Stepping (17 x 17)\r
+#define V_PCH_LPC_RID_B                           0x0C  // B3 Stepping (25 x 27)\r
+#define V_PCH_LPC_RID_C                           0x0D  // C0 Stepping (17 x 17)\r
+#define V_PCH_LPC_RID_D                           0x0E  // C0 Stepping (25 x 27)\r
+\r
+/**\r
+  Return Pch stepping type\r
+\r
+  @param[in] None\r
+\r
+  @retval PCH_STEPPING            Pch stepping type\r
+\r
+**/\r
+PCH_STEPPING\r
+EFIAPI\r
+PchStepping (\r
+  VOID\r
+  )\r
+{\r
+  UINT8 RevId;\r
+\r
+  RevId = MmioRead8 (\r
+          MmPciAddress (0,\r
+            DEFAULT_PCI_BUS_NUMBER_PCH,\r
+            PCI_DEVICE_NUMBER_PCH_LPC,\r
+            PCI_FUNCTION_NUMBER_PCH_LPC,\r
+            R_PCH_LPC_RID_CC)\r
+          );\r
+\r
+  switch (RevId) {\r
+    case V_PCH_LPC_RID_0:\r
+    case V_PCH_LPC_RID_1:\r
+      return PchA0;\r
+      break;\r
+\r
+    case V_PCH_LPC_RID_2:\r
+    case V_PCH_LPC_RID_3:\r
+      return PchA1;\r
+      break;\r
+\r
+    case V_PCH_LPC_RID_4:\r
+    case V_PCH_LPC_RID_5:\r
+      return PchB0;\r
+      break;\r
+\r
+    case V_PCH_LPC_RID_6:\r
+    case V_PCH_LPC_RID_7:\r
+      return PchB1;\r
+      break;\r
+\r
+    case V_PCH_LPC_RID_8:\r
+    case V_PCH_LPC_RID_9:\r
+      return PchB2;\r
+      break;\r
+\r
+    case V_PCH_LPC_RID_A:\r
+    case V_PCH_LPC_RID_B:\r
+      return PchB3;\r
+      break;\r
+\r
+    case V_PCH_LPC_RID_C:\r
+    case V_PCH_LPC_RID_D:\r
+      return PchC0;\r
+      break;\r
+\r
+    default:\r
+      return PchSteppingMax;\r
+      break;\r
+\r
+  }\r
+}\r
+\r
+/**\r
+  Enable legacy decoding on ICH6\r
+\r
+ @param[in] none\r
+\r
+ @retval EFI_SUCCESS     Always returns success.\r
+\r
+**/\r
+VOID\r
+EnableInternalUart(\r
+  VOID\r
+  )\r
+{\r
+\r
+  //\r
+  // Program and enable PMC Base.\r
+  //\r
+  IoWrite32 (PCI_IDX,  PCI_LPC_REG(R_PCH_LPC_PMC_BASE));\r
+  IoWrite32 (PCI_DAT,  (PMC_BASE_ADDRESS | B_PCH_LPC_PMC_BASE_EN));\r
+\r
+  //\r
+  // Enable COM1 for debug message output.\r
+  //\r
+  MmioAndThenOr32 (PMC_BASE_ADDRESS + R_PCH_PMC_GEN_PMCON_1, (UINT32) (~(B_PCH_PMC_GEN_PMCON_SUS_PWR_FLR + B_PCH_PMC_GEN_PMCON_PWROK_FLR)), BIT24);\r
+\r
+  //\r
+  // Silicon Steppings\r
+  //\r
+  if (PchStepping()>= PchB0)\r
+    MmioOr8 (ILB_BASE_ADDRESS + R_PCH_ILB_IRQE, (UINT8) V_PCH_ILB_IRQE_UARTIRQEN_IRQ4);\r
+  else\r
+    MmioOr8 (ILB_BASE_ADDRESS + R_PCH_ILB_IRQE, (UINT8) V_PCH_ILB_IRQE_UARTIRQEN_IRQ3);\r
+  MmioAnd32(IO_BASE_ADDRESS + 0x0520, (UINT32)~(0x00000187));\r
+  MmioOr32 (IO_BASE_ADDRESS + 0x0520, (UINT32)0x81); // UART3_RXD-L\r
+  MmioAnd32(IO_BASE_ADDRESS + 0x0530, (UINT32)~(0x00000007));\r
+  MmioOr32 (IO_BASE_ADDRESS + 0x0530, (UINT32)0x1); // UART3_RXD-L\r
+  MmioOr8 (PciD31F0RegBase + R_PCH_LPC_UART_CTRL, (UINT8) B_PCH_LPC_UART_CTRL_COM1_EN);\r
+\r
+  SerialPortInitialize ();\r
+  SerialPortWrite ("EnableInternalUart!\r\n", sizeof("EnableInternalUart!\r\n") - 1);\r
+\r
+  return  ;\r
+}\r

diff --git a/Vlv2TbltDevicePkg/FvInfoPei/FvInfoPei.c b/Vlv2TbltDevicePkg/FvInfoPei/FvInfoPei.c
new file mode 100644 (file)
index 0000000..5d8aa80
--- /dev/null
+++ b/Vlv2TbltDevicePkg/FvInfoPei/FvInfoPei.c
@@ -0,0 +1,73 @@
+/** @file\r
+\r
+  Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+Module Name:\r
+\r
+    FvInfoPei.c\r
+\r
+Abstract:\r
+\r
+    EFI 2.0 PEIM to initialize the cache and program for unlock processor\r
+\r
+\r
+\r
+--*/\r
+\r
+#include <PiPei.h>\r
+#include <Guid/FirmwareFileSystem2.h>\r
+#include <Ppi/FirmwareVolumeInfo.h>\r
+#include <Library/PcdLib.h>\r
+#include <Library/DebugLib.h>\r
+\r
+EFI_PEI_FIRMWARE_VOLUME_INFO_PPI mAddtionFVPpi = {\r
+  EFI_FIRMWARE_FILE_SYSTEM2_GUID,\r
+  (VOID*)(UINTN)FixedPcdGet32(PcdFlashFvRecovery2Base),\r
+  FixedPcdGet32(PcdFlashFvRecovery2Size),\r
+  NULL,\r
+  NULL\r
+};\r
+\r
+EFI_PEI_PPI_DESCRIPTOR  mPpiList[] = {\r
+  (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),\r
+  &gEfiPeiFirmwareVolumeInfoPpiGuid,\r
+  &mAddtionFVPpi\r
+};\r
+\r
+\r
+/**\r
+  Add Recovery Fv Info to the Pei Core.\r
+\r
+  @param  PeiServices  General purpose services available to every PEIM.\r
+\r
+  @retval  Status\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+PeimInitializeFvInfo (\r
+  IN       EFI_PEI_FILE_HANDLE  FileHandle,\r
+  IN CONST EFI_PEI_SERVICES     **PeiServices\r
+  )\r
+\r
+//\r
+// GC_TODO:    FfsHeader - add argument and description to function comment\r
+//\r
+{\r
+  EFI_STATUS  Status;\r
+  Status = (**PeiServices).InstallPpi (PeiServices, &mPpiList[0]);\r
+  ASSERT_EFI_ERROR (Status);\r
+\r
+  DEBUG ((EFI_D_INFO, "\nFvInfo Add Fv Info\n"));\r
+\r
+  return Status;\r
+}\r

diff --git a/Vlv2TbltDevicePkg/FvInfoPei/FvInfoPei.inf b/Vlv2TbltDevicePkg/FvInfoPei/FvInfoPei.inf
new file mode 100644 (file)
index 0000000..bf0cc3c
--- /dev/null
+++ b/Vlv2TbltDevicePkg/FvInfoPei/FvInfoPei.inf
@@ -0,0 +1,54 @@
+#\r
+#\r
+# Copyright (c)  1999  - 2014, Intel Corporation. All rights reserved\r
+#                                                                                  \r\r
+# This program and the accompanying materials are licensed and made available under\r\r
+# the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+# The full text of the license may be found at                                     \r\r
+# http://opensource.org/licenses/bsd-license.php.                                  \r\r
+#                                                                                  \r\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+#                                                                                  \r\r
+#\r
+#\r
+#  Module Name:\r
+#\r
+#    CpuPeim.inf\r
+#\r
+#  Abstract:\r
+#\r
+#    Component description file for CPU module\r
+#\r
+#\r
+#--*/\r
+\r
+[defines]\r
+  INF_VERSION                    = 0x00010005\r
+  BASE_NAME                      = FvInfoPei\r
+  FILE_GUID                      = 64AAEAE0-92DF-4980-8668-6EB5EAAF4393\r
+  MODULE_TYPE                    = PEIM\r
+  VERSION_STRING                 = 1.0\r
+  ENTRY_POINT                    = PeimInitializeFvInfo\r
+\r
+[sources.common]\r
+  FvInfoPei.c\r
+\r
+[Packages]\r
+  MdePkg/MdePkg.dec\r
+  Vlv2TbltDevicePkg/PlatformPkg.dec\r
+\r
+[LibraryClasses]\r
+  PeimEntryPoint\r
+  DebugLib\r
+\r
+[Pcd.common]\r
+  gPlatformModuleTokenSpaceGuid.PcdFlashFvRecovery2Base\r
+  gPlatformModuleTokenSpaceGuid.PcdFlashFvRecovery2Size\r
+\r
+[Ppis]\r
+  gEfiPeiFirmwareVolumeInfoPpiGuid\r
+\r
+[Depex]\r
+  TRUE\r
+\r

diff --git a/Vlv2TbltDevicePkg/FvbRuntimeDxe/FvbInfo.c b/Vlv2TbltDevicePkg/FvbRuntimeDxe/FvbInfo.c
new file mode 100644 (file)
index 0000000..832e246
--- /dev/null
+++ b/Vlv2TbltDevicePkg/FvbRuntimeDxe/FvbInfo.c
@@ -0,0 +1,175 @@
+/**@file\r
+  Defines data structure that is the volume header found.\r
+  These data is intent to decouple FVB driver with FV header.\r
+\r
+Copyright (c) 2006  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+**/\r
+\r
+#include <PiDxe.h>\r
+#include <Protocol/FirmwareVolumeBlock.h>\r
+#include <Library/PcdLib.h>\r
+#include <Library/DebugLib.h>\r
+#include <Library/BaseLib.h>\r
+#include <Guid/FirmwareFileSystem2.h>\r
+#include <Guid/SystemNvDataGuid.h>\r
+\r
+#define FIRMWARE_BLOCK_SIZE         0x8000\r
+#define FVB_MEDIA_BLOCK_SIZE        (FIRMWARE_BLOCK_SIZE * 2)\r
+\r
+#define FV_RECOVERY_BASE_ADDRESS    FixedPcdGet32(PcdFlashFvRecoveryBase)\r
+#define RECOVERY_BIOS_BLOCK_NUM     (FixedPcdGet32(PcdFlashFvRecoverySize) / FVB_MEDIA_BLOCK_SIZE)\r
+\r
+#define FV_MAIN_BASE_ADDRESS        FixedPcdGet32(PcdFlashFvMainBase)\r
+#define MAIN_BIOS_BLOCK_NUM         (FixedPcdGet32(PcdFlashFvMainSize) / FVB_MEDIA_BLOCK_SIZE)\r
+\r
+#define NV_STORAGE_BASE_ADDRESS     FixedPcdGet32(PcdFlashNvStorageVariableBase)\r
+#define SYSTEM_NV_BLOCK_NUM         ((FixedPcdGet32(PcdFlashNvStorageVariableSize)+ FixedPcdGet32(PcdFlashNvStorageFtwWorkingSize) + FixedPcdGet32(PcdFlashNvStorageFtwSpareSize))/ FVB_MEDIA_BLOCK_SIZE)\r
+\r
+typedef struct {\r
+  EFI_PHYSICAL_ADDRESS        BaseAddress;\r
+  EFI_FIRMWARE_VOLUME_HEADER  FvbInfo;\r
+  EFI_FV_BLOCK_MAP_ENTRY      End[1];\r
+} EFI_FVB2_MEDIA_INFO;\r
+\r
+//\r
+// This data structure contains a template of all correct FV headers, which is used to restore\r
+// Fv header if it's corrupted.\r
+//\r
+EFI_FVB2_MEDIA_INFO mPlatformFvbMediaInfo[] = {\r
+  //\r
+  // Main BIOS FVB\r
+  //\r
+  {\r
+    FV_MAIN_BASE_ADDRESS,\r
+    {\r
+      {0,}, //ZeroVector[16]\r
+      EFI_FIRMWARE_FILE_SYSTEM2_GUID,\r
+      FVB_MEDIA_BLOCK_SIZE * MAIN_BIOS_BLOCK_NUM,\r
+      EFI_FVH_SIGNATURE,\r
+      0x0004feff, // check MdePkg/Include/Pi/PiFirmwareVolume.h for details on EFI_FVB_ATTRIBUTES_2\r
+      sizeof (EFI_FIRMWARE_VOLUME_HEADER) + sizeof (EFI_FV_BLOCK_MAP_ENTRY),\r
+      0,    //CheckSum which will be calucated dynamically.\r
+      0,    //ExtHeaderOffset\r
+      {0,}, //Reserved[1]\r
+      2,    //Revision\r
+      {\r
+        {\r
+          MAIN_BIOS_BLOCK_NUM,\r
+          FVB_MEDIA_BLOCK_SIZE,\r
+        }\r
+      }\r
+    },\r
+    {\r
+      {\r
+        0,\r
+        0\r
+      }\r
+    }\r
+  },\r
+\r
+  //\r
+  // Systen NvStorage FVB\r
+  //\r
+  {\r
+    NV_STORAGE_BASE_ADDRESS,\r
+    {\r
+      {0,}, //ZeroVector[16]\r
+      EFI_SYSTEM_NV_DATA_FV_GUID,\r
+      FVB_MEDIA_BLOCK_SIZE * SYSTEM_NV_BLOCK_NUM,\r
+      EFI_FVH_SIGNATURE,\r
+      0x0004feff, // check MdePkg/Include/Pi/PiFirmwareVolume.h for details on EFI_FVB_ATTRIBUTES_2\r
+      sizeof (EFI_FIRMWARE_VOLUME_HEADER) + sizeof (EFI_FV_BLOCK_MAP_ENTRY),\r
+      0,    //CheckSum which will be calucated dynamically.\r
+      0,    //ExtHeaderOffset\r
+      {0,}, //Reserved[1]\r
+      2,    //Revision\r
+      {\r
+        {\r
+          SYSTEM_NV_BLOCK_NUM,\r
+          FVB_MEDIA_BLOCK_SIZE,\r
+        }\r
+      }\r
+    },\r
+    {\r
+      {\r
+        0,\r
+        0\r
+      }\r
+    }\r
+  },\r
+\r
+  //\r
+  // Recovery BIOS FVB\r
+  //\r
+  {\r
+    FV_RECOVERY_BASE_ADDRESS,\r
+    {\r
+      {0,}, //ZeroVector[16]\r
+      EFI_FIRMWARE_FILE_SYSTEM2_GUID,\r
+      FVB_MEDIA_BLOCK_SIZE * RECOVERY_BIOS_BLOCK_NUM,\r
+      EFI_FVH_SIGNATURE,\r
+      0x0004feff, // check MdePkg/Include/Pi/PiFirmwareVolume.h for details on EFI_FVB_ATTRIBUTES_2\r
+      sizeof (EFI_FIRMWARE_VOLUME_HEADER) + sizeof (EFI_FV_BLOCK_MAP_ENTRY),\r
+      0,    //CheckSum which will be calucated dynamically.\r
+      0,    //ExtHeaderOffset\r
+      {0,}, //Reserved[1]\r
+      2,    //Revision\r
+      {\r
+        {\r
+          RECOVERY_BIOS_BLOCK_NUM,\r
+          FVB_MEDIA_BLOCK_SIZE,\r
+        }\r
+      }\r
+    },\r
+    {\r
+      {\r
+        0,\r
+        0\r
+      }\r
+    }\r
+  }\r
+};\r
+\r
+EFI_STATUS\r
+GetFvbInfo (\r
+  IN  EFI_PHYSICAL_ADDRESS         FvBaseAddress,\r
+  OUT EFI_FIRMWARE_VOLUME_HEADER   **FvbInfo\r
+  )\r
+{\r
+  UINTN                       Index;\r
+  EFI_FIRMWARE_VOLUME_HEADER  *FvHeader;\r
+\r
+  for (Index = 0; Index < sizeof (mPlatformFvbMediaInfo) / sizeof (EFI_FVB2_MEDIA_INFO); Index += 1) {\r
+    if (mPlatformFvbMediaInfo[Index].BaseAddress == FvBaseAddress) {\r
+      FvHeader =  &mPlatformFvbMediaInfo[Index].FvbInfo;\r
+\r
+      //\r
+      // Update the checksum value of FV header.\r
+      //\r
+      FvHeader->Checksum = CalculateCheckSum16 ((UINT16 *) FvHeader, FvHeader->HeaderLength / sizeof (UINT16));\r
+\r
+      *FvbInfo = FvHeader;\r
+\r
+      DEBUG ((EFI_D_INFO, "\nBaseAddr: 0x%lx \n", FvBaseAddress));\r
+      DEBUG ((EFI_D_INFO, "FvLength: 0x%lx \n", (*FvbInfo)->FvLength));\r
+      DEBUG ((EFI_D_INFO, "HeaderLength: 0x%x \n", (*FvbInfo)->HeaderLength));\r
+      DEBUG ((EFI_D_INFO, "FvBlockMap[0].NumBlocks: 0x%x \n", (*FvbInfo)->BlockMap[0].NumBlocks));\r
+      DEBUG ((EFI_D_INFO, "FvBlockMap[0].BlockLength: 0x%x \n", (*FvbInfo)->BlockMap[0].Length));\r
+      DEBUG ((EFI_D_INFO, "FvBlockMap[1].NumBlocks: 0x%x \n",   (*FvbInfo)->BlockMap[1].NumBlocks));\r
+      DEBUG ((EFI_D_INFO, "FvBlockMap[1].BlockLength: 0x%x \n\n", (*FvbInfo)->BlockMap[1].Length));\r
+\r
+      return EFI_SUCCESS;\r
+    }\r
+  }\r
+  return EFI_NOT_FOUND;\r
+}\r

diff --git a/Vlv2TbltDevicePkg/FvbRuntimeDxe/FvbRuntimeDxe.inf b/Vlv2TbltDevicePkg/FvbRuntimeDxe/FvbRuntimeDxe.inf
new file mode 100644 (file)
index 0000000..e8e6411
--- /dev/null
+++ b/Vlv2TbltDevicePkg/FvbRuntimeDxe/FvbRuntimeDxe.inf
@@ -0,0 +1,85 @@
+## @file\r
+# This driver implement the EFI_FIRMWARE_VOLUMEN_PROTOCOL.\r
+#\r
+# Copyright (c) 2006  - 2014, Intel Corporation. All rights reserved.<BR>\r
+#                                                                                  \r\r
+# This program and the accompanying materials are licensed and made available under\r\r
+# the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+# The full text of the license may be found at                                     \r\r
+# http://opensource.org/licenses/bsd-license.php.                                  \r\r
+#                                                                                  \r\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+#                                                                                  \r\r
+#\r
+#\r
+#\r
+##\r
+\r
+[Defines]\r
+  INF_VERSION                    = 0x00010005\r
+  BASE_NAME                      = FvbRuntimeDxe\r
+  FILE_GUID                      = FD3B7E55-FA7B-4e07-AE1D-208B81FB0BAD\r
+  MODULE_TYPE                    = DXE_RUNTIME_DRIVER\r
+  VERSION_STRING                 = 1.0\r
+  ENTRY_POINT                    = DxeFvbInitialize\r
+\r
+#\r
+# The following information is for reference only and not required by the build tools.\r
+#\r
+#  VALID_ARCHITECTURES           = IA32 X64\r
+#\r
+#  VIRTUAL_ADDRESS_MAP_CALLBACK  =  FvbVirtualddressChangeEvent\r
+#\r
+\r
+[Sources]\r
+  FvbInfo.c\r
+  FvbService.h\r
+  FvbService.c\r
+  FvbServiceDxe.c\r
+\r
+[Packages]\r
+  MdePkg/MdePkg.dec\r
+  MdeModulePkg/MdeModulePkg.dec\r
+  Vlv2TbltDevicePkg/PlatformPkg.dec\r
+  Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec\r
+\r
+[LibraryClasses]\r
+  FlashDeviceLib\r
+  PcdLib\r
+  MemoryAllocationLib\r
+  CacheMaintenanceLib\r
+  IoLib\r
+  BaseMemoryLib\r
+  DebugLib\r
+  BaseLib\r
+  UefiLib\r
+  UefiRuntimeLib\r
+  UefiBootServicesTableLib\r
+  UefiDriverEntryPoint\r
+\r
+[Guids]\r
+  gEfiFirmwareFileSystem2Guid                   # ALWAYS_CONSUMED\r
+  gEfiSystemNvDataFvGuid                        # ALWAYS_CONSUMED\r
+  gEfiEventVirtualAddressChangeGuid\r
+\r
+[Protocols]\r
+  gEfiDevicePathProtocolGuid                    # PROTOCOL ALWAYS_PRODUCED\r
+  gEfiFirmwareVolumeBlockProtocolGuid           # PROTOCOL ALWAYS_PRODUCED\r
+\r
+[FixedPcd]\r
+  gPlatformModuleTokenSpaceGuid.PcdFlashFvMainBase\r
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase\r
+  gPlatformModuleTokenSpaceGuid.PcdFlashFvRecoveryBase\r
+\r
+[Pcd]\r
+  gPlatformModuleTokenSpaceGuid.PcdFlashFvMainSize\r
+  gPlatformModuleTokenSpaceGuid.PcdFlashFvRecoverySize\r
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize\r
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize\r
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize\r
+\r
+\r
+[Depex]\r
+  gEfiSpiProtocolGuid AND gEfiRuntimeArchProtocolGuid\r
+\r

diff --git a/Vlv2TbltDevicePkg/FvbRuntimeDxe/FvbService.c b/Vlv2TbltDevicePkg/FvbRuntimeDxe/FvbService.c
new file mode 100644 (file)
index 0000000..da7dce6
--- /dev/null
+++ b/Vlv2TbltDevicePkg/FvbRuntimeDxe/FvbService.c
@@ -0,0 +1,1114 @@
+/** @file\r
+  Firmware Volume Block Driver for Lakeport Platform.\r
+\r
+  Firmware volume block driver for FWH or SPI device.\r
+  It depends on which Flash Device Library to be linked with this driver.\r
+\r
+Copyright (c) 2006  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+**/\r
+\r
+#include "FvbService.h"\r
+\r
+//\r
+// Global variable for this FVB driver  which contains\r
+// the private data of all firmware volume block instances.\r
+//\r
+FWB_GLOBAL   mFvbModuleGlobal;\r
+\r
+//\r
+// This platform driver knows there are 3 FVs on\r
+// FD, which are FvRecovery, FvMain and FvNvStorage.\r
+//\r
+UINT32 mPlatformFvBaseAddress[] = {\r
+  FixedPcdGet32(PcdFlashNvStorageVariableBase),\r
+};\r
+\r
+FV_MEMMAP_DEVICE_PATH mFvMemmapDevicePathTemplate = {\r
+  {\r
+    {\r
+      HARDWARE_DEVICE_PATH,\r
+      HW_MEMMAP_DP,\r
+      {\r
+        (UINT8)(sizeof (MEMMAP_DEVICE_PATH)),\r
+        (UINT8)(sizeof (MEMMAP_DEVICE_PATH) >> 8)\r
+      }\r
+    },\r
+    EfiMemoryMappedIO,\r
+    (EFI_PHYSICAL_ADDRESS) 0,\r
+    (EFI_PHYSICAL_ADDRESS) 0,\r
+  },\r
+  {\r
+    END_DEVICE_PATH_TYPE,\r
+    END_ENTIRE_DEVICE_PATH_SUBTYPE,\r
+    {\r
+      END_DEVICE_PATH_LENGTH,\r
+      0\r
+    }\r
+  }\r
+};\r
+\r
+FV_PIWG_DEVICE_PATH mFvPIWGDevicePathTemplate = {\r
+  {\r
+    {\r
+      MEDIA_DEVICE_PATH,\r
+      MEDIA_PIWG_FW_VOL_DP,\r
+      {\r
+        (UINT8)(sizeof (MEDIA_FW_VOL_DEVICE_PATH)),\r
+        (UINT8)(sizeof (MEDIA_FW_VOL_DEVICE_PATH) >> 8)\r
+      }\r
+    },\r
+    { 0 }\r
+  },\r
+  {\r
+    END_DEVICE_PATH_TYPE,\r
+    END_ENTIRE_DEVICE_PATH_SUBTYPE,\r
+    {\r
+      END_DEVICE_PATH_LENGTH,\r
+      0\r
+    }\r
+  }\r
+};\r
+\r
+//\r
+// Template structure used when installing FVB protocol.\r
+//\r
+EFI_FW_VOL_BLOCK_DEVICE mFvbDeviceTemplate = {\r
+  FVB_DEVICE_SIGNATURE,\r
+  NULL,\r
+  0, // Instance\r
+  {\r
+    FvbProtocolGetAttributes,\r
+    FvbProtocolSetAttributes,\r
+    FvbProtocolGetPhysicalAddress,\r
+    FvbProtocolGetBlockSize,\r
+    FvbProtocolRead,\r
+    FvbProtocolWrite,\r
+    FvbProtocolEraseBlocks,\r
+    NULL\r
+  } // FwVolBlockInstance\r
+};\r
+\r
+\r
+/**\r
+  Get the pointer to EFI_FW_VOL_INSTANCE from the buffer pointed\r
+  by mFvbModuleGlobal.FvInstance based on a index.\r
+  Each EFI_FW_VOL_INSTANCE is  with variable length as\r
+  we have a block map at the end of the EFI_FIRMWARE_VOLUME_HEADER.\r
+\r
+  @param[in] Instance The index of the EFI_FW_VOL_INSTANCE.\r
+\r
+  @return A pointer to EFI_FW_VOL_INSTANCE.\r
+\r
+**/\r
+EFI_FW_VOL_INSTANCE *\r
+GetFvbInstance (\r
+  IN  UINTN             Instance\r
+  )\r
+{\r
+  EFI_FW_VOL_INSTANCE   *FwhRecord;\r
+\r
+  if ( Instance >= mFvbModuleGlobal.NumFv ) {\r
+    ASSERT_EFI_ERROR (EFI_INVALID_PARAMETER);\r
+    return NULL;\r
+  }\r
+\r
+  //\r
+  // Find the right instance of the FVB private data.\r
+  //\r
+  FwhRecord = mFvbModuleGlobal.FvInstance;\r
+  while ( Instance > 0 ) {\r
+    FwhRecord = (EFI_FW_VOL_INSTANCE *) ((UINTN)((UINT8 *)FwhRecord) +\r
+                FwhRecord->VolumeHeader.HeaderLength +\r
+                (sizeof (EFI_FW_VOL_INSTANCE) - sizeof (EFI_FIRMWARE_VOLUME_HEADER)));\r
+    Instance --;\r
+  }\r
+\r
+  return FwhRecord;\r
+\r
+}\r
+\r
+\r
+/**\r
+  Get the EFI_FVB_ATTRIBUTES_2 of a FV.\r
+\r
+  @param[in]  The index of the EFI_FW_VOL_INSTANCE.\r
+\r
+  @return     EFI_FVB_ATTRIBUTES_2 of the FV identified by Instance.\r
+\r
+**/\r
+STATIC\r
+EFI_FVB_ATTRIBUTES_2\r
+FvbGetVolumeAttributes (\r
+  IN UINTN                                Instance\r
+  )\r
+{\r
+  EFI_FW_VOL_INSTANCE *    FwInstance = NULL;\r
+  FwInstance = GetFvbInstance(Instance);\r
+  ASSERT_EFI_ERROR (FwInstance != NULL);\r
+\r
+  if ( FwInstance != NULL ) {\r
+    return FwInstance->VolumeHeader.Attributes;\r
+  } else {\r
+    return 0;\r
+  }\r
+}\r
+\r
+\r
+/**\r
+  Retrieves the starting address of an LBA in an FV. It also\r
+  return a few other attribut of the FV.\r
+\r
+  @param[in]  Instance               The index of the EFI_FW_VOL_INSTANCE.\r
+  @param[in]  Lba                    The logical block address.\r
+  @param[out] LbaAddress             On output, contains the physical starting address\r
+                                     of the Lba.\r
+  @param[out] LbaLength              On output, contains the length of the block.\r
+  @param[out] NumOfBlocks            A pointer to a caller allocated UINTN in which the\r
+                                     number of consecutive blocks starting with Lba is\r
+                                     returned. All blocks in this range have a size of\r
+                                     BlockSize.\r
+\r
+  @retval  EFI_SUCCESS Successfully  returns.\r
+  @retval  EFI_INVALID_PARAMETER     Instance not found.\r
+\r
+**/\r
+STATIC\r
+EFI_STATUS\r
+FvbGetLbaAddress (\r
+  IN  UINTN                               Instance,\r
+  IN  EFI_LBA                             Lba,\r
+  OUT UINTN                               *LbaAddress,\r
+  OUT UINTN                               *LbaLength,\r
+  OUT UINTN                               *NumOfBlocks\r
+  )\r
+{\r
+  UINT32                                  NumBlocks = 0;\r
+  UINT32                                  BlockLength = 0;\r
+  UINTN                                   Offset;\r
+  EFI_LBA                                 StartLba;\r
+  EFI_LBA                                 NextLba;\r
+  EFI_FW_VOL_INSTANCE                     *FwhInstance;\r
+  EFI_FV_BLOCK_MAP_ENTRY                  *BlockMap = NULL;\r
+\r
+  //\r
+  // Find the right instance of the FVB private data.\r
+  //\r
+  FwhInstance = GetFvbInstance (Instance);\r
+\r
+  StartLba  = 0;\r
+  Offset    = 0;\r
+  BlockMap  = &(FwhInstance->VolumeHeader.BlockMap[0]);\r
+  ASSERT_EFI_ERROR (BlockMap != NULL);\r
+\r
+  //\r
+  // Parse the blockmap of the FV to find which map entry the Lba belongs to.\r
+  //\r
+  while (TRUE) {\r
+    if ( BlockMap != NULL) {\r
+      NumBlocks   = BlockMap->NumBlocks;\r
+      BlockLength = BlockMap->Length;\r
+    }\r
+\r
+    if ( NumBlocks == 0 || BlockLength == 0) {\r
+      return EFI_INVALID_PARAMETER;\r
+    }\r
+\r
+    NextLba = StartLba + NumBlocks;\r
+\r
+    //\r
+    // The map entry found.\r
+    //\r
+    if (Lba >= StartLba && Lba < NextLba) {\r
+      Offset = Offset + (UINTN)MultU64x32((Lba - StartLba), BlockLength);\r
+      if ( LbaAddress && FwhInstance ) {\r
+        *LbaAddress = FwhInstance->FvBase + Offset;\r
+      }\r
+\r
+      if (LbaLength ) {\r
+        *LbaLength = BlockLength;\r
+      }\r
+\r
+      if (NumOfBlocks ) {\r
+        *NumOfBlocks = (UINTN)(NextLba - Lba);\r
+      }\r
+      return EFI_SUCCESS;\r
+    }\r
+\r
+    StartLba  = NextLba;\r
+    Offset    = Offset + NumBlocks * BlockLength;\r
+    BlockMap++;\r
+  }\r
+}\r
+\r
+\r
+/**\r
+  Reads specified number of bytes into a buffer from the specified block.\r
+\r
+  @param[in]      Instance               The FV instance to be read from.\r
+  @param[in]      Lba                    The logical block address to be read from.\r
+  @param[in]      BlockOffset            Offset into the block at which to begin reading.\r
+  @param[in]      NumBytes               Pointer that on input contains the total size of\r
+                                         the buffer. On output, it contains the total number\r
+                                         of bytes read.\r
+  @param[in]      Buffer                 Pointer to a caller allocated buffer that will be\r
+                                         used to hold the data read.\r
+\r
+\r
+  @retval         EFI_SUCCESS            The firmware volume was read successfully and\r
+                                         contents are in Buffer.\r
+  @retval         EFI_BAD_BUFFER_SIZE    Read attempted across a LBA boundary. On output,\r
+                                         NumBytes contains the total number of bytes returned\r
+                                         in Buffer.\r
+  @retval         EFI_ACCESS_DENIED      The firmware volume is in the ReadDisabled state.\r
+  @retval         EFI_DEVICE_ERROR       The block device is not functioning correctly and\r
+                                         could not be read.\r
+  @retval         EFI_INVALID_PARAMETER  Instance not found, or NumBytes, Buffer are NULL.\r
+\r
+**/\r
+STATIC\r
+EFI_STATUS\r
+FvbReadBlock (\r
+  IN UINTN                                Instance,\r
+  IN EFI_LBA                              Lba,\r
+  IN UINTN                                BlockOffset,\r
+  IN OUT UINTN                            *NumBytes,\r
+  IN UINT8                                *Buffer\r
+  )\r
+{\r
+  EFI_FVB_ATTRIBUTES_2                    Attributes;\r
+  UINTN                                   LbaAddress;\r
+  UINTN                                   LbaLength;\r
+  EFI_STATUS                              Status;\r
+\r
+  if ( (NumBytes == NULL) || (Buffer == NULL)) {\r
+    return (EFI_INVALID_PARAMETER);\r
+  }\r
+  if (*NumBytes == 0) {\r
+    return (EFI_INVALID_PARAMETER);\r
+  }\r
+\r
+  Status = FvbGetLbaAddress (Instance, Lba, &LbaAddress, &LbaLength, NULL);\r
+  if (EFI_ERROR(Status)) {\r
+    return Status;\r
+  }\r
+\r
+  Attributes = FvbGetVolumeAttributes (Instance);\r
+\r
+  if ( (Attributes & EFI_FVB2_READ_STATUS) == 0) {\r
+    return (EFI_ACCESS_DENIED);\r
+  }\r
+\r
+  if (BlockOffset > LbaLength) {\r
+   return (EFI_INVALID_PARAMETER);\r
+  }\r
+\r
+  if (LbaLength < ( *NumBytes + BlockOffset ) ) {\r
+    *NumBytes = (UINT32) (LbaLength - BlockOffset);\r
+    Status = EFI_BAD_BUFFER_SIZE;\r
+  }\r
+\r
+  LibFvbFlashDeviceRead (LbaAddress + BlockOffset, NumBytes, Buffer);\r
+\r
+  return Status;\r
+}\r
+\r
+\r
+/**\r
+  Writes specified number of bytes from the input buffer to the block.\r
+\r
+  @param[in]  Instance               The FV instance to be written to.\r
+  @param[in]  Lba                    The starting logical block index to write to.\r
+  @param[in]  BlockOffset            Offset into the block at which to begin writing.\r
+  @param[in]  NumBytes               Pointer that on input contains the total size of\r
+                                     the buffer. On output, it contains the total number\r
+                                     of bytes actually written.\r
+  @param[in]  Buffer                 Pointer to a caller allocated buffer that contains\r
+                                     the source for the write.\r
+  @retval     EFI_SUCCESS            The firmware volume was written successfully.\r
+  @retval     EFI_BAD_BUFFER_SIZE    Write attempted across a LBA boundary. On output,\r
+                                     NumBytes contains the total number of bytes\r
+                                     actually writte.\r
+  @retval     EFI_ACCESS_DENIED      The firmware volume is in the WriteDisabled state.\r
+  @retval     EFI_DEVICE_ERROR       The block device is not functioning correctly and\r
+                                     could not be written.\r
+  @retval     EFI_INVALID_PARAMETER  Instance not found, or NumBytes, Buffer are NULL.\r
+\r
+**/\r
+EFI_STATUS\r
+FvbWriteBlock (\r
+  IN UINTN                                Instance,\r
+  IN EFI_LBA                              Lba,\r
+  IN UINTN                                BlockOffset,\r
+  IN OUT UINTN                            *NumBytes,\r
+  IN UINT8                                *Buffer\r
+  )\r
+{\r
+  EFI_FVB_ATTRIBUTES_2                    Attributes;\r
+  UINTN                                   LbaAddress;\r
+  UINTN                                   LbaLength;\r
+  EFI_FW_VOL_INSTANCE                     *FwhInstance;\r
+  EFI_STATUS                              Status;\r
+  EFI_STATUS                              Status1;\r
+\r
+  FwhInstance = GetFvbInstance (Instance);\r
+\r
+  if ( (NumBytes == NULL) || (Buffer == NULL)) {\r
+    return (EFI_INVALID_PARAMETER);\r
+  }\r
+  if (*NumBytes == 0) {\r
+    return (EFI_INVALID_PARAMETER);\r
+  }\r
+\r
+  Status = FvbGetLbaAddress (Instance, Lba, &LbaAddress, &LbaLength, NULL);\r
+  if (EFI_ERROR(Status)) {\r
+    return Status;\r
+  }\r
+\r
+  //\r
+  // Check if the FV is write enabled.\r
+  //\r
+  Attributes = FvbGetVolumeAttributes (Instance);\r
+  if ( (Attributes & EFI_FVB2_WRITE_STATUS) == 0) {\r
+    return (EFI_ACCESS_DENIED);\r
+  }\r
+\r
+  //\r
+  // Perform boundary checks and adjust NumBytes.\r
+  //\r
+  if (BlockOffset > LbaLength) {\r
+    return (EFI_INVALID_PARAMETER);\r
+  }\r
+\r
+  if ( LbaLength < ( *NumBytes + BlockOffset ) ) {\r
+    DEBUG ((EFI_D_ERROR,\r
+      "FvWriteBlock: Reducing Numbytes from 0x%x to 0x%x\n",\r
+      *NumBytes,\r
+      (UINT32)(LbaLength-BlockOffset))\r
+      );\r
+    *NumBytes = (UINT32) (LbaLength - BlockOffset);\r
+    Status = EFI_BAD_BUFFER_SIZE;\r
+  }\r
+\r
+  LibFvbFlashDeviceBlockLock (LbaAddress, LbaLength, FALSE);\r
+\r
+  Status1 = LibFvbFlashDeviceWrite (LbaAddress + BlockOffset, NumBytes, Buffer);\r
+\r
+  LibFvbFlashDeviceBlockLock (LbaAddress, LbaLength, TRUE);\r
+  WriteBackInvalidateDataCacheRange ((VOID *) (LbaAddress + BlockOffset), *NumBytes);\r
+\r
+  if ( EFI_ERROR (Status1) ) {\r
+    return Status1;\r
+  }\r
+\r
+  return Status;\r
+}\r
+\r
+\r
+/**\r
+  Erases and initializes a firmware volume block.\r
+\r
+  @param[in]    Instance           The FV instance to be erased.\r
+  @param[in]    Lba                The logical block index to be erased.\r
+\r
+  @retval   EFI_SUCCESS            The erase request was successfully completed.\r
+  @retval   EFI_ACCESS_DENIED      The firmware volume is in the WriteDisabled state.\r
+  @retval   EFI_DEVICE_ERROR       The block device is not functioning correctly and\r
+                                   could not be written. Firmware device may have been\r
+                                   partially erased.\r
+  @retval   EFI_INVALID_PARAMETER  Instance not found.\r
+\r
+**/\r
+EFI_STATUS\r
+FvbEraseBlock (\r
+  IN UINTN                                Instance,\r
+  IN EFI_LBA                              Lba\r
+  )\r
+{\r
+  EFI_FVB_ATTRIBUTES_2                    Attributes;\r
+  UINTN                                   LbaAddress;\r
+  EFI_FW_VOL_INSTANCE                     *FwhInstance;\r
+  UINTN                                   LbaLength;\r
+  EFI_STATUS                              Status;\r
+\r
+  //\r
+  // Find the right instance of the FVB private data.\r
+  //\r
+  FwhInstance = GetFvbInstance (Instance);\r
+\r
+  //\r
+  // Check if the FV is write enabled.\r
+  //\r
+  Attributes = FvbGetVolumeAttributes (Instance);\r
+\r
+  if( (Attributes & EFI_FVB2_WRITE_STATUS) == 0) {\r
+    return (EFI_ACCESS_DENIED);\r
+  }\r
+\r
+  //\r
+  // Get the starting address of the block for erase.\r
+  //\r
+  Status = FvbGetLbaAddress (Instance, Lba, &LbaAddress, &LbaLength, NULL);\r
+  if (EFI_ERROR(Status)) {\r
+    return Status;\r
+  }\r
+\r
+  LibFvbFlashDeviceBlockLock (LbaAddress, LbaLength, FALSE);\r
+\r
+  Status = LibFvbFlashDeviceBlockErase (LbaAddress, LbaLength);\r
+\r
+  LibFvbFlashDeviceBlockLock (LbaAddress, LbaLength, TRUE);\r
+\r
+  WriteBackInvalidateDataCacheRange ((VOID *) LbaAddress, LbaLength);\r
+\r
+  return Status;\r
+}\r
+\r
+\r
+/**\r
+  Modifies the current settings of the firmware volume according to the\r
+  input parameter, and returns the new setting of the volume.\r
+\r
+  @param[in]  Instance              The FV instance whose attributes is going to be\r
+                                    modified.\r
+  @param[in]  Attributes            On input, it is a pointer to EFI_FVB_ATTRIBUTES_2\r
+                                    containing the desired firmware volume settings.\r
+                                    On successful return, it contains the new settings\r
+                                    of the firmware volume.\r
+\r
+  @retval     EFI_SUCCESS           Successfully returns.\r
+  @retval     EFI_ACCESS_DENIED     The volume setting is locked and cannot be modified.\r
+  @retval     EFI_INVALID_PARAMETER Instance not found, or The attributes requested are\r
+                                    in conflict with the capabilities as declared in the\r
+                                    firmware volume header.\r
+\r
+**/\r
+STATIC\r
+EFI_STATUS\r
+FvbSetVolumeAttributes (\r
+  IN UINTN                                Instance,\r
+  IN OUT EFI_FVB_ATTRIBUTES_2             *Attributes\r
+  )\r
+{\r
+  EFI_FW_VOL_INSTANCE                       *FwhInstance = NULL;\r
+  EFI_FVB_ATTRIBUTES_2                      OldAttributes = 0;\r
+  EFI_FVB_ATTRIBUTES_2                      *AttribPtr = NULL;\r
+  EFI_FVB_ATTRIBUTES_2                      UnchangedAttributes;\r
+  UINT32                                    Capabilities;\r
+  UINT32                                    OldStatus, NewStatus;\r
+\r
+  //\r
+  // Find the right instance of the FVB private data.\r
+  //\r
+  FwhInstance = GetFvbInstance (Instance);\r
+\r
+  AttribPtr     = (EFI_FVB_ATTRIBUTES_2 *) & (FwhInstance->VolumeHeader.Attributes);\r
+  ASSERT_EFI_ERROR (AttribPtr != NULL);\r
+\r
+  if ( AttribPtr != NULL) {\r
+    OldAttributes = *AttribPtr;\r
+  }\r
+\r
+  Capabilities  = OldAttributes & EFI_FVB2_CAPABILITIES;\r
+  OldStatus     = OldAttributes & EFI_FVB2_STATUS;\r
+  NewStatus     = *Attributes & EFI_FVB2_STATUS;\r
+\r
+  UnchangedAttributes = EFI_FVB2_READ_DISABLED_CAP  | \\r
+                        EFI_FVB2_READ_ENABLED_CAP   | \\r
+                        EFI_FVB2_WRITE_DISABLED_CAP | \\r
+                        EFI_FVB2_WRITE_ENABLED_CAP  | \\r
+                        EFI_FVB2_LOCK_CAP           | \\r
+                        EFI_FVB2_STICKY_WRITE       | \\r
+                        EFI_FVB2_MEMORY_MAPPED      | \\r
+                        EFI_FVB2_ERASE_POLARITY     | \\r
+                        EFI_FVB2_READ_LOCK_CAP      | \\r
+                        EFI_FVB2_WRITE_LOCK_CAP     | \\r
+                        EFI_FVB2_ALIGNMENT;\r
+\r
+  //\r
+  // Some attributes of FV is read only can *not* be set.\r
+  //\r
+  if ((OldAttributes & UnchangedAttributes) ^ (*Attributes & UnchangedAttributes)) {\r
+    return EFI_INVALID_PARAMETER;\r
+  }\r
+\r
+  //\r
+  // If firmware volume is locked, no status bit can be updated.\r
+  //\r
+  if ( OldAttributes & EFI_FVB2_LOCK_STATUS ) {\r
+    if ( OldStatus ^ NewStatus ) {\r
+      return EFI_ACCESS_DENIED;\r
+    }\r
+  }\r
+\r
+  //\r
+  // Test read disable.\r
+  //\r
+  if ((Capabilities & EFI_FVB2_READ_DISABLED_CAP) == 0) {\r
+    if ((NewStatus & EFI_FVB2_READ_STATUS) == 0) {\r
+      return EFI_INVALID_PARAMETER;\r
+    }\r
+  }\r
+\r
+  //\r
+  // Test read enable.\r
+  //\r
+  if ((Capabilities & EFI_FVB2_READ_ENABLED_CAP) == 0) {\r
+    if (NewStatus & EFI_FVB2_READ_STATUS) {\r
+      return EFI_INVALID_PARAMETER;\r
+    }\r
+  }\r
+\r
+  //\r
+  // Test write disable.\r
+  //\r
+  if ((Capabilities & EFI_FVB2_WRITE_DISABLED_CAP) == 0) {\r
+    if ((NewStatus & EFI_FVB2_WRITE_STATUS) == 0) {\r
+      return EFI_INVALID_PARAMETER;\r
+    }\r
+  }\r
+\r
+  //\r
+  // Test write enable.\r
+  //\r
+  if ((Capabilities & EFI_FVB2_WRITE_ENABLED_CAP) == 0) {\r
+    if (NewStatus & EFI_FVB2_WRITE_STATUS) {\r
+      return EFI_INVALID_PARAMETER;\r
+    }\r
+  }\r
+\r
+  //\r
+  // Test lock.\r
+  //\r
+  if ((Capabilities & EFI_FVB2_LOCK_CAP) == 0) {\r
+    if (NewStatus & EFI_FVB2_LOCK_STATUS) {\r
+      return EFI_INVALID_PARAMETER;\r
+    }\r
+  }\r
+\r
+  *AttribPtr  = (*AttribPtr) & (0xFFFFFFFF & (~EFI_FVB2_STATUS));\r
+  *AttribPtr  = (*AttribPtr) | NewStatus;\r
+  *Attributes = *AttribPtr;\r
+\r
+  return EFI_SUCCESS;\r
+}\r
+\r
+//\r
+// FVB protocol APIs.\r
+//\r
+/**\r
+  Retrieves the physical address of the device.\r
+\r
+  @param[in]  This    A pointer to EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL.\r
+  @param[out] Address Output buffer containing the address.\r
+\r
+  retval      EFI_SUCCESS The function always return successfully.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+FvbProtocolGetPhysicalAddress (\r
+  IN CONST EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL  *This,\r
+  OUT EFI_PHYSICAL_ADDRESS               *Address\r
+  )\r
+{\r
+  EFI_FW_VOL_BLOCK_DEVICE               *FvbDevice;\r
+  EFI_FW_VOL_INSTANCE                   *FvInstance;\r
+\r
+  FvbDevice = FVB_DEVICE_FROM_THIS (This);\r
+  FvInstance = GetFvbInstance(FvbDevice->Instance);\r
+\r
+  if (FvInstance != NULL) {\r
+    *Address = FvInstance->FvBase;\r
+  }\r
+\r
+  return EFI_SUCCESS;\r
+}\r
+\r
+\r
+/**\r
+  Retrieve the size of a logical block.\r
+\r
+  @param[in]  This         Calling context.\r
+  @param[in]  Lba          Indicates which block to return the size for.\r
+  @param[out] BlockSize    A pointer to a caller allocated UINTN in which\r
+                           the size of the block is returned.\r
+  @param[out] NumOfBlocks  A pointer to a caller allocated UINTN in which the\r
+                           number of consecutive blocks starting with Lba is\r
+                           returned. All blocks in this range have a size of\r
+                           BlockSize.\r
+\r
+  @retval     EFI_SUCCESS  The function always return successfully.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+FvbProtocolGetBlockSize (\r
+  IN CONST EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL  *This,\r
+  IN  EFI_LBA                            Lba,\r
+  OUT UINTN                              *BlockSize,\r
+  OUT UINTN                              *NumOfBlocks\r
+  )\r
+{\r
+  EFI_FW_VOL_BLOCK_DEVICE                 *FvbDevice;\r
+\r
+  DEBUG((EFI_D_INFO,\r
+    "FvbProtocolGetBlockSize: Lba: 0x%lx BlockSize: 0x%x NumOfBlocks: 0x%x\n",\r
+    Lba,\r
+    BlockSize,\r
+    NumOfBlocks)\r
+    );\r
+\r
+  FvbDevice = FVB_DEVICE_FROM_THIS (This);\r
+\r
+  return FvbGetLbaAddress (\r
+           FvbDevice->Instance,\r
+           Lba,\r
+           NULL,\r
+           BlockSize,\r
+           NumOfBlocks\r
+           );\r
+}\r
+\r
+\r
+/**\r
+  Retrieves Volume attributes.  No polarity translations are done.\r
+\r
+  @param[in]    This         Calling context.\r
+  @param[out]   Attributes   Output buffer which contains attributes.\r
+\r
+  @retval       EFI_SUCCESS  The function always return successfully.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+FvbProtocolGetAttributes (\r
+  IN CONST EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL   *This,\r
+  OUT EFI_FVB_ATTRIBUTES_2                *Attributes\r
+  )\r
+{\r
+  EFI_FW_VOL_BLOCK_DEVICE               *FvbDevice;\r
+\r
+  FvbDevice = FVB_DEVICE_FROM_THIS (This);\r
+\r
+  *Attributes = FvbGetVolumeAttributes (FvbDevice->Instance);\r
+\r
+  DEBUG ((EFI_D_INFO,\r
+    "FvbProtocolGetAttributes: This: 0x%x Attributes: 0x%x\n",\r
+    This,\r
+    *Attributes)\r
+    );\r
+\r
+  return EFI_SUCCESS;\r
+}\r
+\r
+\r
+/**\r
+  Sets Volume attributes. No polarity translations are done.\r
+\r
+  @param[in]  This         Calling context.\r
+  @param[out] Attributes   Output buffer which contains attributes.\r
+\r
+  @retval     EFI_SUCCESS  The function always return successfully.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+FvbProtocolSetAttributes (\r
+  IN CONST EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL   *This,\r
+  IN OUT EFI_FVB_ATTRIBUTES_2             *Attributes\r
+  )\r
+{\r
+  EFI_STATUS                            Status;\r
+  EFI_FW_VOL_BLOCK_DEVICE               *FvbDevice;\r
+\r
+  DEBUG((EFI_D_INFO,\r
+    "FvbProtocolSetAttributes: Before SET -  This: 0x%x Attributes: 0x%x\n",\r
+    This,\r
+    *Attributes)\r
+    );\r
+\r
+  FvbDevice = FVB_DEVICE_FROM_THIS (This);\r
+\r
+  Status = FvbSetVolumeAttributes (FvbDevice->Instance, Attributes);\r
+\r
+  DEBUG((EFI_D_INFO,\r
+    "FvbProtocolSetAttributes: After SET -  This: 0x%x Attributes: 0x%x\n",\r
+    This,\r
+    *Attributes)\r
+    );\r
+\r
+  return Status;\r
+}\r
+\r
+\r
+/**\r
+  The EraseBlock() function erases one or more blocks as denoted by the\r
+  variable argument list. The entire parameter list of blocks must be verified\r
+  prior to erasing any blocks.  If a block is requested that does not exist\r
+  within the associated firmware volume (it has a larger index than the last\r
+  block of the firmware volume), the EraseBlock() function must return\r
+  EFI_INVALID_PARAMETER without modifying the contents of the firmware volume.\r
+\r
+  @param[in] This            Calling context.\r
+  @param[in] ...             Starting LBA followed by Number of Lba to erase.\r
+                             a -1 to terminate the list.\r
+\r
+  @retval EFI_SUCCESS        The erase request was successfully completed.\r
+  @retval EFI_ACCESS_DENIED  The firmware volume is in the WriteDisabled state.\r
+  @retval EFI_DEVICE_ERROR   The block device is not functioning correctly and\r
+                             could not be written. Firmware device may have been\r
+                             partially erased.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+FvbProtocolEraseBlocks (\r
+  IN CONST EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL    *This,\r
+  ...\r
+  )\r
+{\r
+  EFI_FW_VOL_BLOCK_DEVICE               *FvbDevice;\r
+  EFI_FW_VOL_INSTANCE                   *FwhInstance;\r
+  UINTN                                 NumOfBlocks = 0;\r
+  VA_LIST                               args;\r
+  EFI_LBA                               StartingLba;\r
+  UINTN                                 NumOfLba;\r
+  EFI_STATUS                            Status;\r
+\r
+  DEBUG((EFI_D_INFO, "FvbProtocolEraseBlocks: \n"));\r
+  FvbDevice = FVB_DEVICE_FROM_THIS (This);\r
+\r
+  FwhInstance  = GetFvbInstance (FvbDevice->Instance);\r
+\r
+  if (FwhInstance != NULL) {\r
+    NumOfBlocks = FwhInstance->NumOfBlocks;\r
+  }\r
+\r
+  VA_START (args, This);\r
+\r
+  do {\r
+    StartingLba = VA_ARG (args, EFI_LBA);\r
+    if ( StartingLba == EFI_LBA_LIST_TERMINATOR ) {\r
+      break;\r
+    }\r
+\r
+    NumOfLba = VA_ARG (args, UINT32);\r
+\r
+    //\r
+    // Check input parameters.\r
+    //\r
+    if (NumOfLba == 0) {\r
+      VA_END (args);\r
+      return EFI_INVALID_PARAMETER;\r
+    }\r
+\r
+    if ( ( StartingLba + NumOfLba ) > NumOfBlocks ) {\r
+      return EFI_INVALID_PARAMETER;\r
+    }\r
+  } while ( 1 );\r
+\r
+  VA_END (args);\r
+\r
+  VA_START (args, This);\r
+  do {\r
+    StartingLba = VA_ARG (args, EFI_LBA);\r
+    if (StartingLba == EFI_LBA_LIST_TERMINATOR) {\r
+      break;\r
+    }\r
+\r
+    NumOfLba = VA_ARG (args, UINT32);\r
+\r
+    while ( NumOfLba > 0 ) {\r
+      Status = FvbEraseBlock (FvbDevice->Instance, StartingLba);\r
+      if ( EFI_ERROR(Status)) {\r
+        VA_END (args);\r
+        return Status;\r
+      }\r
+      StartingLba ++;\r
+      NumOfLba --;\r
+    }\r
+\r
+  } while ( 1 );\r
+\r
+  VA_END (args);\r
+\r
+  return EFI_SUCCESS;\r
+}\r
+\r
+\r
+/**\r
+  Writes data beginning at Lba:Offset from FV. The write terminates either\r
+  when *NumBytes of data have been written, or when a block boundary is\r
+  reached.  *NumBytes is updated to reflect the actual number of bytes\r
+  written. The write opertion does not include erase. This routine will\r
+  attempt to write only the specified bytes. If the writes do not stick,\r
+  it will return an error.\r
+\r
+  @param[in]      This      Calling context.\r
+  @param[in]      Lba       Block in which to begin write.\r
+  @param[in]      Offset    Offset in the block at which to begin write.\r
+  @param[in,out]  NumBytes  On input, indicates the requested write size. On\r
+                            output, indicates the actual number of bytes written\r
+  @param[in]      Buffer    Buffer containing source data for the write.\r
+\r
+  @retval EFI_SUCCESS           The firmware volume was written successfully.\r
+  @retval EFI_BAD_BUFFER_SIZE   Write attempted across a LBA boundary. On output,\r
+                                NumBytes contains the total number of bytes\r
+                                actually written.\r
+  @retval EFI_ACCESS_DENIED     The firmware volume is in the WriteDisabled state.\r
+  @retval EFI_DEVICE_ERROR      The block device is not functioning correctly and\r
+                                could not be written.\r
+  @retval EFI_INVALID_PARAMETER NumBytes or Buffer are NULL.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+FvbProtocolWrite (\r
+  IN CONST EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL   *This,\r
+  IN EFI_LBA                              Lba,\r
+  IN UINTN                                Offset,\r
+  IN OUT UINTN                            *NumBytes,\r
+  IN UINT8                                *Buffer\r
+  )\r
+{\r
+\r
+  EFI_FW_VOL_BLOCK_DEVICE               *FvbDevice;\r
+\r
+  FvbDevice = FVB_DEVICE_FROM_THIS (This);\r
+\r
+  DEBUG((EFI_D_INFO,\r
+    "FvbProtocolWrite: Lba: 0x%lx Offset: 0x%x NumBytes: 0x%x, Buffer: 0x%x\n",\r
+    Lba,\r
+    Offset,\r
+    *NumBytes,\r
+    Buffer)\r
+    );\r
+\r
+  return FvbWriteBlock (FvbDevice->Instance, Lba, Offset, NumBytes, Buffer);\r
+}\r
+\r
+\r
+/**\r
+  Reads data beginning at Lba:Offset from FV. The Read terminates either\r
+  when *NumBytes of data have been read, or when a block boundary is\r
+  reached.  *NumBytes is updated to reflect the actual number of bytes\r
+  written. The write opertion does not include erase. This routine will\r
+  attempt to write only the specified bytes. If the writes do not stick,\r
+  it will return an error.\r
+\r
+  @param[in]      This      Calling context.\r
+  @param[in]      Lba       Block in which to begin write.\r
+  @param[in]      Offset    Offset in the block at which to begin write\r
+  @param[in,out]  NumBytes  On input, indicates the requested write size. On\r
+                            output, indicates the actual number of bytes written.\r
+  @param[in]      Buffer    Buffer containing source data for the write.\r
+\r
+\r
+Returns:\r
+  @retval EFI_SUCCESS            The firmware volume was read successfully and\r
+                                 contents are in Buffer.\r
+  @retval EFI_BAD_BUFFER_SIZE    Read attempted across a LBA boundary. On output,\r
+                                 NumBytes contains the total number of bytes returned\r
+                                 in Buffer.\r
+  @retval EFI_ACCESS_DENIED      The firmware volume is in the ReadDisabled state\r
+  @retval EFI_DEVICE_ERROR       The block device is not functioning correctly and\r
+                                 could not be read.\r
+  @retval EFI_INVALID_PARAMETER  NumBytes or Buffer are NULL.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+FvbProtocolRead (\r
+  IN CONST EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL   *This,\r
+  IN EFI_LBA                              Lba,\r
+  IN UINTN                                Offset,\r
+  IN OUT UINTN                            *NumBytes,\r
+  OUT UINT8                                *Buffer\r
+  )\r
+{\r
+\r
+  EFI_FW_VOL_BLOCK_DEVICE   *FvbDevice;\r
+  EFI_STATUS                Status;\r
+\r
+  FvbDevice = FVB_DEVICE_FROM_THIS (This);\r
+  Status = FvbReadBlock (FvbDevice->Instance, Lba, Offset, NumBytes, Buffer);\r
+  DEBUG((EFI_D_INFO,\r
+    "FvbProtocolRead: Lba: 0x%lx Offset: 0x%x NumBytes: 0x%x, Buffer: 0x%x\n",\r
+    Lba,\r
+    Offset,\r
+    *NumBytes,\r
+    Buffer)\r
+    );\r
+\r
+  return Status;\r
+}\r
+\r
+\r
+/**\r
+  Check the integrity of firmware volume header.\r
+\r
+  @param[in]  FwVolHeader   A pointer to a firmware volume header.\r
+\r
+  @retval     TRUE          The firmware volume is consistent.\r
+  @retval     FALSE         The firmware volume has corrupted.\r
+\r
+**/\r
+BOOLEAN\r
+IsFvHeaderValid (\r
+  IN       EFI_PHYSICAL_ADDRESS          FvBase,\r
+  IN CONST EFI_FIRMWARE_VOLUME_HEADER    *FwVolHeader\r
+  )\r
+{\r
+  if (FvBase == PcdGet32(PcdFlashNvStorageVariableBase)) {\r
+    if (CompareMem (&FwVolHeader->FileSystemGuid, &gEfiSystemNvDataFvGuid, sizeof(EFI_GUID)) != 0 ) {\r
+      return FALSE;\r
+    }\r
+  } else {\r
+    if (CompareMem (&FwVolHeader->FileSystemGuid, &gEfiFirmwareFileSystem2Guid, sizeof(EFI_GUID)) != 0 ) {\r
+      return FALSE;\r
+    }\r
+  }\r
+  if ( (FwVolHeader->Revision != EFI_FVH_REVISION)   ||\r
+       (FwVolHeader->Signature != EFI_FVH_SIGNATURE) ||\r
+       (FwVolHeader->FvLength == ((UINTN) -1))       ||\r
+       ((FwVolHeader->HeaderLength & 0x01 ) !=0) ) {\r
+    return FALSE;\r
+  }\r
+\r
+  if (CalculateCheckSum16 ((UINT16 *) FwVolHeader, FwVolHeader->HeaderLength) != 0) {\r
+    return FALSE;\r
+  }\r
+\r
+  return TRUE;\r
+}\r
+\r
+\r
+/**\r
+  The function does the necessary initialization work for\r
+  Firmware Volume Block Driver.\r
+\r
+  @retval     EFI_SUCCESS       This funtion always return EFI_SUCCESS.\r
+                                It will ASSERT on errors.\r
+\r
+**/\r
+EFI_STATUS\r
+FvbInitialize (\r
+  VOID\r
+  )\r
+{\r
+  EFI_FW_VOL_INSTANCE                   *FwhInstance;\r
+  EFI_FIRMWARE_VOLUME_HEADER            *FwVolHeader;\r
+  EFI_FIRMWARE_VOLUME_HEADER            *FvHeader;\r
+  EFI_FV_BLOCK_MAP_ENTRY                *PtrBlockMapEntry;\r
+  EFI_PHYSICAL_ADDRESS                  BaseAddress;\r
+  EFI_STATUS                            Status;\r
+  UINTN                                 BufferSize;\r
+  UINTN                                 TmpHeaderLength;\r
+  UINTN                                 Idx;\r
+  UINT32                                MaxLbaSize;\r
+  BOOLEAN                               FvHeaderValid;\r
+\r
+  //\r
+  // Calculate the total size for all firmware volume block instances.\r
+  //\r
+  BufferSize = 0;\r
+  for (Idx = 0; Idx < 1; Idx++) {\r
+    FvHeader = (EFI_FIRMWARE_VOLUME_HEADER *) (UINTN) mPlatformFvBaseAddress[Idx];\r
+    BufferSize +=  (FvHeader->HeaderLength +\r
+                    sizeof (EFI_FW_VOL_INSTANCE) -\r
+                    sizeof (EFI_FIRMWARE_VOLUME_HEADER)\r
+                   );\r
+  }\r
+\r
+  mFvbModuleGlobal.FvInstance =  (EFI_FW_VOL_INSTANCE *) AllocateRuntimeZeroPool (BufferSize);\r
+  ASSERT (NULL != mFvbModuleGlobal.FvInstance);\r
+\r
+\r
+  MaxLbaSize      = 0;\r
+  FwhInstance     = mFvbModuleGlobal.FvInstance;\r
+  mFvbModuleGlobal.NumFv   = 0;\r
+\r
+  for (Idx = 0; Idx < 1; Idx++) {\r
+    BaseAddress = mPlatformFvBaseAddress[Idx];\r
+    FwVolHeader = (EFI_FIRMWARE_VOLUME_HEADER *) (UINTN) BaseAddress;\r
+\r
+    if (!IsFvHeaderValid (BaseAddress, FwVolHeader)) {\r
+      FvHeaderValid = FALSE;\r
+      //\r
+      // If not valid, get FvbInfo from the information carried in\r
+      // FVB driver.\r
+      //\r
+      DEBUG ((EFI_D_ERROR, "Fvb: FV header @ 0x%lx invalid\n", BaseAddress));\r
+      Status          = GetFvbInfo (BaseAddress, &FwVolHeader);\r
+      ASSERT_EFI_ERROR(Status);\r
+      //\r
+      //  Write back a healthy FV header.\r
+      //\r
+      DEBUG ((EFI_D_ERROR, "FwBlockService.c: Writing back healthy FV header\n"));\r
+      LibFvbFlashDeviceBlockLock ((UINTN)BaseAddress, FwVolHeader->BlockMap->Length, FALSE);\r
+\r
+      Status = LibFvbFlashDeviceBlockErase ((UINTN)BaseAddress, FwVolHeader->BlockMap->Length);\r
+\r
+      TmpHeaderLength = (UINTN) FwVolHeader->HeaderLength;\r
+      Status = LibFvbFlashDeviceWrite (\r
+                 (UINTN)BaseAddress,\r
+                 &TmpHeaderLength,\r
+                 (UINT8 *) FwVolHeader\r
+                 );\r
+\r
+      LibFvbFlashDeviceBlockLock ((UINTN)BaseAddress, FwVolHeader->BlockMap->Length, TRUE);\r
+\r
+      WriteBackInvalidateDataCacheRange (\r
+        (VOID *) (UINTN) BaseAddress,\r
+        FwVolHeader->BlockMap->Length\r
+        );\r
+\r
+    }\r
+\r
+    CopyMem (&(FwhInstance->VolumeHeader), FwVolHeader, FwVolHeader->HeaderLength);\r
+\r
+    FwVolHeader = &(FwhInstance->VolumeHeader);\r
+    FwhInstance->FvBase = (UINTN)BaseAddress;\r
+\r
+    //\r
+    // Process the block map for each FV.\r
+    //\r
+    FwhInstance->NumOfBlocks = 0;\r
+    for (PtrBlockMapEntry = FwVolHeader->BlockMap; PtrBlockMapEntry->NumBlocks != 0; PtrBlockMapEntry++) {\r
+      //\r
+      // Get the maximum size of a block.\r
+      //\r
+      if (MaxLbaSize < PtrBlockMapEntry->Length) {\r
+        MaxLbaSize  = PtrBlockMapEntry->Length;\r
+      }\r
+      FwhInstance->NumOfBlocks += PtrBlockMapEntry->NumBlocks;\r
+    }\r
+\r
+    //\r
+    // Add a FVB Protocol Instance.\r
+    //\r
+    mFvbModuleGlobal.NumFv++;\r
+    InstallFvbProtocol (FwhInstance, mFvbModuleGlobal.NumFv - 1);\r
+\r
+    //\r
+    // Move on to the next FwhInstance.\r
+    //\r
+    FwhInstance = (EFI_FW_VOL_INSTANCE *) ((UINTN)((UINT8 *)FwhInstance) +\r
+                                          FwVolHeader->HeaderLength +\r
+                                          (sizeof (EFI_FW_VOL_INSTANCE) - sizeof (EFI_FIRMWARE_VOLUME_HEADER)));\r
+\r
+  }\r
+\r
+  return EFI_SUCCESS;\r
+}\r
+\r

diff --git a/Vlv2TbltDevicePkg/FvbRuntimeDxe/FvbService.h b/Vlv2TbltDevicePkg/FvbRuntimeDxe/FvbService.h
new file mode 100644 (file)
index 0000000..cfdb92c
--- /dev/null
+++ b/Vlv2TbltDevicePkg/FvbRuntimeDxe/FvbService.h
@@ -0,0 +1,187 @@
+/** @file\r
+  The header file for Firmware volume block driver.\r
+\r
+Copyright (c) 2006  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+**/\r
+\r
+#ifndef _FW_BLOCK_SERVICE_H\r
+#define _FW_BLOCK_SERVICE_H\r
+\r
+#include <Guid/EventGroup.h>\r
+#include <Guid/FirmwareFileSystem2.h>\r
+#include <Guid/SystemNvDataGuid.h>\r
+#include <Protocol/DevicePath.h>\r
+#include <Protocol/FirmwareVolumeBlock.h>\r
+\r
+#include <Library/UefiDriverEntryPoint.h>\r
+#include <Library/UefiBootServicesTableLib.h>\r
+#include <Library/UefiLib.h>\r
+#include <Library/BaseLib.h>\r
+#include <Library/DebugLib.h>\r
+#include <Library/BaseMemoryLib.h>\r
+#include <Library/IoLib.h>\r
+#include <Library/CacheMaintenanceLib.h>\r
+#include <Library/MemoryAllocationLib.h>\r
+#include <Library/PcdLib.h>\r
+#include <Library/FlashDeviceLib.h>\r
+#include <Library/DevicePathLib.h>\r
+\r
+//\r
+// Define two helper macro to extract the Capability field or Status field in FVB\r
+// bit fields.\r
+//\r
+#define EFI_FVB2_CAPABILITIES (EFI_FVB2_READ_DISABLED_CAP | \\r
+                              EFI_FVB2_READ_ENABLED_CAP | \\r
+                              EFI_FVB2_WRITE_DISABLED_CAP | \\r
+                              EFI_FVB2_WRITE_ENABLED_CAP | \\r
+                              EFI_FVB2_LOCK_CAP \\r
+                              )\r
+\r
+#define EFI_FVB2_STATUS (EFI_FVB2_READ_STATUS | EFI_FVB2_WRITE_STATUS | EFI_FVB2_LOCK_STATUS)\r
+\r
+\r
+typedef struct {\r
+  UINTN                       FvBase;\r
+  UINTN                       NumOfBlocks;\r
+  //\r
+  // Note!!!: VolumeHeader must be the last element\r
+  // of the structure.\r
+  //\r
+  EFI_FIRMWARE_VOLUME_HEADER  VolumeHeader;\r
+} EFI_FW_VOL_INSTANCE;\r
+\r
+typedef struct {\r
+  EFI_FW_VOL_INSTANCE         *FvInstance;\r
+  UINT32                      NumFv;\r
+} FWB_GLOBAL;\r
+\r
+//\r
+// Fvb Protocol instance data.\r
+//\r
+#define FVB_DEVICE_FROM_THIS(a) CR(a, EFI_FW_VOL_BLOCK_DEVICE, FwVolBlockInstance, FVB_DEVICE_SIGNATURE)\r
+#define FVB_EXTEND_DEVICE_FROM_THIS(a) CR(a, EFI_FW_VOL_BLOCK_DEVICE, FvbExtension, FVB_DEVICE_SIGNATURE)\r
+#define FVB_DEVICE_SIGNATURE       SIGNATURE_32('F','V','B','C')\r
+\r
+typedef struct {\r
+  MEDIA_FW_VOL_DEVICE_PATH  FvDevPath;\r
+  EFI_DEVICE_PATH_PROTOCOL  EndDevPath;\r
+} FV_PIWG_DEVICE_PATH;\r
+\r
+typedef struct {\r
+  MEMMAP_DEVICE_PATH          MemMapDevPath;\r
+  EFI_DEVICE_PATH_PROTOCOL    EndDevPath;\r
+} FV_MEMMAP_DEVICE_PATH;\r
+\r
+typedef struct {\r
+  UINT32                                Signature;\r
+  EFI_DEVICE_PATH_PROTOCOL              *DevicePath;\r
+  UINTN                                 Instance;\r
+  EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL    FwVolBlockInstance;\r
+} EFI_FW_VOL_BLOCK_DEVICE;\r
+\r
+EFI_STATUS\r
+GetFvbInfo (\r
+  IN  EFI_PHYSICAL_ADDRESS              FvBaseAddress,\r
+  OUT EFI_FIRMWARE_VOLUME_HEADER        **FvbInfo\r
+  );\r
+\r
+//\r
+// Protocol APIs\r
+//\r
+EFI_STATUS\r
+EFIAPI\r
+FvbProtocolGetAttributes (\r
+  IN CONST EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL   *This,\r
+  OUT EFI_FVB_ATTRIBUTES_2                      *Attributes\r
+  );\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+FvbProtocolSetAttributes (\r
+  IN CONST EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL   *This,\r
+  IN OUT EFI_FVB_ATTRIBUTES_2                   *Attributes\r
+  );\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+FvbProtocolGetPhysicalAddress (\r
+  IN CONST EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL  *This,\r
+       OUT EFI_PHYSICAL_ADDRESS                *Address\r
+  );\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+FvbProtocolGetBlockSize (\r
+  IN CONST EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL  *This,\r
+  IN  EFI_LBA                            Lba,\r
+  OUT UINTN                              *BlockSize,\r
+  OUT UINTN                              *NumOfBlocks\r
+  );\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+FvbProtocolRead (\r
+  IN CONST EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL   *This,\r
+  IN EFI_LBA                              Lba,\r
+  IN UINTN                                Offset,\r
+  IN OUT UINTN                            *NumBytes,\r
+  OUT UINT8                                *Buffer\r
+  );\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+FvbProtocolWrite (\r
+  IN CONST EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL   *This,\r
+  IN EFI_LBA                              Lba,\r
+  IN UINTN                                Offset,\r
+  IN OUT UINTN                            *NumBytes,\r
+  IN UINT8                                *Buffer\r
+  );\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+FvbProtocolEraseBlocks (\r
+  IN CONST EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL    *This,\r
+  ...\r
+  );\r
+\r
+EFI_FW_VOL_INSTANCE *\r
+GetFvbInstance (\r
+  IN  UINTN                              Instance\r
+  );\r
+\r
+BOOLEAN\r
+IsFvHeaderValid (\r
+  IN       EFI_PHYSICAL_ADDRESS          FvBase,\r
+  IN CONST EFI_FIRMWARE_VOLUME_HEADER    *FwVolHeader\r
+  );\r
+\r
+VOID\r
+InstallFvbProtocol (\r
+  IN  EFI_FW_VOL_INSTANCE               *FwhInstance,\r
+  IN  UINTN                             InstanceNum\r
+  );\r
+\r
+EFI_STATUS\r
+FvbInitialize (\r
+  VOID\r
+  );\r
+\r
+extern FWB_GLOBAL              mFvbModuleGlobal;\r
+extern EFI_FW_VOL_BLOCK_DEVICE mFvbDeviceTemplate;\r
+extern FV_MEMMAP_DEVICE_PATH   mFvMemmapDevicePathTemplate;\r
+extern FV_PIWG_DEVICE_PATH     mFvPIWGDevicePathTemplate;\r
+extern UINT32                  mPlatformFvBaseAddress[3];\r
+\r
+#endif\r
+\r

diff --git a/Vlv2TbltDevicePkg/FvbRuntimeDxe/FvbServiceDxe.c b/Vlv2TbltDevicePkg/FvbRuntimeDxe/FvbServiceDxe.c
new file mode 100644 (file)
index 0000000..3b45aa2
--- /dev/null
+++ b/Vlv2TbltDevicePkg/FvbRuntimeDxe/FvbServiceDxe.c
@@ -0,0 +1,204 @@
+/** @file\r
+  Firmware Volume Block Driver for Lakeport Platform.\r
+\r
+  Firmware volume block driver for FWH or SPI device.\r
+  It depends on which Flash Device Library to be linked with this driver.\r
+\r
+Copyright (c) 2006  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+**/\r
+\r
+#include <PiDxe.h>\r
+#include <Library/UefiRuntimeLib.h>\r
+#include "FvbService.h"\r
+\r
+extern FWB_GLOBAL              mFvbModuleGlobal;\r
+\r
+/**\r
+  Call back function on EVT_SIGNAL_VIRTUAL_ADDRESS_CHANGE event.\r
+\r
+  Fixup internal data so that the driver is callable in EFI runtime\r
+  in virtual mode. Convert the mFvbModuleGlobal date items to there\r
+  virtual address.\r
+\r
+  @param  Event     Event whose notification function is being invoked.\r
+  @param  Context   The context of the Notification context. Not used in\r
+                    this call back function.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+FvbVirtualddressChangeEvent (\r
+  IN EFI_EVENT                          Event,\r
+  IN VOID                               *Context\r
+  )\r
+{\r
+  EFI_FW_VOL_INSTANCE                   *FwhInstance;\r
+  UINTN                                 Index;\r
+\r
+  //\r
+  // Convert the base address of all the instances.\r
+  //\r
+  for (Index = 0; Index < mFvbModuleGlobal.NumFv; Index++) {\r
+    FwhInstance = GetFvbInstance (Index);\r
+    EfiConvertPointer (0, (VOID **) &FwhInstance->FvBase);\r
+  }\r
+\r
+  EfiConvertPointer (0, (VOID **) &mFvbModuleGlobal.FvInstance);\r
+}\r
+\r
+\r
+/**\r
+  The function installs EFI_FIRMWARE_VOLUME_BLOCK protocol\r
+  for each FV in the system.\r
+\r
+  @param[in]  FwhInstance   The pointer to a FW volume instance structure,\r
+                            which contains the information about one FV.\r
+  @param[in]  InstanceNum   The instance number which can be used as a ID\r
+                            to locate this FwhInstance in other functions.\r
+\r
+  @retval     VOID\r
+\r
+**/\r
+VOID\r
+InstallFvbProtocol (\r
+  IN  EFI_FW_VOL_INSTANCE               *FwhInstance,\r
+  IN  UINTN                             InstanceNum\r
+  )\r
+{\r
+  EFI_FW_VOL_BLOCK_DEVICE               *FvbDevice;\r
+  EFI_FIRMWARE_VOLUME_HEADER            *FwVolHeader;\r
+  EFI_STATUS                            Status;\r
+  EFI_HANDLE                            FwbHandle;\r
+  EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL    *OldFwbInterface;\r
+\r
+  FvbDevice = (EFI_FW_VOL_BLOCK_DEVICE *) AllocateRuntimeCopyPool (\r
+                                            sizeof (EFI_FW_VOL_BLOCK_DEVICE),\r
+                                            &mFvbDeviceTemplate\r
+                                            );\r
+  ASSERT (FvbDevice != NULL);\r
+\r
+  FvbDevice->Instance = InstanceNum;\r
+  FwVolHeader = &FwhInstance->VolumeHeader;\r
+\r
+  //\r
+  // Set up the devicepath.\r
+  //\r
+  DEBUG ((EFI_D_INFO, "FwBlockService.c: Setting up DevicePath for 0x%lx:\n", FwhInstance->FvBase));\r
+  if (FwVolHeader->ExtHeaderOffset == 0) {\r
+    //\r
+    // FV does not contains extension header, then produce MEMMAP_DEVICE_PATH.\r
+    //\r
+    FvbDevice->DevicePath = (EFI_DEVICE_PATH_PROTOCOL *) AllocateRuntimeCopyPool (sizeof (FV_MEMMAP_DEVICE_PATH), &mFvMemmapDevicePathTemplate);\r
+    ((FV_MEMMAP_DEVICE_PATH *) FvbDevice->DevicePath)->MemMapDevPath.StartingAddress = FwhInstance->FvBase;\r
+    ((FV_MEMMAP_DEVICE_PATH *) FvbDevice->DevicePath)->MemMapDevPath.EndingAddress   = FwhInstance->FvBase + FwVolHeader->FvLength - 1;\r
+  } else {\r
+    FvbDevice->DevicePath = (EFI_DEVICE_PATH_PROTOCOL *) AllocateRuntimeCopyPool (sizeof (FV_PIWG_DEVICE_PATH), &mFvPIWGDevicePathTemplate);\r
+    CopyGuid (\r
+      &((FV_PIWG_DEVICE_PATH *)FvbDevice->DevicePath)->FvDevPath.FvName,\r
+      (GUID *)(UINTN)(FwhInstance->FvBase + FwVolHeader->ExtHeaderOffset)\r
+      );\r
+  }\r
+\r
+  //\r
+  // Find a handle with a matching device path that has supports FW Block protocol.\r
+  //\r
+  Status = gBS->LocateDevicePath (\r
+                  &gEfiFirmwareVolumeBlockProtocolGuid,\r
+                  &FvbDevice->DevicePath,\r
+                  &FwbHandle\r
+                  );\r
+  if (EFI_ERROR (Status) ) {\r
+    //\r
+    // LocateDevicePath fails so install a new interface and device path.\r
+    //\r
+    DEBUG ((EFI_D_INFO, "FwBlockService.c: LocateDevicePath failed, install new interface 0x%lx:\n", FwhInstance->FvBase));\r
+    FwbHandle = NULL;\r
+    Status =  gBS->InstallMultipleProtocolInterfaces (\r
+                     &FwbHandle,\r
+                     &gEfiFirmwareVolumeBlockProtocolGuid,\r
+                     &FvbDevice->FwVolBlockInstance,\r
+                     &gEfiDevicePathProtocolGuid,\r
+                     FvbDevice->DevicePath,\r
+                     NULL\r
+                     );\r
+    ASSERT_EFI_ERROR (Status);\r
+    DEBUG ((EFI_D_INFO, "FwBlockService.c: IMPI FirmwareVolBlockProt, DevPath 0x%lx: %r\n", FwhInstance->FvBase, Status));\r
+\r
+  } else if (IsDevicePathEnd (FvbDevice->DevicePath)) {\r
+    //\r
+    // Device allready exists, so reinstall the FVB protocol.\r
+    //\r
+    DEBUG ((EFI_D_ERROR, "FwBlockService.c: LocateDevicePath succeeded, reinstall interface 0x%lx:\n", FwhInstance->FvBase));\r
+    Status = gBS->HandleProtocol (\r
+                    FwbHandle,\r
+                    &gEfiFirmwareVolumeBlockProtocolGuid,\r
+                    (VOID **) &OldFwbInterface\r
+                    );\r
+    ASSERT_EFI_ERROR (Status);\r
+\r
+    Status =  gBS->ReinstallProtocolInterface (\r
+                     FwbHandle,\r
+                     &gEfiFirmwareVolumeBlockProtocolGuid,\r
+                     OldFwbInterface,\r
+                     &FvbDevice->FwVolBlockInstance\r
+                     );\r
+    ASSERT_EFI_ERROR (Status);\r
+\r
+  } else {\r
+    //\r
+    // There was a FVB protocol on an End Device Path node.\r
+    //\r
+    ASSERT (FALSE);\r
+  }\r
+\r
+}\r
+\r
+\r
+/**\r
+  The driver entry point for Firmware Volume Block Driver.\r
+\r
+  The function does the necessary initialization work for\r
+  Firmware Volume Block Driver.\r
+\r
+  @param[in]  ImageHandle       The firmware allocated handle for the UEFI image.\r
+  @param[in]  SystemTable       A pointer to the EFI system table.\r
+\r
+  @retval     EFI_SUCCESS       This funtion always return EFI_SUCCESS.\r
+                                It will ASSERT on errors.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+DxeFvbInitialize (\r
+  IN EFI_HANDLE                         ImageHandle,\r
+  IN EFI_SYSTEM_TABLE                   *SystemTable\r
+  )\r
+{\r
+  EFI_STATUS                            Status;\r
+  EFI_EVENT                             Event;\r
+\r
+  Status = gBS->CreateEventEx (\r
+                  EVT_NOTIFY_SIGNAL,\r
+                  TPL_NOTIFY,\r
+                  FvbVirtualddressChangeEvent,\r
+                  NULL,\r
+                  &gEfiEventVirtualAddressChangeGuid,\r
+                  &Event\r
+                  );\r
+  ASSERT_EFI_ERROR (Status);\r
+\r
+  FvbInitialize ();\r
+\r
+  return EFI_SUCCESS;\r
+}\r
+\r

diff --git a/Vlv2TbltDevicePkg/FvbRuntimeDxe/FvbServiceSmm.c b/Vlv2TbltDevicePkg/FvbRuntimeDxe/FvbServiceSmm.c
new file mode 100644 (file)
index 0000000..540e9f4
--- /dev/null
+++ b/Vlv2TbltDevicePkg/FvbRuntimeDxe/FvbServiceSmm.c
@@ -0,0 +1,132 @@
+/** @file\r
+  SMM Firmware Volume Block Driver for Lakeport Platform.\r
+\r
+  Firmware volume block driver for FWH or SPI device.\r
+  It depends on which Flash Device Library to be linked with this driver.\r
+\r
+Copyright (c) 2010 - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+**/\r
+\r
+#include <PiSmm.h>\r
+#include <Library/SmmServicesTableLib.h>\r
+#include "FvbSmmCommon.h"\r
+#include "FvbService.h"\r
+\r
+/**\r
+  The function installs EFI_SMM_FIRMWARE_VOLUME_BLOCK protocol\r
+  for each FV in the system.\r
+\r
+  @param[in]  FwhInstance   The pointer to a FW volume instance structure,\r
+                            which contains the information about one FV.\r
+  @param[in]  InstanceNum   The instance number which can be used as a ID\r
+                            to locate this FwhInstance in other functions.\r
+\r
+  @retval     VOID\r
+\r
+**/\r
+VOID\r
+InstallFvbProtocol (\r
+  IN  EFI_FW_VOL_INSTANCE               *FwhInstance,\r
+  IN  UINTN                             InstanceNum\r
+  )\r
+{\r
+  EFI_FW_VOL_BLOCK_DEVICE               *FvbDevice;\r
+  EFI_FIRMWARE_VOLUME_HEADER            *FwVolHeader;\r
+  EFI_STATUS                            Status;\r
+  EFI_HANDLE                            FvbHandle;\r
+\r
+  FvbDevice = (EFI_FW_VOL_BLOCK_DEVICE *) AllocateRuntimeCopyPool (\r
+                                            sizeof (EFI_FW_VOL_BLOCK_DEVICE),\r
+                                            &mFvbDeviceTemplate\r
+                                            );\r
+  ASSERT (FvbDevice != NULL);\r
+\r
+  FvbDevice->Instance = InstanceNum;\r
+  FwVolHeader         = &FwhInstance->VolumeHeader;\r
+\r
+  //\r
+  // Set up the devicepath.\r
+  //\r
+  if (FwVolHeader->ExtHeaderOffset == 0) {\r
+    //\r
+    // FV does not contains extension header, then produce MEMMAP_DEVICE_PATH.\r
+    //\r
+    FvbDevice->DevicePath = (EFI_DEVICE_PATH_PROTOCOL *) AllocateRuntimeCopyPool (sizeof (FV_MEMMAP_DEVICE_PATH), &mFvMemmapDevicePathTemplate);\r
+    ((FV_MEMMAP_DEVICE_PATH *) FvbDevice->DevicePath)->MemMapDevPath.StartingAddress = FwhInstance->FvBase;\r
+    ((FV_MEMMAP_DEVICE_PATH *) FvbDevice->DevicePath)->MemMapDevPath.EndingAddress   = FwhInstance->FvBase + FwVolHeader->FvLength - 1;\r
+  } else {\r
+    FvbDevice->DevicePath = (EFI_DEVICE_PATH_PROTOCOL *) AllocateRuntimeCopyPool (sizeof (FV_PIWG_DEVICE_PATH), &mFvPIWGDevicePathTemplate);\r
+    CopyGuid (\r
+      &((FV_PIWG_DEVICE_PATH *)FvbDevice->DevicePath)->FvDevPath.FvName,\r
+      (GUID *)(UINTN)(FwhInstance->FvBase + FwVolHeader->ExtHeaderOffset)\r
+      );\r
+  }\r
+\r
+  //\r
+  // Install the SMM Firmware Volume Block Protocol and Device Path Protocol.\r
+  //\r
+  FvbHandle = NULL;\r
+  Status = gSmst->SmmInstallProtocolInterface (\r
+                    &FvbHandle,\r
+                    &gEfiSmmFirmwareVolumeBlockProtocolGuid,\r
+                    EFI_NATIVE_INTERFACE,\r
+                    &FvbDevice->FwVolBlockInstance\r
+                    );\r
+  ASSERT_EFI_ERROR (Status);\r
+\r
+  Status = gSmst->SmmInstallProtocolInterface (\r
+                    &FvbHandle,\r
+                    &gEfiDevicePathProtocolGuid,\r
+                    EFI_NATIVE_INTERFACE,\r
+                    FvbDevice->DevicePath\r
+                    );\r
+  ASSERT_EFI_ERROR (Status);\r
+\r
+  //\r
+  // Notify the Fvb wrapper driver SMM fvb is ready.\r
+  //\r
+  FvbHandle = NULL;\r
+  Status = gBS->InstallProtocolInterface (\r
+                  &FvbHandle,\r
+                  &gEfiSmmFirmwareVolumeBlockProtocolGuid,\r
+                  EFI_NATIVE_INTERFACE,\r
+                  &FvbDevice->FwVolBlockInstance\r
+                  );\r
+}\r
+\r
+\r
+/**\r
+  The driver entry point for SMM Firmware Volume Block Driver.\r
+\r
+  The function does the necessary initialization work\r
+  Firmware Volume Block Driver.\r
+\r
+  @param[in]  ImageHandle       The firmware allocated handle for the UEFI image.\r
+  @param[in]  SystemTable       A pointer to the EFI system table.\r
+\r
+  @retval     EFI_SUCCESS       This funtion always return EFI_SUCCESS.\r
+                                It will ASSERT on errors.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+FvbSmmInitialize (\r
+  IN EFI_HANDLE         ImageHandle,\r
+  IN EFI_SYSTEM_TABLE   *SystemTable\r
+  )\r
+{\r
+  FvbInitialize ();\r
+\r
+  return EFI_SUCCESS;\r
+}\r
+\r

diff --git a/Vlv2TbltDevicePkg/FvbRuntimeDxe/FvbSmm.inf b/Vlv2TbltDevicePkg/FvbRuntimeDxe/FvbSmm.inf
new file mode 100644 (file)
index 0000000..718ae0b
--- /dev/null
+++ b/Vlv2TbltDevicePkg/FvbRuntimeDxe/FvbSmm.inf
@@ -0,0 +1,87 @@
+## @file\r
+# This driver implement the EFI_SMM_FIRMWARE_VOLUMEN_PROTOCOL.\r
+#\r
+# Copyright (c) 2010 - 2014, Intel Corporation. All rights reserved.<BR>\r
+#                                                                                  \r\r
+# This program and the accompanying materials are licensed and made available under\r\r
+# the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+# The full text of the license may be found at                                     \r\r
+# http://opensource.org/licenses/bsd-license.php.                                  \r\r
+#                                                                                  \r\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+#                                                                                  \r\r
+#\r
+#\r
+#\r
+##\r
+\r
+[Defines]\r
+  INF_VERSION                    = 0x00010005\r
+  BASE_NAME                      = FvbSmm\r
+  FILE_GUID                      = A4EC8ADB-B7A8-47d1-8E52-EC820D0ACF6F\r
+  MODULE_TYPE                    = DXE_SMM_DRIVER\r
+  VERSION_STRING                 = 1.0\r
+  PI_SPECIFICATION_VERSION       = 0x0001000A\r
+  ENTRY_POINT                    = FvbSmmInitialize\r
+\r
+#\r
+# The following information is for reference only and not required by the build tools.\r
+#\r
+#  VALID_ARCHITECTURES           = IA32 X64\r
+#\r
+#  VIRTUAL_ADDRESS_MAP_CALLBACK  =  FvbVirtualddressChangeEvent\r
+#\r
+\r
+[Sources]\r
+  FvbInfo.c\r
+  FvbService.h\r
+  FvbService.c\r
+  FvbServiceSmm.c\r
+  FvbSmmCommon.h\r
+\r
+[Packages]\r
+  MdePkg/MdePkg.dec\r
+  MdeModulePkg/MdeModulePkg.dec\r
+  Vlv2TbltDevicePkg/PlatformPkg.dec\r
+  Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec\r
+\r
+[LibraryClasses]\r
+  FlashDeviceLib\r
+  PcdLib\r
+  MemoryAllocationLib\r
+  CacheMaintenanceLib\r
+  IoLib\r
+  BaseMemoryLib\r
+  DebugLib\r
+  BaseLib\r
+  UefiLib\r
+  SmmLib\r
+  SmmServicesTableLib\r
+  UefiBootServicesTableLib\r
+  UefiDriverEntryPoint\r
+\r
+[Guids]\r
+  gEfiFirmwareFileSystem2Guid                   # ALWAYS_CONSUMED\r
+  gEfiSystemNvDataFvGuid                        # ALWAYS_CONSUMED\r
+  gEfiEventVirtualAddressChangeGuid\r
+\r
+[Protocols]\r
+  gEfiDevicePathProtocolGuid                    # PROTOCOL ALWAYS_PRODUCED\r
+  gEfiSmmFirmwareVolumeBlockProtocolGuid        # PROTOCOL ALWAYS_PRODUCED\r
+\r
+[FixedPcd]\r
+  gPlatformModuleTokenSpaceGuid.PcdFlashFvMainBase\r
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase\r
+  gPlatformModuleTokenSpaceGuid.PcdFlashFvRecoveryBase\r
+\r
+[Pcd]\r
+  gPlatformModuleTokenSpaceGuid.PcdFlashFvMainSize\r
+  gPlatformModuleTokenSpaceGuid.PcdFlashFvRecoverySize\r
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize\r
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize\r
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize\r
+\r
+[Depex]\r
+  gEfiSmmSpiProtocolGuid\r
+\r

diff --git a/Vlv2TbltDevicePkg/FvbRuntimeDxe/FvbSmmCommon.h b/Vlv2TbltDevicePkg/FvbRuntimeDxe/FvbSmmCommon.h
new file mode 100644 (file)
index 0000000..5660e0b
--- /dev/null
+++ b/Vlv2TbltDevicePkg/FvbRuntimeDxe/FvbSmmCommon.h
@@ -0,0 +1,78 @@
+/** @file\r
+\r
+  The common header file for SMM FVB module and SMM FVB runtime Module.\r
+\r
+Copyright (c) 2010 - 2014, Intel Corporation. All rights reserved. <BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+**/\r
+\r
+#ifndef _SMM_FVB_COMMON_H_\r
+#define _SMM_FVB_COMMON_H_\r
+\r
+#include <Protocol/SmmFirmwareVolumeBlock.h>\r
+\r
+#define EFI_FUNCTION_GET_ATTRIBUTES           1\r
+#define EFI_FUNCTION_SET_ATTRIBUTES           2\r
+#define EFI_FUNCTION_GET_PHYSICAL_ADDRESS     3\r
+#define EFI_FUNCTION_GET_BLOCK_SIZE           4\r
+#define EFI_FUNCTION_READ                     5\r
+#define EFI_FUNCTION_WRITE                    6\r
+#define EFI_FUNCTION_ERASE_BLOCKS             7\r
+\r
+typedef struct {\r
+  UINTN       Function;\r
+  EFI_STATUS  ReturnStatus;\r
+  UINT8       Data[1];\r
+} SMM_FVB_COMMUNICATE_FUNCTION_HEADER;\r
+\r
+\r
+///\r
+/// Size of SMM communicate header, without including the payload.\r
+///\r
+#define SMM_COMMUNICATE_HEADER_SIZE  (OFFSET_OF (EFI_SMM_COMMUNICATE_HEADER, Data))\r
+\r
+///\r
+/// Size of SMM FVB communicate function header, without including the payload.\r
+///\r
+#define SMM_FVB_COMMUNICATE_HEADER_SIZE  (OFFSET_OF (SMM_FVB_COMMUNICATE_FUNCTION_HEADER, Data))\r
+\r
+typedef struct {\r
+  EFI_SMM_FIRMWARE_VOLUME_BLOCK_PROTOCOL     *SmmFvb;\r
+  EFI_FVB_ATTRIBUTES_2                       Attributes;\r
+} SMM_FVB_ATTRIBUTES_HEADER;\r
+\r
+typedef struct {\r
+  EFI_SMM_FIRMWARE_VOLUME_BLOCK_PROTOCOL     *SmmFvb;\r
+  EFI_PHYSICAL_ADDRESS                       Address;\r
+} SMM_FVB_PHYSICAL_ADDRESS_HEADER;\r
+\r
+typedef struct {\r
+  EFI_SMM_FIRMWARE_VOLUME_BLOCK_PROTOCOL     *SmmFvb;\r
+  EFI_LBA                                    Lba;\r
+  UINTN                                      BlockSize;\r
+  UINTN                                      NumOfBlocks;\r
+} SMM_FVB_BLOCK_SIZE_HEADER;\r
+\r
+typedef struct {\r
+  EFI_SMM_FIRMWARE_VOLUME_BLOCK_PROTOCOL     *SmmFvb;\r
+  EFI_LBA                                    Lba;\r
+  UINTN                                      Offset;\r
+  UINTN                                      NumBytes;\r
+} SMM_FVB_READ_WRITE_HEADER;\r
+\r
+typedef struct {\r
+  EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL         *SmmFvb;\r
+  EFI_LBA                                    StartLba;\r
+  UINTN                                      NumOfLba;\r
+} SMM_FVB_BLOCKS_HEADER;\r
+\r
+#endif\r

diff --git a/Vlv2TbltDevicePkg/FvbRuntimeDxe/FvbSmmDxe.c b/Vlv2TbltDevicePkg/FvbRuntimeDxe/FvbSmmDxe.c
new file mode 100644 (file)
index 0000000..20aaf87
--- /dev/null
+++ b/Vlv2TbltDevicePkg/FvbRuntimeDxe/FvbSmmDxe.c
@@ -0,0 +1,949 @@
+/** @file\r
+\r
+  Implement the Firmware Volume Block (FVB) services based on SMM FVB\r
+  module and install FVB protocol.\r
+\r
+Copyright (c) 2010  - 2014, Intel Corporation. All rights reserved. <BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+**/\r
+\r
+#include "FvbSmmDxe.h"\r
+\r
+EFI_HANDLE                       mHandle           = NULL;\r
+EFI_SMM_COMMUNICATION_PROTOCOL  *mSmmCommunication = NULL;\r
+\r
+//\r
+// Template structure used when installing FVB protocol.\r
+//\r
+EFI_FVB_DEVICE    mFvbDeviceTemplate = {\r
+  FVB_DEVICE_SIGNATURE,\r
+  NULL,\r
+  {\r
+    FvbGetAttributes,\r
+    FvbSetAttributes,\r
+    FvbGetPhysicalAddress,\r
+    FvbGetBlockSize,\r
+    FvbRead,\r
+    FvbWrite,\r
+    FvbEraseBlocks,\r
+    NULL\r
+  },\r
+  NULL\r
+};\r
+\r
+FV_MEMMAP_DEVICE_PATH mFvMemmapDevicePathTemplate = {\r
+  {\r
+    {\r
+      HARDWARE_DEVICE_PATH,\r
+      HW_MEMMAP_DP,\r
+      {\r
+        (UINT8)(sizeof (MEMMAP_DEVICE_PATH)),\r
+        (UINT8)(sizeof (MEMMAP_DEVICE_PATH) >> 8)\r
+      }\r
+    },\r
+    EfiMemoryMappedIO,\r
+    (EFI_PHYSICAL_ADDRESS) 0,\r
+    (EFI_PHYSICAL_ADDRESS) 0,\r
+  },\r
+  {\r
+    END_DEVICE_PATH_TYPE,\r
+    END_ENTIRE_DEVICE_PATH_SUBTYPE,\r
+    {\r
+      END_DEVICE_PATH_LENGTH,\r
+      0\r
+    }\r
+  }\r
+};\r
+\r
+FV_PIWG_DEVICE_PATH mFvPIWGDevicePathTemplate = {\r
+  {\r
+    {\r
+      MEDIA_DEVICE_PATH,\r
+      MEDIA_PIWG_FW_VOL_DP,\r
+      {\r
+        (UINT8)(sizeof (MEDIA_FW_VOL_DEVICE_PATH)),\r
+        (UINT8)(sizeof (MEDIA_FW_VOL_DEVICE_PATH) >> 8)\r
+      }\r
+    },\r
+    { 0 }\r
+  },\r
+  {\r
+    END_DEVICE_PATH_TYPE,\r
+    END_ENTIRE_DEVICE_PATH_SUBTYPE,\r
+    {\r
+      END_DEVICE_PATH_LENGTH,\r
+      0\r
+    }\r
+  }\r
+};\r
+\r
+/**\r
+  Initialize the communicate buffer using DataSize and Function.\r
+\r
+  The communicate size is: SMM_COMMUNICATE_HEADER_SIZE + SMM_VARIABLE_COMMUNICATE_HEADER_SIZE +\r
+  DataSize.\r
+\r
+  @param[out]      CommunicateBuffer The communicate buffer. Caller should free it after use.\r
+  @param[out]      DataPtr           Points to the data in the communicate buffer. Caller should not free it.\r
+  @param[in]       DataSize          The payload size.\r
+  @param[in]       Function          The function number used to initialize the communicate header.\r
+\r
+  @retval EFI_INVALID_PARAMETER      The data size is too big.\r
+  @retval EFI_SUCCESS                Find the specified variable.\r
+\r
+**/\r
+EFI_STATUS\r
+InitCommunicateBuffer (\r
+  OUT     VOID                              **CommunicateBuffer,\r
+  OUT     VOID                              **DataPtr,\r
+  IN      UINTN                             DataSize,\r
+  IN      UINTN                             Function\r
+  )\r
+{\r
+  EFI_SMM_COMMUNICATE_HEADER                *SmmCommunicateHeader;\r
+  SMM_FVB_COMMUNICATE_FUNCTION_HEADER       *SmmFvbFunctionHeader;\r
+\r
+  //\r
+  // The whole buffer size: SMM_COMMUNICATE_HEADER_SIZE + SMM_FVB_COMMUNICATE_HEADER_SIZE + DataSize.\r
+  //\r
+  SmmCommunicateHeader = AllocatePool (DataSize + SMM_COMMUNICATE_HEADER_SIZE + SMM_FVB_COMMUNICATE_HEADER_SIZE);\r
+  ASSERT (SmmCommunicateHeader != NULL);\r
+\r
+  //\r
+  // Prepare data buffer.\r
+  //\r
+  CopyGuid (&SmmCommunicateHeader->HeaderGuid, &gEfiSmmFirmwareVolumeBlockProtocolGuid);\r
+  SmmCommunicateHeader->MessageLength = DataSize + SMM_FVB_COMMUNICATE_HEADER_SIZE;\r
+\r
+  SmmFvbFunctionHeader = (SMM_FVB_COMMUNICATE_FUNCTION_HEADER *) SmmCommunicateHeader->Data;\r
+  SmmFvbFunctionHeader->Function = Function;\r
+\r
+  *CommunicateBuffer = SmmCommunicateHeader;\r
+  *DataPtr = SmmFvbFunctionHeader->Data;\r
+\r
+  return EFI_SUCCESS;\r
+}\r
+\r
+\r
+/**\r
+  Send the data in communicate buffer to SMM.\r
+\r
+  @param[out]      SmmCommunicateHeader    The communicate buffer.\r
+  @param[in]       DataSize                The payload size.\r
+\r
+**/\r
+EFI_STATUS\r
+SendCommunicateBuffer (\r
+  IN      EFI_SMM_COMMUNICATE_HEADER        *SmmCommunicateHeader,\r
+  IN      UINTN                             DataSize\r
+  )\r
+{\r
+  EFI_STATUS                                Status;\r
+  UINTN                                     CommSize;\r
+  SMM_FVB_COMMUNICATE_FUNCTION_HEADER       *SmmFvbFunctionHeader;\r
+\r
+  CommSize = DataSize + SMM_COMMUNICATE_HEADER_SIZE + SMM_FVB_COMMUNICATE_HEADER_SIZE;\r
+  Status = mSmmCommunication->Communicate (\r
+                                mSmmCommunication,\r
+                                SmmCommunicateHeader,\r
+                                &CommSize\r
+                                );\r
+  ASSERT_EFI_ERROR (Status);\r
+\r
+  SmmFvbFunctionHeader = (SMM_FVB_COMMUNICATE_FUNCTION_HEADER *) SmmCommunicateHeader->Data;\r
+  return  SmmFvbFunctionHeader->ReturnStatus;\r
+}\r
+\r
+/**\r
+  This function retrieves the attributes and current settings of the block.\r
+\r
+  @param[in]  This       Indicates the EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL instance.\r
+\r
+  @param[out] Attributes Pointer to EFI_FVB_ATTRIBUTES_2 in which the attributes\r
+                         and current settings are returned. Type EFI_FVB_ATTRIBUTES_2\r
+                         is defined in EFI_FIRMWARE_VOLUME_HEADER.\r
+\r
+  @retval EFI_SUCCESS              The firmware volume attributes were returned.\r
+  @retval EFI_INVALID_PARAMETER    Attributes is NULL.\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+FvbGetAttributes (\r
+  IN CONST EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL   *This,\r
+     OUT   EFI_FVB_ATTRIBUTES_2                 *Attributes\r
+  )\r
+{\r
+  EFI_STATUS                                    Status;\r
+  UINTN                                         PayloadSize;\r
+  EFI_SMM_COMMUNICATE_HEADER                    *SmmCommunicateHeader;\r
+  SMM_FVB_ATTRIBUTES_HEADER                     *SmmFvbAttributesHeader;\r
+  EFI_SMM_FIRMWARE_VOLUME_BLOCK_PROTOCOL        *SmmFvb;\r
+  EFI_FVB_DEVICE                                *FvbDevice;\r
+\r
+  if (Attributes == NULL) {\r
+    return EFI_INVALID_PARAMETER;\r
+  }\r
+\r
+  FvbDevice = FVB_DEVICE_FROM_THIS (This);\r
+  SmmFvb    = FvbDevice->SmmFvbInstance;\r
+\r
+  //\r
+  // Initialize the communicate buffer.\r
+  //\r
+  PayloadSize  = sizeof (SMM_FVB_ATTRIBUTES_HEADER);\r
+  Status = InitCommunicateBuffer (\r
+             (VOID **)&SmmCommunicateHeader,\r
+             (VOID **)&SmmFvbAttributesHeader,\r
+             PayloadSize,\r
+             EFI_FUNCTION_GET_ATTRIBUTES\r
+             );\r
+  if (EFI_ERROR (Status)) {\r
+    return Status;\r
+  }\r
+\r
+  SmmFvbAttributesHeader->SmmFvb     = SmmFvb;\r
+  SmmFvbAttributesHeader->Attributes = 0;\r
+\r
+  //\r
+  // Send data to SMM.\r
+  //\r
+  Status = SendCommunicateBuffer (SmmCommunicateHeader, PayloadSize);\r
+\r
+  //\r
+  // Get data from SMM.\r
+  //\r
+  *Attributes = SmmFvbAttributesHeader->Attributes;\r
+  FreePool (SmmCommunicateHeader);\r
+\r
+  return Status;\r
+}\r
+\r
+\r
+/**\r
+  Sets Volume attributes. No polarity translations are done.\r
+\r
+  @param[in]  This        Calling context.\r
+  @param[out] Attributes  Output buffer which contains attributes.\r
+\r
+  @retval     EFI_SUCCESS              Set the Attributes successfully.\r
+  @retval     EFI_INVALID_PARAMETER    Attributes is NULL.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+FvbSetAttributes (\r
+  IN CONST EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL   *This,\r
+  IN OUT   EFI_FVB_ATTRIBUTES_2                 *Attributes\r
+  )\r
+{\r
+  EFI_STATUS                                    Status;\r
+  UINTN                                         PayloadSize;\r
+  EFI_SMM_COMMUNICATE_HEADER                    *SmmCommunicateHeader;\r
+  SMM_FVB_ATTRIBUTES_HEADER                     *SmmFvbAttributesHeader;\r
+  EFI_SMM_FIRMWARE_VOLUME_BLOCK_PROTOCOL        *SmmFvb;\r
+  EFI_FVB_DEVICE                                *FvbDevice;\r
+\r
+  if (Attributes == NULL) {\r
+    return EFI_INVALID_PARAMETER;\r
+  }\r
+\r
+  FvbDevice = FVB_DEVICE_FROM_THIS (This);\r
+  SmmFvb    = FvbDevice->SmmFvbInstance;\r
+\r
+  //\r
+  // Initialize the communicate buffer.\r
+  //\r
+  PayloadSize  = sizeof (SMM_FVB_ATTRIBUTES_HEADER);\r
+  Status = InitCommunicateBuffer (\r
+             (VOID **)&SmmCommunicateHeader,\r
+             (VOID **)&SmmFvbAttributesHeader,\r
+             PayloadSize,\r
+             EFI_FUNCTION_SET_ATTRIBUTES\r
+             );\r
+  if (EFI_ERROR (Status)) {\r
+    return Status;\r
+  }\r
+\r
+  SmmFvbAttributesHeader->SmmFvb     = SmmFvb;\r
+  SmmFvbAttributesHeader->Attributes = *Attributes;\r
+\r
+  //\r
+  // Send data to SMM.\r
+  //\r
+  Status = SendCommunicateBuffer (SmmCommunicateHeader, PayloadSize);\r
+\r
+  //\r
+  // Get data from SMM.\r
+  //\r
+  *Attributes = SmmFvbAttributesHeader->Attributes;\r
+  FreePool (SmmCommunicateHeader);\r
+\r
+  return Status;\r
+}\r
+\r
+\r
+/**\r
+  Retrieves the physical address of the FVB instance.\r
+\r
+  @param[in]  SmmFvb         A pointer to EFI_SMM_FIRMWARE_VOLUME_BLOCK_PROTOCOL.\r
+  @param[out] Address        Output buffer containing the address.\r
+\r
+  @retval     EFI_SUCCESS    Get the address successfully.\r
+  @retval     Others         Failed to get address.\r
+\r
+**/\r
+EFI_STATUS\r
+GetPhysicalAddress (\r
+  IN   EFI_SMM_FIRMWARE_VOLUME_BLOCK_PROTOCOL  *SmmFvb,\r
+  OUT  EFI_PHYSICAL_ADDRESS                    *Address\r
+  )\r
+{\r
+  EFI_STATUS                                   Status;\r
+  UINTN                                        PayloadSize;\r
+  EFI_SMM_COMMUNICATE_HEADER                   *SmmCommunicateHeader;\r
+  SMM_FVB_PHYSICAL_ADDRESS_HEADER              *SmmFvbPhysicalAddressHeader;\r
+\r
+  //\r
+  // Initialize the communicate buffer.\r
+  //\r
+  PayloadSize  = sizeof (SMM_FVB_PHYSICAL_ADDRESS_HEADER);\r
+  Status = InitCommunicateBuffer (\r
+             (VOID **)&SmmCommunicateHeader,\r
+             (VOID **)&SmmFvbPhysicalAddressHeader,\r
+             PayloadSize,\r
+             EFI_FUNCTION_GET_PHYSICAL_ADDRESS\r
+             );\r
+  if (EFI_ERROR (Status)) {\r
+    return Status;\r
+  }\r
+\r
+  SmmFvbPhysicalAddressHeader->SmmFvb  = SmmFvb;\r
+  SmmFvbPhysicalAddressHeader->Address = 0;\r
+\r
+  //\r
+  // Send data to SMM.\r
+  //\r
+  Status = SendCommunicateBuffer (SmmCommunicateHeader, PayloadSize);\r
+\r
+  //\r
+  // Get data from SMM.\r
+  //\r
+  *Address = SmmFvbPhysicalAddressHeader->Address;\r
+  FreePool (SmmCommunicateHeader);\r
+\r
+  return Status;\r
+}\r
+\r
+\r
+/**\r
+  Retrieves the physical address of the FVB instance.\r
+\r
+  @param[in]  This                     A pointer to EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL.\r
+  @param[out] Address                  Output buffer containing the address.\r
+\r
+  @retval     EFI_SUCCESS              Get the address successfully.\r
+  @retval     Others                   Failed to get the address.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+FvbGetPhysicalAddress (\r
+  IN CONST EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL  *This,\r
+     OUT   EFI_PHYSICAL_ADDRESS                *Address\r
+  )\r
+{\r
+  EFI_STATUS                                   Status;\r
+  EFI_SMM_FIRMWARE_VOLUME_BLOCK_PROTOCOL       *SmmFvb;\r
+  EFI_FVB_DEVICE                               *FvbDevice;\r
+\r
+  if (Address == NULL) {\r
+    return EFI_INVALID_PARAMETER;\r
+  }\r
+\r
+  FvbDevice = FVB_DEVICE_FROM_THIS (This);\r
+  SmmFvb    = FvbDevice->SmmFvbInstance;\r
+\r
+  Status = GetPhysicalAddress (SmmFvb, Address);\r
+\r
+  return Status;\r
+}\r
+\r
+\r
+/**\r
+  Retrieve the size of a logical block.\r
+\r
+  @param[in]  This        Calling context.\r
+  @param[in]  Lba         Indicates which block to return the size for.\r
+  @param[out] BlockSize   A pointer to a caller allocated UINTN in which\r
+                          the size of the block is returned.\r
+  @param[out] NumOfBlocks A pointer to a caller allocated UINTN in which the\r
+                          number of consecutive blocks starting with Lba is\r
+                          returned. All blocks in this range have a size of\r
+                          BlockSize.\r
+\r
+  @retval     EFI_SUCCESS              Get BlockSize and NumOfBlocks successfully.\r
+  @retval     EFI_INVALID_PARAMETER    BlockSize or NumOfBlocks are NULL.\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+FvbGetBlockSize (\r
+  IN CONST EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL  *This,\r
+  IN       EFI_LBA                             Lba,\r
+     OUT   UINTN                               *BlockSize,\r
+     OUT   UINTN                               *NumOfBlocks\r
+  )\r
+{\r
+  EFI_STATUS                                   Status;\r
+  UINTN                                        PayloadSize;\r
+  EFI_SMM_COMMUNICATE_HEADER                   *SmmCommunicateHeader;\r
+  SMM_FVB_BLOCK_SIZE_HEADER                    *SmmFvbBlockSizeHeader;\r
+  EFI_SMM_FIRMWARE_VOLUME_BLOCK_PROTOCOL       *SmmFvb;\r
+  EFI_FVB_DEVICE                               *FvbDevice;\r
+\r
+  if ((BlockSize == NULL) || (NumOfBlocks == NULL)) {\r
+    return EFI_INVALID_PARAMETER;\r
+  }\r
+\r
+  FvbDevice = FVB_DEVICE_FROM_THIS (This);\r
+  SmmFvb    = FvbDevice->SmmFvbInstance;\r
+\r
+  //\r
+  // Initialize the communicate buffer.\r
+  //\r
+  PayloadSize  = sizeof (SMM_FVB_BLOCK_SIZE_HEADER);\r
+  Status = InitCommunicateBuffer (\r
+             (VOID **)&SmmCommunicateHeader,\r
+             (VOID **)&SmmFvbBlockSizeHeader,\r
+             PayloadSize,\r
+             EFI_FUNCTION_GET_BLOCK_SIZE\r
+             );\r
+  if (EFI_ERROR (Status)) {\r
+    return Status;\r
+  }\r
+\r
+  SmmFvbBlockSizeHeader->SmmFvb = SmmFvb;\r
+  SmmFvbBlockSizeHeader->Lba    = Lba;\r
+\r
+  //\r
+  // Send data to SMM.\r
+  //\r
+  Status = SendCommunicateBuffer (SmmCommunicateHeader, PayloadSize);\r
+\r
+  //\r
+  // Get data from SMM.\r
+  //\r
+  *BlockSize   = SmmFvbBlockSizeHeader->BlockSize;\r
+  *NumOfBlocks = SmmFvbBlockSizeHeader->NumOfBlocks;\r
+  FreePool (SmmCommunicateHeader);\r
+\r
+  return Status;\r
+}\r
+\r
+\r
+/**\r
+  Reads data beginning at Lba:Offset from FV. The Read terminates either\r
+  when *NumBytes of data have been read, or when a block boundary is\r
+  reached.  *NumBytes is updated to reflect the actual number of bytes\r
+  written. The write opertion does not include erase. This routine will\r
+  attempt to write only the specified bytes. If the writes do not stick,\r
+  it will return an error.\r
+\r
+  @param[in]      This           Calling context\r
+  @param[in]      Lba            Block in which to begin write\r
+  @param[in]      Offset         Offset in the block at which to begin write\r
+  @param[in,out]  NumBytes       On input, indicates the requested write size. On\r
+                                 output, indicates the actual number of bytes written\r
+  @param[in]      Buffer         Buffer containing source data for the write.\r
+\r
+  @retval EFI_SUCCESS            The firmware volume was read successfully and\r
+                                 contents are in Buffer.\r
+  @retval EFI_BAD_BUFFER_SIZE    Read attempted across a LBA boundary. On output,\r
+                                 NumBytes contains the total number of bytes returned\r
+                                 in Buffer.\r
+  @retval EFI_ACCESS_DENIED      The firmware volume is in the ReadDisabled state\r
+  @retval EFI_DEVICE_ERROR       The block device is not functioning correctly and\r
+                                 could not be read.\r
+  @retval EFI_INVALID_PARAMETER  NumBytes or Buffer are NULL.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+FvbRead (\r
+  IN CONST EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL   *This,\r
+  IN       EFI_LBA                              Lba,\r
+  IN       UINTN                                Offset,\r
+  IN OUT   UINTN                                *NumBytes,\r
+     OUT   UINT8                                *Buffer\r
+  )\r
+{\r
+  EFI_STATUS                                    Status;\r
+  UINTN                                         PayloadSize;\r
+  EFI_SMM_COMMUNICATE_HEADER                    *SmmCommunicateHeader;\r
+  SMM_FVB_READ_WRITE_HEADER                     *SmmFvbReadWriteHeader;\r
+  EFI_SMM_FIRMWARE_VOLUME_BLOCK_PROTOCOL        *SmmFvb;\r
+  EFI_FVB_DEVICE                                *FvbDevice;\r
+\r
+  if ((NumBytes == NULL) || (Buffer == NULL)) {\r
+    return EFI_INVALID_PARAMETER;\r
+  }\r
+\r
+  FvbDevice = FVB_DEVICE_FROM_THIS (This);\r
+  SmmFvb    = FvbDevice->SmmFvbInstance;\r
+\r
+  //\r
+  // Initialize the communicate buffer.\r
+  //\r
+  PayloadSize  = sizeof (SMM_FVB_READ_WRITE_HEADER) + *NumBytes;\r
+  Status = InitCommunicateBuffer (\r
+             (VOID **)&SmmCommunicateHeader,\r
+             (VOID **)&SmmFvbReadWriteHeader,\r
+             PayloadSize, EFI_FUNCTION_READ\r
+             );\r
+  if (EFI_ERROR (Status)) {\r
+    return Status;\r
+  }\r
+\r
+  SmmFvbReadWriteHeader->SmmFvb   = SmmFvb;\r
+  SmmFvbReadWriteHeader->Lba      = Lba;\r
+  SmmFvbReadWriteHeader->Offset   = Offset;\r
+  SmmFvbReadWriteHeader->NumBytes = *NumBytes;\r
+\r
+  //\r
+  // Send data to SMM.\r
+  //\r
+  Status = SendCommunicateBuffer (SmmCommunicateHeader, PayloadSize);\r
+\r
+  //\r
+  // Get data from SMM.\r
+  //\r
+  *NumBytes = SmmFvbReadWriteHeader->NumBytes;\r
+  if (!EFI_ERROR (Status)) {\r
+    CopyMem (Buffer, (UINT8 *)(SmmFvbReadWriteHeader + 1), *NumBytes);\r
+  }\r
+  FreePool (SmmCommunicateHeader);\r
+\r
+  return Status;\r
+}\r
+\r
+\r
+/**\r
+  Writes data beginning at Lba:Offset from FV. The write terminates either\r
+  when *NumBytes of data have been written, or when a block boundary is\r
+  reached.  *NumBytes is updated to reflect the actual number of bytes\r
+  written. The write opertion does not include erase. This routine will\r
+  attempt to write only the specified bytes. If the writes do not stick,\r
+  it will return an error.\r
+\r
+  @param[in]      This           Calling context.\r
+  @param[in]      Lba            Block in which to begin write.\r
+  @param[in]      Offset         Offset in the block at which to begin write.\r
+  @param[in,out]  NumBytes       On input, indicates the requested write size. On\r
+                                 output, indicates the actual number of bytes written.\r
+  @param[in]      Buffer         Buffer containing source data for the write.\r
+\r
+  @retval EFI_SUCCESS            The firmware volume was written successfully.\r
+  @retval EFI_BAD_BUFFER_SIZE    Write attempted across a LBA boundary. On output,\r
+                                 NumBytes contains the total number of bytes\r
+                                 actually written.\r
+  @retval EFI_ACCESS_DENIED      The firmware volume is in the WriteDisabled state.\r
+  @retval EFI_DEVICE_ERROR       The block device is not functioning correctly and\r
+                                 could not be written.\r
+  @retval EFI_INVALID_PARAMETER  NumBytes or Buffer are NULL.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+FvbWrite (\r
+  IN CONST EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL   *This,\r
+  IN       EFI_LBA                              Lba,\r
+  IN       UINTN                                Offset,\r
+  IN OUT   UINTN                                *NumBytes,\r
+  IN       UINT8                                *Buffer\r
+  )\r
+{\r
+  EFI_STATUS                                    Status;\r
+  UINTN                                         PayloadSize;\r
+  EFI_SMM_COMMUNICATE_HEADER                    *SmmCommunicateHeader;\r
+  SMM_FVB_READ_WRITE_HEADER                     *SmmFvbReadWriteHeader;\r
+  EFI_SMM_FIRMWARE_VOLUME_BLOCK_PROTOCOL        *SmmFvb;\r
+  EFI_FVB_DEVICE                                *FvbDevice;\r
+\r
+  if ((NumBytes == NULL) || (Buffer == NULL)) {\r
+    return EFI_INVALID_PARAMETER;\r
+  }\r
+\r
+  FvbDevice = FVB_DEVICE_FROM_THIS (This);\r
+  SmmFvb    = FvbDevice->SmmFvbInstance;\r
+\r
+  //\r
+  // Initialize the communicate buffer.\r
+  //\r
+  PayloadSize  = sizeof (SMM_FVB_READ_WRITE_HEADER) + *NumBytes;\r
+  Status = InitCommunicateBuffer (\r
+             (VOID **)&SmmCommunicateHeader,\r
+             (VOID **)&SmmFvbReadWriteHeader,\r
+             PayloadSize,\r
+             EFI_FUNCTION_WRITE\r
+             );\r
+  if (EFI_ERROR (Status)) {\r
+    return Status;\r
+  }\r
+\r
+  SmmFvbReadWriteHeader->SmmFvb   = SmmFvb;\r
+  SmmFvbReadWriteHeader->Lba      = Lba;\r
+  SmmFvbReadWriteHeader->Offset   = Offset;\r
+  SmmFvbReadWriteHeader->NumBytes = *NumBytes;\r
+  CopyMem ((UINT8 *)(SmmFvbReadWriteHeader + 1), Buffer, *NumBytes);\r
+\r
+  //\r
+  // Send data to SMM.\r
+  //\r
+  Status = SendCommunicateBuffer (SmmCommunicateHeader, PayloadSize);\r
+\r
+  //\r
+  // Get data from SMM.\r
+  //\r
+  *NumBytes = SmmFvbReadWriteHeader->NumBytes;\r
+  FreePool (SmmCommunicateHeader);\r
+\r
+  return Status;\r
+}\r
+\r
+\r
+/**\r
+  The EraseBlock() function erases NumOfLba blocks started from StartingLba.\r
+\r
+  @param[in] This            Calling context.\r
+  @param[in] StartingLba     Starting LBA followed to erase.\r
+  @param[in] NumOfLba        Number of block to erase.\r
+\r
+  @retval EFI_SUCCESS        The erase request was successfully completed.\r
+  @retval EFI_ACCESS_DENIED  The firmware volume is in the WriteDisabled state.\r
+  @retval EFI_DEVICE_ERROR   The block device is not functioning correctly and\r
+                             could not be written. Firmware device may have been\r
+                             partially erased.\r
+\r
+**/\r
+EFI_STATUS\r
+EraseBlock (\r
+  IN CONST EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL    *This,\r
+  IN       EFI_LBA                               StartingLba,\r
+  IN       UINTN                                 NumOfLba\r
+  )\r
+{\r
+  EFI_STATUS                                     Status;\r
+  UINTN                                          PayloadSize;\r
+  EFI_SMM_COMMUNICATE_HEADER                    *SmmCommunicateHeader;\r
+  SMM_FVB_BLOCKS_HEADER                         *SmmFvbBlocksHeader;\r
+  EFI_SMM_FIRMWARE_VOLUME_BLOCK_PROTOCOL        *SmmFvb;\r
+  EFI_FVB_DEVICE                                *FvbDevice;\r
+\r
+  FvbDevice = FVB_DEVICE_FROM_THIS (This);\r
+  SmmFvb    = FvbDevice->SmmFvbInstance;\r
+\r
+  //\r
+  // Initialize the communicate buffer.\r
+  //\r
+  PayloadSize  = sizeof (SMM_FVB_BLOCKS_HEADER);\r
+  Status = InitCommunicateBuffer (\r
+             (VOID **)&SmmCommunicateHeader,\r
+             (VOID **)&SmmFvbBlocksHeader,\r
+             PayloadSize,\r
+             EFI_FUNCTION_ERASE_BLOCKS\r
+             );\r
+  if (EFI_ERROR (Status)) {\r
+    return Status;\r
+  }\r
+\r
+  SmmFvbBlocksHeader->SmmFvb   = SmmFvb;\r
+  SmmFvbBlocksHeader->StartLba = StartingLba;\r
+  SmmFvbBlocksHeader->NumOfLba = NumOfLba;\r
+\r
+  //\r
+  // Send data to SMM.\r
+  //\r
+  Status = SendCommunicateBuffer (SmmCommunicateHeader, PayloadSize);\r
+\r
+  //\r
+  // Get data from SMM.\r
+  //\r
+  FreePool (SmmCommunicateHeader);\r
+\r
+  return Status;\r
+}\r
+\r
+\r
+/**\r
+  The EraseBlocks() function erases one or more blocks as denoted by the\r
+  variable argument list. The entire parameter list of blocks must be verified\r
+  prior to erasing any blocks.  If a block is requested that does not exist\r
+  within the associated firmware volume (it has a larger index than the last\r
+  block of the firmware volume), the EraseBlock() function must return\r
+  EFI_INVALID_PARAMETER without modifying the contents of the firmware volume.\r
+\r
+  @param[in] This           Calling context/\r
+  @param[in] ...            Starting LBA followed by Number of Lba to erase.\r
+                            a -1 to terminate the list.\r
+/\r
+  @retval EFI_SUCCESS       The erase request was successfully completed\r
+  @retval EFI_ACCESS_DENIED The firmware volume is in the WriteDisabled state/\r
+  @retval EFI_DEVICE_ERROR  The block device is not functioning correctly and\r
+                            could not be written. Firmware device may have been\r
+                            partially erased/\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+FvbEraseBlocks (\r
+  IN CONST EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL    *This,\r
+  ...\r
+  )\r
+{\r
+  EFI_STATUS                                     Status;\r
+  VA_LIST                                        Marker;\r
+  EFI_LBA                                        StartingLba;\r
+  UINTN                                          NumOfLba;\r
+\r
+  Status = EFI_SUCCESS;\r
+\r
+  //\r
+  // Check the parameter.\r
+  //\r
+  VA_START (Marker, This);\r
+  do {\r
+    StartingLba = VA_ARG (Marker, EFI_LBA);\r
+    if (StartingLba == EFI_LBA_LIST_TERMINATOR ) {\r
+      break;\r
+    }\r
+\r
+    NumOfLba = VA_ARG (Marker, UINT32);\r
+    if (NumOfLba == 0) {\r
+      return EFI_INVALID_PARAMETER;\r
+    }\r
+\r
+  } while ( 1 );\r
+  VA_END (Marker);\r
+\r
+  //\r
+  // Erase the blocks.\r
+  //\r
+  VA_START (Marker, This);\r
+  do {\r
+    StartingLba = VA_ARG (Marker, EFI_LBA);\r
+    if (StartingLba == EFI_LBA_LIST_TERMINATOR ) {\r
+      break;\r
+    }\r
+    NumOfLba = VA_ARG (Marker, UINT32);\r
+    Status = EraseBlock (This, StartingLba, NumOfLba);\r
+    if (EFI_ERROR (Status)) {\r
+      break;\r
+    }\r
+  } while ( 1 );\r
+  VA_END (Marker);\r
+\r
+  return Status;\r
+}\r
+\r
+\r
+/**\r
+  Install the FVB protocol which based on SMM FVB protocol.\r
+\r
+  @param[in] SmmFvb        The SMM FVB protocol.\r
+\r
+**/\r
+VOID\r
+InstallFvb (\r
+  IN    EFI_SMM_FIRMWARE_VOLUME_BLOCK_PROTOCOL  *SmmFvb\r
+  )\r
+{\r
+  EFI_STATUS                                    Status;\r
+  EFI_HANDLE                                    FvbHandle;\r
+  EFI_FVB_DEVICE                                *FvbDevice;\r
+  EFI_FIRMWARE_VOLUME_HEADER                    *VolumeHeader;\r
+  EFI_PHYSICAL_ADDRESS                          Address;\r
+  EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL            *OldFvbInterface;\r
+\r
+  FvbDevice = AllocateRuntimeCopyPool (sizeof (EFI_FVB_DEVICE), &mFvbDeviceTemplate);\r
+  ASSERT (FvbDevice != NULL);\r
+  FvbDevice->SmmFvbInstance = SmmFvb;\r
+\r
+  Status = gBS->LocateProtocol (\r
+                  &gEfiSmmCommunicationProtocolGuid,\r
+                  NULL,\r
+                  (VOID **) &mSmmCommunication\r
+                  );\r
+  ASSERT_EFI_ERROR (Status);\r
+\r
+  Status = GetPhysicalAddress (SmmFvb, &Address);\r
+  ASSERT_EFI_ERROR (Status);\r
+\r
+  VolumeHeader = (EFI_FIRMWARE_VOLUME_HEADER *) (UINTN)Address;\r
+\r
+  //\r
+  // Set up the devicepath.\r
+  //\r
+  if (VolumeHeader->ExtHeaderOffset == 0) {\r
+    //\r
+    // FV does not contains extension header, then produce MEMMAP_DEVICE_PATH.\r
+    //\r
+    FvbDevice->DevicePath = (EFI_DEVICE_PATH_PROTOCOL *) AllocateRuntimeCopyPool (sizeof (FV_MEMMAP_DEVICE_PATH), &mFvMemmapDevicePathTemplate);\r
+    ((FV_MEMMAP_DEVICE_PATH *) FvbDevice->DevicePath)->MemMapDevPath.StartingAddress = (UINTN)Address;\r
+    ((FV_MEMMAP_DEVICE_PATH *) FvbDevice->DevicePath)->MemMapDevPath.EndingAddress   = (UINTN)Address + VolumeHeader->FvLength - 1;\r
+  } else {\r
+    FvbDevice->DevicePath = (EFI_DEVICE_PATH_PROTOCOL *) AllocateRuntimeCopyPool (sizeof (FV_PIWG_DEVICE_PATH), &mFvPIWGDevicePathTemplate);\r
+    CopyGuid (\r
+      &((FV_PIWG_DEVICE_PATH *)FvbDevice->DevicePath)->FvDevPath.FvName,\r
+      (GUID *)(UINTN)((UINTN)Address + VolumeHeader->ExtHeaderOffset)\r
+      );\r
+  }\r
+\r
+  //\r
+  // Find a handle with a matching device path that has supports FW Block protocol.\r
+  //\r
+  Status = gBS->LocateDevicePath (\r
+                  &gEfiFirmwareVolumeBlockProtocolGuid,\r
+                  &FvbDevice->DevicePath,\r
+                  &FvbHandle\r
+                  );\r
+  if (EFI_ERROR (Status) ) {\r
+    //\r
+    // LocateDevicePath fails so install a new interface and device path.\r
+    //\r
+    FvbHandle = NULL;\r
+    Status =  gBS->InstallMultipleProtocolInterfaces (\r
+                     &FvbHandle,\r
+                     &gEfiFirmwareVolumeBlockProtocolGuid,\r
+                     &FvbDevice->FvbInstance,\r
+                     &gEfiDevicePathProtocolGuid,\r
+                     FvbDevice->DevicePath,\r
+                     NULL\r
+                     );\r
+    ASSERT_EFI_ERROR (Status);\r
+  } else if (IsDevicePathEnd (FvbDevice->DevicePath)) {\r
+    //\r
+    // Device allready exists, so reinstall the FVB protocol.\r
+    //\r
+    Status = gBS->HandleProtocol (\r
+                    FvbHandle,\r
+                    &gEfiFirmwareVolumeBlockProtocolGuid,\r
+                    (VOID **) &OldFvbInterface\r
+                    );\r
+    ASSERT_EFI_ERROR (Status);\r
+\r
+    Status =  gBS->ReinstallProtocolInterface (\r
+                     FvbHandle,\r
+                     &gEfiFirmwareVolumeBlockProtocolGuid,\r
+                     OldFvbInterface,\r
+                     &FvbDevice->FvbInstance\r
+                     );\r
+    ASSERT_EFI_ERROR (Status);\r
+  } else {\r
+    //\r
+    // There was a FVB protocol on an End Device Path node.\r
+    //\r
+    ASSERT (FALSE);\r
+  }\r
+}\r
+\r
+\r
+/**\r
+  SMM Firmware Volume Block Protocol notification event handler.\r
+\r
+  Discover NV Variable Store and install Variable Write Arch Protocol.\r
+\r
+  @param[in] Event    Event whose notification function is being invoked.\r
+  @param[in] Context  Pointer to the notification function's context.\r
+**/\r
+VOID\r
+EFIAPI\r
+SmmFvbReady (\r
+  IN  EFI_EVENT                                 Event,\r
+  IN  VOID                                      *Context\r
+  )\r
+{\r
+  EFI_STATUS                                    Status;\r
+  EFI_HANDLE                                    *HandleBuffer;\r
+  UINTN                                         HandleCount;\r
+  UINTN                                         Index;\r
+  EFI_SMM_FIRMWARE_VOLUME_BLOCK_PROTOCOL        *SmmFvb;\r
+\r
+  //\r
+  // Locate all handles of Smm Fvb protocol.\r
+  //\r
+  Status = gBS->LocateHandleBuffer (\r
+                  ByProtocol,\r
+                  &gEfiSmmFirmwareVolumeBlockProtocolGuid,\r
+                  NULL,\r
+                  &HandleCount,\r
+                  &HandleBuffer\r
+                  );\r
+  if (EFI_ERROR (Status)) {\r
+    return ;\r
+  }\r
+\r
+  //\r
+  // Install FVB protocol.\r
+  //\r
+  for (Index = 0; Index < HandleCount; Index++) {\r
+    SmmFvb = NULL;\r
+    Status = gBS->HandleProtocol (\r
+                    HandleBuffer[Index],\r
+                    &gEfiSmmFirmwareVolumeBlockProtocolGuid,\r
+                    (VOID **) &SmmFvb\r
+                    );\r
+    if (EFI_ERROR (Status)) {\r
+      break;\r
+    }\r
+\r
+    InstallFvb (SmmFvb);\r
+  }\r
+\r
+  FreePool (HandleBuffer);\r
+}\r
+\r
+\r
+/**\r
+  The driver entry point for Firmware Volume Block Driver.\r
+\r
+  The function does the necessary initialization work\r
+  Firmware Volume Block Driver.\r
+\r
+  @param[in]  ImageHandle       The firmware allocated handle for the UEFI image.\r
+  @param[in]  SystemTable       A pointer to the EFI system table.\r
+\r
+  @retval     EFI_SUCCESS       This funtion always return EFI_SUCCESS.\r
+                                It will ASSERT on errors.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+FvbSmmDxeInitialize (\r
+  IN EFI_HANDLE                                 ImageHandle,\r
+  IN EFI_SYSTEM_TABLE                           *SystemTable\r
+  )\r
+{\r
+  VOID                                          *SmmFvbRegistration;\r
+\r
+  //\r
+  // Smm FVB driver is ready.\r
+  //\r
+  EfiCreateProtocolNotifyEvent (\r
+    &gEfiSmmFirmwareVolumeBlockProtocolGuid,\r
+    TPL_CALLBACK,\r
+    SmmFvbReady,\r
+    NULL,\r
+    &SmmFvbRegistration\r
+    );\r
+\r
+  return EFI_SUCCESS;\r
+}\r
+\r

diff --git a/Vlv2TbltDevicePkg/FvbRuntimeDxe/FvbSmmDxe.h b/Vlv2TbltDevicePkg/FvbRuntimeDxe/FvbSmmDxe.h
new file mode 100644 (file)
index 0000000..a34028f
--- /dev/null
+++ b/Vlv2TbltDevicePkg/FvbRuntimeDxe/FvbSmmDxe.h
@@ -0,0 +1,237 @@
+/** @file\r
+\r
+  The internal header file includes the common header files, defines\r
+  internal structure and functions used by FVB module.\r
+\r
+Copyright (c) 2010  - 2014, Intel Corporation. All rights reserved. <BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+**/\r
+\r
+#ifndef _SMM_FVB_DXE_H_\r
+#define _SMM_FVB_DXE_H_\r
+\r
+#include <PiDxe.h>\r
+\r
+#include <Protocol/SmmFirmwareVolumeBlock.h>\r
+#include <Protocol/SmmCommunication.h>\r
+\r
+#include <Library/UefiBootServicesTableLib.h>\r
+#include <Library/UefiDriverEntryPoint.h>\r
+#include <Library/DebugLib.h>\r
+#include <Library/BaseMemoryLib.h>\r
+#include <Library/UefiLib.h>\r
+#include <Library/BaseLib.h>\r
+#include <Library/MemoryAllocationLib.h>\r
+#include <Library/DevicePathLib.h>\r
+\r
+#include <Guid/EventGroup.h>\r
+#include "FvbSmmCommon.h"\r
+\r
+#define FVB_DEVICE_SIGNATURE              SIGNATURE_32 ('F', 'V', 'B', 'S')\r
+#define FVB_DEVICE_FROM_THIS(a)           CR (a, EFI_FVB_DEVICE, FvbInstance, FVB_DEVICE_SIGNATURE)\r
+\r
+typedef struct {\r
+  MEDIA_FW_VOL_DEVICE_PATH  FvDevPath;\r
+  EFI_DEVICE_PATH_PROTOCOL  EndDevPath;\r
+} FV_PIWG_DEVICE_PATH;\r
+\r
+typedef struct {\r
+  MEMMAP_DEVICE_PATH          MemMapDevPath;\r
+  EFI_DEVICE_PATH_PROTOCOL    EndDevPath;\r
+} FV_MEMMAP_DEVICE_PATH;\r
+\r
+typedef struct {\r
+  UINTN                                   Signature;\r
+  EFI_DEVICE_PATH_PROTOCOL                *DevicePath;\r
+  EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL      FvbInstance;\r
+  EFI_SMM_FIRMWARE_VOLUME_BLOCK_PROTOCOL  *SmmFvbInstance;\r
+} EFI_FVB_DEVICE;\r
+\r
+/**\r
+  This function retrieves the attributes and current settings of the block.\r
+\r
+  @param[in]  This       Indicates the EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL instance.\r
+\r
+  @param[out] Attributes Pointer to EFI_FVB_ATTRIBUTES_2 in which the attributes\r
+                         and current settings are returned. Type EFI_FVB_ATTRIBUTES_2\r
+                         is defined in EFI_FIRMWARE_VOLUME_HEADER.\r
+\r
+  @retval EFI_SUCCESS    The firmware volume attributes were returned.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+FvbGetAttributes (\r
+  IN CONST EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL   *This,\r
+     OUT   EFI_FVB_ATTRIBUTES_2                 *Attributes\r
+  );\r
+\r
+\r
+  /**\r
+  Sets Volume attributes. No polarity translations are done.\r
+\r
+  @param[in]  This        Calling context.\r
+  @param[out] Attributes  Output buffer which contains attributes.\r
+\r
+  @retval     EFI_SUCCESS The function always return successfully.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+FvbSetAttributes (\r
+  IN CONST EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL   *This,\r
+  IN OUT   EFI_FVB_ATTRIBUTES_2                 *Attributes\r
+  );\r
+\r
+\r
+/**\r
+  Retrieves the physical address of the device.\r
+\r
+  @param[in]  This    A pointer to EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL.\r
+  @param[out] Address Output buffer containing the address.\r
+\r
+  @retval EFI_SUCCESS The function always return successfully.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+FvbGetPhysicalAddress (\r
+  IN CONST EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL  *This,\r
+     OUT   EFI_PHYSICAL_ADDRESS                *Address\r
+  );\r
+\r
+\r
+/**\r
+  Retrieve the size of a logical block.\r
+\r
+  @param[in]  This         Calling context.\r
+  @param[in]  Lba          Indicates which block to return the size for.\r
+  @param[out] BlockSize    A pointer to a caller allocated UINTN in which\r
+                           the size of the block is returned.\r
+  @param[out] NumOfBlocks  A pointer to a caller allocated UINTN in which the\r
+                           number of consecutive blocks starting with Lba is\r
+                           returned. All blocks in this range have a size of\r
+                           BlockSize.\r
+\r
+  @retval     EFI_SUCCESS  The function always return successfully.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+FvbGetBlockSize (\r
+  IN CONST EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL  *This,\r
+  IN       EFI_LBA                             Lba,\r
+     OUT   UINTN                               *BlockSize,\r
+     OUT   UINTN                               *NumOfBlocks\r
+  );\r
+\r
+\r
+/**\r
+  Reads data beginning at Lba:Offset from FV. The Read terminates either\r
+  when *NumBytes of data have been read, or when a block boundary is\r
+  reached.  *NumBytes is updated to reflect the actual number of bytes\r
+  written. The write opertion does not include erase. This routine will\r
+  attempt to write only the specified bytes. If the writes do not stick,\r
+  it will return an error.\r
+\r
+  @param[in]      This           Calling context.\r
+  @param[in]      Lba            Block in which to begin write.\r
+  @param[in]      Offset         Offset in the block at which to begin write\r
+  @param[in,out]  NumBytes       On input, indicates the requested write size. On\r
+                                 output, indicates the actual number of bytes written\r
+  @param[in]      Buffer         Buffer containing source data for the write.\r
+\r
+  @retval EFI_SUCCESS            The firmware volume was read successfully and\r
+                                 contents are in Buffer\r
+  @retval EFI_BAD_BUFFER_SIZE    Read attempted across a LBA boundary. On output,\r
+                                 NumBytes contains the total number of bytes returned\r
+                                 in Buffer\r
+  @retval EFI_ACCESS_DENIED      The firmware volume is in the ReadDisabled state\r
+  @retval EFI_DEVICE_ERROR       The block device is not functioning correctly and\r
+                                 could not be read\r
+  @retval EFI_INVALID_PARAMETER  NumBytes or Buffer are NULL\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+FvbRead (\r
+  IN CONST EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL   *This,\r
+  IN       EFI_LBA                              Lba,\r
+  IN       UINTN                                Offset,\r
+  IN OUT   UINTN                                *NumBytes,\r
+     OUT   UINT8                                *Buffer\r
+  );\r
+\r
+\r
+/**\r
+  Writes data beginning at Lba:Offset from FV. The write terminates either\r
+  when *NumBytes of data have been written, or when a block boundary is\r
+  reached.  *NumBytes is updated to reflect the actual number of bytes\r
+  written. The write opertion does not include erase. This routine will\r
+  attempt to write only the specified bytes. If the writes do not stick,\r
+  it will return an error.\r
+\r
+  @param[in]      This           Calling context.\r
+  @param[in]      Lba            Block in which to begin write.\r
+  @param[in]      Offset         Offset in the block at which to begin write.\r
+  @param[in,out]  NumBytes       On input, indicates the requested write size. On\r
+                                 output, indicates the actual number of bytes written\r
+  @param[in]      Buffer         Buffer containing source data for the write.\r
+\r
+  @retval EFI_SUCCESS            The firmware volume was written successfully\r
+  @retval EFI_BAD_BUFFER_SIZE    Write attempted across a LBA boundary. On output,\r
+                                 NumBytes contains the total number of bytes\r
+                                 actually written.\r
+  @retval EFI_ACCESS_DENIED      The firmware volume is in the WriteDisabled state\r
+  @retval EFI_DEVICE_ERROR       The block device is not functioning correctly and\r
+                                 could not be written.\r
+  @retval EFI_INVALID_PARAMETER  NumBytes or Buffer are NULL.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+FvbWrite (\r
+  IN CONST EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL   *This,\r
+  IN       EFI_LBA                              Lba,\r
+  IN       UINTN                                Offset,\r
+  IN OUT   UINTN                                *NumBytes,\r
+  IN       UINT8                                *Buffer\r
+  );\r
+\r
+\r
+/**\r
+  The EraseBlock() function erases one or more blocks as denoted by the\r
+  variable argument list. The entire parameter list of blocks must be verified\r
+  prior to erasing any blocks.  If a block is requested that does not exist\r
+  within the associated firmware volume (it has a larger index than the last\r
+  block of the firmware volume), the EraseBlock() function must return\r
+  EFI_INVALID_PARAMETER without modifying the contents of the firmware volume.\r
+\r
+  @param[in] This         Calling context.\r
+  @param[in] ...          Starting LBA followed by Number of Lba to erase.\r
+                          a -1 to terminate the list.\r
+\r
+  @retval EFI_SUCCESS       The erase request was successfully completed.\r
+  @retval EFI_ACCESS_DENIED The firmware volume is in the WriteDisabled state\r
+  @retval EFI_DEVICE_ERROR  The block device is not functioning correctly and\r
+                            could not be written. Firmware device may have been\r
+                            partially erased.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+FvbEraseBlocks (\r
+  IN CONST EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL    *This,\r
+  ...\r
+  );\r
+\r
+#endif\r

diff --git a/Vlv2TbltDevicePkg/FvbRuntimeDxe/FvbSmmDxe.inf b/Vlv2TbltDevicePkg/FvbRuntimeDxe/FvbSmmDxe.inf
new file mode 100644 (file)
index 0000000..a588dc1
--- /dev/null
+++ b/Vlv2TbltDevicePkg/FvbRuntimeDxe/FvbSmmDxe.inf
@@ -0,0 +1,55 @@
+## @file\r
+# Component description file for Firmware Volume Block module.\r
+#\r
+# Copyright (c) 2010 - 2014, Intel Corporation. All rights reserved.<BR>\r
+#                                                                                  \r\r
+# This program and the accompanying materials are licensed and made available under\r\r
+# the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+# The full text of the license may be found at                                     \r\r
+# http://opensource.org/licenses/bsd-license.php.                                  \r\r
+#                                                                                  \r\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+#                                                                                  \r\r
+#\r
+#\r
+##\r
+\r
+[Defines]\r
+  INF_VERSION                    = 0x00010005\r
+  BASE_NAME                      = FvbSmmDxe\r
+  FILE_GUID                      = 9E8AD3F4-383D-4ec3-816E-7A4749371290\r
+  MODULE_TYPE                    = DXE_DRIVER\r
+  VERSION_STRING                 = 1.0\r
+  ENTRY_POINT                    = FvbSmmDxeInitialize\r
+\r
+#\r
+# The following information is for reference only and not required by the build tools.\r
+#\r
+#  VALID_ARCHITECTURES           = IA32 X64\r
+#\r
+\r
+[Sources]\r
+  FvbSmmDxe.c\r
+  FvbSmmDxe.h\r
+  FvbSmmCommon.h\r
+\r
+[Packages]\r
+  MdePkg/MdePkg.dec\r
+  MdeModulePkg/MdeModulePkg.dec\r
+\r
+[LibraryClasses]\r
+  BaseLib\r
+  UefiBootServicesTableLib\r
+  DebugLib\r
+  DxeServicesTableLib\r
+  UefiDriverEntryPoint\r
+  PcdLib\r
+\r
+[Protocols]\r
+  gEfiFirmwareVolumeBlockProtocolGuid           ## ALWAYS_PRODUCES\r
+  gEfiSmmCommunicationProtocolGuid\r
+  gEfiSmmFirmwareVolumeBlockProtocolGuid\r
+\r
+[Depex]\r
+  gEfiSmmCommunicationProtocolGuid\r

diff --git a/Vlv2TbltDevicePkg/GenBiosId b/Vlv2TbltDevicePkg/GenBiosId
new file mode 100644 (file)
index 0000000..ef1578f
Binary files /dev/null and b/Vlv2TbltDevicePkg/GenBiosId differ

diff --git a/Vlv2TbltDevicePkg/GenBiosId.exe b/Vlv2TbltDevicePkg/GenBiosId.exe
new file mode 100644 (file)
index 0000000..323b87c
Binary files /dev/null and b/Vlv2TbltDevicePkg/GenBiosId.exe differ

diff --git a/Vlv2TbltDevicePkg/Include/AlertStandardFormatTable.h b/Vlv2TbltDevicePkg/Include/AlertStandardFormatTable.h
new file mode 100644 (file)
index 0000000..c70b395
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Include/AlertStandardFormatTable.h
@@ -0,0 +1,127 @@
+/*++\r
+\r
+  Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+Module Name:\r
+\r
+  AlertStandardFormatTable.h\r
+\r
+Abstract:\r
+\r
+  ACPI Alert Standard Format Description Table ASF! as described\r
+  in the ASF2.0 Specification\r
+\r
+--*/\r
+\r
+#ifndef _ALERT_STANDARD_FORMAT_TABLE_H\r
+#define _ALERT_STANDARD_FORMAT_TABLE_H\r
+\r
+#include <IndustryStandard/Acpi20.h>\r
+\r
+//\r
+// Ensure proper structure formats.\r
+//\r
+#pragma pack (1)\r
+\r
+//\r
+// Information Record header that appears at the beginning of each record.\r
+//\r
+typedef struct {\r
+  UINT8                                Type;\r
+  UINT8                                Reserved;\r
+  UINT16                               RecordLength;\r
+} EFI_ACPI_ASF_RECORD_HEADER;\r
+\r
+//\r
+// This structure contains information that identifies the system type\r
+// and configuration.\r
+//\r
+typedef struct {\r
+  EFI_ACPI_ASF_RECORD_HEADER           RecordHeader;\r
+  UINT8                                MinWatchDogResetValue;\r
+  UINT8                                MinPollingInterval;\r
+  UINT16                               SystemID;\r
+  UINT32                               IANAManufactureID;\r
+  UINT8                                FeatureFlags;\r
+  UINT8                                Reserved[3];\r
+} EFI_ACPI_ASF_INFO;\r
+\r
+//\r
+// Alert sensors definition.\r
+//\r
+#define ASF_ALRT_SENSOR_ARRAY_LENGTH     36\r
+\r
+typedef struct {\r
+  EFI_ACPI_ASF_RECORD_HEADER           RecordHeader;\r
+  UINT8                                AssertionEventBitMask;\r
+  UINT8                                DeassertionEventBitMask;\r
+  UINT8                                NumberOfAlerts;\r
+  UINT8                                ArrayElementLength;\r
+  UINT8                                DeviceArray[ASF_ALRT_SENSOR_ARRAY_LENGTH];\r
+} EFI_ACPI_ASF_ALRT;\r
+\r
+//\r
+// Alert Remote Control System Actions.\r
+//\r
+#define ASF_RCTL_DEVICES_ARRAY_LENGTH      16\r
+\r
+typedef struct {\r
+  EFI_ACPI_ASF_RECORD_HEADER           RecordHeader;\r
+  UINT8                                NumberOfControls;\r
+  UINT8                                ArrayElementLength;\r
+  UINT16                               RctlReserved;\r
+  UINT8                                ControlArray[ASF_RCTL_DEVICES_ARRAY_LENGTH];\r
+} EFI_ACPI_ASF_RCTL;\r
+\r
+//\r
+// Remote Control Capabilities.\r
+//\r
+typedef struct {\r
+  EFI_ACPI_ASF_RECORD_HEADER           RecordHeader;\r
+  UINT8                                RemoteControlCapabilities[7];\r
+  UINT8                                RMCPCompletionCode;\r
+  UINT32                               RMCPIANA;\r
+  UINT8                                RMCPSpecialCommand;\r
+  UINT8                                RMCPSpecialCommandParameter[2];\r
+  UINT8                                RMCPBootOptions[2];\r
+  UINT8                                RMCPOEMParameters[2];\r
+} EFI_ACPI_ASF_RMCP;\r
+\r
+//\r
+// SMBus Devices with fixed addresses.\r
+//\r
+#define ASF_ADDR_DEVICE_ARRAY_LENGTH      16\r
+\r
+typedef struct {\r
+  EFI_ACPI_ASF_RECORD_HEADER           RecordHeader;\r
+  UINT8                                SEEPROMAddress;\r
+  UINT8                                NumberOfDevices;\r
+  UINT8                                FixedSmbusAddresses[ASF_ADDR_DEVICE_ARRAY_LENGTH];\r
+} EFI_ACPI_ASF_ADDR;\r
+\r
+typedef struct {\r
+  EFI_ACPI_DESCRIPTION_HEADER          Header;\r
+  EFI_ACPI_ASF_INFO                    AsfInfo;\r
+  EFI_ACPI_ASF_ALRT                    AsfAlert;\r
+  EFI_ACPI_ASF_RCTL                    AsfRctl;\r
+  EFI_ACPI_ASF_RMCP                    AsfRmcp;\r
+  EFI_ACPI_ASF_ADDR                    AsfAddr;\r
+} EFI_ACPI_1_0_ASF_DESCRIPTION_TABLE;\r
+\r
+//\r
+// "ASF!" ASF Description Table Signature.\r
+//\r
+#define EFI_ACPI_1_0_ASF_DESCRIPTION_TABLE_SIGNATURE  0x21465341\r
+\r
+#pragma pack ()\r
+\r
+#endif // _ALERT_STANDARD_FORMAT_TABLE_H\r

diff --git a/Vlv2TbltDevicePkg/Include/ChipsetAccess.h b/Vlv2TbltDevicePkg/Include/ChipsetAccess.h
new file mode 100644 (file)
index 0000000..baf9b29
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Include/ChipsetAccess.h
@@ -0,0 +1,33 @@
+/*++\r
+\r
+  Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+\r
+Module Name:\r
+\r
+  ChipsetAccess.h\r
+\r
+Abstract:\r
+\r
+  Common Include file for Platform Drivers to access the Chipset registers.\r
+\r
+--*/\r
+\r
+#ifndef _CHIPSET_ACCESS_H_\r
+#define _CHIPSET_ACCESS_H_\r
+\r
+#include "PchAccess.h"\r
+#include "Valleyview.h"\r
+#include "VlvAccess.h"\r
+#include "VlvCommonDefinitions.h"\r
+\r
+#endif\r

diff --git a/Vlv2TbltDevicePkg/Include/CommonIncludes.h b/Vlv2TbltDevicePkg/Include/CommonIncludes.h
new file mode 100644 (file)
index 0000000..04b5405
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Include/CommonIncludes.h
@@ -0,0 +1,120 @@
+/**\r
+\r
+Copyright (c)  1999  - 2014, Intel Corporation. All rights reserved\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+@file\r
+  CommonIncludes.h\r
+\r
+@brief\r
+  This file defines common equates.\r
+\r
+**/\r
+#ifndef _COMMON_INCLUDES_H_\r
+#define _COMMON_INCLUDES_H_\r
+\r
+#define V_INTEL_VID 0x8086\r
+\r
+#ifndef STALL_ONE_MICRO_SECOND\r
+#define STALL_ONE_MICRO_SECOND  1\r
+#endif\r
+#ifndef STALL_ONE_MILLI_SECOND\r
+#define STALL_ONE_MILLI_SECOND  1000\r
+#endif\r
+///\r
+/// Min Max\r
+///\r
+#define V_MIN(a, b) (((a) < (b)) ? (a) : (b))\r
+#define V_MAX(a, b) (((a) > (b)) ? (a) : (b))\r
+\r
+///\r
+/// Bit map macro\r
+///\r
+#ifndef BIT0\r
+\r
+#define BIT63 0x8000000000000000\r
+#define BIT62 0x4000000000000000\r
+#define BIT61 0x2000000000000000\r
+#define BIT60 0x1000000000000000\r
+#define BIT59 0x0800000000000000\r
+#define BIT58 0x0400000000000000\r
+#define BIT57 0x0200000000000000\r
+#define BIT56 0x0100000000000000\r
+#define BIT55 0x0080000000000000\r
+#define BIT54 0x0040000000000000\r
+#define BIT53 0x0020000000000000\r
+#define BIT52 0x0010000000000000\r
+#define BIT51 0x0008000000000000\r
+#define BIT50 0x0004000000000000\r
+#define BIT49 0x0002000000000000\r
+#define BIT48 0x0001000000000000\r
+#define BIT47 0x0000800000000000\r
+#define BIT46 0x0000400000000000\r
+#define BIT45 0x0000200000000000\r
+#define BIT44 0x0000100000000000\r
+#define BIT43 0x0000080000000000\r
+#define BIT42 0x0000040000000000\r
+#define BIT41 0x0000020000000000\r
+#define BIT40 0x0000010000000000\r
+#define BIT39 0x0000008000000000\r
+#define BIT38 0x0000004000000000\r
+#define BIT37 0x0000002000000000\r
+#define BIT36 0x0000001000000000\r
+#define BIT35 0x0000000800000000\r
+#define BIT34 0x0000000400000000\r
+#define BIT33 0x0000000200000000\r
+#define BIT32 0x0000000100000000\r
+\r
+#define BIT31 0x80000000\r
+#define BIT30 0x40000000\r
+#define BIT29 0x20000000\r
+#define BIT28 0x10000000\r
+#define BIT27 0x08000000\r
+#define BIT26 0x04000000\r
+#define BIT25 0x02000000\r
+#define BIT24 0x01000000\r
+#define BIT23 0x00800000\r
+#define BIT22 0x00400000\r
+#define BIT21 0x00200000\r
+#define BIT20 0x00100000\r
+#define BIT19 0x00080000\r
+#define BIT18 0x00040000\r
+#define BIT17 0x00020000\r
+#define BIT16 0x00010000\r
+#define BIT15 0x00008000\r
+#define BIT14 0x00004000\r
+#define BIT13 0x00002000\r
+#define BIT12 0x00001000\r
+#define BIT11 0x00000800\r
+#define BIT10 0x00000400\r
+#define BIT9  0x00000200\r
+#define BIT8  0x00000100\r
+#define BIT7  0x00000080\r
+#define BIT6  0x00000040\r
+#define BIT5  0x00000020\r
+#define BIT4  0x00000010\r
+#define BIT3  0x00000008\r
+#define BIT2  0x00000004\r
+#define BIT1  0x00000002\r
+#define BIT0  0x00000001\r
+#endif\r
+\r
+#define BITS(x) (1 << (x))\r
+\r
+//\r
+// Notes :\r
+// 1.  Bit position always starts at 0.\r
+// 2.  Following macros are applicable only for Word alligned integers.\r
+//\r
+#define BIT(Pos, Value)               (1 << (Pos) & (Value))\r
+#define BITRANGE(From, Width, Value)  (((Value) >> (From)) & ((1 << (Width)) - 1))\r
+\r
+#endif\r

diff --git a/Vlv2TbltDevicePkg/Include/CpuType.h b/Vlv2TbltDevicePkg/Include/CpuType.h
new file mode 100644 (file)
index 0000000..50562dc
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Include/CpuType.h
@@ -0,0 +1,64 @@
+/*++\r
+\r
+  Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+Module Name:\r
+\r
+  CpuType.h\r
+\r
+Abstract:\r
+\r
+--*/\r
+\r
+#ifndef _CPU_TYPE_H\r
+#define _CPU_TYPE_H\r
+\r
+#pragma pack(1)\r
+\r
+typedef enum {\r
+  EnumCpuUarchUnknown = 0,\r
+  EnumNehalemUarch,\r
+} EFI_CPU_UARCH;\r
+\r
+typedef enum {\r
+  EnumCpuPlatformUnknown = 0,\r
+  EnumDesktop,\r
+  EnumMobile,\r
+  EnumServer,\r
+  EnumNetTop\r
+} EFI_CPU_PLATFORM;\r
+\r
+typedef enum {\r
+  EnumCpuTypeUnknown = 0,\r
+  EnumAtom,\r
+  EnumNehalemEx,\r
+  EnumBloomfield,\r
+  EnumGainestown,\r
+  EnumHavendale,\r
+  EnumLynnfield,\r
+  EnumAuburndale,\r
+  EnumClarksfield,\r
+  EnumPineview,\r
+  EnumCedarview,\r
+  EnumValleyview,\r
+  EnumClarkdale // Havendale 32nm\r
+} EFI_CPU_TYPE;\r
+\r
+typedef enum {\r
+  EnumCpuFamilyUnknown = 0,\r
+  EnumFamilyField,\r
+  EnumFamilyDale\r
+} EFI_CPU_FAMILY;\r
+\r
+#pragma pack()\r
+\r
+#endif\r

diff --git a/Vlv2TbltDevicePkg/Include/FileHandleLib.h b/Vlv2TbltDevicePkg/Include/FileHandleLib.h
new file mode 100644 (file)
index 0000000..59d1b92
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Include/FileHandleLib.h
@@ -0,0 +1,504 @@
+/*++\r
+\r
+  Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+**/\r
+\r
+#ifndef _FILE_HANDLE_LIBRARY_HEADER_\r
+#define _FILE_HANDLE_LIBRARY_HEADER_\r
+\r
+#include <Protocol/SimpleFileSystem.h>\r
+\r
+//\r
+// The tag for use in identifying UNICODE files.\r
+// If the file is UNICODE, the first 16 bits of the file will equal this value.\r
+//\r
+extern CONST UINT16 gUnicodeFileTag;\r
+\r
+/**\r
+  This function retrieves information about the file for the handle\r
+  specified and stores it in the allocated pool memory.\r
+\r
+  This function allocates a buffer to store the file's information. It is the\r
+  caller's responsibility to free the buffer.\r
+\r
+  @param[in] FileHandle         The file handle of the file for which information is\r
+                                being requested.\r
+\r
+  @retval NULL                  Information could not be retrieved.\r
+  @retval !NULL                 The information about the file.\r
+**/\r
+EFI_FILE_INFO*\r
+EFIAPI\r
+FileHandleGetInfo (\r
+  IN EFI_FILE_HANDLE            FileHandle\r
+  );\r
+\r
+/**\r
+  This function sets the information about the file for the opened handle\r
+  specified.\r
+\r
+  @param[in]  FileHandle        The file handle of the file for which information\r
+                                is being set.\r
+\r
+  @param[in]  FileInfo          The information to set.\r
+\r
+  @retval EFI_SUCCESS           The information was set.\r
+  @retval EFI_INVALID_PARAMETER A parameter was out of range or invalid.\r
+  @retval EFI_UNSUPPORTED       The FileHandle does not support FileInfo.\r
+  @retval EFI_NO_MEDIA          The device has no medium.\r
+  @retval EFI_DEVICE_ERROR      The device reported an error.\r
+  @retval EFI_VOLUME_CORRUPTED  The file system structures are corrupted.\r
+  @retval EFI_WRITE_PROTECTED   The file or medium is write protected.\r
+  @retval EFI_ACCESS_DENIED     The file was opened read only.\r
+  @retval EFI_VOLUME_FULL       The volume is full.\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+FileHandleSetInfo (\r
+  IN EFI_FILE_HANDLE            FileHandle,\r
+  IN CONST EFI_FILE_INFO        *FileInfo\r
+  );\r
+\r
+/**\r
+  This function reads information from an opened file.\r
+\r
+  If FileHandle is not a directory, the function reads the requested number of\r
+  bytes from the file at the file's current position and returns them in Buffer.\r
+  If the read goes beyond the end of the file, the read length is truncated to the\r
+  end of the file. The file's current position is increased by the number of bytes\r
+  returned.  If FileHandle is a directory, the function reads the directory entry\r
+  at the file's current position and returns the entry in Buffer. If the Buffer\r
+  is not large enough to hold the current directory entry, then\r
+  EFI_BUFFER_TOO_SMALL is returned and the current file position is not updated.\r
+  BufferSize is set to be the size of the buffer needed to read the entry. On\r
+  success, the current position is updated to the next directory entry. If there\r
+  are no more directory entries, the read returns a zero-length buffer.\r
+  EFI_FILE_INFO is the structure returned as the directory entry.\r
+\r
+  @param[in] FileHandle          The opened file handle.\r
+  @param[in, out] BufferSize     On input, the size of buffer in bytes.  On return,\r
+                                 the number of bytes written.\r
+  @param[out] Buffer             The buffer to put read data into.\r
+\r
+  @retval EFI_SUCCESS            Data was read.\r
+  @retval EFI_NO_MEDIA           The device has no media.\r
+  @retval EFI_DEVICE_ERROR       The device reported an error.\r
+  @retval EFI_VOLUME_CORRUPTED   The file system structures are corrupted.\r
+  @retval EFI_BUFFER_TO_SMALL    Buffer is too small. ReadSize contains required\r
+                                 size.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+FileHandleRead(\r
+  IN EFI_FILE_HANDLE            FileHandle,\r
+  IN OUT UINTN                  *BufferSize,\r
+  OUT VOID                      *Buffer\r
+  );\r
+\r
+/**\r
+  Write data to a file.\r
+\r
+  This function writes the specified number of bytes to the file at the current\r
+  file position. The current file position is advanced the actual number of bytes\r
+  written, which is returned in BufferSize. Partial writes only occur when there\r
+  has been a data error during the write attempt (such as "volume space full").\r
+  The file is automatically grown to hold the data if required. Direct writes to\r
+  opened directories are not supported.\r
+\r
+  @param[in] FileHandle         The opened file for writing.\r
+  @param[in, out] BufferSize    On input, the number of bytes in Buffer.  On output,\r
+                                the number of bytes written.\r
+  @param[in] Buffer             The buffer containing data to write is stored.\r
+\r
+  @retval EFI_SUCCESS           Data was written.\r
+  @retval EFI_UNSUPPORTED       Writes to an open directory are not supported.\r
+  @retval EFI_NO_MEDIA          The device has no media.\r
+  @retval EFI_DEVICE_ERROR      The device reported an error.\r
+  @retval EFI_VOLUME_CORRUPTED  The file system structures are corrupted.\r
+  @retval EFI_WRITE_PROTECTED   The device is write-protected.\r
+  @retval EFI_ACCESS_DENIED     The file was opened for read only.\r
+  @retval EFI_VOLUME_FULL       The volume is full.\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+FileHandleWrite(\r
+  IN EFI_FILE_HANDLE            FileHandle,\r
+  IN OUT UINTN                  *BufferSize,\r
+  IN VOID                       *Buffer\r
+  );\r
+\r
+/**\r
+  Close an open file handle.\r
+\r
+  This function closes a specified file handle. All "dirty" cached file data is\r
+  flushed to the device, and the file is closed. In all cases the handle is\r
+  closed.\r
+\r
+  @param[in] FileHandle           The file handle to close.\r
+\r
+  @retval EFI_SUCCESS             The file handle was closed successfully.\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+FileHandleClose (\r
+  IN EFI_FILE_HANDLE            FileHandle\r
+  );\r
+\r
+/**\r
+  Delete a file and close the handle.\r
+\r
+  This function closes and deletes a file. In all cases the file handle is closed.\r
+  If the file cannot be deleted, the warning code EFI_WARN_DELETE_FAILURE is\r
+  returned, but the handle is still closed.\r
+\r
+  @param[in] FileHandle             The file handle to delete.\r
+\r
+  @retval EFI_SUCCESS               The file was closed successfully.\r
+  @retval EFI_WARN_DELETE_FAILURE   The handle was closed, but the file was not\r
+                                    deleted.\r
+  @retval INVALID_PARAMETER         One of the parameters has an invalid value.\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+FileHandleDelete (\r
+  IN EFI_FILE_HANDLE    FileHandle\r
+  );\r
+\r
+/**\r
+  Set the current position in a file.\r
+\r
+  This function sets the current file position for the handle to the position\r
+  supplied. With the exception of moving to position 0xFFFFFFFFFFFFFFFF, only\r
+  absolute positioning is supported, and moving past the end of the file is\r
+  allowed (a subsequent write would grow the file). Moving to position\r
+  0xFFFFFFFFFFFFFFFF causes the current position to be set to the end of the file.\r
+  If FileHandle is a directory, the only position that may be set is zero. This\r
+  has the effect of starting the read process of the directory entries over again.\r
+\r
+  @param[in] FileHandle         The file handle on which the position is being set.\r
+  @param[in] Position           The byte position from the begining of the file.\r
+\r
+  @retval EFI_SUCCESS           The operation completed sucessfully.\r
+  @retval EFI_UNSUPPORTED       The request for non-zero is not valid on\r
+                                directories.\r
+  @retval INVALID_PARAMETER     One of the parameters has an invalid value.\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+FileHandleSetPosition (\r
+  IN EFI_FILE_HANDLE    FileHandle,\r
+  IN UINT64             Position\r
+  );\r
+\r
+/**\r
+  Gets a file's current position.\r
+\r
+  This function retrieves the current file position for the file handle. For\r
+  directories, the current file position has no meaning outside of the file\r
+  system driver. As such, the operation is not supported. An error is returned\r
+  if FileHandle is a directory.\r
+\r
+  @param[in] FileHandle         The open file handle on which to get the position.\r
+  @param[out] Position          The byte position from begining of file.\r
+\r
+  @retval EFI_SUCCESS           The operation completed successfully.\r
+  @retval INVALID_PARAMETER     One of the parameters has an invalid value.\r
+  @retval EFI_UNSUPPORTED       The request is not valid on directories.\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+FileHandleGetPosition (\r
+  IN EFI_FILE_HANDLE            FileHandle,\r
+  OUT UINT64                    *Position\r
+  );\r
+\r
+/**\r
+  Flushes data on a file.\r
+\r
+  This function flushes all modified data associated with a file to a device.\r
+\r
+  @param[in] FileHandle         The file handle on which to flush data.\r
+\r
+  @retval EFI_SUCCESS           The data was flushed.\r
+  @retval EFI_NO_MEDIA          The device has no media.\r
+  @retval EFI_DEVICE_ERROR      The device reported an error.\r
+  @retval EFI_VOLUME_CORRUPTED  The file system structures are corrupted.\r
+  @retval EFI_WRITE_PROTECTED   The file or medium is write protected.\r
+  @retval EFI_ACCESS_DENIED     The file was opened for read only.\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+FileHandleFlush (\r
+  IN EFI_FILE_HANDLE            FileHandle\r
+  );\r
+\r
+/**\r
+  Function to determine if a given handle is a directory handle.\r
+\r
+  If DirHandle is NULL, then ASSERT().\r
+\r
+  Open the file information on the DirHandle, and verify that the Attribute\r
+  includes EFI_FILE_DIRECTORY bit set.\r
+\r
+  @param[in] DirHandle           The handle to open the file.\r
+\r
+  @retval EFI_SUCCESS            DirHandle is a directory.\r
+  @retval EFI_INVALID_PARAMETER  DirHandle did not have EFI_FILE_INFO available.\r
+  @retval EFI_NOT_FOUND          DirHandle is not a directory.\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+FileHandleIsDirectory (\r
+  IN EFI_FILE_HANDLE            DirHandle\r
+  );\r
+\r
+/**\r
+  Retrieve first entry from a directory.\r
+\r
+  This function takes an open directory handle and gets information from the\r
+  first entry in the directory.  A buffer is allocated to contain\r
+  the information and a pointer to the buffer is returned in *Buffer.  The\r
+  caller can use FileHandleFindNextFile() to get subsequent directory entries.\r
+\r
+  The buffer will be freed by FileHandleFindNextFile() when the last directory\r
+  entry is read.  Otherwise, the caller must free the buffer, using FreePool,\r
+  when finished with it.\r
+\r
+  @param[in]  DirHandle         The file handle of the directory to search.\r
+  @param[out] Buffer            The pointer to pointer to buffer for file's information.\r
+\r
+  @retval EFI_SUCCESS           Found the first file.\r
+  @retval EFI_NOT_FOUND         Cannot find the directory.\r
+  @retval EFI_NO_MEDIA          The device has no media.\r
+  @retval EFI_DEVICE_ERROR      The device reported an error.\r
+  @retval EFI_VOLUME_CORRUPTED  The file system structures are corrupted.\r
+  @return Others                The status of FileHandleGetInfo, FileHandleSetPosition,\r
+                                or FileHandleRead.\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+FileHandleFindFirstFile (\r
+  IN EFI_FILE_HANDLE            DirHandle,\r
+  OUT EFI_FILE_INFO             **Buffer\r
+  );\r
+\r
+/**\r
+  Retrieve next entries from a directory.\r
+\r
+  To use this function, the caller must first call the FileHandleFindFirstFile()\r
+  function to get the first directory entry.  Subsequent directory entries are\r
+  retrieved by using the FileHandleFindNextFile() function.  This function can\r
+  be called several times to get each entry from the directory.  If the call of\r
+  FileHandleFindNextFile() retrieved the last directory entry, the next call of\r
+  this function will set *NoFile to TRUE and free the buffer.\r
+\r
+  @param[in]  DirHandle         The file handle of the directory.\r
+  @param[out] Buffer            The pointer to buffer for file's information.\r
+  @param[out] NoFile            The pointer to boolean when last file is found.\r
+\r
+  @retval EFI_SUCCESS           Found the next file, or reached last file.\r
+  @retval EFI_NO_MEDIA          The device has no media.\r
+  @retval EFI_DEVICE_ERROR      The device reported an error.\r
+  @retval EFI_VOLUME_CORRUPTED  The file system structures are corrupted.\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+FileHandleFindNextFile(\r
+  IN EFI_FILE_HANDLE             DirHandle,\r
+  OUT EFI_FILE_INFO              *Buffer,\r
+  OUT BOOLEAN                    *NoFile\r
+  );\r
+\r
+/**\r
+  Retrieve the size of a file.\r
+\r
+  If FileHandle is NULL then ASSERT().\r
+  If Size is NULL then ASSERT().\r
+\r
+  This function extracts the file size info from the FileHandle's EFI_FILE_INFO\r
+  data.\r
+\r
+  @param[in] FileHandle         The file handle from which size is retrieved.\r
+  @param[out] Size              The pointer to size.\r
+\r
+  @retval EFI_SUCCESS           The operation completed successfully.\r
+  @retval EFI_DEVICE_ERROR      Cannot access the file.\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+FileHandleGetSize (\r
+  IN EFI_FILE_HANDLE            FileHandle,\r
+  OUT UINT64                    *Size\r
+  );\r
+\r
+/**\r
+  Set the size of a file.\r
+\r
+  If FileHandle is NULL then ASSERT().\r
+\r
+  This function changes the file size info from the FileHandle's EFI_FILE_INFO\r
+  data.\r
+\r
+  @param[in] FileHandle         The file handle whose size is to be changed.\r
+  @param[in] Size               The new size.\r
+\r
+  @retval EFI_SUCCESS           The operation completed successfully.\r
+  @retval EFI_DEVICE_ERROR      Cannot access the file.\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+FileHandleSetSize (\r
+  IN EFI_FILE_HANDLE            FileHandle,\r
+  IN UINT64                     Size\r
+  );\r
+\r
+/**\r
+  Function to get a full filename given a EFI_FILE_HANDLE somewhere lower on the\r
+  directory 'stack'.\r
+\r
+  @param[in] Handle              Handle to the Directory or File to create path to.\r
+  @param[out] FullFileName       Pointer to pointer to generated full file name.  It\r
+                                 is the responsibility of the caller to free this memory\r
+                                 with a call to FreePool().\r
+  @retval EFI_SUCCESS            The operation was successful and FullFileName is valid.\r
+  @retval EFI_INVALID_PARAMETER  Handle was NULL.\r
+  @retval EFI_INVALID_PARAMETER  FullFileName was NULL.\r
+  @retval EFI_OUT_OF_MEMORY      A memory allocation failed.\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+FileHandleGetFileName (\r
+  IN CONST EFI_FILE_HANDLE      Handle,\r
+  OUT CHAR16                    **FullFileName\r
+  );\r
+\r
+/**\r
+  Function to read a single line (up to but not including the \n) from a file.\r
+\r
+  If the position upon start is 0, then the Ascii Boolean will be set.  This should be\r
+  maintained and not changed for all operations with the same file.\r
+\r
+  @param[in]       Handle         FileHandle to read from.\r
+  @param[in, out]  Buffer         The pointer to buffer to read into.\r
+  @param[in, out]  Size           The pointer to number of bytes in Buffer.\r
+  @param[in]       Truncate       If the buffer is large enough, this has no effect.\r
+                                  If the buffer is is too small and Truncate is TRUE,\r
+                                  the line will be truncated.\r
+                                  If the buffer is is too small and Truncate is FALSE,\r
+                                  then no read will occur.\r
+\r
+  @param[in, out]  Ascii          Boolean value for indicating whether the file is\r
+                                  Ascii (TRUE) or UCS2 (FALSE).\r
+\r
+  @retval EFI_SUCCESS            The operation was successful.  The line is stored in\r
+                                 Buffer.\r
+  @retval EFI_INVALID_PARAMETER  Handle was NULL.\r
+  @retval EFI_INVALID_PARAMETER  Size was NULL.\r
+  @retval EFI_BUFFER_TOO_SMALL   Size was not large enough to store the line.\r
+                                 Size was updated to the minimum space required.\r
+  @sa FileHandleRead\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+FileHandleReadLine(\r
+  IN EFI_FILE_HANDLE            Handle,\r
+  IN OUT CHAR16                 *Buffer,\r
+  IN OUT UINTN                  *Size,\r
+  IN BOOLEAN                    Truncate,\r
+  IN OUT BOOLEAN                *Ascii\r
+  );\r
+\r
+/**\r
+  Function to read a single line from a file. The \n is not included in the returned\r
+  buffer.  The returned buffer must be callee freed.\r
+\r
+  If the position upon start is 0, then the Ascii Boolean will be set.  This should be\r
+  maintained and not changed for all operations with the same file.\r
+\r
+  @param[in]       Handle        FileHandle to read from.\r
+  @param[in, out]  Ascii         Boolean value for indicating whether the file is\r
+                                 Ascii (TRUE) or UCS2 (FALSE).\r
+\r
+  @return                        The line of text from the file.\r
+\r
+  @sa FileHandleReadLine\r
+**/\r
+CHAR16*\r
+EFIAPI\r
+FileHandleReturnLine(\r
+  IN EFI_FILE_HANDLE            Handle,\r
+  IN OUT BOOLEAN                *Ascii\r
+  );\r
+\r
+/**\r
+  Function to write a line of unicode text to a file.\r
+\r
+  If Handle is NULL, ASSERT.\r
+\r
+  @param[in]     Handle         FileHandle to write to.\r
+  @param[in]     Buffer         Buffer to write, if NULL the function will\r
+                                take no action and return EFI_SUCCESS.\r
+\r
+  @retval  EFI_SUCCESS          The data was written.\r
+  @retval  other                Failure.\r
+\r
+  @sa FileHandleWrite\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+FileHandleWriteLine(\r
+  IN EFI_FILE_HANDLE Handle,\r
+  IN CHAR16          *Buffer\r
+  );\r
+\r
+/**\r
+  Function to take a formatted argument and print it to a file.\r
+\r
+  @param[in] Handle   The file handle for the file to write to.\r
+  @param[in] Format   The format argument (see printlib for the format specifier).\r
+  @param[in] ...      The variable arguments for the format.\r
+\r
+  @retval EFI_SUCCESS The operation was successful.\r
+  @retval other       A return value from FileHandleWriteLine.\r
+\r
+  @sa FileHandleWriteLine\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+FileHandlePrintLine(\r
+  IN EFI_FILE_HANDLE  Handle,\r
+  IN CONST CHAR16     *Format,\r
+  ...\r
+  );\r
+\r
+/**\r
+  Function to determine if a FILE_HANDLE is at the end of the file.\r
+\r
+  This will NOT work on directories.\r
+\r
+  If Handle is NULL, then ASSERT().\r
+\r
+  @param[in] Handle     The file handle.\r
+\r
+  @retval TRUE          The position is at the end of the file.\r
+  @retval FALSE         The position is not at the end of the file.\r
+**/\r
+BOOLEAN\r
+EFIAPI\r
+FileHandleEof(\r
+  IN EFI_FILE_HANDLE Handle\r
+  );\r
+\r
+#endif //_FILE_HANDLE_LIBRARY_HEADER_\r
+\r

diff --git a/Vlv2TbltDevicePkg/Include/Guid/AcpiTableStorage.h b/Vlv2TbltDevicePkg/Include/Guid/AcpiTableStorage.h
new file mode 100644 (file)
index 0000000..663b26d
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Include/Guid/AcpiTableStorage.h
@@ -0,0 +1,35 @@
+/*++\r
+\r
+  Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+\r
+Module Name:\r
+\r
+  AcpiTableStorage.h\r
+\r
+Abstract:\r
+\r
+  GUID for the ACPI Table Storage filename.\r
+\r
+  This GUID is defined in the Tiano ACPI Table Storage EPS.\r
+\r
+--*/\r
+\r
+#ifndef _ACPI_TABLE_STORAGE_H_\r
+#define _ACPI_TABLE_STORAGE_H_\r
+\r
+#define EFI_ACPI_TABLE_STORAGE_GUID \\r
+  { 0x7e374e25, 0x8e01, 0x4fee, {0x87, 0xf2, 0x39, 0xc, 0x23, 0xc6, 0x6, 0xcd} }\r
+\r
+extern EFI_GUID gEfiAcpiTableStorageGuid;\r
+\r
+#endif\r

diff --git a/Vlv2TbltDevicePkg/Include/Guid/AlertStandardFormat.h b/Vlv2TbltDevicePkg/Include/Guid/AlertStandardFormat.h
new file mode 100644 (file)
index 0000000..54df0b5
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Include/Guid/AlertStandardFormat.h
@@ -0,0 +1,91 @@
+/*++\r
+\r
+  Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+Module Name:\r
+\r
+  Asf.h\r
+\r
+Abstract:\r
+\r
+  Alert Standard Format address variable\r
+\r
+--*/\r
+\r
+#ifndef AlertStandardFormat_h_included\r
+#define AlertStandardFormat_h_included\r
+\r
+\r
+#pragma pack(1)\r
+\r
+//\r
+// ASF address\r
+//\r
+//\r
+// {3D995FB4-4F05-4073-BE72-A19CFB5DE690}\r
+//\r
+#define  ALERT_STANDARD_FORMAT_VARIABLE_GUID \\r
+  {0x3d995fb4, 0x4f05, 0x4073, 0xbe, 0x72, 0xa1, 0x9c, 0xfb, 0x5d, 0xe6, 0x90}\r
+\r
+#define ALERT_STANDARD_FORMAT_VARIABLE_NAME (L"ASF")\r
+#define ASCII_ALERT_STANDARD_FORMAT_VARIABLE_NAME ("ASF")\r
+\r
+extern EFI_GUID gAlertStandardFormatGuid;\r
+extern CHAR16   gAlertStandardFormatName[];\r
+\r
+typedef struct {\r
+  UINT8   SmbusAddr;\r
+  struct {\r
+    UINT32  VendorSpecificId;\r
+    UINT16  SubsystemDeviceId;\r
+    UINT16  SubsystemVendorId;\r
+    UINT16  Interface;\r
+    UINT16  DeviceId;\r
+    UINT16  VendorId;\r
+    UINT8   VendorRevision;\r
+    UINT8   DeviceCapabilities;\r
+  } Udid;\r
+  struct {\r
+    UINT8     SubCommand;\r
+    UINT8     Version;\r
+    UINT32    IanaId;\r
+    UINT8     SpecialCommand;\r
+    UINT16    SpecialCommandParam;\r
+    UINT16    BootOptionsBits;\r
+    UINT16    OemParam;\r
+  } AsfBootOptions;\r
+  struct {\r
+    UINT8     Bus;\r
+    UINT8     Device;\r
+    UINT8     Function;\r
+    UINT16    VendorId;\r
+    UINT16    DeviceId;\r
+    UINT16    IderCmdBar;\r
+    UINT16    IderCtrlBar;\r
+    UINT8     IderIrq;\r
+    UINT16    SolBar;\r
+    UINT8     SolIrq;\r
+  } PciInfo;\r
+  struct {\r
+  UINT8   IamtProvisioningStatus;\r
+  BOOLEAN IamtIsProvisioned;\r
+  } IamtInfo;\r
+  struct {\r
+    BOOLEAN FlashUpdatingIsAllowed;\r
+  } MeInfoForEbu;\r
+  UINT32  EitBPFAddress;\r
+} EFI_ASF_VARIABLE;\r
+\r
+#pragma pack()\r
+\r
+#endif\r
+\r

diff --git a/Vlv2TbltDevicePkg/Include/Guid/BiosId.h b/Vlv2TbltDevicePkg/Include/Guid/BiosId.h
new file mode 100644 (file)
index 0000000..15914b8
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Include/Guid/BiosId.h
@@ -0,0 +1,35 @@
+/*++\r
+\r
+Copyright (c)  1999  - 2014, Intel Corporation. All rights reserved\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+\r
+Module Name:\r
+\r
+    BiosId.h\r
+\r
+Abstract:\r
+\r
+    GUIDs used for Bios ID.\r
+\r
+--*/\r
+\r
+#ifndef _BIOS_ID_H_\r
+#define _BIOS_ID_H_\r
+\r
+\r
+#define EFI_BIOS_ID_GUID \\r
+{ 0xC3E36D09, 0x8294, 0x4b97, 0xA8, 0x57, 0xD5, 0x28, 0x8F, 0xE3, 0x3E, 0x28 }\r
+\r
+\r
+extern EFI_GUID gEfiBiosIdGuid;\r
+\r
+#endif\r

diff --git a/Vlv2TbltDevicePkg/Include/Guid/BoardFeatures.h b/Vlv2TbltDevicePkg/Include/Guid/BoardFeatures.h
new file mode 100644 (file)
index 0000000..11bb98b
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Include/Guid/BoardFeatures.h
@@ -0,0 +1,219 @@
+/*++\r
+\r
+  Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+\r
+Module Name:\r
+\r
+    BoardFeatures.h\r
+\r
+Abstract:\r
+\r
+    EFI Platform Board Features\r
+\r
+\r
+\r
+--*/\r
+\r
+#ifndef BoardFeatures_h_included\r
+#define BoardFeatures_h_included\r
+\r
+#include <Base.h>\r
+\r
+#pragma pack(1)\r
+\r
+//\r
+// Board Features\r
+//\r
+#if defined LEGACY_BOARD_FEATURES && LEGACY_BOARD_FEATURES\r
+#define B_BOARD_FEATURES_CHIPSET_LAN           BIT0\r
+#define B_BOARD_FEATURES_LAN_MARVELL           BIT1\r
+#define B_BOARD_FEATURES_AA_NOT_FOUND           BIT2\r
+#define B_BOARD_FEATURES_SIO_NO_COM1           BIT3\r
+#define B_BOARD_FEATURES_SIO_COM2              BIT4\r
+#define B_BOARD_FEATURES_SIO_NO_PARALLEL       BIT5\r
+#define B_BOARD_FEATURES_CHIPSET_VIDEO         BIT6\r
+#define B_BOARD_FEATURES_CHIPSET_VIDEO_OPTION0 BIT7\r
+#define B_BOARD_FEATURES_VIDEO_SLOT            BIT8\r
+#define B_BOARD_FEATURES_MINI_CARD             BIT9\r
+#define B_BOARD_FEATURES_DISCRETE_1394         BIT10\r
+#define B_BOARD_FEATURES_LEGACY_FREE           BIT11\r
+#define B_BOARD_FEATURES_USB_HUB               BIT12\r
+#define B_BOARD_FEATURES_TPM                   BIT13\r
+#define B_BOARD_FEATURES_VIIV                   BIT14\r
+#define B_BOARD_FEATURES_FORM_FACTOR_MASK      (BIT15|BIT16|BIT17|BIT18|BIT19)\r
+#define B_BOARD_FEATURES_FORM_FACTOR_PBTX      BIT15\r
+#define B_BOARD_FEATURES_FORM_FACTOR_ATX       BIT16\r
+#define B_BOARD_FEATURES_FORM_FACTOR_BTX       BIT17\r
+#define B_BOARD_FEATURES_FORM_FACTOR_MICRO_ATX BIT18\r
+#define B_BOARD_FEATURES_FORM_FACTOR_MICRO_BTX BIT19\r
+#define B_BOARD_FEATURES_MEMORY_TYPE_DDR1      BIT20\r
+#define B_BOARD_FEATURES_MEMORY_TYPE_DDR2      BIT21\r
+#define B_BOARD_FEATURES_MEMORY_SLOT_MASK      BIT23 | BIT22\r
+#define   V_BOARD_FEATURES_1_MEMORY_SLOT         0              // BIT22=0, BIT23=0\r
+#define   V_BOARD_FEATURES_2_MEMORY_SLOT         BIT22          // BIT22=1, BIT23=0\r
+#define   V_BOARD_FEATURES_3_MEMORY_SLOT         BIT23          // BIT22=0, BIT23=1\r
+#define   V_BOARD_FEATURES_4_MEMORY_SLOT         BIT23 | BIT22  // BIT22=1, BIT23=1\r
+#define B_BOARD_FEATURES_ALT_MEM_CLK_RT         BIT24\r
+#define B_BOARD_FEATURES_SLEEP_MASK            BIT25\r
+#define   V_BOARD_FEATURES_SLEEP_S1              0              // BIT25=0\r
+#define   V_BOARD_FEATURES_SLEEP_S3              BIT25          // BIT25=1\r
+#define B_BOARD_FEATURES_3JACK_AUDIO_SOLUTION    BIT26          // 0/1= 5/3 Rear Jacks\r
+#define B_BOARD_FEATURES_DISCRETE_SATA         BIT27\r
+#define B_BOARD_FEATURES_2_SATA               BIT28    // 2SATA instead of 4(pre Ich8) or 4 SATA instead of 6(Ich8)\r
+#define B_BOARD_FEATURES_RVP                  BIT29    // Board is an RVP board\r
+#define B_BOARD_FEATURES_PORT80_LPC           BIT30    // Port80 PCI(0) or LPC(1)\r
+#define B_BOARD_FEATURES_LIMITED_CPU_SUPPORT  BIT31    // Limited CPU support\r
+#define B_BOARD_FEATURES_PMP_SUPPORT          BIT32    // Support for over-voltaging memory\r
+#define B_BOARD_FEATURES_HW_WATCHDOG_TIMER    BIT33    // Support for the HW-based 555 Watchdog Timer feature\r
+#define B_BOARD_FEATURES_NO_QRT               BIT34    // disable QRT\r
+#define B_BOARD_FEATURES_VERB_TABLE1          BIT35    // Verb table 1\r
+#define B_BOARD_FEATURES_VERB_TABLE2          BIT36    // Verb table 2\r
+#define B_BOARD_FEATURES_VERB_TABLE3          BIT37    // Verb table 3\r
+#define B_BOARD_FEATURES_VERB_TABLE4          BIT38    // Verb table 4\r
+#define B_BOARD_FEATURES_VERB_TABLE5          BIT39    // Reserved for Verb table 5\r
+#define B_BOARD_FEATURES_VERB_TABLE_MASK      BIT35 | BIT36 | BIT37 | BIT38 | BIT39\r
+#define B_BOARD_FEATURES_KENTSFIELD_BLOCK     BIT40    // Kentsfield not supported\r
+#define B_BOARD_FEATURES_KENTSFIELD_WARNING   BIT41    // Kentsfield warning\r
+#define B_BOARD_FEATURES_ESATA_PORT0          BIT42    // E-SATA on Port0\r
+#define B_BOARD_FEATURES_ESATA_PORT1          BIT43    // E-SATA on Port1\r
+#define B_BOARD_FEATURES_ESATA_PORT2          BIT44    // E-SATA on Port2\r
+#define B_BOARD_FEATURES_ESATA_PORT3          BIT45    // E-SATA on Port3\r
+#define B_BOARD_FEATURES_ESATA_PORT4          BIT46    // E-SATA on Port4\r
+#define B_BOARD_FEATURES_ESATA_PORT5          BIT47    // E-SATA on Port5\r
+#define B_BOARD_FEATURES_ECIR                 BIT48    // Enhanced Consumer IR\r
+#define B_BOARD_FEATURES_PS2WAKEFROMS5        BIT49    // Wake from S5 via PS2 keyboard\r
+#define B_BOARD_FEATURES_HDAUDIOLINK          BIT50    // HD audio link support\r
+#define B_BOARD_FEATURES_1_PATA               BIT51\r
+#define B_BOARD_FEATURES_MOBILE               BIT52\r
+#define B_BOARD_FEATURES_NO_FLOPPY            BIT53\r
+#define B_BOARD_FEATURES_DISABLE_UNUSED_FSB   BIT54\r
+\r
+//\r
+// Bit 55-58 reserved by PSID support.  CPU power requirement below are preliminary.\r
+// They might be changed.\r
+// This is not same as 8.6.1 products so be careful.\r
+//\r
+#define B_BOARD_FEATURES_CPU_POWER_BITNUM     55\r
+#define B_BOARD_FEATURES_CPU_POWER_MASK       (BIT55 | BIT56 | BIT57 | BIT58)\r
+#define B_BOARD_FEATURES_CPU_POWER_35W        0     // Theoretically doesn't exist.\r
+#define B_BOARD_FEATURES_CPU_POWER_40W        BIT55 // 0001\r
+#define B_BOARD_FEATURES_CPU_POWER_45W        BIT56 // 0010\r
+#define B_BOARD_FEATURES_CPU_POWER_50W        (BIT55 | BIT56) // 0011\r
+#define B_BOARD_FEATURES_CPU_POWER_65W        BIT57 // 0100 Wolfdale-H/-M\r
+#define B_BOARD_FEATURES_CPU_POWER_70W        (BIT55 | BIT57) // 0101\r
+#define B_BOARD_FEATURES_CPU_POWER_75W        (BIT56 | BIT57) // 0110\r
+#define B_BOARD_FEATURES_CPU_POWER_80W        (BIT55 | BIT56 | BIT57) // 0111\r
+#define B_BOARD_FEATURES_CPU_POWER_95W        BIT58 // 1000 Yorkfield\r
+#define B_BOARD_FEATURES_CPU_POWER_100W       (BIT55 | BIT58) // 1001\r
+#define B_BOARD_FEATURES_CPU_POWER_105W       (BIT56 | BIT58) // 1010\r
+#define B_BOARD_FEATURES_CPU_POWER_110W       (BIT55 | BIT56 | BIT58) // 1011\r
+#define B_BOARD_FEATURES_CPU_POWER_130W       (BIT57 | BIT58) // 1100 XE Yorkfield\r
+#define B_BOARD_FEATURES_CPU_POWER_135W       (BIT55 | BIT57 | BIT58) // 1101\r
+#define B_BOARD_FEATURES_CPU_POWER_Over135W   (BIT56 | BIT57 | BIT58) // 1110 Reserved\r
+#define B_BOARD_FEATURES_CPU_POWER_140W       (BIT55 | BIT56 | BIT57 | BIT58) // 1111 Reserved\r
+#define B_VV_BOARD_FEATURES                    BIT59\r
+#define B_BOARD_FEATURES_IDCC2_SUPPORT         BIT60 // Include IDCC2 support\r
+#define B_BOARD_FEATURES_NO_SATA_PORT2_3       BIT61 // No SATA Port2&3 Connector, used with B_BOARD_FEATURES_2_SATA flag\r
+#define B_BOARD_FEATURES_FORM_FACTOR_MINI_ITX  BIT62\r
+#define B_BOARD_FEATURES_NPI_QPI_VOLTAGE       BIT63\r
+\r
+#else\r
+\r
+#define B_BOARD_FEATURES_CHIPSET_LAN              BIT0\r
+#define B_BOARD_FEATURES_CHIPSET_VIDEO            BIT1\r
+#define B_BOARD_FEATURES_VIDEO_SLOT               BIT2\r
+#define B_BOARD_FEATURES_AA_NOT_FOUND             BIT3\r
+#define B_BOARD_FEATURES_SIO_NO_COM1              BIT4\r
+#define B_BOARD_FEATURES_SIO_COM2                 BIT5\r
+#define B_BOARD_FEATURES_SIO_NO_PARALLEL          BIT6\r
+#define B_BOARD_FEATURES_NO_FLOPPY                BIT7\r
+#define B_BOARD_FEATURES_PS2WAKEFROMS5            BIT8             // Wake from S5 via PS2 keyboard\r
+#define B_BOARD_FEATURES_ECIR                     BIT9             // Enhanced Consumer IR\r
+#define B_BOARD_FEATURES_LEGACY_FREE              BIT10\r
+#define B_BOARD_FEATURES_MINI_CARD                BIT11\r
+#define B_BOARD_FEATURES_DISCRETE_1394            BIT12\r
+#define B_BOARD_FEATURES_USB_HUB                  BIT13\r
+#define B_BOARD_FEATURES_TPM                      BIT14\r
+#define B_BOARD_FEATURES_FORM_FACTOR_MASK         (BIT15|BIT16|BIT17|BIT18|BIT19|BIT20)\r
+#define B_BOARD_FEATURES_FORM_FACTOR_PBTX         BIT15\r
+#define B_BOARD_FEATURES_FORM_FACTOR_ATX          BIT16\r
+#define B_BOARD_FEATURES_FORM_FACTOR_BTX          BIT17\r
+#define B_BOARD_FEATURES_FORM_FACTOR_MICRO_ATX    BIT18\r
+#define B_BOARD_FEATURES_FORM_FACTOR_MICRO_BTX    BIT19\r
+#define B_BOARD_FEATURES_FORM_FACTOR_MINI_ITX     BIT20\r
+#define B_BOARD_FEATURES_MEMORY_TYPE_DDR2         BIT21\r
+#define B_BOARD_FEATURES_MEMORY_TYPE_DDR3         BIT22\r
+#define B_BOARD_FEATURES_MEMORY_SLOT_MASK         (BIT24 | BIT23)\r
+#define   V_BOARD_FEATURES_1_MEMORY_SLOT            0              // BIT23=0, BIT24=0\r
+#define   V_BOARD_FEATURES_2_MEMORY_SLOT          BIT23            // BIT23=1, BIT24=0\r
+#define   V_BOARD_FEATURES_3_MEMORY_SLOT          BIT24            // BIT23=0, BIT24=1\r
+#define   V_BOARD_FEATURES_4_MEMORY_SLOT          (BIT24 | BIT23)  // BIT23=1, BIT24=1\r
+#define B_BOARD_FEATURES_2_C0_MEMORY_SLOT         BIT25            // 2 Channel 0 memory slot\r
+#define B_BOARD_FEATURES_SLEEP_MASK               BIT26\r
+#define   V_BOARD_FEATURES_SLEEP_S1                 0              // BIT26=0\r
+#define   V_BOARD_FEATURES_SLEEP_S3               BIT26            // BIT26=1\r
+#define B_BOARD_FEATURES_3JACK_AUDIO_SOLUTION     BIT27            // 0/1= 5/3 Rear Jacks\r
+#define B_BOARD_FEATURES_HDAUDIOLINK              BIT28            // HD audio link support\r
+#define B_BOARD_FEATURES_DISCRETE_SATA            BIT29\r
+#define B_BOARD_FEATURES_2_SATA                   BIT30            // 2SATA instead of 4(pre Ich8) or 4 SATA instead of 6(Ich8)\r
+#define B_BOARD_FEATURES_NO_SATA_PORT2_3          BIT31            // No SATA Port2&3 Connector, used with B_BOARD_FEATURES_2_SATA flag\r
+#define B_BOARD_FEATURES_RVP                      BIT32            // Board is an RVP board\r
+#define B_BOARD_FEATURES_ESATA_PORT0              BIT33            // E-SATA on Port0\r
+#define B_BOARD_FEATURES_ESATA_PORT1              BIT34            // E-SATA on Port1\r
+#define B_BOARD_FEATURES_ESATA_PORT2              BIT35            // E-SATA on Port2\r
+#define B_BOARD_FEATURES_ESATA_PORT3              BIT36            // E-SATA on Port3\r
+#define B_BOARD_FEATURES_ESATA_PORT4              BIT37            // E-SATA on Port4\r
+#define B_BOARD_FEATURES_ESATA_PORT5              BIT38            // E-SATA on Port5\r
+#define B_BOARD_FEATURES_IDCC2_SUPPORT            BIT39            // Include IDCC2 support\r
+#define B_BOARD_FEATURES_NPI_QPI_VOLTAGE          BIT40\r
+#define B_BOARD_FEATURES_LIMITED_CPU_SUPPORT      BIT41            // Limited CPU support\r
+#define B_BOARD_FEATURES_PMP_SUPPORT              BIT42            // Support for over-voltaging memory\r
+#define B_BOARD_FEATURES_HW_WATCHDOG_TIMER        BIT43            // Support for the HW-based 555 Watchdog Timer feature\r
+#define B_BOARD_FEATURES_LVDS                     BIT44            // Support for LVDS\r
+#define B_BOARD_FEATURES_VERB_TABLE_MASK          (BIT45|BIT46|BIT47|BIT48)    // Verb table\r
+#define B_BOARD_FEATURES_VERB_TABLE1              BIT45            // Verb table 1\r
+#define B_BOARD_FEATURES_VERB_TABLE2              BIT46            // Verb table 2\r
+#define B_BOARD_FEATURES_VERB_TABLE3              BIT47            // Verb table 3\r
+#define B_BOARD_FEATURES_VERB_TABLE4              BIT48            // Verb table 4\r
+#define B_BOARD_FEATURES_NO_MINIPCIE              BIT49            // Mini PCIe slot\r
+#define B_BOARD_FEATURES_HDMI_SLOT                BIT50            // HDMI slot\r
+#define B_BOARD_FEATURES_PS2_HIDE                 BIT51            // PS2 hide\r
+#define B_BOARD_FEATURES_DVID_SLOT                BIT52            // DVID slot\r
+\r
+#define B_BOARD_FEATURES_SIO_COM3                 BIT53\r
+#define B_BOARD_FEATURES_SIO_COM4                 BIT54\r
+\r
+#define B_BOARD_FEATURES_LAN2                     BIT55\r
+#define B_BOARD_FEATURES_PCIe_SLOT                BIT56\r
+#endif\r
+\r
+typedef UINT64 EFI_BOARD_FEATURES;\r
+\r
+#pragma pack()\r
+\r
+//\r
+// Global ID for the Platform Boot Mode Protocol.\r
+//\r
+#define EFI_BOARD_FEATURES_GUID \\r
+  { 0x94b9e8ae, 0x8877, 0x479a, 0x98, 0x42, 0xf5, 0x97, 0x4b, 0x82, 0xce, 0xd3 }\r
+\r
+extern EFI_GUID gEfiBoardFeaturesGuid;\r
+\r
+#define BOARD_FEATURES_NAME   L"BoardFeatures"\r
+\r
+#define EFI_BOARD_ID_GUID \\r
+  { 0x6b2dd245, 0x3f2, 0x414a, 0x8c, 0x2, 0x9f, 0xfc, 0x23, 0x52, 0xe3, 0x1e }\r
+#define EFI_BOARD_ID_NAME (L"BoardId")\r
+\r
+#endif\r
+\r

diff --git a/Vlv2TbltDevicePkg/Include/Guid/EfiVpdData.h b/Vlv2TbltDevicePkg/Include/Guid/EfiVpdData.h
new file mode 100644 (file)
index 0000000..31fa3e0
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Include/Guid/EfiVpdData.h
@@ -0,0 +1,161 @@
+/*++\r
+\r
+  Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+\r
+Module Name:\r
+\r
+  EfiVpdData.h\r
+\r
+Abstract:\r
+\r
+  Constants and declarations that are common accross PEI and DXE.\r
+--*/\r
+\r
+#ifndef _EFI_VPD_DATA_H_\r
+#define _EFI_VPD_DATA_H_\r
+\r
+\r
+#pragma pack(1)\r
+\r
+//\r
+// DMI data\r
+//\r
+typedef struct {\r
+\r
+  CHAR8 DmiGpnvHeader[4];             // $DMI\r
+  CHAR8 SystemInfoManufacturer[0x20]; // Structure Type 1 String 1\r
+  CHAR8 SystemInfoProductName[0x20];  // Structure Type 1 String 2\r
+  CHAR8 SystemInfoVersion[0x18];      // Structure Type 1 String 3\r
+  CHAR8 SystemInfoSerialNumber[0x20]; // Structure Type 1 String 4\r
+  CHAR8 BaseBoardManufacturer[0x20];  // Structure Type 2 String 1\r
+  CHAR8 BaseBoardProductName[0x20];   // Structure Type 2 String 2\r
+  CHAR8 BaseBoardVersion[0x18];       // Structure Type 2 String 3\r
+  CHAR8 BaseBoardSerialNumber[0x20];  // Structure Type 2 String 4\r
+  CHAR8 ChassisManufacturer[0x20];    // Structure Type 3 String 1\r
+  UINT8 ChassisType;                  // Enumerated\r
+  CHAR8 ChassisVersion[0x18];         // Structure Type 3 String 2\r
+  CHAR8 ChassisSerialNumber[0x20];    // Structure Type 3 String 3\r
+  CHAR8 ChassisAssetTag[0x20];        // Structure Type 3 String 4\r
+  UINT8 MfgAccessKeyWorkspace;\r
+\r
+  UINT8 ChecksumFixupPool[0xd];       // Checksum Fix-ups\r
+  UINT8 SwitchboardData[4];           // 32 switch switchboard\r
+  UINT8 IntelReserved;                // Reserved for Future Use\r
+} DMI_DATA;\r
+\r
+#define DMI_DATA_GUID \\r
+  { \\r
+    0x70e56c5e, 0x280c, 0x44b0, 0xa4, 0x97, 0x09, 0x68, 0x1a, 0xbc, 0x37, 0x5e \\r
+  }\r
+\r
+#define DMI_DATA_NAME       (L"DmiData")\r
+#define ASCII_DMI_DATA_NAME ("DmiData")\r
+\r
+extern EFI_GUID gDmiDataGuid;\r
+extern CHAR16   gDmiDataName[];\r
+\r
+//\r
+// UUID - universally unique system id.\r
+//\r
+#define UUID_VARIABLE_GUID \\r
+  { \\r
+    0xd357c710, 0x0ada, 0x4717, 0x8d, 0xba, 0xc6, 0xad, 0xc7, 0xcd, 0x2b, 0x2a \\r
+  }\r
+\r
+#define UUID_VARIABLE_NAME        (L"UUID")\r
+#define ASCII_UUID_VARIABLE_NAME  ("UUID")\r
+\r
+//\r
+// UUID data\r
+//\r
+typedef struct {\r
+  UINT32        UuidHigh;\r
+  UINT32        UuidLow;\r
+} SYSTEM_1394_UUID;\r
+\r
+typedef struct {\r
+  EFI_GUID          SystemUuid;                   // System Unique ID\r
+  SYSTEM_1394_UUID  System1394Uuid;               // Onboard 1394 UUID\r
+} UUID_DATA;\r
+\r
+extern EFI_GUID gUuidVariableGuid;\r
+extern CHAR16   gUuidVariableName[];\r
+\r
+//\r
+// MB32GUID for Computrace.\r
+//\r
+\r
+#define               MB32_GUID \\r
+  { 0x539D62BA, 0xDE35, 0x453E, 0xBA, 0xB0, 0x85, 0xDB, 0x8D, 0xA2, 0x42, 0xF9 }\r
+\r
+#define MB32_VARIABLE_NAME (L"MB32")\r
+#define ASCII_MB32_VARIABLE_NAME ("MB32")\r
+\r
+extern EFI_GUID gMb32Guid;\r
+extern CHAR16   gMb32VariableName[];\r
+\r
+//\r
+// ACPI OSFR Manufacturer String.\r
+//\r
+// {72234213-0FD7-48a1-A59F-B41BC107FBCD}\r
+//\r
+#define  ACPI_OSFR_MFG_STRING_VARIABLE_GUID \\r
+  {0x72234213, 0xfd7, 0x48a1, 0xa5, 0x9f, 0xb4, 0x1b, 0xc1, 0x7, 0xfb, 0xcd}\r
+#define ACPI_OSFR_MFG_STRING_VARIABLE_NAME (L"OcurMfg")\r
+#define ASCII_ACPI_OSFR_MF_STRING_VARIABLE_NAME ("OcurMfg")\r
+\r
+extern EFI_GUID gACPIOSFRMfgStringVariableGuid;\r
+\r
+\r
+//\r
+// ACPI OSFR Model String.\r
+//\r
+// {72234213-0FD7-48a1-A59F-B41BC107FBCD}\r
+//\r
+#define  ACPI_OSFR_MODEL_STRING_VARIABLE_GUID \\r
+  {0x72234213, 0xfd7, 0x48a1, 0xa5, 0x9f, 0xb4, 0x1b, 0xc1, 0x7, 0xfb, 0xcd}\r
+#define ACPI_OSFR_MODEL_STRING_VARIABLE_NAME (L"OcurModel")\r
+#define ASCII_ACPI_OSFR_MODEL_STRING_VARIABLE_NAME ("OcurModel")\r
+\r
+extern EFI_GUID gACPIOSFRModelStringVariableGuid;\r
+\r
+//\r
+// ACPI OSFR Reference Data Block.\r
+//\r
+// {72234213-0FD7-48a1-A59F-B41BC107FBCD}\r
+//\r
+#define  ACPI_OSFR_REF_DATA_BLOCK_VARIABLE_GUID \\r
+  {0x72234213, 0xfd7, 0x48a1, 0xa5, 0x9f, 0xb4, 0x1b, 0xc1, 0x7, 0xfb, 0xcd}\r
+#define ACPI_OSFR_REF_DATA_BLOCK_VARIABLE_NAME (L"OcurRef")\r
+#define ASCII_ACPI_OSFR_REF_DATA_BLOCK_VARIABLE_NAME ("OcurRef")\r
+extern EFI_GUID gACPIOSFRRefDataBlockVariableGuid;\r
+\r
+//\r
+// Manufacturing mode GUID\r
+//\r
+#define MfgMode_GUID \\r
+  { 0xEF14FD78, 0x0793, 0x4e2b, 0xAC, 0x6D, 0x06, 0x28, 0x47, 0xE0, 0x17, 0x91 }\r
+\r
+#define MFGMODE_VARIABLE_NAME (L"MfgMode")\r
+#define ASCII_MFGMODE_VARIABLE_NAME ("MfgMode")\r
+\r
+typedef struct {\r
+       UINT8 MfgModeData;\r
+} MFG_MODE_VAR;\r
+\r
+extern EFI_GUID gMfgModeVariableGuid;\r
+extern CHAR16   gMfgModeVariableName[];\r
+\r
+#pragma pack()\r
+\r
+#endif\r

diff --git a/Vlv2TbltDevicePkg/Include/Guid/FirmwareId.h b/Vlv2TbltDevicePkg/Include/Guid/FirmwareId.h
new file mode 100644 (file)
index 0000000..061ded0
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Include/Guid/FirmwareId.h
@@ -0,0 +1,66 @@
+/*++\r
+\r
+  Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+\r
+Module Name:\r
+\r
+  FirmwareId.h\r
+\r
+--*/\r
+\r
+#ifndef _FirmwareId_h_GUID_included\r
+#define _FirmwareId_h_GUID_included\r
+\r
+\r
+#pragma pack(1)\r
+\r
+//\r
+// Firmware ID\r
+//\r
+\r
+#define FIRMWARE_ID_MAX_LENGTH      35\r
+\r
+typedef struct {\r
+  CHAR8    BiosId[8];\r
+  CHAR8    Separator1;\r
+  CHAR8    OemId[3];\r
+  CHAR8    Separator2;\r
+  CHAR8    BuildId[4];\r
+  CHAR8    Separator3;\r
+  CHAR8    Century[2];\r
+  CHAR8    Year[2];\r
+  CHAR8    Separator4;\r
+  CHAR8    Month[2];\r
+  CHAR8    Date[2];\r
+  CHAR8    Separator5;\r
+  CHAR8    Hour[2];\r
+  CHAR8    Minute[2];\r
+  CHAR8    Dummy[3];\r
+} FIRMWARE_ID_DATA;\r
+\r
+#define  OLD_FIRMWARE_ID_GUID \\r
+  {0xefc071ae, 0x41b8, 0x4018, 0xaf, 0xa7, 0x31, 0x4b, 0x18, 0x5e, 0x57, 0x8b}\r
+\r
+#define  FIRMWARE_ID_GUID \\r
+  {0x5e559c23, 0x1faa, 0x4ae1, 0x8d, 0x4a, 0xc6, 0xcf, 0x02, 0x6c, 0x76, 0x6f}\r
+\r
+#define FIRMWARE_ID_NAME L"FirmwareId"\r
+#define FIRMWARE_ID_NAME_WITH_PASSWORD FIRMWARE_ID_NAME L"H#8,^-!t"\r
+\r
+extern EFI_GUID gFirmwareIdGuid;\r
+extern CHAR16   gFirmwareIdName[];\r
+\r
+#pragma pack()\r
+\r
+#endif\r
+\r

diff --git a/Vlv2TbltDevicePkg/Include/Guid/HwWatchdogTimerHob.h b/Vlv2TbltDevicePkg/Include/Guid/HwWatchdogTimerHob.h
new file mode 100644 (file)
index 0000000..cfb2228
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Include/Guid/HwWatchdogTimerHob.h
@@ -0,0 +1,139 @@
+/*++\r
+\r
+  Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+\r
+Module Name:\r
+\r
+  HwWatchdogTimerHob.h\r
+\r
+Abstract:\r
+\r
+  GUID used for Watchdog Timer status in the HOB list.\r
+\r
+--*/\r
+\r
+#ifndef _EFI_WATCHDOG_TIMER_HOB_GUID_H_\r
+#define _EFI_WATCHDOG_TIMER_HOB_GUID_H_\r
+\r
+#define EFI_WATCHDOG_TIMER_HOB_GUID \\r
+  { 0x226cd3f, 0x69b5, 0x4150, 0xac, 0xbe, 0xbf, 0xbf, 0x18, 0xe3, 0x3, 0xd5 }\r
+\r
+#define EFI_WATCHDOG_TIMER_DEFINITION_HOB_GUID \\r
+  { 0xd29302b0, 0x11ba, 0x4073, 0xa2, 0x27, 0x53, 0x8d, 0x25, 0x42, 0x70, 0x9f }\r
+\r
+typedef enum {\r
+  HWWD_NONE,\r
+  HWWD_TIMER_EXPIRED,\r
+  HWWD_SPONTANEOUS_REBOOT,\r
+  HWWD_FORCED_TIMEOUT\r
+} HW_WATCHDOG_TIMEOUT;\r
+\r
+typedef struct {\r
+  HW_WATCHDOG_TIMEOUT         TimeoutStatus;\r
+} HW_WATCHDOG_INFO;\r
+\r
+//\r
+// Watchdog timer action values.\r
+//\r
+#define WDT_ACTION_RESET                    0x01    // reload/reset timer\r
+#define WDT_ACTION_QUERY_CURRENT_VALUE      0x04    // get current value                     // DON'T NEED FOR OVERCLOCK UTILITY\r
+#define WDT_ACTION_QUERY_COUNTDOWN_PERIOD   0x05    // get countdown period\r
+#define WDT_ACTION_SET_COUNTDOWN_PERIOD     0x06    // set countdown period\r
+#define WDT_ACTION_QUERY_RUNNING_STATE      0x08    // query if running\r
+#define WDT_ACTION_SET_RUNNING_STATE        0x09    // start timer\r
+#define WDT_ACTION_QUERY_STOPPED_STATE      0x0A    // query if stopped\r
+#define WDT_ACTION_SET_STOPPED_STATE        0x0B    // stop timer\r
+#define WDT_ACTION_QUERY_STATUS             0x20    // is current boot cause by wdt timeout?\r
+#define WDT_ACTION_SET_STATUS               0x21    // resets wdt status bit\r
+\r
+//\r
+// Watchdog timer instruction values.\r
+//\r
+#define WDT_INSTR_VALUE_MASK                0x03    // Mask for just the value\r
+#define WDT_INSTR_READ_CMP_VALUE            0x00    // Read / compare value\r
+#define WDT_INSTR_READ_COUNTDOWN            0x01    // read countdown value\r
+#define WDT_INSTR_WRITE_VALUE               0x02    // Write value\r
+#define WDT_INSTR_WRITE_COUNTDOWN           0x03    // write countdown value\r
+#define WDT_INSTR_PRESERVE_REG              0x80    // preserve reg; used in Write Value / Write Countdown\r
+#define WDT_INSTR_WRITE_VALUE_PRES         (0x02 | WDT_INSTR_PRESERVE_REG)   // Write value with preserve\r
+#define WDT_INSTR_WRITE_COUNTDOWN_PRES     (0x03 | WDT_INSTR_PRESERVE_REG)   // write countdown value with preserve\r
+\r
+//\r
+// The Generic Address Structure is defined in the ACPI Specification and should only be\r
+// changed to match updated revisions of that specification.  The GAS_ADDRESS_SPACE and\r
+// GAS_ACCESS_SIZE enumerations are also defined by the ACPI Specification.\r
+//\r
+typedef enum {\r
+  GAS_SYSTEM_MEMORY,\r
+  GAS_SYSTEM_IO,\r
+  GAS_PCI_CONFIG_SPACE,\r
+  GAS_EMBEDDED_CONTROLLER,\r
+  GAS_SMBUS\r
+} GAS_ADDRESS_SPACE;\r
+\r
+typedef enum {\r
+  GAS_UNDEFINED,\r
+  GAS_BYTE_ACCESS,\r
+  GAS_WORD_ACCESS,\r
+  GAS_DWORD_ACCESS,\r
+  GAS_QWORD_ACCESS\r
+} GAS_ACCESS_SIZE;\r
+\r
+#pragma pack(1)\r
+\r
+typedef struct {\r
+  UINT8                       AddressSpaceId;\r
+  UINT8                       RegisterBitWidth;\r
+  UINT8                       RegisterBitOffset;\r
+  UINT8                       AccessSize;\r
+  UINT64                      Address;\r
+} GENERIC_ADDRESS_STRUCTURE;\r
+\r
+//\r
+// GAS_SYSTEM_MEMORY -    When used as the AddressSpaceId, the 64-bit physical memory address\r
+//                        of the register.  32-bit platforms must have the high DWORD set to 0.\r
+// GAS_SYSTEM_IO -        The 64-bit I/O address of the register.  32-bit platforms must have\r
+//                        the high DWORD set to 0.\r
+// GAS_PCI_CONFIG_SPACE - PCI Configuration space addresses must be confined to devices on PCI\r
+//                        Sepment Group 0, Bus 0.  This restriction exists to accommodate access\r
+//                        to fixed hardware prior to PCI bus enumeration.  The format of addresses\r
+//                        are defined as follows:\r
+//                            Highest WORD: Reserved and must be -0-\r
+//                            ...           PCI Device number on bus 0\r
+//                            ...           PCI Function number\r
+//                            Lowest WORD:  Offset in the configuration space header.\r
+//\r
+\r
+typedef struct {\r
+  UINT8                       WdAction;\r
+  UINT8                       Flag;\r
+  UINT16                      Res;\r
+  GENERIC_ADDRESS_STRUCTURE   GenericAddressStructures;\r
+  UINT32                      Value;\r
+  UINT32                      Mask;\r
+} WD_INSTRUCTION;\r
+\r
+typedef struct {\r
+  UINT32                      TimerPeriod;\r
+  UINT32                      MaxTimerCount;\r
+  UINT32                      MinTimerCount;\r
+  UINT16                      InstructionCount;\r
+  WD_INSTRUCTION              ActionDefinitions[1];\r
+} WD_HOB_DEFINITION;\r
+\r
+#pragma pack()\r
+\r
+extern EFI_GUID gWatchdogTimerHobGuid;\r
+extern EFI_GUID gWatchdogTimerDefinitionHobGuid;\r
+\r
+#endif // _EFI_WATCHDOG_TIMER_HOB_GUID_H_\r

diff --git a/Vlv2TbltDevicePkg/Include/Guid/IdccData.h b/Vlv2TbltDevicePkg/Include/Guid/IdccData.h
new file mode 100644 (file)
index 0000000..fa8988b
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Include/Guid/IdccData.h
@@ -0,0 +1,109 @@
+/*++\r
+\r
+  Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+\r
+Module Name:\r
+\r
+  IdccData.h\r
+\r
+Abstract:\r
+\r
+--*/\r
+\r
+#ifndef _IDCCDATAHUB_GUID_H_\r
+#define _IDCCDATAHUB_GUID_H_\r
+\r
+//\r
+// This GUID is for the IDCC related data found in the Data Hub.\r
+//\r
+#define IDCC_DATA_HUB_GUID \\r
+  { 0x788e1d9f, 0x1eab, 0x47d2, 0xa2, 0xf3, 0x78, 0xca, 0xe8, 0x7d, 0x60, 0x12 }\r
+\r
+extern EFI_GUID gIdccDataHubGuid;\r
+\r
+#pragma pack(1)\r
+\r
+typedef struct {\r
+  UINT32    Type;\r
+  UINT32    RecordLength;\r
+} EFI_IDCC_DATA_HEADER;\r
+\r
+typedef struct {\r
+  EFI_IDCC_DATA_HEADER  IdccHeader;\r
+  UINT32                Tcontrol;\r
+} EFI_IDCC_TCONTROL;\r
+\r
+typedef struct {\r
+  UINT32    EntryCount;\r
+} EFI_IDCC_CLOCK_COMMON;\r
+\r
+typedef struct {\r
+  UINT8     Polarity;\r
+  UINT8     Percent;\r
+  UINT32    FpValue;\r
+} EFI_IDCC_TYPE_2_DATA;\r
+\r
+typedef struct {\r
+  UINT8     SetupVal;\r
+  UINT32    FpValue;\r
+} EFI_IDCC_TYPE_3_4_DATA;\r
+\r
+typedef struct {\r
+  EFI_IDCC_DATA_HEADER  IdccHeader;\r
+  UINT32                ProcessorRatio;\r
+} EFI_IDCC_PROCESSOR_RATIO;\r
+\r
+typedef struct {\r
+  EFI_IDCC_DATA_HEADER  IdccHeader;\r
+  UINT32                BoardFormFactor;\r
+} EFI_IDCC_BOARD_FORM_FACTOR;\r
+\r
+typedef struct {\r
+  EFI_IDCC_DATA_HEADER  IdccHeader;\r
+  UINT32                ProcessorInfo;\r
+} EFI_IDCC_PROCESSOR_INFO;\r
+\r
+#define EFI_IDCC_PROCESSOR_UNCON    (1 << 0)  // Bit 0: UnCon CPU\r
+#define EFI_IDCC_PROCESSOR_UNLOCK   (1 << 1)  // Bit 1: UnLock CPU\r
+#define EFI_IDCC_PROCESSOR_CNR      (1 << 2)  // Bit 2: CNR CPU\r
+#define EFI_IDCC_PROCESSOR_KNF      (1 << 3)  // Bit 3: KNF CPU\r
+\r
+typedef struct {\r
+  EFI_IDCC_DATA_HEADER  IdccHeader;\r
+  UINT32    MinFSB;\r
+  UINT32    MaxFSB;\r
+  UINT8     StepFSB;\r
+} EFI_IDCC_FSB_DATA;\r
+\r
+#pragma pack()\r
+\r
+#define EFI_IDCC_POSITIVE   0\r
+#define EFI_IDCC_NEGATIVE   1\r
+\r
+//\r
+// Board Form Factor equates.\r
+//\r
+#define ATX_FORM_FACTOR                0x00\r
+#define BTX_FORM_FACTOR                0x01\r
+\r
+\r
+#define EFI_IDCC_TCONTROL_TYPE          1\r
+#define EFI_IDCC_FSB_TYPE               2\r
+#define EFI_IDCC_PCI_TYPE               3\r
+#define EFI_IDCC_PCIE_TYPE              4\r
+#define EFI_IDCC_PROC_RATIO_TYPE        5\r
+#define EFI_IDCC_BOARD_FORM_FACTOR_TYPE 6\r
+#define EFI_IDCC_PROC_INFO_TYPE         7\r
+#define EFI_IDCC_FSB_DATA_TYPE          8\r
+\r
+#endif\r

diff --git a/Vlv2TbltDevicePkg/Include/Guid/ItkData.h b/Vlv2TbltDevicePkg/Include/Guid/ItkData.h
new file mode 100644 (file)
index 0000000..3e02fd4
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Include/Guid/ItkData.h
@@ -0,0 +1,75 @@
+/*++\r
+\r
+  Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+Module Name:\r
+\r
+  ItkData.h\r
+\r
+Abstract:\r
+\r
+--*/\r
+\r
+#ifndef _ITKDATAHUB_GUID_H_\r
+#define _ITKDATAHUB_GUID_H_\r
+\r
+//\r
+// This GUID is for the ITK related data found in the Data Hub {E7060843-A336-4d5b-9598-13402F5D7375}\r
+//\r
+#define ITK_DATA_HUB_GUID \\r
+  { 0xe7060843, 0xa336, 0x4d5b, 0x95, 0x98, 0x13, 0x40, 0x2f, 0x5d, 0x73, 0x75 }\r
+\r
+extern EFI_GUID gItkDataHubGuid;\r
+\r
+//\r
+// This GUID is for the ITK related data found in a Variable  {3812723D-7E48-4e29-BC27-F5A39AC94EF1}\r
+//\r
+#define ITK_DATA_VAR_GUID \\r
+  { 0x3812723d, 0x7e48, 0x4e29, 0xbc, 0x27, 0xf5, 0xa3, 0x9a, 0xc9, 0x4e, 0xf1 }\r
+\r
+extern EFI_GUID gItkDataVarGuid;\r
+\r
+#define ITK_DATA_VAR_NAME L"ItkDataVar"\r
+\r
+extern CHAR16 gItkDataVarName[];\r
+\r
+#define ITK_BIOS_MOD_VAR_NAME L"ItkBiosModVar"\r
+\r
+extern CHAR16 gItkBiosModVarName[];\r
+\r
+#pragma pack(1)\r
+typedef struct {\r
+  UINT32    Type;\r
+  UINT32    RecordLength;\r
+} EFI_ITK_DATA_HEADER;\r
+\r
+typedef struct {\r
+  EFI_ITK_DATA_HEADER   ItkHeader;\r
+  UINT32                HecetaAddress;\r
+} EFI_ITK_HECETA_ADDRESS;\r
+\r
+typedef struct {\r
+  UINT16    VarEqName;\r
+  UINT16    VarEqValue;\r
+} EFI_ITK_VAR_EQ_RECORD;\r
+\r
+typedef struct {\r
+  EFI_ITK_DATA_HEADER   ItkHeader;\r
+  EFI_ITK_VAR_EQ_RECORD VarEqRecord[0x10000];\r
+} EFI_ITK_VAR_EQ;\r
+#pragma pack()\r
+\r
+#define EFI_ITK_HECETA_ADDRESS_TYPE    1\r
+#define EFI_ITK_MOBILE_BIOS_TYPE       2\r
+#define EFI_ITK_VAR_EQ_TYPE            3\r
+\r
+#endif\r

diff --git a/Vlv2TbltDevicePkg/Include/Guid/MemoryConfigData.h b/Vlv2TbltDevicePkg/Include/Guid/MemoryConfigData.h
new file mode 100644 (file)
index 0000000..6780b3f
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Include/Guid/MemoryConfigData.h
@@ -0,0 +1,37 @@
+/*++\r
+\r
+  Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+\r
+\r
+Module Name:\r
+\r
+  MemoryConfigData.h\r
+\r
+Abstract:\r
+\r
+  GUID used for Memory Configuration Data entries in the HOB list.\r
+\r
+--*/\r
+\r
+#ifndef _MEMORY_CONFIG_DATA_GUID_H_\r
+#define _MEMORY_CONFIG_DATA_GUID_H_\r
+\r
+#define EFI_MEMORY_CONFIG_DATA_GUID \\r
+  { \\r
+    0x80dbd530, 0xb74c, 0x4f11, 0x8c, 0x03, 0x41, 0x86, 0x65, 0x53, 0x28, 0x31 \\r
+  }\r
+\r
+extern EFI_GUID gEfiMemoryConfigDataGuid;\r
+extern CHAR16   EfiMemoryConfigVariable[];\r
+\r
+#endif\r

diff --git a/Vlv2TbltDevicePkg/Include/Guid/OsSelection.h b/Vlv2TbltDevicePkg/Include/Guid/OsSelection.h
new file mode 100644 (file)
index 0000000..3e65ae6
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Include/Guid/OsSelection.h
@@ -0,0 +1,90 @@
+/*++\r
+\r
+  Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+\r
+Module Name:\r
+\r
+  OsSelection.h\r
+\r
+Abstract:\r
+\r
+  GUID used for LPSS, SCC and LPE configuration data entries in the HOB list.\r
+\r
+--*/\r
+\r
+#ifndef _OS_SELECTION_GUID_H_\r
+#define _OS_SELECTION_GUID_H_\r
+\r
+#ifndef ECP_FLAG\r
+#include <PiPei.h>\r
+\r
+#include <Library/HobLib.h>\r
+#include <Library/IoLib.h>\r
+#include <Library/DebugLib.h>\r
+#endif\r
+\r
+#define ANDROID 1\r
+\r
+#define EFI_OS_SELECTION_VARIABLE_GUID \\r
+  { \\r
+    0x86843f56, 0x675d, 0x40a5, 0x95, 0x30, 0xbc, 0x85, 0x83, 0x72, 0xf1, 0x03 \\r
+  }\r
+\r
+extern EFI_GUID gOsSelectionVariableGuid;\r
+\r
+#pragma pack(1)\r
+\r
+typedef struct {\r
+  UINT8           LpssPciModeEnabled;\r
+  //SCC\r
+  UINT8           LpsseMMCEnabled;\r
+  UINT8           LpssSdioEnabled;\r
+  UINT8           LpssSdcardEnabled;\r
+  UINT8           LpssSdCardSDR25Enabled;\r
+  UINT8           LpssSdCardDDR50Enabled;\r
+  UINT8           LpssMipiHsi;\r
+  UINT8           LpsseMMC45Enabled;\r
+  UINT8           LpsseMMC45DDR50Enabled;\r
+  UINT8           LpsseMMC45HS200Enabled;\r
+  UINT8           LpsseMMC45RetuneTimerValue;\r
+  UINT8           eMMCBootMode;\r
+  //LPSS2\r
+  UINT8           LpssDma1Enabled;\r
+  UINT8           LpssI2C0Enabled;\r
+  UINT8           LpssI2C1Enabled;\r
+  UINT8           LpssI2C2Enabled;\r
+  UINT8           LpssI2C3Enabled;\r
+  UINT8           LpssI2C4Enabled;\r
+  UINT8           LpssI2C5Enabled;\r
+  UINT8           LpssI2C6Enabled;\r
+  //LPSS1\r
+  UINT8           LpssDma0Enabled;\r
+  UINT8           LpssPwm0Enabled;\r
+  UINT8           LpssPwm1Enabled;\r
+  UINT8           LpssHsuart0Enabled;\r
+  UINT8           LpssHsuart1Enabled;\r
+  UINT8           LpssSpiEnabled;\r
+  UINT8           I2CTouchAd;\r
+} EFI_PLATFORM_LPSS_DATA;\r
+\r
+typedef struct _EFI_OS_SELECTION_HOB {\r
+  UINT8                       OsSelection;\r
+  UINT8                       OsSelectionChanged;\r
+  UINT8                       Lpe;\r
+  UINT8                       PchAzalia;\r
+  EFI_PLATFORM_LPSS_DATA      LpssData;\r
+} EFI_OS_SELECTION_HOB;\r
+\r
+#pragma pack()\r
+\r
+#endif\r

diff --git a/Vlv2TbltDevicePkg/Include/Guid/PciLanInfo.h b/Vlv2TbltDevicePkg/Include/Guid/PciLanInfo.h
new file mode 100644 (file)
index 0000000..775f710
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Include/Guid/PciLanInfo.h
@@ -0,0 +1,44 @@
+/*++\r
+\r
+  Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+\r
+Module Name:\r
+\r
+  PciLanInfo.h\r
+\r
+Abstract:\r
+\r
+--*/\r
+\r
+#ifndef _PCI_LAN_INFO_GUID_H_\r
+#define _PCI_LAN_INFO_GUID_H_\r
+\r
+#pragma pack(1)\r
+\r
+//\r
+// structure used for Pci Lan variable\r
+//\r
+typedef struct {\r
+  UINT8         PciBus;\r
+  UINT8         PciDevice;\r
+  UINT8         PciFunction;\r
+} PCI_LAN_INFO;\r
+\r
+#pragma pack()\r
+\r
+#define EFI_PCI_LAN_INFO_GUID \\r
+  {0xd9a1427, 0xe02a, 0x437d, 0x92, 0x6b, 0xaa, 0x52, 0x1f, 0xd7, 0x22, 0xba};\r
+\r
+extern EFI_GUID gEfiPciLanInfoGuid;\r
+\r
+#endif\r

diff --git a/Vlv2TbltDevicePkg/Include/Guid/PlatformCpuInfo.h b/Vlv2TbltDevicePkg/Include/Guid/PlatformCpuInfo.h
new file mode 100644 (file)
index 0000000..ec9db67
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Include/Guid/PlatformCpuInfo.h
@@ -0,0 +1,185 @@
+/*++\r
+\r
+  Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+\r
+Module Name:\r
+\r
+  PlatformCpuInfo.h\r
+\r
+Abstract:\r
+\r
+  GUID used for Platform CPU Info Data entries in the HOB list.\r
+\r
+--*/\r
+\r
+#ifndef _PLATFORM_CPU_INFO_GUID_H_\r
+#define _PLATFORM_CPU_INFO_GUID_H_\r
+\r
+#include "CpuType.h"\r
+#include <Library/CpuIA32.h>\r
+\r
+#define EFI_PLATFORM_CPU_INFO_GUID \\r
+  {\\r
+    0xbb9c7ab7, 0xb8d9, 0x4bf3, 0x9c, 0x29, 0x9b, 0xf3, 0x41, 0xe2, 0x17, 0xbc \\r
+  }\r
+\r
+extern EFI_GUID gEfiPlatformCpuInfoGuid;\r
+extern CHAR16   EfiPlatformCpuInfoVariable[];\r
+\r
+//\r
+// Tri-state for feature capabilities and enable/disable.\r
+// [0] clear=feature isn't capable\r
+// [0] set  =feature is capable\r
+// [1] clear=feature is disabled\r
+// [1] set  =feature is enabled\r
+//\r
+#define CPU_FEATURES_CAPABLE      BIT0\r
+#define CPU_FEATURES_ENABLE       BIT1\r
+\r
+#define MAX_CACHE_DESCRIPTORS     64\r
+#define MAXIMUM_CPU_BRAND_STRING_LENGTH 48\r
+\r
+#pragma pack(1)\r
+\r
+typedef struct {\r
+  UINT32              FullCpuId;                // [31:0] & 0x0FFF0FFF\r
+  UINT32              FullFamilyModelId;        // [31:0] & 0x0FFF0FF0\r
+  UINT8               ExtendedFamilyId;         // [27:20]\r
+  UINT8               ExtendedModelId;          // [19:16]\r
+  UINT8               ProcessorType;            // [13:11]\r
+  UINT8               FamilyId;                 // [11:8]\r
+  UINT8               Model;                    // [7:4]\r
+  UINT8               SteppingId;               // [3:0]\r
+} EFI_CPU_VERSION_INFO; // CPUID.1.EAX\r
+\r
+typedef struct {\r
+  UINT32              L1InstructionCacheSize;\r
+  UINT32              L1DataCacheSize;\r
+  UINT32              L2CacheSize;\r
+  UINT32              L3CacheSize;\r
+  UINT32              TraceCacheSize;\r
+  UINT8               CacheDescriptor[MAX_CACHE_DESCRIPTORS];\r
+} EFI_CPU_CACHE_INFO; // CPUID.2.EAX\r
+\r
+typedef struct {\r
+  UINT8               PhysicalPackages;\r
+  UINT8               LogicalProcessorsPerPhysicalPackage;\r
+  UINT8               CoresPerPhysicalPackage;\r
+  UINT8               ThreadsPerCore;\r
+} EFI_CPU_PACKAGE_INFO; // CPUID.4.EAX\r
+\r
+typedef struct {\r
+  UINT32              RegEdx;                   // CPUID.5.EAX\r
+  UINT8               MaxCState;\r
+  UINT8               C0SubCStatesMwait;        // EDX [3:0]\r
+  UINT8               C1SubCStatesMwait;        // EDX [7:4]\r
+  UINT8               C2SubCStatesMwait;        // EDX [11:8]\r
+  UINT8               C3SubCStatesMwait;        // EDX [15:12]\r
+  UINT8               C4SubCStatesMwait;        // EDX [19:16]\r
+  UINT8               C5SubCStatesMwait;        // EDX [23:20]\r
+  UINT8               C6SubCStatesMwait;        // EDX [27:24]\r
+  UINT8               C7SubCStatesMwait;        // EDX [31:28]\r
+  UINT8               MonitorMwaitSupport;      // ECX [0]\r
+  UINT8               InterruptsBreakMwait;     // ECX [1]\r
+} EFI_CPU_CSTATE_INFO; // CPUID.5.EAX\r
+\r
+typedef struct {\r
+  UINT8               Turbo;                    // EAX [1]\r
+  UINT8               PECI;                     // EAX [0]\r
+  UINT8               NumIntThresholds;         // EBX [3:0]\r
+  UINT8               HwCoordinationFeedback;   // ECX [0]\r
+} EFI_CPU_POWER_MANAGEMENT; // CPUID.6.EAX\r
+\r
+//\r
+// IMPORTANT: Each CPU feature enabling entry is assumed a tri-state variable.\r
+//   - Keep the respective feature entry variable as default value (0x00)\r
+//     if the CPU is not capable for the feature.\r
+//   - Use the specially defined programming convention to update the variable\r
+//     to indicate capable, enable or disable.\r
+//     ie. F_CAPABLE for feature available\r
+//         F_ENABLE for feature enable\r
+//         F_DISABLE for feature disable\r
+//\r
+typedef struct {\r
+  EFI_CPUID_REGISTER  Regs;                     // CPUID.1.EAX\r
+  UINT8               Xapic;                    // ECX [21]\r
+  UINT8               SSE4_2;                   // ECX [20]\r
+  UINT8               SSE4_1;                   // ECX [19]\r
+  UINT8               Dca;                      // ECX [18]\r
+  UINT8               SupSSE3;                  // ECX [9]\r
+  UINT8               Tm2;                      // ECX [8]\r
+  UINT8               Eist;                     // ECX [7]\r
+  UINT8               Lt;                       // ECX [6]\r
+  UINT8               Vt;                       // ECX [5]\r
+  UINT8               Mwait;                    // ECX [3]\r
+  UINT8               SSE3;                     // ECX [0]\r
+  UINT8               Tcc;                      // EDX [29]\r
+  UINT8               Mt;                       // EDX [28]\r
+  UINT8               SSE2;                     // EDX [26]\r
+  UINT8               SSE;                      // EDX [25]\r
+  UINT8               MMX;                      // EDX [23]\r
+  EFI_CPUID_REGISTER  ExtRegs;                  // CPUID.80000001.EAX\r
+  UINT8               ExtLahfSahf64;            // ECX [0]\r
+  UINT8               ExtIntel64;               // EDX [29]\r
+  UINT8               ExtXd;                    // EDX [20]\r
+  UINT8               ExtSysCallRet64;          // EDX [11]\r
+  UINT16              Ht;                       // CPUID.0B.EAX EBX [15:0]\r
+} EFI_CPU_FEATURES; // CPUID.1.EAX, CPUID.0B.EAX, CPUID.80000001.EAX\r
+\r
+typedef struct {\r
+  UINT8               PhysicalBits;\r
+  UINT8               VirtualBits;\r
+} EFI_CPU_ADDRESS_BITS; // CPUID.80000008.EAX\r
+\r
+typedef struct {\r
+  UINT8               PlatformID;               // MSR 0x17 [52:50]\r
+  UINT32              MicrocodeRevision;        // MSR 0x8B [63:32]\r
+  UINT8               MaxEfficiencyRatio;       // MSR 0xCE [47:40]\r
+  UINT8               DdrRatioUnlockCap;        // MSR 0xCE [30]\r
+  UINT8               TdcTdpLimitsTurbo;        // MSR 0xCE [29]\r
+  UINT8               RatioLimitsTurbo;         // MSR 0xCE [28]\r
+  UINT8               PreProduction;            // MSR 0xCE [27]\r
+  UINT8               DcuModeSelect;            // MSR 0xCE [26]\r
+  UINT8               MaxNonTurboRatio;         // MSR 0xCE [15:8]\r
+  UINT8               Emrr;                     // MSR 0xFE [12]\r
+  UINT8               Smrr;                     // MSR 0xFE [11]\r
+  UINT8               VariableMtrrCount;        // MSR 0xFE [7:0]\r
+  UINT16              PState;                   // MSR 0x198 [15:0]\r
+  UINT8               TccActivationTemperature; // MSR 0x1A2 [23:16]\r
+  UINT8               TemperatureControlOffset; // MSR 0x1A2 [15:8]\r
+  UINT32              PCIeBar;                  // MSR 0x300 [39:20]\r
+  UINT8               PCIeBarSizeMB;            // MSR 0x300 [3:1]\r
+} EFI_MSR_FEATURES;\r
+\r
+typedef struct {\r
+  BOOLEAN                            IsIntelProcessor;\r
+  UINT8                              BrandString[MAXIMUM_CPU_BRAND_STRING_LENGTH + 1];\r
+  UINT32                             CpuidMaxInputValue;\r
+  UINT32                             CpuidMaxExtInputValue;\r
+  EFI_CPU_UARCH                      CpuUarch;\r
+  EFI_CPU_FAMILY                     CpuFamily;\r
+  EFI_CPU_PLATFORM                   CpuPlatform;\r
+  EFI_CPU_TYPE                       CpuType;\r
+  EFI_CPU_VERSION_INFO               CpuVersion;\r
+  EFI_CPU_CACHE_INFO                 CpuCache;\r
+  EFI_CPU_FEATURES                   CpuFeatures;\r
+  EFI_CPU_CSTATE_INFO                CpuCState;\r
+  EFI_CPU_PACKAGE_INFO               CpuPackage;\r
+  EFI_CPU_POWER_MANAGEMENT           CpuPowerManagement;\r
+  EFI_CPU_ADDRESS_BITS               CpuAddress;\r
+  EFI_MSR_FEATURES                   Msr;\r
+} EFI_PLATFORM_CPU_INFO;\r
+\r
+#pragma pack()\r
+\r
+#endif\r

diff --git a/Vlv2TbltDevicePkg/Include/Guid/PlatformInfo.h b/Vlv2TbltDevicePkg/Include/Guid/PlatformInfo.h
new file mode 100644 (file)
index 0000000..0a73f0d
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Include/Guid/PlatformInfo.h
@@ -0,0 +1,437 @@
+/*++\r
+\r
+  Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+\r
+\r
+Module Name:\r
+\r
+  PlatformInfo.h\r
+\r
+Abstract:\r
+\r
+  GUID used for Platform Info Data entries in the HOB list.\r
+\r
+--*/\r
+\r
+#ifndef _PLATFORM_INFO_GUID_H_\r
+#define _PLATFORM_INFO_GUID_H_\r
+\r
+#ifndef ECP_FLAG\r
+#include <PiPei.h>\r
+\r
+#include <Library/HobLib.h>\r
+#include <Library/IoLib.h>\r
+#include <Library/DebugLib.h>\r
+#include <Library/SmbusLib.h>\r
+#include <IndustryStandard/SmBus.h>\r
+#endif\r
+\r
+#define PLATFORM_INFO_REVISION = 1      // Revision id for current platform information struct.\r
+\r
+//\r
+// Start::BayLake Board Defines\r
+//\r
+#define BOARD_REVISION_DEFAULT = 0xff\r
+#define UNKNOWN_FABID          0x0F\r
+#define FAB_ID_MASK                    0x0F\r
+#define BOARD_ID_2   0x01\r
+#define BOARD_ID_1   0x40\r
+#define BOARD_ID_0   0x04\r
+\r
+#define BOARD_ID_DT_CRB     0x0\r
+#define BOARD_ID_DT_VLVR    0x1\r
+#define BOARD_ID_SVP_VLV    0xC\r
+#define BOARD_ID_SVP_EV_VLV 0xD\r
+//\r
+// End::BayLake Board Defines\r
+//\r
+\r
+//\r
+// Start::Alpine Valley Board Defines\r
+//\r
+#define DC_ID_DDR3L      0x00\r
+#define DC_ID_DDR3       0x04\r
+#define DC_ID_LPDDR3     0x02\r
+#define DC_ID_LPDDR2     0x06\r
+#define DC_ID_DDR4       0x01\r
+#define DC_ID_DDR3L_ECC  0x05\r
+#define DC_ID_NO_MEM     0x07\r
+//\r
+// End::Alpine Valley Board Defines\r
+//\r
+\r
+#define MAX_FAB_ID_RETRY_COUNT  100\r
+#define MAX_FAB_ID_CHECK_COUNT  3\r
+\r
+#define PLATFORM_INFO_HOB_REVISION     0x1\r
+\r
+#define EFI_PLATFORM_INFO_GUID \\r
+  { \\r
+    0x1e2acc41, 0xe26a, 0x483d, 0xaf, 0xc7, 0xa0, 0x56, 0xc3, 0x4e, 0x8, 0x7b \\r
+  }\r
+\r
+extern EFI_GUID gEfiPlatformInfoGuid;\r
+\r
+typedef enum {\r
+  FlavorUnknown = 0,\r
+\r
+  //\r
+  // Mobile\r
+  //\r
+  FlavorMobile = 1,\r
+\r
+  //\r
+  // Desktop\r
+  //\r
+  FlavorDesktop = 2,\r
+\r
+  //\r
+  // Tablet\r
+  //\r
+  FlavorTablet = 3\r
+} PLATFORM_FLAVOR;\r
+\r
+#pragma pack(1)\r
+\r
+typedef struct {\r
+  UINT16  PciResourceIoBase;\r
+  UINT16  PciResourceIoLimit;\r
+  UINT32  PciResourceMem32Base;\r
+  UINT32  PciResourceMem32Limit;\r
+  UINT64  PciResourceMem64Base;\r
+  UINT64  PciResourceMem64Limit;\r
+  UINT64  PciExpressBase;\r
+  UINT32  PciExpressSize;\r
+  UINT8   PciHostAddressWidth;\r
+  UINT8   PciResourceMinSecBus;\r
+} EFI_PLATFORM_PCI_DATA;\r
+\r
+typedef struct {\r
+  UINT8 CpuAddressWidth;\r
+  UINT32 CpuFamilyStepping;\r
+} EFI_PLATFORM_CPU_DATA;\r
+\r
+typedef struct {\r
+  UINT8 SysIoApicEnable;\r
+  UINT8 SysSioExist;\r
+} EFI_PLATFORM_SYS_DATA;\r
+\r
+typedef struct {\r
+  UINT32  MemTolm;\r
+  UINT32  MemMaxTolm;\r
+  UINT32  MemTsegSize;\r
+  UINT32  MemTsegBase;\r
+  UINT32  MemIedSize;\r
+  UINT32  MemIgdSize;\r
+  UINT32  MemIgdBase;\r
+  UINT32  MemIgdGttSize;\r
+  UINT32  MemIgdGttBase;\r
+  UINT64  MemMir0;\r
+  UINT64  MemMir1;\r
+  UINT32  MemConfigSize;\r
+  UINT16  MmioSize;\r
+  UINT8   DdrFreq;\r
+  UINT8   DdrType; \r
+  UINT32  MemSize;\r
+  BOOLEAN EccSupport;\r
+  UINT8   Reserved[3];\r
+  UINT16  DimmSize[2];\r
+} EFI_PLATFORM_MEM_DATA;\r
+\r
+\r
+typedef struct {\r
+  UINT32 IgdOpRegionAddress;    // IGD OpRegion Starting Address\r
+  UINT8  IgdBootType;           // IGD Boot Display Device\r
+  UINT8  IgdPanelType;          // IGD Panel Type CMOs option\r
+  UINT8  IgdTvFormat;           // IGD TV Format CMOS option\r
+  UINT8  IgdTvMinor;            // IGD TV Minor Format CMOS option\r
+  UINT8  IgdPanelScaling;       // IGD Panel Scaling\r
+  UINT8  IgdBlcConfig;          // IGD BLC Configuration\r
+  UINT8  IgdBiaConfig;          // IGD BIA Configuration\r
+  UINT8  IgdSscConfig;          // IGD SSC Configuration\r
+  UINT8  IgdDvmtMemSize;        // IGD DVMT Memory Size\r
+  UINT8  IgdFunc1Enable;        // IGD Function 1 Enable\r
+  UINT8  IgdHpllVco;            // HPLL VCO\r
+  UINT8  IgdSciSmiMode;         // GMCH SMI/SCI mode (0=SCI)\r
+  UINT8  IgdPAVP;               // IGD PAVP data\r
+} EFI_PLATFORM_IGD_DATA;\r
+\r
+typedef enum {\r
+  BOARD_ID_AV_SVP   = 0x0,    // Alpine Valley Board\r
+  BOARD_ID_BL_RVP   = 0x2,    // BayLake Board (RVP)\r
+  BOARD_ID_BL_FFRD8 = 0x3,    // FFRD8 b'0011\r
+  BOARD_ID_BL_FFRD  = 0x4,    // BayLake Board (FFRD)\r
+  BOARD_ID_BL_RVP_DDR3L  = 0x5,    // BayLake Board (RVP DDR3L)\r
+  BOARD_ID_BL_STHI  = 0x7,    // PPV- STHI Board\r
+  BOARD_ID_BB_RVP   = 0x20,   // Bayley Bay Board\r
+  BOARD_ID_BS_RVP   = 0x30,   // Bakersport Board\r
+  BOARD_ID_CVH      = 0x90,   // Crestview Hills\r
+  BOARD_ID_MINNOW2  = 0xA0    // Minnow2\r
+\r
+} BOARD_ID_LIST;\r
+\r
+typedef enum {\r
+  FAB1 = 0,\r
+  FAB2 = 1,\r
+  FAB3 = 2\r
+} FAB_ID_LIST;\r
+\r
+typedef enum {\r
+    PR0  = 0,   // FFRD PR0\r
+    PR05 = 1,   // FFRD PR0.3 and PR 0.5\r
+    PR1  = 2,   // FFRD PR1\r
+    PR11 = 3    // FFRD PR1.1\r
+} FFRD_ID_LIST;\r
+\r
+\r
+//\r
+// VLV2 GPIO GROUP OFFSET\r
+//\r
+#define GPIO_SCORE_OFFSET      0x0000\r
+#define GPIO_NCORE_OFFSET      0x1000\r
+#define GPIO_SSUS_OFFSET       0x2000\r
+\r
+//\r
+// GPIO Initialization Data Structure for BayLake.\r
+// SC = SCORE, SS= SSUS\r
+// Note: NC doesn't support GPIO functionality in IO access mode, only support in MMIO access mode.\r
+//\r
+\r
+//\r
+// IO space\r
+//\r
+typedef struct{\r
+  UINT32  Use_Sel_SC0;\r
+  UINT32  Use_Sel_SC1;\r
+  UINT32  Use_Sel_SC2;\r
+  UINT32  Use_Sel_SS;\r
+\r
+  UINT32  Io_Sel_SC0;\r
+  UINT32  Io_Sel_SC1;\r
+  UINT32  Io_Sel_SC2;\r
+  UINT32  Io_Sel_SS;\r
+\r
+  UINT32  GP_Lvl_SC0;\r
+  UINT32  GP_Lvl_SC1;\r
+  UINT32  GP_Lvl_SC2;\r
+  UINT32  GP_Lvl_SS;\r
+\r
+  UINT32  TPE_SC0;\r
+  UINT32  TPE_SS;\r
+\r
+  UINT32  TNE_SC0;\r
+  UINT32  TNE_SS;\r
+\r
+  UINT32  TS_SC0;\r
+  UINT32  TS_SS;\r
+\r
+  UINT32  WE_SS;\r
+} CFIO_INIT_STRUCT;\r
+\r
+\r
+\r
+//\r
+// CFIO PAD configuration Registers\r
+//\r
+//\r
+// Memory space\r
+//\r
+typedef union {\r
+  UINT32 dw;\r
+  struct {\r
+    UINT32 Func_Pin_Mux:3;  // 0:2 Function of CFIO selection\r
+    UINT32 ipslew:2; // 3:4 Pad (P) Slew Rate Controls PAD slew rate check Width\r
+    UINT32 inslew:2; // 5:6 Pad (N) Slew Rate Controls PAD slew rate\r
+    UINT32 Pull_assign:2; // 7:8 Pull assignment\r
+    UINT32 Pull_strength:2; // 9:10 Pull strength\r
+    UINT32 Bypass_flop:1; // 11 Bypass flop\r
+    UINT32 Filter_en:1; // 12 Filter Enable\r
+    UINT32 Hist_ctrl:2; // 13:14 hysteresis control\r
+    UINT32 Hist_enb:1; // 15 Hysteresis enable, active low\r
+    UINT32 Delay_line:6; // 16:21 Delay line values - Delay values for input or output\r
+    UINT32 Reserved:3; // 22:24 Reserved\r
+    UINT32 TPE:1; // 25 Trigger Positive Edge Enable\r
+    UINT32 TNE:1; // 26 Trigger Negative Edge Enable\r
+    UINT32 Reserved2:3; // 27:29 Reserved\r
+    UINT32 i1p5sel:1; // 30\r
+    UINT32 IODEN:1; // 31 : Open Drain enable. Active high\r
+       } r;\r
+} PAD_CONF0;\r
+\r
+typedef union{\r
+  UINT32 dw;\r
+  struct {\r
+    UINT32 instr:16; // 0:15 Pad (N) strength.\r
+    UINT32 ipstr:16; // 16:31 Pad (P) strength.\r
+  }r;\r
+} PAD_CONF1;\r
+\r
+typedef union{\r
+  UINT32 dw;\r
+  struct {\r
+    UINT32 pad_val:1; // 0 These registers are implemented as dual read/write with dedicated storage each.\r
+    UINT32 ioutenb:1; // 1 output enable\r
+    UINT32 iinenb:1; // 2 input enable\r
+    UINT32 Reserved:29; // 3:31 Reserved\r
+  }r;\r
+} PAD_VAL;\r
+\r
+typedef union{\r
+  UINT32 GPI;\r
+  struct {\r
+    UINT32 ihbpen:1; // 0 Pad high by pass enable\r
+    UINT32 ihbpinen:1; // 1 Pad high by pass input\r
+    UINT32 instaticen:1; // 2 TBD\r
+    UINT32 ipstaticen:1; // 3 TBD\r
+    UINT32 Overide_strap_pin :1; // 4 DFX indicates if it wants to override the strap pin value on this pad, if exists.\r
+    UINT32 Overide_strap_pin_val:1; // 5 In case DFX need to override strap pin value and it exist for the specific pad, this value will be used.\r
+    UINT32 TestMode_Pin_Mux:3; // 6:9 DFX Pin Muxing\r
+  }r;\r
+} PAD_DFT;\r
+\r
+//\r
+// GPIO_USAGE value need to matche the PAD_VAL input/output enable bits.\r
+//\r
+typedef enum {\r
+  Native = 0xFF,  // Native, no need to set PAD_VALUE\r
+  GPI = 2,    // GPI, input only in PAD_VALUE\r
+  GPO = 4,    // GPO, output only in PAD_VALUE\r
+  GPIO = 0,      // GPIO, input & output\r
+  TRISTS = 6,      // Tri-State\r
+  GPIO_NONE\r
+} GPIO_USAGE;\r
+\r
+typedef enum {\r
+  LO = 0,\r
+  HI = 1,\r
+  NA = 0xFF\r
+} GPO_D4;\r
+\r
+typedef enum {\r
+  F0 = 0,\r
+  F1 = 1,\r
+  F2 = 2,\r
+  F3 = 3,\r
+  F4 = 4,\r
+  F5 = 5,\r
+  F6 = 6,\r
+  F7 = 7\r
+} GPIO_FUNC_NUM;\r
+\r
+//\r
+// Mapping to CONF0 bit 27:24\r
+// Note: Assume "Direct Irq En" is not set, unless specially notified.\r
+//\r
+typedef enum {\r
+  TRIG_ = 0,\r
+  TRIG_Edge_High = /*BIT3 |*/ BIT1,    // Positive Edge (Rasing)\r
+  TRIG_Edge_Low  = /*BIT3 |*/ BIT2,    // Negative Edge (Falling)\r
+  TRIG_Edge_Both = /*BIT3 |*/ BIT2 | BIT1,     // Both Edge\r
+  TRIG_Level_High= /*BIT3 |*/ BIT1 | BIT0,     // Level High\r
+  TRIG_Level_Low = /*BIT3 |*/ BIT2 | BIT0,     // Level Low\r
+} INT_TYPE;\r
+\r
+typedef enum {\r
+  P_20K_H,     // Pull Up 20K\r
+  P_20K_L,     // Pull Down 20K\r
+  P_10K_H,     // Pull Up 10K\r
+  P_10K_L,     // Pull Down 10K\r
+  P_2K_H,      // Pull Up 2K\r
+  P_2K_L,      // Pull Down 2K\r
+  P_NONE      // Pull None\r
+} PULL_TYPE;\r
+\r
+#ifdef EFI_DEBUG\r
+  #define GPIO_INIT_ITEM(pad_name, usage, gpod4, func, int_cap, int_type, pull, offset) {pad_name, usage, gpod4, func, /*int_cap,*/ TRIG_##int_type, P_##pull, offset}\r
+#else\r
+  #define GPIO_INIT_ITEM(pad_name, usage, gpod4, func, int_cap, int_type, pull, offset) {          usage, gpod4, func, /*int_cap,*/ TRIG_##int_type, P_##pull, offset}\r
+#endif\r
+\r
+//\r
+// GPIO CONF & PAD Initialization Data Structure for BayLake GPIOs bits.\r
+// NC = NCORE, SC = SCORE, SS= SSUS\r
+//\r
+typedef struct {\r
+\r
+#ifdef EFI_DEBUG\r
+  char         pad_name[32];// GPIO Pin Name for debug purpose\r
+#endif\r
+\r
+  GPIO_USAGE     usage;     // GPIO pin used as Native mode or GPI/GPO/GPIO mode\r
+  GPO_D4         gpod4;     // GPO default value\r
+  GPIO_FUNC_NUM  func;      // Function Number (F0~F7)\r
+  INT_TYPE       int_type;  // Edge or Level trigger, low or high active\r
+  PULL_TYPE      pull;      // Pull Up or Down\r
+  UINT8          offset;    // Equal with (PCONF0 register offset >> 4 bits)\r
+} GPIO_CONF_PAD_INIT;\r
+\r
+//\r
+//typedef UINT64 BOARD_FEATURES\r
+//\r
+typedef struct _EFI_PLATFORM_INFO_HOB {\r
+  UINT16                      PlatformType; // Platform Type\r
+  UINT8                       BoardId;             // Board ID\r
+  UINT8                       BoardRev;            // Board Revision\r
+  PLATFORM_FLAVOR             PlatformFlavor;      // Platform Flavor\r
+  UINT8                       DDRDaughterCardCh0Id;// DDR daughter card channel 0 id\r
+  UINT8                       DDRDaughterCardCh1Id;// DDR daughter card channel 1 id\r
+  UINT8                       ECOId;               // ECO applied on platform\r
+  UINT16                      IohSku;\r
+  UINT8                       IohRevision;\r
+  UINT16                      IchSku;\r
+  UINT8                       IchRevision;\r
+  EFI_PLATFORM_PCI_DATA       PciData;\r
+  EFI_PLATFORM_CPU_DATA       CpuData;\r
+  EFI_PLATFORM_MEM_DATA       MemData;\r
+  EFI_PLATFORM_SYS_DATA       SysData;\r
+  EFI_PLATFORM_IGD_DATA       IgdData;\r
+  UINT8                       RevisonId;           // Structure Revision ID\r
+  EFI_PHYSICAL_ADDRESS        PlatformCfioData;\r
+  EFI_PHYSICAL_ADDRESS        PlatformGpioData_NC;\r
+  EFI_PHYSICAL_ADDRESS        PlatformGpioData_SC;\r
+  EFI_PHYSICAL_ADDRESS        PlatformGpioData_SUS;\r
+  EFI_PHYSICAL_ADDRESS        PlatformGpioData_NC_TRI;\r
+  EFI_PHYSICAL_ADDRESS        PlatformGpioData_SC_TRI;\r
+  EFI_PHYSICAL_ADDRESS        PlatformGpioData_SUS_TRI;\r
+  EFI_PHYSICAL_ADDRESS        PlatformGpioData_SUS_PR1;\r
+  EFI_PHYSICAL_ADDRESS        PlatformGpioData_SC_PR1_1;\r
+  EFI_PHYSICAL_ADDRESS        PlatformGpioData_SUS_PR1_1;\r
+\r
+  UINT8                       CfioEnabled;\r
+  UINT32                      SsidSvid;\r
+  UINT16                      AudioSubsystemDeviceId;\r
+  UINT64                      AcpiOemId;\r
+  UINT64                      AcpiOemTableId;\r
+  UINT16                      MemCfgID;\r
+} EFI_PLATFORM_INFO_HOB;\r
+\r
+#pragma pack()\r
+\r
+EFI_STATUS\r
+GetPlatformInfoHob (\r
+  IN CONST EFI_PEI_SERVICES           **PeiServices,\r
+  OUT EFI_PLATFORM_INFO_HOB           **PlatformInfoHob\r
+  );\r
+\r
+\r
+EFI_STATUS\r
+InstallPlatformClocksNotify (\r
+  IN CONST EFI_PEI_SERVICES           **PeiServices\r
+  );\r
+\r
+EFI_STATUS\r
+InstallPlatformSysCtrlGPIONotify (\r
+  IN CONST EFI_PEI_SERVICES           **PeiServices\r
+  );\r
+\r
+#endif\r

diff --git a/Vlv2TbltDevicePkg/Include/Guid/SensorInfoVariable.h b/Vlv2TbltDevicePkg/Include/Guid/SensorInfoVariable.h
new file mode 100644 (file)
index 0000000..b058e3c
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Include/Guid/SensorInfoVariable.h
@@ -0,0 +1,284 @@
+/*++\r
+\r
+  Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+\r
+\r
+Module Name:\r
+\r
+  SensorInfoVariable.h\r
+\r
+Abstract:\r
+\r
+  GUID used for Sensor Info variable.\r
+\r
+--*/\r
+\r
+\r
+//\r
+//  Module:         SensorInfoVariable.h\r
+//\r
+//  Description:    Provides  structure  and  literal  definitions for the\r
+//                  Sensor Information Variable.  The  BIOS  will  provide\r
+//                  this  variable  to  runtime  applications  via the EFI\r
+//                  GetVariable function.\r
+//\r
+//  Notes:      1.  When defining and initializing the variable within the\r
+//                  BIOS, the module will define the structure  using  the\r
+//                  typedef  macros  in  a block. For an ATX board using a\r
+//                  single Heceta 6P, which has 4 temperature  sensors,  6\r
+//                  voltage  sensors,  4 fan speed sensors and 3 fan speed\r
+//                  controllers, this block would be declared as follows:\r
+//\r
+//                      TYPEDEF_TEMP_SENSOR_SECTION(4);\r
+//                      TYPEDEF_VOLT_SENSOR_SECTION(6);\r
+//                      TYPEDEF_FAN_SENSOR_SECTION(4);\r
+//                      TYPEDEF_FAN_CONTROLLER_SENSOR(3);\r
+//                      TYPEDEF_SENSOR_INFO_VAR;\r
+//\r
+//              2.  When crafting code to access the variable, the  module\r
+//                  will  also  need  to  invoke  the  typedef macros in a\r
+//                  block but, since it cannot declare a structure for the\r
+//                overall variable (because array lengths will vary), it\r
+//                cannot  use  TYPEDEF_SENSOR_INFO_VAR.  The  block will\r
+//                typically be used as follows:\r
+//\r
+//                      TYPEDEF_TEMP_SENSOR_SECTION(1);\r
+//                     TYPEDEF_VOLT_SENSOR_SECTION(1);\r
+//                     TYPEDEF_FAN_SENSOR_SECTION(1);\r
+//                     TYPEDEF_FAN_CONTROLLER_SENSOR(1);\r
+//\r
+//                 The structure buffer should instead be declared  as  a\r
+//                 BYTE  array. Pointers to the various sections can then\r
+//                  be built using the XXXX_SECTION_LEN macros...\r
+//\r
+\r
+\r
+#ifndef _SENSOR_INFO_VAR_GUID_H_\r
+#define _SENSOR_INFO_VAR_GUID_H_\r
+\r
+#define SENSOR_INFO_VAR_GUID \\r
+  { \\r
+    0xE59E7B4D, 0x06DC, 0x44AB, 0xB3, 0x6D, 0x5E, 0xD7, 0x78, 0x9C, 0x53, 0x0A \\r
+  }\r
+\r
+extern EFI_GUID gEfiSensorInfoVarGuid;\r
+extern CHAR16   gEfiSensorInfoVarName[];\r
+extern CHAR16   gEfiSensorInfoVarNameWithPassword[];\r
+\r
+#define SENSOR_INFO_VAR_NAME L"SensorInfoVar"\r
+#define SENSOR_INFO_VAR_NAME_WITH_PASSWORD SENSOR_INFO_VAR_NAME L"S4k?A^7!"\r
+\r
+//\r
+// Sensor/Controller usage definitions\r
+//\r
+\r
+#define UNKNOWN_OTHER                   0\r
+\r
+//\r
+// Temperature Sensors\r
+//\r
+#define CPU_CORE_TEMPERATURE            1\r
+#define CPU_DIE_TEMPERATURE             2\r
+#define ICH_TEMPERATURE                 3\r
+#define MCH_TEMPERATURE                 4\r
+#define VR_TEMPERATURE                  5\r
+#define MEMORY_TEMPERATURE              6\r
+#define MOTHERBOARD_AMBIENT_TEMPERATURE 7\r
+#define SYSTEM_AMBIENT_AIR_TEMPERATURE  8\r
+#define CPU_INLET_AIR_TEMPERATURE       9\r
+#define SYSTEM_INLET_AIR_TEMPERATURE    10\r
+#define SYSTEM_OUTLET_AIR_TEMPERATURE   11\r
+#define PSU_HOTSPOT_TEMPERATURE         12\r
+#define PSU_INLET_AIR_TEMPERATURE       13\r
+#define PSU_OUTLET_AIR_TEMPERATURE      14\r
+#define DRIVE_TEMPERATURE               15\r
+#define GPU_TEMPERATURE                 16\r
+#define IOH_TEMPERATURE                 17\r
+\r
+#define LAST_TEMPERATURE                17\r
+\r
+//\r
+// Voltage Sensors\r
+//\r
+#define PLUS_12_VOLTS                   1\r
+#define NEG_12_VOLTS                    2\r
+#define PLUS_5_VOLTS                    3\r
+#define PLUS_5_VOLT_BACKUP              4\r
+#define NEG_5_VOLTS                     5\r
+#define PLUS_3P3_VOLTS                  6\r
+#define PLUS_2P5_VOLTS                  7\r
+#define PLUS_1P5_VOLTS                  8\r
+#define CPU_1_VCCP_VOLTAGE              9\r
+#define CPU_2_VCCP_VOLTAGE              10\r
+#define CPU_3_VCCP_VOLTAGE              11\r
+#define CPU_4_VCCP_VOLTAGE              12\r
+#define PSU_INPUT_VOLTAGE               13\r
+#define MCH_VCC_VOLTAGE                 14\r
+#define PLUS_3P3_VOLT_STANDBY           15\r
+#define CPU_VTT_VOLTAGE                 16\r
+#define PLUS_1P8_VOLTS                  17\r
+\r
+#define LAST_VOLTAGE                    17\r
+\r
+//\r
+// Fan Speed Sensors and Controllers.\r
+//\r
+#define CPU_COOLING_FAN                 1\r
+#define SYSTEM_COOLING_FAN              2\r
+#define MCH_COOLING_FAN                 3\r
+#define VR_COOLING_FAN                  4\r
+#define CHASSIS_COOLING_FAN             5\r
+#define CHASSIS_INLET_FAN               6\r
+#define CHASSIS_OUTLET_FAN              7\r
+#define PSU_COOLING_FAN                 8\r
+#define PSU_INLET_FAN                   9\r
+#define PSU_OUTLET_FAN                  10\r
+#define DRIVE_COOLING_FAN               11\r
+#define GPU_COOLING_FAN                 12\r
+#define AUX_COOLING_FAN                 13\r
+#define IOH_COOLING_FAN                 14\r
+\r
+#define LAST_FAN                        14\r
+\r
+//\r
+// Fan Type Definitions\r
+//\r
+#define FAN_TYPE_UNKNOWN                0\r
+#define FAN_3WIRE_PULSE                 1\r
+#define FAN_3WIRE_VOLTAGE               2\r
+#define FAN_4WIRE                       3\r
+\r
+#pragma pack(1)\r
+\r
+//\r
+// TEMP_SENSOR_INFO - Structure providing info for a temperature sensor.\r
+//\r
+typedef struct _TEMP_SENSOR_INFO\r
+{\r
+    UINT8                               byDevice;       // Device index\r
+    UINT8                               byIndex;        // Physical sensor index\r
+    UINT8                               byUsage;        // Usage indicator\r
+    UINT8                               bRelative;      // Relative vs. Absolute readings\r
+\r
+} TEMP_SENSOR_INFO, *P_TEMP_SENSOR_INFO;\r
+\r
+//\r
+// TYPEDEF_TEMP_SENSOR_SECTION - Macro that can be used to typedef the\r
+// TEMP_SENSOR_SECTION structure, which provides information about all\r
+// temperature sensors.\r
+//\r
+#define TYPEDEF_TEMP_SENSOR_SECTION(count)                              \\r
+typedef struct _TEMP_SENSOR_SECTION                                     \\r
+{                                                                       \\r
+    UINT8                               byCount;                        \\r
+    TEMP_SENSOR_INFO                    stSensor[count];                \\r
+                                                                        \\r
+} TEMP_SENSOR_SECTION, *P_TEMP_SENSOR_SECTION\r
+\r
+//\r
+// VOLT_SENSOR_INFO - Structure providing info for a voltage sensor.\r
+//\r
+typedef struct _VOLT_SENSOR_INFO\r
+{\r
+    UINT8                               byDevice;       // Device index\r
+    UINT8                               byIndex;        // Physical sensor index\r
+    UINT8                               byUsage;        // Usage indicator\r
+\r
+} VOLT_SENSOR_INFO, *P_VOLT_SENSOR_INFO;\r
+\r
+//\r
+// TYPEDEF_VOLT_SENSOR_SECTION - Macro that can be used to typedef the\r
+// VOLT_SENSOR_SECTION structure, which provides information about all\r
+// voltage sensors.\r
+//\r
+#define TYPEDEF_VOLT_SENSOR_SECTION(count)                              \\r
+typedef struct _VOLT_SENSOR_SECTION                                     \\r
+{                                                                       \\r
+    UINT8                               byCount;                        \\r
+    VOLT_SENSOR_INFO                    stSensor[count];                \\r
+                                                                        \\r
+} VOLT_SENSOR_SECTION, *P_VOLT_SENSOR_SECTION\r
+\r
+//\r
+// FAN_SENSOR_INFO - Structure providing info for a fan speed sensor.\r
+//\r
+typedef struct _FAN_SENSOR_INFO\r
+{\r
+    UINT8                               byDevice;       // Device index\r
+    UINT8                               byIndex;        // Physical sensor index\r
+    UINT8                               byUsage;        // Usage indicator\r
+    UINT8                               byType;         // Fan type\r
+    UINT8                               byController;   // Associated Fan Controller\r
+\r
+} FAN_SENSOR_INFO, *P_FAN_SENSOR_INFO;\r
+\r
+//\r
+// TYPEDEF_FAN_SENSOR_SECTION - Macro that can be used to typedef the\r
+// FAN_SENSOR_SECTION structure, which provides information about all fan\r
+// speed sensors.\r
+//\r
+#define TYPEDEF_FAN_SENSOR_SECTION(count)                               \\r
+typedef struct _FAN_SENSOR_SECTION                                      \\r
+{                                                                       \\r
+    UINT8                               byCount;                        \\r
+    FAN_SENSOR_INFO                     stSensor[count];                \\r
+                                                                        \\r
+} FAN_SENSOR_SECTION, *P_FAN_SENSOR_SECTION\r
+\r
+//\r
+// FAN_CONTROLLER_INFO - Structure providing info for a fan speed controller.\r
+//\r
+#define MAX_ASSOC_FANS                  4\r
+#define ASSOC_UNUSED                    0xFF\r
+\r
+typedef struct _FAN_CONTROLLER_INFO\r
+{\r
+    UINT8                               byDevice;       // Device index\r
+    UINT8                               byIndex;        // Physical Controller Index\r
+    UINT8                               byUsage;        // Usage Indicator\r
+    UINT8                               byFan[MAX_ASSOC_FANS]; // Associated Fan Sensors\r
+\r
+} FAN_CONTROLLER_INFO, *P_FAN_CONTROLLER_INFO;\r
+\r
+//\r
+// TYPEDEF_FAN_CONTROLLER_SECTION - Macro that can be used to typedef the\r
+// FAN_CONTROLLER_SECTION structure, which provides information about all\r
+// fan speed controllers.\r
+//\r
+#define TYPEDEF_FAN_CONTROLLER_SECTION(count)                           \\r
+typedef struct _FAN_CONTROLLER_SECTION                                  \\r
+{                                                                       \\r
+    UINT8                               byCount;                        \\r
+    FAN_CONTROLLER_INFO                 stController[count];            \\r
+                                                                        \\r
+} FAN_CONTROLLER_SECTION, *P_FAN_CONTROLLER_SECTION\r
+\r
+//\r
+// TYPEDEF_SENSOR_INFO_VAR - Macro that can be used to typedef the\r
+// SENSOR_INFO_VAR structure, which provides information about all sensors\r
+// and fan speed controllers. The other TYPEDEF macros must be invoked\r
+// before using this one...\r
+//\r
+#define TYPEDEF_SENSOR_INFO_VAR                                         \\r
+typedef struct _SENSOR_INFO_VAR                                         \\r
+{                                                                       \\r
+    TEMP_SENSOR_SECTION                 stTemps;                        \\r
+    VOLT_SENSOR_SECTION                 stVolts;                        \\r
+    FAN_SENSOR_SECTION                  stFans;                         \\r
+    FAN_CONTROLLER_SECTION              stCtrls;                        \\r
+                                                                        \\r
+} SENSOR_INFO_VAR, *P_SENSOR_INFO_VAR\r
+\r
+#pragma pack()\r
+\r
+#endif\r

diff --git a/Vlv2TbltDevicePkg/Include/Guid/SetupVariable.h b/Vlv2TbltDevicePkg/Include/Guid/SetupVariable.h
new file mode 100644 (file)
index 0000000..eb0a176
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Include/Guid/SetupVariable.h
@@ -0,0 +1,1351 @@
+/*++
+
+  Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>
+                                                                                   
+
+  This program and the accompanying materials are licensed and made available under
+
+  the terms and conditions of the BSD License that accompanies this distribution.  
+
+  The full text of the license may be found at                                     
+
+  http://opensource.org/licenses/bsd-license.php.                                  
+
+                                                                                   
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            
+
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    
+                                                                                   
+
+
+
+Module Name:
+
+    SetupVariable.h
+
+Abstract:
+
+    Driver configuration include file
+
+ 
+--*/
+
+#ifndef _SETUP_VARIABLE_H
+#define _SETUP_VARIABLE_H
+
+//
+// ---------------------------------------------------------------------------
+//
+// Driver Configuration
+//
+// ---------------------------------------------------------------------------
+//
+
+//
+// {EC87D643-EBA4-4bb5-A1E5-3F3E36B20DA9}
+//
+#define SYSTEM_CONFIGURATION_GUID\
+  { \
+    0xec87d643, 0xeba4, 0x4bb5, 0xa1, 0xe5, 0x3f, 0x3e, 0x36, 0xb2, 0xd, 0xa9 \
+  }
+
+#define ROOT_SECURITY_GUID\
+  { \
+    0xd387d688, 0xeba4, 0x45b5, 0xa1, 0xe5, 0x3f, 0x3e, 0x36, 0xb2, 0xd, 0x37 \
+  }
+
+//
+// {6936B3BD-4350-46d9-8940-1FA20961AEB1}
+//
+#define SYSTEM_ROOT_MAIN_GUID\
+  { \
+     0x6936b3bd, 0x4350, 0x46d9, 0x89, 0x40, 0x1f, 0xa2, 0x9, 0x61, 0xae, 0xb1 \
+  }
+
+//  
+// {21FEE8DB-0D29-477e-B5A9-96EB343BA99C}
+//
+#define ADDITIONAL_SYSTEM_INFO_GUID\
+  { \
+     0x21fee8db, 0xd29, 0x477e, 0xb5, 0xa9, 0x96, 0xeb, 0x34, 0x3b, 0xa9, 0x9c \
+  }
+
+#define SETUP_GUID { 0xEC87D643, 0xEBA4, 0x4BB5, 0xA1, 0xE5, 0x3F, 0x3E, 0x36, 0xB2, 0x0D, 0xA9 }
+
+// {1B838190-4625-4ead-ABC9-CD5E6AF18FE0}
+#define EFI_HII_EXPORT_DATABASE_GUID { 0x1b838190, 0x4625, 0x4ead, 0xab, 0xc9, 0xcd, 0x5e, 0x6a, 0xf1, 0x8f, 0xe0 }
+
+#define PASSWORD_MAX_SIZE               20
+
+#define MAX_CUSTOM_VID_TABLE_STATES 6
+//
+// Overclocking Source Defines
+//
+#define OVERCLOCK_SOURCE_BIOS       0
+#define OVERCLOCK_SOURCE_OS         1
+
+#define PCH_PCIE_MAX_ROOT_PORTS     4
+
+#pragma pack(1)
+
+// NOTE: When you add anything to this structure, 
+//   you MUST add it to the very bottom!!!!
+//   You must make sure the structure size is able to divide by 32!
+typedef struct {
+
+  //
+  // Floppy
+  //
+  UINT8         Floppy;
+  UINT8         FloppyLockHide;
+
+  UINT8         FloppyWriteProtect;
+  UINT8         FloppyWriteProtectLockHide;
+
+  //
+  // System ports
+  //
+  UINT8         Serial;
+  UINT8         SerialLockHide;
+
+  UINT8         Serial2;
+  UINT8         Serial2LockHide;
+
+  UINT8         Parallel;
+  UINT8         ParallelLockHide;
+
+  UINT8         ParallelMode;
+  UINT8         ParallelModeLockHide;  
+
+  UINT8         AllUsb;
+  UINT8         UsbPortsLockHide;
+
+  UINT8         Usb2;
+  UINT8         Usb2LockHide;
+
+  UINT8         UsbLegacy;
+  UINT8         UsbLegacyLockHide;
+
+  UINT8         Audio;
+  UINT8         AudioLockHide;
+
+  UINT8         Lan;
+  UINT8         LanLockHide;
+
+  //
+  // Keyboard
+  //
+  UINT8         Numlock;
+  UINT8         NumlockLockHide;
+
+  //
+  // ECIR
+  //
+  UINT8         ECIR;
+  UINT8         ECIRLockHide;
+
+  //
+  // Power State
+  //
+  UINT8         PowerState;
+  UINT8         PowerStateLockHide;
+
+  //
+  // Wake on RTC variables
+  //
+  UINT8         WakeOnRtcS5;
+  UINT8         WakeOnRtcS5LockHide;
+  UINT8         RTCWakeupDate;
+  UINT8         RTCWakeupDateLockHide;
+  UINT8         RTCWakeupTimeHour;
+  UINT8         RTCWakeupHourLockHide;
+  UINT8         RTCWakeupTimeMinute;
+  UINT8         RTCWakeupMinuteLockHide;
+  UINT8         RTCWakeupTimeSecond;
+  UINT8         RTCWakeupSecondLockHide;
+
+  //
+  // Wake On Lan
+  //
+  UINT8         WakeOnLanS5;
+  UINT8         WakeOnLanS5LockHide;
+
+  //Spread spectrum
+  UINT8         SpreadSpectrum;
+
+  //
+  // Boot Order
+  //
+  UINT8         BootOrder[8];
+  UINT8         BootOrderLockHide;
+
+  //
+  // Hard Drive Boot Order
+  //
+  UINT8         HardDriveBootOrder[8];
+  UINT8         HardDriveBootOrderLockHide;  
+
+  //
+  // CD Drive Boot Order
+  //
+  UINT8         CdDriveBootOrder[4];
+  UINT8         CdDriveBootOrderLockHide;  
+
+  //
+  // FDD Drive Boot Order
+  //
+  UINT8         FddDriveBootOrder[4];
+  UINT8         FddDriveBootOrderLockHide;  
+
+  //
+  // Drive Boot Order
+  //
+  UINT8         DriveBootOrder[16];
+  UINT8         DriveBootOrderLockHide;  
+
+  //
+  // Boot Menu Type
+  //
+  UINT8         BootMenuType;
+  UINT8         BootMenuTypeLockHide;  
+
+  //
+  // Boot from Removable Devices
+  //
+  UINT8         BootFloppy;
+  UINT8         BootFloppyLockHide;
+
+  //
+  // Boot from Optical Devices
+  //
+  UINT8         BootCd;
+  UINT8         BootCdLockHide;
+
+  //
+  // Boot from Network
+  //
+  UINT8         BootNetwork;
+  UINT8         BootNetworkLockHide;
+
+  //
+  // Boot USB
+  //
+  UINT8         BootUsb;
+  UINT8         BootUsbLockHide;
+
+  //
+  // USB Zip Emulation Type
+  //
+  UINT8         UsbZipEmulation;
+  UINT8         UsbZipEmulationLockHide;
+
+  //
+  // USB Devices Boot First in Boot Order
+  //
+  UINT8         UsbDevicesBootFirst;
+  UINT8         UsbDevicesBootFirstLockHide;
+
+  //
+  // USB Boot Device SETUP Emulation
+  //
+  UINT8         UsbSetupDeviceEmulation;
+  UINT8         UsbSetupDeviceEmulationLockHide;
+
+  //
+  // BIOS INT13 Emulation for USB Mass Devices
+  //
+  UINT8         UsbBIOSINT13DeviceEmulation;
+  UINT8         UsbBIOSINT13DeviceEmulationLockHide;
+
+  //
+  // BIOS INT13 Emulation Size for USB Mass Devices
+  //
+  UINT16        UsbBIOSINT13DeviceEmulationSize;
+  UINT8         UsbBIOSINT13DeviceEmulationSizeLockHide;
+
+  //
+  // Dummy place holder to prevent VFR compiler problem.
+  //
+  UINT16        DummyDataForVfrBug;  // Don't change or use.
+
+  //
+  // Language Select
+  //
+  UINT8         LanguageSelect;
+
+  //
+  // SATA Type (Ide, Ahci, Raid)
+  //
+  UINT8         SataType;
+  UINT8         SataTypeLockHide;
+  UINT8         SataTestMode;
+
+  //
+  // Fixed Disk Boot Sector (Fdbs)
+  //
+  UINT8         Fdbs;
+  UINT8         FdbsLockHide;
+
+  //
+  // DisplaySetupPrompt
+  //
+  UINT8         DisplaySetupPrompt;
+  UINT8         DisplaySetupPromptLockHide;
+
+  //
+  // ASF
+  //
+  UINT8         Asf;
+  UINT8         AsfLockHide;
+
+  //
+  // Event Logging
+  //
+  UINT8         EventLogging;
+  UINT8         EventLoggingLockHide;
+
+  //
+  // Clear Event Log
+  //
+  UINT8         ClearEvents;
+  UINT8         ClearEventsLockHide;
+
+  //
+  // Expansion Card Text
+  //
+  UINT8         ExpansionCardText;
+  UINT8         ExpansionCardTextLockHide;
+
+  //
+  // Video Adaptor
+  //
+  UINT8         PrimaryVideoAdaptor;
+  UINT8         PrimaryVideoAdaptorLockHide;
+
+  //
+  // Chassis intrusion
+  //
+  UINT8         IntruderDetection;
+  UINT8         IntruderDetectionLockHide;
+
+  //
+  // User Access Level
+  //
+  UINT8         UserPasswordLevel;
+  UINT8         UserPasswordLevelLockHide;
+
+  //
+  // Maximum FSB Automatic/Disable
+  //
+  UINT8         MaxFsb;
+  UINT8         MaxFsbLockHide;
+
+  //
+  // Hard Disk Pre-delay
+  //
+  UINT8         HddPredelay;
+  UINT8         HddPredelayLockHide;
+
+  //
+  // S.M.A.R.T. Mode
+  //
+  UINT8         SmartMode;
+  UINT8         SmartModeLockHide;
+
+  //
+  // ACPI Suspend State
+  //
+  UINT8         AcpiSuspendState;
+  UINT8         AcpiSuspendStateLockHide;  
+
+  //
+  // PCI Latency Timer
+  //
+  UINT8         PciLatency;
+  UINT8         PciLatencyLockHide;  
+
+  //
+  // Fan Control
+  //
+  UINT8         FanControl;
+  UINT8         FanControlLockHide;  
+
+  //
+  // CPU Fan Control
+  //
+  UINT8         CpuFanControl;
+  UINT8         CpuFanControlLockHide;  
+
+  //
+  // Lowest Fan Speed
+  //
+  UINT8         LowestFanSpeed;
+  UINT8         LowestFanSpeedLockHide;  
+
+  //
+  // Processor (CPU)
+  //
+  UINT8         CpuFlavor;
+
+  UINT8         CpuidMaxValue;
+  UINT8         CpuidMaxValueLockHide;
+  
+  UINT8         ExecuteDisableBit;
+  UINT8         ExecuteDisableBitLockHide;  
+
+  //
+  // EIST or GV3 setup option
+  //
+  UINT8         ProcessorEistEnable;            
+  UINT8         ProcessorEistEnableLockHide;
+
+  //
+  // C1E Enable
+  //
+  UINT8         ProcessorC1eEnable;
+  UINT8         ProcessorC1eEnableLockHide;  
+
+  //
+  // Enabling CPU C-States of processor
+  //
+  UINT8         ProcessorCcxEnable;               
+  UINT8         ProcessorCcxEnableLockHide;
+  
+  //
+  // Package C-State Limit
+  //
+  UINT8         PackageCState;
+  UINT8         PackageCStateLockHide;
+  
+  //
+  // Enable/Disable NHM C3(ACPI C2) report to OS
+  //
+  UINT8         OSC2Report;
+  UINT8         OSC2ReportLockHide;
+  
+  //
+  // Enable/Disable NHM C6(ACPI C3) report to OS
+  //
+  UINT8         C6Enable;
+  UINT8         C6EnableLockHide;
+  
+  //
+  // Enable/Disable NHM C7(ACPI C3) report to OS
+  //
+  UINT8         C7Enable;
+  UINT8         C7EnableLockHide;
+
+  //
+  // EIST/PSD Function select option
+  //
+  UINT8         ProcessorEistPsdFunc;
+  UINT8         ProcessorEistPsdFuncLockHide;
+
+  //
+  // 
+  //
+  UINT8         CPU00;
+  UINT8         CPU01;
+
+  //
+  // 
+  //
+  UINT8         CPU02;
+  UINT8         CPU03;
+  
+  //
+  // 
+  //
+  UINT8         CPU04;
+  UINT8         CPU05;
+
+  //
+  // 
+  //
+  UINT8         CPU06;
+  UINT8         CPU07;
+
+  //
+  // 
+  //
+  UINT8         CPU08;
+  UINT8         CPU09;
+
+  //
+  // 
+  //
+  UINT8         CPU10;
+  UINT8         CPU11;  
+
+  //
+  // 
+  //
+  UINT8         CPU12;
+  UINT8         CPU13;
+  
+  //
+  // 
+  //
+  UINT8         CPU14;
+  UINT8         CPU15;
+  
+  //
+  // 
+  //
+  UINT8         CPU16;
+  UINT8         CPU17;
+  
+  //
+  // 
+  //
+  UINT8         CPU18;
+  UINT8         CPU19;  
+  
+  //
+  // 
+  //
+  UINT8         CPU20;
+  UINT8         CPU21;
+  
+  //
+  // 
+  //
+  UINT8         CPU22;
+  UINT8         CPU23;
+  
+  //
+  // 
+  //
+  UINT8         CPU24;
+  UINT8         CPU25;
+  
+  //
+  // 
+  //
+  UINT8         CPU26;
+  UINT8         CPU27;
+
+  //
+  // 
+  //
+  UINT8         CPU28;
+  UINT8         CPU29;
+
+  //
+  // 
+  //
+  UINT8         CPU30;
+  UINT8         CPU31;
+
+  //
+  // 
+  //
+  UINT8         CPU32;
+  UINT8         CPU33;
+  
+  //
+  // 
+  //
+  UINT8         CPU34;
+  UINT8         CPU35;
+  
+  //
+  // 
+  //
+  UINT8         CPU36;
+  UINT8         CPU37;
+  
+  //
+  // 
+  //
+  UINT8         CPU38;
+  UINT8         CPU39;
+  
+  //
+  // 
+  //
+  UINT16        CPU40;
+  UINT8         CPU41;  
+  
+  //
+  // 
+  //
+  UINT8         CPU42;
+  UINT8         CPU43;
+  
+  //
+  // 
+  //
+  UINT16        CPU44;
+  UINT8         CPU45;  
+  
+  //
+  // 
+  //
+  UINT8         CPU46;
+  UINT8         CPU47;
+  
+  //
+  // 
+  //
+  UINT8         CPU48;
+  UINT8         CPU49;
+
+  //
+  // 
+  // 
+  UINT8         CPU50;
+  UINT8         CPU51;
+
+  //
+  // 
+  //
+  UINT8         CPU52;
+  UINT8         CPU53;
+    
+  //
+  // 
+  //
+  UINT8         CPU54;
+  UINT8         CPU55;
+
+  //
+  // 
+  //
+  UINT8         CPU56;
+  UINT8         CPU57;
+
+  //
+  // 
+  //
+  UINT8         CPU58;
+  UINT8         CPU59;
+
+  //
+  // 
+  //
+  UINT8         CPU60;
+  UINT8         CPU61;
+
+  //
+  // 
+  //
+  UINT8         CPU62;
+  UINT8         CPU63;
+
+  //
+  // 
+  //  
+  UINT8         CPU64;
+  UINT8         CPU65;
+
+  //
+  // 
+  //
+  UINT8         CPU66;
+  UINT8         CPU67;
+
+  //
+  // 
+  //
+  UINT16        CPU68;
+  UINT8         CPU69;
+
+  //
+  // 
+  //
+  UINT16        CPU70;
+
+  //
+  // 
+  //
+  UINT8         CPU71;
+
+  //
+  // 
+  //
+  UINT8         MEM00;
+  UINT8         MEM01;
+
+  //
+  // 
+  //
+  UINT8         MEM02;
+  UINT8         MEM03;
+
+  UINT16        MEM04;
+  UINT8         MEM05;
+
+  UINT8         MEM06;
+  UINT8         MEM07;
+
+  UINT8         MEM08;
+  UINT8         MEM09;
+
+  UINT8         MEM10;
+  UINT8         MEM11;
+
+  UINT8         MEM12;
+  UINT8         MEM13;
+
+  UINT8         MEM14;
+  UINT8         MEM15;
+
+  UINT8         MEM16;
+  UINT8         MEM17;
+
+  UINT16        MEM18; 
+  UINT8         MEM19;
+
+  UINT8         MEM20; 
+  UINT8         MEM21;
+
+  UINT8         MEM22; 
+  UINT8         MEM23;
+
+  UINT8         MEM24; 
+  UINT8         MEM25;
+
+  UINT8         MEM26; 
+  UINT8         MEM27;
+
+  UINT8         MEM28; 
+  UINT8         MEM29;
+
+  UINT8         MEM30; 
+  UINT8         MEM31;
+
+  UINT8         MEM32; 
+  UINT8         MEM33;
+
+  UINT8         MEM34;
+  UINT8         MEM35;
+
+  //
+  // 
+  //
+  UINT8         MEM36;
+  UINT8         MEM37;
+  UINT8         MEM38;
+  UINT8         MEM39;
+
+  //
+  // 
+  //
+  UINT8         MEM40;
+  UINT8         MEM41;
+  UINT8         MEM42;
+  UINT8         MEM43;
+  UINT8         MEM44;
+  UINT8         MEM45;
+  UINT8         MEM46;
+  UINT8         MEM47;
+
+
+  //
+  // Port 80 decode 0/1 - PCI/LPC
+  UINT8         Port80Route;
+  UINT8         Port80RouteLockHide;
+
+  //
+  // ECC Event Logging
+  //
+  UINT8         EccEventLogging;
+  UINT8         EccEventLoggingLockHide;
+
+  //
+  // TPM Enable/Disable
+  //
+  UINT8         ETpm; 
+
+  //
+  // TPM question  0 = Disabled, 1 = Enabled
+  //
+  UINT8         ETpmClear;
+
+  //
+  // Secondary SATA Controller question  0 = Disabled, 1 = Enabled
+  //
+  UINT8         ExtSata;
+  UINT8         ExtSataLockHide;
+
+  //
+  // Mode selection for Secondary SATA Controller (0=IDE, 1=RAID)
+  //
+  UINT8         ExtSataMode;
+  UINT8         ExtSataModeLockHide;  
+
+  //
+  // LT Technology 0/1 -> Disable/Enable
+  //
+  UINT8         LtTechnology;
+  UINT8         LtTechnologyLockHide;
+
+  //
+  // HPET Support 0/1 -> Disable/Enable
+  //
+  UINT8         Hpet;
+  UINT8         HpetLockHide;
+
+  //
+  // ICH Function Level Reset enable/disable
+  //
+  UINT8         FlrCapability;
+  UINT8         FlrCapabilityLockHide;
+
+  // VT-d Option
+  UINT8         VTdSupport;  
+  UINT8         VTdSupportLockHide;  
+
+  UINT8         InterruptRemap;
+  UINT8         InterruptRemapLockHide;
+
+  UINT8         Isoc;
+  UINT8         IsocLockHide;
+
+  UINT8         CoherencySupport;
+  UINT8         CoherencySupportLockHide;
+
+  UINT8         ATS;
+  UINT8         ATSLockHide;
+
+  UINT8         PassThroughDma;
+  UINT8         PassThroughDmaLockHide;
+
+  //
+  // IGD option
+  //
+  UINT8         GraphicsDriverMemorySize;
+  UINT8         GraphicsDriverMemorySizeLockHide;
+
+
+  //
+  // Discrete SATA Type (Ide, Raid, Ahci)
+  //
+  UINT8         ExtSataMode2;
+  UINT8         ExtSataMode2LockHide;  
+
+  UINT8         ProcessorReserve00;
+  UINT8         ProcessorReserve01;  
+
+  //
+  // IGD Aperture Size question
+  //
+  UINT8         IgdApertureSize;
+  UINT8         IgdApertureSizeLockHide;
+
+  //
+  // Boot Display Device
+  //
+  UINT8         BootDisplayDevice;
+  UINT8         BootDisplayDeviceLockHide;
+
+
+  //
+  // System fan speed duty cycle
+  //
+  UINT8         SystemFanDuty;
+  UINT8         SystemFanDutyLockHide;
+
+
+  //
+  // S3 state LED indicator
+  //
+  UINT8         S3StateIndicator;
+  UINT8         S3StateIndicatorLockHide;
+
+  //
+  // S1 state LED indicator
+  //
+  UINT8         S1StateIndicator;
+  UINT8         S1StateIndicatorLockHide;
+
+  //
+  // PS/2 Wake from S5
+  //
+  UINT8         WakeOnS5Keyboard;
+  UINT8         WakeOnS5KeyboardLockHide;
+
+
+  //
+  // SATA Controller question  0 = Disabled, 1 = Enabled
+  //
+  UINT8         Sata;
+  UINT8         SataLockHide;  
+  
+  //
+  // PS2 port
+  //
+  UINT8         PS2;
+
+  //
+  // No VideoBeep
+  //
+  UINT8         NoVideoBeepEnable;
+
+  //
+  // Integrated Graphics Device
+  //
+  UINT8         Igd;
+
+  //
+  // Video Device select order
+  //
+  UINT8         VideoSelectOrder[8];
+
+  // Flash update sleep delay
+  UINT8         FlashSleepDelay;
+  UINT8         FlashSleepDelayLockHide;
+
+  //
+  // Boot Display Device2
+  //
+  UINT8         BootDisplayDevice2;
+  UINT8         BootDisplayDevice2LockHide;
+
+  //
+  // Flat Panel 
+  //
+  UINT8         EdpInterfaceType;
+  UINT8         EdpInterfaceTypeLockHide;
+
+  UINT8         LvdsInterfaceType;
+  UINT8         LvdsInterfaceTypeLockHide;
+
+  UINT8         ColorDepth;
+  UINT8         ColorDepthLockHide;
+  
+  UINT8         EdidConfiguration;
+  UINT8         EdidConfigurationLockHide;
+
+  UINT8         PwmReserved;
+  UINT8         MaxInverterPWMLockHide;
+
+  UINT8         PreDefinedEdidConfiguration;
+  UINT8         PreDefinedEdidConfigurationLockHide;
+
+  UINT16        ScreenBrightnessResponseTime;
+  UINT8         ScreenBrightnessResponseTimeLockHide;
+
+  UINT8         Serial3;
+  UINT8         Serial3LockHide;
+  
+  UINT8         Serial4;
+  UINT8         Serial4LockHide;
+
+  UINT8         CurrentSetupProfile;
+  UINT8         CurrentSetupProfileLockHide;
+
+  //
+  // FSC system Variable
+  //
+  UINT8         CPUFanUsage;
+  UINT8         CPUFanUsageLockHide;
+  UINT16        CPUUnderSpeedthreshold;
+  UINT8         CPUUnderSpeedthresholdLockHide;
+  UINT8         CPUFanControlMode;
+  UINT8         CPUFanControlModeLockHide;
+  UINT16        Voltage12UnderVolts;
+  UINT8         Voltage12UnderVoltsLockHide;
+  UINT16        Voltage12OverVolts;
+  UINT8         Voltage12OverVoltsLockHide;
+  UINT16        Voltage5UnderVolts;
+  UINT8         Voltage5UnderVoltsLockHide;
+  UINT16        Voltage5OverVolts;
+  UINT8         Voltage5OverVoltsLockHide;
+  UINT16        Voltage3p3UnderVolts;
+  UINT8         Voltage3p3UnderVoltsLockHide;
+  UINT16        Voltage3p3OverVolts;
+  UINT8         Voltage3p3OverVoltsLockHide;
+  UINT16        Voltage2p5UnderVolts;
+  UINT8         Voltage2p5UnderVoltsLockHide;
+  UINT16        Voltage2p5OverVolts;
+  UINT8         Voltage2p5OverVoltsLockHide;
+  UINT16        VoltageVccpUnderVolts;
+  UINT8         VoltageVccpUnderVoltsLockHide;
+  UINT16        VoltageVccpOverVolts;
+  UINT8         VoltageVccpOverVoltsLockHide;
+  UINT16        Voltage5BackupUnderVolts;
+  UINT8         Voltage5BackupUnderVoltsLockHide;
+  UINT16        Voltage5BackupOverVolts;
+  UINT8         Voltage5BackupOverVoltsLockHide;
+  UINT16        VS3p3StbyUnderVolt;
+  UINT8         VS3p3StbyUnderVoltLockHide;
+  UINT16        VS3p3StbyOverVolt;
+  UINT8         VS3p3StbyOverVoltLockHide;
+  UINT8         CPUFanMinDutyCycle;
+  UINT8         CPUFanMinDutyCycleLockHide;
+  UINT8         CPUFanMaxDutyCycle;
+  UINT8         CPUFanMaxDutyCycleLockHide;
+  UINT8         CPUFanOnDutyCycle;
+  UINT8         CPUFanOnDutyCycleLockHide;
+  UINT16        CpuOverTemp;
+  UINT8         CpuOverTempLockHide;
+  UINT16        CpuControlTemp;
+  UINT8         CpuControlTempLockHide;
+  UINT16        CpuAllOnTemp;
+  UINT8         CpuAllOnTempLockHide;
+  UINT8         CpuResponsiveness;
+  UINT8         CpuResponsivenessLockHide;
+  UINT8         CpuDamping;
+  UINT8         CpuDampingLockHide;
+  UINT16        PchOverTemp;
+  UINT8         PchOverTempLockHide;
+  UINT16        PchControlTemp;
+  UINT8         PchControlTempLockHide;
+  UINT16        PchAllOnTemp;
+  UINT8         PchAllOnTempLockHide;
+  UINT8         PchResponsiveness;
+  UINT8         PchResponsivenessLockHide;
+  UINT8         PchDamping;
+  UINT8         PchDampingLockHide;
+  UINT16        MemoryOverTemp;
+  UINT8         MemoryOverTempLockHide;
+  UINT16        MemoryControlTemp;
+  UINT8         MemoryControlTempLockHide;
+  UINT16        MemoryAllOnTemp;
+  UINT8         MemoryAllOnTempLockHide;
+  UINT8         MemoryResponsiveness;
+  UINT8         MemoryResponsivenessLockHide;
+  UINT8         MemoryDamping;
+  UINT8         MemoryDampingLockHide;
+  UINT16        VROverTemp;
+  UINT8         VROverTempLockHide;
+  UINT16        VRControlTemp;
+  UINT8         VRControlTempLockHide;
+  UINT16        VRAllOnTemp;
+  UINT8         VRAllOnTempLockHide;
+  UINT8         VRResponsiveness;
+  UINT8         VRResponsivenessLockHide;
+  UINT8         VRDamping;
+  UINT8         VRDampingLockHide;
+
+  UINT8         LvdsBrightnessSteps;
+  UINT8         LvdsBrightnessStepsLockHide;
+  UINT8         EdpDataRate;
+  UINT8         EdpDataRateLockHide;
+  UINT16        LvdsPowerOnToBacklightEnableDelayTime;
+  UINT8         LvdsPowerOnToBacklightEnableDelayTimeLockHide;
+  UINT16        LvdsPowerOnDelayTime;
+  UINT8         LvdsPowerOnDelayTimeLockHide;
+  UINT16        LvdsBacklightOffToPowerDownDelayTime;
+  UINT8         LvdsBacklightOffToPowerDownDelayTimeLockHide;
+  UINT16        LvdsPowerDownDelayTime;
+  UINT8         LvdsPowerDownDelayTimeLockHide;
+  UINT16        LvdsPowerCycleDelayTime;
+  UINT8         LvdsPowerCycleDelayTimeLockHide;
+
+  UINT8         IgdFlatPanel;
+  UINT8         IgdFlatPanelLockHide;
+  UINT8         Lan2;
+  UINT8         Lan2LockHide;
+
+  UINT8         SwapMode;
+  UINT8         SwapModeLockHide;
+
+  UINT8         Sata0HotPlugCap;
+  UINT8         Sata0HotPlugCapLockHide;
+  UINT8         Sata1HotPlugCap;
+  UINT8         Sata1HotPlugCapLockHide;
+
+  UINT8         UsbCharging;
+  UINT8         UsbChargingLockHide;
+
+  UINT8         Cstates;
+  UINT8         EnableC4;
+  UINT8         EnableC6;
+  
+  UINT8          FastBoot;
+  UINT8          EfiNetworkSupport;
+  UINT8          PxeRom;
+
+  //Add for PpmPlatformPlicy
+  UINT8          PPM00;
+  UINT8          PPM01;
+  UINT8          PPM02;
+  UINT8          PPM03;
+  UINT8          PPM04;
+  UINT8          PPM05;
+  UINT8          PPM06;
+  UINT8          PPM07;
+  UINT8          PPM08;
+  UINT8          PPM09;
+  UINT8          PPM10;
+  UINT8          QuietBoot;
+  UINT8          LegacyUSBBooting;
+
+  UINT8          PwmReserved02;
+  //
+  // Thermal Policy Values
+  //
+  UINT8           EnableDigitalThermalSensor;
+  UINT8           PassiveThermalTripPoint;
+  UINT8           PassiveTc1Value;
+  UINT8           PassiveTc2Value;
+  UINT8           PassiveTspValue;
+  UINT8           DisableActiveTripPoints; 
+  UINT8           CriticalThermalTripPoint;
+  UINT8           IchPciExp[4];
+  UINT8           DeepStandby;
+  UINT8           AlsEnable;
+  UINT8           IgdLcdIBia;
+  UINT8           LogBootTime;
+
+
+  UINT8           PcieRootPortIOApic[4];
+  UINT8           IffsEnable;
+  UINT8           IffsOnS3RtcWake;
+  UINT8           IffsS3WakeTimerMin;
+  UINT8           IffsOnS3CritBattWake;
+  UINT8           IffsCritBattWakeThreshold;
+  UINT8           ScramblerSupport;
+  UINT8           SecureBoot;
+  UINT8           SecureBootCustomMode;
+  UINT8           SecureBootUserPhysicalPresent;
+  UINT8           CoreFreMultipSelect;
+  UINT8           MaxCState;
+  UINT8           PanelScaling;
+  UINT8           IgdLcdIGmchBlc;
+  UINT8           GfxBoost;
+  UINT8           IgdThermal;
+  UINT8           SEC00;
+  UINT8           SEC01;
+  UINT8           SEC02;
+  UINT8           SEC03;
+  UINT8           MeasuredBootEnable;
+  UINT8           UseProductKey;
+  //Image Signal Processor PCI Device Configuration
+  //
+  UINT8         ISPDevSel;
+  UINT8         ISPEn;
+  // Passwords
+  UINT16          UserPassword[PASSWORD_MAX_SIZE];
+  UINT16          AdminPassword[PASSWORD_MAX_SIZE];
+  UINT8           Tdt;
+  UINT8           Recovery;
+  UINT8           Suspend;
+  UINT8           TdtState;
+  UINT8           TdtEnrolled;
+  UINT8           PBAEnable;
+
+  UINT8           HpetBootTime;
+  UINT8           UsbDebug;
+  UINT8           Lpe;
+  //
+  // LPSS Configuration
+  //
+  UINT8           LpssPciModeEnabled;  
+  //Scc
+  UINT8           LpsseMMCEnabled;
+  UINT8           LpssSdioEnabled;
+  UINT8           LpssSdcardEnabled;
+  UINT8           LpssSdCardSDR25Enabled;
+  UINT8           LpssSdCardDDR50Enabled;
+  UINT8           LpssMipiHsi;
+  UINT8           LpsseMMC45Enabled;
+  UINT8           LpsseMMC45DDR50Enabled;
+  UINT8           LpsseMMC45HS200Enabled;
+  UINT8           LpsseMMC45RetuneTimerValue;
+  UINT8           eMMCBootMode;
+  
+  //LPSS2
+  UINT8           LpssDma1Enabled;
+  UINT8           LpssI2C0Enabled;
+  UINT8           LpssI2C1Enabled;
+  UINT8           LpssI2C2Enabled;
+  UINT8           LpssI2C3Enabled;
+  UINT8           LpssI2C4Enabled;
+  UINT8           LpssI2C5Enabled;
+  UINT8           LpssI2C6Enabled;
+  //LPSS1
+  UINT8           LpssDma0Enabled;
+  UINT8           LpssPwm0Enabled;
+  UINT8           LpssPwm1Enabled;
+  UINT8           LpssHsuart0Enabled;
+  UINT8           LpssHsuart1Enabled;
+  UINT8           LpssSpiEnabled;
+  UINT8           I2CTouchAd;
+
+  UINT8   GTTSize;
+  //
+  // DVMT5.0 Graphic memory setting
+  //
+  UINT8   IgdDvmt50PreAlloc;
+  UINT8   IgdDvmt50TotalAlloc;
+  UINT8   IgdTurboEnabled;
+  
+  //
+  // Usb Config
+  //
+  UINT8   UsbAutoMode;       // PCH controller Auto mode
+  UINT8   UsbXhciSupport;
+  UINT8   Hsic0;
+  UINT8   PchUsb30Mode;
+  UINT8   PchUsb30Streams;
+  UINT8   PchUsb20;
+  UINT8   PchUsbPerPortCtl;
+  UINT8   PchUsbPort[8];
+  UINT8   PchUsbRmh;
+  UINT8   PchUsbOtg;
+  UINT8   PchUsbVbusOn;       //OTG VBUS control
+  UINT8   PchFSAOn;       //FSA control  
+  UINT8   EhciPllCfgEnable;
+
+
+  //Gbe
+  UINT8         PcieRootPortSpeed[PCH_PCIE_MAX_ROOT_PORTS];
+  UINT8   SlpLanLowDc;
+
+  UINT8   ISCT00;
+  UINT8   ISCT01;
+  UINT8   ISCT02;
+  UINT8   ISCT03;
+  UINT8          ISCT04;
+  UINT8          ISCT05;
+  UINT8          ISCT06;
+  UINT8          ISCT07;
+  //
+  // Azalia Configuration
+  //
+  UINT8   PchAzalia;
+  UINT8   AzaliaVCiEnable;
+  UINT8   AzaliaDs;
+  UINT8   AzaliaPme;
+  UINT8   HdmiCodec;
+
+  UINT8   UartInterface;
+  UINT8   PcuUart1;
+  //UINT8   PcuUart2;//for A0
+  UINT8   StateAfterG3;
+  UINT8   EnableClockSpreadSpec;
+  UINT8   GraphicReserve00;
+  UINT8   GOPEnable;
+  UINT8   GOPBrightnessLevel;                     //Gop Brightness level
+  UINT8   PavpMode;
+  UINT8   SEC04;
+  UINT8   SEC05;
+  UINT8   SEC06;
+  UINT8   SEC07;
+  
+  UINT8   HdmiCodecPortB;
+  UINT8   HdmiCodecPortC;
+  UINT8   HdmiCodecPortD;
+  UINT8   LidStatus;
+  UINT8   Reserved00;
+  UINT8   Reserved01; 
+  UINT16  Reserved02; 
+  UINT16  Reserved03; 
+  UINT16  Reserved04;
+  UINT16  Reserved05;
+  UINT16  Reserved06;   
+  UINT16  Reserved07;    
+  UINT16  Reserved08;  
+  UINT16  Reserved09; 
+  UINT16  Reserved0A; 
+  UINT16  Reserved0B; 
+  UINT16  Reserved0C; 
+  UINT16  Reserved0D;
+  UINT8   Reserved0E;
+  UINT8   Reserved0F; 
+  UINT32  Reserved10;
+  UINT32  Reserved11; 
+  UINT32  Reserved12; 
+  UINT32  Reserved13; 
+  UINT32  Reserved14;  
+  UINT8   Reserved15;
+  UINT8   Reserved16;
+  UINT8   Reserved17;
+  UINT8   Reserved18;
+  UINT8   Reserved19;
+  UINT8   Reserved1A;
+  UINT8   Reserved1B;    
+  UINT8   Reserved1C;
+  UINT8   Reserved1D;
+  UINT8   Reserved1E;
+  UINT8   Reserved1F;
+  UINT8   Reserved20;  
+  UINT8   PmicEnable;
+  UINT8   IdleReserve;
+  UINT8   TSEGSizeSel;
+  UINT8   ACPIMemDbg;
+  UINT8          ExISupport;
+  UINT8   BatteryChargingSolution;                 //0-non ULPMC 1-ULPMC
+  UINT8   PnpSettings;
+  UINT8   CfioPnpSettings;
+  UINT8   PchEhciDebug;
+  UINT8   CRIDSettings;
+  UINT8   ULPMCFWLock;
+  UINT8   SpiRwProtect;
+  UINT8   GraphicReserve02;
+  UINT8   PDMConfig;
+  UINT16  LmMemSize;
+  UINT8   PunitBIOSConfig;
+  UINT8   LpssSdioMode;
+  UINT8   ENDBG2;
+  UINT8   WittEnable;
+  UINT8   UtsEnable;
+  UINT8   TristateLpc;
+  UINT8   GraphicReserve05;
+  UINT8   UsbXhciLpmSupport;
+  UINT8   EnableAESNI;
+  UINT8   SecureErase;
+
+  UINT8   MmioSize;
+
+
+  UINT8   SAR1;
+
+  UINT8   DisableCodec262;
+  UINT8   ReservedO;
+  UINT8   PcieDynamicGating;        // Need PMC enable it first from PMC 0x3_12 MCU 318.
+
+  UINT8   MipiDsi;
+
+  //Added flow control item for UART1 and UART2
+  UINT8  LpssHsuart0FlowControlEnabled;
+  UINT8  LpssHsuart1FlowControlEnabled;
+
+  UINT8   SdCardRemovable; // ACPI reporting MMC/SD media as: removable/non-removable
+  
+  UINT8   GpioWakeCapability;
+
+} SYSTEM_CONFIGURATION;
+#pragma pack()
+
+#ifndef PLATFORM_SETUP_VARIABLE_NAME
+#define PLATFORM_SETUP_VARIABLE_NAME             L"Setup"
+#endif
+
+#pragma pack(1)
+typedef struct{
+  // Passwords
+  UINT16        UserPassword[PASSWORD_MAX_SIZE];
+  UINT16        AdminPassword[PASSWORD_MAX_SIZE];
+  UINT16        DummyDataForVfrBug;  // Don't change or use
+
+} SYSTEM_PASSWORDS;
+#pragma pack()
+
+//
+// #defines for Drive Presence
+//
+#define EFI_HDD_PRESENT       0x01
+#define EFI_HDD_NOT_PRESENT   0x00
+#define EFI_CD_PRESENT        0x02
+#define EFI_CD_NOT_PRESENT    0x00
+
+#define EFI_HDD_WARNING_ON    0x01
+#define EFI_CD_WARNING_ON     0x02
+#define EFI_SMART_WARNING_ON  0x04
+#define EFI_HDD_WARNING_OFF   0x00
+#define EFI_CD_WARNING_OFF    0x00
+#define EFI_SMART_WARNING_OFF 0x00
+
+#ifndef VFRCOMPILE
+extern EFI_GUID gEfiSetupVariableGuid;
+#endif
+
+#define SETUP_DATA SYSTEM_CONFIGURATION
+
+#endif // #ifndef _SETUP_VARIABLE

diff --git a/Vlv2TbltDevicePkg/Include/Hpet.h b/Vlv2TbltDevicePkg/Include/Hpet.h
new file mode 100644 (file)
index 0000000..10ada91
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Include/Hpet.h
@@ -0,0 +1,45 @@
+/*++\r
+\r
+  Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+\r
+Module Name:\r
+\r
+  Mseg.h\r
+\r
+Abstract:\r
+\r
+  This file describes the contents of the ACPI HEPT Table.\r
+\r
+--*/\r
+\r
+#ifndef _HPET_H\r
+#define _HPET_H\r
+\r
+//\r
+// Statements that include other files\r
+//\r
+#include <IndustryStandard/Acpi10.h>\r
+#include <IndustryStandard/Acpi20.h>\r
+#include <IndustryStandard/Acpi30.h>\r
+#include <IndustryStandard/HighPrecisionEventTimerTable.h>\r
+\r
+//\r
+// HPET Definitions\r
+//\r
+#define EFI_ACPI_HPET_TABLE_REVISION            0x1\r
+#define MAIN_COUNTER_MIN_PERIODIC_CLOCK_TICKS  0x80        //approx 1ms\r
+\r
+#define HPET_BASE_ADDRESS                       0xFED00000\r
+#define EFI_ACPI_EVENT_TIMER_BLOCK_ID           0x8086A001\r
+\r
+#endif\r

diff --git a/Vlv2TbltDevicePkg/Include/Library/BiosIdLib.h b/Vlv2TbltDevicePkg/Include/Library/BiosIdLib.h
new file mode 100644 (file)
index 0000000..aa20539
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Include/Library/BiosIdLib.h
@@ -0,0 +1,109 @@
+/*++\r
+\r
+  Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+\r
+Module Name:\r
+\r
+  BiosIdLib.h\r
+\r
+Abstract:\r
+\r
+  BIOS ID library definitions.\r
+\r
+  This library provides functions to get BIOS ID, VERSION, DATE and TIME\r
+\r
+--*/\r
+\r
+#ifndef _BIOS_ID_LIB_H_\r
+#define _BIOS_ID_LIB_H_\r
+\r
+//\r
+// BIOS ID string format:\r
+//\r
+// $(BOARD_ID)$(BOARD_REV).$(OEM_ID).$(VERSION_MAJOR).$(BUILD_TYPE)$(VERSION_MINOR).YYMMDDHHMM\r
+//\r
+// Example: "TRFTCRB1.86C.0008.D03.0506081529"\r
+//\r
+#pragma pack(1)\r
+\r
+typedef struct {\r
+  CHAR16  BoardId[7];               // "TRFTCRB"\r
+  CHAR16  BoardRev;                 // "1"\r
+  CHAR16  Dot1;                     // "."\r
+  CHAR16  OemId[3];                 // "86C"\r
+  CHAR16  Dot2;                     // "."\r
+  CHAR16  VersionMajor[4];          // "0008"\r
+  CHAR16  Dot3;                     // "."\r
+  CHAR16  BuildType;                // "D"\r
+  CHAR16  VersionMinor[2];          // "03"\r
+  CHAR16  Dot4;                     // "."\r
+  CHAR16  TimeStamp[10];            // "YYMMDDHHMM"\r
+  CHAR16  NullTerminator;           // 0x0000\r
+} BIOS_ID_STRING;\r
+\r
+#define MEM_IFWIVER_START           0x7E0000\r
+#define MEM_IFWIVER_LENGTH          0x1000\r
+\r
+typedef struct _MANIFEST_OEM_DATA{\r
+  UINT32         Signature;\r
+  unsigned char  FillNull[0x39];\r
+  UINT32         IFWIVersionLen;\r
+  unsigned char  IFWIVersion[32];\r
+}MANIFEST_OEM_DATA;\r
+\r
+//\r
+// A signature precedes the BIOS ID string in the FV to enable search by external tools.\r
+//\r
+typedef struct {\r
+  UINT8           Signature[8];     // "$IBIOSI$"\r
+  BIOS_ID_STRING  BiosIdString;     // "TRFTCRB1.86C.0008.D03.0506081529"\r
+} BIOS_ID_IMAGE;\r
+\r
+#pragma pack()\r
+\r
+/**\r
+  This function returns BIOS ID by searching HOB or FV.\r
+\r
+  @param[in]  BiosIdImage         The BIOS ID got from HOB or FV\r
+\r
+  @retval  EFI_SUCCESS            All parameters were valid and BIOS ID has been got.\r
+  @retval  EFI_NOT_FOUND          BiosId image is not found, and no parameter will be modified.\r
+  @retval  EFI_INVALID_PARAMETER  The parameter is NULL.\r
+\r
+**/\r
+EFI_STATUS\r
+GetBiosId (\r
+  OUT BIOS_ID_IMAGE     *BiosIdImage\r
+  );\r
+\r
+/**\r
+  This function returns the Version & Release Date and Time by getting and converting\r
+  BIOS ID.\r
+\r
+  @param[in] BiosVersion         The Bios Version out of the conversion.\r
+  @param[in] BiosReleaseDate     The Bios Release Date out of the conversion.\r
+  @param[in] BiosReleaseTime     The Bios Release Time out of the conversion.\r
+\r
+  @retval EFI_SUCCESS            BIOS Version & Release Date and Time have been got successfully.\r
+  @retval EFI_NOT_FOUND          BiosId image is not found, and no parameter will be modified.\r
+  @retval EFI_INVALID_PARAMETER  All the parameters are NULL.\r
+\r
+**/\r
+EFI_STATUS\r
+GetBiosVersionDateTime (\r
+  OUT CHAR16    *BiosVersion, OPTIONAL\r
+  OUT CHAR16    *BiosReleaseDate, OPTIONAL\r
+  OUT CHAR16    *BiosReleaseTime OPTIONAL\r
+  );\r
+\r
+#endif\r

diff --git a/Vlv2TbltDevicePkg/Include/Library/CpuIA32.h b/Vlv2TbltDevicePkg/Include/Library/CpuIA32.h
new file mode 100644 (file)
index 0000000..b8c53c9
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Include/Library/CpuIA32.h
@@ -0,0 +1,350 @@
+/*++\r
+\r
+  Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+\r
+Module Name:\r
+\r
+  CpuIA32.h\r
+\r
+Abstract:\r
+\r
+--*/\r
+\r
+#ifndef _CPU_IA32_H\r
+#define _CPU_IA32_H\r
+\r
+typedef struct {\r
+  UINT32  RegEax;\r
+  UINT32  RegEbx;\r
+  UINT32  RegEcx;\r
+  UINT32  RegEdx;\r
+} EFI_CPUID_REGISTER;\r
+\r
+typedef struct {\r
+  UINT32  HeaderVersion;\r
+  UINT32  UpdateRevision;\r
+  UINT32  Date;\r
+  UINT32  ProcessorId;\r
+  UINT32  Checksum;\r
+  UINT32  LoaderRevision;\r
+  UINT32  ProcessorFlags;\r
+  UINT32  DataSize;\r
+  UINT32  TotalSize;\r
+  UINT8   Reserved[12];\r
+} EFI_CPU_MICROCODE_HEADER;\r
+\r
+typedef struct {\r
+  UINT32  ExtendedSignatureCount;\r
+  UINT32  ExtendedTableChecksum;\r
+  UINT8   Reserved[12];\r
+} EFI_CPU_MICROCODE_EXTENDED_TABLE_HEADER;\r
+\r
+typedef struct {\r
+  UINT32  ProcessorSignature;\r
+  UINT32  ProcessorFlag;\r
+  UINT32  ProcessorChecksum;\r
+} EFI_CPU_MICROCODE_EXTENDED_TABLE;\r
+\r
+typedef struct {\r
+  UINT32  Stepping       : 4;\r
+  UINT32  Model          : 4;\r
+  UINT32  Family         : 4;\r
+  UINT32  Type           : 2;\r
+  UINT32  Reserved1      : 2;\r
+  UINT32  ExtendedModel  : 4;\r
+  UINT32  ExtendedFamily : 8;\r
+  UINT32  Reserved2      : 4;\r
+} EFI_CPU_VERSION;\r
+\r
+#define EFI_CPUID_SIGNATURE                   0x0\r
+#define EFI_CPUID_VERSION_INFO                0x1\r
+#define EFI_CPUID_CACHE_INFO                  0x2\r
+#define EFI_CPUID_SERIAL_NUMBER               0x3\r
+#define EFI_CPUID_EXTENDED_FUNCTION           0x80000000\r
+#define EFI_CPUID_EXTENDED_CPU_SIG            0x80000001\r
+#define EFI_CPUID_BRAND_STRING1               0x80000002\r
+#define EFI_CPUID_BRAND_STRING2               0x80000003\r
+#define EFI_CPUID_BRAND_STRING3               0x80000004\r
+\r
+#define EFI_MSR_IA32_PLATFORM_ID              0x17\r
+#define EFI_MSR_IA32_APIC_BASE                0x1B\r
+#define EFI_MSR_EBC_HARD_POWERON              0x2A\r
+#define EFI_MSR_EBC_SOFT_POWERON              0x2B\r
+#define BINIT_DRIVER_DISABLE                  0x40\r
+#define INTERNAL_MCERR_DISABLE                0x20\r
+#define INITIATOR_MCERR_DISABLE               0x10\r
+#define EFI_MSR_EBC_FREQUENCY_ID              0x2C\r
+#define EFI_MSR_IA32_BIOS_UPDT_TRIG           0x79\r
+#define EFI_MSR_IA32_BIOS_SIGN_ID             0x8B\r
+#define EFI_MSR_PSB_CLOCK_STATUS              0xCD\r
+#define EFI_APIC_GLOBAL_ENABLE                0x800\r
+#define EFI_MSR_IA32_MISC_ENABLE              0x1A0\r
+#define LIMIT_CPUID_MAXVAL_ENABLE_BIT         0x00400000\r
+#define AUTOMATIC_THERMAL_CONTROL_ENABLE_BIT  0x00000008\r
+#define COMPATIBLE_FPU_OPCODE_ENABLE_BIT      0x00000004\r
+#define LOGICAL_PROCESSOR_PRIORITY_ENABLE_BIT 0x00000002\r
+#define FAST_STRING_ENABLE_BIT                0x00000001\r
+\r
+#define EFI_CACHE_VARIABLE_MTRR_BASE          0x200\r
+#define EFI_CACHE_VARIABLE_MTRR_END           0x20F\r
+#define EFI_CACHE_IA32_MTRR_DEF_TYPE          0x2FF\r
+#define EFI_CACHE_MTRR_VALID                  0x800\r
+#define EFI_CACHE_FIXED_MTRR_VALID            0x400\r
+#define EFI_CACHE_VALID_ADDRESS               0xFFFFFF000\r
+#define EFI_MSR_VALID_MASK                    0xFFFFFFFFF\r
+#define EFI_CACHE_VALID_EXTENDED_ADDRESS      0xFFFFFFFFFF000\r
+#define EFI_MSR_VALID_EXTENDED_MASK           0xFFFFFFFFFFFFF\r
+\r
+#define EFI_IA32_MTRR_FIX64K_00000            0x250\r
+#define EFI_IA32_MTRR_FIX16K_80000            0x258\r
+#define EFI_IA32_MTRR_FIX16K_A0000            0x259\r
+#define EFI_IA32_MTRR_FIX4K_C0000             0x268\r
+#define EFI_IA32_MTRR_FIX4K_C8000             0x269\r
+#define EFI_IA32_MTRR_FIX4K_D0000             0x26A\r
+#define EFI_IA32_MTRR_FIX4K_D8000             0x26B\r
+#define EFI_IA32_MTRR_FIX4K_E0000             0x26C\r
+#define EFI_IA32_MTRR_FIX4K_E8000             0x26D\r
+#define EFI_IA32_MTRR_FIX4K_F0000             0x26E\r
+#define EFI_IA32_MTRR_FIX4K_F8000             0x26F\r
+\r
+#define EFI_IA32_MCG_CAP                      0x179\r
+#define EFI_IA32_MCG_CTL                      0x17B\r
+#define EFI_IA32_MC0_CTL                      0x400\r
+#define EFI_IA32_MC0_STATUS                   0x401\r
+\r
+#define EFI_IA32_PERF_STATUS                  0x198\r
+#define EFI_IA32_PERF_CTL                     0x199\r
+\r
+#define EFI_CACHE_UNCACHEABLE                 0\r
+#define EFI_CACHE_WRITECOMBINING              1\r
+#define EFI_CACHE_WRITETHROUGH                4\r
+#define EFI_CACHE_WRITEPROTECTED              5\r
+#define EFI_CACHE_WRITEBACK                   6\r
+\r
+//\r
+// Combine f(FamilyId), m(Model), s(SteppingId) to a single 32 bit number\r
+//\r
+#define EfiMakeCpuVersion(f, m, s)         \\r
+  (((UINT32) (f) << 16) | ((UINT32) (m) << 8) | ((UINT32) (s)))\r
+\r
+/**\r
+  Halt the Cpu\r
+\r
+  @param[in] None\r
+\r
+  @retval None\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+EfiHalt (\r
+  VOID\r
+  );\r
+\r
+/**\r
+  Write back and invalidate the Cpu cache\r
+\r
+  @param[in] None\r
+\r
+  @retval None\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+EfiWbinvd (\r
+  VOID\r
+  );\r
+\r
+/**\r
+  Invalidate the Cpu cache\r
+\r
+   @param[in] None\r
+\r
+   @retval None\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+EfiInvd (\r
+  VOID\r
+  );\r
+\r
+/**\r
+  Get the Cpu info by excute the CPUID instruction\r
+\r
+  @param[in] RegisterInEax The input value to put into register EAX\r
+  @param[in] Regs          The Output value\r
+\r
+  @retval None\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+EfiCpuid (\r
+  IN  UINT32                 RegisterInEax,\r
+  OUT EFI_CPUID_REGISTER     *Regs\r
+  );\r
+\r
+/**\r
+  When RegisterInEax != 4, the functionality is the same as EfiCpuid.\r
+  When RegisterInEax == 4, the function return the deterministic cache\r
+  parameters by excuting the CPUID instruction.\r
+\r
+  @param[in]  RegisterInEax  The input value to put into register EAX.\r
+  @param[in]  CacheLevel     The deterministic cache level.\r
+  @param[in]  Regs           The Output value.\r
+\r
+  @retval None\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+EfiCpuidExt (\r
+  IN  UINT32                 RegisterInEax,\r
+  IN  UINT32                 CacheLevel,\r
+  OUT EFI_CPUID_REGISTER     *Regs\r
+  );\r
+\r
+/**\r
+  Read Cpu MSR\r
+\r
+  @param[in] Index  The index value to select the register\r
+\r
+  @retval           Return the read data\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+EfiReadMsr (\r
+  IN UINT32     Index\r
+  );\r
+\r
+/**\r
+  Write Cpu MSR\r
+\r
+  @param[in] Index  The index value to select the register\r
+  @param[in] Value  The value to write to the selected register\r
+\r
+  @retval None\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+EfiWriteMsr (\r
+  IN UINT32     Index,\r
+  IN UINT64     Value\r
+  );\r
+\r
+/**\r
+  Read Time stamp\r
+\r
+  @param[in] None\r
+\r
+  @retval Return the read data\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+EfiReadTsc (\r
+  VOID\r
+  );\r
+\r
+/**\r
+  Writing back and invalidate the cache,then diable it\r
+\r
+  @param[in] None\r
+\r
+  @retval None\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+EfiDisableCache (\r
+  VOID\r
+  );\r
+\r
+/**\r
+  Invalidate the cache,then Enable it\r
+\r
+  @param[in] None\r
+\r
+  @retval None\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+EfiEnableCache (\r
+  VOID\r
+  );\r
+\r
+/**\r
+  Get Eflags\r
+\r
+  @param[in] None\r
+\r
+  @retval Return the Eflags value\r
+\r
+**/\r
+UINT32\r
+EFIAPI\r
+EfiGetEflags (\r
+  VOID\r
+  );\r
+\r
+/**\r
+  Disable Interrupts\r
+\r
+  @param[in] None\r
+\r
+  @retval None\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+EfiDisableInterrupts (\r
+  VOID\r
+  );\r
+\r
+/**\r
+  Enable Interrupts\r
+\r
+  @param[in] None\r
+\r
+  @retval None\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+EfiEnableInterrupts (\r
+  VOID\r
+  );\r
+\r
+/**\r
+  Extract CPU detail version infomation\r
+\r
+  @param[in] FamilyId    FamilyId, including ExtendedFamilyId\r
+  @param[in] Model       Model, including ExtendedModel\r
+  @param[in] SteppingId  SteppingId\r
+  @param[in] Processor   Processor\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+EfiCpuVersion (\r
+  IN   UINT16  *FamilyId,    OPTIONAL\r
+  IN   UINT8   *Model,       OPTIONAL\r
+  IN   UINT8   *SteppingId,  OPTIONAL\r
+  IN   UINT8   *Processor    OPTIONAL\r
+  );\r
+\r
+#endif\r

diff --git a/Vlv2TbltDevicePkg/Include/Library/EfiRegTableLib.h b/Vlv2TbltDevicePkg/Include/Library/EfiRegTableLib.h
new file mode 100644 (file)
index 0000000..796c64c
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Include/Library/EfiRegTableLib.h
@@ -0,0 +1,201 @@
+/*++\r
+\r
+  Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+\r
+Module Name:\r
+\r
+  EfiRegTableLib.h\r
+\r
+Abstract:\r
+\r
+  Definitions and macros for building register tables for chipset\r
+  initialization..\r
+\r
+  Components linking this lib must include CpuIo, PciRootBridgeIo, and\r
+  BootScriptSave protocols in their DPX.\r
+\r
+\r
+\r
+--*/\r
+\r
+#ifndef EFI_REG_TABLE_H\r
+#define EFI_REG_TABLE_H\r
+\r
+\r
+#include <PiDxe.h>\r
+#include <Library/BaseLib.h>\r
+#include <Library/DebugLib.h>\r
+#include <Library/UefiLib.h>\r
+#include <Library/UefiDriverEntryPoint.h>\r
+#include <Protocol/CpuIo.h>\r
+#include <Protocol/BootScriptSave.h>\r
+#include <Framework/BootScript.h>\r
+#include <Protocol/PciRootBridgeIo.h>\r
+\r
+\r
+#define OPCODE_BASE(OpCode)       ((UINT8)((OpCode) & 0xFF))\r
+#define OPCODE_FLAGS(OpCode)      ((UINT8)(((OpCode) >> 8) & 0xFF))\r
+#define OPCODE_EXTRA_DATA(OpCode) ((UINT16)((OpCode) >> 16))\r
+\r
+//\r
+// RegTable Base OpCodes\r
+//\r
+#define OP_TERMINATE_TABLE                0\r
+#define OP_MEM_WRITE                      1\r
+#define OP_MEM_READ_MODIFY_WRITE          2\r
+#define OP_IO_WRITE                       3\r
+#define OP_IO_READ_MODIFY_WRITE           4\r
+#define OP_PCI_WRITE                      5\r
+#define OP_PCI_READ_MODIFY_WRITE          6\r
+#define OP_STALL                          7\r
+\r
+//\r
+// RegTable OpCode Flags\r
+//\r
+#define OPCODE_FLAG_S3SAVE                1\r
+\r
+\r
+#define TERMINATE_TABLE { (UINT32) OP_TERMINATE_TABLE, (UINT32) 0, (UINT32) 0 }\r
+\r
+\r
+//\r
+// REG_TABLE_ENTRY_PCI_WRITE encodes the width in the upper bits of the OpCode\r
+// as one of the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH values\r
+//\r
+typedef struct {\r
+  UINT32                                OpCode;\r
+  UINT32                                PciAddress;\r
+  UINT32                                Data;\r
+} EFI_REG_TABLE_PCI_WRITE;\r
+\r
+#define PCI_WRITE(Bus, Dev, Fnc, Reg, Width, Data, S3Flag)                    \\r
+  {                                                                           \\r
+    (UINT32) (OP_PCI_WRITE | ((S3Flag) << 8) | ((Width) << 16)),              \\r
+    (UINT32) (EFI_PCI_ADDRESS ((Bus), (Dev), (Fnc), (Reg))),                  \\r
+    (UINT32) (Data),                                                          \\r
+    (UINT32) (0)                                                              \\r
+  }\r
+\r
+typedef struct {\r
+  UINT32                                OpCode;\r
+  UINT32                                MemAddress;\r
+  UINT32                                Data;\r
+} EFI_REG_TABLE_MEM_WRITE;\r
+\r
+typedef struct {\r
+  UINT32                                OpCode;\r
+  UINT32                                PciAddress;\r
+  UINT32                                OrMask;\r
+  UINT32                                AndMask;\r
+} EFI_REG_TABLE_PCI_READ_MODIFY_WRITE;\r
+\r
+#define PCI_READ_MODIFY_WRITE(Bus, Dev, Fnc, Reg, Width, OrMask, AndMask, S3Flag)  \\r
+  {                                                                           \\r
+    (UINT32) (OP_PCI_READ_MODIFY_WRITE | ((S3Flag) << 8) | ((Width) << 16)),  \\r
+    (UINT32) (EFI_PCI_ADDRESS ((Bus), (Dev), (Fnc), (Reg))),                  \\r
+    (UINT32) (OrMask),                                                        \\r
+    (UINT32) (AndMask)                                                        \\r
+  }\r
+\r
+typedef struct {\r
+  UINT32                                OpCode;\r
+  UINT32                                MemAddress;\r
+  UINT32                                OrMask;\r
+  UINT32                                AndMask;\r
+} EFI_REG_TABLE_MEM_READ_MODIFY_WRITE;\r
+\r
+#define MEM_READ_MODIFY_WRITE(Address, Width, OrMask, AndMask, S3Flag)  \\r
+  {                                                                           \\r
+    (UINT32) (OP_MEM_READ_MODIFY_WRITE | ((S3Flag) << 8) | ((Width) << 16)),  \\r
+    (UINT32) (Address),                  \\r
+    (UINT32) (OrMask),                                                        \\r
+    (UINT32) (AndMask)                                                        \\r
+  }\r
+\r
+typedef struct {\r
+  UINT32                                OpCode;\r
+  UINT32                                Field2;\r
+  UINT32                                Field3;\r
+  UINT32                                Field4;\r
+} EFI_REG_TABLE_GENERIC;\r
+\r
+typedef union {\r
+  EFI_REG_TABLE_GENERIC                 Generic;\r
+  EFI_REG_TABLE_PCI_WRITE               PciWrite;\r
+  EFI_REG_TABLE_PCI_READ_MODIFY_WRITE   PciReadModifyWrite;\r
+  EFI_REG_TABLE_MEM_READ_MODIFY_WRITE   MemReadModifyWrite;\r
+} EFI_REG_TABLE;\r
+\r
+/**\r
+  Processes register table assuming which may contain PCI, IO, MEM, and STALL\r
+  entries.\r
+\r
+  No parameter checking is done so the caller must be careful about omitting\r
+  values for PciRootBridgeIo or CpuIo parameters.  If the regtable does\r
+  not contain any PCI accesses, it is safe to omit the PciRootBridgeIo (supply\r
+  NULL).  If the regtable does not contain any IO or Mem entries, it is safe to\r
+  omit the CpuIo (supply NULL).\r
+\r
+  The RegTableEntry parameter is not checked, but is required.\r
+\r
+  gBS is assumed to have been defined and is used when processing stalls.\r
+\r
+  The function processes each entry sequentially until an OP_TERMINATE_TABLE\r
+  entry is encountered.\r
+\r
+  @param[in] RegTableEntry    A pointer to the register table to process\r
+\r
+  @param[in] PciRootBridgeIo  A pointer to the instance of PciRootBridgeIo that is used\r
+                              when processing PCI table entries\r
+\r
+  @param[in] CpuIo            A pointer to the instance of CpuIo that is used when processing IO and\r
+                              MEM table entries\r
+\r
+  @retval Nothing.\r
+\r
+**/\r
+VOID\r
+ProcessRegTablePci (\r
+  EFI_REG_TABLE                   * RegTableEntry,\r
+  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL * PciRootBridgeIo,\r
+  EFI_CPU_IO_PROTOCOL             * CpuIo\r
+  );\r
+\r
+/**\r
+  Processes register table assuming which may contain IO, MEM, and STALL\r
+  entries, but must NOT contain any PCI entries.  Any PCI entries cause an\r
+  ASSERT in a DEBUG build and are skipped in a free build.\r
+\r
+  No parameter checking is done.  Both RegTableEntry and CpuIo parameters are\r
+  required.\r
+\r
+  gBS is assumed to have been defined and is used when processing stalls.\r
+\r
+  The function processes each entry sequentially until an OP_TERMINATE_TABLE\r
+  entry is encountered.\r
+\r
+  @param[in] RegTableEntry - A pointer to the register table to process\r
+\r
+  @param[in] CpuIo - A pointer to the instance of CpuIo that is used when processing IO and\r
+                  MEM table entries\r
+\r
+  @retval Nothing.\r
+\r
+**/\r
+VOID\r
+ProcessRegTableCpu (\r
+  EFI_REG_TABLE                   * RegTableEntry,\r
+  EFI_CPU_IO_PROTOCOL             * CpuIo\r
+  );\r
+\r
+#endif\r

diff --git a/Vlv2TbltDevicePkg/Include/Library/Esrt.h b/Vlv2TbltDevicePkg/Include/Library/Esrt.h
new file mode 100644 (file)
index 0000000..06977b6
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Include/Library/Esrt.h
@@ -0,0 +1,79 @@
+/*++\r
+\r
+  Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+\r
+Module Name:\r
+\r
+ Esrt.h\r
+\r
+Abstract:\r
+\r
+--*/\r
+\r
+#ifndef _DFU_ESRT_H_\r
+#define _DFU_ESRT_H_\r
+\r
+typedef struct {\r
+  EFI_GUID         FwClass;\r
+  UINT32           FwType;\r
+  UINT32           FwVersion;\r
+  UINT32           FwLstCompatVersion;\r
+  UINT32           CapsuleFlags;\r
+  UINT32           LastAttemptVersion;\r
+  UINT32           LastAttemptStatus;\r
+} FW_RES_ENTRY;\r
+\r
+typedef struct {\r
+  UINT32           NumEntries;\r
+  FW_RES_ENTRY     FwEntries[256];\r
+} FW_RES_ENTRY_LIST;\r
+\r
+\r
+typedef struct {\r
+  UINT32          FwResourceCount;\r
+  UINT32          FwResourceMax;\r
+  UINT64          FwResourceVersion;\r
+} EFI_SYSTEM_RESOURCE_TABLE;\r
+\r
+\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *ESRT_POPULATE_TABLE) (\r
+);\r
+\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *ESRT_UPDATE_TABLE_ENTRY_BY_GUID) (\r
+       IN EFI_GUID FwEntryGuid,\r
+       IN FW_RES_ENTRY *FwEntry\r
+);\r
+\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *ESRT_GET_FW_ENTRY_BY_GUID) (\r
+    IN EFI_GUID FwEntryGuid,\r
+       OUT FW_RES_ENTRY *FwEntry\r
+);\r
+\r
+\r
+#pragma pack()\r
+\r
+typedef struct _ESRT_OPERATION_PROTOCOL {\r
+   ESRT_POPULATE_TABLE                                 EsrtPopulateTable;\r
+   ESRT_UPDATE_TABLE_ENTRY_BY_GUID             EsrtUpdateTableEntryByGuid;\r
+   ESRT_GET_FW_ENTRY_BY_GUID                   EsrtGetFwEntryByGuid;\r
+} ESRT_OPERATION_PROTOCOL;\r
+\r
+extern EFI_GUID gEfiEsrtOperationProtocolGuid;\r
+\r
+#endif\r

diff --git a/Vlv2TbltDevicePkg/Include/Library/Fd.h b/Vlv2TbltDevicePkg/Include/Library/Fd.h
new file mode 100644 (file)
index 0000000..20c7052
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Include/Library/Fd.h
@@ -0,0 +1,269 @@
+/*++\r
+\r
+  Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+\r
+\r
+Module Name:\r
+\r
+  Fd.h\r
+\r
+Abstract:\r
+\r
+  EFI Intel82802AB/82802AC Firmware Hub.\r
+\r
+\r
+--*/\r
+\r
+\r
+//\r
+// Supported SPI devices\r
+//\r
+\r
+//\r
+// MFG and Device code\r
+//\r
+#define SST_25LF040A        0x0044BF\r
+#define SST_25LF040         0x0040BF\r
+#define SST_25LF080A        0x0080BF\r
+#define SST_25VF080B        0x008EBF\r
+#define SST_25VF016B        0x0041BF\r
+#define SST_25VF032B        0x004ABF\r
+\r
+#define PMC_25LV040         0x007E9D\r
+\r
+#define ATMEL_26DF041       0x00441F\r
+#define Atmel_AT26F004      0x00041F\r
+#define Atmel_AT26DF081A    0x01451F\r
+#define Atmel_AT25DF161     0x02461F\r
+#define Atmel_AT26DF161     0x00461F\r
+#define Atmel_AT25DF641     0x00481F\r
+#define Atmel_AT26DF321     0x00471F\r
+\r
+#define Macronix_MX25L8005  0x1420C2\r
+#define Macronix_MX25L1605A 0x1520C2\r
+#define Macronix_MX25L3205D 0x1620C2\r
+\r
+#define STMicro_M25PE80     0x148020\r
+\r
+#define Winbond_W25X40      0x1330EF\r
+#define Winbond_W25X80      0x1430EF\r
+#define Winbond_W25Q80      0x1440EF\r
+\r
+#define Winbond_W25X16      0x1540EF    // W25Q16\r
+#define Winbond_W25X32      0x1630EF\r
+\r
+//\r
+//  NOTE: Assuming that 8Mbit flash will only contain a 4Mbit binary.\r
+//  Treating 4Mbit and 8Mbit devices the same.\r
+//\r
+\r
+//\r
+// BIOS Base Address\r
+//\r
+#define BIOS_BASE_ADDRESS_4M  0xFFF80000\r
+#define BIOS_BASE_ADDRESS_8M  0xFFF00000\r
+#define BIOS_BASE_ADDRESS_16M 0xFFE00000\r
+\r
+//\r
+// block and sector sizes\r
+//\r
+#define SECTOR_SIZE_256BYTE 0x100       // 256byte page size\r
+#define SECTOR_SIZE_4KB     0x1000      // 4kBytes sector size\r
+#define BLOCK_SIZE_32KB     0x00008000  // 32Kbytes block size\r
+#define MAX_FLASH_SIZE      0x00400000  // 32Mbit (Note that this can also be used for the 4Mbit & 8Mbit)\r
+\r
+//\r
+// Flash commands\r
+//\r
+#define SPI_SST25LF_COMMAND_WRITE         0x02\r
+#define SPI_SST25LF_COMMAND_READ          0x03\r
+#define SPI_SST25LF_COMMAND_ERASE         0x20\r
+#define SPI_SST25LF_COMMAND_WRITE_DISABLE 0x04\r
+#define SPI_SST25LF_COMMAND_READ_STATUS   0x05\r
+#define SPI_SST25LF_COMMAND_WRITE_ENABLE  0x06\r
+#define SPI_SST25LF_COMMAND_READ_ID       0xAB\r
+#define SPI_SST25LF_COMMAND_WRITE_S_EN    0x50\r
+#define SPI_SST25LF_COMMAND_WRITE_S       0x01\r
+\r
+#define SPI_PMC25LV_COMMAND_WRITE         0x02\r
+#define SPI_PMC25LV_COMMAND_READ          0x03\r
+#define SPI_PMC25LV_COMMAND_ERASE         0xD7\r
+#define SPI_PMC25LV_COMMAND_WRITE_DISABLE 0x04\r
+#define SPI_PMC25LV_COMMAND_READ_STATUS   0x05\r
+#define SPI_PMC25LV_COMMAND_WRITE_ENABLE  0x06\r
+#define SPI_PMC25LV_COMMAND_READ_ID       0xAB\r
+#define SPI_PMC25LV_COMMAND_WRITE_S_EN    0x06\r
+#define SPI_PMC25LV_COMMAND_WRITE_S       0x01\r
+\r
+#define SPI_AT26DF_COMMAND_WRITE         0x02\r
+#define SPI_AT26DF_COMMAND_READ          0x03\r
+#define SPI_AT26DF_COMMAND_ERASE         0x20\r
+#define SPI_AT26DF_COMMAND_WRITE_DISABLE 0x00\r
+#define SPI_AT26DF_COMMAND_READ_STATUS   0x05\r
+#define SPI_AT26DF_COMMAND_WRITE_ENABLE  0x00\r
+#define SPI_AT26DF_COMMAND_READ_ID       0x9F\r
+#define SPI_AT26DF_COMMAND_WRITE_S_EN    0x00\r
+#define SPI_AT26DF_COMMAND_WRITE_S       0x00\r
+\r
+#define SPI_AT26F_COMMAND_WRITE          0x02\r
+#define SPI_AT26F_COMMAND_READ           0x03\r
+#define SPI_AT26F_COMMAND_ERASE          0x20\r
+#define SPI_AT26F_COMMAND_WRITE_DISABLE  0x04\r
+#define SPI_AT26F_COMMAND_READ_STATUS    0x05\r
+#define SPI_AT26F_COMMAND_WRITE_ENABLE   0x06\r
+#define SPI_AT26F_COMMAND_JEDEC_ID       0x9F\r
+#define SPI_AT26F_COMMAND_WRITE_S_EN     0x00\r
+#define SPI_AT26F_COMMAND_WRITE_S        0x01\r
+#define SPI_AT26F_COMMAND_WRITE_UNPROTECT 0x39\r
+\r
+#define SPI_SST25VF_COMMAND_WRITE         0x02\r
+#define SPI_SST25VF_COMMAND_READ          0x03\r
+#define SPI_SST25VF_COMMAND_ERASE         0x20\r
+#define SPI_SST25VF_COMMAND_WRITE_DISABLE 0x04\r
+#define SPI_SST25VF_COMMAND_READ_STATUS   0x05\r
+#define SPI_SST25VF_COMMAND_WRITE_ENABLE  0x06\r
+#define SPI_SST25VF_COMMAND_READ_ID       0xAB\r
+#define SPI_SST25VF_COMMAND_JEDEC_ID      0x9F\r
+#define SPI_SST25VF_COMMAND_WRITE_S_EN    0x50\r
+#define SPI_SST25VF_COMMAND_WRITE_S       0x01\r
+\r
+#define SPI_STM25PE_COMMAND_WRITE         0x02\r
+#define SPI_STM25PE_COMMAND_READ          0x03\r
+#define SPI_STM25PE_COMMAND_ERASE         0xDB\r
+#define SPI_STM25PE_COMMAND_WRITE_DISABLE 0x04\r
+#define SPI_STM25PE_COMMAND_READ_STATUS   0x05\r
+#define SPI_STM25PE_COMMAND_WRITE_ENABLE  0x06\r
+#define SPI_STM25PE_COMMAND_JEDEC_ID      0x9F\r
+\r
+#define SPI_WinbondW25X_COMMAND_WRITE_S      0x01\r
+#define SPI_WinbondW25X_COMMAND_WRITE        0x02\r
+#define SPI_WinbondW25X_COMMAND_READ         0x03\r
+#define SPI_WinbondW25X_COMMAND_READ_STATUS  0x05\r
+#define SPI_WinbondW25X_COMMAND_ERASE_S      0x20\r
+#define SPI_WinbondW25X_COMMAND_WRITE_ENABLE 0x06\r
+#define SPI_WinbondW25X_COMMAND_JEDEC_ID     0x9F\r
+\r
+//\r
+// SPI default opcode slots\r
+//\r
+#define SPI_OPCODE_WRITE_INDEX           0\r
+#define SPI_OPCODE_READ_INDEX            1\r
+#define SPI_OPCODE_ERASE_INDEX           2\r
+#define SPI_OPCODE_READ_S_INDEX          3\r
+#define SPI_OPCODE_READ_ID_INDEX         4\r
+#define SPI_OPCODE_WRITE_S_INDEX         6\r
+#define SPI_OPCODE_WRITE_UNPROTECT_INDEX 7\r
+\r
+#define SPI_PREFIX_WRITE_S_EN 1\r
+#define SPI_PREFIX_WRITE_EN   0\r
+\r
+//\r
+// Atmel AT26F00x\r
+//\r
+#define B_AT26F_STS_REG_SPRL  0x80\r
+#define B_AT26F_STS_REG_SWP   0x0C\r
+\r
+//\r
+// Block lock bit definitions:\r
+//\r
+#define READ_LOCK   0x04\r
+#define LOCK_DOWN   0x02\r
+#define WRITE_LOCK  0x01\r
+#define FULL_ACCESS 0x00\r
+\r
+//\r
+// Function Prototypes\r
+//\r
+EFI_STATUS\r
+FlashGetNextBlock (\r
+  IN UINTN*                               Key,\r
+  OUT EFI_PHYSICAL_ADDRESS*               BlockAddress,\r
+  OUT UINTN*                              BlockSize\r
+  );\r
+\r
+EFI_STATUS\r
+FlashGetSize (\r
+  OUT UINTN* Size\r
+  );\r
+\r
+EFI_STATUS\r
+FlashGetUniformBlockSize (\r
+  OUT UINTN* Size\r
+  );\r
+\r
+EFI_STATUS\r
+FlashEraseWithNoTopSwapping (\r
+  IN  UINT8 *BaseAddress,\r
+  IN  UINTN NumBytes\r
+  );\r
+\r
+EFI_STATUS\r
+FlashErase (\r
+  IN  UINT8                 *BaseAddress,\r
+  IN  UINTN                 NumBytes\r
+  );\r
+\r
+EFI_STATUS\r
+FlashWriteWithNoTopSwapping (\r
+  IN UINT8*                 DstBufferPtr,\r
+  IN UINT8*                 SrcBufferPtr,\r
+  IN UINTN                  NumBytes\r
+  );\r
+\r
+EFI_STATUS\r
+FlashWrite (\r
+  IN  UINT8                 *DstBufferPtr,\r
+  IN  UINT8                 *SrcBufferPtr,\r
+  IN  UINTN                 NumBytes\r
+  );\r
+\r
+EFI_STATUS\r
+FlashReadWithNoTopSwapping (\r
+  IN  UINT8                 *BaseAddress,\r
+  IN  UINT8                 *DstBufferPtr,\r
+  IN  UINTN                 NumBytes\r
+  );\r
+\r
+EFI_STATUS\r
+FlashRead (\r
+  IN  UINT8                 *BaseAddress,\r
+  IN  UINT8                 *DstBufferPtr,\r
+  IN  UINTN                 NumBytes\r
+  );\r
+\r
+EFI_STATUS\r
+FlashLockWithNoTopSwapping (\r
+  IN UINT8*                BaseAddress,\r
+  IN UINTN                 NumBytes,\r
+  IN UINT8                 LockState\r
+  );\r
+\r
+EFI_STATUS\r
+FlashLock(\r
+  IN  UINT8                 *BaseAddress,\r
+  IN  UINTN                 NumBytes,\r
+  IN  UINT8                 LockState\r
+  );\r
+\r
+EFI_STATUS\r
+CheckIfErased(\r
+  IN  UINT8       *DstBufferPtr,\r
+  IN  UINTN       NumBytes\r
+  );\r
+\r
+EFI_STATUS\r
+CheckIfFlashIsReadyForWrite (\r
+  IN  UINT8       *DstBufferPtr,\r
+  IN  UINT8       *SrcBufferPtr,\r
+  IN  UINTN       NumBytes\r
+  );\r

diff --git a/Vlv2TbltDevicePkg/Include/Library/FlashDeviceLib.h b/Vlv2TbltDevicePkg/Include/Library/FlashDeviceLib.h
new file mode 100644 (file)
index 0000000..bddc1f8
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Include/Library/FlashDeviceLib.h
@@ -0,0 +1,127 @@
+/*++\r
+\r
+  Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+\r
+  Flash device library class header file.\r
+\r
+  Flash Device Library common type, MACRO and API definition. The basic idea for\r
+  this library is to provide API to abstract the different between flash\r
+  technology (SPI, FWH etc..), flash controller (SPI host controller on\r
+  ICH, MMIO type access for FWH), flash chip (programming command, method\r
+  of status checking). This library class can be consumed by drivers or applications\r
+  such as Firmware Volume Block driver, Flash Update application. These driver\r
+  can be written in a generic manner so that they are more easy to be\r
+  ported to other platforms.\r
+\r
+  This library can be build on a set of APIs which can touch flash controller, flash\r
+  chip directly for a platform with simple flash device configuration.\r
+\r
+  For a platform with complex flash device configuration, this library can be built\r
+  on the Flash Device Operate Library. Please see the header file for that library\r
+  class for detailed usage.\r
+\r
+**/\r
+\r
+#ifndef __FLASHDEVICE_LIB_H__\r
+#define __FLASHDEVICE_LIB_H__\r
+\r
+/**\r
+  Read NumBytes bytes of data from the address specified by\r
+  PAddress into Buffer.\r
+\r
+  @param[in]      PAddress    The starting physical address of the read.\r
+  @param[in,out]  NumBytes    On input, the number of bytes to read. On output, the number\r
+                              of bytes actually read.\r
+  @param[out]     Buffer      The destination data buffer for the read.\r
+\r
+  @retval EFI_SUCCESS.        Opertion is successful.\r
+  @retval EFI_DEVICE_ERROR    If there is any device errors.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+LibFvbFlashDeviceRead (\r
+  IN      UINTN                           PAddress,\r
+  IN  OUT UINTN                           *NumBytes,\r
+      OUT UINT8                           *Buffer\r
+  );\r
+\r
+/**\r
+  Write NumBytes bytes of data from Buffer to the address specified by\r
+  PAddresss.\r
+\r
+  @param[in]      PAddress The starting physical address of the write.\r
+  @param[in,out]  NumBytes On input, the number of bytes to write. On output,\r
+                           the actual number of bytes written.\r
+  @param[in]      Buffer   The source data buffer for the write.\r
+\r
+  @retval EFI_SUCCESS.            Opertion is successful.\r
+  @retval EFI_DEVICE_ERROR        If there is any device errors.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+LibFvbFlashDeviceWrite (\r
+  IN        UINTN                           PAddress,\r
+  IN OUT    UINTN                           *NumBytes,\r
+  IN        UINT8                           *Buffer\r
+  );\r
+\r
+/**\r
+  Erase the block staring at PAddress.\r
+\r
+  @param[in]  PAddress The starting physical address of the region to be erased.\r
+  @param[in]  LbaLength   The length of the region to be erased. This parameter is necessary\r
+                       as the physical block size on a flash device could be different than\r
+                       the logical block size of Firmware Volume Block protocol. Erase on\r
+                       flash chip is always performed block by block. Therefore, the ERASE\r
+                       operation to a logical block is converted a number of ERASE operation\r
+                       (or a partial erase) on the hardware.\r
+\r
+  @retval EFI_SUCCESS.            Opertion is successful.\r
+  @retval EFI_DEVICE_ERROR        If there is any device errors.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+LibFvbFlashDeviceBlockErase (\r
+  IN    UINTN                      PAddress,\r
+  IN    UINTN                      LbaLength\r
+);\r
+\r
+/**\r
+  Lock or unlock the block staring at PAddress.\r
+\r
+  @param[in]  PAddress The starting physical address of region to be (un)locked.\r
+  @param[in]  LbaLength   The length of the region to be (un)locked. This parameter is necessary\r
+                       as the physical block size on a flash device could be different than\r
+                       the logical block size of Firmware Volume Block protocol. (Un)Lock on\r
+                       flash chip is always performed block by block. Therefore, the (Un)Lock\r
+                       operation to a logical block is converted a number of (Un)Lock operation\r
+                       (or a partial erase) on the hardware.\r
+  @param[in]  Lock     TRUE to lock. FALSE to unlock.\r
+\r
+  @retval EFI_SUCCESS. Opertion is successful.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+LibFvbFlashDeviceBlockLock (\r
+  IN    UINTN                          PAddress,\r
+  IN    UINTN                          LbaLength,\r
+  IN    BOOLEAN                        Lock\r
+);\r
+\r
+#endif\r
+\r
+\r

diff --git a/Vlv2TbltDevicePkg/Include/Library/I2cMmioConfigLib.h b/Vlv2TbltDevicePkg/Include/Library/I2cMmioConfigLib.h
new file mode 100644 (file)
index 0000000..b1f9147
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Include/Library/I2cMmioConfigLib.h
@@ -0,0 +1,28 @@
+/*++\r
+\r
+  Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+**/\r
+\r
+#ifndef __MMIO_CONFIG_LIB_H__\r
+#define __MMIO_CONFIG_LIB_H__\r
+\r
+#include <Protocol/MmioDevice.h>\r
+\r
+///\r
+/// Declare the memory mapped I/O devices assocaited with the\r
+/// board.\r
+///\r
+extern CONST EFI_MMIO_DEVICE_PROTOCOL gMmioDeviceList [ ];\r
+extern CONST UINTN gMmioDeviceCount;\r
+\r
+#endif  //  __MMIO_CONFIG_LIB_H__\r

diff --git a/Vlv2TbltDevicePkg/Include/Library/I2cPort_platform.h b/Vlv2TbltDevicePkg/Include/Library/I2cPort_platform.h
new file mode 100644 (file)
index 0000000..f52352f
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Include/Library/I2cPort_platform.h
@@ -0,0 +1,31 @@
+/*++\r
+\r
+  Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+**/\r
+\r
+#ifndef _I2C_PORT_H\r
+#define _I2C_PORT_H\r
+\r
+//\r
+//  Types\r
+//\r
+\r
+//\r
+// Context passed from platform (board) layer to the I2C port driver.\r
+//\r
+typedef struct {\r
+  EFI_PHYSICAL_ADDRESS BaseAddress;\r
+  UINT32 InputFrequencyHertz;\r
+} I2C_PIO_PLATFORM_CONTEXT;\r
+\r
+#endif  //  _I2C_PORT_A0_H\r

diff --git a/Vlv2TbltDevicePkg/Include/Library/PlatformFsaLib.h b/Vlv2TbltDevicePkg/Include/Library/PlatformFsaLib.h
new file mode 100644 (file)
index 0000000..3ff3fb1
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Include/Library/PlatformFsaLib.h
@@ -0,0 +1,55 @@
+/*++\r
+\r
+  Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+--*/\r
+\r
+#ifndef _FSA_LIB_H\r
+#define _FSA_LIB_H\r
+#include <Uefi.h>\r
+#include <Uefi/UefiSpec.h>\r
+\r
+#define FSA_REG_DEVID           0x1\r
+#define FSA_REG_CTRL            0x2\r
+#define FSA_REG_INTR            0x3\r
+#define FSA_REG_INTR_MSK        0x5\r
+#define FSA_REG_RESISTOR_CODE   0x7\r
+#define FSA_REG_TIMING_SET      0x8\r
+#define FSA_REG_STATUS          0x9\r
+#define FSA_REG_DEV_TYPE        0xA\r
+#define FSA_REG_DAC_SAR         0xB\r
+#define FSA_REG_MANUAL_SW       0x13\r
+#define FSA_REG_MANUAL_CHG_CTRL 0x14\r
+\r
+extern\r
+EFI_STATUS\r
+EFIAPI\r
+FsaUsbDeviceMode (\r
+  VOID\r
+);\r
+\r
+\r
+extern\r
+EFI_STATUS\r
+EFIAPI\r
+DisableFsaTimerHandler (\r
+  VOID\r
+);\r
+\r
+extern\r
+EFI_STATUS\r
+EFIAPI\r
+FSAInit (\r
+ IN UINT32 FFRDVer\r
+);\r
+\r
+#endif\r

diff --git a/Vlv2TbltDevicePkg/Include/Library/PlatformFspLib.h b/Vlv2TbltDevicePkg/Include/Library/PlatformFspLib.h
new file mode 100644 (file)
index 0000000..2352514
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Include/Library/PlatformFspLib.h
@@ -0,0 +1,28 @@
+/*++\r
+\r
+  Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+--*/\r
+\r
+#ifndef _PLATFORM_FSP_LIB_H\r
+#define _PLATFORM_FSP_LIB_H\r
+#include <Base.h>\r
+#include <Uefi.h>\r
+\r
+extern\r
+EFI_STATUS\r
+PlatformHobCreateFromFsp (\r
+  IN CONST EFI_PEI_SERVICES     **PeiServices,\r
+  VOID                          *HobList\r
+  );\r
+\r
+#endif\r

diff --git a/Vlv2TbltDevicePkg/Include/Library/SpiFlash.H b/Vlv2TbltDevicePkg/Include/Library/SpiFlash.H
new file mode 100644 (file)
index 0000000..9d1e898
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Include/Library/SpiFlash.H
@@ -0,0 +1,244 @@
+/*++\r
+\r
+  Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+**/\r
+\r
+#ifndef _SPIFlash_H_\r
+#define _SPIFlash_H_\r
+\r
+#include <Protocol/Spi.h>\r
+\r
+//EFI_STATUS SpiFlashLock(BOOLEAN Lock);\r
+//EFI_STATUS SpiFlashInit(void);\r
+\r
+typedef enum {\r
+  EnumSpiFlashW25Q64,\r
+  EnumSpiFlashAT25DF321A,\r
+  EnumSpiFlashAT26DF321,\r
+  EnumSpiFlashAT25DF641,\r
+  EnumSpiFlashW25Q16,\r
+  EnumSpiFlashW25Q32,\r
+  EnumSpiFlashW25X32,\r
+  EnumSpiFlashW25X64,\r
+  EnumSpiFlashW25Q128,\r
+  EnumSpiFlashMX25L16,\r
+  EnumSpiFlashMX25L32,\r
+  EnumSpiFlashMX25L64,\r
+  EnumSpiFlashMX25L128,\r
+  EnumSpiFlashMX25U6435F,\r
+  EnumSpiFlashSST25VF016B,\r
+  EnumSpiFlashSST25VF064C,\r
+  EnumSpiFlashN25Q064,\r
+  EnumSpiFlashM25PX16,\r
+  EnumSpiFlashN25Q032,\r
+  EnumSpiFlashM25PX32,\r
+  EnumSpiFlashM25PX64,\r
+  EnumSpiFlashN25Q128,\r
+  EnumSpiFlashEN25Q16,\r
+  EnumSpiFlashEN25Q32,\r
+  EnumSpiFlashEN25Q64,\r
+  EnumSpiFlashEN25Q128,\r
+  EnumSpiFlashA25L016,\r
+  EnumSpiFlashMax\r
+} SPI_FLASH_TYPES_SUPPORTED;\r
+\r
+//\r
+// Serial Flash VendorId and DeviceId\r
+//\r
+#define SF_VENDOR_ID_ATMEL          0x1F\r
+#define SF_DEVICE_ID0_AT26DF321     0x47\r
+#define SF_DEVICE_ID1_AT26DF321     0x00\r
+#define SF_DEVICE_ID0_AT25DF321A    0x47\r
+#define SF_DEVICE_ID1_AT25DF321A    0x01\r
+#define SF_DEVICE_ID0_AT25DF641     0x48\r
+#define SF_DEVICE_ID1_AT25DF641     0x00\r
+\r
+#define SF_VENDOR_ID_WINBOND        0xEF\r
+#define SF_DEVICE_ID0_W25XXX        0x30\r
+#define SF_DEVICE_ID1_W25X32        0x16\r
+#define SF_DEVICE_ID1_W25X64        0x17\r
+#define SF_DEVICE_ID0_W25QXX        0x60\r
+#define SF_DEVICE_ID1_W25Q16        0x15\r
+#define SF_DEVICE_ID1_W25Q32        0x16\r
+#define SF_DEVICE_ID1_W25Q64        0x17\r
+#define SF_DEVICE_ID1_W25Q128       0x18\r
+\r
+#define        SF_VENDOR_ID_MACRONIX       0xC2\r
+#define        SF_DEVICE_ID0_MX25LXX       0x20\r
+#define        SF_DEVICE_ID1_MX25L16       0x15\r
+#define        SF_DEVICE_ID1_MX25L32       0x16\r
+#define        SF_DEVICE_ID1_MX25L64       0x17\r
+#define        SF_DEVICE_ID1_MX25L128      0x18\r
+#define SF_DEVICE_ID0_MX25UXX       0x25\r
+#define SF_DEVICE_ID1_MX25U6435F    0x37\r
+\r
+#define        SF_VENDOR_ID_NUMONYX        0x20\r
+#define SF_DEVICE_ID0_N25Q064       0xBB\r
+#define SF_DEVICE_ID1_N25Q064       0x17\r
+#define        SF_DEVICE_ID0_M25PXXX       0x71\r
+#define        SF_DEVICE_ID0_N25QXXX       0xBA\r
+#define        SF_DEVICE_ID1_M25PX16       0x15\r
+#define        SF_DEVICE_ID1_N25Q032       0x16\r
+#define        SF_DEVICE_ID1_M25PX32       0x16\r
+#define        SF_DEVICE_ID1_M25PX64       0x17\r
+#define        SF_DEVICE_ID1_N25Q128       0x18\r
+\r
+#define SF_VENDOR_ID_SST            0xBF\r
+#define SF_DEVICE_ID0_SST25VF0XXX   0x25\r
+#define SF_DEVICE_ID1_SST25VF016B   0x41\r
+#define SF_DEVICE_ID1_SST25VF064C   0x4B\r
+\r
+#define SF_VENDOR_ID_EON            0x1C\r
+#define SF_DEVICE_ID0_EN25QXX       0x30\r
+#define SF_DEVICE_ID1_EN25Q16       0x15\r
+#define SF_DEVICE_ID1_EN25Q32       0x16\r
+#define SF_DEVICE_ID1_EN25Q64       0x17\r
+#define SF_DEVICE_ID1_EN25Q128      0x18\r
+\r
+#define SF_VENDOR_ID_AMIC           0x37\r
+#define SF_DEVICE_ID0_A25L016       0x30\r
+#define SF_DEVICE_ID1_A25L016       0x15\r
+\r
+#define ATMEL_AT26DF321_SIZE        0x00400000\r
+#define ATMEL_AT25DF321A_SIZE       0x00400000\r
+#define ATMEL_AT25DF641_SIZE        0x00800000\r
+#define WINBOND_W25X32_SIZE         0x00400000\r
+#define WINBOND_W25X64_SIZE         0x00800000\r
+#define WINBOND_W25Q16_SIZE         0x00200000\r
+#define WINBOND_W25Q32_SIZE         0x00400000\r
+#define WINBOND_W25Q64_SIZE         0x00800000\r
+#define WINBOND_W25Q128_SIZE        0x01000000\r
+#define SST_SST25VF016B_SIZE        0x00200000\r
+#define SST_SST25VF064C_SIZE        0x00800000\r
+#define MACRONIX_MX25L16_SIZE       0x00200000\r
+#define MACRONIX_MX25L32_SIZE       0x00400000\r
+#define MACRONIX_MX25L64_SIZE       0x00800000\r
+#define MACRONIX_MX25U64_SIZE       0x00800000\r
+#define MACRONIX_MX25L128_SIZE      0x01000000\r
+#define NUMONYX_M25PX16_SIZE        0x00400000\r
+#define NUMONYX_N25Q032_SIZE        0x00400000\r
+#define NUMONYX_M25PX32_SIZE        0x00400000\r
+#define NUMONYX_M25PX64_SIZE        0x00800000\r
+#define NUMONYX_N25Q064_SIZE        0x00800000\r
+#define NUMONYX_N25Q128_SIZE        0x01000000\r
+#define EON_EN25Q16_SIZE            0x00200000\r
+#define EON_EN25Q32_SIZE            0x00400000\r
+#define EON_EN25Q64_SIZE            0x00800000\r
+#define EON_EN25Q128_SIZE           0x01000000\r
+#define AMIC_A25L16_SIZE            0x00200000\r
+\r
+#define SF_VENDOR_ID_SST           0xBF\r
+#define SF_DEVICE_ID0_25LF080A     0x25\r
+#define SF_DEVICE_ID1_25LF080A     0x8E\r
+#define SF_DEVICE_ID0_25VF016B     0x25\r
+#define SF_DEVICE_ID1_25VF016B     0x41\r
+\r
+#define SF_VENDOR_ID_ATMEL         0x1F\r
+#define SF_DEVICE_ID0_AT26DF321    0x47\r
+#define SF_DEVICE_ID1_AT26DF321    0x00\r
+\r
+#define SF_VENDOR_ID_STM           0x20\r
+#define SF_DEVICE_ID0_M25P32       0x20\r
+#define SF_DEVICE_ID1_M25P32       0x16\r
+\r
+#define SF_VENDOR_ID_WINBOND       0xEF\r
+#define SF_DEVICE_ID0_W25XXX       0x30\r
+#define SF_DEVICE_ID0_W25QXX       0x60\r
+#define SF_DEVICE_ID1_W25X80       0x14\r
+#define SF_DEVICE_ID1_W25X16       0x15\r
+#define SF_DEVICE_ID1_W25X32       0x16\r
+#define SF_DEVICE_ID1_W25X64       0x17\r
+\r
+#define        SF_VENDOR_ID_MX                         0xC2\r
+#define        SF_DEVICE_ID0_25L1605A          0x20\r
+#define        SF_DEVICE_ID1_25L1605A          0x15\r
+\r
+#define SF_VENDOR_ID_NUMONYX        0x20\r
+#define SF_DEVICE_ID0_M25PX16       0x71\r
+#define SF_DEVICE_ID1_M25PX16       0x15\r
+\r
+#define SST_25LF080A_SIZE          0x00100000\r
+#define SST_25LF016B_SIZE          0x00200000\r
+#define ATMEL_AT26DF321_SIZE       0x00400000\r
+#define STM_M25P32_SIZE            0x00400000\r
+#define WINBOND_W25X80_SIZE        0x00100000\r
+#define WINBOND_W25X16_SIZE        0x00200000\r
+#define WINBOND_W25X32_SIZE        0x00400000\r
+#define WINBOND_W25X64_SIZE        0x00800000\r
+#define MX_25L1605A_SIZE           0x00200000\r
+\r
+//\r
+// Physical Sector Size on the Serial Flash device\r
+//\r
+#define SF_SECTOR_SIZE    0x1000\r
+#define SF_BLOCK_SIZE     0x8000\r
+\r
+//\r
+// Serial Flash Status Register definitions\r
+//\r
+#define SF_SR_BUSY        0x01      // Indicates if internal write operation is in progress\r
+#define SF_SR_WEL         0x02      // Indicates if device is memory write enabled\r
+#define SF_SR_BP0         0x04      // Block protection bit 0\r
+#define SF_SR_BP1         0x08      // Block protection bit 1\r
+#define SF_SR_BP2         0x10      // Block protection bit 2\r
+#define SF_SR_BP3         0x20      // Block protection bit 3\r
+#define SF_SR_WPE         0x3C      // Enable write protection on all blocks\r
+#define SF_SR_AAI         0x40      // Auto Address Increment Programming status\r
+#define SF_SR_BPL         0x80      // Block protection lock-down\r
+\r
+//\r
+// Operation Instruction definitions for  the Serial Flash Device\r
+//\r
+#define SF_INST_WRSR            0x01     // Write Status Register\r
+#define SF_INST_PROG            0x02     // Byte Program\r
+#define SF_INST_READ            0x03     // Read\r
+#define SF_INST_WRDI            0x04     // Write Disable\r
+#define SF_INST_RDSR            0x05     // Read Status Register\r
+#define SF_INST_WREN            0x06     // Write Enable\r
+#define SF_INST_HS_READ         0x0B     // High-speed Read\r
+#define SF_INST_SERASE          0x20     // Sector Erase (4KB)\r
+#define SF_INST_BERASE          0x52     // Block Erase (32KB)\r
+#define SF_INST_64KB_ERASE      0xD8     // Block Erase (64KB)\r
+#define SF_INST_EWSR            0x50     // Enable Write Status Register\r
+#define SF_INST_READ_ID         0xAB     // Read ID\r
+#define SF_INST_JEDEC_READ_ID   0x9F     // JEDEC Read ID\r
+#define SF_INST_DOFR            0x3B     // Dual Output Fast Read\r
+#define SF_INST_SFDP            0x5A     // Serial Flash Discovery Parameters\r
+\r
+#define SECTOR_SIZE_4KB        0x1000       // Common 4kBytes sector size\r
+#define SECTOR_SIZE_64KB       0x10000      // Common 64kBytes sector size\r
+#define BLOCK_SIZE_64KB        0x00010000   // Common 64kBytes block size\r
+#define MAX_FWH_SIZE           0x00100000   // 8Mbit (Note that this can also be used for the 4Mbit )\r
+\r
+//\r
+// Prefix Opcode Index on the host SPI controller\r
+//\r
+typedef enum {\r
+  SPI_WREN,             // Prefix Opcode 0: Write Enable\r
+  SPI_EWSR,             // Prefix Opcode 1: Enable Write Status Register\r
+} PREFIX_OPCODE_INDEX;\r
+\r
+//\r
+// Opcode Menu Index on the host SPI controller\r
+//\r
+typedef enum {\r
+  SPI_READ_ID,        // Opcode 0: READ ID, Read cycle with address\r
+  SPI_READ,           // Opcode 1: READ, Read cycle with address\r
+  SPI_RDSR,           // Opcode 2: Read Status Register, No address\r
+  SPI_WRDI_SFDP,      // Opcode 3: Write Disable or Discovery Parameters, No address\r
+  SPI_SERASE,         // Opcode 4: Sector Erase (4KB), Write cycle with address\r
+  SPI_BERASE,         // Opcode 5: Block Erase (32KB), Write cycle with address\r
+  SPI_PROG,           // Opcode 6: Byte Program, Write cycle with address\r
+  SPI_WRSR,           // Opcode 7: Write Status Register, No address\r
+} SPI_OPCODE_INDEX;\r
+\r
+#endif\r

diff --git a/Vlv2TbltDevicePkg/Include/Library/StallSmmLib.h b/Vlv2TbltDevicePkg/Include/Library/StallSmmLib.h
new file mode 100644 (file)
index 0000000..364dc87
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Include/Library/StallSmmLib.h
@@ -0,0 +1,45 @@
+/*++\r
+\r
+Copyright (c)  1999  - 2014, Intel Corporation. All rights reserved\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+Module Name:\r
+\r
+  SmmStallLib.h\r
+\r
+Abstract:\r
+\r
+  This library provides SMM functions for Stall.\r
+  These can be used to save size and simplify code.\r
+  All contents must be runtime and SMM safe.\r
+\r
+--*/\r
+\r
+#ifndef _SMM_STALL_LIB_H_\r
+#define _SMM_STALL_LIB_H_\r
+#include "PiDxe.h"\r
+#include "Pi/PiSmmCis.h"\r
+extern EFI_SMM_SYSTEM_TABLE2  *mSmst;\r
+\r
+/**\r
+  Delay for at least the request number of microseconds\r
+\r
+  @param[in] Microseconds  Number of microseconds to delay.\r
+\r
+  @retval None\r
+\r
+**/\r
+VOID\r
+SmmStall (\r
+  IN  UINTN   Microseconds\r
+  );\r
+\r
+#endif\r

diff --git a/Vlv2TbltDevicePkg/Include/Library/UsbDeviceModeLib.h b/Vlv2TbltDevicePkg/Include/Library/UsbDeviceModeLib.h
new file mode 100644 (file)
index 0000000..4af713e
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Include/Library/UsbDeviceModeLib.h
@@ -0,0 +1,186 @@
+/*++\r
+\r
+  Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+**/\r
+\r
+#ifndef __BASE_USBDEVICEMODE_LIB_H__\r
+#define __BASE_USBDEVICEMODE_LIB_H__\r
+\r
+#pragma pack(1)\r
+typedef struct {\r
+    UINT8  bLength;\r
+    UINT8  bDescriptorType;\r
+    UINT8  bMaxBurst;\r
+    UINT8  bmAttributes;\r
+    UINT16 wBytesPerInterval;\r
+} endpointCompanionDescriptor;\r
+#pragma pack()\r
+\r
+#pragma pack(1)\r
+typedef struct {\r
+    UINT8  bLength;\r
+    UINT8  bDescriptorType;\r
+    UINT8  bEndpointAddress;\r
+    UINT8  bmAttributes;\r
+    UINT16 wMaxPacketSize;\r
+    UINT8  bInterval;\r
+} endpointDescriptor;\r
+#pragma pack()\r
+\r
+typedef struct {\r
+    endpointDescriptor          *pEpDesc;\r
+    endpointCompanionDescriptor *pEpCompDesc;\r
+} USB_DEV_EP_INFO;    //usbdEpInfo;\r
+\r
+typedef struct {\r
+    VOID        *pBuf;\r
+    UINT32    dataLen;\r
+} USBD_IO_INFO;\r
+\r
+typedef struct {\r
+    USBD_IO_INFO     ioInfo;\r
+    USB_DEV_EP_INFO  epInfo;\r
+} USBD_IO_REQ;\r
+\r
+UINTN\r
+EFIAPI\r
+usbdInitDCI (\r
+  VOID\r
+  );\r
+\r
+BOOLEAN\r
+EFIAPI\r
+fbInit (\r
+  OUT  VOID  *pParams\r
+  );\r
+\r
+BOOLEAN\r
+EFIAPI\r
+fbDeinit (\r
+  VOID\r
+  );\r
+\r
+BOOLEAN\r
+EFIAPI\r
+fbStart (\r
+  VOID\r
+  );\r
+\r
+BOOLEAN\r
+EFIAPI\r
+fbStop (\r
+  VOID\r
+  );\r
+\r
+BOOLEAN\r
+EFIAPI\r
+usbdSetMmioBar (\r
+  UINT32 mmioBar\r
+  );\r
+\r
+BOOLEAN\r
+EFIAPI\r
+udciDeinit (\r
+  VOID    *pUdciHndl,\r
+  UINT32  flags\r
+  );\r
+\r
+BOOLEAN\r
+EFIAPI\r
+udciIsr (\r
+  VOID    *pUdciHndl\r
+  );\r
+\r
+BOOLEAN\r
+EFIAPI\r
+udciConnect (\r
+  VOID    *pUdciHndl\r
+  );\r
+\r
+BOOLEAN\r
+EFIAPI\r
+udciDisconnect (\r
+  VOID    *pUdciHndl\r
+  );\r
+\r
+BOOLEAN\r
+EFIAPI\r
+udciSetAddress (\r
+  VOID    *pUdciHndl,\r
+  UINT8   address\r
+  );\r
+\r
+BOOLEAN\r
+EFIAPI\r
+udciInitEp (\r
+  VOID            *pUdciHndl,\r
+  USB_DEV_EP_INFO *pEpInfo\r
+  );\r
+\r
+BOOLEAN\r
+EFIAPI\r
+udciEnableEp (\r
+  VOID            *pUdciHndl,\r
+  USB_DEV_EP_INFO *pEpInfo\r
+  );\r
+\r
+BOOLEAN\r
+EFIAPI\r
+udciDisableEp (\r
+  VOID            *pUdciHndl,\r
+  USB_DEV_EP_INFO *pEpInfo\r
+  );\r
+\r
+BOOLEAN\r
+EFIAPI\r
+udciStallEp (\r
+  VOID            *pUdciHndl,\r
+  USB_DEV_EP_INFO *pEpInfo\r
+  );\r
+\r
+BOOLEAN\r
+EFIAPI\r
+udciClearStallEp (\r
+  VOID            *pUdciHndl,\r
+  USB_DEV_EP_INFO *pEpInfo\r
+  );\r
+\r
+\r
+BOOLEAN\r
+EFIAPI\r
+udciEp0TxStatus (\r
+  VOID            *pUdciHndl\r
+  );\r
+\r
+\r
+BOOLEAN\r
+EFIAPI\r
+udciEpTxData (\r
+  VOID        *pUdciHndl,\r
+  USBD_IO_REQ *pIoReq\r
+  );\r
+\r
+BOOLEAN\r
+EFIAPI\r
+udciEpRxData (\r
+  VOID        *pUdciHndl,\r
+  USBD_IO_REQ *pIoReq\r
+  );\r
+\r
+BOOLEAN\r
+EFIAPI\r
+udciRegisterCallbacks (\r
+  VOID            *pUdciHndl\r
+  );\r
+\r
+#endif\r

diff --git a/Vlv2TbltDevicePkg/Include/Mcfg.h b/Vlv2TbltDevicePkg/Include/Mcfg.h
new file mode 100644 (file)
index 0000000..50dfc70
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Include/Mcfg.h
@@ -0,0 +1,74 @@
+/*++\r
+\r
+  Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+\r
+Module Name:\r
+\r
+  Mcfg.h\r
+\r
+Abstract:\r
+\r
+  ACPI Memory mapped configuration space base address Description Table\r
+  implementation, based on PCI Firmware Specification Revision 3.0 final draft,\r
+  downloadable at http://www.pcisig.com/home\r
+\r
+**/\r
+\r
+#ifndef _MCFG_H_\r
+#define _MCFG_H_\r
+\r
+//\r
+// Statements that include other files\r
+//\r
+#include <IndustryStandard/Acpi20.h>\r
+#include "McfgTable.h"\r
+#include "Platform.h"\r
+\r
+//\r
+// "MCFG" Static Resource Affinity Table\r
+//\r
+#define EFI_ACPI_3_0_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE_SIGNATURE 0x4746434D\r
+\r
+//\r
+// MCFG Definitions, see specification for details.\r
+//\r
+#define EFI_ACPI_OEM_MCFG_REVISION  0x00000001\r
+\r
+//\r
+// Define the number of each table type.\r
+// This is where the table layout is modified.\r
+//\r
+#define EFI_ACPI_MEMORY_MAPPED_ENHANCED_CONFIGURATION_BASE_ADDRESS_STRUCTURE_COUNT  1\r
+\r
+//\r
+// MCFG Table definition.  The table must be defined in a platform\r
+// specific manner.\r
+//\r
+//\r
+// Ensure proper structure formats\r
+//\r
+#pragma pack(1)\r
+\r
+typedef struct {\r
+  EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE_HEADER        Header;\r
+\r
+#if EFI_ACPI_MEMORY_MAPPED_ENHANCED_CONFIGURATION_BASE_ADDRESS_STRUCTURE_COUNT > 0\r
+  EFI_ACPI_MEMORY_MAPPED_ENHANCED_CONFIGURATION_BASE_ADDRESS_STRUCTURE  Segment[\r
+    EFI_ACPI_MEMORY_MAPPED_ENHANCED_CONFIGURATION_BASE_ADDRESS_STRUCTURE_COUNT];\r
+#endif\r
+\r
+} EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE;\r
+\r
+#pragma pack()\r
+\r
+#endif // _MCFG_H_\r

diff --git a/Vlv2TbltDevicePkg/Include/McfgTable.h b/Vlv2TbltDevicePkg/Include/McfgTable.h
new file mode 100644 (file)
index 0000000..39461a2
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Include/McfgTable.h
@@ -0,0 +1,70 @@
+/*++\r
+\r
+  Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+Module Name:\r
+\r
+  McfgTable.h\r
+\r
+Abstract:\r
+\r
+  ACPI Memory mapped configuration space base address Description Table\r
+  definition, based on PCI Firmware Specification Revision 3.0 final draft,\r
+  downloadable at http://www.pcisig.com/home\r
+\r
+**/\r
+\r
+#ifndef _MCFG_TABLE_H_\r
+#define _MCFG_TABLE_H_\r
+\r
+//\r
+// Include files\r
+//\r
+#include <PiDxe.h>\r
+\r
+//\r
+// Ensure proper structure formats\r
+//\r
+#pragma pack(1)\r
+\r
+//\r
+// MCFG Revision (defined in spec)\r
+//\r
+#define EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE_REVISION  0x01\r
+\r
+//\r
+// MCFG Structure Definitions\r
+//\r
+//\r
+// Memory Mapped Enhanced Configuration Base Address Allocation\r
+// Structure Definition\r
+//\r
+typedef struct {\r
+  UINT64  BaseAddress;\r
+  UINT16  PciSegmentGroupNumber;\r
+  UINT8   StartBusNumber;\r
+  UINT8   EndBusNumber;\r
+  UINT32  Reserved;\r
+} EFI_ACPI_MEMORY_MAPPED_ENHANCED_CONFIGURATION_BASE_ADDRESS_STRUCTURE;\r
+\r
+//\r
+// MCFG Table header definition.  The rest of the table\r
+// must be defined in a platform specific manner.\r
+//\r
+typedef struct {\r
+  EFI_ACPI_DESCRIPTION_HEADER Header;\r
+  UINT64                      Reserved;\r
+} EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE_HEADER;\r
+\r
+#pragma pack()\r
+\r
+#endif // _MCFG_TABLE_H\r

diff --git a/Vlv2TbltDevicePkg/Include/Platform.h b/Vlv2TbltDevicePkg/Include/Platform.h
new file mode 100644 (file)
index 0000000..fa651f5
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Include/Platform.h
@@ -0,0 +1,138 @@
+/*++\r
+\r
+  Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+\r
+Module Name:\r
+\r
+  Platform.h\r
+\r
+Abstract:\r
+\r
+  Pinetrail platform specific information.\r
+\r
+**/\r
+\r
+#ifndef _PLATFORM_H\r
+#define _PLATFORM_H\r
+\r
+#include "ChipsetAccess.h"\r
+#include "PlatformBaseAddresses.h"\r
+\r
+\r
+//\r
+// Number of P & T states supported.\r
+//\r
+#define NPTM_P_STATES_SUPPORTED         16\r
+#define NPTM_T_STATES_SUPPORTED         8\r
+\r
+//\r
+// I/O APIC IDs, the code uses math to generate the numbers\r
+// instead of using these defines.\r
+//\r
+#define ICH_IOAPIC                     (1 << 0)\r
+#define ICH_IOAPIC_ID                   0x08\r
+\r
+//\r
+// Possible SMBus addresses that will be present.\r
+//\r
+#define SMBUS_ADDR_CH_A_1     0xA0\r
+#define SMBUS_ADDR_CH_A_2     0xA2\r
+#define SMBUS_ADDR_CH_B_1     0xA4\r
+#define SMBUS_ADDR_CH_B_2     0xA6\r
+#define SMBUS_ADDR_CH_C_1     0xA8\r
+#define SMBUS_ADDR_CH_C_2     0xAA\r
+#define SMBUS_ADDR_CH_D_1     0xAC\r
+#define SMBUS_ADDR_CH_D_2     0xAE\r
+#define SMBUS_ADDR_HOST_CLK_BUFFER  0xDC\r
+#define SMBUS_ADDR_ICH_SLAVE        0x44\r
+#define SMBUS_ADDR_HECETA     0x5C\r
+#define SMBUS_ADDR_SMBARP     0xC2\r
+#define SMBUS_ADDR_82573E     0xC6\r
+#define SMBUS_ADDR_CLKCHIP    0xD2\r
+#define SMBUS_ADDR_BRD_REV          0x4E\r
+#define SMBUS_ADDR_DB803            0x82\r
+\r
+//\r
+// SMBus addresses that used on this platform.\r
+//\r
+#define PLATFORM_SMBUS_RSVD_ADDRESSES { \\r
+  SMBUS_ADDR_CH_A_1, \\r
+  SMBUS_ADDR_CH_A_2, \\r
+  SMBUS_ADDR_HOST_CLK_BUFFER, \\r
+  SMBUS_ADDR_ICH_SLAVE, \\r
+  SMBUS_ADDR_SMBARP, \\r
+  SMBUS_ADDR_CLKCHIP, \\r
+  SMBUS_ADDR_BRD_REV, \\r
+  SMBUS_ADDR_DB803 \\r
+  }\r
+\r
+//\r
+// Count of addresses present in PLATFORM_SMBUS_RSVD_ADDRESSES.\r
+//\r
+#define PLATFORM_NUM_SMBUS_RSVD_ADDRESSES 8\r
+\r
+//\r
+// CMOS usage\r
+//\r
+#define CMOS_CPU_BSP_SELECT         0x10\r
+#define CMOS_CPU_UP_MODE            0x11\r
+#define CMOS_CPU_RATIO_OFFSET       0x12\r
+#define CMOS_CPU_CORE_HT_OFFSET     0x13\r
+#define CMOS_EFI_DEBUG              0x14\r
+#define CMOS_CPU_BIST_OFFSET        0x15\r
+#define CMOS_CPU_VMX_OFFSET         0x16\r
+#define CMOS_ICH_PORT80_OFFSET      0x17\r
+#define CMOS_PLATFORM_DESIGNATOR    0x18      // Second bank CMOS location of Platform ID.\r
+#define CMOS_VALIDATION_TEST_BYTE   0x19      // BIT0 - Validation mailbox for UPonDP.\r
+#define CMOS_SERIAL_BAUD_RATE       0x1A      // 0=115200; 1=57600; 2=38400; 3=19200; 4=9600\r
+#define CMOS_DCU_MODE_OFFSET        0x1B\r
+#define CMOS_VR11_SET_OFFSET        0x1C\r
+#define CMOS_SBSP_TO_AP_COMM        0x20      // SEC code use ONLY!!!\r
+#define CMOS_RESET_TYPE_BY_OS       0x52\r
+#define TCG_CMOS_MOR_AREA_OFFSET    0x65      // Also Change in Universal\Security\Tpm\PhysicalPresence\Dxe\PhysicalPresence.c &\r
+#define CMOS_S4_WAKEUP_FLAG_ADDRESS 0x6E\r
+#define ACPI_TPM_REQUEST            0x75\r
+#define ACPI_TPM_LAST_REQUEST       0x76\r
+#define CMOS_BOOT_FLAG_ADDRESS      0x7E\r
+\r
+//\r
+// GPIO Index Data Structure.\r
+//\r
+typedef struct {\r
+  UINT8   Register;\r
+  UINT32  Value;\r
+} ICH_GPIO_DEV;\r
+\r
+//\r
+// CPU Equates\r
+//\r
+#define MAX_THREAD                      2\r
+#define MAX_CORE                        1\r
+#define MAX_DIE                         2\r
+#define MAX_CPU_SOCKET                  1\r
+#define MAX_CPU_NUM                     (MAX_THREAD * MAX_CORE * MAX_DIE * MAX_CPU_SOCKET)\r
+\r
+#define MEM64_LEN                       0x00100000000\r
+#define RES_MEM64_36_BASE               0x01000000000 - MEM64_LEN   // 2^36\r
+#define RES_MEM64_36_LIMIT              0x01000000000 - 1           // 2^36\r
+#define RES_MEM64_39_BASE               0x08000000000 - MEM64_LEN   // 2^39\r
+#define RES_MEM64_39_LIMIT              0x08000000000 - 1           // 2^39\r
+#define RES_MEM64_40_BASE               0x10000000000 - MEM64_LEN   // 2^40\r
+#define RES_MEM64_40_LIMIT              0x10000000000 - 1           // 2^40\r
+\r
+#define PLATFORM_MAX_BUS_NUM             0x3f\r
+#define V_DEFAULT_SUBSYSTEM_DEVICE_ID    0x574d\r
+#define V_DEFAULT_SUBSYSTEM_DEVICE_ID_KT 0x544b\r
+#define V_DEFAULT_SUBSYSTEM_VENDOR_ID    0x8086\r
+\r
+#endif\r

diff --git a/Vlv2TbltDevicePkg/Include/PlatformBootMode.h b/Vlv2TbltDevicePkg/Include/PlatformBootMode.h
new file mode 100644 (file)
index 0000000..5335ab9
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Include/PlatformBootMode.h
@@ -0,0 +1,40 @@
+/*++\r
+\r
+  Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+\r
+Module Name:\r
+\r
+    PlatformBootMode.h\r
+\r
+Abstract:\r
+\r
+    EFI Platform Boot Mode\r
+\r
+Revision History\r
+\r
+--*/\r
+\r
+#ifndef _EFI_PLATFORM_BOOT_MODE_H_\r
+#define _EFI_PLATFORM_BOOT_MODE_H_\r
+\r
+//\r
+// Global ID for the Platform Boot Mode Protocol.\r
+//\r
+#define   MANUFACTURE_SETUP_NAME             L"MfgDefault"\r
+#define   SAFE_SETUP_NAME                    L"SetupDefault"\r
+#define   OEM_DEFAULTS_SETUP_NAME            L"OemDefault"\r
+#define   CUSTOM_DEFAULTS_SETUP_NAME         L"CustomDefault"\r
+\r
+#endif\r
+\r
+\r

diff --git a/Vlv2TbltDevicePkg/Include/PlatformDefinitions.h b/Vlv2TbltDevicePkg/Include/PlatformDefinitions.h
new file mode 100644 (file)
index 0000000..edff69d
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Include/PlatformDefinitions.h
@@ -0,0 +1,48 @@
+/*++\r
+\r
+Copyright (c) 1999  - 2014, Intel Corporation. All rights reserved\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+\r
+Module Name:\r
+\r
+  PlatformDefinitions.h\r
+\r
+Abstract:\r
+\r
+  This header file provides platform specific definitions used by other modules\r
+  for platform specific initialization.\r
+\r
+  THIS FILE SHOULD ONLY CONTAIN #defines BECAUSE IT IS CONSUMED BY NON-C MODULES\r
+  (ASL and VFR)\r
+\r
+  This file should not contain addition or other operations that an ASL compiler or\r
+  VFR compiler does not understand.\r
+\r
+--*/\r
+\r
+#ifndef _PLATFORM_DEFINITIONS_H_\r
+#define _PLATFORM_DEFINITIONS_H_\r
+\r
+\r
+//\r
+// Platform Base Address definitions\r
+//\r
+#define PCIEX_BASE_ADDRESS          EDKII_GLUE_PciExpressBaseAddress // Pci Express Configuration Space Base Address\r
+\r
+#define PCIEX_LENGTH                PLATFORM_PCIEXPRESS_LENGTH\r
+\r
+#define THERMAL_BASE_ADDRESS        0xFED08000\r
+\r
+#ifndef MCH_BASE_ADDRESS\r
+#define MCH_BASE_ADDRESS            0xFED10000  // MCH  Register Base Address\r
+#endif\r
+#endif\r

diff --git a/Vlv2TbltDevicePkg/Include/Ppi/MfgMemoryTest.h b/Vlv2TbltDevicePkg/Include/Ppi/MfgMemoryTest.h
new file mode 100644 (file)
index 0000000..fc47448
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Include/Ppi/MfgMemoryTest.h
@@ -0,0 +1,47 @@
+/*++\r
+\r
+  Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+Module Name:\r
+\r
+  BaseMemoryTest.h\r
+\r
+Abstract:\r
+\r
+  Pei memory test PPI as defined in Tiano\r
+\r
+  Used to Pei memory test in PEI\r
+\r
+--*/\r
+\r
+#ifndef _BASE_MEMORY_TEST_H_\r
+#define _BASE_MEMORY_TEST_H_\r
+\r
+typedef struct _PEI_MFG_MEMORY_TEST_PPI PEI_MFG_MEMORY_TEST_PPI;\r
+\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *PEI_MFG_MEMORY_TEST) (\r
+  IN  CONST EFI_PEI_SERVICES                   **PeiServices,\r
+  IN  PEI_MFG_MEMORY_TEST_PPI            * This,\r
+  IN  UINT32                             BeginAddress,\r
+  IN  UINT32                             MemoryLength\r
+  );\r
+\r
+typedef struct _PEI_MFG_MEMORY_TEST_PPI {\r
+  PEI_MFG_MEMORY_TEST  MfgMemoryTest;\r
+}PEI_MFG_MEMORY_TEST_PPI;\r
+\r
+\r
+extern EFI_GUID gPeiMfgMemoryTestPpiGuid;\r
+\r
+#endif\r

diff --git a/Vlv2TbltDevicePkg/Include/Ppi/Sha256Hash.h b/Vlv2TbltDevicePkg/Include/Ppi/Sha256Hash.h
new file mode 100644 (file)
index 0000000..8511b4c
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Include/Ppi/Sha256Hash.h
@@ -0,0 +1,136 @@
+/*++\r
+\r
+  Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+Module Name:\r
+\r
+  Speaker.h\r
+\r
+Abstract:\r
+\r
+  EFI Speaker Interface Protocol\r
+\r
+\r
+\r
+--*/\r
+\r
+#ifndef _PEI_SHA256_HASH_H\r
+#define _PEI_SHA256_HASH_H\r
+\r
+//\r
+// Global ID Speaker Interface\r
+//\r
+#define PEI_SHA256_HASH_PPI_GUID \\r
+  { \\r
+    0x950e191b, 0x8524, 0x4f51,  0x80, 0xa1, 0x5c, 0x4f, 0x1b, 0x3, 0xf3, 0x5c  \\r
+  }\r
+\r
+typedef struct _PEI_SHA256_HASH_PPI PEI_SHA256_HASH_PPI;\r
+\r
+/**\r
+  @return  The size, in bytes, of the context buffer required for hash operations.\r
+\r
+**/\r
+typedef\r
+UINTN\r
+(EFIAPI *HASH_GET_CONTEXT_SIZE)(\r
+  VOID\r
+  );\r
+\r
+/**\r
+  Initializes user-supplied memory pointed by HashContext as hash context for\r
+  subsequent use.\r
+\r
+  If HashContext is NULL, then ASSERT().\r
+\r
+  @param[in, out]  HashContext  Pointer to  Context being initialized.\r
+\r
+  @retval TRUE   HASH context initialization succeeded.\r
+  @retval FALSE  HASH context initialization failed.\r
+\r
+**/\r
+typedef\r
+BOOLEAN\r
+(EFIAPI *HASH_INIT)(\r
+  IN OUT  VOID  *HashContext\r
+  );\r
+\r
+/**\r
+  Performs digest on a data buffer of the specified length. This function can\r
+  be called multiple times to compute the digest of long or discontinuous data streams.\r
+\r
+  If HashContext is NULL, then ASSERT().\r
+\r
+  @param[in, out]  HashContext  Pointer to the MD5 context.\r
+  @param[in]       Data         Pointer to the buffer containing the data to be hashed.\r
+  @param[in]       DataLength   Length of Data buffer in bytes.\r
+\r
+  @retval TRUE     HASH data digest succeeded.\r
+  @retval FALSE    Invalid HASH context. After HashFinal function has been called, the\r
+                   HASH context cannot be reused.\r
+\r
+**/\r
+typedef\r
+BOOLEAN\r
+(EFIAPI *HASH_UPDATE)(\r
+  IN OUT  VOID        *HashContext,\r
+  IN      CONST VOID  *Data,\r
+  IN      UINTN       DataLength\r
+  );\r
+\r
+/**\r
+  Completes hash computation and retrieves the digest value into the specified\r
+  memory. After this function has been called, the context cannot be used again.\r
+\r
+  If HashContext is NULL, then ASSERT().\r
+  If HashValue is NULL, then ASSERT().\r
+\r
+  @param[in, out]  HashContext  Pointer to the MD5 context\r
+  @param[out]      HashValue    Pointer to a buffer that receives the HASH digest\r
+                                value.\r
+\r
+  @retval TRUE   HASH digest computation succeeded.\r
+  @retval FALSE  HASH digest computation failed.\r
+\r
+**/\r
+typedef\r
+BOOLEAN\r
+(EFIAPI *HASH_FINAL)(\r
+  IN OUT  VOID   *HashContext,\r
+  OUT     UINT8  *HashValue\r
+  );\r
+\r
+//\r
+// Ppi definition\r
+//\r
+typedef struct _PEI_SHA256_HASH_PPI {\r
+  //\r
+  // Pointer to Hash GetContentSize function\r
+  //\r
+  HASH_GET_CONTEXT_SIZE    GetContextSize;\r
+  //\r
+  // Pointer to Hash Init function\r
+  //\r
+  HASH_INIT                HashInit;\r
+  //\r
+  // Pointer to Hash Update function\r
+  //\r
+  HASH_UPDATE              HashUpdate;\r
+  //\r
+  // Pointer to Hash Final function\r
+  //\r
+  HASH_FINAL               HashFinal;\r
+\r
+} PEI_SHA256_HASH_PPI;\r
+\r
+extern EFI_GUID gPeiSha256HashPpiGuid;\r
+#endif\r

diff --git a/Vlv2TbltDevicePkg/Include/Ppi/Speaker.h b/Vlv2TbltDevicePkg/Include/Ppi/Speaker.h
new file mode 100644 (file)
index 0000000..2dfdafb
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Include/Ppi/Speaker.h
@@ -0,0 +1,70 @@
+/*++\r
+\r
+  Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+Module Name:\r
+\r
+  Speaker.h\r
+\r
+Abstract:\r
+\r
+  EFI Speaker Interface Protocol\r
+\r
+\r
+\r
+--*/\r
+\r
+#ifndef _PEI_SPEAKER_IF_H\r
+#define _PEI_SPEAKER_IF_H\r
+\r
+//\r
+// Global ID Speaker Interface\r
+//\r
+#define PEI_SPEAKER_INTERFACE_PPI_GUID \\r
+  { \\r
+    0x30ac275e, 0xbb30, 0x4b84, 0xa1, 0xcd, 0x0a, 0xf1, 0x32, 0x2c, 0x89, 0xc0 \\r
+  }\r
+\r
+typedef struct _PEI_SPEAKER_IF_PPI PEI_SPEAKER_IF_PPI;\r
+\r
+//\r
+// Beep Code\r
+//\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *EFI_SPEAKER_GENERATE_BEEP) (\r
+  IN CONST EFI_PEI_SERVICES           **PeiServices,\r
+  IN UINTN                            NumberOfBeep,\r
+  IN UINTN                            BeepDuration,\r
+  IN UINTN                            TimeInterval\r
+  );\r
+\r
+//\r
+// Set Frequency\r
+//\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *EFI_SPEAKER_SET_FREQUENCY) (\r
+  IN CONST EFI_PEI_SERVICES           **PeiServices,\r
+  IN UINT16                           Frequency\r
+  );\r
+\r
+//\r
+// Protocol definition\r
+//\r
+typedef struct _PEI_SPEAKER_IF_PPI {\r
+  EFI_SPEAKER_SET_FREQUENCY SetSpeakerToneFrequency;\r
+  EFI_SPEAKER_GENERATE_BEEP GenerateBeep;\r
+} PEI_SPEAKER_IF_PPI;\r
+\r
+extern EFI_GUID gPeiSpeakerInterfacePpiGuid;\r
+#endif\r

diff --git a/Vlv2TbltDevicePkg/Include/Ppi/UsbController.h b/Vlv2TbltDevicePkg/Include/Ppi/UsbController.h
new file mode 100644 (file)
index 0000000..dc6468a
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Include/Ppi/UsbController.h
@@ -0,0 +1,90 @@
+/*++\r
+\r
+  Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+  Define APIs to retrieve USB Host Controller Info such as controller type and\r
+  I/O Port Base Address.\r
+\r
+\r
+**/\r
+\r
+#ifndef _PEI_USB_CONTROLLER_PPI_H_\r
+#define _PEI_USB_CONTROLLER_PPI_H_\r
+\r
+//\r
+// Global ID for the PEI_USB_CONTROLLER_PPI.\r
+//\r
+#define PEI_USB_CONTROLLER_PPI_GUID \\r
+  { \\r
+    0x3bc1f6de, 0x693e, 0x4547,{ 0xa3, 0x0, 0x21, 0x82, 0x3c, 0xa4, 0x20, 0xb2} \\r
+  }\r
+\r
+//\r
+// Forward declaration for the PEI_USB_CONTROLLER_PPI.\r
+//\r
+typedef struct _PEI_USB_CONTROLLER_PPI PEI_USB_CONTROLLER_PPI;\r
+\r
+//\r
+// This bit is used in the ControllerType return parameter of GetUsbController()\r
+// to identify the USB Host Controller type as UHCI\r
+//\r
+#define PEI_UHCI_CONTROLLER 0x01\r
+\r
+//\r
+// This bit is used in the ControllerType return parameter of GetUsbController()\r
+// to identify the USB Host Controller type as OHCI\r
+//\r
+#define PEI_OHCI_CONTROLLER 0x02\r
+\r
+//\r
+// This bit is used in the ControllerType return parameter of GetUsbController()\r
+// to identify the USB Host Controller type as EHCI\r
+//\r
+#define PEI_EHCI_CONTROLLER 0x03\r
+\r
+/**\r
+  Retrieve USB Host Controller Info such as controller type and I/O Base Address.\r
+\r
+  @param[in]  PeiServices      The pointer to the PEI Services Table.\r
+  @param[in]  This             The pointer to this instance of the PEI_USB_CONTROLLER_PPI.\r
+  @param[in]  ControllerId     The ID of the USB controller.\r
+  @param[out] ControllerType   On output, returns the type of the USB controller.\r
+  @param[out] BaseAddress      On output, returns the base address of UHCI's I/O ports\r
+                               if UHCI is enabled or the base address of EHCI's MMIO\r
+                               if EHCI is enabled.\r
+\r
+  @retval EFI_SUCCESS             USB controller attributes were returned successfully.\r
+  @retval EFI_INVALID_PARAMETER   ControllerId is greater than the maximum number\r
+                                  of USB controller supported by this platform.\r
+\r
+**/\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *PEI_GET_USB_CONTROLLER)(\r
+  IN  EFI_PEI_SERVICES        **PeiServices,\r
+  IN  PEI_USB_CONTROLLER_PPI  *This,\r
+  IN  UINT8                   UsbControllerId,\r
+  OUT UINTN                   *ControllerType,\r
+  OUT UINTN                   *BaseAddress\r
+  );\r
+\r
+//\r
+// This PPI contains a single service to retrieve the USB Host Controller type\r
+// and the base address of the I/O ports used to access the USB Host Controller.\r
+//\r
+struct _PEI_USB_CONTROLLER_PPI {\r
+  PEI_GET_USB_CONTROLLER  GetUsbController;\r
+};\r
+\r
+extern EFI_GUID gPeiUsbControllerPpiGuid;\r
+\r
+#endif\r

diff --git a/Vlv2TbltDevicePkg/Include/Protocol/CK505ClockPlatformInfo.h b/Vlv2TbltDevicePkg/Include/Protocol/CK505ClockPlatformInfo.h
new file mode 100644 (file)
index 0000000..87c1c37
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Include/Protocol/CK505ClockPlatformInfo.h
@@ -0,0 +1,131 @@
+/*++\r
+\r
+  Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+Module Name:\r
+\r
+  CK505ClockPlatformInfo.h\r
+\r
+Abstract:\r
+\r
+  Protocol to communicate product clock routing information.\r
+\r
+GUID Info:\r
+ {3C485EA4-449A-46ce-BB08-2A336EA96B4E}\r
+ 0x3c485ea4, 0x449a, 0x46ce, 0xbb, 0x8, 0x2a, 0x33, 0x6e, 0xa9, 0x6b, 0x4e);\r
+\r
+**/\r
+\r
+#ifndef _CLOCK_PLATFORM_INFO_H_\r
+#define _CLOCK_PLATFORM_INFO_H_\r
+\r
+\r
+#define EFI_CK505_CLOCK_PLATFORM_INFO_GUID  \\r
+  {0x3c485ea4, 0x449a, 0x46ce, 0xbb, 0x8, 0x2a, 0x33, 0x6e, 0xa9, 0x6b, 0x4e}\r
+\r
+//\r
+// Structure to hold register modifications\r
+//\r
+typedef enum {\r
+  None           = 0x00000000,\r
+  nICS9LP505_1   = 0x00000001,\r
+  nICS9LP505_2   = 0x00000002,\r
+  nIDTCV163      = 0x00000004,\r
+  nIDTCV174      = 0x00000008,\r
+  nSLG505YC56    = 0x00000010,\r
+  nSLG505YC64    = 0x00000020,\r
+  nCY28505       = 0x00000040,\r
+  nCY28505_2     = 0x00000080,\r
+  nCY28505LF     = 0x00000100,\r
+  nPI6C505_OLD   = 0x00000200,\r
+  nPI6C505_RevD  = 0x00000400,\r
+  nGENERIC_505   = 0x00000800,\r
+  nSLG505YC264   = 0x00001000,\r
+  nIDTCV183      = 0x00002000,\r
+  nSLG505YC256   = 0x00004000,\r
+  nIDTCV184      = 0x00008000,\r
+  nIDTCV190      = 0x00010000,\r
+  All            = 0xFFFFFFFF\r
+} EFI_CLOCKS_SUPPORTED;\r
+\r
+typedef enum {\r
+  Disabled,\r
+  Enabled,\r
+  EnabledWithoutSwitch,\r
+  EnabledWithSwitch\r
+} EFI_SIGNAL_STATE;\r
+\r
+typedef enum {\r
+  SrcClk11,\r
+  SrcClk10,\r
+  SrcClk9,\r
+  SrcClk8,\r
+  SrcClk7,\r
+  SrcClk6,\r
+  SrcClk5,\r
+  SrcClk4,\r
+  SrcClk3,\r
+  SrcClk2,\r
+  SrcClk1,\r
+  SrcClk0,\r
+  CpuClk1,\r
+  CpuClk0,\r
+  Ref0,\r
+  Dot96,\r
+  Usb48,\r
+  PciClkF5,\r
+  PciClk4,\r
+  PciClk3,\r
+  PciClk2,\r
+  PciClk1,\r
+  PciClk0,\r
+  SaveClockConfiguration,\r
+  MePresent,\r
+  Cr_A,\r
+  Cr_B,\r
+  Cr_C,\r
+  Cr_D,\r
+  Cr_E,\r
+  Cr_F,\r
+  Cr_G,\r
+  Cr_H,\r
+  Clk_None // Dummy entry for dynamic detection\r
+} EFI_CLOCK_SIGNAL_NAME;\r
+\r
+typedef struct {\r
+  EFI_CLOCK_SIGNAL_NAME     Signal;\r
+  EFI_SIGNAL_STATE          State;\r
+  EFI_CLOCKS_SUPPORTED      Supported;\r
+} EFI_STATIC_SIGNALS;\r
+\r
+typedef struct {\r
+  BOOLEAN               BehindBridge;\r
+  UINT16                BridgeBus;\r
+  UINT16                BridgeDev;\r
+  UINT16                BridgeFunction;\r
+  UINT16                TargetDevice;\r
+  EFI_CLOCK_SIGNAL_NAME Signal;\r
+} EFI_DYNAMIC_SIGNALS;\r
+\r
+\r
+typedef struct {\r
+  EFI_STATIC_SIGNALS      *StaticClockTable;\r
+  UINTN                   StaticClockTableCount;\r
+  EFI_STATIC_SIGNALS      *SxClockTable;\r
+  UINTN                   SxClockTableCount;\r
+  EFI_STATIC_SIGNALS     *DynamicDisabledClocksTable;\r
+  UINTN                          DynamicDisabledClocksTableCount;\r
+} EFI_CLOCK_PLATFORM_INFO;\r
+\r
+extern EFI_GUID gEfiCk505ClockPlatformInfoGuid;\r
+\r
+#endif\r

diff --git a/Vlv2TbltDevicePkg/Include/Protocol/EnhancedSpeedstep.h b/Vlv2TbltDevicePkg/Include/Protocol/EnhancedSpeedstep.h
new file mode 100644 (file)
index 0000000..e71778f
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Include/Protocol/EnhancedSpeedstep.h
@@ -0,0 +1,81 @@
+/*++\r
+\r
+  Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+\r
+\r
+Module Name:\r
+\r
+  EnhancedSpeedstep.h\r
+\r
+Abstract:\r
+\r
+  Enhanced Speedstep protocol\r
+\r
+  The Enhanced Speedstep Protocol support.\r
+\r
+**/\r
+\r
+#ifndef _ENHANCED_SPEEDSTEP_H_\r
+#define _ENHANCED_SPEEDSTEP_H_\r
+\r
+#define ENHANCED_SPEEDSTEP_PROTOCOL_GUID \\r
+  { \\r
+    0x91a1ddcf, 0x5374, 0x4939, 0x89, 0x51, 0xd7, 0x29, 0x3f, 0x1a, 0x78, 0x6f \\r
+  }\r
+\r
+typedef struct _ENHANCED_SPEEDSTEP_PROTOCOL ENHANCED_SPEEDSTEP_PROTOCOL;\r
+\r
+typedef struct {\r
+  UINT8   Version;      // EIST State format\r
+  UINT8   Size;         // Size of element\r
+  UINT32  RatioStep;    // Step\r
+  UINT32  MinRatio;     // Calculated min ratio\r
+  UINT32  MaxRatio;     // Calculated max ratio\r
+  UINT32  MinCoreFreq;  // Calculated min freq\r
+  UINT32  MaxCoreFreq;  // Calculated max freq\r
+  UINT32  MinPower;     // Calculated min power\r
+  UINT32  MaxPower;     // Calculated max power\r
+  UINT32  NumStates;    // Number of states\r
+} EIST_INFORMATION;\r
+\r
+typedef struct {\r
+  UINT32  CoreFrequency;\r
+  UINT32  Power;\r
+  UINT32  TransitionLatency;\r
+  UINT32  BusMasterLatency;\r
+  UINT32  Control;\r
+  UINT32  Status;\r
+} EFI_ACPI_CPU_PSS_STATE;\r
+\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *GET_EIST_TABLE) (\r
+  IN    ENHANCED_SPEEDSTEP_PROTOCOL    *This,\r
+  OUT   EIST_INFORMATION               **EistInformation,\r
+  OUT   VOID                           **PssStates\r
+  );\r
+\r
+struct _ENHANCED_SPEEDSTEP_PROTOCOL {\r
+  UINT32              ProcApicId;\r
+  GET_EIST_TABLE      GetEistTable;\r
+};\r
+\r
+//\r
+// There will be an instance of this protocol for every processor\r
+// in the system.  ProcNumber is used to manage all the different\r
+// processors in the system and passed into the MP protocol\r
+// to run code streams on application processors\r
+//\r
+extern EFI_GUID gEnhancedSpeedstepProtocolGuid;\r
+\r
+#endif\r

diff --git a/Vlv2TbltDevicePkg/Include/Protocol/GlobalNvsArea.h b/Vlv2TbltDevicePkg/Include/Protocol/GlobalNvsArea.h
new file mode 100644 (file)
index 0000000..231c8c0
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Include/Protocol/GlobalNvsArea.h
@@ -0,0 +1,484 @@
+/*++
+
+  Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>
+                                                                                   
+
+  This program and the accompanying materials are licensed and made available under
+
+  the terms and conditions of the BSD License that accompanies this distribution.  
+
+  The full text of the license may be found at                                     
+
+  http://opensource.org/licenses/bsd-license.php.                                  
+
+                                                                                   
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            
+
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    
+
+                                                                                   
+
+
+
+Module Name:
+
+  GlobalNvsArea.h
+
+Abstract:
+
+  Definition of the global NVS area protocol.  This protocol
+  publishes the address and format of a global ACPI NVS buffer used as a communications
+  buffer between SMM code and ASL code.
+  The format is derived from the ACPI reference code, version 0.95.
+
+  Note:  Data structures defined in this protocol are not naturally aligned.
+
+**/
+
+
+#ifndef _GLOBAL_NVS_AREA_H_
+#define _GLOBAL_NVS_AREA_H_
+
+//
+// Includes
+//
+#define GLOBAL_NVS_DEVICE_ENABLE 1
+#define GLOBAL_NVS_DEVICE_DISABLE 0
+
+//
+// Forward reference for pure ANSI compatibility
+//
+
+//EFI_FORWARD_DECLARATION (EFI_GLOBAL_NVS_AREA_PROTOCOL);
+
+//
+// Global NVS Area Protocol GUID
+//
+#define EFI_GLOBAL_NVS_AREA_PROTOCOL_GUID \
+{ 0x74e1e48, 0x8132, 0x47a1, 0x8c, 0x2c, 0x3f, 0x14, 0xad, 0x9a, 0x66, 0xdc }
+
+//
+// Revision id - Added TPM related fields
+//
+#define GLOBAL_NVS_AREA_RIVISION_1       1
+
+//
+// Extern the GUID for protocol users.
+//
+extern EFI_GUID gEfiGlobalNvsAreaProtocolGuid;
+
+//
+// Global NVS Area definition
+//
+#pragma pack (1)
+typedef struct {
+  //
+  // Miscellaneous Dynamic Values, the definitions below need to be matched
+  // GNVS definitions in Platform.ASL
+  //
+  UINT16      OperatingSystem;    // 00
+  UINT8       SmiFunction;        // 02   SMI function call via IO Trap
+  UINT8       SmiParameter0;      // 03
+  UINT8       SmiParameter1;      // 04
+  UINT8       SciFunction;        // 05   SCI function call via _L00
+  UINT8       SciParameter0;      // 06
+  UINT8       SciParameter1;      // 07
+  UINT8       GlobalLock;         // 08   Global lock function call
+  UINT8       LockParameter0;     // 09
+  UINT8       LockParameter1;     // 10
+  UINT32      Port80DebugValue;   // 11
+  UINT8       LidState;           // 15   Open = 1
+  UINT8       PowerState;         // 16   AC = 1
+  UINT8       DebugState;         // 17
+
+
+  //
+  // Thermal Policy Values
+  //
+  UINT8       EnableThermalOffset;                        // 18 ThermalOffset for KSC
+  UINT8       Reserved1;                                                 // 19
+  UINT8       Reserved2;                                                         // 20
+  UINT8       PassiveThermalTripPoint;                    // 21
+  UINT8       PassiveTc1Value;                            // 22
+  UINT8       PassiveTc2Value;                            // 23
+  UINT8       PassiveTspValue;                            // 24
+  UINT8       CriticalThermalTripPoint;                   // 25
+  UINT8       ReserveD;
+  UINT8       BspDigitalThermalSensorTemperature;         // 27   Temperature of BSP
+  UINT8       ApDigitalThermalSensorTemperature;          // 28   Temperature of AP
+  UINT8       DigitalThermalSensorSmiFunction;            // 29   SMI function call via DTS IO Trap
+
+  //
+  // Battery Support Values
+  //
+  UINT8       NumberOfBatteries;      // 30
+  UINT8       BatteryCapacity0;       // 31   Battery 0 Stored Capacity
+  UINT8       BatteryCapacity1;       // 32   Battery 1 Stored Capacity
+  UINT8       BatteryCapacity2;       // 33   Battery 2 Stored Capacity
+  UINT8       BatteryStatus0;         // 34   Battery 0 Stored Status
+  UINT8       BatteryStatus1;         // 35   Battery 1 Stored Status
+  UINT8       BatteryStatus2;         // 36   Battery 2 Stored Status
+
+  // NOTE: Do NOT Change the Offset of Revision Field
+  UINT8       Revision;               // 37   Revision of the structure EFI_GLOBAL_NVS_AREA
+  UINT8       Reserved3[2];           // 38:39
+
+  //
+  // Processor Configuration Values
+  //
+  UINT8       ApicEnable;             // 40   APIC Enabled by SBIOS (APIC Enabled = 1)
+  UINT8       LogicalProcessorCount;  // 41   Processor Count Enabled (MP Enabled != 0)
+  UINT8       CurentPdcState0;        // 42   PDC settings, Processor 0
+  UINT8       CurentPdcState1;        // 43   PDC settings, Processor 1
+  UINT8       MaximumPpcState;        // 44   Maximum PPC state
+  UINT32      PpmFlags;               // 45:48 PPM configuration flags, same as CFGD
+  UINT8       Reserved4[1];           // 49
+
+  //
+  // SIO Configuration Values
+  //
+  UINT8       DockedSioPresent;       // 50   Dock SIO Present
+  UINT8       DockComA;               // 51     COM A Port
+  UINT8       DockComB;               // 52     COM B Port
+  UINT8       LptP;                   // 53     LPT Port
+  UINT8       DockFdc;                // 54     FDC Port
+  UINT8       OnboardCom;             // 55   Onboard COM Port
+  UINT8       OnboardComCir;          // 56   Onboard COM CIR Port
+
+  UINT8       WPCN381U;                  // 57
+  UINT8       NPCE791x;               // 58
+  UINT8       Reserved5[1];           // 59
+
+  //
+  // Internal Graphics Device Values
+  //
+  UINT8       IgdState;               // 60   IGD State (Primary Display = 1)
+  UINT8       DisplayToggleList;      // 61   Display Toggle List Selection
+  UINT8       CurrentDeviceList;      // 62   Current Attached Device List
+  UINT8       PreviousDeviceList;     // 63   Previous Attached Device List
+  UINT16      CurrentDisplayState;    // 64   Current Display State
+  UINT16      NextDisplayState;       // 66   Next Display State
+  UINT16      SetDisplayState;        // 68   Set Display State
+  UINT8       NumberOfValidDeviceId;  // 70   Number of Valid Device IDs
+  UINT32      DeviceId1;              // 71   Device ID 1
+  UINT32      DeviceId2;              // 75   Device ID 2
+  UINT32      DeviceId3;              // 79   Device ID 3
+  UINT32      DeviceId4;              // 83   Device ID 4
+  UINT32      DeviceId5;              // 87   Device ID 5
+
+  UINT32      AKsv0;                  // 91:94 First four bytes of AKSV (manufacturing mode)
+  UINT8       AKsv1;                  // 95    Fifth byte of AKSV (manufacturing mode
+
+  UINT8       Reserved6[7];           // 96:102
+
+  //
+  // Backlight Control Values
+  //
+  UINT8       BacklightControlSupport;  // 103  Backlight Control Support
+  UINT8       BrightnessPercentage;     // 104  Brightness Level Percentage
+
+  //
+  // Ambient Light Sensor Values
+  //
+  UINT8       AlsEnable;              // 105  Ambient Light Sensor Enable
+  UINT8       AlsAdjustmentFactor;    // 106  Ambient Light Adjusment Factor
+  UINT8       LuxLowValue;            // 107  LUX Low Value
+  UINT8       LuxHighValue;           // 108  LUX High Value
+
+  UINT8       Reserved7[1];           // 109
+
+  //
+  // Extended Mobile Access Values
+  //
+  UINT8       EmaEnable;              // 110  EMA Enable
+  UINT16      EmaPointer;             // 111  EMA Pointer
+  UINT16      EmaLength;              // 113  EMA Length
+
+  UINT8       Reserved8[1];           // 115
+
+  //
+  // Mobile East Fork Values
+  //
+  UINT8       MefEnable;              // 116 Mobile East Fork Enable
+
+  //
+  // PCIe Dock Status
+  //
+  UINT8       PcieDockStatus;         // 117 PCIe Dock Status
+
+  UINT8       Reserved9[2];           // 118:119
+
+  //
+  // TPM Registers
+  //
+  UINT8       TpmPresent;             // 120 TPM Present
+  UINT8       TpmEnable;              // 121 TPM Enable
+
+  UINT8       MorData;                // 122 Memory Overwrite Request Data
+  UINT8       TcgParamter;            // 123 Used for save the Mor and/or physical presence paramter
+  UINT32      PPResponse;             // 124 Physical Presence request operation response
+  UINT8       PPRequest;              // 128 Physical Presence request operation
+  UINT8       LastPPRequest;          // 129 Last Physical Presence request operation
+
+  //
+  // SATA Values
+  //
+  UINT8       GtfTaskFileBufferPort0[7];    // 130  GTF Task File Buffer for Port 0
+  UINT8       GtfTaskFileBufferPort2[7];    // 137  GTF Task File Buffer for Port 2
+  UINT8       IdeMode;                      // 144  IDE Mode (Compatible\Enhanced)
+  UINT8       GtfTaskFileBufferPort1[7];    // 145:151 GTF Task File Buffer for Port 1
+
+  UINT8       Reserved111[10];                // 152:161
+  UINT64      BootTimeLogAddress;           // 162:169 Boot Time Log Table Address
+
+  UINT32      IgdOpRegionAddress;           // 170  IGD OpRegion Starting Address
+  UINT8       IgdBootType;                  // 174  IGD Boot Type CMOS option
+  UINT8       IgdPanelType;                 // 175  IGD Panel Type CMOs option
+  UINT8       IgdTvFormat;                  // 176  IGD TV Format CMOS option
+  UINT8       IgdTvMinor;                   // 177  IGD TV Minor Format CMOS option
+  UINT8       IgdPanelScaling;              // 178  IGD Panel Scaling
+  UINT8       IgdBlcConfig;                 // 179  IGD BLC Configuration
+  UINT8       IgdBiaConfig;                 // 180  IGD BIA Configuration
+  UINT8       IgdSscConfig;                 // 181  IGD SSC Configuration
+  UINT8       Igd409;                       // 182  IGD 0409 Modified Settings Flag
+  UINT8       Igd509;                       // 183  IGD 0509 Modified Settings Flag
+  UINT8       Igd609;                       // 184  IGD 0609 Modified Settings Flag
+  UINT8       Igd709;                       // 185  IGD 0709 Modified Settings Flag
+  UINT8       IgdPowerConservation;         // 186  IGD Power Conservation Feature Flag
+  UINT8       IgdDvmtMemSize;               // 187  IGD DVMT Memory Size
+  UINT8       IgdFunc1Enable;               // 188  IGD Function 1 Enable
+  UINT8       IgdHpllVco;                   // 189  HPLL VCO
+  UINT32      NextStateDid1;                // 190  Next state DID1 for _DGS
+  UINT32      NextStateDid2;                // 194  Next state DID2 for _DGS
+  UINT32      NextStateDid3;                // 198  Next state DID3 for _DGS
+  UINT32      NextStateDid4;                // 202  Next state DID4 for _DGS
+  UINT32      NextStateDid5;                // 206  Next state DID5 for _DGS
+  UINT32      NextStateDid6;                // 210  Next state DID6 for _DGS
+  UINT32      NextStateDid7;                // 214  Next state DID7 for _DGS
+  UINT32      NextStateDid8;                // 218  Next state DID8 for _DGS
+  UINT8       IgdSciSmiMode;                // 222  GMCH SMI/SCI mode (0=SCI)
+  UINT8       IgdPAVP;                      // 223  IGD PAVP data
+  UINT8       IgdSelfRefresh;               // 224  IGD Self Refresh
+  UINT8       PcieOSCControl;               // 225  PCIE OSC Control
+  UINT8       NativePCIESupport;            // 226  Native PCI Express Support
+
+  //
+  // USB Sideband Deferring Support
+  //
+  UINT8       HostAlertVector;              // 227  GPE vector used for HOST_ALERT
+  UINT8       HostAlertPio;                 // 228  PIO of USB device used for HOST_ALERT
+
+  UINT8       Reserved112[27];               // 229
+  UINT32      NvIgOpRegionAddress;          // 256 NVIG support
+  UINT32      NvHmOpRegionAddress;          // 260 NVHM support
+  UINT32      ApXmOpRegionAddress;          // 264 AMDA support
+  UINT32      DeviceId6;                    // 268   Device ID 6
+  UINT32      DeviceId7;                    // 272   Device ID 7
+  UINT32      DeviceId8;                    // 276   Device ID 8
+  UINT32      EndpointBaseAddress;          // 280 PEG Endpoint PCIe Base Address
+  UINT32      CapStrPresence;               // 284 PEG Endpoint Capability Structure Presence
+  UINT32      EndpointPcieCapBaseAddress;   // 288 PEG Endpoint PCIe Capability Structure Base Address
+  UINT32      EndpointVcCapBaseAddress;     // 292 PEG Endpoint Virtual Channel Capability Structure Base Address
+  UINT32      XPcieCfgBaseAddress;          // 296 Any Device's PCIe Config Space Base Address
+  UINT32      OccupiedBuses1;               // 300 Occupied Buses from 0 to 31
+  UINT32      OccupiedBuses2;               // 304 Occupied Buses from 32 to 63
+  UINT32      OccupiedBuses3;               // 308 Occupied Buses from 64 to 95
+  UINT32      OccupiedBuses4;               // 312 Occupied Buses from 96 to 127
+  UINT32      OccupiedBuses5;               // 316 Occupied Buses from 128 to 159
+  UINT32      OccupiedBuses6;               // 320 Occupied Buses from 160 to 191
+  UINT32      OccupiedBuses7;               // 324 Occupied Buses from 192 to 223
+  UINT32      OccupiedBuses8;               // 328 Occupied Buses from 224 to 255
+  UINT8       UartSelection;                // 332 UART Interface Selection 0: Internal; 1: SIO
+  UINT8       PcuUart1Enable;               // 333 PCU UART 1 Enabled
+  UINT8       PcuUart2Enable;               // 334 PCU UART 2 Enabled
+
+  UINT32      LPEBar0;                      // 335~338  LPE Bar0
+  UINT32      LPEBar1;                      // 339~342  LPE Bar1
+
+  UINT32      LPEBar2;                      // 343~346  LPE Bar2
+  UINT8                    AcSetup;                      // 347 For Ac Powered Config option - IST applet
+  UINT8       BatterySetup;                 // 348 For Battery Powered Config option - IST applet
+  UINT8       PlatformFlavor;               // 349 0:unknown 1: Mobile; 2: desktop
+  UINT8       Reserved113[1];                // 350
+
+  UINT8       IsctReserve;                      // 351 ISCT / AOAC Configuration
+  UINT8       XhciMode;                     // 352 xHCI mode
+  UINT8       PmicEnable;                   // 353 PMIC enable
+
+  UINT8       LpeEnable;                    // 354 LPE enable
+  UINT32      ISPAddr;                      // 355 ISP Base address 
+  UINT8       ISPDevSel;                    // 359 ISP device enabled selection 0: Disabled; 1: PCI Device 2; 2: PCI Device 3
+
+  //
+  // Lpss controllers
+  //
+  UINT32      PCIBottomAddress;            //360  ((4+8+6)*4+2)*4=296
+  UINT32      PCITopAddress;               //364
+
+  UINT32      LDMA1Addr;                   // 368
+  UINT32      LDMA1Len;                    // 372
+  UINT32      LDMA11Addr;                  // 376
+  UINT32      LDMA11Len;                   // 380
+  UINT32      PWM1Addr;                    // 384 PWM1
+  UINT32      PWM1Len;                     // 388
+  UINT32      PWM11Addr;                   // 392
+  UINT32      PWM11Len;                    // 396
+  UINT32      PWM2Addr;                    // 400 PWM2
+  UINT32      PWM2Len;                     // 404
+  UINT32      PWM21Addr;                   // 408
+  UINT32      PWM21Len;                    // 412
+  UINT32      UART1Addr;                   // 416 UART1
+  UINT32      UART1Len;                    // 420
+  UINT32      UART11Addr;                  // 424 UART1
+  UINT32      UART11Len;                   // 428
+  UINT32      UART2Addr;                   // 432 UART2
+  UINT32      UART2Len;                    // 436
+  UINT32      UART21Addr;                  // 440 UART2
+  UINT32      UART21Len;                   // 444
+  UINT32      SPIAddr;                     // 448 SPI
+  UINT32      SPILen;                      // 452
+  UINT32      SPI1Addr;                    // 456
+  UINT32      SPI1Len;                     // 460
+
+  UINT32      LDMA2Addr;                   // 464
+  UINT32      LDMA2Len;                    // 468
+  UINT32      LDMA21Addr;                  // 472
+  UINT32      LDMA21Len;                   // 476
+  UINT32      I2C1Addr;                    // 480 I2C1
+  UINT32      I2C1Len;                     // 484
+  UINT32      I2C11Addr;                   // 488 I2C1
+  UINT32      I2C11Len;                    // 492
+  UINT32      I2C2Addr;                    // 496 I2C2
+  UINT32      I2C2Len;                     // 500
+  UINT32      I2C21Addr;                   // 504 I2C2
+  UINT32      I2C21Len;                    // 508
+  UINT32      I2C3Addr;                    // 512 I2C3
+  UINT32      I2C3Len;                     // 516
+  UINT32      I2C31Addr;                   // 520 I2C3
+  UINT32      I2C31Len;                    // 524
+  UINT32      I2C4Addr;                    // 528 I2C4
+  UINT32      I2C4Len;                     // 532
+  UINT32      I2C41Addr;                   // 536 I2C4
+  UINT32      I2C41Len;                    // 540
+  UINT32      I2C5Addr;                    // 544 I2C5
+  UINT32      I2C5Len;                     // 548
+  UINT32      I2C51Addr;                   // 552 I2C5
+  UINT32      I2C51Len;                    // 556
+  UINT32      I2C6Addr;                    // 560 I2C6
+  UINT32      I2C6Len;                     // 564
+  UINT32      I2C61Addr;                   // 566 I2C6
+  UINT32      I2C61Len;                    // 570
+  UINT32      I2C7Addr;                    // 574 I2C7
+  UINT32      I2C7Len;                     // 578
+  UINT32      I2C71Addr;                   // 582 I2C7
+  UINT32      I2C71Len;                    // 586
+
+  //
+  // Scc controllers
+  //
+  UINT32      eMMCAddr;                    // 590 EMMC
+  UINT32      eMMCLen;                     // 594
+  UINT32      eMMC1Addr;                   // 598
+  UINT32      eMMC1Len;                    // 602
+  UINT32      SDIOAddr;                    // 606 SDIO
+  UINT32      SDIOLen;                     // 610
+  UINT32      SDIO1Addr;                   // 614
+  UINT32      SDIO1Len;                    // 618
+  UINT32      SDCardAddr;                  // 622 SDCard
+  UINT32      SDCardLen;                   // 626
+  UINT32      SDCard1Addr;                 // 630
+  UINT32      SDCard1Len;                  // 636
+  UINT32           MipiHsiAddr;                 // 640 MIPI-HSI
+  UINT32           MipiHsiLen;                  // 644
+  UINT32           MipiHsi1Addr;                // 648
+  UINT32           MipiHsi1Len;                 // 652
+
+  UINT8       SdCardRemovable;                   // 656 reserve offset upto 658
+  UINT8       HideLPSSDevices;                   // 657 Hide unsupported LPSS devices when in ACPI mode
+  UINT8       ReservedO;                         // 658 OS Selection
+  UINT8       Reserved00;                        // 659 
+  UINT8       Reserved01;                        // 660  
+  UINT8       Reserved02;                   // 661  
+  UINT8       Reserved03;                   // 662  
+  UINT8       Reserved04;                   // 663  
+  UINT8       Reserved05;                   // 664  
+  UINT8       Reserved06;                   // 665  
+  UINT8       Reserved07;                       // 666 
+  UINT8       Reserved08;                 // 667  
+  UINT8       Reserved09;                     // 668  
+  UINT8       Reserved0A;                     // 669  
+  UINT32      Reserved0B;       // 670 
+  UINT32      Reserved0C;        // 674 
+  UINT32      Reserved0D;   // 678 
+  UINT32      Reserved0E;    // 682 
+  UINT32      Reserved0F;   // 686 
+  UINT32      Reserved10;    // 690 
+  UINT32      Reserved11;   // 694 
+  UINT32      Reserved12;    // 698 
+  UINT32      Reserved13;   // 702 
+  UINT32      Reserved14;    // 706 
+  UINT32      Reserved15;   // 710 
+  UINT32      Reserved16;    // 714 
+  UINT8       Reserved17;   
+  UINT32      Reserved18;     
+  UINT32      Reserved19;         
+  UINT32      Reserved1A;        
+  UINT32      Reserved1B;           
+  UINT32      Reserved1C;  
+  UINT8       Reserved1D; 
+  UINT32      Reserved1E; 
+  UINT32      Reserved1F;  
+  UINT32      Reserved20; 
+  UINT32      Reserved21;   
+  UINT32      Reserved22;   
+  UINT8       Reserved23; 
+  UINT8       BatteryChargingSolution;           // 761 0-non ULPMC 1-ULPMC
+
+  //
+  //101 bytes
+  //
+  UINT8       NFCnSelect;                        // 762 NFCx Select 1: NFC1    2:NFC2
+  UINT8       LpssSccMode;                       // 763 EMMC device 0-ACPI mode, 1-PCI mode
+
+  UINT32      TPMAddress;                        // 764
+  UINT32      TPMLength;                         // 768
+
+  UINT8       I2CTouchAddress;                   // 772 I2C touch address, 0x4B:RVP   0x4A:FFRD
+  UINT8       IdleReserve;                       // 773  0 - disabled 1 - enabled
+  UINT8       SDIOMode;                          // 774  3 - Default  2 - DDR50
+  UINT8       emmcVersion;                       // 775  0 - 4.41 1 - 4.5
+  UINT32      BmBound;                           // 776 BM Bound
+  UINT8       FsaStatus;                         // 780 0 - Fsa is off, 1- Fsa is on
+
+  //
+  // Board Id
+  // This field is for the ASL code to know whether this board is Baylake or Bayley Bay etc
+  //
+  UINT8       BoardID;                           //  781
+  UINT8       FabID;                             // 782
+  UINT8       OtgMode;                           // 783 0- OTG disable 1- OTG PCI mode
+  UINT8       Stepping;                          //  784 Stepping
+  UINT8       WittEnable;                        // 785 WITT eanble 0 - disable 1 - enable
+
+  UINT8       SocStepping;                       // 786 Soc Stepping infomation
+  UINT8       AmbientTripPointChange;            // 787 DPTF: Controls whether _ATI changes other participant's trip point(enabled/disabled)
+  UINT8       UtsEnable;                         // 788 Uart Test eanble 0 - disable 1 - enable 
+  UINT8          DptfReserve;             // 789  
+
+  UINT8       SarEnable;                          // 790
+  UINT8       PssDeveice;                        // 791 PSS Deveice: 0 - None, 1 - Monzax 2K, 2 - Monzax 8K
+  UINT8       EDPV;                              // 792 Check for eDP display device
+  UINT32      DIDX;                              // 793 Device ID for eDP device
+  UINT8       MicrosoftIoT;                      // (794)JP1 pins are for Microsoft IoT project.
+} EFI_GLOBAL_NVS_AREA;
+#pragma pack ()
+
+//
+// Global NVS Area Protocol
+//
+typedef struct _EFI_GLOBAL_NVS_AREA_PROTOCOL {
+  EFI_GLOBAL_NVS_AREA     *Area;
+} EFI_GLOBAL_NVS_AREA_PROTOCOL;
+
+#endif

diff --git a/Vlv2TbltDevicePkg/Include/Protocol/HwWatchdogTimer.h b/Vlv2TbltDevicePkg/Include/Protocol/HwWatchdogTimer.h
new file mode 100644 (file)
index 0000000..75c7071
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Include/Protocol/HwWatchdogTimer.h
@@ -0,0 +1,240 @@
+/*++\r
+\r
+  Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+\r
+Module Name:\r
+\r
+  HwWatchdogTimer.h\r
+\r
+Abstract:\r
+\r
+\r
+--*/\r
+\r
+#ifndef __EFI_WATCHDOG_TIMER_DRIVER_PROTOCOL_H__\r
+#define __EFI_WATCHDOG_TIMER_DRIVER_PROTOCOL_H__\r
+\r
+#define EFI_WATCHDOG_TIMER_DRIVER_PROTOCOL_GUID \\r
+  { 0xd5b06d16, 0x2ea1, 0x4def, 0x98, 0xd0, 0xa0, 0x5d, 0x40, 0x72, 0x84, 0x17 }\r
+\r
+#define EFI_WATCHDOG_TIMER_NOT_SUPPORTED_PROTOCOL_GUID \\r
+  { 0xe9e156ac, 0x3203, 0x4572, 0xac, 0xdf, 0x84, 0x4f, 0xdc, 0xdb, 0x6, 0xbf }\r
+\r
+\r
+#include <Guid/HwWatchdogTimerHob.h>\r
+\r
+//\r
+// General Purpose Constants\r
+//\r
+#define ICH_INSTAFLUSH_GPIO      BIT16 // BIT 16 in GPIO Level 2 is GPIO 48.\r
+#define B_INSTAFLUSH             BIT4\r
+\r
+//\r
+// Other Watchdog timer values\r
+//\r
+#define WDT_COUNTDOWN_VALUE                 0x14\r
+#define BDS_WDT_COUNTDOWN_VALUE             0x35\r
+\r
+//\r
+// Prototypes for the Watchdog Timer Driver Protocol\r
+//\r
+\r
+/**\r
+  This service begins the Watchdog Timer countdown.  If the countdown completes prior to\r
+  Stop Timer or Restart Timer the system will reset.\r
+\r
+  @param[in] None\r
+\r
+  @retval EFI_SUCCESS        Operation completed successfully\r
+  @retval EFI_DEVICE_ERROR   The command was unsuccessful\r
+\r
+**/\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *EFI_WATCHDOG_START_TIMER) (\r
+  VOID\r
+  );\r
+\r
+/**\r
+  This service resets the Watchdog Timer countdown and should only be called after the\r
+  Start Timer function.\r
+\r
+  @param[in] None\r
+\r
+  @retval EFI_SUCCESS        Operation completed successfully\r
+  @retval EFI_DEVICE_ERROR   The command was unsuccessful\r
+\r
+**/\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *PEI_WATCHDOG_RESET_TIMER) (\r
+  VOID\r
+  );\r
+\r
+/**\r
+  This service restarts the Watchdog Timer countdown and should only be called after the\r
+  Start Timer function.\r
+\r
+  @param[in] None\r
+\r
+  @retval EFI_SUCCESS        Operation completed successfully\r
+  @retval EFI_DEVICE_ERROR   The command was unsuccessful\r
+\r
+**/\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *EFI_WATCHDOG_RESTART_TIMER) (\r
+  VOID\r
+  );\r
+\r
+/**\r
+  This service disables the Watchdog Timer countdown.\r
+\r
+  @param[in] None\r
+\r
+  @retval EFI_SUCCESS        Operation completed successfully\r
+  @retval EFI_DEVICE_ERROR   The command was unsuccessful\r
+\r
+**/\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *EFI_WATCHDOG_STOP_TIMER) (\r
+  VOID\r
+  );\r
+\r
+/**\r
+\r
+**/\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *EFI_WATCHDOG_CHECK_TIMEOUT) (\r
+  OUT HW_WATCHDOG_TIMEOUT       *WatchdogTimeout\r
+  );\r
+\r
+\r
+\r
+/**\r
+  This service forces a reboot of the system due to a reset of the POWERGOOD_PS,\r
+  POWERGOOD_CLK, and the BSEL Override\r
+\r
+  Arguments:\r
+    None\r
+\r
+  Returns:\r
+    This function should not return!\r
+\r
+    EFI_DEVICE_ERROR  - The command was unsuccessful and a reboot did not occur\r
+\r
+**/\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *EFI_WATCHDOG_FORCE_REBOOT) (\r
+  IN BOOLEAN                    ForceTimeout,\r
+  IN UINT8                      ResetType\r
+  );\r
+\r
+/**\r
+  This service notifies the Watchdog Timer of the fact that a known reset is occuring.\r
+\r
+  @param[in] AllowReset  TRUE if a Reset is currently expected\r
+                         FALSE if a Reset is not currently expected\r
+\r
+    This function should not return!\r
+\r
+    EFI_DEVICE_ERROR  - The command was unsuccessful and a reboot did not occur\r
+\r
+**/\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *EFI_WATCHDOG_KNOWN_RESET) (\r
+  IN BOOLEAN                    AllowReset\r
+  );\r
+\r
+/**\r
+  This service reads the current Watchdog Timer countdown reload value.\r
+\r
+  @param[in] CountdownValue      pointer to UINT32 to return the value of the reload register.\r
+\r
+  @retval    EFI_SUCCESS         Operation completed successfully\r
+  @retval    EFI_DEVICE_ERROR    The command was unsuccessful\r
+\r
+**/\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *EFI_GET_TIMER_COUNT_DOWN_PERIOD)(\r
+  OUT UINT32      *CountdownValue\r
+  );\r
+\r
+/**\r
+  This service reads the current Watchdog Timer countdown reload value.\r
+\r
+  @param[in] CountdownValue  Value to set the reload register.\r
+\r
+  @retval EFI_SUCCESS        Operation completed successfully\r
+  @retval EFI_DEVICE_ERROR   The command was unsuccessful\r
+\r
+**/\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *EFI_SET_TIMER_COUNT_DOWN_PERIOD)(\r
+  OUT UINT32      CountdownValue\r
+  );\r
+\r
+/**\r
+  This service clears the state that indicates the Watchdog Timer fired.\r
+\r
+  @retval EFI_SUCCESS       - Operation completed successfully\r
+  @retval EFI_DEVICE_ERROR  - The command was unsuccessful\r
+\r
+**/\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *PEI_WATCHDOG_CLEAR_TIMER_STATE) (\r
+  );\r
+\r
+/**\r
+  This service disables the Watchdog Timer countdown.  It also closes the recurring restart event\r
+  if the event exists.\r
+\r
+  @param[in] Stall  TRUE = Stop the timer countdown\r
+                    FALSE = Start the timer countdown\r
+\r
+  @retval  EFI_SUCCESS        Operation completed successfully\r
+  @retval  EFI_DEVICE_ERROR   The command was unsuccessful\r
+\r
+**/\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *EFI_STALL_WATCHDOG_COUNTDOWN) (\r
+  IN BOOLEAN Stall\r
+  );\r
+\r
+\r
+typedef struct _EFI_WATCHDOG_TIMER_DRIVER_PROTOCOL {\r
+  EFI_WATCHDOG_START_TIMER                      StartWatchdogTimer;\r
+  PEI_WATCHDOG_RESET_TIMER                      ResetWatchdogTimeout;\r
+  EFI_WATCHDOG_RESTART_TIMER                    RestartWatchdogTimer;\r
+  EFI_WATCHDOG_STOP_TIMER                       StopWatchdogTimer;\r
+  EFI_WATCHDOG_CHECK_TIMEOUT                    CheckWatchdogTimeout;\r
+  EFI_WATCHDOG_FORCE_REBOOT                     ForceReboot;\r
+  EFI_WATCHDOG_KNOWN_RESET                      AllowKnownReset;\r
+  EFI_GET_TIMER_COUNT_DOWN_PERIOD               GetCountdownPeriod;\r
+  EFI_SET_TIMER_COUNT_DOWN_PERIOD               SetCountdownPeriod;\r
+  PEI_WATCHDOG_CLEAR_TIMER_STATE                ClearTimerState;\r
+  EFI_STALL_WATCHDOG_COUNTDOWN                  StallWatchdogCountdown;\r
+} EFI_WATCHDOG_TIMER_DRIVER_PROTOCOL;\r
+\r
+extern EFI_GUID gEfiWatchdogTimerDriverProtocolGuid;\r
+extern EFI_GUID gEfiWatchdogTimerNotSupportedProtocolGuid;\r
+\r
+#endif\r

diff --git a/Vlv2TbltDevicePkg/Include/Protocol/I2cAcpi.h b/Vlv2TbltDevicePkg/Include/Protocol/I2cAcpi.h
new file mode 100644 (file)
index 0000000..14a0b70
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Include/Protocol/I2cAcpi.h
@@ -0,0 +1,112 @@
+/*++\r
+\r
+  Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+\r
+**/\r
+\r
+#ifndef __I2C_ACPI_H__\r
+#define __I2C_ACPI_H__\r
+\r
+#include <Protocol/DevicePath.h>\r
+\r
+//\r
+// I2C ACPI protocol\r
+//\r
+typedef struct _EFI_I2C_ACPI_PROTOCOL   EFI_I2C_ACPI_PROTOCOL;\r
+\r
+//\r
+// I2C device description\r
+//\r
+// This structure provides the platform specific information which\r
+// describes an I2C device.\r
+//\r
+typedef struct {\r
+  //\r
+  // Hardware revision - ACPI _HRV value\r
+  //\r
+  UINT32 HardwareRevision;\r
+\r
+  //\r
+  // Device path node for the I2C device.\r
+  //\r
+  CONST EFI_DEVICE_PATH_PROTOCOL *DevicePath;\r
+\r
+  //\r
+  // I2C bus configuration for the I2C device.\r
+  //\r
+  UINT32 I2cBusConfiguration;\r
+\r
+  //\r
+  // Number of slave addresses for the I2C device.\r
+  //\r
+  UINT32 SlaveAddressCount;\r
+\r
+  //\r
+  // Address of the array of slave addresses for the I2C device.\r
+  //\r
+  CONST UINT32 *SlaveAddressArray;\r
+}EFI_I2C_DEVICE;\r
+\r
+\r
+/**\r
+  Enumerate the I2C devices\r
+\r
+  This routine must be called at or below TPL_NOTIFY.\r
+\r
+  This function walks the platform specific data to enumerates the\r
+  I2C devices on an I2C bus.\r
+\r
+  @param[in]  This              Address of an EFI_I2C_ENUM_PROTOCOL\r
+                                structure.\r
+  @param[in, out] Device        Buffer containing the address of an\r
+                                EFI_I2C_DEVICE structure.  Enumeration\r
+                                is started by setting the initial\r
+                                EFI_I2C_DEVICE structure address to NULL.\r
+                                The buffer receives an EFI_I2C_DEVICE\r
+                                structure address for the next I2C device.\r
+\r
+  @retval EFI_SUCCESS           The platform data for the next device\r
+                                on the I2C bus was returned successfully.\r
+  @retval EFI_INVALID_PARAMETER NextDevice was NULL\r
+  @retval EFI_NO_MAPPING        PreviousDevice does not point to a valid\r
+                                EFI_I2C_DEVICE structure.\r
+\r
+**/\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *EFI_I2C_ACPI_ENUMERATE) (\r
+  IN CONST EFI_I2C_ACPI_PROTOCOL *This,\r
+  IN OUT CONST EFI_I2C_DEVICE **Device\r
+  );\r
+\r
+//\r
+// I2C device description\r
+//\r
+// This structure provides the platform specific information which\r
+// describes an I2C device.\r
+//\r
+struct _EFI_I2C_ACPI_PROTOCOL {\r
+  //\r
+  // Walk the platform's list of I2C devices on the bus.  This\r
+  // routine returns the next I2C device in the platform's list\r
+  // for this I2C bus.\r
+  //\r
+  EFI_I2C_ACPI_ENUMERATE Enumerate;\r
+};\r
+\r
+//\r
+// Variable containing the GUID for the I2C device enumeration protocol\r
+//\r
+extern EFI_GUID gEfiI2cAcpiProtocolGuid;\r
+\r
+#endif  //  __I2C_ACPI_H__\r

diff --git a/Vlv2TbltDevicePkg/Include/Protocol/I2cBus.h b/Vlv2TbltDevicePkg/Include/Protocol/I2cBus.h
new file mode 100644 (file)
index 0000000..d32837a
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Include/Protocol/I2cBus.h
@@ -0,0 +1,169 @@
+/*++\r
+\r
+  Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+**/\r
+\r
+#ifndef __I2C_BUS_H__\r
+#define __I2C_BUS_H__\r
+\r
+#include <Protocol/I2cHostMcg.h>\r
+\r
+//\r
+// I2C bus protocol\r
+//\r
+typedef struct _EFI_I2C_BUS_PROTOCOL  EFI_I2C_BUS_PROTOCOL;\r
+\r
+\r
+/**\r
+  Perform an I2C operation on the device\r
+\r
+  This routine must be called at or below TPL_NOTIFY.  For synchronous\r
+  requests this routine must be called at or below TPL_CALLBACK.\r
+\r
+  N.B. The typical consumers of this API are the third party I2C\r
+  drivers.  Extreme care must be taken by other consumers of this\r
+  API to prevent confusing the third party I2C drivers due to a\r
+  state change at the I2C device which the third party I2C drivers\r
+  did not initiate.  I2C platform drivers may use this API within\r
+  these guidelines.\r
+\r
+  This routine queues an operation to the I2C controller for execution\r
+  on the I2C bus.\r
+\r
+  As an upper layer driver writer, the following need to be provided\r
+  to the platform vendor:\r
+\r
+  1.  ACPI CID value or string - this is used to connect the upper layer\r
+      driver to the device.\r
+  2.  Slave address array guidance when the I2C device uses more than one\r
+      slave address.  This is used to access the blocks of hardware within\r
+      the I2C device.\r
+\r
+  @param[in] This               Address of an EFI_I2C_BUS_PROTOCOL\r
+                                structure\r
+  @param[in] SlaveAddressIndex  Index into an array of slave addresses for\r
+                                the I2C device.  The values in the array are\r
+                                specified by the board designer, with the\r
+                                I2C device driver writer providing the slave\r
+                                address order.\r
+\r
+                                For devices that have a single slave address,\r
+                                this value must be zero.  If the I2C device\r
+                                uses more than one slave address then the third\r
+                                party (upper level) I2C driver writer needs to\r
+                                specify the order of entries in the slave address\r
+                                array.\r
+\r
+                                \ref ThirdPartyI2cDrivers "Third Party I2C Drivers"\r
+                                section in I2cMaster.h.\r
+  @param[in] Event              Event to set for asynchronous operations,\r
+                                NULL for synchronous operations\r
+  @param[in] RequestPacket      Address of an EFI_I2C_REQUEST_PACKET\r
+                                structure describing the I2C operation\r
+  @param[out] I2cStatus         Optional buffer to receive the I2C operation\r
+                                completion status\r
+\r
+  @retval EFI_SUCCESS           The operation completed successfully.\r
+  @retval EFI_ABORTED           The request did not complete because the driver\r
+                                was shutdown.\r
+  @retval EFI_ACCESS_DENIED     Invalid SlaveAddressIndex value\r
+  @retval EFI_BAD_BUFFER_SIZE   The WriteBytes or ReadBytes buffer size is too large.\r
+  @retval EFI_DEVICE_ERROR      There was an I2C error (NACK) during the operation.\r
+                                This could indicate the slave device is not present.\r
+  @retval EFI_INVALID_PARAMETER RequestPacket is NULL\r
+  @retval EFI_INVALID_PARAMETER TPL is too high\r
+  @retval EFI_NO_RESPONSE       The I2C device is not responding to the\r
+                                slave address.  EFI_DEVICE_ERROR may also be\r
+                                returned if the controller can not distinguish\r
+                                when the NACK occurred.\r
+  @retval EFI_NOT_FOUND         I2C slave address exceeds maximum address\r
+  @retval EFI_NOT_READY         I2C bus is busy or operation pending, wait for\r
+                                the event and then read status pointed to by\r
+                                the request packet.\r
+  @retval EFI_OUT_OF_RESOURCES  Insufficient memory for I2C operation\r
+  @retval EFI_TIMEOUT           The transaction did not complete within an internally\r
+                                specified timeout period.\r
+\r
+**/\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *EFI_I2C_BUS_START_REQUEST) (\r
+  IN CONST EFI_I2C_BUS_PROTOCOL *This,\r
+  IN UINTN SlaveAddressIndex,\r
+  IN EFI_EVENT Event OPTIONAL,\r
+  IN CONST EFI_I2C_REQUEST_PACKET *RequestPacket,\r
+  OUT EFI_STATUS *I2cStatus OPTIONAL\r
+  );\r
+\r
+//\r
+// The I2C bus protocol enables access to a specific device on the I2C bus.\r
+//\r
+// Each I2C device is described as an ACPI node (HID, UID and CID) within the\r
+// platform layer.  The I2C bus protocol enumerates the I2C devices in the\r
+// platform and creates a unique handle and device path for each I2C device.\r
+//\r
+// I2C slave addressing is abstracted to validate addresses and limit operation\r
+// to the specified I2C device.  The third party providing the I2C device support\r
+// provides an ordered list of slave addresses for the I2C device to the team\r
+// building the platform layer.  The platform team must preserve the order of the\r
+// supplied list.  SlaveAddressCount is the number of entries in this list or\r
+// array within the platform layer.  The third party device support references\r
+// a slave address using an index into the list or array in the range of zero\r
+// to SlaveAddressCount - 1.\r
+//\r
+struct _EFI_I2C_BUS_PROTOCOL {\r
+  //\r
+  // Start an I2C operation on the bus\r
+  //\r
+  EFI_I2C_BUS_START_REQUEST StartRequest;\r
+\r
+  //\r
+  // The maximum number of slave addresses for the I2C device.  The caller may\r
+  // validate this value as a check on the platform layer's configuration.  Slave\r
+  // address selection uses an index value in the range of zero to SlaveAddressCount - 1.\r
+  //\r
+  UINTN SlaveAddressCount;\r
+\r
+  //\r
+  // Hardware revision - Matches the ACPI _HRV value\r
+  //\r
+  // The HardwareRevision value allows a single driver to support multiple hardware\r
+  // revisions and implement the necessary workarounds for limitations within the\r
+  // hardware.\r
+  //\r
+  UINT32 HardwareRevision;\r
+\r
+  //\r
+  // The maximum number of bytes the I2C host controller\r
+  // is able to receive from the I2C bus.\r
+  //\r
+  UINT32 MaximumReceiveBytes;\r
+\r
+  //\r
+  // The maximum number of bytes the I2C host controller\r
+  // is able to send on the I2C bus.\r
+  //\r
+  UINT32 MaximumTransmitBytes;\r
+\r
+  //\r
+  // The maximum number of bytes in the I2C bus transaction.\r
+  //\r
+  UINT32 MaximumTotalBytes;\r
+};\r
+\r
+//\r
+// GUID for the I2C bus protocol\r
+//\r
+extern EFI_GUID gEfiI2cBusProtocolGuid;\r
+\r
+#endif  //  __I2C_BUS_H__\r

diff --git a/Vlv2TbltDevicePkg/Include/Protocol/I2cBusMcg.h b/Vlv2TbltDevicePkg/Include/Protocol/I2cBusMcg.h
new file mode 100644 (file)
index 0000000..0fcadd5
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Include/Protocol/I2cBusMcg.h
@@ -0,0 +1,168 @@
+/*++\r
+\r
+  Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+**/\r
+\r
+#ifndef __I2C_BUS_H__\r
+#define __I2C_BUS_H__\r
+\r
+#include <Protocol/I2cHostMcg.h>\r
+\r
+//\r
+// I2C bus protocol\r
+//\r
+typedef struct _EFI_I2C_BUS_PROTOCOL  EFI_I2C_BUS_PROTOCOL;\r
+\r
+/**\r
+  Perform an I2C operation on the device\r
+\r
+  This routine must be called at or below TPL_NOTIFY.  For synchronous\r
+  requests this routine must be called at or below TPL_CALLBACK.\r
+\r
+  N.B. The typical consumers of this API are the third party I2C\r
+  drivers.  Extreme care must be taken by other consumers of this\r
+  API to prevent confusing the third party I2C drivers due to a\r
+  state change at the I2C device which the third party I2C drivers\r
+  did not initiate.  I2C platform drivers may use this API within\r
+  these guidelines.\r
+\r
+  This routine queues an operation to the I2C controller for execution\r
+  on the I2C bus.\r
+\r
+  As an upper layer driver writer, the following need to be provided\r
+  to the platform vendor:\r
+\r
+  1.  ACPI CID value or string - this is used to connect the upper layer\r
+      driver to the device.\r
+  2.  Slave address array guidance when the I2C device uses more than one\r
+      slave address.  This is used to access the blocks of hardware within\r
+      the I2C device.\r
+\r
+  @param[in] This               Address of an EFI_I2C_BUS_PROTOCOL\r
+                                structure\r
+  @param[in] SlaveAddressIndex  Index into an array of slave addresses for\r
+                                the I2C device.  The values in the array are\r
+                                specified by the board designer, with the\r
+                                I2C device driver writer providing the slave\r
+                                address order.\r
+\r
+                                For devices that have a single slave address,\r
+                                this value must be zero.  If the I2C device\r
+                                uses more than one slave address then the third\r
+                                party (upper level) I2C driver writer needs to\r
+                                specify the order of entries in the slave address\r
+                                array.\r
+\r
+                                \ref ThirdPartyI2cDrivers "Third Party I2C Drivers"\r
+                                section in I2cMaster.h.\r
+  @param[in] Event              Event to set for asynchronous operations,\r
+                                NULL for synchronous operations\r
+  @param[in] RequestPacket      Address of an EFI_I2C_REQUEST_PACKET\r
+                                structure describing the I2C operation\r
+  @param[out] I2cStatus         Optional buffer to receive the I2C operation\r
+                                completion status\r
+\r
+  @retval EFI_SUCCESS           The operation completed successfully.\r
+  @retval EFI_ABORTED           The request did not complete because the driver\r
+                                was shutdown.\r
+  @retval EFI_ACCESS_DENIED     Invalid SlaveAddressIndex value\r
+  @retval EFI_BAD_BUFFER_SIZE   The WriteBytes or ReadBytes buffer size is too large.\r
+  @retval EFI_DEVICE_ERROR      There was an I2C error (NACK) during the operation.\r
+                                This could indicate the slave device is not present.\r
+  @retval EFI_INVALID_PARAMETER RequestPacket is NULL\r
+  @retval EFI_INVALID_PARAMETER TPL is too high\r
+  @retval EFI_NO_RESPONSE       The I2C device is not responding to the\r
+                                slave address.  EFI_DEVICE_ERROR may also be\r
+                                returned if the controller can not distinguish\r
+                                when the NACK occurred.\r
+  @retval EFI_NOT_FOUND         I2C slave address exceeds maximum address\r
+  @retval EFI_NOT_READY         I2C bus is busy or operation pending, wait for\r
+                                the event and then read status pointed to by\r
+                                the request packet.\r
+  @retval EFI_OUT_OF_RESOURCES  Insufficient memory for I2C operation\r
+  @retval EFI_TIMEOUT           The transaction did not complete within an internally\r
+                                specified timeout period.\r
+\r
+**/\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *EFI_I2C_BUS_START_REQUEST) (\r
+  IN CONST EFI_I2C_BUS_PROTOCOL *This,\r
+  IN UINTN SlaveAddressIndex,\r
+  IN EFI_EVENT Event OPTIONAL,\r
+  IN CONST EFI_I2C_REQUEST_PACKET *RequestPacket,\r
+  OUT EFI_STATUS *I2cStatus OPTIONAL\r
+  );\r
+\r
+//\r
+// The I2C bus protocol enables access to a specific device on the I2C bus.\r
+//\r
+// Each I2C device is described as an ACPI node (HID, UID and CID) within the\r
+// platform layer.  The I2C bus protocol enumerates the I2C devices in the\r
+// platform and creates a unique handle and device path for each I2C device.\r
+//\r
+// I2C slave addressing is abstracted to validate addresses and limit operation\r
+// to the specified I2C device.  The third party providing the I2C device support\r
+// provides an ordered list of slave addresses for the I2C device to the team\r
+// building the platform layer.  The platform team must preserve the order of the\r
+// supplied list.  SlaveAddressCount is the number of entries in this list or\r
+// array within the platform layer.  The third party device support references\r
+// a slave address using an index into the list or array in the range of zero\r
+// to SlaveAddressCount - 1.\r
+//\r
+struct _EFI_I2C_BUS_PROTOCOL {\r
+  //\r
+  // Start an I2C operation on the bus\r
+  //\r
+  EFI_I2C_BUS_START_REQUEST StartRequest;\r
+\r
+  //\r
+  // The maximum number of slave addresses for the I2C device.  The caller may\r
+  // validate this value as a check on the platform layer's configuration.  Slave\r
+  // address selection uses an index value in the range of zero to SlaveAddressCount - 1.\r
+  //\r
+  UINTN SlaveAddressCount;\r
+\r
+  //\r
+  // Hardware revision - Matches the ACPI _HRV value\r
+  //\r
+  // The HardwareRevision value allows a single driver to support multiple hardware\r
+  // revisions and implement the necessary workarounds for limitations within the\r
+  // hardware.\r
+  //\r
+  UINT32 HardwareRevision;\r
+\r
+  //\r
+  // The maximum number of bytes the I2C host controller\r
+  // is able to receive from the I2C bus.\r
+  ///\r
+  UINT32 MaximumReceiveBytes;\r
+\r
+  //\r
+  // The maximum number of bytes the I2C host controller\r
+  // is able to send on the I2C bus.\r
+  //\r
+  UINT32 MaximumTransmitBytes;\r
+\r
+  //\r
+  // The maximum number of bytes in the I2C bus transaction.\r
+  //\r
+  UINT32 MaximumTotalBytes;\r
+};\r
+\r
+//\r
+// GUID for the I2C bus protocol\r
+//\r
+extern EFI_GUID gEfiI2cBusProtocolGuid;\r
+\r
+#endif  //  __I2C_BUS_H__\r

diff --git a/Vlv2TbltDevicePkg/Include/Protocol/I2cHostMcg.h b/Vlv2TbltDevicePkg/Include/Protocol/I2cHostMcg.h
new file mode 100644 (file)
index 0000000..3395043
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Include/Protocol/I2cHostMcg.h
@@ -0,0 +1,143 @@
+/*++\r
+\r
+  Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+**/\r
+\r
+#ifndef __I2C_HOST_H__\r
+#define __I2C_HOST_H__\r
+\r
+#include <Protocol/I2cMasterMcg.h>\r
+\r
+/**\r
+  Declare the forward references\r
+\r
+**/\r
+typedef struct _EFI_I2C_HOST_PROTOCOL EFI_I2C_HOST_PROTOCOL;\r
+typedef struct _EFI_I2C_HOST_CALLBACKS EFI_I2C_HOST_CALLBACKS;\r
+\r
+\r
+/**\r
+  Queue an I2C operation for execution on the I2C controller.\r
+\r
+  This routine must be called at or below TPL_NOTIFY.  For synchronous\r
+  requests this routine must be called at or below TPL_CALLBACK.\r
+\r
+  N.B. The typical consumers of this API are the I2C bus driver and\r
+  on rare occasions the I2C test application.  Extreme care must be\r
+  taken by other consumers of this API to prevent confusing the\r
+  third party I2C drivers due to a state change at the I2C device\r
+  which the third party I2C drivers did not initiate.  I2C platform\r
+  drivers may use this API within these guidelines.\r
+\r
+  This layer uses the concept of I2C bus configurations to describe\r
+  the I2C bus.  An I2C bus configuration is defined as a unique\r
+  setting of the multiplexers and switches in the I2C bus which\r
+  enable access to one or more I2C devices.  When using a switch\r
+  to divide a bus, due to speed differences, the I2C platform layer\r
+  would define an I2C bus configuration for the I2C devices on each\r
+  side of the switch.  When using a multiplexer, the I2C platform\r
+  layer defines an I2C bus configuration for each of the selector\r
+  values required to control the multiplexer.  See Figure 1 in the\r
+  <a href="http://www.nxp.com/documents/user_manual/UM10204.pdf">I<sup>2</sup>C\r
+  Specification</a> for a complex I2C bus configuration.\r
+\r
+  The I2C host driver processes all operations in FIFO order.  Prior to\r
+  performing the operation, the I2C host driver calls the I2C platform\r
+  driver to reconfigure the switches and multiplexers in the I2C bus\r
+  enabling access to the specified I2C device.  The I2C platform driver\r
+  also selects the maximum bus speed for the device.  After the I2C bus\r
+  is configured, the I2C host driver calls the I2C port driver to\r
+  initialize the I2C controller and start the I2C operation.\r
+\r
+  @param[in] This             Address of an EFI_I2C_HOST_PROTOCOL instance.\r
+  @param[in] I2cBusConfiguration  I2C bus configuration to access the I2C\r
+                                  device.\r
+  @param[in] SlaveAddress     Address of the device on the I2C bus.\r
+  @param[in] Event            Event to set for asynchronous operations,\r
+                              NULL for synchronous operations\r
+  @param[in] RequestPacket    Address of an EFI_I2C_REQUEST_PACKET\r
+                              structure describing the I2C operation\r
+  @param[out] I2cStatus       Optional buffer to receive the I2C operation\r
+                              completion status\r
+\r
+  @retval EFI_SUCCESS           The operation completed successfully.\r
+  @retval EFI_ABORTED           The request did not complete because the driver\r
+                                was shutdown.\r
+  @retval EFI_BAD_BUFFER_SIZE   The WriteBytes or ReadBytes buffer size is too large.\r
+  @retval EFI_DEVICE_ERROR      There was an I2C error (NACK) during the operation.\r
+                                This could indicate the slave device is not present.\r
+  @retval EFI_INVALID_PARAMETER RequestPacket is NULL\r
+  @retval EFI_INVALID_PARAMETER TPL is too high\r
+  @retval EFI_NO_MAPPING        Invalid I2cBusConfiguration value\r
+  @retval EFI_NO_RESPONSE       The I2C device is not responding to the\r
+                                slave address.  EFI_DEVICE_ERROR may also be\r
+                                returned if the controller cannot distinguish\r
+                                when the NACK occurred.\r
+  @retval EFI_NOT_FOUND         I2C slave address exceeds maximum address\r
+  @retval EFI_NOT_READY         I2C bus is busy or operation pending, wait for\r
+                                the event and then read status pointed to by\r
+                                the request packet.\r
+  @retval EFI_OUT_OF_RESOURCES  Insufficient memory for I2C operation\r
+  @retval EFI_TIMEOUT           The transaction did not complete within an internally\r
+                                specified timeout period.\r
+\r
+**/\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *EFI_I2C_HOST_QUEUE_REQUEST) (\r
+  IN CONST EFI_I2C_HOST_PROTOCOL *This,\r
+  IN UINTN I2cBusConfiguration,\r
+  IN UINTN SlaveAddress,\r
+  IN EFI_EVENT Event OPTIONAL,\r
+  IN CONST EFI_I2C_REQUEST_PACKET *RequestPacket,\r
+  OUT EFI_STATUS *I2cStatus OPTIONAL\r
+  );\r
+\r
+///\r
+/// Host access to the I2C bus.\r
+///\r
+struct _EFI_I2C_HOST_PROTOCOL {\r
+  ///\r
+  /// Queue an operation for execution on the I2C bus\r
+  ///\r
+  EFI_I2C_HOST_QUEUE_REQUEST QueueRequest;\r
+\r
+  ///\r
+  /// The maximum number of I2C bus configurations\r
+  ///\r
+  UINTN I2cBusConfigurationCount;\r
+\r
+  ///\r
+  /// The maximum number of bytes the I2C host controller\r
+  /// is able to receive from the I2C bus.\r
+  ///\r
+  UINT32 MaximumReceiveBytes;\r
+\r
+  ///\r
+  /// The maximum number of bytes the I2C host controller\r
+  /// is able to send on the I2C bus.\r
+  ///\r
+  UINT32 MaximumTransmitBytes;\r
+\r
+  ///\r
+  /// The maximum number of bytes in the I2C bus transaction.\r
+  ///\r
+  UINT32 MaximumTotalBytes;\r
+};\r
+\r
+///\r
+/// GUID for the EFI_I2C_HOST_PROTOCOL\r
+///\r
+extern EFI_GUID gEfiI2cHostProtocolGuid;\r
+\r
+#endif  //  __I2C_HOST_H__\r

diff --git a/Vlv2TbltDevicePkg/Include/Protocol/I2cMasterMcg.h b/Vlv2TbltDevicePkg/Include/Protocol/I2cMasterMcg.h
new file mode 100644 (file)
index 0000000..f239b5e
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Include/Protocol/I2cMasterMcg.h
@@ -0,0 +1,524 @@
+/*++\r
+\r
+  Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+\r
+  \section I2cDriverStack       I2C Driver Stack\r
+\r
+  The following is a representation of the I<sup>2</sup>C (I2C)\r
+  driver stack and an I2C bus layout.\r
+\r
+  <code><pre>\r
+              +-----------------+\r
+              |   Application   |\r
+              +-----------------+\r
+                       |\r
+                       | Third Party or UEFI\r
+                       |\r
+                       V\r
+ +--------+   +-----------------+\r
+ | Slave  |   |   Third Party   |\r
+ | Driver |   |   I2C Device    |\r
+ |        |   |     Driver      |\r
+ +--------+   +-----------------+\r
+      |                |\r
+      |          BUS   |\r
+      |                |\r
+      |                V\r
+      |       +-----------------+\r
+      |       | I2C Bus Driver  |------------------.\r
+      |       +-----------------+                  |\r
+      |                |                           |\r
+      |         HOST   |          BUS              |\r
+      |                |          CONFIGURATION    |\r
+SLAVE |                V          MANAGEMENT       | ACPI\r
+      |       +-----------------+                  |\r
+      |       | I2C Host Driver |----------.       |\r
+      |       +-----------------+          |       |\r
+      |                |                   |       |\r
+      |        MASTER  |                   V       V\r
+      |                |               +-------=-------------+\r
+      |                V               | I2C Platform Driver |\r
+      |       +-----------------+      +---------------------+\r
+      `------>| I2C Port Driver |               |      |\r
+              +-----------------+               |      |\r
+                       |                        |      |\r
+            Software   |                        |      |\r
+            --------------------------------------------------\r
+            Hardware   |                        |      |\r
+                       |                        |      |\r
+                       V                        |      |\r
+              +-----------------+               |      |\r
+              | I2C Controller  |               |      |\r
+              +-----------------+               |      |\r
+                       |                        |      |\r
+            -----------------------             |      |\r
+            I2C Bus    |                        |      |\r
+                       |    +------------+      |      |\r
+                       +----| High speed |      |      |\r
+                       |    | I2C device |      |      |\r
+                       |    |    0x01    |      |      |\r
+                       |    +------------+      |      |\r
+                       |                        |      |\r
+                  +---------+  0                |      |\r
+                  | Switch  |<------------------`      |\r
+                  +---------+  1                       |\r
+                       |                               |\r
+                       |    +------------+             |\r
+                       +----| Fast speed |             |\r
+                       |    | I2C device |             |\r
+                       |    |    0x02    |             |\r
+                       |    +------------+             |\r
+                       |                               |\r
+                +-------------+                        |\r
+                | Multiplexer |<-----------------------`\r
+                +-------------+\r
+                 0 |       | 1\r
+                   |       |\r
+                   |       |\r
+                   |       |    +-------------+\r
+                   |       +----| Third Party |\r
+                   |       |    | I2C Device  |\r
+                   |       |    |  0x03, 0x04 |\r
+                   |       |    +-------------+\r
+                   |       |\r
+                   |\r
+                   |            +-------------+\r
+                   +------------| Third Party |\r
+                   |            | I2C Device  |\r
+                   |            |  0x03, 0x04 |\r
+                   |            +-------------+\r
+                   |\r
+  </pre></code>\r
+\r
+  The platform hardware designer chooses the bus layout based upon\r
+  the platform, I2C chip and software requirements.  The design uses\r
+  switches to truncate the bus to enable higher speed operation for a\r
+  subset of devices which are placed closer to the controller.  When the\r
+  switch is on, the extended bus must operate at a lower speed.  The\r
+  design uses multiplexer to create separate address spaces enabling\r
+  the use of multiple devices which would otherwise have conflicting\r
+  addresses. See the\r
+  <a href="http://www.nxp.com/documents/user_manual/UM10204.pdf">I<sup>2</sup>C\r
+  Specification</a> for more details.\r
+\r
+  N.B. Some operating systems may prohibit the changing of switches\r
+  and multiplexers in the I2C bus.  In this case the platform hardware\r
+  and software designers must select a single I2C bus configuration\r
+  consisting of constant input values for the switches and multiplexers.\r
+  The platform software designer must then ensure that this I2C bus\r
+  configuration is enabled prior to passing control to the operating\r
+  system.\r
+\r
+  The platform hardware designer needs to provide the platform software\r
+  designer the following data for each I2C bus:\r
+\r
+  1.  Which controller controls this bus\r
+\r
+  2.  A list of logic blocks contained in one or more I2C devices:\r
+\r
+      a.  I2C device which contains this logic block\r
+\r
+      b.  Logic block slave address\r
+\r
+      c.  Logic block name\r
+\r
+  3.  For each configuration of the switches and multiplexer\r
+\r
+      a.  What is the maximum speed of operation\r
+\r
+      b.  What devices are accessible\r
+\r
+  4.  The settings for the switches and multiplexers when control is\r
+      given to the operating system.\r
+\r
+  \section ThirdPartyI2cDrivers   Third Party I2C Drivers\r
+\r
+  This layer is I2C chip specific but platform and host controller\r
+  independent.\r
+\r
+  Third party I2C driver writers, typically silicon vendors, need\r
+  to provide:\r
+\r
+  1.  The device path node data that is used to select their\r
+      driver.\r
+\r
+  2.  The order for the blocks of logic that get referenced\r
+      by the entries in the slave address array.\r
+\r
+  3.  The hardware version of the I2C device, this value is passed\r
+      to the third party I2C driver to enable it to perform work\r
+      arounds for the specific hardware version.  This value should\r
+      match the value in the ACPI _HRV tag.\r
+\r
+  The third party I2C driver uses relative addressing to abstract\r
+  the platform specific details of the I2C device.  Using an\r
+  example I2C device containing an accelerometer and a magnetometer\r
+  which consumes two slave addresses, one for each logic block.  The\r
+  third party I2C driver writer may choose to write two drivers, one\r
+  for each block of logic, in which case each driver refers to the\r
+  single I2C slave address using the relative value of zero (0).\r
+  However if the third party I2C driver writer chooses to write a\r
+  single driver which consumes multiple slave addresses then the\r
+  third party I2C driver writer needs to convey the order of the\r
+  I2C slave address entries in the slave address array to the\r
+  platform software designer.  For the example:\r
+\r
+      0: Accelerometer\r
+\r
+      1: Magnetometer\r
+\r
+  The platform hardware designer picks the actual slave addresses\r
+  from the I2C device's data sheet and provides this information\r
+  to the platform software designer.  The platform software designer\r
+  then places the slave addresses into the slave address array in the\r
+  order specified by the third party I2C driver writer.  The third\r
+  party driver I2C writer then indirectly references this array by\r
+  specifying the index value as the relative slave address.  The\r
+  relative value always starts at zero (0) and its maximum value is\r
+  the number of entries in slave address array minus one.\r
+\r
+  The slave address is specified as a 32-bit integer to allow room\r
+  for future slave address expansion.  Only the port driver knows\r
+  the maximum slave address value.  All other drivers and\r
+  applications must look for the EFI_NOT_FOUND status for the\r
+  indication that the maximum slave address was exceeded.\r
+\r
+  \section I2cBusDriver         I2C Bus Driver\r
+\r
+  This layer is platform, host controller, and I2C chip independent.\r
+\r
+  The I2C bus driver creates a handle for each of the I2C devices\r
+  described within the platform driver.  The I2C controller's device\r
+  path is extended with the device path node provided by the platform\r
+  driver and attached to the handle.  The third party I2C device driver\r
+  uses the device path to determine if it may connect.  For ACPI nodes,\r
+  the third party I2C driver should use the CID or CidString value.\r
+\r
+  The I2C bus driver validates the relative address for the I2C device\r
+  and then converts the relative value to an actual I2C slave address.\r
+  The request is then passed to the I2C host driver.\r
+\r
+  \section I2cHostDriver        I2C Host Driver\r
+\r
+  This layer is platform, host controller, and I2C chip independent.\r
+\r
+  N.B. For proper operation of the I2C bus, only the I2C bus driver\r
+  and the I2C test application should connect to the I2C host driver\r
+  via the EFI_I2C_HOST_DRIVER_PROTOCOL.\r
+\r
+  The I2C host driver may access any device on the I2C bus.  The I2C\r
+  host driver has the following responsibilities:\r
+\r
+  1.  Limits the number of requests to the I2C port driver to one.\r
+      The I2C host driver holds on to additional requests until the\r
+      I2C port driver is available to process the request.  The I2C\r
+      requests are issued in FIFO order to the I2C port driver.\r
+\r
+  2.  Enable the proper I2C bus configuration before starting the\r
+      I2C request on the I2C port driver\r
+\r
+  I2C devices are addressed as the tuple: BusConfiguration:SlaveAddress.\r
+  I2C bus configuration zero (0) is the portion of the I2C bus that\r
+  connects to the host controller.  The bus configuration specifies\r
+  the control values for the switches and multiplexers in the I2C bus.\r
+  After the switches and multiplexers are properly configured, the I2C\r
+  controller uses the slave address to access the requested I2C device.\r
+\r
+  Since the I2C driver stack supports asynchronous operations this\r
+  layer maintains a queue of I2C requests until the I2C controller\r
+  is available them.  When a request reaches the head of the queue\r
+  the necessary bus configuration is enabled and then the request\r
+  is sent to the I2C port driver.\r
+\r
+  \section I2cPortDriver        I2C Port Driver\r
+\r
+  This layer is I2C controller specific but platform independent.\r
+\r
+  This layer manipulates the I2C controller to perform an operation\r
+  on the I2C bus.  This layer does not configure the I2C bus so it\r
+  is up to the caller to ensure that the I2C bus is in the proper\r
+  configuration before issuing the I2C request.\r
+\r
+  This layer typically needs the following information:\r
+\r
+  1.  Host controller address\r
+  2.  Controller's input clock frequency\r
+\r
+  Depending upon the I2C controller, more data may be necessary.\r
+  This layer may use any method to get these values: hard coded\r
+  values, PCD values, or may choose to communicate with the platform\r
+  layer using an undefined mechanism to get these values.\r
+\r
+  If the I2C port driver requires data from the platform driver then\r
+  the I2C port driver writer needs to provide the platform interface\r
+  details to the platform software designer.\r
+\r
+  \section I2cPlatformDriver    I2C Platform Driver\r
+\r
+  When enabling access to I2C devices within UEFI, this driver\r
+  installs the EFI_I2C_ACPI_PROTOCOL to provide the I2C device\r
+  descriptions to the I2C bus driver using the EFI_I2C_DEVICE\r
+  structure.  These descriptions include the bus configuration\r
+  number required for the I2C device, the slave address array\r
+  and the device path.\r
+\r
+  The EFI_I2C_BUS_CONFIGURATION_MANAGEMENT protocol is optional.\r
+  This protocol needs to be specified under the following conditions:\r
+\r
+  1.  The I2C bus must operate at a frequency greater than 100 KHz\r
+  2.  The I2C bus contains switches or multiplexers.\r
+\r
+  The EFI_I2C_BUS_CONFIGURATION_MANAGEMENT protocol enables the\r
+  I2C host driver to call into the I2C platform driver to enable\r
+  a specific I2C bus configuration and set its maximum clock speed.\r
+\r
+  The platform software designer collects the data requirements\r
+  from third party I2C driver writers, the I2C controller\r
+  driver writer, the EFI_I2C_ACPI_PROTOCOL and\r
+  EFI_I2C_BUS_CONFIGURATION_MANAGEMENT_PROTOCOL.  The platform\r
+  software designer gets the necessary data from the platform\r
+  hardware designer.  The platform software designer then builds\r
+  the data structures and implements the necessary routines to\r
+  construct the I2C platform driver.\r
+\r
+  \section I2cSwitches          Switches and Multiplexers\r
+\r
+  There are some I2C switches and I2C multiplexers where the control\r
+  is done via I2C commands.  When the control inputs come via the\r
+  same I2C bus that is being configured then the platform driver must\r
+  use the EFI_I2C_MASTER_PROTOCOL that is passed to the platform\r
+  driver.  While the I2C host driver makes the call to the I2C\r
+  platform driver to configure the bus, the host driver keeps the\r
+  I2C port driver idle, to allow the I2C platform driver preform\r
+  the necessary configuration operations.\r
+\r
+  If however the configuration control is done via and I2C device\r
+  connected to a different I2C bus (host controller), then it is\r
+  possible for the platform software designer may choose between\r
+  the following:\r
+\r
+  1.  Call into a third party I2C driver to manipulate the I2C\r
+      bus control device.\r
+  2.  Call into the EFI_I2C_BUS_PROTOCOL if no third party I2C\r
+      driver exists for the I2C bus control device\r
+  3.  Call into the EFI_I2C_HOST_PROTOCOL if the platform does\r
+      not expose the I2C bus control device.\r
+\r
+**/\r
+\r
+#ifndef __I2C_MASTER_H__\r
+#define __I2C_MASTER_H__\r
+\r
+/**\r
+  Declare the forward references\r
+\r
+**/\r
+typedef struct _EFI_I2C_MASTER_PROTOCOL   EFI_I2C_MASTER_PROTOCOL;  ///<  I2C master protocol\r
+\r
+///\r
+/// I2C device operation\r
+///\r
+/// This structure provides the information necessary for an operation\r
+/// on an I2C device\r
+///\r
+typedef struct {\r
+  ///\r
+  /// Number of bytes to send to the I2C device\r
+  ///\r
+  UINT32 WriteBytes;\r
+\r
+  ///\r
+  /// Number of bytes to read, set to zero for write only operations\r
+  ///\r
+  UINT32 ReadBytes;\r
+\r
+  ///\r
+  /// Address of the buffer containing the data to send to the I2C device.\r
+  /// The WriteBuffer must be at least WriteBytes in length.\r
+  ///\r
+  UINT8 *WriteBuffer;\r
+\r
+  ///\r
+  /// Address of the buffer to receive data from the I2C device. Use NULL\r
+  /// for write only operations.  The ReadBuffer must be at least ReadBytes\r
+  /// in length.\r
+  ///\r
+  UINT8 *ReadBuffer;\r
+\r
+  ///\r
+  /// Timeout for the I2C operation in 100 ns units\r
+  ///\r
+  UINT32 Timeout;\r
+} EFI_I2C_REQUEST_PACKET;\r
+\r
+\r
+/**\r
+  Set the I2C controller bus clock frequency.\r
+\r
+  This routine must be called at or below TPL_NOTIFY.\r
+\r
+  The software and controller do a best case effort of using the specified\r
+  frequency for the I2C bus.  If the frequency does not match exactly then\r
+  the controller will use a slightly lower frequency to avoid\r
+  exceeding the operating conditions for any of the I2C devices on the bus.\r
+  For example if 400 KHz was specified and the controller's divide network\r
+  only supports 402 KHz or 398 KHz then the controller would be set to 398\r
+  KHz.  However if the desired frequency is 400 KHz and the controller only\r
+  supports 1 MHz and 100 KHz then this routine would return EFI_UNSUPPORTED.\r
+\r
+  @param[in] This           Address of an EFI_I2C_MASTER_PROTOCOL\r
+                            structure\r
+  @param[in] BusClockHertz  New I2C bus clock frequency in Hertz\r
+\r
+  @retval EFI_SUCCESS       The bus frequency was set successfully.\r
+  @retval EFI_UNSUPPORTED   The controller does not support this frequency.\r
+\r
+**/\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *EFI_I2C_MASTER_BUS_FREQUENCY_SET) (\r
+  IN CONST EFI_I2C_MASTER_PROTOCOL *This,\r
+  IN UINTN BusClockHertz\r
+  );\r
+\r
+/**\r
+  Reset the I2C controller and configure it for use\r
+\r
+  This routine must be called at or below TPL_NOTIFY.\r
+\r
+  The I2C controller is reset and the I2C bus frequency is set to 100 KHz.\r
+\r
+  @param[in]     This       Address of an EFI_I2C_MASTER_PROTOCOL\r
+                            structure\r
+\r
+**/\r
+typedef\r
+VOID\r
+(EFIAPI *EFI_I2C_MASTER_RESET) (\r
+  IN CONST EFI_I2C_MASTER_PROTOCOL *This\r
+  );\r
+\r
+/**\r
+  Start an I2C operation on the host controller\r
+\r
+  This routine must be called at or below TPL_NOTIFY.  For synchronous\r
+  requests this routine must be called at or below TPL_CALLBACK.\r
+\r
+  This function initiates an I2C operation on the controller.\r
+\r
+  The operation is performed by selecting the I2C device with its slave\r
+  address and then sending all write data to the I2C device.  If read data\r
+  is requested, a restart is sent followed by the slave address and then\r
+  the read data is clocked into the I2C controller and placed in the read\r
+  buffer.  When the operation completes, the status value is returned and\r
+  then the event is set.\r
+\r
+  N.B. The typical consumer of this API is the I2C host driver.\r
+  Extreme care must be taken by other consumers of this API to\r
+  prevent confusing the third party I2C drivers due to a state\r
+  change at the I2C device which the third party I2C drivers did\r
+  not initiate.  I2C platform drivers may use this API within\r
+  these guidelines.\r
+\r
+  N.B. This API supports only one operation, no queuing support\r
+  exists at this layer.  This API assumes that the I2C bus is in\r
+  the correct configuration for the I2C request.\r
+\r
+  @param[in] This           Address of an EFI_I2C_MASTER_PROTOCOL\r
+                            structure\r
+  @param[in] SlaveAddress   Address of the device on the I2C bus.\r
+  @param[in] Event          Event to set for asynchronous operations,\r
+                            NULL for synchronous operations\r
+  @param[in] RequestPacket  Address of an EFI_I2C_REQUEST_PACKET\r
+                            structure describing the I2C operation\r
+  @param[out] I2cStatus     Optional buffer to receive the I2C operation\r
+                            completion status\r
+\r
+  @retval EFI_SUCCESS           The operation completed successfully.\r
+  @retval EFI_ABORTED           The request did not complete because the driver\r
+                                was shutdown.\r
+  @retval EFI_BAD_BUFFER_SIZE   The WriteBytes or ReadBytes buffer size is too large.\r
+  @retval EFI_DEVICE_ERROR      There was an I2C error (NACK) during the operation.\r
+                                This could indicate the slave device is not present.\r
+  @retval EFI_INVALID_PARAMETER RequestPacket is NULL\r
+  @retval EFI_INVALID_PARAMETER TPL is too high\r
+  @retval EFI_NOT_FOUND         SlaveAddress exceeds maximum address\r
+  @retval EFI_NOT_READY         I2C bus is busy or operation pending, wait for\r
+                                the event and then read status pointed to by\r
+                                the request packet.\r
+  @retval EFI_NO_RESPONSE       The I2C device is not responding to the\r
+                                slave address.  EFI_DEVICE_ERROR may also be\r
+                                returned if the controller cannot distinguish\r
+                                when the NACK occurred.\r
+  @retval EFI_OUT_OF_RESOURCES  Insufficient memory for I2C operation\r
+  @retval EFI_TIMEOUT           The transaction did not complete within an internally\r
+                                specified timeout period.\r
+\r
+**/\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *EFI_I2C_MASTER_START_REQUEST) (\r
+  IN CONST EFI_I2C_MASTER_PROTOCOL *This,\r
+  IN UINTN SlaveAddress,\r
+  IN EFI_EVENT Event OPTIONAL,\r
+  IN CONST EFI_I2C_REQUEST_PACKET *RequestPacket,\r
+  OUT EFI_STATUS *I2cStatus OPTIONAL\r
+  );\r
+\r
+///\r
+/// I2C master mode protocol\r
+///\r
+/// This protocol manipulates the I2C host controller to perform transactions as a\r
+/// master on the I2C bus using the current state of any switches or multiplexers\r
+/// in the I2C bus.\r
+///\r
+struct _EFI_I2C_MASTER_PROTOCOL {\r
+  ///\r
+  /// Set the clock frequency for the I2C bus\r
+  ///\r
+  EFI_I2C_MASTER_BUS_FREQUENCY_SET BusFrequencySet;\r
+\r
+  ///\r
+  /// Reset the I2C host controller\r
+  ///\r
+  EFI_I2C_MASTER_RESET Reset;\r
+\r
+  ///\r
+  /// Start an I2C transaction in master mode on the host controller\r
+  ///\r
+  EFI_I2C_MASTER_START_REQUEST StartRequest;\r
+\r
+  ///\r
+  /// The maximum number of bytes the I2C host controller\r
+  /// is able to receive from the I2C bus.\r
+  ///\r
+  UINT32 MaximumReceiveBytes;\r
+\r
+  ///\r
+  /// The maximum number of bytes the I2C host controller\r
+  /// is able to send on the I2C bus.\r
+  ///\r
+  UINT32 MaximumTransmitBytes;\r
+\r
+  ///\r
+  /// The maximum number of bytes in the I2C bus transaction.\r
+  ///\r
+  UINT32 MaximumTotalBytes;\r
+};\r
+\r
+///\r
+/// GUID for the EFI_I2C_MASTER_PROTOCOL\r
+///\r
+extern EFI_GUID gEfiI2cMasterProtocolGuid;\r
+\r
+#endif  //  __I2C_MASTER_H__\r

diff --git a/Vlv2TbltDevicePkg/Include/Protocol/I2cSlave.h b/Vlv2TbltDevicePkg/Include/Protocol/I2cSlave.h
new file mode 100644 (file)
index 0000000..ba094ff
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Include/Protocol/I2cSlave.h
@@ -0,0 +1,199 @@
+/*++\r
+\r
+  Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+\r
+**/\r
+\r
+#ifndef __I2C_SLAVE_H__\r
+#define __I2C_SLAVE_H__\r
+\r
+#include <Protocol/I2cHostMcg.h>\r
+\r
+/**\r
+  Declare the forward references\r
+\r
+**/\r
+typedef struct _EFI_I2C_SLAVE_PROTOCOL    EFI_I2C_SLAVE_PROTOCOL;   ///<  I2C slave protocol\r
+\r
+/**\r
+  The I2C controller received a data byte from the\r
+  I2C msster.\r
+\r
+  @param[in] Context        The value passed to the slave enable routine.\r
+  @param[in] NumberOfBytes  Number of data bytes received\r
+  @param[in] Data           Buffer containing the received data bytes\r
+\r
+  @retval EFI_SUCCESS       ACK the data byte\r
+  @retval EFI_UNSUPPORTED   NACK the data byte\r
+\r
+**/\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *EFI_I2C_SLAVE_RECEIVE_DATA) (\r
+  IN VOID *Context,\r
+  IN UINTN NumberOfBytes,\r
+  IN CONST UINT8 *Data\r
+  );\r
+\r
+/**\r
+  The I2C controller received the start bit from the\r
+  I2C master.\r
+\r
+  @param[in] Context        The value passed to the slave enable routine.\r
+\r
+**/\r
+typedef\r
+VOID\r
+(EFIAPI *EFI_I2C_SLAVE_RECEIVE_START) (\r
+  IN VOID *Context,\r
+  IN UINTN BytesSent,\r
+  IN EFI_STATUS Status\r
+  );\r
+\r
+/**\r
+  The I2C controller received the stop bit from the\r
+  I2C master.\r
+\r
+  @param[in] Context        The value passed to the slave enable routine.\r
+  @param[in] BytesSent      Number of bytes successfully ACKed by the\r
+                            I2C master.  This is a hint, not all I2C\r
+                            controllers support the ability to return\r
+                            the number of bytes sent.  When it is not\r
+                            possible, the port driver returns zero.\r
+  @param[in] Status         <ul>\r
+                              <li>EFI_SUCCESS - All of the data was successfully sent</li>\r
+                              <li>EFI_ABORTED - The controller was reset</li>\r
+                              <li>EFI_DEVICE_ERROR - A NACK was received when sending the data.</li>\r
+                              <li>EFI_END_OF_FILE - The stop bit was received before all of\r
+                                the data was sent.</li>\r
+                            </ul>\r
+\r
+**/\r
+typedef\r
+VOID\r
+(EFIAPI *EFI_I2C_SLAVE_RECEIVE_STOP) (\r
+  IN VOID *Context,\r
+  IN UINTN BytesSent,\r
+  IN EFI_STATUS Status\r
+  );\r
+\r
+/**\r
+  Enable or disable I2C slave operation.\r
+\r
+  The ReceiveData callback allows the port driver to return data\r
+  to the driver or application handling slave mode operations.  This\r
+  is data that a remote master has sent to the local I2C controller.\r
+  The data may be returned one byte at a time if the controller supports\r
+  the ability to ACK/NACK on each receive byte.  If not, a block of\r
+  data may be returned by the I2C port driver and the ACK/NACK status\r
+  is used only as a hint for the port driver.\r
+\r
+  The slave mode driver or application should buffer the data until\r
+  either ReceiveStart or ReceiveStop is called.  At that time all of\r
+  the data is received and the command may be processed.\r
+\r
+  ReceiveStart is called when the I2C master is expecting a response.\r
+  After processing the command, but before sending the response the\r
+  slave driver or application should mark the command as processed to\r
+  avoid processing it a second time when ReceiveStop is called.  The\r
+  slave driver or application then calls SendData to send to queue the\r
+  response data for transmission.  The data must remain valid in the\r
+  WriteBuffer until ReceiveStop is called.\r
+\r
+  ReceiveStop is called when the stop bit is received on the I2C bus.\r
+  The slave driver or application starts processing the command if an\r
+  command data is pending in the slave driver's or application's buffer.\r
+  The BytesSent value is a hint to the slave driver or application as\r
+  to how much data was returned to the I2C master.  If the controller\r
+  does not provide this level of support then this value is set to zero.\r
+\r
+  @param[in] This           Address of an EFI_I2C_SLAVE_PROTOCOL\r
+                            structure\r
+  @param[in] SlaveAddress   Slave address for the I2C controller\r
+  @param[in] Context        Address of a context structure for use when\r
+                            calling ReceiveData or ReceiveStop\r
+  @param[in] ReceiveData    Called by the I2C port driver as data bytes\r
+                            are received from the master.  Response status\r
+                            indicates if the byte is ACKed or NACKed. When\r
+                            data is passed back a byte at a time, the port\r
+                            driver must hold the clock until this callback\r
+                            returns.\r
+  @param[in] ReceiveStart   Called when the I2C controller receives a start bit.\r
+  @param[in] ReceiveStop    Called after all of the data bytes are\r
+                            received.\r
+\r
+  @retval EFI_SUCCESS       Slave operation is enabled on the controller.\r
+  @retval EFI_UNSUPPORTED   The controller does not support this frequency.\r
+\r
+**/\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *EFI_I2C_SLAVE_ENABLE) (\r
+  IN CONST EFI_I2C_SLAVE_PROTOCOL *This,\r
+  IN UINT32 SlaveAddress,\r
+  IN VOID *Context,\r
+  IN EFI_I2C_SLAVE_RECEIVE_DATA ReceiveData,\r
+  IN EFI_I2C_SLAVE_RECEIVE_START ReceiveStart,\r
+  IN EFI_I2C_SLAVE_RECEIVE_STOP ReceiveStop\r
+  );\r
+\r
+/**\r
+  Send data to the I2C master.\r
+\r
+  Port drivers may implement this as a blocking or non-blocking call.\r
+  The data in the write buffer must remain valid until ReceiveStop or\r
+  ReceiveStart is called indicating that the I2C master has terminated\r
+  the transfer.\r
+\r
+  @param[in] This         Address of an EFI_I2C_SLAVE_PROTOCOL\r
+                          structure\r
+  @param[in] WriteBytes   Number of bytes to write\r
+  @param[in] WriteBuffer  Buffer containing the data to send\r
+\r
+  @retval EFI_SUCCESS           Data waiting for master access.\r
+  @retval EFI_INVALID_PARAMETER WriteBuffer is NULL or WriteBytes\r
+                                is zero.\r
+\r
+**/\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *EFI_I2C_SLAVE_SEND) (\r
+  IN CONST EFI_I2C_SLAVE_PROTOCOL *This,\r
+  IN UINTN WriteBytes,\r
+  IN CONST UINT8 *WriteBuffer\r
+  );\r
+\r
+///\r
+/// I2C slave protocol\r
+///\r
+/// The port driver publishes this protocol when slave mode is\r
+/// supported by the controller.\r
+///\r
+struct _EFI_I2C_SLAVE_PROTOCOL {\r
+  ///\r
+  /// Enable or disable I2C slave operation\r
+  ///\r
+  EFI_I2C_SLAVE_ENABLE SlaveEnable;\r
+\r
+  ///\r
+  /// Send data to the I2C master\r
+  ///\r
+  EFI_I2C_SLAVE_SEND SendData;\r
+};\r
+\r
+///\r
+/// GUID for the EFI_I2C_SLAVE_PROTOCOL\r
+///\r
+extern EFI_GUID gEfiI2cSlaveProtocolGuid;\r
+\r
+#endif  //  __I2C_SLAVE_H__\r

diff --git a/Vlv2TbltDevicePkg/Include/Protocol/LpcWpc83627Policy.h b/Vlv2TbltDevicePkg/Include/Protocol/LpcWpc83627Policy.h
new file mode 100644 (file)
index 0000000..d7b54be
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Include/Protocol/LpcWpc83627Policy.h
@@ -0,0 +1,97 @@
+/*++\r
+\r
+  Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+\r
+Module Name:\r
+\r
+  LpcWpc83667Policy.h\r
+\r
+Abstract:\r
+\r
+  Protocol used for WPC83627 Policy definition.\r
+-------------------------------------------------------------------------------\r
+   Rev   Date<MM/DD/YYYY>    Name    Description\r
+  -------------------------------------------------------------------------------\r
+  R01   < 4/22/2011>         LB     Update driver for Sio83627UGH support.\r
+  -------------------------------------------------------------------------------\r
+**/\r
+\r
+#ifndef _WPC83627_POLICY_PROTOCOL_H_\r
+#define _WPC83627_POLICY_PROTOCOL_H_\r
+\r
+EFI_FORWARD_DECLARATION (EFI_WPC83627_POLICY_PROTOCOL);\r
+\r
+#define EFI_WPC83627_POLICY_PROTOCOL_GUID \\r
+  { \\r
+    0xd3ecc567, 0x9fd5, 0x44c1, 0x86, 0xcf, 0x5d, 0xa7, 0xa2, 0x4f, 0x4b, 0x5d \\r
+  }\r
+\r
+#define EFI_WPC83627_COM1_ENABLE          0x01\r
+#define EFI_WPC83627_COM2_ENABLE          0x01\r
+\r
+#define EFI_WPC83627_COM3_ENABLE          0x01\r
+#define EFI_WPC83627_COM4_ENABLE          0x01\r
+\r
+#define EFI_WPC83627_LPT1_ENABLE          0x01\r
+#define EFI_WPC83627_LPT1_ENABLE          0x01\r
+#define EFI_WPC83627_FDD_ENABLE           0x01\r
+#define EFI_WPC83627_FDD_WRITE_ENABLE     0x01\r
+#define EFI_WPC83627_PS2_KBC_ENABLE       0x01\r
+#define EFI_WPC83627_ECIR_ENABLE         0x01\r
+\r
+#define EFI_WPC83627_COM1_DISABLE         0x00\r
+#define EFI_WPC83627_COM2_DISABLE         0x00\r
+\r
+#define EFI_WPC83627_COM3_DISABLE         0x00\r
+#define EFI_WPC83627_COM4_DISABLE         0x00\r
+\r
+#define EFI_WPC83627_LPT1_DISABLE         0x00\r
+#define EFI_WPC83627_FDD_DISABLE          0x00\r
+#define EFI_WPC83627_FDD_WRITE_PROTECT    0x00\r
+#define EFI_WPC83627_PS2_KBC_DISABLE      0x00\r
+#define EFI_WPC83627_ECIR_DISABLE         0x00\r
+#define EFI_WPC83627_RESERVED_DEFAULT     0x00\r
+\r
+typedef struct {\r
+  UINT16  Com1               :1;             // 0 = Disable, 1 = Enable\r
+  UINT16  Lpt1               :1;             // 0 = Disable, 1 = Enable\r
+  UINT16  Floppy             :1;             // 0 = Disable, 1 = Enable\r
+  UINT16  FloppyWriteProtect :1;             // 0 = Write Protect, 1 = Write Enable\r
+  UINT16  Port80             :1;             // 0 = Disable, 1 = Enable\r
+  UINT16  CIR                :1;             // CIR enable or disable\r
+  UINT16  Ps2Keyboard        :1;             // 0 = Disable, 1 = Enable\r
+  UINT16  Ps2Mouse           :1;             // 0 = Disable, 1 = Enable\r
+  UINT16  Com2               :1;             // 0 = Disable, 1 = Enable\r
+\r
+  UINT16  Com3               :1;             // 0 = Disable, 1 = Enable\r
+  UINT16  Com4               :1;             // 0 = Disable, 1 = Enable\r
+\r
+  UINT16  Dac                :1;             // 0 = Disable, 1 = Enable\r
+  UINT16  Rsvd               :6;\r
+} EFI_WPC83627_DEVICE_ENABLES;\r
+\r
+typedef enum {\r
+  LptModeOutput,\r
+  LptModeBiDirectional,\r
+  LptModeEpp,\r
+  LptModeEcp\r
+} EFI_LPT_MODE;\r
+\r
+typedef struct _EFI_WPC83627_POLICY_PROTOCOL {\r
+  EFI_WPC83627_DEVICE_ENABLES DeviceEnables;\r
+  EFI_LPT_MODE              LptMode;\r
+} EFI_WPC83627_POLICY_PROTOCOL;\r
+\r
+extern EFI_GUID gEfiLpcWpc83627PolicyProtocolGuid;\r
+\r
+#endif\r

diff --git a/Vlv2TbltDevicePkg/Include/Protocol/LpcWpce791Policy.h b/Vlv2TbltDevicePkg/Include/Protocol/LpcWpce791Policy.h
new file mode 100644 (file)
index 0000000..4c897da
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Include/Protocol/LpcWpce791Policy.h
@@ -0,0 +1,60 @@
+/*++\r
+\r
+  Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+\r
+Module Name:\r
+\r
+  LpcWpce791Policy.h\r
+\r
+Abstract:\r
+\r
+  Protocol used for WPCE791 Policy definition.\r
+\r
+**/\r
+\r
+#ifndef _WPCE791_POLICY_PROTOCOL_H_\r
+#define _WPCE791_POLICY_PROTOCOL_H_\r
+\r
+\r
+#define EFI_WPCE791_POLICY_PROTOCOL_GUID \\r
+  { \\r
+    0xab2bee2f, 0xc1a6, 0x4399, 0x85, 0x3d, 0xc0, 0x7c, 0x77, 0x4f, 0xfd, 0xd \\r
+  }\r
+\r
+#define EFI_WPCE791_PS2_KEYBOARD_ENABLE       0x01\r
+#define EFI_WPCE791_PS2_KEYBOARD_DISABLE      0x00\r
+\r
+#define EFI_WPCE791_PS2_MOUSE_ENABLE       0x01\r
+#define EFI_WPCE791_PS2_MOUSE_DISABLE      0x00\r
+\r
+typedef struct {\r
+  UINT16  Com1               :1;             // 0 = Disable, 1 = Enable\r
+  UINT16  Lpt1               :1;             // 0 = Disable, 1 = Enable\r
+  UINT16  Floppy             :1;             // 0 = Disable, 1 = Enable\r
+  UINT16  FloppyWriteProtect :1;             // 0 = Write Protect, 1 = Write Enable\r
+  UINT16  Port80             :1;             // 0 = Disable, 1 = Enable\r
+  UINT16  CIR                :1;             // CIR enable or disable\r
+  UINT16  Ps2Keyboard        :1;             // 0 = Disable, 1 = Enable\r
+  UINT16  Ps2Mouse           :1;             // 0 = Disable, 1 = Enable\r
+  UINT16  Com2               :1;             // 0 = Disable, 1 = Enable\r
+  UINT16  Dac                :1;             // 0 = Disable, 1 = Enable\r
+  UINT16  Rsvd               :6;\r
+} EFI_WPCE791_DEVICE_ENABLES;\r
+\r
+typedef struct _EFI_WPCE791_POLICY_PROTOCOL {\r
+  EFI_WPCE791_DEVICE_ENABLES DeviceEnables;\r
+} EFI_WPCE791_POLICY_PROTOCOL;\r
+\r
+extern EFI_GUID gEfiLpcWpce791PolicyProtocolGuid;\r
+\r
+#endif\r

diff --git a/Vlv2TbltDevicePkg/Include/Protocol/MmioDevice.h b/Vlv2TbltDevicePkg/Include/Protocol/MmioDevice.h
new file mode 100644 (file)
index 0000000..6848f52
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Include/Protocol/MmioDevice.h
@@ -0,0 +1,89 @@
+/*++\r
+\r
+  Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+**/\r
+\r
+#ifndef __MMIO_DEVICE_H__\r
+#define __MMIO_DEVICE_H__\r
+\r
+//\r
+// Protocol to define for the MMIO device\r
+//\r
+typedef struct {\r
+  //\r
+  // Address of a GUID\r
+  //\r
+  EFI_GUID *Guid;\r
+\r
+  //\r
+  // Context for the protocol\r
+  //\r
+  VOID *Context;\r
+} EFI_MMIO_DEVICE_PROTOCOL_ITEM;\r
+\r
+\r
+typedef struct _EFI_MMIO_DEVICE_PROTOCOL  EFI_MMIO_DEVICE_PROTOCOL;\r
+\r
+//\r
+//  The MMIO device protocol defines a memory mapped I/O device\r
+//  for use by the system.\r
+//\r
+struct _EFI_MMIO_DEVICE_PROTOCOL {\r
+  //\r
+  // Pointer to an ACPI_EXTENDED_HID_DEVICE_PATH structure\r
+  // containing HID/HidStr and CID/CidStr values.\r
+  //\r
+  // See the note below associated with the UnitIdentification\r
+  // field.\r
+  //\r
+  CONST ACPI_EXTENDED_HID_DEVICE_PATH *AcpiPath;\r
+\r
+  //\r
+  // Allow the use of a shared template for the AcpiPath.\r
+  //\r
+  // If this value is non-zero UID value then the AcpiPath must\r
+  // be a template which contains only the HID/HidStr and CID/CidStr\r
+  // values.  The UID/UidStr values in the AcpiPath must be zero!\r
+  //\r
+  // If this value is zero then the AcpiPath is not shared and\r
+  // must contain either a non-zero UID value or a UidStr value.\r
+  //\r
+  UINT32 UnitIdentification;\r
+\r
+  //\r
+  // Hardware revision - ACPI _HRV value\r
+  //\r
+  UINT32 HardwareRevision;\r
+\r
+  //\r
+  // Pointer to a data structure containing the controller\r
+  // resources and configuration.  At a minimum this points\r
+  // to an EFI_PHYSICAL_ADDRESS for the base address of the\r
+  // MMIO device.\r
+  //\r
+  CONST VOID *DriverResources;\r
+\r
+  //\r
+  // Number of protocols in the array\r
+  //\r
+  UINTN ProtocolCount;\r
+\r
+  //\r
+  // List of protocols to define\r
+  //\r
+  CONST EFI_MMIO_DEVICE_PROTOCOL_ITEM *ProtocolArray;\r
+};\r
+\r
+extern EFI_GUID gEfiMmioDeviceProtocolGuid;\r
+\r
+#endif  //  __MMIO_DEVICE_H__\r

diff --git a/Vlv2TbltDevicePkg/Include/Protocol/Observable.h b/Vlv2TbltDevicePkg/Include/Protocol/Observable.h
new file mode 100644 (file)
index 0000000..31af6dd
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Include/Protocol/Observable.h
@@ -0,0 +1,191 @@
+/*++\r
+\r
+  Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+\r
+Module Name:\r
+\r
+  Observable.h\r
+\r
+Abstract:\r
+\r
+  Interface and GUID definitions for Observable protocol.\r
+\r
+**/\r
+\r
+#ifndef _OBSERVABLE_PROTOCOL_H_\r
+#define _OBSERVABLE_PROTOCOL_H_\r
+\r
+//\r
+// GUID Definitions\r
+//\r
+#define OBSERVABLE_PROTOCOL_GUID \\r
+  { \\r
+    0xe227c522, 0xd5fe, 0x4a53, 0x87, 0xb1, 0x0f, 0xbe, 0x57, 0x0f, 0x98, 0xe9 \\r
+  }\r
+\r
+extern EFI_GUID gObservableProtocolGuid;\r
+\r
+typedef struct _OBS_OBSERVABLE_PROTOCOL OBS_OBSERVABLE_PROTOCOL;\r
+\r
+//\r
+// Interface Definitions\r
+//\r
+\r
+/**\r
+  Remove all observables.\r
+\r
+  Remove all observable guids and all interfaces subscribed to them.\r
+\r
+  @param   VOID          No Parameters.\r
+\r
+  @return  EFI_SUCCESS   Successfully removed all observables and subscribed interfaces.\r
+\r
+**/\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *OBS_REMOVE_ALL_OBSERVABLES) (\r
+  VOID\r
+  );\r
+\r
+/**\r
+  Interface for notification functions.\r
+\r
+  Functions that are to be used as callbacks must inherit this interface in order to be used properly.\r
+\r
+  @param   VOID*   Data  Parameter context to be passed to the notification function.\r
+\r
+  @return  EFI_STATUS    Varies depending on implementation.\r
+\r
+**/\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *OBS_CALLBACK) (\r
+  IN  OUT VOID*   Data\r
+  );\r
+\r
+/**\r
+  Subscribe an interface with an observable guid.\r
+\r
+  Use this to register a callback function with a guid. The function provided by CallbackInterface will be executed\r
+  whenever the appropriate observable instance specified by ReferenceGuid calls Publish.\r
+\r
+  @param   EFI_GUID                ReferenceGuid       The observable guid that the callback interface will subscribe to.\r
+           OBS_NOTIFY_INTERFACE    CallbackInterface   A pointer to the function that is subscribing to the observable.\r
+\r
+  @return  EFI_SUCCESS           Successfully subscribed the interface to the observable guid.\r
+           EFI_NOT_FOUND         No match could be found between the provided guid and existing observables.\r
+           EFI_OUT_OF_RESOURCES  Could not subscribe to this observer due to resource limitations.\r
+           EFI_INVALID_PARAMETER Interface is already subscribed to this observer.\r
+**/\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *OBS_SUBSCRIBE) (\r
+  IN      EFI_GUID        ReferenceGuid,\r
+  IN      OBS_CALLBACK    CallbackInterface\r
+  );\r
+\r
+/**\r
+  Unsubscribe an interface with an observable guid.\r
+\r
+  Use this to remove an interface from the callback list associated with an observable guid.\r
+\r
+  @param   EFI_GUID                ReferenceGuid   The observable guid to unsubscribe the interface from.\r
+           OBS_NOTIFY_INTERFACE    NotifyCallback  A pointer to the interface that is being unsubscribed.\r
+\r
+  @return  EFI_SUCCESS           Successfully unsubscribed the interface from the observable guid.\r
+\r
+**/\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *OBS_UNSUBSCRIBE) (\r
+  IN      EFI_GUID        ReferenceGuid,\r
+  IN      OBS_CALLBACK    CallbackInterface\r
+  );\r
+\r
+/**\r
+  Notify observing functions.\r
+\r
+  Use this to notify all functions who are subscribed to the guid specified by ReferenceGuid.\r
+\r
+  @param   EFI_GUID          ReferenceGuid   The observable guid that contains the the list of interfaces to be notified.\r
+           VOID*             Data            Parameter context to be passed to the notification function.\r
+\r
+  @return  EFI_SUCCESS       Successfully notified all observers listening to this guid.\r
+           EFI_NOT_FOUND     No match could be found between the provided guid and existing observables.\r
+\r
+**/\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *OBS_PUBLISH) (\r
+  IN      EFI_GUID        ReferenceGuid,\r
+  IN  OUT VOID*           Data\r
+  );\r
+\r
+/**\r
+  Creates a new observable.\r
+\r
+  Create a new observable that can be observed with the use of Subscribe function.\r
+\r
+  @param   EFI_GUID              ReferenceGuid   The observable guid to add.\r
+\r
+  @return  EFI_SUCCESS           Successfully added observable.\r
+           EFI_INVALID_PARAMETER Observable already exists.\r
+\r
+**/\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *OBS_ADD_OBSERVABLE) (\r
+  IN      EFI_GUID        ReferenceGuid\r
+  );\r
+\r
+/**\r
+  Remove an observable.\r
+\r
+  Remove an observable so that it can no longer be subscribed to. In addition, unsubscribe any functions\r
+  that are subscribed to this guid.\r
+\r
+  @param   EFI_GUID              ReferenceGuid   The observable guid to remove.\r
+\r
+  @return  EFI_SUCCESS           Successfully removed observable.\r
+\r
+**/\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *OBS_REMOVE_OBSERVABLE) (\r
+  IN      EFI_GUID        ReferenceGuid\r
+  );\r
+\r
+//\r
+// Protocol Definitions\r
+//\r
+typedef struct _OBS_LEAF {\r
+  OBS_CALLBACK      Observer;\r
+  struct _OBS_LEAF* Next;\r
+} OBS_LEAF;\r
+\r
+typedef struct _OBS_TREE {\r
+  EFI_GUID              ObservableGuid;\r
+  OBS_LEAF*             Leaf;\r
+  struct _OBS_TREE*     Next;\r
+} OBS_TREE;\r
+\r
+struct _OBS_OBSERVABLE_PROTOCOL {\r
+  OBS_ADD_OBSERVABLE          AddObservable;\r
+  OBS_REMOVE_OBSERVABLE       RemoveObservable;\r
+  OBS_SUBSCRIBE               Subscribe;\r
+  OBS_UNSUBSCRIBE             Unsubscribe;\r
+  OBS_PUBLISH                 Publish;\r
+  OBS_REMOVE_ALL_OBSERVABLES  RemoveAllObservables;\r
+} ;\r
+\r
+#endif\r

diff --git a/Vlv2TbltDevicePkg/Include/Protocol/PlatformGopPolicy.h b/Vlv2TbltDevicePkg/Include/Protocol/PlatformGopPolicy.h
new file mode 100644 (file)
index 0000000..f0d021b
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Include/Protocol/PlatformGopPolicy.h
@@ -0,0 +1,73 @@
+/*++\r
+\r
+Copyright (c)  1999  - 2014, Intel Corporation. All rights reserved\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+--*/\r
+\r
+/** @file\r
+**/\r
+\r
+#ifndef _PLATFORM_GOP_POLICY_PROTOCOL_H_\r
+#define _PLATFORM_GOP_POLICY_PROTOCOL_H_\r
+\r
+#define EFI_PLATFORM_GOP_POLICY_PROTOCOL_GUID \\r
+  { 0xec2e931b, 0x3281, 0x48a5, 0x81, 0x7, 0xdf, 0x8a, 0x8b, 0xed, 0x3c, 0x5d }\r
+\r
+#define EFI_BMP_IMAGE_GUID \\r
+  { 0x878AC2CC, 0x5343, 0x46F2, 0xB5, 0x63, 0x51, 0xF8, 0x9D, 0xAF, 0x56, 0xBA }\r
+\r
+#define PLATFORM_GOP_POLICY_PROTOCOL_REVISION_01 0x01\r
+#define PLATFORM_GOP_POLICY_PROTOCOL_REVISION_02 x0222\r
+\r
+#pragma pack(1)\r
+\r
+typedef enum {\r
+  LidClosed,\r
+  LidOpen,\r
+  LidStatusMax\r
+} LID_STATUS;\r
+\r
+typedef enum {\r
+  Docked,\r
+  UnDocked,\r
+  DockStatusMax\r
+} DOCK_STATUS;\r
+\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *GET_PLATFORM_LID_STATUS) (\r
+   OUT LID_STATUS *CurrentLidStatus\r
+);\r
+\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *GET_VBT_DATA) (\r
+   OUT EFI_PHYSICAL_ADDRESS *VbtAddress,\r
+   OUT UINT32 *VbtSize\r
+);\r
+\r
+#pragma pack()\r
+\r
+typedef struct _PLATFORM_GOP_POLICY_PROTOCOL {\r
+  UINT32                             Revision;\r
+  GET_PLATFORM_LID_STATUS            GetPlatformLidStatus;\r
+  GET_VBT_DATA                       GetVbtData;\r
+} PLATFORM_GOP_POLICY_PROTOCOL;\r
+\r
+//\r
+// Extern the GUID for protocol users.\r
+//\r
+extern EFI_GUID  gPlatformGOPPolicyGuid;\r
+\r
+extern EFI_GUID  gBmpImageGuid;\r
+\r
+#endif\r

diff --git a/Vlv2TbltDevicePkg/Include/Protocol/PlatformIdeInit.h b/Vlv2TbltDevicePkg/Include/Protocol/PlatformIdeInit.h
new file mode 100644 (file)
index 0000000..45add2b
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Include/Protocol/PlatformIdeInit.h
@@ -0,0 +1,48 @@
+/*++\r
+\r
+  Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+\r
+Module Name:\r
+\r
+    PlatformIdeInit.h\r
+\r
+Abstract:\r
+\r
+    EFI Platform Ide Init Protocol\r
+\r
+Revision History\r
+\r
+**/\r
+\r
+#ifndef _EFI_PLATFORM_IDE_INIT_H_\r
+#define _EFI_PLATFORM_IDE_INIT_H_\r
+\r
+//\r
+// Global ID for the IDE Platform Protocol\r
+//\r
+#define EFI_PLATFORM_IDE_INIT_PROTOCOL_GUID \\r
+  { 0x377c66a3, 0x8fe7, 0x4ee8, 0x85, 0xb8, 0xf1, 0xa2, 0x82, 0x56, 0x9e, 0x3b };\r
+\r
+EFI_FORWARD_DECLARATION (EFI_PLATFORM_IDE_INIT_PROTOCOL);\r
+\r
+\r
+//\r
+// Interface structure for the Platform IDE Init Protocol\r
+//\r
+typedef struct _EFI_PLATFORM_IDE_INIT_PROTOCOL {\r
+  BOOLEAN                               SmartMode;\r
+} EFI_PLATFORM_IDE_INIT_PROTOCOL;\r
+\r
+extern EFI_GUID gEfiPlatformIdeInitProtocolGuid;\r
+\r
+#endif\r

diff --git a/Vlv2TbltDevicePkg/Include/Protocol/SetupMode.h b/Vlv2TbltDevicePkg/Include/Protocol/SetupMode.h
new file mode 100644 (file)
index 0000000..87fb523
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Include/Protocol/SetupMode.h
@@ -0,0 +1,84 @@
+/*++\r
+\r
+  Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+\r
+Module Name:\r
+\r
+    SetupMode.h\r
+\r
+Abstract:\r
+\r
+    EFI Setup Mode\r
+\r
+Revision History\r
+\r
+**/\r
+\r
+#ifndef _EFI_SETUP_MODE_H_\r
+#define _EFI_SETUP_MODE_H_\r
+\r
+//\r
+// Global ID for the Setup Mode\r
+//\r
+#define EFI_PLATFORM_BOOT_MODE_GUID \\r
+  { 0xce845704, 0x1683, 0x4d38, 0xa4, 0xf9, 0x7d, 0xb, 0x50, 0x77, 0x57, 0x93 }\r
+\r
+#define EFI_NORMAL_SETUP_GUID \\r
+  { 0xec87d643, 0xeba4, 0x4bb5, 0xa1, 0xe5, 0x3f, 0x3e, 0x36, 0xb2, 0xd, 0xa9 }\r
+\r
+#define EFI_NORMAL_SETUP_RESET_NAME L"Reset"\r
+\r
+enum {\r
+  //\r
+  // This means: "whatever reset defaults in setup does"\r
+  //\r
+  SetupDataResetNormal        = 0,\r
+\r
+  //\r
+  // This means: "the defaults built into the BIOS"\r
+  //\r
+  SetupDataResetStandard      = 1,\r
+\r
+  //\r
+  // This means: "the manufacturing mode defaults"\r
+  //\r
+  SetupDataResetManufacturing = 2,\r
+\r
+  //\r
+  // This means: "the oem defaults"\r
+  //\r
+  SetupDataResetOem           = 3,\r
+};\r
+\r
+//\r
+// PlatformBootMode types\r
+//\r
+#define PLATFORM_NORMAL_MODE          0x01\r
+#define PLATFORM_SAFE_MODE            0x02\r
+#define PLATFORM_RECOVERY_MODE        0x04\r
+#define PLATFORM_MANUFACTURING_MODE   0x08\r
+#define PLATFORM_BACK_TO_BIOS_MODE    0x10\r
+\r
+extern EFI_GUID gEfiPlatformBootModeGuid;\r
+extern EFI_GUID gEfiNormalSetupGuid;\r
+extern CHAR16   gEfiNormalSetupName[];\r
+extern CHAR16   gEfiInSetupName[];\r
+extern CHAR16   gEfiSystemPasswordName[];\r
+\r
+typedef struct {\r
+  EFI_GUID    SetupGuid;\r
+  CHAR16      SetupName[0x20];          // Maximum "Setup" Name\r
+  UINT32      PlatformBootMode;\r
+} EFI_PLATFORM_SETUP_ID;\r
+\r
+#endif\r

diff --git a/Vlv2TbltDevicePkg/Include/Protocol/SmbiosSlotPopulation.h b/Vlv2TbltDevicePkg/Include/Protocol/SmbiosSlotPopulation.h
new file mode 100644 (file)
index 0000000..e677be3
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Include/Protocol/SmbiosSlotPopulation.h
@@ -0,0 +1,52 @@
+/*++\r
+\r
+  Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+Module Name:\r
+\r
+    SmbiosSlotPopulation.h\r
+\r
+Abstract:\r
+\r
+    EFI SMBIOS slot structure control code.\r
+\r
+GUID:\r
+    {EF7BF7D6-F8FF-4a76-8247-C0D0D1CC49C0}\r
+    0xef7bf7d6, 0xf8ff, 0x4a76, 0x82, 0x47, 0xc0, 0xd0, 0xd1, 0xcc, 0x49, 0xc0\r
+\r
+Revision History\r
+\r
+**/\r
+\r
+#ifndef _EFI_SMBIOS_SLOT_POPULATION_H_\r
+#define _EFI_SMBIOS_SLOT_POPULATION_H_\r
+\r
+//\r
+// Slot Population Protocol GUID\r
+//\r
+#define EFI_SMBIOS_SLOT_POPULATION_GUID \\r
+  { 0xef7bf7d6, 0xf8ff, 0x4a76, 0x82, 0x47, 0xc0, 0xd0, 0xd1, 0xcc, 0x49, 0xc0 }\r
+\r
+typedef struct {\r
+  UINT16      SmbiosSlotId;   // SMBIOS Slot ID\r
+  BOOLEAN     InUse;          // Does the slot have a card in it\r
+  BOOLEAN     Disabled;       // Should the slot information be in SMBIOS\r
+} EFI_SMBIOS_SLOT_ENTRY;\r
+\r
+typedef struct {\r
+  UINT32                NumberOfEntries;\r
+  EFI_SMBIOS_SLOT_ENTRY *SlotEntries;\r
+} EFI_SMBIOS_SLOT_POPULATION_INFO;\r
+\r
+extern EFI_GUID gEfiSmbiosSlotPopulationGuid;\r
+\r
+#endif\r

diff --git a/Vlv2TbltDevicePkg/Include/Protocol/Speaker.h b/Vlv2TbltDevicePkg/Include/Protocol/Speaker.h
new file mode 100644 (file)
index 0000000..f76d632
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Include/Protocol/Speaker.h
@@ -0,0 +1,70 @@
+/*++\r
+\r
+  Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+Module Name:\r
+\r
+  Speaker.h\r
+\r
+Abstract:\r
+\r
+  EFI Speaker Interface Protocol\r
+\r
+Revision History\r
+\r
+**/\r
+\r
+#ifndef _EFI_SPEAKER_H\r
+#define _EFI_SPEAKER_H\r
+\r
+//\r
+// Global Id for Speaker Interface\r
+//\r
+#define EFI_SPEAKER_INTERFACE_PROTOCOL_GUID \\r
+  { \\r
+    0x400b4476, 0x3081, 0x11d6, 0x87, 0xed, 0x00, 0x06, 0x29, 0x45, 0xc3, 0xb9 \\r
+  }\r
+\r
+typedef struct _EFI_SPEAKER_IF_PROTOCOL  EFI_SPEAKER_IF_PROTOCOL;\r
+\r
+//\r
+// Beep Code\r
+//\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *EFI_GENERATE_BEEP) (\r
+  IN EFI_SPEAKER_IF_PROTOCOL                * This,\r
+  IN     UINTN                              NumberOfBeep,\r
+  IN     UINTN                              BeepDuration,\r
+  IN     UINTN                              TimeInterval\r
+  );\r
+\r
+//\r
+// Set Frequency\r
+//\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *EFI_SPEAKER_SET_FREQUENCY) (\r
+  IN EFI_SPEAKER_IF_PROTOCOL               * This,\r
+  IN     UINT16                            Frequency\r
+  );\r
+\r
+//\r
+// Protocol definition\r
+//\r
+struct _EFI_SPEAKER_IF_PROTOCOL {\r
+  EFI_SPEAKER_SET_FREQUENCY SetSpeakerToneFrequency;\r
+  EFI_GENERATE_BEEP         GenerateBeep;\r
+} ;\r
+\r
+extern EFI_GUID gEfiSpeakerInterfaceProtocolGuid;\r
+#endif\r

diff --git a/Vlv2TbltDevicePkg/Include/Protocol/TcoReset.h b/Vlv2TbltDevicePkg/Include/Protocol/TcoReset.h
new file mode 100644 (file)
index 0000000..d8047d4
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Include/Protocol/TcoReset.h
@@ -0,0 +1,72 @@
+/*++\r
+\r
+  Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+\r
+Module Name:\r
+\r
+  TcoReset.h\r
+\r
+Abstract:\r
+\r
+  Protocol to communicate with ICH TCO.\r
+\r
+GUID Info:\r
+ {A6A79162-E325-4c30-BCC3-59373064EFB3}\r
+ 0xa6a79162, 0xe325, 0x4c30, 0xbc, 0xc3, 0x59, 0x37, 0x30, 0x64, 0xef, 0xb3);\r
+\r
+\r
+--*/\r
+\r
+#ifndef _TCO_RESET_H_\r
+#define _TCO_RESET_H_\r
+\r
+\r
+#define EFI_TCO_RESET_PROTOCOL_GUID  \\r
+  {0xa6a79162, 0xe325, 0x4c30, 0xbc, 0xc3, 0x59, 0x37, 0x30, 0x64, 0xef, 0xb3}\r
+\r
+typedef struct _EFI_TCO_RESET_PROTOCOL EFI_TCO_RESET_PROTOCOL;\r
+\r
+/**\r
+  Enables the TCO timer to reset the system in case of a system hang.  This is\r
+  used when writing the clock registers.\r
+\r
+  @param[in] RcrbGcsSaveValue  This is the value of the RCRB GCS register before it is\r
+                               changed by this procedure.  This will be used to restore\r
+                               the settings of this register in PpiDisableTcoReset.\r
+**/\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *EFI_TCO_RESET_PROTOCOL_ENABLE_TCO_RESET) (\r
+  IN      UINT32            *RcrbGcsSaveValue\r
+  );\r
+\r
+/**\r
+  Disables the TCO timer.  This is used after writing the clock registers.\r
+\r
+  @param[in] RcrbGcsRestoreValue  Value saved in PpiEnableTcoReset so that it can\r
+                                  restored.\r
+**/\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *EFI_TCO_RESET_PROTOCOL_DISABLE_TCO_RESET) (\r
+  OUT     UINT32    RcrbGcsRestoreValue\r
+  );\r
+\r
+typedef struct _EFI_TCO_RESET_PROTOCOL {\r
+  EFI_TCO_RESET_PROTOCOL_ENABLE_TCO_RESET       EnableTcoReset;\r
+  EFI_TCO_RESET_PROTOCOL_DISABLE_TCO_RESET     DisableTcoReset;\r
+} EFI_TCO_RESET_PROTOCOL;\r
+\r
+extern EFI_GUID gEfiTcoResetProtocolGuid;\r
+\r
+#endif\r

diff --git a/Vlv2TbltDevicePkg/Include/Protocol/TpmMp.h b/Vlv2TbltDevicePkg/Include/Protocol/TpmMp.h
new file mode 100644 (file)
index 0000000..8ce0848
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Include/Protocol/TpmMp.h
@@ -0,0 +1,141 @@
+/*++\r
+\r
+  Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+\r
+Module Name:\r
+\r
+  Tpm.h\r
+\r
+Abstract:\r
+\r
+\r
+--*/\r
+\r
+#ifndef __EFI_TPM_MP_DRIVER_PROTOCOL_H__\r
+#define __EFI_TPM_MP_DRIVER_PROTOCOL_H__\r
+\r
+\r
+#define EFI_TPM_MP_DRIVER_PROTOCOL_GUID \\r
+  { 0xde161cfe, 0x1e60, 0x42a1, 0x8c, 0xc3, 0xee, 0x7e, 0xf0, 0x73, 0x52, 0x12 }\r
+\r
+\r
+EFI_FORWARD_DECLARATION (EFI_TPM_MP_DRIVER_PROTOCOL);\r
+\r
+#define TPM_DRIVER_STATUS         0\r
+#define TPM_DEVICE_STATUS         1\r
+\r
+#define TPM_DRIVER_OK             0\r
+#define TPM_DRIVER_FAILED         1\r
+#define TPM_DRIVER_NOT_OPENED     2\r
+#define TPM_DEVICE_OK             0\r
+#define TPM_DEVICE_UNRECOVERABLE  1\r
+#define TPM_DEVICE_RECOVERABLE    2\r
+#define TPM_DEVICE_NOT_FOUND      3\r
+\r
+//\r
+// Prototypes for the TPM MP Driver Protocol\r
+//\r
+\r
+/**\r
+  This service Open the TPM interface\r
+\r
+  @param[in] This             A pointer to the EFI_TPM_MP_DRIVER_PROTOCOL.\r
+\r
+  @retval  EFI_SUCCESS        Operation completed successfully\r
+  @retval  EFI_DEVICE_ERROR   The command was unsuccessful\r
+  @retval  EFI_NOT_FOUND      The component was not running\r
+\r
+**/\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *EFI_TPM_MP_INIT) (\r
+  IN EFI_TPM_MP_DRIVER_PROTOCOL   *This\r
+  );\r
+\r
+/**\r
+  This service close the TPM interface and deactivate TPM\r
+\r
+  @param[in] This            A pointer to the EFI_TPM_MP_DRIVER_PROTOCOL.\r
+\r
+  @retval EFI_SUCCESS        Operation completed successfully\r
+  @retval EFI_DEVICE_ERROR   The command was unsuccessful\r
+  @retval EFI_NOT_FOUND      The component was not running\r
+\r
+**/\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *EFI_TPM_MP_CLOSE) (\r
+  IN EFI_TPM_MP_DRIVER_PROTOCOL   *This\r
+  );\r
+\r
+/**\r
+  This service get the current status infomation of TPM\r
+\r
+  @param[in]  This                  A pointer to the EFI_TPM_MP_DRIVER_PROTOCOL.\r
+  @param[in]  ReqStatusType            Requested type of status information, driver or device.\r
+  @param[in]  Status                 Pointer to the returned status.\r
+\r
+  @retval  EFI_SUCCESS              Operation completed successfully\r
+  @retval  EFI_DEVICE_ERROR         The command was unsuccessful\r
+  @retval  EFI_INVALID_PARAMETER    One or more of the parameters are incorrect\r
+  @retval  EFI_BUFFER_TOO_SMALL     The receive buffer is too small\r
+  @retval  EFI_NOT_FOUND            The component was not running\r
+\r
+**/\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *EFI_TPM_MP_GET_STATUS_INFO) (\r
+  IN EFI_TPM_MP_DRIVER_PROTOCOL   *This,\r
+  IN UINT32                                            ReqStatusType,\r
+  OUT UINT32                                         *Status\r
+  );\r
+\r
+/**\r
+  This service transmit data to the TPM and get response from TPM\r
+\r
+  @param[in] This                  A pointer to the EFI_TPM_MP_DRIVER_PROTOCOL.\r
+  @param[in] TransmitBuf                Pointer to a buffer containing TPM transmit data.\r
+  @param[in] TransmitBufLen           Sizeof TPM input buffer in bytes.\r
+  @param[in] ReceiveBuf                   Pointer to a buffer containing TPM receive data.\r
+  @param[in]  ReceiveBufLen           On input, size of TPM receive buffer in bytes.\r
+                                   On output, number of bytes written.\r
+\r
+  @retval  EFI_SUCCESS             Operation completed successfully\r
+  @retval  EFI_DEVICE_ERROR        The command was unsuccessful\r
+  @retval  EFI_INVALID_PARAMETER   One or more of the parameters are incorrect\r
+  @retval  EFI_BUFFER_TOO_SMALL    The receive buffer is too small\r
+  @retval  EFI_NOT_FOUND           The component was not running\r
+\r
+**/\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *EFI_TPM_MP_TRANSMIT) (\r
+  IN EFI_TPM_MP_DRIVER_PROTOCOL   *This,\r
+  IN UINT8                                                 *TransmitBuffer,\r
+  IN UINT32                                          TransmitBufferLen,\r
+  OUT UINT8                                                *ReceiveBuf,\r
+  IN OUT UINT32                                          *ReceiveBufLen\r
+  );\r
+\r
+\r
+\r
+typedef struct _EFI_TPM_MP_DRIVER_PROTOCOL {\r
+  EFI_TPM_MP_INIT                                    Init;\r
+  EFI_TPM_MP_CLOSE                                 Close;\r
+  EFI_TPM_MP_GET_STATUS_INFO               GetStatusInfo;\r
+  EFI_TPM_MP_TRANSMIT                      Transmit;\r
+} EFI_TPM_MP_DRIVER_PROTOCOL;\r
+\r
+extern EFI_GUID gEfiTpmMpDriverProtocolGuid;\r
+\r
+#endif\r

diff --git a/Vlv2TbltDevicePkg/Include/Protocol/UsbPolicy.h b/Vlv2TbltDevicePkg/Include/Protocol/UsbPolicy.h
new file mode 100644 (file)
index 0000000..31ac22e
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Include/Protocol/UsbPolicy.h
@@ -0,0 +1,131 @@
+/*++\r
+\r
+  Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+Module Name:\r
+  UsbPolicy.h\r
+\r
+Abstract:\r
+\r
+--*/\r
+\r
+#ifndef _USB_POLICY_H_\r
+#define _USB_POLICY_H_\r
+\r
+EFI_FORWARD_DECLARATION (EFI_USB_POLICY_PROTOCOL);\r
+\r
+#define USB_POLICY_GUID \\r
+  {\\r
+    0xf617b358, 0x12cf, 0x414a, 0xa0, 0x69, 0x60, 0x67, 0x7b, 0xda, 0x13, 0xb4\\r
+  }\r
+\r
+#define TIANO_CODE_BASE           0x00\r
+#define ICBD_CODE_BASE            0x01\r
+\r
+#define ATUO_TYPE                 0x00\r
+#define USB_FDD_TYPE              0x01\r
+#define HDD_TYPE                  0x02\r
+#define ZIP_TYPE                  0x03\r
+#define CDROM_TYPE                0x04\r
+#define SIZE_TYPE                 0x05\r
+\r
+#define ZIP_FDD                 0x80\r
+\r
+#define FDD_EMULATION             0x00\r
+#define HDD_EMULATION             0x01\r
+\r
+#define HIGH_SPEED                0x00\r
+#define FULL_SPEED                0x01\r
+#define SUPER_SPEED               0x02\r
+\r
+#define LEGACY_KB_EN              0x01\r
+#define LEGACY_KB_DIS             0x00\r
+#define LEGACY_MS_EN              0x01\r
+#define LEGACY_MS_DIS             0x00\r
+#define LEGACY_USB_EN             0x00\r
+#define LEGACY_USB_DIS            0x01\r
+#define LEGACY_FREE_SUPP          0x01\r
+#define LEGACY_FREE_UN_SUPP       0x00\r
+#define LEGACY_PERIOD_SUPP        0x01\r
+#define LEGACY_PERIOD_UN_SUPP     0x00\r
+\r
+#define LEGACY_USB_TIME_TUE_ENABLE       0x01\r
+#define LEGACY_USB_TIME_TUE_DISABLE      0x00\r
+#define USB_HAVE_HUB_INTERNEL            0x01\r
+#define USB_NOT_HAVE_HUB_INTERNEL        0x00\r
+\r
+#define USB_POLICY_PROTOCOL_REVISION_1 1\r
+#define USB_POLICY_PROTOCOL_REVISION_2 2\r
+\r
+#ifndef __GNUC__\r
+#pragma warning ( disable : 4306 )\r
+#pragma warning ( disable : 4054 )\r
+#endif\r
+\r
+#define GET_USB_CFG (UsbCfg);\\r
+ do{\\r
+  UINT16                *pSegOfEbda;\\r
+  UINT32                mToEbda;\\r
+  pSegOfEbda = (UINT16 *)(UINTN)0x40E;\\r
+  mToEbda    = (UINT32)(((UINTN)(*pSegOfEbda) << 4) + 0x80);\\r
+  UsbCfg     = (USB_CFG *)(UINTN)mToEbda;\\r
+ }while(0);\r
+\r
+#pragma    pack(1)\r
+typedef struct {\r
+    UINT8   HasUSBKeyboard:1;\r
+    UINT8   HasUSBMouse:1;\r
+    UINT8   LegacyFreeSupport:1;\r
+    UINT8   UsbOperationMode:1;\r
+    UINT8   LegacyKBEnable:1;\r
+    UINT8   LegacyMSEnable:1;\r
+    UINT8   USBPeriodSupport:1;\r
+    UINT8   Reserved:1;\r
+} USB_DEVICE_INFOR;\r
+\r
+typedef struct {\r
+    UINT8               Codebase;\r
+    UINT8               USBHDDForceType;\r
+    UINT8               Configurated;\r
+    UINT8               LpcAcpiBase;\r
+    UINT8               AcpiTimerReg;\r
+    UINT8               Reserved1[0x01];\r
+    UINT8               LegacyUsbEnable;\r
+    USB_DEVICE_INFOR    UsbDeviceInfor;\r
+    UINT16              UsbEmulationSize;\r
+    UINT8               Reserved2[0x06];\r
+} USB_CFG;\r
+#pragma pack()\r
+\r
+typedef struct _EFI_USB_POLICY_PROTOCOL{\r
+  UINT8   Version;\r
+  UINT8   UsbMassStorageEmulationType;  // 1: FDD_Type; 2: HDD_Type; other:Auto_Type*\r
+  UINT8   UsbOperationMode;             // 0: High_Speed; 1: Full_Speed;\r
+  UINT8   LegacyKBEnable;               // 0: Disabled;   1: Enabled*\r
+  UINT8   LegacyMSEnable;               // 0: Disabled;   1: Enabled*\r
+  UINT8   USBPeriodSupport;             // 0; Unsupport;  1: Support\r
+  UINT8   LegacyUsbEnable;              // 1: Disabled;   0: Enabled*\r
+  UINT8   LegacyFreeSupport;            // 0: Unsupport;  1: Support\r
+  UINT8   CodeBase;\r
+  UINT8   LpcAcpiBase;                  // 40h(default)\r
+  UINT8   AcpiTimerReg;\r
+  UINT8   UsbTimeTue;\r
+  UINT8   InternelHubExist;             // 1: Host have internel hub on board; 0: No internel hub on board\r
+  UINT8   EnumWaitPortStableStall;      // Value for wait port stable when enum a new dev.\r
+  UINT16  UsbEmulationSize;             // Mbytes.\r
+  UINT8   UsbZipEmulationType;\r
+  UINT8   Reserved[3];                  // Reserved fields for future expansion w/o protocol change\r
+} EFI_USB_POLICY_PROTOCOL;\r
+\r
+extern EFI_GUID gUsbPolicyGuid;\r
+\r
+#endif\r

diff --git a/Vlv2TbltDevicePkg/Include/Protocol/VlvPlatformPolicy.h b/Vlv2TbltDevicePkg/Include/Protocol/VlvPlatformPolicy.h
new file mode 100644 (file)
index 0000000..8e50093
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Include/Protocol/VlvPlatformPolicy.h
@@ -0,0 +1,108 @@
+/** \r
+  Copyright (c) 2009 - 2013, Intel Corporation. All rights reserved.<BR>\r
+  This program and the accompanying materials\r
+  are licensed and made available under the terms and conditions of the BSD License\r
+  which accompanies this distribution.  The full text of the license may be found at\r
+  http://opensource.org/licenses/bsd-license.php\r
+\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+Module Name:\r
+\r
+  VlvPlatformPolicy.h\r
+\r
+Abstract:\r
+\r
+  Interface definition details between MCH and platform drivers during DXE phase.\r
+\r
+--*/\r
+\r
+#ifndef _VLV_PLATFORM_POLICY_H_\r
+#define _VLV_PLATFORM_POLICY_H_\r
+\r
+//\r
+// VLV Policy provided by platform for DXE phase {5BAB88BA-E0E2-4674-B6AD-B812F6881CD6}\r
+//\r
+#define DXE_VLV_PLATFORM_POLICY_GUID \\r
+  {0x5bab88ba, 0xe0e2, 0x4674, 0xb6, 0xad, 0xb8, 0x12, 0xf6, 0x88, 0x1c, 0xd6}\r
+\r
+//\r
+// Extern the GUID for protocol users.\r
+//\r
+extern EFI_GUID gDxeVlvPlatformPolicyGuid;\r
+\r
+//\r
+// Protocol revision number\r
+// Any backwards compatible changes to this protocol will result in an update in the revision number\r
+// Major changes will require publication of a new protocol\r
+//\r
+#define DXE_VLV_PLATFORM_POLICY_PROTOCOL_REVISION 0\r
+\r
+\r
+typedef struct {\r
+  UINT8  PFITStatus;\r
+  UINT8  IgdTheramlSupport;\r
+  UINT8  ALSEnabled;\r
+  UINT8  LidStatus;\r
+} IGD_PANEL_FEATURES;\r
+\r
+typedef struct {\r
+  UINT8   Reserved00;                     \r
+  UINT8   Reserved01;                     \r
+  UINT16  Reserved02;  \r
+  UINT16  Reserved03; \r
+  UINT16  Reserved04; \r
+  UINT16  Reserved05;  \r
+  UINT16  Reserved06;  \r
+  UINT16  Reserved07; \r
+  UINT16  Reserved08; \r
+  UINT16  Reserved09;  \r
+  UINT16  Reserved0A; \r
+  UINT16  Reserved0B;\r
+  UINT16  Reserved0C;\r
+  UINT16  Reserved0D;\r
+  UINT8   Reserved0E;\r
+  UINT8   Reserved0F;\r
+  UINT32  Reserved10;\r
+  UINT32  Reserved11;\r
+  UINT32  Reserved12;\r
+  UINT32  Reserved13;\r
+  UINT32  Reserved14;\r
+  UINT8   Reserved15;\r
+  UINT8   Reserved16;\r
+} DPTF_SETTINGS;\r
+\r
+//\r
+// MCH DXE Platform Policiy ==================================================\r
+//\r
+\r
+#define NO_AUDIO   0\r
+#define HD_AUDIO   1\r
+#define LPE_AUDIO  2\r
+\r
+typedef struct _DXE_VLV_PLATFORM_POLICY_PROTOCOL {\r
+  UINT8                   Revision;\r
+  IGD_PANEL_FEATURES      IgdPanelFeatures;\r
+  DPTF_SETTINGS           Reserved;\r
+  UINT8                   GraphicReserve00;\r
+  UINT8                   GraphicsPerfAnalyzers;\r
+  UINT8                   PwmReserved00;\r
+  UINT8                   PwmReserved01;  \r
+  UINT8                   PmSupport;\r
+  UINT8                   GraphicReserve01;\r
+  UINT8                   GfxPause;\r
+  UINT8                   GraphicsFreqReq;\r
+  UINT8                   GraphicReserve03;\r
+  UINT8                   GraphicReserve02;\r
+  UINT8                   GraphicReserve04;\r
+  UINT8                   PavpMode;\r
+  UINT8                   GraphicReserve05;\r
+  UINT8                   UlClockGating;\r
+  UINT8                   IdleReserve;\r
+  UINT8                   AudioTypeSupport;\r
+  UINT8                   GraphicReserve06;\r
+} DXE_VLV_PLATFORM_POLICY_PROTOCOL;\r
+\r
+#endif\r

diff --git a/Vlv2TbltDevicePkg/Include/SetupMode.h b/Vlv2TbltDevicePkg/Include/SetupMode.h
new file mode 100644 (file)
index 0000000..f0ec67c
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Include/SetupMode.h
@@ -0,0 +1,90 @@
+/*++\r
+\r
+  Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+\r
+Module Name:\r
+\r
+    SetupMode.h\r
+\r
+Abstract:\r
+\r
+    EFI Setup Mode\r
+\r
+\r
+\r
+--*/\r
+\r
+#ifndef _EFI_SETUP_MODE_H_\r
+#define _EFI_SETUP_MODE_H_\r
+\r
+//\r
+// Global ID for the Setup Mode\r
+//\r
+#define EFI_PLATFORM_BOOT_MODE_GUID \\r
+  { 0xce845704, 0x1683, 0x4d38, 0xa4, 0xf9, 0x7d, 0xb, 0x50, 0x77, 0x57, 0x93 }\r
+\r
+#define EFI_NORMAL_SETUP_GUID \\r
+  { 0xec87d643, 0xeba4, 0x4bb5, 0xa1, 0xe5, 0x3f, 0x3e, 0x36, 0xb2, 0xd, 0xa9 }\r
+\r
+#define EFI_NORMAL_SETUP_RESET_NAME L"Reset"\r
+\r
+enum {\r
+  //\r
+  // This means: "whatever reset defaults in setup does"\r
+  //\r
+  SetupDataResetNormal        = 0,\r
+\r
+  //\r
+  // This means: "the defaults built into the BIOS"\r
+  //\r
+  SetupDataResetStandard      = 1,\r
+\r
+  //\r
+  // This means: "the manufacturing mode defaults"\r
+  //\r
+  SetupDataResetManufacturing = 2,\r
+\r
+  //\r
+  // This means: "the oem defaults"\r
+  //\r
+  SetupDataResetOem           = 3,\r
+};\r
+\r
+//\r
+// PlatformBootMode types\r
+//\r
+#define PLATFORM_NORMAL_MODE          0x01\r
+#define PLATFORM_SAFE_MODE            0x02\r
+#define PLATFORM_RECOVERY_MODE        0x04\r
+#define PLATFORM_MANUFACTURING_MODE   0x08\r
+#define PLATFORM_BACK_TO_BIOS_MODE    0x10\r
+\r
+extern EFI_GUID gEfiPlatformBootModeGuid;\r
+\r
+#define   NORMAL_SETUP_NAME                L"Setup"\r
+#define   IN_SETUP_NAME                    L"InSetup"\r
+#define   SYSTEM_PASSWORD_NAME             L"SystemPassword"\r
+#define   BOOT_TIME_NAME                   L"BootTime"\r
+\r
+extern EFI_GUID gEfiNormalSetupGuid;\r
+extern CHAR16   gEfiNormalSetupName[];\r
+extern CHAR16   gEfiInSetupName[];\r
+extern CHAR16   gEfiSystemPasswordName[];\r
+\r
+typedef struct {\r
+  EFI_GUID    SetupGuid;\r
+  CHAR16      SetupName[0x20];          // Maximum "Setup" Name\r
+  UINT32      PlatformBootMode;\r
+} EFI_PLATFORM_SETUP_ID;\r
+\r
+#endif\r

diff --git a/Vlv2TbltDevicePkg/IntelGopDepex/IntelGopDriver.depex b/Vlv2TbltDevicePkg/IntelGopDepex/IntelGopDriver.depex
new file mode 100644 (file)
index 0000000..011f929
--- /dev/null
+++ b/Vlv2TbltDevicePkg/IntelGopDepex/IntelGopDriver.depex
@@ -0,0 +1 @@
+\ 2\e\93.ì\812¥H\81\aß\8a\8bí<]\b
\ No newline at end of file

diff --git a/Vlv2TbltDevicePkg/Library/BiosIdLib/BiosIdLib.c b/Vlv2TbltDevicePkg/Library/BiosIdLib/BiosIdLib.c
new file mode 100644 (file)
index 0000000..01897b3
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Library/BiosIdLib/BiosIdLib.c
@@ -0,0 +1,342 @@
+/*++\r
+\r
+Copyright (c) 2011  - 2014, Intel Corporation. All rights reserved\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+Module Name:\r
+\r
+  BiosIdLib.c\r
+\r
+Abstract:\r
+\r
+  Boot service DXE BIOS ID library implementation.\r
+\r
+  These functions in this file can be called during DXE and cannot be called during runtime\r
+  or in SMM which should use a RT or SMM library.\r
+\r
+--*/\r
+\r
+#include <PiDxe.h>\r
+#include <Library/BaseLib.h>\r
+#include <Library/HobLib.h>\r
+#include <Library/UefiBootServicesTableLib.h>\r
+#include <Library/BaseMemoryLib.h>\r
+#include <Library/DebugLib.h>\r
+\r
+#include <Library/BiosIdLib.h>\r
+#include <Guid/BiosId.h>\r
+#include <Protocol/FirmwareVolume2.h>\r
+#include <Protocol/LoadedImage.h>\r
+\r
+\r
+EFI_STATUS\r
+GetImageFromFv (\r
+  IN  EFI_FIRMWARE_VOLUME2_PROTOCOL *Fv,\r
+  IN  EFI_GUID           *NameGuid,\r
+  IN  EFI_SECTION_TYPE   SectionType,\r
+  OUT VOID               **Buffer,\r
+  OUT UINTN              *Size\r
+  )\r
+{\r
+  EFI_STATUS                Status;\r
+  EFI_FV_FILETYPE           FileType;\r
+  EFI_FV_FILE_ATTRIBUTES    Attributes;\r
+  UINT32                    AuthenticationStatus;\r
+\r
+  //\r
+  // Read desired section content in NameGuid file\r
+  //\r
+  *Buffer     = NULL;\r
+  *Size       = 0;\r
+  Status      = Fv->ReadSection (\r
+                      Fv,\r
+                      NameGuid,\r
+                      SectionType,\r
+                      0,\r
+                      Buffer,\r
+                      Size,\r
+                      &AuthenticationStatus\r
+                      );\r
+\r
+  if (EFI_ERROR (Status) && (SectionType == EFI_SECTION_TE)) {\r
+    //\r
+    // Try reading PE32 section, since the TE section does not exist\r
+    //\r
+    *Buffer = NULL;\r
+    *Size   = 0;\r
+    Status  = Fv->ReadSection (\r
+                    Fv,\r
+                    NameGuid,\r
+                    EFI_SECTION_PE32,\r
+                    0,\r
+                    Buffer,\r
+                    Size,\r
+                    &AuthenticationStatus\r
+                    );\r
+  }\r
+\r
+  if (EFI_ERROR (Status) &&\r
+      ((SectionType == EFI_SECTION_TE) || (SectionType == EFI_SECTION_PE32))) {\r
+    //\r
+    // Try reading raw file, since the desired section does not exist\r
+    //\r
+    *Buffer = NULL;\r
+    *Size   = 0;\r
+    Status  = Fv->ReadFile (\r
+                    Fv,\r
+                    NameGuid,\r
+                    Buffer,\r
+                    Size,\r
+                    &FileType,\r
+                    &Attributes,\r
+                    &AuthenticationStatus\r
+                    );\r
+  }\r
+\r
+  return Status;\r
+}\r
+\r
+\r
+EFI_STATUS\r
+GetImageEx (\r
+  IN  EFI_HANDLE         ImageHandle,\r
+  IN  EFI_GUID           *NameGuid,\r
+  IN  EFI_SECTION_TYPE   SectionType,\r
+  OUT VOID               **Buffer,\r
+  OUT UINTN              *Size,\r
+  BOOLEAN                WithinImageFv\r
+  )\r
+{\r
+  EFI_STATUS                    Status;\r
+  EFI_HANDLE                    *HandleBuffer;\r
+  UINTN                         HandleCount;\r
+  UINTN                         Index;\r
+  EFI_LOADED_IMAGE_PROTOCOL     *LoadedImage;\r
+\r
+  EFI_FIRMWARE_VOLUME2_PROTOCOL *ImageFv;\r
+  EFI_FIRMWARE_VOLUME2_PROTOCOL *Fv;\r
+\r
+\r
+  if (ImageHandle == NULL && WithinImageFv) {\r
+    return EFI_INVALID_PARAMETER;\r
+  }\r
+\r
+  Status  = EFI_NOT_FOUND;\r
+  ImageFv = NULL;\r
+  if (ImageHandle != NULL) {\r
+    Status = gBS->HandleProtocol (\r
+                    ImageHandle,\r
+                    &gEfiLoadedImageProtocolGuid,\r
+                    (VOID **) &LoadedImage\r
+                    );\r
+    if (EFI_ERROR (Status)) {\r
+      return Status;\r
+    }\r
+    Status = gBS->HandleProtocol (\r
+                    LoadedImage->DeviceHandle,\r
+                    &gEfiFirmwareVolume2ProtocolGuid,\r
+                    (VOID **) &ImageFv\r
+                    );\r
+    if (!EFI_ERROR (Status)) {\r
+      Status = GetImageFromFv (ImageFv, NameGuid, SectionType, Buffer, Size);\r
+    }\r
+  }\r
+\r
+  if (Status == EFI_SUCCESS || WithinImageFv) {\r
+    return Status;\r
+  }\r
+\r
+  Status = gBS->LocateHandleBuffer (\r
+                  ByProtocol,\r
+                  &gEfiFirmwareVolume2ProtocolGuid,\r
+                  NULL,\r
+                  &HandleCount,\r
+                  &HandleBuffer\r
+                  );\r
+  if (EFI_ERROR (Status)) {\r
+    return Status;\r
+  }\r
+\r
+  //\r
+  // Find desired image in all Fvs\r
+  //\r
+  for (Index = 0; Index < HandleCount; ++Index) {\r
+    Status = gBS->HandleProtocol (\r
+                    HandleBuffer[Index],\r
+                    &gEfiFirmwareVolume2ProtocolGuid,\r
+                    (VOID**)&Fv\r
+                    );\r
+\r
+    if (EFI_ERROR (Status)) {\r
+      gBS->FreePool(HandleBuffer);\r
+      return Status;\r
+    }\r
+\r
+    if (ImageFv != NULL && Fv == ImageFv) {\r
+      continue;\r
+    }\r
+\r
+    Status = GetImageFromFv (Fv, NameGuid, SectionType, Buffer, Size);\r
+\r
+    if (!EFI_ERROR (Status)) {\r
+      break;\r
+    }\r
+  }\r
+  gBS->FreePool(HandleBuffer);\r
+\r
+  //\r
+  // Not found image\r
+  //\r
+  if (Index == HandleCount) {\r
+    return EFI_NOT_FOUND;\r
+  }\r
+\r
+  return EFI_SUCCESS;\r
+}\r
+\r
+/**\r
+  This function returns BIOS ID by searching HOB or FV.\r
+\r
+  @param BiosIdImage             The BIOS ID got from HOB or FV.\r
+\r
+  @retval EFI_SUCCESS            All parameters were valid and BIOS ID has been got.\r
+  @retval EFI_NOT_FOUND          BiosId image is not found, and no parameter will be modified.\r
+  @retval EFI_INVALID_PARAMETER  The parameter is NULL.\r
+\r
+**/\r
+EFI_STATUS\r
+GetBiosId (\r
+  OUT BIOS_ID_IMAGE     *BiosIdImage\r
+  )\r
+\r
+{\r
+  EFI_STATUS    Status;\r
+  VOID          *Address = NULL;\r
+  UINTN         Size = 0;\r
+\r
+    DEBUG ((EFI_D_INFO, "Get BIOS ID from FV\n"));\r
+\r
+    Status = GetImageEx (\r
+               NULL,\r
+               &gEfiBiosIdGuid,\r
+               EFI_SECTION_RAW,\r
+               &Address,\r
+               &Size,\r
+               FALSE\r
+               );\r
+\r
+    if (Status == EFI_SUCCESS) {\r
+      //\r
+      // BiosId image is present in FV\r
+      //\r
+      if (Address != NULL) {\r
+        Size = sizeof (BIOS_ID_IMAGE);\r
+        gBS->CopyMem (\r
+              (void *) BiosIdImage,\r
+              Address,\r
+              Size\r
+              );\r
+        //\r
+        // GetImage () allocated buffer for Address, now clear it.\r
+        //\r
+        gBS->FreePool (Address);\r
+\r
+        DEBUG ((EFI_D_INFO, "Get BIOS ID from FV successfully\n"));\r
+        DEBUG ((EFI_D_INFO, "BIOS ID: %s\n", (CHAR16 *) (&(BiosIdImage->BiosIdString))));\r
+\r
+        return EFI_SUCCESS;\r
+      }\r
+    }\r
+  return EFI_NOT_FOUND;\r
+}\r
+\r
+/**\r
+  This function returns the Version & Release Date and Time by getting and converting\r
+  BIOS ID.\r
+\r
+  @param BiosVersion  The Bios Version out of the conversion.\r
+  @param BiosReleaseDate  The Bios Release Date out of the conversion.\r
+  @param BiosReleaseTime - The Bios Release Time out of the conversion.\r
+\r
+  @retval EFI_SUCCESS - BIOS Version & Release Date and Time have been got successfully.\r
+  @retval EFI_NOT_FOUND - BiosId image is not found, and no parameter will be modified.\r
+  @retval EFI_INVALID_PARAMETER - All the parameters are NULL.\r
+\r
+**/\r
+EFI_STATUS\r
+GetBiosVersionDateTime (\r
+  OUT CHAR16    *BiosVersion, OPTIONAL\r
+  OUT CHAR16    *BiosReleaseDate, OPTIONAL\r
+  OUT CHAR16    *BiosReleaseTime OPTIONAL\r
+  )\r
+{\r
+  EFI_STATUS        Status;\r
+  BIOS_ID_IMAGE     BiosIdImage;\r
+\r
+  if ((BiosVersion == NULL) && (BiosReleaseDate == NULL) && (BiosReleaseTime == NULL)) {\r
+    return EFI_INVALID_PARAMETER;\r
+  }\r
+\r
+  Status = GetBiosId (&BiosIdImage);\r
+  if (EFI_ERROR (Status)) {\r
+    return EFI_NOT_FOUND;\r
+  }\r
+\r
+  if (BiosVersion != NULL) {\r
+    //\r
+    // Fill the BiosVersion data from the BIOS ID.\r
+    //\r
+    StrCpy (BiosVersion, (CHAR16 *) (&(BiosIdImage.BiosIdString)));\r
+  }\r
+\r
+  if (BiosReleaseDate != NULL) {\r
+    //\r
+    // Fill the build timestamp date from the BIOS ID in the "MM/DD/YY" format.\r
+    //\r
+    BiosReleaseDate[0] = BiosIdImage.BiosIdString.TimeStamp[2];\r
+    BiosReleaseDate[1] = BiosIdImage.BiosIdString.TimeStamp[3];\r
+    BiosReleaseDate[2] = (CHAR16) ((UINT8) ('/'));\r
+\r
+    BiosReleaseDate[3] = BiosIdImage.BiosIdString.TimeStamp[4];\r
+    BiosReleaseDate[4] = BiosIdImage.BiosIdString.TimeStamp[5];\r
+    BiosReleaseDate[5] = (CHAR16) ((UINT8) ('/'));\r
+\r
+    //\r
+    // Add 20 for SMBIOS table\r
+    // Current Linux kernel will misjudge 09 as year 0, so using 2009 for SMBIOS table\r
+    //\r
+    BiosReleaseDate[6] = '2';\r
+    BiosReleaseDate[7] = '0';\r
+    BiosReleaseDate[8] = BiosIdImage.BiosIdString.TimeStamp[0];\r
+    BiosReleaseDate[9] = BiosIdImage.BiosIdString.TimeStamp[1];\r
+\r
+    BiosReleaseDate[10] = (CHAR16) ((UINT8) ('\0'));\r
+  }\r
+\r
+  if (BiosReleaseTime != NULL) {\r
+\r
+    //\r
+    // Fill the build timestamp time from the BIOS ID in the "HH:MM" format.\r
+    //\r
+\r
+    BiosReleaseTime[0] = BiosIdImage.BiosIdString.TimeStamp[6];\r
+    BiosReleaseTime[1] = BiosIdImage.BiosIdString.TimeStamp[7];\r
+    BiosReleaseTime[2] = (CHAR16) ((UINT8) (':'));\r
+\r
+    BiosReleaseTime[3] = BiosIdImage.BiosIdString.TimeStamp[8];\r
+    BiosReleaseTime[4] = BiosIdImage.BiosIdString.TimeStamp[9];\r
+\r
+    BiosReleaseTime[5] = (CHAR16) ((UINT8) ('\0'));\r
+  }\r
+\r
+  return  EFI_SUCCESS;\r
+}\r
+\r

diff --git a/Vlv2TbltDevicePkg/Library/BiosIdLib/BiosIdLib.inf b/Vlv2TbltDevicePkg/Library/BiosIdLib/BiosIdLib.inf
new file mode 100644 (file)
index 0000000..59058fe
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Library/BiosIdLib/BiosIdLib.inf
@@ -0,0 +1,55 @@
+#/*++\r
+#\r
+# Copyright (c)  2010  - 2014, Intel Corporation. All rights reserved\r
+#                                                                                  \r\r
+# This program and the accompanying materials are licensed and made available under\r\r
+# the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+# The full text of the license may be found at                                     \r\r
+# http://opensource.org/licenses/bsd-license.php.                                  \r\r
+#                                                                                  \r\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+#                                                                                  \r\r
+\r
+#\r
+#  Module Name:\r
+#\r
+#   BiosIdLib.inf\r
+#\r
+#  Abstract:\r
+#\r
+#    Component description file for BIOS ID library\r
+#\r
+#--*/\r
+[Defines]\r
+  INF_VERSION                    = 0x00010005\r
+  BASE_NAME                      = BiosIdLib\r
+  FILE_GUID                      = 98546145-64F1-4d2e-814F-6BF963DB7930\r
+  MODULE_TYPE                    = BASE\r
+  VERSION_STRING                 = 1.0\r
+  LIBRARY_CLASS                  = BiosIdLib\r
+  PI_SPECIFICATION_VERSION       = 0x0001000A\r
+\r
+[Sources]\r
+  BiosIdLib.c\r
+\r
+[Packages]\r
+  MdePkg/MdePkg.dec\r
+  MdePkg/MdePkg.dec\r
+  MdeModulePkg/MdeModulePkg.dec\r
+  Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec\r
+  Vlv2TbltDevicePkg/PlatformPkg.dec\r
+\r
+[LibraryClasses]\r
+  HobLib\r
+\r
+[Guids]\r
+  gEfiBiosIdGuid\r
+\r
+[Protocols]\r
+  gEfiLoadedImageProtocolGuid\r
+  gEfiFirmwareVolume2ProtocolGuid\r
+\r
+[Depex]\r
+  gEfiLoadedImageProtocolGuid AND\r
+  gEfiFirmwareVolume2ProtocolGuid\r

diff --git a/Vlv2TbltDevicePkg/Library/CpuIA32Lib/CpuIA32Lib.inf b/Vlv2TbltDevicePkg/Library/CpuIA32Lib/CpuIA32Lib.inf
new file mode 100644 (file)
index 0000000..11dff9f
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Library/CpuIA32Lib/CpuIA32Lib.inf
@@ -0,0 +1,46 @@
+#\r
+#\r
+# Copyright (c)  1999  - 2014, Intel Corporation. All rights reserved\r
+#                                                                                  \r\r
+# This program and the accompanying materials are licensed and made available under\r\r
+# the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+# The full text of the license may be found at                                     \r\r
+# http://opensource.org/licenses/bsd-license.php.                                  \r\r
+#                                                                                  \r\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+#                                                                                  \r\r
+#\r
+#\r
+#   Module Name:\r
+#\r
+#     CpuIA32Lib.inf\r
+#\r
+#   Abstract:\r
+#\r
+#     Component description file for the Cpu IA32 library.\r
+#\r
+#--*/\r
+\r
+[defines]\r
+  INF_VERSION                    = 0x00010005\r
+  BASE_NAME                      = CpuIA32Lib\r
+  FILE_GUID                      = 98546178-64F1-4d2e-814F-6BF963DB7930\r
+  MODULE_TYPE                    = BASE\r
+  VERSION_STRING                 = 1.0\r
+  LIBRARY_CLASS                  = CpuIA32Lib\r
+  PI_SPECIFICATION_VERSION       = 0x0001000A\r
+\r
+[Sources]\r
+  EfiCpuVersion.c\r
+\r
+[Sources.IA32]\r
+  IA32/CpuIA32.c\r
+\r
+[Sources.X64]\r
+  X64/Cpu.asm\r
+  X64/Cpu.S\r
+\r
+[Packages]\r
+  MdePkg/MdePkg.dec\r
+  Vlv2TbltDevicePkg/PlatformPkg.dec\r

diff --git a/Vlv2TbltDevicePkg/Library/CpuIA32Lib/EfiCpuVersion.c b/Vlv2TbltDevicePkg/Library/CpuIA32Lib/EfiCpuVersion.c
new file mode 100644 (file)
index 0000000..4d3f1e6
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Library/CpuIA32Lib/EfiCpuVersion.c
@@ -0,0 +1,75 @@
+/** @file\r
+\r
+  Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+Module Name:\r
+\r
+\r
+  EfiCpuVersion.c\r
+\r
+Abstract:\r
+\r
+  Provide cpu version extract considering extended family & model ID.\r
+--*/\r
+\r
+#include <Library/CpuIA32.h>\r
+\r
+/**\r
+  Extract CPU detail version infomation\r
+\r
+  @param  FamilyId    FamilyId, including ExtendedFamilyId\r
+  @param  Model       Model, including ExtendedModel\r
+  @param  SteppingId  SteppingId\r
+  @param  Processor   Processor\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+EfiCpuVersion (\r
+  IN  OUT UINT16  *FamilyId,    OPTIONAL\r
+  IN  OUT UINT8   *Model,       OPTIONAL\r
+  IN  OUT UINT8   *SteppingId,  OPTIONAL\r
+  IN  OUT UINT8   *Processor    OPTIONAL\r
+  )\r
+\r
+{\r
+  EFI_CPUID_REGISTER Register;\r
+  UINT8              TempFamilyId;\r
+\r
+  EfiCpuid (EFI_CPUID_VERSION_INFO, &Register);\r
+\r
+  if (SteppingId != NULL) {\r
+    *SteppingId = (UINT8) (Register.RegEax & 0xF);\r
+  }\r
+\r
+  if (Processor != NULL) {\r
+    *Processor = (UINT8) ((Register.RegEax >> 12) & 0x3);\r
+  }\r
+\r
+  if (Model != NULL || FamilyId != NULL) {\r
+    TempFamilyId = (UINT8) ((Register.RegEax >> 8) & 0xF);\r
+\r
+    if (Model != NULL) {\r
+      *Model = (UINT8) ((Register.RegEax >> 4) & 0xF);\r
+      if (TempFamilyId == 0x6 || TempFamilyId == 0xF) {\r
+        *Model = (UINT8) (*Model  | ((Register.RegEax >> 12) & 0xF0));\r
+      }\r
+    }\r
+\r
+    if (FamilyId != NULL) {\r
+      *FamilyId = TempFamilyId;\r
+      if (TempFamilyId == 0xF) {\r
+        *FamilyId = (UINT8 ) (*FamilyId + (UINT16) ((Register.RegEax >> 20) & 0xFF));\r
+      }\r
+    }\r
+  }\r
+}\r

diff --git a/Vlv2TbltDevicePkg/Library/CpuIA32Lib/IA32/CpuIA32.S b/Vlv2TbltDevicePkg/Library/CpuIA32Lib/IA32/CpuIA32.S
new file mode 100644 (file)
index 0000000..b0c5b28
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Library/CpuIA32Lib/IA32/CpuIA32.S
@@ -0,0 +1,228 @@
+#\r
+#\r
+# Copyright (c)  1999  - 2014, Intel Corporation. All rights reserved\r
+#                                                                                  \r\r
+# This program and the accompanying materials are licensed and made available under\r\r
+# the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+# The full text of the license may be found at                                     \r\r
+# http://opensource.org/licenses/bsd-license.php.                                  \r\r
+#                                                                                  \r\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+#                                                                                  \r\r
+#\r
+#\r
+#Module Name:\r
+#\r
+#  CpuIA32.c\r
+#\r
+#Abstract:\r
+#\r
+#--*/\r
+\r
+##include "CpuIA32.h"\r
+#include "EfiBind.h"\r
+\r
+#---------------------------------------------------------------------------\r
+    .586p:\r
+    #.MODEL flat,C\r
+    .code:\r
+\r
+#---------------------------------------------------------------------------\r
+\r
+.globl ASM_PFX(EfiHalt)\r
+.globl ASM_PFX(EfiWbinvd)\r
+.globl ASM_PFX(EfiInvd)\r
+.globl ASM_PFX(EfiCpuid)\r
+.globl ASM_PFX(EfiReadMsr)\r
+.globl ASM_PFX(EfiWriteMsr)\r
+.globl ASM_PFX(EfiReadTsc)\r
+.globl ASM_PFX(EfiDisableCache)\r
+.globl ASM_PFX(EfiEnableCache)\r
+.globl ASM_PFX(EfiGetEflags)\r
+.globl ASM_PFX(EfiDisableInterrupts)\r
+.globl ASM_PFX(EfiEnableInterrupts)\r
+.globl ASM_PFX(EfiCpuidExt)\r
+\r
+\r
+#VOID\r
+#EfiHalt (\r
+#  VOID\r
+#)\r
+ASM_PFX(EfiHalt):\r
+    hlt\r
+    ret\r
+#EfiHalt ENDP\r
+\r
+#VOID\r
+#EfiWbinvd (\r
+#  VOID\r
+#)\r
+ASM_PFX(EfiWbinvd):\r
+    wbinvd\r
+    ret\r
+#EfiWbinvd ENDP\r
+\r
+#VOID\r
+#EfiInvd (\r
+# VOID\r
+#)\r
+ASM_PFX(EfiInvd):\r
+    invd\r
+    ret\r
+#EfiInvd ENDP\r
+\r
+#VOID\r
+#EfiCpuid (IN UINT32 RegisterInEax,\r
+#          OUT EFI_CPUID_REGISTER *Reg OPTIONAL)\r
+ASM_PFX(EfiCpuid):\r
+    pushl %ebp\r
+    movl %esp, %ebp\r
+    pushl %ebx\r
+    pushl %esi\r
+    pushl %edi\r
+    pushal\r
+\r
+    movl   8(%ebp), %eax           #RegisterInEax\r
+    cpuid\r
+    cmpl   $0, 0xC(%ebp)           # Reg\r
+    je     L1\r
+    movl        0xC(%ebp), %edi         # Reg\r
+\r
+    movl        %eax, (%edi)        # Reg->RegEax\r
+    movl        %ebx, 4(%edi)         # Reg->RegEbx\r
+    movl        %ecx, 8(%edi)         # Reg->RegEcx\r
+    movl        %edx, 0xC(%edi)         # Reg->RegEdx\r
+\r
+L1:\r
+    popal\r
+    popl        %edi\r
+    popl        %esi\r
+    popl        %ebx\r
+    popl        %ebp\r
+\r
+    ret\r
+#EfiCpuid ENDP\r
+\r
+\r
+#UINT64\r
+#EfiReadMsr (\r
+#  IN UINT32 Index\r
+#  );\r
+ASM_PFX(EfiReadMsr):\r
+    movl   4(%esp), %ecx           # Index\r
+    rdmsr\r
+    ret\r
+#EfiReadMsr ENDP\r
+\r
+#VOID\r
+#EfiWriteMsr (\r
+#  IN   UINT32  Index,\r
+#  IN   UINT64  Value\r
+#  );\r
+ASM_PFX(EfiWriteMsr):\r
+    movl   4(%esp), %ecx         # Index\r
+    movl   8(%esp), %eax         # DWORD PTR Value[0]\r
+    movl   0xC(%esp), %edx         # DWORD PTR Value[4]\r
+    wrmsr\r
+    ret\r
+#EfiWriteMsr ENDP\r
+\r
+#UINT64\r
+#EfiReadTsc (\r
+#  VOID\r
+#  )\r
+ASM_PFX(EfiReadTsc):\r
+    rdtsc\r
+    ret\r
+#EfiReadTsc ENDP\r
+\r
+#VOID\r
+#EfiDisableCache (\r
+#  VOID\r
+#)\r
+ASM_PFX(EfiDisableCache):\r
+    movl  %cr0, %eax\r
+    bswapl %eax\r
+    andb  $0x60, %al\r
+    cmpb  $0x60, %al\r
+    je    L2\r
+    movl  %cr0, %eax\r
+    orl   $0x60000000, %eax\r
+    movl  %eax, %cr0\r
+    wbinvd\r
+L2:\r
+    ret\r
+#EfiDisableCache ENDP\r
+\r
+#VOID\r
+#EfiEnableCache (\r
+#  VOID\r
+#  )\r
+ASM_PFX(EfiEnableCache):\r
+    wbinvd\r
+    movl  %cr0, %eax\r
+    andl  $0x9fffffff, %eax\r
+    movl  %eax, %cr0\r
+    ret\r
+#EfiEnableCache ENDP\r
+\r
+#UINT32\r
+#EfiGetEflags (\r
+#  VOID\r
+#  )\r
+ASM_PFX(EfiGetEflags):\r
+    pushfl\r
+    popl %eax\r
+    ret\r
+#EfiGetEflags ENDP\r
+\r
+#VOID\r
+#EfiDisableInterrupts (\r
+#  VOID\r
+#  )\r
+ASM_PFX(EfiDisableInterrupts):\r
+    cli\r
+    ret\r
+#EfiDisableInterrupts ENDP\r
+\r
+#VOID\r
+#EfiEnableInterrupts (\r
+#  VOID\r
+#  )\r
+ASM_PFX(EfiEnableInterrupts):\r
+    sti\r
+    ret\r
+#EfiEnableInterrupts ENDP\r
+\r
+#VOID\r
+#EfiCpuidExt (\r
+#  IN   UINT32              RegisterInEax,\r
+#  IN   UINT32              CacheLevel,\r
+#  OUT  EFI_CPUID_REGISTER  *Regs\r
+#  )\r
+ASM_PFX(EfiCpuidExt):\r
+    push   %ebx\r
+    push   %edi\r
+    push   %esi\r
+    pushal\r
+\r
+    movl   0x30(%esp), %eax           # RegisterInEax\r
+    movl   0x34(%esp), %ecx           # CacheLevel\r
+    cpuid\r
+    movl   0x38(%esp), %edi           # DWORD PTR Regs\r
+\r
+    movl   %eax, (%edi)                 # Reg->RegEax\r
+    movl   %ebx, 4(%edi)                # Reg->RegEbx\r
+    movl   %ecx, 8(%edi)                # Reg->RegEcx\r
+    movl   %edx, 0xC(%edi)              # Reg->RegEdx\r
+\r
+    popal\r
+    pop    %esi\r
+    pop    %edi\r
+    pop    %ebx\r
+    ret\r
+#EfiCpuidExt ENDP\r
+\r
+\r
+\r

diff --git a/Vlv2TbltDevicePkg/Library/CpuIA32Lib/IA32/CpuIA32.asm b/Vlv2TbltDevicePkg/Library/CpuIA32Lib/IA32/CpuIA32.asm
new file mode 100644 (file)
index 0000000..2abef79
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Library/CpuIA32Lib/IA32/CpuIA32.asm
@@ -0,0 +1,211 @@
+;\r
+; This file contains an 'Intel Sample Driver' and is\r
+; licensed for Intel CPUs and chipsets under the terms of your\r
+; license agreement with Intel or your vendor.  This file may\r
+; be modified by the user, subject to additional terms of the\r
+; license agreement\r
+;\r
+;\r
+; Copyright (c)  1999  - 2014, Intel Corporation. All rights reserved\r
+;                                                                                  \r\r
+; This program and the accompanying materials are licensed and made available under\r\r
+; the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+; The full text of the license may be found at                                     \r\r
+; http://opensource.org/licenses/bsd-license.php.                                  \r\r
+;                                                                                  \r\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+;                                                                                  \r\r
+;\r
+\r
+;Module Name:\r
+;\r
+;  CpuIA32.c\r
+;\r
+;Abstract:\r
+;\r
+;--*/\r
+\r
+;#include "CpuIA32.h"\r
+\r
+;---------------------------------------------------------------------------\r
+    .586p\r
+    .model  flat,C\r
+    .code\r
+\r
+;---------------------------------------------------------------------------\r
+;VOID\r
+;EfiHalt (\r
+;  VOID\r
+;)\r
+EfiHalt PROC C PUBLIC\r
+    hlt\r
+    ret\r
+EfiHalt ENDP\r
+\r
+;VOID\r
+;EfiWbinvd (\r
+;  VOID\r
+;)\r
+EfiWbinvd PROC C PUBLIC\r
+    wbinvd\r
+    ret\r
+EfiWbinvd ENDP\r
+\r
+;VOID\r
+;EfiInvd (\r
+; VOID\r
+;)\r
+EfiInvd PROC C PUBLIC\r
+    invd\r
+    ret\r
+EfiInvd ENDP\r
+\r
+;VOID\r
+;EfiCpuid (IN UINT32 RegisterInEax,\r
+;          OUT EFI_CPUID_REGISTER *Reg OPTIONAL)\r
+EfiCpuid PROC C PUBLIC\r
+    push ebp\r
+    mov  ebp, esp\r
+    push ebx\r
+    push esi\r
+    push edi\r
+    pushad\r
+\r
+    mov    eax, dword ptr[ebp + 8] ;egisterInEax\r
+    cpuid\r
+    cmp    dword ptr[ebp + 0Ch], 0 ; Reg\r
+    je     @F\r
+    mov         edi,dword ptr [ebp+0Ch] ; Reg\r
+\r
+    mov         dword ptr [edi],eax ; Reg->RegEax\r
+    mov         dword ptr [edi+4],ebx ; Reg->RegEbx\r
+    mov         dword ptr [edi+8],ecx ; Reg->RegEcx\r
+    mov         dword ptr [edi+0Ch],edx ; Reg->RegEdx\r
+\r
+@@:\r
+    popad\r
+    pop         edi\r
+    pop         esi\r
+    pop         ebx\r
+    pop         ebp\r
+\r
+    ret\r
+EfiCpuid ENDP\r
+\r
+\r
+;UINT64\r
+;EfiReadMsr (\r
+;  IN UINT32 Index\r
+;  );\r
+EfiReadMsr PROC C PUBLIC\r
+    mov    ecx, dword ptr [esp + 4]; Index\r
+    rdmsr\r
+    ret\r
+EfiReadMsr ENDP\r
+\r
+;VOID\r
+;EfiWriteMsr (\r
+;  IN   UINT32  Index,\r
+;  IN   UINT64  Value\r
+;  );\r
+EfiWriteMsr PROC C PUBLIC\r
+    mov    ecx, dword ptr [esp+4]; Index\r
+    mov    eax, dword ptr [esp+8]; DWORD PTR Value[0]\r
+    mov    edx, dword ptr [esp+0Ch]; DWORD PTR Value[4]\r
+    wrmsr\r
+    ret\r
+EfiWriteMsr  ENDP\r
+\r
+;UINT64\r
+;EfiReadTsc (\r
+;  VOID\r
+;  )\r
+EfiReadTsc PROC C PUBLIC\r
+    rdtsc\r
+    ret\r
+EfiReadTsc  ENDP\r
+\r
+;VOID\r
+;EfiDisableCache (\r
+;  VOID\r
+;)\r
+EfiDisableCache PROC C PUBLIC\r
+    mov   eax, cr0\r
+    bswap eax\r
+    and   al, 60h\r
+    cmp   al, 60h\r
+    je    @F\r
+    mov   eax, cr0\r
+    or    eax, 060000000h\r
+    mov   cr0, eax\r
+    wbinvd\r
+@@:\r
+    ret\r
+EfiDisableCache  ENDP\r
+\r
+;VOID\r
+;EfiEnableCache (\r
+;  VOID\r
+;  )\r
+EfiEnableCache PROC C PUBLIC\r
+    wbinvd\r
+    mov   eax, cr0\r
+    and   eax, 09fffffffh\r
+    mov   cr0, eax\r
+    ret\r
+EfiEnableCache  ENDP\r
+\r
+;UINT32\r
+;EfiGetEflags (\r
+;  VOID\r
+;  )\r
+EfiGetEflags PROC C PUBLIC\r
+    pushfd\r
+    pop  eax\r
+    ret\r
+EfiGetEflags  ENDP\r
+\r
+;VOID\r
+;EfiDisableInterrupts (\r
+;  VOID\r
+;  )\r
+EfiDisableInterrupts PROC C PUBLIC\r
+    cli\r
+    ret\r
+EfiDisableInterrupts  ENDP\r
+\r
+;VOID\r
+;EfiEnableInterrupts (\r
+;  VOID\r
+;  )\r
+EfiEnableInterrupts  PROC C PUBLIC\r
+    sti\r
+    ret\r
+EfiEnableInterrupts   ENDP\r
+\r
+;VOID\r
+;EfiCpuidExt (\r
+;  IN   UINT32              RegisterInEax,\r
+;  IN   UINT32              CacheLevel,\r
+;  OUT  EFI_CPUID_REGISTER  *Regs\r
+;  )\r
+EfiCpuidExt PROC C PUBLIC USES ebx edi esi\r
+    pushad\r
+\r
+    mov    eax, dword ptr [esp + 30h] ; RegisterInEax\r
+    mov    ecx, dword ptr [esp + 34h] ; CacheLevel\r
+    cpuid\r
+    mov    edi, dword ptr [esp + 38h] ; DWORD PTR Regs\r
+\r
+    mov    dword ptr [edi], eax        ; Reg->RegEax\r
+    mov    dword ptr [edi + 4], ebx    ; Reg->RegEbx\r
+    mov    dword ptr [edi + 8], ecx    ; Reg->RegEcx\r
+    mov    dword ptr [edi + 0Ch], edx   ; Reg->RegEdx\r
+\r
+    popad\r
+    ret\r
+EfiCpuidExt  ENDP\r
+\r
+       END\r
+\r

diff --git a/Vlv2TbltDevicePkg/Library/CpuIA32Lib/IA32/CpuIA32.c b/Vlv2TbltDevicePkg/Library/CpuIA32Lib/IA32/CpuIA32.c
new file mode 100644 (file)
index 0000000..aa18718
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Library/CpuIA32Lib/IA32/CpuIA32.c
@@ -0,0 +1,182 @@
+/** @file\r
+\r
+  Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+Module Name:\r
+\r
+\r
+  CpuIA32.c\r
+\r
+Abstract:\r
+\r
+--*/\r
+\r
+#include <Library/CpuIA32.h>\r
+\r
+VOID\r
+EfiHalt (VOID)\r
+{\r
+  __asm {\r
+    hlt\r
+  }\r
+}\r
+\r
+VOID\r
+EfiWbinvd (VOID)\r
+{\r
+  __asm {\r
+    wbinvd\r
+  }\r
+}\r
+\r
+VOID\r
+EfiInvd (VOID)\r
+{\r
+  __asm {\r
+    invd\r
+  }\r
+}\r
+\r
+VOID\r
+EfiCpuid (IN UINT32 RegisterInEax,\r
+          OUT EFI_CPUID_REGISTER *Reg OPTIONAL)\r
+{\r
+  __asm {\r
+    pushad\r
+\r
+    mov    eax, RegisterInEax\r
+    cpuid\r
+    cmp    Reg, 0\r
+    je     _Exit\r
+    mov    edi, DWORD PTR Reg\r
+\r
+    mov    DWORD PTR [edi].RegEax, eax   ; Reg->RegEax\r
+    mov    DWORD PTR [edi].RegEbx, ebx   ; Reg->RegEbx\r
+    mov    DWORD PTR [edi].RegEcx, ecx   ; Reg->RegEcx\r
+    mov    DWORD PTR [edi].RegEdx, edx   ; Reg->RegEdx\r
+\r
+_Exit:\r
+     popad\r
+  }\r
+}\r
+\r
+UINT64\r
+EfiReadMsr (IN UINT32 Index)\r
+{\r
+  __asm {\r
+    mov    ecx, Index\r
+    rdmsr\r
+  }\r
+}\r
+\r
+VOID\r
+EfiWriteMsr (\r
+  IN   UINT32  Index,\r
+  IN   UINT64  Value\r
+  )\r
+{\r
+  __asm {\r
+    mov    ecx, Index\r
+    mov    eax, DWORD PTR Value[0]\r
+    mov    edx, DWORD PTR Value[4]\r
+    wrmsr\r
+  }\r
+}\r
+\r
+UINT64\r
+EfiReadTsc (VOID)\r
+{\r
+  __asm {\r
+    rdtsc\r
+  }\r
+}\r
+\r
+VOID\r
+EfiDisableCache (VOID)\r
+{\r
+  __asm {\r
+    mov   eax, cr0\r
+    bswap eax\r
+    and   al, 60h\r
+    cmp   al, 60h\r
+    je    Exit\r
+    mov   eax, cr0\r
+    or    eax, 060000000h\r
+    mov   cr0, eax\r
+    wbinvd\r
+Exit:\r
+  }\r
+}\r
+\r
+VOID\r
+EfiEnableCache (VOID)\r
+{\r
+  __asm {\r
+    wbinvd\r
+    mov   eax, cr0\r
+    and   eax, 09fffffffh\r
+    mov   cr0, eax\r
+  }\r
+}\r
+\r
+UINT32\r
+EfiGetEflags (\r
+  VOID\r
+  )\r
+{\r
+  __asm {\r
+    pushfd\r
+    pop  eax\r
+  }\r
+}\r
+\r
+VOID\r
+EfiDisableInterrupts (VOID)\r
+{\r
+  __asm {\r
+    cli\r
+  }\r
+}\r
+\r
+VOID\r
+EfiEnableInterrupts (\r
+  VOID\r
+  )\r
+{\r
+  __asm {\r
+    sti\r
+  }\r
+}\r
+\r
+VOID\r
+EfiCpuidExt (\r
+  IN   UINT32              RegisterInEax,\r
+  IN   UINT32              CacheLevel,\r
+  OUT  EFI_CPUID_REGISTER  *Regs\r
+  )\r
+{\r
+  __asm {\r
+    pushad\r
+\r
+    mov    eax, RegisterInEax\r
+    mov    ecx, CacheLevel\r
+    cpuid\r
+    mov    edi, DWORD PTR Regs\r
+\r
+    mov    DWORD PTR [edi].RegEax, eax   ; Reg->RegEax\r
+    mov    DWORD PTR [edi].RegEbx, ebx   ; Reg->RegEbx\r
+    mov    DWORD PTR [edi].RegEcx, ecx   ; Reg->RegEcx\r
+    mov    DWORD PTR [edi].RegEdx, edx   ; Reg->RegEdx\r
+\r
+    popad\r
+  }\r
+}\r

diff --git a/Vlv2TbltDevicePkg/Library/CpuIA32Lib/X64/Cpu.S b/Vlv2TbltDevicePkg/Library/CpuIA32Lib/X64/Cpu.S
new file mode 100644 (file)
index 0000000..1eab73d
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Library/CpuIA32Lib/X64/Cpu.S
@@ -0,0 +1,212 @@
+#\r
+#\r
+# Copyright (c)  1999  - 2014, Intel Corporation. All rights reserved\r
+#                                                                                  \r\r
+# This program and the accompanying materials are licensed and made available under\r\r
+# the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+# The full text of the license may be found at                                     \r\r
+# http://opensource.org/licenses/bsd-license.php.                                  \r\r
+#                                                                                  \r\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+#                                                                                  \r\r
+#\r
+#\r
+#*   Module Name:\r
+#*\r
+#*    Cpu.asm\r
+#*\r
+#*   Abstract:\r
+#*\r
+#------------------------------------------------------------------------------\r
+##include <EfiBind.h>\r
+\r
+.globl ASM_PFX(EfiHalt)\r
+.globl ASM_PFX(EfiWbinvd)\r
+.globl ASM_PFX(EfiInvd)\r
+.globl ASM_PFX(EfiCpuid)\r
+.globl ASM_PFX(EfiReadTsc)\r
+.globl ASM_PFX(EfiDisableCache)\r
+.globl ASM_PFX(EfiEnableCache)\r
+.globl ASM_PFX(EfiReadMsr)\r
+.globl ASM_PFX(EfiWriteMsr)\r
+.globl ASM_PFX(EfiGetEflags)\r
+.globl ASM_PFX(EfiDisableInterrupts)\r
+.globl ASM_PFX(EfiEnableInterrupts)\r
+.globl ASM_PFX(EfiCpuidExt)\r
+\r
+.text\r
+\r
+\r
+#------------------------------------------------------------------------------\r
+#  VOID\r
+#  EfiHalt (\r
+#    VOID\r
+#    )\r
+#------------------------------------------------------------------------------\r
+ASM_PFX(EfiHalt):\r
+    hlt\r
+    retq\r
+\r
+\r
+#------------------------------------------------------------------------------\r
+#  VOID\r
+#  EfiWbinvd (\r
+#    VOID\r
+#    )\r
+#------------------------------------------------------------------------------\r
+ASM_PFX(EfiWbinvd):\r
+    wbinvd\r
+    retq\r
+\r
+\r
+#------------------------------------------------------------------------------\r
+#  VOID\r
+#  EfiInvd (\r
+#    VOID\r
+#    )\r
+#------------------------------------------------------------------------------\r
+ASM_PFX(EfiInvd):\r
+    invd\r
+    retq\r
+\r
+#------------------------------------------------------------------------------\r
+#  VOID\r
+#  EfiCpuid (\r
+#    IN   UINT32              RegisterInEax,          // rcx\r
+#    OUT  EFI_CPUID_REGISTER  *Reg           OPTIONAL // rdx\r
+#    )\r
+#------------------------------------------------------------------------------\r
+ASM_PFX(EfiCpuid):\r
+      push   %rbx\r
+      mov    %rdx,%r8\r
+      mov    %rcx,%rax\r
+      cpuid\r
+      cmp    $0x0,%r8\r
+      je     _Exit\r
+      mov    %eax,(%r8)\r
+      mov    %ebx,0x4(%r8)\r
+      mov    %ecx,0x8(%r8)\r
+      mov    %edx,0xc(%r8)\r
+_Exit:\r
+      pop    %rbx\r
+      retq\r
+\r
+#------------------------------------------------------------------------------\r
+#  UINT64\r
+#  EfiReadMsr (\r
+#    IN   UINT32  Index,  // rcx\r
+#    )\r
+#------------------------------------------------------------------------------\r
+ASM_PFX(EfiReadMsr):\r
+      rdmsr\r
+      shl    $0x20,%rdx\r
+      or     %rdx,%rax\r
+      retq\r
+\r
+#------------------------------------------------------------------------------\r
+#  VOID\r
+#  EfiWriteMsr (\r
+#    IN   UINT32  Index,  // rcx\r
+#    IN   UINT64  Value   // rdx\r
+#    )\r
+#------------------------------------------------------------------------------\r
+ASM_PFX(EfiWriteMsr):\r
+      mov    %rdx,%rax\r
+      sar    $0x20,%rdx\r
+      wrmsr\r
+      retq\r
+\r
+#------------------------------------------------------------------------------\r
+# UINT64\r
+# EfiReadTsc (\r
+#   VOID\r
+#   );\r
+#------------------------------------------------------------------------------\r
+ASM_PFX(EfiReadTsc):\r
+      rdtsc\r
+      shl    $0x20,%rax\r
+      shrd   $0x20,%rdx,%rax\r
+      retq\r
+\r
+#------------------------------------------------------------------------------\r
+# VOID\r
+# EfiDisableCache (\r
+#   VOID\r
+#   );\r
+#------------------------------------------------------------------------------\r
+ASM_PFX(EfiDisableCache):\r
+# added a check to see if cache is already disabled. If it is, then skip.\r
+      mov    %cr0,%rax\r
+      and    $0x60000000,%rax\r
+      cmp    $0x0,%rax\r
+      jne    1f\r
+      mov    %cr0,%rax\r
+      or     $0x60000000,%rax\r
+      mov    %rax,%cr0\r
+      wbinvd\r
+1:\r
+      retq\r
+\r
+#------------------------------------------------------------------------------\r
+# VOID\r
+# EfiEnableCache (\r
+#   VOID\r
+#   );\r
+#------------------------------------------------------------------------------\r
+ASM_PFX(EfiEnableCache):\r
+      wbinvd\r
+      mov    %cr0,%rax\r
+      and    $0xffffffff9fffffff,%rax\r
+      mov    %rax,%cr0\r
+      retq\r
+\r
+#------------------------------------------------------------------------------\r
+# UINTN\r
+# EfiGetEflags (\r
+#   VOID\r
+#   );\r
+#------------------------------------------------------------------------------\r
+ASM_PFX(EfiGetEflags):\r
+      pushfq\r
+      pop    %rax\r
+      retq\r
+\r
+#------------------------------------------------------------------------------\r
+# VOID\r
+# EfiDisableInterrupts (\r
+#   VOID\r
+#   );\r
+#------------------------------------------------------------------------------\r
+ASM_PFX(EfiDisableInterrupts):\r
+    cli\r
+    ret\r
+\r
+#------------------------------------------------------------------------------\r
+# VOID\r
+# EfiEnableInterrupts (\r
+#   VOID\r
+#   );\r
+#------------------------------------------------------------------------------\r
+ASM_PFX(EfiEnableInterrupts):\r
+    sti\r
+    ret\r
+#------------------------------------------------------------------------------\r
+#  VOID\r
+#  EfiCpuidExt (\r
+#    IN   UINT32              RegisterInEax,\r
+#    IN   UINT32              CacheLevel,\r
+#    OUT  EFI_CPUID_REGISTER  *Regs\r
+#    )\r
+#------------------------------------------------------------------------------\r
+ASM_PFX(EfiCpuidExt):\r
+      push   %rbx\r
+      mov    %rcx,%rax\r
+      mov    %rdx,%rcx\r
+      cpuid\r
+      mov    %eax,(%r8)\r
+      mov    %ebx,0x4(%r8)\r
+      mov    %ecx,0x8(%r8)\r
+      mov    %edx,0xc(%r8)\r
+      pop    %rbx\r
+      retq\r

diff --git a/Vlv2TbltDevicePkg/Library/CpuIA32Lib/X64/Cpu.asm b/Vlv2TbltDevicePkg/Library/CpuIA32Lib/X64/Cpu.asm
new file mode 100644 (file)
index 0000000..d921132
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Library/CpuIA32Lib/X64/Cpu.asm
@@ -0,0 +1,227 @@
+\r
+TITLE   Cpu.asm: Assembly code for the x64 resources\r
+\r
+;\r
+; This file contains an 'Intel Sample Driver' and is\r
+; licensed for Intel CPUs and chipsets under the terms of your\r
+; license agreement with Intel or your vendor.  This file may\r
+; be modified by the user, subject to additional terms of the\r
+; license agreement\r
+;\r
+;\r
+; Copyright (c)  1999  - 2014, Intel Corporation. All rights reserved\r
+;                                                                                  \r\r
+; This program and the accompanying materials are licensed and made available under\r\r
+; the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+; The full text of the license may be found at                                     \r\r
+; http://opensource.org/licenses/bsd-license.php.                                  \r\r
+;                                                                                  \r\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+;                                                                                  \r\r
+;\r
+;\r
+;\r
+;\r
+;*   Module Name:\r
+;*\r
+;*    Cpu.asm\r
+;*\r
+;*   Abstract:\r
+;*\r
+;------------------------------------------------------------------------------\r
+\r
+text    SEGMENT\r
+\r
+\r
+;------------------------------------------------------------------------------\r
+;  VOID\r
+;  EfiHalt (\r
+;    VOID\r
+;    )\r
+;------------------------------------------------------------------------------\r
+EfiHalt PROC    PUBLIC\r
+    hlt\r
+    ret\r
+EfiHalt ENDP\r
+\r
+\r
+;------------------------------------------------------------------------------\r
+;  VOID\r
+;  EfiWbinvd (\r
+;    VOID\r
+;    )\r
+;------------------------------------------------------------------------------\r
+EfiWbinvd PROC    PUBLIC\r
+    wbinvd\r
+    ret\r
+EfiWbinvd ENDP\r
+\r
+\r
+;------------------------------------------------------------------------------\r
+;  VOID\r
+;  EfiInvd (\r
+;    VOID\r
+;    )\r
+;------------------------------------------------------------------------------\r
+EfiInvd PROC    PUBLIC\r
+    invd\r
+    ret\r
+EfiInvd ENDP\r
+\r
+;------------------------------------------------------------------------------\r
+;  VOID\r
+;  EfiCpuid (\r
+;    IN   UINT32              RegisterInEax,          // rcx\r
+;    OUT  EFI_CPUID_REGISTER  *Reg           OPTIONAL // rdx\r
+;    )\r
+;------------------------------------------------------------------------------\r
+EfiCpuid PROC   PUBLIC\r
+    push  rbx\r
+\r
+    mov   r8,   rdx         ; r8 = *Reg\r
+    mov   rax,  rcx         ; RegisterInEax\r
+    cpuid\r
+    cmp   r8,   0\r
+    je    _Exit\r
+    mov   [r8 +  0], eax    ; Reg->RegEax\r
+    mov   [r8 +  4], ebx    ; Reg->RegEbx\r
+    mov   [r8 +  8], ecx    ; Reg->RegEcx\r
+    mov   [r8 + 12], edx    ; Reg->RegEdx\r
+\r
+_Exit:\r
+    pop   rbx\r
+    ret\r
+EfiCpuid  ENDP\r
+\r
+;------------------------------------------------------------------------------\r
+;  UINT64\r
+;  EfiReadMsr (\r
+;    IN   UINT32  Index,  // rcx\r
+;    )\r
+;------------------------------------------------------------------------------\r
+EfiReadMsr PROC  PUBLIC\r
+    rdmsr\r
+    sal     rdx, 32   ; edx:eax -> rax\r
+    or      rax, rdx  ; rax = edx:eax\r
+    ret\r
+EfiReadMsr  ENDP\r
+\r
+;------------------------------------------------------------------------------\r
+;  VOID\r
+;  EfiWriteMsr (\r
+;    IN   UINT32  Index,  // rcx\r
+;    IN   UINT64  Value   // rdx\r
+;    )\r
+;------------------------------------------------------------------------------\r
+EfiWriteMsr PROC   PUBLIC\r
+    mov     rax,  rdx   ; rdx = Value\r
+    sar     rdx,  32    ; convert rdx to edx upper 32-bits\r
+    wrmsr               ; wrmsr[ecx] result = edx:eax\r
+    ret\r
+EfiWriteMsr  ENDP\r
+\r
+\r
+;------------------------------------------------------------------------------\r
+; UINT64\r
+; EfiReadTsc (\r
+;   VOID\r
+;   );\r
+;------------------------------------------------------------------------------\r
+EfiReadTsc PROC    PUBLIC\r
+    rdtsc\r
+    shl     rax, 32\r
+    shrd    rax, rdx, 32\r
+    ret\r
+EfiReadTsc  ENDP\r
+\r
+;------------------------------------------------------------------------------\r
+; VOID\r
+; EfiDisableCache (\r
+;   VOID\r
+;   );\r
+;------------------------------------------------------------------------------\r
+EfiDisableCache PROC    PUBLIC\r
+; added a check to see if cache is already disabled. If it is, then skip.\r
+    mov   rax, cr0\r
+    and   rax, 060000000h\r
+    cmp   rax, 0\r
+    jne   @f\r
+    mov   rax, cr0\r
+    or    rax, 060000000h\r
+    mov   cr0, rax\r
+    wbinvd\r
+@@:\r
+    ret\r
+EfiDisableCache ENDP\r
+\r
+;------------------------------------------------------------------------------\r
+; VOID\r
+; EfiEnableCache (\r
+;   VOID\r
+;   );\r
+;------------------------------------------------------------------------------\r
+EfiEnableCache PROC    PUBLIC\r
+    wbinvd\r
+    mov   rax, cr0\r
+    and   rax, 09fffffffh\r
+    mov   cr0, rax\r
+    ret\r
+EfiEnableCache ENDP\r
+\r
+;------------------------------------------------------------------------------\r
+; UINTN\r
+; EfiGetEflags (\r
+;   VOID\r
+;   );\r
+;------------------------------------------------------------------------------\r
+EfiGetEflags PROC    PUBLIC\r
+    pushfq\r
+    pop   rax\r
+    ret\r
+EfiGetEflags  ENDP\r
+\r
+;------------------------------------------------------------------------------\r
+; VOID\r
+; EfiDisableInterrupts (\r
+;   VOID\r
+;   );\r
+;------------------------------------------------------------------------------\r
+EfiDisableInterrupts PROC    PUBLIC\r
+    cli\r
+    ret\r
+EfiDisableInterrupts  ENDP\r
+\r
+;------------------------------------------------------------------------------\r
+; VOID\r
+; EfiEnableInterrupts (\r
+;   VOID\r
+;   );\r
+;------------------------------------------------------------------------------\r
+EfiEnableInterrupts PROC    PUBLIC\r
+    sti\r
+    ret\r
+EfiEnableInterrupts  ENDP\r
+;------------------------------------------------------------------------------\r
+;  VOID\r
+;  EfiCpuidExt (\r
+;    IN   UINT32              RegisterInEax,\r
+;    IN   UINT32              CacheLevel,\r
+;    OUT  EFI_CPUID_REGISTER  *Regs\r
+;    )\r
+;------------------------------------------------------------------------------\r
+EfiCpuidExt PROC    PUBLIC\r
+     push   rbx\r
+     mov    rax, rcx          ; rax = RegisterInEax\r
+     mov    rcx, rdx          ; rcx = CacheLevel\r
+\r
+     cpuid\r
+     mov    [r8 + 0 ],  eax   ; Reg->RegEax\r
+     mov    [r8 + 4 ],  ebx   ; Reg->RegEbx\r
+     mov    [r8 + 8 ],  ecx   ; Reg->RegEcx\r
+     mov    [r8 + 12],  edx   ; Reg->RegEdx\r
+\r
+     pop rbx\r
+     ret\r
+EfiCpuidExt  ENDP\r
+END\r

diff --git a/Vlv2TbltDevicePkg/Library/EfiRegTableLib/EfiRegTableLib.c b/Vlv2TbltDevicePkg/Library/EfiRegTableLib/EfiRegTableLib.c
new file mode 100644 (file)
index 0000000..fa94cc7
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Library/EfiRegTableLib/EfiRegTableLib.c
@@ -0,0 +1,287 @@
+/*++\r
+\r
+Copyright (c)  1999  - 2014, Intel Corporation. All rights reserved\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+\r
+Module Name:\r
+\r
+  EfiRegTableLib.c\r
+\r
+Abstract:\r
+\r
+  Lib function for table driven register initialization.\r
+\r
+Revision History\r
+\r
+--*/\r
+\r
+#include <Library/EfiRegTableLib.h>\r
+#include <Library/S3BootScriptLib.h>\r
+\r
+//\r
+// Local Functions\r
+//\r
+\r
+/**\r
+  Local worker function to process PCI_WRITE table entries.  Performs write and\r
+  may also call BootScriptSave protocol if indicated in the Entry flags\r
+\r
+  @param Entry            A pointer to the PCI_WRITE entry to process\r
+\r
+  @param PciRootBridgeIo  A pointer to the instance of PciRootBridgeIo that is used\r
+                          when processing the entry.\r
+\r
+  @retval Nothing.\r
+\r
+**/\r
+STATIC\r
+VOID\r
+PciWrite (\r
+  EFI_REG_TABLE_PCI_WRITE             *Entry,\r
+  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL     *PciRootBridgeIo\r
+  )\r
+{\r
+  EFI_STATUS  Status;\r
+\r
+  Status = PciRootBridgeIo->Pci.Write (\r
+                                  PciRootBridgeIo,\r
+                                  (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) (OPCODE_EXTRA_DATA (Entry->OpCode)),\r
+                                  (UINT64) Entry->PciAddress,\r
+                                  1,\r
+                                  &Entry->Data\r
+                                  );\r
+  ASSERT_EFI_ERROR (Status);\r
+\r
+  if (OPCODE_FLAGS (Entry->OpCode) & OPCODE_FLAG_S3SAVE) {\r
+    Status = S3BootScriptSavePciCfgWrite (\r
+              (EFI_BOOT_SCRIPT_WIDTH) (OPCODE_EXTRA_DATA (Entry->OpCode)),\r
+              (UINT64) Entry->PciAddress,\r
+              1,\r
+              &Entry->Data\r
+              );\r
+    ASSERT_EFI_ERROR (Status);\r
+  }\r
+}\r
+\r
+/**\r
+  Local worker function to process PCI_READ_MODIFY_WRITE table entries.\r
+  Performs RMW write and may also call BootScriptSave protocol if indicated in\r
+  the Entry flags.\r
+\r
+  @param Entry            A pointer to the PCI_READ_MODIFY_WRITE entry to process.\r
+\r
+  @param PciRootBridgeIo  A pointer to the instance of PciRootBridgeIo that is used\r
+                          when processing the entry.\r
+\r
+  @retval Nothing.\r
+\r
+**/\r
+STATIC\r
+VOID\r
+PciReadModifyWrite (\r
+  EFI_REG_TABLE_PCI_READ_MODIFY_WRITE *Entry,\r
+  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL     *PciRootBridgeIo\r
+  )\r
+{\r
+  EFI_STATUS  Status;\r
+  UINT32      TempData;\r
+\r
+  Status = PciRootBridgeIo->Pci.Read (\r
+                                  PciRootBridgeIo,\r
+                                  (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) (OPCODE_EXTRA_DATA (Entry->OpCode)),\r
+                                  (UINT64) Entry->PciAddress,\r
+                                  1,\r
+                                  &TempData\r
+                                  );\r
+  ASSERT_EFI_ERROR (Status);\r
+\r
+  Entry->OrMask &= Entry->AndMask;\r
+  TempData &= ~Entry->AndMask;\r
+  TempData |= Entry->OrMask;\r
+\r
+  Status = PciRootBridgeIo->Pci.Write (\r
+                                  PciRootBridgeIo,\r
+                                  (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) (OPCODE_EXTRA_DATA (Entry->OpCode)),\r
+                                  (UINT64) Entry->PciAddress,\r
+                                  1,\r
+                                  &TempData\r
+                                  );\r
+  ASSERT_EFI_ERROR (Status);\r
+\r
+  if (OPCODE_FLAGS (Entry->OpCode) & OPCODE_FLAG_S3SAVE) {\r
+    Status = S3BootScriptSavePciCfgReadWrite (\r
+              (EFI_BOOT_SCRIPT_WIDTH) (OPCODE_EXTRA_DATA (Entry->OpCode)),\r
+              (UINT64) Entry->PciAddress,\r
+              &Entry->OrMask,\r
+              &Entry->AndMask\r
+              );\r
+    ASSERT_EFI_ERROR (Status);\r
+  }\r
+}\r
+\r
+/**\r
+  Local worker function to process MEM_READ_MODIFY_WRITE table entries.\r
+  Performs RMW write and may also call BootScriptSave protocol if indicated in\r
+  the Entry flags.\r
+\r
+  @param Entry            A pointer to the MEM_READ_MODIFY_WRITE entry to process.\r
+\r
+  @param PciRootBridgeIo  A pointer to the instance of PciRootBridgeIo that is used\r
+                          when processing the entry.\r
+\r
+  @retval Nothing.\r
+\r
+**/\r
+STATIC\r
+VOID\r
+MemReadModifyWrite (\r
+  EFI_REG_TABLE_MEM_READ_MODIFY_WRITE *Entry,\r
+  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL     *PciRootBridgeIo\r
+  )\r
+{\r
+  EFI_STATUS  Status;\r
+  UINT32      TempData;\r
+\r
+  Status = PciRootBridgeIo->Mem.Read (\r
+                                  PciRootBridgeIo,\r
+                                  (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) (OPCODE_EXTRA_DATA (Entry->OpCode)),\r
+                                  (UINT64) Entry->MemAddress,\r
+                                  1,\r
+                                  &TempData\r
+                                  );\r
+  ASSERT_EFI_ERROR (Status);\r
+\r
+  Entry->OrMask &= Entry->AndMask;\r
+  TempData &= ~Entry->AndMask;\r
+  TempData |= Entry->OrMask;\r
+\r
+  Status = PciRootBridgeIo->Mem.Write (\r
+                                  PciRootBridgeIo,\r
+                                  (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) (OPCODE_EXTRA_DATA (Entry->OpCode)),\r
+                                  (UINT64) Entry->MemAddress,\r
+                                  1,\r
+                                  &TempData\r
+                                  );\r
+  ASSERT_EFI_ERROR (Status);\r
+\r
+  if (OPCODE_FLAGS (Entry->OpCode) & OPCODE_FLAG_S3SAVE) {\r
+    Status = S3BootScriptSaveMemReadWrite (\r
+              (EFI_BOOT_SCRIPT_WIDTH) (OPCODE_EXTRA_DATA (Entry->OpCode)),\r
+              Entry->MemAddress,\r
+              &Entry->OrMask,\r
+              &Entry->AndMask\r
+              );\r
+    ASSERT_EFI_ERROR (Status);\r
+  }\r
+}\r
+\r
+//\r
+// Exported functions\r
+//\r
+\r
+/**\r
+  Processes register table assuming which may contain PCI, IO, MEM, and STALL\r
+  entries.\r
+\r
+  No parameter checking is done so the caller must be careful about omitting\r
+  values for PciRootBridgeIo or CpuIo parameters.  If the regtable does\r
+  not contain any PCI accesses, it is safe to omit the PciRootBridgeIo (supply\r
+  NULL).  If the regtable does not contain any IO or Mem entries, it is safe to\r
+  omit the CpuIo (supply NULL).\r
+\r
+  The RegTableEntry parameter is not checked, but is required.\r
+\r
+  gBS is assumed to have been defined and is used when processing stalls.\r
+\r
+  The function processes each entry sequentially until an OP_TERMINATE_TABLE\r
+  entry is encountered.\r
+\r
+  @param RegTableEntry    A pointer to the register table to process\r
+\r
+  @param PciRootBridgeIo  A pointer to the instance of PciRootBridgeIo that is used\r
+                          when processing PCI table entries\r
+\r
+  @param CpuIo            A pointer to the instance of CpuIo that is used when processing IO and\r
+                          MEM table entries\r
+\r
+  @retval Nothing.\r
+\r
+**/\r
+VOID\r
+ProcessRegTablePci (\r
+  EFI_REG_TABLE                       *RegTableEntry,\r
+  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL     *PciRootBridgeIo,\r
+  EFI_CPU_IO_PROTOCOL                 *CpuIo\r
+  )\r
+{\r
+  while (OPCODE_BASE (RegTableEntry->Generic.OpCode) != OP_TERMINATE_TABLE) {\r
+    switch (OPCODE_BASE (RegTableEntry->Generic.OpCode)) {\r
+    case OP_PCI_WRITE:\r
+      PciWrite ((EFI_REG_TABLE_PCI_WRITE *) RegTableEntry, PciRootBridgeIo);\r
+      break;\r
+\r
+    case OP_PCI_READ_MODIFY_WRITE:\r
+      PciReadModifyWrite ((EFI_REG_TABLE_PCI_READ_MODIFY_WRITE *) RegTableEntry, PciRootBridgeIo);\r
+      break;\r
+\r
+    case OP_MEM_READ_MODIFY_WRITE:\r
+      MemReadModifyWrite ((EFI_REG_TABLE_MEM_READ_MODIFY_WRITE *) RegTableEntry, PciRootBridgeIo);\r
+      break;\r
+\r
+    default:\r
+      DEBUG ((EFI_D_ERROR, "RegTable ERROR: Unknown RegTable OpCode (%x)\n", OPCODE_BASE (RegTableEntry->Generic.OpCode)));\r
+      ASSERT (0);\r
+      break;\r
+    }\r
+\r
+    RegTableEntry++;\r
+  }\r
+}\r
+\r
+/**\r
+  Processes register table assuming which may contain IO, MEM, and STALL\r
+  entries, but must NOT contain any PCI entries.  Any PCI entries cause an\r
+  ASSERT in a DEBUG build and are skipped in a free build.\r
+\r
+  No parameter checking is done.  Both RegTableEntry and CpuIo parameters are\r
+  required.\r
+\r
+  gBS is assumed to have been defined and is used when processing stalls.\r
+\r
+  The function processes each entry sequentially until an OP_TERMINATE_TABLE\r
+  entry is encountered.\r
+\r
+  @param  RegTableEntry   A pointer to the register table to process\r
+\r
+  @param  CpuIo           A pointer to the instance of CpuIo that is used when processing IO and\r
+                          MEM table entries\r
+\r
+  @retval Nothing.\r
+\r
+**/\r
+VOID\r
+ProcessRegTableCpu (\r
+  EFI_REG_TABLE                       *RegTableEntry,\r
+  EFI_CPU_IO_PROTOCOL                 *CpuIo\r
+  )\r
+{\r
+  while (OPCODE_BASE (RegTableEntry->Generic.OpCode) != OP_TERMINATE_TABLE) {\r
+    switch (OPCODE_BASE (RegTableEntry->Generic.OpCode)) {\r
+    default:\r
+      DEBUG ((EFI_D_ERROR, "RegTable ERROR: Unknown RegTable OpCode (%x)\n", OPCODE_BASE (RegTableEntry->Generic.OpCode)));\r
+      ASSERT (0);\r
+      break;\r
+    }\r
+\r
+    RegTableEntry++;\r
+  }\r
+}\r

diff --git a/Vlv2TbltDevicePkg/Library/EfiRegTableLib/EfiRegTableLib.inf b/Vlv2TbltDevicePkg/Library/EfiRegTableLib/EfiRegTableLib.inf
new file mode 100644 (file)
index 0000000..9a6b29b
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Library/EfiRegTableLib/EfiRegTableLib.inf
@@ -0,0 +1,52 @@
+#\r
+#\r
+#/*++\r
+#\r
+# Copyright (c)  1999  - 2014, Intel Corporation. All rights reserved\r
+#                                                                                  \r\r
+# This program and the accompanying materials are licensed and made available under\r\r
+# the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+# The full text of the license may be found at                                     \r\r
+# http://opensource.org/licenses/bsd-license.php.                                  \r\r
+#                                                                                  \r\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+#                                                                                  \r\r
+\r
+#\r
+#  Module Name:\r
+#\r
+#    EfiRegTableLib.inf\r
+#\r
+#  Abstract:\r
+#\r
+#    Component description file.\r
+#\r
+#--*/\r
+\r
+[Defines]\r
+  INF_VERSION                    = 0x00010005\r
+  BASE_NAME                      = EfiRegTableLib\r
+  FILE_GUID                      = 98546145-64F1-4d2e-814F-6BF963DB7930\r
+  MODULE_TYPE                    = BASE\r
+  VERSION_STRING                 = 1.0\r
+  LIBRARY_CLASS                  = EfiRegTableLib\r
+\r
+#\r
+# The following information is for reference only and not required by the build tools.\r
+#\r
+#  VALID_ARCHITECTURES           = IA32 X64 IPF EBC\r
+#\r
+\r
+[Sources]\r
+  EfiRegTableLib.c\r
+\r
+[Packages]\r
+  MdePkg/MdePkg.dec\r
+  MdeModulePkg/MdeModulePkg.dec\r
+  Vlv2TbltDevicePkg/PlatformPkg.dec\r
+  IntelFrameworkPkg/IntelFrameworkPkg.dec\r
+\r
+\r
+[LibraryClasses]\r
+\r

diff --git a/Vlv2TbltDevicePkg/Library/FlashDeviceLib/FlashDeviceLib.c b/Vlv2TbltDevicePkg/Library/FlashDeviceLib/FlashDeviceLib.c
new file mode 100644 (file)
index 0000000..afb12c9
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Library/FlashDeviceLib/FlashDeviceLib.c
@@ -0,0 +1,467 @@
+/** @file\r
+\r
+  Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+\r
+**/\r
+\r
+#include <PiDxe.h>\r
+\r
+#include <Library/FlashDeviceLib.h>\r
+#include <Library/DebugLib.h>\r
+#include <Library/BaseLib.h>\r
+#include <Library/UefiBootServicesTableLib.h>\r
+#include <Library/UefiRuntimeServicesTableLib.h>\r
+#include <Library/BaseMemoryLib.h>\r
+#include <Library/UefiRuntimeLib.h>\r
+#include <Protocol/SmmBase2.h>\r
+#include <Guid/EventGroup.h>\r
+#include "SpiChipDefinitions.h"\r
+\r
+UINTN FlashDeviceBase = FLASH_DEVICE_BASE_ADDRESS;\r
+\r
+EFI_SPI_PROTOCOL *mSpiProtocol = NULL;\r
+\r
+EFI_STATUS\r
+SpiFlashErase (\r
+  UINT8 *BaseAddress,\r
+  UINTN NumBytes\r
+  )\r
+{\r
+  EFI_STATUS          Status = EFI_SUCCESS;\r
+  UINT32              SectorSize;\r
+  UINT32              SpiAddress;\r
+\r
+  SpiAddress = (UINT32)(UINTN)(BaseAddress) - (UINT32)FlashDeviceBase;\r
+  SectorSize = SECTOR_SIZE_4KB;\r
+  while ( (NumBytes > 0) && (NumBytes <= MAX_FWH_SIZE) ) {\r
+    Status = mSpiProtocol->Execute (\r
+                             mSpiProtocol,\r
+                             SPI_SERASE,\r
+                             SPI_WREN,\r
+                             FALSE,\r
+                             TRUE,\r
+                             FALSE,\r
+                             (UINT32) SpiAddress,\r
+                             0,\r
+                             NULL,\r
+                             EnumSpiRegionBios\r
+                             );\r
+    if (EFI_ERROR (Status)) {\r
+      break;\r
+    }\r
+    SpiAddress += SectorSize;\r
+    NumBytes   -= SectorSize;\r
+  }\r
+\r
+  return Status;\r
+}\r
+\r
+\r
+EFI_STATUS\r
+SpiFlashBlockErase (\r
+  UINT8 *BaseAddress,\r
+  UINTN NumBytes\r
+  )\r
+{\r
+  EFI_STATUS          Status = EFI_SUCCESS;\r
+  UINT32              SectorSize;\r
+  UINT32              SpiAddress;\r
+\r
+  SpiAddress = (UINT32)(UINTN)(BaseAddress) - (UINT32)FlashDeviceBase;\r
+  SectorSize = SECTOR_SIZE_64KB;\r
+  while ( (NumBytes > 0) && (NumBytes <= MAX_FWH_SIZE) ) {\r
+    Status = mSpiProtocol->Execute (\r
+                             mSpiProtocol,\r
+                             SPI_BERASE,\r
+                             SPI_WREN,\r
+                             FALSE,\r
+                             TRUE,\r
+                             FALSE,\r
+                             (UINT32) SpiAddress,\r
+                             0,\r
+                             NULL,\r
+                             EnumSpiRegionBios\r
+                             );\r
+    if (EFI_ERROR (Status)) {\r
+      break;\r
+    }\r
+    SpiAddress += SectorSize;\r
+    NumBytes   -= SectorSize;\r
+  }\r
+\r
+  return Status;\r
+}\r
+\r
+\r
+static\r
+EFI_STATUS\r
+SpiFlashWrite (\r
+  UINT8 *DstBufferPtr,\r
+  UINT8 *Byte,\r
+  IN  UINTN Length\r
+  )\r
+{\r
+  EFI_STATUS                Status;\r
+  UINT32                    NumBytes = (UINT32)Length;\r
+  UINT8*                    pBuf8 = Byte;\r
+  UINT32                    SpiAddress;\r
+\r
+  SpiAddress = (UINT32)(UINTN)(DstBufferPtr) - (UINT32)FlashDeviceBase;\r
+  Status = mSpiProtocol->Execute (\r
+                           mSpiProtocol,\r
+                           SPI_PROG,\r
+                           SPI_WREN,\r
+                           TRUE,\r
+                           TRUE,\r
+                           TRUE,\r
+                           (UINT32)SpiAddress,\r
+                           NumBytes,\r
+                           pBuf8,\r
+                           EnumSpiRegionBios\r
+                           );\r
+  return Status;\r
+}\r
+\r
+/**\r
+  Read the Serial Flash Status Registers.\r
+\r
+  @param  SpiStatus         Pointer to a caller-allocated UINT8. On successful return, it contains the\r
+                            status data read from the Serial Flash Status Register.\r
+\r
+\r
+  @retval EFI_SUCCESS       Operation success, status is returned in SpiStatus.\r
+  @retval EFI_DEVICE_ERROR  The block device is not functioning correctly and the operation failed.\r
+\r
+**/\r
+EFI_STATUS\r
+ReadStatusRegister (\r
+  UINT8   *SpiStatus\r
+  )\r
+{\r
+  EFI_STATUS          Status;\r
+\r
+  Status = mSpiProtocol->Execute (\r
+             mSpiProtocol,\r
+             SPI_RDSR,\r
+             SPI_WREN,\r
+             TRUE,\r
+             FALSE,\r
+             FALSE,\r
+             0,\r
+             1,\r
+             SpiStatus,\r
+             EnumSpiRegionBios\r
+             );\r
+  return Status;\r
+}\r
+\r
+EFI_STATUS\r
+SpiFlashLock (\r
+    IN  UINT8  *BaseAddress,\r
+    IN  UINTN  NumBytes,\r
+    IN  BOOLEAN  Lock\r
+  )\r
+{\r
+  EFI_STATUS          Status;\r
+  UINT8               SpiData;\r
+  UINT8               SpiStatus;\r
+\r
+  if (Lock) {\r
+    SpiData = SF_SR_WPE;\r
+  } else {\r
+    SpiData = 0;\r
+  }\r
+\r
+  //\r
+  // Always disable block protection to workaround tool issue.\r
+  // Feature may be re-enabled in a future bios.\r
+  //\r
+  SpiData = 0;\r
+  Status = mSpiProtocol->Execute (\r
+                           mSpiProtocol,\r
+                           SPI_WRSR,\r
+                           SPI_EWSR,\r
+                           TRUE,\r
+                           TRUE,\r
+                           TRUE,\r
+                           0,\r
+                           1,\r
+                           &SpiData,\r
+                           EnumSpiRegionBios\r
+                           );\r
+  if (EFI_ERROR (Status)) {\r
+    return Status;\r
+  }\r
+\r
+  Status = ReadStatusRegister (&SpiStatus);\r
+  if (EFI_ERROR (Status)) {\r
+    return Status;\r
+  }\r
+\r
+  if ((SpiStatus & SpiData) != SpiData) {\r
+    Status = EFI_DEVICE_ERROR;\r
+  }\r
+\r
+  return Status;\r
+}\r
+\r
+\r
+/**\r
+  Read NumBytes bytes of data from the address specified by\r
+  PAddress into Buffer.\r
+\r
+  @param[in]      PAddress          The starting physical address of the read.\r
+  @param[in,out]  NumBytes          On input, the number of bytes to read. On output, the number\r
+                                    of bytes actually read.\r
+  @param[out]     Buffer            The destination data buffer for the read.\r
+\r
+  @retval         EFI_SUCCESS.      Opertion is successful.\r
+  @retval         EFI_DEVICE_ERROR  If there is any device errors.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+LibFvbFlashDeviceRead (\r
+  IN      UINTN                           PAddress,\r
+  IN  OUT UINTN                           *NumBytes,\r
+      OUT UINT8                           *Buffer\r
+  )\r
+{\r
+  CopyMem(Buffer, (VOID*)PAddress, *NumBytes);\r
+  return EFI_SUCCESS;\r
+}\r
+\r
+\r
+/**\r
+  Write NumBytes bytes of data from Buffer to the address specified by\r
+  PAddresss.\r
+\r
+  @param[in]      PAddress          The starting physical address of the write.\r
+  @param[in,out]  NumBytes          On input, the number of bytes to write. On output,\r
+                                    the actual number of bytes written.\r
+  @param[in]      Buffer            The source data buffer for the write.\r
+\r
+  @retval         EFI_SUCCESS.      Opertion is successful.\r
+  @retval         EFI_DEVICE_ERROR  If there is any device errors.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+LibFvbFlashDeviceWrite (\r
+  IN        UINTN                           PAddress,\r
+  IN OUT    UINTN                           *NumBytes,\r
+  IN        UINT8                           *Buffer\r
+  )\r
+{\r
+EFI_STATUS Status;\r
+  Status =  SpiFlashWrite((UINT8 *)PAddress, Buffer, *NumBytes);\r
+ return Status;\r
+}\r
+\r
+\r
+/**\r
+  Erase the block staring at PAddress.\r
+\r
+  @param[in]  PAddress          The starting physical address of the block to be erased.\r
+                                This library assume that caller garantee that the PAddress\r
+                                is at the starting address of this block.\r
+  @param[in]  LbaLength         The length of the logical block to be erased.\r
+\r
+  @retval     EFI_SUCCESS.      Opertion is successful.\r
+  @retval     EFI_DEVICE_ERROR  If there is any device errors.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+LibFvbFlashDeviceBlockErase (\r
+  IN    UINTN                     PAddress,\r
+  IN    UINTN                     LbaLength\r
+  )\r
+{\r
+  EFI_STATUS Status;\r
+  Status = SpiFlashBlockErase((UINT8 *)PAddress, LbaLength);\r
+\r
+  return Status;\r
+}\r
+\r
+\r
+/**\r
+  Lock or unlock the block staring at PAddress.\r
+\r
+  @param[in]  PAddress        The starting physical address of region to be (un)locked.\r
+  @param[in]  LbaLength       The length of the logical block to be erased.\r
+  @param[in]  Lock            TRUE to lock. FALSE to unlock.\r
+\r
+  @retval     EFI_SUCCESS.      Opertion is successful.\r
+  @retval     EFI_DEVICE_ERROR  If there is any device errors.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+LibFvbFlashDeviceBlockLock (\r
+  IN    UINTN                          PAddress,\r
+  IN    UINTN                          LbaLength,\r
+  IN    BOOLEAN                        Lock\r
+  )\r
+{\r
+  EFI_STATUS Status;\r
+\r
+    Status = SpiFlashLock((UINT8*)PAddress, LbaLength, Lock);\r
+  return Status;\r
+}\r
+\r
+VOID\r
+EFIAPI\r
+LibFvbFlashDeviceVirtualAddressChangeNotifyEvent (\r
+  IN EFI_EVENT        Event,\r
+  IN VOID             *Context\r
+  )\r
+{\r
+  gRT->ConvertPointer (0, (VOID **) &mSpiProtocol);\r
+  gRT->ConvertPointer (0, (VOID **) &FlashDeviceBase);\r
+}\r
+\r
+\r
+/**\r
+  The library constructuor.\r
+\r
+  The function does the necessary initialization work for this library\r
+  instance. Please put all initialization works in it.\r
+\r
+  @param[in]  ImageHandle       The firmware allocated handle for the UEFI image.\r
+  @param[in]  SystemTable       A pointer to the EFI system table.\r
+\r
+  @retval     EFI_SUCCESS       The function always return EFI_SUCCESS for now.\r
+                                It will ASSERT on error for debug version.\r
+  @retval     EFI_ERROR         Please reference LocateProtocol for error code details.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+LibFvbFlashDeviceSupportInit (\r
+  IN EFI_HANDLE         ImageHandle,\r
+  IN EFI_SYSTEM_TABLE   *SystemTable\r
+  )\r
+{\r
+  EFI_STATUS Status;\r
+  EFI_EVENT  Event;\r
+  UINT8                         SfId[3];\r
+  UINT8                         FlashIndex;\r
+  UINT8                         SpiReadError;\r
+  UINT8                         SpiNotMatchError;\r
+  EFI_SMM_BASE2_PROTOCOL       *SmmBase;\r
+  BOOLEAN                       InSmm;\r
+\r
+  SpiReadError     = 0x00;\r
+  SpiNotMatchError = 0x00;\r
+\r
+  InSmm = FALSE;\r
+  Status = gBS->LocateProtocol (\r
+                  &gEfiSmmBase2ProtocolGuid,\r
+                  NULL,\r
+                  (void **)&SmmBase\r
+                  );\r
+  if (!EFI_ERROR(Status)) {\r
+    Status = SmmBase->InSmm(SmmBase, &InSmm);\r
+    if (EFI_ERROR(Status)) {\r
+      InSmm = FALSE;\r
+    }\r
+  }\r
+\r
+  if (!InSmm) {\r
+    Status = gBS->LocateProtocol (\r
+                  &gEfiSpiProtocolGuid,\r
+                  NULL,\r
+                  (VOID **)&mSpiProtocol\r
+                  );\r
+    ASSERT_EFI_ERROR (Status);\r
+\r
+    Status = gBS->CreateEventEx (\r
+                  EVT_NOTIFY_SIGNAL,\r
+                  TPL_NOTIFY,\r
+                  LibFvbFlashDeviceVirtualAddressChangeNotifyEvent,\r
+                  NULL,\r
+                  &gEfiEventVirtualAddressChangeGuid,\r
+                  &Event\r
+                  );\r
+    ASSERT_EFI_ERROR (Status);\r
+  } else {\r
+    Status = gBS->LocateProtocol (\r
+                    &gEfiSmmSpiProtocolGuid,\r
+                    NULL,\r
+                    (VOID **)&mSpiProtocol\r
+                    );\r
+    ASSERT_EFI_ERROR (Status);\r
+  }\r
+\r
+\r
+  for (FlashIndex = EnumSpiFlashW25Q64; FlashIndex < EnumSpiFlashMax; FlashIndex++) {\r
+    Status = mSpiProtocol->Init (mSpiProtocol, &(mInitTable[FlashIndex]));\r
+    if (!EFI_ERROR (Status)) {\r
+      //\r
+      // Read Vendor/Device IDs to check if the driver supports the Serial Flash device.\r
+      //\r
+      Status = mSpiProtocol->Execute (\r
+                               mSpiProtocol,\r
+                               SPI_READ_ID,\r
+                               SPI_WREN,\r
+                               TRUE,\r
+                               FALSE,\r
+                               FALSE,\r
+                               0,\r
+                               3,\r
+                               SfId,\r
+                               EnumSpiRegionAll\r
+                               );\r
+      if (!EFI_ERROR (Status)) {\r
+        if ((SfId[0] == mInitTable[FlashIndex].VendorId)  &&\r
+            (SfId[1] == mInitTable[FlashIndex].DeviceId0) &&\r
+            (SfId[2] == mInitTable[FlashIndex].DeviceId1)) {\r
+            //\r
+            // Found a matching SPI device, FlashIndex now contains flash device.\r
+            //\r
+            DEBUG ((EFI_D_ERROR, "OK - Found SPI Flash Type in SPI Flash Driver, Device Type ID 0 = 0x%02x!\n", mInitTable[FlashIndex].DeviceId0));\r
+            DEBUG ((EFI_D_ERROR, "Device Type ID 1 = 0x%02x!\n", mInitTable[FlashIndex].DeviceId1));\r
+\r
+            if (mInitTable[FlashIndex].BiosStartOffset == (UINTN) (-1)) {\r
+              DEBUG ((EFI_D_ERROR, "ERROR - The size of BIOS image is bigger than SPI Flash device!\n"));\r
+              CpuDeadLoop ();\r
+            }\r
+            break;\r
+        } else {\r
+          SpiNotMatchError++;\r
+        }\r
+      } else {\r
+        SpiReadError++;\r
+      }\r
+    }\r
+  }\r
+\r
+  DEBUG ((EFI_D_ERROR, "SPI flash chip VID = 0x%X, DID0 = 0x%X, DID1 = 0x%X\n", SfId[0], SfId[1], SfId[2]));\r
+\r
+  if (FlashIndex < EnumSpiFlashMax)  {\r
+    return EFI_SUCCESS;\r
+  } else {\r
+  if (SpiReadError != 0) {\r
+      DEBUG ((EFI_D_ERROR, "ERROR - SPI Read ID execution failed! Error Count = %d\n", SpiReadError));\r
+   }    \r
+    else {\r
+      if (SpiNotMatchError != 0) {\r
+        DEBUG ((EFI_D_ERROR, "ERROR - No supported SPI flash chip found! Error Count = %d\n", SpiNotMatchError));\r
+        DEBUG ((EFI_D_ERROR, "SPI flash chip VID = 0x%X, DID0 = 0x%X, DID1 = 0x%X\n", SfId[0], SfId[1], SfId[2]));\r
+      }\r
+    }\r
+    return EFI_UNSUPPORTED;\r
+  }\r
+}\r
+\r

diff --git a/Vlv2TbltDevicePkg/Library/FlashDeviceLib/FlashDeviceLib.inf b/Vlv2TbltDevicePkg/Library/FlashDeviceLib/FlashDeviceLib.inf
new file mode 100644 (file)
index 0000000..423490e
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Library/FlashDeviceLib/FlashDeviceLib.inf
@@ -0,0 +1,50 @@
+#\r
+#\r
+# Copyright (c)  1999  - 2014, Intel Corporation. All rights reserved\r
+#                                                                                  \r\r
+# This program and the accompanying materials are licensed and made available under\r\r
+# the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+# The full text of the license may be found at                                     \r\r
+# http://opensource.org/licenses/bsd-license.php.                                  \r\r
+#                                                                                  \r\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+#                                                                                  \r\r
+#\r
+#\r
+\r
+\r
+[Defines]\r
+  INF_VERSION                    = 0x00010005\r
+  BASE_NAME                      = FlashDeviceLib\r
+  FILE_GUID                      = E38A1C3C-928C-4bf7-B6C1-7F0EF163FAA5\r
+  MODULE_TYPE                    = DXE_DRIVER\r
+  VERSION_STRING                 = 1.0\r
+  LIBRARY_CLASS                  = FlashDeviceLib | DXE_SMM_DRIVER DXE_RUNTIME_DRIVER\r
+  CONSTRUCTOR                               = LibFvbFlashDeviceSupportInit\r
+\r
+\r
+#\r
+# The following information is for reference only and not required by the build tools.\r
+#\r
+#  VALID_ARCHITECTURES           = IA32 X64\r
+#\r
+\r
+[Sources]\r
+  FlashDeviceLib.c\r
+\r
+\r
+[Packages]\r
+  MdePkg/MdePkg.dec\r
+  MdeModulePkg/MdeModulePkg.dec\r
+  Vlv2TbltDevicePkg/PlatformPkg.dec\r
+  Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec\r
+\r
+[LibraryClasses]\r
+  DebugLib\r
+\r
+[Protocols]\r
+  gEfiSpiProtocolGuid\r
+  gEfiSmmSpiProtocolGuid\r
+  gEfiSmmBase2ProtocolGuid\r
+\r

diff --git a/Vlv2TbltDevicePkg/Library/FlashDeviceLib/SpiChipDefinitions.h b/Vlv2TbltDevicePkg/Library/FlashDeviceLib/SpiChipDefinitions.h
new file mode 100644 (file)
index 0000000..15bd1e0
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Library/FlashDeviceLib/SpiChipDefinitions.h
@@ -0,0 +1,840 @@
+/*++\r
+\r
+  Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+\r
+**/\r
+\r
+#include <Library/SpiFlash.H>\r
+\r
+#define FLASH_SIZE  0x300000\r
+#define FLASH_DEVICE_BASE_ADDRESS (0xFFFFFFFF-FLASH_SIZE+1)\r
+\r
+//\r
+// Serial Flash device initialization data table provided to the\r
+// Intel(R) SPI Host Controller Compatibility Interface.\r
+//\r
+SPI_INIT_TABLE  mInitTable[] = {\r
+  {\r
+  SF_VENDOR_ID_WINBOND,     // VendorId\r
+  SF_DEVICE_ID0_W25QXX,     // DeviceId 0\r
+  SF_DEVICE_ID1_W25Q64,     // DeviceId 1\r
+  {\r
+    SF_INST_WREN,           // Prefix Opcode 0: Write Enable\r
+    SF_INST_EWSR            // Prefix Opcode 1: Enable Write Status Register\r
+  },\r
+  {\r
+    {EnumSpiOpcodeReadNoAddr,     SF_INST_JEDEC_READ_ID,  EnumSpiCycle50MHz, EnumSpiOperationJedecId           },     // Opcode 0: Read ID\r
+    {EnumSpiOpcodeRead,           SF_INST_READ,           EnumSpiCycle50MHz, EnumSpiOperationReadData          },     // Opcode 1: Read\r
+    {EnumSpiOpcodeReadNoAddr,     SF_INST_RDSR,           EnumSpiCycle50MHz, EnumSpiOperationReadStatus        },     // Opcode 2: Read Status Register\r
+    {EnumSpiOpcodeRead,           SF_INST_SFDP,           EnumSpiCycle50MHz, EnumSpiOperationDiscoveryParameters},    // Opcode 3: Serial Flash Discovery Parameters\r
+    {EnumSpiOpcodeWrite,          SF_INST_SERASE,         EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte     },     // Opcode 4: Sector Erase (4KB)\r
+    {EnumSpiOpcodeWrite,          SF_INST_64KB_ERASE,     EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte    },     // Opcode 5: Block Erase (64KB\r
+    {EnumSpiOpcodeWrite,          SF_INST_PROG,           EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},     // Opcode 6: Byte Program\r
+    {EnumSpiOpcodeWriteNoAddr,    SF_INST_WRSR,           EnumSpiCycle50MHz, EnumSpiOperationWriteStatus       },     // Opcode 7: Write Status Register\r
+  },\r
+\r
+  //\r
+  // The offset of the start of the BIOS image in flash. This value is platform specific\r
+  // and depends on the system flash map. If BIOS size is bigger than flash return -1.\r
+  //\r
+  ((WINBOND_W25Q64_SIZE >= FLASH_SIZE) ? WINBOND_W25Q64_SIZE - FLASH_SIZE : (UINTN) (-1)),\r
+\r
+  //\r
+  // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.\r
+  //\r
+  FLASH_SIZE\r
+  },\r
+  {\r
+  SF_VENDOR_ID_ATMEL,       // VendorId\r
+  SF_DEVICE_ID0_AT25DF321A,  // DeviceId 0\r
+  SF_DEVICE_ID1_AT25DF321A, // DeviceId 1\r
+  {\r
+    SF_INST_WREN,           // Prefix Opcode 0: Write Enable\r
+    SF_INST_WREN            // Prefix Opcode 1: Write Enable (this part doesn't support EWSR).\r
+  },\r
+  {\r
+    {EnumSpiOpcodeReadNoAddr,     SF_INST_JEDEC_READ_ID,  EnumSpiCycle50MHz, EnumSpiOperationJedecId           },     // Opcode 0: Read ID\r
+    {EnumSpiOpcodeRead,           SF_INST_READ,           EnumSpiCycle50MHz, EnumSpiOperationReadData          },     // Opcode 1: Read\r
+    {EnumSpiOpcodeReadNoAddr,     SF_INST_RDSR,           EnumSpiCycle50MHz, EnumSpiOperationReadStatus        },     // Opcode 2: Read Status Register\r
+    {EnumSpiOpcodeWriteNoAddr,    SF_INST_WRDI,           EnumSpiCycle50MHz, EnumSpiOperationWriteDisable      },     // Opcode 3: Write Disable\r
+    {EnumSpiOpcodeWrite,          SF_INST_SERASE,         EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte     },     // Opcode 4: Sector Erase (4KB)\r
+    {EnumSpiOpcodeWrite,          SF_INST_64KB_ERASE,     EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte    },     // Opcode 5: Block Erase (32KB)\r
+    {EnumSpiOpcodeWrite,          SF_INST_PROG,           EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},     // Opcode 6: Byte Program\r
+    {EnumSpiOpcodeWriteNoAddr,    SF_INST_WRSR,           EnumSpiCycle50MHz, EnumSpiOperationWriteStatus       },     // Opcode 7: Write Status Register\r
+  },\r
+\r
+  //\r
+  // The offset of the start of the BIOS image in flash. This value is platform specific\r
+  // and depends on the system flash map. If BIOS size is bigger than flash return -1.\r
+  //\r
+  ((ATMEL_AT25DF321A_SIZE >= FLASH_SIZE) ? ATMEL_AT25DF321A_SIZE - FLASH_SIZE : (UINTN) (-1)),\r
+\r
+  //\r
+  // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.\r
+  //\r
+  FLASH_SIZE\r
+  },\r
+  {\r
+  SF_VENDOR_ID_ATMEL,       // VendorId\r
+  SF_DEVICE_ID0_AT26DF321,  // DeviceId 0\r
+  SF_DEVICE_ID1_AT26DF321,  // DeviceId 1\r
+  {\r
+    SF_INST_WREN,           // Prefix Opcode 0: Write Enable\r
+    SF_INST_WREN            // Prefix Opcode 1: Write Enable (this part doesn't support EWSR).\r
+  },\r
+  {\r
+    {EnumSpiOpcodeReadNoAddr,     SF_INST_JEDEC_READ_ID,  EnumSpiCycle50MHz, EnumSpiOperationJedecId           },     // Opcode 0: Read ID\r
+    {EnumSpiOpcodeRead,           SF_INST_READ,           EnumSpiCycle50MHz, EnumSpiOperationReadData          },     // Opcode 1: Read\r
+    {EnumSpiOpcodeReadNoAddr,     SF_INST_RDSR,           EnumSpiCycle50MHz, EnumSpiOperationReadStatus        },     // Opcode 2: Read Status Register\r
+    {EnumSpiOpcodeWriteNoAddr,    SF_INST_WRDI,           EnumSpiCycle50MHz, EnumSpiOperationWriteDisable      },     // Opcode 3: Write Disable\r
+    {EnumSpiOpcodeWrite,          SF_INST_SERASE,         EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte     },     // Opcode 4: Sector Erase (4KB)\r
+    {EnumSpiOpcodeWrite,          SF_INST_64KB_ERASE,     EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte    },     // Opcode 5: Block Erase (32KB)\r
+    {EnumSpiOpcodeWrite,          SF_INST_PROG,           EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},     // Opcode 6: Byte Program\r
+    {EnumSpiOpcodeWriteNoAddr,    SF_INST_WRSR,           EnumSpiCycle50MHz, EnumSpiOperationWriteStatus       },     // Opcode 7: Write Status Register\r
+  },\r
+\r
+  //\r
+  // The offset of the start of the BIOS image in flash. This value is platform specific\r
+  // and depends on the system flash map. If BIOS size is bigger than flash return -1.\r
+  //\r
+  ((ATMEL_AT26DF321_SIZE >= FLASH_SIZE) ? ATMEL_AT26DF321_SIZE - FLASH_SIZE : (UINTN) (-1)),\r
+\r
+  //\r
+  // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.\r
+  //\r
+  FLASH_SIZE\r
+  },\r
+  {\r
+  SF_VENDOR_ID_ATMEL,       // VendorId\r
+  SF_DEVICE_ID0_AT25DF641,  // DeviceId 0\r
+  SF_DEVICE_ID1_AT25DF641,  // DeviceId 1\r
+  {\r
+    SF_INST_WREN,           // Prefix Opcode 0: Write Enable\r
+    SF_INST_WREN            // Prefix Opcode 1: Write Enable (this part doesn't support EWSR).\r
+  },\r
+  {\r
+    {EnumSpiOpcodeReadNoAddr,     SF_INST_JEDEC_READ_ID,  EnumSpiCycle50MHz, EnumSpiOperationJedecId           },     // Opcode 0: Read ID\r
+    {EnumSpiOpcodeRead,           SF_INST_READ,           EnumSpiCycle50MHz, EnumSpiOperationReadData          },     // Opcode 1: Read\r
+    {EnumSpiOpcodeReadNoAddr,     SF_INST_RDSR,           EnumSpiCycle50MHz, EnumSpiOperationReadStatus        },     // Opcode 2: Read Status Register\r
+    {EnumSpiOpcodeWriteNoAddr,    SF_INST_WRDI,           EnumSpiCycle50MHz, EnumSpiOperationWriteDisable      },     // Opcode 3: Write Disable\r
+    {EnumSpiOpcodeWrite,          SF_INST_SERASE,         EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte     },     // Opcode 4: Sector Erase (4KB)\r
+    {EnumSpiOpcodeWrite,          SF_INST_64KB_ERASE,     EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte    },     // Opcode 5: Block Erase (32KB)\r
+    {EnumSpiOpcodeWrite,          SF_INST_PROG,           EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},     // Opcode 6: Byte Program\r
+    {EnumSpiOpcodeWriteNoAddr,    SF_INST_WRSR,           EnumSpiCycle50MHz, EnumSpiOperationWriteStatus       },     // Opcode 7: Write Status Register\r
+  },\r
+\r
+  //\r
+  // The offset of the start of the BIOS image in flash. This value is platform specific\r
+  // and depends on the system flash map. If BIOS size is bigger than flash return -1.\r
+  //\r
+  ((ATMEL_AT25DF641_SIZE >= FLASH_SIZE) ? ATMEL_AT25DF641_SIZE - FLASH_SIZE : (UINTN) (-1)),\r
+\r
+  //\r
+  // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.\r
+  //\r
+  FLASH_SIZE\r
+  },\r
+  {\r
+  SF_VENDOR_ID_WINBOND,     // VendorId\r
+  SF_DEVICE_ID0_W25QXX,     // DeviceId 0\r
+  SF_DEVICE_ID1_W25Q16,     // DeviceId 1\r
+  {\r
+    SF_INST_WREN,           // Prefix Opcode 0: Write Enable\r
+    SF_INST_EWSR            // Prefix Opcode 1: Enable Write Status Register\r
+  },\r
+  {\r
+    {EnumSpiOpcodeReadNoAddr,     SF_INST_JEDEC_READ_ID,  EnumSpiCycle50MHz, EnumSpiOperationJedecId           },     // Opcode 0: Read ID\r
+    {EnumSpiOpcodeRead,           SF_INST_READ,           EnumSpiCycle50MHz, EnumSpiOperationReadData          },     // Opcode 1: Read\r
+    {EnumSpiOpcodeReadNoAddr,     SF_INST_RDSR,           EnumSpiCycle50MHz, EnumSpiOperationReadStatus        },     // Opcode 2: Read Status Register\r
+    {EnumSpiOpcodeRead,           SF_INST_SFDP,           EnumSpiCycle50MHz, EnumSpiOperationDiscoveryParameters},    // Opcode 3: Serial Flash Discovery Parameters\r
+    {EnumSpiOpcodeWrite,          SF_INST_SERASE,         EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte     },     // Opcode 4: Sector Erase (4KB)\r
+    {EnumSpiOpcodeWrite,          SF_INST_64KB_ERASE,     EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte    },     // Opcode 5: Block Erase (64KB\r
+    {EnumSpiOpcodeWrite,          SF_INST_PROG,           EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},     // Opcode 6: Byte Program\r
+    {EnumSpiOpcodeWriteNoAddr,    SF_INST_WRSR,           EnumSpiCycle50MHz, EnumSpiOperationWriteStatus       },     // Opcode 7: Write Status Register\r
+  },\r
+\r
+  //\r
+  // The offset of the start of the BIOS image in flash. This value is platform specific\r
+  // and depends on the system flash map. If BIOS size is bigger than flash return -1.\r
+  //\r
+  ((WINBOND_W25Q16_SIZE >= FLASH_SIZE) ? WINBOND_W25Q16_SIZE - FLASH_SIZE : (UINTN) (-1)),\r
+\r
+  //\r
+  // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.\r
+  //\r
+  FLASH_SIZE\r
+  },\r
+  {\r
+  SF_VENDOR_ID_WINBOND,     // VendorId\r
+  SF_DEVICE_ID0_W25QXX,     // DeviceId 0\r
+  SF_DEVICE_ID1_W25Q32,     // DeviceId 1\r
+  {\r
+    SF_INST_WREN,           // Prefix Opcode 0: Write Enable\r
+    SF_INST_EWSR            // Prefix Opcode 1: Enable Write Status Register.\r
+  },\r
+  {\r
+    {EnumSpiOpcodeReadNoAddr,     SF_INST_JEDEC_READ_ID,  EnumSpiCycle50MHz, EnumSpiOperationJedecId           },     // Opcode 0: Read ID\r
+    {EnumSpiOpcodeRead,           SF_INST_READ,           EnumSpiCycle50MHz, EnumSpiOperationReadData          },     // Opcode 1: Read\r
+    {EnumSpiOpcodeReadNoAddr,     SF_INST_RDSR,           EnumSpiCycle50MHz, EnumSpiOperationReadStatus        },     // Opcode 2: Read Status Register\r
+    {EnumSpiOpcodeRead,           SF_INST_SFDP,           EnumSpiCycle50MHz, EnumSpiOperationDiscoveryParameters},    // Opcode 3: Serial Flash Discovery Parameters\r
+    {EnumSpiOpcodeWrite,          SF_INST_SERASE,         EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte     },     // Opcode 4: Sector Erase (4KB)\r
+    {EnumSpiOpcodeWrite,          SF_INST_64KB_ERASE,     EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte    },     // Opcode 5: Block Erase (64KB\r
+    {EnumSpiOpcodeWrite,          SF_INST_PROG,           EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},     // Opcode 6: Byte Program\r
+    {EnumSpiOpcodeWriteNoAddr,    SF_INST_WRSR,           EnumSpiCycle50MHz, EnumSpiOperationWriteStatus       },     // Opcode 7: Write Status Register\r
+  },\r
+\r
+  //\r
+  // The offset of the start of the BIOS image in flash. This value is platform specific\r
+  // and depends on the system flash map. If BIOS size is bigger than flash return -1.\r
+  //\r
+  ((WINBOND_W25Q32_SIZE >= FLASH_SIZE) ? WINBOND_W25Q32_SIZE - FLASH_SIZE : (UINTN) (-1)),\r
+\r
+  //\r
+  // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.\r
+  //\r
+  FLASH_SIZE\r
+  },\r
+  {\r
+  SF_VENDOR_ID_WINBOND,     // VendorId\r
+  SF_DEVICE_ID0_W25XXX,     // DeviceId 0\r
+  SF_DEVICE_ID1_W25X32,     // DeviceId 1\r
+  {\r
+    SF_INST_WREN,           // Prefix Opcode 0: Write Enable\r
+    SF_INST_EWSR            // Prefix Opcode 1: Enable Write Status Register\r
+  },\r
+  {\r
+    {EnumSpiOpcodeReadNoAddr,     SF_INST_JEDEC_READ_ID,  EnumSpiCycle50MHz, EnumSpiOperationJedecId           },     // Opcode 0: Read ID\r
+    {EnumSpiOpcodeRead,           SF_INST_READ,           EnumSpiCycle50MHz, EnumSpiOperationReadData          },     // Opcode 1: Read\r
+    {EnumSpiOpcodeReadNoAddr,     SF_INST_RDSR,           EnumSpiCycle50MHz, EnumSpiOperationReadStatus        },     // Opcode 2: Read Status Register\r
+    {EnumSpiOpcodeRead,           SF_INST_SFDP,           EnumSpiCycle50MHz, EnumSpiOperationDiscoveryParameters},    // Opcode 3: Serial Flash Discovery Parameters\r
+    {EnumSpiOpcodeWrite,          SF_INST_SERASE,         EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte     },     // Opcode 4: Sector Erase (4KB)\r
+    {EnumSpiOpcodeWrite,          SF_INST_64KB_ERASE,     EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte    },     // Opcode 5: Block Erase (64KB\r
+    {EnumSpiOpcodeWrite,          SF_INST_PROG,           EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},     // Opcode 6: Byte Program\r
+    {EnumSpiOpcodeWriteNoAddr,    SF_INST_WRSR,           EnumSpiCycle50MHz, EnumSpiOperationWriteStatus       },     // Opcode 7: Write Status Register\r
+  },\r
+\r
+  //\r
+  // The offset of the start of the BIOS image in flash. This value is platform specific\r
+  // and depends on the system flash map. If BIOS size is bigger than flash return -1.\r
+  //\r
+  ((WINBOND_W25X32_SIZE >= FLASH_SIZE) ? WINBOND_W25X32_SIZE - FLASH_SIZE : (UINTN) (-1)),\r
+\r
+  //\r
+  // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.\r
+  //\r
+  FLASH_SIZE\r
+  },\r
+  {\r
+  SF_VENDOR_ID_WINBOND,     // VendorId\r
+  SF_DEVICE_ID0_W25XXX,     // DeviceId 0\r
+  SF_DEVICE_ID1_W25X64,     // DeviceId 1\r
+  {\r
+    SF_INST_WREN,           // Prefix Opcode 0: Write Enable\r
+    SF_INST_EWSR            // Prefix Opcode 1: Enable Write Status Register\r
+  },\r
+  {\r
+    {EnumSpiOpcodeReadNoAddr,     SF_INST_JEDEC_READ_ID,  EnumSpiCycle50MHz, EnumSpiOperationJedecId      },     // Opcode 0: Read ID\r
+    {EnumSpiOpcodeRead,           SF_INST_READ,           EnumSpiCycle50MHz, EnumSpiOperationReadData      },     // Opcode 1: Read\r
+    {EnumSpiOpcodeReadNoAddr,     SF_INST_RDSR,           EnumSpiCycle50MHz, EnumSpiOperationReadStatus    },     // Opcode 2: Read Status Register\r
+    {EnumSpiOpcodeRead,           SF_INST_SFDP,           EnumSpiCycle50MHz, EnumSpiOperationDiscoveryParameters},    // Opcode 3: Serial Flash Discovery Parameters\r
+    {EnumSpiOpcodeWrite,          SF_INST_SERASE,         EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte  },     // Opcode 4: Sector Erase (4KB)\r
+    {EnumSpiOpcodeWrite,          SF_INST_64KB_ERASE,     EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte  },     // Opcode 5: Block Erase (64KB\r
+    {EnumSpiOpcodeWrite,          SF_INST_PROG,           EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},    // Opcode 6: Byte Program\r
+    {EnumSpiOpcodeWriteNoAddr,    SF_INST_WRSR,           EnumSpiCycle50MHz, EnumSpiOperationWriteStatus    },     // Opcode 7: Write Status Register\r
+  },\r
+\r
+  //\r
+  // The offset of the start of the BIOS image in flash. This value is platform specific\r
+  // and depends on the system flash map. If BIOS size is bigger than flash return -1.\r
+  //\r
+  ((WINBOND_W25X64_SIZE >= FLASH_SIZE) ? WINBOND_W25X64_SIZE - FLASH_SIZE : (UINTN) (-1)),\r
+\r
+  //\r
+  // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.\r
+  //\r
+  FLASH_SIZE\r
+  },\r
+  {\r
+  SF_VENDOR_ID_WINBOND,     // VendorId\r
+  SF_DEVICE_ID0_W25QXX,     // DeviceId 0\r
+  SF_DEVICE_ID1_W25Q128,    // DeviceId 1\r
+  {\r
+    SF_INST_WREN,           // Prefix Opcode 0: Write Enable\r
+    SF_INST_EWSR            // Prefix Opcode 1: Enable Write Status Register\r
+  },\r
+  {\r
+    {EnumSpiOpcodeReadNoAddr,     SF_INST_JEDEC_READ_ID,  EnumSpiCycle50MHz, EnumSpiOperationJedecId           },     // Opcode 0: Read ID\r
+    {EnumSpiOpcodeRead,           SF_INST_READ,           EnumSpiCycle50MHz, EnumSpiOperationReadData          },     // Opcode 1: Read\r
+    {EnumSpiOpcodeReadNoAddr,     SF_INST_RDSR,           EnumSpiCycle50MHz, EnumSpiOperationReadStatus        },     // Opcode 2: Read Status Register\r
+    {EnumSpiOpcodeRead,           SF_INST_SFDP,           EnumSpiCycle50MHz, EnumSpiOperationDiscoveryParameters},    // Opcode 3: Serial Flash Discovery Parameters\r
+    {EnumSpiOpcodeWrite,          SF_INST_SERASE,         EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte     },     // Opcode 4: Sector Erase (4KB)\r
+    {EnumSpiOpcodeWrite,          SF_INST_64KB_ERASE,     EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte    },     // Opcode 5: Block Erase (64KB\r
+    {EnumSpiOpcodeWrite,          SF_INST_PROG,           EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},     // Opcode 6: Byte Program\r
+    {EnumSpiOpcodeWriteNoAddr,    SF_INST_WRSR,           EnumSpiCycle50MHz, EnumSpiOperationWriteStatus       },     // Opcode 7: Write Status Register\r
+  },\r
+\r
+  //\r
+  // The offset of the start of the BIOS image in flash. This value is platform specific\r
+  // and depends on the system flash map. If BIOS size is bigger than flash return -1.\r
+  //\r
+  ((WINBOND_W25Q128_SIZE >= FLASH_SIZE) ? WINBOND_W25Q128_SIZE - FLASH_SIZE : (UINTN) (-1)),\r
+\r
+  //\r
+  // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.\r
+  //\r
+  FLASH_SIZE\r
+  },\r
+  {\r
+  SF_VENDOR_ID_MACRONIX,    // VendorId\r
+  SF_DEVICE_ID0_MX25LXX,    // DeviceId 0\r
+  SF_DEVICE_ID1_MX25L16,    // DeviceId 1\r
+  {\r
+    SF_INST_WREN,           // Prefix Opcode 0: Write Enable\r
+    SF_INST_EWSR            // Prefix Opcode 1:  Write Enable (this part doesn't support EWSR).\r
+  },\r
+  {\r
+    {EnumSpiOpcodeReadNoAddr,     SF_INST_JEDEC_READ_ID,  EnumSpiCycle50MHz, EnumSpiOperationJedecId      },      // Opcode 0: Read ID\r
+    {EnumSpiOpcodeRead,           SF_INST_READ,           EnumSpiCycle33MHz, EnumSpiOperationReadData      },      // Opcode 1: Read\r
+    {EnumSpiOpcodeReadNoAddr,     SF_INST_RDSR,           EnumSpiCycle50MHz, EnumSpiOperationReadStatus    },      // Opcode 2: Read Status Register\r
+    {EnumSpiOpcodeRead,           SF_INST_SFDP,           EnumSpiCycle50MHz, EnumSpiOperationDiscoveryParameters},    // Opcode 3: Serial Flash Discovery Parameters\r
+    {EnumSpiOpcodeWrite,          SF_INST_SERASE,         EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte  },      // Opcode 4: Sector Erase (4KB)\r
+    {EnumSpiOpcodeWrite,          SF_INST_64KB_ERASE,     EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte  },      // Opcode 5: Block Erase (64KB\r
+    {EnumSpiOpcodeWrite,          SF_INST_PROG,           EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},     // Opcode 6: Byte Program\r
+    {EnumSpiOpcodeWriteNoAddr,    SF_INST_WRSR,           EnumSpiCycle50MHz, EnumSpiOperationWriteStatus    },      // Opcode 7: Write Status Register\r
+  },\r
+\r
+  //\r
+  // The offset of the start of the BIOS image in flash. This value is platform specific\r
+  // and depends on the system flash map. If BIOS size is bigger than flash return -1.\r
+  //\r
+  ((MACRONIX_MX25L16_SIZE >= FLASH_SIZE) ? MACRONIX_MX25L16_SIZE - FLASH_SIZE : (UINTN) (-1)),\r
+\r
+  //\r
+  // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.\r
+  //\r
+  FLASH_SIZE\r
+  },\r
+  {\r
+  SF_VENDOR_ID_MACRONIX,    // VendorId\r
+  SF_DEVICE_ID0_MX25LXX,    // DeviceId 0\r
+  SF_DEVICE_ID1_MX25L32,    // DeviceId 1\r
+  {\r
+    SF_INST_WREN,           // Prefix Opcode 0: Write Enable\r
+    SF_INST_EWSR            // Prefix Opcode 1:  Write Enable (this part doesn't support EWSR).\r
+  },\r
+  {\r
+    {EnumSpiOpcodeReadNoAddr,     SF_INST_JEDEC_READ_ID,  EnumSpiCycle50MHz, EnumSpiOperationJedecId      },      // Opcode 0: Read ID\r
+    {EnumSpiOpcodeRead,           SF_INST_READ,           EnumSpiCycle33MHz, EnumSpiOperationReadData      },      // Opcode 1: Read\r
+    {EnumSpiOpcodeReadNoAddr,     SF_INST_RDSR,           EnumSpiCycle50MHz, EnumSpiOperationReadStatus    },      // Opcode 2: Read Status Register\r
+    {EnumSpiOpcodeRead,           SF_INST_SFDP,           EnumSpiCycle50MHz, EnumSpiOperationDiscoveryParameters},    // Opcode 3: Serial Flash Discovery Parameters\r
+    {EnumSpiOpcodeWrite,          SF_INST_SERASE,         EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte  },      // Opcode 4: Sector Erase (4KB)\r
+    {EnumSpiOpcodeWrite,          SF_INST_64KB_ERASE,     EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte  },      // Opcode 5: Block Erase (64KB\r
+    {EnumSpiOpcodeWrite,          SF_INST_PROG,           EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},     // Opcode 6: Byte Program\r
+    {EnumSpiOpcodeWriteNoAddr,    SF_INST_WRSR,           EnumSpiCycle50MHz, EnumSpiOperationWriteStatus    },      // Opcode 7: Write Status Register\r
+  },\r
+\r
+  //\r
+  // The offset of the start of the BIOS image in flash. This value is platform specific\r
+  // and depends on the system flash map. If BIOS size is bigger than flash return -1.\r
+  //\r
+  ((MACRONIX_MX25L32_SIZE >= FLASH_SIZE) ? MACRONIX_MX25L32_SIZE - FLASH_SIZE : (UINTN) (-1)),\r
+\r
+  //\r
+  // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.\r
+  //\r
+  FLASH_SIZE\r
+  },\r
+  {\r
+  SF_VENDOR_ID_MACRONIX,    // VendorId\r
+  SF_DEVICE_ID0_MX25LXX,    // DeviceId 0\r
+  SF_DEVICE_ID1_MX25L64,    // DeviceId 1\r
+  {\r
+    SF_INST_WREN,           // Prefix Opcode 0: Write Enable\r
+    SF_INST_EWSR            // Prefix Opcode 1:  Write Enable (this part doesn't support EWSR)\r
+  },\r
+  {\r
+    {EnumSpiOpcodeReadNoAddr,     SF_INST_JEDEC_READ_ID,  EnumSpiCycle50MHz, EnumSpiOperationJedecId      },      // Opcode 0: Read ID\r
+    {EnumSpiOpcodeRead,           SF_INST_READ,           EnumSpiCycle33MHz, EnumSpiOperationReadData      },      // Opcode 1: Read\r
+    {EnumSpiOpcodeReadNoAddr,     SF_INST_RDSR,           EnumSpiCycle50MHz, EnumSpiOperationReadStatus    },      // Opcode 2: Read Status Register\r
+    {EnumSpiOpcodeRead,           SF_INST_SFDP,           EnumSpiCycle50MHz, EnumSpiOperationDiscoveryParameters},    // Opcode 3: Serial Flash Discovery Parameters\r
+    {EnumSpiOpcodeWrite,          SF_INST_SERASE,         EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte  },      // Opcode 4: Sector Erase (4KB)\r
+    {EnumSpiOpcodeWrite,          SF_INST_64KB_ERASE,     EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte  },      // Opcode 5: Block Erase (64KB\r
+    {EnumSpiOpcodeWrite,          SF_INST_PROG,           EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},     // Opcode 6: Byte Program\r
+    {EnumSpiOpcodeWriteNoAddr,    SF_INST_WRSR,           EnumSpiCycle50MHz, EnumSpiOperationWriteStatus    },      // Opcode 7: Write Status Register\r
+  },\r
+\r
+  //\r
+  // The offset of the start of the BIOS image in flash. This value is platform specific\r
+  // and depends on the system flash map. If BIOS size is bigger than flash return -1.\r
+  //\r
+  ((MACRONIX_MX25L64_SIZE >= FLASH_SIZE) ? MACRONIX_MX25L64_SIZE - FLASH_SIZE : (UINTN) (-1)),\r
+\r
+  //\r
+  // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.\r
+  //\r
+  FLASH_SIZE\r
+  },\r
+  {\r
+  SF_VENDOR_ID_MACRONIX,    // VendorId\r
+  SF_DEVICE_ID0_MX25LXX,    // DeviceId 0\r
+  SF_DEVICE_ID1_MX25L128,   // DeviceId 1\r
+  {\r
+    SF_INST_WREN,           // Prefix Opcode 0: Write Enable\r
+    SF_INST_EWSR            // Prefix Opcode 1:  Write Enable (this part doesn't support EWSR)\r
+  },\r
+  {\r
+    {EnumSpiOpcodeReadNoAddr,     SF_INST_JEDEC_READ_ID,  EnumSpiCycle50MHz, EnumSpiOperationJedecId      },      // Opcode 0: Read ID\r
+    {EnumSpiOpcodeRead,           SF_INST_READ,           EnumSpiCycle33MHz, EnumSpiOperationReadData      },      // Opcode 1: Read\r
+    {EnumSpiOpcodeReadNoAddr,     SF_INST_RDSR,           EnumSpiCycle50MHz, EnumSpiOperationReadStatus    },      // Opcode 2: Read Status Register\r
+    {EnumSpiOpcodeRead,           SF_INST_SFDP,           EnumSpiCycle50MHz, EnumSpiOperationDiscoveryParameters},    // Opcode 3: Serial Flash Discovery Parameters\r
+    {EnumSpiOpcodeWrite,          SF_INST_SERASE,         EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte  },      // Opcode 4: Sector Erase (4KB)\r
+    {EnumSpiOpcodeWrite,          SF_INST_64KB_ERASE,     EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte  },      // Opcode 5: Block Erase (64KB\r
+    {EnumSpiOpcodeWrite,          SF_INST_PROG,           EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},     // Opcode 6: Byte Program\r
+    {EnumSpiOpcodeWriteNoAddr,    SF_INST_WRSR,           EnumSpiCycle50MHz, EnumSpiOperationWriteStatus    },      // Opcode 7: Write Status Register\r
+  },\r
+\r
+  //\r
+  // The offset of the start of the BIOS image in flash. This value is platform specific\r
+  // and depends on the system flash map. If BIOS size is bigger than flash return -1.\r
+  //\r
+  ((MACRONIX_MX25L128_SIZE >= FLASH_SIZE) ? MACRONIX_MX25L128_SIZE - FLASH_SIZE : (UINTN) (-1)),\r
+\r
+  //\r
+  // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.\r
+  //\r
+  FLASH_SIZE\r
+  },\r
+  {\r
+  SF_VENDOR_ID_MACRONIX,         // VendorId\r
+  SF_DEVICE_ID0_MX25UXX,         // DeviceId 0\r
+  SF_DEVICE_ID1_MX25U6435F,   // DeviceId 1\r
+  {\r
+    SF_INST_WREN,                    // Prefix Opcode 0: Write Enable\r
+    SF_INST_EWSR                         // Prefix Opcode 1:  Write Enable (this part doesn't support EWSR)\r
+  },\r
+  {\r
+    {EnumSpiOpcodeReadNoAddr,  SF_INST_JEDEC_READ_ID,  EnumSpiCycle50MHz, EnumSpiOperationJedecId              },              // Opcode 0: Read ID\r
+    {EnumSpiOpcodeRead,                        SF_INST_READ,                   EnumSpiCycle33MHz, EnumSpiOperationReadData      },      // Opcode 1: Read\r
+    {EnumSpiOpcodeReadNoAddr,  SF_INST_RDSR,                   EnumSpiCycle50MHz, EnumSpiOperationReadStatus    },      // Opcode 2: Read Status Register\r
+    {EnumSpiOpcodeRead,                        SF_INST_SFDP,                   EnumSpiCycle50MHz, EnumSpiOperationDiscoveryParameters},        // Opcode 3: Serial Flash Discovery Parameters\r
+    {EnumSpiOpcodeWrite,               SF_INST_SERASE,                 EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte  },      // Opcode 4: Sector Erase (4KB)\r
+    {EnumSpiOpcodeWrite,               SF_INST_64KB_ERASE,     EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte  },      // Opcode 5: Block Erase (64KB\r
+    {EnumSpiOpcodeWrite,               SF_INST_PROG,                   EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},         // Opcode 6: Byte Program\r
+    {EnumSpiOpcodeWriteNoAddr, SF_INST_WRSR,                   EnumSpiCycle50MHz, EnumSpiOperationWriteStatus    },      // Opcode 7: Write Status Register\r
+  },\r
+\r
+  //\r
+  // The offset of the start of the BIOS image in flash. This value is platform specific\r
+  // and depends on the system flash map. If BIOS size is bigger than flash return -1.\r
+  //\r
+  ((MACRONIX_MX25U64_SIZE >= FLASH_SIZE) ? MACRONIX_MX25U64_SIZE - FLASH_SIZE : (UINTN) (-1)),\r
+\r
+  //\r
+  // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.\r
+  //\r
+  FLASH_SIZE\r
+  },\r
+  {\r
+  SF_VENDOR_ID_SST,         // VendorId\r
+  SF_DEVICE_ID0_SST25VF0XXX,// DeviceId 0\r
+  SF_DEVICE_ID1_SST25VF016B,// DeviceId 1\r
+  {\r
+    SF_INST_WREN,           // Prefix Opcode 0: Write Enable\r
+    SF_INST_EWSR            // Prefix Opcode 1: Enable Write Status Register\r
+  },\r
+  {\r
+    {EnumSpiOpcodeReadNoAddr,     SF_INST_JEDEC_READ_ID,  EnumSpiCycle50MHz, EnumSpiOperationJedecId           },     // Opcode 0: Read ID\r
+    {EnumSpiOpcodeRead,           SF_INST_READ,           EnumSpiCycle20MHz, EnumSpiOperationReadData          },     // Opcode 1: Read\r
+    {EnumSpiOpcodeReadNoAddr,     SF_INST_RDSR,           EnumSpiCycle50MHz, EnumSpiOperationReadStatus        },     // Opcode 2: Read Status Register\r
+    {EnumSpiOpcodeWriteNoAddr,    SF_INST_WRDI,           EnumSpiCycle50MHz, EnumSpiOperationWriteDisable      },     // Opcode 3: Write Disable\r
+    {EnumSpiOpcodeWrite,          SF_INST_SERASE,         EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte     },     // Opcode 4: Sector Erase (4KB)\r
+    {EnumSpiOpcodeWrite,          SF_INST_64KB_ERASE,     EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte    },     // Opcode 5: Block Erase (32KB)\r
+    {EnumSpiOpcodeWrite,          SF_INST_PROG,           EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},     // Opcode 6: Byte Program\r
+    {EnumSpiOpcodeWriteNoAddr,    SF_INST_WRSR,           EnumSpiCycle50MHz, EnumSpiOperationWriteStatus       },     // Opcode 7: Write Status Register\r
+  },\r
+\r
+  //\r
+  // The offset of the start of the BIOS image in flash. This value is platform specific\r
+  // and depends on the system flash map. If BIOS size is bigger than flash return -1.\r
+  //\r
+  ((SST_SST25VF016B_SIZE >= FLASH_SIZE) ? SST_SST25VF016B_SIZE - FLASH_SIZE : (UINTN) (-1)),\r
+\r
+  //\r
+  // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.\r
+  //\r
+  FLASH_SIZE\r
+  },\r
+  {\r
+  SF_VENDOR_ID_SST,         // VendorId\r
+  SF_DEVICE_ID0_SST25VF0XXX,// DeviceId 0\r
+  SF_DEVICE_ID1_SST25VF064C,// DeviceId 1\r
+  {\r
+    SF_INST_WREN,           // Prefix Opcode 0: Write Enable\r
+    SF_INST_EWSR            // Prefix Opcode 1: Enable Write Status Register\r
+  },\r
+  {\r
+    {EnumSpiOpcodeReadNoAddr,     SF_INST_JEDEC_READ_ID,  EnumSpiCycle50MHz, EnumSpiOperationJedecId           },     // Opcode 0: Read ID\r
+    {EnumSpiOpcodeRead,           SF_INST_READ,           EnumSpiCycle20MHz, EnumSpiOperationReadData          },     // Opcode 1: Read\r
+    {EnumSpiOpcodeReadNoAddr,     SF_INST_RDSR,           EnumSpiCycle50MHz, EnumSpiOperationReadStatus        },     // Opcode 2: Read Status Register\r
+    {EnumSpiOpcodeWriteNoAddr,    SF_INST_WRDI,           EnumSpiCycle50MHz, EnumSpiOperationWriteDisable      },     // Opcode 3: Write Disable\r
+    {EnumSpiOpcodeWrite,          SF_INST_SERASE,         EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte     },     // Opcode 4: Sector Erase (4KB)\r
+    {EnumSpiOpcodeWrite,          SF_INST_64KB_ERASE,     EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte    },     // Opcode 5: Block Erase (32KB)\r
+    {EnumSpiOpcodeWrite,          SF_INST_PROG,           EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},     // Opcode 6: Byte Program\r
+    {EnumSpiOpcodeWriteNoAddr,    SF_INST_WRSR,           EnumSpiCycle50MHz, EnumSpiOperationWriteStatus       },     // Opcode 7: Write Status Register\r
+  },\r
+\r
+  //\r
+  // The offset of the start of the BIOS image in flash. This value is platform specific\r
+  // and depends on the system flash map. If BIOS size is bigger than flash return -1.\r
+  //\r
+  ((SST_SST25VF064C_SIZE >= FLASH_SIZE) ? SST_SST25VF064C_SIZE - FLASH_SIZE : (UINTN) (-1)),\r
+\r
+  //\r
+  // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.\r
+  //\r
+  FLASH_SIZE\r
+  },\r
+  {\r
+       //\r
+       // Minnow2 SPI type\r
+       //\r
+  SF_VENDOR_ID_NUMONYX,     // VendorId\r
+  SF_DEVICE_ID0_N25Q064,    // DeviceId 0\r
+  SF_DEVICE_ID1_N25Q064,    // DeviceId 1\r
+  {\r
+    SF_INST_WREN,           // Prefix Opcode 0: Write Enable\r
+    SF_INST_WREN            // Prefix Opcode 1: Write Enable (this part doesn't support EWSR)\r
+  },\r
+  {\r
+    {EnumSpiOpcodeReadNoAddr,     SF_INST_JEDEC_READ_ID,  EnumSpiCycle20MHz, EnumSpiOperationJedecId      },      // Opcode 0: Read ID\r
+    {EnumSpiOpcodeRead,           SF_INST_READ,           EnumSpiCycle20MHz, EnumSpiOperationReadData      },      // Opcode 1: Read\r
+    {EnumSpiOpcodeReadNoAddr,     SF_INST_RDSR,           EnumSpiCycle20MHz, EnumSpiOperationReadStatus    },      // Opcode 2: Read Status Register\r
+    {EnumSpiOpcodeWriteNoAddr,    SF_INST_WRDI,           EnumSpiCycle20MHz, EnumSpiOperationWriteDisable    },      // Opcode 3: Write Disable\r
+    {EnumSpiOpcodeWrite,          SF_INST_SERASE,         EnumSpiCycle20MHz, EnumSpiOperationErase_4K_Byte  },      // Opcode 4: Sector Erase (4KB)\r
+    {EnumSpiOpcodeWrite,          SF_INST_64KB_ERASE,     EnumSpiCycle20MHz, EnumSpiOperationErase_64K_Byte  },      // Opcode 5: Block Erase (64KB\r
+    {EnumSpiOpcodeWrite,          SF_INST_PROG,           EnumSpiCycle20MHz, EnumSpiOperationProgramData_1_Byte},     // Opcode 6: Byte Program\r
+    {EnumSpiOpcodeWriteNoAddr,    SF_INST_WRSR,           EnumSpiCycle20MHz, EnumSpiOperationWriteStatus    },      // Opcode 7: Write Status Register\r
+  },\r
+\r
+  //\r
+  // The offset of the start of the BIOS image in flash. This value is platform specific\r
+  // and depends on the system flash map. If BIOS size is bigger than flash return -1.\r
+  //\r
+  ((NUMONYX_N25Q064_SIZE >= FLASH_SIZE) ? NUMONYX_N25Q064_SIZE - FLASH_SIZE : (UINTN) (-1)),\r
+\r
+  //\r
+  // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.\r
+  //\r
+  FLASH_SIZE\r
+  },\r
+  {\r
+  SF_VENDOR_ID_NUMONYX,     // VendorId\r
+  SF_DEVICE_ID0_M25PXXX,    // DeviceId 0\r
+  SF_DEVICE_ID1_M25PX16,    // DeviceId 1\r
+  {\r
+    SF_INST_WREN,           // Prefix Opcode 0: Write Enable\r
+    SF_INST_WREN            // Prefix Opcode 1: Write Enable (this part doesn't support EWSR).\r
+  },\r
+  {\r
+    {EnumSpiOpcodeReadNoAddr,     SF_INST_JEDEC_READ_ID,  EnumSpiCycle50MHz, EnumSpiOperationJedecId      },      // Opcode 0: Read ID\r
+    {EnumSpiOpcodeRead,           SF_INST_READ,           EnumSpiCycle33MHz, EnumSpiOperationReadData      },      // Opcode 1: Read\r
+    {EnumSpiOpcodeReadNoAddr,     SF_INST_RDSR,           EnumSpiCycle50MHz, EnumSpiOperationReadStatus    },      // Opcode 2: Read Status Register\r
+    {EnumSpiOpcodeWriteNoAddr,    SF_INST_WRDI,           EnumSpiCycle50MHz, EnumSpiOperationWriteDisable    },      // Opcode 3: Write Disable\r
+    {EnumSpiOpcodeWrite,          SF_INST_SERASE,         EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte  },      // Opcode 4: Sector Erase (4KB)\r
+    {EnumSpiOpcodeWrite,          SF_INST_64KB_ERASE,     EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte  },      // Opcode 5: Block Erase (64KB\r
+    {EnumSpiOpcodeWrite,          SF_INST_PROG,           EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},     // Opcode 6: Byte Program\r
+    {EnumSpiOpcodeWriteNoAddr,    SF_INST_WRSR,           EnumSpiCycle50MHz, EnumSpiOperationWriteStatus    },      // Opcode 7: Write Status Register\r
+  },\r
+\r
+  //\r
+  // The offset of the start of the BIOS image in flash. This value is platform specific\r
+  // and depends on the system flash map. If BIOS size is bigger than flash return -1.\r
+  //\r
+  ((NUMONYX_M25PX16_SIZE >= FLASH_SIZE) ? NUMONYX_M25PX16_SIZE - FLASH_SIZE : (UINTN) (-1)),\r
+\r
+  //\r
+  // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.\r
+  //\r
+  FLASH_SIZE\r
+  },\r
+  {\r
+  SF_VENDOR_ID_NUMONYX,     // VendorId\r
+  SF_DEVICE_ID0_N25QXXX,    // DeviceId 0\r
+  SF_DEVICE_ID1_N25Q032,    // DeviceId 1\r
+  {\r
+    SF_INST_WREN,           // Prefix Opcode 0: Write Enable\r
+    SF_INST_WREN            // Prefix Opcode 1: Write Enable (this part doesn't support EWSR).\r
+  },\r
+  {\r
+    {EnumSpiOpcodeReadNoAddr,     SF_INST_JEDEC_READ_ID,  EnumSpiCycle50MHz, EnumSpiOperationJedecId      },        // Opcode 0: Read ID\r
+    {EnumSpiOpcodeRead,           SF_INST_READ,           EnumSpiCycle33MHz, EnumSpiOperationReadData      },        // Opcode 1: Read\r
+    {EnumSpiOpcodeReadNoAddr,     SF_INST_RDSR,           EnumSpiCycle50MHz, EnumSpiOperationReadStatus    },        // Opcode 2: Read Status Register\r
+    {EnumSpiOpcodeWriteNoAddr,    SF_INST_WRDI,           EnumSpiCycle50MHz, EnumSpiOperationWriteDisable    },      // Opcode 3: Write Disable\r
+    {EnumSpiOpcodeWrite,          SF_INST_SERASE,         EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte  },      // Opcode 4: Sector Erase (4KB)\r
+    {EnumSpiOpcodeWrite,          SF_INST_64KB_ERASE,     EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte  },      // Opcode 5: Block Erase (64KB\r
+    {EnumSpiOpcodeWrite,          SF_INST_PROG,           EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},   // Opcode 6: Byte Program\r
+    {EnumSpiOpcodeWriteNoAddr,    SF_INST_WRSR,           EnumSpiCycle50MHz, EnumSpiOperationWriteStatus    },      // Opcode 7: Write Status Register\r
+  },\r
+\r
+  //\r
+  // The offset of the start of the BIOS image in flash. This value is platform specific\r
+  // and depends on the system flash map. If BIOS size is bigger than flash return -1.\r
+  //\r
+  ((NUMONYX_N25Q032_SIZE >= FLASH_SIZE) ? NUMONYX_N25Q032_SIZE - FLASH_SIZE : (UINTN) (-1)),\r
+\r
+  //\r
+  // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.\r
+  //\r
+  FLASH_SIZE\r
+  },\r
+  {\r
+  SF_VENDOR_ID_NUMONYX,     // VendorId\r
+  SF_DEVICE_ID0_M25PXXX,    // DeviceId 0\r
+  SF_DEVICE_ID1_M25PX32,    // DeviceId 1\r
+  {\r
+    SF_INST_WREN,           // Prefix Opcode 0: Write Enable\r
+    SF_INST_WREN            // Prefix Opcode 1: Write Enable (this part doesn't support EWSR).\r
+  },\r
+  {\r
+    {EnumSpiOpcodeReadNoAddr,     SF_INST_JEDEC_READ_ID,  EnumSpiCycle50MHz, EnumSpiOperationJedecId      },      // Opcode 0: Read ID\r
+    {EnumSpiOpcodeRead,           SF_INST_READ,           EnumSpiCycle33MHz, EnumSpiOperationReadData      },      // Opcode 1: Read\r
+    {EnumSpiOpcodeReadNoAddr,     SF_INST_RDSR,           EnumSpiCycle50MHz, EnumSpiOperationReadStatus    },      // Opcode 2: Read Status Register\r
+    {EnumSpiOpcodeWriteNoAddr,    SF_INST_WRDI,           EnumSpiCycle50MHz, EnumSpiOperationWriteDisable    },      // Opcode 3: Write Disable\r
+    {EnumSpiOpcodeWrite,          SF_INST_SERASE,         EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte  },      // Opcode 4: Sector Erase (4KB)\r
+    {EnumSpiOpcodeWrite,          SF_INST_64KB_ERASE,     EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte  },      // Opcode 5: Block Erase (64KB\r
+    {EnumSpiOpcodeWrite,          SF_INST_PROG,           EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},     // Opcode 6: Byte Program\r
+    {EnumSpiOpcodeWriteNoAddr,    SF_INST_WRSR,           EnumSpiCycle50MHz, EnumSpiOperationWriteStatus    },      // Opcode 7: Write Status Register\r
+  },\r
+\r
+  //\r
+  // The offset of the start of the BIOS image in flash. This value is platform specific\r
+  // and depends on the system flash map. If BIOS size is bigger than flash return -1.\r
+  //\r
+  ((NUMONYX_M25PX32_SIZE >= FLASH_SIZE) ? NUMONYX_M25PX32_SIZE - FLASH_SIZE : (UINTN) (-1)),\r
+\r
+  //\r
+  // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.\r
+  //\r
+  FLASH_SIZE\r
+  },\r
+  {\r
+  SF_VENDOR_ID_NUMONYX,     // VendorId\r
+  SF_DEVICE_ID0_M25PXXX,    // DeviceId 0\r
+  SF_DEVICE_ID1_M25PX64,    // DeviceId 1\r
+  {\r
+    SF_INST_WREN,           // Prefix Opcode 0: Write Enable\r
+    SF_INST_WREN            // Prefix Opcode 1: Write Enable (this part doesn't support EWSR)\r
+  },\r
+  {\r
+    {EnumSpiOpcodeReadNoAddr,     SF_INST_JEDEC_READ_ID,  EnumSpiCycle50MHz, EnumSpiOperationJedecId      },      // Opcode 0: Read ID\r
+    {EnumSpiOpcodeRead,           SF_INST_READ,           EnumSpiCycle33MHz, EnumSpiOperationReadData      },      // Opcode 1: Read\r
+    {EnumSpiOpcodeReadNoAddr,     SF_INST_RDSR,           EnumSpiCycle50MHz, EnumSpiOperationReadStatus    },      // Opcode 2: Read Status Register\r
+    {EnumSpiOpcodeWriteNoAddr,    SF_INST_WRDI,           EnumSpiCycle50MHz, EnumSpiOperationWriteDisable    },      // Opcode 3: Write Disable\r
+    {EnumSpiOpcodeWrite,          SF_INST_SERASE,         EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte  },      // Opcode 4: Sector Erase (4KB)\r
+    {EnumSpiOpcodeWrite,          SF_INST_64KB_ERASE,     EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte  },      // Opcode 5: Block Erase (64KB\r
+    {EnumSpiOpcodeWrite,          SF_INST_PROG,           EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},     // Opcode 6: Byte Program\r
+    {EnumSpiOpcodeWriteNoAddr,    SF_INST_WRSR,           EnumSpiCycle50MHz, EnumSpiOperationWriteStatus    },      // Opcode 7: Write Status Register\r
+  },\r
+\r
+  //\r
+  // The offset of the start of the BIOS image in flash. This value is platform specific\r
+  // and depends on the system flash map. If BIOS size is bigger than flash return -1.\r
+  //\r
+  ((NUMONYX_M25PX64_SIZE >= FLASH_SIZE) ? NUMONYX_M25PX64_SIZE - FLASH_SIZE : (UINTN) (-1)),\r
+\r
+  //\r
+  // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.\r
+  //\r
+  FLASH_SIZE\r
+  },\r
+  {\r
+  SF_VENDOR_ID_NUMONYX,     // VendorId\r
+  SF_DEVICE_ID0_N25QXXX,    // DeviceId 0\r
+  SF_DEVICE_ID1_N25Q128,    // DeviceId 1\r
+  {\r
+    SF_INST_WREN,           // Prefix Opcode 0: Write Enable\r
+    SF_INST_WREN            // Prefix Opcode 1: Write Enable (this part doesn't support EWSR)\r
+  },\r
+  {\r
+    {EnumSpiOpcodeReadNoAddr,     SF_INST_JEDEC_READ_ID,  EnumSpiCycle50MHz, EnumSpiOperationJedecId      },      // Opcode 0: Read ID\r
+    {EnumSpiOpcodeRead,           SF_INST_READ,           EnumSpiCycle33MHz, EnumSpiOperationReadData      },      // Opcode 1: Read\r
+    {EnumSpiOpcodeReadNoAddr,     SF_INST_RDSR,           EnumSpiCycle50MHz, EnumSpiOperationReadStatus    },      // Opcode 2: Read Status Register\r
+    {EnumSpiOpcodeWriteNoAddr,    SF_INST_WRDI,           EnumSpiCycle50MHz, EnumSpiOperationWriteDisable    },      // Opcode 3: Write Disable\r
+    {EnumSpiOpcodeWrite,          SF_INST_SERASE,         EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte  },      // Opcode 4: Sector Erase (4KB)\r
+    {EnumSpiOpcodeWrite,          SF_INST_64KB_ERASE,     EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte  },      // Opcode 5: Block Erase (64KB\r
+    {EnumSpiOpcodeWrite,          SF_INST_PROG,           EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},     // Opcode 6: Byte Program\r
+    {EnumSpiOpcodeWriteNoAddr,    SF_INST_WRSR,           EnumSpiCycle50MHz, EnumSpiOperationWriteStatus    },      // Opcode 7: Write Status Register\r
+  },\r
+\r
+  //\r
+  // The offset of the start of the BIOS image in flash. This value is platform specific\r
+  // and depends on the system flash map. If BIOS size is bigger than flash return -1.\r
+  //\r
+  ((NUMONYX_N25Q128_SIZE >= FLASH_SIZE) ? NUMONYX_N25Q128_SIZE - FLASH_SIZE : (UINTN) (-1)),\r
+\r
+  //\r
+  // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.\r
+  //\r
+  FLASH_SIZE\r
+  },\r
+  {\r
+  SF_VENDOR_ID_EON,         // VendorId\r
+  SF_DEVICE_ID0_EN25QXX,    // DeviceId 0\r
+  SF_DEVICE_ID1_EN25Q16,    // DeviceId 1\r
+  {\r
+    SF_INST_WREN,           // Prefix Opcode 0: Write Enable\r
+    SF_INST_WREN            // Prefix Opcode 1: Write Enable (this part doesn't support EWSR)\r
+  },\r
+  {\r
+    {EnumSpiOpcodeReadNoAddr,     SF_INST_JEDEC_READ_ID,  EnumSpiCycle50MHz, EnumSpiOperationJedecId      },      // Opcode 0: Read ID\r
+    {EnumSpiOpcodeRead,           SF_INST_READ,           EnumSpiCycle50MHz, EnumSpiOperationReadData      },      // Opcode 1: Read\r
+    {EnumSpiOpcodeReadNoAddr,     SF_INST_RDSR,           EnumSpiCycle50MHz, EnumSpiOperationReadStatus    },      // Opcode 2: Read Status Register\r
+    {EnumSpiOpcodeWriteNoAddr,    SF_INST_WRDI,           EnumSpiCycle50MHz, EnumSpiOperationWriteDisable    },      // Opcode 3: Write Disable\r
+    {EnumSpiOpcodeWrite,          SF_INST_SERASE,         EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte  },      // Opcode 4: Sector Erase (4KB)\r
+    {EnumSpiOpcodeWrite,          SF_INST_64KB_ERASE,     EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte  },      // Opcode 5: Block Erase (64KB\r
+    {EnumSpiOpcodeWrite,          SF_INST_PROG,           EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},     // Opcode 6: Byte Program\r
+    {EnumSpiOpcodeWriteNoAddr,    SF_INST_WRSR,           EnumSpiCycle50MHz, EnumSpiOperationWriteStatus    },      // Opcode 7: Write Status Register\r
+  },\r
+\r
+  //\r
+  // The offset of the start of the BIOS image in flash. This value is platform specific\r
+  // and depends on the system flash map. If BIOS size is bigger than flash return -1.\r
+  //\r
+  ((EON_EN25Q16_SIZE >= FLASH_SIZE) ? EON_EN25Q16_SIZE - FLASH_SIZE : (UINTN) (-1)),\r
+\r
+  //\r
+  // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.\r
+  //\r
+  FLASH_SIZE\r
+  },\r
+  {\r
+  SF_VENDOR_ID_EON,         // VendorId\r
+  SF_DEVICE_ID0_EN25QXX,    // DeviceId 0\r
+  SF_DEVICE_ID1_EN25Q32,    // DeviceId 1\r
+  {\r
+    SF_INST_WREN,           // Prefix Opcode 0: Write Enable\r
+    SF_INST_WREN            // Prefix Opcode 1: Write Enable (this part doesn't support EWSR)\r
+  },\r
+  {\r
+    {EnumSpiOpcodeReadNoAddr,     SF_INST_JEDEC_READ_ID,  EnumSpiCycle50MHz, EnumSpiOperationJedecId      },      // Opcode 0: Read ID\r
+    {EnumSpiOpcodeRead,           SF_INST_READ,           EnumSpiCycle33MHz, EnumSpiOperationReadData      },      // Opcode 1: Read\r
+    {EnumSpiOpcodeReadNoAddr,     SF_INST_RDSR,           EnumSpiCycle50MHz, EnumSpiOperationReadStatus    },      // Opcode 2: Read Status Register\r
+    {EnumSpiOpcodeWriteNoAddr,    SF_INST_WRDI,           EnumSpiCycle50MHz, EnumSpiOperationWriteDisable    },      // Opcode 3: Write Disable\r
+    {EnumSpiOpcodeWrite,          SF_INST_SERASE,         EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte  },      // Opcode 4: Sector Erase (4KB)\r
+    {EnumSpiOpcodeWrite,          SF_INST_64KB_ERASE,     EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte  },      // Opcode 5: Block Erase (64KB\r
+    {EnumSpiOpcodeWrite,          SF_INST_PROG,           EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},     // Opcode 6: Byte Program\r
+    {EnumSpiOpcodeWriteNoAddr,    SF_INST_WRSR,           EnumSpiCycle50MHz, EnumSpiOperationWriteStatus    },      // Opcode 7: Write Status Register\r
+  },\r
+\r
+  //\r
+  // The offset of the start of the BIOS image in flash. This value is platform specific\r
+  // and depends on the system flash map. If BIOS size is bigger than flash return -1.\r
+  //\r
+  ((EON_EN25Q32_SIZE >= FLASH_SIZE) ? EON_EN25Q32_SIZE - FLASH_SIZE : (UINTN) (-1)),\r
+\r
+  //\r
+  // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.\r
+  //\r
+  FLASH_SIZE\r
+  },\r
+  {\r
+  SF_VENDOR_ID_EON,         // VendorId\r
+  SF_DEVICE_ID0_EN25QXX,    // DeviceId 0\r
+  SF_DEVICE_ID1_EN25Q64,    // DeviceId 1\r
+  {\r
+    SF_INST_WREN,           // Prefix Opcode 0: Write Enable\r
+    SF_INST_WREN            // Prefix Opcode 1: Write Enable (this part doesn't support EWSR).\r
+  },\r
+  {\r
+    {EnumSpiOpcodeReadNoAddr,     SF_INST_JEDEC_READ_ID,  EnumSpiCycle50MHz, EnumSpiOperationJedecId      },      // Opcode 0: Read ID\r
+    {EnumSpiOpcodeRead,           SF_INST_READ,           EnumSpiCycle50MHz, EnumSpiOperationReadData      },      // Opcode 1: Read\r
+    {EnumSpiOpcodeReadNoAddr,     SF_INST_RDSR,           EnumSpiCycle50MHz, EnumSpiOperationReadStatus    },      // Opcode 2: Read Status Register\r
+    {EnumSpiOpcodeWriteNoAddr,    SF_INST_WRDI,           EnumSpiCycle50MHz, EnumSpiOperationWriteDisable    },      // Opcode 3: Write Disable\r
+    {EnumSpiOpcodeWrite,          SF_INST_SERASE,         EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte  },      // Opcode 4: Sector Erase (4KB)\r
+    {EnumSpiOpcodeWrite,          SF_INST_64KB_ERASE,     EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte  },      // Opcode 5: Block Erase (64KB\r
+    {EnumSpiOpcodeWrite,          SF_INST_PROG,           EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},     // Opcode 6: Byte Program\r
+    {EnumSpiOpcodeWriteNoAddr,    SF_INST_WRSR,           EnumSpiCycle50MHz, EnumSpiOperationWriteStatus    },      // Opcode 7: Write Status Register\r
+  },\r
+\r
+  //\r
+  // The offset of the start of the BIOS image in flash. This value is platform specific\r
+  // and depends on the system flash map. If BIOS size is bigger than flash return -1.\r
+  //\r
+  ((EON_EN25Q64_SIZE >= FLASH_SIZE) ? EON_EN25Q64_SIZE - FLASH_SIZE : (UINTN) (-1)),\r
+\r
+  //\r
+  // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.\r
+  //\r
+  FLASH_SIZE\r
+  },\r
+  {\r
+  SF_VENDOR_ID_EON,         // VendorId\r
+  SF_DEVICE_ID0_EN25QXX,    // DeviceId 0\r
+  SF_DEVICE_ID1_EN25Q128,   // DeviceId 1\r
+  {\r
+    SF_INST_WREN,           // Prefix Opcode 0: Write Enable\r
+    SF_INST_WREN            // Prefix Opcode 1: Write Enable (this part doesn't support EWSR)\r
+  },\r
+  {\r
+    {EnumSpiOpcodeReadNoAddr,     SF_INST_JEDEC_READ_ID,  EnumSpiCycle50MHz, EnumSpiOperationJedecId      },      // Opcode 0: Read ID\r
+    {EnumSpiOpcodeRead,           SF_INST_READ,           EnumSpiCycle50MHz, EnumSpiOperationReadData      },      // Opcode 1: Read\r
+    {EnumSpiOpcodeReadNoAddr,     SF_INST_RDSR,           EnumSpiCycle50MHz, EnumSpiOperationReadStatus    },      // Opcode 2: Read Status Register\r
+    {EnumSpiOpcodeWriteNoAddr,    SF_INST_WRDI,           EnumSpiCycle50MHz, EnumSpiOperationWriteDisable    },      // Opcode 3: Write Disable\r
+    {EnumSpiOpcodeWrite,          SF_INST_SERASE,         EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte  },      // Opcode 4: Sector Erase (4KB)\r
+    {EnumSpiOpcodeWrite,          SF_INST_64KB_ERASE,     EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte  },      // Opcode 5: Block Erase (64KB\r
+    {EnumSpiOpcodeWrite,          SF_INST_PROG,           EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},     // Opcode 6: Byte Program\r
+    {EnumSpiOpcodeWriteNoAddr,    SF_INST_WRSR,           EnumSpiCycle50MHz, EnumSpiOperationWriteStatus    },      // Opcode 7: Write Status Register\r
+  },\r
+\r
+  //\r
+  // The offset of the start of the BIOS image in flash. This value is platform specific\r
+  // and depends on the system flash map. If BIOS size is bigger than flash return -1.\r
+  //\r
+  ((EON_EN25Q128_SIZE >= FLASH_SIZE) ? EON_EN25Q128_SIZE - FLASH_SIZE : (UINTN) (-1)),\r
+\r
+  //\r
+  // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.\r
+  //\r
+  FLASH_SIZE\r
+  },\r
+  {\r
+  SF_VENDOR_ID_AMIC,        // VendorId\r
+  SF_DEVICE_ID0_A25L016,    // DeviceId 0\r
+  SF_DEVICE_ID1_A25L016,    // DeviceId 1\r
+  {\r
+    SF_INST_WREN,           // Prefix Opcode 0: Write Enable\r
+    SF_INST_WREN            // Prefix Opcode 1: Write Enable (this part doesn't support EWSR)\r
+  },\r
+  {\r
+    {EnumSpiOpcodeReadNoAddr,     SF_INST_JEDEC_READ_ID,  EnumSpiCycle50MHz, EnumSpiOperationJedecId      },      // Opcode 0: Read ID\r
+    {EnumSpiOpcodeRead,           SF_INST_READ,           EnumSpiCycle50MHz, EnumSpiOperationReadData      },      // Opcode 1: Read\r
+    {EnumSpiOpcodeReadNoAddr,     SF_INST_RDSR,           EnumSpiCycle50MHz, EnumSpiOperationReadStatus    },      // Opcode 2: Read Status Register\r
+    {EnumSpiOpcodeWriteNoAddr,    SF_INST_WRDI,           EnumSpiCycle50MHz, EnumSpiOperationWriteDisable    },      // Opcode 3: Write Disable\r
+    {EnumSpiOpcodeWrite,          SF_INST_SERASE,         EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte  },      // Opcode 4: Sector Erase (4KB)\r
+    {EnumSpiOpcodeWrite,          SF_INST_64KB_ERASE,     EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte  },      // Opcode 5: Block Erase (64KB\r
+    {EnumSpiOpcodeWrite,          SF_INST_PROG,           EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},     // Opcode 6: Byte Program\r
+    {EnumSpiOpcodeWriteNoAddr,    SF_INST_WRSR,           EnumSpiCycle50MHz, EnumSpiOperationWriteStatus    },      // Opcode 7: Write Status Register\r
+  },\r
+\r
+  //\r
+  // The offset of the start of the BIOS image in flash. This value is platform specific\r
+  // and depends on the system flash map. If BIOS size is bigger than flash return -1.\r
+  //\r
+  ((AMIC_A25L16_SIZE >= FLASH_SIZE) ? AMIC_A25L16_SIZE - FLASH_SIZE : (UINTN) (-1)),\r
+\r
+  //\r
+  // The size of the BIOS image in flash. This value is platform specific and depends on the system flash map.\r
+  //\r
+  FLASH_SIZE\r
+  }\r
+};\r

diff --git a/Vlv2TbltDevicePkg/Library/I2CLib/I2CLib.c b/Vlv2TbltDevicePkg/Library/I2CLib/I2CLib.c
new file mode 100644 (file)
index 0000000..3e65381
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Library/I2CLib/I2CLib.c
@@ -0,0 +1,51 @@
+/*++\r
+\r
+Copyright (c)  1999  - 2014, Intel Corporation. All rights reserved\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+\r
+Module Name:\r
+\r
+  I2CLib.c\r
+\r
+\r
+\r
+--*/\r
+#ifdef ECP_FLAG\r
+#include "EdkIIGlueDxe.h"\r
+#else\r
+#include <Library/DebugLib.h>\r
+#include <Library/TimerLib.h>\r
+#endif\r
+#include <PchRegs/PchRegsPcu.h>\r
+#include <PchRegs.h>\r
+#include <PlatformBaseAddresses.h>\r
+#include <PchRegs/PchRegsLpss.h>\r
+#ifdef ECP_FLAG\r
+#include "I2CLib.h"\r
+#else\r
+#include <Library/I2CLib.h>\r
+#endif\r
+#include <Protocol/GlobalNvsArea.h>\r
+#ifndef ECP_FLAG\r
+#include <Library/UefiBootServicesTableLib.h>\r
+#endif\r
+\r
+EFI_STATUS ByteReadI2C(\r
+  IN  UINT8 BusNo,\r
+  IN  UINT8 SlaveAddress,\r
+  IN  UINT8 Offset,\r
+  IN  UINTN ReadBytes,\r
+  OUT UINT8 *ReadBuffer\r
+  )\r
+{\r
+  return EFI_SUCCESS;\r
+}\r

diff --git a/Vlv2TbltDevicePkg/Library/I2CLib/I2CLibNull.inf b/Vlv2TbltDevicePkg/Library/I2CLib/I2CLibNull.inf
new file mode 100644 (file)
index 0000000..487982c
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Library/I2CLib/I2CLibNull.inf
@@ -0,0 +1,53 @@
+## @file\r
+# Null instance of Debug Agent Library with empty functions.\r
+#\r
+#  Copyright (c) 2010 - 2014, Intel Corporation. All rights reserved.<BR>\r
+#                                                                                  \r\r
+# This program and the accompanying materials are licensed and made available under\r\r
+# the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+# The full text of the license may be found at                                     \r\r
+# http://opensource.org/licenses/bsd-license.php.                                  \r\r
+#                                                                                  \r\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+#                                                                                  \r\r
+#\r
+#  This program and the accompanying materials\r
+#  are licensed and made available under the terms and conditions of the BSD License\r
+#  which accompanies this distribution. The full text of the license may be found at\r
+#  http://opensource.org/licenses/bsd-license.php\r
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+#\r
+\r
+[Defines]\r
+  INF_VERSION                    = 0x00010005\r
+  BASE_NAME                      = I2CLib\r
+  FILE_GUID                      = 7f62bf44-2ba7-4c2d-9d4a-91c8906ff053\r
+  MODULE_TYPE                    = BASE\r
+  VERSION_STRING                 = 1.0\r
+  LIBRARY_CLASS                  = I2CLib\r
+\r
+#\r
+# The following information is for reference only and not required by the build tools.\r
+#\r
+#  VALID_ARCHITECTURES           = IA32 X64 IPF EBC\r
+#\r
+\r
+[Sources.common]\r
+  I2CLib.c\r
+\r
+[LibraryClasses]\r
+  BaseLib\r
+  IoLib\r
+  TimerLib\r
+\r
+[Packages]\r
+  MdePkg/MdePkg.dec\r
+  MdeModulePkg/MdeModulePkg.dec\r
+  Vlv2TbltDevicePkg/PlatformPkg.dec\r
+  Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec\r
+\r
+[Protocols]\r
+  gEfiGlobalNvsAreaProtocolGuid\r

diff --git a/Vlv2TbltDevicePkg/Library/IntelPchAcpiTimerLib/CommonHeader.h b/Vlv2TbltDevicePkg/Library/IntelPchAcpiTimerLib/CommonHeader.h
new file mode 100644 (file)
index 0000000..213940e
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Library/IntelPchAcpiTimerLib/CommonHeader.h
@@ -0,0 +1,32 @@
+/**@file\r
+  Common header file shared by all source files.\r
+\r
+  This file includes package header files, library classes and protocol, PPI & GUID definitions.\r
+\r
+  Copyright (c) 2007 - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+**/\r
+\r
+#ifndef __COMMON_HEADER_H_\r
+#define __COMMON_HEADER_H_\r
+\r
+\r
+#include <Base.h>\r
+#include <PchAccess.h>\r
+\r
+#include <Library/TimerLib.h>\r
+#include <Library/BaseLib.h>\r
+#include <Library/IoLib.h>\r
+#include <Library/PciLib.h>\r
+#include <Library/PcdLib.h>\r
+\r
+#endif\r

diff --git a/Vlv2TbltDevicePkg/Library/IntelPchAcpiTimerLib/IntelPchAcpiTimerLib.c b/Vlv2TbltDevicePkg/Library/IntelPchAcpiTimerLib/IntelPchAcpiTimerLib.c
new file mode 100644 (file)
index 0000000..09c42a4
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Library/IntelPchAcpiTimerLib/IntelPchAcpiTimerLib.c
@@ -0,0 +1,260 @@
+/** @file\r
+  ICH9 ACPI Timer implements one instance of Timer Library.\r
+\r
+Copyright (c) 2007 - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+**/\r
+\r
+#include "CommonHeader.h"\r
+\r
+/**\r
+  The constructor function enables ACPI IO space.\r
+\r
+  If ACPI I/O space not enabled, this function will enable it.\r
+  It will always return RETURN_SUCCESS.\r
+\r
+  @retval EFI_SUCCESS   The constructor always returns RETURN_SUCCESS.\r
+\r
+**/\r
+RETURN_STATUS\r
+EFIAPI\r
+IntelPchAcpiTimerLibConstructor (\r
+  VOID\r
+  )\r
+{\r
+  if ((PchLpcPciCfg8(R_PCH_LPC_ACPI_BASE) & B_PCH_LPC_ACPI_BASE_EN) == 0) {\r
+  //\r
+  // If ACPI I/O space is not enabled, program ACPI I/O base address and enable it.\r
+  //\r
+    MmioWrite16 (\r
+      MmPciAddress (\r
+        0,\r
+        DEFAULT_PCI_BUS_NUMBER_PCH,\r
+        PCI_DEVICE_NUMBER_PCH_LPC,\r
+        PCI_FUNCTION_NUMBER_PCH_LPC,\r
+        R_PCH_LPC_ACPI_BASE\r
+        ),\r
+      ((PcdGet16 (PcdPchAcpiIoPortBaseAddress) & B_PCH_LPC_ACPI_BASE_BAR) | B_PCH_LPC_ACPI_BASE_EN)\r
+    );\r
+  }\r
+  return RETURN_SUCCESS;\r
+}\r
+\r
+/**\r
+  Internal function to read the current tick counter of ACPI.\r
+\r
+  Internal function to read the current tick counter of ACPI.\r
+\r
+  @return The tick counter read.\r
+\r
+**/\r
+STATIC\r
+UINT32\r
+InternalAcpiGetTimerTick (\r
+  VOID\r
+  )\r
+{\r
+  return IoRead32 (PcdGet16 (PcdPchAcpiIoPortBaseAddress) + R_PCH_ACPI_PM1_TMR);\r
+}\r
+\r
+/**\r
+  Stalls the CPU for at least the given number of ticks.\r
+\r
+  Stalls the CPU for at least the given number of ticks. It's invoked by\r
+  MicroSecondDelay() and NanoSecondDelay().\r
+\r
+  @param  Delay     A period of time to delay in ticks.\r
+\r
+**/\r
+STATIC\r
+VOID\r
+InternalAcpiDelay (\r
+  IN      UINT32                    Delay\r
+  )\r
+{\r
+  UINT32                            Ticks;\r
+  UINT32                            Times;\r
+\r
+  Times    = Delay >> 22;\r
+  Delay   &= BIT22 - 1;\r
+  do {\r
+    //\r
+    // The target timer count is calculated here\r
+    //\r
+    Ticks    = InternalAcpiGetTimerTick () + Delay;\r
+    Delay    = BIT22;\r
+    //\r
+    // Wait until time out\r
+    // Delay >= 2^23 could not be handled by this function\r
+    // Timer wrap-arounds are handled correctly by this function\r
+    //\r
+    while (((Ticks - InternalAcpiGetTimerTick ()) & BIT23) == 0) {\r
+      CpuPause ();\r
+    }\r
+  } while (Times-- > 0);\r
+}\r
+\r
+/**\r
+  Stalls the CPU for at least the given number of microseconds.\r
+\r
+  Stalls the CPU for the number of microseconds specified by MicroSeconds.\r
+\r
+  @param  MicroSeconds  The minimum number of microseconds to delay.\r
+\r
+  @return MicroSeconds\r
+\r
+**/\r
+UINTN\r
+EFIAPI\r
+MicroSecondDelay (\r
+  IN      UINTN                     MicroSeconds\r
+  )\r
+{\r
+  InternalAcpiDelay (\r
+    (UINT32)DivU64x32 (\r
+              MultU64x32 (\r
+                MicroSeconds,\r
+                V_PCH_ACPI_PM1_TMR_FREQUENCY\r
+                ),\r
+              1000000u\r
+              )\r
+    );\r
+  return MicroSeconds;\r
+}\r
+\r
+/**\r
+  Stalls the CPU for at least the given number of nanoseconds.\r
+\r
+  Stalls the CPU for the number of nanoseconds specified by NanoSeconds.\r
+\r
+  @param  NanoSeconds The minimum number of nanoseconds to delay.\r
+\r
+  @return NanoSeconds\r
+\r
+**/\r
+UINTN\r
+EFIAPI\r
+NanoSecondDelay (\r
+  IN      UINTN                     NanoSeconds\r
+  )\r
+{\r
+  InternalAcpiDelay (\r
+    (UINT32)DivU64x32 (\r
+              MultU64x32 (\r
+                NanoSeconds,\r
+                V_PCH_ACPI_PM1_TMR_FREQUENCY\r
+                ),\r
+              1000000000u\r
+              )\r
+    );\r
+  return NanoSeconds;\r
+}\r
+\r
+/**\r
+  Retrieves the current value of a 64-bit free running performance counter.\r
+\r
+  Retrieves the current value of a 64-bit free running performance counter. The\r
+  counter can either count up by 1 or count down by 1. If the physical\r
+  performance counter counts by a larger increment, then the counter values\r
+  must be translated. The properties of the counter can be retrieved from\r
+  GetPerformanceCounterProperties().\r
+\r
+  @return The current value of the free running performance counter.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+GetPerformanceCounter (\r
+  VOID\r
+  )\r
+{\r
+  return (UINT64)InternalAcpiGetTimerTick ();\r
+}\r
+\r
+/**\r
+  Retrieves the 64-bit frequency in Hz and the range of performance counter\r
+  values.\r
+\r
+  If StartValue is not NULL, then the value that the performance counter starts\r
+  with immediately after is it rolls over is returned in StartValue. If\r
+  EndValue is not NULL, then the value that the performance counter end with\r
+  immediately before it rolls over is returned in EndValue. The 64-bit\r
+  frequency of the performance counter in Hz is always returned. If StartValue\r
+  is less than EndValue, then the performance counter counts up. If StartValue\r
+  is greater than EndValue, then the performance counter counts down. For\r
+  example, a 64-bit free running counter that counts up would have a StartValue\r
+  of 0 and an EndValue of 0xFFFFFFFFFFFFFFFF. A 24-bit free running counter\r
+  that counts down would have a StartValue of 0xFFFFFF and an EndValue of 0.\r
+\r
+  @param  StartValue  The value the performance counter starts with when it\r
+                      rolls over.\r
+  @param  EndValue    The value that the performance counter ends with before\r
+                      it rolls over.\r
+\r
+  @return             The frequency in Hz.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+GetPerformanceCounterProperties (\r
+  OUT      UINT64                    *StartValue,  OPTIONAL\r
+  OUT      UINT64                    *EndValue     OPTIONAL\r
+  )\r
+{\r
+  if (StartValue != NULL) {\r
+    *StartValue = 0;\r
+  }\r
+\r
+  if (EndValue != NULL) {\r
+    *EndValue = V_PCH_ACPI_PM1_TMR_MAX_VAL - 1;\r
+  }\r
+\r
+  return V_PCH_ACPI_PM1_TMR_FREQUENCY;\r
+}\r
+\r
+/**\r
+  Converts elapsed ticks of performance counter to time in nanoseconds.\r
+\r
+  This function converts the elapsed ticks of running performance counter to\r
+  time value in unit of nanoseconds.\r
+\r
+  @param  Ticks     The number of elapsed ticks of running performance counter.\r
+\r
+  @return           The elapsed time in nanoseconds.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+GetTimeInNanoSecond (\r
+  IN      UINT64                     Ticks\r
+  )\r
+{\r
+  UINT64  NanoSeconds;\r
+  UINT32  Remainder;\r
+\r
+  //\r
+  //          Ticks\r
+  // Time = --------- x 1,000,000,000\r
+  //        Frequency\r
+  //\r
+  NanoSeconds = MultU64x32 (DivU64x32Remainder (Ticks, V_PCH_ACPI_PM1_TMR_FREQUENCY, &Remainder), 1000000000u);\r
+\r
+  //\r
+  // Frequency < 0x100000000, so Remainder < 0x100000000, then (Remainder * 1,000,000,000)\r
+  // will not overflow 64-bit.\r
+  //\r
+  NanoSeconds += DivU64x32 (MultU64x32 ((UINT64) Remainder, 1000000000u), V_PCH_ACPI_PM1_TMR_FREQUENCY);\r
+\r
+  return NanoSeconds;\r
+}\r
+\r
+\r

diff --git a/Vlv2TbltDevicePkg/Library/IntelPchAcpiTimerLib/IntelPchAcpiTimerLib.inf b/Vlv2TbltDevicePkg/Library/IntelPchAcpiTimerLib/IntelPchAcpiTimerLib.inf
new file mode 100644 (file)
index 0000000..f4fb5ab
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Library/IntelPchAcpiTimerLib/IntelPchAcpiTimerLib.inf
@@ -0,0 +1,56 @@
+#/** @file\r
+# Intel ICH9 Acpi Timer Instance\r
+#\r
+# ICH9 Acpi timer implements one instance of Timer Library. Acpi timer cannot be programmed,\r
+#  so it could be used by any types of drivers, including SMM drivers and Runtime drivers.\r
+# Copyright (c) 2007 - 2014, Intel Corporation. All rights reserved.<BR>\r
+#                                                                                  \r\r
+# This program and the accompanying materials are licensed and made available under\r\r
+# the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+# The full text of the license may be found at                                     \r\r
+# http://opensource.org/licenses/bsd-license.php.                                  \r\r
+#                                                                                  \r\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+#                                                                                  \r\r
+#\r
+#\r
+#\r
+#**/\r
+\r
+[Defines]\r
+  INF_VERSION                    = 0x00010005\r
+  BASE_NAME                      = IntelPchAcpiTimerLib\r
+  FILE_GUID                      = 0C0AC8C1-E368-4d20-85FE-23EFB3DB094E\r
+  MODULE_TYPE                    = BASE\r
+  VERSION_STRING                 = 1.0\r
+  LIBRARY_CLASS                  = TimerLib\r
+  EDK_RELEASE_VERSION            = 0x00020000\r
+  EFI_SPECIFICATION_VERSION      = 0x00020000\r
+\r
+  CONSTRUCTOR                    = IntelPchAcpiTimerLibConstructor\r
+\r
+#\r
+# The following information is for reference only and not required by the build tools.\r
+#\r
+#  VALID_ARCHITECTURES           = IA32 X64 IPF EBC\r
+#\r
+\r
+[Sources.common]\r
+  IntelPchAcpiTimerLib.c\r
+  CommonHeader.h\r
+\r
+[Packages]\r
+  MdePkg/MdePkg.dec\r
+  Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec\r
+  Vlv2TbltDevicePkg/PlatformPkg.dec\r
+\r
+[LibraryClasses]\r
+  PcdLib\r
+  PciLib\r
+  IoLib\r
+  BaseLib\r
+\r
+[Pcd.common]\r
+  gEfiPchTokenSpaceGuid.PcdPchAcpiIoPortBaseAddress\r
+  gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress\r

diff --git a/Vlv2TbltDevicePkg/Library/MultiPlatformLib/BoardClkGens/BoardClkGens.c b/Vlv2TbltDevicePkg/Library/MultiPlatformLib/BoardClkGens/BoardClkGens.c
new file mode 100644 (file)
index 0000000..1fc7312
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Library/MultiPlatformLib/BoardClkGens/BoardClkGens.c
@@ -0,0 +1,426 @@
+/** @file\r
+  Clock generator setting for multiplatform.\r
+\r
+  Copyright (c) 2010 - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+**/\r
+\r
+#include <BoardClkGens.h>\r
+#include <Guid/SetupVariable.h>\r
+#include <Ppi/ReadOnlyVariable2.h>\r
+#include <Library/BaseMemoryLib.h>\r
+\r
+#ifndef __GNUC__\r
+#pragma optimize( "", off )\r
+#endif\r
+\r
+#define CLKGEN_EN 1\r
+#define EFI_DEBUG 1\r
+\r
+CLOCK_GENERATOR_DETAILS   mSupportedClockGeneratorTable[] =\r
+{\r
+  { ClockGeneratorCk410, CK410_GENERATOR_ID , CK410_GENERATOR_SPREAD_SPECTRUM_BYTE, CK410_GENERATOR_SPREAD_SPECTRUM_BIT },\r
+  { ClockGeneratorCk505, CK505_GENERATOR_ID , CK505_GENERATOR_SPREAD_SPECTRUM_BYTE, CK505_GENERATOR_SPREAD_SPECTRUM_BIT }\r
+};\r
+\r
+/**\r
+  Configure the clock generator using the SMBUS PPI services.\r
+\r
+  This function performs a block write, and dumps debug information.\r
+\r
+  @param  PeiServices                General purpose services available to every PEIM.\r
+  @param  ClockType                  Clock generator's model name.\r
+  @param  ClockAddress               SMBUS address of clock generator.\r
+  @param  ConfigurationTableLength   Length of configuration table.\r
+  @param  ConfigurationTable         Pointer of configuration table.\r
+\r
+  @retval EFI_SUCCESS - Operation success.\r
+\r
+**/\r
+EFI_STATUS\r
+ConfigureClockGenerator (\r
+  IN     EFI_PEI_SERVICES              **PeiServices,\r
+  IN     EFI_PEI_SMBUS_PPI                 *SmbusPpi,\r
+  IN     CLOCK_GENERATOR_TYPE          ClockType,\r
+  IN     UINT8                         ClockAddress,\r
+  IN     UINTN                         ConfigurationTableLength,\r
+  IN OUT UINT8                         *ConfigurationTable\r
+  )\r
+{\r
+\r
+  EFI_STATUS                    Status;\r
+  EFI_SMBUS_DEVICE_ADDRESS      SlaveAddress;\r
+  UINT8                         Buffer[MAX_CLOCK_GENERATOR_BUFFER_LENGTH];\r
+  UINTN                         Length;\r
+  EFI_SMBUS_DEVICE_COMMAND      Command;\r
+#if CLKGEN_CONFIG_EXTRA\r
+  UINT8                         j;\r
+#endif\r
+\r
+  //\r
+  // Verify input arguments\r
+  //\r
+  ASSERT_EFI_ERROR (ConfigurationTableLength >= 6);\r
+  ASSERT_EFI_ERROR (ConfigurationTableLength <= MAX_CLOCK_GENERATOR_BUFFER_LENGTH);\r
+  ASSERT_EFI_ERROR (ClockType < ClockGeneratorMax);\r
+  ASSERT_EFI_ERROR (ConfigurationTable != NULL);\r
+\r
+  //\r
+  // Read the clock generator\r
+  //\r
+  SlaveAddress.SmbusDeviceAddress = ClockAddress >> 1;\r
+  Length = sizeof (Buffer);\r
+  Command = 0;\r
+  Status = SmbusPpi->Execute (\r
+    PeiServices,\r
+    SmbusPpi,\r
+    SlaveAddress,\r
+    Command,\r
+    EfiSmbusReadBlock,\r
+    FALSE,\r
+    &Length,\r
+    Buffer\r
+    );\r
+  ASSERT_EFI_ERROR (Status);\r
+\r
+#ifdef EFI_DEBUG\r
+  {\r
+    UINT8 i;\r
+    for (i = 0; i < sizeof (Buffer); i++) {\r
+      DEBUG((EFI_D_ERROR, "CK505 default Clock Generator Byte %d: %x\n", i, Buffer[i]));\r
+    }\r
+#if CLKGEN_EN\r
+    for (i = 0; i < ConfigurationTableLength; i++) {\r
+      DEBUG((EFI_D_ERROR, "BIOS structure Clock Generator Byte %d: %x\n", i, ConfigurationTable[i]));\r
+    }\r
+#endif\r
+  }\r
+#endif\r
+\r
+  DEBUG((EFI_D_ERROR, "Expected Clock Generator ID is %x, expecting %x\n", mSupportedClockGeneratorTable[ClockType].ClockId,(Buffer[7]&0xF)));\r
+\r
+  //\r
+  // Program clock generator\r
+  //\r
+  Command = 0;\r
+#if CLKGEN_EN\r
+#if CLKGEN_CONFIG_EXTRA\r
+  for (j = 0; j < ConfigurationTableLength; j++) {\r
+    Buffer[j] = ConfigurationTable[j];\r
+  }\r
+\r
+  Buffer[30] = 0x00;\r
+\r
+  Status = SmbusPpi->Execute (\r
+    PeiServices,\r
+    SmbusPpi,\r
+    SlaveAddress,\r
+    Command,\r
+    EfiSmbusWriteBlock,\r
+    FALSE,\r
+    &Length,\r
+    Buffer\r
+    );\r
+#else\r
+  Status = SmbusPpi->Execute (\r
+    PeiServices,\r
+    SmbusPpi,\r
+    SlaveAddress,\r
+    Command,\r
+    EfiSmbusWriteBlock,\r
+    FALSE,\r
+    &ConfigurationTableLength,\r
+    ConfigurationTable\r
+    );\r
+#endif // CLKGEN_CONFIG_EXTRA\r
+#else\r
+    ConfigurationTable[4] = (ConfigurationTable[4] & 0x3) | (Buffer[4] & 0xFC);\r
+    Command = 4;\r
+    Length = 1;\r
+  Status = SmbusPpi->Execute (\r
+    PeiServices,\r
+    SmbusPpi,\r
+    SlaveAddress,\r
+    Command,\r
+    EfiSmbusWriteBlock,\r
+    FALSE,\r
+    &Length,\r
+    &ConfigurationTable[4]\r
+    );\r
+#endif //CLKGEN_EN\r
+  ASSERT_EFI_ERROR (Status);\r
+\r
+  //\r
+  // Dump contents after write\r
+  //\r
+  #ifdef EFI_DEBUG\r
+    {\r
+      UINT8   i;\r
+    SlaveAddress.SmbusDeviceAddress = ClockAddress >> 1;\r
+    Length = sizeof (Buffer);\r
+      Command = 0;\r
+      Status =  SmbusPpi->Execute (\r
+        PeiServices,\r
+        SmbusPpi,\r
+        SlaveAddress,\r
+        Command,\r
+        EfiSmbusReadBlock,\r
+        FALSE,\r
+        &Length,\r
+        Buffer\r
+        );\r
+\r
+      for (i = 0; i < ConfigurationTableLength; i++) {\r
+        DEBUG((EFI_D_ERROR, "Clock Generator Byte %d: %x\n", i, Buffer[i]));\r
+      }\r
+    }\r
+    #endif\r
+\r
+  return EFI_SUCCESS;\r
+}\r
+\r
+/**\r
+  Configure the clock generator using the SMBUS PPI services.\r
+\r
+  This function performs a block write, and dumps debug information.\r
+\r
+  @param  PeiServices                General purpose services available to every PEIM.\r
+  @param  ClockType                  Clock generator's model name.\r
+  @param  ClockAddress               SMBUS address of clock generator.\r
+  @param  ConfigurationTableLength   Length of configuration table.\r
+  @param  ConfigurationTable         Pointer of configuration table.\r
+\r
+\r
+  @retval  EFI_SUCCESS  Operation success.\r
+\r
+**/\r
+UINT8\r
+ReadClockGeneratorID (\r
+  IN     EFI_PEI_SERVICES              **PeiServices,\r
+  IN     EFI_PEI_SMBUS_PPI                 *SmbusPpi,\r
+  IN     UINT8                         ClockAddress\r
+  )\r
+{\r
+  EFI_STATUS                    Status;\r
+  EFI_SMBUS_DEVICE_ADDRESS      SlaveAddress;\r
+  UINT8                         Buffer[MAX_CLOCK_GENERATOR_BUFFER_LENGTH];\r
+  UINTN                         Length;\r
+  EFI_SMBUS_DEVICE_COMMAND      Command;\r
+\r
+  //\r
+  // Read the clock generator\r
+  //\r
+  SlaveAddress.SmbusDeviceAddress = ClockAddress >> 1;\r
+  Length = sizeof (Buffer);\r
+  Command = 0;\r
+  Status = SmbusPpi->Execute (\r
+    PeiServices,\r
+    SmbusPpi,\r
+    SlaveAddress,\r
+    Command,\r
+    EfiSmbusReadBlock,\r
+    FALSE,\r
+    &Length,\r
+    Buffer\r
+    );\r
+\r
+  //\r
+  // Sanity check that the requested clock type is present in our supported clocks table\r
+  //\r
+  DEBUG((EFI_D_ERROR, "Expected Clock Generator ID is 0x%x\n", Buffer[7]));\r
+\r
+  return (Buffer[7]);\r
+}\r
+\r
+/**\r
+  Configure the clock generator to enable free-running operation.  This keeps\r
+  the clocks from being stopped when the system enters C3 or C4.\r
+\r
+  @param None\r
+\r
+  @retval EFI_SUCCESS    The function completed successfully.\r
+\r
+**/\r
+EFI_STATUS\r
+ConfigurePlatformClocks (\r
+  IN EFI_PEI_SERVICES           **PeiServices,\r
+  IN EFI_PEI_NOTIFY_DESCRIPTOR  *NotifyDescriptor,\r
+  IN VOID                       *SmbusPpi\r
+  )\r
+{\r
+  //\r
+  // Comment it out for now\r
+  // Not supported by Hybrid model.\r
+  //\r
+  EFI_STATUS                    Status;\r
+  UINT8                         *ConfigurationTable;\r
+\r
+  CLOCK_GENERATOR_TYPE          ClockType = ClockGeneratorCk505;\r
+  UINT8                         ConfigurationTable_Desktop[] = CLOCK_GENERATOR_SETTINGS_DESKTOP;\r
+  UINT8                         ConfigurationTable_Mobile[] = CLOCK_GENERATOR_SETTINGS_MOBILE;\r
+  UINT8                         ConfigurationTable_Tablet[] = CLOCK_GENERATOR_SEETINGS_TABLET;\r
+\r
+  EFI_PLATFORM_INFO_HOB         *PlatformInfoHob;\r
+  BOOLEAN                       EnableSpreadSpectrum;\r
+  UINT8                         ClockGenID=0;\r
+  SYSTEM_CONFIGURATION          SystemConfiguration;\r
+\r
+  UINTN                         Length;\r
+  EFI_SMBUS_DEVICE_COMMAND      Command;\r
+  EFI_SMBUS_DEVICE_ADDRESS      SlaveAddress;\r
+  UINT8                         Data;\r
+\r
+  UINT8                         ClockAddress = CLOCK_GENERATOR_ADDRESS;\r
+  UINTN                         VariableSize;\r
+  EFI_PEI_READ_ONLY_VARIABLE2_PPI   *Variable;\r
+\r
+  //\r
+  // Obtain Platform Info from HOB.\r
+  //\r
+  Status = GetPlatformInfoHob ((CONST EFI_PEI_SERVICES **) PeiServices, &PlatformInfoHob);\r
+  ASSERT_EFI_ERROR (Status);\r
+\r
+  DEBUG((EFI_D_ERROR, "PlatformInfo protocol is working in ConfigurePlatformClocks()...%x\n",PlatformInfoHob->PlatformFlavor));\r
+\r
+  //\r
+  // Locate SMBUS PPI\r
+  //\r
+  Status = (**PeiServices).LocatePpi (\r
+                             (CONST EFI_PEI_SERVICES **) PeiServices,\r
+                             &gEfiPeiSmbusPpiGuid,\r
+                             0,\r
+                             NULL,\r
+                             &SmbusPpi\r
+                             );\r
+  ASSERT_EFI_ERROR (Status);\r
+\r
+  Data  = 0;\r
+  SlaveAddress.SmbusDeviceAddress = ClockAddress >> 1;\r
+  Length = 1;\r
+  Command = 0x87;   //Control Register 7 Vendor ID Check\r
+  Status = ((EFI_PEI_SMBUS_PPI *) SmbusPpi)->Execute (\r
+                                               PeiServices,\r
+                                               SmbusPpi,\r
+                                               SlaveAddress,\r
+                                               Command,\r
+                                               EfiSmbusReadByte,\r
+                                               FALSE,\r
+                                               &Length,\r
+                                               &Data\r
+                                               );\r
+\r
+  if (EFI_ERROR (Status) || ((Data & 0x0F) != CK505_GENERATOR_ID)) {\r
+      DEBUG((EFI_D_ERROR, "Clock Generator CK505 Not Present, vendor ID on board is %x\n",(Data & 0x0F)));\r
+      return EFI_SUCCESS;\r
+}\r
+  ClockGenID = Data & 0x0F;\r
+\r
+  EnableSpreadSpectrum = FALSE;\r
+  VariableSize = sizeof (SYSTEM_CONFIGURATION);\r
+  ZeroMem (&SystemConfiguration, sizeof (SYSTEM_CONFIGURATION));\r
+\r
+  Status = (*PeiServices)->LocatePpi (\r
+                             (CONST EFI_PEI_SERVICES **) PeiServices,\r
+                             &gEfiPeiReadOnlyVariable2PpiGuid,\r
+                             0,\r
+                             NULL,\r
+                             (VOID **) &Variable\r
+                             );\r
+  //\r
+  // Use normal setup default from NVRAM variable,\r
+  // the Platform Mode (manufacturing/safe/normal) is handle in PeiGetVariable.\r
+  //\r
+  VariableSize = sizeof(SYSTEM_CONFIGURATION);\r
+  Status = Variable->GetVariable (Variable,\r
+                                   L"Setup",\r
+                                   &gEfiSetupVariableGuid,\r
+                                   NULL,\r
+                                   &VariableSize,\r
+                                   &SystemConfiguration);\r
+\r
+  if(!EFI_ERROR (Status)){\r
+    EnableSpreadSpectrum = SystemConfiguration.EnableClockSpreadSpec;\r
+  }\r
+\r
+  //\r
+  // Perform platform-specific intialization dependent upon Board ID:\r
+  //\r
+  DEBUG((EFI_D_ERROR, "board id is %x, platform id is %x\n",PlatformInfoHob->BoardId,PlatformInfoHob->PlatformFlavor));\r
+\r
+\r
+  switch (PlatformInfoHob->BoardId) {\r
+    case BOARD_ID_MINNOW2:\r
+    default:\r
+      switch(PlatformInfoHob->PlatformFlavor) {\r
+      case FlavorTablet:\r
+        ConfigurationTable = ConfigurationTable_Tablet;\r
+        Length = sizeof (ConfigurationTable_Tablet);\r
+        break;\r
+      case FlavorMobile:\r
+        ConfigurationTable = ConfigurationTable_Mobile;\r
+        Length = sizeof (ConfigurationTable_Mobile);\r
+        break;\r
+      case FlavorDesktop:\r
+      default:\r
+        ConfigurationTable = ConfigurationTable_Desktop;\r
+        Length = sizeof (ConfigurationTable_Desktop);\r
+        break;\r
+      }\r
+    break;\r
+    }\r
+\r
+  //\r
+  // Perform common clock initialization:\r
+  //\r
+  // Program Spread Spectrum function.\r
+  //\r
+  if (EnableSpreadSpectrum)\r
+  {\r
+    ConfigurationTable[mSupportedClockGeneratorTable[ClockType].SpreadSpectrumByteOffset] |= mSupportedClockGeneratorTable[ClockType].SpreadSpectrumBitOffset;\r
+  } else {\r
+    ConfigurationTable[mSupportedClockGeneratorTable[ClockType].SpreadSpectrumByteOffset] &= ~(mSupportedClockGeneratorTable[ClockType].SpreadSpectrumBitOffset);\r
+  }\r
+\r
+\r
+#if CLKGEN_EN\r
+  Status = ConfigureClockGenerator (PeiServices, SmbusPpi, ClockType, ClockAddress, Length, ConfigurationTable);\r
+  ASSERT_EFI_ERROR (Status);\r
+#endif // CLKGEN_EN\r
+  return EFI_SUCCESS;\r
+}\r
+\r
+static EFI_PEI_NOTIFY_DESCRIPTOR    mNotifyList[] = {\r
+  {\r
+    EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK| EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,\r
+    &gEfiPeiSmbusPpiGuid,\r
+    ConfigurePlatformClocks\r
+  }\r
+};\r
+\r
+EFI_STATUS\r
+InstallPlatformClocksNotify (\r
+  IN CONST EFI_PEI_SERVICES           **PeiServices\r
+  )\r
+{\r
+  EFI_STATUS                    Status;\r
+\r
+  DEBUG ((EFI_D_INFO, "InstallPlatformClocksNotify()...\n"));\r
+\r
+  Status = (*PeiServices)->NotifyPpi(PeiServices, &mNotifyList[0]);\r
+  ASSERT_EFI_ERROR (Status);\r
+  return EFI_SUCCESS;\r
+\r
+}\r
+\r
+#ifndef __GNUC__\r
+#pragma optimize( "", on )\r
+#endif\r

diff --git a/Vlv2TbltDevicePkg/Library/MultiPlatformLib/BoardClkGens/BoardClkGens.h b/Vlv2TbltDevicePkg/Library/MultiPlatformLib/BoardClkGens/BoardClkGens.h
new file mode 100644 (file)
index 0000000..4ec5b88
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Library/MultiPlatformLib/BoardClkGens/BoardClkGens.h
@@ -0,0 +1,260 @@
+/**@file\r
+  Clock generator setting for multiplatform.\r
+\r
+  This file includes package header files, library classes.\r
+\r
+  Copyright (c) 2010 - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+**/\r
+\r
+#ifndef _BOARD_CLK_GEN_H_\r
+#define _BOARD_CLK_GEN_H_\r
+\r
+#include <PiPei.h>\r
+#include <Library/HobLib.h>\r
+#include <Library/IoLib.h>\r
+#include <Library/DebugLib.h>\r
+#include <Library/SmbusLib.h>\r
+#include <Ppi/Smbus.h>\r
+#include <IndustryStandard/SmBus.h>\r
+#include <Guid/PlatformInfo.h>\r
+\r
+\r
+#define CLOCK_GENERATOR_ADDRESS  0xd2\r
+\r
+#define CLOCK_GENERATOR_SEETINGS_TABLET {0xB1, 0x82, 0xFF, 0xBF, 0xFF, 0x80}\r
+#define CLOCK_GENERATOR_SETTINGS_MOBILE {0xB1, 0x82, 0xFF, 0xBF, 0xFF, 0x80}\r
+#define CLOCK_GENERATOR_SETTINGS_DESKTOP {0xB1, 0x82, 0xFF, 0xBF, 0xFF, 0x80}\r
+\r
+typedef enum {\r
+  ClockGeneratorCk410,\r
+  ClockGeneratorCk505,\r
+  ClockGeneratorMax\r
+} CLOCK_GENERATOR_TYPE;\r
+\r
+typedef struct {\r
+  CLOCK_GENERATOR_TYPE      ClockType;\r
+  UINT8                     ClockId;\r
+  UINT8                     SpreadSpectrumByteOffset;\r
+  UINT8                     SpreadSpectrumBitOffset;\r
+} CLOCK_GENERATOR_DETAILS;\r
+\r
+#define MAX_CLOCK_GENERATOR_BUFFER_LENGTH           0x20\r
+\r
+//\r
+// CK410 Definitions\r
+//\r
+#define CK410_GENERATOR_ID                          0x65\r
+#define CK410_GENERATOR_SPREAD_SPECTRUM_BYTE        1\r
+#define CK410_GENERATOR_SPREAD_SPECTRUM_BIT         BIT0\r
+#define CK410_GENERATOR_CLOCK_FREERUN_BYTE          4\r
+#define CK410_GENERATOR_CLOCK_FREERUN_BIT           (BIT0 | BIT1 | BIT2)\r
+\r
+//\r
+// CK505 Definitions\r
+//\r
+#define VF_CK505_GENERATOR_ID                       0x5\r
+#define CK505_GENERATOR_ID                          0x5  // Confirmed readout is 5\r
+#define CK505_GENERATOR_SPREAD_SPECTRUM_BYTE        4\r
+#define CK505_GENERATOR_SPREAD_SPECTRUM_BIT         (BIT0 | BIT1)\r
+#define CK505_GENERATOR_PERCENT_SPREAD_BYTE      1\r
+#define CK505_GENERATOR_PERCENT_MASK        ~(0xE)\r
+#define CK505_GENERATOR_PERCENT_250_VALUE      0xC\r
+#define CK505_GENERATOR_PERCENT_050_VALUE      0x4\r
+#define CK505_GENERATOR_PERCENT_000_VALUE      0x2\r
+\r
+//\r
+// IDT Definitions\r
+//\r
+#define IDT_GENERATOR_ID_REVA                       0x1    //IDT Rev A\r
+#define IDTRevA_GENERATOR_SPREAD_SPECTRUM_BYTE        0\r
+#define IDTRevA_GENERATOR_SPREAD_SPECTRUM_BIT       BIT0\r
+#define IDTRevA_GENERATOR_PERCENT_SPREAD_BYTE      5\r
+#define IDTRevA_GENERATOR_PERCENT_250_VALUE      0xF\r
+#define IDTRevA_GENERATOR_PERCENT_050_VALUE      0x3\r
+#define IDTRevA_GENERATOR_PERCENT_000_VALUE      0xE\r
+#define IDTRevA_GENERATOR_PERCENT_MASK        ~(0xF)\r
+\r
+#define IDT_GENERATOR_ID_REVB                       0x11  //IDT RevB\r
+#define IDT_GENERATOR_ID_REVD                       0x21  //IDT RevD\r
+\r
+//\r
+// CLOCK CONTROLLER\r
+// SmBus address to read DIMM SPD\r
+//\r
+#define SMBUS_BASE_ADDRESS                  0xEFA0\r
+#define SMBUS_BUS_DEV_FUNC                  0x1F0300\r
+#define PLATFORM_NUM_SMBUS_RSVD_ADDRESSES   4\r
+#define SMBUS_ADDR_CH_A_1                   0xA0\r
+#define SMBUS_ADDR_CH_A_2                   0xA2\r
+#define SMBUS_ADDR_CH_B_1                   0xA4\r
+#define SMBUS_ADDR_CH_B_2                   0xA6\r
+\r
+//\r
+// Bits for FWH_DEC_EN1\97Firmware Hub Decode Enable Register (LPC I/F\97D31:F0)\r
+//\r
+#define   B_ICH_LPC_FWH_BIOS_DEC_F0             0x4000\r
+#define   B_ICH_LPC_FWH_BIOS_DEC_E0             0x1000\r
+#define   B_ICH_LPC_FWH_BIOS_DEC_E8             0x2000\r
+#define   B_ICH_LPC_FWH_BIOS_LEG_F              0x0080\r
+#define   B_ICH_LPC_FWH_BIOS_LEG_E              0x0040\r
+\r
+\r
+//\r
+// An arbitrary maximum length for clock generator buffers\r
+//\r
+#define MAX_CLOCK_GENERATOR_BUFFER_LENGTH           0x20\r
+\r
+//\r
+// SmBus Bus Device Function and Register Definitions\r
+//\r
+#define SMBUS_BUS_NUM          0\r
+#define SMBUS_DEV_NUM          31\r
+#define SMBUS_FUNC_NUM          3\r
+#define SMBUS_BUS_DEV_FUNC_NUM    \\r
+      SB_PCI_CFG_ADDRESS(SMBUS_BUS_NUM, SMBUS_DEV_NUM, SMBUS_FUNC_NUM, 0)\r
+\r
+//\r
+//ICH7: SMBus I/O Space Equates;\r
+//\r
+#define  BIT_SLAVE_ADDR    BIT00\r
+#define  BIT_COMMAND      BIT01\r
+#define  BIT_DATA      BIT02\r
+#define  BIT_COUNT      BIT03\r
+#define  BIT_WORD      BIT04\r
+#define  BIT_CONTROL      BIT05\r
+#define  BIT_PEC        BIT06\r
+#define  BIT_READ      BIT07\r
+#define  SMBUS_IO_READ_BIT  BIT00\r
+\r
+\r
+#define  SMB_CMD_QUICK      0x00\r
+#define  SMB_CMD_BYTE      0x04\r
+#define  SMB_CMD_BYTE_DATA    0x08\r
+#define  SMB_CMD_WORD_DATA    0x0C\r
+#define  SMB_CMD_PROCESS_CALL  0x10\r
+#define  SMB_CMD_BLOCK      0x14\r
+#define  SMB_CMD_I2C_READ    0x18\r
+#define  SMB_CMD_RESERVED    0x1c\r
+\r
+#define  HST_STS_BYTE_DONE 0x80\r
+#define SMB_HST_STS    0x000\r
+#define SMB_HST_CNT    0x002\r
+#define SMB_HST_CMD    0x003\r
+#define SMB_HST_ADD    0x004\r
+#define SMB_HST_DAT_0    0x005\r
+#define SMB_HST_DAT_1    0x006\r
+#define SMB_HST_BLK_DAT   0x007\r
+#define SMB_PEC     0x008\r
+#define SMB_RCV_SLVA    0x009\r
+#define SMB_SLV_DAT    0x00A\r
+#define SMB_AUX_STS    0x00C\r
+#define SMB_AUX_CTL    0x00D\r
+#define SMB_SMLINK_PIN_CTL  0x00E\r
+#define SMB_SMBUS_PIN_CTL  0x00F\r
+#define SMB_SLV_STS    0x010\r
+#define SMB_SLV_CMD    0x011\r
+#define SMB_NTFY_DADDR    0x014\r
+#define SMB_NTFY_DLOW    0x016\r
+#define SMB_NTFY_DHIGH    0x017\r
+\r
+//\r
+// PCI Register Definitions - use SmbusPolicyPpi->PciAddress + offset listed below\r
+//\r
+#define R_COMMAND                     0x04      // PCI Command Register, 16bit\r
+#define   B_IOSE                        0x01    // RW\r
+#define R_BASE_ADDRESS                0x20      // PCI BAR for SMBus I/O\r
+#define   B_BASE_ADDRESS                0xFFE0  // RW\r
+#define R_HOST_CONFIGURATION          0x40      // SMBus Host Configuration Register\r
+#define   B_HST_EN                      0x01    // RW\r
+#define   B_SMB_SMI_EN                  0x02    // RW\r
+#define   B_I2C_EN                      0x04    // RW\r
+//\r
+// I/O Register Definitions - use SmbusPolicyPpi->BaseAddress + offset listed below\r
+//\r
+#define HOST_STATUS_REGISTER      0x00  // Host Status Register R/W\r
+#define    HST_STS_HOST_BUSY                  0x01  // RO\r
+#define   HST_STS_INTR                  0x02  // R/WC\r
+#define   HST_STS_DEV_ERR                  0x04  // R/WC\r
+#define   HST_STS_BUS_ERR                  0x08  // R/WC\r
+#define   HST_STS_FAILED                  0x10  // R/WC\r
+#define   SMBUS_B_SMBALERT_STS          0x20  // R/WC\r
+#define   HST_STS_INUSE                   0x40  // R/WC\r
+#define   SMBUS_B_BYTE_DONE_STS         0x80  // R/WC\r
+#define   SMBUS_B_HSTS_ALL              0xFF  // R/WC\r
+#define  HOST_CONTROL_REGISTER                  0x02  // Host Control Register R/W\r
+#define    HST_CNT_INTREN                0x01  // RW\r
+#define   HST_CNT_KILL                  0x02  // RW\r
+#define   SMBUS_B_SMB_CMD               0x1C  // RW\r
+#define     SMBUS_V_SMB_CMD_QUICK         0x00\r
+#define     SMBUS_V_SMB_CMD_BYTE          0x04\r
+#define     SMBUS_V_SMB_CMD_BYTE_DATA     0x08\r
+#define     SMBUS_V_SMB_CMD_WORD_DATA     0x0C\r
+#define     SMBUS_V_SMB_CMD_PROCESS_CALL  0x10\r
+#define     SMBUS_V_SMB_CMD_BLOCK         0x14\r
+#define     SMBUS_V_SMB_CMD_IIC_READ      0x18\r
+#define   SMBUS_B_LAST_BYTE             0x20  // WO\r
+#define   HST_CNT_START                 0x40  // WO\r
+#define   HST_CNT_PEC_EN                0x80  // RW\r
+#define  HOST_COMMAND_REGISTER                  0x03  // Host Command Register R/W\r
+#define  XMIT_SLAVE_ADDRESS_REGISTER                   0x04  // Transmit Slave Address Register R/W\r
+#define   SMBUS_B_RW_SEL                0x01  // RW\r
+#define   SMBUS_B_ADDRESS               0xFE  // RW\r
+#define  HOST_DATA_0_REGISTER                   0x05  // Data 0 Register R/W\r
+#define  HOST_DATA_1_REGISTER                   0x06  // Data 1 Register R/W\r
+#define  HOST_BLOCK_DATA_BYTE_REGISTER          0x07  // Host Block Data Register R/W\r
+#define SMBUS_R_PEC                   0x08  // Packet Error Check Data Register R/W\r
+#define SMBUS_R_RSA                   0x09  // Receive Slave Address Register R/W\r
+#define   SMBUS_B_SLAVE_ADDR            0x7F  // RW\r
+#define SMBUS_R_SD                    0x0A  // Receive Slave Data Register R/W\r
+#define SMBUS_R_AUXS                  0x0C  // Auxiliary Status Register R/WC\r
+#define   SMBUS_B_CRCE                  0x01  //R/WC\r
+#define AUXILIARY_CONTROL_REGISTER                  0x0D  // Auxiliary Control Register R/W\r
+#define   SMBUS_B_AAC                  0x01  //R/W\r
+#define   SMBUS_B_E32B                 0x02  //R/W\r
+#define  SMBUS_R_SMLC                  0x0E  // SMLINK Pin Control Register R/W\r
+#define   SMBUS_B_SMLINK0_CUR_STS       0x01  // RO\r
+#define   SMBUS_B_SMLINK1_CUR_STS       0x02  // RO\r
+#define   SMBUS_B_SMLINK_CLK_CTL        0x04  // RW\r
+#define SMBUS_R_SMBC                  0x0F  // SMBus Pin Control Register R/W\r
+#define   SMBUS_B_SMBCLK_CUR_STS        0x01  // RO\r
+#define   SMBUS_B_SMBDATA_CUR_STS       0x02  // RO\r
+#define   SMBUS_B_SMBCLK_CTL            0x04  // RW\r
+#define SMBUS_R_SSTS                  0x10  // Slave Status Register R/WC\r
+#define   SMBUS_B_HOST_NOTIFY_STS       0x01  // R/WC\r
+#define SMBUS_R_SCMD                  0x11  // Slave Command Register R/W\r
+#define   SMBUS_B_HOST_NOTIFY_INTREN    0x01  // R/W\r
+#define   SMBUS_B_HOST_NOTIFY_WKEN      0x02  // R/W\r
+#define   SMBUS_B_SMBALERT_DIS          0x04  // R/W\r
+#define SMBUS_R_NDA                   0x14  // Notify Device Address Register RO\r
+#define   SMBUS_B_DEVICE_ADDRESS        0xFE  // RO\r
+#define SMBUS_R_NDLB                  0x16  // Notify Data Low Byte Register RO\r
+#define SMBUS_R_NDHB                  0x17  // Notify Data High Byte Register RO\r
+#define BUS_TRIES           3       // How many times to retry on Bus Errors\r
+#define SMBUS_NUM_RESERVED  21      // Number of device addresses that are\r
+                                    //   reserved by the SMBus spec.\r
+#define SMBUS_ADDRESS_ARP   0xC2 >> 1\r
+#define   SMBUS_DATA_PREPARE_TO_ARP   0x01\r
+#define   SMBUS_DATA_RESET_DEVICE     0x02\r
+#define   SMBUS_DATA_GET_UDID_GENERAL 0x03\r
+#define   SMBUS_DATA_ASSIGN_ADDRESS   0x04\r
+#define SMBUS_GET_UDID_LENGTH 17    // 16 byte UDID + 1 byte address\r
+\r
+\r
+EFI_STATUS\r
+ConfigurePlatformClocks (\r
+  IN EFI_PEI_SERVICES           **PeiServices,\r
+  IN EFI_PEI_NOTIFY_DESCRIPTOR  *NotifyDescriptor,\r
+  IN VOID                       *SmbusPpi\r
+  );\r
+\r
+\r
+#endif\r

diff --git a/Vlv2TbltDevicePkg/Library/MultiPlatformLib/BoardGpios/BoardGpios.c b/Vlv2TbltDevicePkg/Library/MultiPlatformLib/BoardGpios/BoardGpios.c
new file mode 100644 (file)
index 0000000..092d3f3
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Library/MultiPlatformLib/BoardGpios/BoardGpios.c
@@ -0,0 +1,535 @@
+/** @file\r
+  Gpio setting for multiplatform..\r
+\r
+  Copyright (c) 2013 - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+**/\r
+\r
+#include <BoardGpios.h>\r
+#include <Guid/SetupVariable.h>\r
+\r
+//\r
+//AlpineValley platform ocde begin\r
+//\r
+#define AV_SC_REG_GPIOS_MUXES_SEL0 0x48\r
+#define AV_SC_REG_GPIOS_MUXES_SEL1 0x4C\r
+#define AV_SC_REG_GPIOS_MUXES_SEL2 0x50\r
+#define AV_SC_REG_GPIOS_MUXES_EN0  0x54\r
+#define AV_SC_REG_GPIOS_MUXES_EN1  0x58\r
+#define AV_SC_REG_GPIOS_MUXES_EN2  0x5C\r
+//\r
+//AlpineValley platform code end\r
+//\r
+\r
+EFI_GUID  gPeiSmbusPpiGuid               = EFI_PEI_SMBUS_PPI_GUID;\r
+\r
+/**\r
+  @param None\r
+\r
+  @retval EFI_SUCCESS    The function completed successfully.\r
+\r
+**/\r
+EFI_STATUS\r
+ConfigurePlatformSysCtrlGpio (\r
+  IN EFI_PEI_SERVICES                   **PeiServices,\r
+  IN EFI_PEI_NOTIFY_DESCRIPTOR          *NotifyDescriptor,\r
+  IN VOID                               *SmbusPpi\r
+  )\r
+{\r
+  //\r
+  //AlpineValley platform code begin\r
+  //\r
+  // Initialize GPIO Settings:\r
+  //\r
+  UINT32        Status;\r
+  EFI_PLATFORM_INFO_HOB               *PlatformInfoHob;\r
+\r
+   DEBUG ((EFI_D_INFO, "ConfigurePlatformSysCtrlGpio()...\n"));\r
+\r
+  //\r
+  // Obtain Platform Info from HOB.\r
+  //\r
+  Status = GetPlatformInfoHob ((const EFI_PEI_SERVICES **)PeiServices, &PlatformInfoHob);\r
+  ASSERT_EFI_ERROR (Status);\r
+\r
+  //\r
+  // The GPIO settings are dependent upon the platform.  Obtain the Board ID through\r
+  // the EC to determine the current platform.\r
+  //\r
+   DEBUG ((EFI_D_INFO, "Platform Flavor | Board ID = 0x%X | 0x%X\n", PlatformInfoHob->PlatformFlavor, PlatformInfoHob->BoardId));\r
+\r
+\r
+\r
+  Status = (**PeiServices).LocatePpi (\r
+                            (const EFI_PEI_SERVICES **)PeiServices,\r
+                            &gPeiSmbusPpiGuid,\r
+                            0,\r
+                            NULL,\r
+                            (void **)&SmbusPpi\r
+                            );\r
+  ASSERT_EFI_ERROR (Status);\r
+\r
+  //\r
+  // Select/modify the GPIO initialization data based on the Board ID.\r
+  //\r
+  switch (PlatformInfoHob->BoardId)\r
+  {\r
+    default:\r
+      Status = EFI_SUCCESS;\r
+\r
+      //\r
+      // Do nothing for other RVP boards.\r
+      //\r
+      break;\r
+  }\r
+  return Status;\r
+}\r
+\r
+static EFI_PEI_NOTIFY_DESCRIPTOR    mNotifyList[] = {\r
+  {\r
+    EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK| EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,\r
+    &gEfiPeiSmbusPpiGuid,\r
+    ConfigurePlatformSysCtrlGpio\r
+  }\r
+};\r
+\r
+EFI_STATUS\r
+InstallPlatformSysCtrlGPIONotify (\r
+  IN CONST EFI_PEI_SERVICES           **PeiServices\r
+  )\r
+{\r
+  EFI_STATUS                    Status;\r
+\r
+  DEBUG ((EFI_D_INFO, "InstallPlatformSysCtrlGPIONotify()...\n"));\r
+\r
+  Status = (*PeiServices)->NotifyPpi(PeiServices, &mNotifyList[0]);\r
+  ASSERT_EFI_ERROR (Status);\r
+  return EFI_SUCCESS;\r
+\r
+}\r
+\r
+#define V_PCH_ILB_IRQE_UARTIRQEN_IRQ3             BIT3 // UART IRQ3 Enable\r
+\r
+/**\r
+  Returns the Correct GPIO table for Mobile/Desktop respectively.\r
+  Before call it, make sure PlatformInfoHob->BoardId&PlatformFlavor is get correctly.\r
+\r
+  @param PeiServices             General purpose services available to every PEIM.\r
+  @param PlatformInfoHob         PlatformInfoHob pointer with PlatformFlavor specified.\r
+  @param BoardId                 BoardId ID as determined through the EC.\r
+\r
+  @retval EFI_SUCCESS            The function completed successfully.\r
+  @retval EFI_DEVICE_ERROR       KSC fails to respond.\r
+\r
+**/\r
+EFI_STATUS\r
+MultiPlatformGpioTableInit (\r
+  IN CONST EFI_PEI_SERVICES     **PeiServices,\r
+  IN EFI_PLATFORM_INFO_HOB      *PlatformInfoHob\r
+  )\r
+{\r
+  EFI_STATUS                      Status;\r
+  EFI_PEI_READ_ONLY_VARIABLE2_PPI *PeiReadOnlyVarPpi;\r
+  UINTN                           VarSize;\r
+  SYSTEM_CONFIGURATION            SystemConfiguration;\r
+\r
+  DEBUG ((EFI_D_INFO, "MultiPlatformGpioTableInit()...\n"));\r
+\r
+  //\r
+  // Select/modify the GPIO initialization data based on the Board ID.\r
+  //\r
+  switch (PlatformInfoHob->BoardId) {\r
+\r
+  case BOARD_ID_MINNOW2: // Minnow2\r
+  \r
+   Status = (**PeiServices).LocatePpi (\r
+                             PeiServices,\r
+                             &gEfiPeiReadOnlyVariable2PpiGuid,\r
+                             0,\r
+                             NULL,\r
+                             (void **)&PeiReadOnlyVarPpi\r
+                             );\r
+    ASSERT_EFI_ERROR (Status);\r
+   \r
+    VarSize = sizeof (SYSTEM_CONFIGURATION);\r
+    Status = PeiReadOnlyVarPpi->GetVariable ( \r
+                                  PeiReadOnlyVarPpi, \r
+                                  PLATFORM_SETUP_VARIABLE_NAME, \r
+                                  &gEfiSetupVariableGuid,\r
+                                  NULL,\r
+                                  &VarSize,\r
+                                  &SystemConfiguration\r
+                                  );\r
+                                                                       \r
+     if (SystemConfiguration.GpioWakeCapability == 1) {\r
+      PlatformInfoHob->PlatformCfioData     = (EFI_PHYSICAL_ADDRESS)(UINTN) &mMinnow2CfioInitData2;\r
+     }\r
+     else {\r
+      PlatformInfoHob->PlatformCfioData     = (EFI_PHYSICAL_ADDRESS)(UINTN) &mMinnow2CfioInitData;\r
+     } \r
+        \r
+     PlatformInfoHob->PlatformGpioData_NC  = (EFI_PHYSICAL_ADDRESS)(UINTN) &mMinnow2_GpioInitData_NC[0];\r
+     PlatformInfoHob->PlatformGpioData_SC  = (EFI_PHYSICAL_ADDRESS)(UINTN) &mMinnow2_GpioInitData_SC[0];\r
+     PlatformInfoHob->PlatformGpioData_SUS = (EFI_PHYSICAL_ADDRESS)(UINTN) &mMinnow2_GpioInitData_SUS[0];\r
+     break;\r
+\r
+  }\r
+\r
+  return EFI_SUCCESS;\r
+}\r
+\r
+UINT32\r
+GPIORead32 (\r
+  IN  UINT32 mmio_conf\r
+  )\r
+{\r
+  UINT32 conf_val;\r
+  UINT32 i;\r
+  conf_val = MmioRead32(mmio_conf);\r
+  for(i=0;i<5;i++){\r
+    if(conf_val == 0xffffffff)\r
+      conf_val = MmioRead32(mmio_conf);\r
+      else\r
+        break;\r
+  }\r
+\r
+  return conf_val;\r
+}\r
+\r
+/**\r
+\r
+  Set GPIO CONF0 and PAD_VAL registers for NC/SC/SUS GPIO clusters\r
+\r
+  @param Gpio_Mmio_Offset          GPIO_SCORE_OFFSET or GPIO_NCORE_OFFSET or GPIO_SSUS_OFFSET.\r
+  @param Gpio_Pin_Num              Pin numbers to config for each GPIO clusters.\r
+  @param Gpio_Conf_Data            GPIO_CONF_PAD_INIT data array for each GPIO clusters.\r
+\r
+**/\r
+VOID\r
+InternalGpioConfig (\r
+  IN UINT32             Gpio_Mmio_Offset,\r
+  IN UINT32             Gpio_Pin_Num,\r
+  GPIO_CONF_PAD_INIT*   Gpio_Conf_Data\r
+  )\r
+{\r
+  UINT32    index;\r
+  UINT32    mmio_conf0;\r
+  UINT32    mmio_padval;\r
+  PAD_CONF0 conf0_val;\r
+  PAD_VAL   pad_val;\r
+\r
+  //\r
+  // GPIO WELL -- Memory base registers\r
+  //\r
+\r
+  // A0 BIOS Spec doesn't mention it although X0 does. comment out now.\r
+  // GPIO write 0x01001002 to IOBASE + Gpio_Mmio_Offset + 0x0900\r
+  //\r
+  for(index=0; index < Gpio_Pin_Num; index++)\r
+  {\r
+       //\r
+    // Calculate the MMIO Address for specific GPIO pin CONF0 register pointed by index.\r
+    //\r
+    mmio_conf0 = IO_BASE_ADDRESS + Gpio_Mmio_Offset + R_PCH_CFIO_PAD_CONF0 + Gpio_Conf_Data[index].offset * 16;\r
+    mmio_padval= IO_BASE_ADDRESS + Gpio_Mmio_Offset + R_PCH_CFIO_PAD_VAL   + Gpio_Conf_Data[index].offset * 16;\r
+\r
+#ifdef EFI_DEBUG\r
+    DEBUG ((EFI_D_INFO, "%s, ", Gpio_Conf_Data[index].pad_name));\r
+\r
+#endif\r
+    DEBUG ((EFI_D_INFO, "Usage = %d, Func# = %d, IntType = %d, Pull Up/Down = %d, MMIO Base = 0x%08x, ",\r
+      Gpio_Conf_Data[index].usage,\r
+      Gpio_Conf_Data[index].func,\r
+      Gpio_Conf_Data[index].int_type,\r
+      Gpio_Conf_Data[index].pull,\r
+      mmio_conf0));\r
+\r
+    //\r
+    // Step 1: PadVal Programming.\r
+    //\r
+    pad_val.dw = GPIORead32(mmio_padval);\r
+\r
+    //\r
+    // Config PAD_VAL only for GPIO (Non-Native) Pin\r
+    //\r
+    if(Native != Gpio_Conf_Data[index].usage)\r
+    {\r
+      pad_val.dw &= ~0x6; // Clear bits 1:2\r
+      pad_val.dw |= (Gpio_Conf_Data[index].usage & 0x6);  // Set bits 1:2 according to PadVal\r
+\r
+        //\r
+        // set GPO default value\r
+        //\r
+        if(Gpio_Conf_Data[index].usage == GPO && Gpio_Conf_Data[index].gpod4 != NA)\r
+        {\r
+        pad_val.r.pad_val = Gpio_Conf_Data[index].gpod4;\r
+        }\r
+    }\r
+\r
+\r
+    DEBUG ((EFI_D_INFO, "Set PAD_VAL = 0x%08x, ", pad_val.dw));\r
+\r
+    MmioWrite32(mmio_padval, pad_val.dw);\r
+\r
+    //\r
+    // Step 2: CONF0 Programming\r
+    // Read GPIO default CONF0 value, which is assumed to be default value after reset.\r
+    //\r
+    conf0_val.dw = GPIORead32(mmio_conf0);\r
+\r
+    //\r
+    // Set Function #\r
+    //\r
+    conf0_val.r.Func_Pin_Mux = Gpio_Conf_Data[index].func;\r
+\r
+    if(GPO == Gpio_Conf_Data[index].usage)\r
+    {\r
+      //\r
+      // If used as GPO, then internal pull need to be disabled.\r
+      //\r
+      conf0_val.r.Pull_assign = 0;  // Non-pull\r
+    }\r
+    else\r
+    {\r
+      //\r
+      // Set PullUp / PullDown\r
+      //\r
+      if(P_20K_H == Gpio_Conf_Data[index].pull)\r
+      {\r
+        conf0_val.r.Pull_assign = 0x1;  // PullUp\r
+        conf0_val.r.Pull_strength = 0x2;// 20K\r
+      }\r
+      else if(P_20K_L == Gpio_Conf_Data[index].pull)\r
+      {\r
+        conf0_val.r.Pull_assign = 0x2;  // PullDown\r
+        conf0_val.r.Pull_strength = 0x2;// 20K\r
+      }\r
+      else if(P_10K_H == Gpio_Conf_Data[index].pull)\r
+      {\r
+        conf0_val.r.Pull_assign = 0x1;         // PullUp\r
+        conf0_val.r.Pull_strength = 0x1;// 10K\r
+      }\r
+      else if(P_10K_L == Gpio_Conf_Data[index].pull)\r
+      {\r
+        conf0_val.r.Pull_assign = 0x2;         // PullDown\r
+        conf0_val.r.Pull_strength = 0x1;// 10K\r
+      }\r
+      else if(P_2K_H == Gpio_Conf_Data[index].pull)\r
+      {\r
+        conf0_val.r.Pull_assign = 0x1;  // PullUp\r
+        conf0_val.r.Pull_strength = 0x0;// 2K\r
+      }\r
+      else if(P_2K_L == Gpio_Conf_Data[index].pull)\r
+      {\r
+        conf0_val.r.Pull_assign = 0x2;  // PullDown\r
+        conf0_val.r.Pull_strength = 0x0;// 2K\r
+      }\r
+      else if(P_NONE == Gpio_Conf_Data[index].pull)\r
+      {\r
+        conf0_val.r.Pull_assign = 0;   // Non-pull\r
+      }\r
+      else\r
+      {\r
+        ASSERT(FALSE);  // Invalid value\r
+      }\r
+    }\r
+\r
+\r
+    //\r
+    // Set INT Trigger Type\r
+    //\r
+    conf0_val.dw &= ~0x0f000000;  // Clear bits 27:24\r
+\r
+    //\r
+    // Set INT Trigger Type\r
+    //\r
+    if(TRIG_ == Gpio_Conf_Data[index].int_type)\r
+    {\r
+      //\r
+      // Interrupt not capable, clear bits 27:24\r
+      //\r
+    }\r
+    else\r
+    {\r
+      conf0_val.dw |= (Gpio_Conf_Data[index].int_type & 0x0f)<<24;\r
+    }\r
+\r
+    DEBUG ((EFI_D_INFO, "Set CONF0 = 0x%08x\n", conf0_val.dw));\r
+\r
+    //\r
+    // Write back the targeted GPIO config value according to platform (board) GPIO setting.\r
+    //\r
+    MmioWrite32 (mmio_conf0, conf0_val.dw);\r
+  }\r
+\r
+  //\r
+  // A0 BIOS Spec doesn't mention it although X0 does. comment out now.\r
+  // GPIO SCORE write 0x01001002 to IOBASE + 0x0900\r
+  //\r
+}\r
+\r
+/**\r
+  Returns the Correct GPIO table for Mobile/Desktop respectively.\r
+  Before call it, make sure PlatformInfoHob->BoardId&PlatformFlavor is get correctly.\r
+\r
+  @param PeiServices               General purpose services available to every PEIM.\r
+  @param PlatformInfoHob           PlatformInfoHob pointer with PlatformFlavor specified.\r
+  @param BoardId                   BoardId ID as determined through the EC.\r
+\r
+  @retval EFI_SUCCESS              The function completed successfully.\r
+  @retval EFI_DEVICE_ERROR         KSC fails to respond.\r
+\r
+**/\r
+EFI_STATUS\r
+MultiPlatformGpioProgram (\r
+  IN CONST EFI_PEI_SERVICES     **PeiServices,\r
+  IN EFI_PLATFORM_INFO_HOB      *PlatformInfoHob\r
+  )\r
+{\r
+#if !_SIMIC_\r
+  CFIO_INIT_STRUCT*           PlatformCfioDataPtr;\r
+\r
+  PlatformCfioDataPtr = (CFIO_INIT_STRUCT *) (UINTN) PlatformInfoHob->PlatformCfioData;\r
+  DEBUG ((EFI_D_INFO, "MultiPlatformGpioProgram()...\n"));\r
+\r
+  //\r
+  //  SCORE GPIO WELL -- IO base registers\r
+  //\r
+\r
+  //\r
+  // GPIO_USE_SEL Register -> 1 = GPIO 0 = Native\r
+  //\r
+  IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SC_USE_SEL, PlatformCfioDataPtr->Use_Sel_SC0);\r
+\r
+  //\r
+  // Set GP_LVL Register\r
+  //\r
+  IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SC_LVL , PlatformCfioDataPtr->GP_Lvl_SC0);\r
+\r
+  //\r
+  // GP_IO_SEL Register -> 1 = Input 0 = Output.  If Native Mode don't care\r
+  //\r
+  IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SC_IO_SEL, PlatformCfioDataPtr->Io_Sel_SC0);\r
+\r
+  //\r
+  // GPIO Triger Positive Edge Enable Register\r
+  //\r
+  IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SC_TPE, PlatformCfioDataPtr->TPE_SC0);\r
+\r
+  //\r
+  //  GPIO Trigger Negative Edge Enable Register\r
+  //\r
+  IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SC_TNE, PlatformCfioDataPtr->TNE_SC0);\r
+\r
+  //\r
+  //  GPIO Trigger Status\r
+  //\r
+  IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SC_TS, PlatformCfioDataPtr->TS_SC0);\r
+\r
+  //\r
+  // GPIO_USE_SEL2 Register -> 1 = GPIO 0 = Native\r
+  //\r
+  IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SC_USE_SEL2, PlatformCfioDataPtr->Use_Sel_SC1);\r
+\r
+  //\r
+  // Set GP_LVL2 Register\r
+  //\r
+  IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SC_LVL2, PlatformCfioDataPtr->GP_Lvl_SC1);\r
+\r
+  //\r
+  // GP_IO_SEL2 Register -> 1 = Input 0 = Output.  If Native Mode don't care\r
+  //\r
+  IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SC_IO_SEL2, PlatformCfioDataPtr->Io_Sel_SC1);\r
+\r
+  //\r
+  // GPIO_USE_SEL3 Register -> 1 = GPIO 0 = Native\r
+  //\r
+  IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SC_USE_SEL3, PlatformCfioDataPtr->Use_Sel_SC2);\r
+\r
+  //\r
+  // Set GP_LVL3 Register\r
+  //\r
+  IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SC_LVL3, PlatformCfioDataPtr->GP_Lvl_SC2);\r
+\r
+  //\r
+  // GP_IO_SEL3 Register -> 1 = Input 0 = Output if Native Mode don't care\r
+  //\r
+  IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SC_IO_SEL3, PlatformCfioDataPtr->Io_Sel_SC2);\r
+\r
+  //\r
+  //  SUS GPIO WELL -- IO base registers\r
+  //\r
+\r
+  //\r
+  // GPIO_USE_SEL Register -> 1 = GPIO 0 = Native\r
+  //\r
+  IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SUS_USE_SEL, PlatformCfioDataPtr->Use_Sel_SS);\r
+\r
+  //\r
+  // Set GP_LVL Register\r
+  //\r
+  IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SUS_LVL , PlatformCfioDataPtr->GP_Lvl_SS);\r
+\r
+  //\r
+  // GP_IO_SEL Register -> 1 = Input 0 = Output.  If Native Mode don't care.\r
+  //\r
+  IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SUS_IO_SEL, PlatformCfioDataPtr->Io_Sel_SS);\r
+\r
+  //\r
+  // GPIO Triger Positive Edge Enable Register.\r
+  //\r
+  IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SUS_TPE, PlatformCfioDataPtr->TPE_SS);\r
+\r
+  //\r
+  //  GPIO Trigger Negative Edge Enable Register.\r
+  //\r
+  IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SUS_TNE, PlatformCfioDataPtr->TNE_SS);\r
+\r
+  //\r
+  //  GPIO Trigger Status.\r
+  //\r
+  IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SUS_TS, PlatformCfioDataPtr->TS_SS);\r
+\r
+  //\r
+  //  GPIO Wake Enable.\r
+  //\r
+  IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SUS_WAKE_EN, PlatformCfioDataPtr->WE_SS);\r
+\r
+  //\r
+  // Config SC/NC/SUS GPIO Pins\r
+  //\r
+  switch (PlatformInfoHob->BoardId) {\r
+    case BOARD_ID_MINNOW2:\r
+      DEBUG ((EFI_D_INFO, "Start to config Minnow2 GPIO pins\n"));\r
+      InternalGpioConfig(GPIO_SCORE_OFFSET, sizeof(mMinnow2_GpioInitData_SC)/sizeof(mMinnow2_GpioInitData_SC[0]),   (GPIO_CONF_PAD_INIT *) (UINTN) PlatformInfoHob->PlatformGpioData_SC);\r
+      InternalGpioConfig(GPIO_NCORE_OFFSET, sizeof(mMinnow2_GpioInitData_NC)/sizeof(mMinnow2_GpioInitData_NC[0]),   (GPIO_CONF_PAD_INIT *) (UINTN) PlatformInfoHob->PlatformGpioData_NC);\r
+      InternalGpioConfig(GPIO_SSUS_OFFSET,  sizeof(mMinnow2_GpioInitData_SUS)/sizeof(mMinnow2_GpioInitData_SUS[0]), (GPIO_CONF_PAD_INIT *) (UINTN) PlatformInfoHob->PlatformGpioData_SUS);\r
+      break;\r
+    default:\r
+\r
+      break;\r
+  }\r
+\r
+   //\r
+   // configure the CFIO Pnp settings\r
+   //\r
+   if (PlatformInfoHob->CfioEnabled) {\r
+     if (PlatformInfoHob->BoardId == BOARD_ID_MINNOW2){\r
+       InternalGpioConfig(GPIO_SCORE_OFFSET, sizeof(mNB_BB_FAB3_GpioInitData_SC_TRI)/sizeof(mNB_BB_FAB3_GpioInitData_SC_TRI[0]), (GPIO_CONF_PAD_INIT *) (UINTN)PlatformInfoHob->PlatformGpioData_SC_TRI);\r
+     }\r
+   }\r
+#else\r
+   DEBUG ((EFI_D_INFO, "Skip MultiPlatformGpioProgram()...for SIMICS or HYB model\n"));\r
+#endif\r
+  return EFI_SUCCESS;\r
+}\r
+\r

diff --git a/Vlv2TbltDevicePkg/Library/MultiPlatformLib/BoardGpios/BoardGpios.h b/Vlv2TbltDevicePkg/Library/MultiPlatformLib/BoardGpios/BoardGpios.h
new file mode 100644 (file)
index 0000000..e7d54d1
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Library/MultiPlatformLib/BoardGpios/BoardGpios.h
@@ -0,0 +1,329 @@
+/**@file\r
+  Gpio setting for multiplatform.\r
+\r
+  This file includes package header files, library classes.\r
+\r
+  Copyright (c) 2013 - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+**/\r
+\r
+#ifndef _BOARDGPIOS_H_\r
+#define _BOARDGPIOS_H_\r
+\r
+#include <PiPei.h>\r
+#include "PchAccess.h"\r
+#include "PlatformBaseAddresses.h"\r
+#include <../MultiPlatformLib.h>\r
+#include <Library/IoLib.h>\r
+#include <Library/HobLib.h>\r
+#include <Guid/PlatformInfo.h>\r
+#include <Ppi/Smbus.h>\r
+#include <Ppi/ReadOnlyVariable2.h>\r
+#include <Guid/SetupVariable.h>\r
+\r
+\r
+GPIO_CONF_PAD_INIT mNB_BB_FAB3_GpioInitData_SC_TRI[] =\r
+{\r
+//              Pad Name          GPIO Number     Used As   GPO Default  Function#     INT Capable   Interrupt Type   PULL H/L    MMIO Offset\r
+GPIO_INIT_ITEM("LPC_CLKOUT1       GPIOC_48 "     ,TRISTS   ,NA           ,F0           ,             ,                ,NONE       ,0x41),\r
+GPIO_INIT_ITEM("PLT_CLK0          GPIOC_96 "     ,TRISTS   ,NA           ,F0           ,             ,                ,NONE       ,0x6a),\r
+GPIO_INIT_ITEM("PLT_CLK3          GPIOC_99 "     ,TRISTS   ,NA           ,F0           ,             ,                ,NONE       ,0x68),\r
+};\r
+\r
+//\r
+// Minnow2\r
+//\r
+#define MINNOW2_GPIO_USE_SEL_VAL_0_31        0x00000000\r
+#define MINNOW2_GPIO_USE_SEL_VAL_32_63       0x00000000\r
+#define MINNOW2_GPIO_USE_SEL_VAL_64_70       0x00000000\r
+#define MINNOW2_GPIO_USE_SEL_VAL_64_70       0x00000000\r
+#define MINNOW2_GPIO_USE_SEL_VAL_SUS         0x00000000\r
+#define MINNOW2_GPIO_USE_SEL_VAL_SUS2        0x00000007\r
+  \r
+\r
+#define MINNOW2_GPIO_IO_SEL_VAL_0_31         0x00000000\r
+#define MINNOW2_GPIO_IO_SEL_VAL_32_63        0x00000000\r
+#define MINNOW2_GPIO_IO_SEL_VAL_64_70        0x00000000\r
+#define MINNOW2_GPIO_IO_SEL_VAL_SUS          0x00000000\r
+#define MINNOW2_GPIO_IO_SEL_VAL_SUS2         0x00000007   \r
+\r
+\r
+#define MINNOW2_GPIO_LVL_VAL_0_31            0x00000000\r
+#define MINNOW2_GPIO_LVL_VAL_32_63           0x00000000\r
+#define MINNOW2_GPIO_LVL_VAL_64_70           0x00000000\r
+#define MINNOW2_GPIO_LVL_VAL_SUS             0x00000000\r
+#define MINNOW2_GPIO_LVL_VAL_SUS2            0x00000007   \r
+\r
+#define MINNOW2_GPIO_TPE_VAL_0_31            0x00000000\r
+#define MINNOW2_GPIO_TPE_VAL_SUS             0x00000000\r
+#define MINNOW2_GPIO_TPE_VAL_SUS2            0x00000007   \r
+\r
+#define MINNOW2_GPIO_TNE_VAL_0_31            0x00000000\r
+#define MINNOW2_GPIO_TNE_VAL_SUS             0x00000000\r
+#define MINNOW2_GPIO_TNE_VAL_SUS2            0x00000007   \r
+\r
+#define MINNOW2_GPIO_TS_VAL_0_31             0x00000000\r
+#define MINNOW2_GPIO_TS_VAL_SUS              0x00000000\r
+#define MINNOW2_GPIO_TS_VAL_SUS2             0x00000007   \r
+\r
+static CFIO_INIT_STRUCT mMinnow2CfioInitData =\r
+{\r
+        MINNOW2_GPIO_USE_SEL_VAL_0_31,\r
+        MINNOW2_GPIO_USE_SEL_VAL_32_63,\r
+        MINNOW2_GPIO_USE_SEL_VAL_64_70,\r
+        MINNOW2_GPIO_USE_SEL_VAL_SUS,\r
+\r
+        MINNOW2_GPIO_IO_SEL_VAL_0_31,\r
+        MINNOW2_GPIO_IO_SEL_VAL_32_63,\r
+        MINNOW2_GPIO_IO_SEL_VAL_64_70,\r
+        MINNOW2_GPIO_IO_SEL_VAL_SUS,\r
+\r
+        MINNOW2_GPIO_LVL_VAL_0_31,\r
+        MINNOW2_GPIO_LVL_VAL_32_63,\r
+        MINNOW2_GPIO_LVL_VAL_64_70,\r
+        MINNOW2_GPIO_LVL_VAL_SUS,\r
+\r
+        MINNOW2_GPIO_TPE_VAL_0_31,\r
+        MINNOW2_GPIO_TPE_VAL_SUS,\r
+        MINNOW2_GPIO_TNE_VAL_0_31,\r
+        MINNOW2_GPIO_TNE_VAL_SUS,\r
+\r
+        MINNOW2_GPIO_TS_VAL_0_31,\r
+        MINNOW2_GPIO_TS_VAL_SUS\r
+};\r
+\r
+static CFIO_INIT_STRUCT mMinnow2CfioInitData2 =\r
+{\r
+        MINNOW2_GPIO_USE_SEL_VAL_0_31,\r
+        MINNOW2_GPIO_USE_SEL_VAL_32_63,\r
+        MINNOW2_GPIO_USE_SEL_VAL_64_70,\r
+        MINNOW2_GPIO_USE_SEL_VAL_SUS2,\r
+\r
+        MINNOW2_GPIO_IO_SEL_VAL_0_31,\r
+        MINNOW2_GPIO_IO_SEL_VAL_32_63,\r
+        MINNOW2_GPIO_IO_SEL_VAL_64_70,\r
+        MINNOW2_GPIO_IO_SEL_VAL_SUS2,\r
+\r
+        MINNOW2_GPIO_LVL_VAL_0_31,\r
+        MINNOW2_GPIO_LVL_VAL_32_63,\r
+        MINNOW2_GPIO_LVL_VAL_64_70,\r
+        MINNOW2_GPIO_LVL_VAL_SUS2,\r
+\r
+        MINNOW2_GPIO_TPE_VAL_0_31,\r
+        MINNOW2_GPIO_TPE_VAL_SUS2,             \r
+        MINNOW2_GPIO_TNE_VAL_0_31,\r
+        MINNOW2_GPIO_TNE_VAL_SUS2,\r
+\r
+        MINNOW2_GPIO_TS_VAL_0_31,\r
+        MINNOW2_GPIO_TS_VAL_SUS2\r
+};\r
+\r
+static GPIO_CONF_PAD_INIT mMinnow2_GpioInitData_NC[] =\r
+{\r
+//              Pad Name          GPIO Number     Used As   GPO Default   Function#     INT Capable   Interrupt Type   PULL H/L    MMIO Offset\r
+GPIO_INIT_ITEM("HV_DDI0_HPD       GPIONC_0 "     ,Native   ,NA           ,F2           ,             ,                ,NONE       ,0x13),\r
+GPIO_INIT_ITEM("HV_DDI0_DDC_SDA   GPIONC_1 "     ,Native   ,NA           ,F2           ,             ,                ,NONE       ,0x12),\r
+GPIO_INIT_ITEM("HV_DDI0_DDC_SCL   GPIONC_2 "     ,Native   ,NA           ,F2           ,             ,                ,NONE       ,0x11),\r
+GPIO_INIT_ITEM("PANEL0_VDDEN      GPIONC_3 "     ,GPIO     ,NA           ,F0           ,             ,                ,NONE       ,0x14),\r
+GPIO_INIT_ITEM("PANEL0_BKLTEN     GPIONC_4 "     ,GPIO     ,NA           ,F0           ,             ,                ,NONE       ,0x15),\r
+GPIO_INIT_ITEM("PANEL0_BKLTCTL    GPIONC_5 "     ,GPIO     ,NA           ,F0           ,             ,                ,NONE       ,0x16),\r
+GPIO_INIT_ITEM("HV_DDI1_HPD       GPIONC_6 "     ,GPI      ,NA           ,F0           ,             ,                ,20K_L      ,0x18),\r
+GPIO_INIT_ITEM("HV_DDI1_DDC_SDA   GPIONC_7 "     ,Native   ,NA           ,F2           ,             ,                ,20K_L      ,0x19),\r
+GPIO_INIT_ITEM("HV_DDI1_DDC_SCL   GPIONC_8 "     ,GPI      ,NA           ,F0           ,             ,                ,20K_L      ,0x17),\r
+GPIO_INIT_ITEM("PANEL1_VDDEN      GPIONC_9 "     ,GPIO     ,NA           ,F0           ,             ,                ,NONE       ,0x10),\r
+GPIO_INIT_ITEM("PANEL1_BKLTEN     GPIONC_10"     ,GPIO     ,NA           ,F0           ,             ,                ,NONE       ,0x0e),\r
+GPIO_INIT_ITEM("PANEL1_BKLTCTL    GPIONC_11"     ,GPIO     ,NA           ,F0           ,             ,                ,NONE       ,0x0f),\r
+GPIO_INIT_ITEM("GP_INTD_DSI_TE1   GPIONC_12"     ,GPO      ,NA           ,F0           ,             ,                ,NONE       ,0x0c),\r
+GPIO_INIT_ITEM("HV_DDI2_DDC_SDA   GPIONC_13"     ,GPI      ,NA           ,F0           ,             ,                ,10K_L      ,0x1a),\r
+GPIO_INIT_ITEM("HV_DDI2_DDC_SCL   GPIONC_14"     ,GPIO     ,NA           ,F0           ,             ,                ,NONE       ,0x1b),\r
+GPIO_INIT_ITEM("GP_CAMERASB00     GPIONC_15"     ,GPIO     ,NA           ,F0           ,             ,                ,NONE       ,0x01),\r
+GPIO_INIT_ITEM("GP_CAMERASB01     GPIONC_16"     ,GPIO     ,NA           ,F0           ,             ,                ,NONE       ,0x04),\r
+GPIO_INIT_ITEM("GP_CAMERASB02     GPIONC_17"     ,GPIO     ,NA           ,F0           ,             ,                ,NONE       ,0x08),\r
+GPIO_INIT_ITEM("GP_CAMERASB03     GPIONC_18"     ,GPIO     ,NA           ,F0           ,             ,                ,NONE       ,0x0b),\r
+GPIO_INIT_ITEM("GP_CAMERASB04     GPIONC_19"     ,GPIO     ,NA           ,F0           ,             ,                ,NONE       ,0x00),\r
+GPIO_INIT_ITEM("GP_CAMERASB05     GPIONC_20"     ,GPIO     ,NA           ,F0           ,             ,                ,NONE       ,0x03),\r
+GPIO_INIT_ITEM("GP_CAMERASB06     GPIONC_21"     ,GPIO     ,NA           ,F0           ,             ,                ,NONE       ,0x06),\r
+GPIO_INIT_ITEM("GP_CAMERASB07     GPIONC_22"     ,GPIO     ,NA           ,F0           ,             ,                ,NONE       ,0x0a),\r
+GPIO_INIT_ITEM("GP_CAMERASB08     GPIONC_23"     ,GPIO     ,NA           ,F0           ,             ,                ,NONE       ,0x0d),\r
+GPIO_INIT_ITEM("GP_CAMERASB09     GPIONC_24"     ,GPIO     ,NA           ,F0           ,             ,                ,NONE       ,0x02),\r
+GPIO_INIT_ITEM("GP_CAMERASB10     GPIONC_25"     ,GPIO     ,NA           ,F0           ,             ,                ,NONE       ,0x05),\r
+GPIO_INIT_ITEM("GP_CAMERASB11     GPIONC_26"     ,GPIO     ,NA           ,F0           ,             ,                ,NONE       ,0x09),\r
+};\r
+\r
+\r
+static GPIO_CONF_PAD_INIT mMinnow2_GpioInitData_SC[] = {\r
+//              Pad Name          GPIO Number     Used As   GPO Default   Function#     INT Capable   Interrupt Type   PULL H/L    MMIO Offset\r
+GPIO_INIT_ITEM("SATA_GP0          GPIOC_0  "     ,Native   ,NA           ,F1           ,             ,                ,NONE       ,0x55),\r
+GPIO_INIT_ITEM("SATA_GP1          GPIOC_1  "     ,Native   ,NA           ,F1           ,             ,                ,NONE       ,0x59),\r
+GPIO_INIT_ITEM("SATA_LEDN         GPIOC_2  "     ,Native   ,NA           ,F1           ,             ,                ,NONE       ,0x5d),\r
+GPIO_INIT_ITEM("PCIE_CLKREQ0B     GPIOC_3  "     ,Native   ,NA           ,F1           ,             ,                ,10K_H      ,0x60),\r
+GPIO_INIT_ITEM("PCIE_CLKREQ1B     GPIOC_4  "     ,Native   ,NA           ,F1           ,             ,                ,10K_H      ,0x63),\r
+GPIO_INIT_ITEM("PCIE_CLKREQ2B     GPIOC_5  "     ,Native   ,NA           ,F1           ,             ,                ,10K_H      ,0x66),\r
+GPIO_INIT_ITEM("PCIE_CLKREQ3B     GPIOC_6  "     ,GPIO     ,NA           ,F0           ,             ,                ,NONE       ,0x62),\r
+GPIO_INIT_ITEM("SDMMC3_WP         GPIOC_7  "     ,Native   ,NA           ,F2           ,             ,                ,NONE       ,0x65),\r
+GPIO_INIT_ITEM("HDA_RSTB          GPIOC_8  "     ,GPIO     ,NA           ,F0           ,             ,                ,NONE       ,0x22),\r
+GPIO_INIT_ITEM("HDA_SYNC          GPIOC_9  "     ,GPIO     ,NA           ,F0           ,             ,                ,NONE       ,0x25),\r
+GPIO_INIT_ITEM("HDA_CLK           GPIOC_10 "     ,GPIO     ,NA           ,F0           ,             ,                ,NONE       ,0x24),\r
+GPIO_INIT_ITEM("HDA_SDO           GPIOC_11 "     ,GPIO     ,NA           ,F0           ,             ,                ,NONE       ,0x26),\r
+GPIO_INIT_ITEM("HDA_SDI0          GPIOC_12 "     ,GPIO     ,NA           ,F0           ,             ,                ,NONE       ,0x27),\r
+GPIO_INIT_ITEM("HDA_SDI1          GPIOC_13 "     ,GPIO     ,NA           ,F0           ,             ,                ,NONE       ,0x23),\r
+GPIO_INIT_ITEM("HDA_DOCKRSTB      GPIOC_14 "     ,GPIO     ,NA           ,F0           ,             ,                ,NONE       ,0x28),\r
+GPIO_INIT_ITEM("HDA_DOCKENB       GPIOC_15 "     ,GPIO     ,NA           ,F0           ,             ,                ,NONE       ,0x54),\r
+GPIO_INIT_ITEM("SDMMC1_CLK        GPIOC_16 "     ,GPIO     ,NA           ,F0           ,             ,                ,NONE       ,0x3e),\r
+GPIO_INIT_ITEM("SDMMC1_D0         GPIOC_17 "     ,GPIO     ,NA           ,F0           ,             ,                ,NONE       ,0x3d),\r
+GPIO_INIT_ITEM("SDMMC1_D1         GPIOC_18 "     ,GPIO     ,NA           ,F0           ,             ,                ,NONE       ,0x40),\r
+GPIO_INIT_ITEM("SDMMC1_D2         GPIOC_19 "     ,GPIO     ,NA           ,F0           ,             ,                ,NONE       ,0x3b),\r
+GPIO_INIT_ITEM("SDMMC1_D3_CD_B    GPIOC_20 "     ,GPIO     ,NA           ,F0           ,             ,                ,NONE       ,0x36),\r
+GPIO_INIT_ITEM("MMC1_D4_SD_WE     GPIOC_21 "     ,GPIO     ,NA           ,F0           ,             ,                ,NONE       ,0x38),\r
+GPIO_INIT_ITEM("MMC1_D5           GPIOC_22 "     ,GPIO     ,NA           ,F0           ,             ,                ,NONE       ,0x3c),\r
+GPIO_INIT_ITEM("MMC1_D6           GPIOC_23 "     ,GPIO     ,NA           ,F0           ,             ,                ,NONE       ,0x37),\r
+GPIO_INIT_ITEM("MMC1_D7           GPIOC_24 "     ,GPIO     ,NA           ,F0           ,             ,                ,NONE       ,0x3f),\r
+GPIO_INIT_ITEM("SDMMC1_CMD        GPIOC_25 "     ,GPIO     ,NA           ,F0           ,             ,                ,NONE       ,0x39),\r
+GPIO_INIT_ITEM("MMC1_RESET_B      GPIOC_26 "     ,GPIO     ,NA           ,F0           ,             ,                ,NONE       ,0x33),\r
+GPIO_INIT_ITEM("SDMMC2_CLK        GPIOC_27 "     ,GPIO     ,NA           ,F0           ,             ,                ,NONE       ,0x32),\r
+GPIO_INIT_ITEM("SDMMC2_D0         GPIOC_28 "     ,GPIO     ,NA           ,F0           ,             ,                ,NONE       ,0x35),\r
+GPIO_INIT_ITEM("SDMMC2_D1         GPIOC_29 "     ,GPIO     ,NA           ,F0           ,             ,                ,NONE       ,0x2f),\r
+GPIO_INIT_ITEM("SDMMC2_D2         GPIOC_30 "     ,GPIO     ,NA           ,F0           ,             ,                ,NONE       ,0x34),\r
+GPIO_INIT_ITEM("SDMMC2_D3_CD_B    GPIOC_31 "     ,GPIO     ,NA           ,F0           ,             ,                ,NONE       ,0x31),\r
+GPIO_INIT_ITEM("SDMMC2_CMD        GPIOC_32 "     ,GPIO     ,NA           ,F0           ,             ,                ,NONE       ,0x30),\r
+//\r
+//Just for test, We make the setting that all is same with Bayleybay.\r
+//\r
+GPIO_INIT_ITEM("SDMMC3_CLK        GPIOC_33 "     ,Native   ,NA           ,F1           ,             ,                ,NONE      ,0x2b),\r
+GPIO_INIT_ITEM("SDMMC3_D0         GPIOC_34 "     ,Native   ,NA           ,F1           ,             ,                ,NONE      ,0x2e),\r
+GPIO_INIT_ITEM("SDMMC3_D1         GPIOC_35 "     ,Native   ,NA           ,F1           ,YES          ,                ,NONE      ,0x29),\r
+GPIO_INIT_ITEM("SDMMC3_D2         GPIOC_36 "     ,Native   ,NA           ,F1           ,             ,                ,NONE      ,0x2d),\r
+GPIO_INIT_ITEM("SDMMC3_D3         GPIOC_37 "     ,Native   ,NA           ,F1           ,             ,                ,NONE      ,0x2a),\r
+GPIO_INIT_ITEM("SDMMC3_CD_B       GPIOC_38 "     ,Native   ,NA           ,F1           ,YES          ,Edge_Both       ,NONE      ,0x3a),\r
+GPIO_INIT_ITEM("SDMMC3_CMD        GPIOC_39 "     ,Native   ,NA           ,F1           ,             ,                ,NONE      ,0x2c),\r
+GPIO_INIT_ITEM("SDMMC3_1P8_EN     GPIOC_40 "     ,Native   ,NA           ,F1           ,             ,                ,NONE      ,0x5f),\r
+GPIO_INIT_ITEM("SDMMC3_PWR_EN_B   GPIOC_41 "     ,Native   ,NA           ,F1           ,             ,                ,NONE      ,0x69),\r
+GPIO_INIT_ITEM("LPC_AD0           GPIOC_42 "     ,GPIO     ,NA           ,F0           ,             ,                ,NONE       ,0x46),\r
+GPIO_INIT_ITEM("LPC_AD1           GPIOC_43 "     ,GPIO     ,NA           ,F0           ,             ,                ,NONE       ,0x44),\r
+GPIO_INIT_ITEM("LPC_AD2           GPIOC_44 "     ,GPIO     ,NA           ,F0           ,             ,                ,NONE       ,0x43),\r
+GPIO_INIT_ITEM("LPC_AD3           GPIOC_45 "     ,GPIO     ,NA           ,F0           ,             ,                ,NONE       ,0x42),\r
+GPIO_INIT_ITEM("LPC_FRAMEB        GPIOC_46 "     ,GPIO     ,NA           ,F0           ,             ,                ,NONE       ,0x45),\r
+GPIO_INIT_ITEM("LPC_CLKOUT0       GPIOC_47 "     ,GPIO     ,NA           ,F0           ,             ,                ,NONE       ,0x47),\r
+GPIO_INIT_ITEM("LPC_CLKOUT1       GPIOC_48 "     ,GPIO     ,NA           ,F0           ,             ,                ,NONE       ,0x41),\r
+GPIO_INIT_ITEM("LPC_CLKRUNB       GPIOC_49 "     ,GPIO     ,NA           ,F0           ,             ,                ,NONE       ,0x48),\r
+GPIO_INIT_ITEM("ILB_SERIRQ        GPIOC_50 "     ,GPIO     ,NA           ,F0           ,             ,                ,NONE       ,0x56),\r
+GPIO_INIT_ITEM("SMB_DATA          GPIOC_51 "     ,Native   ,NA           ,F1           ,             ,                ,NONE       ,0x5a),\r
+GPIO_INIT_ITEM("SMB_CLK           GPIOC_52 "     ,Native   ,NA           ,F1           ,             ,                ,NONE       ,0x58),\r
+GPIO_INIT_ITEM("SMB_ALERTB        GPIOC_53 "     ,Native   ,NA           ,F1           ,             ,                ,10K_H      ,0x5c),\r
+GPIO_INIT_ITEM("SPKR              GPIOC_54 "     ,GPI     ,NA           ,F0           ,             ,                ,20K_H      ,0x67),\r
+GPIO_INIT_ITEM("MHSI_ACDATA       GPIOC_55 "     ,GPIO     ,NA           ,F0           ,             ,                ,NONE       ,0x4d),\r
+GPIO_INIT_ITEM("MHSI_ACFLAG       GPIOC_56 "     ,GPI      ,NA           ,F0           ,             ,                ,20K_H      ,0x4f),\r
+GPIO_INIT_ITEM("MHSI_ACWAKE       GPIOC_58 "     ,GPIO     ,NA           ,F0           ,             ,                ,NONE       ,0x4e),\r
+GPIO_INIT_ITEM("MHSI_CADATA       GPIOC_59 "     ,GPIO     ,NA           ,F0           ,             ,                ,NONE       ,0x51),\r
+GPIO_INIT_ITEM("MHSI_CAFLAG       GPIOC_60 "     ,GPO      ,HI           ,F0           ,             ,                ,20K_H      ,0x50),\r
+GPIO_INIT_ITEM("GP_SSP_2_CLK      GPIOC_62 "     ,GPI     ,NA           ,F0           ,             ,                ,20K_H      ,0x0d),\r
+GPIO_INIT_ITEM("GP_SSP_2_FS       GPIOC_63 "     ,GPI     ,NA           ,F0           ,             ,                ,20K_H      ,0x0c),\r
+GPIO_INIT_ITEM("GP_SSP_2_RXD      GPIOC_64 "     ,GPI       ,NA           ,F0           ,             ,              ,20K_H      ,0x0f),\r
+GPIO_INIT_ITEM("GP_SSP_2_TXD      GPIOC_65 "     ,GPI     ,NA           ,F0           ,             ,                ,20K_H      ,0x0e),\r
+GPIO_INIT_ITEM("SPI1_CS0_B        GPIOC_66 "     ,Native   ,NA           ,F1           ,             ,                ,20K_H      ,0x11),\r
+GPIO_INIT_ITEM("SPI1_MISO         GPIOC_67 "     ,Native   ,NA           ,F1           ,             ,                ,20K_H      ,0x12),\r
+GPIO_INIT_ITEM("SPI1_MOSI         GPIOC_68 "     ,Native   ,NA           ,F1           ,             ,                ,20K_H      ,0x13),\r
+GPIO_INIT_ITEM("SPI1_CLK          GPIOC_69 "     ,Native   ,NA           ,F1           ,             ,                ,20K_H      ,0x10),\r
+GPIO_INIT_ITEM("UART1_RXD         GPIOC_70 "     ,Native   ,NA           ,F1           ,             ,                ,20K_H      ,0x02),\r
+GPIO_INIT_ITEM("UART1_TXD         GPIOC_71 "     ,Native   ,NA           ,F1           ,             ,                ,20K_H      ,0x01),\r
+GPIO_INIT_ITEM("UART1_RTS_B       GPIOC_72 "     ,GPI     ,NA           ,F0           ,             ,                ,20K_H      ,0x00),\r
+GPIO_INIT_ITEM("UART1_CTS_B       GPIOC_73 "     ,GPI     ,NA           ,F0           ,             ,                ,20K_H      ,0x04),\r
+GPIO_INIT_ITEM("UART2_RXD         GPIOC_74 "     ,Native   ,NA           ,F1           ,             ,                ,20K_H      ,0x06),\r
+GPIO_INIT_ITEM("UART2_TXD         GPIOC_75 "     ,Native   ,NA           ,F1           ,             ,                ,20K_H      ,0x07),\r
+GPIO_INIT_ITEM("UART2_RTS_B       GPIOC_76 "     ,GPIO     ,NA           ,F0           ,             ,                ,NONE       ,0x09),\r
+GPIO_INIT_ITEM("UART2_CTS_B       GPIOC_77 "     ,Native   ,NA           ,F1           ,             ,                ,20K_H      ,0x08),\r
+GPIO_INIT_ITEM("I2C0_SDA          GPIOC_78 "     ,GPIO     ,NA           ,F0           ,             ,                ,NONE       ,0x21),\r
+GPIO_INIT_ITEM("I2C0_SCL          GPIOC_79 "     ,GPIO     ,NA           ,F0           ,             ,                ,NONE       ,0x20),\r
+GPIO_INIT_ITEM("I2C1_SDA          GPIOC_80 "     ,Native   ,NA           ,F1           ,             ,                ,NONE       ,0x1f),\r
+GPIO_INIT_ITEM("I2C1_SCL          GPIOC_81 "     ,Native   ,NA           ,F1           ,             ,                ,NONE       ,0x1e),\r
+GPIO_INIT_ITEM("I2C2_SDA          GPIOC_82 "     ,GPIO     ,NA           ,F0           ,             ,                ,NONE       ,0x1d),\r
+GPIO_INIT_ITEM("I2C2_SCL          GPIOC_83 "     ,GPIO     ,NA           ,F0           ,             ,                ,NONE       ,0x1b),\r
+GPIO_INIT_ITEM("I2C3_SDA          GPIOC_84 "     ,GPIO     ,NA           ,F0           ,             ,                ,NONE       ,0x19),\r
+GPIO_INIT_ITEM("I2C3_SCL          GPIOC_85 "     ,GPIO     ,NA           ,F0           ,             ,                ,NONE       ,0x1c),\r
+GPIO_INIT_ITEM("I2C4_SDA          GPIOC_86 "     ,Native   ,NA           ,F1           ,             ,                ,20K_H      ,0x1a),\r
+GPIO_INIT_ITEM("I2C4_SCL          GPIOC_87 "     ,GPIO     ,NA           ,F0           ,             ,                ,NONE       ,0x17),\r
+GPIO_INIT_ITEM("I2C5_SDA          GPIOC_88 "     ,Native   ,NA           ,F1           ,             ,                ,20K_H      ,0x15),\r
+GPIO_INIT_ITEM("I2C5_SCL          GPIOC_89 "     ,Native   ,NA           ,F1           ,             ,                ,20K_H      ,0x14),\r
+GPIO_INIT_ITEM("I2C6_SDA          GPIOC_90 "     ,Native   ,NA           ,F1           ,             ,                ,20K_H      ,0x18),\r
+GPIO_INIT_ITEM("I2C6_SCL          GPIOC_91 "     ,Native   ,NA           ,F1           ,             ,                ,20K_H      ,0x16),\r
+GPIO_INIT_ITEM("I2C_NFC_SDA       GPIOC_92 "     ,GPIO     ,NA           ,F1           ,             ,                ,NONE       ,0x05),\r
+GPIO_INIT_ITEM("I2C_NFC_SCL       GPIOC_93 "     ,GPO      ,LO           ,F1           ,             ,                ,NONE       ,0x03),\r
+GPIO_INIT_ITEM("PWM0              GPIOC_94 "     ,Native   ,NA           ,F1           ,             ,                ,20K_L      ,0x0a),\r
+GPIO_INIT_ITEM("PWM1              GPIOC_95 "     ,Native   ,NA           ,F1           ,             ,                ,20K_L      ,0x0b),\r
+GPIO_INIT_ITEM("PLT_CLK0          GPIOC_96 "     ,GPIO     ,NA           ,F0           ,             ,                ,NONE       ,0x6a),\r
+GPIO_INIT_ITEM("PLT_CLK1          GPIOC_97 "     ,GPIO     ,NA           ,F0           ,             ,                ,NONE       ,0x57),\r
+GPIO_INIT_ITEM("PLT_CLK2          GPIOC_98 "     ,GPIO     ,NA           ,F0           ,             ,                ,NONE       ,0x5b),\r
+GPIO_INIT_ITEM("PLT_CLK3          GPIOC_99 "     ,GPIO     ,NA           ,F0           ,             ,                ,NONE       ,0x68),\r
+GPIO_INIT_ITEM("PLT_CLK4          GPIOC_100"     ,GPIO     ,NA           ,F0           ,             ,                ,NONE       ,0x61),\r
+GPIO_INIT_ITEM("PLT_CLK5          GPIOC_101"     ,GPIO     ,NA           ,F0           ,             ,                ,NONE       ,0x64),\r
+};\r
+\r
+static GPIO_CONF_PAD_INIT mMinnow2_GpioInitData_SUS[] = {\r
+//              Pad Name          GPIO Number     Used As   GPIO Default  Function#     INT Capable   Interrupt Type   PULL H/L    MMIO Offset\r
+GPIO_INIT_ITEM("GPIO_SUS0         GPIO_SUS0"     ,GPI      ,NA           ,F0           ,             ,                ,20K_H      ,0x1d),\r
+GPIO_INIT_ITEM("GPIO_SUS1         GPIO_SUS1"     ,GPI      ,NA           ,F0           ,             ,                ,20K_H      ,0x21),\r
+GPIO_INIT_ITEM("GPIO_SUS2         GPIO_SUS2"     ,GPI      ,NA           ,F0           ,             ,                ,20K_H      ,0x1e),\r
+GPIO_INIT_ITEM("GPIO_SUS3         GPIO_SUS3"     ,Native   ,NA           ,F6           ,YES          ,Level_Low       ,2K_H       ,0x1f),\r
+GPIO_INIT_ITEM("GPIO_SUS4         GPIO_SUS4"     ,GPIO     ,NA           ,F0           ,             ,                ,NONE       ,0x20),\r
+GPIO_INIT_ITEM("GPIO_SUS5         GPIO_SUS5"     ,GPI      ,NA           ,F0           ,             ,                ,NONE       ,0x22),\r
+GPIO_INIT_ITEM("GPIO_SUS6         GPIO_SUS6"     ,GPI      ,NA           ,F0           ,             ,                ,NONE       ,0x24),\r
+GPIO_INIT_ITEM("GPIO_SUS7         GPIO_SUS7"     ,GPI      ,NA           ,F0           ,             ,                ,NONE       ,0x23),\r
+GPIO_INIT_ITEM("SEC_GPIO_SUS8     GPIO_SUS8"     ,GPO      ,HI           ,F0           ,             ,                ,20K_H      ,0x26),\r
+GPIO_INIT_ITEM("SEC_GPIO_SUS9     GPIO_SUS9"     ,GPO      ,HI           ,F0           ,             ,                ,20K_H      ,0x25),\r
+GPIO_INIT_ITEM("SEC_GPIO_SUS10    GPIO_SUS10"    ,GPO      ,HI           ,F0           ,             ,                ,NONE       ,0x12),\r
+GPIO_INIT_ITEM("SUSPWRDNACK       GPIOS_11 "     ,Native   ,NA           ,F0           ,             ,                ,10K_H      ,0x07),\r
+GPIO_INIT_ITEM("PMU_SUSCLK        GPIOS_12 "     ,Native   ,NA           ,F0           ,             ,                ,NONE       ,0x0b),\r
+GPIO_INIT_ITEM("PMU_SLP_S0IX_B    GPIOS_13 "     ,Native   ,NA           ,F0           ,             ,                ,NONE       ,0x14),\r
+GPIO_INIT_ITEM("PMU_SLP_LAN_B     GPIOS_14 "     ,GPO      ,LO           ,F1           ,             ,                ,10K_H      ,0x11),\r
+GPIO_INIT_ITEM("PMU_WAKE_B        GPIOS_15 "     ,Native   ,NA           ,F0           ,             ,                ,20K_H      ,0x01),\r
+GPIO_INIT_ITEM("PMU_PWRBTN_B      GPIOS_16 "     ,Native   ,NA           ,F0           ,             ,                ,20K_H      ,0x08),\r
+GPIO_INIT_ITEM("PMU_WAKE_LAN_B    GPIOS_17 "     ,GPIO     ,NA           ,F1           ,             ,                ,NONE       ,0x0a),\r
+GPIO_INIT_ITEM("SUS_STAT_B        GPIOS_18 "     ,GPO      ,NA           ,F1           ,             ,                ,NONE       ,0x13),\r
+GPIO_INIT_ITEM("USB_OC0_B         GPIOS_19 "     ,Native   ,NA           ,F0           ,             ,                ,10K_H      ,0x0c),\r
+GPIO_INIT_ITEM("USB_OC1_B         GPIOS_20 "     ,Native   ,NA           ,F0           ,             ,                ,10K_H      ,0x00),\r
+GPIO_INIT_ITEM("SPI_CS1_B         GPIOS_21 "     ,Native   ,NA           ,F0           ,             ,                ,NONE       ,0x02),\r
+GPIO_INIT_ITEM("GPIO_DFX0         GPIOS_22 "     ,GPIO     ,NA           ,F0           ,             ,                ,NONE       ,0x17),\r
+GPIO_INIT_ITEM("GPIO_DFX1         GPIOS_23 "     ,GPIO     ,NA           ,F0           ,             ,                ,NONE       ,0x27),\r
+GPIO_INIT_ITEM("GPIO_DFX2         GPIOS_24 "     ,GPIO     ,NA           ,F0           ,             ,                ,NONE       ,0x1c),\r
+GPIO_INIT_ITEM("GPIO_DFX3         GPIOS_25 "     ,GPIO     ,NA           ,F0           ,             ,                ,NONE       ,0x1b),\r
+GPIO_INIT_ITEM("GPIO_DFX4         GPIOS_26 "     ,GPIO     ,NA           ,F0           ,             ,                ,NONE       ,0x16),\r
+GPIO_INIT_ITEM("GPIO_DFX5         GPIOS_27 "     ,GPI      ,NA           ,F0           ,             ,                ,20K_H      ,0x15),\r
+GPIO_INIT_ITEM("GPIO_DFX6         GPIOS_28 "     ,GPI      ,NA           ,F0           ,             ,                ,20K_H      ,0x18),\r
+GPIO_INIT_ITEM("GPIO_DFX7         GPIOS_29 "     ,GPI      ,NA           ,F0           ,             ,                ,20K_H      ,0x19),\r
+GPIO_INIT_ITEM("GPIO_DFX8         GPIOS_30 "     ,GPI      ,NA           ,F0           ,             ,                ,20K_H      ,0x1a),\r
+GPIO_INIT_ITEM("USB_ULPI_0_CLK    GPIOS_31 "     ,GPIO     ,NA           ,F0           ,             ,                ,NONE       ,0x33),\r
+GPIO_INIT_ITEM("USB_ULPI_0_DATA0  GPIOS_32 "     ,GPIO     ,NA           ,F0           ,             ,                ,NONE       ,0x38),\r
+GPIO_INIT_ITEM("USB_ULPI_0_DATA1  GPIOS_33 "     ,GPIO     ,NA           ,F0           ,             ,                ,NONE       ,0x36),\r
+GPIO_INIT_ITEM("USB_ULPI_0_DATA2  GPIOS_34 "     ,GPIO     ,NA           ,F0           ,             ,                ,NONE       ,0x31),\r
+GPIO_INIT_ITEM("USB_ULPI_0_DATA3  GPIOS_35 "     ,GPIO     ,NA           ,F0           ,             ,                ,NONE       ,0x37),\r
+GPIO_INIT_ITEM("USB_ULPI_0_DATA4  GPIOS_36 "     ,GPIO     ,NA           ,F0           ,             ,                ,NONE       ,0x30),\r
+GPIO_INIT_ITEM("USB_ULPI_0_DATA5  GPIOS_37 "     ,GPIO     ,NA           ,F0           ,             ,                ,NONE       ,0x39),\r
+GPIO_INIT_ITEM("USB_ULPI_0_DATA6  GPIOS_38 "     ,GPIO     ,NA           ,F0           ,             ,                ,NONE       ,0x32),\r
+GPIO_INIT_ITEM("USB_ULPI_0_DATA7  GPIOS_39 "     ,GPIO     ,NA           ,F0           ,             ,                ,NONE       ,0x3a),\r
+GPIO_INIT_ITEM("USB_ULPI_0_DIR    GPIOS_40 "     ,GPIO     ,NA           ,F0           ,             ,                ,NONE       ,0x34),\r
+GPIO_INIT_ITEM("USB_ULPI_0_NXT    GPIOS_41 "     ,GPIO     ,NA           ,F0           ,             ,                ,NONE       ,0x35),\r
+GPIO_INIT_ITEM("USB_ULPI_0_STP    GPIOS_42 "     ,GPIO     ,NA           ,F0           ,             ,                ,NONE       ,0x3b),\r
+GPIO_INIT_ITEM("USB_ULPI_0_REFCLK GPIOS_43 "     ,GPIO     ,NA           ,F0           ,             ,                ,NONE       ,0x28),\r
+};\r
+\r
+EFI_STATUS\r
+MultiPlatformGpioTableInit (\r
+  IN CONST EFI_PEI_SERVICES     **PeiServices,\r
+  IN EFI_PLATFORM_INFO_HOB      *PlatformInfoHob\r
+  );\r
+\r
+EFI_STATUS\r
+MultiPlatformGpioProgram (\r
+  IN CONST EFI_PEI_SERVICES     **PeiServices,\r
+  IN EFI_PLATFORM_INFO_HOB      *PlatformInfoHob\r
+  );\r
+\r
+#endif\r

diff --git a/Vlv2TbltDevicePkg/Library/MultiPlatformLib/BoardJumpers/BoardJumpers.c b/Vlv2TbltDevicePkg/Library/MultiPlatformLib/BoardJumpers/BoardJumpers.c
new file mode 100644 (file)
index 0000000..6862c63
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Library/MultiPlatformLib/BoardJumpers/BoardJumpers.c
@@ -0,0 +1,35 @@
+/** @file\r
+  Jumper setting for multiplatform.\r
+\r
+  Copyright (c) 2010 - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+**/\r
+\r
+#include <BoardJumpers.h>\r
+\r
+BOOLEAN\r
+IsRecoveryJumper (\r
+  IN CONST EFI_PEI_SERVICES    **PeiServices,\r
+  IN OUT EFI_PLATFORM_INFO_HOB *PlatformInfoHob\r
+)\r
+{\r
+  return FALSE;\r
+}\r
+\r
+BOOLEAN\r
+IsManufacturingMode(\r
+  IN CONST EFI_PEI_SERVICES    **PeiServices,\r
+  IN OUT EFI_PLATFORM_INFO_HOB *PlatformInfoHob\r
+)\r
+{\r
+  return FALSE;\r
+}\r

diff --git a/Vlv2TbltDevicePkg/Library/MultiPlatformLib/BoardJumpers/BoardJumpers.h b/Vlv2TbltDevicePkg/Library/MultiPlatformLib/BoardJumpers/BoardJumpers.h
new file mode 100644 (file)
index 0000000..e93d55c
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Library/MultiPlatformLib/BoardJumpers/BoardJumpers.h
@@ -0,0 +1,35 @@
+/**@file\r
+  Jumper setting for multiplatform.\r
+\r
+  This file includes package header files, library classes.\r
+\r
+  Copyright (c) 2010 - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+**/\r
+\r
+#ifndef _BOARDJUMPERS_H_\r
+#define _BOARDJUMPERS_H_\r
+\r
+#include <PiPei.h>\r
+#include "PchAccess.h"\r
+#include "PlatformBaseAddresses.h"\r
+\r
+#include <Library/IoLib.h>\r
+#include <Library/DebugLib.h>\r
+#include <Guid/PlatformInfo.h>\r
+\r
+BOOLEAN\r
+IsRecoveryJumper (\r
+  IN CONST EFI_PEI_SERVICES    **PeiServices,\r
+  IN OUT EFI_PLATFORM_INFO_HOB *PlatformInfoHob\r
+);\r
+\r
+#endif\r

diff --git a/Vlv2TbltDevicePkg/Library/MultiPlatformLib/BoardOemIds/BoardOemIds.c b/Vlv2TbltDevicePkg/Library/MultiPlatformLib/BoardOemIds/BoardOemIds.c
new file mode 100644 (file)
index 0000000..7381e00
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Library/MultiPlatformLib/BoardOemIds/BoardOemIds.c
@@ -0,0 +1,47 @@
+/** @file\r
+  ACPI oem ids setting for multiplatform.\r
+\r
+  Copyright (c) 2010 - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+**/\r
+\r
+#include <BoardOemIds.h>\r
+\r
+//\r
+// Global module data\r
+//\r
+EFI_STATUS\r
+InitializeBoardOemId (\r
+  IN CONST EFI_PEI_SERVICES       **PeiServices,\r
+  IN EFI_PLATFORM_INFO_HOB        *PlatformInfoHob\r
+  )\r
+{\r
+    UINT64  OemId;\r
+    UINT64  OemTableId;\r
+\r
+    //\r
+    // Set OEM ID according to Board ID.\r
+    //\r
+    switch (PlatformInfoHob->BoardId) {\r
+\r
+      case BOARD_ID_MINNOW2:\r
+      default:\r
+        OemId = EFI_ACPI_OEM_ID_DEFAULT;\r
+        OemTableId = EFI_ACPI_OEM_TABLE_ID_DEFAULT;\r
+        break;\r
+    }\r
+\r
+    PlatformInfoHob->AcpiOemId = OemId;\r
+    PlatformInfoHob->AcpiOemTableId = OemTableId;\r
+    return  EFI_SUCCESS;\r
+}\r
+\r

diff --git a/Vlv2TbltDevicePkg/Library/MultiPlatformLib/BoardOemIds/BoardOemIds.h b/Vlv2TbltDevicePkg/Library/MultiPlatformLib/BoardOemIds/BoardOemIds.h
new file mode 100644 (file)
index 0000000..d8da53f
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Library/MultiPlatformLib/BoardOemIds/BoardOemIds.h
@@ -0,0 +1,34 @@
+/**@file\r
+  ACPI oem ids setting for multiplatform.\r
+\r
+  This file includes package header files, library classes.\r
+\r
+  Copyright (c) 2010 - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+**/\r
+\r
+#include <Guid/PlatformInfo.h>\r
+#include <Library/BaseMemoryLib.h>\r
+\r
+#define EFI_ACPI_OEM_ID_DEFAULT    SIGNATURE_64('I', 'N', 'T', 'E', 'L', ' ', ' ', ' ')     // max 6 chars\r
+#define EFI_ACPI_OEM_ID1           SIGNATURE_64('I', 'N', 'T', 'E', 'L', '1', ' ', ' ')     // max 6 chars\r
+#define EFI_ACPI_OEM_ID2           SIGNATURE_64('I', 'N', 'T', 'E', 'L', '2', ' ', ' ')     // max 6 chars\r
+\r
+#define EFI_ACPI_OEM_TABLE_ID_DEFAULT   SIGNATURE_64('E', 'D', 'K', '2', ' ', ' ', ' ', ' ')\r
+#define EFI_ACPI_OEM_TABLE_ID1          SIGNATURE_64('E', 'D', 'K', '2', '_', '1', ' ', ' ')\r
+#define EFI_ACPI_OEM_TABLE_ID2          SIGNATURE_64('E', 'D', 'K', '2', '_', '2', ' ', ' ')\r
+\r
+\r
+EFI_STATUS\r
+InitializeBoardOemId (\r
+  IN CONST EFI_PEI_SERVICES      **PeiServices,\r
+  IN EFI_PLATFORM_INFO_HOB        *PlatformInfoHob\r
+  );\r

diff --git a/Vlv2TbltDevicePkg/Library/MultiPlatformLib/BoardSsidSvid/BoardSsidSvid.c b/Vlv2TbltDevicePkg/Library/MultiPlatformLib/BoardSsidSvid/BoardSsidSvid.c
new file mode 100644 (file)
index 0000000..4a05d31
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Library/MultiPlatformLib/BoardSsidSvid/BoardSsidSvid.c
@@ -0,0 +1,42 @@
+/** @file\r
+  Subsystem IDs setting for multiplatform.\r
+\r
+  Copyright (c) 2010 - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+**/\r
+\r
+#include <BoardSsidSvid.h>\r
+\r
+//\r
+// Global module data\r
+//\r
+EFI_STATUS\r
+InitializeBoardSsidSvid (\r
+    IN CONST EFI_PEI_SERVICES       **PeiServices,\r
+    IN EFI_PLATFORM_INFO_HOB        *PlatformInfoHob\r
+  )\r
+{\r
+    UINT32  SsidSvidValue = 0;\r
+\r
+    //\r
+    // Set OEM ID according to Board ID.\r
+    //\r
+    switch (PlatformInfoHob->BoardId) {\r
+      case BOARD_ID_MINNOW2:\r
+             default:\r
+                  SsidSvidValue = SUBSYSTEM_SVID_SSID;//SUBSYSTEM_SVID_SSID_DEFAULT;\r
+                  break;\r
+      }\r
+    PlatformInfoHob->SsidSvid = SsidSvidValue;\r
+    return  EFI_SUCCESS;\r
+}\r
+\r

diff --git a/Vlv2TbltDevicePkg/Library/MultiPlatformLib/BoardSsidSvid/BoardSsidSvid.h b/Vlv2TbltDevicePkg/Library/MultiPlatformLib/BoardSsidSvid/BoardSsidSvid.h
new file mode 100644 (file)
index 0000000..b22c03c
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Library/MultiPlatformLib/BoardSsidSvid/BoardSsidSvid.h
@@ -0,0 +1,40 @@
+/**@file\r
+  Subsystem IDs setting for multiplatform.\r
+\r
+  This file includes package header files, library classes.\r
+\r
+  Copyright (c) 2010 - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+**/\r
+\r
+#include <Guid/PlatformInfo.h>\r
+#include <Library/BaseMemoryLib.h>\r
+\r
+//\r
+// Default Vendor ID and Subsystem ID\r
+//\r
+#define SUBSYSTEM_VENDOR_ID1   0x8086\r
+#define SUBSYSTEM_DEVICE_ID1   0x1999\r
+#define SUBSYSTEM_SVID_SSID1   (SUBSYSTEM_VENDOR_ID1 + (SUBSYSTEM_DEVICE_ID1 << 16))\r
+\r
+#define SUBSYSTEM_VENDOR_ID2   0x8086\r
+#define SUBSYSTEM_DEVICE_ID2   0x1888\r
+#define SUBSYSTEM_SVID_SSID2   (SUBSYSTEM_VENDOR_ID2 + (SUBSYSTEM_DEVICE_ID2 << 16))\r
+\r
+#define SUBSYSTEM_VENDOR_ID   0x8086\r
+#define SUBSYSTEM_DEVICE_ID   0x1234\r
+#define SUBSYSTEM_SVID_SSID   (SUBSYSTEM_VENDOR_ID + (SUBSYSTEM_DEVICE_ID << 16))\r
+\r
+EFI_STATUS\r
+InitializeBoardSsidSvid (\r
+    IN CONST EFI_PEI_SERVICES       **PeiServices,\r
+    IN EFI_PLATFORM_INFO_HOB        *PlatformInfoHob\r
+  );\r

diff --git a/Vlv2TbltDevicePkg/Library/MultiPlatformLib/MultiPlatformLib.c b/Vlv2TbltDevicePkg/Library/MultiPlatformLib/MultiPlatformLib.c
new file mode 100644 (file)
index 0000000..d32deb5
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Library/MultiPlatformLib/MultiPlatformLib.c
@@ -0,0 +1,122 @@
+/** @file\r
+  Multiplatform initialization.\r
+\r
+  Copyright (c) 2010 - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+**/\r
+\r
+#include <MultiPlatformLib.h>\r
+\r
+/**\r
+  Platform Type detection. Because the PEI globle variable\r
+  is in the flash, it could not change directly.So use\r
+  2 PPIs to distinguish the platform type.\r
+\r
+  @param FfsHeader       Pointer to Firmware File System file header.\r
+  @param PeiServices     General purpose services available to every PEIM.\r
+\r
+  @retval EFI_SUCCESS    Memory initialization completed successfully.\r
+  @retval Others         All other error conditions encountered result in an ASSERT.\r
+\r
+**/\r
+EFI_STATUS\r
+MultiPlatformInfoInit (\r
+  IN CONST EFI_PEI_SERVICES             **PeiServices,\r
+  IN OUT EFI_PLATFORM_INFO_HOB          *PlatformInfoHob\r
+  )\r
+{\r
+  UINT32                                PcieLength;\r
+  EFI_STATUS      Status;\r
+\r
+\r
+  PlatformInfoHob->IohSku = MmPci16(0, MC_BUS, MC_DEV, MC_FUN, PCI_DEVICE_ID_OFFSET);\r
+\r
+  PlatformInfoHob->IohRevision = MmPci8(0, MC_BUS, MC_DEV, MC_FUN, PCI_REVISION_ID_OFFSET);\r
+\r
+  //\r
+  // Update ICH Type\r
+  //\r
+  //\r
+  // Device ID\r
+  //\r
+  PlatformInfoHob->IchSku = PchLpcPciCfg16(PCI_DEVICE_ID_OFFSET);\r
+\r
+  PlatformInfoHob->IchRevision = PchLpcPciCfg8(PCI_REVISION_ID_OFFSET);\r
+\r
+       //\r
+    //64MB\r
+    //\r
+    PcieLength = 0x04000000;\r
+\r
+  //\r
+  // Don't support BASE above 4GB currently.\r
+  //\r
+  PlatformInfoHob->PciData.PciExpressSize     = PcieLength;\r
+  PlatformInfoHob->PciData.PciExpressBase     = PcdGet64 (PcdPciExpressBaseAddress);\r
+\r
+  PlatformInfoHob->PciData.PciResourceMem32Base  = (UINT32) (PlatformInfoHob->PciData.PciExpressBase - RES_MEM32_MIN_LEN);\r
+  PlatformInfoHob->PciData.PciResourceMem32Limit = (UINT32) (PlatformInfoHob->PciData.PciExpressBase -1);\r
+\r
+  PlatformInfoHob->PciData.PciResourceMem64Base   = RES_MEM64_36_BASE;\r
+  PlatformInfoHob->PciData.PciResourceMem64Limit  = RES_MEM64_36_LIMIT;\r
+  PlatformInfoHob->CpuData.CpuAddressWidth        = 36;\r
+\r
+  PlatformInfoHob->MemData.MemMir0 = PlatformInfoHob->PciData.PciResourceMem64Base;\r
+  PlatformInfoHob->MemData.MemMir1 = PlatformInfoHob->PciData.PciResourceMem64Limit + 1;\r
+\r
+  PlatformInfoHob->PciData.PciResourceMinSecBus  = 1;  //can be changed by SystemConfiguration->PciMinSecondaryBus;\r
+\r
+  //\r
+  // Set MemMaxTolm to the lowest address between PCIe Base and PCI32 Base.\r
+  //\r
+  if (PlatformInfoHob->PciData.PciExpressBase > PlatformInfoHob->PciData.PciResourceMem32Base ) {\r
+    PlatformInfoHob->MemData.MemMaxTolm = (UINT32) PlatformInfoHob->PciData.PciResourceMem32Base;\r
+  } else {\r
+    PlatformInfoHob->MemData.MemMaxTolm = (UINT32) PlatformInfoHob->PciData.PciExpressBase;\r
+  }\r
+  PlatformInfoHob->MemData.MemTolm = PlatformInfoHob->MemData.MemMaxTolm;\r
+\r
+  //\r
+  // Platform PCI MMIO Size in unit of 1MB.\r
+  //\r
+  PlatformInfoHob->MemData.MmioSize = 0x1000 - (UINT16)(PlatformInfoHob->MemData.MemMaxTolm >> 20);\r
+\r
+  //\r
+  // Enable ICH IOAPIC\r
+  //\r
+  PlatformInfoHob->SysData.SysIoApicEnable  = ICH_IOAPIC;\r
+\r
+   DEBUG ((EFI_D_ERROR,  "PlatformFlavor is %x (%x=tablet,%x=mobile,%x=desktop)\n", PlatformInfoHob->PlatformFlavor,FlavorTablet,FlavorMobile,FlavorDesktop));\r
+\r
+    //\r
+    // Get Platform Info and fill the Hob.\r
+    //\r
+    PlatformInfoHob->RevisonId = PLATFORM_INFO_HOB_REVISION;\r
+\r
+      //\r
+      // Get GPIO table\r
+      //\r
+      Status = MultiPlatformGpioTableInit (PeiServices, PlatformInfoHob);\r
+\r
+      //\r
+      // Program GPIO\r
+      //\r
+      Status = MultiPlatformGpioProgram (PeiServices, PlatformInfoHob);\r
+\r
+      //\r
+      // Update OemId\r
+      //\r
+      Status = InitializeBoardOemId (PeiServices, PlatformInfoHob);\r
+      Status = InitializeBoardSsidSvid (PeiServices, PlatformInfoHob);\r
+\r
+    return EFI_SUCCESS;\r
+}\r

diff --git a/Vlv2TbltDevicePkg/Library/MultiPlatformLib/MultiPlatformLib.h b/Vlv2TbltDevicePkg/Library/MultiPlatformLib/MultiPlatformLib.h
new file mode 100644 (file)
index 0000000..a1fe9d4
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Library/MultiPlatformLib/MultiPlatformLib.h
@@ -0,0 +1,94 @@
+/**@file\r
+  Multiplatform initialization header file.\r
+\r
+  This file includes package header files, library classes.\r
+\r
+  Copyright (c) 2013 - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+**/\r
+\r
+#ifndef _MULTIPLATFORM_LIB_H_\r
+#define _MULTIPLATFORM_LIB_H_\r
+\r
+\r
+#define LEN_64M       0x4000000\r
+\r
+//\r
+// Default PCI32 resource size\r
+//\r
+#define RES_MEM32_MIN_LEN   0x38000000\r
+\r
+#define RES_IO_BASE   0x0D00\r
+#define RES_IO_LIMIT  0xFFFF\r
+\r
+#include <PiDxe.h>\r
+#include <Library/BaseLib.h>\r
+#include <FrameworkPei.h>\r
+\r
+#include "PlatformBaseAddresses.h"\r
+#include "PchAccess.h"\r
+#include "SetupMode.h"\r
+#include "PlatformBootMode.h"\r
+#include "Platform.h"\r
+\r
+#include <Ppi/Stall.h>\r
+#include <Guid/SetupVariable.h>\r
+#include <Ppi/AtaController.h>\r
+#include <Ppi/FindFv.h>\r
+#include <Ppi/BootInRecoveryMode.h>\r
+#include <Ppi/ReadOnlyVariable2.h>\r
+#include <Ppi/Capsule.h>\r
+#include <Guid/EfiVpdData.h>\r
+#include <Library/DebugLib.h>\r
+#include <Library/BaseMemoryLib.h>\r
+#include <Library/PcdLib.h>\r
+#include <Library/IoLib.h>\r
+#include <Library/HobLib.h>\r
+#include <Library/BaseLib.h>\r
+#include <IndustryStandard/Pci22.h>\r
+#include <Ppi/Speaker.h>\r
+#include <Guid/FirmwareFileSystem.h>\r
+#include <Guid/MemoryTypeInformation.h>\r
+#include <Ppi/Cache.h>\r
+#include <Ppi/Reset.h>\r
+#include <Ppi/EndOfPeiPhase.h>\r
+#include <Ppi/MemoryDiscovered.h>\r
+#include <Guid/GlobalVariable.h>\r
+#include <Ppi/RecoveryModule.h>\r
+#include <Ppi/DeviceRecoveryModule.h>\r
+#include <Guid/Capsule.h>\r
+#include <Guid/RecoveryDevice.h>\r
+#include <Ppi/MasterBootMode.h>\r
+#include <Guid/PlatformInfo.h>\r
+\r
+#include <BoardOemIds/BoardOemIds.h>\r
+#include <BoardSsidSvid/BoardSsidSvid.h>\r
+\r
+\r
+EFI_STATUS\r
+GetPlatformInfoHob (\r
+  IN CONST EFI_PEI_SERVICES           **PeiServices,\r
+  OUT EFI_PLATFORM_INFO_HOB     **PlatformInfoHob\r
+  );\r
+\r
+EFI_STATUS\r
+MultiPlatformGpioTableInit (\r
+  IN CONST EFI_PEI_SERVICES     **PeiServices,\r
+  IN EFI_PLATFORM_INFO_HOB      *PlatformInfoHob\r
+  );\r
+\r
+EFI_STATUS\r
+MultiPlatformGpioProgram (\r
+  IN CONST EFI_PEI_SERVICES     **PeiServices,\r
+  IN EFI_PLATFORM_INFO_HOB      *PlatformInfoHob\r
+  );\r
+\r
+#endif\r

diff --git a/Vlv2TbltDevicePkg/Library/MultiPlatformLib/MultiPlatformLib.inf b/Vlv2TbltDevicePkg/Library/MultiPlatformLib/MultiPlatformLib.inf
new file mode 100644 (file)
index 0000000..74ffc78
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Library/MultiPlatformLib/MultiPlatformLib.inf
@@ -0,0 +1,83 @@
+#\r
+#\r
+# Copyright (c)  1999  - 2014, Intel Corporation. All rights reserved\r
+#                                                                                  \r\r
+# This program and the accompanying materials are licensed and made available under\r\r
+# the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+# The full text of the license may be found at                                     \r\r
+# http://opensource.org/licenses/bsd-license.php.                                  \r\r
+#                                                                                  \r\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+#                                                                                  \r\r
+#\r
+#\r
+#\r
+#  Module Name:\r
+#\r
+#   MultiPlatform.inf\r
+#\r
+#  Abstract:\r
+#\r
+#\r
+--*/\r
+\r
+\r
+[defines]\r
+  INF_VERSION                    = 0x00010005\r
+  BASE_NAME                      = MultiPlatformLib\r
+  FILE_GUID                      = AB83A52B-B44A-462c-B099-444CC0ED274D\r
+  MODULE_TYPE                    = PEIM\r
+  VERSION_STRING                 = 1.0\r
+  LIBRARY_CLASS                  = MultiPlatformLib\r
+  PI_SPECIFICATION_VERSION       = 0x0001000A\r
+\r
+[sources]\r
+  MultiPlatformLib.c\r
+  MultiPlatformLib.h\r
+  PlatformInfoHob.c\r
+#GPIO\r
+  BoardGpios/BoardGpios.c\r
+  BoardGpios/BoardGpios.h\r
+\r
+#ClkGen\r
+  BoardClkGens/BoardClkGens.c\r
+  BoardClkGens/BoardClkGens.h\r
+\r
+#Jumper\r
+  BoardJumpers/BoardJumpers.c\r
+  BoardJumpers/BoardJumpers.h\r
+\r
+#OemId\r
+  BoardOemIds/BoardOemIds.c\r
+  BoardOemIds/BoardOemIds.h\r
+\r
+#SSIDSVID\r
+  BoardSsidSvid/BoardSsidSvid.c\r
+  BoardSsidSvid/BoardSsidSvid.h\r
+[Guids]\r
+\r
+  gEfiPlatformInfoGuid                     # ALWAYS_CONSUMED\r
+\r
+[Packages]\r
+  MdePkg/MdePkg.dec\r
+  MdeModulePkg/MdeModulePkg.dec\r
+  Vlv2TbltDevicePkg/PlatformPkg.dec\r
+  IntelFrameworkPkg/IntelFrameworkPkg.dec\r
+  Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec\r
+  IA32FamilyCpuPkg/IA32FamilyCpuPkg.dec\r
+\r
+[LibraryClasses]\r
+  DebugLib\r
+  HobLib\r
+  IoLib\r
+#  PeiKscLib\r
+\r
+[Ppis]\r
+  gEfiPeiReadOnlyVariable2PpiGuid\r
+\r
+[Pcd.common]\r
+  gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress\r
+\r
+[Guids]\r
+  gEfiSetupVariableGuid\r

diff --git a/Vlv2TbltDevicePkg/Library/MultiPlatformLib/PlatformInfoHob.c b/Vlv2TbltDevicePkg/Library/MultiPlatformLib/PlatformInfoHob.c
new file mode 100644 (file)
index 0000000..ebaaf40
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Library/MultiPlatformLib/PlatformInfoHob.c
@@ -0,0 +1,59 @@
+/** @file\r
+  Platform Hob access interface for multiplatform.\r
+\r
+  Copyright (c) 2010 - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+**/\r
+\r
+#include <MultiPlatformLib.h>\r
+\r
+/**\r
+  Returns the Platform Info of the platform from the HOB.\r
+\r
+  @param PeiServices         General purpose services available to every PEIM.\r
+  @param PlatformInfoHob     Pointer to the PLATFORM_INFO_HOB Pointer\r
+\r
+  @retval EFI_SUCCESS        The function completed successfully.\r
+  @retval EFI_NOT_FOUND      PlatformInfoHob data doesn't exist, use default instead.\r
+\r
+**/\r
+EFI_STATUS\r
+GetPlatformInfoHob (\r
+  IN CONST EFI_PEI_SERVICES           **PeiServices,\r
+  OUT EFI_PLATFORM_INFO_HOB     **PlatformInfoHob\r
+  )\r
+{\r
+  EFI_PEI_HOB_POINTERS        GuidHob;\r
+\r
+  //\r
+  // Find the PlatformInfo HOB\r
+  //\r
+  GuidHob.Raw = GetHobList ();\r
+  if (GuidHob.Raw == NULL) {\r
+    return EFI_NOT_FOUND;\r
+  }\r
+\r
+  if ((GuidHob.Raw = GetNextGuidHob (&gEfiPlatformInfoGuid, GuidHob.Raw)) != NULL) {\r
+    *PlatformInfoHob = GET_GUID_HOB_DATA (GuidHob.Guid);\r
+  }\r
+\r
+  //\r
+  // PlatformInfo PEIM should provide this HOB data, if not ASSERT and return error.\r
+  //\r
+  ASSERT_EFI_ERROR (*PlatformInfoHob != NULL);\r
+  if (!(*PlatformInfoHob)) {\r
+    return EFI_NOT_FOUND;\r
+  }\r
+\r
+  return EFI_SUCCESS;\r
+}\r
+\r

diff --git a/Vlv2TbltDevicePkg/Library/PchPlatformLib/PchPlatformLib.inf b/Vlv2TbltDevicePkg/Library/PchPlatformLib/PchPlatformLib.inf
new file mode 100644 (file)
index 0000000..48386cb
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Library/PchPlatformLib/PchPlatformLib.inf
@@ -0,0 +1,55 @@
+#\r
+#\r
+#/*++\r
+#\r
+#  Copyright (c) 2012  - 2014, Intel Corporation. All rights reserved\r
+#                                                                                  \r\r
+# This program and the accompanying materials are licensed and made available under\r\r
+# the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+# The full text of the license may be found at                                     \r\r
+# http://opensource.org/licenses/bsd-license.php.                                  \r\r
+#                                                                                  \r\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+#                                                                                  \r\r
+#\r
+#  Module Name:\r
+#\r
+#    PeiDxePchPlatformLib.inf\r
+#\r
+#  Abstract:\r
+#\r
+#    Component description file for PEI/DXE PCH Platform Lib\r
+#\r
+#--*/\r
+\r
+[defines]\r
+  INF_VERSION                    = 0x00010005\r
+  BASE_NAME                      = PchPlatformLib\r
+  FILE_GUID                      = 32F89CBC-305D-4bdd-8B2C-9C65592E66AC\r
+  MODULE_TYPE                    = BASE\r
+  VERSION_STRING                 = 1.0\r
+  LIBRARY_CLASS                  = PchPlatformLib\r
+\r
+[sources.common]\r
+  PchPlatformLibrary.h\r
+  PchPlatformLibrary.c\r
+\r
+[Packages]\r
+  MdePkg/MdePkg.dec\r
+  MdeModulePkg/MdeModulePkg.dec\r
+  Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec\r
+\r
+[LibraryClasses]\r
+  BaseLib\r
+  PciLib\r
+  IoLib\r
+  DebugLib\r
+\r
+\r
+[Pcd.common]\r
+  gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress\r
+\r
+\r
+[Protocols]\r
+\r

diff --git a/Vlv2TbltDevicePkg/Library/PchPlatformLib/PchPlatformLibrary.c b/Vlv2TbltDevicePkg/Library/PchPlatformLib/PchPlatformLibrary.c
new file mode 100644 (file)
index 0000000..c92308f
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Library/PchPlatformLib/PchPlatformLibrary.c
@@ -0,0 +1,131 @@
+/**\r
+\r
+Copyright (c) 2012  - 2014, Intel Corporation. All rights reserved\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+  @file\r
+  PchPlatformLib.c\r
+\r
+  @brief\r
+  PCH Platform Lib implementation.\r
+\r
+**/\r
+\r
+#include "PchPlatformLibrary.h"\r
+\r
+//\r
+// Silicon Steppings\r
+//\r
+/**\r
+  Return Pch stepping type\r
+\r
+  @param[in] None\r
+\r
+  @retval PCH_STEPPING            Pch stepping type\r
+\r
+**/\r
+PCH_STEPPING\r
+EFIAPI\r
+PchStepping (\r
+  VOID\r
+  )\r
+{\r
+  UINT8 RevId;\r
+\r
+  RevId = MmioRead8 (\r
+          MmPciAddress (0,\r
+            DEFAULT_PCI_BUS_NUMBER_PCH,\r
+            PCI_DEVICE_NUMBER_PCH_LPC,\r
+            PCI_FUNCTION_NUMBER_PCH_LPC,\r
+            R_PCH_LPC_RID_CC)\r
+          );\r
+\r
+  switch (RevId) {\r
+    case V_PCH_LPC_RID_0:\r
+    case V_PCH_LPC_RID_1:\r
+      return PchA0;\r
+      break;\r
+\r
+    case V_PCH_LPC_RID_2:\r
+    case V_PCH_LPC_RID_3:\r
+      return PchA1;\r
+      break;\r
+\r
+    case V_PCH_LPC_RID_4:\r
+    case V_PCH_LPC_RID_5:\r
+      return PchB0;\r
+      break;\r
+\r
+    case V_PCH_LPC_RID_6:\r
+    case V_PCH_LPC_RID_7:\r
+      return PchB1;\r
+      break;\r
+\r
+    case V_PCH_LPC_RID_8:\r
+    case V_PCH_LPC_RID_9:\r
+      return PchB2;\r
+      break;\r
+\r
+    case V_PCH_LPC_RID_A:\r
+    case V_PCH_LPC_RID_B:\r
+      return PchB3;\r
+      break;\r
+\r
+    case V_PCH_LPC_RID_C:\r
+    case V_PCH_LPC_RID_D:\r
+      return PchC0;\r
+      break;\r
+\r
+    default:\r
+      return PchSteppingMax;\r
+      break;\r
+\r
+  }\r
+}\r
+\r
+/**\r
+  Determine if PCH is supported\r
+\r
+  @param[in] None\r
+\r
+  @retval TRUE                    PCH is supported\r
+  @retval FALSE                   PCH is not supported\r
+\r
+**/\r
+BOOLEAN\r
+IsPchSupported (\r
+  VOID\r
+  )\r
+{\r
+  UINT32  Identifiers;\r
+  UINT16  PcuVendorId;\r
+  UINT16  PcuDeviceId;\r
+\r
+  Identifiers = MmioRead32 (\r
+                  MmPciAddress (0,\r
+                  DEFAULT_PCI_BUS_NUMBER_PCH,\r
+                  PCI_DEVICE_NUMBER_PCH_LPC,\r
+                  PCI_FUNCTION_NUMBER_PCH_LPC,\r
+                  R_PCH_LPC_REG_ID)\r
+                );\r
+\r
+  PcuDeviceId = (UINT16) ((Identifiers & B_PCH_LPC_DEVICE_ID) >> 16);\r
+  PcuVendorId = (UINT16) (Identifiers & B_PCH_LPC_VENDOR_ID);\r
+\r
+  //\r
+  // Verify that this is a supported chipset\r
+  //\r
+  if (PcuVendorId != (UINT16) V_PCH_LPC_VENDOR_ID || !IS_PCH_VLV_LPC_DEVICE_ID (PcuDeviceId)) {\r
+    DEBUG ((EFI_D_ERROR, "VLV SC code doesn't support the PcuDeviceId: 0x%04x!\n", PcuDeviceId));\r
+    return FALSE;\r
+  }\r
+  return TRUE;\r
+}\r

diff --git a/Vlv2TbltDevicePkg/Library/PchPlatformLib/PchPlatformLibrary.h b/Vlv2TbltDevicePkg/Library/PchPlatformLib/PchPlatformLibrary.h
new file mode 100644 (file)
index 0000000..7464900
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Library/PchPlatformLib/PchPlatformLibrary.h
@@ -0,0 +1,40 @@
+/**\r
+**/\r
+/**\r
+\r
+Copyright (c) 2012  - 2014, Intel Corporation. All rights reserved\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+  @file\r
+  PchPlatformLibrary.h\r
+\r
+  @brief\r
+  Header file for PCH Platform Lib implementation.\r
+\r
+**/\r
+\r
+#ifndef _PCH_PLATFORM_LIBRARY_IMPLEMENTATION_H_\r
+#define _PCH_PLATFORM_LIBRARY_IMPLEMENTATION_H_\r
+\r
+#include "PchAccess.h"\r
+#ifdef ECP_FLAG\r
+#include "EdkIIGlueBase.h"\r
+#include "Library/EdkIIGlueMemoryAllocationLib.h"\r
+#else\r
+#include "Library/PciLib.h"\r
+#include "Library/IoLib.h"\r
+#include "Library/DebugLib.h"\r
+#include "Library/PcdLib.h"\r
+\r
+#include "PchCommonDefinitions.h"\r
+#endif\r
+\r
+#endif\r

diff --git a/Vlv2TbltDevicePkg/Library/PchSmmLib/CommonHeader.h b/Vlv2TbltDevicePkg/Library/PchSmmLib/CommonHeader.h
new file mode 100644 (file)
index 0000000..aefb5c2
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Library/PchSmmLib/CommonHeader.h
@@ -0,0 +1,37 @@
+/**@file\r
+  Common header file shared by all source files.\r
+\r
+  This file includes package header files, library classes and protocol, PPI & GUID definitions.\r
+\r
+  Copyright (c) 2007 - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+**/\r
+\r
+#ifndef __COMMON_HEADER_H_\r
+#define __COMMON_HEADER_H_\r
+\r
+\r
+#include <Base.h>\r
+\r
+#include <Library/TimerLib.h>\r
+#include <Library/BaseLib.h>\r
+#include <Library/IoLib.h>\r
+#include <Library/PcdLib.h>\r
+#include <Library/DebugLib.h>\r
+\r
+#define R_PCH_ACPI_SMI_EN       0x30\r
+#define B_PCH_ACPI_APMC_EN      0x00000020\r
+#define B_PCH_ACPI_EOS          0x00000002\r
+#define B_PCH_ACPI_GBL_SMI_EN   0x00000001\r
+#define R_PCH_ACPI_SMI_STS      0x34\r
+#define B_PCH_ACPI_APM_STS      0x00000020\r
+\r
+#endif\r

diff --git a/Vlv2TbltDevicePkg/Library/PchSmmLib/PchSmmLib.c b/Vlv2TbltDevicePkg/Library/PchSmmLib/PchSmmLib.c
new file mode 100644 (file)
index 0000000..d4a90ee
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Library/PchSmmLib/PchSmmLib.c
@@ -0,0 +1,162 @@
+/** @file\r
+  PCH Smm Library Services that implements both S/W SMI generation and detection.\r
+\r
+  Copyright (c) 2007  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+**/\r
+\r
+\r
+#include "CommonHeader.h"\r
+\r
+\r
+/**\r
+  Triggers a run time or boot time SMI.\r
+\r
+  This function triggers a software SMM interrupt and set the APMC status with an 8-bit Data.\r
+\r
+  @param  Data                 The value to set the APMC status.\r
+\r
+**/\r
+VOID\r
+InternalTriggerSmi (\r
+  IN UINT8                     Data\r
+  )\r
+{\r
+  ASSERT(FALSE);\r
+}\r
+\r
+\r
+/**\r
+  Triggers an SMI at boot time.\r
+\r
+  This function triggers a software SMM interrupt at boot time.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+TriggerBootServiceSoftwareSmi (\r
+  VOID\r
+  )\r
+{\r
+  ASSERT(FALSE);\r
+}\r
+\r
+\r
+/**\r
+  Triggers an SMI at run time.\r
+\r
+  This function triggers a software SMM interrupt at run time.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+TriggerRuntimeSoftwareSmi (\r
+  VOID\r
+  )\r
+{\r
+  ASSERT(FALSE);\r
+}\r
+\r
+\r
+/**\r
+  Gets the software SMI data.\r
+\r
+  This function tests if a software SMM interrupt happens. If a software SMI happens,\r
+  it retrieves the SMM data and returns it as a non-negative value; otherwise a negative\r
+  value is returned.\r
+\r
+  @return Data                 The data retrieved from SMM data port in case of a software SMI;\r
+                               otherwise a negative value.\r
+\r
+**/\r
+INTN\r
+InternalGetSwSmiData (\r
+  VOID\r
+  )\r
+{\r
+  ASSERT(FALSE);\r
+  return -1;\r
+}\r
+\r
+\r
+/**\r
+  Test if a boot time software SMI happened.\r
+\r
+  This function tests if a software SMM interrupt happened. If a software SMM interrupt happened and\r
+  it was triggered at boot time, it returns TRUE. Otherwise, it returns FALSE.\r
+\r
+  @retval TRUE   A software SMI triggered at boot time happened.\r
+  @retval FLASE  No software SMI happened or the software SMI was triggered at run time.\r
+\r
+**/\r
+BOOLEAN\r
+EFIAPI\r
+IsBootServiceSoftwareSmi (\r
+  VOID\r
+  )\r
+{\r
+  ASSERT(FALSE);\r
+  return FALSE;\r
+}\r
+\r
+\r
+/**\r
+  Test if a run time software SMI happened.\r
+\r
+  This function tests if a software SMM interrupt happened. If a software SMM interrupt happened and\r
+  it was triggered at run time, it returns TRUE. Otherwise, it returns FALSE.\r
+\r
+  @retval TRUE   A software SMI triggered at run time happened.\r
+  @retval FLASE  No software SMI happened or the software SMI was triggered at boot time.\r
+\r
+**/\r
+BOOLEAN\r
+EFIAPI\r
+IsRuntimeSoftwareSmi (\r
+  VOID\r
+  )\r
+{\r
+  ASSERT(FALSE);\r
+  return FALSE;\r
+}\r
+\r
+\r
+/**\r
+\r
+  Clear APM SMI Status Bit; Set the EOS bit.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+ClearSmi (\r
+  VOID\r
+  )\r
+{\r
+\r
+  UINT16                       PmBase;\r
+\r
+  //\r
+  // Get PMBase\r
+  //\r
+  PmBase = PcdGet16 (PcdPchAcpiIoPortBaseAddress);\r
+\r
+  //\r
+  // Clear the APM SMI Status Bit\r
+  //\r
+  IoWrite16 (PmBase + R_PCH_ACPI_SMI_STS, B_PCH_ACPI_APM_STS);\r
+\r
+  //\r
+  // Set the EOS Bit\r
+  //\r
+  IoOr32 (PmBase + R_PCH_ACPI_SMI_EN, B_PCH_ACPI_EOS);\r
+}\r
+\r

diff --git a/Vlv2TbltDevicePkg/Library/PchSmmLib/PchSmmLib.inf b/Vlv2TbltDevicePkg/Library/PchSmmLib/PchSmmLib.inf
new file mode 100644 (file)
index 0000000..e6516fb
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Library/PchSmmLib/PchSmmLib.inf
@@ -0,0 +1,51 @@
+## @file\r
+# Component description file for Intel Ich7 SMM Library.\r
+#\r
+# ICH SMM Library that layers on top of the I/O Library to directly\r
+#  access SMM power management registers.\r
+# Copyright (c) 2007  - 2014, Intel Corporation. All rights reserved.<BR>\r
+#                                                                                  \r\r
+# This program and the accompanying materials are licensed and made available under\r\r
+# the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+# The full text of the license may be found at                                     \r\r
+# http://opensource.org/licenses/bsd-license.php.                                  \r\r
+#                                                                                  \r\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+#                                                                                  \r\r
+#\r
+#\r
+#\r
+##\r
+\r
+[Defines]\r
+  INF_VERSION                    = 0x00010005\r
+  BASE_NAME                      = PchSmmLib\r
+  FILE_GUID                      = A6A16CCB-91B0-42f4-B4F3-D17D7A5662E6\r
+  MODULE_TYPE                    = BASE\r
+  VERSION_STRING                 = 1.0\r
+  LIBRARY_CLASS                  = SmmLib\r
+\r
+\r
+#\r
+# The following information is for reference only and not required by the build tools.\r
+#\r
+#  VALID_ARCHITECTURES           = IA32 X64 IPF EBC\r
+#\r
+\r
+[Sources]\r
+  PchSmmLib.c\r
+\r
+\r
+[Packages]\r
+  MdePkg/MdePkg.dec\r
+  Vlv2TbltDevicePkg/PlatformPkg.dec\r
+\r
+[LibraryClasses]\r
+  PcdLib\r
+  IoLib\r
+\r
+[Pcd]\r
+  gEfiPchTokenSpaceGuid.PcdPchAcpiIoPortBaseAddress\r
+\r
+\r

diff --git a/Vlv2TbltDevicePkg/Library/PlatformBdsLib/BdsPlatform.c b/Vlv2TbltDevicePkg/Library/PlatformBdsLib/BdsPlatform.c
new file mode 100644 (file)
index 0000000..b0ada79
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Library/PlatformBdsLib/BdsPlatform.c
@@ -0,0 +1,2399 @@
+/** @file\r
+\r
+  Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+\r
+Module Name:\r
+\r
+  BdsPlatform.c\r
+\r
+Abstract:\r
+\r
+  This file include all platform action which can be customized\r
+  by IBV/OEM.\r
+\r
+--*/\r
+\r
+#include "BdsPlatform.h"\r
+#include "SetupMode.h"\r
+#include <Guid/SetupVariable.h>\r
+#include <Library/TcgPhysicalPresenceLib.h>\r
+#include <Library/TrEEPhysicalPresenceLib.h>\r
+#include <Protocol/I2cMasterMcg.h>\r
+#include <TianoApi.h>\r
+#include <PlatformBaseAddresses.h>\r
+#include <Protocol/GlobalNvsArea.h>\r
+#include <Library/DxeServicesTableLib.h>\r
+#include <Protocol/BlockIo.h>\r
+#include <PchRegs/PchRegsPcu.h>\r
+#include <Library/S3BootScriptLib.h>\r
+#include "PchAccess.h"\r
+#include "PchRegs/PchRegsSata.h"\r
+#include <Library/SerialPortLib.h>\r
+#include <Library/DebugLib.h>\r
+\r
+\r
+EFI_GUID *ConnectDriverTable[] = {\r
+  &gEfiMmioDeviceProtocolGuid,\r
+  &gEfiI2cMasterProtocolGuid,\r
+  &gEfiI2cHostProtocolGuid\r
+};\r
+\r
+#define SHELL_ENVIRONMENT_INTERFACE_PROTOCOL \\r
+  { \\r
+    0x47c7b221, 0xc42a, 0x11d2, 0x8e, 0x57, 0x0, 0xa0, 0xc9, 0x69, 0x72, 0x3b \\r
+  }\r
+VOID               *mShellImageCallbackReg = NULL;\r
+\r
+\r
+\r
+EFI_USER_PROFILE_HANDLE                           mCurrentUser = NULL;\r
+EFI_EVENT                                         mHotKeyTimerEvent = NULL;\r
+EFI_EVENT                                         mHitHotkeyEvent = NULL;\r
+EFI_EVENT                                         mUsbKeyboardConnectEvent = NULL;\r
+BOOLEAN                                           mHotKeyPressed = FALSE;\r
+VOID                                              *mHitHotkeyRegistration;\r
+#define KEYBOARD_TIMER_INTERVAL                   20000 // 0.02s\r
+\r
+VOID\r
+ConnectUSBController (\r
+  VOID\r
+  );\r
+\r
+EFI_STATUS\r
+PlatformBdsConnectSimpleConsole (\r
+  IN BDS_CONSOLE_CONNECT_ENTRY   *PlatformConsole\r
+);\r
+\r
+VOID \r
+BootIntoFirmwareInterface(\r
+  VOID\r
+  );\r
+  \r
+VOID\r
+EFIAPI\r
+PlatformBdsInitHotKeyEvent (\r
+  VOID\r
+  );\r
+\r
+VOID\r
+EFIAPI\r
+DisableAhciCtlr (\r
+  IN EFI_EVENT                          Event,\r
+  IN VOID                               *Context\r
+  )\r
+{\r
+  UINT32                    PmcDisableAddress;\r
+  UINT8                     SataStorageAmount;\r
+  UINT32                    SataBase;\r
+  UINT16                    SataPortStatus;\r
+\r
+\r
+  DEBUG ((EFI_D_INFO, "Disable AHCI event is signalled\n"));\r
+  SataStorageAmount = 0;\r
+  SataBase = *(UINT32*) Context;\r
+\r
+  //\r
+  // BayTrail-M EDS chapter 16 ---- PCI IO Register Offset 92 (SATA Port Control and Status)\r
+  //\r
+  SataPortStatus = MmioRead16 (SataBase + R_PCH_SATA_PCS);\r
+\r
+  //\r
+  // Bit 8 EN: Port 0 Present\r
+  //\r
+  if ((SataPortStatus & 0x100) == 0x100) {\r
+    SataStorageAmount++;\r
+  }\r
+\r
+  //\r
+  // Bit 9 EN: Port 1 Present\r
+  //\r
+  if ((SataPortStatus & 0x200) == 0x200) {\r
+    SataStorageAmount++;\r
+  }\r
+\r
+  //\r
+  // Disable SATA controller when it sets to AHCI mode without carrying any devices\r
+  // in order to prevent AHCI yellow bang under Win device manager.\r
+  //\r
+  if (SataStorageAmount == 0) {\r
+    PmcDisableAddress = (MmioRead32 ((PCH_PCI_EXPRESS_BASE_ADDRESS + (UINT32) (31 << 15)) + R_PCH_LPC_PMC_BASE) & B_PCH_LPC_PMC_BASE_BAR) + R_PCH_PMC_FUNC_DIS;\r
+    MmioOr32 (PmcDisableAddress, B_PCH_PMC_FUNC_DIS_SATA);\r
+    S3BootScriptSaveMemWrite (\r
+      EfiBootScriptWidthUint32,\r
+      (UINTN) PmcDisableAddress,\r
+      1,\r
+      (VOID *) (UINTN) PmcDisableAddress\r
+      );\r
+  }\r
+}\r
+\r
+VOID\r
+InstallReadyToLock (\r
+  VOID\r
+  )\r
+{\r
+  EFI_STATUS                Status;\r
+  EFI_HANDLE                Handle;\r
+  EFI_SMM_ACCESS2_PROTOCOL  *SmmAccess;\r
+  EFI_ACPI_S3_SAVE_PROTOCOL *AcpiS3Save;\r
+\r
+  //\r
+  // Install DxeSmmReadyToLock protocol prior to the processing of boot options\r
+  //\r
+  Status = gBS->LocateProtocol (\r
+                  &gEfiSmmAccess2ProtocolGuid,\r
+                  NULL,\r
+                  (VOID **) &SmmAccess\r
+                  );\r
+  if (!EFI_ERROR (Status)) {\r
+\r
+    //\r
+    // Prepare S3 information, this MUST be done before DxeSmmReadyToLock\r
+    //\r
+    Status = gBS->LocateProtocol (\r
+                    &gEfiAcpiS3SaveProtocolGuid,\r
+                    NULL,\r
+                    (VOID **)&AcpiS3Save\r
+                    );\r
+    if (!EFI_ERROR (Status)) {\r
+      AcpiS3Save->S3Save (AcpiS3Save, NULL);\r
+    }\r
+\r
+    Handle = NULL;\r
+    Status = gBS->InstallProtocolInterface (\r
+                    &Handle,\r
+                    &gExitPmAuthProtocolGuid,\r
+                    EFI_NATIVE_INTERFACE,\r
+                    NULL\r
+                    );\r
+    ASSERT_EFI_ERROR (Status);\r
+\r
+    Handle = NULL;\r
+    Status = gBS->InstallProtocolInterface (\r
+                    &Handle,\r
+                    &gEfiDxeSmmReadyToLockProtocolGuid,\r
+                    EFI_NATIVE_INTERFACE,\r
+                    NULL\r
+                    );\r
+    ASSERT_EFI_ERROR (Status);\r
+  }\r
+\r
+  return ;\r
+}\r
+\r
+VOID\r
+EFIAPI\r
+ShellImageCallback (\r
+  IN EFI_EVENT                          Event,\r
+  IN VOID                               *Context\r
+  )\r
+{\r
+ BdsSetConsoleMode (TRUE);\r
+ DEBUG ((EFI_D_INFO, "BdsEntry ShellImageCallback \n"));\r
+}\r
+\r
+//\r
+// BDS Platform Functions\r
+//\r
+/**\r
+  Platform Bds init. Incude the platform firmware vendor, revision\r
+  and so crc check.\r
+\r
+  @param VOID\r
+\r
+  @retval  None.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+PlatformBdsInit (\r
+  VOID\r
+  )\r
+{\r
+  EFI_STATUS  Status;\r
+  EFI_EVENT   ShellImageEvent;\r
+  EFI_GUID    ShellEnvProtocol = SHELL_ENVIRONMENT_INTERFACE_PROTOCOL;\r
+\r
+  #ifdef __GNUC__\r
+  SerialPortWrite((UINT8 *)">>>>BdsEntry[GCC]\r\n", 19);\r
+  #else\r
+  SerialPortWrite((UINT8 *)">>>>BdsEntry\r\n", 14);\r
+  #endif\r
+  BdsLibSaveMemoryTypeInformation ();\r
+\r
+  //\r
+  // Before user authentication, the user identification devices need be connected\r
+  // from the platform customized device paths\r
+  //\r
+  PlatformBdsConnectAuthDevice ();\r
+\r
+  //\r
+  // As console is not ready, the auto logon user will be identified.\r
+  //\r
+  BdsLibUserIdentify (&mCurrentUser);\r
+\r
+  //\r
+  // Change Gop mode when boot into Shell\r
+  //\r
+  if (mShellImageCallbackReg == NULL) {\r
+    Status = gBS->CreateEvent (\r
+                    EFI_EVENT_NOTIFY_SIGNAL,\r
+                    EFI_TPL_CALLBACK,\r
+                    ShellImageCallback,\r
+                    NULL,\r
+                    &ShellImageEvent\r
+                    );\r
+    if (!EFI_ERROR (Status)) {\r
+      Status = gBS->RegisterProtocolNotify (\r
+                      &ShellEnvProtocol,\r
+                      ShellImageEvent,\r
+                      &mShellImageCallbackReg\r
+                      );\r
+\r
+      DEBUG ((EFI_D_INFO, "BdsEntry ShellImageCallback \n"));\r
+    }\r
+  }\r
+}\r
+\r
+EFI_STATUS\r
+GetGopDevicePath (\r
+   IN  EFI_DEVICE_PATH_PROTOCOL *PciDevicePath,\r
+   OUT EFI_DEVICE_PATH_PROTOCOL **GopDevicePath\r
+   )\r
+{\r
+  UINTN                           Index;\r
+  EFI_STATUS                      Status;\r
+  EFI_HANDLE                      PciDeviceHandle;\r
+  EFI_DEVICE_PATH_PROTOCOL        *TempDevicePath;\r
+  EFI_DEVICE_PATH_PROTOCOL        *TempPciDevicePath;\r
+  UINTN                           GopHandleCount;\r
+  EFI_HANDLE                      *GopHandleBuffer;\r
+\r
+  UINTN                                 VarSize;\r
+  SYSTEM_CONFIGURATION  mSystemConfiguration;\r
+\r
+  if (PciDevicePath == NULL || GopDevicePath == NULL) {\r
+    return EFI_INVALID_PARAMETER;\r
+  }\r
+\r
+  //\r
+  // Initialize the GopDevicePath to be PciDevicePath\r
+  //\r
+  *GopDevicePath    = PciDevicePath;\r
+  TempPciDevicePath = PciDevicePath;\r
+\r
+  Status = gBS->LocateDevicePath (\r
+                  &gEfiDevicePathProtocolGuid,\r
+                  &TempPciDevicePath,\r
+                  &PciDeviceHandle\r
+                  );\r
+  if (EFI_ERROR (Status)) {\r
+    return Status;\r
+  }\r
+\r
+  //\r
+  // Try to connect this handle, so that GOP dirver could start on this\r
+  // device and create child handles with GraphicsOutput Protocol installed\r
+  // on them, then we get device paths of these child handles and select\r
+  // them as possible console device.\r
+  //\r
+\r
+  //\r
+  // Select display devices\r
+  //\r
+  VarSize = sizeof(SYSTEM_CONFIGURATION);\r
+  Status = gRT->GetVariable(\r
+                  L"Setup",\r
+                  &gEfiNormalSetupGuid,\r
+                  NULL,\r
+                  &VarSize,\r
+                  &mSystemConfiguration\r
+                  );\r
+  ASSERT_EFI_ERROR (Status);\r
+\r
+  if(mSystemConfiguration.BootDisplayDevice != 0x0)\r
+  {\r
+    ACPI_ADR_DEVICE_PATH         AcpiAdr;\r
+    EFI_DEVICE_PATH_PROTOCOL  *MyDevicePath = NULL;\r
+\r
+    AcpiAdr.Header.Type     = ACPI_DEVICE_PATH;\r
+    AcpiAdr.Header.SubType  = ACPI_ADR_DP;\r
+\r
+    switch (mSystemConfiguration.BootDisplayDevice) {\r
+    case 1:\r
+      AcpiAdr.ADR= ACPI_DISPLAY_ADR (1, 0, 0, 1, 0, ACPI_ADR_DISPLAY_TYPE_VGA, PORT_CRT, 0);    //CRT Device\r
+      break;\r
+    case 2:\r
+      AcpiAdr.ADR= ACPI_DISPLAY_ADR (1, 0, 0, 1, 0, ACPI_ADR_DISPLAY_TYPE_EXTERNAL_DIGITAL, PORT_B_HDMI, 0);  //HDMI Device Port B\r
+      break;\r
+    case 3:\r
+      AcpiAdr.ADR= ACPI_DISPLAY_ADR (1, 0, 0, 1, 0, ACPI_ADR_DISPLAY_TYPE_EXTERNAL_DIGITAL, PORT_B_DP, 0);    //DP PortB\r
+      break;\r
+    case 4:\r
+      AcpiAdr.ADR= ACPI_DISPLAY_ADR (1, 0, 0, 1, 0, ACPI_ADR_DISPLAY_TYPE_EXTERNAL_DIGITAL, PORT_C_DP, 0);    //DP PortC\r
+      break;\r
+    case 5:\r
+      AcpiAdr.ADR= ACPI_DISPLAY_ADR (1, 0, 0, 1, 0, ACPI_ADR_DISPLAY_TYPE_INTERNAL_DIGITAL, PORT_C_DP, 0);    //eDP Port C\r
+      break;\r
+    case 6:\r
+      AcpiAdr.ADR= ACPI_DISPLAY_ADR (1, 0, 0, 1, 0, ACPI_ADR_DISPLAY_TYPE_INTERNAL_DIGITAL, PORT_MIPI_A, 0);  //DSI Port A\r
+      break;\r
+    case 7:\r
+      AcpiAdr.ADR= ACPI_DISPLAY_ADR (1, 0, 0, 1, 0, ACPI_ADR_DISPLAY_TYPE_INTERNAL_DIGITAL, PORT_MIPI_C, 0);  //DSI Port C\r
+      break;\r
+    default:\r
+      AcpiAdr.ADR= ACPI_DISPLAY_ADR (1, 0, 0, 1, 0, ACPI_ADR_DISPLAY_TYPE_VGA, PORT_CRT, 0);\r
+      break;\r
+    }\r
+\r
+    SetDevicePathNodeLength (&AcpiAdr.Header, sizeof (ACPI_ADR_DEVICE_PATH));\r
+\r
+    MyDevicePath = AppendDevicePathNode(MyDevicePath, (EFI_DEVICE_PATH_PROTOCOL*)&AcpiAdr);\r
+\r
+    gBS->ConnectController (\r
+           PciDeviceHandle,\r
+           NULL,\r
+           MyDevicePath,\r
+           FALSE\r
+           );\r
+\r
+    FreePool(MyDevicePath);\r
+  }\r
+  else\r
+  {\r
+    gBS->ConnectController (\r
+           PciDeviceHandle,\r
+           NULL,\r
+           NULL,\r
+           FALSE\r
+           );\r
+  }\r
+\r
+  Status = gBS->LocateHandleBuffer (\r
+                  ByProtocol,\r
+                  &gEfiGraphicsOutputProtocolGuid,\r
+                  NULL,\r
+                  &GopHandleCount,\r
+                  &GopHandleBuffer\r
+                  );\r
+  if (!EFI_ERROR (Status)) {\r
+    //\r
+    // Add all the child handles as possible Console Device\r
+    //\r
+    for (Index = 0; Index < GopHandleCount; Index++) {\r
+      Status = gBS->HandleProtocol (\r
+                      GopHandleBuffer[Index],\r
+                      &gEfiDevicePathProtocolGuid,\r
+                      (VOID**)&TempDevicePath\r
+                      );\r
+      if (EFI_ERROR (Status)) {\r
+        continue;\r
+      }\r
+      if (CompareMem (\r
+            PciDevicePath,\r
+            TempDevicePath,\r
+            GetDevicePathSize (PciDevicePath) - END_DEVICE_PATH_LENGTH\r
+            ) == 0) {\r
+        //\r
+        // In current implementation, we only enable one of the child handles\r
+        // as console device, i.e. sotre one of the child handle's device\r
+        // path to variable "ConOut"\r
+        // In futhure, we could select all child handles to be console device\r
+        //\r
+        *GopDevicePath = TempDevicePath;\r
+      }\r
+    }\r
+    gBS->FreePool (GopHandleBuffer);\r
+  }\r
+\r
+  return EFI_SUCCESS;\r
+}\r
+\r
+/**\r
+\r
+  Search out all the platform pci or agp video device. The function may will\r
+  find multiple video device, and return all enabled device path.\r
+\r
+  @param PlugInPciVgaDevicePath    Return the platform plug in pci video device\r
+                                   path if the system have plug in pci video device.\r
+  @param OnboardPciVgaDevicePath   Return the platform active agp video device path\r
+                                   if the system have plug in agp video device or on\r
+                                   chip agp device.\r
+\r
+  @retval EFI_SUCCSS               Get all platform active video device path.\r
+  @retval EFI_STATUS               Return the status of gBS->LocateDevicePath (),\r
+                                   gBS->ConnectController (),\r
+                                   and gBS->LocateHandleBuffer ().\r
+\r
+**/\r
+EFI_STATUS\r
+GetPlugInPciVgaDevicePath (\r
+  IN OUT EFI_DEVICE_PATH_PROTOCOL     **PlugInPciVgaDevicePath,\r
+  IN OUT EFI_DEVICE_PATH_PROTOCOL     **OnboardPciVgaDevicePath\r
+  )\r
+{\r
+  EFI_STATUS                Status;\r
+  EFI_HANDLE                RootHandle;\r
+  UINTN                     HandleCount;\r
+  EFI_HANDLE                *HandleBuffer;\r
+  UINTN                     Index;\r
+  UINTN                     Index1;\r
+  EFI_DEVICE_PATH_PROTOCOL  *DevicePath;\r
+  BOOLEAN                   PlugInPciVga;\r
+  EFI_PCI_IO_PROTOCOL       *PciIo;\r
+  PCI_TYPE00                Pci;\r
+\r
+  DevicePath = NULL;\r
+  PlugInPciVga = TRUE;\r
+  HandleCount = 0;\r
+  HandleBuffer = NULL;\r
+\r
+  //\r
+  // Make all the PCI_IO protocols on PCI Seg 0 show up\r
+  //\r
+  BdsLibConnectDevicePath (gPlatformRootBridges[0]);\r
+\r
+  Status = gBS->LocateDevicePath (\r
+                  &gEfiDevicePathProtocolGuid,\r
+                  &gPlatformRootBridges[0],\r
+                  &RootHandle\r
+                  );\r
+  if (EFI_ERROR (Status)) {\r
+    return Status;\r
+  }\r
+\r
+  Status = gBS->ConnectController (\r
+                  RootHandle,\r
+                  NULL,\r
+                  NULL,\r
+                  FALSE\r
+                  );\r
+  if (EFI_ERROR (Status)) {\r
+    return Status;\r
+  }\r
+\r
+  //\r
+  // Start to check all the pci io to find all possible VGA device\r
+  //\r
+  HandleCount = 0;\r
+  HandleBuffer = NULL;\r
+  Status = gBS->LocateHandleBuffer (\r
+                  ByProtocol,\r
+                  &gEfiPciIoProtocolGuid,\r
+                  NULL,\r
+                  &HandleCount,\r
+                  &HandleBuffer\r
+                  );\r
+  if (EFI_ERROR (Status)) {\r
+    return Status;\r
+  }\r
+\r
+  for (Index = 0; Index < HandleCount; Index++) {\r
+    Status = gBS->HandleProtocol (\r
+                    HandleBuffer[Index],\r
+                    &gEfiPciIoProtocolGuid,\r
+                    (VOID**)&PciIo\r
+                    );\r
+    if (!EFI_ERROR (Status)) {\r
+\r
+      //\r
+      // Check for all VGA device\r
+      //\r
+      Status = PciIo->Pci.Read (\r
+                        PciIo,\r
+                        EfiPciIoWidthUint32,\r
+                        0,\r
+                        sizeof (Pci) / sizeof (UINT32),\r
+                        &Pci\r
+                        );\r
+      if (EFI_ERROR (Status)) {\r
+        continue;\r
+      }\r
+\r
+      //\r
+      // Here we decide which VGA device to enable in PCI bus\r
+      //\r
+      // The first plugin PCI VGA card device will be present as PCI VGA\r
+      // The onchip AGP or AGP card will be present as AGP VGA\r
+      //\r
+      if (!IS_PCI_VGA (&Pci)) {\r
+        continue;\r
+      }\r
+\r
+      //\r
+      // Set the device as the possible console out device,\r
+      //\r
+      // Below code will make every VGA device to be one\r
+      // of the possibe console out device\r
+      //\r
+      PlugInPciVga = TRUE;\r
+      gBS->HandleProtocol (\r
+             HandleBuffer[Index],\r
+             &gEfiDevicePathProtocolGuid,\r
+             (VOID**)&DevicePath\r
+             );\r
+\r
+      Index1 = 0;\r
+\r
+      while (gPlatformAllPossiblePciVgaConsole[Index1] != NULL) {\r
+        if (CompareMem (\r
+              DevicePath,\r
+              gPlatformAllPossiblePciVgaConsole[Index1],\r
+              GetDevicePathSize (gPlatformAllPossiblePciVgaConsole[Index1])\r
+              ) == 0) {\r
+\r
+          //\r
+          // This device is an AGP device\r
+          //\r
+          *OnboardPciVgaDevicePath = DevicePath;\r
+          PlugInPciVga = FALSE;\r
+          break;\r
+        }\r
+\r
+        Index1 ++;\r
+      }\r
+\r
+      if (PlugInPciVga) {\r
+        *PlugInPciVgaDevicePath = DevicePath;\r
+      }\r
+    }\r
+  }\r
+\r
+  FreePool (HandleBuffer);\r
+\r
+  return EFI_SUCCESS;\r
+}\r
+\r
+/**\r
+\r
+  Find the platform  active vga, and base on the policy to enable the vga as\r
+  the console out device. The policy is driven by one setup variable "VBIOS".\r
+\r
+  None.\r
+\r
+  @param EFI_UNSUPPORTED         There is no active vga device\r
+\r
+  @retval EFI_STATUS             Return the status of BdsLibGetVariableAndSize ()\r
+\r
+**/\r
+EFI_STATUS\r
+PlatformBdsForceActiveVga (\r
+  VOID\r
+  )\r
+{\r
+  EFI_STATUS                Status;\r
+  EFI_DEVICE_PATH_PROTOCOL  *PlugInPciVgaDevicePath;\r
+  EFI_DEVICE_PATH_PROTOCOL  *OnboardPciVgaDevicePath;\r
+  EFI_DEVICE_PATH_PROTOCOL  *DevicePathFirst;\r
+  EFI_DEVICE_PATH_PROTOCOL  *DevicePathSecond;\r
+  EFI_DEVICE_PATH_PROTOCOL  *GopDevicePath;\r
+  UINTN                VarSize;\r
+  SYSTEM_CONFIGURATION  mSystemConfiguration;\r
+\r
+  Status = EFI_SUCCESS;\r
+  PlugInPciVgaDevicePath = NULL;\r
+  OnboardPciVgaDevicePath = NULL;\r
+\r
+  //\r
+  // Check the policy which is the first enabled VGA\r
+  //\r
+  GetPlugInPciVgaDevicePath (&PlugInPciVgaDevicePath, &OnboardPciVgaDevicePath);\r
+\r
+  if (PlugInPciVgaDevicePath == NULL && OnboardPciVgaDevicePath == NULL) {\r
+    return EFI_UNSUPPORTED;\r
+  }\r
+\r
+  VarSize = sizeof(SYSTEM_CONFIGURATION);\r
+  Status = gRT->GetVariable(\r
+                  L"Setup",\r
+                  &gEfiNormalSetupGuid,\r
+                  NULL,\r
+                  &VarSize,\r
+                  &mSystemConfiguration\r
+                  );\r
+  ASSERT_EFI_ERROR (Status);\r
+\r
+\r
+  if ((PlugInPciVgaDevicePath == NULL && OnboardPciVgaDevicePath != NULL) ) {\r
+    DEBUG ((EFI_D_ERROR,"Update onboard PCI VGA ...\n"));\r
+    DevicePathFirst  = OnboardPciVgaDevicePath;\r
+    DevicePathSecond = PlugInPciVgaDevicePath;\r
+    goto UpdateConOut;\r
+  }\r
+  if(OnboardPciVgaDevicePath != NULL && mSystemConfiguration.PrimaryVideoAdaptor == 0) {\r
+    DEBUG ((EFI_D_ERROR,"Update onboard PCI VGA When set primary!!!...\n"));\r
+    DevicePathFirst  = OnboardPciVgaDevicePath;\r
+    DevicePathSecond = PlugInPciVgaDevicePath;\r
+    goto UpdateConOut;\r
+  }\r
+\r
+  DEBUG ((EFI_D_ERROR,"Update plug in PCI VGA ...\n"));\r
+  DevicePathFirst  = PlugInPciVgaDevicePath;\r
+  DevicePathSecond = OnboardPciVgaDevicePath;\r
+\r
+UpdateConOut:\r
+  GetGopDevicePath (DevicePathFirst, &GopDevicePath);\r
+  DevicePathFirst = GopDevicePath;\r
+\r
+  Status = BdsLibUpdateConsoleVariable (\r
+             L"ConOut",\r
+             DevicePathFirst,\r
+             DevicePathSecond\r
+             );\r
+\r
+  return Status;\r
+}\r
+\r
+VOID\r
+UpdateConsoleResolution(\r
+  VOID\r
+  )\r
+{\r
+  UINT32                 HorizontalResolution;\r
+  UINT32                 VerticalResolution;\r
+  SYSTEM_CONFIGURATION   SystemConfiguration;\r
+  UINTN                  VarSize;\r
+  EFI_STATUS             Status;\r
+\r
+\r
+  HorizontalResolution = PcdGet32 (PcdSetupVideoHorizontalResolution);\r
+  VerticalResolution = PcdGet32 (PcdSetupVideoVerticalResolution);\r
+\r
+  VarSize = sizeof(SYSTEM_CONFIGURATION);\r
+  Status = gRT->GetVariable(\r
+                  L"Setup",\r
+                  &gEfiNormalSetupGuid,\r
+                  NULL,\r
+                  &VarSize,\r
+                  &SystemConfiguration\r
+                  );\r
+  ASSERT_EFI_ERROR (Status);\r
+\r
+  switch (SystemConfiguration.IgdFlatPanel) {\r
+\r
+  case 0:\r
+    //\r
+    // Use the detault PCD values.\r
+    //\r
+    break;\r
+\r
+  case 1:\r
+    HorizontalResolution = 640;\r
+    VerticalResolution = 480;\r
+    break;\r
+\r
+  case 2:\r
+    HorizontalResolution = 800;\r
+    VerticalResolution = 600;\r
+    break;\r
+\r
+  case 3:\r
+    HorizontalResolution = 1024;\r
+    VerticalResolution = 768;\r
+    break;\r
+\r
+  case 4:\r
+  HorizontalResolution = 1280;\r
+  VerticalResolution = 1024;\r
+  break;\r
+\r
+  case 5:\r
+  HorizontalResolution = 1366;\r
+  VerticalResolution = 768;\r
+  break;\r
+\r
+  case 6:\r
+  HorizontalResolution = 1680;\r
+  VerticalResolution = 1050;\r
+  break;\r
+\r
+  case 7:\r
+  HorizontalResolution = 1920;\r
+  VerticalResolution = 1200;\r
+  break;\r
+\r
+  case 8:\r
+  HorizontalResolution = 1280;\r
+  VerticalResolution = 800;\r
+  break;\r
+  }\r
+\r
+  PcdSet32 (PcdSetupVideoHorizontalResolution, HorizontalResolution);\r
+  PcdSet32 (PcdSetupVideoVerticalResolution, VerticalResolution);\r
+  DEBUG ((EFI_D_ERROR, "HorizontalResolution = %x; VerticalResolution = %x", HorizontalResolution, VerticalResolution));\r
+\r
+  return;\r
+}\r
+\r
+/**\r
+  Connect the predefined platform default console device. Always try to find\r
+  and enable the vga device if have.\r
+\r
+  @param PlatformConsole    Predfined platform default console device array.\r
+\r
+  @retval EFI_SUCCESS       Success connect at least one ConIn and ConOut\r
+                            device, there must have one ConOut device is\r
+                            active vga device.\r
+\r
+  @retval EFI_STATUS        Return the status of\r
+                            BdsLibConnectAllDefaultConsoles ()\r
+\r
+**/\r
+EFI_STATUS\r
+PlatformBdsConnectConsole (\r
+  IN BDS_CONSOLE_CONNECT_ENTRY   *PlatformConsole\r
+)\r
+{\r
+  EFI_STATUS                         Status;\r
+  UINTN                              Index;\r
+  EFI_DEVICE_PATH_PROTOCOL           *VarConout;\r
+  EFI_DEVICE_PATH_PROTOCOL           *VarConin;\r
+  UINTN                              DevicePathSize;\r
+\r
+  UpdateConsoleResolution();\r
+\r
+  Index = 0;\r
+  Status = EFI_SUCCESS;\r
+  DevicePathSize = 0;\r
+  VarConout = BdsLibGetVariableAndSize (\r
+                L"ConOut",\r
+                &gEfiGlobalVariableGuid,\r
+                &DevicePathSize\r
+                );\r
+  VarConin = BdsLibGetVariableAndSize (\r
+               L"ConIn",\r
+               &gEfiGlobalVariableGuid,\r
+               &DevicePathSize\r
+               );\r
+  if (VarConout == NULL || VarConin == NULL) {\r
+    //\r
+    // Have chance to connect the platform default console,\r
+    // the platform default console is the minimue device group\r
+    // the platform should support\r
+    //\r
+    while (PlatformConsole[Index].DevicePath != NULL) {\r
+\r
+      //\r
+      // Update the console variable with the connect type\r
+      //\r
+      if ((PlatformConsole[Index].ConnectType & CONSOLE_IN) == CONSOLE_IN) {\r
+        BdsLibUpdateConsoleVariable (L"ConIn", PlatformConsole[Index].DevicePath, NULL);\r
+      }\r
+\r
+      if ((PlatformConsole[Index].ConnectType & CONSOLE_OUT) == CONSOLE_OUT) {\r
+        BdsLibUpdateConsoleVariable (L"ConOut", PlatformConsole[Index].DevicePath, NULL);\r
+      }\r
+\r
+      if ((PlatformConsole[Index].ConnectType & STD_ERROR) == STD_ERROR) {\r
+        BdsLibUpdateConsoleVariable (L"ErrOut", PlatformConsole[Index].DevicePath, NULL);\r
+      }\r
+\r
+      Index ++;\r
+    }\r
+  }\r
+\r
+  //\r
+  // Make sure we have at least one active VGA, and have the right\r
+  // active VGA in console variable\r
+  //\r
+  Status = PlatformBdsForceActiveVga ();\r
+  if (EFI_ERROR (Status)) {\r
+    return Status;\r
+  }\r
+\r
+  DEBUG ((EFI_D_INFO, "DISPLAY INIT DONE\n"));\r
+\r
+  //\r
+  // Connect the all the default console with current console variable\r
+  //\r
+  Status = BdsLibConnectAllDefaultConsoles ();\r
+  if (EFI_ERROR (Status)) {\r
+    return Status;\r
+  }\r
+\r
+  return EFI_SUCCESS;\r
+}\r
+\r
+/**\r
+  Connect with predeined platform connect sequence,\r
+  the OEM/IBV can customize with their own connect sequence.\r
+\r
+  @param None.\r
+\r
+  @retval None.\r
+\r
+**/\r
+VOID\r
+PlatformBdsConnectSequence (\r
+  VOID\r
+  )\r
+{\r
+  UINTN                     Index;\r
+\r
+  Index = 0;\r
+\r
+  //\r
+  // Here we can get the customized platform connect sequence\r
+  // Notes: we can connect with new variable which record the\r
+  // last time boots connect device path sequence\r
+  //\r
+  while (gPlatformConnectSequence[Index] != NULL) {\r
+\r
+    //\r
+    // Build the platform boot option\r
+    //\r
+    BdsLibConnectDevicePath (gPlatformConnectSequence[Index]);\r
+    Index ++;\r
+  }\r
+\r
+  //\r
+  // Just use the simple policy to connect all devices\r
+  // There should be no difference between debug tip and release tip, or it will be extremely hard to debug.\r
+  //\r
+  // There is case that IdeController driver will write boot script in driver model Start() function. It will be rejected by boot script save.\r
+  // It is only found when DEBUG disabled, because we are using BdsLibConnectAll() when DEBUG enabled.\r
+  //\r
+  // So we use BdsLibConnectAll() here to make sure IdeController.Start() is invoked before InstallReadyToLock().\r
+  // We may also consider to connect SataController only later if needed.\r
+  //\r
+  BdsLibConnectAll ();\r
+}\r
+\r
+/**\r
+\r
+  Load the predefined driver option, OEM/IBV can customize this\r
+  to load their own drivers\r
+\r
+  @param BdsDriverLists  The header of the driver option link list.\r
+\r
+  @retval None.\r
+\r
+**/\r
+VOID\r
+PlatformBdsGetDriverOption (\r
+  IN OUT LIST_ENTRY                  *BdsDriverLists\r
+  )\r
+{\r
+  UINTN                              Index;\r
+\r
+  Index = 0;\r
+\r
+  //\r
+  // Here we can get the customized platform driver option\r
+  //\r
+  while (gPlatformDriverOption[Index] != NULL) {\r
+\r
+    //\r
+    // Build the platform boot option\r
+    //\r
+    BdsLibRegisterNewOption (BdsDriverLists, gPlatformDriverOption[Index], NULL, L"DriverOrder");\r
+    Index ++;\r
+  }\r
+\r
+}\r
+\r
+/**\r
+  This function is used for some critical time if the the system\r
+  have no any boot option, and there is no time out for user to add\r
+  the new boot option. This can also treat as the platform default\r
+  boot option.\r
+\r
+  @param BdsBootOptionList   The header of the boot option link list.\r
+\r
+  @retval None.\r
+\r
+**/\r
+VOID\r
+PlatformBdsPredictBootOption (\r
+  IN OUT LIST_ENTRY                  *BdsBootOptionList\r
+  )\r
+{\r
+  UINTN                              Index;\r
+\r
+  Index = 0;\r
+\r
+  //\r
+  // Here give chance to get platform boot option data\r
+  //\r
+  while (gPlatformBootOption[Index] != NULL) {\r
+\r
+    //\r
+    // Build the platform boot option\r
+    //\r
+    BdsLibRegisterNewOption (BdsBootOptionList, gPlatformBootOption[Index], NULL, L"BootOrder");\r
+    Index ++;\r
+  }\r
+}\r
+\r
+/**\r
+  Perform the platform diagnostic, such like test memory. OEM/IBV also\r
+  can customize this fuction to support specific platform diagnostic.\r
+\r
+  @param MemoryTestLevel   The memory test intensive level\r
+  @param QuietBoot         Indicate if need to enable the quiet boot\r
+  @param BaseMemoryTest    A pointer to BdsMemoryTest()\r
+\r
+  @retval  None.\r
+\r
+**/\r
+VOID\r
+PlatformBdsDiagnostics (\r
+  IN EXTENDMEM_COVERAGE_LEVEL    MemoryTestLevel,\r
+  IN BOOLEAN                     QuietBoot,\r
+  IN BASEM_MEMORY_TEST           BaseMemoryTest\r
+  )\r
+{\r
+  EFI_STATUS                     Status;\r
+\r
+  //\r
+  // Here we can decide if we need to show\r
+  // the diagnostics screen\r
+  // Notes: this quiet boot code should be remove\r
+  // from the graphic lib\r
+  //\r
+  if (QuietBoot) {\r
+    EnableQuietBoot (PcdGetPtr(PcdLogoFile));\r
+\r
+    //\r
+    // Perform system diagnostic\r
+    //\r
+    Status = BaseMemoryTest (MemoryTestLevel);\r
+    if (EFI_ERROR (Status)) {\r
+      DisableQuietBoot ();\r
+    }\r
+\r
+    return;\r
+  }\r
+\r
+  //\r
+  // Perform system diagnostic\r
+  //\r
+  Status = BaseMemoryTest (MemoryTestLevel);\r
+}\r
+\r
+\r
+/**\r
+\r
+  The function will excute with as the platform policy, current policy\r
+  is driven by boot mode. IBV/OEM can customize this code for their specific\r
+  policy action.\r
+\r
+  @param DriverOptionList - The header of the driver option link list\r
+  @param  BootOptionList   - The header of the boot option link list\r
+  @param ProcessCapsules  - A pointer to ProcessCapsules()\r
+  @param BaseMemoryTest   - A pointer to BaseMemoryTest()\r
+\r
+  @retval None.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+PlatformBdsPolicyBehavior (\r
+  IN OUT LIST_ENTRY                  *DriverOptionList,\r
+  IN OUT LIST_ENTRY                  *BootOptionList,\r
+  IN PROCESS_CAPSULES                ProcessCapsules,\r
+  IN BASEM_MEMORY_TEST               BaseMemoryTest\r
+  )\r
+{\r
+  EFI_STATUS                         Status;\r
+  UINT16                             Timeout;\r
+  EFI_BOOT_MODE                      BootMode;\r
+  BOOLEAN                            DeferredImageExist;\r
+  UINTN                              Index;\r
+  CHAR16                             CapsuleVarName[36];\r
+  CHAR16                             *TempVarName;\r
+  SYSTEM_CONFIGURATION               SystemConfiguration;\r
+  UINTN                              VarSize;\r
+  BOOLEAN                            SetVariableFlag;\r
+  PLATFORM_PCI_DEVICE_PATH           *EmmcBootDevPath;\r
+  EFI_GLOBAL_NVS_AREA_PROTOCOL       *GlobalNvsArea;\r
+  EFI_HANDLE                         FvProtocolHandle;\r
+  UINTN                              HandleCount;\r
+  EFI_HANDLE                         *HandleBuffer;\r
+  UINTN                              Index1;\r
+  UINTN                              SataPciRegBase = 0;\r
+  UINT16                             SataModeSelect = 0;\r
+  VOID                               *RegistrationExitPmAuth = NULL;\r
+  EFI_EVENT                          Event;\r
+  BOOLEAN                            IsFirstBoot;\r
+  UINT16                             *BootOrder;\r
+  UINTN                              BootOrderSize;\r
+\r
+  Timeout = PcdGet16 (PcdPlatformBootTimeOut);\r
+  VarSize = sizeof(SYSTEM_CONFIGURATION);\r
+  Status = gRT->GetVariable(\r
+                  NORMAL_SETUP_NAME,\r
+                  &gEfiNormalSetupGuid,\r
+                  NULL,\r
+                  &VarSize,\r
+                  &SystemConfiguration\r
+                  );\r
+  if (EFI_ERROR (Status)) {\r
+    return;\r
+  }\r
+\r
+  //\r
+  // Load the driver option as the driver option list\r
+  //\r
+  PlatformBdsGetDriverOption (DriverOptionList);\r
+\r
+  //\r
+  // Get current Boot Mode\r
+  //\r
+  BootMode = GetBootModeHob();\r
+\r
+  //\r
+  // Clear all the capsule variables CapsuleUpdateData, CapsuleUpdateData1, CapsuleUpdateData2...\r
+  // as early as possible which will avoid the next time boot after the capsule update\r
+  // will still into the capsule loop\r
+  //\r
+  StrCpy (CapsuleVarName, EFI_CAPSULE_VARIABLE_NAME);\r
+  TempVarName = CapsuleVarName + StrLen (CapsuleVarName);\r
+  Index = 0;\r
+  SetVariableFlag = TRUE;\r
+  while (SetVariableFlag) {\r
+    if (Index > 0) {\r
+      UnicodeValueToString (TempVarName, 0, Index, 0);\r
+    }\r
+    Status = gRT->SetVariable (\r
+                    CapsuleVarName,\r
+                    &gEfiCapsuleVendorGuid,\r
+                    EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_RUNTIME_ACCESS |\r
+                    EFI_VARIABLE_BOOTSERVICE_ACCESS,\r
+                    0,\r
+                    (VOID *)NULL\r
+                    );\r
+    if (EFI_ERROR (Status)) {\r
+      //\r
+      // There is no capsule variables, quit\r
+      //\r
+      SetVariableFlag = FALSE;\r
+      continue;\r
+    }\r
+    Index++;\r
+  }\r
+\r
+  //\r
+  // No deferred images exist by default\r
+  //\r
+  DeferredImageExist = FALSE;\r
+  if ((BootMode != BOOT_WITH_MINIMAL_CONFIGURATION) && (PcdGet32(PcdFlashFvShellSize) > 0)){\r
+    gDS->ProcessFirmwareVolume (\r
+           (VOID *)(UINTN)PcdGet32(PcdFlashFvShellBase),\r
+           PcdGet32(PcdFlashFvShellSize),\r
+           &FvProtocolHandle\r
+           );\r
+  }\r
+\r
+  if (SystemConfiguration.FastBoot == 1) {\r
+    BootOrder = BdsLibGetVariableAndSize (\r
+                  L"BootOrder",\r
+                  &gEfiGlobalVariableGuid,\r
+                  &BootOrderSize\r
+                  );\r
+    if ((BootOrder != NULL) && (BootMode != BOOT_ON_FLASH_UPDATE)) {\r
+      //\r
+      // BootOrder exist, it means system has boot before. We can do fast boot.\r
+      //\r
+      BootMode = BOOT_WITH_MINIMAL_CONFIGURATION;\r
+    }\r
+  }\r
+\r
+\r
+  //\r
+  // Use eMMC to boot OS and turn on AHCI, when SATA HDD is diconnected,\r
+  // SATA AHCI CTLR device will show yellow bang, implement this solution to solve it.\r
+  //\r
+  SataPciRegBase  = MmPciAddress (0, 0, PCI_DEVICE_NUMBER_PCH_SATA, 0, 0);\r
+  SataModeSelect  = MmioRead16 (SataPciRegBase + R_PCH_SATA_MAP) & B_PCH_SATA_MAP_SMS_MASK;\r
+  Status          = EFI_SUCCESS;\r
+  if (SataModeSelect != V_PCH_SATA_MAP_SMS_IDE) {\r
+    Status = gBS->CreateEvent (\r
+                    EVT_NOTIFY_SIGNAL,\r
+                    TPL_CALLBACK,\r
+                    DisableAhciCtlr,\r
+                    &SataPciRegBase,\r
+                    &Event\r
+                     );\r
+    if (!EFI_ERROR (Status)) {\r
+      Status = gBS->RegisterProtocolNotify (\r
+                      &gExitPmAuthProtocolGuid,\r
+                      Event,\r
+                      &RegistrationExitPmAuth\r
+                      );\r
+    }\r
+  }\r
+\r
+  switch (BootMode) {\r
+\r
+  case BOOT_WITH_MINIMAL_CONFIGURATION:\r
+    PlatformBdsInitHotKeyEvent ();\r
+    PlatformBdsConnectSimpleConsole (gPlatformSimpleConsole);\r
+\r
+\r
+    //\r
+    // Check to see if it's needed to dispatch more DXE drivers.\r
+    //\r
+    for (Index = 0; Index < sizeof(ConnectDriverTable)/sizeof(EFI_GUID *); Index++) {\r
+      Status = gBS->LocateHandleBuffer (\r
+                      ByProtocol,\r
+                      ConnectDriverTable[Index],\r
+                      NULL,\r
+                      &HandleCount,\r
+                      &HandleBuffer\r
+                      );\r
+      if (!EFI_ERROR (Status)) {\r
+        for (Index1 = 0; Index1 < HandleCount; Index1++) {\r
+          gBS->ConnectController (\r
+                 HandleBuffer[Index1],\r
+                 NULL,\r
+                 NULL,\r
+                 TRUE\r
+                 );\r
+        }\r
+      }\r
+\r
+      if (HandleBuffer != NULL) {\r
+        FreePool (HandleBuffer);\r
+      }\r
+\r
+      gDS->Dispatch ();\r
+    }\r
+\r
+    //\r
+    //  Locate the Global NVS Protocol.\r
+    //\r
+    Status = gBS->LocateProtocol (\r
+                    &gEfiGlobalNvsAreaProtocolGuid,\r
+                    NULL,\r
+                    (void **)&GlobalNvsArea\r
+                    );\r
+    if (GlobalNvsArea->Area->emmcVersion == 0){\r
+      EmmcBootDevPath = (PLATFORM_PCI_DEVICE_PATH *)gPlatformSimpleBootOption[0];\r
+      EmmcBootDevPath->PciDevice.Device = 0x10;\r
+    }\r
+\r
+    //\r
+    // Connect boot device here to give time to read keyboard.\r
+    //\r
+    BdsLibConnectDevicePath (gPlatformSimpleBootOption[0]);\r
+\r
+    //\r
+    // This is a workround for dectecting hotkey from USB keyboard.\r
+    //\r
+    gBS->Stall(KEYBOARD_TIMER_INTERVAL);\r
+\r
+    if (mHotKeyTimerEvent != NULL) {\r
+      gBS->SetTimer (\r
+             mHotKeyTimerEvent,\r
+             TimerCancel,\r
+             0\r
+             );\r
+      gBS->CloseEvent (mHotKeyTimerEvent);\r
+      mHotKeyTimerEvent = NULL;\r
+    }\r
+    if (mHotKeyPressed) {\r
+      //\r
+      // Skip show progress count down\r
+      //\r
+      Timeout = 0xFFFF;\r
+      goto FULL_CONFIGURATION;\r
+    }\r
+\r
+    if (SystemConfiguration.QuietBoot) {\r
+      EnableQuietBoot (PcdGetPtr(PcdLogoFile));\r
+    } else {\r
+      PlatformBdsDiagnostics (IGNORE, FALSE, BaseMemoryTest);\r
+    }\r
+\r
+\r
+#ifdef TPM_ENABLED\r
+       TcgPhysicalPresenceLibProcessRequest();\r
+#endif\r
+\r
+    //\r
+    // Close boot script and install ready to lock\r
+    //\r
+    InstallReadyToLock ();\r
+\r
+    //\r
+    // Give one chance to enter the setup if we \r
+    // select Gummiboot "Reboot Into Firmware Interface" and Fast Boot is enabled.\r
+    //\r
+    BootIntoFirmwareInterface();\r
+    break;\r
+\r
+  case BOOT_ASSUMING_NO_CONFIGURATION_CHANGES:\r
+\r
+    //\r
+    // In no-configuration boot mode, we can connect the\r
+    // console directly.\r
+    //\r
+    BdsLibConnectAllDefaultConsoles ();\r
+    PlatformBdsDiagnostics (IGNORE, TRUE, BaseMemoryTest);\r
+\r
+    //\r
+    // Perform some platform specific connect sequence\r
+    //\r
+    PlatformBdsConnectSequence ();\r
+\r
+    //\r
+    // As console is ready, perform user identification again.\r
+    //\r
+    if (mCurrentUser == NULL) {\r
+      PlatformBdsUserIdentify (&mCurrentUser, &DeferredImageExist);\r
+      if (DeferredImageExist) {\r
+        //\r
+        // After user authentication, the deferred drivers was loaded again.\r
+        // Here, need to ensure the deferred images are connected.\r
+        //\r
+        BdsLibConnectAllDefaultConsoles ();\r
+        PlatformBdsConnectSequence ();\r
+      }\r
+    }\r
+\r
+    //\r
+    // Close boot script and install ready to lock\r
+    //\r
+    InstallReadyToLock ();\r
+\r
+    //\r
+    // Notes: current time out = 0 can not enter the\r
+    // front page\r
+    //\r
+    PlatformBdsEnterFrontPageWithHotKey (Timeout, FALSE);\r
+\r
+    //\r
+    // Check the boot option with the boot option list\r
+    //\r
+    BdsLibBuildOptionFromVar (BootOptionList, L"BootOrder");\r
+    break;\r
+\r
+  case BOOT_ON_FLASH_UPDATE:\r
+\r
+    //\r
+    // Boot with the specific configuration\r
+    //\r
+    PlatformBdsConnectConsole (gPlatformConsole);\r
+    PlatformBdsDiagnostics (EXTENSIVE, FALSE, BaseMemoryTest);\r
+    BdsLibConnectAll ();\r
+\r
+    //\r
+    // Perform user identification\r
+    //\r
+    if (mCurrentUser == NULL) {\r
+      PlatformBdsUserIdentify (&mCurrentUser, &DeferredImageExist);\r
+      if (DeferredImageExist) {\r
+        //\r
+        // After user authentication, the deferred drivers was loaded again.\r
+        // Here, need to ensure the deferred images are connected.\r
+        //\r
+        BdsLibConnectAll ();\r
+      }\r
+    }\r
+\r
+    //\r
+    // Close boot script and install ready to lock\r
+    //\r
+    InstallReadyToLock ();\r
+\r
+    ProcessCapsules (BOOT_ON_FLASH_UPDATE);\r
+    break;\r
+\r
+  case BOOT_IN_RECOVERY_MODE:\r
+\r
+    //\r
+    // In recovery mode, just connect platform console\r
+    // and show up the front page\r
+    //\r
+    PlatformBdsConnectConsole (gPlatformConsole);\r
+    PlatformBdsDiagnostics (EXTENSIVE, FALSE, BaseMemoryTest);\r
+    BdsLibConnectAll ();\r
+\r
+    //\r
+    // Perform user identification\r
+    //\r
+    if (mCurrentUser == NULL) {\r
+      PlatformBdsUserIdentify (&mCurrentUser, &DeferredImageExist);\r
+      if (DeferredImageExist) {\r
+        //\r
+        // After user authentication, the deferred drivers was loaded again.\r
+        // Here, need to ensure the deferred drivers are connected.\r
+        //\r
+        BdsLibConnectAll ();\r
+      }\r
+    }\r
+\r
+    //\r
+    // Close boot script and install ready to lock\r
+    //\r
+    InstallReadyToLock ();\r
+\r
+    //\r
+    // In recovery boot mode, we still enter to the\r
+    // frong page now\r
+    //\r
+    PlatformBdsEnterFrontPageWithHotKey (Timeout, FALSE);\r
+    break;\r
+\r
+FULL_CONFIGURATION:\r
+  case BOOT_WITH_FULL_CONFIGURATION:\r
+  case BOOT_WITH_FULL_CONFIGURATION_PLUS_DIAGNOSTICS:\r
+  case BOOT_WITH_DEFAULT_SETTINGS:\r
+  default:\r
+\r
+    //\r
+    // Connect platform console\r
+    //\r
+    Status = PlatformBdsConnectConsole (gPlatformConsole);\r
+    if (EFI_ERROR (Status)) {\r
+\r
+      //\r
+      // Here OEM/IBV can customize with defined action\r
+      //\r
+      PlatformBdsNoConsoleAction ();\r
+    }\r
+\r
+    //\r
+    // Chenyunh[TODO]: This is Workgroud to show the fs for uSDcard,\r
+    // Need to root cause this issue.\r
+    //\r
+    DEBUG ((DEBUG_ERROR, "Start to reconnect all driver.\n"));\r
+    BdsLibDisconnectAllEfi();\r
+    BdsLibConnectAll ();\r
+    DEBUG ((DEBUG_ERROR, "End to reconnect all driver.\n"));\r
+\r
+    //\r
+    // Perform some platform specific connect sequence\r
+    //\r
+    PlatformBdsConnectSequence ();\r
+    if (SystemConfiguration.QuietBoot) {\r
+        EnableQuietBoot (PcdGetPtr(PcdLogoFile));\r
+    } else {\r
+        PlatformBdsDiagnostics (IGNORE, FALSE, BaseMemoryTest);\r
+    }\r
+\r
+    //\r
+    // Do a pre-delay so Hard Disk can spin up and see more logo.\r
+    //\r
+    gBS->Stall(SystemConfiguration.HddPredelay * 1000000);\r
+\r
+    //\r
+    // Perform user identification\r
+    //\r
+    if (mCurrentUser == NULL) {\r
+      PlatformBdsUserIdentify (&mCurrentUser, &DeferredImageExist);\r
+      if (DeferredImageExist) {\r
+        //\r
+        // After user authentication, the deferred drivers was loaded again.\r
+        // Here, need to ensure the deferred drivers are connected.\r
+        //\r
+        Status = PlatformBdsConnectConsole (gPlatformConsole);\r
+        if (EFI_ERROR (Status)) {\r
+          PlatformBdsNoConsoleAction ();\r
+        }\r
+        PlatformBdsConnectSequence ();\r
+      }\r
+    }\r
+#ifdef TPM_ENABLED\r
+   TcgPhysicalPresenceLibProcessRequest();\r
+#endif\r
+\r
+    //\r
+    // Close boot script and install ready to lock\r
+    //\r
+    InstallReadyToLock ();\r
+\r
+    //\r
+    // Give one chance to enter the setup if we\r
+    // have the time out\r
+    //\r
+    PlatformBdsEnterFrontPageWithHotKey (Timeout, FALSE);\r
+\r
+       //\r
+       // Give one chance to enter the setup if we \r
+       // select Gummiboot "Reboot Into Firmware Interface"\r
+       //\r
+       BootIntoFirmwareInterface();\r
+\r
+    //\r
+    // In default boot mode, always find all boot\r
+    // option and do enumerate all the default boot option\r
+    //\r
+    if (Timeout == 0) {\r
+      BdsLibBuildOptionFromVar (BootOptionList, L"BootOrder");\r
+      if (IsListEmpty(BootOptionList)) {\r
+        PlatformBdsPredictBootOption (BootOptionList);\r
+      }\r
+\r
+      return;\r
+    }\r
+\r
+    //\r
+    // Here we have enough time to do the enumeration of boot device\r
+    //\r
+    BdsLibEnumerateAllBootOption (BootOptionList);\r
+    break;\r
+  }\r
+\r
+\r
+  IsFirstBoot = PcdGetBool(PcdBootState);\r
+  if (IsFirstBoot) {\r
+    PcdSetBool(PcdBootState, FALSE);\r
+  }\r
+  return;\r
+\r
+}\r
+\r
+/**\r
+  Hook point after a boot attempt succeeds. We don't expect a boot option to\r
+  return, so the UEFI 2.0 specification defines that you will default to an\r
+  interactive mode and stop processing the BootOrder list in this case. This\r
+  is alos a platform implementation and can be customized by IBV/OEM.\r
+\r
+  @param Option  Pointer to Boot Option that succeeded to boot.\r
+\r
+  @retval None.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+PlatformBdsBootSuccess (\r
+  IN  BDS_COMMON_OPTION *Option\r
+  )\r
+{\r
+  CHAR16  *TmpStr;\r
+\r
+  //\r
+  // If Boot returned with EFI_SUCCESS and there is not in the boot device\r
+  // select loop then we need to pop up a UI and wait for user input.\r
+  //\r
+  TmpStr =  Option->StatusString;\r
+  if (TmpStr != NULL) {\r
+    BdsLibOutputStrings (gST->ConOut, TmpStr, Option->Description, L"\n\r", NULL);\r
+    FreePool(TmpStr);\r
+  }\r
+}\r
+\r
+/**\r
+  Hook point after a boot attempt fails.\r
+\r
+  @param Option - Pointer to Boot Option that failed to boot.\r
+  @param Status - Status returned from failed boot.\r
+  @param ExitData - Exit data returned from failed boot.\r
+  @param ExitDataSize - Exit data size returned from failed boot.\r
+\r
+  @retval None.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+PlatformBdsBootFail (\r
+  IN  BDS_COMMON_OPTION  *Option,\r
+  IN  EFI_STATUS         Status,\r
+  IN  CHAR16             *ExitData,\r
+  IN  UINTN              ExitDataSize\r
+  )\r
+{\r
+  CHAR16          *TmpStr;\r
+  EFI_HANDLE      FvProtocolHandle;\r
+\r
+  //\r
+  // If Boot returned with failed status then we need to pop up a UI and wait\r
+  // for user input.\r
+  //\r
+  TmpStr = Option->StatusString;\r
+  if (TmpStr != NULL) {\r
+    BdsLibOutputStrings (gST->ConOut, TmpStr, Option->Description, L"\n\r", NULL);\r
+    FreePool(TmpStr);\r
+  }\r
+  if (PcdGet32(PcdFlashFvShellSize) > 0){\r
+    gDS->ProcessFirmwareVolume (\r
+           (VOID *)(UINTN)PcdGet32(PcdFlashFvShellBase),\r
+           PcdGet32(PcdFlashFvShellSize),\r
+           &FvProtocolHandle\r
+           );\r
+  }\r
+  PlatformBdsConnectSequence ();\r
+}\r
+\r
+/**\r
+  This function is remained for IBV/OEM to do some platform action,\r
+  if there no console device can be connected.\r
+\r
+  @param  None.\r
+\r
+  @retval EFI_SUCCESS       Direct return success now.\r
+\r
+**/\r
+EFI_STATUS\r
+PlatformBdsNoConsoleAction (\r
+  VOID\r
+  )\r
+{\r
+  return EFI_SUCCESS;\r
+}\r
+\r
+/**\r
+  This function locks the block\r
+\r
+  @param Base            The base address flash region to be locked.\r
+\r
+**/\r
+VOID\r
+BdsLockFv (\r
+  IN EFI_PHYSICAL_ADDRESS  Base\r
+  )\r
+{\r
+  EFI_FV_BLOCK_MAP_ENTRY      *BlockMap;\r
+  EFI_FIRMWARE_VOLUME_HEADER  *FvHeader;\r
+  EFI_PHYSICAL_ADDRESS        BaseAddress;\r
+  UINT8                       Data;\r
+  UINT32                      BlockLength;\r
+  UINTN                       Index;\r
+\r
+  BaseAddress = Base - 0x400000 + 2;\r
+  FvHeader    = (EFI_FIRMWARE_VOLUME_HEADER *) ((UINTN) (Base));\r
+  BlockMap    = &(FvHeader->BlockMap[0]);\r
+\r
+  while ((BlockMap->NumBlocks != 0) && (BlockMap->Length != 0)) {\r
+    BlockLength = BlockMap->Length;\r
+    for (Index = 0; Index < BlockMap->NumBlocks; Index++) {\r
+      Data = MmioOr8 ((UINTN) BaseAddress, 0x03);\r
+      BaseAddress += BlockLength;\r
+    }\r
+    BlockMap++;\r
+  }\r
+}\r
+\r
+VOID\r
+EFIAPI\r
+PlatformBdsLockNonUpdatableFlash (\r
+  VOID\r
+  )\r
+{\r
+  EFI_PHYSICAL_ADDRESS  Base;\r
+\r
+  Base = (EFI_PHYSICAL_ADDRESS) PcdGet32 (PcdFlashFvMainBase);\r
+  if (Base > 0) {\r
+    BdsLockFv (Base);\r
+  }\r
+\r
+  Base = (EFI_PHYSICAL_ADDRESS) PcdGet32 (PcdFlashFvRecoveryBase);\r
+  if (Base > 0) {\r
+    BdsLockFv (Base);\r
+  }\r
+}\r
+\r
+/**\r
+  Lock the ConsoleIn device in system table. All key\r
+  presses will be ignored until the Password is typed in. The only way to\r
+  disable the password is to type it in to a ConIn device.\r
+\r
+  @param  Password        Password used to lock ConIn device.\r
+\r
+  @retval EFI_SUCCESS     lock the Console In Spliter virtual handle successfully.\r
+  @retval EFI_UNSUPPORTED Password not found\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+LockKeyboards (\r
+  IN  CHAR16    *Password\r
+  )\r
+{\r
+    return EFI_UNSUPPORTED;\r
+}\r
+\r
+/**\r
+  Connect the predefined platform default authentication devices.\r
+\r
+  This function connects the predefined device path for authentication device,\r
+  and if the predefined device path has child device path, the child handle will\r
+  be connected too. But the child handle of the child will not be connected.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+PlatformBdsConnectAuthDevice (\r
+  VOID\r
+  )\r
+{\r
+  EFI_STATUS                   Status;\r
+  UINTN                        Index;\r
+  UINTN                        HandleIndex;\r
+  UINTN                        HandleCount;\r
+  EFI_HANDLE                   *HandleBuffer;\r
+  EFI_DEVICE_PATH_PROTOCOL     *ChildDevicePath;\r
+  EFI_USER_MANAGER_PROTOCOL    *Manager;\r
+\r
+  Status = gBS->LocateProtocol (\r
+                  &gEfiUserManagerProtocolGuid,\r
+                  NULL,\r
+                  (VOID **) &Manager\r
+                  );\r
+  if (EFI_ERROR (Status)) {\r
+    //\r
+    // As user manager protocol is not installed, the authentication devices\r
+    // should not be connected.\r
+    //\r
+    return ;\r
+  }\r
+\r
+  Index = 0;\r
+  while (gUserAuthenticationDevice[Index] != NULL) {\r
+    //\r
+    // Connect the platform customized device paths\r
+    //\r
+    BdsLibConnectDevicePath (gUserAuthenticationDevice[Index]);\r
+    Index++;\r
+  }\r
+\r
+  //\r
+  // Find and connect the child device paths of the platform customized device paths\r
+  //\r
+  HandleBuffer = NULL;\r
+  for (Index = 0; gUserAuthenticationDevice[Index] != NULL; Index++) {\r
+    HandleCount = 0;\r
+    Status = gBS->LocateHandleBuffer (\r
+                    AllHandles,\r
+                    NULL,\r
+                    NULL,\r
+                    &HandleCount,\r
+                    &HandleBuffer\r
+                    );\r
+    ASSERT (!EFI_ERROR (Status));\r
+\r
+    //\r
+    // Find and connect the child device paths of gUserIdentificationDevice[Index]\r
+    //\r
+    for (HandleIndex = 0; HandleIndex < HandleCount; HandleIndex++) {\r
+      ChildDevicePath = NULL;\r
+      Status = gBS->HandleProtocol (\r
+                      HandleBuffer[HandleIndex],\r
+                      &gEfiDevicePathProtocolGuid,\r
+                      (VOID **) &ChildDevicePath\r
+                      );\r
+      if (EFI_ERROR (Status) || ChildDevicePath == NULL) {\r
+        continue;\r
+      }\r
+\r
+      if (CompareMem (\r
+            ChildDevicePath,\r
+            gUserAuthenticationDevice[Index],\r
+            (GetDevicePathSize (gUserAuthenticationDevice[Index]) - sizeof (EFI_DEVICE_PATH_PROTOCOL))\r
+            ) != 0) {\r
+        continue;\r
+      }\r
+      gBS->ConnectController (\r
+             HandleBuffer[HandleIndex],\r
+             NULL,\r
+             NULL,\r
+             TRUE\r
+             );\r
+    }\r
+  }\r
+\r
+  if (HandleBuffer != NULL) {\r
+    FreePool (HandleBuffer);\r
+  }\r
+}\r
+\r
+/**\r
+  This function is to identify a user, and return whether deferred images exist.\r
+\r
+  @param[out]  User               Point to user profile handle.\r
+  @param[out]  DeferredImageExist On return, points to TRUE if the deferred image\r
+                                  exist or FALSE if it did not exist.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+PlatformBdsUserIdentify (\r
+  OUT EFI_USER_PROFILE_HANDLE        *User,\r
+  OUT BOOLEAN                        *DeferredImageExist\r
+  )\r
+{\r
+  EFI_STATUS                         Status;\r
+  EFI_DEFERRED_IMAGE_LOAD_PROTOCOL   *DeferredImage;\r
+  UINTN                              HandleCount;\r
+  EFI_HANDLE                         *HandleBuf;\r
+  UINTN                              Index;\r
+  UINTN                              DriverIndex;\r
+  EFI_DEVICE_PATH_PROTOCOL           *ImageDevicePath;\r
+  VOID                               *DriverImage;\r
+  UINTN                              ImageSize;\r
+  BOOLEAN                            BootOption;\r
+\r
+  //\r
+  // Perform user identification\r
+  //\r
+  do {\r
+    Status = BdsLibUserIdentify (User);\r
+  } while (EFI_ERROR (Status));\r
+\r
+  //\r
+  // After user authentication now, try to find whether deferred image exists\r
+  //\r
+  HandleCount = 0;\r
+  HandleBuf   = NULL;\r
+  *DeferredImageExist = FALSE;\r
+  Status = gBS->LocateHandleBuffer (\r
+                  ByProtocol,\r
+                  &gEfiDeferredImageLoadProtocolGuid,\r
+                  NULL,\r
+                  &HandleCount,\r
+                  &HandleBuf\r
+                  );\r
+  if (EFI_ERROR (Status)) {\r
+    return ;\r
+  }\r
+\r
+  for (Index = 0; Index < HandleCount; Index++) {\r
+    Status = gBS->HandleProtocol (\r
+                    HandleBuf[Index],\r
+                    &gEfiDeferredImageLoadProtocolGuid,\r
+                    (VOID **) &DeferredImage\r
+                    );\r
+    if (!EFI_ERROR (Status)) {\r
+      //\r
+      // Find whether deferred image exists in this instance.\r
+      //\r
+      DriverIndex = 0;\r
+      Status = DeferredImage->GetImageInfo(\r
+                                DeferredImage,\r
+                                DriverIndex,\r
+                                &ImageDevicePath,\r
+                                (VOID **) &DriverImage,\r
+                                &ImageSize,\r
+                                &BootOption\r
+                                );\r
+      if (!EFI_ERROR (Status)) {\r
+        //\r
+        // The deferred image is found.\r
+        //\r
+        FreePool (HandleBuf);\r
+        *DeferredImageExist = TRUE;\r
+        return ;\r
+      }\r
+    }\r
+  }\r
+\r
+  FreePool (HandleBuf);\r
+}\r
+\r
+UINTN gHotKey = 0;\r
+\r
+\r
+EFI_STATUS\r
+ShowProgressHotKey (\r
+  IN UINT16                       TimeoutDefault\r
+  )\r
+{\r
+  CHAR16                        *TmpStr;\r
+  UINT16                        TimeoutRemain;\r
+  EFI_STATUS                    Status;\r
+  EFI_INPUT_KEY                 Key;\r
+  EFI_GRAPHICS_OUTPUT_BLT_PIXEL Foreground;\r
+  EFI_GRAPHICS_OUTPUT_BLT_PIXEL Background;\r
+  EFI_GRAPHICS_OUTPUT_BLT_PIXEL Color;\r
+  UINT32                        GpioValue;\r
+\r
+  if (TimeoutDefault == 0) {\r
+    return EFI_TIMEOUT;\r
+  }\r
+\r
+  if (DebugAssertEnabled())\r
+  {\r
+    DEBUG ((EFI_D_INFO, "\n\nStart showing progress bar... Press any key to stop it, or press <F2> or <DEL> to enter setup page! ...Zzz....\n"));\r
+  }\r
+  else\r
+  {  \r
+    #ifdef __GNUC__\r
+    SerialPortWrite((UINT8 *)"\n\n>>>>Start boot option, Press <F2> or <DEL> to enter setup page(5 Sec)[GCC]", 76);\r
+    #else\r
+    SerialPortWrite((UINT8 *)"\n\n>>>>Start boot option, Press <F2> or <DEL> to enter setup page(5 Sec)", 71);\r
+    #endif\r
+  } \r
+  SetMem (&Foreground, sizeof (EFI_GRAPHICS_OUTPUT_BLT_PIXEL), 0xff);\r
+  SetMem (&Background, sizeof (EFI_GRAPHICS_OUTPUT_BLT_PIXEL), 0x0);\r
+  SetMem (&Color, sizeof (EFI_GRAPHICS_OUTPUT_BLT_PIXEL), 0xff);\r
+\r
+  //\r
+  // Clear the progress status bar first\r
+  //\r
+  TmpStr = L"Start boot option, Press <F2> or <DEL> to enter setup page.";\r
+  PlatformBdsShowProgress (Foreground, Background, TmpStr, Color, 0, 0);\r
+\r
+  TimeoutRemain = TimeoutDefault;\r
+  while (TimeoutRemain != 0) {\r
+    if (DebugAssertEnabled())\r
+    {\r
+    DEBUG ((EFI_D_INFO, "Showing progress bar...Remaining %d second!\n", TimeoutRemain));\r
+    }\r
+    else\r
+    {  \r
+    SerialPortWrite ((UINT8 *)".", 1);\r
+    }\r
+    Status = WaitForSingleEvent (gST->ConIn->WaitForKey, ONE_SECOND);\r
+    if (Status != EFI_TIMEOUT) {\r
+      break;\r
+    }\r
+    TimeoutRemain--;\r
+\r
+    //\r
+    // Show progress\r
+    //\r
+    if (TmpStr != NULL) {\r
+      PlatformBdsShowProgress (\r
+        Foreground,\r
+        Background,\r
+        TmpStr,\r
+        Color,\r
+        ((TimeoutDefault - TimeoutRemain) * 100 / TimeoutDefault),\r
+        0\r
+        );\r
+    }\r
+  }\r
+\r
+  //\r
+  // Timeout expired\r
+  //\r
+  if (TimeoutRemain == 0) {\r
+    if (DebugAssertEnabled())\r
+       {\r
+       }\r
+    else\r
+    {  \r
+    SerialPortWrite ((UINT8 *)"\r\n", 2);\r
+    }\r
+    return EFI_TIMEOUT;\r
+  }\r
+\r
+  //\r
+  // User pressed some key\r
+  //\r
+  Status = gST->ConIn->ReadKeyStroke (gST->ConIn, &Key);\r
+  if (EFI_ERROR (Status)) {\r
+    return Status;\r
+  }\r
+\r
+  //\r
+  // Check Volume Up Key to enter Setup\r
+  //\r
+  GpioValue = MmioRead32 (IO_BASE_ADDRESS + 0x0668);  // The value of GPIOC_5\r
+  if (((GpioValue & BIT0) == 0) && (Key.ScanCode == SCAN_UP)) {\r
+    gHotKey = 0;\r
+    return EFI_SUCCESS;\r
+  }\r
+\r
+  if (Key.UnicodeChar == CHAR_CARRIAGE_RETURN) {\r
+    //\r
+    // User pressed enter, equivalent to select "continue"\r
+    //\r
+    return EFI_TIMEOUT;\r
+  }\r
+\r
+  //\r
+  //F2 --  Front Page\r
+  //F5 --  Device Manager\r
+  //F7 --  Boot Manager\r
+  // do not use F8. generally people assume it is windows safe mode key.\r
+  //F9 --  Boot order\r
+  //\r
+  DEBUG ((EFI_D_INFO, "[Key Pressed]: ScanCode 0x%x\n", Key.ScanCode));\r
+  switch(Key.ScanCode) {\r
+      case SCAN_F2:\r
+          gHotKey = 0;\r
+          break;\r
+\r
+      case SCAN_DELETE:\r
+          gHotKey = 0;\r
+          break;\r
+\r
+      case SCAN_F5:\r
+          gHotKey = FRONT_PAGE_KEY_DEVICE_MANAGER;\r
+          break;\r
+\r
+      case SCAN_F7:\r
+          gHotKey = FRONT_PAGE_KEY_BOOT_MANAGER;\r
+          break;\r
+\r
+      case SCAN_F9:\r
+          gHotKey = FRONT_PAGE_KEY_BOOT_MAINTAIN;\r
+          break;\r
+\r
+      default:\r
+          //set gHotKey to continue so that flow will not go into CallFrontPage\r
+          gHotKey = FRONT_PAGE_KEY_CONTINUE;\r
+          return EFI_TIMEOUT;\r
+          break;\r
+  }\r
+\r
+  return EFI_SUCCESS;\r
+}\r
+\r
+\r
+\r
+/**\r
+  This function is the main entry of the platform setup entry.\r
+  The function will present the main menu of the system setup,\r
+  this is the platform reference part and can be customize.\r
+\r
+\r
+  @param TimeoutDefault     The fault time out value before the system\r
+                            continue to boot.\r
+  @param ConnectAllHappened The indicater to check if the connect all have\r
+                            already happened.\r
+\r
+**/\r
+VOID\r
+PlatformBdsEnterFrontPageWithHotKey (\r
+  IN UINT16                       TimeoutDefault,\r
+  IN BOOLEAN                      ConnectAllHappened\r
+  )\r
+{\r
+  EFI_STATUS                    Status;\r
+\r
+  EFI_GRAPHICS_OUTPUT_PROTOCOL       *GraphicsOutput;\r
+  EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL    *SimpleTextOut;\r
+  UINTN                              BootTextColumn;\r
+  UINTN                              BootTextRow;\r
+\r
+  GraphicsOutput = NULL;\r
+  SimpleTextOut = NULL;\r
+\r
+  PERF_START (NULL, "BdsTimeOut", "BDS", 0);\r
+\r
+  //\r
+  // Indicate if we need connect all in the platform setup\r
+  //\r
+  if (ConnectAllHappened) {\r
+    gConnectAllHappened = TRUE;\r
+  }\r
+\r
+  if (!mModeInitialized) {\r
+    //\r
+    // After the console is ready, get current video resolution\r
+    // and text mode before launching setup at first time.\r
+    //\r
+    Status = gBS->HandleProtocol (\r
+                    gST->ConsoleOutHandle,\r
+                    &gEfiGraphicsOutputProtocolGuid,\r
+                    (VOID**)&GraphicsOutput\r
+                    );\r
+    if (EFI_ERROR (Status)) {\r
+      GraphicsOutput = NULL;\r
+    }\r
+\r
+    Status = gBS->HandleProtocol (\r
+                    gST->ConsoleOutHandle,\r
+                    &gEfiSimpleTextOutProtocolGuid,\r
+                    (VOID**)&SimpleTextOut\r
+                    );\r
+    if (EFI_ERROR (Status)) {\r
+      SimpleTextOut = NULL;\r
+    }\r
+\r
+    if (GraphicsOutput != NULL) {\r
+      //\r
+      // Get current video resolution and text mode.\r
+      //\r
+      mBootHorizontalResolution = GraphicsOutput->Mode->Info->HorizontalResolution;\r
+      mBootVerticalResolution   = GraphicsOutput->Mode->Info->VerticalResolution;\r
+    }\r
+\r
+    if (SimpleTextOut != NULL) {\r
+      Status = SimpleTextOut->QueryMode (\r
+                                SimpleTextOut,\r
+                                SimpleTextOut->Mode->Mode,\r
+                                &BootTextColumn,\r
+                                &BootTextRow\r
+                                );\r
+      mBootTextModeColumn = (UINT32)BootTextColumn;\r
+      mBootTextModeRow    = (UINT32)BootTextRow;\r
+    }\r
+\r
+    //\r
+    // Get user defined text mode for setup.\r
+    //\r
+    mSetupHorizontalResolution = PcdGet32 (PcdSetupVideoHorizontalResolution);\r
+    mSetupVerticalResolution   = PcdGet32 (PcdSetupVideoVerticalResolution);\r
+    mSetupTextModeColumn       = PcdGet32 (PcdSetupConOutColumn);\r
+    mSetupTextModeRow          = PcdGet32 (PcdSetupConOutRow);\r
+\r
+    mModeInitialized           = TRUE;\r
+  }\r
+\r
+  if (TimeoutDefault != 0xffff) {\r
+    Status = ShowProgressHotKey (TimeoutDefault);\r
+\r
+    //\r
+    // Ensure screen is clear when switch Console from Graphics mode to Text mode\r
+    //\r
+    gST->ConOut->EnableCursor (gST->ConOut, TRUE);\r
+    gST->ConOut->ClearScreen (gST->ConOut);\r
+\r
+    if (EFI_ERROR (Status)) {\r
+      //\r
+      // Timeout or user press enter to continue\r
+      //\r
+      goto Exit;\r
+    }\r
+  }\r
+\r
+  do {\r
+\r
+    BdsSetConsoleMode (TRUE);\r
+\r
+    InitializeFrontPage (FALSE);\r
+\r
+    //\r
+    // Update Front Page strings\r
+    //\r
+    UpdateFrontPageStrings ();\r
+\r
+    Status = EFI_SUCCESS;\r
+    gCallbackKey = 0;\r
+    if (gHotKey == 0) {\r
+      Status = CallFrontPage ();\r
+    } else {\r
+      gCallbackKey = gHotKey;\r
+      gHotKey = 0;\r
+    }\r
+\r
+    //\r
+    // If gCallbackKey is greater than 1 and less or equal to 5,\r
+    // it will launch configuration utilities.\r
+    // 2 = set language\r
+    // 3 = boot manager\r
+    // 4 = device manager\r
+    // 5 = boot maintenance manager\r
+    //\r
+    if (gCallbackKey != 0) {\r
+      REPORT_STATUS_CODE (\r
+        EFI_PROGRESS_CODE,\r
+        (EFI_SOFTWARE_DXE_BS_DRIVER | EFI_SW_PC_USER_SETUP)\r
+        );\r
+    }\r
+\r
+    //\r
+    // Based on the key that was set, we can determine what to do\r
+    //\r
+    switch (gCallbackKey) {\r
+    //\r
+    // The first 4 entries in the Front Page are to be GUARANTEED to remain constant so IHV's can\r
+    // describe to their customers in documentation how to find their setup information (namely\r
+    // under the device manager and specific buckets)\r
+    //\r
+    // These entries consist of the Continue, Select language, Boot Manager, and Device Manager\r
+    //\r
+    case FRONT_PAGE_KEY_CONTINUE:\r
+\r
+      //\r
+      // User hit continue\r
+      //\r
+      break;\r
+\r
+    case FRONT_PAGE_KEY_LANGUAGE:\r
+\r
+      //\r
+      // User made a language setting change - display front page again\r
+      //\r
+      break;\r
+\r
+    case FRONT_PAGE_KEY_BOOT_MANAGER:\r
+\r
+      //\r
+      // User chose to run the Boot Manager\r
+      //\r
+      CallBootManager ();\r
+      break;\r
+\r
+    case FRONT_PAGE_KEY_DEVICE_MANAGER:\r
+\r
+      //\r
+      // Display the Device Manager\r
+      //\r
+      do {\r
+        CallDeviceManager ();\r
+      } while (gCallbackKey == FRONT_PAGE_KEY_DEVICE_MANAGER);\r
+      break;\r
+\r
+    case FRONT_PAGE_KEY_BOOT_MAINTAIN:\r
+\r
+      //\r
+      // Display the Boot Maintenance Manager\r
+      //\r
+      BdsStartBootMaint ();\r
+      break;\r
+    }\r
+\r
+  } while (((UINTN)gCallbackKey) != FRONT_PAGE_KEY_CONTINUE);\r
+\r
+  //\r
+  //Will leave browser, check any reset required change is applied? if yes, reset system\r
+  //\r
+  SetupResetReminder ();\r
+\r
+Exit:\r
+  //\r
+  // Automatically load current entry\r
+  // Note: The following lines of code only execute when Auto boot\r
+  // takes affect\r
+  //\r
+  PERF_END (NULL, "BdsTimeOut", "BDS", 0);\r
+}\r
+\r
+\r
+VOID \r
+BootIntoFirmwareInterface(\r
+VOID\r
+)\r
+{\r
+  EFI_STATUS        Status;\r
+  UINTN             DataSize;\r
+  UINT16            Timeout;    \r
+  UINT64            OsIndication;\r
+\r
+  \r
+  OsIndication = 0;\r
+  DataSize = sizeof(UINT64);\r
+  Status = gRT->GetVariable (\r
+                  L"OsIndications",\r
+                  &gEfiGlobalVariableGuid,\r
+                  NULL,\r
+                  &DataSize,\r
+                  &OsIndication\r
+                  );\r
+                                 \r
+  DEBUG ((EFI_D_INFO, "OSIndication Variable Value %d\n", OsIndication));\r
+  //\r
+  //Goto FrontPage directly when bit EFI_OS_INDICATIONS_BOOT_TO_FW_UI in OSIndication Variable is setted.\r
+  //  \r
+  if (!EFI_ERROR(Status) && (OsIndication != 0)) {                               \r
+   Timeout = 0xffff;\r
+   PlatformBdsEnterFrontPage (Timeout, FALSE);\r
+   }\r
+}\r
+\r
+\r
+EFI_STATUS\r
+PlatformBdsConnectSimpleConsole (\r
+  IN BDS_CONSOLE_CONNECT_ENTRY   *PlatformConsole\r
+)\r
+{\r
+  EFI_STATUS                         Status;\r
+  UINTN                              Index;\r
+  EFI_DEVICE_PATH_PROTOCOL           *VarConout;\r
+  EFI_DEVICE_PATH_PROTOCOL           *VarConin;\r
+  UINTN                              DevicePathSize;\r
+\r
+\r
+  Index = 0;\r
+  Status = EFI_SUCCESS;\r
+  DevicePathSize = 0;\r
+  VarConout = BdsLibGetVariableAndSize (\r
+                L"ConOut",\r
+                &gEfiGlobalVariableGuid,\r
+                &DevicePathSize\r
+                );\r
+  VarConin = BdsLibGetVariableAndSize (\r
+               L"ConIn",\r
+               &gEfiGlobalVariableGuid,\r
+               &DevicePathSize\r
+               );\r
+  if (VarConout == NULL || VarConin == NULL) {\r
+    //\r
+    // Have chance to connect the platform default console,\r
+    // the platform default console is the minimue device group\r
+    // the platform should support\r
+    //\r
+    while (PlatformConsole[Index].DevicePath != NULL) {\r
+\r
+      //\r
+      // Update the console variable with the connect type\r
+      //\r
+      if ((PlatformConsole[Index].ConnectType & CONSOLE_IN) == CONSOLE_IN) {\r
+        BdsLibUpdateConsoleVariable (L"ConIn", PlatformConsole[Index].DevicePath, NULL);\r
+      }\r
+\r
+      if ((PlatformConsole[Index].ConnectType & CONSOLE_OUT) == CONSOLE_OUT) {\r
+        BdsLibUpdateConsoleVariable (L"ConOut", PlatformConsole[Index].DevicePath, NULL);\r
+      }\r
+\r
+      if ((PlatformConsole[Index].ConnectType & STD_ERROR) == STD_ERROR) {\r
+        BdsLibUpdateConsoleVariable (L"ErrOut", PlatformConsole[Index].DevicePath, NULL);\r
+      }\r
+\r
+      Index ++;\r
+    }\r
+  }\r
+\r
+  //\r
+  // Connect ConIn first to give keyboard time to parse hot key event.\r
+  //\r
+  Status = BdsLibConnectConsoleVariable (L"ConIn");\r
+  if (EFI_ERROR (Status)) {\r
+    return Status;\r
+  }\r
+\r
+  //\r
+  // Make sure we have at least one active VGA, and have the right\r
+  // active VGA in console variable\r
+  //\r
+  Status = PlatformBdsForceActiveVga ();\r
+\r
+  //\r
+  // It seems impossible not to have any ConOut device on platform,\r
+  // so we check the status here.\r
+  //\r
+  Status = BdsLibConnectConsoleVariable (L"ConOut");\r
+  if (EFI_ERROR (Status)) {\r
+    return Status;\r
+  }\r
+\r
+  return EFI_SUCCESS;\r
+}\r
+\r
+\r
+/**\r
+  Timer handler to convert the key from USB.\r
+\r
+  @param  Event                    Indicates the event that invoke this function.\r
+  @param  Context                  Indicates the calling context.\r
+**/\r
+VOID\r
+EFIAPI\r
+HotKeyTimerHandler (\r
+  IN  EFI_EVENT                 Event,\r
+  IN  VOID                      *Context\r
+  )\r
+{\r
+  EFI_STATUS                    Status;\r
+  EFI_INPUT_KEY                 Key;\r
+\r
+  Status = gST->ConIn->ReadKeyStroke (gST->ConIn, &Key);\r
+  if (EFI_ERROR (Status)) {\r
+    return;\r
+  }\r
+\r
+  switch(Key.ScanCode) {\r
+  case SCAN_F2:\r
+    gHotKey = 0;\r
+    mHotKeyPressed = TRUE;\r
+    break;\r
+\r
+  case SCAN_F5:\r
+    gHotKey = FRONT_PAGE_KEY_DEVICE_MANAGER;\r
+    mHotKeyPressed = TRUE;\r
+    break;\r
+\r
+  case SCAN_F7:\r
+    gHotKey = FRONT_PAGE_KEY_BOOT_MANAGER;\r
+    mHotKeyPressed = TRUE;\r
+    break;\r
+\r
+  case SCAN_F9:\r
+    gHotKey = FRONT_PAGE_KEY_BOOT_MAINTAIN;\r
+    mHotKeyPressed = TRUE;\r
+    break;\r
+  }\r
+\r
+  if (mHotKeyPressed) {\r
+    gBS->SetTimer (\r
+           mHotKeyTimerEvent,\r
+           TimerCancel,\r
+           0\r
+           );\r
+    gBS->CloseEvent (mHotKeyTimerEvent);\r
+    mHotKeyTimerEvent = NULL;\r
+  }\r
+\r
+  return;\r
+}\r
+\r
+\r
+/**\r
+  Callback function for SimpleTextInEx protocol install events\r
+\r
+  @param Event           the event that is signaled.\r
+  @param Context         not used here.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+HitHotkeyEvent (\r
+  IN EFI_EVENT    Event,\r
+  IN VOID         *Context\r
+  )\r
+{\r
+  EFI_STATUS                         Status;\r
+\r
+  Status = gBS->CloseEvent(mHitHotkeyEvent);\r
+  if (EFI_ERROR (Status)) {\r
+    return;\r
+  }\r
+  Status = gBS->CreateEvent (\r
+                  EVT_TIMER | EVT_NOTIFY_SIGNAL,\r
+                  TPL_NOTIFY,\r
+                  HotKeyTimerHandler,\r
+                  NULL,\r
+                  &mHotKeyTimerEvent\r
+                  );\r
+  if (EFI_ERROR (Status)) {\r
+    return;\r
+  }\r
+  Status = gBS->SetTimer (\r
+                  mHotKeyTimerEvent,\r
+                  TimerPeriodic,\r
+                  KEYBOARD_TIMER_INTERVAL\r
+                  );\r
+  if (EFI_ERROR (Status)) {\r
+    return;\r
+  }\r
+\r
+  return;\r
+}\r
+\r
+\r
+VOID\r
+EFIAPI\r
+PlatformBdsInitHotKeyEvent (\r
+  VOID\r
+  )\r
+{\r
+  EFI_STATUS      Status;\r
+\r
+  //\r
+  // Register Protocol notify for Hotkey service\r
+  //\r
+  Status = gBS->CreateEvent (\r
+                  EVT_NOTIFY_SIGNAL,\r
+                  TPL_CALLBACK,\r
+                  HitHotkeyEvent,\r
+                  NULL,\r
+                  &mHitHotkeyEvent\r
+                  );\r
+  ASSERT_EFI_ERROR (Status);\r
+\r
+  //\r
+  // Register for protocol notifications on this event\r
+  //\r
+  Status = gBS->RegisterProtocolNotify (\r
+                  &gEfiSimpleTextInputExProtocolGuid,\r
+                  mHitHotkeyEvent,\r
+                  &mHitHotkeyRegistration\r
+                  );\r
+  ASSERT_EFI_ERROR (Status);\r
+}\r

diff --git a/Vlv2TbltDevicePkg/Library/PlatformBdsLib/BdsPlatform.h b/Vlv2TbltDevicePkg/Library/PlatformBdsLib/BdsPlatform.h
new file mode 100644 (file)
index 0000000..63972b5
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Library/PlatformBdsLib/BdsPlatform.h
@@ -0,0 +1,484 @@
+/*++\r
+\r
+  Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+\r
+Module Name:\r
+\r
+  BdsPlatform.h\r
+\r
+Abstract:\r
+\r
+  Head file for BDS Platform specific code\r
+\r
+--*/\r
+\r
+#ifndef _BDS_PLATFORM_H\r
+#define _BDS_PLATFORM_H\r
+\r
+#include <FrameworkDxe.h>\r
+\r
+#include <Protocol/FirmwareVolume2.h>\r
+#include <Protocol/DevicePath.h>\r
+#include <Protocol/SimpleNetwork.h>\r
+#include <Protocol/PciRootBridgeIo.h>\r
+#include <Protocol/LoadFile.h>\r
+#include <Protocol/LegacyBios.h>\r
+#include <Protocol/PciIo.h>\r
+#include <Protocol/SmmAccess2.h>\r
+#include <Protocol/DxeSmmReadyToLock.h>\r
+#include <Protocol/UserManager.h>\r
+#include <Protocol/DeferredImageLoad.h>\r
+#include <Protocol/AcpiS3Save.h>\r
+#include <Protocol/ExitPmAuth.h>\r
+#include <Protocol/MmioDevice.h>\r
+#include <Protocol/I2cBusMcg.h>\r
+#include <Protocol/I2cHostMcg.h>\r
+#include <Guid/CapsuleVendor.h>\r
+#include <Guid/MemoryTypeInformation.h>\r
+#include <Guid/GlobalVariable.h>\r
+\r
+\r
+#include <Library/DebugLib.h>\r
+#include <Library/BaseMemoryLib.h>\r
+#include <Library/UefiBootServicesTableLib.h>\r
+#include <Library/UefiRuntimeServicesTableLib.h>\r
+#include <Library/MemoryAllocationLib.h>\r
+#include <Library/BaseLib.h>\r
+#include <Library/PcdLib.h>\r
+#include <Library/IoLib.h>\r
+#include <Library/GenericBdsLib.h>\r
+#include <Library/PlatformBdsLib.h>\r
+#include <Library/DevicePathLib.h>\r
+#include <Library/UefiLib.h>\r
+#include <Library/HobLib.h>\r
+#include <Library/PrintLib.h>\r
+#include <Library/PerformanceLib.h>\r
+#include <Library/ReportStatusCodeLib.h>\r
+\r
+#include <IndustryStandard/Pci.h>\r
+\r
+extern EFI_DEVICE_PATH_PROTOCOL  *gPlatformRootBridges [];\r
+extern BDS_CONSOLE_CONNECT_ENTRY gPlatformConsole [];\r
+extern EFI_DEVICE_PATH_PROTOCOL  *gPlatformAllPossiblePciVgaConsole [];\r
+extern EFI_DEVICE_PATH_PROTOCOL  *gPlatformConnectSequence [];\r
+extern EFI_DEVICE_PATH_PROTOCOL  *gPlatformDriverOption [];\r
+extern EFI_DEVICE_PATH_PROTOCOL  *gPlatformBootOption [];\r
+extern EFI_DEVICE_PATH_PROTOCOL  *gUserAuthenticationDevice[];\r
+extern BDS_CONSOLE_CONNECT_ENTRY gPlatformSimpleConsole [];\r
+extern EFI_DEVICE_PATH_PROTOCOL  *gPlatformSimpleBootOption [];\r
+\r
+//\r
+// the short form device path for Usb keyboard\r
+//\r
+#define CLASS_HID           3\r
+#define SUBCLASS_BOOT       1\r
+#define PROTOCOL_KEYBOARD   1\r
+\r
+#define PCI_DEVICE_PATH_NODE(Func, Dev) \\r
+  { \\r
+    HARDWARE_DEVICE_PATH, \\r
+    HW_PCI_DP, \\r
+    { \\r
+      (UINT8) (sizeof (PCI_DEVICE_PATH)), \\r
+      (UINT8) ((sizeof (PCI_DEVICE_PATH)) >> 8) \\r
+    }, \\r
+    (Func), \\r
+    (Dev) \\r
+  }\r
+\r
+#define PNPID_DEVICE_PATH_NODE(PnpId) \\r
+  { \\r
+    { \\r
+      ACPI_DEVICE_PATH, \\r
+      ACPI_DP, \\r
+      { \\r
+        (UINT8) (sizeof (ACPI_HID_DEVICE_PATH)), \\r
+        (UINT8) ((sizeof (ACPI_HID_DEVICE_PATH)) >> 8) \\r
+      } \\r
+    }, \\r
+    EISA_PNP_ID((PnpId)), \\r
+    0 \\r
+  }\r
+\r
+#define gUart(BaudRate, DataBits, Parity, StopBits) \\r
+  { \\r
+    { \\r
+      MESSAGING_DEVICE_PATH, \\r
+      MSG_UART_DP, \\r
+      { \\r
+        (UINT8) (sizeof (UART_DEVICE_PATH)), \\r
+        (UINT8) ((sizeof (UART_DEVICE_PATH)) >> 8) \\r
+      } \\r
+    }, \\r
+    0, \\r
+    (BaudRate), \\r
+    (DataBits), \\r
+    (Parity), \\r
+    (StopBits) \\r
+  }\r
+\r
+#define gPcAnsiTerminal \\r
+  { \\r
+    { \\r
+      MESSAGING_DEVICE_PATH, \\r
+      MSG_VENDOR_DP, \\r
+      { \\r
+        (UINT8) (sizeof (VENDOR_DEVICE_PATH)), \\r
+        (UINT8) ((sizeof (VENDOR_DEVICE_PATH)) >> 8) \\r
+      } \\r
+    }, \\r
+    DEVICE_PATH_MESSAGING_PC_ANSI \\r
+  }\r
+\r
+#define gUsbKeyboardMouse \\r
+  { \\r
+    { \\r
+      MESSAGING_DEVICE_PATH, \\r
+      MSG_USB_CLASS_DP, \\r
+      (UINT8) (sizeof (USB_CLASS_DEVICE_PATH)), \\r
+      (UINT8) ((sizeof (USB_CLASS_DEVICE_PATH)) >> 8) \\r
+    }, \\r
+    0xffff, \\r
+    0xffff, \\r
+    CLASS_HID, \\r
+    SUBCLASS_BOOT, \\r
+    PROTOCOL_KEYBOARD \\r
+  }\r
+\r
+#define gEndEntire \\r
+  { \\r
+    END_DEVICE_PATH_TYPE, \\r
+    END_ENTIRE_DEVICE_PATH_SUBTYPE, \\r
+    { \\r
+      END_DEVICE_PATH_LENGTH, \\r
+      0 \\r
+    } \\r
+  }\r
+\r
+#define gPciRootBridge \\r
+  PNPID_DEVICE_PATH_NODE(0x0A03)\r
+\r
+#define gPnpPs2Keyboard \\r
+  PNPID_DEVICE_PATH_NODE(0x0303)\r
+\r
+#define gPnp16550ComPort \\r
+  PNPID_DEVICE_PATH_NODE(0x0501)\r
+\r
+#define gPciePort0Bridge \\r
+  PCI_DEVICE_PATH_NODE(0, 0x1C)\r
+\r
+#define gPciePort1Bridge \\r
+  PCI_DEVICE_PATH_NODE(1, 0x1C)\r
+\r
+#define gPciePort2Bridge \\r
+  PCI_DEVICE_PATH_NODE(2, 0x1C)\r
+\r
+#define gPciePort3Bridge \\r
+  PCI_DEVICE_PATH_NODE(3, 0x1C)\r
+\r
+#define gPciIsaBridge \\r
+  PCI_DEVICE_PATH_NODE(0, 0x1f)\r
+\r
+//\r
+// Platform Root Bridge\r
+//\r
+typedef struct {\r
+  ACPI_HID_DEVICE_PATH      PciRootBridge;\r
+  EFI_DEVICE_PATH_PROTOCOL  End;\r
+} PLATFORM_ROOT_BRIDGE_DEVICE_PATH;\r
+\r
+//\r
+// Below is the platform console device path\r
+//\r
+typedef struct {\r
+  ACPI_HID_DEVICE_PATH      PciRootBridge;\r
+  PCI_DEVICE_PATH           IsaBridge;\r
+  ACPI_HID_DEVICE_PATH      Keyboard;\r
+  EFI_DEVICE_PATH_PROTOCOL  End;\r
+} PLATFORM_ISA_KEYBOARD_DEVICE_PATH;\r
+\r
+typedef struct {\r
+  VENDOR_DEVICE_PATH             VendorDevicePath;\r
+  EFI_DEVICE_PATH_PROTOCOL       End;\r
+} HII_VENDOR_DEVICE_PATH;\r
+\r
+typedef struct {\r
+  USB_CLASS_DEVICE_PATH           UsbClass;\r
+  EFI_DEVICE_PATH_PROTOCOL        End;\r
+} USB_CLASS_FORMAT_DEVICE_PATH;\r
+\r
+typedef struct {\r
+  ACPI_HID_DEVICE_PATH      PciRootBridge;\r
+  PCI_DEVICE_PATH           OnboardVga;\r
+  EFI_DEVICE_PATH_PROTOCOL  End;\r
+} PLATFORM_ONBOARD_VGA_DEVICE_PATH;\r
+\r
+typedef struct {\r
+  ACPI_HID_DEVICE_PATH      PciRootBridge;\r
+  PCI_DEVICE_PATH           AgpBridge;\r
+  PCI_DEVICE_PATH           AgpDevice;\r
+  EFI_DEVICE_PATH_PROTOCOL  End;\r
+} PLATFORM_OFFBOARD_VGA_DEVICE_PATH;\r
+\r
+typedef struct {\r
+  ACPI_HID_DEVICE_PATH      PciRootBridge;\r
+  PCI_DEVICE_PATH           IsaBridge;\r
+  ACPI_HID_DEVICE_PATH      IsaSerial;\r
+  UART_DEVICE_PATH          Uart;\r
+  VENDOR_DEVICE_PATH        TerminalType;\r
+  EFI_DEVICE_PATH_PROTOCOL  End;\r
+} PLATFORM_ISA_SERIAL_DEVICE_PATH;\r
+\r
+//\r
+// Below is the boot option device path\r
+//\r
+typedef struct {\r
+  BBS_BBS_DEVICE_PATH             LegacyHD;\r
+  EFI_DEVICE_PATH_PROTOCOL        End;\r
+} LEGACY_HD_DEVICE_PATH;\r
+\r
+//\r
+// Below is the platform IDE device path\r
+//\r
+typedef struct {\r
+  ACPI_HID_DEVICE_PATH      PciRootBridge;\r
+  PCI_DEVICE_PATH           IsaBridge;\r
+  ATAPI_DEVICE_PATH         Ide;\r
+  EFI_DEVICE_PATH_PROTOCOL  End;\r
+} PLATFORM_IDE_DEVICE_PATH;\r
+\r
+//\r
+// Floppy device path definition\r
+//\r
+typedef struct {\r
+  ACPI_HID_DEVICE_PATH      PciRootBridge;\r
+  PCI_DEVICE_PATH           IsaBridge;\r
+  ACPI_HID_DEVICE_PATH      Floppy;\r
+  EFI_DEVICE_PATH_PROTOCOL  End;\r
+} PLATFORM_FLOPPY_DEVICE_PATH;\r
+\r
+//\r
+// Below is the platform USB controller device path for\r
+// USB disk as user authentication device.\r
+//\r
+typedef struct {\r
+  ACPI_HID_DEVICE_PATH      PciRootBridge;\r
+  PCI_DEVICE_PATH           PciDevice;\r
+  EFI_DEVICE_PATH_PROTOCOL  End;\r
+} PLATFORM_USB_DEVICE_PATH;\r
+\r
+//\r
+// Below is the platform PCI device path\r
+//\r
+typedef struct {\r
+  ACPI_HID_DEVICE_PATH      PciRootBridge;\r
+  PCI_DEVICE_PATH           PciDevice;\r
+  EFI_DEVICE_PATH_PROTOCOL  End;\r
+} PLATFORM_PCI_DEVICE_PATH;\r
+\r
+typedef enum {\r
+  PMIC_Equal         = 0, // =         0\r
+  PMIC_Greater_Than,     // >          1\r
+  PMIC_Smaller_Than,     // <          2\r
+  PMIC_Greater_Equal,    // >=         3\r
+  PMIC_Smaller_Equal,    // <=         4\r
+  PMIC_Any                               // don't care 5\r
+} PMIC_Condition_list;\r
+\r
+typedef enum {\r
+  PMIC_White_List      = 0,  //White list\r
+  PMIC_Black_List      = 1   //Black list\r
+} PMIC_Compliance_mode;\r
+\r
+typedef struct {\r
+  UINT8                Cond_Choice;    // PMIC_Condition_list\r
+  UINT8                Cond_Number;            // the number\r
+}PMIC_Condition_Item;\r
+\r
+typedef struct {\r
+  PMIC_Condition_Item                                          PMIC_BoardID;\r
+  PMIC_Condition_Item                                          PMIC_FabID;\r
+  PMIC_Condition_Item                                          Soc_Stepping;//define PMIC type, 1:Dialog , 2:Rohm\r
+  PMIC_Condition_Item                                          PMIC_VendID;\r
+  PMIC_Condition_Item                                          PMIC_RevID;\r
+  PMIC_Compliance_mode                                         mode;        //if 1, blacklist; if 0, white list.\r
+} PMIC_Compliance_Item;\r
+\r
+//\r
+// Platform BDS Functions\r
+//\r
+VOID\r
+PlatformBdsGetDriverOption (\r
+  IN LIST_ENTRY                   *BdsDriverLists\r
+  );\r
+\r
+VOID\r
+PlatformBdsPredictBootOption (\r
+  IN  LIST_ENTRY                     *BdsBootOptionList\r
+  );\r
+\r
+EFI_STATUS\r
+PlatformBdsShowProgress (\r
+  EFI_GRAPHICS_OUTPUT_BLT_PIXEL TitleForeground,\r
+  EFI_GRAPHICS_OUTPUT_BLT_PIXEL TitleBackground,\r
+  CHAR16                        *Title,\r
+  EFI_GRAPHICS_OUTPUT_BLT_PIXEL ProgressColor,\r
+  UINTN                         Progress,\r
+  UINTN                         PreviousValue\r
+  );\r
+\r
+VOID\r
+PlatformBdsConnectSequence (\r
+  VOID\r
+  );\r
+\r
+EFI_STATUS\r
+PlatformBdsConnectConsole (\r
+  IN BDS_CONSOLE_CONNECT_ENTRY   *PlatformConsole\r
+  );\r
+\r
+EFI_STATUS\r
+PlatformBdsNoConsoleAction (\r
+  VOID\r
+  );\r
+\r
+VOID\r
+PlatformBdsEnterFrontPage (\r
+  IN UINT16                 TimeoutDefault,\r
+  IN BOOLEAN                ConnectAllHappened\r
+  );\r
+\r
+VOID\r
+EFIAPI\r
+PlatformBdsUserIdentify (\r
+  OUT EFI_USER_PROFILE_HANDLE        *User,\r
+  OUT BOOLEAN                        *DeferredImage\r
+  );\r
+\r
+VOID\r
+EFIAPI\r
+PlatformBdsConnectAuthDevice (\r
+  VOID\r
+  );\r
+\r
+VOID\r
+PlatformBdsEnterFrontPageWithHotKey (\r
+  IN UINT16                       TimeoutDefault,\r
+  IN BOOLEAN                      ConnectAllHappened\r
+  );\r
+\r
+ EFI_STATUS\r
+ ShowProgress (\r
+   IN UINT16                                      TimeoutDefault\r
+   );\r
+\r
+ EFI_STATUS\r
+ InitializeFrontPage (\r
+   IN BOOLEAN                                            InitializeHiiData\r
+   );\r
+\r
+ VOID\r
+ UpdateFrontPageStrings (\r
+   VOID\r
+   );\r
+\r
+ EFI_STATUS\r
+ CallFrontPage (\r
+   VOID\r
+   );\r
+\r
+\r
+ VOID\r
+ CallBootManager (\r
+   VOID\r
+   );\r
+\r
+VOID\r
+CallDeviceManager (\r
+  VOID\r
+  );\r
+\r
+VOID\r
+BdsStartBootMaint (\r
+  VOID\r
+  );\r
+\r
+CHAR16 *\r
+GetStringById (\r
+  IN  EFI_STRING_ID   Id\r
+  );\r
+\r
+EFI_STATUS\r
+WaitForSingleEvent (\r
+  IN EFI_EVENT                  Event,\r
+  IN UINT64                     Timeout OPTIONAL\r
+  );\r
+\r
+\r
+#define ONE_SECOND  10000000\r
+#define FRONT_PAGE_KEY_CONTINUE        0x1000\r
+#define FRONT_PAGE_KEY_LANGUAGE        0x1234\r
+#define FRONT_PAGE_KEY_BOOT_MANAGER    0x1064\r
+#define FRONT_PAGE_KEY_DEVICE_MANAGER  0x8567\r
+#define FRONT_PAGE_KEY_BOOT_MAINTAIN   0x9876\r
+\r
+#define PORT_A_DVO                     0           // ; DVO A\r
+#define PORT_B_DVO                     1           // ; DVO B\r
+#define PORT_C_DVO                     2           // ; DVO C\r
+#define PORT_D_DVO                     3           // ; DVO D\r
+#define PORT_LVDS                      4           // ; Integrated LVDS port\r
+#define PORT_ANALOG_TV                 5           // ; Integrated TV port\r
+#define PORT_CRT                       6           // ; integrated Analog port\r
+#define PORT_B_DP                      7           // ; DisplayPort B\r
+#define PORT_C_DP                      8           // ; DisplayPort C\r
+#define PORT_D_DP                      9           // ; DisplayPort D\r
+#define PORT_A_DP                      10          // ; DisplayPort A (for eDP on ILK)\r
+#define PORT_B_HDMI                    11          // ; HDMI B\r
+#define PORT_C_HDMI                    12          // ; HDMI C\r
+#define PORT_D_HDMI                    13          // ; HDMI D\r
+#define PORT_B_DVI                     14          // ; DVI B\r
+#define PORT_C_DVI                     15          // ; DVI C\r
+#define PORT_D_DVI                     16          // ; DVI D\r
+#define PORT_MIPI_A                    21          // ; MIPI\r
+#define PORT_MIPI_B                    22\r
+#define PORT_MIPI_C                    23\r
+\r
+\r
+extern BOOLEAN gConnectAllHappened;\r
+extern UINTN gCallbackKey;\r
+\r
+VOID\r
+BdsBootDeviceSelect (\r
+  VOID\r
+);\r
+VOID FastBoot(VOID);\r
+\r
+extern BOOLEAN    mModeInitialized;\r
+\r
+//\r
+// Boot video resolution and text mode.\r
+//\r
+extern UINT32     mBootHorizontalResolution    ;\r
+extern UINT32     mBootVerticalResolution      ;\r
+extern UINT32     mBootTextModeColumn          ;\r
+extern UINT32     mBootTextModeRow             ;\r
+\r
+//\r
+// BIOS setup video resolution and text mode.\r
+//\r
+extern UINT32     mSetupTextModeColumn         ;\r
+extern UINT32     mSetupTextModeRow            ;\r
+extern UINT32     mSetupHorizontalResolution   ;\r
+extern UINT32     mSetupVerticalResolution     ;\r
+extern EFI_STATUS BdsSetConsoleMode (BOOLEAN);\r
+#endif // _BDS_PLATFORM_H\r

diff --git a/Vlv2TbltDevicePkg/Library/PlatformBdsLib/PlatformBdsLib.inf b/Vlv2TbltDevicePkg/Library/PlatformBdsLib/PlatformBdsLib.inf
new file mode 100644 (file)
index 0000000..31ff8b8
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Library/PlatformBdsLib/PlatformBdsLib.inf
@@ -0,0 +1,118 @@
+#/** @file\r
+# Component name for module PlatformBootManagerLib\r
+#\r
+# Copyright (c) 2008  - 2014, Intel Corporation. All rights reserved.<BR>\r
+#                                                                                  \r\r
+# This program and the accompanying materials are licensed and made available under\r\r
+# the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+# The full text of the license may be found at                                     \r\r
+# http://opensource.org/licenses/bsd-license.php.                                  \r\r
+#                                                                                  \r\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+#                                                                                  \r\r
+#\r
+#\r
+#\r
+#**/\r
+\r
+[Defines]\r
+  INF_VERSION                    = 0x00010005\r
+  BASE_NAME                      = PlatformBdsLib\r
+  FILE_GUID                      = A6BC385D-59E5-4b77-87D7-200ABAA83C15\r
+  MODULE_TYPE                    = DXE_DRIVER\r
+  VERSION_STRING                 = 1.0\r
+  LIBRARY_CLASS                  = PlatformBootManagerLib|DXE_DRIVER\r
+  EDK_RELEASE_VERSION            = 0x00020000\r
+  EFI_SPECIFICATION_VERSION      = 0x0002000A\r
+\r
+\r
+#\r
+# The following information is for reference only and not required by the build tools.\r
+#\r
+#  VALID_ARCHITECTURES           = IA32 X64 EBC\r
+#\r
+\r
+[Sources]\r
+  BdsPlatform.c\r
+  BdsPlatform.h\r
+  PlatformData.c\r
+\r
+[Packages]\r
+  MdePkg/MdePkg.dec\r
+  MdeModulePkg/MdeModulePkg.dec\r
+  IntelFrameworkPkg/IntelFrameworkPkg.dec\r
+  IntelFrameworkModulePkg/IntelFrameworkModulePkg.dec\r
+  Vlv2TbltDevicePkg/PlatformPkg.dec\r
+  Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec\r
+  ShellPkg/ShellPkg.dec\r
+  CryptoPkg/CryptoPkg.dec\r
+  SecurityPkg/SecurityPkg.dec\r
+\r
+[LibraryClasses]\r
+  DxeServicesTableLib\r
+  BaseLib\r
+  MemoryAllocationLib\r
+  UefiBootServicesTableLib\r
+  UefiRuntimeServicesTableLib\r
+  BaseMemoryLib\r
+  DebugLib\r
+  PcdLib\r
+  GenericBdsLib\r
+  DevicePathLib\r
+  UefiLib\r
+  HobLib\r
+  PciLib\r
+  PrintLib\r
+  BaseCryptLib\r
+#  TcgPhysicalPresenceLib\r
+#  TrEEPhysicalPresenceLib\r
+  FileHandleLib\r
+  S3BootScriptLib\r
+  SerialPortLib\r
+\r
+[Protocols]\r
+  gEfiFirmwareVolume2ProtocolGuid\r
+  gEfiSimpleNetworkProtocolGuid\r
+  gEfiLoadFileProtocolGuid\r
+  gEfiPciIoProtocolGuid\r
+  gEfiSmmAccess2ProtocolGuid\r
+  gEfiDxeSmmReadyToLockProtocolGuid\r
+  gEfiUserManagerProtocolGuid\r
+  gEfiDeferredImageLoadProtocolGuid\r
+  gEfiAcpiS3SaveProtocolGuid\r
+  gEfiSpiProtocolGuid                           ## PROTOCOL CONSUMES\r
+  gExitPmAuthProtocolGuid\r
+  gEfiTdtOperationProtocolGuid\r
+  gEfiGlobalNvsAreaProtocolGuid\r
+  gEfiMmioDeviceProtocolGuid\r
+  gEfiI2cMasterProtocolGuid\r
+  gEfiI2cHostProtocolGuid\r
+\r
+[Guids]\r
+  gEfiMemoryTypeInformationGuid\r
+  gEfiCapsuleVendorGuid\r
+  gEfiGlobalVariableGuid\r
+  gEfiNormalSetupGuid\r
+  gEfiPartTypeSystemPartGuid\r
+\r
+[Pcd]\r
+  gPlatformModuleTokenSpaceGuid.PcdFlashFvRecovery2Base\r
+  gPlatformModuleTokenSpaceGuid.PcdFlashFvMainBase\r
+  gPlatformModuleTokenSpaceGuid.PcdFlashFvRecoveryBase\r
+  gPlatformModuleTokenSpaceGuid.PcdFlashFvShellBase\r
+  gPlatformModuleTokenSpaceGuid.PcdFlashFvShellSize\r
+  gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdPlatformBootTimeOut\r
+  gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdLogoFile\r
+  gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdShellFile\r
+  gPlatformModuleTokenSpaceGuid.PcdIFWISigBaseAddress\r
+  gEfiMdeModulePkgTokenSpaceGuid.PcdConOutRow\r
+  gEfiMdeModulePkgTokenSpaceGuid.PcdConOutColumn\r
+  gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution\r
+  gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution\r
+  gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress\r
+  gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdSetupConOutColumn\r
+  gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdSetupConOutRow\r
+  gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdSetupVideoHorizontalResolution\r
+  gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdSetupVideoVerticalResolution\r
+  gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdBootState\r

diff --git a/Vlv2TbltDevicePkg/Library/PlatformBdsLib/PlatformData.c b/Vlv2TbltDevicePkg/Library/PlatformBdsLib/PlatformData.c
new file mode 100644 (file)
index 0000000..64e68d3
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Library/PlatformBdsLib/PlatformData.c
@@ -0,0 +1,265 @@
+/** @file\r
+\r
+  Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+Module Name:\r
+\r
+  PlatformData.c\r
+\r
+Abstract:\r
+\r
+  Defined the platform specific device path which will be used by\r
+  platform Bbd to perform the platform policy connect.\r
+\r
+--*/\r
+\r
+#include "BdsPlatform.h"\r
+\r
+//\r
+// Predefined platform default time out value\r
+//\r
+UINT16  gPlatformBootTimeOutDefault = 10;\r
+\r
+//\r
+// Predefined platform root bridge\r
+//\r
+PLATFORM_ROOT_BRIDGE_DEVICE_PATH gPlatformRootBridge0 = {\r
+  gPciRootBridge,\r
+  gEndEntire\r
+};\r
+\r
+EFI_DEVICE_PATH_PROTOCOL* gPlatformRootBridges [] = {\r
+  (EFI_DEVICE_PATH_PROTOCOL*)&gPlatformRootBridge0,\r
+  NULL\r
+};\r
+\r
+//\r
+// Platform specific ISA keyboard device path\r
+//\r
+PLATFORM_ISA_KEYBOARD_DEVICE_PATH gIsaKeyboardDevicePath = {\r
+  gPciRootBridge,\r
+  gPciIsaBridge,\r
+  gPnpPs2Keyboard,\r
+  gEndEntire\r
+};\r
+\r
+//\r
+// Platform specific on chip PCI VGA device path\r
+//\r
+PLATFORM_ONBOARD_VGA_DEVICE_PATH gOnChipPciVgaDevicePath = {\r
+  gPciRootBridge,\r
+  PCI_DEVICE_PATH_NODE(0, 0x2),\r
+  gEndEntire\r
+};\r
+\r
+//\r
+// Platform specific plug in PCI VGA device path\r
+//\r
+PLATFORM_OFFBOARD_VGA_DEVICE_PATH gPlugInPciVgaDevicePath = {\r
+  gPciRootBridge,\r
+  PCI_DEVICE_PATH_NODE(0, 0x1),\r
+  PCI_DEVICE_PATH_NODE(0, 0x0),\r
+  gEndEntire\r
+};\r
+\r
+//\r
+// Platform specific ISA serial device path\r
+//\r
+PLATFORM_ISA_SERIAL_DEVICE_PATH gIsaSerialDevicePath = {\r
+  gPciRootBridge,\r
+  gPciIsaBridge,\r
+  gPnp16550ComPort,\r
+  gUart(115200, 8, 1, 1),\r
+  gPcAnsiTerminal,\r
+  gEndEntire\r
+};\r
+\r
+\r
+//\r
+// Platform specific Button Array device path\r
+//\r
+HII_VENDOR_DEVICE_PATH  gHiiVendorDevicePath0 = {\r
+  {\r
+    {\r
+      HARDWARE_DEVICE_PATH,\r
+      HW_VENDOR_DP,\r
+      {\r
+        (UINT8) (sizeof (VENDOR_DEVICE_PATH)),\r
+        (UINT8) ((sizeof (VENDOR_DEVICE_PATH)) >> 8)\r
+      }\r
+    },\r
+\r
+    //\r
+    // {C8752FDE-B5C8-4528-897D-6920FE771E38}\r
+    //\r
+    { 0xC8752FDE, 0xB5C8, 0x4528, { 0x89, 0x7D, 0x69, 0x20, 0xFE, 0x77, 0x1E, 0x38 } }\r
+  },\r
+  {\r
+    END_DEVICE_PATH_TYPE,\r
+    END_ENTIRE_DEVICE_PATH_SUBTYPE,\r
+    {\r
+      (UINT8) (END_DEVICE_PATH_LENGTH),\r
+      (UINT8) ((END_DEVICE_PATH_LENGTH) >> 8)\r
+    }\r
+  }\r
+};\r
+\r
+USB_CLASS_FORMAT_DEVICE_PATH gUsbClassKeyboardDevicePath = {\r
+  gUsbKeyboardMouse,\r
+  gEndEntire\r
+};\r
+\r
+//\r
+// Predefined platform default console device path\r
+//\r
+BDS_CONSOLE_CONNECT_ENTRY gPlatformConsole [] = {\r
+  {(EFI_DEVICE_PATH_PROTOCOL*)&gIsaSerialDevicePath, CONSOLE_ALL},\r
+  {(EFI_DEVICE_PATH_PROTOCOL*)&gHiiVendorDevicePath0, CONSOLE_IN},\r
+  {(EFI_DEVICE_PATH_PROTOCOL*)&gIsaKeyboardDevicePath, CONSOLE_IN},\r
+  {(EFI_DEVICE_PATH_PROTOCOL*)&gUsbClassKeyboardDevicePath, CONSOLE_IN},\r
+  {NULL, 0}\r
+};\r
+\r
+//\r
+// All the possible platform PCI VGA device path\r
+//\r
+EFI_DEVICE_PATH_PROTOCOL* gPlatformAllPossiblePciVgaConsole [] = {\r
+  (EFI_DEVICE_PATH_PROTOCOL*)&gOnChipPciVgaDevicePath,\r
+  (EFI_DEVICE_PATH_PROTOCOL*)&gPlugInPciVgaDevicePath,\r
+  NULL\r
+};\r
+\r
+//\r
+// Legacy hard disk boot option\r
+//\r
+LEGACY_HD_DEVICE_PATH gLegacyHd = {\r
+  {\r
+    BBS_DEVICE_PATH,\r
+    BBS_BBS_DP,\r
+    (UINT8)(sizeof(BBS_BBS_DEVICE_PATH)),\r
+    (UINT8)((sizeof(BBS_BBS_DEVICE_PATH)) >> 8),\r
+    BBS_TYPE_HARDDRIVE,\r
+    0,\r
+    0\r
+  },\r
+  gEndEntire\r
+};\r
+\r
+//\r
+// Legacy cdrom boot option\r
+//\r
+LEGACY_HD_DEVICE_PATH gLegacyCdrom = {\r
+  {\r
+    BBS_DEVICE_PATH,\r
+    BBS_BBS_DP,\r
+    (UINT8)(sizeof(BBS_BBS_DEVICE_PATH)),\r
+    (UINT8)((sizeof(BBS_BBS_DEVICE_PATH)) >> 8),\r
+    BBS_TYPE_CDROM,\r
+    0,\r
+    0\r
+  },\r
+  gEndEntire\r
+};\r
+\r
+//\r
+// Predefined platform specific perdict boot option\r
+//\r
+EFI_DEVICE_PATH_PROTOCOL* gPlatformBootOption [] = {\r
+  (EFI_DEVICE_PATH_PROTOCOL*)&gLegacyHd,\r
+  (EFI_DEVICE_PATH_PROTOCOL*)&gLegacyCdrom,\r
+  NULL\r
+};\r
+\r
+//\r
+// Predefined platform specific driver option\r
+//\r
+EFI_DEVICE_PATH_PROTOCOL* gPlatformDriverOption [] = {\r
+  NULL\r
+};\r
+\r
+//\r
+// Predefined platform connect sequence\r
+//\r
+EFI_DEVICE_PATH_PROTOCOL* gPlatformConnectSequence [] = {\r
+  (EFI_DEVICE_PATH_PROTOCOL *)&gPlatformRootBridge0,  // Force PCI enumer before Legacy OpROM shadow\r
+  NULL\r
+};\r
+\r
+//\r
+// Platform specific USB controller device path\r
+//\r
+PLATFORM_USB_DEVICE_PATH gUsbDevicePath0 = {\r
+  gPciRootBridge,\r
+  PCI_DEVICE_PATH_NODE(0, 0x1D),\r
+  gEndEntire\r
+};\r
+\r
+PLATFORM_USB_DEVICE_PATH gUsbDevicePath1 = {\r
+  gPciRootBridge,\r
+  PCI_DEVICE_PATH_NODE(1, 0x1D),\r
+  gEndEntire\r
+};\r
+\r
+PLATFORM_USB_DEVICE_PATH gUsbDevicePath2 = {\r
+  gPciRootBridge,\r
+  PCI_DEVICE_PATH_NODE(2, 0x1D),\r
+  gEndEntire\r
+};\r
+\r
+PLATFORM_USB_DEVICE_PATH gUsbDevicePath3 = {\r
+  gPciRootBridge,\r
+  PCI_DEVICE_PATH_NODE(3, 0x1D),\r
+  gEndEntire\r
+};\r
+\r
+//\r
+// Predefined platform device path for user authtication\r
+//\r
+EFI_DEVICE_PATH_PROTOCOL* gUserAuthenticationDevice[] = {\r
+  //\r
+  // Predefined device path for secure card (USB disk).\r
+  //\r
+  (EFI_DEVICE_PATH_PROTOCOL*)&gUsbDevicePath0,\r
+  (EFI_DEVICE_PATH_PROTOCOL*)&gUsbDevicePath1,\r
+  (EFI_DEVICE_PATH_PROTOCOL*)&gUsbDevicePath2,\r
+  (EFI_DEVICE_PATH_PROTOCOL*)&gUsbDevicePath3,\r
+  NULL\r
+};\r
+\r
+//\r
+// Predefined platform console device path\r
+//\r
+BDS_CONSOLE_CONNECT_ENTRY gPlatformSimpleConsole [] = {\r
+  {(EFI_DEVICE_PATH_PROTOCOL*)&gOnChipPciVgaDevicePath, CONSOLE_OUT},\r
+  {(EFI_DEVICE_PATH_PROTOCOL*)&gIsaSerialDevicePath, CONSOLE_ALL},\r
+  {(EFI_DEVICE_PATH_PROTOCOL*)&gHiiVendorDevicePath0, CONSOLE_IN},\r
+  {(EFI_DEVICE_PATH_PROTOCOL*)&gUsbClassKeyboardDevicePath, CONSOLE_IN},\r
+  {NULL, 0}\r
+};\r
+\r
+//\r
+// eMMC device at BDF(0x0, 0x17, 0x0)\r
+//\r
+PLATFORM_PCI_DEVICE_PATH gEmmcBootDevPath0 = {\r
+  gPciRootBridge,\r
+  PCI_DEVICE_PATH_NODE (0x00, 0x10),\r
+  gEndEntire\r
+};\r
+\r
+//\r
+// Predefined platform specific perdict boot option\r
+//\r
+EFI_DEVICE_PATH_PROTOCOL* gPlatformSimpleBootOption [] = {\r
+  (EFI_DEVICE_PATH_PROTOCOL*)&gEmmcBootDevPath0,\r
+  NULL\r
+};\r
+\r

diff --git a/Vlv2TbltDevicePkg/Library/PlatformCmosLib/PlatformCmosLib.c b/Vlv2TbltDevicePkg/Library/PlatformCmosLib/PlatformCmosLib.c
new file mode 100644 (file)
index 0000000..10d0573
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Library/PlatformCmosLib/PlatformCmosLib.c
@@ -0,0 +1,111 @@
+/*++\r
+\r
+Copyright (c) 2010 - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+\r
+Module Name:\r
+\r
+  CmosTable.h\r
+\r
+Abstract:\r
+\r
+--*/\r
+\r
+#include <Base.h>\r
+#include <Library/IoLib.h>\r
+#include <Library/PlatformCmosLib.h>\r
+#include "CmosMap.h"\r
+#include <PchAccess.h>\r
+#include "PlatformBaseAddresses.h"\r
+\r
+#define DEFAULT_VALUE          0\r
+#define  DEFAULT_ATTRIBUTES     0\r
+#define  EXCLUDE_FROM_CHECKSUM   CMOS_ATTRIBUTE_EXCLUDE_FROM_CHECKSUM\r
+\r
+#define CMOS_DEBUG_PRINT_LEVEL_DEFAULT_VALUE      0x46   // EFI_D_WARN|EFI_D_INFO|EFI_D_LOAD\r
+#define CMOS_DEBUG_PRINT_LEVEL_3_DEFAULT_VALUE    0x80   // EFI_D_ERROR\r
+\r
+//\r
+// Add the CMOS entry below\r
+//\r
+CMOS_ENTRY mCmosTable[] = {\r
+{ CPU_HT_POLICY, CPU_HT_POLICY_ENABLED, EXCLUDE_FROM_CHECKSUM },\r
+{ TPM_POLICY, TPM_POLICY_ENABLED, DEFAULT_ATTRIBUTES },\r
+{ CMOS_LCDPANELTYPE_REG, DEFAULT_VALUE, DEFAULT_ATTRIBUTES },\r
+{ CMOS_LCDPANELSCALING_REG, DEFAULT_VALUE, DEFAULT_ATTRIBUTES },\r
+{ CMOS_IGDBOOTTYPE_REG, DEFAULT_VALUE, DEFAULT_ATTRIBUTES },\r
+{ CMOS_BACKLIGHT_REG, DEFAULT_VALUE, DEFAULT_ATTRIBUTES },\r
+{ CMOS_LFP_PANEL_COLOR_DEPTH_REG, DEFAULT_VALUE, DEFAULT_ATTRIBUTES },\r
+{ CMOS_EDP_ACTIVE_LFP_CONFIG_REG, DEFAULT_VALUE, DEFAULT_ATTRIBUTES },\r
+{ CMOS_PRIMARY_DISPLAY_REG, DEFAULT_VALUE, DEFAULT_ATTRIBUTES },\r
+{ CMOS_IGD_DISPLAY_PIPE_B_REG, DEFAULT_VALUE, DEFAULT_ATTRIBUTES },\r
+{ CMOS_SDVOPANELTYPE_REG, DEFAULT_VALUE, DEFAULT_ATTRIBUTES },\r
+{ CMOS_PLATFORM_RESET_OS, DEFAULT_VALUE, DEFAULT_ATTRIBUTES },\r
+{ CMOS_CPU_BSP_SELECT, DEFAULT_VALUE, DEFAULT_ATTRIBUTES },\r
+{ CMOS_CPU_RATIO_OFFSET, DEFAULT_VALUE, DEFAULT_ATTRIBUTES },\r
+{ CMOS_ICH_PORT80_OFFSET, DEFAULT_VALUE, DEFAULT_ATTRIBUTES },\r
+{ CMOS_MAXRATIO_CONFIG_REG, DEFAULT_VALUE, DEFAULT_ATTRIBUTES },\r
+{ RTC_ADDRESS_CENTURY, RTC_ADDRESS_CENTURY_DEFAULT, CMOS_ATTRIBUTE_EXCLUDE_FROM_CHECKSUM },\r
+{ CMOS_POST_CODE_BREAK_REG, DEFAULT_VALUE, EXCLUDE_FROM_CHECKSUM },\r
+{ CMOS_POST_CODE_BREAK_1_REG, DEFAULT_VALUE, EXCLUDE_FROM_CHECKSUM },\r
+{ CMOS_POST_CODE_BREAK_2_REG, DEFAULT_VALUE, EXCLUDE_FROM_CHECKSUM },\r
+{ CMOS_POST_CODE_BREAK_3_REG, DEFAULT_VALUE, EXCLUDE_FROM_CHECKSUM },\r
+{ CMOS_DEBUG_PRINT_LEVEL_REG, CMOS_DEBUG_PRINT_LEVEL_DEFAULT_VALUE, EXCLUDE_FROM_CHECKSUM },\r
+{ CMOS_DEBUG_PRINT_LEVEL_1_REG, DEFAULT_VALUE, EXCLUDE_FROM_CHECKSUM },\r
+{ CMOS_DEBUG_PRINT_LEVEL_2_REG, DEFAULT_VALUE, EXCLUDE_FROM_CHECKSUM },\r
+{ CMOS_DEBUG_PRINT_LEVEL_3_REG, CMOS_DEBUG_PRINT_LEVEL_3_DEFAULT_VALUE, EXCLUDE_FROM_CHECKSUM },\r
+};\r
+\r
+/**\r
+  Funtion to return platform CMOS entry.\r
+\r
+  @param [out]  CmosEntry  Platform CMOS entry.\r
+\r
+  @param [out]  CmosEntryCount Number of platform CMOS entry.\r
+\r
+  @return Status.\r
+**/\r
+RETURN_STATUS\r
+EFIAPI\r
+GetPlatformCmosEntry (\r
+  OUT CMOS_ENTRY  **CmosEntry,\r
+  OUT UINTN       *CmosEntryCount\r
+  )\r
+{\r
+  *CmosEntry = mCmosTable;\r
+  *CmosEntryCount = sizeof(mCmosTable)/sizeof(mCmosTable[0]);\r
+  return RETURN_SUCCESS;\r
+}\r
+\r
+/**\r
+  Function to check if Battery lost or CMOS cleared.\r
+\r
+  @reval TRUE  Battery is always present.\r
+  @reval FALSE CMOS is cleared.\r
+**/\r
+BOOLEAN\r
+EFIAPI\r
+CheckCmosBatteryStatus (\r
+  VOID\r
+  )\r
+{\r
+  //\r
+  // Check if the CMOS battery is present\r
+  // Checks RTC_PWR_STS bit in the GEN_PMCON_1 register\r
+  //\r
+\r
+  if ((MmioRead8 (PMC_BASE_ADDRESS + R_PCH_PMC_GEN_PMCON_1) & B_PCH_PMC_GEN_PMCON_RTC_PWR_STS) == 0) {\r
+    return TRUE;\r
+  } else {\r
+    return FALSE;\r
+  }\r
+}\r

diff --git a/Vlv2TbltDevicePkg/Library/PlatformCmosLib/PlatformCmosLib.inf b/Vlv2TbltDevicePkg/Library/PlatformCmosLib/PlatformCmosLib.inf
new file mode 100644 (file)
index 0000000..af91a29
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Library/PlatformCmosLib/PlatformCmosLib.inf
@@ -0,0 +1,35 @@
+#/** @file\r
+#\r
+# Copyright (c) 2010 - 2014, Intel Corporation. All rights reserved.<BR>\r
+#                                                                                  \r\r
+# This program and the accompanying materials are licensed and made available under\r\r
+# the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+# The full text of the license may be found at                                     \r\r
+# http://opensource.org/licenses/bsd-license.php.                                  \r\r
+#                                                                                  \r\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+#                                                                                  \r\r
+#\r
+#\r
+#**/\r
+\r
+[Defines]\r
+  INF_VERSION                    = 0x00010005\r
+  BASE_NAME                      = PlatformCmosLib\r
+  FILE_GUID                      = ECA883EF-0CBE-40b6-84BC-FA4A709782F7\r
+  MODULE_TYPE                    = BASE\r
+  VERSION_STRING                 = 1.0\r
+  LIBRARY_CLASS                  = PlatformCmosLib\r
+\r
+[Sources]\r
+  PlatformCmosLib.c\r
+\r
+[LibraryClasses]\r
+  IoLib\r
+\r
+[Packages]\r
+  Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec\r
+  MdePkg/MdePkg.dec\r
+  MdeModulePkg/MdeModulePkg.dec\r
+  Vlv2TbltDevicePkg/PlatformPkg.dec\r

diff --git a/Vlv2TbltDevicePkg/Library/PlatformFspLib/PlatformFspLib.c b/Vlv2TbltDevicePkg/Library/PlatformFspLib/PlatformFspLib.c
new file mode 100644 (file)
index 0000000..1306399
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Library/PlatformFspLib/PlatformFspLib.c
@@ -0,0 +1,49 @@
+/** @file\r
+\r
+  Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+**/\r
+#include "PiPei.h"\r
+#include <Library/HobLib.h>\r
+#include <Library\BaseLib.h>\r
+#include <Library/DebugLib.h>\r
+#include <Guid/MemoryConfigData.h>\r
+#include <PlatformFspLib.h>\r
+\r
+EFI_STATUS\r
+PlatformHobCreateFromFsp (\r
+  IN CONST EFI_PEI_SERVICES     **PeiServices,\r
+  VOID                          *HobList\r
+  )\r
+{\r
+  VOID       *HobData;\r
+  VOID       *NewHobData;\r
+  UINTN      DataSize;\r
+\r
+  //\r
+  // Other hob, todo: put this into FspWrapPlatformLib\r
+  //\r
+  if ((HobList = GetNextGuidHob (&gEfiMemoryConfigDataGuid, HobList)) != NULL) {\r
+    HobData = GET_GUID_HOB_DATA (HobList);\r
+    DataSize = GET_GUID_HOB_DATA_SIZE(HobList);\r
+    DEBUG((EFI_D_ERROR, "gEfiMemoryConfigDataGuid Hob found: 0x%x.\n", DataSize));\r
+\r
+    NewHobData = BuildGuidHob (&gEfiMemoryConfigDataGuid, DataSize);\r
+    (*PeiServices)->CopyMem (\r
+                      NewHobData,\r
+                      HobData,\r
+                      DataSize\r
+                      );\r
+  }\r
+\r
+  return EFI_SUCCESS;\r
+}\r

diff --git a/Vlv2TbltDevicePkg/Library/PlatformFspLib/PlatformFspLib.inf b/Vlv2TbltDevicePkg/Library/PlatformFspLib/PlatformFspLib.inf
new file mode 100644 (file)
index 0000000..e64ceac
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Library/PlatformFspLib/PlatformFspLib.inf
@@ -0,0 +1,54 @@
+#\r
+#\r
+# Copyright (c)  1999  - 2014, Intel Corporation. All rights reserved\r
+#                                                                                  \r\r
+# This program and the accompanying materials are licensed and made available under\r\r
+# the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+# The full text of the license may be found at                                     \r\r
+# http://opensource.org/licenses/bsd-license.php.                                  \r\r
+#                                                                                  \r\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+#                                                                                  \r\r
+#\r
+#\r
+#\r
+#    FSP Platform HOB Library\r
+#\r
+#\r
+#\r
+##\r
+\r
+\r
+[Defines]\r
+  INF_VERSION                    = 0x00010005\r
+  BASE_NAME                      = PlatformFspLib\r
+  FILE_GUID                      = 1305A712-33A6-4fa7-BA59-AEAC3362931A\r
+  MODULE_TYPE                    = BASE\r
+  VERSION_STRING                 = 1.0\r
+  LIBRARY_CLASS                  = PlatformFspLib\r
+\r
+#\r
+# The following information is for reference only and not required by the build tools.\r
+#\r
+#  VALID_ARCHITECTURES           = IA32 X64 IPF EBC\r
+#\r
+\r
+[Sources]\r
+  PlatformFspLib.c\r
+\r
+[Packages]\r
+  MdePkg/MdePkg.dec\r
+  IntelFrameworkPkg/IntelFrameworkPkg.dec\r
+  Vlv2TbltDevicePkg/PlatformPkg.dec\r
+  Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec\r
+  IntelFspWrapperPkg/IntelFspWrapperPkg.dec\r
+\r
+[LibraryClasses]\r
+  BaseLib\r
+  DebugLib\r
+  HobLib\r
+\r
+[Guids]\r
+  gEfiMemoryConfigDataGuid\r
+\r

diff --git a/Vlv2TbltDevicePkg/Library/ResetSystemLib/ResetSystemLib.c b/Vlv2TbltDevicePkg/Library/ResetSystemLib/ResetSystemLib.c
new file mode 100644 (file)
index 0000000..1a6da83
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Library/ResetSystemLib/ResetSystemLib.c
@@ -0,0 +1,178 @@
+/** @file\r
+\r
+Copyright (c) 2007  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+\r
+Module Name:\r
+\r
+  IdeBus.h\r
+\r
+Abstract:\r
+\r
+  System reset Library Services.  This library class provides a set of\r
+  methods to reset whole system with manipulate ICH.\r
+\r
+**/\r
+\r
+\r
+#include <Base.h>\r
+\r
+\r
+#include <Library/ResetSystemLib.h>\r
+#include <Library/BaseLib.h>\r
+#include <Library/IoLib.h>\r
+#include <Library/DebugLib.h>\r
+#include <Library/PciLib.h>\r
+\r
+#include "PchRegs.h"\r
+#include "Rsci.h"\r
+#include "Platform.h"\r
+\r
+#define RESET_GENERATOR_PORT R_PCH_RST_CNT\r
+\r
+VOID\r
+EFIAPI\r
+PlatformResetHook (\r
+  UINT8 ResetType\r
+  )\r
+{\r
+  //\r
+  // Platform need to save OS reset request/types for next Android boot\r
+  //\r
+  IoWrite8 (0x72, CMOS_RESET_TYPE_BY_OS);\r
+  IoWrite8 (0x73, ResetType);\r
+}\r
+\r
+/**\r
+  Calling this function causes a system-wide reset. This sets\r
+  all circuitry within the system to its initial state. This type of reset\r
+  is asynchronous to system operation and operates without regard to\r
+  cycle boundaries.\r
+\r
+  System reset should not return, if it returns, it means the system does\r
+  not support cold reset.\r
+**/\r
+VOID\r
+EFIAPI\r
+ResetCold (\r
+  VOID\r
+  )\r
+{\r
+  PlatformResetHook(COLD_RESET);\r
+  IoWrite8 (RESET_GENERATOR_PORT, 0x2);\r
+  IoWrite8 (RESET_GENERATOR_PORT, 0x6);\r
+}\r
+\r
+/**\r
+  Calling this function causes a system-wide initialization. The processors\r
+  are set to their initial state, and pending cycles are not corrupted.\r
+\r
+  System reset should not return, if it returns, it means the system does\r
+  not support warm reset.\r
+**/\r
+VOID\r
+EFIAPI\r
+ResetWarm (\r
+  VOID\r
+  )\r
+{\r
+  PlatformResetHook(WARM_RESET);\r
+  IoWrite8 (RESET_GENERATOR_PORT, 0x0);\r
+  IoWrite8 (RESET_GENERATOR_PORT, 0x4);\r
+}\r
+\r
+/**\r
+  Calling this function causes the system to enter a power state equivalent\r
+  to the ACPI G2/S5 or G3 states.\r
+\r
+  System shutdown should not return, if it returns, it means the system does\r
+  not support shut down reset.\r
+**/\r
+VOID\r
+EFIAPI\r
+ResetShutdown (\r
+  VOID\r
+  )\r
+{\r
+  UINT16  PchPmioBase;\r
+  UINT16  Data16;\r
+  UINT32  Data32;\r
+\r
+  PchPmioBase = (UINT16) (PciRead16 (PCI_LIB_ADDRESS(0, PCI_DEVICE_NUMBER_PCH_LPC, 0, R_PCH_LPC_ACPI_BASE)) & ~BIT0);\r
+\r
+  //\r
+  // Then, GPE0_EN should be disabled to avoid any GPI waking up the system from S5\r
+  //\r
+  Data16 = 0;\r
+  IoWrite16 (\r
+    (UINTN)(PchPmioBase + R_PCH_ACPI_GPE0a_EN),\r
+    (UINT16)Data16\r
+    );\r
+\r
+  //\r
+  // Clear Sleep SMI Status\r
+  //\r
+  IoWrite16 (PchPmioBase + R_PCH_SMI_STS,\r
+             (UINT16)(IoRead16 (PchPmioBase + R_PCH_SMI_STS) | B_PCH_SMI_STS_ON_SLP_EN));\r
+  //\r
+  // Clear Sleep Type Enable\r
+  //\r
+  IoWrite16 (PchPmioBase + R_PCH_SMI_EN,\r
+             (UINT16)(IoRead16 (PchPmioBase + R_PCH_SMI_EN) & (~B_PCH_SMI_EN_ON_SLP_EN)));\r
+  //\r
+  // Clear Power Button Status\r
+  //\r
+  IoWrite16(PchPmioBase + R_PCH_ACPI_PM1_STS, B_PCH_ACPI_PM1_STS_PWRBTN);\r
+\r
+  //\r
+  // Secondly, Power Button Status bit must be cleared\r
+  //\r
+  // Write a "1" to bit[8] of power button status register at\r
+  // (ABASE + PM1_STS) to clear this bit\r
+  // Clear it through SMI Status register\r
+  //\r
+  Data16 = B_PCH_SMI_STS_PM1_STS_REG;\r
+  IoWrite16 ((UINTN) (PchPmioBase + R_PCH_SMI_STS), Data16);\r
+\r
+  //\r
+  // Finally, transform system into S5 sleep state\r
+  //\r
+  Data32  = IoRead32 ((UINTN) (PchPmioBase + R_PCH_ACPI_PM1_CNT));\r
+\r
+  Data32  = (UINT32) ((Data32 &~(B_PCH_ACPI_PM1_CNT_SLP_TYP + B_PCH_ACPI_PM1_CNT_SLP_EN)) | V_PCH_ACPI_PM1_CNT_S5);\r
+\r
+  IoWrite32 ((UINTN) (PchPmioBase + R_PCH_ACPI_PM1_CNT), Data32);\r
+\r
+  Data32 = Data32 | B_PCH_ACPI_PM1_CNT_SLP_EN;\r
+\r
+  IoWrite32 ((UINTN) (PchPmioBase + R_PCH_ACPI_PM1_CNT), Data32);\r
+\r
+  return;\r
+}\r
+\r
+/**\r
+  Calling this function causes the system to enter a power state for capsule\r
+  update.\r
+\r
+  Reset update should not return, if it returns, it means the system does\r
+  not support capsule update.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+EnterS3WithImmediateWake (\r
+  VOID\r
+  )\r
+{\r
+  ASSERT (FALSE);\r
+}\r
+\r

diff --git a/Vlv2TbltDevicePkg/Library/ResetSystemLib/ResetSystemLib.inf b/Vlv2TbltDevicePkg/Library/ResetSystemLib/ResetSystemLib.inf
new file mode 100644 (file)
index 0000000..94b2c97
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Library/ResetSystemLib/ResetSystemLib.inf
@@ -0,0 +1,52 @@
+#/** @file\r
+# Component description file for Intel Ich7 Reset System Library.\r
+#\r
+# Reset System Library that layers on top of the I/O Library to directly\r
+#  access a standard SMBUS host controller.\r
+# Copyright (c) 2007 - 2014, Intel Corporation. All rights reserved.<BR>\r
+#                                                                                  \r\r
+# This program and the accompanying materials are licensed and made available under\r\r
+# the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+# The full text of the license may be found at                                     \r\r
+# http://opensource.org/licenses/bsd-license.php.                                  \r\r
+#                                                                                  \r\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+#                                                                                  \r\r
+#\r
+#\r
+#\r
+#**/\r
+\r
+[Defines]\r
+  INF_VERSION                    = 0x00010005\r
+  BASE_NAME                      = ResetSystemLib\r
+  FILE_GUID                      = D4FF05AA-3C7D-4b8a-A1EE-AA5EFA0B1732\r
+  MODULE_TYPE                    = BASE\r
+  VERSION_STRING                 = 1.0\r
+  LIBRARY_CLASS                  = ResetSystemLib\r
+  EDK_RELEASE_VERSION            = 0x00020000\r
+  EFI_SPECIFICATION_VERSION      = 0x00020000\r
+\r
+\r
+#\r
+# The following information is for reference only and not required by the build tools.\r
+#\r
+#  VALID_ARCHITECTURES           = IA32 X64 IPF\r
+#\r
+\r
+[Sources.common]\r
+  ResetSystemLib.c\r
+\r
+\r
+[Packages]\r
+  Vlv2TbltDevicePkg/PlatformPkg.dec\r
+  MdePkg/MdePkg.dec\r
+  MdeModulePkg/MdeModulePkg.dec\r
+  Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec\r
+\r
+[LibraryClasses]\r
+  IoLib\r
+  BaseLib\r
+  DebugLib\r
+  PciLib\r

diff --git a/Vlv2TbltDevicePkg/Library/SerialPortLib/PlatformSerialPortLib.h b/Vlv2TbltDevicePkg/Library/SerialPortLib/PlatformSerialPortLib.h
new file mode 100644 (file)
index 0000000..e59ae92
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Library/SerialPortLib/PlatformSerialPortLib.h
@@ -0,0 +1,69 @@
+/** @file\r
+  Header file of Serial port hardware definition.\r
+\r
+  Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+  This software and associated documentation\r
+  (if any) is furnished under a license and may only be used or\r
+  copied in accordance with the terms of the license.  Except as\r
+  permitted by such license, no part of this software or\r
+  documentation may be reproduced, stored in a retrieval system, or\r
+  transmitted in any form or by any means without the express written\r
+  consent of Intel Corporation.\r
+\r
+  Module Name:  PlatformSerialPortLib.h\r
+\r
+**/\r
+\r
+#ifndef __PLATFORM_SERIAL_PORT_LIB_H_\r
+#define __PLATFORM_SERIAL_PORT_LIB_H_\r
+\r
+#include <Base.h>\r
+#include <Library/BaseLib.h>\r
+#include <Library/IoLib.h>\r
+#include <Library/PcdLib.h>\r
+#include <Library/SerialPortLib.h>\r
+\r
+//\r
+// UART Register Offsets\r
+//\r
+#define BAUD_LOW_OFFSET   0x00\r
+#define BAUD_HIGH_OFFSET  0x01\r
+#define IER_OFFSET        0x01\r
+#define LCR_SHADOW_OFFSET 0x01\r
+#define FCR_SHADOW_OFFSET 0x02\r
+#define IR_CONTROL_OFFSET 0x02\r
+#define FCR_OFFSET        0x02\r
+#define EIR_OFFSET        0x02\r
+#define BSR_OFFSET        0x03\r
+#define LCR_OFFSET        0x03\r
+#define MCR_OFFSET        0x04\r
+#define LSR_OFFSET        0x05\r
+#define MSR_OFFSET        0x06\r
+\r
+//\r
+// UART Register Bit Defines\r
+//\r
+#define LSR_TXRDY 0x20\r
+#define LSR_RXDA  0x01\r
+#define DLAB      0x01\r
+\r
+#define UART_DATA    8\r
+#define UART_STOP    1\r
+#define UART_PARITY  0\r
+#define UART_BREAK_SET  0\r
+\r
+VOID\r
+InitializeSio (\r
+  VOID\r
+  );\r
+\r
+#endif\r

diff --git a/Vlv2TbltDevicePkg/Library/SerialPortLib/SerialPortLib.c b/Vlv2TbltDevicePkg/Library/SerialPortLib/SerialPortLib.c
new file mode 100644 (file)
index 0000000..21d5e8a
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Library/SerialPortLib/SerialPortLib.c
@@ -0,0 +1,262 @@
+/** @file\r
+  Serial I/O Port library functions with no library constructor/destructor\r
+\r
+  Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+  This software and associated documentation\r
+  (if any) is furnished under a license and may only be used or\r
+  copied in accordance with the terms of the license.  Except as\r
+  permitted by such license, no part of this software or\r
+  documentation may be reproduced, stored in a retrieval system, or\r
+  transmitted in any form or by any means without the express written\r
+  consent of Intel Corporation.\r
+\r
+  Module Name:  SerialPortLib.c\r
+\r
+**/\r
+\r
+#include "PlatformSerialPortLib.h"\r
+\r
+UINT16 gComBase  = 0x3f8;\r
+UINTN  gBps      = 115200;\r
+UINT8  gData     = 8;\r
+UINT8  gStop     = 1;\r
+UINT8  gParity   = 0;\r
+UINT8  gBreakSet = 0;\r
+\r
+/**\r
+  Initialize Serial Port\r
+\r
+  The Baud Rate Divisor registers are programmed and the LCR\r
+  is used to configure the communications format. Hard coded\r
+  UART config comes from globals in DebugSerialPlatform lib.\r
+\r
+  @param None\r
+\r
+  @retval None\r
+\r
+**/\r
+RETURN_STATUS\r
+EFIAPI\r
+UARTInitialize (\r
+  VOID\r
+  )\r
+{\r
+  UINTN Divisor;\r
+  UINT8 OutputData;\r
+  UINT8 Data;\r
+\r
+  //\r
+  // Map 5..8 to 0..3\r
+  //\r
+  Data = (UINT8) (gData - (UINT8) 5);\r
+\r
+  //\r
+  // Calculate divisor for baud generator\r
+  //\r
+  Divisor = 115200 / gBps;\r
+\r
+  //\r
+  // Set communications format\r
+  //\r
+  OutputData = (UINT8) ((DLAB << 7) | ((gBreakSet << 6) | ((gParity << 3) | ((gStop << 2) | Data))));\r
+  IoWrite8 (gComBase + LCR_OFFSET, OutputData);\r
+\r
+  //\r
+  // Configure baud rate\r
+  //\r
+  IoWrite8 (gComBase + BAUD_HIGH_OFFSET, (UINT8) (Divisor >> 8));\r
+  IoWrite8 (gComBase + BAUD_LOW_OFFSET, (UINT8) (Divisor & 0xff));\r
+\r
+  //\r
+  // Switch back to bank 0\r
+  //\r
+  OutputData = (UINT8) ((~DLAB << 7) | ((gBreakSet << 6) | ((gParity << 3) | ((gStop << 2) | Data))));\r
+  IoWrite8 (gComBase + LCR_OFFSET, OutputData);\r
+\r
+  return RETURN_SUCCESS;\r
+}\r
+\r
+/**\r
+  Common function to initialize UART Serial device and USB Serial device.\r
+\r
+  @param None\r
+\r
+  @retval None\r
+\r
+**/\r
+RETURN_STATUS\r
+EFIAPI\r
+SerialPortInitialize (\r
+  VOID\r
+  )\r
+{\r
+\r
+  UARTInitialize ();\r
+\r
+\r
+  return RETURN_SUCCESS;\r
+}\r
+\r
+/**\r
+  Write data to serial device.\r
+\r
+  If the buffer is NULL, then return 0;\r
+  if NumberOfBytes is zero, then return 0.\r
+\r
+  @param  Buffer           Point of data buffer which need to be writed.\r
+  @param  NumberOfBytes    Number of output bytes which are cached in Buffer.\r
+\r
+  @retval 0                Write data failed.\r
+  @retval !0               Actual number of bytes writed to serial device.\r
+\r
+**/\r
+UINTN\r
+EFIAPI\r
+UARTDbgOut (\r
+  IN UINT8     *Buffer,\r
+  IN UINTN     NumberOfBytes\r
+)\r
+{\r
+  UINTN Result;\r
+  UINT8 Data;\r
+\r
+  if (NULL == Buffer) {\r
+    return 0;\r
+  }\r
+\r
+  Result = NumberOfBytes;\r
+\r
+  while (NumberOfBytes--) {\r
+    //\r
+    // Wait for the serial port to be ready.\r
+    //\r
+    do {\r
+      Data = IoRead8 ((UINT16) PcdGet64 (PcdSerialRegisterBase) + LSR_OFFSET);\r
+    } while ((Data & LSR_TXRDY) == 0);\r
+    IoWrite8 ((UINT16) PcdGet64 (PcdSerialRegisterBase), *Buffer++);\r
+  }\r
+\r
+  return Result;\r
+}\r
+\r
+/**\r
+  Common function to write data to UART Serial device and USB Serial device.\r
+\r
+  @param  Buffer           Point of data buffer which need to be writed.\r
+  @param  NumberOfBytes    Number of output bytes which are cached in Buffer.\r
+\r
+**/\r
+UINTN\r
+EFIAPI\r
+SerialPortWrite (\r
+  IN UINT8     *Buffer,\r
+  IN UINTN     NumberOfBytes\r
+)\r
+{\r
+  if (FeaturePcdGet (PcdStatusCodeUseIsaSerial)) {\r
+    UARTDbgOut (Buffer, NumberOfBytes);\r
+  }\r
+\r
+  return RETURN_SUCCESS;\r
+}\r
+\r
+/**\r
+  Read data from serial device and save the datas in buffer.\r
+\r
+  If the buffer is NULL, then return 0;\r
+  if NumberOfBytes is zero, then return 0.\r
+\r
+  @param  Buffer           Point of data buffer which need to be writed.\r
+  @param  NumberOfBytes    Number of output bytes which are cached in Buffer.\r
+\r
+  @retval 0                Read data failed.\r
+  @retval !0               Actual number of bytes raed to serial device.\r
+\r
+**/\r
+UINTN\r
+EFIAPI\r
+UARTDbgIn (\r
+  OUT UINT8     *Buffer,\r
+  IN  UINTN     NumberOfBytes\r
+)\r
+{\r
+  UINTN Result;\r
+  UINT8 Data;\r
+\r
+  if (NULL == Buffer) {\r
+    return 0;\r
+  }\r
+\r
+  Result = NumberOfBytes;\r
+\r
+  while (NumberOfBytes--) {\r
+    //\r
+    // Wait for the serial port to be ready.\r
+    //\r
+    do {\r
+      Data = IoRead8 ((UINT16) PcdGet64 (PcdSerialRegisterBase) + LSR_OFFSET);\r
+    } while ((Data & LSR_RXDA) == 0);\r
+\r
+    *Buffer++ = IoRead8 ((UINT16) PcdGet64 (PcdSerialRegisterBase));\r
+  }\r
+\r
+  return Result;\r
+}\r
+\r
+/**\r
+  Common function to Read data from UART serial device, USB serial device and save the datas in buffer.\r
+\r
+  @param  Buffer           Point of data buffer which need to be writed.\r
+  @param  NumberOfBytes    Number of output bytes which are cached in Buffer.\r
+\r
+**/\r
+UINTN\r
+EFIAPI\r
+SerialPortRead (\r
+  OUT UINT8     *Buffer,\r
+  IN  UINTN     NumberOfBytes\r
+)\r
+{\r
+  if (FeaturePcdGet (PcdStatusCodeUseIsaSerial)) {\r
+    UARTDbgIn (Buffer, NumberOfBytes);\r
+  }\r
+\r
+  return RETURN_SUCCESS;\r
+}\r
+\r
+\r
+/**\r
+  Polls a serial device to see if there is any data waiting to be read.\r
+\r
+  Polls aserial device to see if there is any data waiting to be read.\r
+  If there is data waiting to be read from the serial device, then TRUE is returned.\r
+  If there is no data waiting to be read from the serial device, then FALSE is returned.\r
+\r
+  @retval TRUE             Data is waiting to be read from the serial device.\r
+  @retval FALSE            There is no data waiting to be read from the serial device.\r
+\r
+**/\r
+BOOLEAN\r
+EFIAPI\r
+SerialPortPoll (\r
+  VOID\r
+  )\r
+{\r
+  UINT8  Data;\r
+\r
+  //\r
+  // Read the serial port status.\r
+  //\r
+  Data = IoRead8 ((UINT16) PcdGet64 (PcdSerialRegisterBase) + LSR_OFFSET);\r
+\r
+  return (BOOLEAN) ((Data & LSR_RXDA) != 0);\r
+}\r

diff --git a/Vlv2TbltDevicePkg/Library/SerialPortLib/SerialPortLib.inf b/Vlv2TbltDevicePkg/Library/SerialPortLib/SerialPortLib.inf
new file mode 100644 (file)
index 0000000..92cdf99
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Library/SerialPortLib/SerialPortLib.inf
@@ -0,0 +1,57 @@
+#/** @file\r
+#\r
+# Copyright (c) 2008 - 2014, Intel Corporation. All rights reserved.<BR>\r
+#                                                                                  \r\r
+# This program and the accompanying materials are licensed and made available under\r\r
+# the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+# The full text of the license may be found at                                     \r\r
+# http://opensource.org/licenses/bsd-license.php.                                  \r\r
+#                                                                                  \r\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+#                                                                                  \r\r
+#\r
+#\r
+#\r
+#**/\r
+\r
+[Defines]\r
+  INF_VERSION                    = 0x00010005\r
+  BASE_NAME                      = SerialPortLib\r
+  FILE_GUID                      = 15B26F43-A389-4bae-BDE3-4BB0719B7D4F\r
+  MODULE_TYPE                    = BASE\r
+  VERSION_STRING                 = 1.0\r
+  LIBRARY_CLASS                  = SerialPortLib\r
+\r
+#\r
+# The following information is for reference only and not required by the build tools.\r
+#\r
+#  VALID_ARCHITECTURES           = IA32 X64 IPF\r
+#\r
+\r
+[Sources]\r
+  SerialPortLib.c\r
+  SioInit.c\r
+\r
+[Packages]\r
+  MdePkg/MdePkg.dec\r
+  MdeModulePkg/MdeModulePkg.dec\r
+  IntelFrameworkPkg/IntelFrameworkPkg.dec\r
+  Vlv2TbltDevicePkg/PlatformPkg.dec\r
+  Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec\r
+\r
+[LibraryClasses]\r
+  BaseLib\r
+  PcdLib\r
+  IoLib\r
+  PciLib\r
+  TimerLib\r
+\r
+[FixedPcd.common]\r
+  gEfiSerialPortTokenSpaceGuid.PcdSerialBoudRate\r
+  gEfiSerialPortTokenSpaceGuid.PcdSerialRegisterBase\r
+\r
+[FeaturePcd]\r
+  gEfiSerialPortTokenSpaceGuid.PcdStatusCodeUseIsaSerial\r
+  gEfiSerialPortTokenSpaceGuid.PcdStatusCodeUseUsbSerial\r
+  gEfiSerialPortTokenSpaceGuid.PcdStatusCodeUseRam\r

diff --git a/Vlv2TbltDevicePkg/Library/SerialPortLib/SioInit.c b/Vlv2TbltDevicePkg/Library/SerialPortLib/SioInit.c
new file mode 100644 (file)
index 0000000..78a380a
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Library/SerialPortLib/SioInit.c
@@ -0,0 +1,132 @@
+/** @file\r
+\r
+  Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+Module Name:\r
+\r
+    SioInit.c\r
+\r
+Abstract:\r
+\r
+    Functions for LpcSio initialization\r
+\r
+--*/\r
+\r
+#include "PlatformSerialPortLib.h"\r
+#include "SioInit.h"\r
+\r
+typedef struct {\r
+  UINT8 Register;\r
+  UINT8 Value;\r
+} EFI_SIO_TABLE;\r
+\r
+EFI_SIO_TABLE mSioTableWpcn381u[] = {\r
+    {0x29, 0x0A0},\r
+    {WPCN381U_LD_SEL_REGISTER, WPCN381U_LDN_UART0},                                       // Select UART0 device\r
+    {WPCN381U_BASE1_HI_REGISTER, (UINT8)(WPCN381U_SERIAL_PORT0_BASE_ADDRESS >> 8)},       // Set Base Address MSB\r
+    {WPCN381U_BASE1_LO_REGISTER, (UINT8)(WPCN381U_SERIAL_PORT0_BASE_ADDRESS & 0x00FF)},   // Set Base Address LSB\r
+    {WPCN381U_IRQ1_REGISTER, 0x014},                                                      // Set to IRQ4\r
+    {WPCN381U_ACTIVATE_REGISTER, WPCN381U_ACTIVATE_VALUE},                                // Enable it with Activation bit\r
+    {WPCN381U_LD_SEL_REGISTER, WPCN381U_LDN_UART1},                                       // Select UART1 device\r
+    {WPCN381U_BASE1_HI_REGISTER, (UINT8)(WPCN381U_SERIAL_PORT1_BASE_ADDRESS >> 8)},       // Set Base Address MSB\r
+    {WPCN381U_BASE1_LO_REGISTER, (UINT8)(WPCN381U_SERIAL_PORT1_BASE_ADDRESS & 0x00FF)},   // Set Base Address LSB\r
+    {WPCN381U_IRQ1_REGISTER, 0x013},                                                      // Set to IRQ3\r
+    {WPCN381U_ACTIVATE_REGISTER, WPCN381U_ACTIVATE_VALUE},                                // Enable it with Activation bit\r
+    {WPCN381U_LD_SEL_REGISTER, WPCN381U_LDN_GPIO},                                        // Select GPIO device\r
+    {WPCN381U_BASE1_HI_REGISTER, (UINT8)(WPCN381U_GPIO_BASE_ADDRESS >> 8)},               // Set Base Address MSB\r
+    {WPCN381U_BASE1_LO_REGISTER, (UINT8)(WPCN381U_GPIO_BASE_ADDRESS & 0x00FF)},           // Set Base Address LSB\r
+    {WPCN381U_ACTIVATE_REGISTER, WPCN381U_ACTIVATE_VALUE},                                // Enable it with Activation bit\r
+    {0x21, 0x001},                                                                        // Global Device Enable\r
+    {0x26, 0x000}\r
+};\r
+\r
+EFI_SIO_TABLE mSioTableWdcp376[] = {\r
+    {0x29, 0x0A0},\r
+    {WPCN381U_LD_SEL_REGISTER, WPCN381U_LDN_UART0},                                       // Select UART0 device\r
+    {WPCN381U_BASE1_HI_REGISTER, (UINT8)(WPCN381U_SERIAL_PORT0_BASE_ADDRESS >> 8)},       // Set Base Address MSB\r
+    {WPCN381U_BASE1_LO_REGISTER, (UINT8)(WPCN381U_SERIAL_PORT0_BASE_ADDRESS & 0x00FF)},   // Set Base Address LSB\r
+    {WPCN381U_IRQ1_REGISTER, 0x014},                                                      // Set to IRQ4\r
+    {WPCN381U_ACTIVATE_REGISTER, WPCN381U_ACTIVATE_VALUE},                                // Enable it with Activation bit\r
+    {WPCN381U_LD_SEL_REGISTER, WPCN381U_LDN_UART1},                                       // Select UART1 device\r
+    {WPCN381U_BASE1_HI_REGISTER, (UINT8)(WPCN381U_SERIAL_PORT1_BASE_ADDRESS >> 8)},       // Set Base Address MSB\r
+    {WPCN381U_BASE1_LO_REGISTER, (UINT8)(WPCN381U_SERIAL_PORT1_BASE_ADDRESS & 0x00FF)},   // Set Base Address LSB\r
+    {WPCN381U_IRQ1_REGISTER, 0x013},                                                      // Set to IRQ3\r
+    {WPCN381U_ACTIVATE_REGISTER, WPCN381U_ACTIVATE_VALUE},                                // Enable it with Activation bit\r
+    {WPCN381U_LD_SEL_REGISTER, WPCN381U_LDN_GPIO},                                        // Select GPIO device\r
+    {WPCN381U_BASE1_HI_REGISTER, (UINT8)(WPCN381U_GPIO_BASE_ADDRESS >> 8)},               // Set Base Address MSB\r
+    {WPCN381U_BASE1_LO_REGISTER, (UINT8)(WPCN381U_GPIO_BASE_ADDRESS & 0x00FF)},           // Set Base Address LSB\r
+    {WPCN381U_ACTIVATE_REGISTER, WPCN381U_ACTIVATE_VALUE},                                // Enable it with Activation bit\r
+    {0x21, 0x001},                                                                        // Global Device Enable\r
+    {0x26, 0x000},\r
+    {WPCN381U_LD_SEL_REGISTER, WPCN381U_LDN_PS2K},                                        // Select PS2 Keyboard\r
+    {WPCN381U_BASE1_HI_REGISTER, (UINT8)(WPCN381U_KB_BASE1_ADDRESS >> 8)},                // Set Base Address MSB\r
+    {WPCN381U_BASE1_LO_REGISTER, (UINT8)(WPCN381U_KB_BASE1_ADDRESS & 0x00FF)},            // Set Base Address LSB\r
+    {WPCN381U_BASE2_HI_REGISTER, (UINT8)(WPCN381U_KB_BASE2_ADDRESS >> 8)},                // Set Base Address MSB\r
+    {WPCN381U_BASE2_LO_REGISTER, (UINT8)(WPCN381U_KB_BASE2_ADDRESS & 0x00FF)},            // Set Base Address LSB\r
+    {WPCN381U_IRQ1_REGISTER, 0x011},                                                      // Set to IRQ1\r
+    {0xF0, (SIO_KBC_CLOCK << 6)},                                                         // Select KBC Clock Source\r
+    {WPCN381U_ACTIVATE_REGISTER, WPCN381U_ACTIVATE_VALUE},                                // Enable it with Activation bit\r
+    {WPCN381U_LD_SEL_REGISTER, WPCN381U_LDN_PS2M},                                        // Select PS2 Mouse\r
+    {WPCN381U_IRQ1_REGISTER, 0x01c},                                                      // Set to IRQ12\r
+    {WPCN381U_ACTIVATE_REGISTER, WPCN381U_ACTIVATE_VALUE}                                 // Enable it with Activation bit\r
+};\r
+\r
+/**\r
+  Initialization for SIO.\r
+\r
+  @param FfsHeader     FV this PEIM was loaded from.\r
+  @param PeiServices   General purpose services available to every PEIM.\r
+\r
+  None\r
+\r
+**/\r
+VOID\r
+InitializeSio (\r
+  VOID\r
+  )\r
+{\r
+  UINT16          Index;\r
+  UINT16          IndexPort;\r
+  UINT16          DataPort;\r
+\r
+  //\r
+  // Super I/O initialization for Winbond WPCN381U\r
+  //\r
+  IndexPort  = WPCN381U_CONFIG_INDEX;\r
+  DataPort   = WPCN381U_CONFIG_DATA;\r
+\r
+  //\r
+  // Check for Winbond WPCN381U\r
+  //\r
+  IoWrite8 (IndexPort, WPCN381U_DEV_ID_REGISTER);   // Winbond WPCN381U Device ID register is 0x20\r
+\r
+  if (IoRead8 (DataPort) == WPCN381U_CHIP_ID) {   // Winbond WPCN381U Device ID is 0xF4\r
+    //\r
+    // Configure WPCN381U SIO\r
+    //\r
+    for (Index = 0; Index < sizeof (mSioTableWpcn381u) / sizeof (EFI_SIO_TABLE); Index++) {\r
+      IoWrite8 (IndexPort, mSioTableWpcn381u[Index].Register);\r
+      IoWrite8 (DataPort, mSioTableWpcn381u[Index].Value);\r
+    }\r
+  }\r
+\r
+  if (IoRead8 (DataPort) == WDCP376_CHIP_ID) {   // Winbond WDCP376 Device ID is 0xF1\r
+    //\r
+    // Configure WDCP376 SIO\r
+    //\r
+    for (Index = 0; Index < sizeof (mSioTableWdcp376) / sizeof (EFI_SIO_TABLE); Index++) {\r
+      IoWrite8 (IndexPort, mSioTableWdcp376[Index].Register);\r
+      IoWrite8 (DataPort, mSioTableWdcp376[Index].Value);\r
+    }\r
+  }\r
+  return;\r
+}\r

diff --git a/Vlv2TbltDevicePkg/Library/SerialPortLib/SioInit.h b/Vlv2TbltDevicePkg/Library/SerialPortLib/SioInit.h
new file mode 100644 (file)
index 0000000..cded45c
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Library/SerialPortLib/SioInit.h
@@ -0,0 +1,78 @@
+/** @file\r
+  Header file of Serial port hardware definition.\r
+\r
+  Copyright (c) 2012  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+  This software and associated documentation\r
+  (if any) is furnished under a license and may only be used or\r
+  copied in accordance with the terms of the license.  Except as\r
+  permitted by such license, no part of this software or\r
+  documentation may be reproduced, stored in a retrieval system, or\r
+  transmitted in any form or by any means without the express written\r
+  consent of Intel Corporation.\r
+\r
+  Module Name:  PlatformSerialPortLib.h\r
+\r
+**/\r
+\r
+#ifndef _SIO_INIT_H_\r
+#define _SIO_INIT_H_\r
+\r
+#define WPCN381U_CONFIG_INDEX               0x2E\r
+#define WPCN381U_CONFIG_DATA                0x2F\r
+#define WPCN381U_CONFIG_INDEX1              0x164E\r
+#define WPCN381U_CONFIG_DATA1               0x164F\r
+#define WPCN381U_CHIP_ID                    0xF4\r
+#define WDCP376_CHIP_ID                     0xF1\r
+\r
+//\r
+// SIO Logical Devices Numbers\r
+//\r
+#define WPCN381U_LDN_UART0                  0x03   // LDN for Serial Port Controller\r
+#define WPCN381U_LDN_UART1                  0x02   // LDN for Parallel Port Controller\r
+#define WPCN381U_LDN_PS2K                   0x06   // LDN for PS2 Keyboard Controller\r
+#define WPCN381U_LDN_PS2M                   0x05   // LDN for PS2 Mouse Controller\r
+#define WPCN381U_KB_BASE1_ADDRESS           0x60   // Base Address of KB controller\r
+#define WPCN381U_KB_BASE2_ADDRESS           0x64   // Base Address of KB controller\r
+#define SIO_KBC_CLOCK                       0x01   // 0/1/2 - 8/12/16 MHz KBC Clock Source\r
+#define WPCN381U_LDN_GPIO                   0x07   // LDN for GPIO\r
+\r
+//\r
+// SIO Registers Layout\r
+//\r
+#define WPCN381U_LD_SEL_REGISTER            0x07   // Logical Device Select Register Address\r
+#define WPCN381U_DEV_ID_REGISTER            0x20   // Device Identification Register Address\r
+#define WPCN381U_ACTIVATE_REGISTER          0x30   // Device Identification Register Address\r
+#define WPCN381U_BASE1_HI_REGISTER          0x60   // Device BaseAddres Register #1 MSB Address\r
+#define WPCN381U_BASE1_LO_REGISTER          0x61   // Device BaseAddres Register #1 LSB Address\r
+#define WPCN381U_BASE2_HI_REGISTER          0x62   // Device BaseAddres Register #1 MSB Address\r
+#define WPCN381U_BASE2_LO_REGISTER          0x63   // Device Ba1eAddres Register #1 LSB Address\r
+#define WPCN381U_IRQ1_REGISTER              0x70   // Device IRQ Register #1 Address\r
+#define WPCN381U_IRQ2_REGISTER              0x71   // Device IRQ Register #2 Address\r
+\r
+//\r
+// SIO Activation Values\r
+//\r
+#define WPCN381U_ACTIVATE_VALUE             0x01   // Value to activate Device\r
+#define WPCN381U_DEACTIVATE_VALUE           0x00   // Value to deactivate Device\r
+\r
+//\r
+// SIO GPIO\r
+//\r
+#define WPCN381U_GPIO_BASE_ADDRESS          0x0A20 // SIO GPIO Base Address\r
+\r
+//\r
+// SIO Serial Port Settings\r
+//\r
+#define WPCN381U_SERIAL_PORT0_BASE_ADDRESS  0x03F8 // Base Address of Serial Port 0 (COMA / UART0)\r
+#define WPCN381U_SERIAL_PORT1_BASE_ADDRESS  0x02F8 // Base Address of Serial Port 1 (COMB / UART1)\r
+\r
+#endif\r

diff --git a/Vlv2TbltDevicePkg/Library/SmbusLib/CommonHeader.h b/Vlv2TbltDevicePkg/Library/SmbusLib/CommonHeader.h
new file mode 100644 (file)
index 0000000..430672f
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Library/SmbusLib/CommonHeader.h
@@ -0,0 +1,31 @@
+/**@file\r
+  Common header file shared by all source files.\r
+\r
+  This file includes package header files, library classes.\r
+\r
+  Copyright (c) 2010 - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+**/\r
+\r
+#ifndef __COMMON_HEADER_H_\r
+#define __COMMON_HEADER_H_\r
+\r
+\r
+#include <Base.h>\r
+#include <PchAccess.h>\r
+\r
+#include <Library/SmbusLib.h>\r
+#include <Library/IoLib.h>\r
+#include <Library/PciLib.h>\r
+#include <Library/DebugLib.h>\r
+#include <Library/PcdLib.h>\r
+\r
+#endif\r

diff --git a/Vlv2TbltDevicePkg/Library/SmbusLib/SmbusLib.c b/Vlv2TbltDevicePkg/Library/SmbusLib/SmbusLib.c
new file mode 100644 (file)
index 0000000..8ca472d
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Library/SmbusLib/SmbusLib.c
@@ -0,0 +1,878 @@
+/** @file\r
+  Intel ICH9 SMBUS library implementation built upon I/O library.\r
+\r
+  Copyright (c) 2010 - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+**/\r
+\r
+#include "CommonHeader.h"\r
+\r
+/**\r
+  Gets Io port base address of Smbus Host Controller.\r
+\r
+  This internal function depends on a feature flag named PcdIchSmbusFixedIoPortBaseAddress\r
+  to retrieve Smbus Io port base. If that feature flag is true, it will get Smbus Io port base\r
+  address from a preset Pcd entry named PcdIchSmbusIoPortBaseAddress; otherwise, it will always\r
+  read Pci configuration space to get that value in each Smbus bus transaction.\r
+\r
+  @return The Io port base address of Smbus host controller.\r
+\r
+**/\r
+UINTN\r
+InternalGetSmbusIoPortBaseAddress (\r
+  VOID\r
+  )\r
+{\r
+  UINTN     IoPortBaseAddress;\r
+\r
+  IoPortBaseAddress = (UINTN) MmioRead32 (MmPciAddress (0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_SMBUS, PCI_FUNCTION_NUMBER_PCH_SMBUS, R_PCH_SMBUS_BASE)) & B_PCH_SMBUS_BASE_BAR;\r
+\r
+  //\r
+  // Make sure that the IO port base address has been properly set.\r
+  //\r
+  ASSERT (IoPortBaseAddress != 0);\r
+\r
+  return IoPortBaseAddress;\r
+}\r
+\r
+/**\r
+  Acquires the ownership of SMBUS.\r
+\r
+  This internal function reads the host state register.\r
+  If the SMBUS is not available, RETURN_TIMEOUT is returned;\r
+  Otherwise, it performs some basic initializations and returns\r
+  RETURN_SUCCESS.\r
+\r
+  @param  IoPortBaseAddress The Io port base address of Smbus Host controller.\r
+\r
+  @retval RETURN_SUCCESS    The SMBUS command was executed successfully.\r
+  @retval RETURN_TIMEOUT    A timeout occurred while executing the SMBUS command.\r
+\r
+**/\r
+RETURN_STATUS\r
+InternalSmBusAcquire (\r
+  UINTN                     IoPortBaseAddress\r
+  )\r
+{\r
+  UINT8   HostStatus;\r
+\r
+  HostStatus = IoRead8 (IoPortBaseAddress + R_PCH_SMBUS_HSTS);\r
+  if ((HostStatus & B_PCH_SMBUS_IUS) != 0) {\r
+    return RETURN_TIMEOUT;\r
+  } else if ((HostStatus & B_PCH_SMBUS_HBSY) != 0) {\r
+    //\r
+    // Clear host status register and exit.\r
+    //\r
+    IoWrite8 (IoPortBaseAddress + R_PCH_SMBUS_HSTS, B_PCH_SMBUS_HSTS_ALL);\r
+    return RETURN_TIMEOUT;\r
+  }\r
+  //\r
+  // Clear out any odd status information (Will Not Clear In Use).\r
+  //\r
+  IoWrite8 (IoPortBaseAddress + R_PCH_SMBUS_HSTS, HostStatus);\r
+\r
+  return RETURN_SUCCESS;\r
+}\r
+\r
+/**\r
+  Starts the SMBUS transaction and waits until the end.\r
+\r
+  This internal function start the SMBUS transaction and waits until the transaction\r
+  of SMBUS is over by polling the INTR bit of Host status register.\r
+  If the SMBUS is not available, RETURN_TIMEOUT is returned;\r
+  Otherwise, it performs some basic initializations and returns\r
+  RETURN_SUCCESS.\r
+\r
+  @param  IoPortBaseAddress   The Io port base address of Smbus Host controller.\r
+  @param  HostControl         The Host control command to start SMBUS transaction.\r
+\r
+  @retval RETURN_SUCCESS      The SMBUS command was executed successfully.\r
+  @retval RETURN_CRC_ERROR    The checksum is not correct (PEC is incorrect).\r
+  @retval RETURN_DEVICE_ERROR The request was not completed because a failure reflected\r
+                              in the Host Status Register bit.  Device errors are\r
+                              a result of a transaction collision, illegal command field,\r
+                              unclaimed cycle (host initiated), or bus errors (collisions).\r
+\r
+**/\r
+RETURN_STATUS\r
+InternalSmBusStart (\r
+  IN  UINTN                   IoPortBaseAddress,\r
+  IN  UINT8                   HostControl\r
+  )\r
+{\r
+  UINT8   HostStatus;\r
+  UINT8   AuxiliaryStatus;\r
+\r
+  //\r
+  // Set Host Control Register (Initiate Operation, Interrupt disabled).\r
+  //\r
+  IoWrite8 (IoPortBaseAddress + R_PCH_SMBUS_HCTL, (UINT8)(HostControl + B_PCH_SMBUS_START));\r
+\r
+  do {\r
+    //\r
+    // Poll INTR bit of Host Status Register.\r
+    //\r
+    HostStatus = IoRead8 (IoPortBaseAddress + R_PCH_SMBUS_HSTS);\r
+  } while ((HostStatus & (B_PCH_SMBUS_INTR | B_PCH_SMBUS_ERRORS | B_PCH_SMBUS_BYTE_DONE_STS)) == 0);\r
+\r
+  if ((HostStatus & B_PCH_SMBUS_ERRORS) == 0) {\r
+    return RETURN_SUCCESS;\r
+  }\r
+\r
+  //\r
+  // Clear error bits of Host Status Register.\r
+  //\r
+  IoWrite8 (IoPortBaseAddress + R_PCH_SMBUS_HSTS, B_PCH_SMBUS_ERRORS);\r
+\r
+  //\r
+  // Read Auxiliary Status Register to judge CRC error.\r
+  //\r
+  AuxiliaryStatus = IoRead8 (IoPortBaseAddress + R_PCH_SMBUS_AUXS);\r
+  if ((AuxiliaryStatus & B_PCH_SMBUS_CRCE) != 0) {\r
+    return RETURN_CRC_ERROR;\r
+  }\r
+\r
+  return RETURN_DEVICE_ERROR;\r
+}\r
+\r
+/**\r
+  Executes an SMBUS quick, byte or word command.\r
+\r
+  This internal function executes an SMBUS quick, byte or word commond.\r
+  If Status is not NULL, then the status of the executed command is returned in Status.\r
+\r
+  @param  HostControl     The value of Host Control Register to set.\r
+  @param  SmBusAddress    Address that encodes the SMBUS Slave Address,\r
+                          SMBUS Command, SMBUS Data Length, and PEC.\r
+  @param  Value           The byte/word write to the SMBUS.\r
+  @param  Status          Return status for the executed command.\r
+                          This is an optional parameter and may be NULL.\r
+\r
+  @return The byte/word read from the SMBUS.\r
+\r
+**/\r
+UINT16\r
+InternalSmBusNonBlock (\r
+  IN  UINT8                     HostControl,\r
+  IN  UINTN                     SmBusAddress,\r
+  IN  UINT16                    Value,\r
+  OUT RETURN_STATUS             *Status\r
+  )\r
+{\r
+  RETURN_STATUS                 ReturnStatus;\r
+  UINTN                         IoPortBaseAddress;\r
+  UINT8                         AuxiliaryControl;\r
+\r
+  IoPortBaseAddress = InternalGetSmbusIoPortBaseAddress ();\r
+\r
+  //\r
+  // Try to acquire the ownership of ICH SMBUS.\r
+  //\r
+  ReturnStatus = InternalSmBusAcquire (IoPortBaseAddress);\r
+  if (RETURN_ERROR (ReturnStatus)) {\r
+    goto Done;\r
+  }\r
+\r
+  //\r
+  // Set the appropriate Host Control Register and auxiliary Control Register.\r
+  //\r
+  AuxiliaryControl = 0;\r
+  if (SMBUS_LIB_PEC (SmBusAddress)) {\r
+    AuxiliaryControl |= B_PCH_SMBUS_AAC;\r
+    HostControl      |= B_PCH_SMBUS_PEC_EN;\r
+  }\r
+\r
+  //\r
+  // Set Host Command Register.\r
+  //\r
+  IoWrite8 (IoPortBaseAddress + R_PCH_SMBUS_HCMD, (UINT8) SMBUS_LIB_COMMAND (SmBusAddress));\r
+\r
+  //\r
+  // Write value to Host Data 0 and Host Data 1 Registers.\r
+  //\r
+  IoWrite8 (IoPortBaseAddress + R_PCH_SMBUS_HD0, (UINT8) Value);\r
+  IoWrite8 (IoPortBaseAddress + R_PCH_SMBUS_HD1, (UINT8) (Value >> 8));\r
+\r
+  //\r
+  // Set Auxiliary Control Register.\r
+  //\r
+  IoWrite8 (IoPortBaseAddress + R_PCH_SMBUS_AUXC, AuxiliaryControl);\r
+\r
+  //\r
+  // Set SMBUS slave address for the device to send/receive from.\r
+  //\r
+  IoWrite8 (IoPortBaseAddress + R_PCH_SMBUS_TSA, (UINT8) SmBusAddress);\r
+\r
+  //\r
+  // Start the SMBUS transaction and wait for the end.\r
+  //\r
+  ReturnStatus = InternalSmBusStart (IoPortBaseAddress, HostControl);\r
+\r
+  //\r
+  // Read value from Host Data 0 and Host Data 1 Registers.\r
+  //\r
+  Value = (UINT16)(IoRead8 (IoPortBaseAddress + R_PCH_SMBUS_HD1) << 8);\r
+  Value = (UINT16)(Value | IoRead8 (IoPortBaseAddress + R_PCH_SMBUS_HD0));\r
+\r
+  //\r
+  // Clear Host Status Register and Auxiliary Status Register.\r
+  //\r
+  IoWrite8 (IoPortBaseAddress + R_PCH_SMBUS_HSTS, B_PCH_SMBUS_HSTS_ALL);\r
+  IoWrite8 (IoPortBaseAddress + R_PCH_SMBUS_AUXS, B_PCH_SMBUS_CRCE);\r
+\r
+Done:\r
+  if (Status != NULL) {\r
+    *Status = ReturnStatus;\r
+  }\r
+\r
+  return Value;\r
+}\r
+\r
+/**\r
+  Executes an SMBUS quick read command.\r
+\r
+  Executes an SMBUS quick read command on the SMBUS device specified by SmBusAddress.\r
+  Only the SMBUS slave address field of SmBusAddress is required.\r
+  If Status is not NULL, then the status of the executed command is returned in Status.\r
+  If PEC is set in SmBusAddress, then ASSERT().\r
+  If Command in SmBusAddress is not zero, then ASSERT().\r
+  If Length in SmBusAddress is not zero, then ASSERT().\r
+  If any reserved bits of SmBusAddress are set, then ASSERT().\r
+\r
+  @param  SmBusAddress    Address that encodes the SMBUS Slave Address,\r
+                          SMBUS Command, SMBUS Data Length, and PEC.\r
+  @param  Status          Return status for the executed command.\r
+                          This is an optional parameter and may be NULL.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+SmBusQuickRead (\r
+  IN  UINTN                     SmBusAddress,\r
+  OUT RETURN_STATUS             *Status       OPTIONAL\r
+  )\r
+{\r
+  ASSERT (!SMBUS_LIB_PEC (SmBusAddress));\r
+  ASSERT (SMBUS_LIB_COMMAND (SmBusAddress)   == 0);\r
+  ASSERT (SMBUS_LIB_LENGTH (SmBusAddress)    == 0);\r
+  ASSERT (SMBUS_LIB_RESERVED (SmBusAddress)  == 0);\r
+\r
+  InternalSmBusNonBlock (\r
+    V_PCH_SMBUS_SMB_CMD_QUICK,\r
+    SmBusAddress | B_PCH_SMBUS_RW_SEL_READ,\r
+    0,\r
+    Status\r
+    );\r
+}\r
+\r
+/**\r
+  Executes an SMBUS quick write command.\r
+\r
+  Executes an SMBUS quick write command on the SMBUS device specified by SmBusAddress.\r
+  Only the SMBUS slave address field of SmBusAddress is required.\r
+  If Status is not NULL, then the status of the executed command is returned in Status.\r
+  If PEC is set in SmBusAddress, then ASSERT().\r
+  If Command in SmBusAddress is not zero, then ASSERT().\r
+  If Length in SmBusAddress is not zero, then ASSERT().\r
+  If any reserved bits of SmBusAddress are set, then ASSERT().\r
+\r
+  @param  SmBusAddress    Address that encodes the SMBUS Slave Address,\r
+                          SMBUS Command, SMBUS Data Length, and PEC.\r
+  @param  Status          Return status for the executed command.\r
+                          This is an optional parameter and may be NULL.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+SmBusQuickWrite (\r
+  IN  UINTN                     SmBusAddress,\r
+  OUT RETURN_STATUS             *Status       OPTIONAL\r
+  )\r
+{\r
+  ASSERT (!SMBUS_LIB_PEC (SmBusAddress));\r
+  ASSERT (SMBUS_LIB_COMMAND (SmBusAddress)   == 0);\r
+  ASSERT (SMBUS_LIB_LENGTH (SmBusAddress)    == 0);\r
+  ASSERT (SMBUS_LIB_RESERVED (SmBusAddress) == 0);\r
+\r
+  InternalSmBusNonBlock (\r
+    V_PCH_SMBUS_SMB_CMD_QUICK,\r
+    SmBusAddress | B_PCH_SMBUS_RW_SEL_WRITE,\r
+    0,\r
+    Status\r
+    );\r
+}\r
+\r
+/**\r
+  Executes an SMBUS receive byte command.\r
+\r
+  Executes an SMBUS receive byte command on the SMBUS device specified by SmBusAddress.\r
+  Only the SMBUS slave address field of SmBusAddress is required.\r
+  The byte received from the SMBUS is returned.\r
+  If Status is not NULL, then the status of the executed command is returned in Status.\r
+  If Command in SmBusAddress is not zero, then ASSERT().\r
+  If Length in SmBusAddress is not zero, then ASSERT().\r
+  If any reserved bits of SmBusAddress are set, then ASSERT().\r
+\r
+  @param  SmBusAddress    Address that encodes the SMBUS Slave Address,\r
+                          SMBUS Command, SMBUS Data Length, and PEC.\r
+  @param  Status          Return status for the executed command.\r
+                          This is an optional parameter and may be NULL.\r
+\r
+  @return The byte received from the SMBUS.\r
+\r
+**/\r
+UINT8\r
+EFIAPI\r
+SmBusReceiveByte (\r
+  IN  UINTN          SmBusAddress,\r
+  OUT RETURN_STATUS  *Status        OPTIONAL\r
+  )\r
+{\r
+  UINT8 ValueReturn = 0;\r
+\r
+  ASSERT (SMBUS_LIB_COMMAND (SmBusAddress)   == 0);\r
+  ASSERT (SMBUS_LIB_LENGTH (SmBusAddress)    == 0);\r
+  ASSERT (SMBUS_LIB_RESERVED (SmBusAddress) == 0);\r
+\r
+  ValueReturn = (UINT8) InternalSmBusNonBlock (\r
+                   V_PCH_SMBUS_SMB_CMD_BYTE,\r
+                   SmBusAddress | B_PCH_SMBUS_RW_SEL_READ,\r
+                   0,\r
+                   Status\r
+                   );\r
+  return ValueReturn;\r
+\r
+  }\r
+\r
+/**\r
+  Executes an SMBUS send byte command.\r
+\r
+  Executes an SMBUS send byte command on the SMBUS device specified by SmBusAddress.\r
+  The byte specified by Value is sent.\r
+  Only the SMBUS slave address field of SmBusAddress is required.  Value is returned.\r
+  If Status is not NULL, then the status of the executed command is returned in Status.\r
+  If Command in SmBusAddress is not zero, then ASSERT().\r
+  If Length in SmBusAddress is not zero, then ASSERT().\r
+  If any reserved bits of SmBusAddress are set, then ASSERT().\r
+\r
+  @param  SmBusAddress    Address that encodes the SMBUS Slave Address,\r
+                          SMBUS Command, SMBUS Data Length, and PEC.\r
+  @param  Value           The 8-bit value to send.\r
+  @param  Status          Return status for the executed command.\r
+                          This is an optional parameter and may be NULL.\r
+\r
+  @return The parameter of Value.\r
+\r
+**/\r
+UINT8\r
+EFIAPI\r
+SmBusSendByte (\r
+  IN  UINTN          SmBusAddress,\r
+  IN  UINT8          Value,\r
+  OUT RETURN_STATUS  *Status        OPTIONAL\r
+  )\r
+{\r
+  UINT8 ValueReturn = 0;\r
+\r
+  ASSERT (SMBUS_LIB_COMMAND (SmBusAddress)   == 0);\r
+  ASSERT (SMBUS_LIB_LENGTH (SmBusAddress)    == 0);\r
+  ASSERT (SMBUS_LIB_RESERVED (SmBusAddress) == 0);\r
+\r
+  ValueReturn = (UINT8) InternalSmBusNonBlock (\r
+                          V_PCH_SMBUS_SMB_CMD_BYTE,\r
+                          SmBusAddress | B_PCH_SMBUS_RW_SEL_WRITE,\r
+                          Value,\r
+                          Status\r
+                          );\r
+  return ValueReturn;\r
+\r
+  }\r
+\r
+/**\r
+  Executes an SMBUS read data byte command.\r
+\r
+  Executes an SMBUS read data byte command on the SMBUS device specified by SmBusAddress.\r
+  Only the SMBUS slave address and SMBUS command fields of SmBusAddress are required.\r
+  The 8-bit value read from the SMBUS is returned.\r
+  If Status is not NULL, then the status of the executed command is returned in Status.\r
+  If Length in SmBusAddress is not zero, then ASSERT().\r
+  If any reserved bits of SmBusAddress are set, then ASSERT().\r
+\r
+  @param  SmBusAddress    Address that encodes the SMBUS Slave Address,\r
+                          SMBUS Command, SMBUS Data Length, and PEC.\r
+  @param  Status          Return status for the executed command.\r
+                          This is an optional parameter and may be NULL.\r
+\r
+  @return The byte read from the SMBUS.\r
+\r
+**/\r
+UINT8\r
+EFIAPI\r
+SmBusReadDataByte (\r
+  IN  UINTN          SmBusAddress,\r
+  OUT RETURN_STATUS  *Status        OPTIONAL\r
+  )\r
+{\r
+  UINT8 ValueReturn = 0;\r
+\r
+  ASSERT (SMBUS_LIB_LENGTH (SmBusAddress)    == 0);\r
+  ASSERT (SMBUS_LIB_RESERVED (SmBusAddress) == 0);\r
+   ValueReturn = (UINT8) InternalSmBusNonBlock (\r
+                           V_PCH_SMBUS_SMB_CMD_BYTE_DATA,\r
+                           SmBusAddress | B_PCH_SMBUS_RW_SEL_READ,\r
+                           0,\r
+                           Status\r
+                           );\r
+  return ValueReturn;\r
+}\r
+\r
+/**\r
+  Executes an SMBUS write data byte command.\r
+\r
+  Executes an SMBUS write data byte command on the SMBUS device specified by SmBusAddress.\r
+  The 8-bit value specified by Value is written.\r
+  Only the SMBUS slave address and SMBUS command fields of SmBusAddress are required.\r
+  Value is returned.\r
+  If Status is not NULL, then the status of the executed command is returned in Status.\r
+  If Length in SmBusAddress is not zero, then ASSERT().\r
+  If any reserved bits of SmBusAddress are set, then ASSERT().\r
+\r
+  @param  SmBusAddress    Address that encodes the SMBUS Slave Address,\r
+                          SMBUS Command, SMBUS Data Length, and PEC.\r
+  @param  Value           The 8-bit value to write.\r
+  @param  Status          Return status for the executed command.\r
+                          This is an optional parameter and may be NULL.\r
+\r
+  @return The parameter of Value.\r
+\r
+**/\r
+UINT8\r
+EFIAPI\r
+SmBusWriteDataByte (\r
+  IN  UINTN          SmBusAddress,\r
+  IN  UINT8          Value,\r
+  OUT RETURN_STATUS  *Status        OPTIONAL\r
+  )\r
+{\r
+  UINT8 ValueReturn = 0;\r
+\r
+  ASSERT (SMBUS_LIB_LENGTH (SmBusAddress)    == 0);\r
+  ASSERT (SMBUS_LIB_RESERVED (SmBusAddress) == 0);\r
+\r
+  ValueReturn = (UINT8) InternalSmBusNonBlock (\r
+                          V_PCH_SMBUS_SMB_CMD_BYTE_DATA,\r
+                          SmBusAddress | B_PCH_SMBUS_RW_SEL_WRITE,\r
+                          Value,\r
+                          Status\r
+                          );\r
+  return ValueReturn;\r
+\r
+}\r
+\r
+/**\r
+  Executes an SMBUS read data word command.\r
+\r
+  Executes an SMBUS read data word command on the SMBUS device specified by SmBusAddress.\r
+  Only the SMBUS slave address and SMBUS command fields of SmBusAddress are required.\r
+  The 16-bit value read from the SMBUS is returned.\r
+  If Status is not NULL, then the status of the executed command is returned in Status.\r
+  If Length in SmBusAddress is not zero, then ASSERT().\r
+  If any reserved bits of SmBusAddress are set, then ASSERT().\r
+\r
+  @param  SmBusAddress    Address that encodes the SMBUS Slave Address,\r
+                          SMBUS Command, SMBUS Data Length, and PEC.\r
+  @param  Status          Return status for the executed command.\r
+                          This is an optional parameter and may be NULL.\r
+\r
+  @return The byte read from the SMBUS.\r
+\r
+**/\r
+UINT16\r
+EFIAPI\r
+SmBusReadDataWord (\r
+  IN  UINTN          SmBusAddress,\r
+  OUT RETURN_STATUS  *Status        OPTIONAL\r
+  )\r
+{\r
+  UINT16 ValueReturn = 0;\r
+  ASSERT (SMBUS_LIB_LENGTH (SmBusAddress)    == 0);\r
+  ASSERT (SMBUS_LIB_RESERVED (SmBusAddress) == 0);\r
+\r
+  ValueReturn = InternalSmBusNonBlock (\r
+                  V_PCH_SMBUS_SMB_CMD_WORD_DATA,\r
+                  SmBusAddress | B_PCH_SMBUS_RW_SEL_READ,\r
+                  0,\r
+                  Status\r
+                  );\r
+  return ValueReturn;\r
+\r
+}\r
+\r
+/**\r
+  Executes an SMBUS write data word command.\r
+\r
+  Executes an SMBUS write data word command on the SMBUS device specified by SmBusAddress.\r
+  The 16-bit value specified by Value is written.\r
+  Only the SMBUS slave address and SMBUS command fields of SmBusAddress are required.\r
+  Value is returned.\r
+  If Status is not NULL, then the status of the executed command is returned in Status.\r
+  If Length in SmBusAddress is not zero, then ASSERT().\r
+  If any reserved bits of SmBusAddress are set, then ASSERT().\r
+\r
+  @param  SmBusAddress    Address that encodes the SMBUS Slave Address,\r
+                          SMBUS Command, SMBUS Data Length, and PEC.\r
+  @param  Value           The 16-bit value to write.\r
+  @param  Status          Return status for the executed command.\r
+                          This is an optional parameter and may be NULL.\r
+\r
+  @return The parameter of Value.\r
+\r
+**/\r
+UINT16\r
+EFIAPI\r
+SmBusWriteDataWord (\r
+  IN  UINTN          SmBusAddress,\r
+  IN  UINT16         Value,\r
+  OUT RETURN_STATUS  *Status        OPTIONAL\r
+  )\r
+{\r
+  UINT16 ValueReturn = 0;\r
+  ASSERT (SMBUS_LIB_LENGTH (SmBusAddress)    == 0);\r
+  ASSERT (SMBUS_LIB_RESERVED (SmBusAddress) == 0);\r
+\r
+  ValueReturn = InternalSmBusNonBlock (\r
+                  V_PCH_SMBUS_SMB_CMD_WORD_DATA,\r
+                  SmBusAddress | B_PCH_SMBUS_RW_SEL_WRITE,\r
+                  Value,\r
+                  Status\r
+                  );\r
+  return ValueReturn;\r
+}\r
+\r
+/**\r
+  Executes an SMBUS process call command.\r
+\r
+  Executes an SMBUS process call command on the SMBUS device specified by SmBusAddress.\r
+  The 16-bit value specified by Value is written.\r
+  Only the SMBUS slave address and SMBUS command fields of SmBusAddress are required.\r
+  The 16-bit value returned by the process call command is returned.\r
+  If Status is not NULL, then the status of the executed command is returned in Status.\r
+  If Length in SmBusAddress is not zero, then ASSERT().\r
+  If any reserved bits of SmBusAddress are set, then ASSERT().\r
+\r
+  @param  SmBusAddress    Address that encodes the SMBUS Slave Address,\r
+                          SMBUS Command, SMBUS Data Length, and PEC.\r
+  @param  Value           The 16-bit value to write.\r
+  @param  Status          Return status for the executed command.\r
+                          This is an optional parameter and may be NULL.\r
+\r
+  @return The 16-bit value returned by the process call command.\r
+\r
+**/\r
+UINT16\r
+EFIAPI\r
+SmBusProcessCall (\r
+  IN  UINTN          SmBusAddress,\r
+  IN  UINT16         Value,\r
+  OUT RETURN_STATUS  *Status        OPTIONAL\r
+  )\r
+{\r
+  UINT16 ValueReturn = 0;\r
+  ASSERT (SMBUS_LIB_LENGTH (SmBusAddress)    == 0);\r
+  ASSERT (SMBUS_LIB_RESERVED (SmBusAddress) == 0);\r
+\r
+  ValueReturn = InternalSmBusNonBlock (\r
+                  V_PCH_SMBUS_SMB_CMD_PROCESS_CALL,\r
+                  SmBusAddress | B_PCH_SMBUS_RW_SEL_WRITE,\r
+                  Value,\r
+                  Status\r
+                  );\r
+  return ValueReturn;\r
+}\r
+\r
+/**\r
+  Executes an SMBUS block command.\r
+\r
+  Executes an SMBUS block read, block write and block write-block read command\r
+  on the SMBUS device specified by SmBusAddress.\r
+  Bytes are read from the SMBUS and stored in Buffer.\r
+  The number of bytes read is returned, and will never return a value larger than 32-bytes.\r
+  If Status is not NULL, then the status of the executed command is returned in Status.\r
+  It is the caller's responsibility to make sure Buffer is large enough for the total number of bytes read.\r
+  SMBUS supports a maximum transfer size of 32 bytes, so Buffer does not need to be any larger than 32 bytes.\r
+\r
+  @param  HostControl     The value of Host Control Register to set.\r
+  @param  SmBusAddress    Address that encodes the SMBUS Slave Address,\r
+                          SMBUS Command, SMBUS Data Length, and PEC.\r
+  @param  WriteBuffer     Pointer to the buffer of bytes to write to the SMBUS.\r
+  @param  ReadBuffer      Pointer to the buffer of bytes to read from the SMBUS.\r
+  @param  Status          Return status for the executed command.\r
+                          This is an optional parameter and may be NULL.\r
+\r
+  @return The number of bytes read from the SMBUS.\r
+\r
+**/\r
+UINTN\r
+InternalSmBusBlock (\r
+  IN  UINT8                     HostControl,\r
+  IN  UINTN                     SmBusAddress,\r
+  IN  UINT8                     *WriteBuffer,\r
+  OUT UINT8                     *ReadBuffer,\r
+  OUT RETURN_STATUS             *Status\r
+  )\r
+{\r
+  RETURN_STATUS                 ReturnStatus;\r
+  UINTN                         Index;\r
+  UINTN                         BytesCount;\r
+  UINTN                         IoPortBaseAddress;\r
+  UINT8                         AuxiliaryControl;\r
+\r
+  IoPortBaseAddress = InternalGetSmbusIoPortBaseAddress ();\r
+\r
+  BytesCount = SMBUS_LIB_LENGTH (SmBusAddress);\r
+\r
+  //\r
+  // Try to acquire the ownership of ICH SMBUS.\r
+  //\r
+  ReturnStatus = InternalSmBusAcquire (IoPortBaseAddress);\r
+  if (RETURN_ERROR (ReturnStatus)) {\r
+    goto Done;\r
+  }\r
+\r
+  //\r
+  // Set the appropriate Host Control Register and auxiliary Control Register.\r
+  //\r
+  AuxiliaryControl = B_PCH_SMBUS_E32B;\r
+  if (SMBUS_LIB_PEC (SmBusAddress)) {\r
+    AuxiliaryControl |= B_PCH_SMBUS_AAC;\r
+    HostControl      |= B_PCH_SMBUS_PEC_EN;\r
+  }\r
+\r
+  //\r
+  // Set Host Command Register.\r
+  //\r
+  IoWrite8 (IoPortBaseAddress + R_PCH_SMBUS_HCMD, (UINT8) SMBUS_LIB_COMMAND (SmBusAddress));\r
+\r
+  //\r
+  // Set Auxiliary Control Regiester.\r
+  //\r
+  IoWrite8 (IoPortBaseAddress + R_PCH_SMBUS_AUXC, AuxiliaryControl);\r
+\r
+  //\r
+  // Clear byte pointer of 32-byte buffer.\r
+  //\r
+  IoRead8 (IoPortBaseAddress + R_PCH_SMBUS_HCTL);\r
+\r
+  if (WriteBuffer != NULL) {\r
+    //\r
+    // Write the number of block to Host Block Data Byte Register.\r
+    //\r
+    IoWrite8 (IoPortBaseAddress + R_PCH_SMBUS_HD0, (UINT8) BytesCount);\r
+\r
+    //\r
+    // Write data block to Host Block Data Register.\r
+    //\r
+    for (Index = 0; Index < BytesCount; Index++) {\r
+      IoWrite8 (IoPortBaseAddress + R_PCH_SMBUS_HBD, WriteBuffer[Index]);\r
+    }\r
+  }\r
+\r
+  //\r
+  // Set SMBUS slave address for the device to send/receive from.\r
+  //\r
+  IoWrite8 (IoPortBaseAddress + R_PCH_SMBUS_TSA, (UINT8) SmBusAddress);\r
+\r
+  //\r
+  // Start the SMBUS transaction and wait for the end.\r
+  //\r
+  ReturnStatus = InternalSmBusStart (IoPortBaseAddress, HostControl);\r
+  if (RETURN_ERROR (ReturnStatus)) {\r
+    goto Done;\r
+  }\r
+\r
+  if (ReadBuffer != NULL) {\r
+    //\r
+    // Read the number of block from host block data byte register.\r
+    //\r
+    BytesCount = IoRead8 (IoPortBaseAddress + R_PCH_SMBUS_HD0);\r
+\r
+    //\r
+    // Write data block from Host Block Data Register.\r
+    //\r
+    for (Index = 0; Index < BytesCount; Index++) {\r
+      ReadBuffer[Index] = IoRead8 (IoPortBaseAddress + R_PCH_SMBUS_HBD);\r
+    }\r
+  }\r
+\r
+Done:\r
+  //\r
+  // Clear Host Status Register and Auxiliary Status Register.\r
+  //\r
+  IoWrite8 (IoPortBaseAddress + R_PCH_SMBUS_HSTS, B_PCH_SMBUS_HSTS_ALL);\r
+  IoWrite8 (IoPortBaseAddress + R_PCH_SMBUS_AUXS, B_PCH_SMBUS_CRCE);\r
+\r
+  if (Status != NULL) {\r
+    *Status = ReturnStatus;\r
+  }\r
+\r
+  return BytesCount;\r
+}\r
+\r
+/**\r
+  Executes an SMBUS read block command.\r
+\r
+  Executes an SMBUS read block command on the SMBUS device specified by SmBusAddress.\r
+  Only the SMBUS slave address and SMBUS command fields of SmBusAddress are required.\r
+  Bytes are read from the SMBUS and stored in Buffer.\r
+  The number of bytes read is returned, and will never return a value larger than 32-bytes.\r
+  If Status is not NULL, then the status of the executed command is returned in Status.\r
+  It is the caller's responsibility to make sure Buffer is large enough for the total number of bytes read.\r
+  SMBUS supports a maximum transfer size of 32 bytes, so Buffer does not need to be any larger than 32 bytes.\r
+  If Length in SmBusAddress is not zero, then ASSERT().\r
+  If Buffer is NULL, then ASSERT().\r
+  If any reserved bits of SmBusAddress are set, then ASSERT().\r
+\r
+  @param  SmBusAddress    Address that encodes the SMBUS Slave Address,\r
+                          SMBUS Command, SMBUS Data Length, and PEC.\r
+  @param  Buffer          Pointer to the buffer to store the bytes read from the SMBUS.\r
+  @param  Status          Return status for the executed command.\r
+                          This is an optional parameter and may be NULL.\r
+\r
+  @return The number of bytes read.\r
+\r
+**/\r
+UINTN\r
+EFIAPI\r
+SmBusReadBlock (\r
+  IN  UINTN          SmBusAddress,\r
+  OUT VOID           *Buffer,\r
+  OUT RETURN_STATUS  *Status        OPTIONAL\r
+  )\r
+{\r
+  UINTN BytesCount = 0;\r
+\r
+  ASSERT (Buffer != NULL);\r
+  ASSERT (SMBUS_LIB_LENGTH (SmBusAddress) == 0);\r
+  ASSERT (SMBUS_LIB_RESERVED (SmBusAddress) == 0);\r
+\r
+\r
+  BytesCount = InternalSmBusBlock (\r
+                 V_PCH_SMBUS_SMB_CMD_BLOCK,\r
+                 SmBusAddress | B_PCH_SMBUS_RW_SEL_READ,\r
+                 NULL,\r
+                 Buffer,\r
+                 Status\r
+                 );\r
+  return BytesCount;\r
+\r
+}\r
+\r
+/**\r
+  Executes an SMBUS write block command.\r
+\r
+  Executes an SMBUS write block command on the SMBUS device specified by SmBusAddress.\r
+  The SMBUS slave address, SMBUS command, and SMBUS length fields of SmBusAddress are required.\r
+  Bytes are written to the SMBUS from Buffer.\r
+  The number of bytes written is returned, and will never return a value larger than 32-bytes.\r
+  If Status is not NULL, then the status of the executed command is returned in Status.\r
+  If Length in SmBusAddress is zero or greater than 32, then ASSERT().\r
+  If Buffer is NULL, then ASSERT().\r
+  If any reserved bits of SmBusAddress are set, then ASSERT().\r
+\r
+  @param  SmBusAddress    Address that encodes the SMBUS Slave Address,\r
+                          SMBUS Command, SMBUS Data Length, and PEC.\r
+  @param  Buffer          Pointer to the buffer to store the bytes read from the SMBUS.\r
+  @param  Status          Return status for the executed command.\r
+                          This is an optional parameter and may be NULL.\r
+\r
+  @return The number of bytes written.\r
+\r
+**/\r
+UINTN\r
+EFIAPI\r
+SmBusWriteBlock (\r
+  IN  UINTN          SmBusAddress,\r
+  OUT VOID           *Buffer,\r
+  OUT RETURN_STATUS  *Status        OPTIONAL\r
+  )\r
+{\r
+  UINTN        BytesCount = 0;\r
+\r
+  ASSERT (Buffer != NULL);\r
+  ASSERT (SMBUS_LIB_LENGTH (SmBusAddress) >= 1);\r
+  ASSERT (SMBUS_LIB_LENGTH (SmBusAddress) <= 32);\r
+  ASSERT (SMBUS_LIB_RESERVED (SmBusAddress) == 0);\r
+\r
+\r
+ BytesCount = InternalSmBusBlock (\r
+\r
+                V_PCH_SMBUS_SMB_CMD_BLOCK,\r
+                SmBusAddress | B_PCH_SMBUS_RW_SEL_WRITE,\r
+                Buffer,\r
+                NULL,\r
+                Status\r
+                );\r
+\r
+  return BytesCount;\r
+}\r
+\r
+/**\r
+  Executes an SMBUS block process call command.\r
+\r
+  Executes an SMBUS block process call command on the SMBUS device specified by SmBusAddress.\r
+  The SMBUS slave address, SMBUS command, and SMBUS length fields of SmBusAddress are required.\r
+  Bytes are written to the SMBUS from WriteBuffer.  Bytes are then read from the SMBUS into ReadBuffer.\r
+  If Status is not NULL, then the status of the executed command is returned in Status.\r
+  It is the caller's responsibility to make sure ReadBuffer is large enough for the total number of bytes read.\r
+  SMBUS supports a maximum transfer size of 32 bytes, so Buffer does not need to be any larger than 32 bytes.\r
+  If Length in SmBusAddress is zero or greater than 32, then ASSERT().\r
+  If WriteBuffer is NULL, then ASSERT().\r
+  If ReadBuffer is NULL, then ASSERT().\r
+  If any reserved bits of SmBusAddress are set, then ASSERT().\r
+\r
+  @param  SmBusAddress    Address that encodes the SMBUS Slave Address,\r
+                          SMBUS Command, SMBUS Data Length, and PEC.\r
+  @param  WriteBuffer     Pointer to the buffer of bytes to write to the SMBUS.\r
+  @param  ReadBuffer      Pointer to the buffer of bytes to read from the SMBUS.\r
+  @param  Status          Return status for the executed command.\r
+                          This is an optional parameter and may be NULL.\r
+\r
+  @return The number of bytes written.\r
+\r
+**/\r
+UINTN\r
+EFIAPI\r
+SmBusBlockProcessCall (\r
+  IN  UINTN          SmBusAddress,\r
+  IN  VOID           *WriteBuffer,\r
+  OUT VOID           *ReadBuffer,\r
+  OUT RETURN_STATUS  *Status        OPTIONAL\r
+  )\r
+{\r
+  UINTN BytesCount = 0;\r
+\r
+  ASSERT (WriteBuffer != NULL);\r
+  ASSERT (ReadBuffer  != NULL);\r
+  ASSERT (SMBUS_LIB_LENGTH (SmBusAddress) >= 1);\r
+  ASSERT (SMBUS_LIB_LENGTH (SmBusAddress) <= 32);\r
+  ASSERT (SMBUS_LIB_RESERVED (SmBusAddress) == 0);\r
+\r
+  BytesCount = InternalSmBusBlock (\r
+                 V_PCH_SMBUS_SMB_CMD_BLOCK_PROCESS,\r
+                 SmBusAddress | B_PCH_SMBUS_RW_SEL_WRITE,\r
+                 WriteBuffer,\r
+                 ReadBuffer,\r
+                 Status\r
+                 );\r
+  return BytesCount;\r
+\r
+  }\r

diff --git a/Vlv2TbltDevicePkg/Library/SmbusLib/SmbusLib.inf b/Vlv2TbltDevicePkg/Library/SmbusLib/SmbusLib.inf
new file mode 100644 (file)
index 0000000..ac05aea
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Library/SmbusLib/SmbusLib.inf
@@ -0,0 +1,51 @@
+## @file\r
+# Component description file for Intel Ich9 Smbus Library.\r
+#\r
+# SMBUS Library that layers on top of the I/O Library to directly\r
+#  access a standard SMBUS host controller.\r
+# Copyright (c) 2010 - 2014, Intel Corporation. All rights reserved.<BR>\r
+#                                                                                  \r\r
+# This program and the accompanying materials are licensed and made available under\r\r
+# the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+# The full text of the license may be found at                                     \r\r
+# http://opensource.org/licenses/bsd-license.php.                                  \r\r
+#                                                                                  \r\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+#                                                                                  \r\r
+#\r
+#\r
+#\r
+##\r
+\r
+[Defines]\r
+  INF_VERSION                    = 0x00010005\r
+  BASE_NAME                      = SmbusLib\r
+  FILE_GUID                      = 0558CAEA-FEF3-4b6d-915E-8742EFE6DEE1\r
+  MODULE_TYPE                    = BASE\r
+  VERSION_STRING                 = 1.0\r
+  LIBRARY_CLASS                  = SmbusLib\r
+\r
+#\r
+# The following information is for reference only and not required by the build tools.\r
+#\r
+#  VALID_ARCHITECTURES           = IA32 X64 IPF EBC\r
+#\r
+\r
+[Sources]\r
+  SmbusLib.c\r
+\r
+[Packages]\r
+  Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec\r
+  MdePkg/MdePkg.dec\r
+  Vlv2TbltDevicePkg/PlatformPkg.dec\r
+\r
+[LibraryClasses]\r
+  PcdLib\r
+  DebugLib\r
+  PciLib\r
+  IoLib\r
+\r
+[Pcd.common]\r
+  gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress\r
+\r

diff --git a/Vlv2TbltDevicePkg/Library/StallSmmLib/StallSmm.c b/Vlv2TbltDevicePkg/Library/StallSmmLib/StallSmm.c
new file mode 100644 (file)
index 0000000..80fa817
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Library/StallSmmLib/StallSmm.c
@@ -0,0 +1,94 @@
+/*++\r
+\r
+Copyright (c)  1999  - 2014, Intel Corporation. All rights reserved\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+\r
+Module Name:\r
+\r
+  SmmIo.c\r
+\r
+Abstract:\r
+\r
+  SMM I/O access utility implementation file, for Ia32\r
+\r
+--*/\r
+\r
+//\r
+// Include files\r
+//\r
+#include "Library/StallSmmLib.h"\r
+#include "Pi/PiSmmCis.h"\r
+#include "PiDxe.h"\r
+#include <Library/IoLib.h>\r
+#include <Library/PcdLib.h>\r
+#include "PchAccess.h"\r
+\r
+/**\r
+  Delay for at least the request number of microseconds.\r
+  Timer used is ACPI time counter, which has 1us granularity.\r
+\r
+  @param Microseconds  Number of microseconds to delay.\r
+\r
+  @retval None\r
+\r
+**/\r
+VOID\r
+SmmStall (\r
+  IN  UINTN   Microseconds\r
+  )\r
+{\r
+  UINTN   Ticks;\r
+  UINTN   Counts;\r
+  UINTN   CurrentTick;\r
+  UINTN   OriginalTick;\r
+  UINTN   RemainingTick;\r
+  UINT16  AcpiBaseAddr;\r
+\r
+  if (Microseconds == 0) {\r
+    return;\r
+  }\r
+\r
+  AcpiBaseAddr = PchLpcPciCfg16 (R_PCH_LPC_ACPI_BASE) & B_PCH_LPC_ACPI_BASE_BAR;\r
+\r
+  OriginalTick = IoRead32 (AcpiBaseAddr + R_PCH_ACPI_PM1_TMR);\r
+  CurrentTick = OriginalTick;\r
+\r
+  //\r
+  // The timer frequency is 3.579545 MHz, so 1 ms corresponds 3.58 clocks\r
+  //\r
+  Ticks = Microseconds * 358 / 100 + OriginalTick + 1;\r
+\r
+  //\r
+  // The loops needed by timer overflow\r
+  //\r
+  Counts = Ticks / V_PCH_ACPI_PM1_TMR_MAX_VAL;\r
+\r
+  //\r
+  // Remaining clocks within one loop\r
+  //\r
+  RemainingTick = Ticks % V_PCH_ACPI_PM1_TMR_MAX_VAL;\r
+\r
+  //\r
+  // not intend to use TMROF_STS bit of register PM1_STS, because this adds extra\r
+  // one I/O operation, and maybe generate SMI\r
+  //\r
+  while ((Counts != 0) || (RemainingTick > CurrentTick)) {\r
+    CurrentTick = IoRead32 (AcpiBaseAddr + R_PCH_ACPI_PM1_TMR);\r
+    //\r
+    // Check if timer overflow\r
+    //\r
+    if (CurrentTick < OriginalTick) {\r
+      Counts--;\r
+    }\r
+    OriginalTick = CurrentTick;\r
+  }\r
+}\r

diff --git a/Vlv2TbltDevicePkg/Library/StallSmmLib/StallSmmLib.inf b/Vlv2TbltDevicePkg/Library/StallSmmLib/StallSmmLib.inf
new file mode 100644 (file)
index 0000000..a313481
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Library/StallSmmLib/StallSmmLib.inf
@@ -0,0 +1,56 @@
+#/*++\r
+#\r
+# Copyright (c)  1999  - 2014, Intel Corporation. All rights reserved\r
+#                                                                                  \r\r
+# This program and the accompanying materials are licensed and made available under\r\r
+# the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+# The full text of the license may be found at                                     \r\r
+# http://opensource.org/licenses/bsd-license.php.                                  \r\r
+#                                                                                  \r\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+#                                                                                  \r\r
+\r
+#\r
+#  Module Name:\r
+#\r
+#   SmmStallLib.inf\r
+#\r
+#  Abstract:\r
+#\r
+#    Component description file for SmmStall library\r
+#\r
+#--*/\r
+\r
+[Defines]\r
+  INF_VERSION                    = 0x00010005\r
+  BASE_NAME                      = StallSmmLib\r
+  FILE_GUID                      = A6A16CCB-91B0-42f4-B4F3-D16D7A8662E6\r
+  MODULE_TYPE                    = BASE\r
+  VERSION_STRING                 = 1.0\r
+  LIBRARY_CLASS                  = StallSmmLib\r
+\r
+\r
+#\r
+# The following information is for reference only and not required by the build tools.\r
+#\r
+#  VALID_ARCHITECTURES           = IA32 X64 IPF EBC\r
+#\r
+\r
+[Sources]\r
+ StallSmm.c\r
+\r
+\r
+[Packages]\r
+  MdePkg/MdePkg.dec\r
+  Vlv2TbltDevicePkg/PlatformPkg.dec\r
+  Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec\r
+\r
+[LibraryClasses]\r
+  PcdLib\r
+  PciLib\r
+  IoLib\r
+  BaseLib\r
+\r
+[Pcd.common]\r
+  gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress\r

diff --git a/Vlv2TbltDevicePkg/Logo/Logo.bmp b/Vlv2TbltDevicePkg/Logo/Logo.bmp
new file mode 100644 (file)
index 0000000..26ac1a8
Binary files /dev/null and b/Vlv2TbltDevicePkg/Logo/Logo.bmp differ

diff --git a/Vlv2TbltDevicePkg/Metronome/LegacyMetronome.c b/Vlv2TbltDevicePkg/Metronome/LegacyMetronome.c
new file mode 100644 (file)
index 0000000..5cae2f2
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Metronome/LegacyMetronome.c
@@ -0,0 +1,190 @@
+/** @file\r
+\r
+  Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+Module Name:\r
+\r
+\r
+  LegacyMetronome.c\r
+\r
+Abstract:\r
+\r
+  This contains the installation function for the driver.\r
+\r
+--*/\r
+\r
+#include "LegacyMetronome.h"\r
+\r
+//\r
+// Handle for the Metronome Architectural Protocol instance produced by this driver\r
+//\r
+EFI_HANDLE                  mMetronomeHandle = NULL;\r
+\r
+//\r
+// The Metronome Architectural Protocol instance produced by this driver\r
+//\r
+EFI_METRONOME_ARCH_PROTOCOL mMetronome = {\r
+  WaitForTick,\r
+  TICK_PERIOD\r
+};\r
+\r
+//\r
+// The CPU I/O Protocol used to access system hardware\r
+//\r
+EFI_CPU_IO_PROTOCOL         *mCpuIo = NULL;\r
+\r
+//\r
+// Worker Functions\r
+//\r
+\r
+/**\r
+  Write an 8 bit value to an I/O port and save it to the S3 script\r
+\r
+  @param Port  IO Port\r
+  @param Data  Data in IO Port\r
+\r
+  @retval None.\r
+\r
+**/\r
+VOID\r
+ScriptWriteIo8 (\r
+  UINT16  Port,\r
+  UINT8   Data\r
+  )\r
+{\r
+  mCpuIo->Io.Write (\r
+               mCpuIo,\r
+               EfiCpuIoWidthUint8,\r
+               Port,\r
+               1,\r
+               &Data\r
+               );\r
+\r
+}\r
+\r
+/**\r
+\r
+  Read the refresh bit from the REFRESH_PORT\r
+\r
+  @param None.\r
+\r
+  @retval Refresh bit.\r
+\r
+**/\r
+UINT8\r
+ReadRefresh (\r
+  VOID\r
+  )\r
+{\r
+  UINT8 Data;\r
+\r
+  mCpuIo->Io.Read (\r
+               mCpuIo,\r
+               EfiCpuIoWidthUint8,\r
+               REFRESH_PORT,\r
+               1,\r
+               &Data\r
+               );\r
+  return (UINT8) (Data & REFRESH_ON);\r
+}\r
+\r
+/**\r
+\r
+  Waits for the TickNumber of ticks from a known platform time source.\r
+\r
+  @param This                Pointer to the protocol instance.\r
+  @param TickNumber          Tick Number to be waited\r
+\r
+\r
+  @retval EFI_SUCCESS         If number of ticks occurred.\r
+  @retval EFI_NOT_FOUND       Could not locate CPU IO protocol\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+WaitForTick (\r
+  IN EFI_METRONOME_ARCH_PROTOCOL  *This,\r
+  IN UINT32                       TickNumber\r
+  )\r
+{\r
+  //\r
+  // Wait for TickNumber toggles of the Refresh bit\r
+  //\r
+  for (; TickNumber != 0x00; TickNumber--) {\r
+    while (ReadRefresh () == REFRESH_ON)\r
+      ;\r
+    while (ReadRefresh () == REFRESH_OFF)\r
+      ;\r
+  }\r
+\r
+  return EFI_SUCCESS;\r
+}\r
+\r
+//\r
+// Driver Entry Point\r
+//\r
+/**\r
+  Install the LegacyMetronome driver.  Loads a Metronome Arch Protocol based\r
+  on the Port 61 timer.\r
+\r
+  @param ImageHandle      Handle for the image of this driver\r
+  @param SystemTable      Pointer to the EFI System Table\r
+\r
+  @retval EFI_SUCCESS     Metronome Architectural Protocol Installed\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+InstallLegacyMetronome (\r
+  IN EFI_HANDLE        ImageHandle,\r
+  IN EFI_SYSTEM_TABLE  *SystemTable\r
+  )\r
+{\r
+  EFI_STATUS  Status;\r
+\r
+  //\r
+  // Make sure the Metronome Architectural Protocol is not already installed in the system\r
+  //\r
+  ASSERT_PROTOCOL_ALREADY_INSTALLED (NULL, &gEfiMetronomeArchProtocolGuid);\r
+\r
+  //\r
+  // Get the CPU I/O Protocol that this driver requires\r
+  // If the CPU I/O Protocol is not found, then ASSERT because the dependency expression\r
+  // should guarantee that it is present in the handle database.\r
+  //\r
+  Status = gBS->LocateProtocol (\r
+                  &gEfiCpuIoProtocolGuid,\r
+                  NULL,\r
+                  (void **)&mCpuIo\r
+                  );\r
+  ASSERT_EFI_ERROR (Status);\r
+\r
+  //\r
+  // Program port 61 timer 1 as refresh timer. We could use ACPI timer in the\r
+  // future.\r
+  //\r
+  ScriptWriteIo8 (TIMER1_CONTROL_PORT, LOAD_COUNTER1_LSB);\r
+  ScriptWriteIo8 (TIMER1_COUNT_PORT, COUNTER1_COUNT);\r
+\r
+  //\r
+  // Install on a new handle\r
+  //\r
+  Status = gBS->InstallMultipleProtocolInterfaces (\r
+                  &mMetronomeHandle,\r
+                  &gEfiMetronomeArchProtocolGuid,\r
+                  &mMetronome,\r
+                  NULL\r
+                  );\r
+  ASSERT_EFI_ERROR (Status);\r
+\r
+  return Status;\r
+}\r

diff --git a/Vlv2TbltDevicePkg/Metronome/LegacyMetronome.h b/Vlv2TbltDevicePkg/Metronome/LegacyMetronome.h
new file mode 100644 (file)
index 0000000..b9c32da
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Metronome/LegacyMetronome.h
@@ -0,0 +1,69 @@
+/*++\r
+\r
+  Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+Module Name:\r
+\r
+  LegacyMetronome.h\r
+\r
+Abstract:\r
+\r
+  Driver implementing the EFI 2.0 metronome protocol using the legacy PORT 61\r
+  timer.\r
+\r
+--*/\r
+\r
+#ifndef _LEGACY_METRONOME_H\r
+#define _LEGACY_METRONOME_H\r
+\r
+//\r
+// Statements that include other files\r
+//\r
+#include "Protocol/Metronome.h"\r
+#include "Protocol/CpuIo.h"\r
+#include "Library/DebugLib.h"\r
+#include "Library/UefiBootServicesTableLib.h"\r
+\r
+\r
+//\r
+// Private definitions\r
+//\r
+#define TICK_PERIOD         300\r
+#define REFRESH_PORT        0x61\r
+#define REFRESH_ON          0x10\r
+#define REFRESH_OFF         0x00\r
+#define TIMER1_CONTROL_PORT 0x43\r
+#define TIMER1_COUNT_PORT   0x41\r
+#define LOAD_COUNTER1_LSB   0x54\r
+#define COUNTER1_COUNT      0x12\r
+\r
+//\r
+// Function Prototypes\r
+//\r
+/**\r
+  Waits for the TickNumber of ticks from a known platform time source.\r
+\r
+  @param This                 Pointer to the protocol instance.\r
+  @param TickNumber           Tick Number to be waited\r
+\r
+  @retval EFI_SUCCESS         If number of ticks occurred.\r
+  @retval EFI_NOT_FOUND       Could not locate CPU IO protocol\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+WaitForTick (\r
+  IN EFI_METRONOME_ARCH_PROTOCOL  *This,\r
+  IN UINT32                       TickNumber\r
+  );\r
+\r
+#endif\r

diff --git a/Vlv2TbltDevicePkg/Metronome/Metronome.inf b/Vlv2TbltDevicePkg/Metronome/Metronome.inf
new file mode 100644 (file)
index 0000000..85237bd
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Metronome/Metronome.inf
@@ -0,0 +1,54 @@
+#\r
+#\r
+# Copyright (c)  1999  - 2014, Intel Corporation. All rights reserved\r
+#                                                                                  \r\r
+# This program and the accompanying materials are licensed and made available under\r\r
+# the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+# The full text of the license may be found at                                     \r\r
+# http://opensource.org/licenses/bsd-license.php.                                  \r\r
+#                                                                                  \r\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+#                                                                                  \r\r
+#\r
+\r
+#  Module Name:\r
+#\r
+#    LegacyMetronome.inf\r
+#\r
+#  Abstract:\r
+#\r
+#    Component description file for LegacyMetronome module\r
+#\r
+#--*/\r
+[defines]\r
+  INF_VERSION         = 0x00010005\r
+  BASE_NAME            = LegacyMetronome\r
+  FILE_GUID            = 07A9330A-F347-11d4-9A49-0090273FC14D\r
+  MODULE_TYPE          = DXE_DRIVER\r
+  VERSION_STRING       = 1.0\r
+  ENTRY_POINT         = InstallLegacyMetronome\r
+\r
+[sources.common]\r
+  LegacyMetronome.c\r
+  LegacyMetronome.h\r
+\r
+[Packages]\r
+  MdePkg/MdePkg.dec\r
+  IntelFrameworkPkg/IntelFrameworkPkg.dec\r
+\r
+[LibraryClasses]\r
+  UefiDriverEntryPoint\r
+  UefiBootServicesTableLib\r
+  DevicePathLib\r
+  UefiLib\r
+\r
+[Protocols]\r
+\r
+gEfiMetronomeArchProtocolGuid\r
+gEfiCpuIoProtocolGuid\r
+\r
+[Depex]\r
+gEfiCpuIoProtocolGuid  AND  gEfiBootScriptSaveProtocolGuid\r
+\r
+\r

diff --git a/Vlv2TbltDevicePkg/MonoStatusCode/EfiStatusCode.h b/Vlv2TbltDevicePkg/MonoStatusCode/EfiStatusCode.h
new file mode 100644 (file)
index 0000000..a18fef2
--- /dev/null
+++ b/Vlv2TbltDevicePkg/MonoStatusCode/EfiStatusCode.h
@@ -0,0 +1,183 @@
+/*++\r
+\r
+  Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+Module Name:\r
+\r
+  EfiStatusCode.h\r
+\r
+Abstract:\r
+\r
+  Status Code Definitions, according to Intel Platform Innovation Framework\r
+  for EFI Status Codes Specification\r
+  Revision 0.92\r
+\r
+  The file is divided into sections for ease of use.\r
+\r
+  Section:    Contents:\r
+    1           General Status Code Definitions\r
+    2           Class definitions\r
+    3           Computing Unit Subclasses, Progress and Error Codes\r
+    4           Peripheral Subclasses, Progress and Error Codes.\r
+    5           IO Bus Subclasses, Progress and Error Codes.\r
+    6           Software Subclasses, Progress and Error Codes.\r
+    7           Debug Codes\r
+\r
+--*/\r
+\r
+#ifndef _EFI_STATUS_CODE_H_\r
+#define _EFI_STATUS_CODE_H_\r
+\r
+\r
+\r
+#define EFI_SW_PEIM_EC_NO_RECOVERY_CAPSULE        (EFI_SUBCLASS_SPECIFIC | 0x00000000)\r
+#define EFI_SW_PEIM_EC_INVALID_CAPSULE_DESCRIPTOR (EFI_SUBCLASS_SPECIFIC | 0x00000001)\r
+\r
+\r
+\r
+#define EFI_SW_PEIM_PC_RECOVERY_BEGIN (EFI_SUBCLASS_SPECIFIC | 0x00000000)\r
+#define EFI_SW_PEIM_PC_CAPSULE_LOAD   (EFI_SUBCLASS_SPECIFIC | 0x00000001)\r
+#define EFI_SW_PEIM_PC_CAPSULE_START  (EFI_SUBCLASS_SPECIFIC | 0x00000002)\r
+#define EFI_SW_PEIM_PC_RECOVERY_USER  (EFI_SUBCLASS_SPECIFIC | 0x00000003)\r
+#define EFI_SW_PEIM_PC_RECOVERY_AUTO  (EFI_SUBCLASS_SPECIFIC | 0x00000004)\r
+\r
+\r
+\r
+#define EFI_CU_MEMORY_PC_SPD_READ         (EFI_SUBCLASS_SPECIFIC | 0x00000000)\r
+#define EFI_CU_MEMORY_PC_PRESENCE_DETECT  (EFI_SUBCLASS_SPECIFIC | 0x00000001)\r
+#define EFI_CU_MEMORY_PC_TIMING           (EFI_SUBCLASS_SPECIFIC | 0x00000002)\r
+#define EFI_CU_MEMORY_PC_CONFIGURING      (EFI_SUBCLASS_SPECIFIC | 0x00000003)\r
+#define EFI_CU_MEMORY_PC_OPTIMIZING       (EFI_SUBCLASS_SPECIFIC | 0x00000004)\r
+#define EFI_CU_MEMORY_PC_INIT             (EFI_SUBCLASS_SPECIFIC | 0x00000005)\r
+#define EFI_CU_MEMORY_PC_TEST             (EFI_SUBCLASS_SPECIFIC | 0x00000006)\r
+#define EFI_CU_MEMORY_PC_COMPLETE         (EFI_SUBCLASS_SPECIFIC | 0x00000007)\r
+#define EFI_CU_MEMORY_PC_INIT_BEGIN       (EFI_SUBCLASS_SPECIFIC | 0x00000008)\r
+\r
+\r
+#define EFI_DC_UNSPECIFIED  0x0\r
+\r
+//\r
+// CPU PEI\r
+//\r
+#define EFI_CU_HP_PC_PEI_INIT                     (EFI_SUBCLASS_SPECIFIC | 0x00000010)\r
+#define EFI_CU_HP_PC_PEI_STEP1                    (EFI_SUBCLASS_SPECIFIC | 0x00000011)\r
+#define EFI_CU_HP_PC_PEI_STEP2                    (EFI_SUBCLASS_SPECIFIC | 0x00000012)\r
+#define EFI_CU_HP_PC_PEI_STEP3                    (EFI_SUBCLASS_SPECIFIC | 0x00000013)\r
+#define EFI_CU_HP_PC_PEI_STEP4                    (EFI_SUBCLASS_SPECIFIC | 0x00000014)\r
+#define EFI_CU_HP_PC_PEI_STEP5                    (EFI_SUBCLASS_SPECIFIC | 0x00000015)\r
+#define EFI_CU_HP_PC_PEI_STEP6                    (EFI_SUBCLASS_SPECIFIC | 0x00000016)\r
+#define EFI_CU_HP_PC_PEI_STEP7                    (EFI_SUBCLASS_SPECIFIC | 0x00000017)\r
+#define EFI_CU_HP_PC_PEI_STEP8                    (EFI_SUBCLASS_SPECIFIC | 0x00000018)\r
+#define EFI_CU_HP_PC_PEI_STEP9                    (EFI_SUBCLASS_SPECIFIC | 0x00000019)\r
+#define EFI_CU_HP_PC_PEI_STEP10                   (EFI_SUBCLASS_SPECIFIC | 0x0000001A)\r
+#define EFI_CU_HP_PC_PEI_STEP11                   (EFI_SUBCLASS_SPECIFIC | 0x0000001B)\r
+#define EFI_CU_HP_PC_PEI_STEP12                   (EFI_SUBCLASS_SPECIFIC | 0x0000001C)\r
+#define EFI_CU_HP_PC_PEI_STEP13                   (EFI_SUBCLASS_SPECIFIC | 0x0000001D)\r
+#define EFI_CU_HP_PC_PEI_STEP14                   (EFI_SUBCLASS_SPECIFIC | 0x0000001E)\r
+#define EFI_CU_HP_PC_PEI_END                      (EFI_SUBCLASS_SPECIFIC | 0x0000001F)\r
+\r
+//\r
+// CPU DXE\r
+//\r
+#define EFI_CU_HP_PC_DXE_INIT                     (EFI_SUBCLASS_SPECIFIC | 0x00000020)\r
+#define EFI_CU_HP_PC_DXE_STEP1                    (EFI_SUBCLASS_SPECIFIC | 0x00000021)\r
+#define EFI_CU_HP_PC_DXE_STEP2                    (EFI_SUBCLASS_SPECIFIC | 0x00000022)\r
+#define EFI_CU_HP_PC_DXE_STEP3                    (EFI_SUBCLASS_SPECIFIC | 0x00000023)\r
+#define EFI_CU_HP_PC_DXE_STEP4                    (EFI_SUBCLASS_SPECIFIC | 0x00000024)\r
+#define EFI_CU_HP_PC_DXE_STEP5                    (EFI_SUBCLASS_SPECIFIC | 0x00000025)\r
+#define EFI_CU_HP_PC_DXE_STEP6                    (EFI_SUBCLASS_SPECIFIC | 0x00000026)\r
+#define EFI_CU_HP_PC_DXE_STEP7                    (EFI_SUBCLASS_SPECIFIC | 0x00000027)\r
+#define EFI_CU_HP_PC_DXE_STEP8                    (EFI_SUBCLASS_SPECIFIC | 0x00000028)\r
+#define EFI_CU_HP_PC_DXE_STEP9                    (EFI_SUBCLASS_SPECIFIC | 0x00000029)\r
+#define EFI_CU_HP_PC_DXE_STEP10                   (EFI_SUBCLASS_SPECIFIC | 0x0000002A)\r
+#define EFI_CU_HP_PC_DXE_STEP11                   (EFI_SUBCLASS_SPECIFIC | 0x0000002B)\r
+#define EFI_CU_HP_PC_DXE_STEP12                   (EFI_SUBCLASS_SPECIFIC | 0x0000002C)\r
+#define EFI_CU_HP_PC_DXE_STEP13                   (EFI_SUBCLASS_SPECIFIC | 0x0000002D)\r
+#define EFI_CU_HP_PC_DXE_STEP14                   (EFI_SUBCLASS_SPECIFIC | 0x0000002E)\r
+#define EFI_CU_HP_PC_DXE_END                      (EFI_SUBCLASS_SPECIFIC | 0x0000002F)\r
+\r
+//\r
+// CPU SMM PEI\r
+//\r
+#define EFI_CU_HP_PC_SMM_PEI_INIT                 (EFI_SUBCLASS_SPECIFIC | 0x00000030)\r
+#define EFI_CU_HP_PC_SMM_PEI_STEP1                (EFI_SUBCLASS_SPECIFIC | 0x00000031)\r
+#define EFI_CU_HP_PC_SMM_PEI_STEP2                (EFI_SUBCLASS_SPECIFIC | 0x00000032)\r
+#define EFI_CU_HP_PC_SMM_PEI_STEP3                (EFI_SUBCLASS_SPECIFIC | 0x00000033)\r
+#define EFI_CU_HP_PC_SMM_PEI_STEP4                (EFI_SUBCLASS_SPECIFIC | 0x00000034)\r
+#define EFI_CU_HP_PC_SMM_PEI_STEP5                (EFI_SUBCLASS_SPECIFIC | 0x00000035)\r
+#define EFI_CU_HP_PC_SMM_PEI_STEP6                (EFI_SUBCLASS_SPECIFIC | 0x00000036)\r
+#define EFI_CU_HP_PC_SMM_PEI_END                  (EFI_SUBCLASS_SPECIFIC | 0x0000003F)\r
+\r
+//\r
+// CPU SMM DXE\r
+//\r
+#define EFI_CU_HP_PC_SMM_DXE_INIT                 (EFI_SUBCLASS_SPECIFIC | 0x00000040)\r
+#define EFI_CU_HP_PC_SMM_DXE_STEP1                (EFI_SUBCLASS_SPECIFIC | 0x00000041)\r
+#define EFI_CU_HP_PC_SMM_DXE_STEP2                (EFI_SUBCLASS_SPECIFIC | 0x00000042)\r
+#define EFI_CU_HP_PC_SMM_DXE_STEP3                (EFI_SUBCLASS_SPECIFIC | 0x00000043)\r
+#define EFI_CU_HP_PC_SMM_DXE_STEP4                (EFI_SUBCLASS_SPECIFIC | 0x00000044)\r
+#define EFI_CU_HP_PC_SMM_DXE_STEP5                (EFI_SUBCLASS_SPECIFIC | 0x00000045)\r
+#define EFI_CU_HP_PC_SMM_DXE_STEP6                (EFI_SUBCLASS_SPECIFIC | 0x00000046)\r
+#define EFI_CU_HP_PC_SMM_DXE_END                  (EFI_SUBCLASS_SPECIFIC | 0x0000004F)\r
+\r
+//\r
+// PEI before memory initialization\r
+//\r
+#define EFI_CU_PLATFORM_PEI_INIT                     (EFI_OEM_SPECIFIC | 0x00000001)\r
+#define EFI_CU_PLATFORM_PEI_STEP1                    (EFI_OEM_SPECIFIC | 0x00000002)\r
+#define EFI_CU_PLATFORM_PEI_STEP2                    (EFI_OEM_SPECIFIC | 0x00000003)\r
+#define EFI_CU_PLATFORM_PEI_STEP3                    (EFI_OEM_SPECIFIC | 0x00000004)\r
+#define EFI_CU_PLATFORM_PEI_STEP4                    (EFI_OEM_SPECIFIC | 0x00000005)\r
+#define EFI_CU_SMBUS_PEI_INIT                        (EFI_OEM_SPECIFIC | 0x00000006)\r
+#define EFI_CU_SMBUS_PEI_EXEC_ENTRY                  (EFI_OEM_SPECIFIC | 0x00000007)\r
+#define EFI_CU_SMBUS_PEI_EXEC_EXIT                   (EFI_OEM_SPECIFIC | 0x00000008)\r
+#define EFI_CU_CLOCK_PEI_INIT_ENTRY                  (EFI_OEM_SPECIFIC | 0x00000009)\r
+#define EFI_CU_CLOCK_PEI_INIT_EXIT                   (EFI_OEM_SPECIFIC | 0x0000000A)\r
+#define EFI_CU_MEMORY_PC_PROG_MTRR                   (EFI_OEM_SPECIFIC | 0x0000000B)\r
+#define EFI_CU_MEMORY_PC_PROG_MTRR_END               (EFI_OEM_SPECIFIC | 0x0000000C)\r
+#define EFI_CU_PLATFORM_PEI_STEP12                   (EFI_OEM_SPECIFIC | 0x0000000D)\r
+#define EFI_CU_PLATFORM_PEI_STEP13                   (EFI_OEM_SPECIFIC | 0x0000000E)\r
+#define EFI_CU_PLATFORM_PEI_END                      (EFI_OEM_SPECIFIC | 0x0000000F)\r
+\r
+#define EFI_CU_PLATFORM_DXE_INIT                     (EFI_OEM_SPECIFIC | 0x00000011)\r
+#define EFI_CU_PLATFORM_DXE_STEP1                    (EFI_OEM_SPECIFIC | 0x00000012)\r
+#define EFI_CU_PLATFORM_DXE_STEP2                    (EFI_OEM_SPECIFIC | 0x00000013)\r
+#define EFI_CU_PLATFORM_DXE_STEP3                    (EFI_OEM_SPECIFIC | 0x00000014)\r
+#define EFI_CU_PLATFORM_DXE_STEP4                    (EFI_OEM_SPECIFIC | 0x00000015)\r
+#define EFI_CU_PLATFORM_DXE_INIT_DONE                (EFI_OEM_SPECIFIC | 0x00000016)\r
+\r
+#define EFI_CU_OVERCLOCK_PEI_INIT_ENTRY              (EFI_OEM_SPECIFIC | 0x00000017)\r
+#define EFI_CU_OVERCLOCK_PEI_INIT_EXIT               (EFI_OEM_SPECIFIC | 0x00000018)\r
+\r
+//\r
+// BDS\r
+//\r
+#define EFI_CU_BDS_INIT                              (EFI_OEM_SPECIFIC | 0x00000060)\r
+#define EFI_CU_BDS_STEP1                             (EFI_OEM_SPECIFIC | 0x00000061)\r
+#define EFI_CU_BDS_STEP2                             (EFI_OEM_SPECIFIC | 0x00000062)\r
+#define EFI_CU_BDS_STEP3                             (EFI_OEM_SPECIFIC | 0x00000063)\r
+#define EFI_CU_BDS_STEP4                             (EFI_OEM_SPECIFIC | 0x00000064)\r
+#define EFI_CU_BDS_STEP5                             (EFI_OEM_SPECIFIC | 0x00000065)\r
+#define EFI_CU_BDS_STEP6                             (EFI_OEM_SPECIFIC | 0x00000066)\r
+#define EFI_CU_BDS_STEP7                             (EFI_OEM_SPECIFIC | 0x00000067)\r
+#define EFI_CU_BDS_STEP8                             (EFI_OEM_SPECIFIC | 0x00000068)\r
+#define EFI_CU_BDS_STEP9                             (EFI_OEM_SPECIFIC | 0x00000069)\r
+#define EFI_CU_BDS_STEP10                            (EFI_OEM_SPECIFIC | 0x0000006A)\r
+#define EFI_CU_BDS_STEP11                            (EFI_OEM_SPECIFIC | 0x0000006B)\r
+#define EFI_CU_BDS_STEP12                            (EFI_OEM_SPECIFIC | 0x0000006C)\r
+#define EFI_CU_BDS_STEP13                            (EFI_OEM_SPECIFIC | 0x0000006D)\r
+#define EFI_CU_BDS_STEP14                            (EFI_OEM_SPECIFIC | 0x0000006E)\r
+#define EFI_CU_BDS_END                               (EFI_OEM_SPECIFIC | 0x0000006F)\r
+\r
+\r
+\r
+#endif\r

diff --git a/Vlv2TbltDevicePkg/MonoStatusCode/MonoStatusCode.c b/Vlv2TbltDevicePkg/MonoStatusCode/MonoStatusCode.c
new file mode 100644 (file)
index 0000000..80a05b9
--- /dev/null
+++ b/Vlv2TbltDevicePkg/MonoStatusCode/MonoStatusCode.c
@@ -0,0 +1,137 @@
+/** @file\r
+\r
+  Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+Module Name:\r
+\r
+\r
+  MonoStatusCode.c\r
+\r
+Abstract:\r
+\r
+  PEIM to provide the status code functionality, to aid in system debug.\r
+  It includes output to 0x80 port and/or to serial port.\r
+  This PEIM is monolithic. Different platform should provide different library.\r
+\r
+--*/\r
+\r
+#include "MonoStatusCode.h"\r
+#include "PlatformStatusCode.h"\r
+#define CMOS_EFI_DEBUG              0x14\r
+\r
+//\r
+// Module globals\r
+//\r
+EFI_PEI_PROGRESS_CODE_PPI     mStatusCodePpi = { PlatformReportStatusCode };\r
+\r
+EFI_PEI_PPI_DESCRIPTOR  mPpiListStatusCode = {\r
+  (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),\r
+  &gEfiPeiStatusCodePpiGuid,\r
+  &mStatusCodePpi\r
+};\r
+\r
+//\r
+// Function implemenations\r
+//\r
+\r
+/**\r
+  Translate from a DXE status code interface into a PEI-callable\r
+  interface, making the PEI the least common denominator..\r
+\r
+  Same as DXE ReportStatusCode RT service\r
+\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+TranslateDxeStatusCodeToPeiStatusCode (\r
+  IN EFI_STATUS_CODE_TYPE     CodeType,\r
+  IN EFI_STATUS_CODE_VALUE    Value,\r
+  IN UINT32                   Instance,\r
+  IN EFI_GUID                 * CallerId,\r
+  IN EFI_STATUS_CODE_DATA     * Data OPTIONAL\r
+  )\r
+{\r
+  return PlatformReportStatusCode (NULL, CodeType, Value, Instance, CallerId, Data);\r
+}\r
+\r
+/**\r
+  Build a hob describing the status code listener that has been installed.\r
+  This will be used by DXE code until a runtime status code listener is\r
+  installed.\r
+\r
+  @param PeiServices      General purpose services available to every PEIM.\r
+\r
+  @retval Status          EFI_SUCCESS if the interface could be successfully\r
+                          installed\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+InitializeDxeReportStatusCode (\r
+  IN const EFI_PEI_SERVICES       **PeiServices\r
+  )\r
+{\r
+  EFI_STATUS  Status = EFI_UNSUPPORTED;\r
+\r
+  VOID        *Instance;\r
+\r
+  VOID        *Result;\r
+\r
+  Instance = (VOID *) (UINTN) TranslateDxeStatusCodeToPeiStatusCode;\r
+\r
+  Result = BuildGuidDataHob (\r
+             &gEfiStatusCodeRuntimeProtocolGuid,\r
+             &Instance,\r
+             sizeof (VOID *)\r
+             );\r
+  if (Result != NULL) {\r
+    Status = EFI_SUCCESS;\r
+  }\r
+  return Status;\r
+}\r
+\r
+/**\r
+  Initialize the platform status codes and publish the platform status code\r
+  PPI.\r
+\r
+  @param  FfsHeader      FV this PEIM was loaded from.\r
+  @param  PeiServices    General purpose services available to every PEIM.\r
+\r
+  @retval Status         EFI_SUCCESS\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+InitializeMonoStatusCode (\r
+  IN EFI_FFS_FILE_HEADER       *FfsHeader,\r
+  IN CONST EFI_PEI_SERVICES          **PeiServices\r
+  )\r
+{\r
+  EFI_STATUS  Status;\r
+\r
+  //\r
+  // Initialize status code listeners.\r
+  //\r
+  PlatformInitializeStatusCode (FfsHeader, PeiServices);\r
+\r
+  //\r
+  // Publish the status code capability to other modules\r
+  //\r
+  Status = (*PeiServices)->InstallPpi (PeiServices, &mPpiListStatusCode);\r
+\r
+  ASSERT_EFI_ERROR (Status);\r
+\r
+  DEBUG ((DEBUG_ERROR, "\nMono Status Code PEIM Loaded\n"));\r
+\r
+  return ;\r
+}\r

diff --git a/Vlv2TbltDevicePkg/MonoStatusCode/MonoStatusCode.h b/Vlv2TbltDevicePkg/MonoStatusCode/MonoStatusCode.h
new file mode 100644 (file)
index 0000000..65fd3de
--- /dev/null
+++ b/Vlv2TbltDevicePkg/MonoStatusCode/MonoStatusCode.h
@@ -0,0 +1,133 @@
+/*++\r
+\r
+  Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+Module Name:\r
+\r
+  MonoStatusCode.h\r
+\r
+Abstract:\r
+\r
+  Monolithic single PEIM to provide the status code functionality.\r
+  The PEIM is a blend of libraries that correspond to the different status code\r
+  listeners that a platform installs.\r
+\r
+--*/\r
+\r
+#ifndef _MONO_STATUS_CODE_H_\r
+#define _MONO_STATUS_CODE_H_\r
+\r
+//\r
+// Statements that include other files.\r
+//\r
+#include "PiPei.h"\r
+\r
+#include "Pi/PiBootMode.h"\r
+\r
+#include "Ppi/StatusCode.h"\r
+#include "Ppi/MemoryDiscovered.h"\r
+#include "Ppi/FvLoadFile.h"\r
+\r
+#include "Library/HobLib.h"\r
+#include "Library/DebugLib.h"\r
+#include "Library/IoLib.h"\r
+#include "Library/SerialPortLib.h"\r
+#include "Protocol/StatusCode.h"\r
+\r
+\r
+#ifndef _STATUS_CODE_ENABLER_H_\r
+#define _STATUS_CODE_ENABLER_H_\r
+\r
+#ifdef EFI_DEBUG\r
+\r
+#define EFI_STATUS_CODE_ENABLER_HOB_GUID \\r
+  { \\r
+    0x5ffc6cf3, 0x71ad, 0x46f5, 0xbd, 0x8b, 0x7e, 0x8f, 0xfe, 0x19, 0x7, 0xd7 \\r
+  }\r
+\r
+extern EFI_GUID gEfiSerialStatusCodeEnablerHobGuid;\r
+\r
+typedef struct _EFI_STATUS_CODE_INFO {\r
+  BOOLEAN    StatusCodeDisable;\r
+} EFI_STATUS_CODE_INFO;\r
+\r
+#endif\r
+#endif\r
+\r
+\r
+\r
+//\r
+// Platform specific function Declarations.  These must be implemented in a\r
+// subdirectory named PlatformName in a file named PlatformStatusCode.c.\r
+//\r
+\r
+//\r
+// This is the platform function to initialize the listeners desired by the\r
+// platform.\r
+//\r
+VOID\r
+PlatformInitializeStatusCode (\r
+  IN EFI_FFS_FILE_HEADER       *FfsHeader,\r
+  IN CONST EFI_PEI_SERVICES          **PeiServices\r
+  );\r
+\r
+//\r
+// This is the platform function that calls all of the listeners desired by the\r
+// platform.\r
+//\r
+EFI_STATUS\r
+EFIAPI\r
+PlatformReportStatusCode (\r
+  IN CONST EFI_PEI_SERVICES       **PeiServices,\r
+  IN EFI_STATUS_CODE_TYPE         CodeType,\r
+  IN EFI_STATUS_CODE_VALUE        Value,\r
+  IN UINT32                       Instance,\r
+  IN CONST EFI_GUID               * CallerId,\r
+  IN CONST EFI_STATUS_CODE_DATA   * Data OPTIONAL\r
+  );\r
+\r
+//\r
+// Platform independent function Declarations\r
+//\r
+//\r
+// Initialize the status code listeners and publish the status code PPI.\r
+//\r
+VOID\r
+EFIAPI\r
+InitializeMonoStatusCode (\r
+  IN EFI_FFS_FILE_HEADER       *FfsHeader,\r
+  IN const EFI_PEI_SERVICES    **PeiServices\r
+  );\r
+\r
+//\r
+// Convert a DXE status code call into a PEI status code call.\r
+//\r
+EFI_STATUS\r
+EFIAPI\r
+TranslateDxeStatusCodeToPeiStatusCode (\r
+  IN EFI_STATUS_CODE_TYPE     CodeType,\r
+  IN EFI_STATUS_CODE_VALUE    Value,\r
+  IN UINT32                   Instance,\r
+  IN EFI_GUID                 * CallerId,\r
+  IN EFI_STATUS_CODE_DATA     * Data OPTIONAL\r
+  );\r
+\r
+//\r
+// Publish a HOB that contains the listener to be used by DXE.\r
+//\r
+EFI_STATUS\r
+EFIAPI\r
+InitializeDxeReportStatusCode (\r
+  IN const EFI_PEI_SERVICES       **PeiServices\r
+  );\r
+\r
+#endif\r

diff --git a/Vlv2TbltDevicePkg/MonoStatusCode/MonoStatusCode.inf b/Vlv2TbltDevicePkg/MonoStatusCode/MonoStatusCode.inf
new file mode 100644 (file)
index 0000000..d16c04d
--- /dev/null
+++ b/Vlv2TbltDevicePkg/MonoStatusCode/MonoStatusCode.inf
@@ -0,0 +1,78 @@
+#\r
+#\r
+# Copyright (c)  1999  - 2014, Intel Corporation. All rights reserved\r
+#                                                                                  \r\r
+# This program and the accompanying materials are licensed and made available under\r\r
+# the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+# The full text of the license may be found at                                     \r\r
+# http://opensource.org/licenses/bsd-license.php.                                  \r\r
+#                                                                                  \r\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+#                                                                                  \r\r
+#\r
+#  Module Name:\r
+#\r
+#    MonoStatusCode.inf\r
+#\r
+#  Abstract:\r
+#\r
+#    Component description file for Status Code PEI module\r
+#\r
+#--*/\r
+\r
+[defines]\r
+  INF_VERSION                    = 0x00010005\r
+  BASE_NAME                      = MonoStatusCode\r
+  FILE_GUID                      = 4BB346D2-8076-4671-8BC9-7B95CBB9A6DF\r
+  MODULE_TYPE                    = PEIM\r
+  VERSION_STRING                 = 1.0\r
+#  ENTRY_POINT                    = InstallMonoStatusCode\r
+  LIBRARY_CLASS                  = MonoStatusCodeLib\r
+\r
+[sources.common]\r
+  MonoStatusCode.c\r
+  MonoStatusCode.h\r
+  PlatformStatusCode.c\r
+  PlatformStatusCode.h\r
+  PeiPostCode.c\r
+\r
+[Packages]\r
+  MdePkg/MdePkg.dec\r
+  MdeModulePkg/MdeModulePkg.dec\r
+  IA32FamilyCpuPkg/IA32FamilyCpuPkg.dec\r
+  Vlv2TbltDevicePkg/PlatformPkg.dec\r
+  Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec\r
+  IntelFrameworkPkg/IntelFrameworkPkg.dec\r
+\r
+[LibraryClasses]\r
+  PeimEntryPoint\r
+  HobLib\r
+  DebugLib\r
+  SerialPortLib\r
+  ReportStatusCodeLib\r
+  PrintLib\r
+  BaseMemoryLib\r
+  PchPlatformLib\r
+\r
+[Ppis]\r
+  gEfiPeiMemoryDiscoveredPpiGuid\r
+  gEfiPeiStatusCodePpiGuid\r
+  gEfiPeiFvFileLoaderPpiGuid\r
+\r
+[Protocols]\r
+  gEfiStatusCodeRuntimeProtocolGuid\r
+\r
+[Pcd]\r
+  gEfiSerialPortTokenSpaceGuid.PcdStatusCodeUseRam\r
+\r
+[Guids]\r
+  gEfiPlatformCpuInfoGuid\r
+  gEfiHtBistHobGuid\r
+  gEfiStatusCodeDataTypeStringGuid              ## CONSUMES\r
+\r
+[Depex]\r
+  TRUE\r
+\r
+\r
+\r

diff --git a/Vlv2TbltDevicePkg/MonoStatusCode/PeiPostCode.c b/Vlv2TbltDevicePkg/MonoStatusCode/PeiPostCode.c
new file mode 100644 (file)
index 0000000..b730267
--- /dev/null
+++ b/Vlv2TbltDevicePkg/MonoStatusCode/PeiPostCode.c
@@ -0,0 +1,126 @@
+/** @file\r
+\r
+  Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+Module Name:\r
+\r
+\r
+  PeiPostCode.c\r
+\r
+Abstract:\r
+\r
+  Worker functions for PostCode\r
+\r
+--*/\r
+\r
+#include "EfiStatusCode.h"\r
+\r
+#pragma pack(1)\r
+typedef struct {\r
+  EFI_STATUS_CODE_VALUE   StatusValue;\r
+  UINT8                   Port80Value;\r
+} EFI_STATUS_CODE_TO_PORT_80;\r
+#pragma pack()\r
+\r
+//\r
+// see Edk\Foundation\Library\EfiCommonLib\PostCode.c for DXE/BDS POST codes.\r
+//\r
+EFI_STATUS_CODE_TO_PORT_80  mPeiPort80Table[] = {\r
+  //\r
+  // Platform init\r
+  //\r
+  {EFI_COMPUTING_UNIT_CHIPSET | EFI_CU_PLATFORM_PEI_INIT,          0x11},\r
+  {EFI_COMPUTING_UNIT_CHIPSET | EFI_CU_PLATFORM_PEI_STEP1,         0x12},\r
+  {EFI_COMPUTING_UNIT_CHIPSET | EFI_CU_PLATFORM_PEI_STEP2,         0x13},\r
+  {EFI_COMPUTING_UNIT_CHIPSET | EFI_CU_PLATFORM_PEI_STEP3,         0x14},\r
+  {EFI_COMPUTING_UNIT_CHIPSET | EFI_CU_PLATFORM_PEI_STEP4,         0x15},\r
+\r
+  //\r
+  // SMBUS\r
+  //\r
+  {EFI_COMPUTING_UNIT_CHIPSET | EFI_CU_SMBUS_PEI_INIT,             0x16},\r
+  {EFI_COMPUTING_UNIT_CHIPSET | EFI_CU_SMBUS_PEI_EXEC_ENTRY,       0x17},\r
+  {EFI_COMPUTING_UNIT_CHIPSET | EFI_CU_SMBUS_PEI_EXEC_EXIT,        0x18},\r
+\r
+  //\r
+  // Clock\r
+  //\r
+  {EFI_COMPUTING_UNIT_CHIPSET | EFI_CU_CLOCK_PEI_INIT_ENTRY,       0x19},\r
+  {EFI_COMPUTING_UNIT_CHIPSET | EFI_CU_CLOCK_PEI_INIT_EXIT,        0x1A},\r
+\r
+  //\r
+  // Over clocking support\r
+  //\r
+  {EFI_COMPUTING_UNIT_CHIPSET | EFI_CU_OVERCLOCK_PEI_INIT_ENTRY,   0x1B},\r
+  {EFI_COMPUTING_UNIT_CHIPSET | EFI_CU_OVERCLOCK_PEI_INIT_EXIT,    0x1C},\r
+\r
+  //\r
+  // MRC\r
+  //\r
+  {EFI_COMPUTING_UNIT_MEMORY | EFI_CU_MEMORY_PC_INIT_BEGIN,        0x21},\r
+  {EFI_COMPUTING_UNIT_MEMORY | EFI_CU_MEMORY_PC_SPD_READ,          0x23},\r
+  {EFI_COMPUTING_UNIT_MEMORY | EFI_CU_MEMORY_PC_PRESENCE_DETECT,   0x24},\r
+  {EFI_COMPUTING_UNIT_MEMORY | EFI_CU_MEMORY_PC_TIMING,            0x25},\r
+  {EFI_COMPUTING_UNIT_MEMORY | EFI_CU_MEMORY_PC_OPTIMIZING,        0x26},\r
+  {EFI_COMPUTING_UNIT_MEMORY | EFI_CU_MEMORY_PC_CONFIGURING,       0x27},\r
+  {EFI_COMPUTING_UNIT_MEMORY | EFI_CU_MEMORY_PC_TEST,              0x28},\r
+  {EFI_COMPUTING_UNIT_MEMORY | EFI_CU_MEMORY_PC_COMPLETE,          0x29},\r
+\r
+  //\r
+  // Platform Init after MRC\r
+  //\r
+  {EFI_COMPUTING_UNIT_MEMORY | EFI_CU_MEMORY_PC_PROG_MTRR,         0x2A},\r
+  {EFI_COMPUTING_UNIT_MEMORY | EFI_CU_MEMORY_PC_PROG_MTRR_END,     0x2B},\r
+\r
+  {EFI_SOFTWARE_PEI_MODULE | EFI_SW_PEIM_PC_RECOVERY_BEGIN,        0x31},\r
+  {EFI_SOFTWARE_PEI_MODULE | EFI_SW_PEIM_PC_RECOVERY_AUTO,         0x32},\r
+  {EFI_SOFTWARE_PEI_MODULE | EFI_SW_PEIM_PC_CAPSULE_LOAD,          0x33},\r
+  {EFI_SOFTWARE_PEI_MODULE | EFI_SW_PEIM_PC_CAPSULE_START,         0x34},\r
+  {EFI_SOFTWARE_PEI_MODULE | EFI_SW_PEIM_EC_NO_RECOVERY_CAPSULE,   0x35},\r
+\r
+  {EFI_COMPUTING_UNIT_HOST_PROCESSOR | EFI_CU_HP_PC_PEI_INIT,      0x41},\r
+  {EFI_COMPUTING_UNIT_HOST_PROCESSOR | EFI_CU_HP_PC_PEI_STEP1,     0x42},\r
+  {EFI_COMPUTING_UNIT_HOST_PROCESSOR | EFI_CU_HP_PC_PEI_END,       0x43},\r
+  {EFI_COMPUTING_UNIT_HOST_PROCESSOR | EFI_CU_HP_PC_SMM_PEI_INIT,  0x44},\r
+  {EFI_COMPUTING_UNIT_HOST_PROCESSOR | EFI_CU_HP_PC_SMM_PEI_STEP1, 0x45},\r
+  {EFI_COMPUTING_UNIT_HOST_PROCESSOR | EFI_CU_HP_PC_SMM_PEI_END,   0x46}\r
+};\r
+\r
+BOOLEAN\r
+PeiCodeTypeToPostCode (\r
+  IN  EFI_STATUS_CODE_TYPE    CodeType,\r
+  IN  EFI_STATUS_CODE_VALUE   Value,\r
+  OUT UINT8                   *PostCode\r
+  )\r
+{\r
+  UINTN             Index;\r
+\r
+  if (CodeType == EFI_PROGRESS_CODE) {\r
+    if ((Value == (EFI_SOFTWARE_PEI_CORE | EFI_SW_PC_INIT_BEGIN)) ||\r
+        (Value == (EFI_SOFTWARE_PEI_CORE | EFI_SW_PC_INIT_END)) ||\r
+        (Value == (EFI_SOFTWARE_DXE_CORE | EFI_SW_PC_INIT_BEGIN)) ||\r
+        (Value == (EFI_SOFTWARE_DXE_CORE | EFI_SW_PC_INIT_END))) {\r
+      return FALSE;\r
+    }\r
+  } else {\r
+    return FALSE;\r
+  }\r
+\r
+  for (Index = 0; Index < sizeof(mPeiPort80Table)/sizeof(EFI_STATUS_CODE_TO_PORT_80); Index++) {\r
+    if (mPeiPort80Table[Index].StatusValue == Value) {\r
+      *PostCode = mPeiPort80Table[Index].Port80Value;\r
+      return TRUE;\r
+    }\r
+  }\r
+\r
+  return FALSE;\r
+}\r

diff --git a/Vlv2TbltDevicePkg/MonoStatusCode/PlatformStatusCode.c b/Vlv2TbltDevicePkg/MonoStatusCode/PlatformStatusCode.c
new file mode 100644 (file)
index 0000000..3927cda
--- /dev/null
+++ b/Vlv2TbltDevicePkg/MonoStatusCode/PlatformStatusCode.c
@@ -0,0 +1,386 @@
+/** @file\r
+\r
+  Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+Module Name:\r
+\r
+\r
+  PlatformStatusCode.c\r
+\r
+Abstract:\r
+\r
+  Contains Platform specific implementations required to use status codes.\r
+\r
+--*/\r
+\r
+#include "PlatformStatusCode.h"\r
+#include <PchRegs.h>\r
+#include <PlatformBaseAddresses.h>\r
+#include <Library/PeiServicesLib.h>\r
+#include <Library/PcdLib.h>\r
+\r
+typedef struct {\r
+  EFI_STATUS_CODE_DATA  DataHeader;\r
+  EFI_HANDLE            Handle;\r
+} PEIM_FILE_HANDLE_EXTENDED_DATA;\r
+\r
+#define CONFIG_PORT0    0x4E\r
+#define PCI_IDX         0xCF8\r
+#define PCI_DAT         0xCFC\r
+\r
+#define PCI_LPC_BASE    (0x8000F800)\r
+#define PCI_LPC_REG(x)  (PCI_LPC_BASE + (x))\r
+\r
+//\r
+// Function implementations\r
+//\r
+BOOLEAN\r
+PeiCodeTypeToPostCode (\r
+  IN  EFI_STATUS_CODE_TYPE    CodeType,\r
+  IN  EFI_STATUS_CODE_VALUE   Value,\r
+  OUT UINT8                   *PostCode\r
+  );\r
+\r
+/**\r
+  Provide a port 80 status code\r
+\r
+  @param Same as ReportStatusCode PPI\r
+\r
+  @retval EFI_SUCCESS   Always returns success.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+Port80ReportStatusCode (\r
+  IN CONST EFI_PEI_SERVICES         **PeiServices,\r
+  IN EFI_STATUS_CODE_TYPE           CodeType,\r
+  IN EFI_STATUS_CODE_VALUE          Value,\r
+  IN UINT32                         Instance,\r
+  IN CONST EFI_GUID                 *CallerId,\r
+  IN CONST EFI_STATUS_CODE_DATA     *Data OPTIONAL\r
+  )\r
+\r
+{\r
+  EFI_STATUS               Status;\r
+  EFI_FV_FILE_INFO         FvFileInfo;\r
+  UINT16                   Port80Code = 0;\r
+\r
+  //\r
+  // Progress or error code, Output Port 80h card.\r
+  //\r
+  if (!PeiCodeTypeToPostCode (CodeType, Value, (UINT8 *)&Port80Code)) {\r
+    if ((Data != NULL) && (Value ==(EFI_SOFTWARE_PEI_CORE | EFI_SW_PC_INIT_BEGIN))){\r
+      Status = PeiServicesFfsGetFileInfo (\r
+                 ((PEIM_FILE_HANDLE_EXTENDED_DATA *) (Data + 1))->Handle,\r
+                 &FvFileInfo\r
+                 );\r
+      if (!EFI_ERROR (Status)) {\r
+        Port80Code = (FvFileInfo.FileName.Data4[6]<<8) + (FvFileInfo.FileName.Data4[7]);\r
+      }\r
+    }\r
+  }\r
+  if (Port80Code != 0){\r
+    IoWrite16 (0x80, (UINT16) Port80Code);\r
+    DEBUG ((EFI_D_ERROR, "POSTCODE=<%04x>\n", Port80Code));\r
+  }\r
+  return  EFI_SUCCESS;\r
+}\r
+\r
+/**\r
+  Provide a serial status code\r
+\r
+  @param Same as ReportStatusCode PPI\r
+\r
+  @retval EFI_SUCCESS   Always returns success.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+SerialReportStatusCode (\r
+  IN CONST EFI_PEI_SERVICES         **PeiServices,\r
+  IN EFI_STATUS_CODE_TYPE           CodeType,\r
+  IN EFI_STATUS_CODE_VALUE          Value,\r
+  IN UINT32                         Instance,\r
+  IN CONST EFI_GUID                 * CallerId,\r
+  IN CONST EFI_STATUS_CODE_DATA     * Data OPTIONAL\r
+  )\r
+{\r
+  CHAR8           *Filename;\r
+  CHAR8           *Description;\r
+  CHAR8           *Format;\r
+  CHAR8           Buffer[EFI_STATUS_CODE_DATA_MAX_SIZE];\r
+  UINT32          ErrorLevel;\r
+  UINT32          LineNumber;\r
+  UINTN           CharCount;\r
+  BASE_LIST       Marker;\r
+\r
+  Buffer[0] = '\0';\r
+\r
+  if (Data != NULL &&\r
+      ReportStatusCodeExtractAssertInfo (CodeType, Value, Data, &Filename, &Description, &LineNumber)) {\r
+    //\r
+    // Print ASSERT() information into output buffer.\r
+    //\r
+    CharCount = AsciiSPrint (\r
+                  Buffer,\r
+                  sizeof (Buffer),\r
+                  "\n\rPEI_ASSERT!: %a (%d): %a\n\r",\r
+                  Filename,\r
+                  LineNumber,\r
+                  Description\r
+                  );\r
+  } else if (Data != NULL &&\r
+             ReportStatusCodeExtractDebugInfo (Data, &ErrorLevel, &Marker, &Format)) {\r
+    //\r
+    // Print DEBUG() information into output buffer.\r
+    //\r
+    CharCount = AsciiBSPrint (\r
+                  Buffer,\r
+                  sizeof (Buffer),\r
+                  Format,\r
+                  Marker\r
+                  );\r
+  } else if ((CodeType & EFI_STATUS_CODE_TYPE_MASK) == EFI_ERROR_CODE) {\r
+    //\r
+    // Print ERROR information into output buffer.\r
+    //\r
+    CharCount = AsciiSPrint (\r
+                  Buffer,\r
+                  sizeof (Buffer),\r
+                  "ERROR: C%x:V%x I%x",\r
+                  CodeType,\r
+                  Value,\r
+                  Instance\r
+                  );\r
+\r
+    ASSERT(CharCount > 0);\r
+\r
+    if (CallerId != NULL) {\r
+      CharCount += AsciiSPrint (\r
+                     &Buffer[CharCount],\r
+                     (sizeof (Buffer) - (sizeof (Buffer[0]) * CharCount)),\r
+                     " %g",\r
+                     CallerId\r
+                     );\r
+    }\r
+\r
+    if (Data != NULL) {\r
+      CharCount += AsciiSPrint (\r
+                     &Buffer[CharCount],\r
+                     (sizeof (Buffer) - (sizeof (Buffer[0]) * CharCount)),\r
+                     " %x",\r
+                     Data\r
+                     );\r
+    }\r
+\r
+    CharCount += AsciiSPrint (\r
+                   &Buffer[CharCount],\r
+                   (sizeof (Buffer) - (sizeof (Buffer[0]) * CharCount)),\r
+                   "\n\r"\r
+                   );\r
+  } else if ((CodeType & EFI_STATUS_CODE_TYPE_MASK) == EFI_PROGRESS_CODE) {\r
+    //\r
+    // Print PROGRESS information into output buffer.\r
+    //\r
+    CharCount = AsciiSPrint (\r
+                  Buffer,\r
+                  sizeof (Buffer),\r
+                  "PROGRESS CODE: V%x I%x\n\r",\r
+                  Value,\r
+                  Instance\r
+                  );\r
+  } else if (Data != NULL &&\r
+             CompareGuid (&Data->Type, &gEfiStatusCodeDataTypeStringGuid) &&\r
+             ((EFI_STATUS_CODE_STRING_DATA *) Data)->StringType == EfiStringAscii) {\r
+    //\r
+    // EFI_STATUS_CODE_STRING_DATA\r
+    //\r
+    CharCount = AsciiSPrint (\r
+                  Buffer,\r
+                  sizeof (Buffer),\r
+                  "%a\n\r",\r
+                  ((EFI_STATUS_CODE_STRING_DATA *) Data)->String.Ascii\r
+                  );\r
+  } else {\r
+    //\r
+    // Code type is not defined.\r
+    //\r
+    CharCount = AsciiSPrint (\r
+                  Buffer,\r
+                  sizeof (Buffer),\r
+                  "Undefined: C%x:V%x I%x\n\r",\r
+                  CodeType,\r
+                  Value,\r
+                  Instance\r
+                  );\r
+  }\r
+\r
+  //\r
+  // Call SerialPort Lib function to do print.\r
+  //\r
+  SerialPortWrite ((UINT8 *) Buffer, CharCount);\r
+\r
+  return EFI_SUCCESS;\r
+}\r
+\r
+/**\r
+\r
+  Call all status code listeners in the MonoStatusCode.\r
+\r
+  @param PeiServices    The PEI core services table.\r
+  @param CodeType       Type of Status Code.\r
+  @param Value          Value to output for Status Code.\r
+  @param Instance       Instance Number of this status code.\r
+  @param CallerId       ID of the caller of this status code.\r
+  @param Data           Optional data associated with this status code.\r
+\r
+  @retval EFI_SUCCESS              If status code is successfully reported.\r
+  @retval EFI_NOT_AVAILABLE_YET    If StatusCodePpi has not been installed.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+PlatformReportStatusCode (\r
+  IN  CONST EFI_PEI_SERVICES        **PeiServices,\r
+  IN EFI_STATUS_CODE_TYPE           CodeType,\r
+  IN EFI_STATUS_CODE_VALUE          Value,\r
+  IN UINT32                         Instance,\r
+  IN CONST EFI_GUID                 * CallerId,\r
+  IN CONST EFI_STATUS_CODE_DATA     * Data OPTIONAL\r
+  )\r
+{\r
+  //\r
+  // If we are in debug mode, we will allow serial status codes\r
+  //\r
+  SerialReportStatusCode (PeiServices, CodeType, Value, Instance, CallerId, Data);\r
+\r
+  Port80ReportStatusCode (PeiServices, CodeType, Value, Instance, CallerId, Data);\r
+\r
+  return EFI_SUCCESS;\r
+}\r
+\r
+/**\r
+  Install the PEIM.  Initialize listeners, publish the PPI and HOB for PEI and\r
+  DXE use respectively.\r
+\r
+  @param FfsHeader      FV this PEIM was loaded from.\r
+  @param PeiServices    General purpose services available to every PEIM.\r
+\r
+  @retval EFI_SUCCESS   The function always returns success.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+InstallMonoStatusCode (\r
+  IN EFI_FFS_FILE_HEADER       *FfsHeader,\r
+  IN CONST EFI_PEI_SERVICES    **PeiServices\r
+  )\r
+{\r
+\r
+  //\r
+  // Initialize all listeners\r
+  //\r
+  InitializeMonoStatusCode (FfsHeader, PeiServices);\r
+\r
+  //\r
+  // Publish the listener in a HOB for DXE use.\r
+  //\r
+  InitializeDxeReportStatusCode (PeiServices);\r
+\r
+  return EFI_SUCCESS;\r
+}\r
+\r
+#define V_PCH_ILB_IRQE_UARTIRQEN_IRQ3             BIT3 // UART IRQ3 Enable\r
+#define V_PCH_ILB_IRQE_UARTIRQEN_IRQ4             BIT4 // UART IRQ4 Enable\r
+#define PCIEX_BASE_ADDRESS                        0xE0000000\r
+#define PciD31F0RegBase                           PCIEX_BASE_ADDRESS + (UINT32) (31 << 15)\r
+#define SB_RCBA                                   0xfed1c000\r
+\r
+extern PCH_STEPPING EFIAPI PchStepping (VOID);\r
+\r
+VOID\r
+RamDebugInit (\r
+  VOID\r
+  );\r
+\r
+/**\r
+  Enable legacy decoding on ICH6\r
+\r
+  @param none\r
+\r
+  @retval EFI_SUCCESS     Always returns success.\r
+\r
+**/\r
+EFI_STATUS\r
+EnableInternalUart(\r
+  VOID\r
+  )\r
+{\r
+\r
+  //\r
+  // Program and enable PMC Base.\r
+  //\r
+  IoWrite32 (PCI_IDX,  PCI_LPC_REG(R_PCH_LPC_PMC_BASE));\r
+  IoWrite32 (PCI_DAT,  (PMC_BASE_ADDRESS | B_PCH_LPC_PMC_BASE_EN));\r
+\r
+  //\r
+  // Enable COM1 for debug message output.\r
+  //\r
+  MmioAndThenOr32 (PMC_BASE_ADDRESS + R_PCH_PMC_GEN_PMCON_1, (UINT32) (~(B_PCH_PMC_GEN_PMCON_SUS_PWR_FLR + B_PCH_PMC_GEN_PMCON_PWROK_FLR)), BIT24);\r
+\r
+  //\r
+  // Silicon Steppings\r
+  //\r
+  if (PchStepping()>= PchB0)\r
+    MmioOr8 (ILB_BASE_ADDRESS + R_PCH_ILB_IRQE, (UINT8) V_PCH_ILB_IRQE_UARTIRQEN_IRQ4);\r
+  else\r
+    MmioOr8 (ILB_BASE_ADDRESS + R_PCH_ILB_IRQE, (UINT8) V_PCH_ILB_IRQE_UARTIRQEN_IRQ3);\r
+  MmioAnd32(IO_BASE_ADDRESS + 0x0520, (UINT32)~(0x00000187));\r
+  MmioOr32 (IO_BASE_ADDRESS + 0x0520, (UINT32)0x81); // UART3_RXD-L\r
+  MmioAnd32(IO_BASE_ADDRESS + 0x0530, (UINT32)~(0x00000007));\r
+  MmioOr32 (IO_BASE_ADDRESS + 0x0530, (UINT32)0x1); // UART3_RXD-L\r
+  MmioOr8 (PciD31F0RegBase + R_PCH_LPC_UART_CTRL, (UINT8) B_PCH_LPC_UART_CTRL_COM1_EN);\r
+\r
+  return  EFI_SUCCESS;\r
+}\r
+\r
+/**\r
+  INIT the SIO. Ported this code and I don't undertand the comments either.\r
+\r
+  @param FfsHeader    FV this PEIM was loaded from.\r
+  @param PeiServices  General purpose services available to every PEIM.\r
+\r
+  None\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+PlatformInitializeStatusCode (\r
+  IN EFI_FFS_FILE_HEADER       *FfsHeader,\r
+  IN CONST EFI_PEI_SERVICES    **PeiServices\r
+  )\r
+{\r
+\r
+  //\r
+  // Enable internal COM1 on South Cluster.\r
+  //\r
+       EnableInternalUart();\r
+\r
+\r
+  //\r
+  // Initialize additional debug status code listeners.\r
+  //\r
+   SerialPortInitialize();\r
+\r
+}\r
+//#endif //EFI_DEBUG\r
+\r

diff --git a/Vlv2TbltDevicePkg/MonoStatusCode/PlatformStatusCode.h b/Vlv2TbltDevicePkg/MonoStatusCode/PlatformStatusCode.h
new file mode 100644 (file)
index 0000000..51e13e0
--- /dev/null
+++ b/Vlv2TbltDevicePkg/MonoStatusCode/PlatformStatusCode.h
@@ -0,0 +1,207 @@
+/*++\r
+\r
+  Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+Module Name:\r
+\r
+  PlatformStatusCode.h\r
+\r
+Abstract:\r
+\r
+  Contains Platform specific implementations required to use status codes.\r
+\r
+--*/\r
+\r
+#ifndef _PLATFORM_STATUS_CODE_H_\r
+#define _PLATFORM_STATUS_CODE_H_\r
+\r
+\r
+#define CONFIG_PORT0    0x4E\r
+#define INDEX_PORT0     0x4E\r
+#define DATA_PORT0      0x4F\r
+#define PCI_IDX        0xCF8\r
+#define PCI_DAT        0xCFC\r
+\r
+#include "MonoStatusCode.h"\r
+\r
+/*++\r
+\r
+Copyright (c)  1999  - 2014, Intel Corporation. All rights reserved\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+This software and associated documentation (if any) is furnished\r
+under a license and may only be used or copied in accordance\r
+with the terms of the license. Except as permitted by such\r
+license, no part of this software or documentation may be\r
+reproduced, stored in a retrieval system, or transmitted in any\r
+form or by any means without the express written consent of\r
+Intel Corporation.\r
+\r
+\r
+Module Name:\r
+\r
+  Port80StatusCodeLib.h\r
+\r
+Abstract:\r
+\r
+  Lib to provide status code reporting via port 80.\r
+\r
+--*/\r
+\r
+#ifndef _PEI_PORT_80_STATUS_CODE_H_\r
+#define _PEI_PORT_80_STATUS_CODE_H_\r
+\r
+\r
+\r
+//\r
+// Status code reporting function\r
+//\r
+EFI_STATUS\r
+Port80ReportStatusCode (\r
+  IN CONST EFI_PEI_SERVICES         **PeiServices,\r
+  IN EFI_STATUS_CODE_TYPE           CodeType,\r
+  IN EFI_STATUS_CODE_VALUE          Value,\r
+  IN UINT32                         Instance,\r
+  IN CONST EFI_GUID                 * CallerId,\r
+  IN CONST EFI_STATUS_CODE_DATA     * Data OPTIONAL\r
+  );\r
+\r
+#endif\r
+\r
+/*++\r
+\r
+Copyright (c)  1999  - 2014, Intel Corporation. All rights reserved\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+This software and associated documentation (if any) is furnished\r
+under a license and may only be used or copied in accordance\r
+with the terms of the license. Except as permitted by such\r
+license, no part of this software or documentation may be\r
+reproduced, stored in a retrieval system, or transmitted in any\r
+form or by any means without the express written consent of\r
+Intel Corporation.\r
+\r
+\r
+Module Name:\r
+\r
+  SerialStatusCodeLib.h\r
+\r
+Abstract:\r
+\r
+  Lib to provide Serial I/O status code reporting.\r
+\r
+--*/\r
+\r
+#ifndef _PEI_SERIAL_STATUS_CODE_LIB_H_\r
+#define _PEI_SERIAL_STATUS_CODE_LIB_H_\r
+\r
+\r
+#include <Guid/StatusCodeDataTypeId.h>\r
+#include <Guid/StatusCodeDataTypeDebug.h>\r
+#include <Library/ReportStatusCodeLib.h>\r
+#include <Library/PrintLib.h>\r
+#include <Library/BaseMemoryLib.h>\r
+\r
+//\r
+// Initialization function\r
+//\r
+VOID\r
+SerialInitializeStatusCode (\r
+  VOID\r
+  );\r
+\r
+//\r
+// Status code reporting function\r
+//\r
+EFI_STATUS\r
+SerialReportStatusCode (\r
+  IN CONST EFI_PEI_SERVICES         **PeiServices,\r
+  IN EFI_STATUS_CODE_TYPE     CodeType,\r
+  IN EFI_STATUS_CODE_VALUE    Value,\r
+  IN UINT32                   Instance,\r
+  IN CONST EFI_GUID                 * CallerId,\r
+  IN CONST EFI_STATUS_CODE_DATA     * Data OPTIONAL\r
+  );\r
+\r
+#endif\r
+\r
+extern EFI_PEI_PROGRESS_CODE_PPI    mStatusCodePpi;\r
+extern EFI_PEI_PPI_DESCRIPTOR mPpiListStatusCode;\r
+#define EFI_SIGNATURE_16(A, B)        ((A) | (B << 8))\r
+#define EFI_SIGNATURE_32(A, B, C, D)  (EFI_SIGNATURE_16 (A, B) | (EFI_SIGNATURE_16 (C, D) << 16))\r
+#define STATUSCODE_PEIM_SIGNATURE EFI_SIGNATURE_32 ('p', 's', 't', 'c')\r
+\r
+typedef struct {\r
+  UINT32                    Signature;\r
+  EFI_FFS_FILE_HEADER       *FfsHeader;\r
+  EFI_PEI_NOTIFY_DESCRIPTOR StatusCodeNotify;\r
+} STATUSCODE_CALLBACK_STATE_INFORMATION;\r
+\r
+#pragma pack(1)\r
+typedef struct {\r
+  UINT16  Limit;\r
+  UINT32  Base;\r
+} GDT_DSCRIPTOR;\r
+#pragma pack()\r
+\r
+#define STATUSCODE_PEIM_FROM_THIS(a) \\r
+  BASE_CR ( \\r
+  a, \\r
+  STATUSCODE_CALLBACK_STATE_INFORMATION, \\r
+  StatusCodeNotify \\r
+  )\r
+\r
+VOID\r
+EFIAPI\r
+PlatformInitializeStatusCode (\r
+  IN EFI_FFS_FILE_HEADER       *FfsHeader,\r
+  IN CONST EFI_PEI_SERVICES    **PeiServices\r
+  );\r
+\r
+\r
+//\r
+// Function declarations\r
+//\r
+/**\r
+  Install Firmware Volume Hob's once there is main memory\r
+\r
+  @param PeiServices        General purpose services available to every PEIM.\r
+  @param NotifyDescriptor   Not Used\r
+  @param Ppi                Not Used\r
+\r
+  @retval Status            EFI_SUCCESS if the interface could be successfully\r
+                            installed\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+MemoryDiscoveredPpiNotifyCallback (\r
+  IN EFI_PEI_SERVICES           **PeiServices,\r
+  IN EFI_PEI_NOTIFY_DESCRIPTOR  *NotifyDescriptor,\r
+  IN VOID                       *Ppi\r
+  );\r
+\r
+#endif\r

diff --git a/Vlv2TbltDevicePkg/Override/IntelFrameworkModulePkg/Library/GenericBdsLib/BdsBoot.c b/Vlv2TbltDevicePkg/Override/IntelFrameworkModulePkg/Library/GenericBdsLib/BdsBoot.c
new file mode 100644 (file)
index 0000000..b19550f
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Override/IntelFrameworkModulePkg/Library/GenericBdsLib/BdsBoot.c
@@ -0,0 +1,4310 @@
+/** @file\r
+  BDS Lib functions which relate with create or process the boot option.\r
+\r
+Copyright (c) 2004 - 2013, Intel Corporation. All rights reserved.<BR>\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution.  The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#include "InternalBdsLib.h"\r
+#include "String.h"\r
+\r
+BOOLEAN mEnumBootDevice = FALSE;\r
+EFI_HII_HANDLE gBdsLibStringPackHandle = NULL;\r
+\r
+/**\r
+  The constructor function register UNI strings into imageHandle.\r
+  \r
+  It will ASSERT() if that operation fails and it will always return EFI_SUCCESS. \r
+\r
+  @param  ImageHandle   The firmware allocated handle for the EFI image.\r
+  @param  SystemTable   A pointer to the EFI System Table.\r
+  \r
+  @retval EFI_SUCCESS   The constructor successfully added string package.\r
+  @retval Other value   The constructor can't add string package.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+GenericBdsLibConstructor (\r
+  IN EFI_HANDLE        ImageHandle,\r
+  IN EFI_SYSTEM_TABLE  *SystemTable\r
+  )\r
+{\r
+\r
+  gBdsLibStringPackHandle = HiiAddPackages (\r
+                              &gBdsLibStringPackageGuid,\r
+                              ImageHandle,\r
+                              GenericBdsLibStrings,\r
+                              NULL\r
+                              );\r
+\r
+  ASSERT (gBdsLibStringPackHandle != NULL);\r
+\r
+  return EFI_SUCCESS;\r
+}\r
+\r
+/**\r
+  Deletete the Boot Option from EFI Variable. The Boot Order Arrray\r
+  is also updated.\r
+\r
+  @param OptionNumber    The number of Boot option want to be deleted.\r
+  @param BootOrder       The Boot Order array.\r
+  @param BootOrderSize   The size of the Boot Order Array.\r
+\r
+  @retval  EFI_SUCCESS           The Boot Option Variable was found and removed\r
+  @retval  EFI_UNSUPPORTED       The Boot Option Variable store was inaccessible\r
+  @retval  EFI_NOT_FOUND         The Boot Option Variable was not found\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+BdsDeleteBootOption (\r
+  IN UINTN                       OptionNumber,\r
+  IN OUT UINT16                  *BootOrder,\r
+  IN OUT UINTN                   *BootOrderSize\r
+  )\r
+{\r
+  CHAR16      BootOption[9];\r
+  UINTN       Index;\r
+  EFI_STATUS  Status;\r
+\r
+  UnicodeSPrint (BootOption, sizeof (BootOption), L"Boot%04x", OptionNumber);\r
+  Status = gRT->SetVariable (\r
+                  BootOption,\r
+                  &gEfiGlobalVariableGuid,\r
+                  0,\r
+                  0,\r
+                  NULL\r
+                  );\r
+\r
+  //\r
+  // adjust boot order array\r
+  //\r
+  for (Index = 0; Index < *BootOrderSize / sizeof (UINT16); Index++) {\r
+    if (BootOrder[Index] == OptionNumber) {\r
+      CopyMem (&BootOrder[Index], &BootOrder[Index+1], *BootOrderSize - (Index+1) * sizeof (UINT16));\r
+      *BootOrderSize -= sizeof (UINT16);\r
+      break;\r
+    }\r
+  }\r
+\r
+  return Status;\r
+}\r
+/**\r
+\r
+  Translate the first n characters of an Ascii string to\r
+  Unicode characters. The count n is indicated by parameter\r
+  Size. If Size is greater than the length of string, then\r
+  the entire string is translated.\r
+\r
+\r
+  @param AStr               Pointer to input Ascii string.\r
+  @param Size               The number of characters to translate.\r
+  @param UStr               Pointer to output Unicode string buffer.\r
+\r
+**/\r
+VOID\r
+AsciiToUnicodeSize (\r
+  IN UINT8              *AStr,\r
+  IN UINTN              Size,\r
+  OUT UINT16            *UStr\r
+  )\r
+{\r
+  UINTN Idx;\r
+\r
+  Idx = 0;\r
+  while (AStr[Idx] != 0) {\r
+    UStr[Idx] = (CHAR16) AStr[Idx];\r
+    if (Idx == Size) {\r
+      break;\r
+    }\r
+\r
+    Idx++;\r
+  }\r
+  UStr[Idx] = 0;\r
+}\r
+\r
+/**\r
+  Build Legacy Device Name String according.\r
+\r
+  @param CurBBSEntry     BBS Table.\r
+  @param Index           Index.\r
+  @param BufSize         The buffer size.\r
+  @param BootString      The output string.\r
+\r
+**/\r
+VOID\r
+BdsBuildLegacyDevNameString (\r
+  IN  BBS_TABLE                 *CurBBSEntry,\r
+  IN  UINTN                     Index,\r
+  IN  UINTN                     BufSize,\r
+  OUT CHAR16                    *BootString\r
+  )\r
+{\r
+  CHAR16  *Fmt;\r
+  CHAR16  *Type;\r
+  UINT8   *StringDesc;\r
+  CHAR16  Temp[80];\r
+\r
+  switch (Index) {\r
+  //\r
+  // Primary Master\r
+  //\r
+  case 1:\r
+    Fmt = L"Primary Master %s";\r
+    break;\r
+\r
+ //\r
+ // Primary Slave\r
+ //\r
+  case 2:\r
+    Fmt = L"Primary Slave %s";\r
+    break;\r
+\r
+  //\r
+  // Secondary Master\r
+  //\r
+  case 3:\r
+    Fmt = L"Secondary Master %s";\r
+    break;\r
+\r
+  //\r
+  // Secondary Slave\r
+  //\r
+  case 4:\r
+    Fmt = L"Secondary Slave %s";\r
+    break;\r
+\r
+  default:\r
+    Fmt = L"%s";\r
+    break;\r
+  }\r
+\r
+  switch (CurBBSEntry->DeviceType) {\r
+  case BBS_FLOPPY:\r
+    Type = L"Floppy";\r
+    break;\r
+\r
+  case BBS_HARDDISK:\r
+    Type = L"Harddisk";\r
+    break;\r
+\r
+  case BBS_CDROM:\r
+    Type = L"CDROM";\r
+    break;\r
+\r
+  case BBS_PCMCIA:\r
+    Type = L"PCMCIAe";\r
+    break;\r
+\r
+  case BBS_USB:\r
+    Type = L"USB";\r
+    break;\r
+\r
+  case BBS_EMBED_NETWORK:\r
+    Type = L"Network";\r
+    break;\r
+\r
+  case BBS_BEV_DEVICE:\r
+    Type = L"BEVe";\r
+    break;\r
+\r
+  case BBS_UNKNOWN:\r
+  default:\r
+    Type = L"Unknown";\r
+    break;\r
+  }\r
+  //\r
+  // If current BBS entry has its description then use it.\r
+  //\r
+  StringDesc = (UINT8 *) (UINTN) ((CurBBSEntry->DescStringSegment << 4) + CurBBSEntry->DescStringOffset);\r
+  if (NULL != StringDesc) {\r
+    //\r
+    // Only get fisrt 32 characters, this is suggested by BBS spec\r
+    //\r
+    AsciiToUnicodeSize (StringDesc, 32, Temp);\r
+    Fmt   = L"%s";\r
+    Type  = Temp;\r
+  }\r
+\r
+  //\r
+  // BbsTable 16 entries are for onboard IDE.\r
+  // Set description string for SATA harddisks, Harddisk 0 ~ Harddisk 11\r
+  //\r
+  if (Index >= 5 && Index <= 16 && (CurBBSEntry->DeviceType == BBS_HARDDISK || CurBBSEntry->DeviceType == BBS_CDROM)) {\r
+    Fmt = L"%s %d";\r
+    UnicodeSPrint (BootString, BufSize, Fmt, Type, Index - 5);\r
+  } else {\r
+    UnicodeSPrint (BootString, BufSize, Fmt, Type);\r
+  }\r
+}\r
+\r
+/**\r
+\r
+  Create a legacy boot option for the specified entry of\r
+  BBS table, save it as variable, and append it to the boot\r
+  order list.\r
+\r
+\r
+  @param CurrentBbsEntry    Pointer to current BBS table.\r
+  @param CurrentBbsDevPath  Pointer to the Device Path Protocol instance of BBS\r
+  @param Index              Index of the specified entry in BBS table.\r
+  @param BootOrderList      On input, the original boot order list.\r
+                            On output, the new boot order list attached with the\r
+                            created node.\r
+  @param BootOrderListSize  On input, the original size of boot order list.\r
+                            On output, the size of new boot order list.\r
+\r
+  @retval  EFI_SUCCESS             Boot Option successfully created.\r
+  @retval  EFI_OUT_OF_RESOURCES    Fail to allocate necessary memory.\r
+  @retval  Other                   Error occurs while setting variable.\r
+\r
+**/\r
+EFI_STATUS\r
+BdsCreateLegacyBootOption (\r
+  IN BBS_TABLE                        *CurrentBbsEntry,\r
+  IN EFI_DEVICE_PATH_PROTOCOL         *CurrentBbsDevPath,\r
+  IN UINTN                            Index,\r
+  IN OUT UINT16                       **BootOrderList,\r
+  IN OUT UINTN                        *BootOrderListSize\r
+  )\r
+{\r
+  EFI_STATUS           Status;\r
+  UINT16               CurrentBootOptionNo;\r
+  UINT16               BootString[10];\r
+  CHAR16               BootDesc[100];\r
+  CHAR8                HelpString[100];\r
+  UINT16               *NewBootOrderList;\r
+  UINTN                BufferSize;\r
+  UINTN                StringLen;\r
+  VOID                 *Buffer;\r
+  UINT8                *Ptr;\r
+  UINT16               CurrentBbsDevPathSize;\r
+  UINTN                BootOrderIndex;\r
+  UINTN                BootOrderLastIndex;\r
+  UINTN                ArrayIndex;\r
+  BOOLEAN              IndexNotFound;\r
+  BBS_BBS_DEVICE_PATH  *NewBbsDevPathNode;\r
+\r
+  if ((*BootOrderList) == NULL) {\r
+    CurrentBootOptionNo = 0;\r
+  } else {\r
+    for (ArrayIndex = 0; ArrayIndex < (UINTN) (*BootOrderListSize / sizeof (UINT16)); ArrayIndex++) {\r
+      IndexNotFound = TRUE;\r
+      for (BootOrderIndex = 0; BootOrderIndex < (UINTN) (*BootOrderListSize / sizeof (UINT16)); BootOrderIndex++) {\r
+        if ((*BootOrderList)[BootOrderIndex] == ArrayIndex) {\r
+          IndexNotFound = FALSE;\r
+          break;\r
+        }\r
+      }\r
+\r
+      if (!IndexNotFound) {\r
+        continue;\r
+      } else {\r
+        break;\r
+      }\r
+    }\r
+\r
+    CurrentBootOptionNo = (UINT16) ArrayIndex;\r
+  }\r
+\r
+  UnicodeSPrint (\r
+    BootString,\r
+    sizeof (BootString),\r
+    L"Boot%04x",\r
+    CurrentBootOptionNo\r
+    );\r
+\r
+  BdsBuildLegacyDevNameString (CurrentBbsEntry, Index, sizeof (BootDesc), BootDesc);\r
+\r
+  //\r
+  // Create new BBS device path node with description string\r
+  //\r
+  UnicodeStrToAsciiStr (BootDesc, HelpString);\r
+\r
+  StringLen = AsciiStrLen (HelpString);\r
+  NewBbsDevPathNode = AllocateZeroPool (sizeof (BBS_BBS_DEVICE_PATH) + StringLen);\r
+  if (NewBbsDevPathNode == NULL) {\r
+    return EFI_OUT_OF_RESOURCES;\r
+  }\r
+  CopyMem (NewBbsDevPathNode, CurrentBbsDevPath, sizeof (BBS_BBS_DEVICE_PATH));\r
+  CopyMem (NewBbsDevPathNode->String, HelpString, StringLen + 1);\r
+  SetDevicePathNodeLength (&(NewBbsDevPathNode->Header), sizeof (BBS_BBS_DEVICE_PATH) + StringLen);\r
+\r
+  //\r
+  // Create entire new CurrentBbsDevPath with end node\r
+  //\r
+  CurrentBbsDevPath = AppendDevicePathNode (\r
+                        NULL,\r
+                        (EFI_DEVICE_PATH_PROTOCOL *) NewBbsDevPathNode\r
+                        );\r
+   if (CurrentBbsDevPath == NULL) {\r
+    FreePool (NewBbsDevPathNode);\r
+    return EFI_OUT_OF_RESOURCES;\r
+  }\r
+\r
+  CurrentBbsDevPathSize = (UINT16) (GetDevicePathSize (CurrentBbsDevPath));\r
+\r
+  BufferSize = sizeof (UINT32) +\r
+    sizeof (UINT16) +\r
+    StrSize (BootDesc) +\r
+    CurrentBbsDevPathSize +\r
+    sizeof (BBS_TABLE) +\r
+    sizeof (UINT16);\r
+\r
+  Buffer = AllocateZeroPool (BufferSize);\r
+  if (Buffer == NULL) {\r
+    FreePool (NewBbsDevPathNode);\r
+    FreePool (CurrentBbsDevPath);\r
+    return EFI_OUT_OF_RESOURCES;\r
+  }\r
+\r
+  Ptr               = (UINT8 *) Buffer;\r
+\r
+  *((UINT32 *) Ptr) = LOAD_OPTION_ACTIVE;\r
+  Ptr += sizeof (UINT32);\r
+\r
+  *((UINT16 *) Ptr) = CurrentBbsDevPathSize;\r
+  Ptr += sizeof (UINT16);\r
+\r
+  CopyMem (\r
+    Ptr,\r
+    BootDesc,\r
+    StrSize (BootDesc)\r
+    );\r
+  Ptr += StrSize (BootDesc);\r
+\r
+  CopyMem (\r
+    Ptr,\r
+    CurrentBbsDevPath,\r
+    CurrentBbsDevPathSize\r
+    );\r
+  Ptr += CurrentBbsDevPathSize;\r
+\r
+  CopyMem (\r
+    Ptr,\r
+    CurrentBbsEntry,\r
+    sizeof (BBS_TABLE)\r
+    );\r
+\r
+  Ptr += sizeof (BBS_TABLE);\r
+  *((UINT16 *) Ptr) = (UINT16) Index;\r
+\r
+  Status = gRT->SetVariable (\r
+                  BootString,\r
+                  &gEfiGlobalVariableGuid,\r
+                  EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS | EFI_VARIABLE_NON_VOLATILE,\r
+                  BufferSize,\r
+                  Buffer\r
+                  );\r
+\r
+  FreePool (Buffer);\r
+  \r
+  Buffer = NULL;\r
+\r
+  NewBootOrderList = AllocateZeroPool (*BootOrderListSize + sizeof (UINT16));\r
+  if (NULL == NewBootOrderList) {\r
+    FreePool (NewBbsDevPathNode);\r
+    FreePool (CurrentBbsDevPath);\r
+    return EFI_OUT_OF_RESOURCES;\r
+  }\r
+\r
+  if (*BootOrderList != NULL) {\r
+    CopyMem (NewBootOrderList, *BootOrderList, *BootOrderListSize);\r
+    FreePool (*BootOrderList);\r
+  }\r
+\r
+  BootOrderLastIndex                    = (UINTN) (*BootOrderListSize / sizeof (UINT16));\r
+  NewBootOrderList[BootOrderLastIndex]  = CurrentBootOptionNo;\r
+  *BootOrderListSize += sizeof (UINT16);\r
+  *BootOrderList = NewBootOrderList;\r
+\r
+  FreePool (NewBbsDevPathNode);\r
+  FreePool (CurrentBbsDevPath);\r
+  return Status;\r
+}\r
+\r
+/**\r
+  Check if the boot option is a legacy one.\r
+\r
+  @param BootOptionVar   The boot option data payload.\r
+  @param BbsEntry        The BBS Table.\r
+  @param BbsIndex        The table index.\r
+\r
+  @retval TRUE           It is a legacy boot option.\r
+  @retval FALSE          It is not a legacy boot option.\r
+\r
+**/\r
+BOOLEAN\r
+BdsIsLegacyBootOption (\r
+  IN UINT8                 *BootOptionVar,\r
+  OUT BBS_TABLE            **BbsEntry,\r
+  OUT UINT16               *BbsIndex\r
+  )\r
+{\r
+  UINT8                     *Ptr;\r
+  EFI_DEVICE_PATH_PROTOCOL  *DevicePath;\r
+  BOOLEAN                   Ret;\r
+  UINT16                    DevPathLen;\r
+\r
+  Ptr = BootOptionVar;\r
+  Ptr += sizeof (UINT32);\r
+  DevPathLen = *(UINT16 *) Ptr;\r
+  Ptr += sizeof (UINT16);\r
+  Ptr += StrSize ((UINT16 *) Ptr);\r
+  DevicePath = (EFI_DEVICE_PATH_PROTOCOL *) Ptr;\r
+  if ((BBS_DEVICE_PATH == DevicePath->Type) && (BBS_BBS_DP == DevicePath->SubType)) {\r
+    Ptr += DevPathLen;\r
+    *BbsEntry = (BBS_TABLE *) Ptr;\r
+    Ptr += sizeof (BBS_TABLE);\r
+    *BbsIndex = *(UINT16 *) Ptr;\r
+    Ret       = TRUE;\r
+  } else {\r
+    *BbsEntry = NULL;\r
+    Ret       = FALSE;\r
+  }\r
+\r
+  return Ret;\r
+}\r
+\r
+/**\r
+  Delete all the invalid legacy boot options.\r
+\r
+  @retval EFI_SUCCESS             All invalide legacy boot options are deleted.\r
+  @retval EFI_OUT_OF_RESOURCES    Fail to allocate necessary memory.\r
+  @retval EFI_NOT_FOUND           Fail to retrive variable of boot order.\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+BdsDeleteAllInvalidLegacyBootOptions (\r
+  VOID\r
+  )\r
+{\r
+  UINT16                    *BootOrder;\r
+  UINT8                     *BootOptionVar;\r
+  UINTN                     BootOrderSize;\r
+  UINTN                     BootOptionSize;\r
+  EFI_STATUS                Status;\r
+  UINT16                    HddCount;\r
+  UINT16                    BbsCount;\r
+  HDD_INFO                  *LocalHddInfo;\r
+  BBS_TABLE                 *LocalBbsTable;\r
+  BBS_TABLE                 *BbsEntry;\r
+  UINT16                    BbsIndex;\r
+  EFI_LEGACY_BIOS_PROTOCOL  *LegacyBios;\r
+  UINTN                     Index;\r
+  UINT16                    BootOption[10];\r
+  UINT16                    BootDesc[100];\r
+  BOOLEAN                   DescStringMatch;\r
+\r
+  Status        = EFI_SUCCESS;\r
+  BootOrder     = NULL;\r
+  BootOrderSize = 0;\r
+  HddCount      = 0;\r
+  BbsCount      = 0;\r
+  LocalHddInfo  = NULL;\r
+  LocalBbsTable = NULL;\r
+  BbsEntry      = NULL;\r
+\r
+  Status        = gBS->LocateProtocol (&gEfiLegacyBiosProtocolGuid, NULL, (VOID **) &LegacyBios);\r
+  if (EFI_ERROR (Status)) {\r
+    return Status;\r
+  }\r
+\r
+  LegacyBios->GetBbsInfo (\r
+                LegacyBios,\r
+                &HddCount,\r
+                &LocalHddInfo,\r
+                &BbsCount,\r
+                &LocalBbsTable\r
+                );\r
+\r
+  BootOrder = BdsLibGetVariableAndSize (\r
+                L"BootOrder",\r
+                &gEfiGlobalVariableGuid,\r
+                &BootOrderSize\r
+                );\r
+  if (BootOrder == NULL) {\r
+    BootOrderSize = 0;\r
+  }\r
+\r
+  Index = 0;\r
+  while (Index < BootOrderSize / sizeof (UINT16)) {\r
+    UnicodeSPrint (BootOption, sizeof (BootOption), L"Boot%04x", BootOrder[Index]);\r
+    BootOptionVar = BdsLibGetVariableAndSize (\r
+                      BootOption,\r
+                      &gEfiGlobalVariableGuid,\r
+                      &BootOptionSize\r
+                      );\r
+    if (NULL == BootOptionVar) {\r
+      BootOptionSize = 0;\r
+      Status = gRT->GetVariable (\r
+                      BootOption,\r
+                      &gEfiGlobalVariableGuid,\r
+                      NULL,\r
+                      &BootOptionSize,\r
+                      BootOptionVar\r
+                      );\r
+      if (Status == EFI_NOT_FOUND) {\r
+        //\r
+        // Update BootOrder\r
+        //\r
+        BdsDeleteBootOption (\r
+          BootOrder[Index],\r
+          BootOrder,\r
+          &BootOrderSize\r
+          );\r
+        continue;\r
+      } else {\r
+        FreePool (BootOrder);\r
+        return EFI_OUT_OF_RESOURCES;\r
+      }\r
+    }\r
+  \r
+    //\r
+    // Skip Non-Legacy boot option\r
+    // \r
+    if (!BdsIsLegacyBootOption (BootOptionVar, &BbsEntry, &BbsIndex)) {\r
+      if (BootOptionVar!= NULL) {\r
+        FreePool (BootOptionVar);\r
+      }\r
+      Index++;\r
+      continue;\r
+    }\r
+\r
+    if (BbsIndex < BbsCount) {\r
+      //\r
+      // Check if BBS Description String is changed\r
+      //\r
+      DescStringMatch = FALSE;\r
+      BdsBuildLegacyDevNameString (\r
+        &LocalBbsTable[BbsIndex],\r
+        BbsIndex,\r
+        sizeof (BootDesc),\r
+        BootDesc\r
+        );\r
+\r
+      if (StrCmp (BootDesc, (UINT16*)(BootOptionVar + sizeof (UINT32) + sizeof (UINT16))) == 0) {\r
+        DescStringMatch = TRUE;\r
+      }\r
+\r
+      if (!((LocalBbsTable[BbsIndex].BootPriority == BBS_IGNORE_ENTRY) ||\r
+            (LocalBbsTable[BbsIndex].BootPriority == BBS_DO_NOT_BOOT_FROM)) &&\r
+          (LocalBbsTable[BbsIndex].DeviceType == BbsEntry->DeviceType) &&\r
+          DescStringMatch) {\r
+        Index++;\r
+        continue;\r
+      }\r
+    }\r
+\r
+    if (BootOptionVar != NULL) {\r
+      FreePool (BootOptionVar);\r
+    }\r
+    //\r
+    // should delete\r
+    //\r
+    BdsDeleteBootOption (\r
+      BootOrder[Index],\r
+      BootOrder,\r
+      &BootOrderSize\r
+      );\r
+  }\r
+\r
+  //\r
+  // Adjust the number of boot options.\r
+  //\r
+  Status = gRT->SetVariable (\r
+                  L"BootOrder",\r
+                  &gEfiGlobalVariableGuid,\r
+                  EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS | EFI_VARIABLE_NON_VOLATILE,\r
+                  BootOrderSize,\r
+                  BootOrder\r
+                  );\r
+  if (BootOrder != NULL) {\r
+    FreePool (BootOrder);\r
+  }\r
+\r
+  return Status;\r
+}\r
+\r
+/**\r
+  Find all legacy boot option by device type.\r
+\r
+  @param BootOrder       The boot order array.\r
+  @param BootOptionNum   The number of boot option.\r
+  @param DevType         Device type.\r
+  @param DevName         Device name.\r
+  @param Attribute       The boot option attribute.\r
+  @param BbsIndex        The BBS table index.\r
+  @param OptionNumber    The boot option index.\r
+\r
+  @retval TRUE           The Legacy boot option is found.\r
+  @retval FALSE          The legacy boot option is not found.\r
+\r
+**/\r
+BOOLEAN\r
+BdsFindLegacyBootOptionByDevTypeAndName (\r
+  IN UINT16                 *BootOrder,\r
+  IN UINTN                  BootOptionNum,\r
+  IN UINT16                 DevType,\r
+  IN CHAR16                 *DevName,\r
+  OUT UINT32                *Attribute,\r
+  OUT UINT16                *BbsIndex,\r
+  OUT UINT16                *OptionNumber\r
+  )\r
+{\r
+  UINTN     Index;\r
+  CHAR16    BootOption[9];\r
+  UINTN     BootOptionSize;\r
+  UINT8     *BootOptionVar;\r
+  BBS_TABLE *BbsEntry;\r
+  BOOLEAN   Found;\r
+\r
+  BbsEntry  = NULL;\r
+  Found     = FALSE;\r
+\r
+  if (NULL == BootOrder) {\r
+    return Found;\r
+  }\r
+\r
+  //\r
+  // Loop all boot option from variable\r
+  //\r
+  for (Index = 0; Index < BootOptionNum; Index++) {\r
+    UnicodeSPrint (BootOption, sizeof (BootOption), L"Boot%04x", (UINTN) BootOrder[Index]);\r
+    BootOptionVar = BdsLibGetVariableAndSize (\r
+                      BootOption,\r
+                      &gEfiGlobalVariableGuid,\r
+                      &BootOptionSize\r
+                      );\r
+    if (NULL == BootOptionVar) {\r
+      continue;\r
+    }\r
+\r
+    //\r
+    // Skip Non-legacy boot option\r
+    //\r
+    if (!BdsIsLegacyBootOption (BootOptionVar, &BbsEntry, BbsIndex)) {\r
+      FreePool (BootOptionVar);\r
+      continue;\r
+    }\r
+\r
+    if (\r
+        (BbsEntry->DeviceType != DevType) ||\r
+        (StrCmp (DevName, (CHAR16*)(BootOptionVar + sizeof (UINT32) + sizeof (UINT16))) != 0)\r
+       ) {\r
+      FreePool (BootOptionVar);\r
+      continue;\r
+    }\r
+\r
+    *Attribute    = *(UINT32 *) BootOptionVar;\r
+    *OptionNumber = BootOrder[Index];\r
+    Found         = TRUE;\r
+    FreePool (BootOptionVar);\r
+    break;\r
+  }\r
+\r
+  return Found;\r
+}\r
+\r
+/**\r
+  Create a legacy boot option.\r
+\r
+  @param BbsItem         The BBS Table entry.\r
+  @param Index           Index of the specified entry in BBS table.\r
+  @param BootOrderList   The boot order list.\r
+  @param BootOrderListSize The size of boot order list.\r
+\r
+  @retval EFI_OUT_OF_RESOURCE  No enough memory.\r
+  @retval EFI_SUCCESS          The function complete successfully.\r
+  @return Other value if the legacy boot option is not created.\r
+\r
+**/\r
+EFI_STATUS\r
+BdsCreateOneLegacyBootOption (\r
+  IN BBS_TABLE              *BbsItem,\r
+  IN UINTN                  Index,\r
+  IN OUT UINT16             **BootOrderList,\r
+  IN OUT UINTN              *BootOrderListSize\r
+  )\r
+{\r
+  BBS_BBS_DEVICE_PATH       BbsDevPathNode;\r
+  EFI_STATUS                Status;\r
+  EFI_DEVICE_PATH_PROTOCOL  *DevPath;\r
+\r
+  DevPath                       = NULL;\r
+\r
+  //\r
+  // Create device path node.\r
+  //\r
+  BbsDevPathNode.Header.Type    = BBS_DEVICE_PATH;\r
+  BbsDevPathNode.Header.SubType = BBS_BBS_DP;\r
+  SetDevicePathNodeLength (&BbsDevPathNode.Header, sizeof (BBS_BBS_DEVICE_PATH));\r
+  BbsDevPathNode.DeviceType = BbsItem->DeviceType;\r
+  CopyMem (&BbsDevPathNode.StatusFlag, &BbsItem->StatusFlags, sizeof (UINT16));\r
+\r
+  DevPath = AppendDevicePathNode (\r
+              NULL,\r
+              (EFI_DEVICE_PATH_PROTOCOL *) &BbsDevPathNode\r
+              );\r
+  if (NULL == DevPath) {\r
+    return EFI_OUT_OF_RESOURCES;\r
+  }\r
+\r
+  Status = BdsCreateLegacyBootOption (\r
+            BbsItem,\r
+            DevPath,\r
+            Index,\r
+            BootOrderList,\r
+            BootOrderListSize\r
+            );\r
+  BbsItem->BootPriority = 0x00;\r
+\r
+  FreePool (DevPath);\r
+\r
+  return Status;\r
+}\r
+\r
+/**\r
+  Add the legacy boot options from BBS table if they do not exist.\r
+\r
+  @retval EFI_SUCCESS          The boot options are added successfully \r
+                               or they are already in boot options.\r
+  @retval EFI_NOT_FOUND        No legacy boot options is found.\r
+  @retval EFI_OUT_OF_RESOURCE  No enough memory.\r
+  @return Other value          LegacyBoot options are not added.\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+BdsAddNonExistingLegacyBootOptions (\r
+  VOID\r
+  )\r
+{\r
+  UINT16                    *BootOrder;\r
+  UINTN                     BootOrderSize;\r
+  EFI_STATUS                Status;\r
+  CHAR16                    Desc[100];\r
+  UINT16                    HddCount;\r
+  UINT16                    BbsCount;\r
+  HDD_INFO                  *LocalHddInfo;\r
+  BBS_TABLE                 *LocalBbsTable;\r
+  UINT16                    BbsIndex;\r
+  EFI_LEGACY_BIOS_PROTOCOL  *LegacyBios;\r
+  UINT16                    Index;\r
+  UINT32                    Attribute;\r
+  UINT16                    OptionNumber;\r
+  BOOLEAN                   Exist;\r
+\r
+  HddCount      = 0;\r
+  BbsCount      = 0;\r
+  LocalHddInfo  = NULL;\r
+  LocalBbsTable = NULL;\r
+\r
+  Status        = gBS->LocateProtocol (&gEfiLegacyBiosProtocolGuid, NULL, (VOID **) &LegacyBios);\r
+  if (EFI_ERROR (Status)) {\r
+    return Status;\r
+  }\r
+\r
+  LegacyBios->GetBbsInfo (\r
+                LegacyBios,\r
+                &HddCount,\r
+                &LocalHddInfo,\r
+                &BbsCount,\r
+                &LocalBbsTable\r
+                );\r
+\r
+  BootOrder = BdsLibGetVariableAndSize (\r
+                L"BootOrder",\r
+                &gEfiGlobalVariableGuid,\r
+                &BootOrderSize\r
+                );\r
+  if (BootOrder == NULL) {\r
+    BootOrderSize = 0;\r
+  }\r
+\r
+  for (Index = 0; Index < BbsCount; Index++) {\r
+    if ((LocalBbsTable[Index].BootPriority == BBS_IGNORE_ENTRY) ||\r
+        (LocalBbsTable[Index].BootPriority == BBS_DO_NOT_BOOT_FROM)\r
+        ) {\r
+      continue;\r
+    }\r
+\r
+    BdsBuildLegacyDevNameString (&LocalBbsTable[Index], Index, sizeof (Desc), Desc);\r
+\r
+    Exist = BdsFindLegacyBootOptionByDevTypeAndName (\r
+              BootOrder,\r
+              BootOrderSize / sizeof (UINT16),\r
+              LocalBbsTable[Index].DeviceType,\r
+              Desc,\r
+              &Attribute,\r
+              &BbsIndex,\r
+              &OptionNumber\r
+              );\r
+    if (!Exist) {\r
+      //\r
+      // Not found such type of legacy device in boot options or we found but it's disabled\r
+      // so we have to create one and put it to the tail of boot order list\r
+      //\r
+      Status = BdsCreateOneLegacyBootOption (\r
+                &LocalBbsTable[Index],\r
+                Index,\r
+                &BootOrder,\r
+                &BootOrderSize\r
+                );\r
+      if (EFI_ERROR (Status)) {\r
+        break;\r
+      }\r
+      BbsIndex     = Index;\r
+      OptionNumber = BootOrder[BootOrderSize / sizeof (UINT16) - 1];\r
+    }\r
+\r
+    ASSERT (BbsIndex == Index);\r
+  }\r
+\r
+  Status = gRT->SetVariable (\r
+                  L"BootOrder",\r
+                  &gEfiGlobalVariableGuid,\r
+                  EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS | EFI_VARIABLE_NON_VOLATILE,\r
+                  BootOrderSize,\r
+                  BootOrder\r
+                  );\r
+  if (BootOrder != NULL) {\r
+    FreePool (BootOrder);\r
+  }\r
+\r
+  return Status;\r
+}\r
+\r
+/**\r
+  Fill the device order buffer.\r
+\r
+  @param BbsTable        The BBS table.\r
+  @param BbsType         The BBS Type.\r
+  @param BbsCount        The BBS Count.\r
+  @param Buf             device order buffer.\r
+\r
+  @return The device order buffer.\r
+\r
+**/\r
+UINT16 *\r
+BdsFillDevOrderBuf (\r
+  IN BBS_TABLE                    *BbsTable,\r
+  IN BBS_TYPE                     BbsType,\r
+  IN UINTN                        BbsCount,\r
+  OUT UINT16                      *Buf\r
+  )\r
+{\r
+  UINTN Index;\r
+\r
+  for (Index = 0; Index < BbsCount; Index++) {\r
+    if (BbsTable[Index].BootPriority == BBS_IGNORE_ENTRY) {\r
+      continue;\r
+    }\r
+\r
+    if (BbsTable[Index].DeviceType != BbsType) {\r
+      continue;\r
+    }\r
+\r
+    *Buf = (UINT16) (Index & 0xFF);\r
+    Buf++;\r
+  }\r
+\r
+  return Buf;\r
+}\r
+\r
+/**\r
+  Create the device order buffer.\r
+\r
+  @param BbsTable        The BBS table.\r
+  @param BbsCount        The BBS Count.\r
+\r
+  @retval EFI_SUCCES             The buffer is created and the EFI variable named \r
+                                 VAR_LEGACY_DEV_ORDER and gEfiLegacyDevOrderVariableGuid is\r
+                                 set correctly.\r
+  @retval EFI_OUT_OF_RESOURCES   Memmory or storage is not enough.\r
+  @retval EFI_DEVICE_ERROR       Fail to add the device order into EFI variable fail\r
+                                 because of hardware error.\r
+**/\r
+EFI_STATUS\r
+BdsCreateDevOrder (\r
+  IN BBS_TABLE                  *BbsTable,\r
+  IN UINT16                     BbsCount\r
+  )\r
+{\r
+  UINTN                       Index;\r
+  UINTN                       FDCount;\r
+  UINTN                       HDCount;\r
+  UINTN                       CDCount;\r
+  UINTN                       NETCount;\r
+  UINTN                       BEVCount;\r
+  UINTN                       TotalSize;\r
+  UINTN                       HeaderSize;\r
+  LEGACY_DEV_ORDER_ENTRY      *DevOrder;\r
+  LEGACY_DEV_ORDER_ENTRY      *DevOrderPtr;\r
+  EFI_STATUS                  Status;\r
+\r
+  FDCount     = 0;\r
+  HDCount     = 0;\r
+  CDCount     = 0;\r
+  NETCount    = 0;\r
+  BEVCount    = 0;\r
+  TotalSize   = 0;\r
+  HeaderSize  = sizeof (BBS_TYPE) + sizeof (UINT16);\r
+  DevOrder    = NULL;\r
+  Status      = EFI_SUCCESS;\r
+\r
+  //\r
+  // Count all boot devices\r
+  //\r
+  for (Index = 0; Index < BbsCount; Index++) {\r
+    if (BbsTable[Index].BootPriority == BBS_IGNORE_ENTRY) {\r
+      continue;\r
+    }\r
+\r
+    switch (BbsTable[Index].DeviceType) {\r
+    case BBS_FLOPPY:\r
+      FDCount++;\r
+      break;\r
+\r
+    case BBS_HARDDISK:\r
+      HDCount++;\r
+      break;\r
+\r
+    case BBS_CDROM:\r
+      CDCount++;\r
+      break;\r
+\r
+    case BBS_EMBED_NETWORK:\r
+      NETCount++;\r
+      break;\r
+\r
+    case BBS_BEV_DEVICE:\r
+      BEVCount++;\r
+      break;\r
+\r
+    default:\r
+      break;\r
+    }\r
+  }\r
+\r
+  TotalSize += (HeaderSize + sizeof (UINT16) * FDCount);\r
+  TotalSize += (HeaderSize + sizeof (UINT16) * HDCount);\r
+  TotalSize += (HeaderSize + sizeof (UINT16) * CDCount);\r
+  TotalSize += (HeaderSize + sizeof (UINT16) * NETCount);\r
+  TotalSize += (HeaderSize + sizeof (UINT16) * BEVCount);\r
+\r
+  //\r
+  // Create buffer to hold all boot device order\r
+  //\r
+  DevOrder = AllocateZeroPool (TotalSize);\r
+  if (NULL == DevOrder) {\r
+    return EFI_OUT_OF_RESOURCES;\r
+  }\r
+  DevOrderPtr          = DevOrder;\r
+\r
+  DevOrderPtr->BbsType = BBS_FLOPPY;\r
+  DevOrderPtr->Length  = (UINT16) (sizeof (DevOrderPtr->Length) + FDCount * sizeof (UINT16));\r
+  DevOrderPtr          = (LEGACY_DEV_ORDER_ENTRY *) BdsFillDevOrderBuf (BbsTable, BBS_FLOPPY, BbsCount, DevOrderPtr->Data);\r
+\r
+  DevOrderPtr->BbsType = BBS_HARDDISK;\r
+  DevOrderPtr->Length  = (UINT16) (sizeof (UINT16) + HDCount * sizeof (UINT16));\r
+  DevOrderPtr          = (LEGACY_DEV_ORDER_ENTRY *) BdsFillDevOrderBuf (BbsTable, BBS_HARDDISK, BbsCount, DevOrderPtr->Data);\r
+  \r
+  DevOrderPtr->BbsType = BBS_CDROM;\r
+  DevOrderPtr->Length  = (UINT16) (sizeof (UINT16) + CDCount * sizeof (UINT16));\r
+  DevOrderPtr          = (LEGACY_DEV_ORDER_ENTRY *) BdsFillDevOrderBuf (BbsTable, BBS_CDROM, BbsCount, DevOrderPtr->Data);\r
+  \r
+  DevOrderPtr->BbsType = BBS_EMBED_NETWORK;\r
+  DevOrderPtr->Length  = (UINT16) (sizeof (UINT16) + NETCount * sizeof (UINT16));\r
+  DevOrderPtr          = (LEGACY_DEV_ORDER_ENTRY *) BdsFillDevOrderBuf (BbsTable, BBS_EMBED_NETWORK, BbsCount, DevOrderPtr->Data);\r
+\r
+  DevOrderPtr->BbsType = BBS_BEV_DEVICE;\r
+  DevOrderPtr->Length  = (UINT16) (sizeof (UINT16) + BEVCount * sizeof (UINT16));\r
+  DevOrderPtr          = (LEGACY_DEV_ORDER_ENTRY *) BdsFillDevOrderBuf (BbsTable, BBS_BEV_DEVICE, BbsCount, DevOrderPtr->Data);\r
+\r
+  ASSERT (TotalSize == (UINTN) ((UINT8 *) DevOrderPtr - (UINT8 *) DevOrder));\r
+\r
+  //\r
+  // Save device order for legacy boot device to variable.\r
+  //\r
+  Status = gRT->SetVariable (\r
+                  VAR_LEGACY_DEV_ORDER,\r
+                  &gEfiLegacyDevOrderVariableGuid,\r
+                  EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS | EFI_VARIABLE_NON_VOLATILE,\r
+                  TotalSize,\r
+                  DevOrder\r
+                  );\r
+  FreePool (DevOrder);\r
+\r
+  return Status;\r
+}\r
+\r
+/**\r
+  Add the legacy boot devices from BBS table into \r
+  the legacy device boot order.\r
+\r
+  @retval EFI_SUCCESS           The boot devices are added successfully.\r
+  @retval EFI_NOT_FOUND         The legacy boot devices are not found.\r
+  @retval EFI_OUT_OF_RESOURCES  Memmory or storage is not enough.\r
+  @retval EFI_DEVICE_ERROR      Fail to add the legacy device boot order into EFI variable\r
+                                because of hardware error.\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+BdsUpdateLegacyDevOrder (\r
+  VOID\r
+  )\r
+{\r
+  LEGACY_DEV_ORDER_ENTRY      *DevOrder;\r
+  LEGACY_DEV_ORDER_ENTRY      *NewDevOrder;\r
+  LEGACY_DEV_ORDER_ENTRY      *Ptr;\r
+  LEGACY_DEV_ORDER_ENTRY      *NewPtr;\r
+  UINTN                       DevOrderSize;\r
+  EFI_LEGACY_BIOS_PROTOCOL    *LegacyBios;\r
+  EFI_STATUS                  Status;\r
+  UINT16                      HddCount;\r
+  UINT16                      BbsCount;\r
+  HDD_INFO                    *LocalHddInfo;\r
+  BBS_TABLE                   *LocalBbsTable;\r
+  UINTN                       Index;\r
+  UINTN                       Index2;\r
+  UINTN                       *Idx;\r
+  UINTN                       FDCount;\r
+  UINTN                       HDCount;\r
+  UINTN                       CDCount;\r
+  UINTN                       NETCount;\r
+  UINTN                       BEVCount;\r
+  UINTN                       TotalSize;\r
+  UINTN                       HeaderSize;\r
+  UINT16                      *NewFDPtr;\r
+  UINT16                      *NewHDPtr;\r
+  UINT16                      *NewCDPtr;\r
+  UINT16                      *NewNETPtr;\r
+  UINT16                      *NewBEVPtr;\r
+  UINT16                      *NewDevPtr;\r
+  UINTN                       FDIndex;\r
+  UINTN                       HDIndex;\r
+  UINTN                       CDIndex;\r
+  UINTN                       NETIndex;\r
+  UINTN                       BEVIndex;\r
+\r
+  Idx           = NULL;\r
+  FDCount       = 0;\r
+  HDCount       = 0;\r
+  CDCount       = 0;\r
+  NETCount      = 0;\r
+  BEVCount      = 0;\r
+  TotalSize     = 0;\r
+  HeaderSize    = sizeof (BBS_TYPE) + sizeof (UINT16);\r
+  FDIndex       = 0;\r
+  HDIndex       = 0;\r
+  CDIndex       = 0;\r
+  NETIndex      = 0;\r
+  BEVIndex      = 0;\r
+  NewDevPtr     = NULL;\r
+\r
+  Status        = gBS->LocateProtocol (&gEfiLegacyBiosProtocolGuid, NULL, (VOID **) &LegacyBios);\r
+  if (EFI_ERROR (Status)) {\r
+    return Status;\r
+  }\r
+\r
+  Status = LegacyBios->GetBbsInfo (\r
+                         LegacyBios,\r
+                         &HddCount,\r
+                         &LocalHddInfo,\r
+                         &BbsCount,\r
+                         &LocalBbsTable\r
+                         );\r
+  if (EFI_ERROR (Status)) {\r
+    return Status;\r
+  }\r
+\r
+  DevOrder = BdsLibGetVariableAndSize (\r
+               VAR_LEGACY_DEV_ORDER,\r
+               &gEfiLegacyDevOrderVariableGuid,\r
+               &DevOrderSize\r
+               );\r
+  if (NULL == DevOrder) {\r
+    return BdsCreateDevOrder (LocalBbsTable, BbsCount);\r
+  }\r
+  //\r
+  // First we figure out how many boot devices with same device type respectively\r
+  //\r
+  for (Index = 0; Index < BbsCount; Index++) {\r
+    if ((LocalBbsTable[Index].BootPriority == BBS_IGNORE_ENTRY) ||\r
+        (LocalBbsTable[Index].BootPriority == BBS_DO_NOT_BOOT_FROM)\r
+        ) {\r
+      continue;\r
+    }\r
+\r
+    switch (LocalBbsTable[Index].DeviceType) {\r
+    case BBS_FLOPPY:\r
+      FDCount++;\r
+      break;\r
+\r
+    case BBS_HARDDISK:\r
+      HDCount++;\r
+      break;\r
+\r
+    case BBS_CDROM:\r
+      CDCount++;\r
+      break;\r
+\r
+    case BBS_EMBED_NETWORK:\r
+      NETCount++;\r
+      break;\r
+\r
+    case BBS_BEV_DEVICE:\r
+      BEVCount++;\r
+      break;\r
+\r
+    default:\r
+      break;\r
+    }\r
+  }\r
+\r
+  TotalSize += (HeaderSize + FDCount * sizeof (UINT16));\r
+  TotalSize += (HeaderSize + HDCount * sizeof (UINT16));\r
+  TotalSize += (HeaderSize + CDCount * sizeof (UINT16));\r
+  TotalSize += (HeaderSize + NETCount * sizeof (UINT16));\r
+  TotalSize += (HeaderSize + BEVCount * sizeof (UINT16));\r
+\r
+  NewDevOrder = AllocateZeroPool (TotalSize);\r
+  if (NULL == NewDevOrder) {\r
+    return EFI_OUT_OF_RESOURCES;\r
+  }\r
+\r
+\r
+\r
+  //\r
+  // copy FD\r
+  //\r
+  Ptr             = DevOrder;\r
+  NewPtr          = NewDevOrder;\r
+  NewPtr->BbsType = Ptr->BbsType;\r
+  NewPtr->Length  = (UINT16) (sizeof (UINT16) + FDCount * sizeof (UINT16));\r
+  for (Index = 0; Index < Ptr->Length / sizeof (UINT16) - 1; Index++) {\r
+    if (LocalBbsTable[Ptr->Data[Index] & 0xFF].BootPriority == BBS_IGNORE_ENTRY ||\r
+        LocalBbsTable[Ptr->Data[Index] & 0xFF].BootPriority == BBS_DO_NOT_BOOT_FROM ||\r
+        LocalBbsTable[Ptr->Data[Index] & 0xFF].DeviceType != BBS_FLOPPY\r
+        ) {\r
+      continue;\r
+    }\r
+\r
+    NewPtr->Data[FDIndex] = Ptr->Data[Index];\r
+    FDIndex++;\r
+  }\r
+  NewFDPtr = NewPtr->Data;\r
+\r
+  //\r
+  // copy HD\r
+  //\r
+  Ptr             = (LEGACY_DEV_ORDER_ENTRY *) (&Ptr->Data[Ptr->Length / sizeof (UINT16) - 1]);\r
+  NewPtr          = (LEGACY_DEV_ORDER_ENTRY *) (&NewPtr->Data[NewPtr->Length / sizeof (UINT16) -1]);\r
+  NewPtr->BbsType = Ptr->BbsType;\r
+  NewPtr->Length  = (UINT16) (sizeof (UINT16) + HDCount * sizeof (UINT16));\r
+  for (Index = 0; Index < Ptr->Length / sizeof (UINT16) - 1; Index++) {\r
+    if (LocalBbsTable[Ptr->Data[Index] & 0xFF].BootPriority == BBS_IGNORE_ENTRY ||\r
+        LocalBbsTable[Ptr->Data[Index] & 0xFF].BootPriority == BBS_DO_NOT_BOOT_FROM ||\r
+        LocalBbsTable[Ptr->Data[Index] & 0xFF].BootPriority == BBS_LOWEST_PRIORITY ||\r
+        LocalBbsTable[Ptr->Data[Index] & 0xFF].DeviceType != BBS_HARDDISK\r
+        ) {\r
+      continue;\r
+    }\r
+\r
+    NewPtr->Data[HDIndex] = Ptr->Data[Index];\r
+    HDIndex++;\r
+  }\r
+  NewHDPtr = NewPtr->Data;\r
+\r
+  //\r
+  // copy CD\r
+  //\r
+  Ptr    = (LEGACY_DEV_ORDER_ENTRY *) (&Ptr->Data[Ptr->Length / sizeof (UINT16) - 1]);\r
+  NewPtr = (LEGACY_DEV_ORDER_ENTRY *) (&NewPtr->Data[NewPtr->Length / sizeof (UINT16) -1]);\r
+  NewPtr->BbsType = Ptr->BbsType;\r
+  NewPtr->Length  = (UINT16) (sizeof (UINT16) + CDCount * sizeof (UINT16));\r
+  for (Index = 0; Index < Ptr->Length / sizeof (UINT16) - 1; Index++) {\r
+    if (LocalBbsTable[Ptr->Data[Index] & 0xFF].BootPriority == BBS_IGNORE_ENTRY ||\r
+        LocalBbsTable[Ptr->Data[Index] & 0xFF].BootPriority == BBS_DO_NOT_BOOT_FROM ||\r
+        LocalBbsTable[Ptr->Data[Index] & 0xFF].BootPriority == BBS_LOWEST_PRIORITY ||\r
+        LocalBbsTable[Ptr->Data[Index] & 0xFF].DeviceType != BBS_CDROM\r
+        ) {\r
+      continue;\r
+    }\r
+\r
+    NewPtr->Data[CDIndex] = Ptr->Data[Index];\r
+    CDIndex++;\r
+  }\r
+  NewCDPtr = NewPtr->Data;\r
+\r
+  //\r
+  // copy NET\r
+  //\r
+  Ptr    = (LEGACY_DEV_ORDER_ENTRY *) (&Ptr->Data[Ptr->Length / sizeof (UINT16) - 1]);\r
+  NewPtr = (LEGACY_DEV_ORDER_ENTRY *) (&NewPtr->Data[NewPtr->Length / sizeof (UINT16) -1]);\r
+  NewPtr->BbsType = Ptr->BbsType;\r
+  NewPtr->Length  = (UINT16) (sizeof (UINT16) + NETCount * sizeof (UINT16));\r
+  for (Index = 0; Index < Ptr->Length / sizeof (UINT16) - 1; Index++) {\r
+    if (LocalBbsTable[Ptr->Data[Index] & 0xFF].BootPriority == BBS_IGNORE_ENTRY ||\r
+        LocalBbsTable[Ptr->Data[Index] & 0xFF].BootPriority == BBS_DO_NOT_BOOT_FROM ||\r
+        LocalBbsTable[Ptr->Data[Index] & 0xFF].BootPriority == BBS_LOWEST_PRIORITY ||\r
+        LocalBbsTable[Ptr->Data[Index] & 0xFF].DeviceType != BBS_EMBED_NETWORK\r
+        ) {\r
+      continue;\r
+    }\r
+\r
+    NewPtr->Data[NETIndex] = Ptr->Data[Index];\r
+    NETIndex++;\r
+  }\r
+  NewNETPtr = NewPtr->Data;\r
+  \r
+  //\r
+  // copy BEV\r
+  //\r
+  Ptr    = (LEGACY_DEV_ORDER_ENTRY *) (&Ptr->Data[Ptr->Length / sizeof (UINT16) - 1]);\r
+  NewPtr = (LEGACY_DEV_ORDER_ENTRY *) (&NewPtr->Data[NewPtr->Length / sizeof (UINT16) -1]);\r
+  NewPtr->BbsType = Ptr->BbsType;\r
+  NewPtr->Length  = (UINT16) (sizeof (UINT16) + BEVCount * sizeof (UINT16));\r
+  for (Index = 0; Index < Ptr->Length / sizeof (UINT16) - 1; Index++) {\r
+    if (LocalBbsTable[Ptr->Data[Index] & 0xFF].BootPriority == BBS_IGNORE_ENTRY ||\r
+        LocalBbsTable[Ptr->Data[Index] & 0xFF].BootPriority == BBS_DO_NOT_BOOT_FROM ||\r
+        LocalBbsTable[Ptr->Data[Index] & 0xFF].BootPriority == BBS_LOWEST_PRIORITY ||\r
+        LocalBbsTable[Ptr->Data[Index] & 0xFF].DeviceType != BBS_BEV_DEVICE\r
+        ) {\r
+      continue;\r
+    }\r
+\r
+    NewPtr->Data[BEVIndex] = Ptr->Data[Index];\r
+    BEVIndex++;\r
+  }\r
+  NewBEVPtr = NewPtr->Data;\r
+\r
+  for (Index = 0; Index < BbsCount; Index++) {\r
+    if ((LocalBbsTable[Index].BootPriority == BBS_IGNORE_ENTRY) ||\r
+        (LocalBbsTable[Index].BootPriority == BBS_DO_NOT_BOOT_FROM)\r
+        ) {\r
+      continue;\r
+    }\r
+\r
+    switch (LocalBbsTable[Index].DeviceType) {\r
+    case BBS_FLOPPY:\r
+      Idx       = &FDIndex;\r
+      NewDevPtr = NewFDPtr;\r
+      break;\r
+\r
+    case BBS_HARDDISK:\r
+      Idx       = &HDIndex;\r
+      NewDevPtr = NewHDPtr;\r
+      break;\r
+\r
+    case BBS_CDROM:\r
+      Idx       = &CDIndex;\r
+      NewDevPtr = NewCDPtr;\r
+      break;\r
+\r
+    case BBS_EMBED_NETWORK:\r
+      Idx       = &NETIndex;\r
+      NewDevPtr = NewNETPtr;\r
+      break;\r
+\r
+    case BBS_BEV_DEVICE:\r
+      Idx       = &BEVIndex;\r
+      NewDevPtr = NewBEVPtr;\r
+      break;\r
+\r
+    default:\r
+      Idx = NULL;\r
+      break;\r
+    }\r
+    //\r
+    // at this point we have copied those valid indexes to new buffer\r
+    // and we should check if there is any new appeared boot device\r
+    //\r
+    if (Idx != NULL) {\r
+      for (Index2 = 0; Index2 < *Idx; Index2++) {\r
+        if ((NewDevPtr[Index2] & 0xFF) == (UINT16) Index) {\r
+          break;\r
+        }\r
+      }\r
+\r
+      if (Index2 == *Idx) {\r
+        //\r
+        // Index2 == *Idx means we didn't find Index\r
+        // so Index is a new appeared device's index in BBS table\r
+        // insert it before disabled indexes.\r
+        //\r
+        for (Index2 = 0; Index2 < *Idx; Index2++) {\r
+          if ((NewDevPtr[Index2] & 0xFF00) == 0xFF00) {\r
+            break;\r
+          }\r
+        }\r
+        CopyMem (&NewDevPtr[Index2 + 1], &NewDevPtr[Index2], (*Idx - Index2) * sizeof (UINT16));\r
+        NewDevPtr[Index2] = (UINT16) (Index & 0xFF);\r
+        (*Idx)++;\r
+      }\r
+    }\r
+  }\r
+\r
+  FreePool (DevOrder);\r
+\r
+  Status = gRT->SetVariable (\r
+                  VAR_LEGACY_DEV_ORDER,\r
+                  &gEfiLegacyDevOrderVariableGuid,\r
+                  EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS | EFI_VARIABLE_NON_VOLATILE,\r
+                  TotalSize,\r
+                  NewDevOrder\r
+                  );\r
+  FreePool (NewDevOrder);\r
+\r
+  return Status;\r
+}\r
+\r
+/**\r
+  Set Boot Priority for specified device type.\r
+\r
+  @param DeviceType      The device type.\r
+  @param BbsIndex        The BBS index to set the highest priority. Ignore when -1.\r
+  @param LocalBbsTable   The BBS table.\r
+  @param Priority        The prority table.\r
+\r
+  @retval EFI_SUCCESS           The function completes successfully.\r
+  @retval EFI_NOT_FOUND         Failed to find device.\r
+  @retval EFI_OUT_OF_RESOURCES  Failed to get the efi variable of device order.\r
+\r
+**/\r
+EFI_STATUS\r
+BdsSetBootPriority4SameTypeDev (\r
+  IN UINT16                                              DeviceType,\r
+  IN UINTN                                               BbsIndex,\r
+  IN OUT BBS_TABLE                                       *LocalBbsTable,\r
+  IN OUT UINT16                                          *Priority\r
+  )\r
+{\r
+  LEGACY_DEV_ORDER_ENTRY      *DevOrder;\r
+  LEGACY_DEV_ORDER_ENTRY      *DevOrderPtr;\r
+  UINTN                       DevOrderSize;\r
+  UINTN                       Index;\r
+\r
+  DevOrder = BdsLibGetVariableAndSize (\r
+               VAR_LEGACY_DEV_ORDER,\r
+               &gEfiLegacyDevOrderVariableGuid,\r
+               &DevOrderSize\r
+               );\r
+  if (NULL == DevOrder) {\r
+    return EFI_OUT_OF_RESOURCES;\r
+  }\r
+\r
+  DevOrderPtr = DevOrder;\r
+  while ((UINT8 *) DevOrderPtr < (UINT8 *) DevOrder + DevOrderSize) {\r
+    if (DevOrderPtr->BbsType == DeviceType) {\r
+      break;\r
+    }\r
+\r
+    DevOrderPtr = (LEGACY_DEV_ORDER_ENTRY *) ((UINT8 *) DevOrderPtr + sizeof (BBS_TYPE) + DevOrderPtr->Length);\r
+  }\r
+\r
+  if ((UINT8 *) DevOrderPtr >= (UINT8 *) DevOrder + DevOrderSize) {\r
+    FreePool (DevOrder);\r
+    return EFI_NOT_FOUND;\r
+  }\r
+\r
+  if (BbsIndex != (UINTN) -1) {\r
+    LocalBbsTable[BbsIndex].BootPriority = *Priority;\r
+    (*Priority)++;\r
+  }\r
+  //\r
+  // If the high byte of the DevIndex is 0xFF, it indicates that this device has been disabled.\r
+  //\r
+  for (Index = 0; Index < DevOrderPtr->Length / sizeof (UINT16) - 1; Index++) {\r
+    if ((DevOrderPtr->Data[Index] & 0xFF00) == 0xFF00) {\r
+      //\r
+      // LocalBbsTable[DevIndex[Index] & 0xFF].BootPriority = BBS_DISABLED_ENTRY;\r
+      //\r
+    } else if (DevOrderPtr->Data[Index] != BbsIndex) {\r
+      LocalBbsTable[DevOrderPtr->Data[Index]].BootPriority = *Priority;\r
+      (*Priority)++;\r
+    }\r
+  }\r
+\r
+  FreePool (DevOrder);\r
+  return EFI_SUCCESS;\r
+}\r
+\r
+/**\r
+  Print the BBS Table.\r
+\r
+  @param LocalBbsTable   The BBS table.\r
+  @param BbsCount        The count of entry in BBS table.\r
+**/\r
+VOID\r
+PrintBbsTable (\r
+  IN BBS_TABLE  *LocalBbsTable,\r
+  IN UINT16     BbsCount\r
+  )\r
+{\r
+  UINT16  Idx;\r
+\r
+  DEBUG ((DEBUG_ERROR, "\n"));\r
+  DEBUG ((DEBUG_ERROR, " NO  Prio bb/dd/ff cl/sc Type Stat segm:offs\n"));\r
+  DEBUG ((DEBUG_ERROR, "=============================================\n"));\r
+  for (Idx = 0; Idx < BbsCount; Idx++) {\r
+    if ((LocalBbsTable[Idx].BootPriority == BBS_IGNORE_ENTRY) ||\r
+        (LocalBbsTable[Idx].BootPriority == BBS_DO_NOT_BOOT_FROM) ||\r
+        (LocalBbsTable[Idx].BootPriority == BBS_LOWEST_PRIORITY)\r
+        ) {\r
+      continue;\r
+    }\r
+\r
+    DEBUG (\r
+      (DEBUG_ERROR,\r
+      " %02x: %04x %02x/%02x/%02x %02x/%02x %04x %04x %04x:%04x\n",\r
+      (UINTN) Idx,\r
+      (UINTN) LocalBbsTable[Idx].BootPriority,\r
+      (UINTN) LocalBbsTable[Idx].Bus,\r
+      (UINTN) LocalBbsTable[Idx].Device,\r
+      (UINTN) LocalBbsTable[Idx].Function,\r
+      (UINTN) LocalBbsTable[Idx].Class,\r
+      (UINTN) LocalBbsTable[Idx].SubClass,\r
+      (UINTN) LocalBbsTable[Idx].DeviceType,\r
+      (UINTN) * (UINT16 *) &LocalBbsTable[Idx].StatusFlags,\r
+      (UINTN) LocalBbsTable[Idx].BootHandlerSegment,\r
+      (UINTN) LocalBbsTable[Idx].BootHandlerOffset,\r
+      (UINTN) ((LocalBbsTable[Idx].MfgStringSegment << 4) + LocalBbsTable[Idx].MfgStringOffset),\r
+      (UINTN) ((LocalBbsTable[Idx].DescStringSegment << 4) + LocalBbsTable[Idx].DescStringOffset))\r
+      );\r
+  }\r
+\r
+  DEBUG ((DEBUG_ERROR, "\n"));\r
+}\r
+\r
+/**\r
+  Set the boot priority for BBS entries based on boot option entry and boot order.\r
+\r
+  @param  Entry             The boot option is to be checked for refresh BBS table.\r
+  \r
+  @retval EFI_SUCCESS           The boot priority for BBS entries is refreshed successfully.\r
+  @retval EFI_NOT_FOUND         BBS entries can't be found.\r
+  @retval EFI_OUT_OF_RESOURCES  Failed to get the legacy device boot order.\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+BdsRefreshBbsTableForBoot (\r
+  IN BDS_COMMON_OPTION        *Entry\r
+  )\r
+{\r
+  EFI_STATUS                Status;\r
+  UINT16                    BbsIndex;\r
+  UINT16                    HddCount;\r
+  UINT16                    BbsCount;\r
+  HDD_INFO                  *LocalHddInfo;\r
+  BBS_TABLE                 *LocalBbsTable;\r
+  UINT16                    DevType;\r
+  EFI_LEGACY_BIOS_PROTOCOL  *LegacyBios;\r
+  UINTN                     Index;\r
+  UINT16                    Priority;\r
+  UINT16                    *BootOrder;\r
+  UINTN                     BootOrderSize;\r
+  UINT8                     *BootOptionVar;\r
+  UINTN                     BootOptionSize;\r
+  CHAR16                    BootOption[9];\r
+  UINT8                     *Ptr;\r
+  UINT16                    DevPathLen;\r
+  EFI_DEVICE_PATH_PROTOCOL  *DevPath;\r
+  UINT16                    *DeviceType;\r
+  UINTN                     DeviceTypeCount;\r
+  UINTN                     DeviceTypeIndex;\r
+\r
+  HddCount      = 0;\r
+  BbsCount      = 0;\r
+  LocalHddInfo  = NULL;\r
+  LocalBbsTable = NULL;\r
+  DevType       = BBS_UNKNOWN;\r
+\r
+  Status        = gBS->LocateProtocol (&gEfiLegacyBiosProtocolGuid, NULL, (VOID **) &LegacyBios);\r
+  if (EFI_ERROR (Status)) {\r
+    return Status;\r
+  }\r
+\r
+  LegacyBios->GetBbsInfo (\r
+                LegacyBios,\r
+                &HddCount,\r
+                &LocalHddInfo,\r
+                &BbsCount,\r
+                &LocalBbsTable\r
+                );\r
+  //\r
+  // First, set all the present devices' boot priority to BBS_UNPRIORITIZED_ENTRY\r
+  // We will set them according to the settings setup by user\r
+  //\r
+  for (Index = 0; Index < BbsCount; Index++) {\r
+    if (!((BBS_IGNORE_ENTRY == LocalBbsTable[Index].BootPriority) ||\r
+        (BBS_DO_NOT_BOOT_FROM == LocalBbsTable[Index].BootPriority) ||\r
+         (BBS_LOWEST_PRIORITY == LocalBbsTable[Index].BootPriority))) {\r
+      LocalBbsTable[Index].BootPriority = BBS_UNPRIORITIZED_ENTRY;\r
+    }\r
+  }\r
+  //\r
+  // boot priority always starts at 0\r
+  //\r
+  Priority = 0;\r
+  if (Entry->LoadOptionsSize == sizeof (BBS_TABLE) + sizeof (UINT16)) {\r
+    //\r
+    // If Entry stands for a legacy boot option, we prioritize the devices with the same type first.\r
+    //\r
+    DevType  = ((BBS_TABLE *) Entry->LoadOptions)->DeviceType;\r
+    BbsIndex = *(UINT16 *) ((BBS_TABLE *) Entry->LoadOptions + 1);\r
+    Status = BdsSetBootPriority4SameTypeDev (\r
+              DevType,\r
+              BbsIndex,\r
+              LocalBbsTable,\r
+              &Priority\r
+              );\r
+    if (EFI_ERROR (Status)) {\r
+      return Status;\r
+    }\r
+  }\r
+  //\r
+  // we have to set the boot priority for other BBS entries with different device types\r
+  //\r
+  BootOrder = BdsLibGetVariableAndSize (\r
+                L"BootOrder",\r
+                &gEfiGlobalVariableGuid,\r
+                &BootOrderSize\r
+                );\r
+  DeviceType = AllocatePool (BootOrderSize + sizeof (UINT16));\r
+  ASSERT (DeviceType != NULL);\r
+\r
+  DeviceType[0]   = DevType;\r
+  DeviceTypeCount = 1;\r
+  for (Index = 0; ((BootOrder != NULL) && (Index < BootOrderSize / sizeof (UINT16))); Index++) {\r
+    UnicodeSPrint (BootOption, sizeof (BootOption), L"Boot%04x", BootOrder[Index]);\r
+    BootOptionVar = BdsLibGetVariableAndSize (\r
+                      BootOption,\r
+                      &gEfiGlobalVariableGuid,\r
+                      &BootOptionSize\r
+                      );\r
+    if (NULL == BootOptionVar) {\r
+      continue;\r
+    }\r
+\r
+    Ptr = BootOptionVar;\r
+\r
+    Ptr += sizeof (UINT32);\r
+    DevPathLen = *(UINT16 *) Ptr;\r
+    Ptr += sizeof (UINT16);\r
+    Ptr += StrSize ((UINT16 *) Ptr);\r
+    DevPath = (EFI_DEVICE_PATH_PROTOCOL *) Ptr;\r
+    if (BBS_DEVICE_PATH != DevPath->Type || BBS_BBS_DP != DevPath->SubType) {\r
+      FreePool (BootOptionVar);\r
+      continue;\r
+    }\r
+\r
+    Ptr += DevPathLen;\r
+    DevType = ((BBS_TABLE *) Ptr)->DeviceType;\r
+    for (DeviceTypeIndex = 0; DeviceTypeIndex < DeviceTypeCount; DeviceTypeIndex++) {\r
+      if (DeviceType[DeviceTypeIndex] == DevType) {\r
+        break;\r
+      }\r
+    }\r
+    if (DeviceTypeIndex < DeviceTypeCount) {\r
+      //\r
+      // We don't want to process twice for a device type\r
+      //\r
+      FreePool (BootOptionVar);\r
+      continue;\r
+    }\r
+\r
+    DeviceType[DeviceTypeCount] = DevType;\r
+    DeviceTypeCount++;\r
+\r
+    Status = BdsSetBootPriority4SameTypeDev (\r
+              DevType,\r
+              (UINTN) -1,\r
+              LocalBbsTable,\r
+              &Priority\r
+              );\r
+    FreePool (BootOptionVar);\r
+    if (EFI_ERROR (Status)) {\r
+      break;\r
+    }\r
+  }\r
+\r
+  if (BootOrder != NULL) {\r
+    FreePool (BootOrder);\r
+  }\r
+\r
+  DEBUG_CODE_BEGIN();\r
+    PrintBbsTable (LocalBbsTable, BbsCount);\r
+  DEBUG_CODE_END();\r
+\r
+  return Status;\r
+}\r
+\r
+/**\r
+  Boot the legacy system with the boot option\r
+\r
+  @param  Option                 The legacy boot option which have BBS device path\r
+\r
+  @retval EFI_UNSUPPORTED        There is no legacybios protocol, do not support\r
+                                 legacy boot.\r
+  @retval EFI_STATUS             Return the status of LegacyBios->LegacyBoot ().\r
+\r
+**/\r
+EFI_STATUS\r
+BdsLibDoLegacyBoot (\r
+  IN  BDS_COMMON_OPTION           *Option\r
+  )\r
+{\r
+  EFI_STATUS                Status;\r
+  EFI_LEGACY_BIOS_PROTOCOL  *LegacyBios;\r
+  EFI_EVENT                 LegacyBootEvent;\r
+\r
+  Status = gBS->LocateProtocol (&gEfiLegacyBiosProtocolGuid, NULL, (VOID **) &LegacyBios);\r
+  if (EFI_ERROR (Status)) {\r
+    //\r
+    // If no LegacyBios protocol we do not support legacy boot\r
+    //\r
+    return EFI_UNSUPPORTED;\r
+  }\r
+  //\r
+  // Notes: if we separate the int 19, then we don't need to refresh BBS\r
+  //\r
+  BdsRefreshBbsTableForBoot (Option);\r
+\r
+  //\r
+  // Write boot to OS performance data for legacy boot.\r
+  //\r
+  PERF_CODE (\r
+    //\r
+    // Create an event to be signalled when Legacy Boot occurs to write performance data.\r
+    //\r
+    Status = EfiCreateEventLegacyBootEx(\r
+               TPL_NOTIFY,\r
+               WriteBootToOsPerformanceData,\r
+               NULL, \r
+               &LegacyBootEvent\r
+               );\r
+    ASSERT_EFI_ERROR (Status);\r
+  );\r
+\r
+  DEBUG ((DEBUG_INFO | DEBUG_LOAD, "Legacy Boot: %S\n", Option->Description));\r
+  return LegacyBios->LegacyBoot (\r
+                      LegacyBios,\r
+                      (BBS_BBS_DEVICE_PATH *) Option->DevicePath,\r
+                      Option->LoadOptionsSize,\r
+                      Option->LoadOptions\r
+                      );\r
+}\r
+\r
+/**\r
+  Internal function to check if the input boot option is a valid EFI NV Boot####.\r
+\r
+  @param OptionToCheck  Boot option to be checked.\r
+\r
+  @retval TRUE      This boot option matches a valid EFI NV Boot####.\r
+  @retval FALSE     If not.\r
+\r
+**/\r
+BOOLEAN\r
+IsBootOptionValidNVVarialbe (\r
+  IN  BDS_COMMON_OPTION             *OptionToCheck\r
+  )\r
+{\r
+  LIST_ENTRY        TempList;\r
+  BDS_COMMON_OPTION *BootOption;\r
+  BOOLEAN           Valid;\r
+  CHAR16            OptionName[20];\r
+\r
+  Valid = FALSE;\r
+\r
+  InitializeListHead (&TempList);\r
+  UnicodeSPrint (OptionName, sizeof (OptionName), L"Boot%04x", OptionToCheck->BootCurrent);\r
+\r
+  BootOption = BdsLibVariableToOption (&TempList, OptionName);\r
+  if (BootOption == NULL) {\r
+    return FALSE;\r
+  }\r
+\r
+  //\r
+  // If the Boot Option Number and Device Path matches, OptionToCheck matches a\r
+  // valid EFI NV Boot####.\r
+  //\r
+  if ((OptionToCheck->BootCurrent == BootOption->BootCurrent) &&\r
+      (CompareMem (OptionToCheck->DevicePath, BootOption->DevicePath, GetDevicePathSize (OptionToCheck->DevicePath)) == 0))\r
+      {\r
+    Valid = TRUE;\r
+  }\r
+\r
+  FreePool (BootOption);\r
+\r
+  return Valid;\r
+}\r
+\r
+/**\r
+  Check whether a USB device match the specified USB Class device path. This\r
+  function follows "Load Option Processing" behavior in UEFI specification.\r
+\r
+  @param UsbIo       USB I/O protocol associated with the USB device.\r
+  @param UsbClass    The USB Class device path to match.\r
+\r
+  @retval TRUE       The USB device match the USB Class device path.\r
+  @retval FALSE      The USB device does not match the USB Class device path.\r
+\r
+**/\r
+BOOLEAN\r
+BdsMatchUsbClass (\r
+  IN EFI_USB_IO_PROTOCOL        *UsbIo,\r
+  IN USB_CLASS_DEVICE_PATH      *UsbClass\r
+  )\r
+{\r
+  EFI_STATUS                    Status;\r
+  EFI_USB_DEVICE_DESCRIPTOR     DevDesc;\r
+  EFI_USB_INTERFACE_DESCRIPTOR  IfDesc;\r
+  UINT8                         DeviceClass;\r
+  UINT8                         DeviceSubClass;\r
+  UINT8                         DeviceProtocol;\r
+\r
+  if ((DevicePathType (UsbClass) != MESSAGING_DEVICE_PATH) ||\r
+      (DevicePathSubType (UsbClass) != MSG_USB_CLASS_DP)){\r
+    return FALSE;\r
+  }\r
+\r
+  //\r
+  // Check Vendor Id and Product Id.\r
+  //\r
+  Status = UsbIo->UsbGetDeviceDescriptor (UsbIo, &DevDesc);\r
+  if (EFI_ERROR (Status)) {\r
+    return FALSE;\r
+  }\r
+\r
+  if ((UsbClass->VendorId != 0xffff) &&\r
+      (UsbClass->VendorId != DevDesc.IdVendor)) {\r
+    return FALSE;\r
+  }\r
+\r
+  if ((UsbClass->ProductId != 0xffff) &&\r
+      (UsbClass->ProductId != DevDesc.IdProduct)) {\r
+    return FALSE;\r
+  }\r
+\r
+  DeviceClass    = DevDesc.DeviceClass;\r
+  DeviceSubClass = DevDesc.DeviceSubClass;\r
+  DeviceProtocol = DevDesc.DeviceProtocol;\r
+  if (DeviceClass == 0) {\r
+    //\r
+    // If Class in Device Descriptor is set to 0, use the Class, SubClass and\r
+    // Protocol in Interface Descriptor instead.\r
+    //\r
+    Status = UsbIo->UsbGetInterfaceDescriptor (UsbIo, &IfDesc);\r
+    if (EFI_ERROR (Status)) {\r
+      return FALSE;\r
+    }\r
+\r
+    DeviceClass    = IfDesc.InterfaceClass;\r
+    DeviceSubClass = IfDesc.InterfaceSubClass;\r
+    DeviceProtocol = IfDesc.InterfaceProtocol;\r
+  }\r
+\r
+  //\r
+  // Check Class, SubClass and Protocol.\r
+  //\r
+  if ((UsbClass->DeviceClass != 0xff) &&\r
+      (UsbClass->DeviceClass != DeviceClass)) {\r
+    return FALSE;\r
+  }\r
+\r
+  if ((UsbClass->DeviceSubClass != 0xff) &&\r
+      (UsbClass->DeviceSubClass != DeviceSubClass)) {\r
+    return FALSE;\r
+  }\r
+\r
+  if ((UsbClass->DeviceProtocol != 0xff) &&\r
+      (UsbClass->DeviceProtocol != DeviceProtocol)) {\r
+    return FALSE;\r
+  }\r
+\r
+  return TRUE;\r
+}\r
+\r
+/**\r
+  Check whether a USB device match the specified USB WWID device path. This\r
+  function follows "Load Option Processing" behavior in UEFI specification.\r
+\r
+  @param UsbIo       USB I/O protocol associated with the USB device.\r
+  @param UsbWwid     The USB WWID device path to match.\r
+\r
+  @retval TRUE       The USB device match the USB WWID device path.\r
+  @retval FALSE      The USB device does not match the USB WWID device path.\r
+\r
+**/\r
+BOOLEAN\r
+BdsMatchUsbWwid (\r
+  IN EFI_USB_IO_PROTOCOL        *UsbIo,\r
+  IN USB_WWID_DEVICE_PATH       *UsbWwid\r
+  )\r
+{\r
+  EFI_STATUS                   Status;\r
+  EFI_USB_DEVICE_DESCRIPTOR    DevDesc;\r
+  EFI_USB_INTERFACE_DESCRIPTOR IfDesc;\r
+  UINT16                       *LangIdTable;\r
+  UINT16                       TableSize;\r
+  UINT16                       Index;\r
+  CHAR16                       *CompareStr;\r
+  UINTN                        CompareLen;\r
+  CHAR16                       *SerialNumberStr;\r
+  UINTN                        Length;\r
+\r
+  if ((DevicePathType (UsbWwid) != MESSAGING_DEVICE_PATH) ||\r
+      (DevicePathSubType (UsbWwid) != MSG_USB_WWID_DP )){\r
+    return FALSE;\r
+  }\r
+\r
+  //\r
+  // Check Vendor Id and Product Id.\r
+  //\r
+  Status = UsbIo->UsbGetDeviceDescriptor (UsbIo, &DevDesc);\r
+  if (EFI_ERROR (Status)) {\r
+    return FALSE;\r
+  }\r
+  if ((DevDesc.IdVendor != UsbWwid->VendorId) ||\r
+      (DevDesc.IdProduct != UsbWwid->ProductId)) {\r
+    return FALSE;\r
+  }\r
+\r
+  //\r
+  // Check Interface Number.\r
+  //\r
+  Status = UsbIo->UsbGetInterfaceDescriptor (UsbIo, &IfDesc);\r
+  if (EFI_ERROR (Status)) {\r
+    return FALSE;\r
+  }\r
+  if (IfDesc.InterfaceNumber != UsbWwid->InterfaceNumber) {\r
+    return FALSE;\r
+  }\r
+\r
+  //\r
+  // Check Serial Number.\r
+  //\r
+  if (DevDesc.StrSerialNumber == 0) {\r
+    return FALSE;\r
+  }\r
+\r
+  //\r
+  // Get all supported languages.\r
+  //\r
+  TableSize = 0;\r
+  LangIdTable = NULL;\r
+  Status = UsbIo->UsbGetSupportedLanguages (UsbIo, &LangIdTable, &TableSize);\r
+  if (EFI_ERROR (Status) || (TableSize == 0) || (LangIdTable == NULL)) {\r
+    return FALSE;\r
+  }\r
+\r
+  //\r
+  // Serial number in USB WWID device path is the last 64-or-less UTF-16 characters.\r
+  //\r
+  CompareStr = (CHAR16 *) (UINTN) (UsbWwid + 1);\r
+  CompareLen = (DevicePathNodeLength (UsbWwid) - sizeof (USB_WWID_DEVICE_PATH)) / sizeof (CHAR16);\r
+  if (CompareStr[CompareLen - 1] == L'\0') {\r
+    CompareLen--;\r
+  }\r
+\r
+  //\r
+  // Compare serial number in each supported language.\r
+  //\r
+  for (Index = 0; Index < TableSize / sizeof (UINT16); Index++) {\r
+    SerialNumberStr = NULL;\r
+    Status = UsbIo->UsbGetStringDescriptor (\r
+                      UsbIo,\r
+                      LangIdTable[Index],\r
+                      DevDesc.StrSerialNumber,\r
+                      &SerialNumberStr\r
+                      );\r
+    if (EFI_ERROR (Status) || (SerialNumberStr == NULL)) {\r
+      continue;\r
+    }\r
+\r
+    Length = StrLen (SerialNumberStr);\r
+    if ((Length >= CompareLen) &&\r
+        (CompareMem (SerialNumberStr + Length - CompareLen, CompareStr, CompareLen * sizeof (CHAR16)) == 0)) {\r
+      FreePool (SerialNumberStr);\r
+      return TRUE;\r
+    }\r
+\r
+    FreePool (SerialNumberStr);\r
+  }\r
+\r
+  return FALSE;\r
+}\r
+\r
+/**\r
+  Find a USB device path which match the specified short-form device path start\r
+  with USB Class or USB WWID device path and load the boot file then return the \r
+  image handle. If ParentDevicePath is NULL, this function will search in all USB\r
+  devices of the platform. If ParentDevicePath is not NULL,this function will only\r
+  search in its child devices.\r
+\r
+  @param ParentDevicePath      The device path of the parent.\r
+  @param ShortFormDevicePath   The USB Class or USB WWID device path to match.\r
+\r
+  @return  The image Handle if find load file from specified short-form device path\r
+           or NULL if not found.\r
+\r
+**/\r
+EFI_HANDLE *\r
+BdsFindUsbDevice (\r
+  IN EFI_DEVICE_PATH_PROTOCOL   *ParentDevicePath,\r
+  IN EFI_DEVICE_PATH_PROTOCOL   *ShortFormDevicePath\r
+  )\r
+{\r
+  EFI_STATUS                Status;\r
+  UINTN                     UsbIoHandleCount;\r
+  EFI_HANDLE                *UsbIoHandleBuffer;\r
+  EFI_DEVICE_PATH_PROTOCOL  *UsbIoDevicePath;\r
+  EFI_USB_IO_PROTOCOL       *UsbIo;\r
+  UINTN                     Index;\r
+  UINTN                     ParentSize;\r
+  UINTN                     Size;\r
+  EFI_HANDLE                ImageHandle;\r
+  EFI_HANDLE                Handle;\r
+  EFI_DEVICE_PATH_PROTOCOL  *FullDevicePath;\r
+  EFI_DEVICE_PATH_PROTOCOL  *NextDevicePath;\r
+\r
+  FullDevicePath = NULL;\r
+  ImageHandle    = NULL;\r
+\r
+  //\r
+  // Get all UsbIo Handles.\r
+  //\r
+  UsbIoHandleCount = 0;\r
+  UsbIoHandleBuffer = NULL;\r
+  Status = gBS->LocateHandleBuffer (\r
+                  ByProtocol,\r
+                  &gEfiUsbIoProtocolGuid,\r
+                  NULL,\r
+                  &UsbIoHandleCount,\r
+                  &UsbIoHandleBuffer\r
+                  );\r
+  if (EFI_ERROR (Status) || (UsbIoHandleCount == 0) || (UsbIoHandleBuffer == NULL)) {\r
+    return NULL;\r
+  }\r
+\r
+  ParentSize = (ParentDevicePath == NULL) ? 0 : GetDevicePathSize (ParentDevicePath);\r
+  for (Index = 0; Index < UsbIoHandleCount; Index++) {\r
+    //\r
+    // Get the Usb IO interface.\r
+    //\r
+    Status = gBS->HandleProtocol(\r
+                    UsbIoHandleBuffer[Index],\r
+                    &gEfiUsbIoProtocolGuid,\r
+                    (VOID **) &UsbIo\r
+                    );\r
+    if (EFI_ERROR (Status)) {\r
+      continue;\r
+    }\r
+\r
+    UsbIoDevicePath = DevicePathFromHandle (UsbIoHandleBuffer[Index]);\r
+    if (UsbIoDevicePath == NULL) {\r
+      continue;\r
+    }\r
+\r
+    if (ParentDevicePath != NULL) {\r
+      //\r
+      // Compare starting part of UsbIoHandle's device path with ParentDevicePath.\r
+      //\r
+      Size = GetDevicePathSize (UsbIoDevicePath);\r
+      if ((Size < ParentSize) ||\r
+          (CompareMem (UsbIoDevicePath, ParentDevicePath, ParentSize - END_DEVICE_PATH_LENGTH) != 0)) {\r
+        continue;\r
+      }\r
+    }\r
+\r
+    if (BdsMatchUsbClass (UsbIo, (USB_CLASS_DEVICE_PATH *) ShortFormDevicePath) ||\r
+        BdsMatchUsbWwid (UsbIo, (USB_WWID_DEVICE_PATH *) ShortFormDevicePath)) {\r
+      //\r
+      // Try to find if there is the boot file in this DevicePath\r
+      //\r
+      NextDevicePath = NextDevicePathNode (ShortFormDevicePath);\r
+      if (!IsDevicePathEnd (NextDevicePath)) {\r
+        FullDevicePath = AppendDevicePath (UsbIoDevicePath, NextDevicePath);\r
+        //\r
+        // Connect the full device path, so that Simple File System protocol\r
+        // could be installed for this USB device.\r
+        //\r
+        BdsLibConnectDevicePath (FullDevicePath);\r
+        REPORT_STATUS_CODE (EFI_PROGRESS_CODE, PcdGet32 (PcdProgressCodeOsLoaderLoad));\r
+        Status = gBS->LoadImage (\r
+                       TRUE,\r
+                       gImageHandle,\r
+                       FullDevicePath,\r
+                       NULL,\r
+                       0,\r
+                       &ImageHandle\r
+                       );\r
+        FreePool (FullDevicePath);\r
+      } else {\r
+        FullDevicePath = UsbIoDevicePath;\r
+        Status = EFI_NOT_FOUND;\r
+      }\r
+\r
+      //\r
+      // If we didn't find an image directly, we need to try as if it is a removable device boot option\r
+      // and load the image according to the default boot behavior for removable device.\r
+      //\r
+      if (EFI_ERROR (Status)) {\r
+        //\r
+        // check if there is a bootable removable media could be found in this device path ,\r
+        // and get the bootable media handle\r
+        //\r
+        Handle = BdsLibGetBootableHandle(UsbIoDevicePath);\r
+        if (Handle == NULL) {\r
+          continue;\r
+        }\r
+        //\r
+        // Load the default boot file \EFI\BOOT\boot{machinename}.EFI from removable Media\r
+        //  machinename is ia32, ia64, x64, ...\r
+        //\r
+        FullDevicePath = FileDevicePath (Handle, EFI_REMOVABLE_MEDIA_FILE_NAME);\r
+        if (FullDevicePath != NULL) {\r
+          REPORT_STATUS_CODE (EFI_PROGRESS_CODE, PcdGet32 (PcdProgressCodeOsLoaderLoad));\r
+          Status = gBS->LoadImage (\r
+                          TRUE,\r
+                          gImageHandle,\r
+                          FullDevicePath,\r
+                          NULL,\r
+                          0,\r
+                          &ImageHandle\r
+                          );\r
+          if (EFI_ERROR (Status)) {\r
+            //\r
+            // The DevicePath failed, and it's not a valid\r
+            // removable media device.\r
+            //\r
+            continue;\r
+          }\r
+        } else {\r
+          continue;\r
+        }\r
+      }\r
+      break;\r
+    }\r
+  }\r
+\r
+  FreePool (UsbIoHandleBuffer);\r
+  return ImageHandle;\r
+}\r
+\r
+/**\r
+  Expand USB Class or USB WWID device path node to be full device path of a USB\r
+  device in platform then load the boot file on this full device path and return the \r
+  image handle.\r
+\r
+  This function support following 4 cases:\r
+  1) Boot Option device path starts with a USB Class or USB WWID device path,\r
+     and there is no Media FilePath device path in the end.\r
+     In this case, it will follow Removable Media Boot Behavior.\r
+  2) Boot Option device path starts with a USB Class or USB WWID device path,\r
+     and ended with Media FilePath device path.\r
+  3) Boot Option device path starts with a full device path to a USB Host Controller,\r
+     contains a USB Class or USB WWID device path node, while not ended with Media\r
+     FilePath device path. In this case, it will follow Removable Media Boot Behavior.\r
+  4) Boot Option device path starts with a full device path to a USB Host Controller,\r
+     contains a USB Class or USB WWID device path node, and ended with Media\r
+     FilePath device path.\r
+\r
+  @param  DevicePath    The Boot Option device path.\r
+\r
+  @return  The image handle of boot file, or NULL if there is no boot file found in\r
+           the specified USB Class or USB WWID device path.\r
+\r
+**/\r
+EFI_HANDLE *\r
+BdsExpandUsbShortFormDevicePath (\r
+  IN EFI_DEVICE_PATH_PROTOCOL       *DevicePath\r
+  )\r
+{\r
+  EFI_HANDLE                *ImageHandle;\r
+  EFI_DEVICE_PATH_PROTOCOL  *TempDevicePath;\r
+  EFI_DEVICE_PATH_PROTOCOL  *ShortFormDevicePath;\r
+\r
+  //\r
+  // Search for USB Class or USB WWID device path node.\r
+  //\r
+  ShortFormDevicePath = NULL;\r
+  ImageHandle         = NULL;\r
+  TempDevicePath      = DevicePath;\r
+  while (!IsDevicePathEnd (TempDevicePath)) {\r
+    if ((DevicePathType (TempDevicePath) == MESSAGING_DEVICE_PATH) &&\r
+        ((DevicePathSubType (TempDevicePath) == MSG_USB_CLASS_DP) ||\r
+         (DevicePathSubType (TempDevicePath) == MSG_USB_WWID_DP))) {\r
+      ShortFormDevicePath = TempDevicePath;\r
+      break;\r
+    }\r
+    TempDevicePath = NextDevicePathNode (TempDevicePath);\r
+  }\r
+\r
+  if (ShortFormDevicePath == NULL) {\r
+    //\r
+    // No USB Class or USB WWID device path node found, do nothing.\r
+    //\r
+    return NULL;\r
+  }\r
+\r
+  if (ShortFormDevicePath == DevicePath) {\r
+    //\r
+    // Boot Option device path starts with USB Class or USB WWID device path.\r
+    //\r
+    ImageHandle = BdsFindUsbDevice (NULL, ShortFormDevicePath);\r
+    if (ImageHandle == NULL) {\r
+      //\r
+      // Failed to find a match in existing devices, connect the short form USB\r
+      // device path and try again.\r
+      //\r
+      BdsLibConnectUsbDevByShortFormDP (0xff, ShortFormDevicePath);\r
+      ImageHandle = BdsFindUsbDevice (NULL, ShortFormDevicePath);\r
+    }\r
+  } else {\r
+    //\r
+    // Boot Option device path contains USB Class or USB WWID device path node.\r
+    //\r
+\r
+    //\r
+    // Prepare the parent device path for search.\r
+    //\r
+    TempDevicePath = DuplicateDevicePath (DevicePath);\r
+    ASSERT (TempDevicePath != NULL);\r
+    SetDevicePathEndNode (((UINT8 *) TempDevicePath) + ((UINTN) ShortFormDevicePath - (UINTN) DevicePath));\r
+\r
+    //\r
+    // The USB Host Controller device path is already in Boot Option device path\r
+    // and USB Bus driver already support RemainingDevicePath starts with USB\r
+    // Class or USB WWID device path, so just search in existing USB devices and\r
+    // doesn't perform ConnectController here.\r
+    //\r
+    ImageHandle = BdsFindUsbDevice (TempDevicePath, ShortFormDevicePath);\r
+    FreePool (TempDevicePath);\r
+  }\r
+\r
+  return ImageHandle;\r
+}\r
+\r
+/**\r
+  Process the boot option follow the UEFI specification and\r
+  special treat the legacy boot option with BBS_DEVICE_PATH.\r
+\r
+  @param  Option                 The boot option need to be processed\r
+  @param  DevicePath             The device path which describe where to load the\r
+                                 boot image or the legacy BBS device path to boot\r
+                                 the legacy OS\r
+  @param  ExitDataSize           The size of exit data.\r
+  @param  ExitData               Data returned when Boot image failed.\r
+\r
+  @retval EFI_SUCCESS            Boot from the input boot option successfully.\r
+  @retval EFI_NOT_FOUND          If the Device Path is not found in the system\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+BdsLibBootViaBootOption (\r
+  IN  BDS_COMMON_OPTION             *Option,\r
+  IN  EFI_DEVICE_PATH_PROTOCOL      *DevicePath,\r
+  OUT UINTN                         *ExitDataSize,\r
+  OUT CHAR16                        **ExitData OPTIONAL\r
+  )\r
+{\r
+  EFI_STATUS                Status;\r
+  EFI_STATUS                StatusLogo;\r
+  EFI_HANDLE                Handle;\r
+  EFI_HANDLE                ImageHandle;\r
+  EFI_DEVICE_PATH_PROTOCOL  *FilePath;\r
+  EFI_LOADED_IMAGE_PROTOCOL *ImageInfo;\r
+  EFI_DEVICE_PATH_PROTOCOL  *WorkingDevicePath;\r
+  EFI_ACPI_S3_SAVE_PROTOCOL *AcpiS3Save;\r
+  LIST_ENTRY                TempBootLists;\r
+  EFI_BOOT_LOGO_PROTOCOL    *BootLogo;\r
+\r
+  *ExitDataSize = 0;\r
+  *ExitData     = NULL;\r
+\r
+  //\r
+  // Notes: this code can be remove after the s3 script table\r
+  // hook on the event EVT_SIGNAL_READY_TO_BOOT or\r
+  // EVT_SIGNAL_LEGACY_BOOT\r
+  //\r
+  Status = gBS->LocateProtocol (&gEfiAcpiS3SaveProtocolGuid, NULL, (VOID **) &AcpiS3Save);\r
+  if (!EFI_ERROR (Status)) {\r
+    AcpiS3Save->S3Save (AcpiS3Save, NULL);\r
+  }\r
+  //\r
+  // If it's Device Path that starts with a hard drive path, append it with the front part to compose a\r
+  // full device path\r
+  //\r
+  WorkingDevicePath = NULL;\r
+  if ((DevicePathType (DevicePath) == MEDIA_DEVICE_PATH) &&\r
+      (DevicePathSubType (DevicePath) == MEDIA_HARDDRIVE_DP)) {\r
+    WorkingDevicePath = BdsExpandPartitionPartialDevicePathToFull (\r
+                          (HARDDRIVE_DEVICE_PATH *)DevicePath\r
+                          );\r
+    if (WorkingDevicePath != NULL) {\r
+      DevicePath = WorkingDevicePath;\r
+    }\r
+  }\r
+\r
+  //\r
+  // Set Boot Current\r
+  //\r
+  if (IsBootOptionValidNVVarialbe (Option)) {\r
+    //\r
+    // For a temporary boot (i.e. a boot by selected a EFI Shell using "Boot From File"), Boot Current is actually not valid.\r
+    // In this case, "BootCurrent" is not created.\r
+    // Only create the BootCurrent variable when it points to a valid Boot#### variable.\r
+    //\r
+    gRT->SetVariable (\r
+          L"BootCurrent",\r
+          &gEfiGlobalVariableGuid,\r
+          EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS,\r
+          sizeof (UINT16),\r
+          &Option->BootCurrent\r
+          );\r
+  }\r
+\r
+  //\r
+  // Report Status Code to indicate ReadyToBoot event will be signalled\r
+  //\r
+  REPORT_STATUS_CODE (EFI_PROGRESS_CODE, (EFI_SOFTWARE_DXE_BS_DRIVER | EFI_SW_DXE_BS_PC_READY_TO_BOOT_EVENT));\r
+\r
+  //\r
+  // Signal the EVT_SIGNAL_READY_TO_BOOT event\r
+  //\r
+  EfiSignalEventReadyToBoot();\r
+\r
+  //\r
+  // Expand USB Class or USB WWID device path node to be full device path of a USB\r
+  // device in platform then load the boot file on this full device path and get the\r
+  // image handle.\r
+  //\r
+  ImageHandle = BdsExpandUsbShortFormDevicePath (DevicePath);\r
+\r
+  //\r
+  // Adjust the different type memory page number just before booting\r
+  // and save the updated info into the variable for next boot to use\r
+  //\r
+  BdsSetMemoryTypeInformationVariable ();\r
+\r
+  //\r
+  // By expanding the USB Class or WWID device path, the ImageHandle has returnned.\r
+  // Here get the ImageHandle for the non USB class or WWID device path.\r
+  //\r
+  if (ImageHandle == NULL) {\r
+    ASSERT (Option->DevicePath != NULL);\r
+    if ((DevicePathType (Option->DevicePath) == BBS_DEVICE_PATH) &&\r
+        (DevicePathSubType (Option->DevicePath) == BBS_BBS_DP)\r
+       ) {\r
+      //\r
+      // Check to see if we should legacy BOOT. If yes then do the legacy boot\r
+      //\r
+      return BdsLibDoLegacyBoot (Option);\r
+    }\r
+\r
+    //\r
+    // If the boot option point to Internal FV shell, make sure it is valid\r
+    //\r
+    Status = BdsLibUpdateFvFileDevicePath (&DevicePath, PcdGetPtr(PcdShellFile));\r
+    if (!EFI_ERROR(Status)) {\r
+      if (Option->DevicePath != NULL) {\r
+        FreePool(Option->DevicePath);\r
+      }\r
+      Option->DevicePath  = AllocateZeroPool (GetDevicePathSize (DevicePath));\r
+      ASSERT(Option->DevicePath != NULL);\r
+      CopyMem (Option->DevicePath, DevicePath, GetDevicePathSize (DevicePath));\r
+      //\r
+      // Update the shell boot option\r
+      //\r
+      InitializeListHead (&TempBootLists);\r
+      BdsLibRegisterNewOption (&TempBootLists, DevicePath, L"EFI Internal Shell", L"BootOrder");\r
+\r
+      //\r
+      // free the temporary device path created by BdsLibUpdateFvFileDevicePath()\r
+      //\r
+      FreePool (DevicePath);\r
+      DevicePath = Option->DevicePath;\r
+    }\r
+\r
+    DEBUG_CODE_BEGIN();\r
+\r
+    if (Option->Description == NULL) {\r
+      DEBUG ((DEBUG_INFO | DEBUG_LOAD, "Booting from unknown device path\n"));\r
+    } else {\r
+      DEBUG ((DEBUG_INFO | DEBUG_LOAD, "Booting %S\n", Option->Description));\r
+    }\r
+        \r
+    DEBUG_CODE_END();\r
+  \r
+    //\r
+    // Report status code for OS Loader LoadImage.\r
+    //\r
+    REPORT_STATUS_CODE (EFI_PROGRESS_CODE, PcdGet32 (PcdProgressCodeOsLoaderLoad));\r
+    Status = gBS->LoadImage (\r
+                    TRUE,\r
+                    gImageHandle,\r
+                    DevicePath,\r
+                    NULL,\r
+                    0,\r
+                    &ImageHandle\r
+                    );\r
+\r
+    //\r
+    // If we didn't find an image directly, we need to try as if it is a removable device boot option\r
+    // and load the image according to the default boot behavior for removable device.\r
+    //\r
+    if (EFI_ERROR (Status)) {\r
+      //\r
+      // check if there is a bootable removable media could be found in this device path ,\r
+      // and get the bootable media handle\r
+      //\r
+      Handle = BdsLibGetBootableHandle(DevicePath);\r
+      if (Handle != NULL) {\r
+        //\r
+        // Load the default boot file \EFI\BOOT\boot{machinename}.EFI from removable Media\r
+        //  machinename is ia32, ia64, x64, ...\r
+        //\r
+        FilePath = FileDevicePath (Handle, EFI_REMOVABLE_MEDIA_FILE_NAME);\r
+        if (FilePath != NULL) {\r
+          REPORT_STATUS_CODE (EFI_PROGRESS_CODE, PcdGet32 (PcdProgressCodeOsLoaderLoad));\r
+          Status = gBS->LoadImage (\r
+                          TRUE,\r
+                          gImageHandle,\r
+                          FilePath,\r
+                          NULL,\r
+                          0,\r
+                          &ImageHandle\r
+                          );\r
+        }\r
+      }\r
+    }\r
+  }\r
+  //\r
+  // Provide the image with it's load options\r
+  //\r
+  if ((ImageHandle == NULL) || (EFI_ERROR(Status))) {\r
+    //\r
+    // Report Status Code to indicate that the failure to load boot option\r
+    //\r
+    REPORT_STATUS_CODE (\r
+      EFI_ERROR_CODE | EFI_ERROR_MINOR,\r
+      (EFI_SOFTWARE_DXE_BS_DRIVER | EFI_SW_DXE_BS_EC_BOOT_OPTION_LOAD_ERROR)\r
+      );    \r
+    goto Done;\r
+  }\r
+\r
+  Status = gBS->HandleProtocol (ImageHandle, &gEfiLoadedImageProtocolGuid, (VOID **) &ImageInfo);\r
+  ASSERT_EFI_ERROR (Status);\r
+\r
+  if (Option->LoadOptionsSize != 0) {\r
+    ImageInfo->LoadOptionsSize  = Option->LoadOptionsSize;\r
+    ImageInfo->LoadOptions      = Option->LoadOptions;\r
+  }\r
+\r
+  //\r
+  // Clean to NULL because the image is loaded directly from the firmwares boot manager.\r
+  //\r
+  ImageInfo->ParentHandle = NULL;\r
+\r
+  //\r
+  // Before calling the image, enable the Watchdog Timer for\r
+  // the 5 Minute period\r
+  //\r
+  gBS->SetWatchdogTimer (5 * 60, 0x0000, 0x00, NULL);\r
+\r
+  //\r
+  // Write boot to OS performance data for UEFI boot\r
+  //\r
+  PERF_CODE (\r
+    WriteBootToOsPerformanceData (NULL, NULL);\r
+  );\r
+\r
+  //\r
+  // Report status code for OS Loader StartImage.\r
+  //\r
+  REPORT_STATUS_CODE (EFI_PROGRESS_CODE, PcdGet32 (PcdProgressCodeOsLoaderStart));\r
+\r
+  Status = gBS->StartImage (ImageHandle, ExitDataSize, ExitData);\r
+  DEBUG ((DEBUG_INFO | DEBUG_LOAD, "Image Return Status = %r\n", Status));\r
+  if (EFI_ERROR (Status)) {\r
+    //\r
+    // Report Status Code to indicate that boot failure\r
+    //\r
+    REPORT_STATUS_CODE (\r
+      EFI_ERROR_CODE | EFI_ERROR_MINOR,\r
+      (EFI_SOFTWARE_DXE_BS_DRIVER | EFI_SW_DXE_BS_EC_BOOT_OPTION_FAILED)\r
+      );\r
+  }\r
+\r
+  //\r
+  // Clear the Watchdog Timer after the image returns\r
+  //\r
+  gBS->SetWatchdogTimer (0x0000, 0x0000, 0x0000, NULL);\r
+\r
+Done:\r
+  //\r
+  // Set Logo status invalid after trying one boot option\r
+  //\r
+  BootLogo = NULL;\r
+  StatusLogo = gBS->LocateProtocol (&gEfiBootLogoProtocolGuid, NULL, (VOID **) &BootLogo);\r
+  if (!EFI_ERROR (StatusLogo) && (BootLogo != NULL)) {\r
+    BootLogo->SetBootLogo (BootLogo, NULL, 0, 0, 0, 0);\r
+  }\r
+\r
+  //\r
+  // Clear Boot Current\r
+  //\r
+  gRT->SetVariable (\r
+        L"BootCurrent",\r
+        &gEfiGlobalVariableGuid,\r
+        EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS,\r
+        0,\r
+        &Option->BootCurrent\r
+        );\r
+\r
+  return Status;\r
+}\r
+\r
+\r
+/**\r
+  Expand a device path that starts with a hard drive media device path node to be a\r
+  full device path that includes the full hardware path to the device. We need\r
+  to do this so it can be booted. As an optimization the front match (the part point\r
+  to the partition node. E.g. ACPI() /PCI()/ATA()/Partition() ) is saved in a variable\r
+  so a connect all is not required on every boot. All successful history device path\r
+  which point to partition node (the front part) will be saved.\r
+\r
+  @param  HardDriveDevicePath    EFI Device Path to boot, if it starts with a hard\r
+                                 drive media device path.\r
+  @return A Pointer to the full device path or NULL if a valid Hard Drive devic path\r
+          cannot be found.\r
+\r
+**/\r
+EFI_DEVICE_PATH_PROTOCOL *\r
+EFIAPI\r
+BdsExpandPartitionPartialDevicePathToFull (\r
+  IN  HARDDRIVE_DEVICE_PATH      *HardDriveDevicePath\r
+  )\r
+{\r
+  EFI_STATUS                Status;\r
+  UINTN                     BlockIoHandleCount;\r
+  EFI_HANDLE                *BlockIoBuffer;\r
+  EFI_DEVICE_PATH_PROTOCOL  *FullDevicePath;\r
+  EFI_DEVICE_PATH_PROTOCOL  *BlockIoDevicePath;\r
+  EFI_DEVICE_PATH_PROTOCOL  *DevicePath;\r
+  UINTN                     Index;\r
+  UINTN                     InstanceNum;\r
+  EFI_DEVICE_PATH_PROTOCOL  *CachedDevicePath;\r
+  EFI_DEVICE_PATH_PROTOCOL  *TempNewDevicePath;\r
+  UINTN                     CachedDevicePathSize;\r
+  BOOLEAN                   DeviceExist;\r
+  BOOLEAN                   NeedAdjust;\r
+  EFI_DEVICE_PATH_PROTOCOL  *Instance;\r
+  UINTN                     Size;\r
+\r
+  FullDevicePath = NULL;\r
+  //\r
+  // Check if there is prestore HD_BOOT_DEVICE_PATH_VARIABLE_NAME variable.\r
+  // If exist, search the front path which point to partition node in the variable instants.\r
+  // If fail to find or HD_BOOT_DEVICE_PATH_VARIABLE_NAME not exist, reconnect all and search in all system\r
+  //\r
+  CachedDevicePath = BdsLibGetVariableAndSize (\r
+                      HD_BOOT_DEVICE_PATH_VARIABLE_NAME,\r
+                      &gHdBootDevicePathVariablGuid,\r
+                      &CachedDevicePathSize\r
+                      );\r
+\r
+  if (CachedDevicePath != NULL) {\r
+    TempNewDevicePath = CachedDevicePath;\r
+    DeviceExist = FALSE;\r
+    NeedAdjust = FALSE;\r
+    do {\r
+      //\r
+      // Check every instance of the variable\r
+      // First, check whether the instance contain the partition node, which is needed for distinguishing  multi\r
+      // partial partition boot option. Second, check whether the instance could be connected.\r
+      //\r
+      Instance  = GetNextDevicePathInstance (&TempNewDevicePath, &Size);\r
+      if (MatchPartitionDevicePathNode (Instance, HardDriveDevicePath)) {\r
+        //\r
+        // Connect the device path instance, the device path point to hard drive media device path node\r
+        // e.g. ACPI() /PCI()/ATA()/Partition()\r
+        //\r
+        Status = BdsLibConnectDevicePath (Instance);\r
+        if (!EFI_ERROR (Status)) {\r
+          DeviceExist = TRUE;\r
+          break;\r
+        }\r
+      }\r
+      //\r
+      // Come here means the first instance is not matched\r
+      //\r
+      NeedAdjust = TRUE;\r
+      FreePool(Instance);\r
+    } while (TempNewDevicePath != NULL);\r
+\r
+    if (DeviceExist) {\r
+      //\r
+      // Find the matched device path.\r
+      // Append the file path information from the boot option and return the fully expanded device path.\r
+      //\r
+      DevicePath     = NextDevicePathNode ((EFI_DEVICE_PATH_PROTOCOL *) HardDriveDevicePath);\r
+      FullDevicePath = AppendDevicePath (Instance, DevicePath);\r
+\r
+      //\r
+      // Adjust the HD_BOOT_DEVICE_PATH_VARIABLE_NAME instances sequence if the matched one is not first one.\r
+      //\r
+      if (NeedAdjust) {\r
+        //\r
+        // First delete the matched instance.\r
+        //\r
+        TempNewDevicePath = CachedDevicePath;\r
+        CachedDevicePath  = BdsLibDelPartMatchInstance (CachedDevicePath, Instance );\r
+        FreePool (TempNewDevicePath);\r
+\r
+        //\r
+        // Second, append the remaining path after the matched instance\r
+        //\r
+        TempNewDevicePath = CachedDevicePath;\r
+        CachedDevicePath = AppendDevicePathInstance (Instance, CachedDevicePath );\r
+        FreePool (TempNewDevicePath);\r
+        //\r
+        // Save the matching Device Path so we don't need to do a connect all next time\r
+        //\r
+        Status = gRT->SetVariable (\r
+                        HD_BOOT_DEVICE_PATH_VARIABLE_NAME,\r
+                        &gHdBootDevicePathVariablGuid,\r
+                        EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS | EFI_VARIABLE_NON_VOLATILE,\r
+                        GetDevicePathSize (CachedDevicePath),\r
+                        CachedDevicePath\r
+                        );\r
+      }\r
+\r
+      FreePool (Instance);\r
+      FreePool (CachedDevicePath);\r
+      return FullDevicePath;\r
+    }\r
+  }\r
+\r
+  //\r
+  // If we get here we fail to find or HD_BOOT_DEVICE_PATH_VARIABLE_NAME not exist, and now we need\r
+  // to search all devices in the system for a matched partition\r
+  //\r
+  BdsLibConnectAllDriversToAllControllers ();\r
+  Status = gBS->LocateHandleBuffer (ByProtocol, &gEfiBlockIoProtocolGuid, NULL, &BlockIoHandleCount, &BlockIoBuffer);\r
+  if (EFI_ERROR (Status) || BlockIoHandleCount == 0 || BlockIoBuffer == NULL) {\r
+    //\r
+    // If there was an error or there are no device handles that support\r
+    // the BLOCK_IO Protocol, then return.\r
+    //\r
+    return NULL;\r
+  }\r
+  //\r
+  // Loop through all the device handles that support the BLOCK_IO Protocol\r
+  //\r
+  for (Index = 0; Index < BlockIoHandleCount; Index++) {\r
+\r
+    Status = gBS->HandleProtocol (BlockIoBuffer[Index], &gEfiDevicePathProtocolGuid, (VOID *) &BlockIoDevicePath);\r
+    if (EFI_ERROR (Status) || BlockIoDevicePath == NULL) {\r
+      continue;\r
+    }\r
+\r
+    if (MatchPartitionDevicePathNode (BlockIoDevicePath, HardDriveDevicePath)) {\r
+      //\r
+      // Find the matched partition device path\r
+      //\r
+      DevicePath    = NextDevicePathNode ((EFI_DEVICE_PATH_PROTOCOL *) HardDriveDevicePath);\r
+      FullDevicePath = AppendDevicePath (BlockIoDevicePath, DevicePath);\r
+\r
+      //\r
+      // Save the matched partition device path in HD_BOOT_DEVICE_PATH_VARIABLE_NAME variable\r
+      //\r
+      if (CachedDevicePath != NULL) {\r
+        //\r
+        // Save the matched partition device path as first instance of HD_BOOT_DEVICE_PATH_VARIABLE_NAME variable\r
+        //\r
+        if (BdsLibMatchDevicePaths (CachedDevicePath, BlockIoDevicePath)) {\r
+          TempNewDevicePath = CachedDevicePath;\r
+          CachedDevicePath = BdsLibDelPartMatchInstance (CachedDevicePath, BlockIoDevicePath);\r
+          FreePool(TempNewDevicePath);\r
+        }\r
+\r
+        if (CachedDevicePath != NULL) {\r
+          TempNewDevicePath = CachedDevicePath;\r
+          CachedDevicePath = AppendDevicePathInstance (BlockIoDevicePath, CachedDevicePath);\r
+          FreePool(TempNewDevicePath);\r
+        } else {\r
+          CachedDevicePath = DuplicateDevicePath (BlockIoDevicePath);\r
+        }\r
+\r
+        //\r
+        // Here limit the device path instance number to 12, which is max number for a system support 3 IDE controller\r
+        // If the user try to boot many OS in different HDs or partitions, in theory, \r
+        // the HD_BOOT_DEVICE_PATH_VARIABLE_NAME variable maybe become larger and larger.\r
+        //\r
+        InstanceNum = 0;\r
+        ASSERT (CachedDevicePath != NULL);\r
+        TempNewDevicePath = CachedDevicePath;\r
+        while (!IsDevicePathEnd (TempNewDevicePath)) {\r
+          TempNewDevicePath = NextDevicePathNode (TempNewDevicePath);\r
+          //\r
+          // Parse one instance\r
+          //\r
+          while (!IsDevicePathEndType (TempNewDevicePath)) {\r
+            TempNewDevicePath = NextDevicePathNode (TempNewDevicePath);\r
+          }\r
+          InstanceNum++;\r
+          //\r
+          // If the CachedDevicePath variable contain too much instance, only remain 12 instances.\r
+          //\r
+          if (InstanceNum >= 12) {\r
+            SetDevicePathEndNode (TempNewDevicePath);\r
+            break;\r
+          }\r
+        }\r
+      } else {\r
+        CachedDevicePath = DuplicateDevicePath (BlockIoDevicePath);\r
+      }\r
+\r
+      //\r
+      // Save the matching Device Path so we don't need to do a connect all next time\r
+      //\r
+      Status = gRT->SetVariable (\r
+                      HD_BOOT_DEVICE_PATH_VARIABLE_NAME,\r
+                      &gHdBootDevicePathVariablGuid,\r
+                      EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS | EFI_VARIABLE_NON_VOLATILE,\r
+                      GetDevicePathSize (CachedDevicePath),\r
+                      CachedDevicePath\r
+                      );\r
+\r
+      break;\r
+    }\r
+  }\r
+\r
+  if (CachedDevicePath != NULL) {\r
+    FreePool (CachedDevicePath);\r
+  }\r
+  if (BlockIoBuffer != NULL) {\r
+    FreePool (BlockIoBuffer);\r
+  }\r
+  return FullDevicePath;\r
+}\r
+\r
+/**\r
+  Check whether there is a instance in BlockIoDevicePath, which contain multi device path\r
+  instances, has the same partition node with HardDriveDevicePath device path\r
+\r
+  @param  BlockIoDevicePath      Multi device path instances which need to check\r
+  @param  HardDriveDevicePath    A device path which starts with a hard drive media\r
+                                 device path.\r
+\r
+  @retval TRUE                   There is a matched device path instance.\r
+  @retval FALSE                  There is no matched device path instance.\r
+\r
+**/\r
+BOOLEAN\r
+EFIAPI\r
+MatchPartitionDevicePathNode (\r
+  IN  EFI_DEVICE_PATH_PROTOCOL   *BlockIoDevicePath,\r
+  IN  HARDDRIVE_DEVICE_PATH      *HardDriveDevicePath\r
+  )\r
+{\r
+  HARDDRIVE_DEVICE_PATH     *TmpHdPath;\r
+  EFI_DEVICE_PATH_PROTOCOL  *DevicePath;\r
+  BOOLEAN                   Match;\r
+  EFI_DEVICE_PATH_PROTOCOL  *BlockIoHdDevicePathNode;\r
+\r
+  if ((BlockIoDevicePath == NULL) || (HardDriveDevicePath == NULL)) {\r
+    return FALSE;\r
+  }\r
+\r
+  //\r
+  // Make PreviousDevicePath == the device path node before the end node\r
+  //\r
+  DevicePath              = BlockIoDevicePath;\r
+  BlockIoHdDevicePathNode = NULL;\r
+\r
+  //\r
+  // find the partition device path node\r
+  //\r
+  while (!IsDevicePathEnd (DevicePath)) {\r
+    if ((DevicePathType (DevicePath) == MEDIA_DEVICE_PATH) &&\r
+        (DevicePathSubType (DevicePath) == MEDIA_HARDDRIVE_DP)\r
+        ) {\r
+      BlockIoHdDevicePathNode = DevicePath;\r
+      break;\r
+    }\r
+\r
+    DevicePath = NextDevicePathNode (DevicePath);\r
+  }\r
+\r
+  if (BlockIoHdDevicePathNode == NULL) {\r
+    return FALSE;\r
+  }\r
+  //\r
+  // See if the harddrive device path in blockio matches the orig Hard Drive Node\r
+  //\r
+  TmpHdPath = (HARDDRIVE_DEVICE_PATH *) BlockIoHdDevicePathNode;\r
+  Match = FALSE;\r
+\r
+  //\r
+  // Check for the match\r
+  //\r
+  if ((TmpHdPath->MBRType == HardDriveDevicePath->MBRType) &&\r
+      (TmpHdPath->SignatureType == HardDriveDevicePath->SignatureType)) {\r
+    switch (TmpHdPath->SignatureType) {\r
+    case SIGNATURE_TYPE_GUID:\r
+      Match = CompareGuid ((EFI_GUID *)TmpHdPath->Signature, (EFI_GUID *)HardDriveDevicePath->Signature);\r
+      break;\r
+    case SIGNATURE_TYPE_MBR:\r
+      Match = (BOOLEAN)(*((UINT32 *)(&(TmpHdPath->Signature[0]))) == ReadUnaligned32((UINT32 *)(&(HardDriveDevicePath->Signature[0]))));\r
+      break;\r
+    default:\r
+      Match = FALSE;\r
+      break;\r
+    }\r
+  }\r
+\r
+  return Match;\r
+}\r
+\r
+/**\r
+  Delete the boot option associated with the handle passed in.\r
+\r
+  @param  Handle                 The handle which present the device path to create\r
+                                 boot option\r
+\r
+  @retval EFI_SUCCESS            Delete the boot option success\r
+  @retval EFI_NOT_FOUND          If the Device Path is not found in the system\r
+  @retval EFI_OUT_OF_RESOURCES   Lack of memory resource\r
+  @retval Other                  Error return value from SetVariable()\r
+\r
+**/\r
+EFI_STATUS\r
+BdsLibDeleteOptionFromHandle (\r
+  IN  EFI_HANDLE                 Handle\r
+  )\r
+{\r
+  UINT16                    *BootOrder;\r
+  UINT8                     *BootOptionVar;\r
+  UINTN                     BootOrderSize;\r
+  UINTN                     BootOptionSize;\r
+  EFI_STATUS                Status;\r
+  UINTN                     Index;\r
+  UINT16                    BootOption[BOOT_OPTION_MAX_CHAR];\r
+  UINTN                     DevicePathSize;\r
+  UINTN                     OptionDevicePathSize;\r
+  EFI_DEVICE_PATH_PROTOCOL  *DevicePath;\r
+  EFI_DEVICE_PATH_PROTOCOL  *OptionDevicePath;\r
+  UINT8                     *TempPtr;\r
+\r
+  Status        = EFI_SUCCESS;\r
+  BootOrder     = NULL;\r
+  BootOrderSize = 0;\r
+\r
+  //\r
+  // Check "BootOrder" variable, if no, means there is no any boot order.\r
+  //\r
+  BootOrder = BdsLibGetVariableAndSize (\r
+                L"BootOrder",\r
+                &gEfiGlobalVariableGuid,\r
+                &BootOrderSize\r
+                );\r
+  if (BootOrder == NULL) {\r
+    return EFI_NOT_FOUND;\r
+  }\r
+\r
+  //\r
+  // Convert device handle to device path protocol instance\r
+  //\r
+  DevicePath = DevicePathFromHandle (Handle);\r
+  if (DevicePath == NULL) {\r
+    return EFI_NOT_FOUND;\r
+  }\r
+  DevicePathSize = GetDevicePathSize (DevicePath);\r
+\r
+  //\r
+  // Loop all boot order variable and find the matching device path\r
+  //\r
+  Index = 0;\r
+  while (Index < BootOrderSize / sizeof (UINT16)) {\r
+    UnicodeSPrint (BootOption, sizeof (BootOption), L"Boot%04x", BootOrder[Index]);\r
+    BootOptionVar = BdsLibGetVariableAndSize (\r
+                      BootOption,\r
+                      &gEfiGlobalVariableGuid,\r
+                      &BootOptionSize\r
+                      );\r
+\r
+    if (BootOptionVar == NULL) {\r
+      FreePool (BootOrder);\r
+      return EFI_OUT_OF_RESOURCES;\r
+    }\r
+\r
+    if (!ValidateOption(BootOptionVar, BootOptionSize)) {\r
+      BdsDeleteBootOption (BootOrder[Index], BootOrder, &BootOrderSize);\r
+      FreePool (BootOptionVar);\r
+      Index++;\r
+      continue;\r
+    }\r
+\r
+    TempPtr = BootOptionVar;\r
+    TempPtr += sizeof (UINT32) + sizeof (UINT16);\r
+    TempPtr += StrSize ((CHAR16 *) TempPtr);\r
+    OptionDevicePath = (EFI_DEVICE_PATH_PROTOCOL *) TempPtr;\r
+    OptionDevicePathSize = GetDevicePathSize (OptionDevicePath);\r
+\r
+    //\r
+    // Check whether the device path match\r
+    //\r
+    if ((OptionDevicePathSize == DevicePathSize) &&\r
+        (CompareMem (DevicePath, OptionDevicePath, DevicePathSize) == 0)) {\r
+      BdsDeleteBootOption (BootOrder[Index], BootOrder, &BootOrderSize);\r
+      FreePool (BootOptionVar);\r
+      break;\r
+    }\r
+\r
+    FreePool (BootOptionVar);\r
+    Index++;\r
+  }\r
+\r
+  //\r
+  // Adjust number of boot option for "BootOrder" variable.\r
+  //\r
+  Status = gRT->SetVariable (\r
+                  L"BootOrder",\r
+                  &gEfiGlobalVariableGuid,\r
+                  EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS | EFI_VARIABLE_NON_VOLATILE,\r
+                  BootOrderSize,\r
+                  BootOrder\r
+                  );\r
+\r
+  FreePool (BootOrder);\r
+\r
+  return Status;\r
+}\r
+\r
+\r
+/**\r
+  Delete all invalid EFI boot options.\r
+\r
+  @retval EFI_SUCCESS            Delete all invalid boot option success\r
+  @retval EFI_NOT_FOUND          Variable "BootOrder" is not found\r
+  @retval EFI_OUT_OF_RESOURCES   Lack of memory resource\r
+  @retval Other                  Error return value from SetVariable()\r
+\r
+**/\r
+EFI_STATUS\r
+BdsDeleteAllInvalidEfiBootOption (\r
+  VOID\r
+  )\r
+{\r
+  UINT16                    *BootOrder;\r
+  UINT8                     *BootOptionVar;\r
+  UINTN                     BootOrderSize;\r
+  UINTN                     BootOptionSize;\r
+  EFI_STATUS                Status;\r
+  UINTN                     Index;\r
+  UINTN                     Index2;\r
+  UINT16                    BootOption[BOOT_OPTION_MAX_CHAR];\r
+  EFI_DEVICE_PATH_PROTOCOL  *OptionDevicePath;\r
+  UINT8                     *TempPtr;\r
+  CHAR16                    *Description;\r
+  BOOLEAN                   Corrupted;\r
+\r
+  Status           = EFI_SUCCESS;\r
+  BootOrder        = NULL;\r
+  Description      = NULL;\r
+  OptionDevicePath = NULL;\r
+  BootOrderSize    = 0;\r
+  Corrupted        = FALSE;\r
+\r
+  //\r
+  // Check "BootOrder" variable firstly, this variable hold the number of boot options\r
+  //\r
+  BootOrder = BdsLibGetVariableAndSize (\r
+                L"BootOrder",\r
+                &gEfiGlobalVariableGuid,\r
+                &BootOrderSize\r
+                );\r
+  if (NULL == BootOrder) {\r
+    return EFI_NOT_FOUND;\r
+  }\r
+\r
+  Index = 0;\r
+  while (Index < BootOrderSize / sizeof (UINT16)) {\r
+    UnicodeSPrint (BootOption, sizeof (BootOption), L"Boot%04x", BootOrder[Index]);\r
+    BootOptionVar = BdsLibGetVariableAndSize (\r
+                      BootOption,\r
+                      &gEfiGlobalVariableGuid,\r
+                      &BootOptionSize\r
+                      );\r
+    if (NULL == BootOptionVar) {\r
+      FreePool (BootOrder);\r
+      return EFI_OUT_OF_RESOURCES;\r
+    }\r
+\r
+    if (!ValidateOption(BootOptionVar, BootOptionSize)) {\r
+      Corrupted = TRUE;\r
+    } else {\r
+      TempPtr = BootOptionVar;\r
+      TempPtr += sizeof (UINT32) + sizeof (UINT16);\r
+      Description = (CHAR16 *) TempPtr;\r
+      TempPtr += StrSize ((CHAR16 *) TempPtr);\r
+      OptionDevicePath = (EFI_DEVICE_PATH_PROTOCOL *) TempPtr;\r
+\r
+      //\r
+      // Skip legacy boot option (BBS boot device)\r
+      //\r
+      if ((DevicePathType (OptionDevicePath) == BBS_DEVICE_PATH) &&\r
+          (DevicePathSubType (OptionDevicePath) == BBS_BBS_DP)) {\r
+        FreePool (BootOptionVar);\r
+        Index++;\r
+        continue;\r
+      }\r
+    }\r
+\r
+    if (Corrupted || !BdsLibIsValidEFIBootOptDevicePathExt (OptionDevicePath, FALSE, Description)) {\r
+      //\r
+      // Delete this invalid boot option "Boot####"\r
+      //\r
+      Status = gRT->SetVariable (\r
+                      BootOption,\r
+                      &gEfiGlobalVariableGuid,\r
+                      EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS | EFI_VARIABLE_NON_VOLATILE,\r
+                      0,\r
+                      NULL\r
+                      );\r
+      //\r
+      // Mark this boot option in boot order as deleted\r
+      //\r
+      BootOrder[Index] = 0xffff;\r
+      Corrupted        = FALSE;\r
+    }\r
+\r
+    FreePool (BootOptionVar);\r
+    Index++;\r
+  }\r
+\r
+  //\r
+  // Adjust boot order array\r
+  //\r
+  Index2 = 0;\r
+  for (Index = 0; Index < BootOrderSize / sizeof (UINT16); Index++) {\r
+    if (BootOrder[Index] != 0xffff) {\r
+      BootOrder[Index2] = BootOrder[Index];\r
+      Index2 ++;\r
+    }\r
+  }\r
+  Status = gRT->SetVariable (\r
+                  L"BootOrder",\r
+                  &gEfiGlobalVariableGuid,\r
+                  EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS | EFI_VARIABLE_NON_VOLATILE,\r
+                  Index2 * sizeof (UINT16),\r
+                  BootOrder\r
+                  );\r
+\r
+  FreePool (BootOrder);\r
+\r
+  return Status;\r
+}\r
+\r
+\r
+/**\r
+  For EFI boot option, BDS separate them as six types:\r
+  1. Network - The boot option points to the SimpleNetworkProtocol device.\r
+               Bds will try to automatically create this type boot option when enumerate.\r
+  2. Shell   - The boot option points to internal flash shell.\r
+               Bds will try to automatically create this type boot option when enumerate.\r
+  3. Removable BlockIo      - The boot option only points to the removable media\r
+                              device, like USB flash disk, DVD, Floppy etc.\r
+                              These device should contain a *removable* blockIo\r
+                              protocol in their device handle.\r
+                              Bds will try to automatically create this type boot option\r
+                              when enumerate.\r
+  4. Fixed BlockIo          - The boot option only points to a Fixed blockIo device,\r
+                              like HardDisk.\r
+                              These device should contain a *fixed* blockIo\r
+                              protocol in their device handle.\r
+                              BDS will skip fixed blockIo devices, and NOT\r
+                              automatically create boot option for them. But BDS\r
+                              will help to delete those fixed blockIo boot option,\r
+                              whose description rule conflict with other auto-created\r
+                              boot options.\r
+  5. Non-BlockIo Simplefile - The boot option points to a device whose handle\r
+                              has SimpleFileSystem Protocol, but has no blockio\r
+                              protocol. These devices do not offer blockIo\r
+                              protocol, but BDS still can get the\r
+                              \EFI\BOOT\boot{machinename}.EFI by SimpleFileSystem\r
+                              Protocol.\r
+  6. File    - The boot option points to a file. These boot options are usually\r
+               created by user manually or OS loader. BDS will not delete or modify\r
+               these boot options.\r
+\r
+  This function will enumerate all possible boot device in the system, and\r
+  automatically create boot options for Network, Shell, Removable BlockIo,\r
+  and Non-BlockIo Simplefile devices.\r
+  It will only execute once of every boot.\r
+\r
+  @param  BdsBootOptionList      The header of the link list which indexed all\r
+                                 current boot options\r
+\r
+  @retval EFI_SUCCESS            Finished all the boot device enumerate and create\r
+                                 the boot option base on that boot device\r
+\r
+  @retval EFI_OUT_OF_RESOURCES   Failed to enumerate the boot device and create the boot option list\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+BdsLibEnumerateAllBootOption (\r
+  IN OUT LIST_ENTRY          *BdsBootOptionList\r
+  )\r
+{\r
+  EFI_STATUS                    Status;\r
+  UINT16                        FloppyNumber;\r
+  UINT16                        HarddriveNumber;\r
+  UINT16                        CdromNumber;\r
+  UINT16                        UsbNumber;\r
+  UINT16                        MiscNumber;\r
+  UINT16                        ScsiNumber;\r
+  UINT16                        NonBlockNumber;\r
+  UINTN                         NumberBlockIoHandles;\r
+  EFI_HANDLE                    *BlockIoHandles;\r
+  EFI_BLOCK_IO_PROTOCOL         *BlkIo;\r
+  BOOLEAN                       Removable[2];\r
+  UINTN                         RemovableIndex;\r
+  UINTN                         Index;\r
+  UINTN                         NumOfLoadFileHandles;\r
+  EFI_HANDLE                    *LoadFileHandles;\r
+  UINTN                         FvHandleCount;\r
+  EFI_HANDLE                    *FvHandleBuffer;\r
+  EFI_FV_FILETYPE               Type;\r
+  UINTN                         Size;\r
+  EFI_FV_FILE_ATTRIBUTES        Attributes;\r
+  UINT32                        AuthenticationStatus;\r
+  EFI_FIRMWARE_VOLUME2_PROTOCOL *Fv;\r
+  EFI_DEVICE_PATH_PROTOCOL      *DevicePath;\r
+  UINTN                         DevicePathType;\r
+  CHAR16                        Buffer[40];\r
+  EFI_HANDLE                    *FileSystemHandles;\r
+  UINTN                         NumberFileSystemHandles;\r
+  BOOLEAN                       NeedDelete;\r
+  EFI_IMAGE_DOS_HEADER          DosHeader;\r
+  CHAR8                         *PlatLang;\r
+  CHAR8                         *LastLang;\r
+  EFI_IMAGE_OPTIONAL_HEADER_UNION       HdrData;\r
+  EFI_IMAGE_OPTIONAL_HEADER_PTR_UNION   Hdr;\r
+\r
+  FloppyNumber    = 0;\r
+  HarddriveNumber = 0;\r
+  CdromNumber     = 0;\r
+  UsbNumber       = 0;\r
+  MiscNumber      = 0;\r
+  ScsiNumber      = 0;\r
+  PlatLang        = NULL;\r
+  LastLang        = NULL;\r
+  ZeroMem (Buffer, sizeof (Buffer));\r
+\r
+  //\r
+  // If the boot device enumerate happened, just get the boot\r
+  // device from the boot order variable\r
+  //\r
+  if (mEnumBootDevice) {\r
+    GetVariable2 (LAST_ENUM_LANGUAGE_VARIABLE_NAME, &gLastEnumLangGuid, (VOID**)&LastLang, NULL);\r
+    GetEfiGlobalVariable2 (L"PlatformLang", (VOID**)&PlatLang, NULL);\r
+    ASSERT (PlatLang != NULL);\r
+    if ((LastLang != NULL) && (AsciiStrCmp (LastLang, PlatLang) == 0)) {\r
+      Status = BdsLibBuildOptionFromVar (BdsBootOptionList, L"BootOrder");\r
+      FreePool (LastLang);\r
+      FreePool (PlatLang);\r
+      return Status;\r
+    } else {\r
+      Status = gRT->SetVariable (\r
+        LAST_ENUM_LANGUAGE_VARIABLE_NAME,\r
+        &gLastEnumLangGuid,\r
+        EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_NON_VOLATILE,\r
+        AsciiStrSize (PlatLang),\r
+        PlatLang\r
+        );\r
+      ASSERT_EFI_ERROR (Status);\r
+\r
+      if (LastLang != NULL) {\r
+        FreePool (LastLang);\r
+      }\r
+      FreePool (PlatLang);\r
+    }\r
+  }\r
+\r
+  //\r
+  // Notes: this dirty code is to get the legacy boot option from the\r
+  // BBS table and create to variable as the EFI boot option, it should\r
+  // be removed after the CSM can provide legacy boot option directly\r
+  //\r
+  REFRESH_LEGACY_BOOT_OPTIONS;\r
+\r
+  //\r
+  // Delete invalid boot option\r
+  //\r
+  BdsDeleteAllInvalidEfiBootOption ();\r
+\r
+  //\r
+  // Parse removable media followed by fixed media.\r
+  // The Removable[] array is used by the for-loop below to create removable media boot options \r
+  // at first, and then to create fixed media boot options.\r
+  //\r
+  Removable[0]  = FALSE;\r
+  Removable[1]  = TRUE;\r
+\r
+  gBS->LocateHandleBuffer (\r
+        ByProtocol,\r
+        &gEfiBlockIoProtocolGuid,\r
+        NULL,\r
+        &NumberBlockIoHandles,\r
+        &BlockIoHandles\r
+        );\r
+\r
+  for (RemovableIndex = 0; RemovableIndex < 2; RemovableIndex++) {\r
+    for (Index = 0; Index < NumberBlockIoHandles; Index++) {\r
+      Status = gBS->HandleProtocol (\r
+                      BlockIoHandles[Index],\r
+                      &gEfiBlockIoProtocolGuid,\r
+                      (VOID **) &BlkIo\r
+                      );\r
+      //\r
+      // skip the fixed block io then the removable block io\r
+      //\r
+      if (EFI_ERROR (Status) || (BlkIo->Media->RemovableMedia == Removable[RemovableIndex])) {\r
+        continue;\r
+      }\r
+      DevicePath  = DevicePathFromHandle (BlockIoHandles[Index]);\r
+      DevicePathType = BdsGetBootTypeFromDevicePath (DevicePath);\r
+\r
+      switch (DevicePathType) {\r
+      case BDS_EFI_ACPI_FLOPPY_BOOT:\r
+        if (FloppyNumber != 0) {\r
+          UnicodeSPrint (Buffer, sizeof (Buffer), L"%s %d", BdsLibGetStringById (STRING_TOKEN (STR_DESCRIPTION_FLOPPY)), FloppyNumber);\r
+        } else {\r
+          UnicodeSPrint (Buffer, sizeof (Buffer), L"%s", BdsLibGetStringById (STRING_TOKEN (STR_DESCRIPTION_FLOPPY)));\r
+        }\r
+        BdsLibBuildOptionFromHandle (BlockIoHandles[Index], BdsBootOptionList, Buffer);\r
+        FloppyNumber++;\r
+        break;\r
+\r
+      //\r
+      // Assume a removable SATA device should be the DVD/CD device, a fixed SATA device should be the Hard Drive device.\r
+      //\r
+      case BDS_EFI_MESSAGE_ATAPI_BOOT:\r
+      case BDS_EFI_MESSAGE_SATA_BOOT:\r
+        if (BlkIo->Media->RemovableMedia) {\r
+          if (CdromNumber != 0) {\r
+            UnicodeSPrint (Buffer, sizeof (Buffer), L"%s %d", BdsLibGetStringById (STRING_TOKEN (STR_DESCRIPTION_CD_DVD)), CdromNumber);\r
+          } else {\r
+            UnicodeSPrint (Buffer, sizeof (Buffer), L"%s", BdsLibGetStringById (STRING_TOKEN (STR_DESCRIPTION_CD_DVD)));\r
+          }\r
+          CdromNumber++;\r
+        } else {\r
+          if (HarddriveNumber != 0) {\r
+            UnicodeSPrint (Buffer, sizeof (Buffer), L"%s %d", BdsLibGetStringById (STRING_TOKEN (STR_DESCRIPTION_HARDDRIVE)), HarddriveNumber);\r
+          } else {\r
+            UnicodeSPrint (Buffer, sizeof (Buffer), L"%s", BdsLibGetStringById (STRING_TOKEN (STR_DESCRIPTION_HARDDRIVE)));\r
+          }\r
+          HarddriveNumber++;\r
+        }\r
+        DEBUG ((DEBUG_INFO | DEBUG_LOAD, "Buffer: %S\n", Buffer));\r
+        BdsLibBuildOptionFromHandle (BlockIoHandles[Index], BdsBootOptionList, Buffer);\r
+        break;\r
+\r
+      case BDS_EFI_MESSAGE_USB_DEVICE_BOOT:\r
+        if (UsbNumber != 0) {\r
+          UnicodeSPrint (Buffer, sizeof (Buffer), L"%s %d", BdsLibGetStringById (STRING_TOKEN (STR_DESCRIPTION_USB)), UsbNumber);\r
+        } else {\r
+          UnicodeSPrint (Buffer, sizeof (Buffer), L"%s", BdsLibGetStringById (STRING_TOKEN (STR_DESCRIPTION_USB)));\r
+        }\r
+        BdsLibBuildOptionFromHandle (BlockIoHandles[Index], BdsBootOptionList, Buffer);\r
+        UsbNumber++;\r
+        break;\r
+\r
+      case BDS_EFI_MESSAGE_SCSI_BOOT:\r
+        if (ScsiNumber != 0) {\r
+          UnicodeSPrint (Buffer, sizeof (Buffer), L"%s %d", BdsLibGetStringById (STRING_TOKEN (STR_DESCRIPTION_SCSI)), ScsiNumber);\r
+        } else {\r
+          UnicodeSPrint (Buffer, sizeof (Buffer), L"%s", BdsLibGetStringById (STRING_TOKEN (STR_DESCRIPTION_SCSI)));\r
+        }\r
+        BdsLibBuildOptionFromHandle (BlockIoHandles[Index], BdsBootOptionList, Buffer);\r
+        ScsiNumber++;\r
+        break;\r
+\r
+      case BDS_EFI_MESSAGE_MISC_BOOT:\r
+        if (MiscNumber != 0) {\r
+          UnicodeSPrint (Buffer, sizeof (Buffer), L"%s %d", BdsLibGetStringById (STRING_TOKEN (STR_DESCRIPTION_MISC)), MiscNumber);\r
+        } else {\r
+          UnicodeSPrint (Buffer, sizeof (Buffer), L"%s", BdsLibGetStringById (STRING_TOKEN (STR_DESCRIPTION_MISC)));\r
+        }\r
+        BdsLibBuildOptionFromHandle (BlockIoHandles[Index], BdsBootOptionList, Buffer);\r
+        MiscNumber++;\r
+        break;\r
+\r
+      default:\r
+        break;\r
+      }\r
+    }\r
+  }\r
+\r
+  if (NumberBlockIoHandles != 0) {\r
+    FreePool (BlockIoHandles);\r
+  }\r
+\r
+  //\r
+  // If there is simple file protocol which does not consume block Io protocol, create a boot option for it here.\r
+  //\r
+  NonBlockNumber = 0;\r
+  gBS->LocateHandleBuffer (\r
+        ByProtocol,\r
+        &gEfiSimpleFileSystemProtocolGuid,\r
+        NULL,\r
+        &NumberFileSystemHandles,\r
+        &FileSystemHandles\r
+        );\r
+  for (Index = 0; Index < NumberFileSystemHandles; Index++) {\r
+    Status = gBS->HandleProtocol (\r
+                    FileSystemHandles[Index],\r
+                    &gEfiBlockIoProtocolGuid,\r
+                    (VOID **) &BlkIo\r
+                    );\r
+     if (!EFI_ERROR (Status)) {\r
+      //\r
+      //  Skip if the file system handle supports a BlkIo protocol,\r
+      //\r
+      continue;\r
+    }\r
+\r
+    //\r
+    // Do the removable Media thing. \EFI\BOOT\boot{machinename}.EFI\r
+    //  machinename is ia32, ia64, x64, ...\r
+    //\r
+    Hdr.Union  = &HdrData;\r
+    NeedDelete = TRUE;\r
+    Status     = BdsLibGetImageHeader (\r
+                   FileSystemHandles[Index],\r
+                   EFI_REMOVABLE_MEDIA_FILE_NAME,\r
+                   &DosHeader,\r
+                   Hdr\r
+                   );\r
+    if (!EFI_ERROR (Status) &&\r
+        EFI_IMAGE_MACHINE_TYPE_SUPPORTED (Hdr.Pe32->FileHeader.Machine) &&\r
+        Hdr.Pe32->OptionalHeader.Subsystem == EFI_IMAGE_SUBSYSTEM_EFI_APPLICATION) {\r
+      NeedDelete = FALSE;\r
+    }\r
+\r
+    if (NeedDelete) {\r
+      //\r
+      // No such file or the file is not a EFI application, delete this boot option\r
+      //\r
+      BdsLibDeleteOptionFromHandle (FileSystemHandles[Index]);\r
+    } else {\r
+      if (NonBlockNumber != 0) {\r
+        UnicodeSPrint (Buffer, sizeof (Buffer), L"%s %d", BdsLibGetStringById (STRING_TOKEN (STR_DESCRIPTION_NON_BLOCK)), NonBlockNumber);\r
+      } else {\r
+        UnicodeSPrint (Buffer, sizeof (Buffer), L"%s", BdsLibGetStringById (STRING_TOKEN (STR_DESCRIPTION_NON_BLOCK)));\r
+      }\r
+      BdsLibBuildOptionFromHandle (FileSystemHandles[Index], BdsBootOptionList, Buffer);\r
+      NonBlockNumber++;\r
+    }\r
+  }\r
+\r
+  if (NumberFileSystemHandles != 0) {\r
+    FreePool (FileSystemHandles);\r
+  }\r
+\r
+  //\r
+  // Parse Network Boot Device\r
+  //\r
+  NumOfLoadFileHandles = 0;\r
+  //\r
+  // Search Load File protocol for PXE boot option.\r
+  //\r
+  gBS->LocateHandleBuffer (\r
+        ByProtocol,\r
+        &gEfiLoadFileProtocolGuid,\r
+        NULL,\r
+        &NumOfLoadFileHandles,\r
+        &LoadFileHandles\r
+        );\r
+\r
+  for (Index = 0; Index < NumOfLoadFileHandles; Index++) {\r
+    if (Index != 0) {\r
+      UnicodeSPrint (Buffer, sizeof (Buffer), L"%s%d", BdsLibGetStringById (STRING_TOKEN (STR_DESCRIPTION_NETWORK)), 6);\r
+    } else {\r
+      UnicodeSPrint (Buffer, sizeof (Buffer), L"%s%d", BdsLibGetStringById (STRING_TOKEN (STR_DESCRIPTION_NETWORK)), 4);\r
+    }\r
+    BdsLibBuildOptionFromHandle (LoadFileHandles[Index], BdsBootOptionList, Buffer);\r
+  }\r
+\r
+  if (NumOfLoadFileHandles != 0) {\r
+    FreePool (LoadFileHandles);\r
+  }\r
+\r
+  //\r
+  // Check if we have on flash shell\r
+  //\r
+  gBS->LocateHandleBuffer (\r
+        ByProtocol,\r
+        &gEfiFirmwareVolume2ProtocolGuid,\r
+        NULL,\r
+        &FvHandleCount,\r
+        &FvHandleBuffer\r
+        );\r
+  for (Index = 0; Index < FvHandleCount; Index++) {\r
+    gBS->HandleProtocol (\r
+          FvHandleBuffer[Index],\r
+          &gEfiFirmwareVolume2ProtocolGuid,\r
+          (VOID **) &Fv\r
+          );\r
+\r
+    Status = Fv->ReadFile (\r
+                  Fv,\r
+                  PcdGetPtr(PcdShellFile),\r
+                  NULL,\r
+                  &Size,\r
+                  &Type,\r
+                  &Attributes,\r
+                  &AuthenticationStatus\r
+                  );\r
+    if (EFI_ERROR (Status)) {\r
+      //\r
+      // Skip if no shell file in the FV\r
+      //\r
+      continue;\r
+    }\r
+    //\r
+    // Build the shell boot option\r
+    //\r
+    BdsLibBuildOptionFromShell (FvHandleBuffer[Index], BdsBootOptionList);\r
+  }\r
+\r
+  if (FvHandleCount != 0) {\r
+    FreePool (FvHandleBuffer);\r
+  }\r
+  //\r
+  // Make sure every boot only have one time\r
+  // boot device enumerate\r
+  //\r
+  Status = BdsLibBuildOptionFromVar (BdsBootOptionList, L"BootOrder");\r
+  mEnumBootDevice = TRUE;\r
+\r
+  return Status;\r
+}\r
+\r
+/**\r
+  Build the boot option with the handle parsed in\r
+\r
+  @param  Handle                 The handle which present the device path to create\r
+                                 boot option\r
+  @param  BdsBootOptionList      The header of the link list which indexed all\r
+                                 current boot options\r
+  @param  String                 The description of the boot option.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+BdsLibBuildOptionFromHandle (\r
+  IN  EFI_HANDLE                 Handle,\r
+  IN  LIST_ENTRY                 *BdsBootOptionList,\r
+  IN  CHAR16                     *String\r
+  )\r
+{\r
+  EFI_DEVICE_PATH_PROTOCOL  *DevicePath;\r
+\r
+  DevicePath = DevicePathFromHandle (Handle);\r
+\r
+  //\r
+  // Create and register new boot option\r
+  //\r
+  BdsLibRegisterNewOption (BdsBootOptionList, DevicePath, String, L"BootOrder");\r
+}\r
+\r
+\r
+/**\r
+  Build the on flash shell boot option with the handle parsed in.\r
+\r
+  @param  Handle                 The handle which present the device path to create\r
+                                 on flash shell boot option\r
+  @param  BdsBootOptionList      The header of the link list which indexed all\r
+                                 current boot options\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+BdsLibBuildOptionFromShell (\r
+  IN EFI_HANDLE                  Handle,\r
+  IN OUT LIST_ENTRY              *BdsBootOptionList\r
+  )\r
+{\r
+  EFI_DEVICE_PATH_PROTOCOL          *DevicePath;\r
+  MEDIA_FW_VOL_FILEPATH_DEVICE_PATH ShellNode;\r
+\r
+  DevicePath = DevicePathFromHandle (Handle);\r
+\r
+  //\r
+  // Build the shell device path\r
+  //\r
+  EfiInitializeFwVolDevicepathNode (&ShellNode, PcdGetPtr(PcdShellFile));\r
+\r
+  DevicePath = AppendDevicePathNode (DevicePath, (EFI_DEVICE_PATH_PROTOCOL *) &ShellNode);\r
+\r
+  //\r
+  // Create and register the shell boot option\r
+  //\r
+  BdsLibRegisterNewOption (BdsBootOptionList, DevicePath, L"EFI Internal Shell", L"BootOrder");\r
+\r
+}\r
+\r
+/**\r
+  Boot from the UEFI spec defined "BootNext" variable.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+BdsLibBootNext (\r
+  VOID\r
+  )\r
+{\r
+  UINT16            *BootNext;\r
+  UINTN             BootNextSize;\r
+  CHAR16            Buffer[20];\r
+  BDS_COMMON_OPTION *BootOption;\r
+  LIST_ENTRY        TempList;\r
+  UINTN             ExitDataSize;\r
+  CHAR16            *ExitData;\r
+\r
+  //\r
+  // Init the boot option name buffer and temp link list\r
+  //\r
+  InitializeListHead (&TempList);\r
+  ZeroMem (Buffer, sizeof (Buffer));\r
+\r
+  BootNext = BdsLibGetVariableAndSize (\r
+              L"BootNext",\r
+              &gEfiGlobalVariableGuid,\r
+              &BootNextSize\r
+              );\r
+\r
+  //\r
+  // Clear the boot next variable first\r
+  //\r
+  if (BootNext != NULL) {\r
+    gRT->SetVariable (\r
+          L"BootNext",\r
+          &gEfiGlobalVariableGuid,\r
+          EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS | EFI_VARIABLE_NON_VOLATILE,\r
+          0,\r
+          BootNext\r
+          );\r
+\r
+    //\r
+    // Start to build the boot option and try to boot\r
+    //\r
+    UnicodeSPrint (Buffer, sizeof (Buffer), L"Boot%04x", *BootNext);\r
+    BootOption = BdsLibVariableToOption (&TempList, Buffer);\r
+    ASSERT (BootOption != NULL);\r
+    BdsLibConnectDevicePath (BootOption->DevicePath);\r
+    BdsLibBootViaBootOption (BootOption, BootOption->DevicePath, &ExitDataSize, &ExitData);\r
+  }\r
+\r
+}\r
+\r
+/**\r
+  Return the bootable media handle.\r
+  First, check the device is connected\r
+  Second, check whether the device path point to a device which support SimpleFileSystemProtocol,\r
+  Third, detect the the default boot file in the Media, and return the removable Media handle.\r
+\r
+  @param  DevicePath  Device Path to a  bootable device\r
+\r
+  @return  The bootable media handle. If the media on the DevicePath is not bootable, NULL will return.\r
+\r
+**/\r
+EFI_HANDLE\r
+EFIAPI\r
+BdsLibGetBootableHandle (\r
+  IN  EFI_DEVICE_PATH_PROTOCOL      *DevicePath\r
+  )\r
+{\r
+  EFI_STATUS                      Status;\r
+  EFI_TPL                         OldTpl;\r
+  EFI_DEVICE_PATH_PROTOCOL        *UpdatedDevicePath;\r
+  EFI_DEVICE_PATH_PROTOCOL        *DupDevicePath;\r
+  EFI_HANDLE                      Handle;\r
+  EFI_BLOCK_IO_PROTOCOL           *BlockIo;\r
+  VOID                            *Buffer;\r
+  EFI_DEVICE_PATH_PROTOCOL        *TempDevicePath;\r
+  UINTN                           Size;\r
+  UINTN                           TempSize;\r
+  EFI_HANDLE                      ReturnHandle;\r
+  EFI_HANDLE                      *SimpleFileSystemHandles;\r
+\r
+  UINTN                           NumberSimpleFileSystemHandles;\r
+  UINTN                           Index;\r
+  EFI_IMAGE_DOS_HEADER            DosHeader;\r
+  EFI_IMAGE_OPTIONAL_HEADER_UNION       HdrData;\r
+  EFI_IMAGE_OPTIONAL_HEADER_PTR_UNION   Hdr;\r
+\r
+  UpdatedDevicePath = DevicePath;\r
+\r
+  //\r
+  // Enter to critical section to protect the acquired BlockIo instance \r
+  // from getting released due to the USB mass storage hotplug event\r
+  //\r
+  OldTpl = gBS->RaiseTPL (TPL_CALLBACK);\r
+\r
+  //\r
+  // Check whether the device is connected\r
+  //\r
+  Status = gBS->LocateDevicePath (&gEfiBlockIoProtocolGuid, &UpdatedDevicePath, &Handle);\r
+  if (EFI_ERROR (Status)) {\r
+    //\r
+    // Skip the case that the boot option point to a simple file protocol which does not consume block Io protocol,\r
+    //\r
+    Status = gBS->LocateDevicePath (&gEfiSimpleFileSystemProtocolGuid, &UpdatedDevicePath, &Handle);\r
+    if (EFI_ERROR (Status)) {\r
+      //\r
+      // Fail to find the proper BlockIo and simple file protocol, maybe because device not present,  we need to connect it firstly\r
+      //\r
+      UpdatedDevicePath = DevicePath;\r
+      Status            = gBS->LocateDevicePath (&gEfiDevicePathProtocolGuid, &UpdatedDevicePath, &Handle);\r
+      gBS->ConnectController (Handle, NULL, NULL, TRUE);\r
+    }\r
+  } else {\r
+    //\r
+    // For removable device boot option, its contained device path only point to the removable device handle, \r
+    // should make sure all its children handles (its child partion or media handles) are created and connected. \r
+    //\r
+    gBS->ConnectController (Handle, NULL, NULL, TRUE); \r
+    //\r
+    // Get BlockIo protocol and check removable attribute\r
+    //\r
+    Status = gBS->HandleProtocol (Handle, &gEfiBlockIoProtocolGuid, (VOID **)&BlockIo);\r
+    ASSERT_EFI_ERROR (Status);\r
+\r
+    //\r
+    // Issue a dummy read to the device to check for media change.\r
+    // When the removable media is changed, any Block IO read/write will\r
+    // cause the BlockIo protocol be reinstalled and EFI_MEDIA_CHANGED is\r
+    // returned. After the Block IO protocol is reinstalled, subsequent\r
+    // Block IO read/write will success.\r
+    //\r
+    Buffer = AllocatePool (BlockIo->Media->BlockSize);\r
+    if (Buffer != NULL) {\r
+      BlockIo->ReadBlocks (\r
+               BlockIo,\r
+               BlockIo->Media->MediaId,\r
+               0,\r
+               BlockIo->Media->BlockSize,\r
+               Buffer\r
+               );\r
+      FreePool(Buffer);\r
+    }\r
+  }\r
+\r
+  //\r
+  // Detect the the default boot file from removable Media\r
+  //\r
+\r
+  //\r
+  // If fail to get bootable handle specified by a USB boot option, the BDS should try to find other bootable device in the same USB bus\r
+  // Try to locate the USB node device path first, if fail then use its previous PCI node to search\r
+  //\r
+  DupDevicePath = DuplicateDevicePath (DevicePath);\r
+  ASSERT (DupDevicePath != NULL);\r
+\r
+  UpdatedDevicePath = DupDevicePath;\r
+  Status = gBS->LocateDevicePath (&gEfiDevicePathProtocolGuid, &UpdatedDevicePath, &Handle);\r
+  //\r
+  // if the resulting device path point to a usb node, and the usb node is a dummy node, should only let device path only point to the previous Pci node\r
+  // Acpi()/Pci()/Usb() --> Acpi()/Pci()\r
+  //\r
+  if ((DevicePathType (UpdatedDevicePath) == MESSAGING_DEVICE_PATH) &&\r
+      (DevicePathSubType (UpdatedDevicePath) == MSG_USB_DP)) {\r
+    //\r
+    // Remove the usb node, let the device path only point to PCI node\r
+    //\r
+    SetDevicePathEndNode (UpdatedDevicePath);\r
+    UpdatedDevicePath = DupDevicePath;\r
+  } else {\r
+    UpdatedDevicePath = DevicePath;\r
+  }\r
+\r
+  //\r
+  // Get the device path size of boot option\r
+  //\r
+  Size = GetDevicePathSize(UpdatedDevicePath) - sizeof (EFI_DEVICE_PATH_PROTOCOL); // minus the end node\r
+  ReturnHandle = NULL;\r
+  gBS->LocateHandleBuffer (\r
+      ByProtocol,\r
+      &gEfiSimpleFileSystemProtocolGuid,\r
+      NULL,\r
+      &NumberSimpleFileSystemHandles,\r
+      &SimpleFileSystemHandles\r
+      );\r
+  for (Index = 0; Index < NumberSimpleFileSystemHandles; Index++) {\r
+    //\r
+    // Get the device path size of SimpleFileSystem handle\r
+    //\r
+    TempDevicePath = DevicePathFromHandle (SimpleFileSystemHandles[Index]);\r
+    TempSize = GetDevicePathSize (TempDevicePath)- sizeof (EFI_DEVICE_PATH_PROTOCOL); // minus the end node\r
+    //\r
+    // Check whether the device path of boot option is part of the  SimpleFileSystem handle's device path\r
+    //\r
+    if (Size <= TempSize && CompareMem (TempDevicePath, UpdatedDevicePath, Size)==0) {\r
+      //\r
+      // Load the default boot file \EFI\BOOT\boot{machinename}.EFI from removable Media\r
+      //  machinename is ia32, ia64, x64, ...\r
+      //\r
+      Hdr.Union = &HdrData;\r
+      Status = BdsLibGetImageHeader (\r
+                 SimpleFileSystemHandles[Index],\r
+                 EFI_REMOVABLE_MEDIA_FILE_NAME,\r
+                 &DosHeader,\r
+                 Hdr\r
+                 );\r
+      if (!EFI_ERROR (Status) &&\r
+        EFI_IMAGE_MACHINE_TYPE_SUPPORTED (Hdr.Pe32->FileHeader.Machine) &&\r
+        Hdr.Pe32->OptionalHeader.Subsystem == EFI_IMAGE_SUBSYSTEM_EFI_APPLICATION) {\r
+        ReturnHandle = SimpleFileSystemHandles[Index];\r
+        break;\r
+      }\r
+    }\r
+  }\r
+\r
+  FreePool(DupDevicePath);\r
+\r
+  if (SimpleFileSystemHandles != NULL) {\r
+    FreePool(SimpleFileSystemHandles);\r
+  }\r
+\r
+  gBS->RestoreTPL (OldTpl);\r
+\r
+  return ReturnHandle;\r
+}\r
+\r
+/**\r
+  Check to see if the network cable is plugged in. If the DevicePath is not\r
+  connected it will be connected.\r
+\r
+  @param  DevicePath             Device Path to check\r
+\r
+  @retval TRUE                   DevicePath points to an Network that is connected\r
+  @retval FALSE                  DevicePath does not point to a bootable network\r
+\r
+**/\r
+BOOLEAN\r
+BdsLibNetworkBootWithMediaPresent (\r
+  IN  EFI_DEVICE_PATH_PROTOCOL      *DevicePath\r
+  )\r
+{\r
+  EFI_STATUS                      Status;\r
+  EFI_DEVICE_PATH_PROTOCOL        *UpdatedDevicePath;\r
+  EFI_HANDLE                      Handle;\r
+  EFI_SIMPLE_NETWORK_PROTOCOL     *Snp;\r
+  BOOLEAN                         MediaPresent;\r
+  UINT32                          InterruptStatus;\r
+\r
+  MediaPresent = FALSE;\r
+\r
+  UpdatedDevicePath = DevicePath;\r
+  //\r
+  // Locate Load File Protocol for PXE boot option first\r
+  //\r
+  Status = gBS->LocateDevicePath (&gEfiLoadFileProtocolGuid, &UpdatedDevicePath, &Handle);\r
+  if (EFI_ERROR (Status)) {\r
+    //\r
+    // Device not present so see if we need to connect it\r
+    //\r
+    Status = BdsLibConnectDevicePath (DevicePath);\r
+    if (!EFI_ERROR (Status)) {\r
+      //\r
+      // This one should work after we did the connect\r
+      //\r
+      Status = gBS->LocateDevicePath (&gEfiLoadFileProtocolGuid, &UpdatedDevicePath, &Handle);\r
+    }\r
+  }\r
+\r
+  if (!EFI_ERROR (Status)) {\r
+    Status = gBS->HandleProtocol (Handle, &gEfiSimpleNetworkProtocolGuid, (VOID **)&Snp);\r
+    if (EFI_ERROR (Status)) {\r
+      //\r
+      // Failed to open SNP from this handle, try to get SNP from parent handle\r
+      //\r
+      UpdatedDevicePath = DevicePathFromHandle (Handle);\r
+      if (UpdatedDevicePath != NULL) {\r
+        Status = gBS->LocateDevicePath (&gEfiSimpleNetworkProtocolGuid, &UpdatedDevicePath, &Handle);\r
+        if (!EFI_ERROR (Status)) {\r
+          //\r
+          // SNP handle found, get SNP from it\r
+          //\r
+          Status = gBS->HandleProtocol (Handle, &gEfiSimpleNetworkProtocolGuid, (VOID **) &Snp);\r
+        }\r
+      }\r
+    }\r
+\r
+    if (!EFI_ERROR (Status)) {\r
+      if (Snp->Mode->MediaPresentSupported) {\r
+        if (Snp->Mode->State == EfiSimpleNetworkInitialized) {\r
+          //\r
+          // Invoke Snp->GetStatus() to refresh the media status\r
+          //\r
+          Snp->GetStatus (Snp, &InterruptStatus, NULL);\r
+\r
+          //\r
+          // In case some one else is using the SNP check to see if it's connected\r
+          //\r
+          MediaPresent = Snp->Mode->MediaPresent;\r
+        } else {\r
+          //\r
+          // No one is using SNP so we need to Start and Initialize so\r
+          // MediaPresent will be valid.\r
+          //\r
+          Status = Snp->Start (Snp);\r
+          if (!EFI_ERROR (Status)) {\r
+            Status = Snp->Initialize (Snp, 0, 0);\r
+            if (!EFI_ERROR (Status)) {\r
+              MediaPresent = Snp->Mode->MediaPresent;\r
+              Snp->Shutdown (Snp);\r
+            }\r
+            Snp->Stop (Snp);\r
+          }\r
+        }\r
+      } else {\r
+        MediaPresent = TRUE;\r
+      }\r
+    }\r
+  }\r
+\r
+  return MediaPresent;\r
+}\r
+\r
+/**\r
+  For a bootable Device path, return its boot type.\r
+\r
+  @param  DevicePath                      The bootable device Path to check\r
+\r
+  @retval BDS_EFI_MEDIA_HD_BOOT           If given device path contains MEDIA_DEVICE_PATH type device path node\r
+                                          which subtype is MEDIA_HARDDRIVE_DP\r
+  @retval BDS_EFI_MEDIA_CDROM_BOOT        If given device path contains MEDIA_DEVICE_PATH type device path node\r
+                                          which subtype is MEDIA_CDROM_DP\r
+  @retval BDS_EFI_ACPI_FLOPPY_BOOT        If given device path contains ACPI_DEVICE_PATH type device path node\r
+                                          which HID is floppy device.\r
+  @retval BDS_EFI_MESSAGE_ATAPI_BOOT      If given device path contains MESSAGING_DEVICE_PATH type device path node\r
+                                          and its last device path node's subtype is MSG_ATAPI_DP.\r
+  @retval BDS_EFI_MESSAGE_SCSI_BOOT       If given device path contains MESSAGING_DEVICE_PATH type device path node\r
+                                          and its last device path node's subtype is MSG_SCSI_DP.\r
+  @retval BDS_EFI_MESSAGE_USB_DEVICE_BOOT If given device path contains MESSAGING_DEVICE_PATH type device path node\r
+                                          and its last device path node's subtype is MSG_USB_DP.\r
+  @retval BDS_EFI_MESSAGE_MISC_BOOT       If the device path not contains any media device path node,  and\r
+                                          its last device path node point to a message device path node.\r
+  @retval BDS_LEGACY_BBS_BOOT             If given device path contains BBS_DEVICE_PATH type device path node.\r
+  @retval BDS_EFI_UNSUPPORT               An EFI Removable BlockIO device path not point to a media and message device,\r
+\r
+**/\r
+UINT32\r
+EFIAPI\r
+BdsGetBootTypeFromDevicePath (\r
+  IN  EFI_DEVICE_PATH_PROTOCOL     *DevicePath\r
+  )\r
+{\r
+  ACPI_HID_DEVICE_PATH          *Acpi;\r
+  EFI_DEVICE_PATH_PROTOCOL      *TempDevicePath;\r
+  EFI_DEVICE_PATH_PROTOCOL      *LastDeviceNode;\r
+  UINT32                        BootType;\r
+\r
+  if (NULL == DevicePath) {\r
+    return BDS_EFI_UNSUPPORT;\r
+  }\r
+\r
+  TempDevicePath = DevicePath;\r
+\r
+  while (!IsDevicePathEndType (TempDevicePath)) {\r
+    switch (DevicePathType (TempDevicePath)) {\r
+      case BBS_DEVICE_PATH:\r
+         return BDS_LEGACY_BBS_BOOT;\r
+      case MEDIA_DEVICE_PATH:\r
+        if (DevicePathSubType (TempDevicePath) == MEDIA_HARDDRIVE_DP) {\r
+          return BDS_EFI_MEDIA_HD_BOOT;\r
+        } else if (DevicePathSubType (TempDevicePath) == MEDIA_CDROM_DP) {\r
+          return BDS_EFI_MEDIA_CDROM_BOOT;\r
+        }\r
+        break;\r
+      case ACPI_DEVICE_PATH:\r
+        Acpi = (ACPI_HID_DEVICE_PATH *) TempDevicePath;\r
+        if (EISA_ID_TO_NUM (Acpi->HID) == 0x0604) {\r
+          return BDS_EFI_ACPI_FLOPPY_BOOT;\r
+        }\r
+        break;\r
+      case MESSAGING_DEVICE_PATH:\r
+        //\r
+        // Get the last device path node\r
+        //\r
+        LastDeviceNode = NextDevicePathNode (TempDevicePath);\r
+        if (DevicePathSubType(LastDeviceNode) == MSG_DEVICE_LOGICAL_UNIT_DP) {\r
+          //\r
+          // if the next node type is Device Logical Unit, which specify the Logical Unit Number (LUN),\r
+          // skip it\r
+          //\r
+          LastDeviceNode = NextDevicePathNode (LastDeviceNode);\r
+        }\r
+        //\r
+        // if the device path not only point to driver device, it is not a messaging device path,\r
+        //\r
+        if (!IsDevicePathEndType (LastDeviceNode)) {\r
+          break;\r
+        }\r
+\r
+        switch (DevicePathSubType (TempDevicePath)) {\r
+        case MSG_ATAPI_DP:\r
+          BootType = BDS_EFI_MESSAGE_ATAPI_BOOT;\r
+          break;\r
+\r
+        case MSG_USB_DP:\r
+          BootType = BDS_EFI_MESSAGE_USB_DEVICE_BOOT;\r
+          break;\r
+\r
+        case MSG_SCSI_DP:\r
+          BootType = BDS_EFI_MESSAGE_SCSI_BOOT;\r
+          break;\r
+\r
+        case MSG_SATA_DP:\r
+          BootType = BDS_EFI_MESSAGE_SATA_BOOT;\r
+          break;\r
+\r
+        case MSG_MAC_ADDR_DP:\r
+        case MSG_VLAN_DP:\r
+        case MSG_IPv4_DP:\r
+        case MSG_IPv6_DP:\r
+          BootType = BDS_EFI_MESSAGE_MAC_BOOT;\r
+          break;\r
+\r
+        default:\r
+          BootType = BDS_EFI_MESSAGE_MISC_BOOT;\r
+          break;\r
+        }\r
+        return BootType;\r
+\r
+      default:\r
+        break;\r
+    }\r
+    TempDevicePath = NextDevicePathNode (TempDevicePath);\r
+  }\r
+\r
+  return BDS_EFI_UNSUPPORT;\r
+}\r
+\r
+/**\r
+  Check whether the Device path in a boot option point to a valid bootable device,\r
+  And if CheckMedia is true, check the device is ready to boot now.\r
+\r
+  @param  DevPath     the Device path in a boot option\r
+  @param  CheckMedia  if true, check the device is ready to boot now.\r
+\r
+  @retval TRUE        the Device path  is valid\r
+  @retval FALSE       the Device path  is invalid .\r
+\r
+**/\r
+BOOLEAN\r
+EFIAPI\r
+BdsLibIsValidEFIBootOptDevicePath (\r
+  IN EFI_DEVICE_PATH_PROTOCOL     *DevPath,\r
+  IN BOOLEAN                      CheckMedia\r
+  )\r
+{\r
+  return BdsLibIsValidEFIBootOptDevicePathExt (DevPath, CheckMedia, NULL);\r
+}\r
+\r
+/**\r
+  Check whether the Device path in a boot option point to a valid bootable device,\r
+  And if CheckMedia is true, check the device is ready to boot now.\r
+  If Description is not NULL and the device path point to a fixed BlockIo\r
+  device, check the description whether conflict with other auto-created\r
+  boot options.\r
+\r
+  @param  DevPath     the Device path in a boot option\r
+  @param  CheckMedia  if true, check the device is ready to boot now.\r
+  @param  Description the description in a boot option\r
+\r
+  @retval TRUE        the Device path  is valid\r
+  @retval FALSE       the Device path  is invalid .\r
+\r
+**/\r
+BOOLEAN\r
+EFIAPI\r
+BdsLibIsValidEFIBootOptDevicePathExt (\r
+  IN EFI_DEVICE_PATH_PROTOCOL     *DevPath,\r
+  IN BOOLEAN                      CheckMedia,\r
+  IN CHAR16                       *Description\r
+  )\r
+{\r
+  EFI_STATUS                Status;\r
+  EFI_HANDLE                Handle;\r
+  EFI_DEVICE_PATH_PROTOCOL  *TempDevicePath;\r
+  EFI_DEVICE_PATH_PROTOCOL  *LastDeviceNode;\r
+  EFI_BLOCK_IO_PROTOCOL     *BlockIo;\r
+\r
+  TempDevicePath = DevPath;\r
+  LastDeviceNode = DevPath;\r
+\r
+  //\r
+  // Check if it's a valid boot option for network boot device.\r
+  // Check if there is EfiLoadFileProtocol installed. \r
+  // If yes, that means there is a boot option for network.\r
+  //\r
+  Status = gBS->LocateDevicePath (\r
+                  &gEfiLoadFileProtocolGuid,\r
+                  &TempDevicePath,\r
+                  &Handle\r
+                  );\r
+  if (EFI_ERROR (Status)) {\r
+    //\r
+    // Device not present so see if we need to connect it\r
+    //\r
+    TempDevicePath = DevPath;\r
+    BdsLibConnectDevicePath (TempDevicePath);\r
+    Status = gBS->LocateDevicePath (\r
+                    &gEfiLoadFileProtocolGuid,\r
+                    &TempDevicePath,\r
+                    &Handle\r
+                    );\r
+  }\r
+\r
+  if (!EFI_ERROR (Status)) {\r
+    if (!IsDevicePathEnd (TempDevicePath)) {\r
+      //\r
+      // LoadFile protocol is not installed on handle with exactly the same DevPath\r
+      //\r
+      return FALSE;\r
+    }\r
+\r
+    if (CheckMedia) {\r
+      //\r
+      // Test if it is ready to boot now\r
+      //\r
+      if (BdsLibNetworkBootWithMediaPresent(DevPath)) {\r
+        return TRUE;\r
+      }\r
+    } else {\r
+      return TRUE;\r
+    }    \r
+  }\r
+\r
+  //\r
+  // If the boot option point to a file, it is a valid EFI boot option,\r
+  // and assume it is ready to boot now\r
+  //\r
+  while (!IsDevicePathEnd (TempDevicePath)) {\r
+    //\r
+    // If there is USB Class or USB WWID device path node, treat it as valid EFI\r
+    // Boot Option. BdsExpandUsbShortFormDevicePath () will be used to expand it\r
+    // to full device path.\r
+    //\r
+    if ((DevicePathType (TempDevicePath) == MESSAGING_DEVICE_PATH) &&\r
+        ((DevicePathSubType (TempDevicePath) == MSG_USB_CLASS_DP) ||\r
+         (DevicePathSubType (TempDevicePath) == MSG_USB_WWID_DP))) {\r
+      return TRUE;\r
+    }\r
+\r
+    LastDeviceNode = TempDevicePath;\r
+    TempDevicePath = NextDevicePathNode (TempDevicePath);\r
+  }\r
+  if ((DevicePathType (LastDeviceNode) == MEDIA_DEVICE_PATH) &&\r
+    (DevicePathSubType (LastDeviceNode) == MEDIA_FILEPATH_DP)) {\r
+    return TRUE;\r
+  }\r
+\r
+  //\r
+  // Check if it's a valid boot option for internal FV application\r
+  //\r
+  if (EfiGetNameGuidFromFwVolDevicePathNode ((MEDIA_FW_VOL_FILEPATH_DEVICE_PATH *) LastDeviceNode) != NULL) {\r
+    //\r
+    // If the boot option point to internal FV application, make sure it is valid\r
+    //\r
+    TempDevicePath = DevPath;\r
+    Status = BdsLibUpdateFvFileDevicePath (\r
+               &TempDevicePath,\r
+               EfiGetNameGuidFromFwVolDevicePathNode ((MEDIA_FW_VOL_FILEPATH_DEVICE_PATH *) LastDeviceNode)\r
+               );\r
+    if (Status == EFI_ALREADY_STARTED) {\r
+      return TRUE;\r
+    } else {\r
+      if (Status == EFI_SUCCESS) {\r
+        FreePool (TempDevicePath);\r
+      }\r
+      return FALSE;\r
+    }\r
+  }\r
+\r
+  //\r
+  // If the boot option point to a blockIO device:\r
+  //    if it is a removable blockIo device, it is valid.\r
+  //    if it is a fixed blockIo device, check its description confliction.\r
+  //\r
+  TempDevicePath = DevPath;\r
+  Status = gBS->LocateDevicePath (&gEfiBlockIoProtocolGuid, &TempDevicePath, &Handle);\r
+  if (EFI_ERROR (Status)) {\r
+    //\r
+    // Device not present so see if we need to connect it\r
+    //\r
+    Status = BdsLibConnectDevicePath (DevPath);\r
+    if (!EFI_ERROR (Status)) {\r
+      //\r
+      // Try again to get the Block Io protocol after we did the connect\r
+      //\r
+      TempDevicePath = DevPath;\r
+      Status = gBS->LocateDevicePath (&gEfiBlockIoProtocolGuid, &TempDevicePath, &Handle);\r
+    }\r
+  }\r
+\r
+  if (!EFI_ERROR (Status)) {\r
+    Status = gBS->HandleProtocol (Handle, &gEfiBlockIoProtocolGuid, (VOID **)&BlockIo);\r
+    if (!EFI_ERROR (Status)) {\r
+      if (CheckMedia) {\r
+        //\r
+        // Test if it is ready to boot now\r
+        //\r
+        if (BdsLibGetBootableHandle (DevPath) != NULL) {\r
+          return TRUE;\r
+        }\r
+      } else {\r
+        return TRUE;\r
+      }\r
+    }\r
+  } else {\r
+    //\r
+    // if the boot option point to a simple file protocol which does not consume block Io protocol, it is also a valid EFI boot option,\r
+    //\r
+    Status = gBS->LocateDevicePath (&gEfiSimpleFileSystemProtocolGuid, &TempDevicePath, &Handle);\r
+    if (!EFI_ERROR (Status)) {\r
+      if (CheckMedia) {\r
+        //\r
+        // Test if it is ready to boot now\r
+        //\r
+        if (BdsLibGetBootableHandle (DevPath) != NULL) {\r
+          return TRUE;\r
+        }\r
+      } else {\r
+        return TRUE;\r
+      }\r
+    }\r
+  }\r
+\r
+  return FALSE;\r
+}\r
+\r
+\r
+/**\r
+  According to a file guild, check a Fv file device path is valid. If it is invalid,\r
+  try to return the valid device path.\r
+  FV address maybe changes for memory layout adjust from time to time, use this function\r
+  could promise the Fv file device path is right.\r
+\r
+  @param  DevicePath             on input, the Fv file device path need to check on\r
+                                 output, the updated valid Fv file device path\r
+  @param  FileGuid               the Fv file guild\r
+\r
+  @retval EFI_INVALID_PARAMETER  the input DevicePath or FileGuid is invalid\r
+                                 parameter\r
+  @retval EFI_UNSUPPORTED        the input DevicePath does not contain Fv file\r
+                                 guild at all\r
+  @retval EFI_ALREADY_STARTED    the input DevicePath has pointed to Fv file, it is\r
+                                 valid\r
+  @retval EFI_SUCCESS            has successfully updated the invalid DevicePath,\r
+                                 and return the updated device path in DevicePath\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+BdsLibUpdateFvFileDevicePath (\r
+  IN  OUT EFI_DEVICE_PATH_PROTOCOL      ** DevicePath,\r
+  IN  EFI_GUID                          *FileGuid\r
+  )\r
+{\r
+  EFI_DEVICE_PATH_PROTOCOL      *TempDevicePath;\r
+  EFI_DEVICE_PATH_PROTOCOL      *LastDeviceNode;\r
+  EFI_STATUS                    Status;\r
+  EFI_GUID                      *GuidPoint;\r
+  UINTN                         Index;\r
+  UINTN                         FvHandleCount;\r
+  EFI_HANDLE                    *FvHandleBuffer;\r
+  EFI_FV_FILETYPE               Type;\r
+  UINTN                         Size;\r
+  EFI_FV_FILE_ATTRIBUTES        Attributes;\r
+  UINT32                        AuthenticationStatus;\r
+  BOOLEAN                       FindFvFile;\r
+  EFI_LOADED_IMAGE_PROTOCOL     *LoadedImage;\r
+  EFI_FIRMWARE_VOLUME2_PROTOCOL *Fv;\r
+  MEDIA_FW_VOL_FILEPATH_DEVICE_PATH FvFileNode;\r
+  EFI_HANDLE                    FoundFvHandle;\r
+  EFI_DEVICE_PATH_PROTOCOL      *NewDevicePath;\r
+\r
+  if ((DevicePath == NULL) || (*DevicePath == NULL)) {\r
+    return EFI_INVALID_PARAMETER;\r
+  }\r
+  if (FileGuid == NULL) {\r
+    return EFI_INVALID_PARAMETER;\r
+  }\r
+\r
+  //\r
+  // Check whether the device path point to the default the input Fv file\r
+  //\r
+  TempDevicePath = *DevicePath;\r
+  LastDeviceNode = TempDevicePath;\r
+  while (!IsDevicePathEnd (TempDevicePath)) {\r
+     LastDeviceNode = TempDevicePath;\r
+     TempDevicePath = NextDevicePathNode (TempDevicePath);\r
+  }\r
+  GuidPoint = EfiGetNameGuidFromFwVolDevicePathNode (\r
+                (MEDIA_FW_VOL_FILEPATH_DEVICE_PATH *) LastDeviceNode\r
+                );\r
+  if (GuidPoint == NULL) {\r
+    //\r
+    // if this option does not points to a Fv file, just return EFI_UNSUPPORTED\r
+    //\r
+    return EFI_UNSUPPORTED;\r
+  }\r
+  if (!CompareGuid (GuidPoint, FileGuid)) {\r
+    //\r
+    // If the Fv file is not the input file guid, just return EFI_UNSUPPORTED\r
+    //\r
+    return EFI_UNSUPPORTED;\r
+  }\r
+\r
+  //\r
+  // Check whether the input Fv file device path is valid\r
+  //\r
+  TempDevicePath = *DevicePath;\r
+  FoundFvHandle = NULL;\r
+  Status = gBS->LocateDevicePath (\r
+                  &gEfiFirmwareVolume2ProtocolGuid,\r
+                  &TempDevicePath,\r
+                  &FoundFvHandle\r
+                  );\r
+  if (!EFI_ERROR (Status)) {\r
+    Status = gBS->HandleProtocol (\r
+                    FoundFvHandle,\r
+                    &gEfiFirmwareVolume2ProtocolGuid,\r
+                    (VOID **) &Fv\r
+                    );\r
+    if (!EFI_ERROR (Status)) {\r
+      //\r
+      // Set FV ReadFile Buffer as NULL, only need to check whether input Fv file exist there\r
+      //\r
+      Status = Fv->ReadFile (\r
+                    Fv,\r
+                    FileGuid,\r
+                    NULL,\r
+                    &Size,\r
+                    &Type,\r
+                    &Attributes,\r
+                    &AuthenticationStatus\r
+                    );\r
+      if (!EFI_ERROR (Status)) {\r
+        return EFI_ALREADY_STARTED;\r
+      }\r
+    }\r
+  }\r
+\r
+  //\r
+  // Look for the input wanted FV file in current FV\r
+  // First, try to look for in Bds own FV. Bds and input wanted FV file usually are in the same FV\r
+  //\r
+  FindFvFile = FALSE;\r
+  FoundFvHandle = NULL;\r
+  Status = gBS->HandleProtocol (\r
+             gImageHandle,\r
+             &gEfiLoadedImageProtocolGuid,\r
+             (VOID **) &LoadedImage\r
+             );\r
+  if (!EFI_ERROR (Status)) {\r
+    Status = gBS->HandleProtocol (\r
+                    LoadedImage->DeviceHandle,\r
+                    &gEfiFirmwareVolume2ProtocolGuid,\r
+                    (VOID **) &Fv\r
+                    );\r
+    if (!EFI_ERROR (Status)) {\r
+      Status = Fv->ReadFile (\r
+                    Fv,\r
+                    FileGuid,\r
+                    NULL,\r
+                    &Size,\r
+                    &Type,\r
+                    &Attributes,\r
+                    &AuthenticationStatus\r
+                    );\r
+      if (!EFI_ERROR (Status)) {\r
+        FindFvFile = TRUE;\r
+        FoundFvHandle = LoadedImage->DeviceHandle;\r
+      }\r
+    }\r
+  }\r
+  //\r
+  // Second, if fail to find, try to enumerate all FV\r
+  //\r
+  if (!FindFvFile) {\r
+    FvHandleBuffer = NULL;\r
+    gBS->LocateHandleBuffer (\r
+          ByProtocol,\r
+          &gEfiFirmwareVolume2ProtocolGuid,\r
+          NULL,\r
+          &FvHandleCount,\r
+          &FvHandleBuffer\r
+          );\r
+    for (Index = 0; Index < FvHandleCount; Index++) {\r
+      gBS->HandleProtocol (\r
+            FvHandleBuffer[Index],\r
+            &gEfiFirmwareVolume2ProtocolGuid,\r
+            (VOID **) &Fv\r
+            );\r
+\r
+      Status = Fv->ReadFile (\r
+                    Fv,\r
+                    FileGuid,\r
+                    NULL,\r
+                    &Size,\r
+                    &Type,\r
+                    &Attributes,\r
+                    &AuthenticationStatus\r
+                    );\r
+      if (EFI_ERROR (Status)) {\r
+        //\r
+        // Skip if input Fv file not in the FV\r
+        //\r
+        continue;\r
+      }\r
+      FindFvFile = TRUE;\r
+      FoundFvHandle = FvHandleBuffer[Index];\r
+      break;\r
+    }\r
+\r
+    if (FvHandleBuffer != NULL) {\r
+      FreePool (FvHandleBuffer);\r
+    }\r
+  }\r
+\r
+  if (FindFvFile) {\r
+    //\r
+    // Build the shell device path\r
+    //\r
+    NewDevicePath = DevicePathFromHandle (FoundFvHandle);\r
+    EfiInitializeFwVolDevicepathNode (&FvFileNode, FileGuid);\r
+    NewDevicePath = AppendDevicePathNode (NewDevicePath, (EFI_DEVICE_PATH_PROTOCOL *) &FvFileNode);\r
+    *DevicePath = NewDevicePath;\r
+    return EFI_SUCCESS;\r
+  }\r
+  return EFI_NOT_FOUND;\r
+}\r

diff --git a/Vlv2TbltDevicePkg/Override/IntelFrameworkModulePkg/Library/GenericBdsLib/BdsConnect.c b/Vlv2TbltDevicePkg/Override/IntelFrameworkModulePkg/Library/GenericBdsLib/BdsConnect.c
new file mode 100644 (file)
index 0000000..f487aa6
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Override/IntelFrameworkModulePkg/Library/GenericBdsLib/BdsConnect.c
@@ -0,0 +1,435 @@
+/** @file\r
+  BDS Lib functions which relate with connect the device\r
+\r
+Copyright (c) 2004 - 2013, Intel Corporation. All rights reserved.<BR>\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution.  The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#include "InternalBdsLib.h"\r
+\r
+\r
+/**\r
+  This function will connect all the system driver to controller\r
+  first, and then special connect the default console, this make\r
+  sure all the system controller available and the platform default\r
+  console connected.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+BdsLibConnectAll (\r
+  VOID\r
+  )\r
+{\r
+  //\r
+  // Connect the platform console first\r
+  //\r
+  BdsLibConnectAllDefaultConsoles ();\r
+\r
+  //\r
+  // Generic way to connect all the drivers\r
+  //\r
+  BdsLibConnectAllDriversToAllControllers ();\r
+\r
+  //\r
+  // Here we have the assumption that we have already had\r
+  // platform default console\r
+  //\r
+  BdsLibConnectAllDefaultConsoles ();\r
+}\r
+\r
+\r
+/**\r
+  This function will connect all the system drivers to all controllers\r
+  first, and then connect all the console devices the system current\r
+  have. After this we should get all the device work and console available\r
+  if the system have console device.\r
+\r
+**/\r
+VOID\r
+BdsLibGenericConnectAll (\r
+  VOID\r
+  )\r
+{\r
+  //\r
+  // Most generic way to connect all the drivers\r
+  //\r
+  BdsLibConnectAllDriversToAllControllers ();\r
+  BdsLibConnectAllConsoles ();\r
+}\r
+\r
+/**\r
+  This function will create all handles associate with every device\r
+  path node. If the handle associate with one device path node can not\r
+  be created successfully, then still give chance to do the dispatch,\r
+  which load the missing drivers if possible.\r
+\r
+  @param  DevicePathToConnect   The device path which will be connected, it can be\r
+                                a multi-instance device path\r
+\r
+  @retval EFI_SUCCESS           All handles associate with every device path  node\r
+                                have been created\r
+  @retval EFI_OUT_OF_RESOURCES  There is no resource to create new handles\r
+  @retval EFI_NOT_FOUND         Create the handle associate with one device  path\r
+                                node failed\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+BdsLibConnectDevicePath (\r
+  IN EFI_DEVICE_PATH_PROTOCOL  *DevicePathToConnect\r
+  )\r
+{\r
+  EFI_STATUS                Status;\r
+  EFI_DEVICE_PATH_PROTOCOL  *DevicePath;\r
+  EFI_DEVICE_PATH_PROTOCOL  *CopyOfDevicePath;\r
+  EFI_DEVICE_PATH_PROTOCOL  *Instance;\r
+  EFI_DEVICE_PATH_PROTOCOL  *RemainingDevicePath;\r
+  EFI_DEVICE_PATH_PROTOCOL  *Next;\r
+  EFI_HANDLE                Handle;\r
+  EFI_HANDLE                PreviousHandle;\r
+  UINTN                     Size;\r
+  EFI_TPL                   CurrentTpl;\r
+\r
+  if (DevicePathToConnect == NULL) {\r
+    return EFI_SUCCESS;\r
+  }\r
+\r
+  CurrentTpl  = EfiGetCurrentTpl ();\r
+\r
+  DevicePath        = DuplicateDevicePath (DevicePathToConnect);\r
+  if (DevicePath == NULL) {\r
+    return EFI_OUT_OF_RESOURCES;\r
+  }\r
+  CopyOfDevicePath  = DevicePath;\r
+  \r
+  do {\r
+    //\r
+    // The outer loop handles multi instance device paths.\r
+    // Only console variables contain multiple instance device paths.\r
+    //\r
+    // After this call DevicePath points to the next Instance\r
+    //\r
+    Instance  = GetNextDevicePathInstance (&DevicePath, &Size);\r
+    if (Instance == NULL) {\r
+      FreePool (CopyOfDevicePath);\r
+      return EFI_OUT_OF_RESOURCES;\r
+    }\r
+    \r
+    Next      = Instance;\r
+    while (!IsDevicePathEndType (Next)) {\r
+      Next = NextDevicePathNode (Next);\r
+    }\r
+\r
+    SetDevicePathEndNode (Next);\r
+\r
+    //\r
+    // Start the real work of connect with RemainingDevicePath\r
+    //\r
+    PreviousHandle = NULL;\r
+    do {\r
+      //\r
+      // Find the handle that best matches the Device Path. If it is only a\r
+      // partial match the remaining part of the device path is returned in\r
+      // RemainingDevicePath.\r
+      //\r
+      RemainingDevicePath = Instance;\r
+      Status              = gBS->LocateDevicePath (&gEfiDevicePathProtocolGuid, &RemainingDevicePath, &Handle);\r
+\r
+      if (!EFI_ERROR (Status)) {\r
+        if (Handle == PreviousHandle) {\r
+          //\r
+          // If no forward progress is made try invoking the Dispatcher.\r
+          // A new FV may have been added to the system an new drivers\r
+          // may now be found.\r
+          // Status == EFI_SUCCESS means a driver was dispatched\r
+          // Status == EFI_NOT_FOUND means no new drivers were dispatched\r
+          //\r
+          if (CurrentTpl == TPL_APPLICATION) {\r
+            //\r
+            // Dispatch calls LoadImage/StartImage which cannot run at TPL > TPL_APPLICATION\r
+            //\r
+            Status = gDS->Dispatch ();\r
+          } else {\r
+            //\r
+            // Always return EFI_NOT_FOUND here\r
+            // to prevent dead loop when control handle is found but connection failded case\r
+            //\r
+            Status = EFI_NOT_FOUND;\r
+          }\r
+        }\r
+\r
+        if (!EFI_ERROR (Status)) {\r
+          PreviousHandle = Handle;\r
+          //\r
+          // Connect all drivers that apply to Handle and RemainingDevicePath,\r
+          // the Recursive flag is FALSE so only one level will be expanded.\r
+          //\r
+          // Do not check the connect status here, if the connect controller fail,\r
+          // then still give the chance to do dispatch, because partial\r
+          // RemainingDevicepath may be in the new FV\r
+          //\r
+          // 1. If the connect fail, RemainingDevicepath and handle will not\r
+          //    change, so next time will do the dispatch, then dispatch's status\r
+          //    will take effect\r
+          // 2. If the connect success, the RemainingDevicepath and handle will\r
+          //    change, then avoid the dispatch, we have chance to continue the\r
+          //    next connection\r
+          //\r
+          gBS->ConnectController (Handle, NULL, RemainingDevicePath, FALSE);\r
+        }\r
+      }\r
+      //\r
+      // Loop until RemainingDevicePath is an empty device path\r
+      //\r
+    } while (!EFI_ERROR (Status) && !IsDevicePathEnd (RemainingDevicePath));\r
+\r
+  } while (DevicePath != NULL);\r
+\r
+  if (CopyOfDevicePath != NULL) {\r
+    FreePool (CopyOfDevicePath);\r
+  }\r
+  //\r
+  // All handle with DevicePath exists in the handle database\r
+  //\r
+  return Status;\r
+}\r
+\r
+/**\r
+  This function will connect all current system handles recursively. \r
+  \r
+  gBS->ConnectController() service is invoked for each handle exist in system handler buffer.\r
+  If the handle is bus type handler, all childrens also will be connected recursively\r
+  by gBS->ConnectController().\r
+\r
+  @retval EFI_SUCCESS           All handles and it's child handle have been connected\r
+  @retval EFI_STATUS            Error status returned by of gBS->LocateHandleBuffer().\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+BdsLibConnectAllEfi (\r
+  VOID\r
+  )\r
+{\r
+  EFI_STATUS  Status;\r
+  UINTN       HandleCount;\r
+  EFI_HANDLE  *HandleBuffer;\r
+  UINTN       Index;\r
+\r
+  Status = gBS->LocateHandleBuffer (\r
+                  AllHandles,\r
+                  NULL,\r
+                  NULL,\r
+                  &HandleCount,\r
+                  &HandleBuffer\r
+                  );\r
+  if (EFI_ERROR (Status)) {\r
+    return Status;\r
+  }\r
+\r
+  for (Index = 0; Index < HandleCount; Index++) {\r
+    Status = gBS->ConnectController (HandleBuffer[Index], NULL, NULL, TRUE);\r
+  }\r
+\r
+  if (HandleBuffer != NULL) {\r
+    FreePool (HandleBuffer);\r
+  }\r
+\r
+  return EFI_SUCCESS;\r
+}\r
+\r
+/**\r
+  This function will disconnect all current system handles. \r
+  \r
+  gBS->DisconnectController() is invoked for each handle exists in system handle buffer.\r
+  If handle is a bus type handle, all childrens also are disconnected recursively by\r
+  gBS->DisconnectController().\r
+\r
+  @retval EFI_SUCCESS           All handles have been disconnected\r
+  @retval EFI_STATUS            Error status returned by of gBS->LocateHandleBuffer().\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+BdsLibDisconnectAllEfi (\r
+  VOID\r
+  )\r
+{\r
+  EFI_STATUS  Status;\r
+  UINTN       HandleCount;\r
+  EFI_HANDLE  *HandleBuffer;\r
+  UINTN       Index;\r
+\r
+  //\r
+  // Disconnect all\r
+  //\r
+  Status = gBS->LocateHandleBuffer (\r
+                  AllHandles,\r
+                  NULL,\r
+                  NULL,\r
+                  &HandleCount,\r
+                  &HandleBuffer\r
+                  );\r
+  if (EFI_ERROR (Status)) {\r
+    return Status;\r
+  }\r
+\r
+  for (Index = 0; Index < HandleCount; Index++) {\r
+    Status = gBS->DisconnectController (HandleBuffer[Index], NULL, NULL);\r
+  }\r
+\r
+  if (HandleBuffer != NULL) {\r
+    FreePool (HandleBuffer);\r
+  }\r
+\r
+  return EFI_SUCCESS;\r
+}\r
+\r
+\r
+/**\r
+  Connects all drivers to all controllers.\r
+  This function make sure all the current system driver will manage\r
+  the correspoinding controllers if have. And at the same time, make\r
+  sure all the system controllers have driver to manage it if have.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+BdsLibConnectAllDriversToAllControllers (\r
+  VOID\r
+  )\r
+{\r
+  EFI_STATUS  Status;\r
+\r
+  do {\r
+    //\r
+    // Connect All EFI 1.10 drivers following EFI 1.10 algorithm\r
+    //\r
+    BdsLibConnectAllEfi ();\r
+\r
+    //\r
+    // Check to see if it's possible to dispatch an more DXE drivers.\r
+    // The BdsLibConnectAllEfi () may have made new DXE drivers show up.\r
+    // If anything is Dispatched Status == EFI_SUCCESS and we will try\r
+    // the connect again.\r
+    //\r
+    Status = gDS->Dispatch ();\r
+\r
+  } while (!EFI_ERROR (Status));\r
+\r
+}\r
+\r
+\r
+/**\r
+  Connect the specific Usb device which match the short form device path,\r
+  and whose bus is determined by Host Controller (Uhci or Ehci).\r
+\r
+  @param  HostControllerPI      Uhci (0x00) or Ehci (0x20) or Both uhci and ehci\r
+                                (0xFF)\r
+  @param  RemainingDevicePath   a short-form device path that starts with the first\r
+                                element  being a USB WWID or a USB Class device\r
+                                path\r
+\r
+  @return EFI_INVALID_PARAMETER  RemainingDevicePath is NULL pointer.\r
+                                 RemainingDevicePath is not a USB device path.\r
+                                 Invalid HostControllerPI type.\r
+  @return EFI_SUCCESS            Success to connect USB device\r
+  @return EFI_NOT_FOUND          Fail to find handle for USB controller to connect.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+BdsLibConnectUsbDevByShortFormDP(\r
+  IN UINT8                      HostControllerPI,\r
+  IN EFI_DEVICE_PATH_PROTOCOL   *RemainingDevicePath\r
+  )\r
+{\r
+  EFI_STATUS                            Status;\r
+  EFI_HANDLE                            *HandleArray;\r
+  UINTN                                 HandleArrayCount;\r
+  UINTN                                 Index;\r
+  EFI_PCI_IO_PROTOCOL                   *PciIo;\r
+  UINT8                                 Class[3];\r
+  BOOLEAN                               AtLeastOneConnected;\r
+\r
+  //\r
+  // Check the passed in parameters\r
+  //\r
+  if (RemainingDevicePath == NULL) {\r
+    return EFI_INVALID_PARAMETER;\r
+  }\r
+\r
+  if ((DevicePathType (RemainingDevicePath) != MESSAGING_DEVICE_PATH) ||\r
+      ((DevicePathSubType (RemainingDevicePath) != MSG_USB_CLASS_DP)\r
+      && (DevicePathSubType (RemainingDevicePath) != MSG_USB_WWID_DP)\r
+      )) {\r
+    return EFI_INVALID_PARAMETER;\r
+  }\r
+\r
+  if (HostControllerPI != 0xFF &&\r
+      HostControllerPI != 0x00 &&\r
+      HostControllerPI != 0x20) {\r
+    return EFI_INVALID_PARAMETER;\r
+  }\r
+\r
+  //\r
+  // Find the usb host controller firstly, then connect with the remaining device path\r
+  //\r
+  AtLeastOneConnected = FALSE;\r
+  Status = gBS->LocateHandleBuffer (\r
+                  ByProtocol,\r
+                  &gEfiPciIoProtocolGuid,\r
+                  NULL,\r
+                  &HandleArrayCount,\r
+                  &HandleArray\r
+                  );\r
+  if (!EFI_ERROR (Status)) {\r
+    for (Index = 0; Index < HandleArrayCount; Index++) {\r
+      Status = gBS->HandleProtocol (\r
+                      HandleArray[Index],\r
+                      &gEfiPciIoProtocolGuid,\r
+                      (VOID **)&PciIo\r
+                      );\r
+      if (!EFI_ERROR (Status)) {\r
+        //\r
+        // Check whether the Pci device is the wanted usb host controller\r
+        //\r
+        Status = PciIo->Pci.Read (PciIo, EfiPciIoWidthUint8, 0x09, 3, &Class);\r
+        if (!EFI_ERROR (Status)) {\r
+          if ((PCI_CLASS_SERIAL == Class[2]) &&\r
+              (PCI_CLASS_SERIAL_USB == Class[1])) {\r
+            if (HostControllerPI == Class[0] || HostControllerPI == 0xFF) {\r
+              Status = gBS->ConnectController (\r
+                              HandleArray[Index],\r
+                              NULL,\r
+                              RemainingDevicePath,\r
+                              FALSE\r
+                              );\r
+              if (!EFI_ERROR(Status)) {\r
+                AtLeastOneConnected = TRUE;\r
+              }\r
+            }\r
+          }\r
+        }\r
+      }\r
+    }\r
+\r
+    if (HandleArray != NULL) {\r
+      FreePool (HandleArray);\r
+    }\r
+\r
+    if (AtLeastOneConnected) {\r
+      return EFI_SUCCESS;\r
+    }\r
+  }\r
+\r
+  return EFI_NOT_FOUND;\r
+}\r

diff --git a/Vlv2TbltDevicePkg/Override/IntelFrameworkModulePkg/Library/GenericBdsLib/BdsConsole.c b/Vlv2TbltDevicePkg/Override/IntelFrameworkModulePkg/Library/GenericBdsLib/BdsConsole.c
new file mode 100644 (file)
index 0000000..84e4a0e
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Override/IntelFrameworkModulePkg/Library/GenericBdsLib/BdsConsole.c
@@ -0,0 +1,1302 @@
+/** @file\r
+  BDS Lib functions which contain all the code to connect console device\r
+\r
+Copyright (c) 2004 - 2013, Intel Corporation. All rights reserved.<BR>\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution.  The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#include "InternalBdsLib.h"\r
+#include <IndustryStandard/Bmp.h>\r
+\r
+\r
+/**\r
+  Check if we need to save the EFI variable with "ConVarName" as name\r
+  as NV type\r
+  If ConVarName is NULL, then ASSERT().\r
+  \r
+  @param ConVarName The name of the EFI variable.\r
+\r
+  @retval TRUE    Set the EFI variable as NV type.\r
+  @retval FALSE   EFI variable as NV type can be set NonNV.\r
+**/\r
+BOOLEAN\r
+IsNvNeed (\r
+  IN CHAR16 *ConVarName\r
+  )\r
+{\r
+  CHAR16 *Ptr;\r
+\r
+  ASSERT (ConVarName != NULL);\r
+  \r
+  Ptr = ConVarName;\r
+\r
+  //\r
+  // If the variable includes "Dev" at last, we consider\r
+  // it does not support NV attribute.\r
+  //\r
+  while (*Ptr != L'\0') {\r
+    Ptr++;\r
+  }\r
+\r
+  if (((INTN)((UINTN)Ptr - (UINTN)ConVarName) / sizeof (CHAR16)) <= 3) {\r
+    return TRUE;\r
+  }\r
+  \r
+  if ((*(Ptr - 3) == 'D') && (*(Ptr - 2) == 'e') && (*(Ptr - 1) == 'v')) {\r
+    return FALSE;\r
+  } else {\r
+    return TRUE;\r
+  }\r
+}\r
+\r
+/**\r
+  Fill console handle in System Table if there are no valid console handle in.\r
+\r
+  Firstly, check the validation of console handle in System Table. If it is invalid,\r
+  update it by the first console device handle from EFI console variable. \r
+\r
+  @param  VarName            The name of the EFI console variable.\r
+  @param  ConsoleGuid        Specified Console protocol GUID.\r
+  @param  ConsoleHandle      On IN,  console handle in System Table to be checked. \r
+                             On OUT, new console hanlde in system table.\r
+  @param  ProtocolInterface  On IN,  console protocol on console handle in System Table to be checked. \r
+                             On OUT, new console protocol on new console hanlde in system table.\r
+\r
+  @retval TRUE               System Table has been updated.\r
+  @retval FALSE              System Table hasn't been updated.\r
+\r
+**/\r
+BOOLEAN \r
+UpdateSystemTableConsole (\r
+  IN     CHAR16                          *VarName,\r
+  IN     EFI_GUID                        *ConsoleGuid,\r
+  IN OUT EFI_HANDLE                      *ConsoleHandle,\r
+  IN OUT VOID                            **ProtocolInterface\r
+  )\r
+{\r
+  EFI_STATUS                Status;\r
+  UINTN                     DevicePathSize;\r
+  EFI_DEVICE_PATH_PROTOCOL  *FullDevicePath;\r
+  EFI_DEVICE_PATH_PROTOCOL  *VarConsole;\r
+  EFI_DEVICE_PATH_PROTOCOL  *Instance;\r
+  VOID                      *Interface;\r
+  EFI_HANDLE                NewHandle;\r
+  EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL *TextOut;\r
+\r
+  ASSERT (VarName != NULL);\r
+  ASSERT (ConsoleHandle != NULL);\r
+  ASSERT (ConsoleGuid != NULL);\r
+  ASSERT (ProtocolInterface != NULL);\r
+\r
+  if (*ConsoleHandle != NULL) {\r
+    Status = gBS->HandleProtocol (\r
+                   *ConsoleHandle,\r
+                   ConsoleGuid,\r
+                   &Interface\r
+                   );\r
+    if (Status == EFI_SUCCESS && Interface == *ProtocolInterface) {\r
+      //\r
+      // If ConsoleHandle is valid and console protocol on this handle also\r
+      // also matched, just return.\r
+      //\r
+      return FALSE;\r
+    }\r
+  }\r
+  \r
+  //\r
+  // Get all possible consoles device path from EFI variable\r
+  //\r
+  VarConsole = BdsLibGetVariableAndSize (\r
+                VarName,\r
+                &gEfiGlobalVariableGuid,\r
+                &DevicePathSize\r
+                );\r
+  if (VarConsole == NULL) {\r
+    //\r
+    // If there is no any console device, just return.\r
+    //\r
+    return FALSE;\r
+  }\r
+\r
+  FullDevicePath = VarConsole;\r
+\r
+  do {\r
+    //\r
+    // Check every instance of the console variable\r
+    //\r
+    Instance  = GetNextDevicePathInstance (&VarConsole, &DevicePathSize);\r
+    if (Instance == NULL) {\r
+      FreePool (FullDevicePath);\r
+      ASSERT (FALSE);\r
+    }\r
+    \r
+    //\r
+    // Find console device handle by device path instance\r
+    //\r
+    Status = gBS->LocateDevicePath (\r
+                   ConsoleGuid,\r
+                   &Instance,\r
+                   &NewHandle\r
+                   );\r
+    if (!EFI_ERROR (Status)) {\r
+      //\r
+      // Get the console protocol on this console device handle\r
+      //\r
+      Status = gBS->HandleProtocol (\r
+                     NewHandle,\r
+                     ConsoleGuid,\r
+                     &Interface\r
+                     );\r
+      if (!EFI_ERROR (Status)) {\r
+        //\r
+        // Update new console handle in System Table.\r
+        //\r
+        *ConsoleHandle     = NewHandle;\r
+        *ProtocolInterface = Interface;\r
+        if (CompareGuid (ConsoleGuid, &gEfiSimpleTextOutProtocolGuid)) {\r
+          //\r
+          // If it is console out device, set console mode 80x25 if current mode is invalid.\r
+          //\r
+          TextOut = (EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL *) Interface;\r
+          if (TextOut->Mode->Mode == -1) {\r
+            TextOut->SetMode (TextOut, 0);\r
+          }\r
+        }\r
+        return TRUE;\r
+      }\r
+    }\r
+\r
+  } while (Instance != NULL);\r
+\r
+  //\r
+  // No any available console devcie found.\r
+  //\r
+  return FALSE;\r
+}\r
+\r
+/**\r
+  This function update console variable based on ConVarName, it can\r
+  add or remove one specific console device path from the variable\r
+\r
+  @param  ConVarName               Console related variable name, ConIn, ConOut,\r
+                                   ErrOut.\r
+  @param  CustomizedConDevicePath  The console device path which will be added to\r
+                                   the console variable ConVarName, this parameter\r
+                                   can not be multi-instance.\r
+  @param  ExclusiveDevicePath      The console device path which will be removed\r
+                                   from the console variable ConVarName, this\r
+                                   parameter can not be multi-instance.\r
+\r
+  @retval EFI_UNSUPPORTED          The added device path is same to the removed one.\r
+  @retval EFI_SUCCESS              Success add or remove the device path from  the\r
+                                   console variable.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+BdsLibUpdateConsoleVariable (\r
+  IN  CHAR16                    *ConVarName,\r
+  IN  EFI_DEVICE_PATH_PROTOCOL  *CustomizedConDevicePath,\r
+  IN  EFI_DEVICE_PATH_PROTOCOL  *ExclusiveDevicePath\r
+  )\r
+{\r
+  EFI_STATUS                Status;\r
+  EFI_DEVICE_PATH_PROTOCOL  *VarConsole;\r
+  UINTN                     DevicePathSize;\r
+  EFI_DEVICE_PATH_PROTOCOL  *NewDevicePath;\r
+  EFI_DEVICE_PATH_PROTOCOL  *TempNewDevicePath;\r
+  UINT32                    Attributes;\r
+\r
+  VarConsole      = NULL;\r
+  DevicePathSize  = 0;\r
+\r
+  //\r
+  // Notes: check the device path point, here should check\r
+  // with compare memory\r
+  //\r
+  if (CustomizedConDevicePath == ExclusiveDevicePath) {\r
+    return EFI_UNSUPPORTED;\r
+  }\r
+  //\r
+  // Delete the ExclusiveDevicePath from current default console\r
+  //\r
+  VarConsole = BdsLibGetVariableAndSize (\r
+                ConVarName,\r
+                &gEfiGlobalVariableGuid,\r
+                &DevicePathSize\r
+                );\r
+\r
+  //\r
+  // Initialize NewDevicePath\r
+  //\r
+  NewDevicePath  = VarConsole;\r
+\r
+  //\r
+  // If ExclusiveDevicePath is even the part of the instance in VarConsole, delete it.\r
+  // In the end, NewDevicePath is the final device path.\r
+  //\r
+  if (ExclusiveDevicePath != NULL && VarConsole != NULL) {\r
+      NewDevicePath = BdsLibDelPartMatchInstance (VarConsole, ExclusiveDevicePath);\r
+  }\r
+  //\r
+  // Try to append customized device path to NewDevicePath.\r
+  //\r
+  if (CustomizedConDevicePath != NULL) {\r
+    if (!BdsLibMatchDevicePaths (NewDevicePath, CustomizedConDevicePath)) {\r
+      //\r
+      // Check if there is part of CustomizedConDevicePath in NewDevicePath, delete it.\r
+      //\r
+      NewDevicePath = BdsLibDelPartMatchInstance (NewDevicePath, CustomizedConDevicePath);\r
+      //\r
+      // In the first check, the default console variable will be _ModuleEntryPoint,\r
+      // just append current customized device path\r
+      //\r
+      TempNewDevicePath = NewDevicePath;\r
+      NewDevicePath = AppendDevicePathInstance (NewDevicePath, CustomizedConDevicePath);\r
+      if (TempNewDevicePath != NULL) {\r
+        FreePool(TempNewDevicePath);\r
+      }\r
+    }\r
+  }\r
+\r
+  //\r
+  // The attribute for ConInDev, ConOutDev and ErrOutDev does not include NV.\r
+  //\r
+  if (IsNvNeed(ConVarName)) {\r
+    //\r
+    // ConVarName has NV attribute.\r
+    //\r
+    Attributes = EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS | EFI_VARIABLE_NON_VOLATILE;\r
+  } else {\r
+    //\r
+    // ConVarName does not have NV attribute.\r
+    //\r
+    Attributes = EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS;\r
+  }\r
+\r
+  //\r
+  // Finally, Update the variable of the default console by NewDevicePath\r
+  //\r
+  DevicePathSize = GetDevicePathSize (NewDevicePath);\r
+  Status = gRT->SetVariable (\r
+                  ConVarName,\r
+                  &gEfiGlobalVariableGuid,\r
+                  Attributes,\r
+                  DevicePathSize,\r
+                  NewDevicePath\r
+                  );\r
+  if ((DevicePathSize == 0) && (Status == EFI_NOT_FOUND)) {\r
+    Status = EFI_SUCCESS;\r
+  }\r
+  ASSERT_EFI_ERROR (Status);\r
+\r
+  if (VarConsole == NewDevicePath) {\r
+    if (VarConsole != NULL) {\r
+      FreePool(VarConsole);\r
+    }\r
+  } else {\r
+    if (VarConsole != NULL) {\r
+      FreePool(VarConsole);\r
+    }\r
+    if (NewDevicePath != NULL) {\r
+      FreePool(NewDevicePath);\r
+    }\r
+  }\r
+\r
+  return Status;\r
+\r
+}\r
+\r
+\r
+/**\r
+  Connect the console device base on the variable ConVarName, if\r
+  device path of the ConVarName is multi-instance device path and\r
+  anyone of the instances is connected success, then this function\r
+  will return success.\r
+  If the handle associate with one device path node can not\r
+  be created successfully, then still give chance to do the dispatch,\r
+  which load the missing drivers if possible..\r
+\r
+  @param  ConVarName               Console related variable name, ConIn, ConOut,\r
+                                   ErrOut.\r
+\r
+  @retval EFI_NOT_FOUND            There is not any console devices connected\r
+                                   success\r
+  @retval EFI_SUCCESS              Success connect any one instance of the console\r
+                                   device path base on the variable ConVarName.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+BdsLibConnectConsoleVariable (\r
+  IN  CHAR16                 *ConVarName\r
+  )\r
+{\r
+  EFI_STATUS                Status;\r
+  EFI_DEVICE_PATH_PROTOCOL  *StartDevicePath;\r
+  UINTN                     VariableSize;\r
+  EFI_DEVICE_PATH_PROTOCOL  *Instance;\r
+  EFI_DEVICE_PATH_PROTOCOL  *Next;\r
+  EFI_DEVICE_PATH_PROTOCOL  *CopyOfDevicePath;\r
+  UINTN                     Size;\r
+  BOOLEAN                   DeviceExist;\r
+\r
+  Status      = EFI_SUCCESS;\r
+  DeviceExist = FALSE;\r
+\r
+  //\r
+  // Check if the console variable exist\r
+  //\r
+  StartDevicePath = BdsLibGetVariableAndSize (\r
+                      ConVarName,\r
+                      &gEfiGlobalVariableGuid,\r
+                      &VariableSize\r
+                      );\r
+  if (StartDevicePath == NULL) {\r
+    return EFI_UNSUPPORTED;\r
+  }\r
+\r
+  CopyOfDevicePath = StartDevicePath;\r
+  do {\r
+    //\r
+    // Check every instance of the console variable\r
+    //\r
+    Instance  = GetNextDevicePathInstance (&CopyOfDevicePath, &Size);\r
+    if (Instance == NULL) {\r
+      FreePool (StartDevicePath);\r
+      return EFI_UNSUPPORTED;\r
+    }\r
+    \r
+    Next      = Instance;\r
+    while (!IsDevicePathEndType (Next)) {\r
+      Next = NextDevicePathNode (Next);\r
+    }\r
+\r
+    SetDevicePathEndNode (Next);\r
+    //\r
+    // Connect the USB console\r
+    // USB console device path is a short-form device path that \r
+    //  starts with the first element being a USB WWID\r
+    //  or a USB Class device path\r
+    //\r
+    if ((DevicePathType (Instance) == MESSAGING_DEVICE_PATH) &&\r
+       ((DevicePathSubType (Instance) == MSG_USB_CLASS_DP)\r
+       || (DevicePathSubType (Instance) == MSG_USB_WWID_DP)\r
+       )) {\r
+      Status = BdsLibConnectUsbDevByShortFormDP (0xFF, Instance);\r
+      if (!EFI_ERROR (Status)) {\r
+        DeviceExist = TRUE;\r
+      }\r
+    } else {\r
+      //\r
+      // Connect the instance device path\r
+      //\r
+      Status = BdsLibConnectDevicePath (Instance);\r
+\r
+      if (EFI_ERROR (Status)) {\r
+        //\r
+        // Delete the instance from the console varialbe\r
+        //\r
+        BdsLibUpdateConsoleVariable (ConVarName, NULL, Instance);\r
+      } else {\r
+        DeviceExist = TRUE;\r
+      }\r
+    }\r
+    FreePool(Instance);\r
+  } while (CopyOfDevicePath != NULL);\r
+\r
+  FreePool (StartDevicePath);\r
+\r
+  if (!DeviceExist) {\r
+    return EFI_NOT_FOUND;\r
+  }\r
+\r
+  return EFI_SUCCESS;\r
+}\r
+\r
+/**\r
+  This function will search every simpletext device in current system,\r
+  and make every simpletext device as pertantial console device.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+BdsLibConnectAllConsoles (\r
+  VOID\r
+  )\r
+{\r
+  UINTN                     Index;\r
+  EFI_DEVICE_PATH_PROTOCOL  *ConDevicePath;\r
+  UINTN                     HandleCount;\r
+  EFI_HANDLE                *HandleBuffer;\r
+\r
+  Index         = 0;\r
+  HandleCount   = 0;\r
+  HandleBuffer  = NULL;\r
+  ConDevicePath = NULL;\r
+\r
+  //\r
+  // Update all the console variables\r
+  //\r
+  gBS->LocateHandleBuffer (\r
+          ByProtocol,\r
+          &gEfiSimpleTextInProtocolGuid,\r
+          NULL,\r
+          &HandleCount,\r
+          &HandleBuffer\r
+          );\r
+\r
+  for (Index = 0; Index < HandleCount; Index++) {\r
+    gBS->HandleProtocol (\r
+            HandleBuffer[Index],\r
+            &gEfiDevicePathProtocolGuid,\r
+            (VOID **) &ConDevicePath\r
+            );\r
+    BdsLibUpdateConsoleVariable (L"ConIn", ConDevicePath, NULL);\r
+  }\r
+\r
+  if (HandleBuffer != NULL) {\r
+    FreePool(HandleBuffer);\r
+    HandleBuffer = NULL;\r
+  }\r
+\r
+  gBS->LocateHandleBuffer (\r
+          ByProtocol,\r
+          &gEfiSimpleTextOutProtocolGuid,\r
+          NULL,\r
+          &HandleCount,\r
+          &HandleBuffer\r
+          );\r
+  for (Index = 0; Index < HandleCount; Index++) {\r
+    gBS->HandleProtocol (\r
+            HandleBuffer[Index],\r
+            &gEfiDevicePathProtocolGuid,\r
+            (VOID **) &ConDevicePath\r
+            );\r
+    BdsLibUpdateConsoleVariable (L"ConOut", ConDevicePath, NULL);\r
+    BdsLibUpdateConsoleVariable (L"ErrOut", ConDevicePath, NULL);\r
+  }\r
+\r
+  if (HandleBuffer != NULL) {\r
+    FreePool(HandleBuffer);\r
+  }\r
+\r
+  //\r
+  // Connect all console variables\r
+  //\r
+  BdsLibConnectAllDefaultConsoles ();\r
+\r
+}\r
+\r
+/**\r
+  This function will connect console device base on the console\r
+  device variable ConIn, ConOut and ErrOut.\r
+\r
+  @retval EFI_SUCCESS              At least one of the ConIn and ConOut device have\r
+                                   been connected success.\r
+  @retval EFI_STATUS               Return the status of BdsLibConnectConsoleVariable ().\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+BdsLibConnectAllDefaultConsoles (\r
+  VOID\r
+  )\r
+{\r
+  EFI_STATUS                Status;\r
+  BOOLEAN                   SystemTableUpdated;\r
+\r
+  //\r
+  // Connect all default console variables\r
+  //\r
+\r
+  //\r
+  // It seems impossible not to have any ConOut device on platform,\r
+  // so we check the status here.\r
+  //\r
+  Status = BdsLibConnectConsoleVariable (L"ConOut");\r
+  if (EFI_ERROR (Status)) {\r
+    return Status;\r
+  }\r
+\r
+  //\r
+  // Insert the performance probe for Console Out\r
+  //\r
+  PERF_START (NULL, "ConOut", "BDS", 1);\r
+  PERF_END (NULL, "ConOut", "BDS", 0);\r
+\r
+  //\r
+  // Because possibly the platform is legacy free, in such case,\r
+  // ConIn devices (Serial Port and PS2 Keyboard ) does not exist,\r
+  // so we need not check the status.\r
+  //\r
+  BdsLibConnectConsoleVariable (L"ConIn");\r
+\r
+  //\r
+  // The _ModuleEntryPoint err out var is legal.\r
+  //\r
+  BdsLibConnectConsoleVariable (L"ErrOut");\r
+\r
+  SystemTableUpdated = FALSE;\r
+  //\r
+  // Fill console handles in System Table if no console device assignd.\r
+  //\r
+  if (UpdateSystemTableConsole (L"ConIn", &gEfiSimpleTextInProtocolGuid, &gST->ConsoleInHandle, (VOID **) &gST->ConIn)) {\r
+    SystemTableUpdated = TRUE;\r
+  }\r
+  if (UpdateSystemTableConsole (L"ConOut", &gEfiSimpleTextOutProtocolGuid, &gST->ConsoleOutHandle, (VOID **) &gST->ConOut)) {\r
+    SystemTableUpdated = TRUE;\r
+  }\r
+  if (UpdateSystemTableConsole (L"ErrOut", &gEfiSimpleTextOutProtocolGuid, &gST->StandardErrorHandle, (VOID **) &gST->StdErr)) {\r
+    SystemTableUpdated = TRUE;\r
+  }\r
+\r
+  if (SystemTableUpdated) {\r
+    //\r
+    // Update the CRC32 in the EFI System Table header\r
+    //\r
+    gST->Hdr.CRC32 = 0;\r
+    gBS->CalculateCrc32 (\r
+          (UINT8 *) &gST->Hdr,\r
+          gST->Hdr.HeaderSize,\r
+          &gST->Hdr.CRC32\r
+          );\r
+  }\r
+\r
+  return EFI_SUCCESS;\r
+\r
+}\r
+\r
+/**\r
+  This function will connect console device except ConIn base on the console\r
+  device variable  ConOut and ErrOut.\r
+\r
+  @retval EFI_SUCCESS              At least one of the ConOut device have\r
+                                   been connected success.\r
+  @retval EFI_STATUS               Return the status of BdsLibConnectConsoleVariable ().\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+BdsLibConnectAllDefaultConsolesWithOutConIn (\r
+  VOID\r
+  )\r
+{\r
+  EFI_STATUS                Status;\r
+  BOOLEAN                   SystemTableUpdated;\r
+\r
+  //\r
+  // Connect all default console variables except ConIn\r
+  //\r
+\r
+  //\r
+  // It seems impossible not to have any ConOut device on platform,\r
+  // so we check the status here.\r
+  //\r
+  Status = BdsLibConnectConsoleVariable (L"ConOut");\r
+  if (EFI_ERROR (Status)) {\r
+    return Status;\r
+  }\r
+\r
+  //\r
+  // Insert the performance probe for Console Out\r
+  //\r
+  PERF_START (NULL, "ConOut", "BDS", 1);\r
+  PERF_END (NULL, "ConOut", "BDS", 0);\r
+\r
+  //\r
+  // The _ModuleEntryPoint err out var is legal.\r
+  //\r
+  BdsLibConnectConsoleVariable (L"ErrOut");\r
+\r
+  SystemTableUpdated = FALSE;\r
+  //\r
+  // Fill console handles in System Table if no console device assignd.\r
+  //\r
+  if (UpdateSystemTableConsole (L"ConOut", &gEfiSimpleTextOutProtocolGuid, &gST->ConsoleOutHandle, (VOID **) &gST->ConOut)) {\r
+    SystemTableUpdated = TRUE;\r
+  }\r
+  if (UpdateSystemTableConsole (L"ErrOut", &gEfiSimpleTextOutProtocolGuid, &gST->StandardErrorHandle, (VOID **) &gST->StdErr)) {\r
+    SystemTableUpdated = TRUE;\r
+  }\r
+\r
+  if (SystemTableUpdated) {\r
+    //\r
+    // Update the CRC32 in the EFI System Table header\r
+    //\r
+    gST->Hdr.CRC32 = 0;\r
+    gBS->CalculateCrc32 (\r
+          (UINT8 *) &gST->Hdr,\r
+          gST->Hdr.HeaderSize,\r
+          &gST->Hdr.CRC32\r
+          );\r
+  }\r
+\r
+  return EFI_SUCCESS;\r
+\r
+}\r
+\r
+/**\r
+  Convert a *.BMP graphics image to a GOP blt buffer. If a NULL Blt buffer\r
+  is passed in a GopBlt buffer will be allocated by this routine. If a GopBlt\r
+  buffer is passed in it will be used if it is big enough.\r
+\r
+  @param  BmpImage      Pointer to BMP file\r
+  @param  BmpImageSize  Number of bytes in BmpImage\r
+  @param  GopBlt        Buffer containing GOP version of BmpImage.\r
+  @param  GopBltSize    Size of GopBlt in bytes.\r
+  @param  PixelHeight   Height of GopBlt/BmpImage in pixels\r
+  @param  PixelWidth    Width of GopBlt/BmpImage in pixels\r
+\r
+  @retval EFI_SUCCESS           GopBlt and GopBltSize are returned.\r
+  @retval EFI_UNSUPPORTED       BmpImage is not a valid *.BMP image\r
+  @retval EFI_BUFFER_TOO_SMALL  The passed in GopBlt buffer is not big enough.\r
+                                GopBltSize will contain the required size.\r
+  @retval EFI_OUT_OF_RESOURCES  No enough buffer to allocate.\r
+\r
+**/\r
+EFI_STATUS\r
+ConvertBmpToGopBlt (\r
+  IN     VOID      *BmpImage,\r
+  IN     UINTN     BmpImageSize,\r
+  IN OUT VOID      **GopBlt,\r
+  IN OUT UINTN     *GopBltSize,\r
+     OUT UINTN     *PixelHeight,\r
+     OUT UINTN     *PixelWidth\r
+  )\r
+{\r
+  UINT8                         *Image;\r
+  UINT8                         *ImageHeader;\r
+  BMP_IMAGE_HEADER              *BmpHeader;\r
+  BMP_COLOR_MAP                 *BmpColorMap;\r
+  EFI_GRAPHICS_OUTPUT_BLT_PIXEL *BltBuffer;\r
+  EFI_GRAPHICS_OUTPUT_BLT_PIXEL *Blt;\r
+  UINT64                        BltBufferSize;\r
+  UINTN                         Index;\r
+  UINTN                         Height;\r
+  UINTN                         Width;\r
+  UINTN                         ImageIndex;\r
+  UINT32                        DataSizePerLine;\r
+  BOOLEAN                       IsAllocated;\r
+  UINT32                        ColorMapNum;\r
+\r
+  if (sizeof (BMP_IMAGE_HEADER) > BmpImageSize) {\r
+    return EFI_INVALID_PARAMETER;\r
+  }\r
+\r
+  BmpHeader = (BMP_IMAGE_HEADER *) BmpImage;\r
+\r
+  if (BmpHeader->CharB != 'B' || BmpHeader->CharM != 'M') {\r
+    return EFI_UNSUPPORTED;\r
+  }\r
+\r
+  //\r
+  // Doesn't support compress.\r
+  //\r
+  if (BmpHeader->CompressionType != 0) {\r
+    return EFI_UNSUPPORTED;\r
+  }\r
+\r
+  //\r
+  // Only support BITMAPINFOHEADER format.\r
+  // BITMAPFILEHEADER + BITMAPINFOHEADER = BMP_IMAGE_HEADER\r
+  //\r
+  if (BmpHeader->HeaderSize != sizeof (BMP_IMAGE_HEADER) - OFFSET_OF(BMP_IMAGE_HEADER, HeaderSize)) {\r
+    return EFI_UNSUPPORTED;\r
+  }\r
+\r
+  //\r
+  // The data size in each line must be 4 byte alignment.\r
+  //\r
+  DataSizePerLine = ((BmpHeader->PixelWidth * BmpHeader->BitPerPixel + 31) >> 3) & (~0x3);\r
+  BltBufferSize = MultU64x32 (DataSizePerLine, BmpHeader->PixelHeight);\r
+  if (BltBufferSize > (UINT32) ~0) {\r
+    return EFI_INVALID_PARAMETER;\r
+  }\r
+\r
+  if ((BmpHeader->Size != BmpImageSize) || \r
+      (BmpHeader->Size < BmpHeader->ImageOffset) ||\r
+      (BmpHeader->Size - BmpHeader->ImageOffset !=  BmpHeader->PixelHeight * DataSizePerLine)) {\r
+    return EFI_INVALID_PARAMETER;\r
+  }\r
+\r
+  //\r
+  // Calculate Color Map offset in the image.\r
+  //\r
+  Image       = BmpImage;\r
+  BmpColorMap = (BMP_COLOR_MAP *) (Image + sizeof (BMP_IMAGE_HEADER));\r
+  if (BmpHeader->ImageOffset < sizeof (BMP_IMAGE_HEADER)) {\r
+    return EFI_INVALID_PARAMETER;\r
+  }\r
+\r
+  if (BmpHeader->ImageOffset > sizeof (BMP_IMAGE_HEADER)) {\r
+    switch (BmpHeader->BitPerPixel) {\r
+      case 1:\r
+        ColorMapNum = 2;\r
+        break;\r
+      case 4:\r
+        ColorMapNum = 16;\r
+        break;\r
+      case 8:\r
+        ColorMapNum = 256;\r
+        break;\r
+      default:\r
+        ColorMapNum = 0;\r
+        break;\r
+      }\r
+    //\r
+    // BMP file may has padding data between the bmp header section and the bmp data section.\r
+    //\r
+    if (BmpHeader->ImageOffset - sizeof (BMP_IMAGE_HEADER) < sizeof (BMP_COLOR_MAP) * ColorMapNum) {\r
+      return EFI_INVALID_PARAMETER;\r
+    }\r
+  }\r
+\r
+  //\r
+  // Calculate graphics image data address in the image\r
+  //\r
+  Image         = ((UINT8 *) BmpImage) + BmpHeader->ImageOffset;\r
+  ImageHeader   = Image;\r
+\r
+  //\r
+  // Calculate the BltBuffer needed size.\r
+  //\r
+  BltBufferSize = MultU64x32 ((UINT64) BmpHeader->PixelWidth, BmpHeader->PixelHeight);\r
+  //\r
+  // Ensure the BltBufferSize * sizeof (EFI_GRAPHICS_OUTPUT_BLT_PIXEL) doesn't overflow\r
+  //\r
+  if (BltBufferSize > DivU64x32 ((UINTN) ~0, sizeof (EFI_GRAPHICS_OUTPUT_BLT_PIXEL))) {\r
+    return EFI_UNSUPPORTED;\r
+  }\r
+  BltBufferSize = MultU64x32 (BltBufferSize, sizeof (EFI_GRAPHICS_OUTPUT_BLT_PIXEL));\r
+\r
+  IsAllocated   = FALSE;\r
+  if (*GopBlt == NULL) {\r
+    //\r
+    // GopBlt is not allocated by caller.\r
+    //\r
+    *GopBltSize = (UINTN) BltBufferSize;\r
+    *GopBlt     = AllocatePool (*GopBltSize);\r
+    IsAllocated = TRUE;\r
+    if (*GopBlt == NULL) {\r
+      return EFI_OUT_OF_RESOURCES;\r
+    }\r
+  } else {\r
+    //\r
+    // GopBlt has been allocated by caller.\r
+    //\r
+    if (*GopBltSize < (UINTN) BltBufferSize) {\r
+      *GopBltSize = (UINTN) BltBufferSize;\r
+      return EFI_BUFFER_TOO_SMALL;\r
+    }\r
+  }\r
+\r
+  *PixelWidth   = BmpHeader->PixelWidth;\r
+  *PixelHeight  = BmpHeader->PixelHeight;\r
+\r
+  //\r
+  // Convert image from BMP to Blt buffer format\r
+  //\r
+  BltBuffer = *GopBlt;\r
+  for (Height = 0; Height < BmpHeader->PixelHeight; Height++) {\r
+    Blt = &BltBuffer[(BmpHeader->PixelHeight - Height - 1) * BmpHeader->PixelWidth];\r
+    for (Width = 0; Width < BmpHeader->PixelWidth; Width++, Image++, Blt++) {\r
+      switch (BmpHeader->BitPerPixel) {\r
+      case 1:\r
+        //\r
+        // Convert 1-bit (2 colors) BMP to 24-bit color\r
+        //\r
+        for (Index = 0; Index < 8 && Width < BmpHeader->PixelWidth; Index++) {\r
+          Blt->Red    = BmpColorMap[((*Image) >> (7 - Index)) & 0x1].Red;\r
+          Blt->Green  = BmpColorMap[((*Image) >> (7 - Index)) & 0x1].Green;\r
+          Blt->Blue   = BmpColorMap[((*Image) >> (7 - Index)) & 0x1].Blue;\r
+          Blt++;\r
+          Width++;\r
+        }\r
+\r
+        Blt--;\r
+        Width--;\r
+        break;\r
+\r
+      case 4:\r
+        //\r
+        // Convert 4-bit (16 colors) BMP Palette to 24-bit color\r
+        //\r
+        Index       = (*Image) >> 4;\r
+        Blt->Red    = BmpColorMap[Index].Red;\r
+        Blt->Green  = BmpColorMap[Index].Green;\r
+        Blt->Blue   = BmpColorMap[Index].Blue;\r
+        if (Width < (BmpHeader->PixelWidth - 1)) {\r
+          Blt++;\r
+          Width++;\r
+          Index       = (*Image) & 0x0f;\r
+          Blt->Red    = BmpColorMap[Index].Red;\r
+          Blt->Green  = BmpColorMap[Index].Green;\r
+          Blt->Blue   = BmpColorMap[Index].Blue;\r
+        }\r
+        break;\r
+\r
+      case 8:\r
+        //\r
+        // Convert 8-bit (256 colors) BMP Palette to 24-bit color\r
+        //\r
+        Blt->Red    = BmpColorMap[*Image].Red;\r
+        Blt->Green  = BmpColorMap[*Image].Green;\r
+        Blt->Blue   = BmpColorMap[*Image].Blue;\r
+        break;\r
+\r
+      case 24:\r
+        //\r
+        // It is 24-bit BMP.\r
+        //\r
+        Blt->Blue   = *Image++;\r
+        Blt->Green  = *Image++;\r
+        Blt->Red    = *Image;\r
+        break;\r
+\r
+      default:\r
+        //\r
+        // Other bit format BMP is not supported.\r
+        //\r
+        if (IsAllocated) {\r
+          FreePool (*GopBlt);\r
+          *GopBlt = NULL;\r
+        }\r
+        return EFI_UNSUPPORTED;\r
+        break;\r
+      };\r
+\r
+    }\r
+\r
+    ImageIndex = (UINTN) (Image - ImageHeader);\r
+    if ((ImageIndex % 4) != 0) {\r
+      //\r
+      // Bmp Image starts each row on a 32-bit boundary!\r
+      //\r
+      Image = Image + (4 - (ImageIndex % 4));\r
+    }\r
+  }\r
+\r
+  return EFI_SUCCESS;\r
+}\r
+\r
+/**\r
+  Use SystemTable Conout to stop video based Simple Text Out consoles from going\r
+  to the video device. Put up LogoFile on every video device that is a console.\r
+\r
+  @param[in]  LogoFile   File name of logo to display on the center of the screen.\r
+\r
+  @retval EFI_SUCCESS     ConsoleControl has been flipped to graphics and logo displayed.\r
+  @retval EFI_UNSUPPORTED Logo not found\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+EnableQuietBoot (\r
+  IN  EFI_GUID  *LogoFile\r
+  )\r
+{\r
+  EFI_STATUS                    Status;\r
+  EFI_OEM_BADGING_PROTOCOL      *Badging;\r
+  UINT32                        SizeOfX;\r
+  UINT32                        SizeOfY;\r
+  INTN                          DestX;\r
+  INTN                          DestY;\r
+  UINT8                         *ImageData;\r
+  UINTN                         ImageSize;\r
+  UINTN                         BltSize;\r
+  UINT32                        Instance;\r
+  EFI_BADGING_FORMAT            Format;\r
+  EFI_BADGING_DISPLAY_ATTRIBUTE Attribute;\r
+  UINTN                         CoordinateX;\r
+  UINTN                         CoordinateY;\r
+  UINTN                         Height;\r
+  UINTN                         Width;\r
+  EFI_GRAPHICS_OUTPUT_BLT_PIXEL *Blt;\r
+  EFI_UGA_DRAW_PROTOCOL         *UgaDraw;\r
+  UINT32                        ColorDepth;\r
+  UINT32                        RefreshRate;\r
+  EFI_GRAPHICS_OUTPUT_PROTOCOL  *GraphicsOutput;\r
+  EFI_BOOT_LOGO_PROTOCOL        *BootLogo;\r
+  UINTN                         NumberOfLogos;\r
+  EFI_GRAPHICS_OUTPUT_BLT_PIXEL *LogoBlt;\r
+  UINTN                         LogoDestX;\r
+  UINTN                         LogoDestY;\r
+  UINTN                         LogoHeight;\r
+  UINTN                         LogoWidth;\r
+  UINTN                         NewDestX;\r
+  UINTN                         NewDestY;\r
+  UINTN                         NewHeight;\r
+  UINTN                         NewWidth;\r
+  UINT64                        BufferSize;\r
+\r
+  UgaDraw = NULL;\r
+  //\r
+  // Try to open GOP first\r
+  //\r
+  Status = gBS->HandleProtocol (gST->ConsoleOutHandle, &gEfiGraphicsOutputProtocolGuid, (VOID **) &GraphicsOutput);\r
+  if (EFI_ERROR (Status) && FeaturePcdGet (PcdUgaConsumeSupport)) {\r
+    GraphicsOutput = NULL;\r
+    //\r
+    // Open GOP failed, try to open UGA\r
+    //\r
+    Status = gBS->HandleProtocol (gST->ConsoleOutHandle, &gEfiUgaDrawProtocolGuid, (VOID **) &UgaDraw);\r
+  }\r
+  if (EFI_ERROR (Status)) {\r
+    return EFI_UNSUPPORTED;\r
+  }\r
+\r
+  //\r
+  // Try to open Boot Logo Protocol.\r
+  //\r
+  BootLogo = NULL;\r
+  gBS->LocateProtocol (&gEfiBootLogoProtocolGuid, NULL, (VOID **) &BootLogo);\r
+\r
+  //\r
+  // Erase Cursor from screen\r
+  //\r
+  gST->ConOut->EnableCursor (gST->ConOut, FALSE);\r
+\r
+  Badging = NULL;\r
+  Status  = gBS->LocateProtocol (&gEfiOEMBadgingProtocolGuid, NULL, (VOID **) &Badging);\r
+\r
+  if (GraphicsOutput != NULL) {\r
+    SizeOfX = GraphicsOutput->Mode->Info->HorizontalResolution;\r
+    SizeOfY = GraphicsOutput->Mode->Info->VerticalResolution;\r
+\r
+  } else if (UgaDraw != NULL && FeaturePcdGet (PcdUgaConsumeSupport)) {\r
+    Status = UgaDraw->GetMode (UgaDraw, &SizeOfX, &SizeOfY, &ColorDepth, &RefreshRate);\r
+    if (EFI_ERROR (Status)) {\r
+      return EFI_UNSUPPORTED;\r
+    }\r
+  } else {\r
+    return EFI_UNSUPPORTED;\r
+  }\r
+\r
+  Blt = NULL;\r
+  NumberOfLogos = 0;\r
+  LogoDestX = 0;\r
+  LogoDestY = 0;\r
+  LogoHeight = 0;\r
+  LogoWidth = 0;\r
+  NewDestX = 0;\r
+  NewDestY = 0;\r
+  NewHeight = 0;\r
+  NewWidth = 0;\r
+  Instance = 0;\r
+  while (1) {\r
+    ImageData = NULL;\r
+    ImageSize = 0;\r
+\r
+    if (Badging != NULL) {\r
+      //\r
+      // Get image from OEMBadging protocol.\r
+      //\r
+      Status = Badging->GetImage (\r
+                          Badging,\r
+                          &Instance,\r
+                          &Format,\r
+                          &ImageData,\r
+                          &ImageSize,\r
+                          &Attribute,\r
+                          &CoordinateX,\r
+                          &CoordinateY\r
+                          );\r
+      if (EFI_ERROR (Status)) {\r
+        goto Done;\r
+      }\r
+\r
+      //\r
+      // Currently only support BMP format.\r
+      //\r
+      if (Format != EfiBadgingFormatBMP) {\r
+        if (ImageData != NULL) {\r
+          FreePool (ImageData);\r
+        }\r
+        continue;\r
+      }\r
+    } else {\r
+      //\r
+      // Get the specified image from FV.\r
+      //\r
+      Status = GetSectionFromAnyFv (LogoFile, EFI_SECTION_RAW, 0, (VOID **) &ImageData, &ImageSize);\r
+      if (EFI_ERROR (Status)) {\r
+        return EFI_UNSUPPORTED;\r
+      }\r
+\r
+      CoordinateX = 0;\r
+      CoordinateY = 0;\r
+      if (!FeaturePcdGet(PcdBootlogoOnlyEnable)) {\r
+        Attribute   = EfiBadgingDisplayAttributeCenter;\r
+      } else {\r
+        Attribute   = EfiBadgingDisplayAttributeCustomized;\r
+      } \r
+    }\r
+\r
+    if (Blt != NULL) {\r
+      FreePool (Blt);\r
+    }\r
+    Blt = NULL;\r
+    Status = ConvertBmpToGopBlt (\r
+              ImageData,\r
+              ImageSize,\r
+              (VOID **) &Blt,\r
+              &BltSize,\r
+              &Height,\r
+              &Width\r
+              );\r
+    if (EFI_ERROR (Status)) {\r
+      FreePool (ImageData);\r
+\r
+      if (Badging == NULL) {\r
+        return Status;\r
+      } else {\r
+        continue;\r
+      }\r
+    }\r
+\r
+    //\r
+    // Calculate the display position according to Attribute.\r
+    //\r
+    switch (Attribute) {\r
+    case EfiBadgingDisplayAttributeLeftTop:\r
+      DestX = CoordinateX;\r
+      DestY = CoordinateY;\r
+      break;\r
+\r
+    case EfiBadgingDisplayAttributeCenterTop:\r
+      DestX = (SizeOfX - Width) / 2;\r
+      DestY = CoordinateY;\r
+      break;\r
+\r
+    case EfiBadgingDisplayAttributeRightTop:\r
+      DestX = (SizeOfX - Width - CoordinateX);\r
+      DestY = CoordinateY;;\r
+      break;\r
+\r
+    case EfiBadgingDisplayAttributeCenterRight:\r
+      DestX = (SizeOfX - Width - CoordinateX);\r
+      DestY = (SizeOfY - Height) / 2;\r
+      break;\r
+\r
+    case EfiBadgingDisplayAttributeRightBottom:\r
+      DestX = (SizeOfX - Width - CoordinateX);\r
+      DestY = (SizeOfY - Height - CoordinateY);\r
+      break;\r
+\r
+    case EfiBadgingDisplayAttributeCenterBottom:\r
+      DestX = (SizeOfX - Width) / 2;\r
+      DestY = (SizeOfY - Height - CoordinateY);\r
+      break;\r
+\r
+    case EfiBadgingDisplayAttributeLeftBottom:\r
+      DestX = CoordinateX;\r
+      DestY = (SizeOfY - Height - CoordinateY);\r
+      break;\r
+\r
+    case EfiBadgingDisplayAttributeCenterLeft:\r
+      DestX = CoordinateX;\r
+      DestY = (SizeOfY - Height) / 2;\r
+      break;\r
+\r
+    case EfiBadgingDisplayAttributeCenter:\r
+      DestX = (SizeOfX - Width) / 2;\r
+      DestY = (SizeOfY - Height) / 2;\r
+      break;\r
+\r
+    case EfiBadgingDisplayAttributeCustomized:\r
+      DestX = (SizeOfX - Width) / 2;\r
+      DestY = ((SizeOfY * 382) / 1000) - Height / 2;\r
+      break;\r
+\r
+    default:\r
+      DestX = CoordinateX;\r
+      DestY = CoordinateY;\r
+      break;\r
+    }\r
+\r
+    if ((DestX >= 0) && (DestY >= 0)) {\r
+      if (GraphicsOutput != NULL) {\r
+        Status = GraphicsOutput->Blt (\r
+                            GraphicsOutput,\r
+                            Blt,\r
+                            EfiBltBufferToVideo,\r
+                            0,\r
+                            0,\r
+                            (UINTN) DestX,\r
+                            (UINTN) DestY,\r
+                            Width,\r
+                            Height,\r
+                            Width * sizeof (EFI_GRAPHICS_OUTPUT_BLT_PIXEL)\r
+                            );\r
+      } else if (UgaDraw != NULL && FeaturePcdGet (PcdUgaConsumeSupport)) {\r
+        Status = UgaDraw->Blt (\r
+                            UgaDraw,\r
+                            (EFI_UGA_PIXEL *) Blt,\r
+                            EfiUgaBltBufferToVideo,\r
+                            0,\r
+                            0,\r
+                            (UINTN) DestX,\r
+                            (UINTN) DestY,\r
+                            Width,\r
+                            Height,\r
+                            Width * sizeof (EFI_UGA_PIXEL)\r
+                            );\r
+      } else {\r
+        Status = EFI_UNSUPPORTED;\r
+      }\r
+\r
+      //\r
+      // Report displayed Logo information.\r
+      //\r
+      if (!EFI_ERROR (Status)) {\r
+        NumberOfLogos++;\r
+\r
+        if (LogoWidth == 0) {\r
+          //\r
+          // The first Logo.\r
+          //\r
+          LogoDestX = (UINTN) DestX;\r
+          LogoDestY = (UINTN) DestY;\r
+          LogoWidth = Width;\r
+          LogoHeight = Height;\r
+        } else {\r
+          //\r
+          // Merge new logo with old one.\r
+          //\r
+          NewDestX = MIN ((UINTN) DestX, LogoDestX);\r
+          NewDestY = MIN ((UINTN) DestY, LogoDestY);\r
+          NewWidth = MAX ((UINTN) DestX + Width, LogoDestX + LogoWidth) - NewDestX;\r
+          NewHeight = MAX ((UINTN) DestY + Height, LogoDestY + LogoHeight) - NewDestY;\r
+\r
+          LogoDestX = NewDestX;\r
+          LogoDestY = NewDestY;\r
+          LogoWidth = NewWidth;\r
+          LogoHeight = NewHeight;\r
+        }\r
+      }\r
+    }\r
+\r
+    FreePool (ImageData);\r
+\r
+    if (Badging == NULL) {\r
+      break;\r
+    }\r
+  }\r
+\r
+Done:\r
+  if (BootLogo == NULL || NumberOfLogos == 0) {\r
+    //\r
+    // No logo displayed.\r
+    //\r
+    if (Blt != NULL) {\r
+      FreePool (Blt);\r
+    }\r
+\r
+    return Status;\r
+  }\r
+\r
+  //\r
+  // Advertise displayed Logo information.\r
+  //\r
+  if (NumberOfLogos == 1) {\r
+    //\r
+    // Only one logo displayed, use its Blt buffer directly for BootLogo protocol.\r
+    //\r
+    LogoBlt = Blt;\r
+    Status = EFI_SUCCESS;\r
+  } else {\r
+    //\r
+    // More than one Logo displayed, get merged BltBuffer using VideoToBuffer operation. \r
+    //\r
+    if (Blt != NULL) {\r
+      FreePool (Blt);\r
+    }\r
+\r
+    //\r
+    // Ensure the LogoHeight * LogoWidth doesn't overflow\r
+    //\r
+    if (LogoHeight > DivU64x64Remainder ((UINTN) ~0, LogoWidth, NULL)) {\r
+      return EFI_UNSUPPORTED;\r
+    }\r
+    BufferSize = MultU64x64 (LogoWidth, LogoHeight);\r
+\r
+    //\r
+    // Ensure the BufferSize * sizeof (EFI_GRAPHICS_OUTPUT_BLT_PIXEL) doesn't overflow\r
+    //\r
+    if (BufferSize > DivU64x32 ((UINTN) ~0, sizeof (EFI_GRAPHICS_OUTPUT_BLT_PIXEL))) {\r
+      return EFI_UNSUPPORTED;\r
+    }\r
+\r
+    LogoBlt = AllocateZeroPool ((UINTN)BufferSize * sizeof (EFI_GRAPHICS_OUTPUT_BLT_PIXEL));\r
+    if (LogoBlt == NULL) {\r
+      return EFI_OUT_OF_RESOURCES;\r
+    }\r
+\r
+    if (GraphicsOutput != NULL) {\r
+      Status = GraphicsOutput->Blt (\r
+                          GraphicsOutput,\r
+                          LogoBlt,\r
+                          EfiBltVideoToBltBuffer,\r
+                          LogoDestX,\r
+                          LogoDestY,\r
+                          0,\r
+                          0,\r
+                          LogoWidth,\r
+                          LogoHeight,\r
+                          LogoWidth * sizeof (EFI_GRAPHICS_OUTPUT_BLT_PIXEL)\r
+                          );\r
+    } else if (UgaDraw != NULL && FeaturePcdGet (PcdUgaConsumeSupport)) {\r
+      Status = UgaDraw->Blt (\r
+                          UgaDraw,\r
+                          (EFI_UGA_PIXEL *) LogoBlt,\r
+                          EfiUgaVideoToBltBuffer,\r
+                          LogoDestX,\r
+                          LogoDestY,\r
+                          0,\r
+                          0,\r
+                          LogoWidth,\r
+                          LogoHeight,\r
+                          LogoWidth * sizeof (EFI_UGA_PIXEL)\r
+                          );\r
+    } else {\r
+      Status = EFI_UNSUPPORTED;\r
+    }\r
+  }\r
+\r
+  if (!EFI_ERROR (Status)) {\r
+    BootLogo->SetBootLogo (BootLogo, LogoBlt, LogoDestX, LogoDestY, LogoWidth, LogoHeight);\r
+  }\r
+  FreePool (LogoBlt);\r
+\r
+  return Status;\r
+}\r
+\r
+/**\r
+  Use SystemTable Conout to turn on video based Simple Text Out consoles. The \r
+  Simple Text Out screens will now be synced up with all non video output devices\r
+\r
+  @retval EFI_SUCCESS     UGA devices are back in text mode and synced up.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+DisableQuietBoot (\r
+  VOID\r
+  )\r
+{\r
+\r
+  //\r
+  // Enable Cursor on Screen\r
+  //\r
+  gST->ConOut->EnableCursor (gST->ConOut, TRUE);\r
+  return EFI_SUCCESS;\r
+}\r
+\r

diff --git a/Vlv2TbltDevicePkg/Override/IntelFrameworkModulePkg/Library/GenericBdsLib/BdsMisc.c b/Vlv2TbltDevicePkg/Override/IntelFrameworkModulePkg/Library/GenericBdsLib/BdsMisc.c
new file mode 100644 (file)
index 0000000..971188b
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Override/IntelFrameworkModulePkg/Library/GenericBdsLib/BdsMisc.c
@@ -0,0 +1,1484 @@
+/** @file\r
+  Misc BDS library function\r
+\r
+Copyright (c) 2004 - 2012, Intel Corporation. All rights reserved.<BR>\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution.  The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#include "InternalBdsLib.h"\r
+\r
+\r
+#define MAX_STRING_LEN        200\r
+\r
+BOOLEAN   mFeaturerSwitch = TRUE;\r
+BOOLEAN   mResetRequired  = FALSE;\r
+\r
+extern UINT16 gPlatformBootTimeOutDefault;\r
+\r
+/**\r
+  The function will go through the driver option link list, load and start\r
+  every driver the driver option device path point to.\r
+\r
+  @param  BdsDriverLists        The header of the current driver option link list\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+BdsLibLoadDrivers (\r
+  IN LIST_ENTRY                   *BdsDriverLists\r
+  )\r
+{\r
+  EFI_STATUS                Status;\r
+  LIST_ENTRY                *Link;\r
+  BDS_COMMON_OPTION         *Option;\r
+  EFI_HANDLE                ImageHandle;\r
+  EFI_LOADED_IMAGE_PROTOCOL *ImageInfo;\r
+  UINTN                     ExitDataSize;\r
+  CHAR16                    *ExitData;\r
+  BOOLEAN                   ReconnectAll;\r
+\r
+  ReconnectAll = FALSE;\r
+\r
+  //\r
+  // Process the driver option\r
+  //\r
+  for (Link = BdsDriverLists->ForwardLink; Link != BdsDriverLists; Link = Link->ForwardLink) {\r
+    Option = CR (Link, BDS_COMMON_OPTION, Link, BDS_LOAD_OPTION_SIGNATURE);\r
+    \r
+    //\r
+    // If a load option is not marked as LOAD_OPTION_ACTIVE,\r
+    // the boot manager will not automatically load the option.\r
+    //\r
+    if (!IS_LOAD_OPTION_TYPE (Option->Attribute, LOAD_OPTION_ACTIVE)) {\r
+      continue;\r
+    }\r
+    \r
+    //\r
+    // If a driver load option is marked as LOAD_OPTION_FORCE_RECONNECT,\r
+    // then all of the EFI drivers in the system will be disconnected and\r
+    // reconnected after the last driver load option is processed.\r
+    //\r
+    if (IS_LOAD_OPTION_TYPE (Option->Attribute, LOAD_OPTION_FORCE_RECONNECT)) {\r
+      ReconnectAll = TRUE;\r
+    }\r
+    \r
+    //\r
+    // Make sure the driver path is connected.\r
+    //\r
+    BdsLibConnectDevicePath (Option->DevicePath);\r
+\r
+    //\r
+    // Load and start the image that Driver#### describes\r
+    //\r
+    Status = gBS->LoadImage (\r
+                    FALSE,\r
+                    gImageHandle,\r
+                    Option->DevicePath,\r
+                    NULL,\r
+                    0,\r
+                    &ImageHandle\r
+                    );\r
+\r
+    if (!EFI_ERROR (Status)) {\r
+      gBS->HandleProtocol (ImageHandle, &gEfiLoadedImageProtocolGuid, (VOID **) &ImageInfo);\r
+\r
+      //\r
+      // Verify whether this image is a driver, if not,\r
+      // exit it and continue to parse next load option\r
+      //\r
+      if (ImageInfo->ImageCodeType != EfiBootServicesCode && ImageInfo->ImageCodeType != EfiRuntimeServicesCode) {\r
+        gBS->Exit (ImageHandle, EFI_INVALID_PARAMETER, 0, NULL);\r
+        continue;\r
+      }\r
+\r
+      if (Option->LoadOptionsSize != 0) {\r
+        ImageInfo->LoadOptionsSize  = Option->LoadOptionsSize;\r
+        ImageInfo->LoadOptions      = Option->LoadOptions;\r
+      }\r
+      //\r
+      // Before calling the image, enable the Watchdog Timer for\r
+      // the 5 Minute period\r
+      //\r
+      gBS->SetWatchdogTimer (5 * 60, 0x0000, 0x00, NULL);\r
+\r
+      Status = gBS->StartImage (ImageHandle, &ExitDataSize, &ExitData);\r
+      DEBUG ((DEBUG_INFO | DEBUG_LOAD, "Driver Return Status = %r\n", Status));\r
+\r
+      //\r
+      // Clear the Watchdog Timer after the image returns\r
+      //\r
+      gBS->SetWatchdogTimer (0x0000, 0x0000, 0x0000, NULL);\r
+    }\r
+  }\r
+  \r
+  //\r
+  // Process the LOAD_OPTION_FORCE_RECONNECT driver option\r
+  //\r
+  if (ReconnectAll) {\r
+    BdsLibDisconnectAllEfi ();\r
+    BdsLibConnectAll ();\r
+  }\r
+\r
+}\r
+\r
+/**\r
+  Get the Option Number that does not used.\r
+  Try to locate the specific option variable one by one utile find a free number.\r
+\r
+  @param  VariableName          Indicate if the boot#### or driver#### option\r
+\r
+  @return The Minimal Free Option Number\r
+\r
+**/\r
+UINT16\r
+BdsLibGetFreeOptionNumber (\r
+  IN  CHAR16    *VariableName\r
+  )\r
+{\r
+  UINTN         Index;\r
+  CHAR16        StrTemp[10];\r
+  UINT16        *OptionBuffer;\r
+  UINTN         OptionSize;\r
+\r
+  //\r
+  // Try to find the minimum free number from 0, 1, 2, 3....\r
+  //\r
+  Index = 0;\r
+  do {\r
+    if (*VariableName == 'B') {\r
+      UnicodeSPrint (StrTemp, sizeof (StrTemp), L"Boot%04x", Index);\r
+    } else {\r
+      UnicodeSPrint (StrTemp, sizeof (StrTemp), L"Driver%04x", Index);\r
+    }\r
+    //\r
+    // try if the option number is used\r
+    //\r
+    OptionBuffer = BdsLibGetVariableAndSize (\r
+                     StrTemp,\r
+                     &gEfiGlobalVariableGuid,\r
+                     &OptionSize\r
+                     );\r
+    if (OptionBuffer == NULL) {\r
+      break;\r
+    }\r
+    Index++;\r
+  } while (TRUE);\r
+\r
+  return ((UINT16) Index);\r
+}\r
+\r
+\r
+/**\r
+  This function will register the new boot#### or driver#### option base on\r
+  the VariableName. The new registered boot#### or driver#### will be linked\r
+  to BdsOptionList and also update to the VariableName. After the boot#### or\r
+  driver#### updated, the BootOrder or DriverOrder will also be updated.\r
+\r
+  @param  BdsOptionList         The header of the boot#### or driver#### link list\r
+  @param  DevicePath            The device path which the boot#### or driver####\r
+                                option present\r
+  @param  String                The description of the boot#### or driver####\r
+  @param  VariableName          Indicate if the boot#### or driver#### option\r
+\r
+  @retval EFI_SUCCESS           The boot#### or driver#### have been success\r
+                                registered\r
+  @retval EFI_STATUS            Return the status of gRT->SetVariable ().\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+BdsLibRegisterNewOption (\r
+  IN  LIST_ENTRY                     *BdsOptionList,\r
+  IN  EFI_DEVICE_PATH_PROTOCOL       *DevicePath,\r
+  IN  CHAR16                         *String,\r
+  IN  CHAR16                         *VariableName\r
+  )\r
+{\r
+  EFI_STATUS                Status;\r
+  UINTN                     Index;\r
+  UINT16                    RegisterOptionNumber;\r
+  UINT16                    *TempOptionPtr;\r
+  UINTN                     TempOptionSize;\r
+  UINT16                    *OptionOrderPtr;\r
+  VOID                      *OptionPtr;\r
+  UINTN                     OptionSize;\r
+  UINT8                     *TempPtr;\r
+  EFI_DEVICE_PATH_PROTOCOL  *OptionDevicePath;\r
+  CHAR16                    *Description;\r
+  CHAR16                    OptionName[10];\r
+  BOOLEAN                   UpdateDescription;\r
+  UINT16                    BootOrderEntry;\r
+  UINTN                     OrderItemNum;\r
+\r
+\r
+  OptionPtr             = NULL;\r
+  OptionSize            = 0;\r
+  TempPtr               = NULL;\r
+  OptionDevicePath      = NULL;\r
+  Description           = NULL;\r
+  OptionOrderPtr        = NULL;\r
+  UpdateDescription     = FALSE;\r
+  Status                = EFI_SUCCESS;\r
+  ZeroMem (OptionName, sizeof (OptionName));\r
+\r
+  TempOptionSize = 0;\r
+  TempOptionPtr = BdsLibGetVariableAndSize (\r
+                    VariableName,\r
+                    &gEfiGlobalVariableGuid,\r
+                    &TempOptionSize\r
+                    );\r
+  //\r
+  // Compare with current option variable if the previous option is set in global variable.\r
+  //\r
+  for (Index = 0; Index < TempOptionSize / sizeof (UINT16); Index++) {\r
+    //\r
+    // TempOptionPtr must not be NULL if we have non-zero TempOptionSize.\r
+    //\r
+    ASSERT (TempOptionPtr != NULL);\r
+\r
+    if (*VariableName == 'B') {\r
+      UnicodeSPrint (OptionName, sizeof (OptionName), L"Boot%04x", TempOptionPtr[Index]);\r
+    } else {\r
+      UnicodeSPrint (OptionName, sizeof (OptionName), L"Driver%04x", TempOptionPtr[Index]);\r
+    }\r
+\r
+    OptionPtr = BdsLibGetVariableAndSize (\r
+                  OptionName,\r
+                  &gEfiGlobalVariableGuid,\r
+                  &OptionSize\r
+                  );\r
+    if (OptionPtr == NULL) {\r
+      continue;\r
+    }\r
+\r
+    //\r
+    // Validate the variable.\r
+    //\r
+    if (!ValidateOption(OptionPtr, OptionSize)) {\r
+      continue;\r
+    }\r
+\r
+    TempPtr         =   OptionPtr;\r
+    TempPtr         +=  sizeof (UINT32) + sizeof (UINT16);\r
+    Description     =   (CHAR16 *) TempPtr;\r
+    TempPtr         +=  StrSize ((CHAR16 *) TempPtr);\r
+    OptionDevicePath =  (EFI_DEVICE_PATH_PROTOCOL *) TempPtr;\r
+\r
+    //\r
+    // Notes: the description may will change base on the GetStringToken\r
+    //\r
+    if (CompareMem (OptionDevicePath, DevicePath, GetDevicePathSize (OptionDevicePath)) == 0) {\r
+      if (CompareMem (Description, String, StrSize (Description)) == 0) { \r
+        //\r
+        // Got the option, so just return\r
+        //\r
+        FreePool (OptionPtr);\r
+        FreePool (TempOptionPtr);\r
+        return EFI_SUCCESS;\r
+      } else {\r
+        //\r
+        // Option description changed, need update.\r
+        //\r
+        UpdateDescription = TRUE;\r
+        FreePool (OptionPtr);\r
+        break;\r
+      }\r
+    }\r
+\r
+    FreePool (OptionPtr);\r
+  }\r
+\r
+  OptionSize          = sizeof (UINT32) + sizeof (UINT16) + StrSize (String);\r
+  OptionSize          += GetDevicePathSize (DevicePath);\r
+  OptionPtr           = AllocateZeroPool (OptionSize);\r
+  ASSERT (OptionPtr != NULL);\r
+  \r
+  TempPtr             = OptionPtr;\r
+  *(UINT32 *) TempPtr = LOAD_OPTION_ACTIVE;\r
+  TempPtr             += sizeof (UINT32);\r
+  *(UINT16 *) TempPtr = (UINT16) GetDevicePathSize (DevicePath);\r
+  TempPtr             += sizeof (UINT16);\r
+  CopyMem (TempPtr, String, StrSize (String));\r
+  TempPtr             += StrSize (String);\r
+  CopyMem (TempPtr, DevicePath, GetDevicePathSize (DevicePath));\r
+\r
+  if (UpdateDescription) {\r
+    //\r
+    // The number in option#### to be updated. \r
+    // In this case, we must have non-NULL TempOptionPtr.\r
+    //\r
+    ASSERT (TempOptionPtr != NULL);\r
+    RegisterOptionNumber = TempOptionPtr[Index];\r
+  } else {\r
+    //\r
+    // The new option#### number\r
+    //\r
+    RegisterOptionNumber = BdsLibGetFreeOptionNumber(VariableName);\r
+  }\r
+\r
+  if (*VariableName == 'B') {\r
+    UnicodeSPrint (OptionName, sizeof (OptionName), L"Boot%04x", RegisterOptionNumber);\r
+  } else {\r
+    UnicodeSPrint (OptionName, sizeof (OptionName), L"Driver%04x", RegisterOptionNumber);\r
+  }\r
+\r
+  Status = gRT->SetVariable (\r
+                  OptionName,\r
+                  &gEfiGlobalVariableGuid,\r
+                  EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS | EFI_VARIABLE_NON_VOLATILE,\r
+                  OptionSize,\r
+                  OptionPtr\r
+                  );\r
+  //\r
+  // Return if only need to update a changed description or fail to set option.\r
+  //\r
+  if (EFI_ERROR (Status) || UpdateDescription) {\r
+    FreePool (OptionPtr);\r
+    if (TempOptionPtr != NULL) {\r
+      FreePool (TempOptionPtr);\r
+    }\r
+    return Status;\r
+  }\r
+\r
+  FreePool (OptionPtr);\r
+\r
+  //\r
+  // Update the option order variable\r
+  //\r
+\r
+  //\r
+  // If no option order\r
+  //\r
+  if (TempOptionSize == 0) {\r
+    BootOrderEntry = 0;\r
+    Status = gRT->SetVariable (\r
+                    VariableName,\r
+                    &gEfiGlobalVariableGuid,\r
+                    EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS | EFI_VARIABLE_NON_VOLATILE,\r
+                    sizeof (UINT16),\r
+                    &BootOrderEntry\r
+                    );\r
+    if (TempOptionPtr != NULL) {\r
+      FreePool (TempOptionPtr);\r
+    }\r
+    return Status;\r
+  }\r
+  \r
+  //\r
+  // TempOptionPtr must not be NULL if TempOptionSize is not zero.\r
+  //\r
+  ASSERT (TempOptionPtr != NULL);\r
+  //\r
+  // Append the new option number to the original option order\r
+  //\r
+  OrderItemNum = (TempOptionSize / sizeof (UINT16)) + 1 ;\r
+  OptionOrderPtr = AllocateZeroPool ( OrderItemNum * sizeof (UINT16));\r
+  ASSERT (OptionOrderPtr!= NULL);\r
+  CopyMem (OptionOrderPtr, TempOptionPtr, (OrderItemNum - 1) * sizeof (UINT16));\r
+\r
+  OptionOrderPtr[Index] = RegisterOptionNumber;\r
+\r
+  Status = gRT->SetVariable (\r
+                  VariableName,\r
+                  &gEfiGlobalVariableGuid,\r
+                  EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS | EFI_VARIABLE_NON_VOLATILE,\r
+                  OrderItemNum * sizeof (UINT16),\r
+                  OptionOrderPtr\r
+                  );\r
+  FreePool (TempOptionPtr);\r
+  FreePool (OptionOrderPtr);\r
+\r
+  return Status;\r
+}\r
+\r
+/**\r
+  Returns the size of a device path in bytes.\r
+\r
+  This function returns the size, in bytes, of the device path data structure \r
+  specified by DevicePath including the end of device path node. If DevicePath \r
+  is NULL, then 0 is returned. If the length of the device path is bigger than\r
+  MaxSize, also return 0 to indicate this is an invalidate device path.\r
+\r
+  @param  DevicePath         A pointer to a device path data structure.\r
+  @param  MaxSize            Max valid device path size. If big than this size, \r
+                             return error.\r
+  \r
+  @retval 0                  An invalid device path.\r
+  @retval Others             The size of a device path in bytes.\r
+\r
+**/\r
+UINTN\r
+GetDevicePathSizeEx (\r
+  IN CONST EFI_DEVICE_PATH_PROTOCOL  *DevicePath,\r
+  IN UINTN                           MaxSize\r
+  )\r
+{\r
+  UINTN  Size;\r
+  UINTN  NodeSize;\r
+\r
+  if (DevicePath == NULL) {\r
+    return 0;\r
+  }\r
+\r
+  //\r
+  // Search for the end of the device path structure\r
+  //\r
+  Size = 0;\r
+  while (!IsDevicePathEnd (DevicePath)) {\r
+    NodeSize = DevicePathNodeLength (DevicePath);\r
+    if (NodeSize < END_DEVICE_PATH_LENGTH) {\r
+      return 0;\r
+    }\r
+    Size += NodeSize;\r
+    if (Size > MaxSize) {\r
+      return 0;\r
+    }\r
+    DevicePath = NextDevicePathNode (DevicePath);\r
+  }\r
+  Size += DevicePathNodeLength (DevicePath);\r
+  if (Size > MaxSize) {\r
+    return 0;\r
+  }\r
+\r
+  return Size;\r
+}\r
+\r
+/**\r
+  Returns the length of a Null-terminated Unicode string. If the length is \r
+  bigger than MaxStringLen, return length 0 to indicate that this is an \r
+  invalidate string.\r
+\r
+  This function returns the byte length of Unicode characters in the Null-terminated\r
+  Unicode string specified by String. \r
+\r
+  If String is NULL, then ASSERT().\r
+  If String is not aligned on a 16-bit boundary, then ASSERT().\r
+\r
+  @param  String           A pointer to a Null-terminated Unicode string.\r
+  @param  MaxStringLen     Max string len in this string.\r
+\r
+  @retval 0                An invalid string.\r
+  @retval Others           The length of String.\r
+\r
+**/\r
+UINTN\r
+StrSizeEx (\r
+  IN      CONST CHAR16              *String,\r
+  IN      UINTN                     MaxStringLen\r
+  )\r
+{\r
+  UINTN                             Length;\r
+\r
+  ASSERT (String != NULL && MaxStringLen != 0);\r
+  ASSERT (((UINTN) String & BIT0) == 0);\r
+\r
+  for (Length = 0; *String != L'\0' && MaxStringLen != Length; String++, Length+=2);\r
+\r
+  if (*String != L'\0' && MaxStringLen == Length) {\r
+    return 0;\r
+  }\r
+\r
+  return Length + 2;\r
+}\r
+\r
+/**\r
+  Validate the EFI Boot#### variable (VendorGuid/Name)\r
+\r
+  @param  Variable              Boot#### variable data.\r
+  @param  VariableSize          Returns the size of the EFI variable that was read\r
+\r
+  @retval TRUE                  The variable data is correct.\r
+  @retval FALSE                 The variable data is corrupted.\r
+\r
+**/\r
+BOOLEAN \r
+ValidateOption (\r
+  UINT8                     *Variable,\r
+  UINTN                     VariableSize\r
+  )\r
+{\r
+  UINT16                    FilePathSize;\r
+  UINT8                     *TempPtr;\r
+  EFI_DEVICE_PATH_PROTOCOL  *DevicePath;\r
+  UINTN                     TempSize;\r
+\r
+  if (VariableSize <= sizeof (UINT16) + sizeof (UINT32)) {\r
+    return FALSE;\r
+  }\r
+\r
+  //\r
+  // Skip the option attribute\r
+  //\r
+  TempPtr    = Variable;\r
+  TempPtr   += sizeof (UINT32);\r
+\r
+  //\r
+  // Get the option's device path size\r
+  //\r
+  FilePathSize  = *(UINT16 *) TempPtr;\r
+  TempPtr      += sizeof (UINT16);\r
+\r
+  //\r
+  // Get the option's description string size\r
+  //\r
+  TempSize = StrSizeEx ((CHAR16 *) TempPtr, VariableSize - sizeof (UINT16) - sizeof (UINT32));\r
+  TempPtr += TempSize;\r
+\r
+  //\r
+  // Get the option's device path\r
+  //\r
+  DevicePath =  (EFI_DEVICE_PATH_PROTOCOL *) TempPtr;\r
+  TempPtr   += FilePathSize;\r
+\r
+  //\r
+  // Validation boot option variable.\r
+  //\r
+  if ((FilePathSize == 0) || (TempSize == 0)) {\r
+    return FALSE;\r
+  }\r
+\r
+  if (TempSize + FilePathSize + sizeof (UINT16) + sizeof (UINT32) > VariableSize) {\r
+    return FALSE;\r
+  }\r
+\r
+  return (BOOLEAN) (GetDevicePathSizeEx (DevicePath, FilePathSize) != 0);\r
+}\r
+\r
+/**\r
+  Convert a single character to number.\r
+  It assumes the input Char is in the scope of L'0' ~ L'9' and L'A' ~ L'F'\r
+  \r
+  @param Char    The input char which need to change to a hex number.\r
+  \r
+**/\r
+UINTN\r
+CharToUint (\r
+  IN CHAR16                           Char\r
+  )\r
+{\r
+  if ((Char >= L'0') && (Char <= L'9')) {\r
+    return (UINTN) (Char - L'0');\r
+  }\r
+\r
+  if ((Char >= L'A') && (Char <= L'F')) {\r
+    return (UINTN) (Char - L'A' + 0xA);\r
+  }\r
+\r
+  ASSERT (FALSE);\r
+  return 0;\r
+}\r
+\r
+/**\r
+  Build the boot#### or driver#### option from the VariableName, the\r
+  build boot#### or driver#### will also be linked to BdsCommonOptionList.\r
+\r
+  @param  BdsCommonOptionList   The header of the boot#### or driver#### option\r
+                                link list\r
+  @param  VariableName          EFI Variable name indicate if it is boot#### or\r
+                                driver####\r
+\r
+  @retval BDS_COMMON_OPTION     Get the option just been created\r
+  @retval NULL                  Failed to get the new option\r
+\r
+**/\r
+BDS_COMMON_OPTION *\r
+EFIAPI\r
+BdsLibVariableToOption (\r
+  IN OUT LIST_ENTRY                   *BdsCommonOptionList,\r
+  IN  CHAR16                          *VariableName\r
+  )\r
+{\r
+  UINT32                    Attribute;\r
+  UINT16                    FilePathSize;\r
+  UINT8                     *Variable;\r
+  UINT8                     *TempPtr;\r
+  UINTN                     VariableSize;\r
+  EFI_DEVICE_PATH_PROTOCOL  *DevicePath;\r
+  BDS_COMMON_OPTION         *Option;\r
+  VOID                      *LoadOptions;\r
+  UINT32                    LoadOptionsSize;\r
+  CHAR16                    *Description;\r
+  UINT8                     NumOff;\r
+\r
+  //\r
+  // Read the variable. We will never free this data.\r
+  //\r
+  Variable = BdsLibGetVariableAndSize (\r
+              VariableName,\r
+              &gEfiGlobalVariableGuid,\r
+              &VariableSize\r
+              );\r
+  if (Variable == NULL) {\r
+    return NULL;\r
+  }\r
+\r
+  //\r
+  // Validate Boot#### variable data.\r
+  //\r
+  if (!ValidateOption(Variable, VariableSize)) {\r
+    return NULL;\r
+  }\r
+\r
+  //\r
+  // Notes: careful defined the variable of Boot#### or\r
+  // Driver####, consider use some macro to abstract the code\r
+  //\r
+  //\r
+  // Get the option attribute\r
+  //\r
+  TempPtr   =  Variable;\r
+  Attribute =  *(UINT32 *) Variable;\r
+  TempPtr   += sizeof (UINT32);\r
+\r
+  //\r
+  // Get the option's device path size\r
+  //\r
+  FilePathSize =  *(UINT16 *) TempPtr;\r
+  TempPtr      += sizeof (UINT16);\r
+\r
+  //\r
+  // Get the option's description string\r
+  //\r
+  Description = (CHAR16 *) TempPtr;\r
+\r
+  //\r
+  // Get the option's description string size\r
+  //\r
+  TempPtr += StrSize((CHAR16 *) TempPtr);\r
+\r
+  //\r
+  // Get the option's device path\r
+  //\r
+  DevicePath =  (EFI_DEVICE_PATH_PROTOCOL *) TempPtr;\r
+  TempPtr    += FilePathSize;\r
+\r
+  //\r
+  // Get load opion data.\r
+  //\r
+  LoadOptions     = TempPtr;\r
+  LoadOptionsSize = (UINT32) (VariableSize - (UINTN) (TempPtr - Variable));\r
+\r
+  //\r
+  // The Console variables may have multiple device paths, so make\r
+  // an Entry for each one.\r
+  //\r
+  Option = AllocateZeroPool (sizeof (BDS_COMMON_OPTION));\r
+  if (Option == NULL) {\r
+    return NULL;\r
+  }\r
+\r
+  Option->Signature   = BDS_LOAD_OPTION_SIGNATURE;\r
+  Option->DevicePath  = AllocateZeroPool (GetDevicePathSize (DevicePath));\r
+  ASSERT(Option->DevicePath != NULL);\r
+  CopyMem (Option->DevicePath, DevicePath, GetDevicePathSize (DevicePath));\r
+\r
+  Option->Attribute   = Attribute;\r
+  Option->Description = AllocateZeroPool (StrSize (Description));\r
+  ASSERT(Option->Description != NULL);\r
+  CopyMem (Option->Description, Description, StrSize (Description));\r
+\r
+  Option->LoadOptions = AllocateZeroPool (LoadOptionsSize);\r
+  ASSERT(Option->LoadOptions != NULL);\r
+  CopyMem (Option->LoadOptions, LoadOptions, LoadOptionsSize);\r
+  Option->LoadOptionsSize = LoadOptionsSize;\r
+\r
+  //\r
+  // Get the value from VariableName Unicode string\r
+  // since the ISO standard assumes ASCII equivalent abbreviations, we can be safe in converting this\r
+  // Unicode stream to ASCII without any loss in meaning.\r
+  //\r
+  if (*VariableName == 'B') {\r
+    NumOff = (UINT8) (sizeof (L"Boot") / sizeof (CHAR16) - 1);\r
+    Option->BootCurrent = (UINT16) (CharToUint (VariableName[NumOff+0]) * 0x1000) \r
+               + (UINT16) (CharToUint (VariableName[NumOff+1]) * 0x100)\r
+               + (UINT16) (CharToUint (VariableName[NumOff+2]) * 0x10)\r
+               + (UINT16) (CharToUint (VariableName[NumOff+3]) * 0x1);\r
+  }\r
+  InsertTailList (BdsCommonOptionList, &Option->Link);\r
+  FreePool (Variable);\r
+  return Option;\r
+}\r
+\r
+/**\r
+  Process BootOrder, or DriverOrder variables, by calling\r
+  BdsLibVariableToOption () for each UINT16 in the variables.\r
+\r
+  @param  BdsCommonOptionList   The header of the option list base on variable\r
+                                VariableName\r
+  @param  VariableName          EFI Variable name indicate the BootOrder or\r
+                                DriverOrder\r
+\r
+  @retval EFI_SUCCESS           Success create the boot option or driver option\r
+                                list\r
+  @retval EFI_OUT_OF_RESOURCES  Failed to get the boot option or driver option list\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+BdsLibBuildOptionFromVar (\r
+  IN  LIST_ENTRY                      *BdsCommonOptionList,\r
+  IN  CHAR16                          *VariableName\r
+  )\r
+{\r
+  UINT16            *OptionOrder;\r
+  UINTN             OptionOrderSize;\r
+  UINTN             Index;\r
+  BDS_COMMON_OPTION *Option;\r
+  CHAR16            OptionName[20];\r
+\r
+  //\r
+  // Zero Buffer in order to get all BOOT#### variables\r
+  //\r
+  ZeroMem (OptionName, sizeof (OptionName));\r
+\r
+  //\r
+  // Read the BootOrder, or DriverOrder variable.\r
+  //\r
+  OptionOrder = BdsLibGetVariableAndSize (\r
+                  VariableName,\r
+                  &gEfiGlobalVariableGuid,\r
+                  &OptionOrderSize\r
+                  );\r
+  if (OptionOrder == NULL) {\r
+    return EFI_OUT_OF_RESOURCES;\r
+  }\r
+\r
+  for (Index = 0; Index < OptionOrderSize / sizeof (UINT16); Index++) {\r
+    if (*VariableName == 'B') {\r
+      UnicodeSPrint (OptionName, sizeof (OptionName), L"Boot%04x", OptionOrder[Index]);\r
+    } else {\r
+      UnicodeSPrint (OptionName, sizeof (OptionName), L"Driver%04x", OptionOrder[Index]);\r
+    }\r
+\r
+    Option              = BdsLibVariableToOption (BdsCommonOptionList, OptionName);\r
+    if (Option != NULL) {\r
+      Option->BootCurrent = OptionOrder[Index];\r
+    }\r
+  }\r
+\r
+  FreePool (OptionOrder);\r
+\r
+  return EFI_SUCCESS;\r
+}\r
+\r
+/**\r
+  Get boot mode by looking up configuration table and parsing HOB list\r
+\r
+  @param  BootMode              Boot mode from PEI handoff HOB.\r
+\r
+  @retval EFI_SUCCESS           Successfully get boot mode\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+BdsLibGetBootMode (\r
+  OUT EFI_BOOT_MODE       *BootMode\r
+  )\r
+{\r
+  *BootMode = GetBootModeHob ();\r
+\r
+  return EFI_SUCCESS;\r
+}\r
+\r
+/**\r
+  Read the EFI variable (VendorGuid/Name) and return a dynamically allocated\r
+  buffer, and the size of the buffer. If failure return NULL.\r
+\r
+  @param  Name                  String part of EFI variable name\r
+  @param  VendorGuid            GUID part of EFI variable name\r
+  @param  VariableSize          Returns the size of the EFI variable that was read\r
+\r
+  @return                       Dynamically allocated memory that contains a copy of the EFI variable\r
+                                Caller is responsible freeing the buffer.\r
+  @retval NULL                  Variable was not read\r
+\r
+**/\r
+VOID *\r
+EFIAPI\r
+BdsLibGetVariableAndSize (\r
+  IN  CHAR16              *Name,\r
+  IN  EFI_GUID            *VendorGuid,\r
+  OUT UINTN               *VariableSize\r
+  )\r
+{\r
+  EFI_STATUS  Status;\r
+  UINTN       BufferSize;\r
+  VOID        *Buffer;\r
+\r
+  Buffer = NULL;\r
+\r
+  //\r
+  // Pass in a zero size buffer to find the required buffer size.\r
+  //\r
+  BufferSize  = 0;\r
+  Status      = gRT->GetVariable (Name, VendorGuid, NULL, &BufferSize, Buffer);\r
+  if (Status == EFI_BUFFER_TOO_SMALL) {\r
+    //\r
+    // Allocate the buffer to return\r
+    //\r
+    Buffer = AllocateZeroPool (BufferSize);\r
+    if (Buffer == NULL) {\r
+      *VariableSize = 0;\r
+      return NULL;\r
+    }\r
+    //\r
+    // Read variable into the allocated buffer.\r
+    //\r
+    Status = gRT->GetVariable (Name, VendorGuid, NULL, &BufferSize, Buffer);\r
+    if (EFI_ERROR (Status)) {\r
+      FreePool (Buffer);\r
+      BufferSize = 0;\r
+      Buffer     = NULL;\r
+    }\r
+  }\r
+\r
+  ASSERT (((Buffer == NULL) && (BufferSize == 0)) ||\r
+          ((Buffer != NULL) && (BufferSize != 0))\r
+          );\r
+  *VariableSize = BufferSize;\r
+  return Buffer;\r
+}\r
+\r
+/**\r
+  Delete the instance in Multi which matches partly with Single instance\r
+\r
+  @param  Multi                 A pointer to a multi-instance device path data\r
+                                structure.\r
+  @param  Single                A pointer to a single-instance device path data\r
+                                structure.\r
+\r
+  @return This function will remove the device path instances in Multi which partly\r
+          match with the Single, and return the result device path. If there is no\r
+          remaining device path as a result, this function will return NULL.\r
+\r
+**/\r
+EFI_DEVICE_PATH_PROTOCOL *\r
+EFIAPI\r
+BdsLibDelPartMatchInstance (\r
+  IN     EFI_DEVICE_PATH_PROTOCOL  *Multi,\r
+  IN     EFI_DEVICE_PATH_PROTOCOL  *Single\r
+  )\r
+{\r
+  EFI_DEVICE_PATH_PROTOCOL  *Instance;\r
+  EFI_DEVICE_PATH_PROTOCOL  *NewDevicePath;\r
+  EFI_DEVICE_PATH_PROTOCOL  *TempNewDevicePath;\r
+  UINTN                     InstanceSize;\r
+  UINTN                     SingleDpSize;\r
+  UINTN                     Size;\r
+\r
+  NewDevicePath     = NULL;\r
+  TempNewDevicePath = NULL;\r
+\r
+  if (Multi == NULL || Single == NULL) {\r
+    return Multi;\r
+  }\r
+\r
+  Instance        =  GetNextDevicePathInstance (&Multi, &InstanceSize);\r
+  SingleDpSize    =  GetDevicePathSize (Single) - END_DEVICE_PATH_LENGTH;\r
+  InstanceSize    -= END_DEVICE_PATH_LENGTH;\r
+\r
+  while (Instance != NULL) {\r
+\r
+    Size = (SingleDpSize < InstanceSize) ? SingleDpSize : InstanceSize;\r
+\r
+    if ((CompareMem (Instance, Single, Size) != 0)) {\r
+      //\r
+      // Append the device path instance which does not match with Single\r
+      //\r
+      TempNewDevicePath = NewDevicePath;\r
+      NewDevicePath = AppendDevicePathInstance (NewDevicePath, Instance);\r
+      if (TempNewDevicePath != NULL) {\r
+        FreePool(TempNewDevicePath);\r
+      }\r
+    }\r
+    FreePool(Instance);\r
+    Instance = GetNextDevicePathInstance (&Multi, &InstanceSize);\r
+    InstanceSize  -= END_DEVICE_PATH_LENGTH;\r
+  }\r
+\r
+  return NewDevicePath;\r
+}\r
+\r
+/**\r
+  Function compares a device path data structure to that of all the nodes of a\r
+  second device path instance.\r
+\r
+  @param  Multi                 A pointer to a multi-instance device path data\r
+                                structure.\r
+  @param  Single                A pointer to a single-instance device path data\r
+                                structure.\r
+\r
+  @retval TRUE                  If the Single device path is contained within Multi device path.\r
+  @retval FALSE                 The Single device path is not match within Multi device path.\r
+\r
+**/\r
+BOOLEAN\r
+EFIAPI\r
+BdsLibMatchDevicePaths (\r
+  IN  EFI_DEVICE_PATH_PROTOCOL  *Multi,\r
+  IN  EFI_DEVICE_PATH_PROTOCOL  *Single\r
+  )\r
+{\r
+  EFI_DEVICE_PATH_PROTOCOL  *DevicePath;\r
+  EFI_DEVICE_PATH_PROTOCOL  *DevicePathInst;\r
+  UINTN                     Size;\r
+\r
+  if (Multi == NULL || Single  == NULL) {\r
+    return FALSE;\r
+  }\r
+\r
+  DevicePath      = Multi;\r
+  DevicePathInst  = GetNextDevicePathInstance (&DevicePath, &Size);\r
+\r
+  //\r
+  // Search for the match of 'Single' in 'Multi'\r
+  //\r
+  while (DevicePathInst != NULL) {\r
+    //\r
+    // If the single device path is found in multiple device paths,\r
+    // return success\r
+    //\r
+    if (CompareMem (Single, DevicePathInst, Size) == 0) {\r
+      FreePool (DevicePathInst);\r
+      return TRUE;\r
+    }\r
+\r
+    FreePool (DevicePathInst);\r
+    DevicePathInst = GetNextDevicePathInstance (&DevicePath, &Size);\r
+  }\r
+\r
+  return FALSE;\r
+}\r
+\r
+/**\r
+  This function prints a series of strings.\r
+\r
+  @param  ConOut                Pointer to EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL\r
+  @param  ...                   A variable argument list containing series of\r
+                                strings, the last string must be NULL.\r
+\r
+  @retval EFI_SUCCESS           Success print out the string using ConOut.\r
+  @retval EFI_STATUS            Return the status of the ConOut->OutputString ().\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+BdsLibOutputStrings (\r
+  IN EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL   *ConOut,\r
+  ...\r
+  )\r
+{\r
+  VA_LIST     Args;\r
+  EFI_STATUS  Status;\r
+  CHAR16      *String;\r
+\r
+  Status = EFI_SUCCESS;\r
+  VA_START (Args, ConOut);\r
+\r
+  while (!EFI_ERROR (Status)) {\r
+    //\r
+    // If String is NULL, then it's the end of the list\r
+    //\r
+    String = VA_ARG (Args, CHAR16 *);\r
+    if (String == NULL) {\r
+      break;\r
+    }\r
+\r
+    Status = ConOut->OutputString (ConOut, String);\r
+\r
+    if (EFI_ERROR (Status)) {\r
+      break;\r
+    }\r
+  }\r
+  \r
+  VA_END(Args);\r
+  return Status;\r
+}\r
+\r
+//\r
+//  Following are BDS Lib functions which contain all the code about setup browser reset reminder feature.\r
+//  Setup Browser reset reminder feature is that an reset reminder will be given before user leaves the setup browser  if\r
+//  user change any option setting which needs a reset to be effective, and  the reset will be applied according to  the user selection.\r
+//\r
+\r
+\r
+/**\r
+  Enable the setup browser reset reminder feature.\r
+  This routine is used in platform tip. If the platform policy need the feature, use the routine to enable it.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+EnableResetReminderFeature (\r
+  VOID\r
+  )\r
+{\r
+  mFeaturerSwitch = TRUE;\r
+}\r
+\r
+\r
+/**\r
+  Disable the setup browser reset reminder feature.\r
+  This routine is used in platform tip. If the platform policy do not want the feature, use the routine to disable it.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+DisableResetReminderFeature (\r
+  VOID\r
+  )\r
+{\r
+  mFeaturerSwitch = FALSE;\r
+}\r
+\r
+\r
+/**\r
+  Record the info that  a reset is required.\r
+  A  module boolean variable is used to record whether a reset is required.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+EnableResetRequired (\r
+  VOID\r
+  )\r
+{\r
+  mResetRequired = TRUE;\r
+}\r
+\r
+\r
+/**\r
+  Record the info that  no reset is required.\r
+  A  module boolean variable is used to record whether a reset is required.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+DisableResetRequired (\r
+  VOID\r
+  )\r
+{\r
+  mResetRequired = FALSE;\r
+}\r
+\r
+\r
+/**\r
+  Check whether platform policy enable the reset reminder feature. The default is enabled.\r
+\r
+**/\r
+BOOLEAN\r
+EFIAPI\r
+IsResetReminderFeatureEnable (\r
+  VOID\r
+  )\r
+{\r
+  return mFeaturerSwitch;\r
+}\r
+\r
+\r
+/**\r
+  Check if  user changed any option setting which needs a system reset to be effective.\r
+\r
+**/\r
+BOOLEAN\r
+EFIAPI\r
+IsResetRequired (\r
+  VOID\r
+  )\r
+{\r
+  return mResetRequired;\r
+}\r
+\r
+\r
+/**\r
+  Check whether a reset is needed, and finish the reset reminder feature.\r
+  If a reset is needed, Popup a menu to notice user, and finish the feature\r
+  according to the user selection.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+SetupResetReminder (\r
+  VOID\r
+  )\r
+{\r
+  EFI_INPUT_KEY                 Key;\r
+  CHAR16                        *StringBuffer1;\r
+  CHAR16                        *StringBuffer2;\r
+\r
+\r
+  //\r
+  //check any reset required change is applied? if yes, reset system\r
+  //\r
+  if (IsResetReminderFeatureEnable ()) {\r
+    if (IsResetRequired ()) {\r
+\r
+      StringBuffer1 = AllocateZeroPool (MAX_STRING_LEN * sizeof (CHAR16));\r
+      ASSERT (StringBuffer1 != NULL);\r
+      StringBuffer2 = AllocateZeroPool (MAX_STRING_LEN * sizeof (CHAR16));\r
+      ASSERT (StringBuffer2 != NULL);\r
+      StrCpy (StringBuffer1, L"Configuration changed. Reset to apply it Now.");\r
+      StrCpy (StringBuffer2, L"Press ENTER to reset");\r
+      //\r
+      // Popup a menu to notice user\r
+      //\r
+      do {\r
+        CreatePopUp (EFI_LIGHTGRAY | EFI_BACKGROUND_BLUE, &Key, StringBuffer1, StringBuffer2, NULL);\r
+      } while (Key.UnicodeChar != CHAR_CARRIAGE_RETURN);\r
+\r
+      FreePool (StringBuffer1);\r
+      FreePool (StringBuffer2);\r
+\r
+      gRT->ResetSystem (EfiResetCold, EFI_SUCCESS, 0, NULL);\r
+    }\r
+  }\r
+}\r
+\r
+/**\r
+  Get the headers (dos, image, optional header) from an image\r
+\r
+  @param  Device                SimpleFileSystem device handle\r
+  @param  FileName              File name for the image\r
+  @param  DosHeader             Pointer to dos header\r
+  @param  Hdr                   The buffer in which to return the PE32, PE32+, or TE header.\r
+\r
+  @retval EFI_SUCCESS           Successfully get the machine type.\r
+  @retval EFI_NOT_FOUND         The file is not found.\r
+  @retval EFI_LOAD_ERROR        File is not a valid image file.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+BdsLibGetImageHeader (\r
+  IN  EFI_HANDLE                  Device,\r
+  IN  CHAR16                      *FileName,\r
+  OUT EFI_IMAGE_DOS_HEADER        *DosHeader,\r
+  OUT EFI_IMAGE_OPTIONAL_HEADER_PTR_UNION   Hdr\r
+  )\r
+{\r
+  EFI_STATUS                       Status;\r
+  EFI_SIMPLE_FILE_SYSTEM_PROTOCOL  *Volume;\r
+  EFI_FILE_HANDLE                  Root;\r
+  EFI_FILE_HANDLE                  ThisFile;\r
+  UINTN                            BufferSize;\r
+  UINT64                           FileSize;\r
+  EFI_FILE_INFO                    *Info;\r
+\r
+  Root     = NULL;\r
+  ThisFile = NULL;\r
+  //\r
+  // Handle the file system interface to the device\r
+  //\r
+  Status = gBS->HandleProtocol (\r
+                  Device,\r
+                  &gEfiSimpleFileSystemProtocolGuid,\r
+                  (VOID *) &Volume\r
+                  );\r
+  if (EFI_ERROR (Status)) {\r
+    goto Done;\r
+  }\r
+\r
+  Status = Volume->OpenVolume (\r
+                     Volume,\r
+                     &Root\r
+                     );\r
+  if (EFI_ERROR (Status)) {\r
+    Root = NULL;\r
+    goto Done;\r
+  }\r
+  ASSERT (Root != NULL);\r
+  Status = Root->Open (Root, &ThisFile, FileName, EFI_FILE_MODE_READ, 0);\r
+  if (EFI_ERROR (Status)) {\r
+    goto Done;\r
+  }\r
+  ASSERT (ThisFile != NULL);\r
+\r
+  //\r
+  // Get file size\r
+  //\r
+  BufferSize  = SIZE_OF_EFI_FILE_INFO + 200;\r
+  do {\r
+    Info   = NULL;\r
+    Status = gBS->AllocatePool (EfiBootServicesData, BufferSize, (VOID **) &Info);\r
+    if (EFI_ERROR (Status)) {\r
+      goto Done;\r
+    }\r
+    Status = ThisFile->GetInfo (\r
+                         ThisFile,\r
+                         &gEfiFileInfoGuid,\r
+                         &BufferSize,\r
+                         Info\r
+                         );\r
+    if (!EFI_ERROR (Status)) {\r
+      break;\r
+    }\r
+    if (Status != EFI_BUFFER_TOO_SMALL) {\r
+      FreePool (Info);\r
+      goto Done;\r
+    }\r
+    FreePool (Info);\r
+  } while (TRUE);\r
+\r
+  FileSize = Info->FileSize;\r
+  FreePool (Info);\r
+\r
+  //\r
+  // Read dos header\r
+  //\r
+  BufferSize = sizeof (EFI_IMAGE_DOS_HEADER);\r
+  Status = ThisFile->Read (ThisFile, &BufferSize, DosHeader);\r
+  if (EFI_ERROR (Status) ||\r
+      BufferSize < sizeof (EFI_IMAGE_DOS_HEADER) ||\r
+      FileSize <= DosHeader->e_lfanew ||\r
+      DosHeader->e_magic != EFI_IMAGE_DOS_SIGNATURE) {\r
+    Status = EFI_LOAD_ERROR;\r
+    goto Done;\r
+  }\r
+\r
+  //\r
+  // Move to PE signature\r
+  //\r
+  Status = ThisFile->SetPosition (ThisFile, DosHeader->e_lfanew);\r
+  if (EFI_ERROR (Status)) {\r
+    Status = EFI_LOAD_ERROR;\r
+    goto Done;\r
+  }\r
+\r
+  //\r
+  // Read and check PE signature\r
+  //\r
+  BufferSize = sizeof (EFI_IMAGE_OPTIONAL_HEADER_UNION);\r
+  Status = ThisFile->Read (ThisFile, &BufferSize, Hdr.Pe32);\r
+  if (EFI_ERROR (Status) ||\r
+      BufferSize < sizeof (EFI_IMAGE_OPTIONAL_HEADER_UNION) ||\r
+      Hdr.Pe32->Signature != EFI_IMAGE_NT_SIGNATURE) {\r
+    Status = EFI_LOAD_ERROR;\r
+    goto Done;\r
+  }\r
+\r
+  //\r
+  // Check PE32 or PE32+ magic\r
+  //\r
+  if (Hdr.Pe32->OptionalHeader.Magic != EFI_IMAGE_NT_OPTIONAL_HDR32_MAGIC &&\r
+      Hdr.Pe32->OptionalHeader.Magic != EFI_IMAGE_NT_OPTIONAL_HDR64_MAGIC) {\r
+    Status = EFI_LOAD_ERROR;\r
+    goto Done;\r
+  }\r
+\r
+ Done:\r
+  if (ThisFile != NULL) {\r
+    ThisFile->Close (ThisFile);\r
+  }\r
+  if (Root != NULL) {\r
+    Root->Close (Root);\r
+  }\r
+  return Status;\r
+}\r
+\r
+/**\r
+  This routine adjust the memory information for different memory type and \r
+  save them into the variables for next boot.\r
+**/\r
+VOID\r
+BdsSetMemoryTypeInformationVariable (\r
+  VOID\r
+  )\r
+{\r
+  EFI_STATUS                   Status;\r
+  EFI_MEMORY_TYPE_INFORMATION  *PreviousMemoryTypeInformation;\r
+  EFI_MEMORY_TYPE_INFORMATION  *CurrentMemoryTypeInformation;\r
+  UINTN                        VariableSize;\r
+  UINTN                        Index;\r
+  UINTN                        Index1;\r
+  UINT32                       Previous;\r
+  UINT32                       Current;\r
+  UINT32                       Next;\r
+  EFI_HOB_GUID_TYPE            *GuidHob;\r
+  BOOLEAN                      MemoryTypeInformationModified;\r
+  BOOLEAN                      MemoryTypeInformationVariableExists;\r
+  EFI_BOOT_MODE                BootMode;\r
+\r
+  MemoryTypeInformationModified       = FALSE;\r
+  MemoryTypeInformationVariableExists = FALSE;\r
+\r
+\r
+  BootMode = GetBootModeHob ();\r
+  //\r
+  // In BOOT_IN_RECOVERY_MODE, Variable region is not reliable.\r
+  //\r
+  if (BootMode == BOOT_IN_RECOVERY_MODE) {\r
+    return;\r
+  }\r
+\r
+  //\r
+  // Only check the the Memory Type Information variable in the boot mode \r
+  // other than BOOT_WITH_DEFAULT_SETTINGS because the Memory Type\r
+  // Information is not valid in this boot mode.\r
+  //\r
+  if (BootMode != BOOT_WITH_DEFAULT_SETTINGS) {\r
+    VariableSize = 0;\r
+    Status = gRT->GetVariable (\r
+                    EFI_MEMORY_TYPE_INFORMATION_VARIABLE_NAME,\r
+                    &gEfiMemoryTypeInformationGuid,\r
+                    NULL, \r
+                    &VariableSize, \r
+                    NULL\r
+                    );\r
+    if (Status == EFI_BUFFER_TOO_SMALL) {\r
+      MemoryTypeInformationVariableExists = TRUE;\r
+    }\r
+  }\r
+\r
+  //\r
+  // Retrieve the current memory usage statistics.  If they are not found, then\r
+  // no adjustments can be made to the Memory Type Information variable.\r
+  //\r
+  Status = EfiGetSystemConfigurationTable (\r
+             &gEfiMemoryTypeInformationGuid,\r
+             (VOID **) &CurrentMemoryTypeInformation\r
+             );\r
+  if (EFI_ERROR (Status) || CurrentMemoryTypeInformation == NULL) {\r
+    return;\r
+  }\r
+\r
+  //\r
+  // Get the Memory Type Information settings from Hob if they exist,\r
+  // PEI is responsible for getting them from variable and build a Hob to save them.\r
+  // If the previous Memory Type Information is not available, then set defaults\r
+  //\r
+  GuidHob = GetFirstGuidHob (&gEfiMemoryTypeInformationGuid);\r
+  if (GuidHob == NULL) {\r
+    //\r
+    // If Platform has not built Memory Type Info into the Hob, just return.\r
+    //\r
+    return;\r
+  }\r
+  PreviousMemoryTypeInformation = GET_GUID_HOB_DATA (GuidHob);\r
+  VariableSize = GET_GUID_HOB_DATA_SIZE (GuidHob);\r
+\r
+  //\r
+  // Use a heuristic to adjust the Memory Type Information for the next boot\r
+  //\r
+  DEBUG ((EFI_D_INFO, "Memory  Previous  Current    Next   \n"));\r
+  DEBUG ((EFI_D_INFO, " Type    Pages     Pages     Pages  \n"));\r
+  DEBUG ((EFI_D_INFO, "======  ========  ========  ========\n"));\r
+\r
+  for (Index = 0; PreviousMemoryTypeInformation[Index].Type != EfiMaxMemoryType; Index++) {\r
+\r
+    for (Index1 = 0; CurrentMemoryTypeInformation[Index1].Type != EfiMaxMemoryType; Index1++) {\r
+      if (PreviousMemoryTypeInformation[Index].Type == CurrentMemoryTypeInformation[Index1].Type) {\r
+        break;\r
+      }\r
+    }\r
+    if (CurrentMemoryTypeInformation[Index1].Type == EfiMaxMemoryType) {\r
+      continue;\r
+    }\r
+\r
+    //\r
+    // Previous is the number of pages pre-allocated\r
+    // Current is the number of pages actually needed\r
+    //\r
+    Previous = PreviousMemoryTypeInformation[Index].NumberOfPages;\r
+    Current  = CurrentMemoryTypeInformation[Index1].NumberOfPages;\r
+    Next     = Previous;\r
+\r
+    //\r
+    // Inconsistent Memory Reserved across bootings may lead to S4 fail\r
+    // Write next varible to 125% * current when the pre-allocated memory is:\r
+    //  1. More than 150% of needed memory and boot mode is BOOT_WITH_DEFAULT_SETTING\r
+    //  2. Less than the needed memory\r
+    //\r
+    if ((Current + (Current >> 1)) < Previous) {\r
+      if (BootMode == BOOT_WITH_DEFAULT_SETTINGS) {\r
+        Next = Current + (Current >> 2);\r
+      }\r
+    } else if (Current > Previous) {\r
+      Next = Current + (Current >> 2);\r
+    }\r
+    if (Next > 0 && Next < 4) {\r
+      Next = 4;\r
+    }\r
+\r
+    if (Next != Previous) {\r
+      PreviousMemoryTypeInformation[Index].NumberOfPages = Next;\r
+      MemoryTypeInformationModified = TRUE;\r
+    }\r
+\r
+    DEBUG ((EFI_D_INFO, "  %02x    %08x  %08x  %08x\n", PreviousMemoryTypeInformation[Index].Type, Previous, Current, Next));\r
+  }\r
+\r
+  //\r
+  // If any changes were made to the Memory Type Information settings, then set the new variable value;\r
+  // Or create the variable in first boot.\r
+  //\r
+  if (MemoryTypeInformationModified || !MemoryTypeInformationVariableExists) {\r
+    Status = gRT->SetVariable (\r
+                    EFI_MEMORY_TYPE_INFORMATION_VARIABLE_NAME,\r
+                    &gEfiMemoryTypeInformationGuid,\r
+                    EFI_VARIABLE_NON_VOLATILE  | EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS,\r
+                    VariableSize,\r
+                    PreviousMemoryTypeInformation\r
+                    );\r
+\r
+    //\r
+    // If the Memory Type Information settings have been modified, then reset the platform\r
+    // so the new Memory Type Information setting will be used to guarantee that an S4\r
+    // entry/resume cycle will not fail.\r
+    //\r
+    if (MemoryTypeInformationModified && PcdGetBool (PcdResetOnMemoryTypeInformationChange)) {\r
+      DEBUG ((EFI_D_INFO, "Memory Type Information settings change. Warm Reset!!!\n"));\r
+      gRT->ResetSystem (EfiResetWarm, EFI_SUCCESS, 0, NULL);\r
+    }\r
+  }\r
+}\r
+\r
+/**\r
+  This routine is kept for backward compatibility.\r
+**/\r
+VOID\r
+EFIAPI\r
+BdsLibSaveMemoryTypeInformation (\r
+  VOID\r
+  )\r
+{\r
+}\r
+\r
+\r
+/**\r
+  Identify a user and, if authenticated, returns the current user profile handle.\r
+\r
+  @param[out]  User           Point to user profile handle.\r
+  \r
+  @retval EFI_SUCCESS         User is successfully identified, or user identification\r
+                              is not supported.\r
+  @retval EFI_ACCESS_DENIED   User is not successfully identified\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+BdsLibUserIdentify (\r
+  OUT EFI_USER_PROFILE_HANDLE         *User\r
+  )\r
+{\r
+  EFI_STATUS                          Status;\r
+  EFI_USER_MANAGER_PROTOCOL           *Manager;\r
+  \r
+  Status = gBS->LocateProtocol (\r
+                  &gEfiUserManagerProtocolGuid,\r
+                  NULL,\r
+                  (VOID **) &Manager\r
+                  );\r
+  if (EFI_ERROR (Status)) {\r
+    return EFI_SUCCESS;\r
+  }\r
+\r
+  return Manager->Identify (Manager, User);\r
+}\r
+\r

diff --git a/Vlv2TbltDevicePkg/Override/IntelFrameworkModulePkg/Library/GenericBdsLib/DevicePath.c b/Vlv2TbltDevicePkg/Override/IntelFrameworkModulePkg/Library/GenericBdsLib/DevicePath.c
new file mode 100644 (file)
index 0000000..2f22e7d
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Override/IntelFrameworkModulePkg/Library/GenericBdsLib/DevicePath.c
@@ -0,0 +1,33 @@
+/** @file\r
+  BDS internal function define the default device path string, it can be\r
+  replaced by platform device path.\r
+\r
+Copyright (c) 2004 - 2013, Intel Corporation. All rights reserved.<BR>\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution.  The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#include "InternalBdsLib.h"\r
+\r
+/**\r
+  This function converts an input device structure to a Unicode string.\r
+\r
+  @param DevPath                  A pointer to the device path structure.\r
+\r
+  @return A new allocated Unicode string that represents the device path.\r
+\r
+**/\r
+CHAR16 *\r
+EFIAPI\r
+DevicePathToStr (\r
+  IN EFI_DEVICE_PATH_PROTOCOL     *DevPath\r
+  )\r
+{\r
+  return ConvertDevicePathToText (DevPath, TRUE, TRUE);\r
+}\r

diff --git a/Vlv2TbltDevicePkg/Override/IntelFrameworkModulePkg/Library/GenericBdsLib/GenericBdsLib.inf b/Vlv2TbltDevicePkg/Override/IntelFrameworkModulePkg/Library/GenericBdsLib/GenericBdsLib.inf
new file mode 100644 (file)
index 0000000..2fb9916
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Override/IntelFrameworkModulePkg/Library/GenericBdsLib/GenericBdsLib.inf
@@ -0,0 +1,114 @@
+## @file\r
+#  \r
+#  General BDS defines and produce general interfaces for platform BDS driver including:\r
+#  1) BDS boot policy interface;\r
+#  2) BDS boot device connect interface;\r
+#  3) BDS Misc interfaces for mainting boot variable, ouput string, etc.\r
+#  \r
+#  Copyright (c) 2007 - 2013, Intel Corporation. All rights reserved.<BR>\r
+#  This program and the accompanying materials\r
+#  are licensed and made available under the terms and conditions of the BSD License\r
+#  which accompanies this distribution.  The full text of the license may be found at\r
+#  http://opensource.org/licenses/bsd-license.php\r
+#  \r
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#  \r
+##\r
+\r
+[Defines]\r
+  INF_VERSION                    = 0x00010005\r
+  BASE_NAME                      = GenericBdsLib\r
+  FILE_GUID                      = e405ec31-ccaa-4dd4-83e8-0aec01703f7e\r
+  MODULE_TYPE                    = DXE_DRIVER\r
+  VERSION_STRING                 = 1.0\r
+  LIBRARY_CLASS                  = GenericBdsLib|DXE_DRIVER DXE_RUNTIME_DRIVER UEFI_APPLICATION \r
+  CONSTRUCTOR                    = GenericBdsLibConstructor\r
+\r
+#\r
+# The following information is for reference only and not required by the build tools.\r
+#\r
+#  VALID_ARCHITECTURES           = IA32 X64 IPF EBC\r
+#\r
+\r
+[Sources]\r
+  DevicePath.c\r
+  Performance.c\r
+  BdsConnect.c\r
+  BdsMisc.c\r
+  BdsConsole.c\r
+  BdsBoot.c\r
+  InternalBdsLib.h\r
+  String.h\r
+  String.c\r
+  GenericBdsStrings.uni\r
+  \r
+[Packages]\r
+  MdePkg/MdePkg.dec\r
+  MdeModulePkg/MdeModulePkg.dec\r
+  IntelFrameworkPkg/IntelFrameworkPkg.dec\r
+  IntelFrameworkModulePkg/IntelFrameworkModulePkg.dec\r
+\r
+[LibraryClasses]\r
+  DevicePathLib\r
+  PeCoffGetEntryPointLib\r
+  BaseLib\r
+  HobLib\r
+  UefiRuntimeServicesTableLib\r
+  DxeServicesTableLib\r
+  MemoryAllocationLib\r
+  UefiLib\r
+  UefiBootServicesTableLib\r
+  BaseMemoryLib\r
+  DebugLib\r
+  PrintLib\r
+  PcdLib\r
+  PerformanceLib\r
+  TimerLib\r
+  DxeServicesLib\r
+  HiiLib\r
+  ReportStatusCodeLib\r
+\r
+[Guids]\r
+  gEfiMemoryTypeInformationGuid                 ## CONSUMES ## GUID (The identifier of memory type information type in system table)\r
+  gEfiGlobalVariableGuid                        ## SOMETIMES_PRODUCES ## Variable:L"BootCurrent" (The boot option of current boot)\r
+  gEfiFileInfoGuid                              ## CONSUMES ## GUID\r
+  gPerformanceProtocolGuid                      ## SOMETIMES_PRODUCES ## Variable:L"PerfDataMemAddr" (The ACPI address of performance data)\r
+  gEfiUartDevicePathGuid                        ## CONSUMES ## GUID (Identify the device path for UARD device)\r
+  gLastEnumLangGuid                             ## SOMETIMES_PRODUCES ## Variable:L"LastEnumLang" (Platform language at last time enumeration.)\r
+  gHdBootDevicePathVariablGuid                  ## SOMETIMES_PRODUCES ## Variable:L"HDDP" (The device path of Boot file on Hard device.)\r
+  gBdsLibStringPackageGuid                      ## PRODUCES ## GUID (HII String PackageList Guid)\r
+  gEfiLegacyDevOrderVariableGuid                ## CONSUMES ## GUID\r
+\r
+[Protocols]\r
+  gEfiSimpleFileSystemProtocolGuid              # PROTOCOL CONSUMES\r
+  gEfiLoadFileProtocolGuid                      # PROTOCOL CONSUMES\r
+  gEfiSimpleTextOutProtocolGuid                 # PROTOCOL CONSUMES\r
+  gEfiPciIoProtocolGuid                         # PROTOCOL CONSUMES\r
+  gEfiLoadedImageProtocolGuid                   # PROTOCOL CONSUMES\r
+  gEfiSimpleNetworkProtocolGuid                 # PROTOCOL CONSUMES\r
+  gEfiDebugPortProtocolGuid                     # PROTOCOL CONSUMES\r
+  gEfiSimpleTextInProtocolGuid                  # PROTOCOL CONSUMES\r
+  gEfiBlockIoProtocolGuid                       # PROTOCOL CONSUMES\r
+  gEfiFirmwareVolume2ProtocolGuid               # PROTOCOL CONSUMES\r
+  gEfiLegacyBiosProtocolGuid                    # PROTOCOL SOMETIMES_CONSUMES\r
+  gEfiCpuArchProtocolGuid                       # PROTOCOL CONSUMES\r
+  gEfiDevicePathProtocolGuid                    # PROTOCOL CONSUMES\r
+  gEfiAcpiS3SaveProtocolGuid                    # PROTOCOL CONSUMES\r
+  gEfiGraphicsOutputProtocolGuid                # PROTOCOL SOMETIMES_CONSUMES\r
+  gEfiUgaDrawProtocolGuid |gEfiMdePkgTokenSpaceGuid.PcdUgaConsumeSupport # PROTOCOL SOMETIMES_CONSUMES\r
+  gEfiOEMBadgingProtocolGuid                    # PROTOCOL CONSUMES\r
+  gEfiHiiFontProtocolGuid                       # PROTOCOL CONSUMES\r
+  gEfiUserManagerProtocolGuid                   # PROTOCOL CONSUMES\r
+  gEfiUsbIoProtocolGuid                         # PROTOCOL SOMETIMES_CONSUMES\r
+  gEfiBootLogoProtocolGuid                      # PROTOCOL SOMETIMES_CONSUMES\r
+\r
+[FeaturePcd]\r
+  gEfiMdePkgTokenSpaceGuid.PcdUgaConsumeSupport\r
+  gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdBootlogoOnlyEnable\r
+\r
+[Pcd]\r
+  gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange\r
+  gEfiMdeModulePkgTokenSpaceGuid.PcdProgressCodeOsLoaderLoad\r
+  gEfiMdeModulePkgTokenSpaceGuid.PcdProgressCodeOsLoaderStart\r
+  gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdShellFile\r

diff --git a/Vlv2TbltDevicePkg/Override/IntelFrameworkModulePkg/Library/GenericBdsLib/GenericBdsStrings.uni b/Vlv2TbltDevicePkg/Override/IntelFrameworkModulePkg/Library/GenericBdsLib/GenericBdsStrings.uni
new file mode 100644 (file)
index 0000000..81621d6
Binary files /dev/null and b/Vlv2TbltDevicePkg/Override/IntelFrameworkModulePkg/Library/GenericBdsLib/GenericBdsStrings.uni differ

diff --git a/Vlv2TbltDevicePkg/Override/IntelFrameworkModulePkg/Library/GenericBdsLib/InternalBdsLib.h b/Vlv2TbltDevicePkg/Override/IntelFrameworkModulePkg/Library/GenericBdsLib/InternalBdsLib.h
new file mode 100644 (file)
index 0000000..80b1f49
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Override/IntelFrameworkModulePkg/Library/GenericBdsLib/InternalBdsLib.h
@@ -0,0 +1,150 @@
+/** @file\r
+  BDS library definition, include the file and data structure\r
+\r
+Copyright (c) 2004 - 2013, Intel Corporation. All rights reserved.<BR>\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution.  The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#ifndef _INTERNAL_BDS_LIB_H_\r
+#define _INTERNAL_BDS_LIB_H_\r
+\r
+#include <FrameworkDxe.h>\r
+\r
+#include <IndustryStandard/Pci.h>\r
+#include <IndustryStandard/PeImage.h>\r
+\r
+#include <Protocol/BlockIo.h>\r
+#include <Protocol/LoadedImage.h>\r
+#include <Protocol/Cpu.h>\r
+#include <Protocol/SimpleFileSystem.h>\r
+#include <Protocol/LoadFile.h>\r
+#include <Protocol/DebugPort.h>\r
+#include <Protocol/DevicePath.h>\r
+#include <Protocol/SimpleTextIn.h>\r
+#include <Protocol/LegacyBios.h>\r
+#include <Protocol/SimpleTextOut.h>\r
+#include <Protocol/SimpleNetwork.h>\r
+#include <Protocol/FirmwareVolume2.h>\r
+#include <Protocol/PciIo.h>\r
+#include <Protocol/AcpiS3Save.h>\r
+#include <Protocol/OEMBadging.h>\r
+#include <Protocol/GraphicsOutput.h>\r
+#include <Protocol/UgaDraw.h>\r
+#include <Protocol/HiiFont.h>\r
+#include <Protocol/HiiImage.h>\r
+#include <Protocol/UsbIo.h>\r
+#include <Protocol/BootLogo.h>\r
+\r
+#include <Guid/MemoryTypeInformation.h>\r
+#include <Guid/FileInfo.h>\r
+#include <Guid/GlobalVariable.h>\r
+#include <Guid/PcAnsi.h>\r
+#include <Guid/Performance.h>\r
+#include <Guid/BdsLibHii.h>\r
+#include <Guid/HdBootVariable.h>\r
+#include <Guid/LastEnumLang.h>\r
+#include <Guid/LegacyDevOrder.h>\r
+\r
+#include <Library/PrintLib.h>\r
+#include <Library/DebugLib.h>\r
+#include <Library/BaseMemoryLib.h>\r
+#include <Library/UefiBootServicesTableLib.h>\r
+#include <Library/UefiLib.h>\r
+#include <Library/MemoryAllocationLib.h>\r
+#include <Library/DxeServicesTableLib.h>\r
+#include <Library/UefiRuntimeServicesTableLib.h>\r
+#include <Library/HobLib.h>\r
+#include <Library/BaseLib.h>\r
+#include <Library/DevicePathLib.h>\r
+#include <Library/PerformanceLib.h>\r
+#include <Library/PcdLib.h>\r
+#include <Library/PeCoffGetEntryPointLib.h>\r
+#include <Library/GenericBdsLib.h>\r
+#include <Library/TimerLib.h>\r
+#include <Library/PcdLib.h>\r
+#include <Library/DxeServicesLib.h>\r
+#include <Library/ReportStatusCodeLib.h>\r
+\r
+#if !defined (EFI_REMOVABLE_MEDIA_FILE_NAME)\r
+    #if defined (MDE_CPU_EBC)\r
+        //\r
+        // Uefi specification only defines the default boot file name for IA32, X64\r
+        // and IPF processor, so need define boot file name for EBC architecture here.\r
+        //\r
+        #define EFI_REMOVABLE_MEDIA_FILE_NAME L"\\EFI\\BOOT\\BOOTEBC.EFI"\r
+    #else\r
+        #error "Can not determine the default boot file name for unknown processor type!"\r
+    #endif\r
+#endif\r
+\r
+/**\r
+\r
+  Writes performance data of booting into the allocated memory.\r
+  OS can process these records.\r
+\r
+  @param  Event                 The triggered event.\r
+  @param  Context               Context for this event.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+WriteBootToOsPerformanceData (\r
+  IN EFI_EVENT  Event,\r
+  IN VOID       *Context\r
+  );\r
+\r
+/**\r
+  Get the headers (dos, image, optional header) from an image\r
+\r
+  @param  Device                SimpleFileSystem device handle\r
+  @param  FileName              File name for the image\r
+  @param  DosHeader             Pointer to dos header\r
+  @param  Hdr                   The buffer in which to return the PE32, PE32+, or TE header.\r
+\r
+  @retval EFI_SUCCESS           Successfully get the machine type.\r
+  @retval EFI_NOT_FOUND         The file is not found.\r
+  @retval EFI_LOAD_ERROR        File is not a valid image file.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+BdsLibGetImageHeader (\r
+  IN  EFI_HANDLE                  Device,\r
+  IN  CHAR16                      *FileName,\r
+  OUT EFI_IMAGE_DOS_HEADER        *DosHeader,\r
+  OUT EFI_IMAGE_OPTIONAL_HEADER_PTR_UNION   Hdr\r
+  );\r
+\r
+/**\r
+  This routine adjust the memory information for different memory type and \r
+  save them into the variables for next boot.\r
+**/\r
+VOID\r
+BdsSetMemoryTypeInformationVariable (\r
+  VOID\r
+  );\r
+\r
+/**\r
+  Validate the EFI Boot#### or Driver#### variable (VendorGuid/Name)\r
+\r
+  @param  Variable              Boot#### variable data.\r
+  @param  VariableSize          Returns the size of the EFI variable that was read\r
+\r
+  @retval TRUE                  The variable data is correct.\r
+  @retval FALSE                 The variable data is corrupted.\r
+\r
+**/\r
+BOOLEAN \r
+ValidateOption (\r
+  UINT8                     *Variable,\r
+  UINTN                     VariableSize\r
+  );\r
+\r
+#endif // _BDS_LIB_H_\r

diff --git a/Vlv2TbltDevicePkg/Override/IntelFrameworkModulePkg/Library/GenericBdsLib/Performance.c b/Vlv2TbltDevicePkg/Override/IntelFrameworkModulePkg/Library/GenericBdsLib/Performance.c
new file mode 100644 (file)
index 0000000..047d2a7
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Override/IntelFrameworkModulePkg/Library/GenericBdsLib/Performance.c
@@ -0,0 +1,358 @@
+/** @file\r
+  This file include the file which can help to get the system\r
+  performance, all the function will only include if the performance\r
+  switch is set.\r
+\r
+Copyright (c) 2004 - 2013, Intel Corporation. All rights reserved.<BR>\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution.  The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#include "InternalBdsLib.h"\r
+\r
+PERF_HEADER               mPerfHeader;\r
+PERF_DATA                 mPerfData;\r
+EFI_PHYSICAL_ADDRESS      mAcpiLowMemoryBase = 0x0FFFFFFFFULL;\r
+\r
+/**\r
+  Get the short verion of PDB file name to be\r
+  used in performance data logging.\r
+\r
+  @param PdbFileName     The long PDB file name.\r
+  @param GaugeString     The output string to be logged by performance logger.\r
+\r
+**/\r
+VOID\r
+GetShortPdbFileName (\r
+  IN  CONST CHAR8  *PdbFileName,\r
+  OUT       CHAR8  *GaugeString\r
+  )\r
+{\r
+  UINTN Index;\r
+  UINTN Index1;\r
+  UINTN StartIndex;\r
+  UINTN EndIndex;\r
+\r
+  if (PdbFileName == NULL) {\r
+    AsciiStrCpy (GaugeString, " ");\r
+  } else {\r
+    StartIndex = 0;\r
+    for (EndIndex = 0; PdbFileName[EndIndex] != 0; EndIndex++)\r
+      ;\r
+\r
+    for (Index = 0; PdbFileName[Index] != 0; Index++) {\r
+      if (PdbFileName[Index] == '\\') {\r
+        StartIndex = Index + 1;\r
+      }\r
+\r
+      if (PdbFileName[Index] == '.') {\r
+        EndIndex = Index;\r
+      }\r
+    }\r
+\r
+    Index1 = 0;\r
+    for (Index = StartIndex; Index < EndIndex; Index++) {\r
+      GaugeString[Index1] = PdbFileName[Index];\r
+      Index1++;\r
+      if (Index1 == PERF_TOKEN_LENGTH - 1) {\r
+        break;\r
+      }\r
+    }\r
+\r
+    GaugeString[Index1] = 0;\r
+  }\r
+\r
+  return ;\r
+}\r
+\r
+/**\r
+  Get the name from the Driver handle, which can be a handle with\r
+  EFI_LOADED_IMAGE_PROTOCOL or EFI_DRIVER_BINDING_PROTOCOL installed.\r
+  This name can be used in performance data logging.\r
+\r
+  @param Handle          Driver handle.\r
+  @param GaugeString     The output string to be logged by performance logger.\r
+\r
+**/\r
+VOID\r
+GetNameFromHandle (\r
+  IN  EFI_HANDLE     Handle,\r
+  OUT CHAR8          *GaugeString\r
+  )\r
+{\r
+  EFI_STATUS                  Status;\r
+  EFI_LOADED_IMAGE_PROTOCOL   *Image;\r
+  CHAR8                       *PdbFileName;\r
+  EFI_DRIVER_BINDING_PROTOCOL *DriverBinding;\r
+\r
+  AsciiStrCpy (GaugeString, " ");\r
+\r
+  //\r
+  // Get handle name from image protocol\r
+  //\r
+  Status = gBS->HandleProtocol (\r
+                  Handle,\r
+                  &gEfiLoadedImageProtocolGuid,\r
+                  (VOID **) &Image\r
+                  );\r
+\r
+  if (EFI_ERROR (Status)) {\r
+    Status = gBS->OpenProtocol (\r
+                    Handle,\r
+                    &gEfiDriverBindingProtocolGuid,\r
+                    (VOID **) &DriverBinding,\r
+                    NULL,\r
+                    NULL,\r
+                    EFI_OPEN_PROTOCOL_GET_PROTOCOL\r
+                    );\r
+    if (EFI_ERROR (Status)) {\r
+      return ;\r
+    }\r
+    //\r
+    // Get handle name from image protocol\r
+    //\r
+    Status = gBS->HandleProtocol (\r
+                    DriverBinding->ImageHandle,\r
+                    &gEfiLoadedImageProtocolGuid,\r
+                    (VOID **) &Image\r
+                    );\r
+  }\r
+\r
+  PdbFileName = PeCoffLoaderGetPdbPointer (Image->ImageBase);\r
+\r
+  if (PdbFileName != NULL) {\r
+    GetShortPdbFileName (PdbFileName, GaugeString);\r
+  }\r
+\r
+  return ;\r
+}\r
+\r
+/**\r
+\r
+  Writes performance data of booting into the allocated memory.\r
+  OS can process these records.\r
+\r
+  @param  Event                 The triggered event.\r
+  @param  Context               Context for this event.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+WriteBootToOsPerformanceData (\r
+  IN EFI_EVENT  Event,\r
+  IN VOID       *Context\r
+  )\r
+{\r
+  EFI_STATUS                Status;\r
+  UINT32                    LimitCount;\r
+  EFI_HANDLE                *Handles;\r
+  UINTN                     NoHandles;\r
+  CHAR8                     GaugeString[PERF_TOKEN_LENGTH];\r
+  UINT8                     *Ptr;\r
+  UINT32                    Index;\r
+  UINT64                    Ticker;\r
+  UINT64                    Freq;\r
+  UINT32                    Duration;\r
+  UINTN                     LogEntryKey;\r
+  CONST VOID                *Handle;\r
+  CONST CHAR8               *Token;\r
+  CONST CHAR8               *Module;\r
+  UINT64                    StartTicker;\r
+  UINT64                    EndTicker;\r
+  UINT64                    StartValue;\r
+  UINT64                    EndValue;\r
+  BOOLEAN                   CountUp;\r
+  UINTN                     EntryIndex;\r
+  UINTN                     NumPerfEntries;\r
+  //\r
+  // List of flags indicating PerfEntry contains DXE handle\r
+  //\r
+  BOOLEAN                   *PerfEntriesAsDxeHandle;\r
+  UINTN                     VarSize;\r
+\r
+  //\r
+  // Record the performance data for End of BDS\r
+  //\r
+  PERF_END(NULL, "BDS", NULL, 0);\r
+\r
+  //\r
+  // Retrieve time stamp count as early as possible\r
+  //\r
+  Ticker  = GetPerformanceCounter ();\r
+\r
+  Freq    = GetPerformanceCounterProperties (&StartValue, &EndValue);\r
+  \r
+  Freq    = DivU64x32 (Freq, 1000);\r
+\r
+  mPerfHeader.CpuFreq = Freq;\r
+\r
+  //\r
+  // Record BDS raw performance data\r
+  //\r
+  if (EndValue >= StartValue) {\r
+    mPerfHeader.BDSRaw = Ticker - StartValue;\r
+    CountUp            = TRUE;\r
+  } else {\r
+    mPerfHeader.BDSRaw = StartValue - Ticker;\r
+    CountUp            = FALSE;\r
+  }\r
+\r
+  if (mAcpiLowMemoryBase == 0x0FFFFFFFF) {\r
+    VarSize = sizeof (EFI_PHYSICAL_ADDRESS);\r
+    Status = gRT->GetVariable (\r
+                    L"PerfDataMemAddr",\r
+                    &gPerformanceProtocolGuid,\r
+                    NULL,\r
+                    &VarSize,\r
+                    &mAcpiLowMemoryBase\r
+                    );\r
+    if (EFI_ERROR (Status)) {\r
+      //\r
+      // Fail to get the variable, return.\r
+      //\r
+      return;\r
+    }\r
+  }\r
+\r
+  //\r
+  // Put Detailed performance data into memory\r
+  //\r
+  Handles = NULL;\r
+  Status = gBS->LocateHandleBuffer (\r
+                  AllHandles,\r
+                  NULL,\r
+                  NULL,\r
+                  &NoHandles,\r
+                  &Handles\r
+                  );\r
+  if (EFI_ERROR (Status)) {\r
+    return ;\r
+  }\r
+\r
+  Ptr        = (UINT8 *) ((UINT32) mAcpiLowMemoryBase + sizeof (PERF_HEADER));\r
+  LimitCount = (UINT32) (PERF_DATA_MAX_LENGTH - sizeof (PERF_HEADER)) / sizeof (PERF_DATA);\r
+\r
+  NumPerfEntries = 0;\r
+  LogEntryKey    = 0;\r
+  while ((LogEntryKey = GetPerformanceMeasurement (\r
+                          LogEntryKey,\r
+                          &Handle,\r
+                          &Token,\r
+                          &Module,\r
+                          &StartTicker,\r
+                          &EndTicker)) != 0) {\r
+    NumPerfEntries++;\r
+  }\r
+  PerfEntriesAsDxeHandle = AllocateZeroPool (NumPerfEntries * sizeof (BOOLEAN));\r
+  ASSERT (PerfEntriesAsDxeHandle != NULL);\r
+  \r
+  //\r
+  // Get DXE drivers performance\r
+  //\r
+  for (Index = 0; Index < NoHandles; Index++) {\r
+    Ticker = 0;\r
+    LogEntryKey = 0;\r
+    EntryIndex  = 0;\r
+    while ((LogEntryKey = GetPerformanceMeasurement (\r
+                            LogEntryKey,\r
+                            &Handle,\r
+                            &Token,\r
+                            &Module,\r
+                            &StartTicker,\r
+                            &EndTicker)) != 0) {\r
+      if (Handle == Handles[Index] && !PerfEntriesAsDxeHandle[EntryIndex]) {\r
+        PerfEntriesAsDxeHandle[EntryIndex] = TRUE;\r
+      }\r
+      EntryIndex++;\r
+      if ((Handle == Handles[Index]) && (EndTicker != 0)) {\r
+        if (StartTicker == 1) {\r
+          StartTicker = StartValue;\r
+        }\r
+        if (EndTicker == 1) {\r
+          EndTicker = StartValue;\r
+        }\r
+        Ticker += CountUp ? (EndTicker - StartTicker) : (StartTicker - EndTicker);\r
+      }\r
+    }\r
+\r
+    Duration = (UINT32) DivU64x32 (Ticker, (UINT32) Freq);\r
+\r
+    if (Duration > 0) {\r
+\r
+      GetNameFromHandle (Handles[Index], GaugeString);\r
+\r
+      AsciiStrCpy (mPerfData.Token, GaugeString);\r
+      mPerfData.Duration = Duration;\r
+\r
+      CopyMem (Ptr, &mPerfData, sizeof (PERF_DATA));\r
+      Ptr += sizeof (PERF_DATA);\r
+\r
+      mPerfHeader.Count++;\r
+      if (mPerfHeader.Count == LimitCount) {\r
+        goto Done;\r
+      }\r
+    }\r
+  }\r
+\r
+  //\r
+  // Get inserted performance data\r
+  //\r
+  LogEntryKey = 0;\r
+  EntryIndex  = 0;\r
+  while ((LogEntryKey = GetPerformanceMeasurement (\r
+                          LogEntryKey,\r
+                          &Handle,\r
+                          &Token,\r
+                          &Module,\r
+                          &StartTicker,\r
+                          &EndTicker)) != 0) {\r
+    if (!PerfEntriesAsDxeHandle[EntryIndex] && EndTicker != 0) {\r
+\r
+      ZeroMem (&mPerfData, sizeof (PERF_DATA));\r
+\r
+      AsciiStrnCpy (mPerfData.Token, Token, PERF_TOKEN_LENGTH);\r
+      if (StartTicker == 1) {\r
+        StartTicker = StartValue;\r
+      }\r
+      if (EndTicker == 1) {\r
+        EndTicker = StartValue;\r
+      }\r
+      Ticker = CountUp ? (EndTicker - StartTicker) : (StartTicker - EndTicker);\r
+\r
+      mPerfData.Duration = (UINT32) DivU64x32 (Ticker, (UINT32) Freq);\r
+\r
+      CopyMem (Ptr, &mPerfData, sizeof (PERF_DATA));\r
+      Ptr += sizeof (PERF_DATA);\r
+\r
+      mPerfHeader.Count++;\r
+      if (mPerfHeader.Count == LimitCount) {\r
+        goto Done;\r
+      }\r
+    }\r
+    EntryIndex++;\r
+  }\r
+\r
+Done:\r
+\r
+  FreePool (Handles);\r
+  FreePool (PerfEntriesAsDxeHandle);\r
+\r
+  mPerfHeader.Signiture = PERFORMANCE_SIGNATURE;\r
+\r
+  //\r
+  // Put performance data to Reserved memory\r
+  //\r
+  CopyMem (\r
+    (UINTN *) (UINTN) mAcpiLowMemoryBase,\r
+    &mPerfHeader,\r
+    sizeof (PERF_HEADER)\r
+    );\r
+\r
+  return ;\r
+}\r

diff --git a/Vlv2TbltDevicePkg/Override/IntelFrameworkModulePkg/Library/GenericBdsLib/String.c b/Vlv2TbltDevicePkg/Override/IntelFrameworkModulePkg/Library/GenericBdsLib/String.c
new file mode 100644 (file)
index 0000000..7628716
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Override/IntelFrameworkModulePkg/Library/GenericBdsLib/String.c
@@ -0,0 +1,32 @@
+/** @file\r
+  String support\r
+\r
+Copyright (c) 2010, Intel Corporation. All rights reserved.<BR>\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution.  The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+#include "String.h"\r
+\r
+/**\r
+  Get string by string id from HII Interface\r
+\r
+\r
+  @param Id              String ID.\r
+\r
+  @retval  CHAR16 *  String from ID.\r
+  @retval  NULL      If error occurs.\r
+\r
+**/\r
+CHAR16 *\r
+BdsLibGetStringById (\r
+  IN  EFI_STRING_ID   Id\r
+  )\r
+{\r
+  return HiiGetString (gBdsLibStringPackHandle, Id, NULL);\r
+}\r

diff --git a/Vlv2TbltDevicePkg/Override/IntelFrameworkModulePkg/Library/GenericBdsLib/String.h b/Vlv2TbltDevicePkg/Override/IntelFrameworkModulePkg/Library/GenericBdsLib/String.h
new file mode 100644 (file)
index 0000000..13b745d
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Override/IntelFrameworkModulePkg/Library/GenericBdsLib/String.h
@@ -0,0 +1,48 @@
+/** @file\r
+  String support\r
+\r
+Copyright (c) 2010, Intel Corporation. All rights reserved.<BR>\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution.  The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#ifndef _STRING_H_\r
+#define _STRING_H_\r
+\r
+#include <Library/HiiLib.h>\r
+#include <Library/DebugLib.h>\r
+#include <Library/DevicePathLib.h>\r
+#include <Library/UefiLib.h>\r
+#include <Library/UefiBootServicesTableLib.h>\r
+\r
+extern EFI_HII_HANDLE gBdsLibStringPackHandle;\r
+\r
+//\r
+// This is the VFR compiler generated header file which defines the\r
+// string identifiers.\r
+//\r
+\r
+extern UINT8  GenericBdsLibStrings[];\r
+\r
+/**\r
+  Get string by string id from HII Interface\r
+\r
+\r
+  @param Id              String ID.\r
+\r
+  @retval  CHAR16 *  String from ID.\r
+  @retval  NULL      If error occurs.\r
+\r
+**/\r
+CHAR16 *\r
+BdsLibGetStringById (\r
+  IN  EFI_STRING_ID   Id\r
+  );\r
+\r
+#endif // _STRING_H_\r

diff --git a/Vlv2TbltDevicePkg/Override/MdeModulePkg/Universal/Console/ConSplitterDxe/ComponentName.c b/Vlv2TbltDevicePkg/Override/MdeModulePkg/Universal/Console/ConSplitterDxe/ComponentName.c
new file mode 100644 (file)
index 0000000..9ad1726
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Override/MdeModulePkg/Universal/Console/ConSplitterDxe/ComponentName.c
@@ -0,0 +1,776 @@
+/** @file\r
+  UEFI Component Name(2) protocol implementation for ConSplitter driver.\r
+\r
+Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.<BR>\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution.  The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#include "ConSplitter.h"\r
+\r
+//\r
+// EFI Component Name Protocol\r
+//\r
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_COMPONENT_NAME_PROTOCOL  gConSplitterConInComponentName = {\r
+  ConSplitterComponentNameGetDriverName,\r
+  ConSplitterConInComponentNameGetControllerName,\r
+  "eng"\r
+};\r
+\r
+//\r
+// EFI Component Name 2 Protocol\r
+//\r
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_COMPONENT_NAME2_PROTOCOL gConSplitterConInComponentName2 = {\r
+  (EFI_COMPONENT_NAME2_GET_DRIVER_NAME) ConSplitterComponentNameGetDriverName,\r
+  (EFI_COMPONENT_NAME2_GET_CONTROLLER_NAME) ConSplitterConInComponentNameGetControllerName,\r
+  "en"\r
+};\r
+\r
+\r
+//\r
+// EFI Component Name Protocol\r
+//\r
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_COMPONENT_NAME_PROTOCOL  gConSplitterSimplePointerComponentName = {\r
+  ConSplitterComponentNameGetDriverName,\r
+  ConSplitterSimplePointerComponentNameGetControllerName,\r
+  "eng"\r
+};\r
+\r
+//\r
+// EFI Component Name 2 Protocol\r
+//\r
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_COMPONENT_NAME2_PROTOCOL gConSplitterSimplePointerComponentName2 = {\r
+  (EFI_COMPONENT_NAME2_GET_DRIVER_NAME) ConSplitterComponentNameGetDriverName,\r
+  (EFI_COMPONENT_NAME2_GET_CONTROLLER_NAME) ConSplitterSimplePointerComponentNameGetControllerName,\r
+  "en"\r
+};\r
+\r
+//\r
+// EFI Component Name Protocol\r
+//\r
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_COMPONENT_NAME_PROTOCOL gConSplitterAbsolutePointerComponentName = {\r
+  ConSplitterComponentNameGetDriverName,\r
+  ConSplitterAbsolutePointerComponentNameGetControllerName,\r
+  "eng"\r
+};\r
+\r
+//\r
+// EFI Component Name 2 Protocol\r
+//\r
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_COMPONENT_NAME2_PROTOCOL gConSplitterAbsolutePointerComponentName2 = {\r
+  (EFI_COMPONENT_NAME2_GET_DRIVER_NAME) ConSplitterComponentNameGetDriverName,\r
+  (EFI_COMPONENT_NAME2_GET_CONTROLLER_NAME) ConSplitterAbsolutePointerComponentNameGetControllerName,\r
+  "en"\r
+};\r
+\r
+//\r
+// EFI Component Name Protocol\r
+//\r
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_COMPONENT_NAME_PROTOCOL  gConSplitterConOutComponentName = {\r
+  ConSplitterComponentNameGetDriverName,\r
+  ConSplitterConOutComponentNameGetControllerName,\r
+  "eng"\r
+};\r
+\r
+//\r
+// EFI Component Name 2 Protocol\r
+//\r
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_COMPONENT_NAME2_PROTOCOL gConSplitterConOutComponentName2 = {\r
+  (EFI_COMPONENT_NAME2_GET_DRIVER_NAME) ConSplitterComponentNameGetDriverName,\r
+  (EFI_COMPONENT_NAME2_GET_CONTROLLER_NAME) ConSplitterConOutComponentNameGetControllerName,\r
+  "en"\r
+};\r
+\r
+\r
+//\r
+// EFI Component Name Protocol\r
+//\r
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_COMPONENT_NAME_PROTOCOL  gConSplitterStdErrComponentName = {\r
+  ConSplitterComponentNameGetDriverName,\r
+  ConSplitterStdErrComponentNameGetControllerName,\r
+  "eng"\r
+};\r
+\r
+//\r
+// EFI Component Name 2 Protocol\r
+//\r
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_COMPONENT_NAME2_PROTOCOL gConSplitterStdErrComponentName2 = {\r
+  (EFI_COMPONENT_NAME2_GET_DRIVER_NAME) ConSplitterComponentNameGetDriverName,\r
+  (EFI_COMPONENT_NAME2_GET_CONTROLLER_NAME) ConSplitterStdErrComponentNameGetControllerName,\r
+  "en"\r
+};\r
+\r
+\r
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_UNICODE_STRING_TABLE mConSplitterDriverNameTable[] = {\r
+  {\r
+    "eng;en",\r
+    (CHAR16 *) L"Console Splitter Driver"\r
+  },\r
+  {\r
+    NULL,\r
+    NULL\r
+  }\r
+};\r
+\r
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_UNICODE_STRING_TABLE mConSplitterConInControllerNameTable[] = {\r
+  {\r
+    "eng;en",\r
+    (CHAR16 *) L"Primary Console Input Device"\r
+  },\r
+  {\r
+    NULL,\r
+    NULL\r
+  }\r
+};\r
+\r
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_UNICODE_STRING_TABLE mConSplitterSimplePointerControllerNameTable[] = {\r
+  {\r
+    "eng;en",\r
+    (CHAR16 *) L"Primary Simple Pointer Device"\r
+  },\r
+  {\r
+    NULL,\r
+    NULL\r
+  }\r
+};\r
+\r
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_UNICODE_STRING_TABLE mConSplitterAbsolutePointerControllerNameTable[] = {\r
+  {\r
+    "eng;en",\r
+    (CHAR16 *)L"Primary Absolute Pointer Device"\r
+  },\r
+  {\r
+    NULL,\r
+    NULL\r
+  }\r
+};\r
+\r
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_UNICODE_STRING_TABLE mConSplitterConOutControllerNameTable[] = {\r
+  {\r
+    "eng;en",\r
+    (CHAR16 *) L"Primary Console Output Device"\r
+  },\r
+  {\r
+    NULL,\r
+    NULL\r
+  }\r
+};\r
+\r
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_UNICODE_STRING_TABLE mConSplitterStdErrControllerNameTable[] = {\r
+  {\r
+    "eng;en",\r
+    (CHAR16 *) L"Primary Standard Error Device"\r
+  },\r
+  {\r
+    NULL,\r
+    NULL\r
+  }\r
+};\r
+\r
+/**\r
+  Retrieves a Unicode string that is the user readable name of the driver.\r
+\r
+  This function retrieves the user readable name of a driver in the form of a\r
+  Unicode string. If the driver specified by This has a user readable name in\r
+  the language specified by Language, then a pointer to the driver name is\r
+  returned in DriverName, and EFI_SUCCESS is returned. If the driver specified\r
+  by This does not support the language specified by Language,\r
+  then EFI_UNSUPPORTED is returned.\r
+\r
+  @param  This[in]              A pointer to the EFI_COMPONENT_NAME2_PROTOCOL or\r
+                                EFI_COMPONENT_NAME_PROTOCOL instance.\r
+\r
+  @param  Language[in]          A pointer to a Null-terminated ASCII string\r
+                                array indicating the language. This is the\r
+                                language of the driver name that the caller is\r
+                                requesting, and it must match one of the\r
+                                languages specified in SupportedLanguages. The\r
+                                number of languages supported by a driver is up\r
+                                to the driver writer. Language is specified\r
+                                in RFC 4646 or ISO 639-2 language code format.\r
+\r
+  @param  DriverName[out]       A pointer to the Unicode string to return.\r
+                                This Unicode string is the name of the\r
+                                driver specified by This in the language\r
+                                specified by Language.\r
+\r
+  @retval EFI_SUCCESS           The Unicode string for the Driver specified by\r
+                                This and the language specified by Language was\r
+                                returned in DriverName.\r
+\r
+  @retval EFI_INVALID_PARAMETER Language is NULL.\r
+\r
+  @retval EFI_INVALID_PARAMETER DriverName is NULL.\r
+\r
+  @retval EFI_UNSUPPORTED       The driver specified by This does not support\r
+                                the language specified by Language.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+ConSplitterComponentNameGetDriverName (\r
+  IN  EFI_COMPONENT_NAME_PROTOCOL  *This,\r
+  IN  CHAR8                        *Language,\r
+  OUT CHAR16                       **DriverName\r
+  )\r
+{\r
+  return LookupUnicodeString2 (\r
+           Language,\r
+           This->SupportedLanguages,\r
+           mConSplitterDriverNameTable,\r
+           DriverName,\r
+           (BOOLEAN)((This == &gConSplitterConInComponentName) || \r
+                     (This == &gConSplitterSimplePointerComponentName) ||\r
+                     (This == &gConSplitterAbsolutePointerComponentName) ||\r
+                     (This == &gConSplitterConOutComponentName) ||\r
+                     (This == &gConSplitterStdErrComponentName))\r
+           );\r
+}\r
+\r
+/**\r
+  Tests whether a controller handle is being managed by a specific driver and\r
+  the child handle is a child device of the controller.\r
+\r
+  @param  ControllerHandle     A handle for a controller to test.\r
+  @param  DriverBindingHandle  Specifies the driver binding handle for the\r
+                               driver.\r
+  @param  ProtocolGuid         Specifies the protocol that the driver specified\r
+                               by DriverBindingHandle opens in its Start()\r
+                               function.\r
+  @param  ChildHandle          A child handle to test.\r
+  @param  ConsumsedGuid        Supplies the protocol that the child controller\r
+                               opens on its parent controller.\r
+\r
+  @retval EFI_SUCCESS          ControllerHandle is managed by the driver\r
+                               specifed by DriverBindingHandle and ChildHandle\r
+                               is a child of the ControllerHandle.\r
+  @retval EFI_UNSUPPORTED      ControllerHandle is not managed by the driver\r
+                               specifed by DriverBindingHandle.\r
+  @retval EFI_UNSUPPORTED      ChildHandle is not a child of the\r
+                               ControllerHandle.\r
+\r
+**/\r
+EFI_STATUS\r
+ConSplitterTestControllerHandles (\r
+  IN  CONST EFI_HANDLE       ControllerHandle,\r
+  IN  CONST EFI_HANDLE       DriverBindingHandle,\r
+  IN  CONST EFI_GUID         *ProtocolGuid,\r
+  IN  EFI_HANDLE             ChildHandle,\r
+  IN  CONST EFI_GUID         *ConsumsedGuid\r
+  )\r
+{\r
+  EFI_STATUS                 Status;\r
+\r
+  //\r
+  // here ChildHandle is not an Optional parameter.\r
+  //\r
+  if (ChildHandle == NULL) {\r
+    return EFI_UNSUPPORTED;\r
+  }\r
+\r
+  //\r
+  // Tests whether a controller handle is being managed by a specific driver.\r
+  //\r
+  Status = EfiTestManagedDevice (\r
+             ControllerHandle,\r
+             DriverBindingHandle,\r
+             ProtocolGuid\r
+             );\r
+  if (EFI_ERROR (Status)) {\r
+    return Status;\r
+  }\r
+\r
+  //\r
+  // Tests whether a child handle is a child device of the controller.\r
+  //\r
+  Status = EfiTestChildHandle (\r
+             ControllerHandle,\r
+             ChildHandle,\r
+             ConsumsedGuid\r
+             );\r
+\r
+  return Status;\r
+}\r
+\r
+/**\r
+  Retrieves a Unicode string that is the user readable name of the controller\r
+  that is being managed by a driver.\r
+\r
+  This function retrieves the user readable name of the controller specified by\r
+  ControllerHandle and ChildHandle in the form of a Unicode string. If the\r
+  driver specified by This has a user readable name in the language specified by\r
+  Language, then a pointer to the controller name is returned in ControllerName,\r
+  and EFI_SUCCESS is returned.  If the driver specified by This is not currently\r
+  managing the controller specified by ControllerHandle and ChildHandle,\r
+  then EFI_UNSUPPORTED is returned.  If the driver specified by This does not\r
+  support the language specified by Language, then EFI_UNSUPPORTED is returned.\r
+\r
+  @param  This[in]              A pointer to the EFI_COMPONENT_NAME2_PROTOCOL or\r
+                                EFI_COMPONENT_NAME_PROTOCOL instance.\r
+\r
+  @param  ControllerHandle[in]  The handle of a controller that the driver\r
+                                specified by This is managing.  This handle\r
+                                specifies the controller whose name is to be\r
+                                returned.\r
+\r
+  @param  ChildHandle[in]       The handle of the child controller to retrieve\r
+                                the name of.  This is an optional parameter that\r
+                                may be NULL.  It will be NULL for device\r
+                                drivers.  It will also be NULL for a bus drivers\r
+                                that wish to retrieve the name of the bus\r
+                                controller.  It will not be NULL for a bus\r
+                                driver that wishes to retrieve the name of a\r
+                                child controller.\r
+\r
+  @param  Language[in]          A pointer to a Null-terminated ASCII string\r
+                                array indicating the language.  This is the\r
+                                language of the driver name that the caller is\r
+                                requesting, and it must match one of the\r
+                                languages specified in SupportedLanguages. The\r
+                                number of languages supported by a driver is up\r
+                                to the driver writer. Language is specified in\r
+                                RFC 4646 or ISO 639-2 language code format.\r
+\r
+  @param  ControllerName[out]   A pointer to the Unicode string to return.\r
+                                This Unicode string is the name of the\r
+                                controller specified by ControllerHandle and\r
+                                ChildHandle in the language specified by\r
+                                Language from the point of view of the driver\r
+                                specified by This.\r
+\r
+  @retval EFI_SUCCESS           The Unicode string for the user readable name in\r
+                                the language specified by Language for the\r
+                                driver specified by This was returned in\r
+                                DriverName.\r
+\r
+  @retval EFI_INVALID_PARAMETER ControllerHandle is NULL.\r
+\r
+  @retval EFI_INVALID_PARAMETER ChildHandle is not NULL and it is not a valid\r
+                                EFI_HANDLE.\r
+\r
+  @retval EFI_INVALID_PARAMETER Language is NULL.\r
+\r
+  @retval EFI_INVALID_PARAMETER ControllerName is NULL.\r
+\r
+  @retval EFI_UNSUPPORTED       The driver specified by This is not currently\r
+                                managing the controller specified by\r
+                                ControllerHandle and ChildHandle.\r
+\r
+  @retval EFI_UNSUPPORTED       The driver specified by This does not support\r
+                                the language specified by Language.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+ConSplitterConInComponentNameGetControllerName (\r
+  IN  EFI_COMPONENT_NAME_PROTOCOL                     *This,\r
+  IN  EFI_HANDLE                                      ControllerHandle,\r
+  IN  EFI_HANDLE                                      ChildHandle        OPTIONAL,\r
+  IN  CHAR8                                           *Language,\r
+  OUT CHAR16                                          **ControllerName\r
+  )\r
+{\r
+  EFI_STATUS                     Status;\r
+\r
+  Status = ConSplitterTestControllerHandles (\r
+             ControllerHandle,\r
+             gConSplitterConInDriverBinding.DriverBindingHandle,\r
+             &gEfiConsoleInDeviceGuid,\r
+             ChildHandle,\r
+             &gEfiConsoleInDeviceGuid\r
+             );\r
+  if (EFI_ERROR (Status)) {\r
+    return Status;\r
+  }\r
+\r
+  return LookupUnicodeString2 (\r
+           Language,\r
+           This->SupportedLanguages,\r
+           mConSplitterConInControllerNameTable,\r
+           ControllerName,\r
+           (BOOLEAN)(This == &gConSplitterConInComponentName)\r
+           );\r
+}\r
+\r
+/**\r
+  Retrieves a Unicode string that is the user readable name of the controller\r
+  that is being managed by a driver.\r
+\r
+  This function retrieves the user readable name of the controller specified by\r
+  ControllerHandle and ChildHandle in the form of a Unicode string. If the\r
+  driver specified by This has a user readable name in the language specified by\r
+  Language, then a pointer to the controller name is returned in ControllerName,\r
+  and EFI_SUCCESS is returned.  If the driver specified by This is not currently\r
+  managing the controller specified by ControllerHandle and ChildHandle,\r
+  then EFI_UNSUPPORTED is returned.  If the driver specified by This does not\r
+  support the language specified by Language, then EFI_UNSUPPORTED is returned.\r
+\r
+  @param  This[in]              A pointer to the EFI_COMPONENT_NAME2_PROTOCOL or\r
+                                EFI_COMPONENT_NAME_PROTOCOL instance.\r
+\r
+  @param  ControllerHandle[in]  The handle of a controller that the driver\r
+                                specified by This is managing.  This handle\r
+                                specifies the controller whose name is to be\r
+                                returned.\r
+\r
+  @param  ChildHandle[in]       The handle of the child controller to retrieve\r
+                                the name of.  This is an optional parameter that\r
+                                may be NULL.  It will be NULL for device\r
+                                drivers.  It will also be NULL for a bus drivers\r
+                                that wish to retrieve the name of the bus\r
+                                controller.  It will not be NULL for a bus\r
+                                driver that wishes to retrieve the name of a\r
+                                child controller.\r
+\r
+  @param  Language[in]          A pointer to a Null-terminated ASCII string\r
+                                array indicating the language.  This is the\r
+                                language of the driver name that the caller is\r
+                                requesting, and it must match one of the\r
+                                languages specified in SupportedLanguages. The\r
+                                number of languages supported by a driver is up\r
+                                to the driver writer. Language is specified in\r
+                                RFC 4646 or ISO 639-2 language code format.\r
+\r
+  @param  ControllerName[out]   A pointer to the Unicode string to return.\r
+                                This Unicode string is the name of the\r
+                                controller specified by ControllerHandle and\r
+                                ChildHandle in the language specified by\r
+                                Language from the point of view of the driver\r
+                                specified by This.\r
+\r
+  @retval EFI_SUCCESS           The Unicode string for the user readable name in\r
+                                the language specified by Language for the\r
+                                driver specified by This was returned in\r
+                                DriverName.\r
+\r
+  @retval EFI_INVALID_PARAMETER ControllerHandle is NULL.\r
+\r
+  @retval EFI_INVALID_PARAMETER ChildHandle is not NULL and it is not a valid\r
+                                EFI_HANDLE.\r
+\r
+  @retval EFI_INVALID_PARAMETER Language is NULL.\r
+\r
+  @retval EFI_INVALID_PARAMETER ControllerName is NULL.\r
+\r
+  @retval EFI_UNSUPPORTED       The driver specified by This is not currently\r
+                                managing the controller specified by\r
+                                ControllerHandle and ChildHandle.\r
+\r
+  @retval EFI_UNSUPPORTED       The driver specified by This does not support\r
+                                the language specified by Language.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+ConSplitterSimplePointerComponentNameGetControllerName (\r
+  IN  EFI_COMPONENT_NAME_PROTOCOL                     *This,\r
+  IN  EFI_HANDLE                                      ControllerHandle,\r
+  IN  EFI_HANDLE                                      ChildHandle        OPTIONAL,\r
+  IN  CHAR8                                           *Language,\r
+  OUT CHAR16                                          **ControllerName\r
+  )\r
+{\r
+  EFI_STATUS                  Status;\r
+\r
+  Status = ConSplitterTestControllerHandles (\r
+             ControllerHandle,\r
+             gConSplitterSimplePointerDriverBinding.DriverBindingHandle,\r
+             &gEfiSimplePointerProtocolGuid,\r
+             ChildHandle,\r
+             &gEfiSimplePointerProtocolGuid\r
+             );\r
+  if (EFI_ERROR (Status)) {\r
+    return Status;\r
+  }\r
+\r
+  return LookupUnicodeString2 (\r
+           Language,\r
+           This->SupportedLanguages,\r
+           mConSplitterSimplePointerControllerNameTable,\r
+           ControllerName,\r
+           (BOOLEAN)(This == &gConSplitterSimplePointerComponentName)\r
+           );\r
+}\r
+\r
+\r
+/**\r
+  Retrieves a Unicode string that is the user readable name of the controller\r
+  that is being managed by an EFI Driver.\r
+\r
+  @param  This                   A pointer to the EFI_COMPONENT_NAME_PROTOCOL\r
+                                 instance.\r
+  @param  ControllerHandle       The handle of a controller that the driver\r
+                                 specified by This is managing.  This handle\r
+                                 specifies the controller whose name is to be\r
+                                 returned.\r
+  @param  ChildHandle            The handle of the child controller to retrieve the\r
+                                 name of.  This is an optional parameter that may\r
+                                 be NULL.  It will be NULL for device drivers.  It\r
+                                 will also be NULL for a bus drivers that wish to\r
+                                 retrieve the name of the bus controller.  It will\r
+                                 not be NULL for a bus driver that wishes to\r
+                                 retrieve the name of a child controller.\r
+  @param  Language               A pointer to RFC4646 language identifier. This is\r
+                                 the language of the controller name that that the\r
+                                 caller is requesting, and it must match one of the\r
+                                 languages specified in SupportedLanguages.  The\r
+                                 number of languages supported by a driver is up to\r
+                                 the driver writer.\r
+  @param  ControllerName         A pointer to the Unicode string to return.  This\r
+                                 Unicode string is the name of the controller\r
+                                 specified by ControllerHandle and ChildHandle in\r
+                                 the language specified by Language from the point\r
+                                 of view of the driver specified by This.\r
+\r
+  @retval EFI_SUCCESS            The Unicode string for the user readable name in\r
+                                 the language specified by Language for the driver\r
+                                 specified by This was returned in DriverName.\r
+  @retval EFI_INVALID_PARAMETER  ControllerHandle is NULL.\r
+  @retval EFI_INVALID_PARAMETER  ChildHandle is not NULL and it is not a valid\r
+                                 EFI_HANDLE.\r
+  @retval EFI_INVALID_PARAMETER  Language is NULL.\r
+  @retval EFI_INVALID_PARAMETER  ControllerName is NULL.\r
+  @retval EFI_UNSUPPORTED        The driver specified by This is not currently\r
+                                 managing the controller specified by\r
+                                 ControllerHandle and ChildHandle.\r
+  @retval EFI_UNSUPPORTED        The driver specified by This does not support the\r
+                                 language specified by Language.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+ConSplitterAbsolutePointerComponentNameGetControllerName (\r
+  IN  EFI_COMPONENT_NAME_PROTOCOL                    *This,\r
+  IN  EFI_HANDLE                                      ControllerHandle,\r
+  IN  EFI_HANDLE                                      ChildHandle        OPTIONAL,\r
+  IN  CHAR8                                           *Language,\r
+  OUT CHAR16                                          **ControllerName\r
+  )\r
+{\r
+  EFI_STATUS                    Status;\r
+\r
+  Status = ConSplitterTestControllerHandles (\r
+             ControllerHandle,\r
+             gConSplitterAbsolutePointerDriverBinding.DriverBindingHandle,\r
+             &gEfiAbsolutePointerProtocolGuid,\r
+             ChildHandle,\r
+             &gEfiAbsolutePointerProtocolGuid\r
+             );\r
+  if (EFI_ERROR (Status)) {\r
+    return Status;\r
+  }\r
+\r
+  return LookupUnicodeString2 (\r
+           Language,\r
+           This->SupportedLanguages,\r
+           mConSplitterAbsolutePointerControllerNameTable,\r
+           ControllerName,\r
+           (BOOLEAN)(This == &gConSplitterAbsolutePointerComponentName)\r
+           );\r
+}\r
+\r
+/**\r
+  Retrieves a Unicode string that is the user readable name of the controller\r
+  that is being managed by a driver.\r
+\r
+  This function retrieves the user readable name of the controller specified by\r
+  ControllerHandle and ChildHandle in the form of a Unicode string. If the\r
+  driver specified by This has a user readable name in the language specified by\r
+  Language, then a pointer to the controller name is returned in ControllerName,\r
+  and EFI_SUCCESS is returned.  If the driver specified by This is not currently\r
+  managing the controller specified by ControllerHandle and ChildHandle,\r
+  then EFI_UNSUPPORTED is returned.  If the driver specified by This does not\r
+  support the language specified by Language, then EFI_UNSUPPORTED is returned.\r
+\r
+  @param  This[in]              A pointer to the EFI_COMPONENT_NAME2_PROTOCOL or\r
+                                EFI_COMPONENT_NAME_PROTOCOL instance.\r
+\r
+  @param  ControllerHandle[in]  The handle of a controller that the driver\r
+                                specified by This is managing.  This handle\r
+                                specifies the controller whose name is to be\r
+                                returned.\r
+\r
+  @param  ChildHandle[in]       The handle of the child controller to retrieve\r
+                                the name of.  This is an optional parameter that\r
+                                may be NULL.  It will be NULL for device\r
+                                drivers.  It will also be NULL for a bus drivers\r
+                                that wish to retrieve the name of the bus\r
+                                controller.  It will not be NULL for a bus\r
+                                driver that wishes to retrieve the name of a\r
+                                child controller.\r
+\r
+  @param  Language[in]          A pointer to a Null-terminated ASCII string\r
+                                array indicating the language.  This is the\r
+                                language of the driver name that the caller is\r
+                                requesting, and it must match one of the\r
+                                languages specified in SupportedLanguages. The\r
+                                number of languages supported by a driver is up\r
+                                to the driver writer. Language is specified in\r
+                                RFC 4646 or ISO 639-2 language code format.\r
+\r
+  @param  ControllerName[out]   A pointer to the Unicode string to return.\r
+                                This Unicode string is the name of the\r
+                                controller specified by ControllerHandle and\r
+                                ChildHandle in the language specified by\r
+                                Language from the point of view of the driver\r
+                                specified by This.\r
+\r
+  @retval EFI_SUCCESS           The Unicode string for the user readable name in\r
+                                the language specified by Language for the\r
+                                driver specified by This was returned in\r
+                                DriverName.\r
+\r
+  @retval EFI_INVALID_PARAMETER ControllerHandle is NULL.\r
+\r
+  @retval EFI_INVALID_PARAMETER ChildHandle is not NULL and it is not a valid\r
+                                EFI_HANDLE.\r
+\r
+  @retval EFI_INVALID_PARAMETER Language is NULL.\r
+\r
+  @retval EFI_INVALID_PARAMETER ControllerName is NULL.\r
+\r
+  @retval EFI_UNSUPPORTED       The driver specified by This is not currently\r
+                                managing the controller specified by\r
+                                ControllerHandle and ChildHandle.\r
+\r
+  @retval EFI_UNSUPPORTED       The driver specified by This does not support\r
+                                the language specified by Language.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+ConSplitterConOutComponentNameGetControllerName (\r
+  IN  EFI_COMPONENT_NAME_PROTOCOL                     *This,\r
+  IN  EFI_HANDLE                                      ControllerHandle,\r
+  IN  EFI_HANDLE                                      ChildHandle        OPTIONAL,\r
+  IN  CHAR8                                           *Language,\r
+  OUT CHAR16                                          **ControllerName\r
+  )\r
+{\r
+  EFI_STATUS                       Status;\r
+\r
+  Status = ConSplitterTestControllerHandles (\r
+             ControllerHandle,\r
+             gConSplitterConOutDriverBinding.DriverBindingHandle,\r
+             &gEfiConsoleOutDeviceGuid,\r
+             ChildHandle,\r
+             &gEfiConsoleOutDeviceGuid\r
+             );\r
+  if (EFI_ERROR (Status)) {\r
+    return Status;\r
+  }\r
+\r
+  return LookupUnicodeString2 (\r
+           Language,\r
+           This->SupportedLanguages,\r
+           mConSplitterConOutControllerNameTable,\r
+           ControllerName,\r
+           (BOOLEAN)(This == &gConSplitterConOutComponentName)\r
+           );\r
+}\r
+\r
+/**\r
+  Retrieves a Unicode string that is the user readable name of the controller\r
+  that is being managed by a driver.\r
+\r
+  This function retrieves the user readable name of the controller specified by\r
+  ControllerHandle and ChildHandle in the form of a Unicode string. If the\r
+  driver specified by This has a user readable name in the language specified by\r
+  Language, then a pointer to the controller name is returned in ControllerName,\r
+  and EFI_SUCCESS is returned.  If the driver specified by This is not currently\r
+  managing the controller specified by ControllerHandle and ChildHandle,\r
+  then EFI_UNSUPPORTED is returned.  If the driver specified by This does not\r
+  support the language specified by Language, then EFI_UNSUPPORTED is returned.\r
+\r
+  @param  This[in]              A pointer to the EFI_COMPONENT_NAME2_PROTOCOL or\r
+                                EFI_COMPONENT_NAME_PROTOCOL instance.\r
+\r
+  @param  ControllerHandle[in]  The handle of a controller that the driver\r
+                                specified by This is managing.  This handle\r
+                                specifies the controller whose name is to be\r
+                                returned.\r
+\r
+  @param  ChildHandle[in]       The handle of the child controller to retrieve\r
+                                the name of.  This is an optional parameter that\r
+                                may be NULL.  It will be NULL for device\r
+                                drivers.  It will also be NULL for a bus drivers\r
+                                that wish to retrieve the name of the bus\r
+                                controller.  It will not be NULL for a bus\r
+                                driver that wishes to retrieve the name of a\r
+                                child controller.\r
+\r
+  @param  Language[in]          A pointer to a Null-terminated ASCII string\r
+                                array indicating the language.  This is the\r
+                                language of the driver name that the caller is\r
+                                requesting, and it must match one of the\r
+                                languages specified in SupportedLanguages. The\r
+                                number of languages supported by a driver is up\r
+                                to the driver writer. Language is specified in\r
+                                RFC 4646 or ISO 639-2 language code format.\r
+\r
+  @param  ControllerName[out]   A pointer to the Unicode string to return.\r
+                                This Unicode string is the name of the\r
+                                controller specified by ControllerHandle and\r
+                                ChildHandle in the language specified by\r
+                                Language from the point of view of the driver\r
+                                specified by This.\r
+\r
+  @retval EFI_SUCCESS           The Unicode string for the user readable name in\r
+                                the language specified by Language for the\r
+                                driver specified by This was returned in\r
+                                DriverName.\r
+\r
+  @retval EFI_INVALID_PARAMETER ControllerHandle is NULL.\r
+\r
+  @retval EFI_INVALID_PARAMETER ChildHandle is not NULL and it is not a valid\r
+                                EFI_HANDLE.\r
+\r
+  @retval EFI_INVALID_PARAMETER Language is NULL.\r
+\r
+  @retval EFI_INVALID_PARAMETER ControllerName is NULL.\r
+\r
+  @retval EFI_UNSUPPORTED       The driver specified by This is not currently\r
+                                managing the controller specified by\r
+                                ControllerHandle and ChildHandle.\r
+\r
+  @retval EFI_UNSUPPORTED       The driver specified by This does not support\r
+                                the language specified by Language.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+ConSplitterStdErrComponentNameGetControllerName (\r
+  IN  EFI_COMPONENT_NAME_PROTOCOL                     *This,\r
+  IN  EFI_HANDLE                                      ControllerHandle,\r
+  IN  EFI_HANDLE                                      ChildHandle        OPTIONAL,\r
+  IN  CHAR8                                           *Language,\r
+  OUT CHAR16                                          **ControllerName\r
+  )\r
+{\r
+  EFI_STATUS                       Status;\r
+\r
+  Status = ConSplitterTestControllerHandles (\r
+             ControllerHandle,\r
+             gConSplitterStdErrDriverBinding.DriverBindingHandle,\r
+             &gEfiStandardErrorDeviceGuid,\r
+             ChildHandle,\r
+             &gEfiStandardErrorDeviceGuid\r
+             );\r
+  if (EFI_ERROR (Status)) {\r
+    return Status;\r
+  }\r
+\r
+  return LookupUnicodeString2 (\r
+           Language,\r
+           This->SupportedLanguages,\r
+           mConSplitterStdErrControllerNameTable,\r
+           ControllerName,\r
+           (BOOLEAN)(This == &gConSplitterStdErrComponentName)\r
+           );\r
+}\r

diff --git a/Vlv2TbltDevicePkg/Override/MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitter.c b/Vlv2TbltDevicePkg/Override/MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitter.c
new file mode 100644 (file)
index 0000000..79e6153
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Override/MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitter.c
@@ -0,0 +1,4776 @@
+/** @file\r
+  Console Splitter Driver. Any Handle that attatched console I/O protocols\r
+  (Console In device, Console Out device, Console Error device, Simple Pointer\r
+  protocol, Absolute Pointer protocol) can be bound by this driver.\r
+\r
+  So far it works like any other driver by opening a SimpleTextIn and/or\r
+  SimpleTextOut protocol with EFI_OPEN_PROTOCOL_BY_DRIVER attributes. The big\r
+  difference is this driver does not layer a protocol on the passed in\r
+  handle, or construct a child handle like a standard device or bus driver.\r
+  This driver produces three virtual handles as children, one for console input\r
+  splitter, one for console output splitter and one for error output splitter.\r
+  These 3 virtual handles would be installed on gST.\r
+\r
+  Each virtual handle, that supports the Console I/O protocol, will be produced\r
+  in the driver entry point. The virtual handle are added on driver entry and\r
+  never removed. Such design ensures sytem function well during none console\r
+  device situation.\r
+\r
+Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.<BR>\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution.  The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#include "ConSplitter.h"\r
+\r
+//\r
+// Identify if ConIn is connected in PcdConInConnectOnDemand enabled mode. \r
+// default not connect\r
+//\r
+BOOLEAN  mConInIsConnect = FALSE;\r
+\r
+//\r
+// Text In Splitter Private Data template\r
+//\r
+GLOBAL_REMOVE_IF_UNREFERENCED TEXT_IN_SPLITTER_PRIVATE_DATA  mConIn = {\r
+  TEXT_IN_SPLITTER_PRIVATE_DATA_SIGNATURE,\r
+  (EFI_HANDLE) NULL,\r
+\r
+  {\r
+    ConSplitterTextInReset,\r
+    ConSplitterTextInReadKeyStroke,\r
+    (EFI_EVENT) NULL\r
+  },\r
+  0,\r
+  (EFI_SIMPLE_TEXT_INPUT_PROTOCOL **) NULL,\r
+  0,\r
+\r
+  {\r
+    ConSplitterTextInResetEx,\r
+    ConSplitterTextInReadKeyStrokeEx,\r
+    (EFI_EVENT) NULL,\r
+    ConSplitterTextInSetState,\r
+    ConSplitterTextInRegisterKeyNotify,\r
+    ConSplitterTextInUnregisterKeyNotify\r
+  },\r
+  0,\r
+  (EFI_SIMPLE_TEXT_INPUT_EX_PROTOCOL **) NULL,\r
+  0,\r
+  {\r
+    (LIST_ENTRY *) NULL,\r
+    (LIST_ENTRY *) NULL\r
+  },\r
+\r
+  {\r
+    ConSplitterSimplePointerReset,\r
+    ConSplitterSimplePointerGetState,\r
+    (EFI_EVENT) NULL,\r
+    (EFI_SIMPLE_POINTER_MODE *) NULL\r
+  },\r
+  {\r
+    0x10000,\r
+    0x10000,\r
+    0x10000,\r
+    TRUE,\r
+    TRUE\r
+  },\r
+  0,\r
+  (EFI_SIMPLE_POINTER_PROTOCOL **) NULL,\r
+  0,\r
+\r
+  {\r
+    ConSplitterAbsolutePointerReset,\r
+    ConSplitterAbsolutePointerGetState,\r
+    (EFI_EVENT) NULL,\r
+    (EFI_ABSOLUTE_POINTER_MODE *) NULL\r
+  },\r
+  {\r
+    0,       // AbsoluteMinX\r
+    0,       // AbsoluteMinY\r
+    0,       // AbsoluteMinZ\r
+    0x10000, // AbsoluteMaxX\r
+    0x10000, // AbsoluteMaxY\r
+    0x10000, // AbsoluteMaxZ\r
+    0        // Attributes\r
+  },\r
+  0,\r
+  (EFI_ABSOLUTE_POINTER_PROTOCOL **) NULL,\r
+  0,\r
+  FALSE,\r
+\r
+  FALSE,\r
+  FALSE\r
+};\r
+\r
+\r
+//\r
+// Uga Draw Protocol Private Data template\r
+//\r
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_UGA_DRAW_PROTOCOL mUgaDrawProtocolTemplate = {\r
+  ConSplitterUgaDrawGetMode,\r
+  ConSplitterUgaDrawSetMode,\r
+  ConSplitterUgaDrawBlt\r
+};\r
+\r
+//\r
+// Graphics Output Protocol Private Data template\r
+//\r
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_GRAPHICS_OUTPUT_PROTOCOL mGraphicsOutputProtocolTemplate = {\r
+  ConSplitterGraphicsOutputQueryMode,\r
+  ConSplitterGraphicsOutputSetMode,\r
+  ConSplitterGraphicsOutputBlt,\r
+  NULL\r
+};\r
+\r
+\r
+//\r
+// Text Out Splitter Private Data template\r
+//\r
+GLOBAL_REMOVE_IF_UNREFERENCED TEXT_OUT_SPLITTER_PRIVATE_DATA mConOut = {\r
+  TEXT_OUT_SPLITTER_PRIVATE_DATA_SIGNATURE,\r
+  (EFI_HANDLE) NULL,\r
+  {\r
+    ConSplitterTextOutReset,\r
+    ConSplitterTextOutOutputString,\r
+    ConSplitterTextOutTestString,\r
+    ConSplitterTextOutQueryMode,\r
+    ConSplitterTextOutSetMode,\r
+    ConSplitterTextOutSetAttribute,\r
+    ConSplitterTextOutClearScreen,\r
+    ConSplitterTextOutSetCursorPosition,\r
+    ConSplitterTextOutEnableCursor,\r
+    (EFI_SIMPLE_TEXT_OUTPUT_MODE *) NULL\r
+  },\r
+  {\r
+    1,\r
+    0,\r
+    0,\r
+    0,\r
+    0,\r
+    FALSE,\r
+  },\r
+\r
+  {\r
+    NULL,\r
+    NULL,\r
+    NULL\r
+  },\r
+  0,\r
+  0,\r
+  0,\r
+  0,\r
+\r
+  {\r
+    NULL,\r
+    NULL,\r
+    NULL,\r
+    NULL\r
+  },\r
+  (EFI_GRAPHICS_OUTPUT_MODE_INFORMATION *) NULL,\r
+  0,\r
+  0,\r
+\r
+  0,\r
+  (TEXT_OUT_AND_GOP_DATA *) NULL,\r
+  0,\r
+  (TEXT_OUT_SPLITTER_QUERY_DATA *) NULL,\r
+  0,\r
+  (INT32 *) NULL\r
+};\r
+\r
+//\r
+// Standard Error Text Out Splitter Data Template\r
+//\r
+GLOBAL_REMOVE_IF_UNREFERENCED TEXT_OUT_SPLITTER_PRIVATE_DATA mStdErr = {\r
+  TEXT_OUT_SPLITTER_PRIVATE_DATA_SIGNATURE,\r
+  (EFI_HANDLE) NULL,\r
+  {\r
+    ConSplitterTextOutReset,\r
+    ConSplitterTextOutOutputString,\r
+    ConSplitterTextOutTestString,\r
+    ConSplitterTextOutQueryMode,\r
+    ConSplitterTextOutSetMode,\r
+    ConSplitterTextOutSetAttribute,\r
+    ConSplitterTextOutClearScreen,\r
+    ConSplitterTextOutSetCursorPosition,\r
+    ConSplitterTextOutEnableCursor,\r
+    (EFI_SIMPLE_TEXT_OUTPUT_MODE *) NULL\r
+  },\r
+  {\r
+    1,\r
+    0,\r
+    0,\r
+    0,\r
+    0,\r
+    FALSE,\r
+  },\r
+\r
+  {\r
+    NULL,\r
+    NULL,\r
+    NULL\r
+  },\r
+  0,\r
+  0,\r
+  0,\r
+  0,\r
+\r
+  {\r
+    NULL,\r
+    NULL,\r
+    NULL,\r
+    NULL\r
+  },\r
+  (EFI_GRAPHICS_OUTPUT_MODE_INFORMATION *) NULL,\r
+  0,\r
+  0,\r
+\r
+  0,\r
+  (TEXT_OUT_AND_GOP_DATA *) NULL,\r
+  0,\r
+  (TEXT_OUT_SPLITTER_QUERY_DATA *) NULL,\r
+  0,\r
+  (INT32 *) NULL\r
+};\r
+\r
+//\r
+// Driver binding instance for Console Input Device\r
+//\r
+EFI_DRIVER_BINDING_PROTOCOL           gConSplitterConInDriverBinding = {\r
+  ConSplitterConInDriverBindingSupported,\r
+  ConSplitterConInDriverBindingStart,\r
+  ConSplitterConInDriverBindingStop,\r
+  0xa,\r
+  NULL,\r
+  NULL\r
+};\r
+\r
+//\r
+// Driver binding instance for Console Out device\r
+//\r
+EFI_DRIVER_BINDING_PROTOCOL           gConSplitterConOutDriverBinding = {\r
+  ConSplitterConOutDriverBindingSupported,\r
+  ConSplitterConOutDriverBindingStart,\r
+  ConSplitterConOutDriverBindingStop,\r
+  0xa,\r
+  NULL,\r
+  NULL\r
+};\r
+\r
+//\r
+// Driver binding instance for Standard Error device\r
+//\r
+EFI_DRIVER_BINDING_PROTOCOL           gConSplitterStdErrDriverBinding = {\r
+  ConSplitterStdErrDriverBindingSupported,\r
+  ConSplitterStdErrDriverBindingStart,\r
+  ConSplitterStdErrDriverBindingStop,\r
+  0xa,\r
+  NULL,\r
+  NULL\r
+};\r
+\r
+//\r
+// Driver binding instance for Simple Pointer protocol\r
+//\r
+EFI_DRIVER_BINDING_PROTOCOL           gConSplitterSimplePointerDriverBinding = {\r
+  ConSplitterSimplePointerDriverBindingSupported,\r
+  ConSplitterSimplePointerDriverBindingStart,\r
+  ConSplitterSimplePointerDriverBindingStop,\r
+  0xa,\r
+  NULL,\r
+  NULL\r
+};\r
+\r
+//\r
+// Driver binding instance for Absolute Pointer protocol\r
+//\r
+EFI_DRIVER_BINDING_PROTOCOL           gConSplitterAbsolutePointerDriverBinding = {\r
+  ConSplitterAbsolutePointerDriverBindingSupported,\r
+  ConSplitterAbsolutePointerDriverBindingStart,\r
+  ConSplitterAbsolutePointerDriverBindingStop,\r
+  0xa,\r
+  NULL,\r
+  NULL\r
+};\r
+\r
+/**\r
+  The Entry Point for module ConSplitter. The user code starts with this function.\r
+\r
+  Installs driver module protocols and. Creates virtual device handles for ConIn,\r
+  ConOut, and StdErr. Installs Simple Text In protocol, Simple Text In Ex protocol,\r
+  Simple Pointer protocol, Absolute Pointer protocol on those virtual handlers.\r
+  Installs Graphics Output protocol and/or UGA Draw protocol if needed.\r
+\r
+  @param[in] ImageHandle    The firmware allocated handle for the EFI image.\r
+  @param[in] SystemTable    A pointer to the EFI System Table.\r
+\r
+  @retval EFI_SUCCESS       The entry point is executed successfully.\r
+  @retval other             Some error occurs when executing this entry point.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+ConSplitterDriverEntry(\r
+  IN EFI_HANDLE           ImageHandle,\r
+  IN EFI_SYSTEM_TABLE     *SystemTable\r
+  )\r
+{\r
+  EFI_STATUS              Status;\r
+\r
+  //\r
+  // Install driver model protocol(s).\r
+  //\r
+  Status = EfiLibInstallDriverBindingComponentName2 (\r
+             ImageHandle,\r
+             SystemTable,\r
+             &gConSplitterConInDriverBinding,\r
+             ImageHandle,\r
+             &gConSplitterConInComponentName,\r
+             &gConSplitterConInComponentName2\r
+             );\r
+  ASSERT_EFI_ERROR (Status);\r
+\r
+  Status = EfiLibInstallDriverBindingComponentName2 (\r
+             ImageHandle,\r
+             SystemTable,\r
+             &gConSplitterSimplePointerDriverBinding,\r
+             NULL,\r
+             &gConSplitterSimplePointerComponentName,\r
+             &gConSplitterSimplePointerComponentName2\r
+             );\r
+  ASSERT_EFI_ERROR (Status);\r
+\r
+  Status = EfiLibInstallDriverBindingComponentName2 (\r
+             ImageHandle,\r
+             SystemTable,\r
+             &gConSplitterAbsolutePointerDriverBinding,\r
+             NULL,\r
+             &gConSplitterAbsolutePointerComponentName,\r
+             &gConSplitterAbsolutePointerComponentName2\r
+             );\r
+  ASSERT_EFI_ERROR (Status);\r
+\r
+  Status = EfiLibInstallDriverBindingComponentName2 (\r
+             ImageHandle,\r
+             SystemTable,\r
+             &gConSplitterConOutDriverBinding,\r
+             NULL,\r
+             &gConSplitterConOutComponentName,\r
+             &gConSplitterConOutComponentName2\r
+             );\r
+  ASSERT_EFI_ERROR (Status);\r
+\r
+  Status = EfiLibInstallDriverBindingComponentName2 (\r
+             ImageHandle,\r
+             SystemTable,\r
+             &gConSplitterStdErrDriverBinding,\r
+             NULL,\r
+             &gConSplitterStdErrComponentName,\r
+             &gConSplitterStdErrComponentName2\r
+             );\r
+  ASSERT_EFI_ERROR (Status);\r
+\r
+  //\r
+  // Either Graphics Output protocol or UGA Draw protocol must be supported.\r
+  //\r
+  ASSERT (FeaturePcdGet (PcdConOutGopSupport) ||\r
+          FeaturePcdGet (PcdConOutUgaSupport));\r
+\r
+  //\r
+  // The driver creates virtual handles for ConIn, ConOut, StdErr.\r
+  // The virtual handles will always exist even if no console exist in the\r
+  // system. This is need to support hotplug devices like USB.\r
+  //\r
+  //\r
+  // Create virtual device handle for ConIn Splitter\r
+  //\r
+  Status = ConSplitterTextInConstructor (&mConIn);\r
+  if (!EFI_ERROR (Status)) {\r
+    Status = gBS->InstallMultipleProtocolInterfaces (\r
+                    &mConIn.VirtualHandle,\r
+                    &gEfiSimpleTextInProtocolGuid,\r
+                    &mConIn.TextIn,\r
+                    &gEfiSimpleTextInputExProtocolGuid,\r
+                    &mConIn.TextInEx,\r
+                    &gEfiSimplePointerProtocolGuid,\r
+                    &mConIn.SimplePointer,\r
+                    &gEfiAbsolutePointerProtocolGuid,\r
+                    &mConIn.AbsolutePointer,\r
+                    NULL\r
+                    );\r
+    if (!EFI_ERROR (Status)) {\r
+      //\r
+      // Update the EFI System Table with new virtual console\r
+      // and update the pointer to Simple Text Input protocol.\r
+      //\r
+      gST->ConsoleInHandle  = mConIn.VirtualHandle;\r
+      gST->ConIn            = &mConIn.TextIn;\r
+    }\r
+  }\r
+  //\r
+  // Create virtual device handle for ConOut Splitter\r
+  //\r
+  Status = ConSplitterTextOutConstructor (&mConOut);\r
+  if (!EFI_ERROR (Status)) {\r
+    Status = gBS->InstallMultipleProtocolInterfaces (\r
+                    &mConOut.VirtualHandle,\r
+                    &gEfiSimpleTextOutProtocolGuid,\r
+                    &mConOut.TextOut,\r
+                    NULL\r
+                    );\r
+    if (!EFI_ERROR (Status)) {\r
+      //\r
+      // Update the EFI System Table with new virtual console\r
+      // and Update the pointer to Text Output protocol.\r
+      //\r
+      gST->ConsoleOutHandle = mConOut.VirtualHandle;\r
+      gST->ConOut           = &mConOut.TextOut;\r
+    }\r
+\r
+  }\r
+\r
+  //\r
+  // Create virtual device handle for StdErr Splitter\r
+  //\r
+  Status = ConSplitterTextOutConstructor (&mStdErr);\r
+  if (!EFI_ERROR (Status)) {\r
+    Status = gBS->InstallMultipleProtocolInterfaces (\r
+                    &mStdErr.VirtualHandle,\r
+                    &gEfiSimpleTextOutProtocolGuid,\r
+                    &mStdErr.TextOut,\r
+                    NULL\r
+                    );\r
+    if (!EFI_ERROR (Status)) {  \r
+      //\r
+      // Update the EFI System Table with new virtual console\r
+      // and update the pointer to Text Output protocol.\r
+      //\r
+      gST->StandardErrorHandle  = mStdErr.VirtualHandle;\r
+      gST->StdErr               = &mStdErr.TextOut;\r
+    }\r
+  }\r
+  \r
+  //\r
+  // Update the CRC32 in the EFI System Table header\r
+  //\r
+  gST->Hdr.CRC32 = 0;\r
+  gBS->CalculateCrc32 (\r
+        (UINT8 *) &gST->Hdr,\r
+        gST->Hdr.HeaderSize,\r
+        &gST->Hdr.CRC32\r
+        );\r
+\r
+  return EFI_SUCCESS;\r
+\r
+}\r
+\r
+/**\r
+  Construct console input devices' private data.\r
+\r
+  @param  ConInPrivate             A pointer to the TEXT_IN_SPLITTER_PRIVATE_DATA\r
+                                   structure.\r
+\r
+  @retval EFI_OUT_OF_RESOURCES     Out of resources.\r
+  @retval EFI_SUCCESS              Text Input Devcie's private data has been constructed.\r
+  @retval other                    Failed to construct private data.\r
+\r
+**/\r
+EFI_STATUS\r
+ConSplitterTextInConstructor (\r
+  TEXT_IN_SPLITTER_PRIVATE_DATA       *ConInPrivate\r
+  )\r
+{\r
+  EFI_STATUS  Status;\r
+\r
+  //\r
+  // Allocate buffer for Simple Text Input device\r
+  //\r
+  Status = ConSplitterGrowBuffer (\r
+            sizeof (EFI_SIMPLE_TEXT_INPUT_PROTOCOL *),\r
+            &ConInPrivate->TextInListCount,\r
+            (VOID **) &ConInPrivate->TextInList\r
+            );\r
+  if (EFI_ERROR (Status)) {\r
+    return EFI_OUT_OF_RESOURCES;\r
+  }\r
+\r
+  //\r
+  // Create Event to wait for a key\r
+  //\r
+  Status = gBS->CreateEvent (\r
+                  EVT_NOTIFY_WAIT,\r
+                  TPL_NOTIFY,\r
+                  ConSplitterTextInWaitForKey,\r
+                  ConInPrivate,\r
+                  &ConInPrivate->TextIn.WaitForKey\r
+                  );\r
+  ASSERT_EFI_ERROR (Status);\r
+\r
+  //\r
+  // Allocate buffer for Simple Text Input Ex device\r
+  //\r
+  Status = ConSplitterGrowBuffer (\r
+             sizeof (EFI_SIMPLE_TEXT_INPUT_EX_PROTOCOL *),\r
+             &ConInPrivate->TextInExListCount,\r
+             (VOID **) &ConInPrivate->TextInExList\r
+             );\r
+  if (EFI_ERROR (Status)) {\r
+    return EFI_OUT_OF_RESOURCES;\r
+  }\r
+  //\r
+  // Create Event to wait for a key Ex\r
+  //\r
+  Status = gBS->CreateEvent (\r
+                  EVT_NOTIFY_WAIT,\r
+                  TPL_NOTIFY,\r
+                  ConSplitterTextInWaitForKey,\r
+                  ConInPrivate,\r
+                  &ConInPrivate->TextInEx.WaitForKeyEx\r
+                  );\r
+  ASSERT_EFI_ERROR (Status);\r
+\r
+  InitializeListHead (&ConInPrivate->NotifyList);\r
+\r
+  ConInPrivate->AbsolutePointer.Mode = &ConInPrivate->AbsolutePointerMode;\r
+  //\r
+  // Allocate buffer for Absolute Pointer device\r
+  //\r
+  Status = ConSplitterGrowBuffer (\r
+            sizeof (EFI_ABSOLUTE_POINTER_PROTOCOL *),\r
+            &ConInPrivate->AbsolutePointerListCount,\r
+            (VOID **) &ConInPrivate->AbsolutePointerList\r
+            );\r
+  if (EFI_ERROR (Status)) {\r
+    return EFI_OUT_OF_RESOURCES;\r
+  }\r
+  //\r
+  // Create Event to wait for device input for Absolute pointer device\r
+  //\r
+  Status = gBS->CreateEvent (\r
+            EVT_NOTIFY_WAIT,\r
+            TPL_NOTIFY,\r
+            ConSplitterAbsolutePointerWaitForInput,\r
+            ConInPrivate,\r
+            &ConInPrivate->AbsolutePointer.WaitForInput\r
+        );\r
+  ASSERT_EFI_ERROR (Status);\r
+\r
+  ConInPrivate->SimplePointer.Mode = &ConInPrivate->SimplePointerMode;\r
+  //\r
+  // Allocate buffer for Simple Pointer device\r
+  //\r
+  Status = ConSplitterGrowBuffer (\r
+            sizeof (EFI_SIMPLE_POINTER_PROTOCOL *),\r
+            &ConInPrivate->PointerListCount,\r
+            (VOID **) &ConInPrivate->PointerList\r
+            );\r
+  if (EFI_ERROR (Status)) {\r
+    return EFI_OUT_OF_RESOURCES;\r
+  }\r
+  //\r
+  // Create Event to wait for device input for Simple pointer device\r
+  //\r
+  Status = gBS->CreateEvent (\r
+                  EVT_NOTIFY_WAIT,\r
+                  TPL_NOTIFY,\r
+                  ConSplitterSimplePointerWaitForInput,\r
+                  ConInPrivate,\r
+                  &ConInPrivate->SimplePointer.WaitForInput\r
+                  );\r
+  ASSERT_EFI_ERROR (Status);\r
+  //\r
+  // Create Event to signal ConIn connection request\r
+  //\r
+  Status = gBS->CreateEventEx (\r
+                  EVT_NOTIFY_SIGNAL,\r
+                  TPL_CALLBACK,\r
+                  ConSplitterEmptyCallbackFunction,\r
+                  NULL,\r
+                  &gConnectConInEventGuid,\r
+                  &ConInPrivate->ConnectConInEvent\r
+                  );\r
+\r
+  return Status;\r
+}\r
+\r
+/**\r
+  Construct console output devices' private data.\r
+\r
+  @param  ConOutPrivate            A pointer to the TEXT_OUT_SPLITTER_PRIVATE_DATA\r
+                                   structure.\r
+\r
+  @retval EFI_OUT_OF_RESOURCES     Out of resources.\r
+  @retval EFI_SUCCESS              Text Input Devcie's private data has been constructed.\r
+\r
+**/\r
+EFI_STATUS\r
+ConSplitterTextOutConstructor (\r
+  TEXT_OUT_SPLITTER_PRIVATE_DATA      *ConOutPrivate\r
+  )\r
+{\r
+  EFI_STATUS  Status;\r
+  EFI_GRAPHICS_OUTPUT_MODE_INFORMATION  *Info;\r
+\r
+  //\r
+  // Copy protocols template\r
+  //\r
+  if (FeaturePcdGet (PcdConOutUgaSupport)) {\r
+    CopyMem (&ConOutPrivate->UgaDraw, &mUgaDrawProtocolTemplate, sizeof (EFI_UGA_DRAW_PROTOCOL));\r
+  }\r
+  if (FeaturePcdGet (PcdConOutGopSupport)) {\r
+    CopyMem (&ConOutPrivate->GraphicsOutput, &mGraphicsOutputProtocolTemplate, sizeof (EFI_GRAPHICS_OUTPUT_PROTOCOL));\r
+  }\r
+\r
+  //\r
+  // Initilize console output splitter's private data.\r
+  //\r
+  ConOutPrivate->TextOut.Mode = &ConOutPrivate->TextOutMode;\r
+\r
+  //\r
+  // When new console device is added, the new mode will be set later,\r
+  // so put current mode back to init state.\r
+  //\r
+  ConOutPrivate->TextOutMode.Mode = 0xFF;\r
+  //\r
+  // Allocate buffer for Console Out device\r
+  //\r
+  Status = ConSplitterGrowBuffer (\r
+            sizeof (TEXT_OUT_AND_GOP_DATA),\r
+            &ConOutPrivate->TextOutListCount,\r
+            (VOID **) &ConOutPrivate->TextOutList\r
+            );\r
+  if (EFI_ERROR (Status)) {\r
+    return EFI_OUT_OF_RESOURCES;\r
+  }\r
+  //\r
+  // Allocate buffer for Text Out query data\r
+  //\r
+  Status = ConSplitterGrowBuffer (\r
+            sizeof (TEXT_OUT_SPLITTER_QUERY_DATA),\r
+            &ConOutPrivate->TextOutQueryDataCount,\r
+            (VOID **) &ConOutPrivate->TextOutQueryData\r
+            );\r
+  if (EFI_ERROR (Status)) {\r
+    return EFI_OUT_OF_RESOURCES;\r
+  }\r
+\r
+  //\r
+  // Setup the default console to 80 x 25 and mode to 0\r
+  //\r
+  ConOutPrivate->TextOutQueryData[0].Columns  = 80;\r
+  ConOutPrivate->TextOutQueryData[0].Rows     = 25;\r
+  TextOutSetMode (ConOutPrivate, 0);\r
+\r
+\r
+  if (FeaturePcdGet (PcdConOutUgaSupport)) {\r
+    //\r
+    // Setup the UgaDraw to 800 x 600 x 32 bits per pixel, 60Hz.\r
+    //\r
+    ConSplitterUgaDrawSetMode (&ConOutPrivate->UgaDraw, 800, 600, 32, 60);\r
+  }\r
+  if (FeaturePcdGet (PcdConOutGopSupport)) {\r
+    //\r
+    // Setup resource for mode information in Graphics Output Protocol interface\r
+    //\r
+    if ((ConOutPrivate->GraphicsOutput.Mode = AllocateZeroPool (sizeof (EFI_GRAPHICS_OUTPUT_PROTOCOL_MODE))) == NULL) {\r
+      return EFI_OUT_OF_RESOURCES;\r
+    }\r
+    if ((ConOutPrivate->GraphicsOutput.Mode->Info = AllocateZeroPool (sizeof (EFI_GRAPHICS_OUTPUT_MODE_INFORMATION))) == NULL) {\r
+      return EFI_OUT_OF_RESOURCES;\r
+    }\r
+    //\r
+    // Setup the DevNullGraphicsOutput to 800 x 600 x 32 bits per pixel\r
+    // DevNull will be updated to user-defined mode after driver has started.\r
+    //\r
+    if ((ConOutPrivate->GraphicsOutputModeBuffer = AllocateZeroPool (sizeof (EFI_GRAPHICS_OUTPUT_MODE_INFORMATION))) == NULL) {\r
+      return EFI_OUT_OF_RESOURCES;\r
+    }\r
+    Info = &ConOutPrivate->GraphicsOutputModeBuffer[0];\r
+    Info->Version = 0;\r
+    Info->HorizontalResolution = 800;\r
+    Info->VerticalResolution = 600;\r
+    Info->PixelFormat = PixelBltOnly;\r
+    Info->PixelsPerScanLine = 800;\r
+    CopyMem (ConOutPrivate->GraphicsOutput.Mode->Info, Info, sizeof (EFI_GRAPHICS_OUTPUT_MODE_INFORMATION));\r
+    ConOutPrivate->GraphicsOutput.Mode->SizeOfInfo = sizeof (EFI_GRAPHICS_OUTPUT_MODE_INFORMATION);\r
+\r
+    //\r
+    // Initialize the following items, theset items remain unchanged in GraphicsOutput->SetMode()\r
+    // GraphicsOutputMode->FrameBufferBase, GraphicsOutputMode->FrameBufferSize\r
+    //\r
+    ConOutPrivate->GraphicsOutput.Mode->FrameBufferBase = (EFI_PHYSICAL_ADDRESS) (UINTN) NULL;\r
+    ConOutPrivate->GraphicsOutput.Mode->FrameBufferSize = 0;\r
+\r
+    ConOutPrivate->GraphicsOutput.Mode->MaxMode = 1;\r
+    //\r
+    // Initial current mode to unknown state, and then set to mode 0\r
+    //\r
+    ConOutPrivate->GraphicsOutput.Mode->Mode = 0xffff;\r
+    ConOutPrivate->GraphicsOutput.SetMode (&ConOutPrivate->GraphicsOutput, 0);\r
+  }\r
+\r
+  return EFI_SUCCESS;\r
+}\r
+\r
+\r
+/**\r
+  Test to see if the specified protocol could be supported on the specified device.\r
+\r
+  @param  This                Driver Binding protocol pointer.\r
+  @param  ControllerHandle    Handle of device to test.\r
+  @param  Guid                The specified protocol.\r
+\r
+  @retval EFI_SUCCESS         The specified protocol is supported on this device.\r
+  @retval EFI_UNSUPPORTED     The specified protocol attempts to be installed on virtul handle.\r
+  @retval other               Failed to open specified protocol on this device.\r
+\r
+**/\r
+EFI_STATUS\r
+ConSplitterSupported (\r
+  IN  EFI_DRIVER_BINDING_PROTOCOL     *This,\r
+  IN  EFI_HANDLE                      ControllerHandle,\r
+  IN  EFI_GUID                        *Guid\r
+  )\r
+{\r
+  EFI_STATUS  Status;\r
+  VOID        *Instance;\r
+\r
+  //\r
+  // Make sure the Console Splitter does not attempt to attach to itself\r
+  //\r
+  if (ControllerHandle == mConIn.VirtualHandle  ||\r
+      ControllerHandle == mConOut.VirtualHandle ||\r
+      ControllerHandle == mStdErr.VirtualHandle\r
+      ) {\r
+    return EFI_UNSUPPORTED;\r
+  }\r
+\r
+  //\r
+  // Check to see whether the specific protocol could be opened BY_DRIVER\r
+  //\r
+  Status = gBS->OpenProtocol (\r
+                  ControllerHandle,\r
+                  Guid,\r
+                  &Instance,\r
+                  This->DriverBindingHandle,\r
+                  ControllerHandle,\r
+                  EFI_OPEN_PROTOCOL_BY_DRIVER\r
+                  );\r
+\r
+  if (EFI_ERROR (Status)) {\r
+    return Status;\r
+  }\r
+\r
+  gBS->CloseProtocol (\r
+        ControllerHandle,\r
+        Guid,\r
+        This->DriverBindingHandle,\r
+        ControllerHandle\r
+        );\r
+\r
+  return EFI_SUCCESS;\r
+}\r
+\r
+/**\r
+  Test to see if Console In Device could be supported on the Controller.\r
+\r
+  @param  This                Driver Binding protocol instance pointer.\r
+  @param  ControllerHandle    Handle of device to test.\r
+  @param  RemainingDevicePath Optional parameter use to pick a specific child\r
+                              device to start.\r
+\r
+  @retval EFI_SUCCESS         This driver supports this device.\r
+  @retval other               This driver does not support this device.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+ConSplitterConInDriverBindingSupported (\r
+  IN  EFI_DRIVER_BINDING_PROTOCOL     *This,\r
+  IN  EFI_HANDLE                      ControllerHandle,\r
+  IN  EFI_DEVICE_PATH_PROTOCOL        *RemainingDevicePath\r
+  )\r
+{\r
+  return ConSplitterSupported (\r
+          This,\r
+          ControllerHandle,\r
+          &gEfiConsoleInDeviceGuid\r
+          );\r
+}\r
+\r
+/**\r
+  Test to see if Simple Pointer protocol could be supported on the Controller.\r
+\r
+  @param  This                Driver Binding protocol instance pointer.\r
+  @param  ControllerHandle    Handle of device to test.\r
+  @param  RemainingDevicePath Optional parameter use to pick a specific child\r
+                              device to start.\r
+\r
+  @retval EFI_SUCCESS         This driver supports this device.\r
+  @retval other               This driver does not support this device.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+ConSplitterSimplePointerDriverBindingSupported (\r
+  IN  EFI_DRIVER_BINDING_PROTOCOL     *This,\r
+  IN  EFI_HANDLE                      ControllerHandle,\r
+  IN  EFI_DEVICE_PATH_PROTOCOL        *RemainingDevicePath\r
+  )\r
+{\r
+  return ConSplitterSupported (\r
+          This,\r
+          ControllerHandle,\r
+          &gEfiSimplePointerProtocolGuid\r
+          );\r
+}\r
+\r
+/**\r
+  Test to see if Absolute Pointer protocol could be supported on the Controller.\r
+\r
+  @param  This                Driver Binding protocol instance pointer.\r
+  @param  ControllerHandle    Handle of device to test.\r
+  @param  RemainingDevicePath Optional parameter use to pick a specific child\r
+                              device to start.\r
+\r
+  @retval EFI_SUCCESS         This driver supports this device.\r
+  @retval other               This driver does not support this device.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+ConSplitterAbsolutePointerDriverBindingSupported (\r
+  IN  EFI_DRIVER_BINDING_PROTOCOL     *This,\r
+  IN  EFI_HANDLE                      ControllerHandle,\r
+  IN  EFI_DEVICE_PATH_PROTOCOL        *RemainingDevicePath\r
+  )\r
+{\r
+  return ConSplitterSupported (\r
+          This,\r
+          ControllerHandle,\r
+          &gEfiAbsolutePointerProtocolGuid\r
+          );\r
+}\r
+\r
+\r
+/**\r
+  Test to see if Console Out Device could be supported on the Controller.\r
+\r
+  @param  This                Driver Binding protocol instance pointer.\r
+  @param  ControllerHandle    Handle of device to test.\r
+  @param  RemainingDevicePath Optional parameter use to pick a specific child\r
+                              device to start.\r
+\r
+  @retval EFI_SUCCESS         This driver supports this device.\r
+  @retval other               This driver does not support this device.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+ConSplitterConOutDriverBindingSupported (\r
+  IN  EFI_DRIVER_BINDING_PROTOCOL     *This,\r
+  IN  EFI_HANDLE                      ControllerHandle,\r
+  IN  EFI_DEVICE_PATH_PROTOCOL        *RemainingDevicePath\r
+  )\r
+{\r
+  return ConSplitterSupported (\r
+          This,\r
+          ControllerHandle,\r
+          &gEfiConsoleOutDeviceGuid\r
+          );\r
+}\r
+\r
+/**\r
+  Test to see if Standard Error Device could be supported on the Controller.\r
+\r
+  @param  This                Driver Binding protocol instance pointer.\r
+  @param  ControllerHandle    Handle of device to test.\r
+  @param  RemainingDevicePath Optional parameter use to pick a specific child\r
+                              device to start.\r
+\r
+  @retval EFI_SUCCESS         This driver supports this device.\r
+  @retval other               This driver does not support this device.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+ConSplitterStdErrDriverBindingSupported (\r
+  IN  EFI_DRIVER_BINDING_PROTOCOL     *This,\r
+  IN  EFI_HANDLE                      ControllerHandle,\r
+  IN  EFI_DEVICE_PATH_PROTOCOL        *RemainingDevicePath\r
+  )\r
+{\r
+  return ConSplitterSupported (\r
+          This,\r
+          ControllerHandle,\r
+          &gEfiStandardErrorDeviceGuid\r
+          );\r
+}\r
+\r
+\r
+/**\r
+  Start ConSplitter on devcie handle by opening Console Device Guid on device handle\r
+  and the console virtual handle. And Get the console interface on controller handle.\r
+\r
+  @param  This                      Driver Binding protocol instance pointer.\r
+  @param  ControllerHandle          Handle of device.\r
+  @param  ConSplitterVirtualHandle  Console virtual Handle.\r
+  @param  DeviceGuid                The specified Console Device, such as ConInDev,\r
+                                    ConOutDev.\r
+  @param  InterfaceGuid             The specified protocol to be opened.\r
+  @param  Interface                 Protocol interface returned.\r
+\r
+  @retval EFI_SUCCESS               This driver supports this device.\r
+  @retval other                     Failed to open the specified Console Device Guid\r
+                                    or specified protocol.\r
+\r
+**/\r
+EFI_STATUS\r
+ConSplitterStart (\r
+  IN  EFI_DRIVER_BINDING_PROTOCOL     *This,\r
+  IN  EFI_HANDLE                      ControllerHandle,\r
+  IN  EFI_HANDLE                      ConSplitterVirtualHandle,\r
+  IN  EFI_GUID                        *DeviceGuid,\r
+  IN  EFI_GUID                        *InterfaceGuid,\r
+  OUT VOID                            **Interface\r
+  )\r
+{\r
+  EFI_STATUS  Status;\r
+  VOID        *Instance;\r
+\r
+  //\r
+  // Check to see whether the ControllerHandle has the DeviceGuid on it.\r
+  //\r
+  Status = gBS->OpenProtocol (\r
+                  ControllerHandle,\r
+                  DeviceGuid,\r
+                  &Instance,\r
+                  This->DriverBindingHandle,\r
+                  ControllerHandle,\r
+                  EFI_OPEN_PROTOCOL_BY_DRIVER\r
+                  );\r
+  if (EFI_ERROR (Status)) {\r
+    return Status;\r
+  }\r
+\r
+  //\r
+  // Open the Parent Handle for the child.\r
+  //\r
+  Status = gBS->OpenProtocol (\r
+                  ControllerHandle,\r
+                  DeviceGuid,\r
+                  &Instance,\r
+                  This->DriverBindingHandle,\r
+                  ConSplitterVirtualHandle,\r
+                  EFI_OPEN_PROTOCOL_BY_CHILD_CONTROLLER\r
+                  );\r
+  if (EFI_ERROR (Status)) {\r
+    goto Err;\r
+  }\r
+\r
+  //\r
+  // Open InterfaceGuid on the virtul handle.\r
+  //\r
+  Status =  gBS->OpenProtocol (\r
+                ControllerHandle,\r
+                InterfaceGuid,\r
+                Interface,\r
+                This->DriverBindingHandle,\r
+                ConSplitterVirtualHandle,\r
+                EFI_OPEN_PROTOCOL_GET_PROTOCOL\r
+                );\r
+\r
+  if (!EFI_ERROR (Status)) {\r
+    return EFI_SUCCESS;\r
+  }\r
+\r
+  //\r
+  // close the DeviceGuid on ConSplitter VirtualHandle.\r
+  //\r
+  gBS->CloseProtocol (\r
+        ControllerHandle,\r
+        DeviceGuid,\r
+        This->DriverBindingHandle,\r
+        ConSplitterVirtualHandle\r
+        );\r
+\r
+Err:\r
+  //\r
+  // close the DeviceGuid on ControllerHandle.\r
+  //\r
+  gBS->CloseProtocol (\r
+        ControllerHandle,\r
+        DeviceGuid,\r
+        This->DriverBindingHandle,\r
+        ControllerHandle\r
+        );\r
+\r
+  return Status;\r
+}\r
+\r
+\r
+/**\r
+  Start Console In Consplitter on device handle.\r
+\r
+  @param  This                 Driver Binding protocol instance pointer.\r
+  @param  ControllerHandle     Handle of device to bind driver to.\r
+  @param  RemainingDevicePath  Optional parameter use to pick a specific child\r
+                               device to start.\r
+\r
+  @retval EFI_SUCCESS          Console In Consplitter is added to ControllerHandle.\r
+  @retval other                Console In Consplitter does not support this device.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+ConSplitterConInDriverBindingStart (\r
+  IN  EFI_DRIVER_BINDING_PROTOCOL     *This,\r
+  IN  EFI_HANDLE                      ControllerHandle,\r
+  IN  EFI_DEVICE_PATH_PROTOCOL        *RemainingDevicePath\r
+  )\r
+{\r
+  EFI_STATUS                          Status;\r
+  EFI_SIMPLE_TEXT_INPUT_PROTOCOL      *TextIn;\r
+  EFI_SIMPLE_TEXT_INPUT_EX_PROTOCOL   *TextInEx;\r
+\r
+  //\r
+  // Start ConSplitter on ControllerHandle, and create the virtual\r
+  // agrogated console device on first call Start for a SimpleTextIn handle.\r
+  //\r
+  Status = ConSplitterStart (\r
+            This,\r
+            ControllerHandle,\r
+            mConIn.VirtualHandle,\r
+            &gEfiConsoleInDeviceGuid,\r
+            &gEfiSimpleTextInProtocolGuid,\r
+            (VOID **) &TextIn\r
+            );\r
+  if (EFI_ERROR (Status)) {\r
+    return Status;\r
+  }\r
+\r
+  //\r
+  // Add this device into Text In devices list.\r
+  //\r
+  Status = ConSplitterTextInAddDevice (&mConIn, TextIn);\r
+  if (EFI_ERROR (Status)) {\r
+    return Status;\r
+  }\r
+\r
+  Status = gBS->OpenProtocol (\r
+                  ControllerHandle,\r
+                  &gEfiSimpleTextInputExProtocolGuid,\r
+                  (VOID **) &TextInEx,\r
+                  This->DriverBindingHandle,\r
+                  mConIn.VirtualHandle,\r
+                  EFI_OPEN_PROTOCOL_GET_PROTOCOL\r
+                  );\r
+  if (!EFI_ERROR (Status)) {\r
+    //\r
+    // If Simple Text Input Ex protocol exists,\r
+    // add this device into Text In Ex devices list.\r
+    //\r
+    Status = ConSplitterTextInExAddDevice (&mConIn, TextInEx);\r
+  }\r
+\r
+  return Status;\r
+}\r
+\r
+\r
+/**\r
+  Start Simple Pointer Consplitter on device handle.\r
+\r
+  @param  This                 Driver Binding protocol instance pointer.\r
+  @param  ControllerHandle     Handle of device to bind driver to.\r
+  @param  RemainingDevicePath  Optional parameter use to pick a specific child\r
+                               device to start.\r
+\r
+  @retval EFI_SUCCESS          Simple Pointer Consplitter is added to ControllerHandle.\r
+  @retval other                Simple Pointer Consplitter does not support this device.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+ConSplitterSimplePointerDriverBindingStart (\r
+  IN  EFI_DRIVER_BINDING_PROTOCOL     *This,\r
+  IN  EFI_HANDLE                      ControllerHandle,\r
+  IN  EFI_DEVICE_PATH_PROTOCOL        *RemainingDevicePath\r
+  )\r
+{\r
+  EFI_STATUS                  Status;\r
+  EFI_SIMPLE_POINTER_PROTOCOL *SimplePointer;\r
+\r
+  //\r
+  // Start ConSplitter on ControllerHandle, and create the virtual\r
+  // agrogated console device on first call Start for a SimplePointer handle.\r
+  //\r
+  Status = ConSplitterStart (\r
+            This,\r
+            ControllerHandle,\r
+            mConIn.VirtualHandle,\r
+            &gEfiSimplePointerProtocolGuid,\r
+            &gEfiSimplePointerProtocolGuid,\r
+            (VOID **) &SimplePointer\r
+            );\r
+  if (EFI_ERROR (Status)) {\r
+    return Status;\r
+  }\r
+\r
+  //\r
+  // Add this devcie into Simple Pointer devices list.\r
+  //\r
+  return ConSplitterSimplePointerAddDevice (&mConIn, SimplePointer);\r
+}\r
+\r
+\r
+/**\r
+  Start Absolute Pointer Consplitter on device handle.\r
+\r
+  @param  This                 Driver Binding protocol instance pointer.\r
+  @param  ControllerHandle     Handle of device to bind driver to.\r
+  @param  RemainingDevicePath  Optional parameter use to pick a specific child\r
+                               device to start.\r
+\r
+  @retval EFI_SUCCESS          Absolute Pointer Consplitter is added to ControllerHandle.\r
+  @retval other                Absolute Pointer Consplitter does not support this device.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+ConSplitterAbsolutePointerDriverBindingStart (\r
+  IN  EFI_DRIVER_BINDING_PROTOCOL     *This,\r
+  IN  EFI_HANDLE                      ControllerHandle,\r
+  IN  EFI_DEVICE_PATH_PROTOCOL        *RemainingDevicePath\r
+  )\r
+{\r
+  EFI_STATUS                        Status;\r
+  EFI_ABSOLUTE_POINTER_PROTOCOL     *AbsolutePointer;\r
+\r
+  //\r
+  // Start ConSplitter on ControllerHandle, and create the virtual\r
+  // agrogated console device on first call Start for a AbsolutePointer handle.\r
+  //\r
+  Status = ConSplitterStart (\r
+             This,\r
+             ControllerHandle,\r
+             mConIn.VirtualHandle,\r
+             &gEfiAbsolutePointerProtocolGuid,\r
+             &gEfiAbsolutePointerProtocolGuid,\r
+             (VOID **) &AbsolutePointer\r
+             );\r
+\r
+  if (EFI_ERROR (Status)) {\r
+    return Status;\r
+  }\r
+\r
+  //\r
+  // Add this devcie into Absolute Pointer devices list.\r
+  //\r
+  return ConSplitterAbsolutePointerAddDevice (&mConIn, AbsolutePointer);\r
+}\r
+\r
+\r
+/**\r
+  Start Console Out Consplitter on device handle.\r
+\r
+  @param  This                 Driver Binding protocol instance pointer.\r
+  @param  ControllerHandle     Handle of device to bind driver to.\r
+  @param  RemainingDevicePath  Optional parameter use to pick a specific child\r
+                               device to start.\r
+\r
+  @retval EFI_SUCCESS          Console Out Consplitter is added to ControllerHandle.\r
+  @retval other                Console Out Consplitter does not support this device.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+ConSplitterConOutDriverBindingStart (\r
+  IN  EFI_DRIVER_BINDING_PROTOCOL     *This,\r
+  IN  EFI_HANDLE                      ControllerHandle,\r
+  IN  EFI_DEVICE_PATH_PROTOCOL        *RemainingDevicePath\r
+  )\r
+{\r
+  EFI_STATUS                           Status;\r
+  EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL      *TextOut;\r
+  EFI_GRAPHICS_OUTPUT_PROTOCOL         *GraphicsOutput;\r
+  EFI_UGA_DRAW_PROTOCOL                *UgaDraw;\r
+  UINTN                                SizeOfInfo;\r
+  EFI_GRAPHICS_OUTPUT_MODE_INFORMATION *Info;\r
+\r
+  //\r
+  // Start ConSplitter on ControllerHandle, and create the virtual\r
+  // agrogated console device on first call Start for a ConsoleOut handle.\r
+  //\r
+  Status = ConSplitterStart (\r
+            This,\r
+            ControllerHandle,\r
+            mConOut.VirtualHandle,\r
+            &gEfiConsoleOutDeviceGuid,\r
+            &gEfiSimpleTextOutProtocolGuid,\r
+            (VOID **) &TextOut\r
+            );\r
+  if (EFI_ERROR (Status)) {\r
+    return Status;\r
+  }\r
+\r
+  GraphicsOutput = NULL;\r
+  UgaDraw        = NULL;\r
+  //\r
+  // Try to Open Graphics Output protocol\r
+  //\r
+  Status = gBS->OpenProtocol (\r
+                  ControllerHandle,\r
+                  &gEfiGraphicsOutputProtocolGuid,\r
+                  (VOID **) &GraphicsOutput,\r
+                  This->DriverBindingHandle,\r
+                  mConOut.VirtualHandle,\r
+                  EFI_OPEN_PROTOCOL_GET_PROTOCOL\r
+                  );\r
+\r
+  if (EFI_ERROR (Status) && FeaturePcdGet (PcdUgaConsumeSupport)) {\r
+    //\r
+    // Open UGA DRAW protocol\r
+    //\r
+    gBS->OpenProtocol (\r
+           ControllerHandle,\r
+           &gEfiUgaDrawProtocolGuid,\r
+           (VOID **) &UgaDraw,\r
+           This->DriverBindingHandle,\r
+           mConOut.VirtualHandle,\r
+           EFI_OPEN_PROTOCOL_GET_PROTOCOL\r
+           );\r
+  }\r
+\r
+  //\r
+  // When new console device is added, the new mode will be set later,\r
+  // so put current mode back to init state.\r
+  //\r
+  mConOut.TextOutMode.Mode = 0xFF;\r
+\r
+  //\r
+  // If both ConOut and StdErr incorporate the same Text Out device,\r
+  // their MaxMode and QueryData should be the intersection of both.\r
+  //\r
+  Status = ConSplitterTextOutAddDevice (&mConOut, TextOut, GraphicsOutput, UgaDraw);\r
+  ConSplitterTextOutSetAttribute (&mConOut.TextOut, EFI_TEXT_ATTR (EFI_LIGHTGRAY, EFI_BLACK));\r
+\r
+  if (FeaturePcdGet (PcdConOutUgaSupport)) {\r
+    //\r
+    // Get the UGA mode data of ConOut from the current mode\r
+    //\r
+    if (GraphicsOutput != NULL) {\r
+      Status = GraphicsOutput->QueryMode (GraphicsOutput, GraphicsOutput->Mode->Mode, &SizeOfInfo, &Info);\r
+      if (EFI_ERROR (Status)) {\r
+        return Status;\r
+      }\r
+      ASSERT ( SizeOfInfo <= sizeof (EFI_GRAPHICS_OUTPUT_MODE_INFORMATION));\r
+\r
+      mConOut.UgaHorizontalResolution = Info->HorizontalResolution;\r
+      mConOut.UgaVerticalResolution   = Info->VerticalResolution;\r
+      mConOut.UgaColorDepth           = 32;\r
+      mConOut.UgaRefreshRate          = 60;\r
+\r
+      FreePool (Info);\r
+\r
+    } else if (UgaDraw != NULL) {\r
+      Status = UgaDraw->GetMode (\r
+                 UgaDraw,\r
+                 &mConOut.UgaHorizontalResolution,\r
+                 &mConOut.UgaVerticalResolution,\r
+                 &mConOut.UgaColorDepth,\r
+                 &mConOut.UgaRefreshRate\r
+                 );\r
+    }\r
+  }\r
+\r
+  return Status;\r
+}\r
+\r
+\r
+/**\r
+  Start Standard Error Consplitter on device handle.\r
+\r
+  @param  This                 Driver Binding protocol instance pointer.\r
+  @param  ControllerHandle     Handle of device to bind driver to.\r
+  @param  RemainingDevicePath  Optional parameter use to pick a specific child\r
+                               device to start.\r
+\r
+  @retval EFI_SUCCESS          Standard Error Consplitter is added to ControllerHandle.\r
+  @retval other                Standard Error Consplitter does not support this device.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+ConSplitterStdErrDriverBindingStart (\r
+  IN  EFI_DRIVER_BINDING_PROTOCOL     *This,\r
+  IN  EFI_HANDLE                      ControllerHandle,\r
+  IN  EFI_DEVICE_PATH_PROTOCOL        *RemainingDevicePath\r
+  )\r
+{\r
+  EFI_STATUS                       Status;\r
+  EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL  *TextOut;\r
+\r
+  //\r
+  // Start ConSplitter on ControllerHandle, and create the virtual\r
+  // agrogated console device on first call Start for a StandardError handle.\r
+  //\r
+  Status = ConSplitterStart (\r
+            This,\r
+            ControllerHandle,\r
+            mStdErr.VirtualHandle,\r
+            &gEfiStandardErrorDeviceGuid,\r
+            &gEfiSimpleTextOutProtocolGuid,\r
+            (VOID **) &TextOut\r
+            );\r
+  if (EFI_ERROR (Status)) {\r
+    return Status;\r
+  }\r
+\r
+  //\r
+  // When new console device is added, the new mode will be set later,\r
+  // so put current mode back to init state.\r
+  //\r
+  mStdErr.TextOutMode.Mode = 0xFF;\r
+\r
+  //\r
+  // If both ConOut and StdErr incorporate the same Text Out device,\r
+  // their MaxMode and QueryData should be the intersection of both.\r
+  //\r
+  Status = ConSplitterTextOutAddDevice (&mStdErr, TextOut, NULL, NULL);\r
+  ConSplitterTextOutSetAttribute (&mStdErr.TextOut, EFI_TEXT_ATTR (EFI_LIGHTGRAY, EFI_BLACK));\r
+  if (EFI_ERROR (Status)) {\r
+    return Status;\r
+  }\r
+\r
+  return Status;\r
+}\r
+\r
+\r
+/**\r
+  Stop ConSplitter on device handle by closing Console Device Guid on device handle\r
+  and the console virtual handle.\r
+\r
+  @param  This                      Protocol instance pointer.\r
+  @param  ControllerHandle          Handle of device.\r
+  @param  ConSplitterVirtualHandle  Console virtual Handle.\r
+  @param  DeviceGuid                The specified Console Device, such as ConInDev,\r
+                                    ConOutDev.\r
+  @param  InterfaceGuid             The specified protocol to be opened.\r
+  @param  Interface                 Protocol interface returned.\r
+\r
+  @retval EFI_SUCCESS               Stop ConSplitter on ControllerHandle successfully.\r
+  @retval other                     Failed to Stop ConSplitter on ControllerHandle.\r
+\r
+**/\r
+EFI_STATUS\r
+ConSplitterStop (\r
+  IN  EFI_DRIVER_BINDING_PROTOCOL     *This,\r
+  IN  EFI_HANDLE                      ControllerHandle,\r
+  IN  EFI_HANDLE                      ConSplitterVirtualHandle,\r
+  IN  EFI_GUID                        *DeviceGuid,\r
+  IN  EFI_GUID                        *InterfaceGuid,\r
+  IN  VOID                            **Interface\r
+  )\r
+{\r
+  EFI_STATUS  Status;\r
+\r
+  Status = gBS->OpenProtocol (\r
+                  ControllerHandle,\r
+                  InterfaceGuid,\r
+                  Interface,\r
+                  This->DriverBindingHandle,\r
+                  ControllerHandle,\r
+                  EFI_OPEN_PROTOCOL_GET_PROTOCOL\r
+                  );\r
+  if (EFI_ERROR (Status)) {\r
+    return Status;\r
+  }\r
+  //\r
+  // close the protocol refered.\r
+  //\r
+  gBS->CloseProtocol (\r
+        ControllerHandle,\r
+        DeviceGuid,\r
+        This->DriverBindingHandle,\r
+        ConSplitterVirtualHandle\r
+        );\r
+\r
+  gBS->CloseProtocol (\r
+        ControllerHandle,\r
+        DeviceGuid,\r
+        This->DriverBindingHandle,\r
+        ControllerHandle\r
+        );\r
+\r
+  return EFI_SUCCESS;\r
+}\r
+\r
+\r
+/**\r
+  Stop Console In ConSplitter on ControllerHandle by closing Console In Devcice GUID.\r
+\r
+  @param  This              Driver Binding protocol instance pointer.\r
+  @param  ControllerHandle  Handle of device to stop driver on\r
+  @param  NumberOfChildren  Number of Handles in ChildHandleBuffer. If number of\r
+                            children is zero stop the entire bus driver.\r
+  @param  ChildHandleBuffer List of Child Handles to Stop.\r
+\r
+  @retval EFI_SUCCESS       This driver is removed ControllerHandle\r
+  @retval other             This driver was not removed from this device\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+ConSplitterConInDriverBindingStop (\r
+  IN  EFI_DRIVER_BINDING_PROTOCOL     *This,\r
+  IN  EFI_HANDLE                      ControllerHandle,\r
+  IN  UINTN                           NumberOfChildren,\r
+  IN  EFI_HANDLE                      *ChildHandleBuffer\r
+  )\r
+{\r
+  EFI_STATUS                        Status;\r
+  EFI_SIMPLE_TEXT_INPUT_PROTOCOL    *TextIn;\r
+  EFI_SIMPLE_TEXT_INPUT_EX_PROTOCOL *TextInEx;\r
+\r
+  if (NumberOfChildren == 0) {\r
+    return EFI_SUCCESS;\r
+  }\r
+\r
+  Status = gBS->OpenProtocol (\r
+                  ControllerHandle,\r
+                  &gEfiSimpleTextInputExProtocolGuid,\r
+                  (VOID **) &TextInEx,\r
+                  This->DriverBindingHandle,\r
+                  ControllerHandle,\r
+                  EFI_OPEN_PROTOCOL_GET_PROTOCOL\r
+                  );\r
+  if (!EFI_ERROR (Status)) {\r
+    //\r
+    // If Simple Text Input Ex protocol exists,\r
+    // remove device from Text Input Ex devices list.\r
+    //\r
+    Status = ConSplitterTextInExDeleteDevice (&mConIn, TextInEx);\r
+    if (EFI_ERROR (Status)) {\r
+      return Status;\r
+    }\r
+  }\r
+\r
+  //\r
+  // Close Simple Text In protocol on controller handle and virtual handle.\r
+  //\r
+  Status = ConSplitterStop (\r
+            This,\r
+            ControllerHandle,\r
+            mConIn.VirtualHandle,\r
+            &gEfiConsoleInDeviceGuid,\r
+            &gEfiSimpleTextInProtocolGuid,\r
+            (VOID **) &TextIn\r
+            );\r
+  if (EFI_ERROR (Status)) {\r
+    return Status;\r
+  }\r
+\r
+  //\r
+  // Remove device from Text Input devices list.\r
+  //\r
+  return ConSplitterTextInDeleteDevice (&mConIn, TextIn);\r
+}\r
+\r
+\r
+/**\r
+  Stop Simple Pointer protocol ConSplitter on ControllerHandle by closing\r
+  Simple Pointer protocol.\r
+\r
+  @param  This              Driver Binding protocol instance pointer.\r
+  @param  ControllerHandle  Handle of device to stop driver on\r
+  @param  NumberOfChildren  Number of Handles in ChildHandleBuffer. If number of\r
+                            children is zero stop the entire bus driver.\r
+  @param  ChildHandleBuffer List of Child Handles to Stop.\r
+\r
+  @retval EFI_SUCCESS       This driver is removed ControllerHandle\r
+  @retval other             This driver was not removed from this device\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+ConSplitterSimplePointerDriverBindingStop (\r
+  IN  EFI_DRIVER_BINDING_PROTOCOL     *This,\r
+  IN  EFI_HANDLE                      ControllerHandle,\r
+  IN  UINTN                           NumberOfChildren,\r
+  IN  EFI_HANDLE                      *ChildHandleBuffer\r
+  )\r
+{\r
+  EFI_STATUS                  Status;\r
+  EFI_SIMPLE_POINTER_PROTOCOL *SimplePointer;\r
+\r
+  if (NumberOfChildren == 0) {\r
+    return EFI_SUCCESS;\r
+  }\r
+\r
+  //\r
+  // Close Simple Pointer protocol on controller handle and virtual handle.\r
+  //\r
+  Status = ConSplitterStop (\r
+            This,\r
+            ControllerHandle,\r
+            mConIn.VirtualHandle,\r
+            &gEfiSimplePointerProtocolGuid,\r
+            &gEfiSimplePointerProtocolGuid,\r
+            (VOID **) &SimplePointer\r
+            );\r
+  if (EFI_ERROR (Status)) {\r
+    return Status;\r
+  }\r
+\r
+  //\r
+  // Remove this device from Simple Pointer device list.\r
+  //\r
+  return ConSplitterSimplePointerDeleteDevice (&mConIn, SimplePointer);\r
+}\r
+\r
+\r
+/**\r
+  Stop Absolute Pointer protocol ConSplitter on ControllerHandle by closing\r
+  Absolute Pointer protocol.\r
+\r
+  @param  This              Driver Binding protocol instance pointer.\r
+  @param  ControllerHandle  Handle of device to stop driver on\r
+  @param  NumberOfChildren  Number of Handles in ChildHandleBuffer. If number of\r
+                            children is zero stop the entire bus driver.\r
+  @param  ChildHandleBuffer List of Child Handles to Stop.\r
+\r
+  @retval EFI_SUCCESS       This driver is removed ControllerHandle\r
+  @retval other             This driver was not removed from this device\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+ConSplitterAbsolutePointerDriverBindingStop (\r
+  IN  EFI_DRIVER_BINDING_PROTOCOL     *This,\r
+  IN  EFI_HANDLE                      ControllerHandle,\r
+  IN  UINTN                           NumberOfChildren,\r
+  IN  EFI_HANDLE                      *ChildHandleBuffer\r
+  )\r
+{\r
+  EFI_STATUS                        Status;\r
+  EFI_ABSOLUTE_POINTER_PROTOCOL     *AbsolutePointer;\r
+\r
+  if (NumberOfChildren == 0) {\r
+    return EFI_SUCCESS;\r
+  }\r
+\r
+  //\r
+  // Close Absolute Pointer protocol on controller handle and virtual handle.\r
+  //\r
+  Status = ConSplitterStop (\r
+             This,\r
+             ControllerHandle,\r
+             mConIn.VirtualHandle,\r
+             &gEfiAbsolutePointerProtocolGuid,\r
+             &gEfiAbsolutePointerProtocolGuid,\r
+             (VOID **) &AbsolutePointer\r
+             );\r
+  if (EFI_ERROR (Status)) {\r
+    return Status;\r
+  }\r
+\r
+  //\r
+  // Remove this device from Absolute Pointer device list.\r
+  //\r
+  return ConSplitterAbsolutePointerDeleteDevice (&mConIn, AbsolutePointer);\r
+}\r
+\r
+\r
+/**\r
+  Stop Console Out ConSplitter on device handle by closing Console Out Devcice GUID.\r
+\r
+  @param  This              Driver Binding protocol instance pointer.\r
+  @param  ControllerHandle  Handle of device to stop driver on\r
+  @param  NumberOfChildren  Number of Handles in ChildHandleBuffer. If number of\r
+                            children is zero stop the entire bus driver.\r
+  @param  ChildHandleBuffer List of Child Handles to Stop.\r
+\r
+  @retval EFI_SUCCESS       This driver is removed ControllerHandle\r
+  @retval other             This driver was not removed from this device\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+ConSplitterConOutDriverBindingStop (\r
+  IN  EFI_DRIVER_BINDING_PROTOCOL     *This,\r
+  IN  EFI_HANDLE                      ControllerHandle,\r
+  IN  UINTN                           NumberOfChildren,\r
+  IN  EFI_HANDLE                      *ChildHandleBuffer\r
+  )\r
+{\r
+  EFI_STATUS                       Status;\r
+  EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL  *TextOut;\r
+\r
+  if (NumberOfChildren == 0) {\r
+    return EFI_SUCCESS;\r
+  }\r
+\r
+  //\r
+  // Close Absolute Pointer protocol on controller handle and virtual handle.\r
+  //\r
+  Status = ConSplitterStop (\r
+            This,\r
+            ControllerHandle,\r
+            mConOut.VirtualHandle,\r
+            &gEfiConsoleOutDeviceGuid,\r
+            &gEfiSimpleTextOutProtocolGuid,\r
+            (VOID **) &TextOut\r
+            );\r
+  if (EFI_ERROR (Status)) {\r
+    return Status;\r
+  }\r
+\r
+  //\r
+  // Remove this device from Text Out device list.\r
+  //\r
+  return ConSplitterTextOutDeleteDevice (&mConOut, TextOut);\r
+}\r
+\r
+\r
+/**\r
+  Stop Standard Error ConSplitter on ControllerHandle by closing Standard Error GUID.\r
+\r
+  @param  This              Driver Binding protocol instance pointer.\r
+  @param  ControllerHandle  Handle of device to stop driver on\r
+  @param  NumberOfChildren  Number of Handles in ChildHandleBuffer. If number of\r
+                            children is zero stop the entire bus driver.\r
+  @param  ChildHandleBuffer List of Child Handles to Stop.\r
+\r
+  @retval EFI_SUCCESS       This driver is removed ControllerHandle\r
+  @retval other             This driver was not removed from this device\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+ConSplitterStdErrDriverBindingStop (\r
+  IN  EFI_DRIVER_BINDING_PROTOCOL     *This,\r
+  IN  EFI_HANDLE                      ControllerHandle,\r
+  IN  UINTN                           NumberOfChildren,\r
+  IN  EFI_HANDLE                      *ChildHandleBuffer\r
+  )\r
+{\r
+  EFI_STATUS                       Status;\r
+  EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL  *TextOut;\r
+\r
+  if (NumberOfChildren == 0) {\r
+    return EFI_SUCCESS;\r
+  }\r
+\r
+  //\r
+  // Close Standard Error Device on controller handle and virtual handle.\r
+  //\r
+  Status = ConSplitterStop (\r
+            This,\r
+            ControllerHandle,\r
+            mStdErr.VirtualHandle,\r
+            &gEfiStandardErrorDeviceGuid,\r
+            &gEfiSimpleTextOutProtocolGuid,\r
+            (VOID **) &TextOut\r
+            );\r
+  if (EFI_ERROR (Status)) {\r
+    return Status;\r
+  }\r
+  //\r
+  // Delete this console error out device's data structures.\r
+  //\r
+  return ConSplitterTextOutDeleteDevice (&mStdErr, TextOut);\r
+}\r
+\r
+\r
+/**\r
+  Take the passed in Buffer of size ElementSize and grow the buffer\r
+  by CONSOLE_SPLITTER_ALLOC_UNIT * ElementSize bytes.\r
+  Copy the current data in Buffer to the new version of Buffer and\r
+  free the old version of buffer.\r
+\r
+  @param  ElementSize              Size of element in array.\r
+  @param  Count                    Current number of elements in array.\r
+  @param  Buffer                   Bigger version of passed in Buffer with all the\r
+                                   data.\r
+\r
+  @retval EFI_SUCCESS              Buffer size has grown.\r
+  @retval EFI_OUT_OF_RESOURCES     Could not grow the buffer size.\r
+\r
+**/\r
+EFI_STATUS\r
+ConSplitterGrowBuffer (\r
+  IN      UINTN                       ElementSize,\r
+  IN OUT  UINTN                       *Count,\r
+  IN OUT  VOID                        **Buffer\r
+  )\r
+{\r
+  VOID  *Ptr;\r
+\r
+  //\r
+  // grow the buffer to new buffer size,\r
+  // copy the old buffer's content to the new-size buffer,\r
+  // then free the old buffer.\r
+  //\r
+  Ptr = ReallocatePool (\r
+          ElementSize * (*Count),\r
+          ElementSize * ((*Count) + CONSOLE_SPLITTER_ALLOC_UNIT),\r
+          *Buffer\r
+          );\r
+  if (Ptr == NULL) {\r
+    return EFI_OUT_OF_RESOURCES;\r
+  }\r
+  *Count += CONSOLE_SPLITTER_ALLOC_UNIT;\r
+  *Buffer = Ptr;\r
+  return EFI_SUCCESS;\r
+}\r
+\r
+\r
+/**\r
+  Add Text Input Device in Consplitter Text Input list.\r
+\r
+  @param  Private                  Text In Splitter pointer.\r
+  @param  TextIn                   Simple Text Input protocol pointer.\r
+\r
+  @retval EFI_SUCCESS              Text Input Device added successfully.\r
+  @retval EFI_OUT_OF_RESOURCES     Could not grow the buffer size.\r
+\r
+**/\r
+EFI_STATUS\r
+ConSplitterTextInAddDevice (\r
+  IN  TEXT_IN_SPLITTER_PRIVATE_DATA   *Private,\r
+  IN  EFI_SIMPLE_TEXT_INPUT_PROTOCOL  *TextIn\r
+  )\r
+{\r
+  EFI_STATUS  Status;\r
+\r
+  //\r
+  // If the Text In List is full, enlarge it by calling ConSplitterGrowBuffer().\r
+  //\r
+  if (Private->CurrentNumberOfConsoles >= Private->TextInListCount) {\r
+    Status = ConSplitterGrowBuffer (\r
+              sizeof (EFI_SIMPLE_TEXT_INPUT_PROTOCOL *),\r
+              &Private->TextInListCount,\r
+              (VOID **) &Private->TextInList\r
+              );\r
+    if (EFI_ERROR (Status)) {\r
+      return EFI_OUT_OF_RESOURCES;\r
+    }\r
+  }\r
+  //\r
+  // Add the new text-in device data structure into the Text In List.\r
+  //\r
+  Private->TextInList[Private->CurrentNumberOfConsoles] = TextIn;\r
+  Private->CurrentNumberOfConsoles++;\r
+\r
+  //\r
+  // Extra CheckEvent added to reduce the double CheckEvent().\r
+  //\r
+  gBS->CheckEvent (TextIn->WaitForKey);\r
+\r
+  return EFI_SUCCESS;\r
+}\r
+\r
+\r
+/**\r
+  Remove Text Input Device from Consplitter Text Input list.\r
+\r
+  @param  Private                  Text In Splitter pointer.\r
+  @param  TextIn                   Simple Text protocol pointer.\r
+\r
+  @retval EFI_SUCCESS              Simple Text Device removed successfully.\r
+  @retval EFI_NOT_FOUND            No Simple Text Device found.\r
+\r
+**/\r
+EFI_STATUS\r
+ConSplitterTextInDeleteDevice (\r
+  IN  TEXT_IN_SPLITTER_PRIVATE_DATA   *Private,\r
+  IN  EFI_SIMPLE_TEXT_INPUT_PROTOCOL  *TextIn\r
+  )\r
+{\r
+  UINTN Index;\r
+  //\r
+  // Remove the specified text-in device data structure from the Text In List,\r
+  // and rearrange the remaining data structures in the Text In List.\r
+  //\r
+  for (Index = 0; Index < Private->CurrentNumberOfConsoles; Index++) {\r
+    if (Private->TextInList[Index] == TextIn) {\r
+      for (; Index < Private->CurrentNumberOfConsoles - 1; Index++) {\r
+        Private->TextInList[Index] = Private->TextInList[Index + 1];\r
+      }\r
+\r
+      Private->CurrentNumberOfConsoles--;\r
+      return EFI_SUCCESS;\r
+    }\r
+  }\r
+\r
+  return EFI_NOT_FOUND;\r
+}\r
+\r
+/**\r
+  Add Text Input Ex Device in Consplitter Text Input Ex list.\r
+\r
+  @param  Private                  Text In Splitter pointer.\r
+  @param  TextInEx                 Simple Text Input Ex Input protocol pointer.\r
+\r
+  @retval EFI_SUCCESS              Text Input Ex Device added successfully.\r
+  @retval EFI_OUT_OF_RESOURCES     Could not grow the buffer size.\r
+\r
+**/\r
+EFI_STATUS\r
+ConSplitterTextInExAddDevice (\r
+  IN  TEXT_IN_SPLITTER_PRIVATE_DATA         *Private,\r
+  IN  EFI_SIMPLE_TEXT_INPUT_EX_PROTOCOL     *TextInEx\r
+  )\r
+{\r
+  EFI_STATUS                  Status;\r
+  LIST_ENTRY                  *Link;\r
+  TEXT_IN_EX_SPLITTER_NOTIFY  *CurrentNotify;\r
+  UINTN                       TextInExListCount;\r
+\r
+  //\r
+  // Enlarge the NotifyHandleList and the TextInExList\r
+  //\r
+  if (Private->CurrentNumberOfExConsoles >= Private->TextInExListCount) {\r
+    for (Link = Private->NotifyList.ForwardLink; Link != &Private->NotifyList; Link = Link->ForwardLink) {\r
+      CurrentNotify     = TEXT_IN_EX_SPLITTER_NOTIFY_FROM_THIS (Link);\r
+      TextInExListCount = Private->TextInExListCount;\r
+\r
+      Status = ConSplitterGrowBuffer (\r
+                 sizeof (EFI_HANDLE),\r
+                 &TextInExListCount,\r
+                 (VOID **) &CurrentNotify->NotifyHandleList\r
+                 );\r
+      if (EFI_ERROR (Status)) {\r
+        return EFI_OUT_OF_RESOURCES;\r
+      }\r
+    }\r
+    Status = ConSplitterGrowBuffer (\r
+              sizeof (EFI_SIMPLE_TEXT_INPUT_EX_PROTOCOL *),\r
+              &Private->TextInExListCount,\r
+              (VOID **) &Private->TextInExList\r
+              );\r
+    if (EFI_ERROR (Status)) {\r
+      return EFI_OUT_OF_RESOURCES;\r
+    }\r
+  }\r
+\r
+  //\r
+  // Register the key notify in the new text-in device\r
+  //\r
+  for (Link = Private->NotifyList.ForwardLink; Link != &Private->NotifyList; Link = Link->ForwardLink) {\r
+    CurrentNotify = TEXT_IN_EX_SPLITTER_NOTIFY_FROM_THIS (Link);\r
+    Status = TextInEx->RegisterKeyNotify (\r
+                         TextInEx,\r
+                         &CurrentNotify->KeyData,\r
+                         CurrentNotify->KeyNotificationFn,\r
+                         &CurrentNotify->NotifyHandleList[Private->CurrentNumberOfExConsoles]\r
+                         );\r
+    if (EFI_ERROR (Status)) {\r
+      for (Link = Link->BackLink; Link != &Private->NotifyList; Link = Link->BackLink) {\r
+        CurrentNotify = TEXT_IN_EX_SPLITTER_NOTIFY_FROM_THIS (Link);\r
+        TextInEx->UnregisterKeyNotify (\r
+                    TextInEx,\r
+                    CurrentNotify->NotifyHandleList[Private->CurrentNumberOfExConsoles]\r
+                    );\r
+      }\r
+      return Status;\r
+    }\r
+  }\r
+\r
+  //\r
+  // Add the new text-in device data structure into the Text Input Ex List.\r
+  //\r
+  Private->TextInExList[Private->CurrentNumberOfExConsoles] = TextInEx;\r
+  Private->CurrentNumberOfExConsoles++;\r
+\r
+  //\r
+  // Extra CheckEvent added to reduce the double CheckEvent().\r
+  //\r
+  gBS->CheckEvent (TextInEx->WaitForKeyEx);\r
+\r
+  return EFI_SUCCESS;\r
+}\r
+\r
+/**\r
+  Remove Text Ex Device from Consplitter Text Input Ex list.\r
+\r
+  @param  Private                  Text In Splitter pointer.\r
+  @param  TextInEx                 Simple Text Ex protocol pointer.\r
+\r
+  @retval EFI_SUCCESS              Simple Text Input Ex Device removed successfully.\r
+  @retval EFI_NOT_FOUND            No Simple Text Input Ex Device found.\r
+\r
+**/\r
+EFI_STATUS\r
+ConSplitterTextInExDeleteDevice (\r
+  IN  TEXT_IN_SPLITTER_PRIVATE_DATA         *Private,\r
+  IN  EFI_SIMPLE_TEXT_INPUT_EX_PROTOCOL     *TextInEx\r
+  )\r
+{\r
+  UINTN Index;\r
+  //\r
+  // Remove the specified text-in device data structure from the Text Input Ex List,\r
+  // and rearrange the remaining data structures in the Text In List.\r
+  //\r
+  for (Index = 0; Index < Private->CurrentNumberOfExConsoles; Index++) {\r
+    if (Private->TextInExList[Index] == TextInEx) {\r
+      for (; Index < Private->CurrentNumberOfExConsoles - 1; Index++) {\r
+        Private->TextInExList[Index] = Private->TextInExList[Index + 1];\r
+      }\r
+\r
+      Private->CurrentNumberOfExConsoles--;\r
+      return EFI_SUCCESS;\r
+    }\r
+  }\r
+\r
+  return EFI_NOT_FOUND;\r
+}\r
+\r
+\r
+/**\r
+  Add Simple Pointer Device in Consplitter Simple Pointer list.\r
+\r
+  @param  Private                  Text In Splitter pointer.\r
+  @param  SimplePointer            Simple Pointer protocol pointer.\r
+\r
+  @retval EFI_SUCCESS              Simple Pointer Device added successfully.\r
+  @retval EFI_OUT_OF_RESOURCES     Could not grow the buffer size.\r
+\r
+**/\r
+EFI_STATUS\r
+ConSplitterSimplePointerAddDevice (\r
+  IN  TEXT_IN_SPLITTER_PRIVATE_DATA   *Private,\r
+  IN  EFI_SIMPLE_POINTER_PROTOCOL     *SimplePointer\r
+  )\r
+{\r
+  EFI_STATUS  Status;\r
+\r
+  //\r
+  // If the Simple Pointer List is full, enlarge it by calling ConSplitterGrowBuffer().\r
+  //\r
+  if (Private->CurrentNumberOfPointers >= Private->PointerListCount) {\r
+    Status = ConSplitterGrowBuffer (\r
+              sizeof (EFI_SIMPLE_POINTER_PROTOCOL *),\r
+              &Private->PointerListCount,\r
+              (VOID **) &Private->PointerList\r
+              );\r
+    if (EFI_ERROR (Status)) {\r
+      return EFI_OUT_OF_RESOURCES;\r
+    }\r
+  }\r
+  //\r
+  // Add the new text-in device data structure into the Simple Pointer List.\r
+  //\r
+  Private->PointerList[Private->CurrentNumberOfPointers] = SimplePointer;\r
+  Private->CurrentNumberOfPointers++;\r
+\r
+  return EFI_SUCCESS;\r
+}\r
+\r
+\r
+/**\r
+  Remove Simple Pointer Device from Consplitter Simple Pointer list.\r
+\r
+  @param  Private                  Text In Splitter pointer.\r
+  @param  SimplePointer            Simple Pointer protocol pointer.\r
+\r
+  @retval EFI_SUCCESS              Simple Pointer Device removed successfully.\r
+  @retval EFI_NOT_FOUND            No Simple Pointer Device found.\r
+\r
+**/\r
+EFI_STATUS\r
+ConSplitterSimplePointerDeleteDevice (\r
+  IN  TEXT_IN_SPLITTER_PRIVATE_DATA   *Private,\r
+  IN  EFI_SIMPLE_POINTER_PROTOCOL     *SimplePointer\r
+  )\r
+{\r
+  UINTN Index;\r
+  //\r
+  // Remove the specified text-in device data structure from the Simple Pointer List,\r
+  // and rearrange the remaining data structures in the Text In List.\r
+  //\r
+  for (Index = 0; Index < Private->CurrentNumberOfPointers; Index++) {\r
+    if (Private->PointerList[Index] == SimplePointer) {\r
+      for (; Index < Private->CurrentNumberOfPointers - 1; Index++) {\r
+        Private->PointerList[Index] = Private->PointerList[Index + 1];\r
+      }\r
+\r
+      Private->CurrentNumberOfPointers--;\r
+      return EFI_SUCCESS;\r
+    }\r
+  }\r
+\r
+  return EFI_NOT_FOUND;\r
+}\r
+\r
+\r
+/**\r
+  Add Absolute Pointer Device in Consplitter Absolute Pointer list.\r
+\r
+  @param  Private                  Text In Splitter pointer.\r
+  @param  AbsolutePointer          Absolute Pointer protocol pointer.\r
+\r
+  @retval EFI_SUCCESS              Absolute Pointer Device added successfully.\r
+  @retval EFI_OUT_OF_RESOURCES     Could not grow the buffer size.\r
+\r
+**/\r
+EFI_STATUS\r
+ConSplitterAbsolutePointerAddDevice (\r
+  IN  TEXT_IN_SPLITTER_PRIVATE_DATA     *Private,\r
+  IN  EFI_ABSOLUTE_POINTER_PROTOCOL     *AbsolutePointer\r
+  )\r
+{\r
+  EFI_STATUS  Status;\r
+\r
+  //\r
+  // If the Absolute Pointer List is full, enlarge it by calling ConSplitterGrowBuffer().\r
+  //\r
+  if (Private->CurrentNumberOfAbsolutePointers >= Private->AbsolutePointerListCount) {\r
+    Status = ConSplitterGrowBuffer (\r
+              sizeof (EFI_ABSOLUTE_POINTER_PROTOCOL *),\r
+              &Private->AbsolutePointerListCount,\r
+              (VOID **) &Private->AbsolutePointerList\r
+              );\r
+    if (EFI_ERROR (Status)) {\r
+      return EFI_OUT_OF_RESOURCES;\r
+    }\r
+  }\r
+  //\r
+  // Add the new text-in device data structure into the Absolute Pointer List.\r
+  //\r
+  Private->AbsolutePointerList[Private->CurrentNumberOfAbsolutePointers] = AbsolutePointer;\r
+  Private->CurrentNumberOfAbsolutePointers++;\r
+\r
+  return EFI_SUCCESS;\r
+}\r
+\r
+\r
+/**\r
+  Remove Absolute Pointer Device from Consplitter Absolute Pointer list.\r
+\r
+  @param  Private                  Text In Splitter pointer.\r
+  @param  AbsolutePointer          Absolute Pointer protocol pointer.\r
+\r
+  @retval EFI_SUCCESS              Absolute Pointer Device removed successfully.\r
+  @retval EFI_NOT_FOUND            No Absolute Pointer Device found.\r
+\r
+**/\r
+EFI_STATUS\r
+ConSplitterAbsolutePointerDeleteDevice (\r
+  IN  TEXT_IN_SPLITTER_PRIVATE_DATA     *Private,\r
+  IN  EFI_ABSOLUTE_POINTER_PROTOCOL     *AbsolutePointer\r
+  )\r
+{\r
+  UINTN Index;\r
+  //\r
+  // Remove the specified text-in device data structure from the Absolute Pointer List,\r
+  // and rearrange the remaining data structures from the Absolute Pointer List.\r
+  //\r
+  for (Index = 0; Index < Private->CurrentNumberOfAbsolutePointers; Index++) {\r
+    if (Private->AbsolutePointerList[Index] == AbsolutePointer) {\r
+      for (; Index < Private->CurrentNumberOfAbsolutePointers - 1; Index++) {\r
+        Private->AbsolutePointerList[Index] = Private->AbsolutePointerList[Index + 1];\r
+      }\r
+\r
+      Private->CurrentNumberOfAbsolutePointers--;\r
+      return EFI_SUCCESS;\r
+    }\r
+  }\r
+\r
+  return EFI_NOT_FOUND;\r
+}\r
+\r
+/**\r
+  Reallocate Text Out mode map.\r
+\r
+  Allocate new buffer and copy original buffer into the new buffer.\r
+\r
+  @param  Private                  Consplitter Text Out pointer.\r
+\r
+  @retval EFI_SUCCESS              Buffer size has grown\r
+  @retval EFI_OUT_OF_RESOURCES     Could not grow the buffer size.\r
+\r
+**/\r
+EFI_STATUS\r
+ConSplitterGrowMapTable (\r
+  IN  TEXT_OUT_SPLITTER_PRIVATE_DATA  *Private\r
+  )\r
+{\r
+  UINTN Size;\r
+  UINTN NewSize;\r
+  UINTN TotalSize;\r
+  INT32 *TextOutModeMap;\r
+  INT32 *OldTextOutModeMap;\r
+  INT32 *SrcAddress;\r
+  INT32 Index;\r
+  UINTN OldStepSize;\r
+  UINTN NewStepSize;\r
+\r
+  NewSize           = Private->TextOutListCount * sizeof (INT32);\r
+  OldTextOutModeMap = Private->TextOutModeMap;\r
+  TotalSize         = NewSize * (Private->TextOutQueryDataCount);\r
+\r
+  //\r
+  // Allocate new buffer for Text Out List.\r
+  //\r
+  TextOutModeMap    = AllocatePool (TotalSize);\r
+  if (TextOutModeMap == NULL) {\r
+    return EFI_OUT_OF_RESOURCES;\r
+  }\r
+\r
+  SetMem (TextOutModeMap, TotalSize, 0xFF);\r
+  Private->TextOutModeMap = TextOutModeMap;\r
+\r
+  //\r
+  // If TextOutList has been enlarged, need to realloc the mode map table\r
+  // The mode map table is regarded as a two dimension array.\r
+  //\r
+  //                         Old                    New\r
+  //  0   ---------> TextOutListCount ----> TextOutListCount\r
+  //  |   -------------------------------------------\r
+  //  |  |                    |                      |\r
+  //  |  |                    |                      |\r
+  //  |  |                    |                      |\r
+  //  |  |                    |                      |\r
+  //  |  |                    |                      |\r
+  // \/  |                    |                      |\r
+  //      -------------------------------------------\r
+  // QueryDataCount\r
+  //\r
+  if (OldTextOutModeMap != NULL) {\r
+\r
+    Size        = Private->CurrentNumberOfConsoles * sizeof (INT32);\r
+    Index       = 0;\r
+    SrcAddress  = OldTextOutModeMap;\r
+    NewStepSize = NewSize / sizeof(INT32);    \r
+    // If Private->CurrentNumberOfConsoles is not zero and OldTextOutModeMap\r
+    // is not NULL, it indicates that the original TextOutModeMap is not enough\r
+    // for the new console devices and has been enlarged by CONSOLE_SPLITTER_ALLOC_UNIT columns.\r
+    //\r
+    OldStepSize = NewStepSize - CONSOLE_SPLITTER_ALLOC_UNIT;\r
+\r
+    //\r
+    // Copy the old data to the new one\r
+    //\r
+    while (Index < Private->TextOutMode.MaxMode) {\r
+      CopyMem (TextOutModeMap, SrcAddress, Size);\r
+      //\r
+      // Go to next row of new TextOutModeMap.\r
+      //\r
+      TextOutModeMap += NewStepSize;\r
+      //\r
+      // Go to next row of old TextOutModeMap.\r
+      //\r
+      SrcAddress += OldStepSize;\r
+      Index++;\r
+    }\r
+    //\r
+    // Free the old buffer\r
+    //\r
+    FreePool (OldTextOutModeMap);\r
+  }\r
+\r
+  return EFI_SUCCESS;\r
+}\r
+\r
+\r
+/**\r
+  Add new device's output mode to console splitter's mode list.\r
+\r
+  @param  Private               Text Out Splitter pointer\r
+  @param  TextOut               Simple Text Output protocol pointer.\r
+\r
+  @retval EFI_SUCCESS           Device added successfully.\r
+  @retval EFI_OUT_OF_RESOURCES  Could not grow the buffer size.\r
+\r
+**/\r
+EFI_STATUS\r
+ConSplitterAddOutputMode (\r
+  IN  TEXT_OUT_SPLITTER_PRIVATE_DATA     *Private,\r
+  IN  EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL    *TextOut\r
+  )\r
+{\r
+  EFI_STATUS  Status;\r
+  INT32       MaxMode;\r
+  INT32       Mode;\r
+  UINTN       Index;\r
+\r
+  MaxMode                       = TextOut->Mode->MaxMode;\r
+  Private->TextOutMode.MaxMode  = MaxMode;\r
+\r
+  //\r
+  // Grow the buffer if query data buffer is not large enough to\r
+  // hold all the mode supported by the first console.\r
+  //\r
+  while (MaxMode > (INT32) Private->TextOutQueryDataCount) {\r
+    Status = ConSplitterGrowBuffer (\r
+              sizeof (TEXT_OUT_SPLITTER_QUERY_DATA),\r
+              &Private->TextOutQueryDataCount,\r
+              (VOID **) &Private->TextOutQueryData\r
+              );\r
+    if (EFI_ERROR (Status)) {\r
+      return EFI_OUT_OF_RESOURCES;\r
+    }\r
+  }\r
+  //\r
+  // Allocate buffer for the output mode map\r
+  //\r
+  Status = ConSplitterGrowMapTable (Private);\r
+  if (EFI_ERROR (Status)) {\r
+    return EFI_OUT_OF_RESOURCES;\r
+  }\r
+  //\r
+  // As the first textout device, directly add the mode in to QueryData\r
+  // and at the same time record the mapping between QueryData and TextOut.\r
+  //\r
+  Mode  = 0;\r
+  Index = 0;\r
+  while (Mode < MaxMode) {\r
+    Status = TextOut->QueryMode (\r
+                  TextOut,\r
+                  Mode,\r
+                  &Private->TextOutQueryData[Mode].Columns,\r
+                  &Private->TextOutQueryData[Mode].Rows\r
+                  );\r
+    //\r
+    // If mode 1 (80x50) is not supported, make sure mode 1 in TextOutQueryData\r
+    // is clear to 0x0.\r
+    //\r
+    if ((EFI_ERROR(Status)) && (Mode == 1)) {\r
+      Private->TextOutQueryData[Mode].Columns = 0;\r
+      Private->TextOutQueryData[Mode].Rows = 0;\r
+    }\r
+    Private->TextOutModeMap[Index] = Mode;\r
+    Mode++;\r
+    Index += Private->TextOutListCount;\r
+  }\r
+\r
+  return EFI_SUCCESS;\r
+}\r
+\r
+/**\r
+  Reconstruct TextOutModeMap to get intersection of modes.\r
+\r
+  This routine reconstruct TextOutModeMap to get the intersection\r
+  of modes for all console out devices. Because EFI/UEFI spec require\r
+  mode 0 is 80x25, mode 1 is 80x50, this routine will not check the\r
+  intersection for mode 0 and mode 1.\r
+\r
+  @param TextOutModeMap  Current text out mode map, begin with the mode 80x25\r
+  @param NewlyAddedMap   New text out mode map, begin with the mode 80x25\r
+  @param MapStepSize     Mode step size for one console device\r
+  @param NewMapStepSize  New Mode step size for one console device\r
+  @param MaxMode         IN: Current max text mode, OUT: Updated max text mode.\r
+  @param CurrentMode     IN: Current text mode,     OUT: Updated current text mode.\r
+\r
+**/\r
+VOID\r
+ConSplitterGetIntersection (\r
+  IN     INT32                        *TextOutModeMap,\r
+  IN     INT32                        *NewlyAddedMap,\r
+  IN     UINTN                        MapStepSize,\r
+  IN     UINTN                        NewMapStepSize,\r
+  IN OUT INT32                        *MaxMode,\r
+  IN OUT INT32                        *CurrentMode\r
+  )\r
+{\r
+  INT32 Index;\r
+  INT32 *CurrentMapEntry;\r
+  INT32 *NextMapEntry;\r
+  INT32 *NewMapEntry;\r
+  INT32 CurrentMaxMode;\r
+  INT32 Mode;\r
+\r
+  //\r
+  // According to EFI/UEFI spec, mode 0 and mode 1 have been reserved\r
+  // for 80x25 and 80x50 in Simple Text Out protocol, so don't make intersection\r
+  // for mode 0 and mode 1, mode number starts from 2.\r
+  //\r
+  Index           = 2;\r
+  CurrentMapEntry = &TextOutModeMap[MapStepSize * 2];\r
+  NextMapEntry    = CurrentMapEntry;\r
+  NewMapEntry     = &NewlyAddedMap[NewMapStepSize * 2];\r
+\r
+  CurrentMaxMode  = *MaxMode;\r
+  Mode            = *CurrentMode;\r
+\r
+  while (Index < CurrentMaxMode) {\r
+    if (*NewMapEntry == -1) {\r
+      //\r
+      // This mode is not supported any more. Remove it. Special care\r
+      // must be taken as this remove will also affect current mode;\r
+      //\r
+      if (Index == *CurrentMode) {\r
+        Mode = -1;\r
+      } else if (Index < *CurrentMode) {\r
+        Mode--;\r
+      }\r
+      (*MaxMode)--;\r
+    } else {\r
+      if (CurrentMapEntry != NextMapEntry) {\r
+        CopyMem (NextMapEntry, CurrentMapEntry, MapStepSize * sizeof (INT32));\r
+      }\r
+\r
+      NextMapEntry += MapStepSize;\r
+    }\r
+\r
+    CurrentMapEntry += MapStepSize;\r
+    NewMapEntry     += NewMapStepSize;\r
+    Index++;\r
+  }\r
+\r
+  *CurrentMode = Mode;\r
+\r
+  return ;\r
+}\r
+\r
+/**\r
+  Sync the device's output mode to console splitter's mode list.\r
+\r
+  @param  Private               Text Out Splitter pointer.\r
+  @param  TextOut               Simple Text Output protocol pointer.\r
+\r
+**/\r
+VOID\r
+ConSplitterSyncOutputMode (\r
+  IN  TEXT_OUT_SPLITTER_PRIVATE_DATA     *Private,\r
+  IN  EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL    *TextOut\r
+  )\r
+{\r
+  INT32                         CurrentMaxMode;\r
+  INT32                         Mode;\r
+  INT32                         Index;\r
+  INT32                         *TextOutModeMap;\r
+  INT32                         *MapTable;\r
+  INT32                         QueryMode;\r
+  TEXT_OUT_SPLITTER_QUERY_DATA  *TextOutQueryData;\r
+  UINTN                         Rows;\r
+  UINTN                         Columns;\r
+  UINTN                         StepSize;\r
+  EFI_STATUS                    Status;\r
+\r
+  //\r
+  // Must make sure that current mode won't change even if mode number changes\r
+  //\r
+  CurrentMaxMode    = Private->TextOutMode.MaxMode;\r
+  TextOutModeMap    = Private->TextOutModeMap;\r
+  StepSize          = Private->TextOutListCount;\r
+  TextOutQueryData  = Private->TextOutQueryData;\r
+\r
+  //\r
+  // Query all the mode that the newly added TextOut supports\r
+  //\r
+  Mode      = 0;\r
+  MapTable  = TextOutModeMap + Private->CurrentNumberOfConsoles;\r
+  while (Mode < TextOut->Mode->MaxMode) {\r
+    Status = TextOut->QueryMode (TextOut, Mode, &Columns, &Rows);\r
+\r
+    if (EFI_ERROR(Status)) {\r
+      if (Mode == 1) {\r
+        //\r
+        // If mode 1 (80x50) is not supported, make sure mode 1 in TextOutQueryData\r
+        // is clear to 0x0.\r
+        //\r
+        MapTable[StepSize] = Mode;\r
+        TextOutQueryData[Mode].Columns = 0;\r
+        TextOutQueryData[Mode].Rows = 0;\r
+      }\r
+      Mode++;\r
+      continue;\r
+    }\r
+    //\r
+    // Search the intersection map and QueryData database to see if they intersects\r
+    //\r
+    Index = 0;\r
+    while (Index < CurrentMaxMode) {\r
+      QueryMode = *(TextOutModeMap + Index * StepSize);\r
+      if ((TextOutQueryData[QueryMode].Rows == Rows) && (TextOutQueryData[QueryMode].Columns == Columns)) {\r
+        MapTable[Index * StepSize] = Mode;\r
+        break;\r
+      }\r
+      Index++;\r
+    }\r
+    Mode++;\r
+  }\r
+  //\r
+  // Now search the TextOutModeMap table to find the intersection of supported\r
+  // mode between ConSplitter and the newly added device.\r
+  //\r
+  ConSplitterGetIntersection (\r
+    TextOutModeMap,\r
+    MapTable,\r
+    StepSize,\r
+    StepSize,\r
+    &Private->TextOutMode.MaxMode,\r
+    &Private->TextOutMode.Mode\r
+    );\r
+\r
+  return ;\r
+}\r
+\r
+\r
+/**\r
+  Sync output device between ConOut and StdErr output.\r
+\r
+  @retval EFI_SUCCESS              Sync implemented successfully.\r
+  @retval EFI_OUT_OF_RESOURCES     Could not grow the buffer size.\r
+\r
+**/\r
+EFI_STATUS\r
+ConSplitterGetIntersectionBetweenConOutAndStrErr (\r
+  VOID\r
+  )\r
+{\r
+  UINTN                         ConOutNumOfConsoles;\r
+  UINTN                         StdErrNumOfConsoles;\r
+  TEXT_OUT_AND_GOP_DATA         *ConOutTextOutList;\r
+  TEXT_OUT_AND_GOP_DATA         *StdErrTextOutList;\r
+  UINTN                         Indexi;\r
+  UINTN                         Indexj;\r
+  UINTN                         ConOutRows;\r
+  UINTN                         ConOutColumns;\r
+  UINTN                         StdErrRows;\r
+  UINTN                         StdErrColumns;\r
+  INT32                         ConOutMaxMode;\r
+  INT32                         StdErrMaxMode;\r
+  INT32                         ConOutMode;\r
+  INT32                         StdErrMode;\r
+  INT32                         Mode;\r
+  INT32                         Index;\r
+  INT32                         *ConOutModeMap;\r
+  INT32                         *StdErrModeMap;\r
+  INT32                         *ConOutMapTable;\r
+  INT32                         *StdErrMapTable;\r
+  TEXT_OUT_SPLITTER_QUERY_DATA  *ConOutQueryData;\r
+  TEXT_OUT_SPLITTER_QUERY_DATA  *StdErrQueryData;\r
+  UINTN                         ConOutStepSize;\r
+  UINTN                         StdErrStepSize;\r
+  BOOLEAN                       FoundTheSameTextOut;\r
+  UINTN                         ConOutMapTableSize;\r
+  UINTN                         StdErrMapTableSize;\r
+\r
+  ConOutNumOfConsoles = mConOut.CurrentNumberOfConsoles;\r
+  StdErrNumOfConsoles = mStdErr.CurrentNumberOfConsoles;\r
+  ConOutTextOutList   = mConOut.TextOutList;\r
+  StdErrTextOutList   = mStdErr.TextOutList;\r
+\r
+  Indexi              = 0;\r
+  FoundTheSameTextOut = FALSE;\r
+  while ((Indexi < ConOutNumOfConsoles) && (!FoundTheSameTextOut)) {\r
+    Indexj = 0;\r
+    while (Indexj < StdErrNumOfConsoles) {\r
+      if (ConOutTextOutList->TextOut == StdErrTextOutList->TextOut) {\r
+        FoundTheSameTextOut = TRUE;\r
+        break;\r
+      }\r
+\r
+      Indexj++;\r
+      StdErrTextOutList++;\r
+    }\r
+\r
+    Indexi++;\r
+    ConOutTextOutList++;\r
+  }\r
+\r
+  if (!FoundTheSameTextOut) {\r
+    return EFI_SUCCESS;\r
+  }\r
+  //\r
+  // Must make sure that current mode won't change even if mode number changes\r
+  //\r
+  ConOutMaxMode     = mConOut.TextOutMode.MaxMode;\r
+  ConOutModeMap     = mConOut.TextOutModeMap;\r
+  ConOutStepSize    = mConOut.TextOutListCount;\r
+  ConOutQueryData   = mConOut.TextOutQueryData;\r
+\r
+  StdErrMaxMode     = mStdErr.TextOutMode.MaxMode;\r
+  StdErrModeMap     = mStdErr.TextOutModeMap;\r
+  StdErrStepSize    = mStdErr.TextOutListCount;\r
+  StdErrQueryData   = mStdErr.TextOutQueryData;\r
+\r
+  //\r
+  // Allocate the map table and set the map table's index to -1.\r
+  //\r
+  ConOutMapTableSize  = ConOutMaxMode * sizeof (INT32);\r
+  ConOutMapTable      = AllocateZeroPool (ConOutMapTableSize);\r
+  if (ConOutMapTable == NULL) {\r
+    return EFI_OUT_OF_RESOURCES;\r
+  }\r
+\r
+  SetMem (ConOutMapTable, ConOutMapTableSize, 0xFF);\r
+\r
+  StdErrMapTableSize  = StdErrMaxMode * sizeof (INT32);\r
+  StdErrMapTable      = AllocateZeroPool (StdErrMapTableSize);\r
+  if (StdErrMapTable == NULL) {\r
+    return EFI_OUT_OF_RESOURCES;\r
+  }\r
+\r
+  SetMem (StdErrMapTable, StdErrMapTableSize, 0xFF);\r
+\r
+  //\r
+  // Find the intersection of the two set of modes. If they actually intersect, the\r
+  // correponding entry in the map table is set to 1.\r
+  //\r
+  Mode = 0;\r
+  while (Mode < ConOutMaxMode) {\r
+    //\r
+    // Search the intersection map and QueryData database to see if they intersect\r
+    //\r
+    Index = 0;\r
+    ConOutMode    = *(ConOutModeMap + Mode * ConOutStepSize);\r
+    ConOutRows    = ConOutQueryData[ConOutMode].Rows;\r
+    ConOutColumns = ConOutQueryData[ConOutMode].Columns;\r
+    while (Index < StdErrMaxMode) {\r
+      StdErrMode    = *(StdErrModeMap + Index * StdErrStepSize);\r
+      StdErrRows    = StdErrQueryData[StdErrMode].Rows;\r
+      StdErrColumns = StdErrQueryData[StdErrMode].Columns;\r
+      if ((StdErrRows == ConOutRows) && (StdErrColumns == ConOutColumns)) {\r
+        ConOutMapTable[Mode]  = 1;\r
+        StdErrMapTable[Index] = 1;\r
+        break;\r
+      }\r
+\r
+      Index++;\r
+    }\r
+\r
+    Mode++;\r
+  }\r
+  //\r
+  // Now search the TextOutModeMap table to find the intersection of supported\r
+  // mode between ConSplitter and the newly added device.\r
+  //\r
+  ConSplitterGetIntersection (\r
+    ConOutModeMap,\r
+    ConOutMapTable,\r
+    mConOut.TextOutListCount,\r
+    1,\r
+    &(mConOut.TextOutMode.MaxMode),\r
+    &(mConOut.TextOutMode.Mode)\r
+    );\r
+\r
+  if (mConOut.TextOutMode.Mode < 0) {\r
+    mConOut.TextOut.SetMode (&(mConOut.TextOut), 0);\r
+  }\r
+\r
+  ConSplitterGetIntersection (\r
+    StdErrModeMap,\r
+    StdErrMapTable,\r
+    mStdErr.TextOutListCount,\r
+    1,\r
+    &(mStdErr.TextOutMode.MaxMode),\r
+    &(mStdErr.TextOutMode.Mode)\r
+    );\r
+\r
+  if (mStdErr.TextOutMode.Mode < 0) {\r
+    mStdErr.TextOut.SetMode (&(mStdErr.TextOut), 0);\r
+  }\r
+\r
+  FreePool (ConOutMapTable);\r
+  FreePool (StdErrMapTable);\r
+\r
+  return EFI_SUCCESS;\r
+}\r
+\r
+\r
+/**\r
+  Add Grahpics Output modes into Consplitter Text Out list.\r
+\r
+  @param  Private               Text Out Splitter pointer.\r
+  @param  GraphicsOutput        Graphics Output protocol pointer.\r
+  @param  UgaDraw               UGA Draw protocol pointer.\r
+\r
+  @retval EFI_SUCCESS           Output mode added successfully.\r
+  @retval other                 Failed to add output mode.\r
+\r
+**/\r
+EFI_STATUS\r
+ConSplitterAddGraphicsOutputMode (\r
+  IN  TEXT_OUT_SPLITTER_PRIVATE_DATA  *Private,\r
+  IN  EFI_GRAPHICS_OUTPUT_PROTOCOL    *GraphicsOutput,\r
+  IN  EFI_UGA_DRAW_PROTOCOL           *UgaDraw\r
+  )\r
+{\r
+  EFI_STATUS                           Status;\r
+  UINTN                                Index;\r
+  UINTN                                CurrentIndex;\r
+  EFI_GRAPHICS_OUTPUT_MODE_INFORMATION *Mode;\r
+  UINTN                                SizeOfInfo;\r
+  EFI_GRAPHICS_OUTPUT_MODE_INFORMATION *Info;\r
+  EFI_GRAPHICS_OUTPUT_PROTOCOL_MODE    *CurrentGraphicsOutputMode;\r
+  EFI_GRAPHICS_OUTPUT_MODE_INFORMATION *ModeBuffer;\r
+  EFI_GRAPHICS_OUTPUT_MODE_INFORMATION *MatchedMode;\r
+  UINTN                                NumberIndex;\r
+  BOOLEAN                              Match;\r
+  BOOLEAN                              AlreadyExist;\r
+  UINT32                               UgaHorizontalResolution;\r
+  UINT32                               UgaVerticalResolution;\r
+  UINT32                               UgaColorDepth;\r
+  UINT32                               UgaRefreshRate;\r
+\r
+  ASSERT (GraphicsOutput != NULL || UgaDraw != NULL);\r
+\r
+  CurrentGraphicsOutputMode = Private->GraphicsOutput.Mode;\r
+\r
+  Index        = 0;\r
+  CurrentIndex = 0;\r
+  Status       = EFI_SUCCESS;\r
+\r
+  if (Private->CurrentNumberOfUgaDraw != 0) {\r
+    //\r
+    // If any UGA device has already been added, then there is no need to\r
+    // calculate intersection of display mode of different GOP/UGA device,\r
+    // since only one display mode will be exported (i.e. user-defined mode)\r
+    //\r
+    goto Done;\r
+  }\r
+\r
+  if (GraphicsOutput != NULL) {\r
+    if (Private->CurrentNumberOfGraphicsOutput == 0) {\r
+        //\r
+        // This is the first Graphics Output device added\r
+        //\r
+        CurrentGraphicsOutputMode->MaxMode = GraphicsOutput->Mode->MaxMode;\r
+        CurrentGraphicsOutputMode->Mode = GraphicsOutput->Mode->Mode;\r
+        CopyMem (CurrentGraphicsOutputMode->Info, GraphicsOutput->Mode->Info, GraphicsOutput->Mode->SizeOfInfo);\r
+        CurrentGraphicsOutputMode->SizeOfInfo = GraphicsOutput->Mode->SizeOfInfo;\r
+        CurrentGraphicsOutputMode->FrameBufferBase = GraphicsOutput->Mode->FrameBufferBase;\r
+        CurrentGraphicsOutputMode->FrameBufferSize = GraphicsOutput->Mode->FrameBufferSize;\r
+\r
+        //\r
+        // Allocate resource for the private mode buffer\r
+        //\r
+        ModeBuffer = AllocatePool (sizeof (EFI_GRAPHICS_OUTPUT_MODE_INFORMATION) * GraphicsOutput->Mode->MaxMode);\r
+        if (ModeBuffer == NULL) {\r
+          return EFI_OUT_OF_RESOURCES;\r
+        }\r
+        FreePool (Private->GraphicsOutputModeBuffer);\r
+        Private->GraphicsOutputModeBuffer = ModeBuffer;\r
+\r
+        //\r
+        // Store all supported display modes to the private mode buffer\r
+        //\r
+        Mode = ModeBuffer;\r
+        for (Index = 0; Index < GraphicsOutput->Mode->MaxMode; Index++) {\r
+          //\r
+          // The Info buffer would be allocated by callee\r
+          //\r
+          Status = GraphicsOutput->QueryMode (GraphicsOutput, (UINT32) Index, &SizeOfInfo, &Info);\r
+          if (EFI_ERROR (Status)) {\r
+            return Status;\r
+          }\r
+          ASSERT ( SizeOfInfo <= sizeof (EFI_GRAPHICS_OUTPUT_MODE_INFORMATION));\r
+          CopyMem (Mode, Info, SizeOfInfo);\r
+          Mode++;\r
+          FreePool (Info);\r
+        }\r
+    } else {\r
+      //\r
+      // Check intersection of display mode\r
+      //\r
+      ModeBuffer = AllocatePool (sizeof (EFI_GRAPHICS_OUTPUT_MODE_INFORMATION) * CurrentGraphicsOutputMode->MaxMode);\r
+      if (ModeBuffer == NULL) {\r
+        return EFI_OUT_OF_RESOURCES;\r
+      }\r
+\r
+      MatchedMode = ModeBuffer;\r
+      Mode = &Private->GraphicsOutputModeBuffer[0];\r
+      for (Index = 0; Index < CurrentGraphicsOutputMode->MaxMode; Index++) {\r
+        Match = FALSE;\r
+\r
+        for (NumberIndex = 0; NumberIndex < GraphicsOutput->Mode->MaxMode; NumberIndex++) {\r
+          //\r
+          // The Info buffer would be allocated by callee\r
+          //\r
+          Status = GraphicsOutput->QueryMode (GraphicsOutput, (UINT32) NumberIndex, &SizeOfInfo, &Info);\r
+          if (EFI_ERROR (Status)) {\r
+            return Status;\r
+          }\r
+          if ((Info->HorizontalResolution == Mode->HorizontalResolution) &&\r
+              (Info->VerticalResolution == Mode->VerticalResolution)) {\r
+            //\r
+            // If GOP device supports one mode in current mode buffer,\r
+            // it will be added into matched mode buffer\r
+            //\r
+            Match = TRUE;\r
+            FreePool (Info);\r
+            break;\r
+          }\r
+          FreePool (Info);\r
+        }\r
+\r
+        if (Match) {\r
+          AlreadyExist = FALSE;\r
+\r
+          //\r
+          // Check if GOP mode has been in the mode buffer, ModeBuffer = MatchedMode at begin.\r
+          //\r
+          for (Info = ModeBuffer; Info < MatchedMode; Info++) {\r
+            if ((Info->HorizontalResolution == Mode->HorizontalResolution) &&\r
+                (Info->VerticalResolution == Mode->VerticalResolution)) {\r
+              AlreadyExist = TRUE;\r
+              break;\r
+            }\r
+          }\r
+\r
+          if (!AlreadyExist) {\r
+            CopyMem (MatchedMode, Mode, sizeof (EFI_GRAPHICS_OUTPUT_MODE_INFORMATION));\r
+\r
+            //\r
+            // Physical frame buffer is no longer available, change PixelFormat to PixelBltOnly\r
+            //\r
+            MatchedMode->Version = 0;\r
+            MatchedMode->PixelFormat = PixelBltOnly;\r
+            ZeroMem (&MatchedMode->PixelInformation, sizeof (EFI_PIXEL_BITMASK));\r
+\r
+            MatchedMode++;\r
+          }\r
+        }\r
+\r
+        Mode++;\r
+      }\r
+\r
+      //\r
+      // Drop the old mode buffer, assign it to a new one\r
+      //\r
+      FreePool (Private->GraphicsOutputModeBuffer);\r
+      Private->GraphicsOutputModeBuffer = ModeBuffer;\r
+\r
+      //\r
+      // Physical frame buffer is no longer available when there are more than one physical GOP devices\r
+      //\r
+      CurrentGraphicsOutputMode->MaxMode = (UINT32) (((UINTN) MatchedMode - (UINTN) ModeBuffer) / sizeof (EFI_GRAPHICS_OUTPUT_MODE_INFORMATION));\r
+      CurrentGraphicsOutputMode->Info->PixelFormat = PixelBltOnly;\r
+      ZeroMem (&CurrentGraphicsOutputMode->Info->PixelInformation, sizeof (EFI_PIXEL_BITMASK));\r
+      CurrentGraphicsOutputMode->SizeOfInfo = sizeof (EFI_GRAPHICS_OUTPUT_MODE_INFORMATION);\r
+      CurrentGraphicsOutputMode->FrameBufferBase = (EFI_PHYSICAL_ADDRESS) (UINTN) NULL;\r
+      CurrentGraphicsOutputMode->FrameBufferSize = 0;\r
+    }\r
+\r
+    //\r
+    // Graphics console driver can ensure the same mode for all GOP devices\r
+    //\r
+    for (Index = 0; Index < CurrentGraphicsOutputMode->MaxMode; Index++) {\r
+      Mode = &Private->GraphicsOutputModeBuffer[Index];\r
+      if ((Mode->HorizontalResolution == GraphicsOutput->Mode->Info->HorizontalResolution) &&\r
+         (Mode->VerticalResolution == GraphicsOutput->Mode->Info->VerticalResolution)) {\r
+        CurrentIndex = Index;\r
+        break;\r
+      }\r
+    }\r
+    if (Index >= CurrentGraphicsOutputMode->MaxMode) {\r
+      //\r
+      // if user defined mode is not found, set to default mode 800x600\r
+      //\r
+      for (Index = 0; Index < CurrentGraphicsOutputMode->MaxMode; Index++) {\r
+        Mode = &Private->GraphicsOutputModeBuffer[Index];\r
+        if ((Mode->HorizontalResolution == 800) && (Mode->VerticalResolution == 600)) {\r
+          CurrentIndex = Index;\r
+          break;\r
+        }\r
+      }\r
+    }\r
+  } else if (UgaDraw != NULL) {\r
+    //\r
+    // Graphics console driver can ensure the same mode for all GOP devices\r
+    // so we can get the current mode from this video device\r
+    //\r
+    UgaDraw->GetMode (\r
+               UgaDraw,\r
+               &UgaHorizontalResolution,\r
+               &UgaVerticalResolution,\r
+               &UgaColorDepth,\r
+               &UgaRefreshRate\r
+               );\r
+\r
+    CurrentGraphicsOutputMode->MaxMode = 1;\r
+    Info = CurrentGraphicsOutputMode->Info;\r
+    Info->Version = 0;\r
+    Info->HorizontalResolution                 = UgaHorizontalResolution;\r
+    Info->VerticalResolution                   = UgaVerticalResolution;\r
+    Info->PixelFormat                          = PixelBltOnly;\r
+    Info->PixelsPerScanLine                    = UgaHorizontalResolution;\r
+    CurrentGraphicsOutputMode->SizeOfInfo      = sizeof (EFI_GRAPHICS_OUTPUT_MODE_INFORMATION);\r
+    CurrentGraphicsOutputMode->FrameBufferBase = (EFI_PHYSICAL_ADDRESS) (UINTN) NULL;\r
+    CurrentGraphicsOutputMode->FrameBufferSize = 0;\r
+\r
+    //\r
+    // Update the private mode buffer\r
+    //\r
+    CopyMem (&Private->GraphicsOutputModeBuffer[0], Info, sizeof (EFI_GRAPHICS_OUTPUT_MODE_INFORMATION));\r
+\r
+    //\r
+    // Only mode 0 is available to be set\r
+    //\r
+    CurrentIndex = 0;\r
+  }\r
+\r
+Done:\r
+\r
+  if (GraphicsOutput != NULL) {\r
+    Private->CurrentNumberOfGraphicsOutput++;\r
+  }\r
+  if (UgaDraw != NULL) {\r
+    Private->CurrentNumberOfUgaDraw++;\r
+  }\r
+\r
+  //\r
+  // Force GraphicsOutput mode to be set,\r
+  //\r
+  \r
+  Mode = &Private->GraphicsOutputModeBuffer[CurrentIndex];\r
+  if ((GraphicsOutput != NULL) &&\r
+      (Mode->HorizontalResolution == CurrentGraphicsOutputMode->Info->HorizontalResolution) &&\r
+      (Mode->VerticalResolution == CurrentGraphicsOutputMode->Info->VerticalResolution)) {\r
+    CurrentGraphicsOutputMode->Mode = (UINT32) CurrentIndex;\r
+    if ((Mode->HorizontalResolution != GraphicsOutput->Mode->Info->HorizontalResolution) ||\r
+        (Mode->VerticalResolution != GraphicsOutput->Mode->Info->VerticalResolution)) {\r
+      //\r
+      // If all existing video device has been set to common mode, only set new GOP device to\r
+      // the common mode\r
+      //\r
+      for (NumberIndex = 0; NumberIndex < GraphicsOutput->Mode->MaxMode; NumberIndex ++) {\r
+        Status = GraphicsOutput->QueryMode (GraphicsOutput, (UINT32) NumberIndex, &SizeOfInfo, &Info);\r
+        if (EFI_ERROR (Status)) {\r
+          return Status;\r
+        }\r
+        if ((Info->HorizontalResolution == Mode->HorizontalResolution) && (Info->VerticalResolution == Mode->VerticalResolution)) {\r
+          FreePool (Info);\r
+          break;\r
+        }\r
+        FreePool (Info);\r
+      }\r
+      Status = GraphicsOutput->SetMode (GraphicsOutput, (UINT32) NumberIndex);\r
+    }\r
+  } else {\r
+    //\r
+    // Current mode number may need update now, so set it to an invalid mode number\r
+    //\r
+    CurrentGraphicsOutputMode->Mode = 0xffff;\r
+    //\r
+    // Graphics console can ensure all GOP devices have the same mode which can be taken as current mode.\r
+    //\r
+    Status = Private->GraphicsOutput.SetMode (&Private->GraphicsOutput, (UINT32) CurrentIndex);\r
+    if (EFI_ERROR(Status)) {\r
+      //\r
+      // If user defined mode is not valid for display device, set to the default mode 800x600.\r
+      //\r
+      (Private->GraphicsOutputModeBuffer[0]).HorizontalResolution = 800;\r
+      (Private->GraphicsOutputModeBuffer[0]).VerticalResolution   = 600;\r
+      Status = Private->GraphicsOutput.SetMode (&Private->GraphicsOutput, 0);\r
+    }\r
+  }\r
+\r
+  return Status;\r
+}\r
+\r
+/**\r
+  Set the current console out mode.\r
+\r
+  This routine will get the current console mode information (column, row)\r
+  from ConsoleOutMode variable and set it; if the variable does not exist,\r
+  set to user defined console mode.\r
+\r
+  @param  Private            Consplitter Text Out pointer.\r
+\r
+**/\r
+VOID\r
+ConsplitterSetConsoleOutMode (\r
+  IN  TEXT_OUT_SPLITTER_PRIVATE_DATA  *Private\r
+  )\r
+{\r
+  UINTN                            Col;\r
+  UINTN                            Row;\r
+  UINTN                            Mode;\r
+  UINTN                            PreferMode;\r
+  UINTN                            BaseMode;\r
+  UINTN                            MaxMode;\r
+  EFI_STATUS                       Status;\r
+  CONSOLE_OUT_MODE                 ModeInfo;\r
+  CONSOLE_OUT_MODE                 MaxModeInfo;\r
+  EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL  *TextOut;\r
+\r
+  PreferMode   = 0xFF;\r
+  BaseMode     = 0xFF;\r
+  TextOut      = &Private->TextOut;\r
+  MaxMode      = (UINTN) (TextOut->Mode->MaxMode);\r
+\r
+  MaxModeInfo.Column = 0;\r
+  MaxModeInfo.Row    = 0; \r
+  ModeInfo.Column    = PcdGet32 (PcdConOutColumn);\r
+  ModeInfo.Row       = PcdGet32 (PcdConOutRow);\r
+\r
+  //\r
+  // To find the prefer mode and basic mode from Text Out mode list\r
+  //\r
+  for (Mode = 0; Mode < MaxMode; Mode++) {\r
+    Status = TextOut->QueryMode (TextOut, Mode, &Col, &Row);\r
+    if (!EFI_ERROR(Status)) {\r
+      if ((ModeInfo.Column != 0) && (ModeInfo.Row != 0)) {\r
+        //\r
+        // Use user defined column and row\r
+        //\r
+        if (Col == ModeInfo.Column && Row == ModeInfo.Row) {\r
+          PreferMode = Mode;\r
+        }\r
+      } else {\r
+        //\r
+        // If user sets PcdConOutColumn or PcdConOutRow to 0,\r
+        // find and set the highest text mode.\r
+        //\r
+        if ((Col >= MaxModeInfo.Column) && (Row >= MaxModeInfo.Row)) {\r
+          MaxModeInfo.Column  = Col;\r
+          MaxModeInfo.Row     = Row;\r
+          PreferMode          = Mode;\r
+        }\r
+      }\r
+      if (Col == 80 && Row == 25) {\r
+        BaseMode = Mode;\r
+      }\r
+    }\r
+  }\r
+\r
+  //\r
+  // Set prefer mode to Text Out devices.\r
+  //\r
+  Status = TextOut->SetMode (TextOut, PreferMode);\r
+  if (EFI_ERROR(Status)) {\r
+    //\r
+    // if current mode setting is failed, default 80x25 mode will be set.\r
+    //\r
+    Status = TextOut->SetMode (TextOut, BaseMode);\r
+    ASSERT(!EFI_ERROR(Status));\r
+\r
+    PcdSet32 (PcdConOutColumn, 80);\r
+    PcdSet32 (PcdConOutRow, 25);\r
+  }\r
+\r
+  return ;\r
+}\r
+\r
+\r
+/**\r
+  Add Text Output Device in Consplitter Text Output list.\r
+\r
+  @param  Private                  Text Out Splitter pointer.\r
+  @param  TextOut                  Simple Text Output protocol pointer.\r
+  @param  GraphicsOutput           Graphics Output protocol pointer.\r
+  @param  UgaDraw                  UGA Draw protocol pointer.\r
+\r
+  @retval EFI_SUCCESS              Text Output Device added successfully.\r
+  @retval EFI_OUT_OF_RESOURCES     Could not grow the buffer size.\r
+\r
+**/\r
+EFI_STATUS\r
+ConSplitterTextOutAddDevice (\r
+  IN  TEXT_OUT_SPLITTER_PRIVATE_DATA     *Private,\r
+  IN  EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL    *TextOut,\r
+  IN  EFI_GRAPHICS_OUTPUT_PROTOCOL       *GraphicsOutput,\r
+  IN  EFI_UGA_DRAW_PROTOCOL              *UgaDraw\r
+  )\r
+{\r
+  EFI_STATUS                           Status;\r
+  UINTN                                CurrentNumOfConsoles;\r
+  INT32                                MaxMode;\r
+  UINT32                               UgaHorizontalResolution;\r
+  UINT32                               UgaVerticalResolution;\r
+  UINT32                               UgaColorDepth;\r
+  UINT32                               UgaRefreshRate;\r
+  TEXT_OUT_AND_GOP_DATA                *TextAndGop;\r
+  UINTN                                SizeOfInfo;\r
+  EFI_GRAPHICS_OUTPUT_MODE_INFORMATION *Info;\r
+  EFI_STATUS                           DeviceStatus;\r
+\r
+  Status                = EFI_SUCCESS;\r
+  CurrentNumOfConsoles  = Private->CurrentNumberOfConsoles;\r
+\r
+  //\r
+  // If the Text Out List is full, enlarge it by calling ConSplitterGrowBuffer().\r
+  //\r
+  while (CurrentNumOfConsoles >= Private->TextOutListCount) {\r
+    Status = ConSplitterGrowBuffer (\r
+              sizeof (TEXT_OUT_AND_GOP_DATA),\r
+              &Private->TextOutListCount,\r
+              (VOID **) &Private->TextOutList\r
+              );\r
+    if (EFI_ERROR (Status)) {\r
+      return EFI_OUT_OF_RESOURCES;\r
+    }\r
+    //\r
+    // Also need to reallocate the TextOutModeMap table\r
+    //\r
+    Status = ConSplitterGrowMapTable (Private);\r
+    if (EFI_ERROR (Status)) {\r
+      return EFI_OUT_OF_RESOURCES;\r
+    }\r
+  }\r
+\r
+  TextAndGop          = &Private->TextOutList[CurrentNumOfConsoles];\r
+\r
+  TextAndGop->TextOut        = TextOut;\r
+  TextAndGop->GraphicsOutput = GraphicsOutput;\r
+  TextAndGop->UgaDraw        = UgaDraw;\r
+\r
+  if (CurrentNumOfConsoles == 0) {\r
+    //\r
+    // Add the first device's output mode to console splitter's mode list\r
+    //\r
+    Status = ConSplitterAddOutputMode (Private, TextOut);\r
+  } else {\r
+    ConSplitterSyncOutputMode (Private, TextOut);\r
+  }\r
+\r
+  Private->CurrentNumberOfConsoles++;\r
+\r
+  //\r
+  // Scan both TextOutList, for the intersection TextOut device\r
+  // maybe both ConOut and StdErr incorporate the same Text Out\r
+  // device in them, thus the output of both should be synced.\r
+  //\r
+  ConSplitterGetIntersectionBetweenConOutAndStrErr ();\r
+\r
+  MaxMode     = Private->TextOutMode.MaxMode;\r
+  ASSERT (MaxMode >= 1);\r
+\r
+  DeviceStatus = EFI_DEVICE_ERROR;\r
+  Status       = EFI_DEVICE_ERROR;\r
+  \r
+  //\r
+  // This device display mode will be added into Graphics Ouput modes.\r
+  //\r
+  if ((GraphicsOutput != NULL) || (UgaDraw != NULL)) {\r
+    DeviceStatus = ConSplitterAddGraphicsOutputMode (Private, GraphicsOutput, UgaDraw);\r
+  }\r
+\r
+  if (FeaturePcdGet (PcdConOutUgaSupport)) {\r
+    //\r
+    // If UGA is produced by Consplitter\r
+    //\r
+    if (GraphicsOutput != NULL) {\r
+      Status = GraphicsOutput->QueryMode (GraphicsOutput, GraphicsOutput->Mode->Mode, &SizeOfInfo, &Info);\r
+      if (EFI_ERROR (Status)) {\r
+        return Status;\r
+      }\r
+      ASSERT ( SizeOfInfo <= sizeof (EFI_GRAPHICS_OUTPUT_MODE_INFORMATION));\r
+\r
+      UgaHorizontalResolution = Info->HorizontalResolution;\r
+      UgaVerticalResolution   = Info->VerticalResolution;\r
+\r
+      FreePool (Info);\r
+\r
+    } else if (UgaDraw != NULL) {\r
+      Status = UgaDraw->GetMode (\r
+                    UgaDraw,\r
+                    &UgaHorizontalResolution,\r
+                    &UgaVerticalResolution,\r
+                    &UgaColorDepth,\r
+                    &UgaRefreshRate\r
+                    );\r
+      if (!EFI_ERROR (Status) && EFI_ERROR (DeviceStatus)) {\r
+        //\r
+        // if GetMode is successfully and UGA device hasn't been set, set it\r
+        //\r
+        Status = ConSplitterUgaDrawSetMode (\r
+                    &Private->UgaDraw,\r
+                    UgaHorizontalResolution,\r
+                    UgaVerticalResolution,\r
+                    UgaColorDepth,\r
+                    UgaRefreshRate\r
+                    );\r
+      }\r
+      //\r
+      // If GetMode/SetMode is failed, set to 800x600 mode\r
+      //\r
+      if(EFI_ERROR (Status)) {\r
+        Status = ConSplitterUgaDrawSetMode (\r
+                    &Private->UgaDraw,\r
+                    800,\r
+                    600,\r
+                    32,\r
+                    60\r
+                    );\r
+      }\r
+    }\r
+  }\r
+\r
+  if (((!EFI_ERROR (DeviceStatus)) || (!EFI_ERROR (Status))) &&\r
+      ((Private->CurrentNumberOfGraphicsOutput + Private->CurrentNumberOfUgaDraw) == 1)) {\r
+    if (!FeaturePcdGet (PcdConOutGopSupport)) {\r
+      //\r
+      // If Graphics Outpurt protocol not supported, UGA Draw protocol is installed\r
+      // on the virtual handle.\r
+      //\r
+      Status = gBS->InstallMultipleProtocolInterfaces (\r
+                      &mConOut.VirtualHandle,\r
+                      &gEfiUgaDrawProtocolGuid,\r
+                      &mConOut.UgaDraw,\r
+                      NULL\r
+                      );\r
+    } else if (!FeaturePcdGet (PcdConOutUgaSupport)) {\r
+      //\r
+      // If UGA Draw protocol not supported, Graphics Output Protocol is installed\r
+      // on virtual handle.\r
+      //\r
+      Status = gBS->InstallMultipleProtocolInterfaces (\r
+                      &mConOut.VirtualHandle,\r
+                      &gEfiGraphicsOutputProtocolGuid,\r
+                      &mConOut.GraphicsOutput,\r
+                      NULL\r
+                      );\r
+    } else {\r
+      //\r
+      // Boot Graphics Output protocol and UGA Draw protocol are supported,\r
+      // both they will be installed on virtual handle.\r
+      //\r
+      Status = gBS->InstallMultipleProtocolInterfaces (\r
+                      &mConOut.VirtualHandle,\r
+                      &gEfiGraphicsOutputProtocolGuid,\r
+                      &mConOut.GraphicsOutput,\r
+                      &gEfiUgaDrawProtocolGuid,\r
+                      &mConOut.UgaDraw,\r
+                      NULL\r
+                      );\r
+    }\r
+  }\r
+\r
+  //\r
+  // After adding new console device, all existing console devices should be\r
+  // synced to the current shared mode.\r
+  //\r
+  ConsplitterSetConsoleOutMode (Private);\r
+\r
+  return Status;\r
+}\r
+\r
+\r
+/**\r
+  Remove Text Out Device in Consplitter Text Out list.\r
+\r
+  @param  Private                  Text Out Splitter pointer.\r
+  @param  TextOut                  Simple Text Output Pointer protocol pointer.\r
+\r
+  @retval EFI_SUCCESS              Text Out Device removed successfully.\r
+  @retval EFI_NOT_FOUND            No Text Out Device found.\r
+\r
+**/\r
+EFI_STATUS\r
+ConSplitterTextOutDeleteDevice (\r
+  IN  TEXT_OUT_SPLITTER_PRIVATE_DATA     *Private,\r
+  IN  EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL    *TextOut\r
+  )\r
+{\r
+  INT32                 Index;\r
+  UINTN                 CurrentNumOfConsoles;\r
+  TEXT_OUT_AND_GOP_DATA *TextOutList;\r
+  EFI_STATUS            Status;\r
+\r
+  //\r
+  // Remove the specified text-out device data structure from the Text out List,\r
+  // and rearrange the remaining data structures in the Text out List.\r
+  //\r
+  CurrentNumOfConsoles  = Private->CurrentNumberOfConsoles;\r
+  Index                 = (INT32) CurrentNumOfConsoles - 1;\r
+  TextOutList           = Private->TextOutList;\r
+  while (Index >= 0) {\r
+    if (TextOutList->TextOut == TextOut) {\r
+      if (TextOutList->UgaDraw != NULL) {\r
+        Private->CurrentNumberOfUgaDraw--;\r
+      }\r
+      if (TextOutList->GraphicsOutput != NULL) {\r
+        Private->CurrentNumberOfGraphicsOutput--;\r
+      }\r
+      CopyMem (TextOutList, TextOutList + 1, sizeof (TEXT_OUT_AND_GOP_DATA) * Index);\r
+      CurrentNumOfConsoles--;\r
+      break;\r
+    }\r
+\r
+    Index--;\r
+    TextOutList++;\r
+  }\r
+  //\r
+  // The specified TextOut is not managed by the ConSplitter driver\r
+  //\r
+  if (Index < 0) {\r
+    return EFI_NOT_FOUND;\r
+  }\r
+\r
+  if ((Private->CurrentNumberOfGraphicsOutput == 0) && (Private->CurrentNumberOfUgaDraw == 0)) {\r
+    //\r
+    // If there is not any physical GOP and UGA device in system,\r
+    // Consplitter GOP or UGA protocol will be uninstalled\r
+    //\r
+    if (!FeaturePcdGet (PcdConOutGopSupport)) {\r
+      Status = gBS->UninstallProtocolInterface (\r
+                      Private->VirtualHandle,\r
+                      &gEfiUgaDrawProtocolGuid,\r
+                      &Private->UgaDraw\r
+                      );      \r
+    } else if (!FeaturePcdGet (PcdConOutUgaSupport)) {\r
+      Status = gBS->UninstallProtocolInterface (\r
+                      Private->VirtualHandle,\r
+                      &gEfiGraphicsOutputProtocolGuid,\r
+                      &Private->GraphicsOutput\r
+                      );\r
+    } else {\r
+      Status = gBS->UninstallMultipleProtocolInterfaces (\r
+             Private->VirtualHandle,\r
+             &gEfiUgaDrawProtocolGuid,\r
+             &Private->UgaDraw,\r
+             &gEfiGraphicsOutputProtocolGuid,\r
+             &Private->GraphicsOutput,\r
+             NULL\r
+             );\r
+    }\r
+  }\r
+\r
+  if (CurrentNumOfConsoles == 0) {\r
+    //\r
+    // If the number of consoles is zero, reset all parameters\r
+    //\r
+    Private->CurrentNumberOfConsoles      = 0;\r
+    Private->TextOutMode.MaxMode          = 1;\r
+    Private->TextOutQueryData[0].Columns  = 80;\r
+    Private->TextOutQueryData[0].Rows     = 25;\r
+    TextOutSetMode (Private, 0);\r
+\r
+    return EFI_SUCCESS;\r
+  }\r
+  //\r
+  // Max Mode is realy an intersection of the QueryMode command to all\r
+  // devices. So we must copy the QueryMode of the first device to\r
+  // QueryData.\r
+  //\r
+  ZeroMem (\r
+    Private->TextOutQueryData,\r
+    Private->TextOutQueryDataCount * sizeof (TEXT_OUT_SPLITTER_QUERY_DATA)\r
+    );\r
+\r
+  FreePool (Private->TextOutModeMap);\r
+  Private->TextOutModeMap = NULL;\r
+  TextOutList             = Private->TextOutList;\r
+\r
+  //\r
+  // Add the first TextOut to the QueryData array and ModeMap table\r
+  //\r
+  Status = ConSplitterAddOutputMode (Private, TextOutList->TextOut);\r
+\r
+  //\r
+  // Now add one by one\r
+  //\r
+  Index = 1;\r
+  Private->CurrentNumberOfConsoles = 1;\r
+  TextOutList++;\r
+  while ((UINTN) Index < CurrentNumOfConsoles) {\r
+    ConSplitterSyncOutputMode (Private, TextOutList->TextOut);\r
+    Index++;\r
+    Private->CurrentNumberOfConsoles++;\r
+    TextOutList++;\r
+  }\r
+\r
+  ConSplitterGetIntersectionBetweenConOutAndStrErr ();\r
+\r
+  return Status;\r
+}\r
+\r
+\r
+/**\r
+  Reset the input device and optionaly run diagnostics\r
+\r
+  @param  This                     Protocol instance pointer.\r
+  @param  ExtendedVerification     Driver may perform diagnostics on reset.\r
+\r
+  @retval EFI_SUCCESS              The device was reset.\r
+  @retval EFI_DEVICE_ERROR         The device is not functioning properly and could\r
+                                   not be reset.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+ConSplitterTextInReset (\r
+  IN  EFI_SIMPLE_TEXT_INPUT_PROTOCOL  *This,\r
+  IN  BOOLEAN                         ExtendedVerification\r
+  )\r
+{\r
+  EFI_STATUS                    Status;\r
+  EFI_STATUS                    ReturnStatus;\r
+  TEXT_IN_SPLITTER_PRIVATE_DATA *Private;\r
+  UINTN                         Index;\r
+\r
+  Private                       = TEXT_IN_SPLITTER_PRIVATE_DATA_FROM_THIS (This);\r
+\r
+  Private->KeyEventSignalState  = FALSE;\r
+\r
+  //\r
+  // return the worst status met\r
+  //\r
+  for (Index = 0, ReturnStatus = EFI_SUCCESS; Index < Private->CurrentNumberOfConsoles; Index++) {\r
+    Status = Private->TextInList[Index]->Reset (\r
+                                          Private->TextInList[Index],\r
+                                          ExtendedVerification\r
+                                          );\r
+    if (EFI_ERROR (Status)) {\r
+      ReturnStatus = Status;\r
+    }\r
+  }\r
+\r
+  return ReturnStatus;\r
+}\r
+\r
+\r
+/**\r
+  Reads the next keystroke from the input device. The WaitForKey Event can\r
+  be used to test for existance of a keystroke via WaitForEvent () call.\r
+\r
+  @param  Private                  Protocol instance pointer.\r
+  @param  Key                      Driver may perform diagnostics on reset.\r
+\r
+  @retval EFI_SUCCESS              The keystroke information was returned.\r
+  @retval EFI_NOT_READY            There was no keystroke data availiable.\r
+  @retval EFI_DEVICE_ERROR         The keydtroke information was not returned due\r
+                                   to hardware errors.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+ConSplitterTextInPrivateReadKeyStroke (\r
+  IN  TEXT_IN_SPLITTER_PRIVATE_DATA   *Private,\r
+  OUT EFI_INPUT_KEY                   *Key\r
+  )\r
+{\r
+  EFI_STATUS    Status;\r
+  UINTN         Index;\r
+  EFI_INPUT_KEY CurrentKey;\r
+\r
+  Key->UnicodeChar  = 0;\r
+  Key->ScanCode     = SCAN_NULL;\r
+\r
+  //\r
+  // if no physical console input device exists, return EFI_NOT_READY;\r
+  // if any physical console input device has key input,\r
+  // return the key and EFI_SUCCESS.\r
+  //\r
+  for (Index = 0; Index < Private->CurrentNumberOfConsoles; Index++) {\r
+    Status = Private->TextInList[Index]->ReadKeyStroke (\r
+                                          Private->TextInList[Index],\r
+                                          &CurrentKey\r
+                                          );\r
+    if (!EFI_ERROR (Status)) {\r
+      *Key = CurrentKey;\r
+      return Status;\r
+    }\r
+  }\r
+\r
+  return EFI_NOT_READY;\r
+}\r
+\r
+\r
+\r
+/**\r
+  Reads the next keystroke from the input device. The WaitForKey Event can\r
+  be used to test for existance of a keystroke via WaitForEvent () call.\r
+\r
+  @param  This                     Protocol instance pointer.\r
+  @param  Key                      Driver may perform diagnostics on reset.\r
+\r
+  @retval EFI_SUCCESS              The keystroke information was returned.\r
+  @retval EFI_NOT_READY            There was no keystroke data availiable.\r
+  @retval EFI_DEVICE_ERROR         The keydtroke information was not returned due\r
+                                   to hardware errors.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+ConSplitterTextInReadKeyStroke (\r
+  IN  EFI_SIMPLE_TEXT_INPUT_PROTOCOL  *This,\r
+  OUT EFI_INPUT_KEY                   *Key\r
+  )\r
+{\r
+  TEXT_IN_SPLITTER_PRIVATE_DATA *Private;\r
+\r
+  Private = TEXT_IN_SPLITTER_PRIVATE_DATA_FROM_THIS (This);\r
+\r
+  Private->KeyEventSignalState = FALSE;\r
+\r
+  //\r
+  // Signal ConnectConIn event on first call in Lazy ConIn mode\r
+  //\r
+  if (!mConInIsConnect && PcdGetBool (PcdConInConnectOnDemand)) {\r
+    DEBUG ((EFI_D_INFO, "Connect ConIn in first ReadKeyStoke in Lazy ConIn mode.\n"));    \r
+    gBS->SignalEvent (Private->ConnectConInEvent);\r
+    mConInIsConnect = TRUE;\r
+  }\r
+\r
+  return ConSplitterTextInPrivateReadKeyStroke (Private, Key);\r
+}\r
+\r
+\r
+/**\r
+  This event aggregates all the events of the ConIn devices in the spliter.\r
+\r
+  If any events of physical ConIn devices are signaled, signal the ConIn\r
+  spliter event. This will cause the calling code to call\r
+  ConSplitterTextInReadKeyStroke ().\r
+\r
+  @param  Event                    The Event assoicated with callback.\r
+  @param  Context                  Context registered when Event was created.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+ConSplitterTextInWaitForKey (\r
+  IN  EFI_EVENT                       Event,\r
+  IN  VOID                            *Context\r
+  )\r
+{\r
+  EFI_STATUS                    Status;\r
+  TEXT_IN_SPLITTER_PRIVATE_DATA *Private;\r
+  UINTN                         Index;\r
+\r
+  Private = (TEXT_IN_SPLITTER_PRIVATE_DATA *) Context;\r
+\r
+  if (Private->KeyEventSignalState) {\r
+    //\r
+    // If KeyEventSignalState is flagged before, and not cleared by Reset() or ReadKeyStroke()\r
+    //\r
+    gBS->SignalEvent (Event);\r
+    return ;\r
+  }\r
+\r
+  //\r
+  // If any physical console input device has key input, signal the event.\r
+  //\r
+  for (Index = 0; Index < Private->CurrentNumberOfConsoles; Index++) {\r
+    Status = gBS->CheckEvent (Private->TextInList[Index]->WaitForKey);\r
+    if (!EFI_ERROR (Status)) {\r
+      gBS->SignalEvent (Event);\r
+      Private->KeyEventSignalState = TRUE;\r
+    }\r
+  }\r
+}\r
+\r
+\r
+\r
+/**\r
+  Test if the key has been registered on input device.\r
+\r
+  @param  RegsiteredData           A pointer to a buffer that is filled in with the\r
+                                   keystroke state data for the key that was\r
+                                   registered.\r
+  @param  InputData                A pointer to a buffer that is filled in with the\r
+                                   keystroke state data for the key that was\r
+                                   pressed.\r
+\r
+  @retval TRUE                     Key be pressed matches a registered key.\r
+  @retval FLASE                    Match failed.\r
+\r
+**/\r
+BOOLEAN\r
+IsKeyRegistered (\r
+  IN EFI_KEY_DATA  *RegsiteredData,\r
+  IN EFI_KEY_DATA  *InputData\r
+  )\r
+{\r
+  ASSERT (RegsiteredData != NULL && InputData != NULL);\r
+\r
+  if ((RegsiteredData->Key.ScanCode    != InputData->Key.ScanCode) ||\r
+      (RegsiteredData->Key.UnicodeChar != InputData->Key.UnicodeChar)) {\r
+    return FALSE;\r
+  }\r
+\r
+  //\r
+  // Assume KeyShiftState/KeyToggleState = 0 in Registered key data means these state could be ignored.\r
+  //\r
+  if (RegsiteredData->KeyState.KeyShiftState != 0 &&\r
+      RegsiteredData->KeyState.KeyShiftState != InputData->KeyState.KeyShiftState) {\r
+    return FALSE;\r
+  }\r
+  if (RegsiteredData->KeyState.KeyToggleState != 0 &&\r
+      RegsiteredData->KeyState.KeyToggleState != InputData->KeyState.KeyToggleState) {\r
+    return FALSE;\r
+  }\r
+\r
+  return TRUE;\r
+\r
+}\r
+\r
+\r
+/**\r
+  Reset the input device and optionaly run diagnostics\r
+\r
+  @param  This                     Protocol instance pointer.\r
+  @param  ExtendedVerification     Driver may perform diagnostics on reset.\r
+\r
+  @retval EFI_SUCCESS              The device was reset.\r
+  @retval EFI_DEVICE_ERROR         The device is not functioning properly and could\r
+                                   not be reset.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+ConSplitterTextInResetEx (\r
+  IN EFI_SIMPLE_TEXT_INPUT_EX_PROTOCOL  *This,\r
+  IN BOOLEAN                            ExtendedVerification\r
+  )\r
+{\r
+  EFI_STATUS                    Status;\r
+  EFI_STATUS                    ReturnStatus;\r
+  TEXT_IN_SPLITTER_PRIVATE_DATA *Private;\r
+  UINTN                         Index;\r
+\r
+  Private                       = TEXT_IN_EX_SPLITTER_PRIVATE_DATA_FROM_THIS (This);\r
+\r
+  Private->KeyEventSignalState  = FALSE;\r
+\r
+  //\r
+  // return the worst status met\r
+  //\r
+  for (Index = 0, ReturnStatus = EFI_SUCCESS; Index < Private->CurrentNumberOfExConsoles; Index++) {\r
+    Status = Private->TextInExList[Index]->Reset (\r
+                                             Private->TextInExList[Index],\r
+                                             ExtendedVerification\r
+                                             );\r
+    if (EFI_ERROR (Status)) {\r
+      ReturnStatus = Status;\r
+    }\r
+  }\r
+\r
+  return ReturnStatus;\r
+\r
+}\r
+\r
+\r
+/**\r
+  Reads the next keystroke from the input device. The WaitForKey Event can\r
+  be used to test for existance of a keystroke via WaitForEvent () call.\r
+\r
+  @param  This                     Protocol instance pointer.\r
+  @param  KeyData                  A pointer to a buffer that is filled in with the\r
+                                   keystroke state data for the key that was\r
+                                   pressed.\r
+\r
+  @retval EFI_SUCCESS              The keystroke information was returned.\r
+  @retval EFI_NOT_READY            There was no keystroke data availiable.\r
+  @retval EFI_DEVICE_ERROR         The keystroke information was not returned due\r
+                                   to hardware errors.\r
+  @retval EFI_INVALID_PARAMETER    KeyData is NULL.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+ConSplitterTextInReadKeyStrokeEx (\r
+  IN  EFI_SIMPLE_TEXT_INPUT_EX_PROTOCOL *This,\r
+  OUT EFI_KEY_DATA                      *KeyData\r
+  )\r
+{\r
+  TEXT_IN_SPLITTER_PRIVATE_DATA *Private;\r
+  EFI_STATUS                    Status;\r
+  UINTN                         Index;\r
+  EFI_KEY_DATA                  CurrentKeyData;\r
+\r
+\r
+  if (KeyData == NULL) {\r
+    return EFI_INVALID_PARAMETER;\r
+  }\r
+\r
+  Private = TEXT_IN_EX_SPLITTER_PRIVATE_DATA_FROM_THIS (This);\r
+\r
+  Private->KeyEventSignalState = FALSE;\r
+\r
+  KeyData->Key.UnicodeChar  = 0;\r
+  KeyData->Key.ScanCode     = SCAN_NULL;\r
+\r
+  //\r
+  // Signal ConnectConIn event on first call in Lazy ConIn mode\r
+  //\r
+  if (!mConInIsConnect && PcdGetBool (PcdConInConnectOnDemand)) {\r
+    DEBUG ((EFI_D_INFO, "Connect ConIn in first ReadKeyStoke in Lazy ConIn mode.\n"));    \r
+    gBS->SignalEvent (Private->ConnectConInEvent);\r
+    mConInIsConnect = TRUE;\r
+  }\r
+\r
+  //\r
+  // if no physical console input device exists, return EFI_NOT_READY;\r
+  // if any physical console input device has key input,\r
+  // return the key and EFI_SUCCESS.\r
+  //\r
+  for (Index = 0; Index < Private->CurrentNumberOfExConsoles; Index++) {\r
+    Status = Private->TextInExList[Index]->ReadKeyStrokeEx (\r
+                                          Private->TextInExList[Index],\r
+                                          &CurrentKeyData\r
+                                          );\r
+    if (!EFI_ERROR (Status)) {\r
+      CopyMem (KeyData, &CurrentKeyData, sizeof (CurrentKeyData));\r
+      return Status;\r
+    }\r
+  }\r
+\r
+  return EFI_NOT_READY;\r
+}\r
+\r
+\r
+/**\r
+  Set certain state for the input device.\r
+\r
+  @param  This                     Protocol instance pointer.\r
+  @param  KeyToggleState           A pointer to the EFI_KEY_TOGGLE_STATE to set the\r
+                                   state for the input device.\r
+\r
+  @retval EFI_SUCCESS              The device state was set successfully.\r
+  @retval EFI_DEVICE_ERROR         The device is not functioning correctly and\r
+                                   could not have the setting adjusted.\r
+  @retval EFI_UNSUPPORTED          The device does not have the ability to set its\r
+                                   state.\r
+  @retval EFI_INVALID_PARAMETER    KeyToggleState is NULL.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+ConSplitterTextInSetState (\r
+  IN EFI_SIMPLE_TEXT_INPUT_EX_PROTOCOL  *This,\r
+  IN EFI_KEY_TOGGLE_STATE               *KeyToggleState\r
+  )\r
+{\r
+  TEXT_IN_SPLITTER_PRIVATE_DATA *Private;\r
+  EFI_STATUS                    Status;\r
+  UINTN                         Index;\r
+\r
+  if (KeyToggleState == NULL) {\r
+    return EFI_INVALID_PARAMETER;\r
+  }\r
+\r
+  Private = TEXT_IN_EX_SPLITTER_PRIVATE_DATA_FROM_THIS (This);\r
+\r
+  //\r
+  // if no physical console input device exists, return EFI_SUCCESS;\r
+  // otherwise return the status of setting state of physical console input device\r
+  //\r
+  for (Index = 0; Index < Private->CurrentNumberOfExConsoles; Index++) {\r
+    Status = Private->TextInExList[Index]->SetState (\r
+                                             Private->TextInExList[Index],\r
+                                             KeyToggleState\r
+                                             );\r
+    if (EFI_ERROR (Status)) {\r
+      return Status;\r
+    }\r
+  }\r
+\r
+  return EFI_SUCCESS;\r
+\r
+}\r
+\r
+\r
+/**\r
+  Register a notification function for a particular keystroke for the input device.\r
+\r
+  @param  This                     Protocol instance pointer.\r
+  @param  KeyData                  A pointer to a buffer that is filled in with the\r
+                                   keystroke information data for the key that was\r
+                                   pressed.\r
+  @param  KeyNotificationFunction  Points to the function to be called when the key\r
+                                   sequence is typed specified by KeyData.\r
+  @param  NotifyHandle             Points to the unique handle assigned to the\r
+                                   registered notification.\r
+\r
+  @retval EFI_SUCCESS              The notification function was registered\r
+                                   successfully.\r
+  @retval EFI_OUT_OF_RESOURCES     Unable to allocate resources for necesssary data\r
+                                   structures.\r
+  @retval EFI_INVALID_PARAMETER    KeyData or KeyNotificationFunction or NotifyHandle is NULL.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+ConSplitterTextInRegisterKeyNotify (\r
+  IN EFI_SIMPLE_TEXT_INPUT_EX_PROTOCOL  *This,\r
+  IN EFI_KEY_DATA                       *KeyData,\r
+  IN EFI_KEY_NOTIFY_FUNCTION            KeyNotificationFunction,\r
+  OUT VOID                              **NotifyHandle\r
+  )\r
+{\r
+  TEXT_IN_SPLITTER_PRIVATE_DATA *Private;\r
+  EFI_STATUS                    Status;\r
+  UINTN                         Index;\r
+  TEXT_IN_EX_SPLITTER_NOTIFY    *NewNotify;\r
+  LIST_ENTRY                    *Link;\r
+  TEXT_IN_EX_SPLITTER_NOTIFY    *CurrentNotify;\r
+\r
+\r
+  if (KeyData == NULL || NotifyHandle == NULL || KeyNotificationFunction == NULL) {\r
+    return EFI_INVALID_PARAMETER;\r
+  }\r
+\r
+  Private = TEXT_IN_EX_SPLITTER_PRIVATE_DATA_FROM_THIS (This);\r
+\r
+  //\r
+  // Return EFI_SUCCESS if the (KeyData, NotificationFunction) is already registered.\r
+  //\r
+  for (Link = Private->NotifyList.ForwardLink; Link != &Private->NotifyList; Link = Link->ForwardLink) {\r
+    CurrentNotify = TEXT_IN_EX_SPLITTER_NOTIFY_FROM_THIS (Link);\r
+    if (IsKeyRegistered (&CurrentNotify->KeyData, KeyData)) {\r
+      if (CurrentNotify->KeyNotificationFn == KeyNotificationFunction) {\r
+        *NotifyHandle = CurrentNotify;\r
+        return EFI_SUCCESS;\r
+      }\r
+    }\r
+  }\r
+\r
+  //\r
+  // Allocate resource to save the notification function\r
+  //\r
+  NewNotify = (TEXT_IN_EX_SPLITTER_NOTIFY *) AllocateZeroPool (sizeof (TEXT_IN_EX_SPLITTER_NOTIFY));\r
+  if (NewNotify == NULL) {\r
+    return EFI_OUT_OF_RESOURCES;\r
+  }\r
+  NewNotify->NotifyHandleList = (EFI_HANDLE *) AllocateZeroPool (sizeof (EFI_HANDLE) *  Private->TextInExListCount);\r
+  if (NewNotify->NotifyHandleList == NULL) {\r
+    gBS->FreePool (NewNotify);\r
+    return EFI_OUT_OF_RESOURCES;\r
+  }\r
+  NewNotify->Signature         = TEXT_IN_EX_SPLITTER_NOTIFY_SIGNATURE;\r
+  NewNotify->KeyNotificationFn = KeyNotificationFunction;\r
+  CopyMem (&NewNotify->KeyData, KeyData, sizeof (EFI_KEY_DATA));\r
+\r
+  //\r
+  // Return the wrong status of registering key notify of\r
+  // physical console input device if meet problems\r
+  //\r
+  for (Index = 0; Index < Private->CurrentNumberOfExConsoles; Index++) {\r
+    Status = Private->TextInExList[Index]->RegisterKeyNotify (\r
+                                             Private->TextInExList[Index],\r
+                                             KeyData,\r
+                                             KeyNotificationFunction,\r
+                                             &NewNotify->NotifyHandleList[Index]\r
+                                             );\r
+    if (EFI_ERROR (Status)) {\r
+      //\r
+      // Un-register the key notify on all physical console input devices\r
+      //\r
+      while (Index-- != 0) {\r
+        Private->TextInExList[Index]->UnregisterKeyNotify (\r
+                                        Private->TextInExList[Index],\r
+                                        NewNotify->NotifyHandleList[Index]\r
+                                        );\r
+      }\r
+      gBS->FreePool (NewNotify->NotifyHandleList);\r
+      gBS->FreePool (NewNotify);\r
+      return Status;\r
+    }\r
+  }\r
+\r
+  InsertTailList (&mConIn.NotifyList, &NewNotify->NotifyEntry);\r
+\r
+  *NotifyHandle                = NewNotify;\r
+\r
+  return EFI_SUCCESS;\r
+\r
+}\r
+\r
+\r
+/**\r
+  Remove a registered notification function from a particular keystroke.\r
+\r
+  @param  This                     Protocol instance pointer.\r
+  @param  NotificationHandle       The handle of the notification function being\r
+                                   unregistered.\r
+\r
+  @retval EFI_SUCCESS              The notification function was unregistered\r
+                                   successfully.\r
+  @retval EFI_INVALID_PARAMETER    The NotificationHandle is invalid.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+ConSplitterTextInUnregisterKeyNotify (\r
+  IN EFI_SIMPLE_TEXT_INPUT_EX_PROTOCOL  *This,\r
+  IN VOID                               *NotificationHandle\r
+  )\r
+{\r
+  TEXT_IN_SPLITTER_PRIVATE_DATA *Private;\r
+  UINTN                         Index;\r
+  TEXT_IN_EX_SPLITTER_NOTIFY    *CurrentNotify;\r
+  LIST_ENTRY                    *Link;\r
+\r
+  if (NotificationHandle == NULL) {\r
+    return EFI_INVALID_PARAMETER;\r
+  }\r
+\r
+  Private = TEXT_IN_EX_SPLITTER_PRIVATE_DATA_FROM_THIS (This);\r
+\r
+  for (Link = Private->NotifyList.ForwardLink; Link != &Private->NotifyList; Link = Link->ForwardLink) {\r
+    CurrentNotify = TEXT_IN_EX_SPLITTER_NOTIFY_FROM_THIS (Link);\r
+    if (CurrentNotify == NotificationHandle) {\r
+      for (Index = 0; Index < Private->CurrentNumberOfExConsoles; Index++) {\r
+        Private->TextInExList[Index]->UnregisterKeyNotify (\r
+                                        Private->TextInExList[Index],\r
+                                        CurrentNotify->NotifyHandleList[Index]\r
+                                        );\r
+      }\r
+      RemoveEntryList (&CurrentNotify->NotifyEntry);\r
+\r
+      gBS->FreePool (CurrentNotify->NotifyHandleList);\r
+      gBS->FreePool (CurrentNotify);\r
+      return EFI_SUCCESS;\r
+    }\r
+  }\r
+\r
+  //\r
+  // NotificationHandle is not found in database\r
+  //\r
+  return EFI_INVALID_PARAMETER;\r
+}\r
+\r
+\r
+/**\r
+  Reset the input device and optionaly run diagnostics\r
+\r
+  @param  This                     Protocol instance pointer.\r
+  @param  ExtendedVerification     Driver may perform diagnostics on reset.\r
+\r
+  @retval EFI_SUCCESS              The device was reset.\r
+  @retval EFI_DEVICE_ERROR         The device is not functioning properly and could\r
+                                   not be reset.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+ConSplitterSimplePointerReset (\r
+  IN  EFI_SIMPLE_POINTER_PROTOCOL     *This,\r
+  IN  BOOLEAN                         ExtendedVerification\r
+  )\r
+{\r
+  EFI_STATUS                    Status;\r
+  EFI_STATUS                    ReturnStatus;\r
+  TEXT_IN_SPLITTER_PRIVATE_DATA *Private;\r
+  UINTN                         Index;\r
+\r
+  Private                         = TEXT_IN_SPLITTER_PRIVATE_DATA_FROM_SIMPLE_POINTER_THIS (This);\r
+\r
+  Private->InputEventSignalState  = FALSE;\r
+\r
+  if (Private->CurrentNumberOfPointers == 0) {\r
+    return EFI_SUCCESS;\r
+  }\r
+  //\r
+  // return the worst status met\r
+  //\r
+  for (Index = 0, ReturnStatus = EFI_SUCCESS; Index < Private->CurrentNumberOfPointers; Index++) {\r
+    Status = Private->PointerList[Index]->Reset (\r
+                                            Private->PointerList[Index],\r
+                                            ExtendedVerification\r
+                                            );\r
+    if (EFI_ERROR (Status)) {\r
+      ReturnStatus = Status;\r
+    }\r
+  }\r
+\r
+  return ReturnStatus;\r
+}\r
+\r
+\r
+/**\r
+  Reads the next keystroke from the input device. The WaitForKey Event can\r
+  be used to test for existance of a keystroke via WaitForEvent () call.\r
+\r
+  @param  Private                  Protocol instance pointer.\r
+  @param  State                    The state information of simple pointer device.\r
+\r
+  @retval EFI_SUCCESS              The keystroke information was returned.\r
+  @retval EFI_NOT_READY            There was no keystroke data availiable.\r
+  @retval EFI_DEVICE_ERROR         The keydtroke information was not returned due\r
+                                   to hardware errors.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+ConSplitterSimplePointerPrivateGetState (\r
+  IN  TEXT_IN_SPLITTER_PRIVATE_DATA   *Private,\r
+  IN OUT EFI_SIMPLE_POINTER_STATE     *State\r
+  )\r
+{\r
+  EFI_STATUS                Status;\r
+  EFI_STATUS                ReturnStatus;\r
+  UINTN                     Index;\r
+  EFI_SIMPLE_POINTER_STATE  CurrentState;\r
+\r
+  State->RelativeMovementX  = 0;\r
+  State->RelativeMovementY  = 0;\r
+  State->RelativeMovementZ  = 0;\r
+  State->LeftButton         = FALSE;\r
+  State->RightButton        = FALSE;\r
+\r
+  //\r
+  // if no physical console input device exists, return EFI_NOT_READY;\r
+  // if any physical console input device has key input,\r
+  // return the key and EFI_SUCCESS.\r
+  //\r
+  ReturnStatus = EFI_NOT_READY;\r
+  for (Index = 0; Index < Private->CurrentNumberOfPointers; Index++) {\r
+\r
+    Status = Private->PointerList[Index]->GetState (\r
+                                            Private->PointerList[Index],\r
+                                            &CurrentState\r
+                                            );\r
+    if (!EFI_ERROR (Status)) {\r
+      if (ReturnStatus == EFI_NOT_READY) {\r
+        ReturnStatus = EFI_SUCCESS;\r
+      }\r
+\r
+      if (CurrentState.LeftButton) {\r
+        State->LeftButton = TRUE;\r
+      }\r
+\r
+      if (CurrentState.RightButton) {\r
+        State->RightButton = TRUE;\r
+      }\r
+\r
+      if (CurrentState.RelativeMovementX != 0 && Private->PointerList[Index]->Mode->ResolutionX != 0) {\r
+        State->RelativeMovementX += (CurrentState.RelativeMovementX * (INT32) Private->SimplePointerMode.ResolutionX) / (INT32) Private->PointerList[Index]->Mode->ResolutionX;\r
+      }\r
+\r
+      if (CurrentState.RelativeMovementY != 0 && Private->PointerList[Index]->Mode->ResolutionY != 0) {\r
+        State->RelativeMovementY += (CurrentState.RelativeMovementY * (INT32) Private->SimplePointerMode.ResolutionY) / (INT32) Private->PointerList[Index]->Mode->ResolutionY;\r
+      }\r
+\r
+      if (CurrentState.RelativeMovementZ != 0 && Private->PointerList[Index]->Mode->ResolutionZ != 0) {\r
+        State->RelativeMovementZ += (CurrentState.RelativeMovementZ * (INT32) Private->SimplePointerMode.ResolutionZ) / (INT32) Private->PointerList[Index]->Mode->ResolutionZ;\r
+      }\r
+    } else if (Status == EFI_DEVICE_ERROR) {\r
+      ReturnStatus = EFI_DEVICE_ERROR;\r
+    }\r
+  }\r
+\r
+  return ReturnStatus;\r
+}\r
+\r
+\r
+/**\r
+  Reads the next keystroke from the input device. The WaitForKey Event can\r
+  be used to test for existance of a keystroke via WaitForEvent () call.\r
+\r
+  @param  This                     A pointer to protocol instance.\r
+  @param  State                    A pointer to state information on the pointer device\r
+\r
+  @retval EFI_SUCCESS              The keystroke information was returned in State.\r
+  @retval EFI_NOT_READY            There was no keystroke data availiable.\r
+  @retval EFI_DEVICE_ERROR         The keydtroke information was not returned due\r
+                                   to hardware errors.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+ConSplitterSimplePointerGetState (\r
+  IN  EFI_SIMPLE_POINTER_PROTOCOL     *This,\r
+  IN OUT EFI_SIMPLE_POINTER_STATE     *State\r
+  )\r
+{\r
+  TEXT_IN_SPLITTER_PRIVATE_DATA *Private;\r
+\r
+  Private = TEXT_IN_SPLITTER_PRIVATE_DATA_FROM_SIMPLE_POINTER_THIS (This);\r
+\r
+  Private->InputEventSignalState = FALSE;\r
+\r
+  return ConSplitterSimplePointerPrivateGetState (Private, State);\r
+}\r
+\r
+\r
+/**\r
+  This event agregates all the events of the ConIn devices in the spliter.\r
+  If any events of physical ConIn devices are signaled, signal the ConIn\r
+  spliter event. This will cause the calling code to call\r
+  ConSplitterTextInReadKeyStroke ().\r
+\r
+  @param  Event                    The Event assoicated with callback.\r
+  @param  Context                  Context registered when Event was created.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+ConSplitterSimplePointerWaitForInput (\r
+  IN  EFI_EVENT                       Event,\r
+  IN  VOID                            *Context\r
+  )\r
+{\r
+  EFI_STATUS                    Status;\r
+  TEXT_IN_SPLITTER_PRIVATE_DATA *Private;\r
+  UINTN                         Index;\r
+\r
+  Private = (TEXT_IN_SPLITTER_PRIVATE_DATA *) Context;\r
+\r
+  //\r
+  // if InputEventSignalState is flagged before, and not cleared by Reset() or ReadKeyStroke()\r
+  //\r
+  if (Private->InputEventSignalState) {\r
+    gBS->SignalEvent (Event);\r
+    return ;\r
+  }\r
+  //\r
+  // if any physical console input device has key input, signal the event.\r
+  //\r
+  for (Index = 0; Index < Private->CurrentNumberOfPointers; Index++) {\r
+    Status = gBS->CheckEvent (Private->PointerList[Index]->WaitForInput);\r
+    if (!EFI_ERROR (Status)) {\r
+      gBS->SignalEvent (Event);\r
+      Private->InputEventSignalState = TRUE;\r
+    }\r
+  }\r
+}\r
+\r
+/**\r
+  Resets the pointer device hardware.\r
+\r
+  @param  This                     Protocol instance pointer.\r
+  @param  ExtendedVerification     Driver may perform diagnostics on reset.\r
+\r
+  @retval EFI_SUCCESS              The device was reset.\r
+  @retval EFI_DEVICE_ERROR         The device is not functioning correctly and\r
+                                   could not be reset.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+ConSplitterAbsolutePointerReset (\r
+  IN EFI_ABSOLUTE_POINTER_PROTOCOL   *This,\r
+  IN BOOLEAN                         ExtendedVerification\r
+  )\r
+{\r
+  EFI_STATUS                    Status;\r
+  EFI_STATUS                    ReturnStatus;\r
+  TEXT_IN_SPLITTER_PRIVATE_DATA *Private;\r
+  UINTN                         Index;\r
+\r
+  Private = TEXT_IN_SPLITTER_PRIVATE_DATA_FROM_ABSOLUTE_POINTER_THIS (This);\r
+\r
+  Private->AbsoluteInputEventSignalState = FALSE;\r
+\r
+  if (Private->CurrentNumberOfAbsolutePointers == 0) {\r
+    return EFI_SUCCESS;\r
+  }\r
+  //\r
+  // return the worst status met\r
+  //\r
+  for (Index = 0, ReturnStatus = EFI_SUCCESS; Index < Private->CurrentNumberOfAbsolutePointers; Index++) {\r
+    Status = Private->AbsolutePointerList[Index]->Reset (\r
+                                                    Private->AbsolutePointerList[Index],\r
+                                                    ExtendedVerification\r
+                                                    );\r
+    if (EFI_ERROR (Status)) {\r
+      ReturnStatus = Status;\r
+    }\r
+  }\r
+\r
+  return ReturnStatus;\r
+}\r
+\r
+\r
+/**\r
+  Retrieves the current state of a pointer device.\r
+\r
+  @param  This                     Protocol instance pointer.\r
+  @param  State                    A pointer to the state information on the\r
+                                   pointer device.\r
+\r
+  @retval EFI_SUCCESS              The state of the pointer device was returned in\r
+                                   State..\r
+  @retval EFI_NOT_READY            The state of the pointer device has not changed\r
+                                   since the last call to GetState().\r
+  @retval EFI_DEVICE_ERROR         A device error occurred while attempting to\r
+                                   retrieve the pointer device's current state.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+ConSplitterAbsolutePointerGetState (\r
+  IN EFI_ABSOLUTE_POINTER_PROTOCOL   *This,\r
+  IN OUT EFI_ABSOLUTE_POINTER_STATE  *State\r
+  )\r
+{\r
+  TEXT_IN_SPLITTER_PRIVATE_DATA *Private;\r
+  EFI_STATUS                    Status;\r
+  EFI_STATUS                    ReturnStatus;\r
+  UINTN                         Index;\r
+  EFI_ABSOLUTE_POINTER_STATE    CurrentState;\r
+\r
+\r
+  Private = TEXT_IN_SPLITTER_PRIVATE_DATA_FROM_ABSOLUTE_POINTER_THIS (This);\r
+\r
+  Private->AbsoluteInputEventSignalState = FALSE;\r
+\r
+  State->CurrentX                        = 0;\r
+  State->CurrentY                        = 0;\r
+  State->CurrentZ                        = 0;\r
+  State->ActiveButtons                   = 0;\r
+\r
+  //\r
+  // if no physical pointer device exists, return EFI_NOT_READY;\r
+  // if any physical pointer device has changed state,\r
+  // return the state and EFI_SUCCESS.\r
+  //\r
+  ReturnStatus = EFI_NOT_READY;\r
+  for (Index = 0; Index < Private->CurrentNumberOfAbsolutePointers; Index++) {\r
+\r
+    Status = Private->AbsolutePointerList[Index]->GetState (\r
+                                                    Private->AbsolutePointerList[Index],\r
+                                                    &CurrentState\r
+                                                    );\r
+    if (!EFI_ERROR (Status)) {\r
+      if (ReturnStatus == EFI_NOT_READY) {\r
+        ReturnStatus = EFI_SUCCESS;\r
+      }\r
+\r
+      State->ActiveButtons = CurrentState.ActiveButtons;\r
+\r
+      if (!(Private->AbsolutePointerMode.AbsoluteMinX == 0 && Private->AbsolutePointerMode.AbsoluteMaxX == 0)) {\r
+        State->CurrentX = CurrentState.CurrentX;\r
+      }\r
+      if (!(Private->AbsolutePointerMode.AbsoluteMinY == 0 && Private->AbsolutePointerMode.AbsoluteMaxY == 0)) {\r
+        State->CurrentY = CurrentState.CurrentY;\r
+      }\r
+      if (!(Private->AbsolutePointerMode.AbsoluteMinZ == 0 && Private->AbsolutePointerMode.AbsoluteMaxZ == 0)) {\r
+        State->CurrentZ = CurrentState.CurrentZ;\r
+      }\r
+\r
+    } else if (Status == EFI_DEVICE_ERROR) {\r
+      ReturnStatus = EFI_DEVICE_ERROR;\r
+    }\r
+  }\r
+\r
+  return ReturnStatus;\r
+}\r
+\r
+\r
+/**\r
+  This event agregates all the events of the pointer devices in the splitter.\r
+  If any events of physical pointer devices are signaled, signal the pointer\r
+  splitter event. This will cause the calling code to call\r
+  ConSplitterAbsolutePointerGetState ().\r
+\r
+  @param  Event                    The Event assoicated with callback.\r
+  @param  Context                  Context registered when Event was created.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+ConSplitterAbsolutePointerWaitForInput (\r
+  IN  EFI_EVENT                       Event,\r
+  IN  VOID                            *Context\r
+  )\r
+{\r
+  EFI_STATUS                    Status;\r
+  TEXT_IN_SPLITTER_PRIVATE_DATA *Private;\r
+  UINTN                         Index;\r
+\r
+  Private = (TEXT_IN_SPLITTER_PRIVATE_DATA *) Context;\r
+\r
+  //\r
+  // if AbsoluteInputEventSignalState is flagged before,\r
+  // and not cleared by Reset() or GetState(), signal it\r
+  //\r
+  if (Private->AbsoluteInputEventSignalState) {\r
+    gBS->SignalEvent (Event);\r
+    return ;\r
+  }\r
+  //\r
+  // if any physical console input device has key input, signal the event.\r
+  //\r
+  for (Index = 0; Index < Private->CurrentNumberOfAbsolutePointers; Index++) {\r
+    Status = gBS->CheckEvent (Private->AbsolutePointerList[Index]->WaitForInput);\r
+    if (!EFI_ERROR (Status)) {\r
+      gBS->SignalEvent (Event);\r
+      Private->AbsoluteInputEventSignalState = TRUE;\r
+    }\r
+  }\r
+}\r
+\r
+\r
+/**\r
+  Reset the text output device hardware and optionaly run diagnostics\r
+\r
+  @param  This                     Protocol instance pointer.\r
+  @param  ExtendedVerification     Driver may perform more exhaustive verfication\r
+                                   operation of the device during reset.\r
+\r
+  @retval EFI_SUCCESS              The text output device was reset.\r
+  @retval EFI_DEVICE_ERROR         The text output device is not functioning\r
+                                   correctly and could not be reset.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+ConSplitterTextOutReset (\r
+  IN  EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL    *This,\r
+  IN  BOOLEAN                            ExtendedVerification\r
+  )\r
+{\r
+  EFI_STATUS                      Status;\r
+  TEXT_OUT_SPLITTER_PRIVATE_DATA  *Private;\r
+  UINTN                           Index;\r
+  EFI_STATUS                      ReturnStatus;\r
+\r
+  Private = TEXT_OUT_SPLITTER_PRIVATE_DATA_FROM_THIS (This);\r
+\r
+  //\r
+  // return the worst status met\r
+  //\r
+  for (Index = 0, ReturnStatus = EFI_SUCCESS; Index < Private->CurrentNumberOfConsoles; Index++) {\r
+    Status = Private->TextOutList[Index].TextOut->Reset (\r
+                                                    Private->TextOutList[Index].TextOut,\r
+                                                    ExtendedVerification\r
+                                                    );\r
+    if (EFI_ERROR (Status)) {\r
+      ReturnStatus = Status;\r
+    }\r
+  }\r
+\r
+  This->SetAttribute (This, EFI_TEXT_ATTR (This->Mode->Attribute & 0x0F, EFI_BLACK));\r
+\r
+  //\r
+  // reset all mode parameters\r
+  //\r
+  TextOutSetMode (Private, 0);\r
+\r
+  return ReturnStatus;\r
+}\r
+\r
+\r
+/**\r
+  Write a Unicode string to the output device.\r
+\r
+  @param  This                     Protocol instance pointer.\r
+  @param  WString                  The NULL-terminated Unicode string to be\r
+                                   displayed on the output device(s). All output\r
+                                   devices must also support the Unicode drawing\r
+                                   defined in this file.\r
+\r
+  @retval EFI_SUCCESS              The string was output to the device.\r
+  @retval EFI_DEVICE_ERROR         The device reported an error while attempting to\r
+                                   output the text.\r
+  @retval EFI_UNSUPPORTED          The output device's mode is not currently in a\r
+                                   defined text mode.\r
+  @retval EFI_WARN_UNKNOWN_GLYPH   This warning code indicates that some of the\r
+                                   characters in the Unicode string could not be\r
+                                   rendered and were skipped.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+ConSplitterTextOutOutputString (\r
+  IN  EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL    *This,\r
+  IN  CHAR16                             *WString\r
+  )\r
+{\r
+  EFI_STATUS                      Status;\r
+  TEXT_OUT_SPLITTER_PRIVATE_DATA  *Private;\r
+  UINTN                           Index;\r
+  EFI_STATUS                      ReturnStatus;\r
+  UINTN                           MaxColumn;\r
+  UINTN                           MaxRow;\r
+\r
+  This->SetAttribute (This, This->Mode->Attribute);\r
+\r
+  Private         = TEXT_OUT_SPLITTER_PRIVATE_DATA_FROM_THIS (This);\r
+\r
+  //\r
+  // return the worst status met\r
+  //\r
+  for (Index = 0, ReturnStatus = EFI_SUCCESS; Index < Private->CurrentNumberOfConsoles; Index++) {\r
+    Status = Private->TextOutList[Index].TextOut->OutputString (\r
+                                                    Private->TextOutList[Index].TextOut,\r
+                                                    WString\r
+                                                    );\r
+    if (EFI_ERROR (Status)) {\r
+      ReturnStatus = Status;\r
+    }\r
+  }\r
+\r
+  if (Private->CurrentNumberOfConsoles > 0) {\r
+    Private->TextOutMode.CursorColumn = Private->TextOutList[0].TextOut->Mode->CursorColumn;\r
+    Private->TextOutMode.CursorRow    = Private->TextOutList[0].TextOut->Mode->CursorRow;\r
+  } else {\r
+    //\r
+    // When there is no real console devices in system, \r
+    // update cursor position for the virtual device in consplitter.\r
+    //\r
+    Private->TextOut.QueryMode (\r
+                       &Private->TextOut,\r
+                       Private->TextOutMode.Mode,\r
+                       &MaxColumn,\r
+                       &MaxRow\r
+                       );    \r
+    for (; *WString != CHAR_NULL; WString++) {\r
+      switch (*WString) {\r
+      case CHAR_BACKSPACE:\r
+        if (Private->TextOutMode.CursorColumn == 0 && Private->TextOutMode.CursorRow > 0) {\r
+          Private->TextOutMode.CursorRow--;\r
+          Private->TextOutMode.CursorColumn = (INT32) (MaxColumn - 1);          \r
+        } else if (Private->TextOutMode.CursorColumn > 0) {\r
+          Private->TextOutMode.CursorColumn--;\r
+        }\r
+        break;\r
+      \r
+      case CHAR_LINEFEED:\r
+        if (Private->TextOutMode.CursorRow < (INT32) (MaxRow - 1)) {\r
+          Private->TextOutMode.CursorRow++;\r
+        }\r
+        break;\r
+      \r
+      case CHAR_CARRIAGE_RETURN:\r
+        Private->TextOutMode.CursorColumn = 0;\r
+        break;\r
+      \r
+      default:\r
+        if (Private->TextOutMode.CursorColumn < (INT32) (MaxColumn - 1)) {\r
+          Private->TextOutMode.CursorColumn++;\r
+        } else {\r
+          Private->TextOutMode.CursorColumn = 0;\r
+          if (Private->TextOutMode.CursorRow < (INT32) (MaxRow - 1)) {\r
+            Private->TextOutMode.CursorRow++;\r
+          }\r
+        }\r
+        break;\r
+      }\r
+    }\r
+  }\r
+\r
+  return ReturnStatus;\r
+}\r
+\r
+\r
+/**\r
+  Verifies that all characters in a Unicode string can be output to the\r
+  target device.\r
+\r
+  @param  This                     Protocol instance pointer.\r
+  @param  WString                  The NULL-terminated Unicode string to be\r
+                                   examined for the output device(s).\r
+\r
+  @retval EFI_SUCCESS              The device(s) are capable of rendering the\r
+                                   output string.\r
+  @retval EFI_UNSUPPORTED          Some of the characters in the Unicode string\r
+                                   cannot be rendered by one or more of the output\r
+                                   devices mapped by the EFI handle.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+ConSplitterTextOutTestString (\r
+  IN  EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL    *This,\r
+  IN  CHAR16                             *WString\r
+  )\r
+{\r
+  EFI_STATUS                      Status;\r
+  TEXT_OUT_SPLITTER_PRIVATE_DATA  *Private;\r
+  UINTN                           Index;\r
+  EFI_STATUS                      ReturnStatus;\r
+\r
+  Private = TEXT_OUT_SPLITTER_PRIVATE_DATA_FROM_THIS (This);\r
+\r
+  //\r
+  // return the worst status met\r
+  //\r
+  for (Index = 0, ReturnStatus = EFI_SUCCESS; Index < Private->CurrentNumberOfConsoles; Index++) {\r
+    Status = Private->TextOutList[Index].TextOut->TestString (\r
+                                                    Private->TextOutList[Index].TextOut,\r
+                                                    WString\r
+                                                    );\r
+    if (EFI_ERROR (Status)) {\r
+      ReturnStatus = Status;\r
+    }\r
+  }\r
+  //\r
+  // There is no DevNullTextOutTestString () since a Unicode buffer would\r
+  // always return EFI_SUCCESS.\r
+  // ReturnStatus will be EFI_SUCCESS if no consoles are present\r
+  //\r
+  return ReturnStatus;\r
+}\r
+\r
+\r
+/**\r
+  Returns information for an available text mode that the output device(s)\r
+  supports.\r
+\r
+  @param  This                     Protocol instance pointer.\r
+  @param  ModeNumber               The mode number to return information on.\r
+  @param  Columns                  Returns the columns of the text output device\r
+                                   for the requested ModeNumber.\r
+  @param  Rows                     Returns the rows of the text output device\r
+                                   for the requested ModeNumber.\r
+\r
+  @retval EFI_SUCCESS              The requested mode information was returned.\r
+  @retval EFI_DEVICE_ERROR         The device had an error and could not complete\r
+                                   the request.\r
+  @retval EFI_UNSUPPORTED          The mode number was not valid.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+ConSplitterTextOutQueryMode (\r
+  IN  EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL    *This,\r
+  IN  UINTN                              ModeNumber,\r
+  OUT UINTN                              *Columns,\r
+  OUT UINTN                              *Rows\r
+  )\r
+{\r
+  TEXT_OUT_SPLITTER_PRIVATE_DATA  *Private;\r
+  UINTN                           CurrentMode;\r
+  INT32                           *TextOutModeMap;\r
+\r
+  Private = TEXT_OUT_SPLITTER_PRIVATE_DATA_FROM_THIS (This);\r
+\r
+  //\r
+  // Check whether param ModeNumber is valid.\r
+  // ModeNumber should be within range 0 ~ MaxMode - 1.\r
+  //\r
+  if ( (ModeNumber > (UINTN)(((UINT32)-1)>>1)) ) {\r
+    return EFI_UNSUPPORTED;\r
+  }\r
+\r
+  if ((INT32) ModeNumber >= This->Mode->MaxMode) {\r
+    return EFI_UNSUPPORTED;\r
+  }\r
+\r
+  //\r
+  // We get the available mode from mode intersection map if it's available\r
+  //\r
+  if (Private->TextOutModeMap != NULL) {\r
+    TextOutModeMap = Private->TextOutModeMap + Private->TextOutListCount * ModeNumber;\r
+    CurrentMode    = (UINTN)(*TextOutModeMap);\r
+    *Columns       = Private->TextOutQueryData[CurrentMode].Columns;\r
+    *Rows          = Private->TextOutQueryData[CurrentMode].Rows;\r
+  } else {\r
+    *Columns  = Private->TextOutQueryData[ModeNumber].Columns;\r
+    *Rows     = Private->TextOutQueryData[ModeNumber].Rows;\r
+  }\r
+\r
+  if (*Columns <= 0 && *Rows <= 0) {\r
+    return EFI_UNSUPPORTED;\r
+\r
+  }\r
+\r
+  return EFI_SUCCESS;\r
+}\r
+\r
+\r
+/**\r
+  Sets the output device(s) to a specified mode.\r
+\r
+  @param  This                     Protocol instance pointer.\r
+  @param  ModeNumber               The mode number to set.\r
+\r
+  @retval EFI_SUCCESS              The requested text mode was set.\r
+  @retval EFI_DEVICE_ERROR         The device had an error and could not complete\r
+                                   the request.\r
+  @retval EFI_UNSUPPORTED          The mode number was not valid.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+ConSplitterTextOutSetMode (\r
+  IN  EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL    *This,\r
+  IN  UINTN                              ModeNumber\r
+  )\r
+{\r
+  EFI_STATUS                      Status;\r
+  TEXT_OUT_SPLITTER_PRIVATE_DATA  *Private;\r
+  UINTN                           Index;\r
+  INT32                           *TextOutModeMap;\r
+  EFI_STATUS                      ReturnStatus;\r
+\r
+  Private = TEXT_OUT_SPLITTER_PRIVATE_DATA_FROM_THIS (This);\r
+\r
+  //\r
+  // Check whether param ModeNumber is valid.\r
+  // ModeNumber should be within range 0 ~ MaxMode - 1.\r
+  //\r
+  if ( (ModeNumber > (UINTN)(((UINT32)-1)>>1)) ) {\r
+    return EFI_UNSUPPORTED;\r
+  }\r
+\r
+  if ((INT32) ModeNumber >= This->Mode->MaxMode) {\r
+    return EFI_UNSUPPORTED;\r
+  }\r
+  //\r
+  // If the mode is being set to the curent mode, then just clear the screen and return.\r
+  //\r
+  if (Private->TextOutMode.Mode == (INT32) ModeNumber) {\r
+    return ConSplitterTextOutClearScreen (This);\r
+  }\r
+  //\r
+  // return the worst status met\r
+  //\r
+  TextOutModeMap = Private->TextOutModeMap + Private->TextOutListCount * ModeNumber;\r
+  for (Index = 0, ReturnStatus = EFI_SUCCESS; Index < Private->CurrentNumberOfConsoles; Index++) {\r
+    Status = Private->TextOutList[Index].TextOut->SetMode (\r
+                                                    Private->TextOutList[Index].TextOut,\r
+                                                    TextOutModeMap[Index]\r
+                                                    );\r
+    if (EFI_ERROR (Status)) {\r
+      ReturnStatus = Status;\r
+    }\r
+  }\r
+\r
+  //\r
+  // Set mode parameter to specified mode number\r
+  //\r
+  TextOutSetMode (Private, ModeNumber);\r
+\r
+  return ReturnStatus;\r
+}\r
+\r
+\r
+/**\r
+  Sets the background and foreground colors for the OutputString () and\r
+  ClearScreen () functions.\r
+\r
+  @param  This                     Protocol instance pointer.\r
+  @param  Attribute                The attribute to set. Bits 0..3 are the\r
+                                   foreground color, and bits 4..6 are the\r
+                                   background color. All other bits are undefined\r
+                                   and must be zero. The valid Attributes are\r
+                                   defined in this file.\r
+\r
+  @retval EFI_SUCCESS              The attribute was set.\r
+  @retval EFI_DEVICE_ERROR         The device had an error and could not complete\r
+                                   the request.\r
+  @retval EFI_UNSUPPORTED          The attribute requested is not defined.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+ConSplitterTextOutSetAttribute (\r
+  IN  EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL    *This,\r
+  IN  UINTN                              Attribute\r
+  )\r
+{\r
+  EFI_STATUS                      Status;\r
+  TEXT_OUT_SPLITTER_PRIVATE_DATA  *Private;\r
+  UINTN                           Index;\r
+  EFI_STATUS                      ReturnStatus;\r
+\r
+  Private = TEXT_OUT_SPLITTER_PRIVATE_DATA_FROM_THIS (This);\r
+\r
+  //\r
+  // Check whether param Attribute is valid.\r
+  //\r
+  if ( (Attribute > (UINTN)(((UINT32)-1)>>1)) ) {\r
+    return EFI_UNSUPPORTED;\r
+  }\r
+\r
+  //\r
+  // return the worst status met\r
+  //\r
+  for (Index = 0, ReturnStatus = EFI_SUCCESS; Index < Private->CurrentNumberOfConsoles; Index++) {\r
+    Status = Private->TextOutList[Index].TextOut->SetAttribute (\r
+                                                    Private->TextOutList[Index].TextOut,\r
+                                                    Attribute\r
+                                                    );\r
+    if (EFI_ERROR (Status)) {\r
+      ReturnStatus = Status;\r
+    }\r
+  }\r
+\r
+  Private->TextOutMode.Attribute = (INT32) Attribute;\r
+\r
+  return ReturnStatus;\r
+}\r
+\r
+\r
+/**\r
+  Clears the output device(s) display to the currently selected background\r
+  color.\r
+\r
+  @param  This                     Protocol instance pointer.\r
+\r
+  @retval EFI_SUCCESS              The operation completed successfully.\r
+  @retval EFI_DEVICE_ERROR         The device had an error and could not complete\r
+                                   the request.\r
+  @retval EFI_UNSUPPORTED          The output device is not in a valid text mode.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+ConSplitterTextOutClearScreen (\r
+  IN  EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL    *This\r
+  )\r
+{\r
+  EFI_STATUS                      Status;\r
+  TEXT_OUT_SPLITTER_PRIVATE_DATA  *Private;\r
+  UINTN                           Index;\r
+  EFI_STATUS                      ReturnStatus;\r
+\r
+  Private = TEXT_OUT_SPLITTER_PRIVATE_DATA_FROM_THIS (This);\r
+\r
+  //\r
+  // return the worst status met\r
+  //\r
+  for (Index = 0, ReturnStatus = EFI_SUCCESS; Index < Private->CurrentNumberOfConsoles; Index++) {\r
+    Status = Private->TextOutList[Index].TextOut->ClearScreen (Private->TextOutList[Index].TextOut);\r
+    if (EFI_ERROR (Status)) {\r
+      ReturnStatus = Status;\r
+    }\r
+  }\r
+\r
+  //\r
+  // No need to do extra check here as whether (Column, Row) is valid has\r
+  // been checked in ConSplitterTextOutSetCursorPosition. And (0, 0) should\r
+  // always be supported.\r
+  //\r
+  Private->TextOutMode.CursorColumn = 0;\r
+  Private->TextOutMode.CursorRow    = 0;\r
+  Private->TextOutMode.CursorVisible = TRUE;\r
+\r
+  return ReturnStatus;\r
+}\r
+\r
+\r
+/**\r
+  Sets the current coordinates of the cursor position\r
+\r
+  @param  This                     Protocol instance pointer.\r
+  @param  Column                   The column position to set the cursor to. Must be\r
+                                   greater than or equal to zero and less than the\r
+                                   number of columns by QueryMode ().\r
+  @param  Row                      The row position to set the cursor to. Must be\r
+                                   greater than or equal to zero and less than the\r
+                                   number of rows by QueryMode ().\r
+\r
+  @retval EFI_SUCCESS              The operation completed successfully.\r
+  @retval EFI_DEVICE_ERROR         The device had an error and could not complete\r
+                                   the request.\r
+  @retval EFI_UNSUPPORTED          The output device is not in a valid text mode,\r
+                                   or the cursor position is invalid for the\r
+                                   current mode.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+ConSplitterTextOutSetCursorPosition (\r
+  IN  EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL    *This,\r
+  IN  UINTN                              Column,\r
+  IN  UINTN                              Row\r
+  )\r
+{\r
+  EFI_STATUS                      Status;\r
+  TEXT_OUT_SPLITTER_PRIVATE_DATA  *Private;\r
+  UINTN                           Index;\r
+  EFI_STATUS                      ReturnStatus;\r
+  UINTN                           MaxColumn;\r
+  UINTN                           MaxRow;\r
+  INT32                           *TextOutModeMap;\r
+  INT32                           ModeNumber;\r
+  INT32                           CurrentMode;\r
+\r
+  Private   = TEXT_OUT_SPLITTER_PRIVATE_DATA_FROM_THIS (This);\r
+  TextOutModeMap  = NULL;\r
+  ModeNumber      = Private->TextOutMode.Mode;\r
+\r
+  //\r
+  // Get current MaxColumn and MaxRow from intersection map\r
+  //\r
+  if (Private->TextOutModeMap != NULL) {\r
+    TextOutModeMap = Private->TextOutModeMap + Private->TextOutListCount * ModeNumber;\r
+    CurrentMode    = *TextOutModeMap;\r
+  } else {\r
+    CurrentMode = ModeNumber;\r
+  }\r
+\r
+  MaxColumn = Private->TextOutQueryData[CurrentMode].Columns;\r
+  MaxRow    = Private->TextOutQueryData[CurrentMode].Rows;\r
+\r
+  if (Column >= MaxColumn || Row >= MaxRow) {\r
+    return EFI_UNSUPPORTED;\r
+  }\r
+  //\r
+  // return the worst status met\r
+  //\r
+  for (Index = 0, ReturnStatus = EFI_SUCCESS; Index < Private->CurrentNumberOfConsoles; Index++) {\r
+    Status = Private->TextOutList[Index].TextOut->SetCursorPosition (\r
+                                                    Private->TextOutList[Index].TextOut,\r
+                                                    Column,\r
+                                                    Row\r
+                                                    );\r
+    if (EFI_ERROR (Status)) {\r
+      ReturnStatus = Status;\r
+    }\r
+  }\r
+\r
+  //\r
+  // No need to do extra check here as whether (Column, Row) is valid has\r
+  // been checked in ConSplitterTextOutSetCursorPosition. And (0, 0) should\r
+  // always be supported.\r
+  //\r
+  Private->TextOutMode.CursorColumn = (INT32) Column;\r
+  Private->TextOutMode.CursorRow    = (INT32) Row;\r
+\r
+  return ReturnStatus;\r
+}\r
+\r
+\r
+/**\r
+  Makes the cursor visible or invisible\r
+\r
+  @param  This                     Protocol instance pointer.\r
+  @param  Visible                  If TRUE, the cursor is set to be visible. If\r
+                                   FALSE, the cursor is set to be invisible.\r
+\r
+  @retval EFI_SUCCESS              The operation completed successfully.\r
+  @retval EFI_DEVICE_ERROR         The device had an error and could not complete\r
+                                   the request, or the device does not support\r
+                                   changing the cursor mode.\r
+  @retval EFI_UNSUPPORTED          The output device is not in a valid text mode.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+ConSplitterTextOutEnableCursor (\r
+  IN  EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL    *This,\r
+  IN  BOOLEAN                            Visible\r
+  )\r
+{\r
+  EFI_STATUS                      Status;\r
+  TEXT_OUT_SPLITTER_PRIVATE_DATA  *Private;\r
+  UINTN                           Index;\r
+  EFI_STATUS                      ReturnStatus;\r
+\r
+  Private = TEXT_OUT_SPLITTER_PRIVATE_DATA_FROM_THIS (This);\r
+\r
+  //\r
+  // return the worst status met\r
+  //\r
+  for (Index = 0, ReturnStatus = EFI_SUCCESS; Index < Private->CurrentNumberOfConsoles; Index++) {\r
+    Status = Private->TextOutList[Index].TextOut->EnableCursor (\r
+                                                    Private->TextOutList[Index].TextOut,\r
+                                                    Visible\r
+                                                    );\r
+    if (EFI_ERROR (Status)) {\r
+      ReturnStatus = Status;\r
+    }\r
+  }\r
+\r
+  Private->TextOutMode.CursorVisible = Visible;\r
+\r
+  return ReturnStatus;\r
+}\r
+\r
+\r
+/**\r
+  An empty function to pass error checking of CreateEventEx ().\r
+\r
+  @param  Event                 Event whose notification function is being invoked.\r
+  @param  Context               Pointer to the notification function's context,\r
+                                which is implementation-dependent.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+ConSplitterEmptyCallbackFunction (\r
+  IN EFI_EVENT                Event,\r
+  IN VOID                     *Context\r
+  )\r
+{\r
+}\r

diff --git a/Vlv2TbltDevicePkg/Override/MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitter.h b/Vlv2TbltDevicePkg/Override/MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitter.h
new file mode 100644 (file)
index 0000000..e32abba
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Override/MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitter.h
@@ -0,0 +1,2004 @@
+/** @file\r
+  Private data structures for the Console Splitter driver\r
+\r
+Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.<BR>\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution.  The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#ifndef _CON_SPLITTER_H_\r
+#define _CON_SPLITTER_H_\r
+\r
+#include <Uefi.h>\r
+#include <PiDxe.h>\r
+\r
+#include <Protocol/DevicePath.h>\r
+#include <Protocol/ComponentName.h>\r
+#include <Protocol/DriverBinding.h>\r
+#include <Protocol/SimplePointer.h>\r
+#include <Protocol/AbsolutePointer.h>\r
+#include <Protocol/SimpleTextOut.h>\r
+#include <Protocol/SimpleTextIn.h>\r
+#include <Protocol/SimpleTextInEx.h>\r
+#include <Protocol/GraphicsOutput.h>\r
+#include <Protocol/UgaDraw.h>\r
+\r
+#include <Guid/ConsoleInDevice.h>\r
+#include <Guid/StandardErrorDevice.h>\r
+#include <Guid/ConsoleOutDevice.h>\r
+#include <Guid/ConnectConInEvent.h>\r
+\r
+#include <Library/PcdLib.h>\r
+#include <Library/DebugLib.h>\r
+#include <Library/UefiDriverEntryPoint.h>\r
+#include <Library/UefiLib.h>\r
+#include <Library/BaseLib.h>\r
+#include <Library/BaseMemoryLib.h>\r
+#include <Library/MemoryAllocationLib.h>\r
+#include <Library/UefiBootServicesTableLib.h>\r
+#include <Library/UefiRuntimeServicesTableLib.h>\r
+\r
+//\r
+// Driver Binding Externs\r
+//\r
+extern EFI_DRIVER_BINDING_PROTOCOL  gConSplitterConInDriverBinding;\r
+extern EFI_COMPONENT_NAME_PROTOCOL  gConSplitterConInComponentName;\r
+extern EFI_COMPONENT_NAME2_PROTOCOL gConSplitterConInComponentName2;\r
+extern EFI_DRIVER_BINDING_PROTOCOL  gConSplitterSimplePointerDriverBinding;\r
+extern EFI_COMPONENT_NAME_PROTOCOL  gConSplitterSimplePointerComponentName;\r
+extern EFI_COMPONENT_NAME2_PROTOCOL gConSplitterSimplePointerComponentName2;\r
+extern EFI_DRIVER_BINDING_PROTOCOL  gConSplitterAbsolutePointerDriverBinding;\r
+extern EFI_COMPONENT_NAME_PROTOCOL  gConSplitterAbsolutePointerComponentName;\r
+extern EFI_COMPONENT_NAME2_PROTOCOL gConSplitterAbsolutePointerComponentName2;\r
+extern EFI_DRIVER_BINDING_PROTOCOL  gConSplitterConOutDriverBinding;\r
+extern EFI_COMPONENT_NAME_PROTOCOL  gConSplitterConOutComponentName;\r
+extern EFI_COMPONENT_NAME2_PROTOCOL gConSplitterConOutComponentName2;\r
+extern EFI_DRIVER_BINDING_PROTOCOL  gConSplitterStdErrDriverBinding;\r
+extern EFI_COMPONENT_NAME_PROTOCOL  gConSplitterStdErrComponentName;\r
+extern EFI_COMPONENT_NAME2_PROTOCOL gConSplitterStdErrComponentName2;\r
+\r
+\r
+//\r
+// These definitions were in the old Hii protocol, but are not in the new UEFI\r
+// version. So they are defined locally.\r
+//\r
+#define UNICODE_NARROW_CHAR   0xFFF0\r
+#define UNICODE_WIDE_CHAR     0xFFF1\r
+\r
+\r
+//\r
+// Private Data Structures\r
+//\r
+#define CONSOLE_SPLITTER_ALLOC_UNIT  32\r
+\r
+\r
+typedef struct {\r
+  UINTN   Column;\r
+  UINTN   Row;\r
+} CONSOLE_OUT_MODE;\r
+\r
+typedef struct {\r
+  UINTN   Columns;\r
+  UINTN   Rows;\r
+} TEXT_OUT_SPLITTER_QUERY_DATA;\r
+\r
+\r
+#define TEXT_IN_EX_SPLITTER_NOTIFY_SIGNATURE    SIGNATURE_32 ('T', 'i', 'S', 'n')\r
+\r
+//\r
+// Private data for Text In Ex Splitter Notify\r
+//\r
+typedef struct _TEXT_IN_EX_SPLITTER_NOTIFY {\r
+  UINTN                                 Signature;\r
+  VOID                                  **NotifyHandleList;\r
+  EFI_KEY_DATA                          KeyData;\r
+  EFI_KEY_NOTIFY_FUNCTION               KeyNotificationFn;\r
+  LIST_ENTRY                            NotifyEntry;\r
+} TEXT_IN_EX_SPLITTER_NOTIFY;\r
+\r
+#define TEXT_IN_EX_SPLITTER_NOTIFY_FROM_THIS(a)  \\r
+  CR ((a),                                       \\r
+      TEXT_IN_EX_SPLITTER_NOTIFY,                \\r
+      NotifyEntry,                               \\r
+      TEXT_IN_EX_SPLITTER_NOTIFY_SIGNATURE       \\r
+      )\r
+\r
+#define TEXT_IN_SPLITTER_PRIVATE_DATA_SIGNATURE SIGNATURE_32 ('T', 'i', 'S', 'p')\r
+\r
+//\r
+// Private data for the Console In splitter\r
+//\r
+typedef struct {\r
+  UINT64                             Signature;\r
+  EFI_HANDLE                         VirtualHandle;\r
+\r
+  EFI_SIMPLE_TEXT_INPUT_PROTOCOL     TextIn;\r
+  UINTN                              CurrentNumberOfConsoles;\r
+  EFI_SIMPLE_TEXT_INPUT_PROTOCOL     **TextInList;\r
+  UINTN                              TextInListCount;\r
+\r
+  EFI_SIMPLE_TEXT_INPUT_EX_PROTOCOL  TextInEx;\r
+  UINTN                              CurrentNumberOfExConsoles;\r
+  EFI_SIMPLE_TEXT_INPUT_EX_PROTOCOL  **TextInExList;\r
+  UINTN                              TextInExListCount;\r
+  LIST_ENTRY                         NotifyList;\r
+\r
+\r
+  EFI_SIMPLE_POINTER_PROTOCOL        SimplePointer;\r
+  EFI_SIMPLE_POINTER_MODE            SimplePointerMode;\r
+  UINTN                              CurrentNumberOfPointers;\r
+  EFI_SIMPLE_POINTER_PROTOCOL        **PointerList;\r
+  UINTN                              PointerListCount;\r
+\r
+  EFI_ABSOLUTE_POINTER_PROTOCOL      AbsolutePointer;\r
+  EFI_ABSOLUTE_POINTER_MODE          AbsolutePointerMode;\r
+  UINTN                              CurrentNumberOfAbsolutePointers;\r
+  EFI_ABSOLUTE_POINTER_PROTOCOL      **AbsolutePointerList;\r
+  UINTN                              AbsolutePointerListCount;\r
+  BOOLEAN                            AbsoluteInputEventSignalState;\r
+\r
+  BOOLEAN                            KeyEventSignalState;\r
+  BOOLEAN                            InputEventSignalState;\r
+  EFI_EVENT                          ConnectConInEvent;\r
+} TEXT_IN_SPLITTER_PRIVATE_DATA;\r
+\r
+#define TEXT_IN_SPLITTER_PRIVATE_DATA_FROM_THIS(a)  \\r
+  CR ((a),                                          \\r
+      TEXT_IN_SPLITTER_PRIVATE_DATA,                \\r
+      TextIn,                                       \\r
+      TEXT_IN_SPLITTER_PRIVATE_DATA_SIGNATURE       \\r
+      )\r
+\r
+#define TEXT_IN_SPLITTER_PRIVATE_DATA_FROM_SIMPLE_POINTER_THIS(a) \\r
+  CR ((a),                                                        \\r
+      TEXT_IN_SPLITTER_PRIVATE_DATA,                              \\r
+      SimplePointer,                                              \\r
+      TEXT_IN_SPLITTER_PRIVATE_DATA_SIGNATURE                     \\r
+      )\r
+#define TEXT_IN_EX_SPLITTER_PRIVATE_DATA_FROM_THIS(a) \\r
+  CR (a,                                              \\r
+      TEXT_IN_SPLITTER_PRIVATE_DATA,                  \\r
+      TextInEx,                                       \\r
+      TEXT_IN_SPLITTER_PRIVATE_DATA_SIGNATURE         \\r
+      )\r
+\r
+#define TEXT_IN_SPLITTER_PRIVATE_DATA_FROM_ABSOLUTE_POINTER_THIS(a) \\r
+  CR (a,                                                            \\r
+      TEXT_IN_SPLITTER_PRIVATE_DATA,                                \\r
+      AbsolutePointer,                                              \\r
+      TEXT_IN_SPLITTER_PRIVATE_DATA_SIGNATURE                       \\r
+      )\r
+\r
+\r
+#define TEXT_OUT_SPLITTER_PRIVATE_DATA_SIGNATURE  SIGNATURE_32 ('T', 'o', 'S', 'p')\r
+\r
+typedef struct {\r
+  EFI_GRAPHICS_OUTPUT_PROTOCOL     *GraphicsOutput;\r
+  EFI_UGA_DRAW_PROTOCOL            *UgaDraw;\r
+  EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL  *TextOut;\r
+} TEXT_OUT_AND_GOP_DATA;\r
+\r
+//\r
+// Private data for the Console Out splitter\r
+//\r
+typedef struct {\r
+  UINT64                                Signature;\r
+  EFI_HANDLE                            VirtualHandle;\r
+  EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL       TextOut;\r
+  EFI_SIMPLE_TEXT_OUTPUT_MODE           TextOutMode;\r
+\r
+  EFI_UGA_DRAW_PROTOCOL                 UgaDraw;\r
+  UINT32                                UgaHorizontalResolution;\r
+  UINT32                                UgaVerticalResolution;\r
+  UINT32                                UgaColorDepth;\r
+  UINT32                                UgaRefreshRate;\r
+\r
+  EFI_GRAPHICS_OUTPUT_PROTOCOL          GraphicsOutput;\r
+  EFI_GRAPHICS_OUTPUT_MODE_INFORMATION  *GraphicsOutputModeBuffer;\r
+  UINTN                                 CurrentNumberOfGraphicsOutput;\r
+  UINTN                                 CurrentNumberOfUgaDraw;\r
+\r
+  UINTN                                 CurrentNumberOfConsoles;\r
+  TEXT_OUT_AND_GOP_DATA                 *TextOutList;\r
+  UINTN                                 TextOutListCount;\r
+  TEXT_OUT_SPLITTER_QUERY_DATA          *TextOutQueryData;\r
+  UINTN                                 TextOutQueryDataCount;\r
+  INT32                                 *TextOutModeMap;\r
+\r
+} TEXT_OUT_SPLITTER_PRIVATE_DATA;\r
+\r
+#define TEXT_OUT_SPLITTER_PRIVATE_DATA_FROM_THIS(a) \\r
+  CR ((a),                                          \\r
+      TEXT_OUT_SPLITTER_PRIVATE_DATA,               \\r
+      TextOut,                                      \\r
+      TEXT_OUT_SPLITTER_PRIVATE_DATA_SIGNATURE      \\r
+      )\r
+\r
+#define GRAPHICS_OUTPUT_SPLITTER_PRIVATE_DATA_FROM_THIS(a)  \\r
+  CR ((a),                                                  \\r
+      TEXT_OUT_SPLITTER_PRIVATE_DATA,                       \\r
+      GraphicsOutput,                                       \\r
+      TEXT_OUT_SPLITTER_PRIVATE_DATA_SIGNATURE              \\r
+      )\r
+\r
+#define UGA_DRAW_SPLITTER_PRIVATE_DATA_FROM_THIS(a) \\r
+  CR ((a),                                          \\r
+      TEXT_OUT_SPLITTER_PRIVATE_DATA,               \\r
+      UgaDraw,                                      \\r
+      TEXT_OUT_SPLITTER_PRIVATE_DATA_SIGNATURE      \\r
+      )\r
+\r
+#define CONSOLE_CONTROL_SPLITTER_PRIVATE_DATA_FROM_THIS(a)  \\r
+  CR ((a),                                                  \\r
+      TEXT_OUT_SPLITTER_PRIVATE_DATA,                       \\r
+      ConsoleControl,                                       \\r
+      TEXT_OUT_SPLITTER_PRIVATE_DATA_SIGNATURE              \\r
+      )\r
+\r
+//\r
+// Function Prototypes\r
+//\r
+\r
+/**\r
+  The user Entry Point for module ConSplitter. The user code starts with this function.\r
+\r
+  Installs driver module protocols and. Creates virtual device handles for ConIn,\r
+  ConOut, and StdErr. Installs Simple Text In protocol, Simple Text In Ex protocol,\r
+  Simple Pointer protocol, Absolute Pointer protocol on those virtual handlers.\r
+  Installs Graphics Output protocol and/or UGA Draw protocol if needed.\r
+\r
+  @param[in] ImageHandle    The firmware allocated handle for the EFI image.\r
+  @param[in] SystemTable    A pointer to the EFI System Table.\r
+\r
+  @retval EFI_SUCCESS       The entry point is executed successfully.\r
+  @retval other             Some error occurs when executing this entry point.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+ConSplitterDriverEntry (\r
+  IN EFI_HANDLE                       ImageHandle,\r
+  IN EFI_SYSTEM_TABLE                 *SystemTable\r
+  );\r
+\r
+/**\r
+  Construct console input devices' private data.\r
+\r
+  @param  ConInPrivate             A pointer to the TEXT_IN_SPLITTER_PRIVATE_DATA\r
+                                   structure.\r
+\r
+  @retval EFI_OUT_OF_RESOURCES     Out of resources.\r
+  @retval EFI_SUCCESS              Text Input Devcie's private data has been constructed.\r
+  @retval other                    Failed to construct private data.\r
+\r
+**/\r
+EFI_STATUS\r
+ConSplitterTextInConstructor (\r
+  TEXT_IN_SPLITTER_PRIVATE_DATA       *ConInPrivate\r
+  );\r
+\r
+/**\r
+  Construct console output devices' private data.\r
+\r
+  @param  ConOutPrivate            A pointer to the TEXT_OUT_SPLITTER_PRIVATE_DATA\r
+                                   structure.\r
+\r
+  @retval EFI_OUT_OF_RESOURCES     Out of resources.\r
+  @retval EFI_SUCCESS              Text Input Devcie's private data has been constructed.\r
+\r
+**/\r
+EFI_STATUS\r
+ConSplitterTextOutConstructor (\r
+  TEXT_OUT_SPLITTER_PRIVATE_DATA      *ConOutPrivate\r
+  );\r
+\r
+\r
+/**\r
+  Test to see if Console In Device could be supported on the Controller.\r
+\r
+  @param  This                Driver Binding protocol instance pointer.\r
+  @param  ControllerHandle    Handle of device to test.\r
+  @param  RemainingDevicePath Optional parameter use to pick a specific child\r
+                              device to start.\r
+\r
+  @retval EFI_SUCCESS         This driver supports this device.\r
+  @retval other               This driver does not support this device.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+ConSplitterConInDriverBindingSupported (\r
+  IN  EFI_DRIVER_BINDING_PROTOCOL     *This,\r
+  IN  EFI_HANDLE                      ControllerHandle,\r
+  IN  EFI_DEVICE_PATH_PROTOCOL        *RemainingDevicePath\r
+  );\r
+\r
+/**\r
+  Test to see if Simple Pointer protocol could be supported on the Controller.\r
+\r
+  @param  This                Driver Binding protocol instance pointer.\r
+  @param  ControllerHandle    Handle of device to test.\r
+  @param  RemainingDevicePath Optional parameter use to pick a specific child\r
+                              device to start.\r
+\r
+  @retval EFI_SUCCESS         This driver supports this device.\r
+  @retval other               This driver does not support this device.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+ConSplitterSimplePointerDriverBindingSupported (\r
+  IN  EFI_DRIVER_BINDING_PROTOCOL     *This,\r
+  IN  EFI_HANDLE                      ControllerHandle,\r
+  IN  EFI_DEVICE_PATH_PROTOCOL        *RemainingDevicePath\r
+  );\r
+\r
+/**\r
+  Test to see if Console Out Device could be supported on the Controller.\r
+\r
+  @param  This                Driver Binding protocol instance pointer.\r
+  @param  ControllerHandle    Handle of device to test.\r
+  @param  RemainingDevicePath Optional parameter use to pick a specific child\r
+                              device to start.\r
+\r
+  @retval EFI_SUCCESS         This driver supports this device.\r
+  @retval other               This driver does not support this device.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+ConSplitterConOutDriverBindingSupported (\r
+  IN  EFI_DRIVER_BINDING_PROTOCOL     *This,\r
+  IN  EFI_HANDLE                      ControllerHandle,\r
+  IN  EFI_DEVICE_PATH_PROTOCOL        *RemainingDevicePath\r
+  );\r
+\r
+/**\r
+  Test to see if Standard Error Device could be supported on the Controller.\r
+\r
+  @param  This                Driver Binding protocol instance pointer.\r
+  @param  ControllerHandle    Handle of device to test.\r
+  @param  RemainingDevicePath Optional parameter use to pick a specific child\r
+                              device to start.\r
+\r
+  @retval EFI_SUCCESS         This driver supports this device.\r
+  @retval other               This driver does not support this device.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+ConSplitterStdErrDriverBindingSupported (\r
+  IN  EFI_DRIVER_BINDING_PROTOCOL     *This,\r
+  IN  EFI_HANDLE                      ControllerHandle,\r
+  IN  EFI_DEVICE_PATH_PROTOCOL        *RemainingDevicePath\r
+  );\r
+\r
+/**\r
+  Start Console In Consplitter on device handle.\r
+\r
+  @param  This                 Driver Binding protocol instance pointer.\r
+  @param  ControllerHandle     Handle of device to bind driver to.\r
+  @param  RemainingDevicePath  Optional parameter use to pick a specific child\r
+                               device to start.\r
+\r
+  @retval EFI_SUCCESS          Console In Consplitter is added to ControllerHandle.\r
+  @retval other                Console In Consplitter does not support this device.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+ConSplitterConInDriverBindingStart (\r
+  IN  EFI_DRIVER_BINDING_PROTOCOL     *This,\r
+  IN  EFI_HANDLE                      ControllerHandle,\r
+  IN  EFI_DEVICE_PATH_PROTOCOL        *RemainingDevicePath\r
+  );\r
+\r
+/**\r
+  Start Simple Pointer Consplitter on device handle.\r
+\r
+  @param  This                 Driver Binding protocol instance pointer.\r
+  @param  ControllerHandle     Handle of device to bind driver to.\r
+  @param  RemainingDevicePath  Optional parameter use to pick a specific child\r
+                               device to start.\r
+\r
+  @retval EFI_SUCCESS          Simple Pointer Consplitter is added to ControllerHandle.\r
+  @retval other                Simple Pointer Consplitter does not support this device.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+ConSplitterSimplePointerDriverBindingStart (\r
+  IN  EFI_DRIVER_BINDING_PROTOCOL     *This,\r
+  IN  EFI_HANDLE                      ControllerHandle,\r
+  IN  EFI_DEVICE_PATH_PROTOCOL        *RemainingDevicePath\r
+  );\r
+\r
+/**\r
+  Start Console Out Consplitter on device handle.\r
+\r
+  @param  This                 Driver Binding protocol instance pointer.\r
+  @param  ControllerHandle     Handle of device to bind driver to.\r
+  @param  RemainingDevicePath  Optional parameter use to pick a specific child\r
+                               device to start.\r
+\r
+  @retval EFI_SUCCESS          Console Out Consplitter is added to ControllerHandle.\r
+  @retval other                Console Out Consplitter does not support this device.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+ConSplitterConOutDriverBindingStart (\r
+  IN  EFI_DRIVER_BINDING_PROTOCOL     *This,\r
+  IN  EFI_HANDLE                      ControllerHandle,\r
+  IN  EFI_DEVICE_PATH_PROTOCOL        *RemainingDevicePath\r
+  );\r
+\r
+/**\r
+  Start Standard Error Consplitter on device handle.\r
+\r
+  @param  This                 Driver Binding protocol instance pointer.\r
+  @param  ControllerHandle     Handle of device to bind driver to.\r
+  @param  RemainingDevicePath  Optional parameter use to pick a specific child\r
+                               device to start.\r
+\r
+  @retval EFI_SUCCESS          Standard Error Consplitter is added to ControllerHandle.\r
+  @retval other                Standard Error Consplitter does not support this device.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+ConSplitterStdErrDriverBindingStart (\r
+  IN  EFI_DRIVER_BINDING_PROTOCOL     *This,\r
+  IN  EFI_HANDLE                      ControllerHandle,\r
+  IN  EFI_DEVICE_PATH_PROTOCOL        *RemainingDevicePath\r
+  );\r
+\r
+/**\r
+  Stop Console In ConSplitter on ControllerHandle by closing Console In Devcice GUID.\r
+\r
+  @param  This              Driver Binding protocol instance pointer.\r
+  @param  ControllerHandle  Handle of device to stop driver on\r
+  @param  NumberOfChildren  Number of Handles in ChildHandleBuffer. If number of\r
+                            children is zero stop the entire bus driver.\r
+  @param  ChildHandleBuffer List of Child Handles to Stop.\r
+\r
+  @retval EFI_SUCCESS       This driver is removed ControllerHandle\r
+  @retval other             This driver was not removed from this device\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+ConSplitterConInDriverBindingStop (\r
+  IN  EFI_DRIVER_BINDING_PROTOCOL     *This,\r
+  IN  EFI_HANDLE                      ControllerHandle,\r
+  IN  UINTN                           NumberOfChildren,\r
+  IN  EFI_HANDLE                      *ChildHandleBuffer\r
+  );\r
+\r
+/**\r
+  Stop Simple Pointer protocol ConSplitter on ControllerHandle by closing\r
+  Simple Pointer protocol.\r
+\r
+  @param  This              Driver Binding protocol instance pointer.\r
+  @param  ControllerHandle  Handle of device to stop driver on\r
+  @param  NumberOfChildren  Number of Handles in ChildHandleBuffer. If number of\r
+                            children is zero stop the entire bus driver.\r
+  @param  ChildHandleBuffer List of Child Handles to Stop.\r
+\r
+  @retval EFI_SUCCESS       This driver is removed ControllerHandle\r
+  @retval other             This driver was not removed from this device\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+ConSplitterSimplePointerDriverBindingStop (\r
+  IN  EFI_DRIVER_BINDING_PROTOCOL     *This,\r
+  IN  EFI_HANDLE                      ControllerHandle,\r
+  IN  UINTN                           NumberOfChildren,\r
+  IN  EFI_HANDLE                      *ChildHandleBuffer\r
+  );\r
+\r
+/**\r
+  Stop Console Out ConSplitter on device handle by closing Console Out Devcice GUID.\r
+\r
+  @param  This              Driver Binding protocol instance pointer.\r
+  @param  ControllerHandle  Handle of device to stop driver on\r
+  @param  NumberOfChildren  Number of Handles in ChildHandleBuffer. If number of\r
+                            children is zero stop the entire bus driver.\r
+  @param  ChildHandleBuffer List of Child Handles to Stop.\r
+\r
+  @retval EFI_SUCCESS       This driver is removed ControllerHandle\r
+  @retval other             This driver was not removed from this device\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+ConSplitterConOutDriverBindingStop (\r
+  IN  EFI_DRIVER_BINDING_PROTOCOL     *This,\r
+  IN  EFI_HANDLE                      ControllerHandle,\r
+  IN  UINTN                           NumberOfChildren,\r
+  IN  EFI_HANDLE                      *ChildHandleBuffer\r
+  );\r
+\r
+/**\r
+  Stop Standard Error ConSplitter on ControllerHandle by closing Standard Error GUID.\r
+\r
+  @param  This              Driver Binding protocol instance pointer.\r
+  @param  ControllerHandle  Handle of device to stop driver on\r
+  @param  NumberOfChildren  Number of Handles in ChildHandleBuffer. If number of\r
+                            children is zero stop the entire bus driver.\r
+  @param  ChildHandleBuffer List of Child Handles to Stop.\r
+\r
+  @retval EFI_SUCCESS       This driver is removed ControllerHandle\r
+  @retval other             This driver was not removed from this device\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+ConSplitterStdErrDriverBindingStop (\r
+  IN  EFI_DRIVER_BINDING_PROTOCOL     *This,\r
+  IN  EFI_HANDLE                      ControllerHandle,\r
+  IN  UINTN                           NumberOfChildren,\r
+  IN  EFI_HANDLE                      *ChildHandleBuffer\r
+  );\r
+\r
+\r
+/**\r
+  Test to see if Absolute Pointer protocol could be supported on the Controller.\r
+\r
+  @param  This                Driver Binding protocol instance pointer.\r
+  @param  ControllerHandle    Handle of device to test.\r
+  @param  RemainingDevicePath Optional parameter use to pick a specific child\r
+                              device to start.\r
+\r
+  @retval EFI_SUCCESS         This driver supports this device.\r
+  @retval other               This driver does not support this device.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+ConSplitterAbsolutePointerDriverBindingSupported (\r
+  IN  EFI_DRIVER_BINDING_PROTOCOL     *This,\r
+  IN  EFI_HANDLE                      ControllerHandle,\r
+  IN  EFI_DEVICE_PATH_PROTOCOL        *RemainingDevicePath\r
+  );\r
+\r
+/**\r
+  Start Absolute Pointer Consplitter on device handle.\r
+\r
+  @param  This                 Driver Binding protocol instance pointer.\r
+  @param  ControllerHandle     Handle of device to bind driver to.\r
+  @param  RemainingDevicePath  Optional parameter use to pick a specific child\r
+                               device to start.\r
+\r
+  @retval EFI_SUCCESS          Absolute Pointer Consplitter is added to ControllerHandle.\r
+  @retval other                Absolute Pointer Consplitter does not support this device.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+ConSplitterAbsolutePointerDriverBindingStart (\r
+  IN  EFI_DRIVER_BINDING_PROTOCOL     *This,\r
+  IN  EFI_HANDLE                      ControllerHandle,\r
+  IN  EFI_DEVICE_PATH_PROTOCOL        *RemainingDevicePath\r
+  );\r
+\r
+/**\r
+  Stop Absolute Pointer protocol ConSplitter on ControllerHandle by closing\r
+  Absolute Pointer protocol.\r
+\r
+  @param  This              Driver Binding protocol instance pointer.\r
+  @param  ControllerHandle  Handle of device to stop driver on\r
+  @param  NumberOfChildren  Number of Handles in ChildHandleBuffer. If number of\r
+                            children is zero stop the entire bus driver.\r
+  @param  ChildHandleBuffer List of Child Handles to Stop.\r
+\r
+  @retval EFI_SUCCESS       This driver is removed ControllerHandle\r
+  @retval other             This driver was not removed from this device\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+ConSplitterAbsolutePointerDriverBindingStop (\r
+  IN  EFI_DRIVER_BINDING_PROTOCOL     *This,\r
+  IN  EFI_HANDLE                      ControllerHandle,\r
+  IN  UINTN                           NumberOfChildren,\r
+  IN  EFI_HANDLE                      *ChildHandleBuffer\r
+  );\r
+\r
+/**\r
+  Add Absolute Pointer Device in Consplitter Absolute Pointer list.\r
+\r
+  @param  Private                  Text In Splitter pointer.\r
+  @param  AbsolutePointer          Absolute Pointer protocol pointer.\r
+\r
+  @retval EFI_SUCCESS              Absolute Pointer Device added successfully.\r
+  @retval EFI_OUT_OF_RESOURCES     Could not grow the buffer size.\r
+\r
+**/\r
+EFI_STATUS\r
+ConSplitterAbsolutePointerAddDevice (\r
+  IN  TEXT_IN_SPLITTER_PRIVATE_DATA     *Private,\r
+  IN  EFI_ABSOLUTE_POINTER_PROTOCOL     *AbsolutePointer\r
+  );\r
+\r
+/**\r
+  Remove Absolute Pointer Device from Consplitter Absolute Pointer list.\r
+\r
+  @param  Private                  Text In Splitter pointer.\r
+  @param  AbsolutePointer          Absolute Pointer protocol pointer.\r
+\r
+  @retval EFI_SUCCESS              Absolute Pointer Device removed successfully.\r
+  @retval EFI_NOT_FOUND            No Absolute Pointer Device found.\r
+\r
+**/\r
+EFI_STATUS\r
+ConSplitterAbsolutePointerDeleteDevice (\r
+  IN  TEXT_IN_SPLITTER_PRIVATE_DATA     *Private,\r
+  IN  EFI_ABSOLUTE_POINTER_PROTOCOL     *AbsolutePointer\r
+  );\r
+\r
+//\r
+// Absolute Pointer protocol interfaces\r
+//\r
+\r
+\r
+/**\r
+  Resets the pointer device hardware.\r
+\r
+  @param  This                     Protocol instance pointer.\r
+  @param  ExtendedVerification     Driver may perform diagnostics on reset.\r
+\r
+  @retval EFI_SUCCESS              The device was reset.\r
+  @retval EFI_DEVICE_ERROR         The device is not functioning correctly and\r
+                                   could not be reset.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+ConSplitterAbsolutePointerReset (\r
+  IN EFI_ABSOLUTE_POINTER_PROTOCOL   *This,\r
+  IN BOOLEAN                         ExtendedVerification\r
+  );\r
+\r
+\r
+/**\r
+  Retrieves the current state of a pointer device.\r
+\r
+  @param  This                     Protocol instance pointer.\r
+  @param  State                    A pointer to the state information on the\r
+                                   pointer device.\r
+\r
+  @retval EFI_SUCCESS              The state of the pointer device was returned in\r
+                                   State..\r
+  @retval EFI_NOT_READY            The state of the pointer device has not changed\r
+                                   since the last call to GetState().\r
+  @retval EFI_DEVICE_ERROR         A device error occurred while attempting to\r
+                                   retrieve the pointer device's current state.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+ConSplitterAbsolutePointerGetState (\r
+  IN EFI_ABSOLUTE_POINTER_PROTOCOL   *This,\r
+  IN OUT EFI_ABSOLUTE_POINTER_STATE  *State\r
+  );\r
+\r
+/**\r
+  This event agregates all the events of the pointer devices in the splitter.\r
+\r
+  If any events of physical pointer devices are signaled, signal the pointer\r
+  splitter event. This will cause the calling code to call\r
+  ConSplitterAbsolutePointerGetState ().\r
+\r
+  @param  Event                    The Event assoicated with callback.\r
+  @param  Context                  Context registered when Event was created.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+ConSplitterAbsolutePointerWaitForInput (\r
+  IN  EFI_EVENT                       Event,\r
+  IN  VOID                            *Context\r
+  );\r
+\r
+/**\r
+  Retrieves a Unicode string that is the user readable name of the driver.\r
+\r
+  This function retrieves the user readable name of a driver in the form of a\r
+  Unicode string. If the driver specified by This has a user readable name in\r
+  the language specified by Language, then a pointer to the driver name is\r
+  returned in DriverName, and EFI_SUCCESS is returned. If the driver specified\r
+  by This does not support the language specified by Language,\r
+  then EFI_UNSUPPORTED is returned.\r
+\r
+  @param  This[in]              A pointer to the EFI_COMPONENT_NAME2_PROTOCOL or\r
+                                EFI_COMPONENT_NAME_PROTOCOL instance.\r
+\r
+  @param  Language[in]          A pointer to a Null-terminated ASCII string\r
+                                array indicating the language. This is the\r
+                                language of the driver name that the caller is\r
+                                requesting, and it must match one of the\r
+                                languages specified in SupportedLanguages. The\r
+                                number of languages supported by a driver is up\r
+                                to the driver writer. Language is specified\r
+                                in RFC 4646 or ISO 639-2 language code format.\r
+\r
+  @param  DriverName[out]       A pointer to the Unicode string to return.\r
+                                This Unicode string is the name of the\r
+                                driver specified by This in the language\r
+                                specified by Language.\r
+\r
+  @retval EFI_SUCCESS           The Unicode string for the Driver specified by\r
+                                This and the language specified by Language was\r
+                                returned in DriverName.\r
+\r
+  @retval EFI_INVALID_PARAMETER Language is NULL.\r
+\r
+  @retval EFI_INVALID_PARAMETER DriverName is NULL.\r
+\r
+  @retval EFI_UNSUPPORTED       The driver specified by This does not support\r
+                                the language specified by Language.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+ConSplitterComponentNameGetDriverName (\r
+  IN  EFI_COMPONENT_NAME_PROTOCOL  *This,\r
+  IN  CHAR8                        *Language,\r
+  OUT CHAR16                       **DriverName\r
+  );\r
+\r
+\r
+/**\r
+  Retrieves a Unicode string that is the user readable name of the controller\r
+  that is being managed by a driver.\r
+\r
+  This function retrieves the user readable name of the controller specified by\r
+  ControllerHandle and ChildHandle in the form of a Unicode string. If the\r
+  driver specified by This has a user readable name in the language specified by\r
+  Language, then a pointer to the controller name is returned in ControllerName,\r
+  and EFI_SUCCESS is returned.  If the driver specified by This is not currently\r
+  managing the controller specified by ControllerHandle and ChildHandle,\r
+  then EFI_UNSUPPORTED is returned.  If the driver specified by This does not\r
+  support the language specified by Language, then EFI_UNSUPPORTED is returned.\r
+\r
+  @param  This[in]              A pointer to the EFI_COMPONENT_NAME2_PROTOCOL or\r
+                                EFI_COMPONENT_NAME_PROTOCOL instance.\r
+\r
+  @param  ControllerHandle[in]  The handle of a controller that the driver\r
+                                specified by This is managing.  This handle\r
+                                specifies the controller whose name is to be\r
+                                returned.\r
+\r
+  @param  ChildHandle[in]       The handle of the child controller to retrieve\r
+                                the name of.  This is an optional parameter that\r
+                                may be NULL.  It will be NULL for device\r
+                                drivers.  It will also be NULL for a bus drivers\r
+                                that wish to retrieve the name of the bus\r
+                                controller.  It will not be NULL for a bus\r
+                                driver that wishes to retrieve the name of a\r
+                                child controller.\r
+\r
+  @param  Language[in]          A pointer to a Null-terminated ASCII string\r
+                                array indicating the language.  This is the\r
+                                language of the driver name that the caller is\r
+                                requesting, and it must match one of the\r
+                                languages specified in SupportedLanguages. The\r
+                                number of languages supported by a driver is up\r
+                                to the driver writer. Language is specified in\r
+                                RFC 4646 or ISO 639-2 language code format.\r
+\r
+  @param  ControllerName[out]   A pointer to the Unicode string to return.\r
+                                This Unicode string is the name of the\r
+                                controller specified by ControllerHandle and\r
+                                ChildHandle in the language specified by\r
+                                Language from the point of view of the driver\r
+                                specified by This.\r
+\r
+  @retval EFI_SUCCESS           The Unicode string for the user readable name in\r
+                                the language specified by Language for the\r
+                                driver specified by This was returned in\r
+                                DriverName.\r
+\r
+  @retval EFI_INVALID_PARAMETER ControllerHandle is NULL.\r
+\r
+  @retval EFI_INVALID_PARAMETER ChildHandle is not NULL and it is not a valid\r
+                                EFI_HANDLE.\r
+\r
+  @retval EFI_INVALID_PARAMETER Language is NULL.\r
+\r
+  @retval EFI_INVALID_PARAMETER ControllerName is NULL.\r
+\r
+  @retval EFI_UNSUPPORTED       The driver specified by This is not currently\r
+                                managing the controller specified by\r
+                                ControllerHandle and ChildHandle.\r
+\r
+  @retval EFI_UNSUPPORTED       The driver specified by This does not support\r
+                                the language specified by Language.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+ConSplitterConInComponentNameGetControllerName (\r
+  IN  EFI_COMPONENT_NAME_PROTOCOL                     *This,\r
+  IN  EFI_HANDLE                                      ControllerHandle,\r
+  IN  EFI_HANDLE                                      ChildHandle        OPTIONAL,\r
+  IN  CHAR8                                           *Language,\r
+  OUT CHAR16                                          **ControllerName\r
+  );\r
+\r
+\r
+/**\r
+  Retrieves a Unicode string that is the user readable name of the controller\r
+  that is being managed by a driver.\r
+\r
+  This function retrieves the user readable name of the controller specified by\r
+  ControllerHandle and ChildHandle in the form of a Unicode string. If the\r
+  driver specified by This has a user readable name in the language specified by\r
+  Language, then a pointer to the controller name is returned in ControllerName,\r
+  and EFI_SUCCESS is returned.  If the driver specified by This is not currently\r
+  managing the controller specified by ControllerHandle and ChildHandle,\r
+  then EFI_UNSUPPORTED is returned.  If the driver specified by This does not\r
+  support the language specified by Language, then EFI_UNSUPPORTED is returned.\r
+\r
+  @param  This[in]              A pointer to the EFI_COMPONENT_NAME2_PROTOCOL or\r
+                                EFI_COMPONENT_NAME_PROTOCOL instance.\r
+\r
+  @param  ControllerHandle[in]  The handle of a controller that the driver\r
+                                specified by This is managing.  This handle\r
+                                specifies the controller whose name is to be\r
+                                returned.\r
+\r
+  @param  ChildHandle[in]       The handle of the child controller to retrieve\r
+                                the name of.  This is an optional parameter that\r
+                                may be NULL.  It will be NULL for device\r
+                                drivers.  It will also be NULL for a bus drivers\r
+                                that wish to retrieve the name of the bus\r
+                                controller.  It will not be NULL for a bus\r
+                                driver that wishes to retrieve the name of a\r
+                                child controller.\r
+\r
+  @param  Language[in]          A pointer to a Null-terminated ASCII string\r
+                                array indicating the language.  This is the\r
+                                language of the driver name that the caller is\r
+                                requesting, and it must match one of the\r
+                                languages specified in SupportedLanguages. The\r
+                                number of languages supported by a driver is up\r
+                                to the driver writer. Language is specified in\r
+                                RFC 4646 or ISO 639-2 language code format.\r
+\r
+  @param  ControllerName[out]   A pointer to the Unicode string to return.\r
+                                This Unicode string is the name of the\r
+                                controller specified by ControllerHandle and\r
+                                ChildHandle in the language specified by\r
+                                Language from the point of view of the driver\r
+                                specified by This.\r
+\r
+  @retval EFI_SUCCESS           The Unicode string for the user readable name in\r
+                                the language specified by Language for the\r
+                                driver specified by This was returned in\r
+                                DriverName.\r
+\r
+  @retval EFI_INVALID_PARAMETER ControllerHandle is NULL.\r
+\r
+  @retval EFI_INVALID_PARAMETER ChildHandle is not NULL and it is not a valid\r
+                                EFI_HANDLE.\r
+\r
+  @retval EFI_INVALID_PARAMETER Language is NULL.\r
+\r
+  @retval EFI_INVALID_PARAMETER ControllerName is NULL.\r
+\r
+  @retval EFI_UNSUPPORTED       The driver specified by This is not currently\r
+                                managing the controller specified by\r
+                                ControllerHandle and ChildHandle.\r
+\r
+  @retval EFI_UNSUPPORTED       The driver specified by This does not support\r
+                                the language specified by Language.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+ConSplitterSimplePointerComponentNameGetControllerName (\r
+  IN  EFI_COMPONENT_NAME_PROTOCOL                     *This,\r
+  IN  EFI_HANDLE                                      ControllerHandle,\r
+  IN  EFI_HANDLE                                      ChildHandle        OPTIONAL,\r
+  IN  CHAR8                                           *Language,\r
+  OUT CHAR16                                          **ControllerName\r
+  );\r
+\r
+/**\r
+  Retrieves a Unicode string that is the user readable name of the controller\r
+  that is being managed by an EFI Driver.\r
+\r
+  @param  This                   A pointer to the EFI_COMPONENT_NAME_PROTOCOL\r
+                                 instance.\r
+  @param  ControllerHandle       The handle of a controller that the driver\r
+                                 specified by This is managing.  This handle\r
+                                 specifies the controller whose name is to be\r
+                                 returned.\r
+  @param  ChildHandle            The handle of the child controller to retrieve the\r
+                                 name of.  This is an optional parameter that may\r
+                                 be NULL.  It will be NULL for device drivers.  It\r
+                                 will also be NULL for a bus drivers that wish to\r
+                                 retrieve the name of the bus controller.  It will\r
+                                 not be NULL for a bus driver that wishes to\r
+                                 retrieve the name of a child controller.\r
+  @param  Language               A pointer to RFC4646 language identifier. This is\r
+                                 the language of the controller name that that the\r
+                                 caller is requesting, and it must match one of the\r
+                                 languages specified in SupportedLanguages.  The\r
+                                 number of languages supported by a driver is up to\r
+                                 the driver writer.\r
+  @param  ControllerName         A pointer to the Unicode string to return.  This\r
+                                 Unicode string is the name of the controller\r
+                                 specified by ControllerHandle and ChildHandle in\r
+                                 the language specified by Language from the point\r
+                                 of view of the driver specified by This.\r
+\r
+  @retval EFI_SUCCESS            The Unicode string for the user readable name in\r
+                                 the language specified by Language for the driver\r
+                                 specified by This was returned in DriverName.\r
+  @retval EFI_INVALID_PARAMETER  ControllerHandle is NULL.\r
+  @retval EFI_INVALID_PARAMETER  ChildHandle is not NULL and it is not a valid\r
+                                 EFI_HANDLE.\r
+  @retval EFI_INVALID_PARAMETER  Language is NULL.\r
+  @retval EFI_INVALID_PARAMETER  ControllerName is NULL.\r
+  @retval EFI_UNSUPPORTED        The driver specified by This is not currently\r
+                                 managing the controller specified by\r
+                                 ControllerHandle and ChildHandle.\r
+  @retval EFI_UNSUPPORTED        The driver specified by This does not support the\r
+                                 language specified by Language.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+ConSplitterAbsolutePointerComponentNameGetControllerName (\r
+  IN  EFI_COMPONENT_NAME_PROTOCOL                    *This,\r
+  IN  EFI_HANDLE                                      ControllerHandle,\r
+  IN  EFI_HANDLE                                      ChildHandle        OPTIONAL,\r
+  IN  CHAR8                                           *Language,\r
+  OUT CHAR16                                          **ControllerName\r
+  );\r
+\r
+/**\r
+  Retrieves a Unicode string that is the user readable name of the controller\r
+  that is being managed by a driver.\r
+\r
+  This function retrieves the user readable name of the controller specified by\r
+  ControllerHandle and ChildHandle in the form of a Unicode string. If the\r
+  driver specified by This has a user readable name in the language specified by\r
+  Language, then a pointer to the controller name is returned in ControllerName,\r
+  and EFI_SUCCESS is returned.  If the driver specified by This is not currently\r
+  managing the controller specified by ControllerHandle and ChildHandle,\r
+  then EFI_UNSUPPORTED is returned.  If the driver specified by This does not\r
+  support the language specified by Language, then EFI_UNSUPPORTED is returned.\r
+\r
+  @param  This[in]              A pointer to the EFI_COMPONENT_NAME2_PROTOCOL or\r
+                                EFI_COMPONENT_NAME_PROTOCOL instance.\r
+\r
+  @param  ControllerHandle[in]  The handle of a controller that the driver\r
+                                specified by This is managing.  This handle\r
+                                specifies the controller whose name is to be\r
+                                returned.\r
+\r
+  @param  ChildHandle[in]       The handle of the child controller to retrieve\r
+                                the name of.  This is an optional parameter that\r
+                                may be NULL.  It will be NULL for device\r
+                                drivers.  It will also be NULL for a bus drivers\r
+                                that wish to retrieve the name of the bus\r
+                                controller.  It will not be NULL for a bus\r
+                                driver that wishes to retrieve the name of a\r
+                                child controller.\r
+\r
+  @param  Language[in]          A pointer to a Null-terminated ASCII string\r
+                                array indicating the language.  This is the\r
+                                language of the driver name that the caller is\r
+                                requesting, and it must match one of the\r
+                                languages specified in SupportedLanguages. The\r
+                                number of languages supported by a driver is up\r
+                                to the driver writer. Language is specified in\r
+                                RFC 4646 or ISO 639-2 language code format.\r
+\r
+  @param  ControllerName[out]   A pointer to the Unicode string to return.\r
+                                This Unicode string is the name of the\r
+                                controller specified by ControllerHandle and\r
+                                ChildHandle in the language specified by\r
+                                Language from the point of view of the driver\r
+                                specified by This.\r
+\r
+  @retval EFI_SUCCESS           The Unicode string for the user readable name in\r
+                                the language specified by Language for the\r
+                                driver specified by This was returned in\r
+                                DriverName.\r
+\r
+  @retval EFI_INVALID_PARAMETER ControllerHandle is NULL.\r
+\r
+  @retval EFI_INVALID_PARAMETER ChildHandle is not NULL and it is not a valid\r
+                                EFI_HANDLE.\r
+\r
+  @retval EFI_INVALID_PARAMETER Language is NULL.\r
+\r
+  @retval EFI_INVALID_PARAMETER ControllerName is NULL.\r
+\r
+  @retval EFI_UNSUPPORTED       The driver specified by This is not currently\r
+                                managing the controller specified by\r
+                                ControllerHandle and ChildHandle.\r
+\r
+  @retval EFI_UNSUPPORTED       The driver specified by This does not support\r
+                                the language specified by Language.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+ConSplitterConOutComponentNameGetControllerName (\r
+  IN  EFI_COMPONENT_NAME_PROTOCOL                     *This,\r
+  IN  EFI_HANDLE                                      ControllerHandle,\r
+  IN  EFI_HANDLE                                      ChildHandle        OPTIONAL,\r
+  IN  CHAR8                                           *Language,\r
+  OUT CHAR16                                          **ControllerName\r
+  );\r
+\r
+\r
+/**\r
+  Retrieves a Unicode string that is the user readable name of the controller\r
+  that is being managed by a driver.\r
+\r
+  This function retrieves the user readable name of the controller specified by\r
+  ControllerHandle and ChildHandle in the form of a Unicode string. If the\r
+  driver specified by This has a user readable name in the language specified by\r
+  Language, then a pointer to the controller name is returned in ControllerName,\r
+  and EFI_SUCCESS is returned.  If the driver specified by This is not currently\r
+  managing the controller specified by ControllerHandle and ChildHandle,\r
+  then EFI_UNSUPPORTED is returned.  If the driver specified by This does not\r
+  support the language specified by Language, then EFI_UNSUPPORTED is returned.\r
+\r
+  @param  This[in]              A pointer to the EFI_COMPONENT_NAME2_PROTOCOL or\r
+                                EFI_COMPONENT_NAME_PROTOCOL instance.\r
+\r
+  @param  ControllerHandle[in]  The handle of a controller that the driver\r
+                                specified by This is managing.  This handle\r
+                                specifies the controller whose name is to be\r
+                                returned.\r
+\r
+  @param  ChildHandle[in]       The handle of the child controller to retrieve\r
+                                the name of.  This is an optional parameter that\r
+                                may be NULL.  It will be NULL for device\r
+                                drivers.  It will also be NULL for a bus drivers\r
+                                that wish to retrieve the name of the bus\r
+                                controller.  It will not be NULL for a bus\r
+                                driver that wishes to retrieve the name of a\r
+                                child controller.\r
+\r
+  @param  Language[in]          A pointer to a Null-terminated ASCII string\r
+                                array indicating the language.  This is the\r
+                                language of the driver name that the caller is\r
+                                requesting, and it must match one of the\r
+                                languages specified in SupportedLanguages. The\r
+                                number of languages supported by a driver is up\r
+                                to the driver writer. Language is specified in\r
+                                RFC 4646 or ISO 639-2 language code format.\r
+\r
+  @param  ControllerName[out]   A pointer to the Unicode string to return.\r
+                                This Unicode string is the name of the\r
+                                controller specified by ControllerHandle and\r
+                                ChildHandle in the language specified by\r
+                                Language from the point of view of the driver\r
+                                specified by This.\r
+\r
+  @retval EFI_SUCCESS           The Unicode string for the user readable name in\r
+                                the language specified by Language for the\r
+                                driver specified by This was returned in\r
+                                DriverName.\r
+\r
+  @retval EFI_INVALID_PARAMETER ControllerHandle is NULL.\r
+\r
+  @retval EFI_INVALID_PARAMETER ChildHandle is not NULL and it is not a valid\r
+                                EFI_HANDLE.\r
+\r
+  @retval EFI_INVALID_PARAMETER Language is NULL.\r
+\r
+  @retval EFI_INVALID_PARAMETER ControllerName is NULL.\r
+\r
+  @retval EFI_UNSUPPORTED       The driver specified by This is not currently\r
+                                managing the controller specified by\r
+                                ControllerHandle and ChildHandle.\r
+\r
+  @retval EFI_UNSUPPORTED       The driver specified by This does not support\r
+                                the language specified by Language.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+ConSplitterStdErrComponentNameGetControllerName (\r
+  IN  EFI_COMPONENT_NAME_PROTOCOL                     *This,\r
+  IN  EFI_HANDLE                                      ControllerHandle,\r
+  IN  EFI_HANDLE                                      ChildHandle        OPTIONAL,\r
+  IN  CHAR8                                           *Language,\r
+  OUT CHAR16                                          **ControllerName\r
+  );\r
+\r
+\r
+//\r
+// TextIn Constructor/Destructor functions\r
+//\r
+\r
+/**\r
+  Add Text Input Device in Consplitter Text Input list.\r
+\r
+  @param  Private                  Text In Splitter pointer.\r
+  @param  TextIn                   Simple Text Input protocol pointer.\r
+\r
+  @retval EFI_SUCCESS              Text Input Device added successfully.\r
+  @retval EFI_OUT_OF_RESOURCES     Could not grow the buffer size.\r
+\r
+**/\r
+EFI_STATUS\r
+ConSplitterTextInAddDevice (\r
+  IN  TEXT_IN_SPLITTER_PRIVATE_DATA   *Private,\r
+  IN  EFI_SIMPLE_TEXT_INPUT_PROTOCOL  *TextIn\r
+  );\r
+\r
+/**\r
+  Remove Text Input Device from Consplitter Text Input list.\r
+\r
+  @param  Private                  Text In Splitter pointer.\r
+  @param  TextIn                   Simple Text protocol pointer.\r
+\r
+  @retval EFI_SUCCESS              Simple Text Device removed successfully.\r
+  @retval EFI_NOT_FOUND            No Simple Text Device found.\r
+\r
+**/\r
+EFI_STATUS\r
+ConSplitterTextInDeleteDevice (\r
+  IN  TEXT_IN_SPLITTER_PRIVATE_DATA   *Private,\r
+  IN  EFI_SIMPLE_TEXT_INPUT_PROTOCOL  *TextIn\r
+  );\r
+\r
+//\r
+// SimplePointer Constuctor/Destructor functions\r
+//\r
+\r
+/**\r
+  Add Simple Pointer Device in Consplitter Simple Pointer list.\r
+\r
+  @param  Private                  Text In Splitter pointer.\r
+  @param  SimplePointer            Simple Pointer protocol pointer.\r
+\r
+  @retval EFI_SUCCESS              Simple Pointer Device added successfully.\r
+  @retval EFI_OUT_OF_RESOURCES     Could not grow the buffer size.\r
+\r
+**/\r
+EFI_STATUS\r
+ConSplitterSimplePointerAddDevice (\r
+  IN  TEXT_IN_SPLITTER_PRIVATE_DATA   *Private,\r
+  IN  EFI_SIMPLE_POINTER_PROTOCOL     *SimplePointer\r
+  );\r
+\r
+/**\r
+  Remove Simple Pointer Device from Consplitter Simple Pointer list.\r
+\r
+  @param  Private                  Text In Splitter pointer.\r
+  @param  SimplePointer            Simple Pointer protocol pointer.\r
+\r
+  @retval EFI_SUCCESS              Simple Pointer Device removed successfully.\r
+  @retval EFI_NOT_FOUND            No Simple Pointer Device found.\r
+\r
+**/\r
+EFI_STATUS\r
+ConSplitterSimplePointerDeleteDevice (\r
+  IN  TEXT_IN_SPLITTER_PRIVATE_DATA   *Private,\r
+  IN  EFI_SIMPLE_POINTER_PROTOCOL     *SimplePointer\r
+  );\r
+\r
+//\r
+// TextOut Constuctor/Destructor functions\r
+//\r
+\r
+/**\r
+  Add Text Output Device in Consplitter Text Output list.\r
+\r
+  @param  Private                  Text Out Splitter pointer.\r
+  @param  TextOut                  Simple Text Output protocol pointer.\r
+  @param  GraphicsOutput           Graphics Output protocol pointer.\r
+  @param  UgaDraw                  UGA Draw protocol pointer.\r
+\r
+  @retval EFI_SUCCESS              Text Output Device added successfully.\r
+  @retval EFI_OUT_OF_RESOURCES     Could not grow the buffer size.\r
+\r
+**/\r
+EFI_STATUS\r
+ConSplitterTextOutAddDevice (\r
+  IN  TEXT_OUT_SPLITTER_PRIVATE_DATA     *Private,\r
+  IN  EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL    *TextOut,\r
+  IN  EFI_GRAPHICS_OUTPUT_PROTOCOL       *GraphicsOutput,\r
+  IN  EFI_UGA_DRAW_PROTOCOL              *UgaDraw\r
+  );\r
+\r
+/**\r
+  Remove Text Out Device in Consplitter Text Out list.\r
+\r
+  @param  Private                  Text Out Splitter pointer.\r
+  @param  TextOut                  Simple Text Output Pointer protocol pointer.\r
+\r
+  @retval EFI_SUCCESS              Text Out Device removed successfully.\r
+  @retval EFI_NOT_FOUND            No Text Out Device found.\r
+\r
+**/\r
+EFI_STATUS\r
+ConSplitterTextOutDeleteDevice (\r
+  IN  TEXT_OUT_SPLITTER_PRIVATE_DATA     *Private,\r
+  IN  EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL    *TextOut\r
+  );\r
+\r
+//\r
+// TextIn I/O Functions\r
+//\r
+\r
+/**\r
+  Reset the input device and optionaly run diagnostics\r
+\r
+  @param  This                     Protocol instance pointer.\r
+  @param  ExtendedVerification     Driver may perform diagnostics on reset.\r
+\r
+  @retval EFI_SUCCESS              The device was reset.\r
+  @retval EFI_DEVICE_ERROR         The device is not functioning properly and could\r
+                                   not be reset.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+ConSplitterTextInReset (\r
+  IN  EFI_SIMPLE_TEXT_INPUT_PROTOCOL  *This,\r
+  IN  BOOLEAN                         ExtendedVerification\r
+  );\r
+\r
+/**\r
+  Reads the next keystroke from the input device. The WaitForKey Event can\r
+  be used to test for existance of a keystroke via WaitForEvent () call.\r
+\r
+  @param  This                     Protocol instance pointer.\r
+  @param  Key                      Driver may perform diagnostics on reset.\r
+\r
+  @retval EFI_SUCCESS              The keystroke information was returned.\r
+  @retval EFI_NOT_READY            There was no keystroke data availiable.\r
+  @retval EFI_DEVICE_ERROR         The keydtroke information was not returned due\r
+                                   to hardware errors.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+ConSplitterTextInReadKeyStroke (\r
+  IN  EFI_SIMPLE_TEXT_INPUT_PROTOCOL  *This,\r
+  OUT EFI_INPUT_KEY                   *Key\r
+  );\r
+\r
+/**\r
+  Add Text Input Ex Device in Consplitter Text Input Ex list.\r
+\r
+  @param  Private                  Text In Splitter pointer.\r
+  @param  TextInEx                 Simple Text Input Ex Input protocol pointer.\r
+\r
+  @retval EFI_SUCCESS              Text Input Ex Device added successfully.\r
+  @retval EFI_OUT_OF_RESOURCES     Could not grow the buffer size.\r
+\r
+**/\r
+EFI_STATUS\r
+ConSplitterTextInExAddDevice (\r
+  IN  TEXT_IN_SPLITTER_PRIVATE_DATA         *Private,\r
+  IN  EFI_SIMPLE_TEXT_INPUT_EX_PROTOCOL     *TextInEx\r
+  );\r
+\r
+/**\r
+  Remove Text Ex Device from Consplitter Text Input Ex list.\r
+\r
+  @param  Private                  Text In Splitter pointer.\r
+  @param  TextInEx                 Simple Text Ex protocol pointer.\r
+\r
+  @retval EFI_SUCCESS              Simple Text Input Ex Device removed successfully.\r
+  @retval EFI_NOT_FOUND            No Simple Text Input Ex Device found.\r
+\r
+**/\r
+EFI_STATUS\r
+ConSplitterTextInExDeleteDevice (\r
+  IN  TEXT_IN_SPLITTER_PRIVATE_DATA         *Private,\r
+  IN  EFI_SIMPLE_TEXT_INPUT_EX_PROTOCOL     *TextInEx\r
+  );\r
+\r
+//\r
+// Simple Text Input Ex protocol function prototypes\r
+//\r
+\r
+/**\r
+  Reset the input device and optionaly run diagnostics\r
+\r
+  @param  This                     Protocol instance pointer.\r
+  @param  ExtendedVerification     Driver may perform diagnostics on reset.\r
+\r
+  @retval EFI_SUCCESS              The device was reset.\r
+  @retval EFI_DEVICE_ERROR         The device is not functioning properly and could\r
+                                   not be reset.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+ConSplitterTextInResetEx (\r
+  IN EFI_SIMPLE_TEXT_INPUT_EX_PROTOCOL  *This,\r
+  IN BOOLEAN                            ExtendedVerification\r
+  );\r
+\r
+\r
+/**\r
+  Reads the next keystroke from the input device. The WaitForKey Event can\r
+  be used to test for existance of a keystroke via WaitForEvent () call.\r
+\r
+  @param  This                     Protocol instance pointer.\r
+  @param  KeyData                  A pointer to a buffer that is filled in with the\r
+                                   keystroke state data for the key that was\r
+                                   pressed.\r
+\r
+  @retval EFI_SUCCESS              The keystroke information was returned.\r
+  @retval EFI_NOT_READY            There was no keystroke data availiable.\r
+  @retval EFI_DEVICE_ERROR         The keystroke information was not returned due\r
+                                   to hardware errors.\r
+  @retval EFI_INVALID_PARAMETER    KeyData is NULL.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+ConSplitterTextInReadKeyStrokeEx (\r
+  IN  EFI_SIMPLE_TEXT_INPUT_EX_PROTOCOL *This,\r
+  OUT EFI_KEY_DATA                      *KeyData\r
+  );\r
+\r
+\r
+/**\r
+  Set certain state for the input device.\r
+\r
+  @param  This                     Protocol instance pointer.\r
+  @param  KeyToggleState           A pointer to the EFI_KEY_TOGGLE_STATE to set the\r
+                                   state for the input device.\r
+\r
+  @retval EFI_SUCCESS              The device state was set successfully.\r
+  @retval EFI_DEVICE_ERROR         The device is not functioning correctly and\r
+                                   could not have the setting adjusted.\r
+  @retval EFI_UNSUPPORTED          The device does not have the ability to set its\r
+                                   state.\r
+  @retval EFI_INVALID_PARAMETER    KeyToggleState is NULL.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+ConSplitterTextInSetState (\r
+  IN EFI_SIMPLE_TEXT_INPUT_EX_PROTOCOL  *This,\r
+  IN EFI_KEY_TOGGLE_STATE               *KeyToggleState\r
+  );\r
+\r
+\r
+/**\r
+  Register a notification function for a particular keystroke for the input device.\r
+\r
+  @param  This                     Protocol instance pointer.\r
+  @param  KeyData                  A pointer to a buffer that is filled in with the\r
+                                   keystroke information data for the key that was\r
+                                   pressed.\r
+  @param  KeyNotificationFunction  Points to the function to be called when the key\r
+                                   sequence is typed specified by KeyData.\r
+  @param  NotifyHandle             Points to the unique handle assigned to the\r
+                                   registered notification.\r
+\r
+  @retval EFI_SUCCESS              The notification function was registered\r
+                                   successfully.\r
+  @retval EFI_OUT_OF_RESOURCES     Unable to allocate resources for necesssary data\r
+                                   structures.\r
+  @retval EFI_INVALID_PARAMETER    KeyData or KeyNotificationFunction or NotifyHandle is NULL.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+ConSplitterTextInRegisterKeyNotify (\r
+  IN EFI_SIMPLE_TEXT_INPUT_EX_PROTOCOL  *This,\r
+  IN EFI_KEY_DATA                       *KeyData,\r
+  IN EFI_KEY_NOTIFY_FUNCTION            KeyNotificationFunction,\r
+  OUT VOID                              **NotifyHandle\r
+  );\r
+\r
+\r
+/**\r
+  Remove a registered notification function from a particular keystroke.\r
+\r
+  @param  This                     Protocol instance pointer.\r
+  @param  NotificationHandle       The handle of the notification function being\r
+                                   unregistered.\r
+\r
+  @retval EFI_SUCCESS              The notification function was unregistered\r
+                                   successfully.\r
+  @retval EFI_INVALID_PARAMETER    The NotificationHandle is invalid.\r
+  @retval EFI_NOT_FOUND            Can not find the matching entry in database.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+ConSplitterTextInUnregisterKeyNotify (\r
+  IN EFI_SIMPLE_TEXT_INPUT_EX_PROTOCOL  *This,\r
+  IN VOID                               *NotificationHandle\r
+  );\r
+\r
+/**\r
+  This event aggregates all the events of the ConIn devices in the spliter.\r
+\r
+  If any events of physical ConIn devices are signaled, signal the ConIn\r
+  spliter event. This will cause the calling code to call\r
+  ConSplitterTextInReadKeyStroke ().\r
+\r
+  @param  Event                    The Event assoicated with callback.\r
+  @param  Context                  Context registered when Event was created.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+ConSplitterTextInWaitForKey (\r
+  IN  EFI_EVENT                       Event,\r
+  IN  VOID                            *Context\r
+  );\r
+\r
+\r
+/**\r
+  Reads the next keystroke from the input device. The WaitForKey Event can\r
+  be used to test for existance of a keystroke via WaitForEvent () call.\r
+\r
+  @param  Private                  Protocol instance pointer.\r
+  @param  Key                      Driver may perform diagnostics on reset.\r
+\r
+  @retval EFI_SUCCESS              The keystroke information was returned.\r
+  @retval EFI_NOT_READY            There was no keystroke data availiable.\r
+  @retval EFI_DEVICE_ERROR         The keydtroke information was not returned due\r
+                                   to hardware errors.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+ConSplitterTextInPrivateReadKeyStroke (\r
+  IN  TEXT_IN_SPLITTER_PRIVATE_DATA   *Private,\r
+  OUT EFI_INPUT_KEY                   *Key\r
+  );\r
+\r
+/**\r
+  Reset the input device and optionaly run diagnostics\r
+\r
+  @param  This                     Protocol instance pointer.\r
+  @param  ExtendedVerification     Driver may perform diagnostics on reset.\r
+\r
+  @retval EFI_SUCCESS              The device was reset.\r
+  @retval EFI_DEVICE_ERROR         The device is not functioning properly and could\r
+                                   not be reset.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+ConSplitterSimplePointerReset (\r
+  IN  EFI_SIMPLE_POINTER_PROTOCOL     *This,\r
+  IN  BOOLEAN                         ExtendedVerification\r
+  );\r
+\r
+/**\r
+  Reads the next keystroke from the input device. The WaitForKey Event can\r
+  be used to test for existance of a keystroke via WaitForEvent () call.\r
+\r
+  @param  This                     A pointer to protocol instance.\r
+  @param  State                    A pointer to state information on the pointer device\r
+\r
+  @retval EFI_SUCCESS              The keystroke information was returned in State.\r
+  @retval EFI_NOT_READY            There was no keystroke data availiable.\r
+  @retval EFI_DEVICE_ERROR         The keydtroke information was not returned due\r
+                                   to hardware errors.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+ConSplitterSimplePointerGetState (\r
+  IN  EFI_SIMPLE_POINTER_PROTOCOL     *This,\r
+  IN OUT EFI_SIMPLE_POINTER_STATE     *State\r
+  );\r
+\r
+/**\r
+  This event agregates all the events of the ConIn devices in the spliter.\r
+  If any events of physical ConIn devices are signaled, signal the ConIn\r
+  spliter event. This will cause the calling code to call\r
+  ConSplitterTextInReadKeyStroke ().\r
+\r
+  @param  Event                    The Event assoicated with callback.\r
+  @param  Context                  Context registered when Event was created.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+ConSplitterSimplePointerWaitForInput (\r
+  IN  EFI_EVENT                       Event,\r
+  IN  VOID                            *Context\r
+  );\r
+\r
+//\r
+// TextOut I/O Functions\r
+//\r
+\r
+/**\r
+  Reset the text output device hardware and optionaly run diagnostics\r
+\r
+  @param  This                     Protocol instance pointer.\r
+  @param  ExtendedVerification     Driver may perform more exhaustive verfication\r
+                                   operation of the device during reset.\r
+\r
+  @retval EFI_SUCCESS              The text output device was reset.\r
+  @retval EFI_DEVICE_ERROR         The text output device is not functioning\r
+                                   correctly and could not be reset.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+ConSplitterTextOutReset (\r
+  IN  EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL    *This,\r
+  IN  BOOLEAN                            ExtendedVerification\r
+  );\r
+\r
+/**\r
+  Write a Unicode string to the output device.\r
+\r
+  @param  This                     Protocol instance pointer.\r
+  @param  WString                  The NULL-terminated Unicode string to be\r
+                                   displayed on the output device(s). All output\r
+                                   devices must also support the Unicode drawing\r
+                                   defined in this file.\r
+\r
+  @retval EFI_SUCCESS              The string was output to the device.\r
+  @retval EFI_DEVICE_ERROR         The device reported an error while attempting to\r
+                                   output the text.\r
+  @retval EFI_UNSUPPORTED          The output device's mode is not currently in a\r
+                                   defined text mode.\r
+  @retval EFI_WARN_UNKNOWN_GLYPH   This warning code indicates that some of the\r
+                                   characters in the Unicode string could not be\r
+                                   rendered and were skipped.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+ConSplitterTextOutOutputString (\r
+  IN  EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL    *This,\r
+  IN  CHAR16                             *WString\r
+  );\r
+\r
+/**\r
+  Verifies that all characters in a Unicode string can be output to the\r
+  target device.\r
+\r
+  @param  This                     Protocol instance pointer.\r
+  @param  WString                  The NULL-terminated Unicode string to be\r
+                                   examined for the output device(s).\r
+\r
+  @retval EFI_SUCCESS              The device(s) are capable of rendering the\r
+                                   output string.\r
+  @retval EFI_UNSUPPORTED          Some of the characters in the Unicode string\r
+                                   cannot be rendered by one or more of the output\r
+                                   devices mapped by the EFI handle.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+ConSplitterTextOutTestString (\r
+  IN  EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL    *This,\r
+  IN  CHAR16                             *WString\r
+  );\r
+\r
+/**\r
+  Returns information for an available text mode that the output device(s)\r
+  supports.\r
+\r
+  @param  This                     Protocol instance pointer.\r
+  @param  ModeNumber               The mode number to return information on.\r
+  @param  Columns                  Returns the columns of the text output device\r
+                                   for the requested ModeNumber.\r
+  @param  Rows                     Returns the rows of the text output device\r
+                                   for the requested ModeNumber.\r
+\r
+  @retval EFI_SUCCESS              The requested mode information was returned.\r
+  @retval EFI_DEVICE_ERROR         The device had an error and could not complete\r
+                                   the request.\r
+  @retval EFI_UNSUPPORTED          The mode number was not valid.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+ConSplitterTextOutQueryMode (\r
+  IN  EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL    *This,\r
+  IN  UINTN                              ModeNumber,\r
+  OUT UINTN                              *Columns,\r
+  OUT UINTN                              *Rows\r
+  );\r
+\r
+/**\r
+  Sets the output device(s) to a specified mode.\r
+\r
+  @param  This                     Protocol instance pointer.\r
+  @param  ModeNumber               The mode number to set.\r
+\r
+  @retval EFI_SUCCESS              The requested text mode was set.\r
+  @retval EFI_DEVICE_ERROR         The device had an error and could not complete\r
+                                   the request.\r
+  @retval EFI_UNSUPPORTED          The mode number was not valid.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+ConSplitterTextOutSetMode (\r
+  IN  EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL    *This,\r
+  IN  UINTN                              ModeNumber\r
+  );\r
+\r
+/**\r
+  Sets the background and foreground colors for the OutputString () and\r
+  ClearScreen () functions.\r
+\r
+  @param  This                     Protocol instance pointer.\r
+  @param  Attribute                The attribute to set. Bits 0..3 are the\r
+                                   foreground color, and bits 4..6 are the\r
+                                   background color. All other bits are undefined\r
+                                   and must be zero. The valid Attributes are\r
+                                   defined in this file.\r
+\r
+  @retval EFI_SUCCESS              The attribute was set.\r
+  @retval EFI_DEVICE_ERROR         The device had an error and could not complete\r
+                                   the request.\r
+  @retval EFI_UNSUPPORTED          The attribute requested is not defined.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+ConSplitterTextOutSetAttribute (\r
+  IN  EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL    *This,\r
+  IN  UINTN                              Attribute\r
+  );\r
+\r
+/**\r
+  Clears the output device(s) display to the currently selected background\r
+  color.\r
+\r
+  @param  This                     Protocol instance pointer.\r
+\r
+  @retval EFI_SUCCESS              The operation completed successfully.\r
+  @retval EFI_DEVICE_ERROR         The device had an error and could not complete\r
+                                   the request.\r
+  @retval EFI_UNSUPPORTED          The output device is not in a valid text mode.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+ConSplitterTextOutClearScreen (\r
+  IN  EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL    *This\r
+  );\r
+\r
+/**\r
+  Sets the current coordinates of the cursor position\r
+\r
+  @param  This                     Protocol instance pointer.\r
+  @param  Column                   The column position to set the cursor to. Must be\r
+                                   greater than or equal to zero and less than the\r
+                                   number of columns by QueryMode ().\r
+  @param  Row                      The row position to set the cursor to. Must be\r
+                                   greater than or equal to zero and less than the\r
+                                   number of rows by QueryMode ().\r
+\r
+  @retval EFI_SUCCESS              The operation completed successfully.\r
+  @retval EFI_DEVICE_ERROR         The device had an error and could not complete\r
+                                   the request.\r
+  @retval EFI_UNSUPPORTED          The output device is not in a valid text mode,\r
+                                   or the cursor position is invalid for the\r
+                                   current mode.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+ConSplitterTextOutSetCursorPosition (\r
+  IN  EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL    *This,\r
+  IN  UINTN                              Column,\r
+  IN  UINTN                              Row\r
+  );\r
+\r
+\r
+/**\r
+  Makes the cursor visible or invisible\r
+\r
+  @param  This                     Protocol instance pointer.\r
+  @param  Visible                  If TRUE, the cursor is set to be visible. If\r
+                                   FALSE, the cursor is set to be invisible.\r
+\r
+  @retval EFI_SUCCESS              The operation completed successfully.\r
+  @retval EFI_DEVICE_ERROR         The device had an error and could not complete\r
+                                   the request, or the device does not support\r
+                                   changing the cursor mode.\r
+  @retval EFI_UNSUPPORTED          The output device is not in a valid text mode.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+ConSplitterTextOutEnableCursor (\r
+  IN  EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL    *This,\r
+  IN  BOOLEAN                            Visible\r
+  );\r
+\r
+/**\r
+  Take the passed in Buffer of size ElementSize and grow the buffer\r
+  by CONSOLE_SPLITTER_ALLOC_UNIT * ElementSize bytes.\r
+  Copy the current data in Buffer to the new version of Buffer and\r
+  free the old version of buffer.\r
+\r
+  @param  ElementSize              Size of element in array.\r
+  @param  Count                    Current number of elements in array.\r
+  @param  Buffer                   Bigger version of passed in Buffer with all the\r
+                                   data.\r
+\r
+  @retval EFI_SUCCESS              Buffer size has grown.\r
+  @retval EFI_OUT_OF_RESOURCES     Could not grow the buffer size.\r
+\r
+**/\r
+EFI_STATUS\r
+ConSplitterGrowBuffer (\r
+  IN      UINTN                       ElementSize,\r
+  IN OUT  UINTN                       *Count,\r
+  IN OUT  VOID                        **Buffer\r
+  );\r
+\r
+/**\r
+  Returns information for an available graphics mode that the graphics device\r
+  and the set of active video output devices supports.\r
+\r
+  @param  This                  The EFI_GRAPHICS_OUTPUT_PROTOCOL instance.\r
+  @param  ModeNumber            The mode number to return information on.\r
+  @param  SizeOfInfo            A pointer to the size, in bytes, of the Info buffer.\r
+  @param  Info                  A pointer to callee allocated buffer that returns information about ModeNumber.\r
+\r
+  @retval EFI_SUCCESS           Mode information returned.\r
+  @retval EFI_BUFFER_TOO_SMALL  The Info buffer was too small.\r
+  @retval EFI_DEVICE_ERROR      A hardware error occurred trying to retrieve the video mode.\r
+  @retval EFI_INVALID_PARAMETER One of the input args was NULL.\r
+  @retval EFI_OUT_OF_RESOURCES  No resource available.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+ConSplitterGraphicsOutputQueryMode (\r
+  IN  EFI_GRAPHICS_OUTPUT_PROTOCOL          *This,\r
+  IN  UINT32                                ModeNumber,\r
+  OUT UINTN                                 *SizeOfInfo,\r
+  OUT EFI_GRAPHICS_OUTPUT_MODE_INFORMATION  **Info\r
+  );\r
+\r
+/**\r
+  Set the video device into the specified mode and clears the visible portions of\r
+  the output display to black.\r
+\r
+  @param  This                  The EFI_GRAPHICS_OUTPUT_PROTOCOL instance.\r
+  @param  ModeNumber            Abstraction that defines the current video mode.\r
+\r
+  @retval EFI_SUCCESS           The graphics mode specified by ModeNumber was selected.\r
+  @retval EFI_DEVICE_ERROR      The device had an error and could not complete the request.\r
+  @retval EFI_UNSUPPORTED       ModeNumber is not supported by this device.\r
+  @retval EFI_OUT_OF_RESOURCES  No resource available.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+ConSplitterGraphicsOutputSetMode (\r
+  IN  EFI_GRAPHICS_OUTPUT_PROTOCOL * This,\r
+  IN  UINT32                       ModeNumber\r
+  );\r
+\r
+/**\r
+  The following table defines actions for BltOperations.\r
+\r
+  EfiBltVideoFill - Write data from the  BltBuffer pixel (SourceX, SourceY)\r
+  directly to every pixel of the video display rectangle\r
+  (DestinationX, DestinationY)\r
+  (DestinationX + Width, DestinationY + Height).\r
+  Only one pixel will be used from the BltBuffer. Delta is NOT used.\r
+  EfiBltVideoToBltBuffer - Read data from the video display rectangle\r
+  (SourceX, SourceY) (SourceX + Width, SourceY + Height) and place it in\r
+  the BltBuffer rectangle (DestinationX, DestinationY )\r
+  (DestinationX + Width, DestinationY + Height). If DestinationX or\r
+  DestinationY is not zero then Delta must be set to the length in bytes\r
+  of a row in the BltBuffer.\r
+  EfiBltBufferToVideo - Write data from the  BltBuffer rectangle\r
+  (SourceX, SourceY) (SourceX + Width, SourceY + Height) directly to the\r
+  video display rectangle (DestinationX, DestinationY)\r
+  (DestinationX + Width, DestinationY + Height). If SourceX or SourceY is\r
+  not zero then Delta must be set to the length in bytes of a row in the\r
+  BltBuffer.\r
+  EfiBltVideoToVideo - Copy from the video display rectangle\r
+  (SourceX, SourceY) (SourceX + Width, SourceY + Height) .\r
+  to the video display rectangle (DestinationX, DestinationY)\r
+  (DestinationX + Width, DestinationY + Height).\r
+  The BltBuffer and Delta  are not used in this mode.\r
+\r
+  @param  This                    Protocol instance pointer.\r
+  @param  BltBuffer               Buffer containing data to blit into video buffer.\r
+                                  This buffer has a size of\r
+                                  Width*Height*sizeof(EFI_GRAPHICS_OUTPUT_BLT_PIXEL)\r
+  @param  BltOperation            Operation to perform on BlitBuffer and video\r
+                                  memory\r
+  @param  SourceX                 X coordinate of source for the BltBuffer.\r
+  @param  SourceY                 Y coordinate of source for the BltBuffer.\r
+  @param  DestinationX            X coordinate of destination for the BltBuffer.\r
+  @param  DestinationY            Y coordinate of destination for the BltBuffer.\r
+  @param  Width                   Width of rectangle in BltBuffer in pixels.\r
+  @param  Height                  Hight of rectangle in BltBuffer in pixels.\r
+  @param  Delta                   OPTIONAL.\r
+\r
+  @retval EFI_SUCCESS             The Blt operation completed.\r
+  @retval EFI_INVALID_PARAMETER   BltOperation is not valid.\r
+  @retval EFI_DEVICE_ERROR        A hardware error occured writting to the video\r
+                                  buffer.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+ConSplitterGraphicsOutputBlt (\r
+  IN  EFI_GRAPHICS_OUTPUT_PROTOCOL                  *This,\r
+  IN  EFI_GRAPHICS_OUTPUT_BLT_PIXEL                 *BltBuffer, OPTIONAL\r
+  IN  EFI_GRAPHICS_OUTPUT_BLT_OPERATION             BltOperation,\r
+  IN  UINTN                                         SourceX,\r
+  IN  UINTN                                         SourceY,\r
+  IN  UINTN                                         DestinationX,\r
+  IN  UINTN                                         DestinationY,\r
+  IN  UINTN                                         Width,\r
+  IN  UINTN                                         Height,\r
+  IN  UINTN                                         Delta         OPTIONAL\r
+  );\r
+\r
+\r
+/**\r
+  Return the current video mode information.\r
+\r
+  @param  This                  The EFI_UGA_DRAW_PROTOCOL instance.\r
+  @param  HorizontalResolution  The size of video screen in pixels in the X dimension.\r
+  @param  VerticalResolution    The size of video screen in pixels in the Y dimension.\r
+  @param  ColorDepth            Number of bits per pixel, currently defined to be 32.\r
+  @param  RefreshRate           The refresh rate of the monitor in Hertz.\r
+\r
+  @retval EFI_SUCCESS           Mode information returned.\r
+  @retval EFI_NOT_STARTED       Video display is not initialized. Call SetMode ()\r
+  @retval EFI_INVALID_PARAMETER One of the input args was NULL.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+ConSplitterUgaDrawGetMode (\r
+  IN  EFI_UGA_DRAW_PROTOCOL           *This,\r
+  OUT UINT32                          *HorizontalResolution,\r
+  OUT UINT32                          *VerticalResolution,\r
+  OUT UINT32                          *ColorDepth,\r
+  OUT UINT32                          *RefreshRate\r
+  );\r
+\r
+/**\r
+  Set the current video mode information.\r
+\r
+  @param  This                 The EFI_UGA_DRAW_PROTOCOL instance.\r
+  @param  HorizontalResolution The size of video screen in pixels in the X dimension.\r
+  @param  VerticalResolution   The size of video screen in pixels in the Y dimension.\r
+  @param  ColorDepth           Number of bits per pixel, currently defined to be 32.\r
+  @param  RefreshRate          The refresh rate of the monitor in Hertz.\r
+\r
+  @retval EFI_SUCCESS          Mode information returned.\r
+  @retval EFI_NOT_STARTED      Video display is not initialized. Call SetMode ()\r
+  @retval EFI_OUT_OF_RESOURCES Out of resources.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+ConSplitterUgaDrawSetMode (\r
+  IN  EFI_UGA_DRAW_PROTOCOL           *This,\r
+  IN UINT32                           HorizontalResolution,\r
+  IN UINT32                           VerticalResolution,\r
+  IN UINT32                           ColorDepth,\r
+  IN UINT32                           RefreshRate\r
+  );\r
+\r
+/**\r
+  Blt a rectangle of pixels on the graphics screen.\r
+\r
+  The following table defines actions for BltOperations.\r
+\r
+  EfiUgaVideoFill:\r
+    Write data from the  BltBuffer pixel (SourceX, SourceY)\r
+    directly to every pixel of the video display rectangle\r
+    (DestinationX, DestinationY)\r
+    (DestinationX + Width, DestinationY + Height).\r
+    Only one pixel will be used from the BltBuffer. Delta is NOT used.\r
+  EfiUgaVideoToBltBuffer:\r
+    Read data from the video display rectangle\r
+    (SourceX, SourceY) (SourceX + Width, SourceY + Height) and place it in\r
+    the BltBuffer rectangle (DestinationX, DestinationY )\r
+    (DestinationX + Width, DestinationY + Height). If DestinationX or\r
+    DestinationY is not zero then Delta must be set to the length in bytes\r
+    of a row in the BltBuffer.\r
+  EfiUgaBltBufferToVideo:\r
+    Write data from the  BltBuffer rectangle\r
+    (SourceX, SourceY) (SourceX + Width, SourceY + Height) directly to the\r
+    video display rectangle (DestinationX, DestinationY)\r
+    (DestinationX + Width, DestinationY + Height). If SourceX or SourceY is\r
+    not zero then Delta must be set to the length in bytes of a row in the\r
+    BltBuffer.\r
+  EfiUgaVideoToVideo:\r
+    Copy from the video display rectangle\r
+    (SourceX, SourceY) (SourceX + Width, SourceY + Height) .\r
+    to the video display rectangle (DestinationX, DestinationY)\r
+    (DestinationX + Width, DestinationY + Height).\r
+    The BltBuffer and Delta  are not used in this mode.\r
+\r
+  @param  This           Protocol instance pointer.\r
+  @param  BltBuffer      Buffer containing data to blit into video buffer. This\r
+                         buffer has a size of Width*Height*sizeof(EFI_UGA_PIXEL)\r
+  @param  BltOperation   Operation to perform on BlitBuffer and video memory\r
+  @param  SourceX        X coordinate of source for the BltBuffer.\r
+  @param  SourceY        Y coordinate of source for the BltBuffer.\r
+  @param  DestinationX   X coordinate of destination for the BltBuffer.\r
+  @param  DestinationY   Y coordinate of destination for the BltBuffer.\r
+  @param  Width          Width of rectangle in BltBuffer in pixels.\r
+  @param  Height         Hight of rectangle in BltBuffer in pixels.\r
+  @param  Delta          OPTIONAL\r
+\r
+  @retval EFI_SUCCESS            The Blt operation completed.\r
+  @retval EFI_INVALID_PARAMETER  BltOperation is not valid.\r
+  @retval EFI_DEVICE_ERROR       A hardware error occured writting to the video buffer.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+ConSplitterUgaDrawBlt (\r
+  IN  EFI_UGA_DRAW_PROTOCOL                         *This,\r
+  IN  EFI_UGA_PIXEL                                 *BltBuffer, OPTIONAL\r
+  IN  EFI_UGA_BLT_OPERATION                         BltOperation,\r
+  IN  UINTN                                         SourceX,\r
+  IN  UINTN                                         SourceY,\r
+  IN  UINTN                                         DestinationX,\r
+  IN  UINTN                                         DestinationY,\r
+  IN  UINTN                                         Width,\r
+  IN  UINTN                                         Height,\r
+  IN  UINTN                                         Delta         OPTIONAL\r
+  );\r
+\r
+/**\r
+  Sets the output device(s) to a specified mode.\r
+\r
+  @param  Private                 Text Out Splitter pointer.\r
+  @param  ModeNumber              The mode number to set.\r
+\r
+**/\r
+VOID\r
+TextOutSetMode (\r
+  IN  TEXT_OUT_SPLITTER_PRIVATE_DATA  *Private,\r
+  IN  UINTN                           ModeNumber\r
+  );\r
+\r
+/**\r
+  An empty function to pass error checking of CreateEventEx ().\r
+\r
+  @param  Event                 Event whose notification function is being invoked.\r
+  @param  Context               Pointer to the notification function's context,\r
+                                which is implementation-dependent.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+ConSplitterEmptyCallbackFunction (\r
+  IN EFI_EVENT                Event,\r
+  IN VOID                     *Context\r
+  );\r
+\r
+\r
+#endif\r

diff --git a/Vlv2TbltDevicePkg/Override/MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf b/Vlv2TbltDevicePkg/Override/MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
new file mode 100644 (file)
index 0000000..4885dc7
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Override/MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
@@ -0,0 +1,96 @@
+## @file\r
+# This driver provides multi console supports.\r
+#\r
+# This driver acts as a virtual console, takes over the console I/O control from selected\r
+# standard console devices, and transmits console I/O to related console device drivers.\r
+# Consplitter could install Graphics Output protocol and/or UGA Draw protocol in system\r
+# table according PCD settings(PcdConOutGopSupport, and PcdConOutUgaSupport). It always\r
+# consumes Graphics Output protocol which is produced by display device, and consumes UGA Draw\r
+# protocol which is produced by display device according to PcdUgaConsumeSupport value.\r
+# Note: If only UGA Draw protocol is installed in system table, PcdUgaConsumeSupport\r
+# should be set to TRUE.\r
+#\r
+# Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.<BR>\r
+#\r
+#  This program and the accompanying materials\r
+#  are licensed and made available under the terms and conditions of the BSD License\r
+#  which accompanies this distribution. The full text of the license may be found at\r
+#  http://opensource.org/licenses/bsd-license.php\r
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+#\r
+##\r
+\r
+[Defines]\r
+  INF_VERSION                    = 0x00010005\r
+  BASE_NAME                      = ConSplitterDxe\r
+  FILE_GUID                      = 408edcec-cf6d-477c-a5a8-b4844e3de281\r
+  MODULE_TYPE                    = UEFI_DRIVER\r
+  VERSION_STRING                 = 1.0\r
+  ENTRY_POINT                    = ConSplitterDriverEntry\r
+\r
+#\r
+# The following information is for reference only and not required by the build tools.\r
+#\r
+#  VALID_ARCHITECTURES           = IA32 X64 IPF EBC\r
+#\r
+#  DRIVER_BINDING                =  gConSplitterConInDriverBinding\r
+#  COMPONENT_NAME                =  gConSplitterConInComponentName\r
+#  COMPONENT_NAME2               =  gConSplitterConInComponentName2\r
+#  DRIVER_BINDING                =  gConSplitterSimplePointerDriverBinding\r
+#  COMPONENT_NAME                =  gConSplitterSimplePointerComponentName\r
+#  COMPONENT_NAME2               =  gConSplitterSimplePointerComponentName2\r
+#  DRIVER_BINDING                =  gConSplitterConOutDriverBinding\r
+#  COMPONENT_NAME                =  gConSplitterConOutComponentName\r
+#  COMPONENT_NAME2               =  gConSplitterConOutComponentName2\r
+#  DRIVER_BINDING                =  gConSplitterStdErrDriverBinding\r
+#  COMPONENT_NAME                =  gConSplitterStdErrComponentName\r
+#  COMPONENT_NAME2               =  gConSplitterStdErrComponentName2\r
+#\r
+\r
+[Sources]\r
+  ConSplitterGraphics.c\r
+  ComponentName.c\r
+  ConSplitter.h\r
+  ConSplitter.c\r
+\r
+[Packages]\r
+  MdePkg/MdePkg.dec\r
+  MdeModulePkg/MdeModulePkg.dec\r
+\r
+[LibraryClasses]\r
+  UefiBootServicesTableLib\r
+  MemoryAllocationLib\r
+  BaseMemoryLib\r
+  BaseLib\r
+  UefiLib\r
+  UefiDriverEntryPoint\r
+  DebugLib\r
+  PcdLib\r
+\r
+[Guids]\r
+  gEfiConsoleInDeviceGuid                       ## SOMETIMES_CONSUMES\r
+  gEfiStandardErrorDeviceGuid                   ## SOMETIMES_CONSUMES\r
+  gEfiConsoleOutDeviceGuid                      ## SOMETIMES_CONSUMES\r
+  gConnectConInEventGuid                        ## ALWAYS_CONSUMES\r
+\r
+[Protocols]\r
+  gEfiSimplePointerProtocolGuid                 ## BY_START\r
+  gEfiAbsolutePointerProtocolGuid               ## BY_START\r
+  gEfiSimpleTextInProtocolGuid                  ## BY_START\r
+  gEfiSimpleTextInputExProtocolGuid             ## BY_START\r
+  gEfiSimpleTextOutProtocolGuid                 ## BY_START\r
+  gEfiGraphicsOutputProtocolGuid                ## BY_START\r
+  gEfiUgaDrawProtocolGuid                       ## BY_START\r
+\r
+\r
+[FeaturePcd]\r
+  gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport\r
+  gEfiMdeModulePkgTokenSpaceGuid.PcdConOutUgaSupport\r
+  gEfiMdePkgTokenSpaceGuid.PcdUgaConsumeSupport\r
+\r
+[Pcd]\r
+  gEfiMdeModulePkgTokenSpaceGuid.PcdConOutRow\r
+  gEfiMdeModulePkgTokenSpaceGuid.PcdConOutColumn\r
+  gEfiMdeModulePkgTokenSpaceGuid.PcdConInConnectOnDemand\r

diff --git a/Vlv2TbltDevicePkg/Override/MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterGraphics.c b/Vlv2TbltDevicePkg/Override/MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterGraphics.c
new file mode 100644 (file)
index 0000000..b7cdd7a
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Override/MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterGraphics.c
@@ -0,0 +1,628 @@
+/** @file\r
+  Support for Graphics output spliter.\r
+  \r
+Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.<BR>\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution.  The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+**/\r
+\r
+#include "ConSplitter.h"\r
+\r
+\r
+CHAR16 mCrLfString[3] = { CHAR_CARRIAGE_RETURN, CHAR_LINEFEED, CHAR_NULL };\r
+\r
+/**\r
+  Returns information for an available graphics mode that the graphics device\r
+  and the set of active video output devices supports.\r
+\r
+  @param  This                  The EFI_GRAPHICS_OUTPUT_PROTOCOL instance.\r
+  @param  ModeNumber            The mode number to return information on.\r
+  @param  SizeOfInfo            A pointer to the size, in bytes, of the Info buffer.\r
+  @param  Info                  A pointer to callee allocated buffer that returns information about ModeNumber.\r
+\r
+  @retval EFI_SUCCESS           Mode information returned.\r
+  @retval EFI_BUFFER_TOO_SMALL  The Info buffer was too small.\r
+  @retval EFI_DEVICE_ERROR      A hardware error occurred trying to retrieve the video mode.\r
+  @retval EFI_INVALID_PARAMETER One of the input args was NULL.\r
+  @retval EFI_OUT_OF_RESOURCES  No resource available.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+ConSplitterGraphicsOutputQueryMode (\r
+  IN  EFI_GRAPHICS_OUTPUT_PROTOCOL          *This,\r
+  IN  UINT32                                ModeNumber,\r
+  OUT UINTN                                 *SizeOfInfo,\r
+  OUT EFI_GRAPHICS_OUTPUT_MODE_INFORMATION  **Info\r
+  )\r
+{\r
+  TEXT_OUT_SPLITTER_PRIVATE_DATA  *Private;\r
+  EFI_GRAPHICS_OUTPUT_PROTOCOL    *GraphicsOutput;\r
+  EFI_STATUS                      Status;\r
+  UINTN                           Index;\r
+\r
+  if (This == NULL || Info == NULL || SizeOfInfo == NULL || ModeNumber >= This->Mode->MaxMode) {\r
+    return EFI_INVALID_PARAMETER;\r
+  }\r
+\r
+  //\r
+  // retrieve private data\r
+  //\r
+  Private = GRAPHICS_OUTPUT_SPLITTER_PRIVATE_DATA_FROM_THIS (This);\r
+\r
+  GraphicsOutput = NULL;\r
+  \r
+  if (Private->CurrentNumberOfGraphicsOutput == 1) {\r
+    //\r
+    // Find the only one GraphicsOutput.\r
+    //\r
+    for (Index = 0; Index < Private->CurrentNumberOfConsoles; Index++) {\r
+      GraphicsOutput = Private->TextOutList[Index].GraphicsOutput;\r
+      if (GraphicsOutput != NULL) {\r
+        break;\r
+      }\r
+    }\r
+  }\r
+  \r
+  if (GraphicsOutput != NULL) {\r
+    //\r
+    // If only one physical GOP device exist, return its information.\r
+    //\r
+    Status = GraphicsOutput->QueryMode (GraphicsOutput, (UINT32) ModeNumber, SizeOfInfo, Info);\r
+    return Status;\r
+  } else {\r
+    //\r
+    // If 2 more phyiscal GOP device exist or GOP protocol does not exist, \r
+    // return GOP information (PixelFormat is PixelBltOnly) created in ConSplitterAddGraphicsOutputMode ().\r
+    //\r
+    *Info = AllocatePool (sizeof (EFI_GRAPHICS_OUTPUT_MODE_INFORMATION));\r
+    if (*Info == NULL) {\r
+      return EFI_OUT_OF_RESOURCES;\r
+    }\r
+    *SizeOfInfo = sizeof (EFI_GRAPHICS_OUTPUT_MODE_INFORMATION);\r
+    CopyMem (*Info, &Private->GraphicsOutputModeBuffer[ModeNumber], *SizeOfInfo);\r
+  }\r
+\r
+  return EFI_SUCCESS;\r
+}\r
+\r
+\r
+/**\r
+  Set the video device into the specified mode and clears the visible portions of\r
+  the output display to black.\r
+\r
+  @param  This                  The EFI_GRAPHICS_OUTPUT_PROTOCOL instance.\r
+  @param  ModeNumber            Abstraction that defines the current video mode.\r
+\r
+  @retval EFI_SUCCESS           The graphics mode specified by ModeNumber was selected.\r
+  @retval EFI_DEVICE_ERROR      The device had an error and could not complete the request.\r
+  @retval EFI_UNSUPPORTED       ModeNumber is not supported by this device.\r
+  @retval EFI_OUT_OF_RESOURCES  No resource available.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+ConSplitterGraphicsOutputSetMode (\r
+  IN  EFI_GRAPHICS_OUTPUT_PROTOCOL * This,\r
+  IN  UINT32                       ModeNumber\r
+  )\r
+{\r
+  EFI_STATUS                             Status;\r
+  TEXT_OUT_SPLITTER_PRIVATE_DATA         *Private;\r
+  UINTN                                  Index;\r
+  EFI_STATUS                             ReturnStatus;\r
+  EFI_GRAPHICS_OUTPUT_MODE_INFORMATION   *Mode;\r
+  EFI_GRAPHICS_OUTPUT_PROTOCOL           *GraphicsOutput;\r
+  EFI_GRAPHICS_OUTPUT_PROTOCOL           *PhysicalGraphicsOutput;\r
+  UINTN                                  NumberIndex;\r
+  UINTN                                  SizeOfInfo;\r
+  EFI_GRAPHICS_OUTPUT_MODE_INFORMATION   *Info;\r
+  EFI_UGA_DRAW_PROTOCOL                  *UgaDraw;\r
+\r
+  if (ModeNumber >= This->Mode->MaxMode) {\r
+    return EFI_UNSUPPORTED;\r
+  }\r
+\r
+  Private = GRAPHICS_OUTPUT_SPLITTER_PRIVATE_DATA_FROM_THIS (This);\r
+  Mode = &Private->GraphicsOutputModeBuffer[ModeNumber];\r
+\r
+  ReturnStatus = EFI_SUCCESS;\r
+  GraphicsOutput = NULL;\r
+  PhysicalGraphicsOutput = NULL;\r
+  //\r
+  // return the worst status met\r
+  //\r
+  for (Index = 0; Index < Private->CurrentNumberOfConsoles; Index++) {\r
+    GraphicsOutput = Private->TextOutList[Index].GraphicsOutput;\r
+    if (GraphicsOutput != NULL) {\r
+      PhysicalGraphicsOutput = GraphicsOutput;\r
+      //\r
+      // Find corresponding ModeNumber of this GraphicsOutput instance\r
+      //\r
+      for (NumberIndex = 0; NumberIndex < GraphicsOutput->Mode->MaxMode; NumberIndex ++) {\r
+        Status = GraphicsOutput->QueryMode (GraphicsOutput, (UINT32) NumberIndex, &SizeOfInfo, &Info);\r
+        if (EFI_ERROR (Status)) {\r
+          return Status;\r
+        }\r
+        if ((Info->HorizontalResolution == Mode->HorizontalResolution) && (Info->VerticalResolution == Mode->VerticalResolution)) {\r
+          FreePool (Info);\r
+          break;\r
+        }\r
+        FreePool (Info);\r
+      }\r
+\r
+      Status = GraphicsOutput->SetMode (GraphicsOutput, (UINT32) NumberIndex);\r
+      if (EFI_ERROR (Status)) {\r
+        ReturnStatus = Status;\r
+      }\r
+    } else if (FeaturePcdGet (PcdUgaConsumeSupport)) {\r
+      UgaDraw = Private->TextOutList[Index].UgaDraw;\r
+      if (UgaDraw != NULL) {\r
+        Status = UgaDraw->SetMode (\r
+                            UgaDraw,\r
+                            Mode->HorizontalResolution,\r
+                            Mode->VerticalResolution,\r
+                            32,\r
+                            60\r
+                            );\r
+        if (EFI_ERROR (Status)) {\r
+          ReturnStatus = Status;\r
+        }\r
+      }\r
+    }\r
+  }\r
+\r
+  This->Mode->Mode = ModeNumber;\r
+\r
+  if ((Private->CurrentNumberOfGraphicsOutput == 1) && (PhysicalGraphicsOutput != NULL)) {\r
+    //\r
+    // If only one physical GOP device exist, copy physical information to consplitter.\r
+    //\r
+    CopyMem (This->Mode->Info, PhysicalGraphicsOutput->Mode->Info, PhysicalGraphicsOutput->Mode->SizeOfInfo);\r
+    This->Mode->SizeOfInfo = PhysicalGraphicsOutput->Mode->SizeOfInfo;\r
+    This->Mode->FrameBufferBase = PhysicalGraphicsOutput->Mode->FrameBufferBase;\r
+    This->Mode->FrameBufferSize = PhysicalGraphicsOutput->Mode->FrameBufferSize;\r
+  } else {\r
+    //\r
+    // If 2 more phyiscal GOP device exist or GOP protocol does not exist, \r
+    // return GOP information (PixelFormat is PixelBltOnly) created in ConSplitterAddGraphicsOutputMode ().\r
+    //\r
+    CopyMem (This->Mode->Info, &Private->GraphicsOutputModeBuffer[ModeNumber], This->Mode->SizeOfInfo);\r
+  }\r
+\r
+  return ReturnStatus;\r
+}\r
+\r
+\r
+\r
+/**\r
+  The following table defines actions for BltOperations.\r
+\r
+  EfiBltVideoFill - Write data from the  BltBuffer pixel (SourceX, SourceY)\r
+  directly to every pixel of the video display rectangle\r
+  (DestinationX, DestinationY)\r
+  (DestinationX + Width, DestinationY + Height).\r
+  Only one pixel will be used from the BltBuffer. Delta is NOT used.\r
+  EfiBltVideoToBltBuffer - Read data from the video display rectangle\r
+  (SourceX, SourceY) (SourceX + Width, SourceY + Height) and place it in\r
+  the BltBuffer rectangle (DestinationX, DestinationY )\r
+  (DestinationX + Width, DestinationY + Height). If DestinationX or\r
+  DestinationY is not zero then Delta must be set to the length in bytes\r
+  of a row in the BltBuffer.\r
+  EfiBltBufferToVideo - Write data from the  BltBuffer rectangle\r
+  (SourceX, SourceY) (SourceX + Width, SourceY + Height) directly to the\r
+  video display rectangle (DestinationX, DestinationY)\r
+  (DestinationX + Width, DestinationY + Height). If SourceX or SourceY is\r
+  not zero then Delta must be set to the length in bytes of a row in the\r
+  BltBuffer.\r
+  EfiBltVideoToVideo - Copy from the video display rectangle\r
+  (SourceX, SourceY) (SourceX + Width, SourceY + Height) .\r
+  to the video display rectangle (DestinationX, DestinationY)\r
+  (DestinationX + Width, DestinationY + Height).\r
+  The BltBuffer and Delta  are not used in this mode.\r
+\r
+  @param  This                    Protocol instance pointer.\r
+  @param  BltBuffer               Buffer containing data to blit into video buffer.\r
+                                  This buffer has a size of\r
+                                  Width*Height*sizeof(EFI_GRAPHICS_OUTPUT_BLT_PIXEL)\r
+  @param  BltOperation            Operation to perform on BlitBuffer and video\r
+                                  memory\r
+  @param  SourceX                 X coordinate of source for the BltBuffer.\r
+  @param  SourceY                 Y coordinate of source for the BltBuffer.\r
+  @param  DestinationX            X coordinate of destination for the BltBuffer.\r
+  @param  DestinationY            Y coordinate of destination for the BltBuffer.\r
+  @param  Width                   Width of rectangle in BltBuffer in pixels.\r
+  @param  Height                  Hight of rectangle in BltBuffer in pixels.\r
+  @param  Delta                   OPTIONAL.\r
+\r
+  @retval EFI_SUCCESS             The Blt operation completed.\r
+  @retval EFI_INVALID_PARAMETER   BltOperation is not valid.\r
+  @retval EFI_DEVICE_ERROR        A hardware error occured writting to the video\r
+                                  buffer.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+ConSplitterGraphicsOutputBlt (\r
+  IN  EFI_GRAPHICS_OUTPUT_PROTOCOL                  *This,\r
+  IN  EFI_GRAPHICS_OUTPUT_BLT_PIXEL                 *BltBuffer, OPTIONAL\r
+  IN  EFI_GRAPHICS_OUTPUT_BLT_OPERATION             BltOperation,\r
+  IN  UINTN                                         SourceX,\r
+  IN  UINTN                                         SourceY,\r
+  IN  UINTN                                         DestinationX,\r
+  IN  UINTN                                         DestinationY,\r
+  IN  UINTN                                         Width,\r
+  IN  UINTN                                         Height,\r
+  IN  UINTN                                         Delta         OPTIONAL\r
+  )\r
+{\r
+  EFI_STATUS                      Status;\r
+  EFI_STATUS                      ReturnStatus;\r
+  TEXT_OUT_SPLITTER_PRIVATE_DATA  *Private;\r
+  UINTN                           Index;\r
+  EFI_GRAPHICS_OUTPUT_PROTOCOL    *GraphicsOutput;\r
+  EFI_UGA_DRAW_PROTOCOL           *UgaDraw;\r
+\r
+  if (This == NULL || ((UINTN) BltOperation) >= EfiGraphicsOutputBltOperationMax) {\r
+    return EFI_INVALID_PARAMETER;\r
+  }\r
+  \r
+  Private = GRAPHICS_OUTPUT_SPLITTER_PRIVATE_DATA_FROM_THIS (This);\r
+\r
+  ReturnStatus = EFI_SUCCESS;\r
+\r
+  //\r
+  // return the worst status met\r
+  //\r
+  for (Index = 0; Index < Private->CurrentNumberOfConsoles; Index++) {\r
+    GraphicsOutput = Private->TextOutList[Index].GraphicsOutput;\r
+    if (GraphicsOutput != NULL) {\r
+      Status = GraphicsOutput->Blt (\r
+                              GraphicsOutput,\r
+                              BltBuffer,\r
+                              BltOperation,\r
+                              SourceX,\r
+                              SourceY,\r
+                              DestinationX,\r
+                              DestinationY,\r
+                              Width,\r
+                              Height,\r
+                              Delta\r
+                              );\r
+      if (EFI_ERROR (Status)) {\r
+        ReturnStatus = Status;\r
+      } else if (BltOperation == EfiBltVideoToBltBuffer) {\r
+        //\r
+        // Only need to read the data into buffer one time\r
+        //\r
+        return EFI_SUCCESS;\r
+      }\r
+    }\r
+\r
+    UgaDraw = Private->TextOutList[Index].UgaDraw;\r
+    if (UgaDraw != NULL && FeaturePcdGet (PcdUgaConsumeSupport)) {\r
+      Status = UgaDraw->Blt (\r
+                              UgaDraw,\r
+                              (EFI_UGA_PIXEL *) BltBuffer,\r
+                              (EFI_UGA_BLT_OPERATION) BltOperation,\r
+                              SourceX,\r
+                              SourceY,\r
+                              DestinationX,\r
+                              DestinationY,\r
+                              Width,\r
+                              Height,\r
+                              Delta\r
+                              );\r
+      if (EFI_ERROR (Status)) {\r
+        ReturnStatus = Status;\r
+      } else if (BltOperation == EfiBltVideoToBltBuffer) {\r
+        //\r
+        // Only need to read the data into buffer one time\r
+        //\r
+        return EFI_SUCCESS;\r
+      }\r
+    }\r
+  }\r
+\r
+  return ReturnStatus;\r
+}\r
+\r
+/**\r
+  Return the current video mode information.\r
+\r
+  @param  This                  The EFI_UGA_DRAW_PROTOCOL instance.\r
+  @param  HorizontalResolution  The size of video screen in pixels in the X dimension.\r
+  @param  VerticalResolution    The size of video screen in pixels in the Y dimension.\r
+  @param  ColorDepth            Number of bits per pixel, currently defined to be 32.\r
+  @param  RefreshRate           The refresh rate of the monitor in Hertz.\r
+\r
+  @retval EFI_SUCCESS           Mode information returned.\r
+  @retval EFI_NOT_STARTED       Video display is not initialized. Call SetMode ()\r
+  @retval EFI_INVALID_PARAMETER One of the input args was NULL.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+ConSplitterUgaDrawGetMode (\r
+  IN  EFI_UGA_DRAW_PROTOCOL           *This,\r
+  OUT UINT32                          *HorizontalResolution,\r
+  OUT UINT32                          *VerticalResolution,\r
+  OUT UINT32                          *ColorDepth,\r
+  OUT UINT32                          *RefreshRate\r
+  )\r
+{\r
+  TEXT_OUT_SPLITTER_PRIVATE_DATA  *Private;\r
+\r
+  if ((HorizontalResolution == NULL) ||\r
+      (VerticalResolution   == NULL) ||\r
+      (RefreshRate          == NULL) ||\r
+      (ColorDepth           == NULL)) {\r
+    return EFI_INVALID_PARAMETER;\r
+  }\r
+  //\r
+  // retrieve private data\r
+  //\r
+  Private               = UGA_DRAW_SPLITTER_PRIVATE_DATA_FROM_THIS (This);\r
+\r
+  *HorizontalResolution = Private->UgaHorizontalResolution;\r
+  *VerticalResolution   = Private->UgaVerticalResolution;\r
+  *ColorDepth           = Private->UgaColorDepth;\r
+  *RefreshRate          = Private->UgaRefreshRate;\r
+\r
+  return EFI_SUCCESS;\r
+}\r
+\r
+\r
+/**\r
+  Set the current video mode information.\r
+\r
+  @param  This                 The EFI_UGA_DRAW_PROTOCOL instance.\r
+  @param  HorizontalResolution The size of video screen in pixels in the X dimension.\r
+  @param  VerticalResolution   The size of video screen in pixels in the Y dimension.\r
+  @param  ColorDepth           Number of bits per pixel, currently defined to be 32.\r
+  @param  RefreshRate          The refresh rate of the monitor in Hertz.\r
+\r
+  @retval EFI_SUCCESS          Mode information returned.\r
+  @retval EFI_NOT_STARTED      Video display is not initialized. Call SetMode ()\r
+  @retval EFI_OUT_OF_RESOURCES Out of resources.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+ConSplitterUgaDrawSetMode (\r
+  IN  EFI_UGA_DRAW_PROTOCOL           *This,\r
+  IN UINT32                           HorizontalResolution,\r
+  IN UINT32                           VerticalResolution,\r
+  IN UINT32                           ColorDepth,\r
+  IN UINT32                           RefreshRate\r
+  )\r
+{\r
+  EFI_STATUS                             Status;\r
+  TEXT_OUT_SPLITTER_PRIVATE_DATA         *Private;\r
+  UINTN                                  Index;\r
+  EFI_STATUS                             ReturnStatus;\r
+  EFI_GRAPHICS_OUTPUT_PROTOCOL           *GraphicsOutput;\r
+  UINTN                                  NumberIndex;\r
+  UINTN                                  SizeOfInfo;\r
+  EFI_GRAPHICS_OUTPUT_MODE_INFORMATION   *Info;\r
+  EFI_UGA_DRAW_PROTOCOL                  *UgaDraw;\r
+\r
+  Private = UGA_DRAW_SPLITTER_PRIVATE_DATA_FROM_THIS (This);\r
+\r
+  ReturnStatus = EFI_SUCCESS;\r
+\r
+  //\r
+  // Update the Mode data\r
+  //\r
+  Private->UgaHorizontalResolution  = HorizontalResolution;\r
+  Private->UgaVerticalResolution    = VerticalResolution;\r
+  Private->UgaColorDepth            = ColorDepth;\r
+  Private->UgaRefreshRate           = RefreshRate;\r
+\r
+  //\r
+  // return the worst status met\r
+  //\r
+  for (Index = 0; Index < Private->CurrentNumberOfConsoles; Index++) {\r
+\r
+    GraphicsOutput = Private->TextOutList[Index].GraphicsOutput;\r
+    if (GraphicsOutput != NULL) {\r
+      //\r
+      // Find corresponding ModeNumber of this GraphicsOutput instance\r
+      //\r
+      for (NumberIndex = 0; NumberIndex < GraphicsOutput->Mode->MaxMode; NumberIndex ++) {\r
+        Status = GraphicsOutput->QueryMode (GraphicsOutput, (UINT32) NumberIndex, &SizeOfInfo, &Info);\r
+        if (EFI_ERROR (Status)) {\r
+          return Status;\r
+        }\r
+        if ((Info->HorizontalResolution == HorizontalResolution) && (Info->VerticalResolution == VerticalResolution)) {\r
+          FreePool (Info);\r
+          break;\r
+        }\r
+        FreePool (Info);\r
+      }\r
+\r
+      Status = GraphicsOutput->SetMode (GraphicsOutput, (UINT32) NumberIndex);\r
+      if (EFI_ERROR (Status)) {\r
+        ReturnStatus = Status;\r
+      }\r
+    } else if (FeaturePcdGet (PcdUgaConsumeSupport)){\r
+      UgaDraw = Private->TextOutList[Index].UgaDraw;\r
+      if (UgaDraw != NULL) {\r
+        Status = UgaDraw->SetMode (\r
+                          UgaDraw,\r
+                          HorizontalResolution,\r
+                          VerticalResolution,\r
+                          ColorDepth,\r
+                          RefreshRate\r
+                          );\r
+        if (EFI_ERROR (Status)) {\r
+          ReturnStatus = Status;\r
+        }\r
+      }\r
+    }\r
+  }\r
+\r
+  return ReturnStatus;\r
+}\r
+\r
+\r
+/**\r
+  Blt a rectangle of pixels on the graphics screen.\r
+\r
+  The following table defines actions for BltOperations.\r
+\r
+  EfiUgaVideoFill:\r
+    Write data from the  BltBuffer pixel (SourceX, SourceY)\r
+    directly to every pixel of the video display rectangle\r
+    (DestinationX, DestinationY)\r
+    (DestinationX + Width, DestinationY + Height).\r
+    Only one pixel will be used from the BltBuffer. Delta is NOT used.\r
+  EfiUgaVideoToBltBuffer:\r
+    Read data from the video display rectangle\r
+    (SourceX, SourceY) (SourceX + Width, SourceY + Height) and place it in\r
+    the BltBuffer rectangle (DestinationX, DestinationY )\r
+    (DestinationX + Width, DestinationY + Height). If DestinationX or\r
+    DestinationY is not zero then Delta must be set to the length in bytes\r
+    of a row in the BltBuffer.\r
+  EfiUgaBltBufferToVideo:\r
+    Write data from the  BltBuffer rectangle\r
+    (SourceX, SourceY) (SourceX + Width, SourceY + Height) directly to the\r
+    video display rectangle (DestinationX, DestinationY)\r
+    (DestinationX + Width, DestinationY + Height). If SourceX or SourceY is\r
+    not zero then Delta must be set to the length in bytes of a row in the\r
+    BltBuffer.\r
+  EfiUgaVideoToVideo:\r
+    Copy from the video display rectangle\r
+    (SourceX, SourceY) (SourceX + Width, SourceY + Height) .\r
+    to the video display rectangle (DestinationX, DestinationY)\r
+    (DestinationX + Width, DestinationY + Height).\r
+    The BltBuffer and Delta  are not used in this mode.\r
+\r
+  @param  This           Protocol instance pointer.\r
+  @param  BltBuffer      Buffer containing data to blit into video buffer. This\r
+                         buffer has a size of Width*Height*sizeof(EFI_UGA_PIXEL)\r
+  @param  BltOperation   Operation to perform on BlitBuffer and video memory\r
+  @param  SourceX        X coordinate of source for the BltBuffer.\r
+  @param  SourceY        Y coordinate of source for the BltBuffer.\r
+  @param  DestinationX   X coordinate of destination for the BltBuffer.\r
+  @param  DestinationY   Y coordinate of destination for the BltBuffer.\r
+  @param  Width          Width of rectangle in BltBuffer in pixels.\r
+  @param  Height         Hight of rectangle in BltBuffer in pixels.\r
+  @param  Delta          OPTIONAL\r
+\r
+  @retval EFI_SUCCESS            The Blt operation completed.\r
+  @retval EFI_INVALID_PARAMETER  BltOperation is not valid.\r
+  @retval EFI_DEVICE_ERROR       A hardware error occured writting to the video buffer.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+ConSplitterUgaDrawBlt (\r
+  IN  EFI_UGA_DRAW_PROTOCOL                         *This,\r
+  IN  EFI_UGA_PIXEL                                 *BltBuffer, OPTIONAL\r
+  IN  EFI_UGA_BLT_OPERATION                         BltOperation,\r
+  IN  UINTN                                         SourceX,\r
+  IN  UINTN                                         SourceY,\r
+  IN  UINTN                                         DestinationX,\r
+  IN  UINTN                                         DestinationY,\r
+  IN  UINTN                                         Width,\r
+  IN  UINTN                                         Height,\r
+  IN  UINTN                                         Delta         OPTIONAL\r
+  )\r
+{\r
+  EFI_STATUS                      Status;\r
+  TEXT_OUT_SPLITTER_PRIVATE_DATA  *Private;\r
+  UINTN                           Index;\r
+  EFI_STATUS                      ReturnStatus;\r
+  EFI_GRAPHICS_OUTPUT_PROTOCOL    *GraphicsOutput;\r
+\r
+  Private = UGA_DRAW_SPLITTER_PRIVATE_DATA_FROM_THIS (This);\r
+\r
+  ReturnStatus = EFI_SUCCESS;\r
+  //\r
+  // return the worst status met\r
+  //\r
+  for (Index = 0; Index < Private->CurrentNumberOfConsoles; Index++) {\r
+    GraphicsOutput = Private->TextOutList[Index].GraphicsOutput;\r
+    if (GraphicsOutput != NULL) {\r
+      Status = GraphicsOutput->Blt (\r
+                              GraphicsOutput,\r
+                              (EFI_GRAPHICS_OUTPUT_BLT_PIXEL *) BltBuffer,\r
+                              (EFI_GRAPHICS_OUTPUT_BLT_OPERATION) BltOperation,\r
+                              SourceX,\r
+                              SourceY,\r
+                              DestinationX,\r
+                              DestinationY,\r
+                              Width,\r
+                              Height,\r
+                              Delta\r
+                              );\r
+      if (EFI_ERROR (Status)) {\r
+        ReturnStatus = Status;\r
+      } else if (BltOperation == EfiUgaVideoToBltBuffer) {\r
+        //\r
+        // Only need to read the data into buffer one time\r
+        //\r
+        return EFI_SUCCESS;\r
+      }\r
+    }\r
+\r
+    if (Private->TextOutList[Index].UgaDraw != NULL && FeaturePcdGet (PcdUgaConsumeSupport)) {\r
+      Status = Private->TextOutList[Index].UgaDraw->Blt (\r
+                                                      Private->TextOutList[Index].UgaDraw,\r
+                                                      BltBuffer,\r
+                                                      BltOperation,\r
+                                                      SourceX,\r
+                                                      SourceY,\r
+                                                      DestinationX,\r
+                                                      DestinationY,\r
+                                                      Width,\r
+                                                      Height,\r
+                                                      Delta\r
+                                                      );\r
+      if (EFI_ERROR (Status)) {\r
+        ReturnStatus = Status;\r
+      } else if (BltOperation == EfiUgaVideoToBltBuffer) {\r
+        //\r
+        // Only need to read the data into buffer one time\r
+        //\r
+        return EFI_SUCCESS;\r
+      }\r
+    }\r
+  }\r
+\r
+  return ReturnStatus;\r
+}\r
+\r
+/**\r
+  Sets the output device(s) to a specified mode.\r
+\r
+  @param  Private                 Text Out Splitter pointer.\r
+  @param  ModeNumber              The mode number to set.\r
+\r
+**/\r
+VOID\r
+TextOutSetMode (\r
+  IN  TEXT_OUT_SPLITTER_PRIVATE_DATA  *Private,\r
+  IN  UINTN                           ModeNumber\r
+  )\r
+{\r
+  //\r
+  // No need to do extra check here as whether (Column, Row) is valid has\r
+  // been checked in ConSplitterTextOutSetCursorPosition. And (0, 0) should\r
+  // always be supported.\r
+  //\r
+  Private->TextOutMode.Mode          = (INT32) ModeNumber;\r
+  Private->TextOutMode.CursorColumn  = 0;\r
+  Private->TextOutMode.CursorRow     = 0;\r
+  Private->TextOutMode.CursorVisible = TRUE;\r
+\r
+  return;\r
+}\r

diff --git a/Vlv2TbltDevicePkg/PciPlatform/BoardPciPlatform.c b/Vlv2TbltDevicePkg/PciPlatform/BoardPciPlatform.c
new file mode 100644 (file)
index 0000000..1f26178
--- /dev/null
+++ b/Vlv2TbltDevicePkg/PciPlatform/BoardPciPlatform.c
@@ -0,0 +1,60 @@
+/** @file\r
+\r
+  Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+Module Name:\r
+\r
+\r
+    BoardPciPlatform.c\r
+\r
+Abstract:\r
+\r
+Revision History:\r
+--*/\r
+\r
+\r
+#include "PciPlatform.h"\r
+#include "PchRegs.h"\r
+#include "VlvAccess.h"\r
+\r
+#define R_INTEL_LAN_VENDOR_ID           0x00\r
+#define   V_INTEL_LAN_VENDOR_ID         0x8086     // INTEL 82574 Gbe Controller Vendor ID\r
+#define R_INTEL_LAN_DEVICE_ID           0x02\r
+#define   V_INTEL_LAN_DEVICE_ID         0x153E     // INTEL 82574 Gbe Controller Device ID\r
+\r
+//\r
+// Global variables for Option ROMs\r
+//\r
+\r
+#define ONBOARD_VIDEO_OPTION_ROM_FILE_GUID \\r
+{ 0xF2FE1FAA, 0xF04A, 0x4ba1, 0xAE, 0x73, 0xD1, 0x84, 0x6A, 0x6C, 0xD6, 0xD8 }\r
+\r
+#define PXE_UNDI_OPTION_ROM_INTELPXE_GUID \\r
+{0x49F2C48B, 0x4D8E, 0x4238, 0x8D, 0x82, 0x9B, 0x27, 0xF4, 0x38, 0x44, 0xB0}\r
+\r
+#define SATA_AHCI_ROM_GUID \\r
+  {0x592bfc62, 0xd817, 0x4d1a, 0x86, 0xf8, 0x33, 0x33, 0x4c, 0x9e, 0x90, 0xd8}\r
+\r
+#define NULL_ROM_FILE_GUID \\r
+{ 0x00000000, 0x0000, 0x0000, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }\r
+\r
+PCI_OPTION_ROM_TABLE mPciOptionRomTable[] = {\r
+  { ONBOARD_VIDEO_OPTION_ROM_FILE_GUID,     0, 0, 0x02, 0, IGD_VID, IGD_DID_VLV_A0, 0},\r
+  { ONBOARD_VIDEO_OPTION_ROM_FILE_GUID,     0, 0, 0x02, 0, IGD_VID, IGD_DID, 0},  // Desktop/Mobile IGD\r
+  { ONBOARD_VIDEO_OPTION_ROM_FILE_GUID,     0, 0, 0x02, 0, IGD_VID, IGD_DID_II, 0},  // Desktop/Mobile IGD\r
+  { ONBOARD_VIDEO_OPTION_ROM_FILE_GUID,     0, 0, 0x02, 0, IGD_VID, IGD_DID_QS, 0},\r
+  { NULL_ROM_FILE_GUID,                     0, 0, 0, 0, 0xffff, 0xffff, 0}\r
+};\r
+\r
+UINTN mSizeOptionRomTable =  sizeof(mPciOptionRomTable)/sizeof(PCI_OPTION_ROM_TABLE);\r
+\r
+\r

diff --git a/Vlv2TbltDevicePkg/PciPlatform/PciPlatform.c b/Vlv2TbltDevicePkg/PciPlatform/PciPlatform.c
new file mode 100644 (file)
index 0000000..1b59eee
--- /dev/null
+++ b/Vlv2TbltDevicePkg/PciPlatform/PciPlatform.c
@@ -0,0 +1,361 @@
+/** @file\r
+\r
+  Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+Module Name:\r
+\r
+\r
+    PciPlatform.c\r
+\r
+Abstract:\r
+--*/\r
+\r
+\r
+#include "PciPlatform.h"\r
+#include "PchRegs.h"\r
+#include "PchAccess.h"\r
+#include "VlvCommonDefinitions.h"\r
+#include "PlatformBootMode.h"\r
+\r
+#include <Library/BaseLib.h>\r
+#include <Library/BaseMemoryLib.h>\r
+#include <Protocol/CpuIo.h>\r
+#include <Protocol/PciIo.h>\r
+#include <Guid/SetupVariable.h>\r
+#include <Protocol/PciRootBridgeIo.h>\r
+#include "SetupMode.h"\r
+#include <Library/UefiBootServicesTableLib.h>\r
+#include <Library/UefiRuntimeServicesTableLib.h>\r
+#include <Library/DebugLib.h>\r
+#include <Protocol/FirmwareVolume.h>\r
+#include <Library/HobLib.h>\r
+#include <IndustryStandard/Pci22.h>\r
+\r
+extern  PCI_OPTION_ROM_TABLE  mPciOptionRomTable[];\r
+extern  UINTN                 mSizeOptionRomTable;\r
+\r
+EFI_PCI_PLATFORM_PROTOCOL mPciPlatform = {\r
+  PhaseNotify,\r
+  PlatformPrepController,\r
+  GetPlatformPolicy,\r
+  GetPciRom\r
+};\r
+\r
+EFI_HANDLE mPciPlatformHandle = NULL;\r
+\r
+\r
+SYSTEM_CONFIGURATION          mSystemConfiguration;\r
+\r
+EFI_STATUS\r
+GetRawImage (\r
+  IN EFI_GUID   *NameGuid,\r
+  IN OUT VOID   **Buffer,\r
+  IN OUT UINTN  *Size\r
+  )\r
+{\r
+  EFI_STATUS                    Status;\r
+  EFI_HANDLE                    *HandleBuffer;\r
+  UINTN                         HandleCount;\r
+  UINTN                         Index;\r
+  EFI_FIRMWARE_VOLUME_PROTOCOL  *Fv;\r
+  UINT32                        AuthenticationStatus;\r
+\r
+  Status = gBS->LocateHandleBuffer (\r
+                  ByProtocol,\r
+                  &gEfiFirmwareVolumeProtocolGuid,\r
+                  NULL,\r
+                  &HandleCount,\r
+                  &HandleBuffer\r
+                  );\r
+  if (EFI_ERROR (Status) || HandleCount == 0) {\r
+    return EFI_NOT_FOUND;\r
+  }\r
+\r
+  //\r
+  // Find desired image in all Fvs\r
+  //\r
+  for (Index = 0; Index < HandleCount; Index++) {\r
+    Status = gBS->HandleProtocol(\r
+                    HandleBuffer[Index],\r
+                    &gEfiFirmwareVolumeProtocolGuid,\r
+                    (VOID **) &Fv\r
+                    );\r
+\r
+    if ( EFI_ERROR ( Status ) ) {\r
+      return EFI_LOAD_ERROR;\r
+    }\r
+\r
+    //\r
+    // Try a raw file\r
+    //\r
+    *Buffer = NULL;\r
+    *Size = 0;\r
+    Status = Fv->ReadSection (\r
+                   Fv,\r
+                   NameGuid,\r
+                   EFI_SECTION_RAW,\r
+                   0,\r
+                   Buffer,\r
+                   Size,\r
+                   &AuthenticationStatus\r
+                   );\r
+\r
+    if ( !EFI_ERROR ( Status )) {\r
+        break;\r
+    }\r
+  }\r
+\r
+  if ( Index >= HandleCount ) {\r
+    return EFI_NOT_FOUND;\r
+  }\r
+\r
+  return EFI_SUCCESS;\r
+}\r
+\r
+EFI_STATUS\r
+EFIAPI    \r
+PhaseNotify (\r
+  IN EFI_PCI_PLATFORM_PROTOCOL              *This,\r
+  IN  EFI_HANDLE                                     HostBridge,\r
+  IN  EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PHASE  Phase,\r
+  IN  EFI_PCI_CHIPSET_EXECUTION_PHASE                ChipsetPhase\r
+  )\r
+{\r
+  return EFI_UNSUPPORTED;\r
+}\r
+\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+PlatformPrepController (\r
+  IN EFI_PCI_PLATFORM_PROTOCOL                      *This,\r
+  IN  EFI_HANDLE                                     HostBridge,\r
+  IN  EFI_HANDLE                                     RootBridge,\r
+  IN  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS    PciAddress,\r
+  IN  EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE   Phase,\r
+  IN  EFI_PCI_CHIPSET_EXECUTION_PHASE                ChipsetPhase\r
+  )\r
+{\r
+  return EFI_UNSUPPORTED;\r
+}\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+GetPlatformPolicy (\r
+  IN CONST EFI_PCI_PLATFORM_PROTOCOL        *This,\r
+  OUT EFI_PCI_PLATFORM_POLICY               *PciPolicy\r
+  )\r
+{\r
+  *PciPolicy = EFI_RESERVE_VGA_IO_ALIAS;\r
+  return EFI_SUCCESS;\r
+}\r
+\r
+/**\r
+  GetPciRom from platform specific location for specific PCI device\r
+\r
+  @param This        Protocol instance\r
+  @param PciHandle   Identify the specific PCI devic\r
+  @param RomImage    Returns the ROM Image memory location\r
+  @param RomSize     Returns Rom Image size\r
+\r
+  @retval EFI_SUCCESS\r
+  @retval EFI_NOT_FOUND\r
+  @retval  EFI_OUT_OF_RESOURCES\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI    \r
+GetPciRom (\r
+  IN CONST EFI_PCI_PLATFORM_PROTOCOL     *This,\r
+  IN EFI_HANDLE                           PciHandle,\r
+  OUT  VOID                               **RomImage,\r
+  OUT  UINTN                              *RomSize\r
+  )\r
+{\r
+  EFI_STATUS                    Status;\r
+  EFI_PCI_IO_PROTOCOL           *PciIo;\r
+  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;\r
+  UINTN                         Segment;\r
+  UINTN                         Bus;\r
+  UINTN                         Device;\r
+  UINTN                         Function;\r
+  UINT16                        VendorId;\r
+  UINT16                        DeviceId;\r
+  UINT16                        DeviceClass;\r
+  UINTN                         TableIndex;\r
+  UINT8                         Data8;\r
+  BOOLEAN                       MfgMode;\r
+  EFI_PLATFORM_SETUP_ID         *BootModeBuffer;\r
+\r
+  EFI_PEI_HOB_POINTERS        GuidHob;\r
+\r
+  MfgMode = FALSE;\r
+\r
+//\r
+// Check if system is in manufacturing mode.\r
+//\r
+  GuidHob.Raw = GetHobList ();\r
+  if (GuidHob.Raw == NULL) {\r
+    return EFI_NOT_FOUND;\r
+  }\r
+\r
+  if ((GuidHob.Raw = GetNextGuidHob (&gEfiPlatformBootModeGuid, GuidHob.Raw)) != NULL) {\r
+    BootModeBuffer = GET_GUID_HOB_DATA (GuidHob.Guid);\r
+    if (!CompareMem (&BootModeBuffer->SetupName, MANUFACTURE_SETUP_NAME,\r
+        StrSize (MANUFACTURE_SETUP_NAME)))\r
+      {\r
+       //\r
+        // System is in manufacturing mode.\r
+        //\r
+        MfgMode = TRUE;\r
+      }\r
+   }\r
+\r
+  Status = gBS->HandleProtocol (\r
+                  PciHandle,\r
+                  &gEfiPciIoProtocolGuid,\r
+                  (void **)&PciIo\r
+                  );\r
+  if (EFI_ERROR (Status)) {\r
+    return EFI_NOT_FOUND;\r
+  }\r
+\r
+  Status = gBS->LocateProtocol (\r
+                  &gEfiPciRootBridgeIoProtocolGuid,\r
+                  NULL,\r
+                  (void **)&PciRootBridgeIo\r
+                  );\r
+\r
+  if (EFI_ERROR (Status)) {\r
+    return EFI_NOT_FOUND;\r
+  }\r
+\r
+  PciIo->Pci.Read (PciIo, EfiPciIoWidthUint16, 0x0A, 1, &DeviceClass);\r
+\r
+  PciIo->GetLocation (PciIo, &Segment, &Bus, &Device, &Function);\r
+\r
+  PciIo->Pci.Read (PciIo, EfiPciIoWidthUint16, 0, 1, &VendorId);\r
+\r
+  PciIo->Pci.Read (PciIo, EfiPciIoWidthUint16, 2, 1, &DeviceId);\r
+\r
+  //\r
+  // WA for PCIe SATA card (SYBA SY-PEX400-40)\r
+  //\r
+  if ((VendorId == 0x1B21) && (DeviceId == 0x0612)) {\r
+    Data8 = 0x07;\r
+    PciIo->Pci.Write (PciIo, EfiPciIoWidthUint8, 4, 1, &Data8);\r
+  }\r
+\r
+    //\r
+    // Do not run RAID or AHCI Option ROM if IDE\r
+    //\r
+    if ( (DeviceClass == ((PCI_CLASS_MASS_STORAGE << 8 ) | PCI_CLASS_MASS_STORAGE_IDE)) ) {\r
+      return EFI_NOT_FOUND;\r
+    }\r
+\r
+    //\r
+    // Run PXE ROM only if Boot network is enabled and not in MFG mode\r
+    //\r
+    if (DeviceClass == ((PCI_CLASS_NETWORK << 8 ) | PCI_CLASS_NETWORK_ETHERNET)) {\r
+      if (((mSystemConfiguration.BootNetwork == 0) && (MfgMode == FALSE )) || (mSystemConfiguration.FastBoot == 1)) {\r
+      return EFI_NOT_FOUND;\r
+      }\r
+    }\r
+\r
+    //\r
+    // Loop through table of Onboard option rom descriptions\r
+    //\r
+    for (TableIndex = 0; mPciOptionRomTable[TableIndex].VendorId != 0xffff; TableIndex++) {\r
+\r
+      //\r
+      // See if the PCI device specified by PciHandle matches at device in mPciOptionRomTable\r
+      //\r
+      if (VendorId != mPciOptionRomTable[TableIndex].VendorId ||\r
+          DeviceId != mPciOptionRomTable[TableIndex].DeviceId ||\r
+          ((DeviceClass == ((PCI_CLASS_NETWORK << 8 ) | PCI_CLASS_NETWORK_ETHERNET)) &&\r
+           (mPciOptionRomTable[TableIndex].Flag != mSystemConfiguration.BootNetwork))  ) {\r
+        continue;\r
+      }\r
+\r
+      Status = GetRawImage(\r
+                 &mPciOptionRomTable[TableIndex].FileName,\r
+                 RomImage,\r
+                 RomSize\r
+                 );\r
+\r
+      if ((VendorId == IGD_VID) && (DeviceId == IGD_DID_VLV_A0)) {\r
+        *(UINT16 *)(((UINTN) *RomImage) + OPROM_DID_OFFSET) = IGD_DID_VLV_A0;\r
+      }\r
+\r
+      if ((VendorId == IGD_VID) && (DeviceId == IGD_DID_II)) {\r
+        *(UINT16 *)(((UINTN) *RomImage) + OPROM_DID_OFFSET) = IGD_DID_II;\r
+      }\r
+\r
+      if ((VendorId == IGD_VID) && (DeviceId == IGD_DID_0BE4)) {\r
+        *(UINT16 *)(((UINTN) *RomImage) + OPROM_DID_OFFSET) = IGD_DID_0BE4;\r
+      }\r
+\r
+      if ((VendorId == IGD_VID) && (DeviceId == IGD_DID_QS)) {\r
+        *(UINT16 *)(((UINTN) *RomImage) + OPROM_DID_OFFSET) = IGD_DID_QS;\r
+      }\r
+\r
+\r
+        if (EFI_ERROR (Status)) {\r
+          continue;\r
+        }\r
+        return EFI_SUCCESS;\r
+      }\r
+\r
+  return EFI_NOT_FOUND;\r
+}\r
+\r
+/**\r
+\r
+  @param  (Standard EFI Image entry - EFI_IMAGE_ENTRY_POINT)\r
+\r
+  @retval EFI_STATUS\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+PciPlatformDriverEntry (\r
+  IN EFI_HANDLE        ImageHandle,\r
+  IN EFI_SYSTEM_TABLE  *SystemTable\r
+  )\r
+{\r
+  EFI_STATUS  Status;\r
+  UINTN       VarSize;\r
+\r
+  VarSize = sizeof(SYSTEM_CONFIGURATION);\r
+  Status = gRT->GetVariable(\r
+                  L"Setup",\r
+                  &gEfiNormalSetupGuid,\r
+                  NULL,\r
+                  &VarSize,\r
+                  &mSystemConfiguration\r
+                  );\r
+  ASSERT_EFI_ERROR(Status);\r
+\r
+  //\r
+  // Install on a new handle\r
+  //\r
+  Status = gBS->InstallProtocolInterface (\r
+                  &mPciPlatformHandle,\r
+                  &gEfiPciPlatformProtocolGuid,\r
+                  EFI_NATIVE_INTERFACE,\r
+                  &mPciPlatform\r
+                  );\r
+\r
+  return Status;\r
+}\r
+\r
+\r

diff --git a/Vlv2TbltDevicePkg/PciPlatform/PciPlatform.h b/Vlv2TbltDevicePkg/PciPlatform/PciPlatform.h
new file mode 100644 (file)
index 0000000..7507644
--- /dev/null
+++ b/Vlv2TbltDevicePkg/PciPlatform/PciPlatform.h
@@ -0,0 +1,88 @@
+/*++\r
+\r
+  Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+Module Name:\r
+\r
+    PciPlatform.h\r
+\r
+Abstract:\r
+\r
+--*/\r
+#ifndef PCI_PLATFORM_H_\r
+#define PCI_PLATFORM_H_\r
+\r
+\r
+#include <PiDxe.h>\r
+#include "Platform.h"\r
+\r
+//\r
+// Produced Protocols\r
+//\r
+#include <Protocol/PciPlatform.h>\r
+\r
+#define IGD_DID_II                     0x0BE1\r
+#define IGD_DID_0BE4                   0x0BE4\r
+#define IGD_DID_VLV_A0                 0x0F31\r
+#define OPROM_DID_OFFSET               0x46\r
+\r
+typedef struct {\r
+  EFI_GUID  FileName;\r
+  UINTN     Segment;\r
+  UINTN     Bus;\r
+  UINTN     Device;\r
+  UINTN     Function;\r
+  UINT16    VendorId;\r
+  UINT16    DeviceId;\r
+  UINT8     Flag;\r
+} PCI_OPTION_ROM_TABLE;\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+PhaseNotify (\r
+  IN  EFI_PCI_PLATFORM_PROTOCOL                     *This,\r
+  IN  EFI_HANDLE                                    HostBridge,\r
+  IN  EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PHASE Phase,\r
+  IN  EFI_PCI_CHIPSET_EXECUTION_PHASE               ChipsetPhase\r
+  );\r
+\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+PlatformPrepController (\r
+  IN EFI_PCI_PLATFORM_PROTOCOL                      *This,\r
+  IN   EFI_HANDLE                                   HostBridge,\r
+  IN  EFI_HANDLE                                    RootBridge,\r
+  IN  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS   PciAddress,\r
+  IN  EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE  Phase,\r
+  IN  EFI_PCI_CHIPSET_EXECUTION_PHASE               ChipsetPhase\r
+  );\r
+\r
+EFI_STATUS\r
+EFIAPI    \r
+GetPlatformPolicy (\r
+  IN CONST EFI_PCI_PLATFORM_PROTOCOL                      *This,\r
+  OUT EFI_PCI_PLATFORM_POLICY                       *PciPolicy\r
+  );\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+GetPciRom (\r
+  IN CONST EFI_PCI_PLATFORM_PROTOCOL                      *This,\r
+  IN EFI_HANDLE                                     PciHandle,\r
+  OUT  VOID                                         **RomImage,\r
+  OUT  UINTN                                        *RomSize\r
+  );\r
+\r
+#endif\r
+\r
+\r

diff --git a/Vlv2TbltDevicePkg/PciPlatform/PciPlatform.inf b/Vlv2TbltDevicePkg/PciPlatform/PciPlatform.inf
new file mode 100644 (file)
index 0000000..a296c24
--- /dev/null
+++ b/Vlv2TbltDevicePkg/PciPlatform/PciPlatform.inf
@@ -0,0 +1,70 @@
+#/*++\r
+#\r
+# Copyright (c)  2003  - 2014, Intel Corporation. All rights reserved\r
+#                                                                                  \r\r
+# This program and the accompanying materials are licensed and made available under\r\r
+# the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+# The full text of the license may be found at                                     \r\r
+# http://opensource.org/licenses/bsd-license.php.                                  \r\r
+#                                                                                  \r\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+#                                                                                  \r\r
+\r
+#\r
+#  Module Name:\r
+#\r
+#    PciPlatform.inf\r
+#\r
+#  Abstract:\r
+#\r
+#    Component description file for PciPlatform module.\r
+#\r
+--*/\r
+\r
+[defines]\r
+  INF_VERSION          = 0x00010005\r
+  BASE_NAME            = PciPlatform\r
+  FILE_GUID            = E2441B64-7EF4-41fe-B3A3-8CAA7F8D3017\r
+  MODULE_TYPE          = DXE_DRIVER\r
+  VERSION_STRING       = 1.0\r
+  ENTRY_POINT          = PciPlatformDriverEntry\r
+\r
+[sources.common]\r
+  BoardPciPlatform.c\r
+  PciPlatform.c\r
+  PciPlatform.h\r
+\r
+[Guids]\r
+  gEfiNormalSetupGuid\r
+  gEfiPlatformBootModeGuid\r
+\r
+[Protocols]\r
+  gEfiPciPlatformProtocolGuid\r
+  gEfiCpuIoProtocolGuid\r
+  gEfiFirmwareVolumeProtocolGuid\r
+  gEfiPciRootBridgeIoProtocolGuid\r
+  gEfiPciIoProtocolGuid\r
+\r
+[Packages]\r
+  MdePkg/MdePkg.dec\r
+  MdeModulePkg/MdeModulePkg.dec\r
+  Vlv2TbltDevicePkg/PlatformPkg.dec\r
+  Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec\r
+  IntelFrameworkPkg/IntelFrameworkPkg.dec\r
+\r
+[LibraryClasses]\r
+  HobLib\r
+  UefiDriverEntryPoint\r
+  BaseLib\r
+  BaseMemoryLib\r
+  UefiDriverEntryPoint\r
+  UefiBootServicesTableLib\r
+  UefiRuntimeServicesTableLib\r
+  DxeServicesTableLib\r
+\r
+[BuildOptions]\r
+\r
+[Depex]\r
+  gEfiVariableArchProtocolGuid AND\r
+  gEfiVariableWriteArchProtocolGuid\r

diff --git a/Vlv2TbltDevicePkg/PlatformCpuInfoDxe/PlatformCpuInfoDxe.c b/Vlv2TbltDevicePkg/PlatformCpuInfoDxe/PlatformCpuInfoDxe.c
new file mode 100644 (file)
index 0000000..bd46a13
--- /dev/null
+++ b/Vlv2TbltDevicePkg/PlatformCpuInfoDxe/PlatformCpuInfoDxe.c
@@ -0,0 +1,65 @@
+/** @file\r
+\r
+  Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+Module Name:\r
+\r
+  PlatformCpuInfoDxe.c\r
+\r
+Abstract:\r
+  Platform Cpu Info driver to public platform related HOB data\r
+\r
+--*/\r
+\r
+#include "PlatformCpuInfoDxe.h"\r
+\r
+CHAR16    EfiPlatformCpuInfoVariable[] = L"PlatformCpuInfo";\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+PlatformCpuInfoInit (\r
+  IN EFI_HANDLE                         ImageHandle,\r
+  IN EFI_SYSTEM_TABLE                   *SystemTable\r
+  )\r
+{\r
+  EFI_STATUS                  Status;\r
+  EFI_PLATFORM_CPU_INFO       *PlatformCpuInfoPtr;\r
+  EFI_PEI_HOB_POINTERS        GuidHob;\r
+\r
+  //\r
+  // Get Platform Cpu Info HOB\r
+  //\r
+  GuidHob.Raw = GetHobList ();\r
+  while ((GuidHob.Raw = GetNextGuidHob (&gEfiPlatformCpuInfoGuid, GuidHob.Raw)) != NULL) {\r
+    PlatformCpuInfoPtr = GET_GUID_HOB_DATA (GuidHob.Guid);\r
+    GuidHob.Raw = GET_NEXT_HOB (GuidHob);\r
+\r
+      //\r
+      // Write the Platform CPU Info to volatile memory for runtime purposes.\r
+      // This must be done in its own driver because SetVariable protocol is dependent on chipset,\r
+      // which is dependent on CpuIo, PlatformInfo, and Metronome.\r
+      //\r
+      Status = gRT->SetVariable(\r
+                      EfiPlatformCpuInfoVariable,\r
+                      &gEfiVlv2VariableGuid,\r
+                      EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS,\r
+                      sizeof(EFI_PLATFORM_CPU_INFO),\r
+                      PlatformCpuInfoPtr\r
+                      );\r
+      if (EFI_ERROR(Status)) {\r
+        return Status;\r
+      }\r
+  }\r
+\r
+   return EFI_SUCCESS;\r
+}\r
+\r

diff --git a/Vlv2TbltDevicePkg/PlatformCpuInfoDxe/PlatformCpuInfoDxe.h b/Vlv2TbltDevicePkg/PlatformCpuInfoDxe/PlatformCpuInfoDxe.h
new file mode 100644 (file)
index 0000000..3d8803a
--- /dev/null
+++ b/Vlv2TbltDevicePkg/PlatformCpuInfoDxe/PlatformCpuInfoDxe.h
@@ -0,0 +1,34 @@
+/*++\r
+\r
+  Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+\r
+Module Name:\r
+  PlatformCpuInfoDxe.h\r
+\r
+Abstract:\r
+  Platform Cpu Info Driver.\r
+\r
+--*/\r
+\r
+#ifndef _PLATFORM_CPU_INFO_DRIVER_H_\r
+#define _PLATFORM_CPU_INFO_DRIVER_H_\r
+\r
+#include "PiDxe.h"\r
+#include "Library/HobLib.h"\r
+#include "Guid/GlobalVariable.h"\r
+#include "Guid/AcpiVariableCompatibility.h"\r
+#include "Guid/PlatformCpuInfo.h"\r
+#include "Library/UefiRuntimeServicesTableLib.h"\r
+#include <Guid/Vlv2Variable.h>\r
+\r
+#endif\r

diff --git a/Vlv2TbltDevicePkg/PlatformCpuInfoDxe/PlatformCpuInfoDxe.inf b/Vlv2TbltDevicePkg/PlatformCpuInfoDxe/PlatformCpuInfoDxe.inf
new file mode 100644 (file)
index 0000000..a0e99fb
--- /dev/null
+++ b/Vlv2TbltDevicePkg/PlatformCpuInfoDxe/PlatformCpuInfoDxe.inf
@@ -0,0 +1,61 @@
+#/*++\r
+#\r
+# Copyright (c)  1999  - 2014, Intel Corporation. All rights reserved\r
+#                                                                                  \r\r
+# This program and the accompanying materials are licensed and made available under\r\r
+# the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+# The full text of the license may be found at                                     \r\r
+# http://opensource.org/licenses/bsd-license.php.                                  \r\r
+#                                                                                  \r\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+#                                                                                  \r\r
+\r
+#\r
+#  Module Name:\r
+#\r
+#   PlatformCpuInfoDxe.inf\r
+#\r
+#  Abstract:\r
+#\r
+#\r
+--*/\r
+\r
+\r
+[Defines]\r
+  INF_VERSION          = 0x00010005\r
+  BASE_NAME            = PlatformCpuInfoDxe\r
+  FILE_GUID            = 025F738B-4EBD-4d55-B728-5F421B601F20\r
+  MODULE_TYPE          = DXE_DRIVER\r
+  VERSION_STRING       = 1.0\r
+  ENTRY_POINT          = PlatformCpuInfoInit\r
+\r
+[Sources]\r
+  PlatformCpuInfoDxe.c\r
+  PlatformCpuInfoDxe.h\r
+\r
+[Guids]\r
+  gEfiPlatformCpuInfoGuid\r
+  gEfiVlv2VariableGuid\r
+\r
+[Packages]\r
+  MdePkg/MdePkg.dec\r
+  MdeModulePkg/MdeModulePkg.dec\r
+  Vlv2TbltDevicePkg/PlatformPkg.dec\r
+  IA32FamilyCpuPkg/IA32FamilyCpuPkg.dec #CpuConfigLib.h\r
+  Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec\r
+  IntelFrameworkModulePkg/IntelFrameworkModulePkg.dec\r
+\r
+[LibraryClasses]\r
+  HobLib\r
+  UefiRuntimeServicesTableLib\r
+  UefiDriverEntryPoint\r
+\r
+[BuildOptions]\r
+  MSFT:*_*_*_CC_FLAGS = /Od /GL-\r
+  INTEL:*_*_*_CC_FLAGS = /Od /GL-\r
+\r
+[Depex]\r
+  gEfiVariableArchProtocolGuid AND\r
+  gEfiVariableWriteArchProtocolGuid\r
+\r

diff --git a/Vlv2TbltDevicePkg/PlatformDxe/AzaliaVerbTable.h b/Vlv2TbltDevicePkg/PlatformDxe/AzaliaVerbTable.h
new file mode 100644 (file)
index 0000000..47a2d1a
--- /dev/null
+++ b/Vlv2TbltDevicePkg/PlatformDxe/AzaliaVerbTable.h
@@ -0,0 +1,252 @@
+/*++\r
+\r
+  Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+--*/\r
+\r
+UINT32 mAzaliaVerbTableData12[] = {\r
+  //\r
+  // Audio Verb Table - 0x80862805\r
+  //\r
+  // Pin Widget 5 - PORT B\r
+  0x20471C10,\r
+  0x20471D00,\r
+  0x20471E56,\r
+  0x20471F18,\r
+\r
+  // Pin Widget 6 - PORT C\r
+  0x20571C20,\r
+  0x20571D00,\r
+  0x20571E56,\r
+  0x20571F18,\r
+\r
+  // Pin Widget 7 - PORT D\r
+  0x20671C30,\r
+  0x20671D00,\r
+  0x20671E56,\r
+  0x20671F58\r
+};\r
+\r
+\r
+PCH_AZALIA_VERB_TABLE mAzaliaVerbTable[] = {\r
+  {\r
+    //\r
+    // VerbTable:\r
+    //  Revision ID = 0xFF, support all steps\r
+    //  Codec Verb Table For AZALIA\r
+    //  Codec Address: CAd value (0/1/2)\r
+    //  Codec Vendor:  0x10EC0880\r
+    //\r
+    {\r
+      0x10EC0880,     // Vendor ID/Device ID\r
+      0x0000,         // SubSystem ID\r
+      0xFF,           // Revision ID\r
+      0x01,           // Front panel support (1=yes, 2=no)\r
+      0x000A,         // Number of Rear Jacks = 10\r
+      0x0002          // Number of Front Jacks = 2\r
+    },\r
+    0                 // Pointer to verb table data, need to be inited in the code.\r
+  },\r
+  {\r
+    //\r
+    // Revision ID >= 0x03\r
+    // Codec Verb Table For AZALIA\r
+    // Codec Address: CAd value (0/1/2)\r
+    // Codec Vendor: 0x434D4980\r
+    //\r
+    {\r
+      0x434D4980,     // Vendor ID/Device ID\r
+      0x0000,         // SubSystem ID\r
+      0x00,           // Revision ID\r
+      0x01,           // Front panel support (1=yes, 2=no)\r
+      0x0009,         // Number of Rear Jacks = 9\r
+      0x0002          // Number of Front Jacks = 2\r
+    },\r
+    0                 // Pointer to verb table data, need to be inited in the code.\r
+  },\r
+  {\r
+    //\r
+    // Lawndale Azalia Audio Codec Verb Table\r
+    // Revision ID = 0x00\r
+    // Codec Address: CAd value (0/1/2)\r
+    // Codec Vendor: 0x11D41984\r
+    //\r
+    {\r
+      0x11D41984,     // Vendor ID/Device ID\r
+      0x0000,         // SubSystem ID\r
+      0x04,           // Revision ID\r
+      0x01,           // Front panel support (1=yes, 2=no)\r
+      0x0009,         // Number of Rear Jacks = 9\r
+      0x0002          // Number of Front Jacks = 2\r
+    },\r
+    0                 // Pointer to verb table data, need to be inited in the code.\r
+  },\r
+  {\r
+    //\r
+    // VerbTable:\r
+    //  Revision ID = 0xFF, support all steps\r
+    //  Codec Verb Table For AZALIA\r
+    //  Codec Address: CAd value (0/1/2)\r
+    //  Codec Vendor: 0x11D41986\r
+    //\r
+    {\r
+      0x11D41986,     // Vendor ID/Device ID\r
+      0x0001,         // SubSystem ID\r
+      0xFF,           // Revision ID\r
+      0x01,           // Front panel support (1=yes, 2=no)\r
+      0x000A,         // Number of Rear Jacks = 8\r
+      0x0002          // Number of Front Jacks = 2\r
+    },\r
+    0                 // Pointer to verb table data, need to be inited in the code.\r
+  },\r
+  {\r
+    //\r
+    // VerbTable: (for Slim River, FFDS3)\r
+    //  Revision ID = 0x00\r
+    //  Codec Verb Table For AZALIA\r
+    //  Codec Address: CAd value (0/1/2)\r
+    //  Codec Vendor: 0x10EC0272\r
+    //\r
+    {\r
+      0x10EC0272,     // Vendor ID/Device ID\r
+      0x0000,         // SubSystem ID\r
+      0x00,           // Revision ID\r
+      0x01,           // Front panel support (1=yes, 2=no)\r
+      0x000E,         // Number of Rear Jacks\r
+      0x0002          // Number of Front Jacks\r
+    },\r
+    0                 // Pointer to verb table data, need to be inited in the code.\r
+  },\r
+  {\r
+    //\r
+    //  VerbTable: (for Buffalo Trail)\r
+    //  Revision ID = 0x00\r
+    //  Codec Verb Table For AZALIA\r
+    //  Codec Address: CAd value (0/1/2)\r
+    //  Codec Vendor: 0x10EC0269\r
+    //\r
+    {\r
+      0x10EC0269,     // Vendor ID/Device ID\r
+      0x0000,         // SubSystem ID\r
+      0x00,           // Revision ID\r
+      0x01,           // Front panel support (1=yes, 2=no)\r
+      0x000A,         // Number of Rear Jacks\r
+      0x0002          // Number of Front Jacks\r
+    },\r
+    0                 // Pointer to verb table data, need to be inited in the code.\r
+  },\r
+  {\r
+    //\r
+    //  VerbTable: (RealTek ALC888)\r
+    //  Revision ID = 0xFF\r
+    //  Codec Verb Table For Redfort\r
+    //  Codec Address: CAd value (0/1/2)\r
+    //  Codec Vendor: 0x10EC0888\r
+    //\r
+    {\r
+      0x10EC0888,     // Vendor ID/Device ID\r
+      0x0000,         // SubSystem ID\r
+      0xFF,           // Revision ID\r
+      0x01,           // Front panel support (1=yes, 2=no)\r
+      0x000B,         // Number of Rear Jacks\r
+      0x0002          // Number of Front Jacks\r
+    },\r
+    0                 // Pointer to verb table data, need to be inited in the code.\r
+  },\r
+  {\r
+    //\r
+    //  VerbTable: (RealTek ALC885)\r
+    //  Revision ID = 0xFF\r
+    //  Codec Verb Table For Redfort\r
+    //  Codec Address: CAd value (0/1/2)\r
+    //  Codec Vendor: 0x10EC0885\r
+    //\r
+    {\r
+      0x10EC0885,     // Vendor ID/Device ID\r
+      0x0000,         // SubSystem ID\r
+      0xFF,           // Revision ID\r
+      0x01,           // Front panel support (1=yes, 2=no)\r
+      0x000B,         // Number of Rear Jacks\r
+      0x0002          // Number of Front Jacks\r
+    },\r
+    0                 // Pointer to verb table data, need to be inited in the code.\r
+  },\r
+  {\r
+    //\r
+    //  VerbTable: (IDT 92HD81)\r
+    //  Revision ID = 0xFF\r
+    //  Codec Vendor: 0x111D7605\r
+    //\r
+    {\r
+      0x111D76d5,     // Vendor ID/Device ID\r
+      0x0000,         // SubSystem ID\r
+      0xFF,           // Revision ID\r
+      0x01,           // Front panel support (1=yes, 2=no)\r
+      0x0008,         // Number of Rear Jacks\r
+      0x0002          // Number of Front Jacks\r
+    },\r
+    0                 // Pointer to verb table data, need to be inited in the code.\r
+  },\r
+  {\r
+    //\r
+    //  VerbTable: (Intel VLV HDMI)\r
+    //  Revision ID = 0xFF\r
+    //  Codec Verb Table For EmeraldLake/LosLunas\r
+    //  Codec Vendor: 0x80862804\r
+    //\r
+    {\r
+      0x80862882,     // Vendor ID/Device ID\r
+      0x0000,         // SubSystem ID\r
+      0xFF,           // Revision ID\r
+      0x02,           // Front panel support (1=yes, 2=no)\r
+      0x0003,         // Number of Rear Jacks\r
+      0x0000          // Number of Front Jacks\r
+    },\r
+    0                 // Pointer to verb table data, need to be inited in the code.\r
+  },\r
+  {\r
+    //\r
+    // VerbTable: (RealTek ALC262)\r
+    //  Revision ID = 0xFF, support all steps\r
+    //  Codec Verb Table For AZALIA\r
+    //  Codec Address: CAd value (0/1/2)\r
+    //  Codec Vendor:  0x10EC0262\r
+    //\r
+    {\r
+      0x10EC0262,     // Vendor ID/Device ID\r
+      0x0000,         // SubSystem ID\r
+      0xFF,           // Revision ID\r
+      0x01,           // Front panel support (1=yes, 2=no)\r
+      0x000B,         // Number of Rear Jacks = 11\r
+      0x0002          // Number of Front Jacks = 2\r
+    },\r
+    0                 // Pointer to verb table data, need to be inited in the code.\r
+  },\r
+  {\r
+    //\r
+    //  VerbTable: (RealTek ALC282)\r
+    //  Revision ID = 0xff\r
+    //  Codec Verb Table For Azalia on SharkBay-WhiteBluff refresh and Haswell ULT FFRD Harris Beach, WTM1, WTM2iCRB\r
+    //  Codec Address: CAd value (0/1/2)\r
+    //  Codec Vendor: 0x10EC0282\r
+    //\r
+    {\r
+      0x10EC0282, // Vendor ID/Device ID\r
+      0x0000,     // SubSystem ID\r
+      0xff,       // Revision ID\r
+      0x01,       // Front panel support (1=yes, 2=no)\r
+      0x000C,     // Number of Rear Jacks, 0x0010 for Harris Beach, 0x000B for WTM1 & WTM2iCRB\r
+      0x0002      // Number of Front Jacks\r
+    },\r
+    0             // Pointer to verb table data, need to be inited in the code.\r
+  }\r
+};\r

diff --git a/Vlv2TbltDevicePkg/PlatformDxe/BoardId.c b/Vlv2TbltDevicePkg/PlatformDxe/BoardId.c
new file mode 100644 (file)
index 0000000..5b6139b
--- /dev/null
+++ b/Vlv2TbltDevicePkg/PlatformDxe/BoardId.c
@@ -0,0 +1,228 @@
+/** @file\r
+\r
+  Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+Module Name:\r
+\r
+\r
+  BoardId.c\r
+\r
+Abstract:\r
+\r
+  Initialization for the board ID.\r
+\r
+  This code should be common across a chipset family of products.\r
+\r
+\r
+\r
+--*/\r
+\r
+#include "PchRegs.h"\r
+#include "PlatformDxe.h"\r
+#include <Guid/IdccData.h>\r
+#include <Guid/EfiVpdData.h>\r
+#include <Protocol/DataHub.h>\r
+\r
+\r
+extern EFI_GUID mPlatformDriverGuid;\r
+\r
+//\r
+// Global module data\r
+//\r
+UINT32 mBoardId;\r
+UINT8  mBoardIdIndex;\r
+EFI_BOARD_FEATURES mBoardFeatures;\r
+UINT16 mSubsystemDeviceId;\r
+UINT16 mSubsystemAudioDeviceId;\r
+CHAR8  BoardAaNumber[7];\r
+BOOLEAN mFoundAANum;\r
+\r
+/**\r
+\r
+  Write the boardid variable if it does not already exist.\r
+\r
+**/\r
+VOID\r
+InitializeBoardId (\r
+  )\r
+{\r
+\r
+  UINT32                        BoardIdBufferSize;\r
+  EFI_IDCC_BOARD_FORM_FACTOR    IdccBoardFormFactor;\r
+  EFI_DATA_HUB_PROTOCOL         *DataHub;\r
+  EFI_STATUS                    Status;\r
+  DMI_DATA                      DmiDataVariable;\r
+  UINTN                         Size;\r
+#if defined(DUPLICATE_AA_NO_BASE_ADDR)\r
+  CHAR8                         DuplicateAaNoAscii[sizeof(DmiDataVariable.BaseBoardVersion)];\r
+  UINTN                         iter;\r
+#endif\r
+#if defined(GPIO_BOARD_ID_SUPPORT) && GPIO_BOARD_ID_SUPPORT != 0\r
+  UINT8                         Data8;\r
+#endif\r
+\r
+  //\r
+  // Update data from the updatable DMI data area\r
+  //\r
+  Size = sizeof (DMI_DATA);\r
+  SetMem(&DmiDataVariable, Size, 0xFF);\r
+  Status = gRT->GetVariable (\r
+                  DMI_DATA_NAME,\r
+                  &gDmiDataGuid,\r
+                  NULL,\r
+                  &Size,\r
+                  &DmiDataVariable\r
+                  );\r
+\r
+#if defined(DUPLICATE_AA_NO_BASE_ADDR)\r
+  //\r
+  // Get AA# from flash descriptor region\r
+  //\r
+  EfiSetMem(DuplicateAaNoAscii, sizeof(DuplicateAaNoAscii), 0xFF);\r
+  FlashRead((UINT8 *)(UINTN)DUPLICATE_AA_NO_BASE_ADDR,\r
+            (UINT8 *)DuplicateAaNoAscii,\r
+            sizeof(DuplicateAaNoAscii));\r
+\r
+  //\r
+  // Validate AA# read from VPD\r
+  //\r
+  for (iter = 0; iter < sizeof(DuplicateAaNoAscii); iter++) {\r
+     if ((DuplicateAaNoAscii[iter] != 0xFF) &&\r
+         (DuplicateAaNoAscii[iter] != DmiDataVariable.BaseBoardVersion[iter])) {\r
+       DmiDataVariable.BaseBoardVersion[iter] = DuplicateAaNoAscii[iter];\r
+     }\r
+  }\r
+\r
+  Status = EFI_SUCCESS;\r
+#endif\r
+\r
+  mFoundAANum = FALSE;\r
+\r
+  //\r
+  // No variable...no copy\r
+  //\r
+  if (EFI_ERROR (Status)) {\r
+    mBoardIdIndex = 0; // If we can't find the BoardId in the table, use the first entry\r
+  } else {\r
+       //\r
+    // This is the correct method of checking for AA#.\r
+    //\r
+    CopyMem(&BoardAaNumber, ((((UINT8*)&DmiDataVariable.BaseBoardVersion)+2)), 6);\r
+    BoardAaNumber[6] = 0;\r
+    for (mBoardIdIndex = 0; mBoardIdIndex < mBoardIdDecodeTableSize; mBoardIdIndex++) {\r
+      if (AsciiStrnCmp(mBoardIdDecodeTable[mBoardIdIndex].AaNumber, BoardAaNumber, 6) == 0) {\r
+        mFoundAANum = TRUE;\r
+        break;\r
+      }\r
+    }\r
+\r
+    if(!mFoundAANum) {\r
+       //\r
+      // Add check for AA#'s that is programmed without the AA as leading chars.\r
+      //\r
+      CopyMem(&BoardAaNumber, (((UINT8*)&DmiDataVariable.BaseBoardVersion)), 6);\r
+      BoardAaNumber[6] = 0;\r
+      for (mBoardIdIndex = 0; mBoardIdIndex < mBoardIdDecodeTableSize; mBoardIdIndex++) {\r
+        if (AsciiStrnCmp(mBoardIdDecodeTable[mBoardIdIndex].AaNumber, BoardAaNumber, 6) == 0) {\r
+          mFoundAANum = TRUE;\r
+          break;\r
+        }\r
+      }\r
+    }\r
+  }\r
+\r
+#if defined(GPIO_BOARD_ID_SUPPORT) && GPIO_BOARD_ID_SUPPORT != 0\r
+  //\r
+  // If we can't find the BoardAA# in the table, find BoardId\r
+  //\r
+  if (mFoundAANum != TRUE) {\r
+    //\r
+    // BoardID BIT    Location\r
+    //  0             GPIO33  (ICH)\r
+    //  1             GPIO34  (ICH)\r
+    //\r
+    Data8 = IoRead8(GPIO_BASE_ADDRESS + R_PCH_GPIO_SC_LVL2);\r
+\r
+    //\r
+    // BoardId[0]\r
+    //\r
+    mBoardId = (UINT32)((Data8 >> 1) & BIT0);\r
+    //\r
+    // BoardId[1]\r
+    //\r
+    mBoardId |= (UINT32)((Data8 >> 1) & BIT1);\r
+\r
+    for (mBoardIdIndex = 0; mBoardIdIndex < mBoardIdDecodeTableSize; mBoardIdIndex++) {\r
+      if (mBoardIdDecodeTable[mBoardIdIndex].BoardId == mBoardId) {\r
+        break;\r
+      }\r
+    }\r
+#endif\r
+    if (mBoardIdIndex == mBoardIdDecodeTableSize) {\r
+      mBoardIdIndex = 0; // If we can't find the BoardId in the table, use the first entry\r
+    }\r
+#if defined(GPIO_BOARD_ID_SUPPORT) && GPIO_BOARD_ID_SUPPORT != 0\r
+  }\r
+#endif\r
+\r
+  mBoardFeatures = mBoardIdDecodeTable[mBoardIdIndex].Features;\r
+  mSubsystemDeviceId = mBoardIdDecodeTable[mBoardIdIndex].SubsystemDeviceId;\r
+  mSubsystemAudioDeviceId = mBoardIdDecodeTable[mBoardIdIndex].AudioSubsystemDeviceId;\r
+\r
+  //\r
+  // Set the BoardFeatures variable\r
+  //\r
+  BoardIdBufferSize = sizeof (mBoardFeatures);\r
+  gRT->SetVariable (\r
+         BOARD_FEATURES_NAME,\r
+         &gEfiBoardFeaturesGuid,\r
+         EFI_VARIABLE_NON_VOLATILE |\r
+         EFI_VARIABLE_BOOTSERVICE_ACCESS |\r
+         EFI_VARIABLE_RUNTIME_ACCESS,\r
+         BoardIdBufferSize,\r
+         &mBoardFeatures\r
+         );\r
+\r
+  //\r
+  // Get the Data Hub protocol\r
+  //\r
+  Status = gBS->LocateProtocol (\r
+                  &gEfiDataHubProtocolGuid,\r
+                  NULL,\r
+                  (VOID **) &DataHub\r
+                  );\r
+  if (!(EFI_ERROR(Status))) {\r
+    //\r
+    // Fill out data\r
+    //\r
+    IdccBoardFormFactor.IdccHeader.Type = EFI_IDCC_BOARD_FORM_FACTOR_TYPE;\r
+    IdccBoardFormFactor.IdccHeader.RecordLength = sizeof(EFI_IDCC_BOARD_FORM_FACTOR);\r
+    if ((mBoardFeatures & B_BOARD_FEATURES_FORM_FACTOR_ATX) || (mBoardFeatures & B_BOARD_FEATURES_FORM_FACTOR_MICRO_ATX)) {\r
+        IdccBoardFormFactor.BoardFormFactor = ATX_FORM_FACTOR; // ATX\r
+    } else {\r
+        IdccBoardFormFactor.BoardFormFactor = BTX_FORM_FACTOR; // BTX\r
+    }\r
+\r
+    //\r
+    // Publish the Board Form Factor value for IDCC\r
+    //\r
+    Status = DataHub->LogData (\r
+                        DataHub,\r
+                        &gIdccDataHubGuid,\r
+                        &mPlatformDriverGuid,\r
+                        EFI_DATA_RECORD_CLASS_DATA,\r
+                        &IdccBoardFormFactor,\r
+                        sizeof(EFI_IDCC_BOARD_FORM_FACTOR)\r
+                        );\r
+  }\r
+}\r
+\r

diff --git a/Vlv2TbltDevicePkg/PlatformDxe/BoardIdDecode.c b/Vlv2TbltDevicePkg/PlatformDxe/BoardIdDecode.c
new file mode 100644 (file)
index 0000000..cf9b904
--- /dev/null
+++ b/Vlv2TbltDevicePkg/PlatformDxe/BoardIdDecode.c
@@ -0,0 +1,134 @@
+/** @file\r
+\r
+  Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+Module Name:\r
+\r
+\r
+  BoardIdDecode.c\r
+\r
+Abstract:\r
+\r
+--*/\r
+\r
+#include "PchRegs.h"\r
+#include "PlatformDxe.h"\r
+#include "Platform.h"\r
+\r
+\r
+//\r
+// Define macros to build data structure signatures from characters.\r
+//\r
+#define EFI_SIGNATURE_16(A, B)        ((A) | (B << 8))\r
+#define EFI_SIGNATURE_32(A, B, C, D)  (EFI_SIGNATURE_16 (A, B) | (EFI_SIGNATURE_16 (C, D) << 16))\r
+#define EFI_SIGNATURE_64(A, B, C, D, E, F, G, H) \\r
+    (EFI_SIGNATURE_32 (A, B, C, D) | ((UINT64) (EFI_SIGNATURE_32 (E, F, G, H)) << 32))\r
+\r
+BOARD_ID_DECODE mBoardIdDecodeTable[] = {\r
+  //\r
+  // Board ID, Board Features bitmap, Subsystem Device ID\r
+  // This is a dummy entry that has to exist. Do not delete, just make a generic entry that fit for product.\r
+  //\r
+  {\r
+       MW_ITX_MPCIE_LVDS_LOEM_AA,\r
+    MW_ITX_MPCIE_LVDS_LOEM_ID,\r
+    B_BOARD_FEATURES_FORM_FACTOR_ATX |\r
+    B_BOARD_FEATURES_SIO_COM2 |\r
+    B_BOARD_FEATURES_2_C0_MEMORY_SLOT |\r
+    V_BOARD_FEATURES_SLEEP_S3 |\r
+    B_BOARD_FEATURES_PS2WAKEFROMS5 |\r
+    B_BOARD_FEATURES_LVDS |\r
+    B_BOARD_FEATURES_VERB_TABLE1,\r
+    V_DEFAULT_SUBSYSTEM_DEVICE_ID,\r
+    0xD625,\r
+    EFI_SIGNATURE_64('M','W','P','N','T','1','0','N')\r
+  },\r
+\r
+  {\r
+        MW_ITX_MPCIE_LVDS_CHANNEL_AA,\r
+    MW_ITX_MPCIE_LVDS_CHANNEL_ID,\r
+    B_BOARD_FEATURES_FORM_FACTOR_ATX |\r
+    B_BOARD_FEATURES_SIO_COM2 |\r
+    B_BOARD_FEATURES_2_C0_MEMORY_SLOT |\r
+    V_BOARD_FEATURES_SLEEP_S3 |\r
+    B_BOARD_FEATURES_PS2WAKEFROMS5 |\r
+    B_BOARD_FEATURES_LVDS |\r
+    B_BOARD_FEATURES_VERB_TABLE1,\r
+    V_DEFAULT_SUBSYSTEM_DEVICE_ID,\r
+    0xD625,\r
+    EFI_SIGNATURE_64('M','W','P','N','T','1','0','N')\r
+  },\r
+\r
+  {\r
+       MW_ITX_MPCIE_CHANNEL_AA,\r
+    MW_ITX_MPCIE_CHANNEL_ID,\r
+    B_BOARD_FEATURES_FORM_FACTOR_ATX |\r
+    B_BOARD_FEATURES_SIO_COM2 |\r
+    B_BOARD_FEATURES_2_C0_MEMORY_SLOT |\r
+    V_BOARD_FEATURES_SLEEP_S3 |\r
+    B_BOARD_FEATURES_PS2WAKEFROMS5 |\r
+    B_BOARD_FEATURES_VERB_TABLE1,\r
+    V_DEFAULT_SUBSYSTEM_DEVICE_ID,\r
+    0xD625,\r
+    EFI_SIGNATURE_64('M','W','P','N','T','1','0','N')\r
+  },\r
+\r
+  {\r
+       KT_ITX_MPCIE_LVDS_LOEM_AA,\r
+    KT_ITX_MPCIE_LVDS_LOEM_ID,\r
+    B_BOARD_FEATURES_FORM_FACTOR_ATX |\r
+    B_BOARD_FEATURES_SIO_COM2 |\r
+    B_BOARD_FEATURES_2_C0_MEMORY_SLOT |\r
+    V_BOARD_FEATURES_SLEEP_S3 |\r
+    B_BOARD_FEATURES_PS2WAKEFROMS5 |\r
+    B_BOARD_FEATURES_LVDS |\r
+    B_BOARD_FEATURES_VERB_TABLE2,\r
+    V_DEFAULT_SUBSYSTEM_DEVICE_ID_KT,\r
+    0xD626,\r
+    EFI_SIGNATURE_64('K','T','P','N','T','1','0','N')\r
+  },\r
+\r
+  {\r
+       KT_ITX_CHANNEL_AA,\r
+    KT_ITX_CHANNEL_ID,\r
+    B_BOARD_FEATURES_FORM_FACTOR_ATX |\r
+    B_BOARD_FEATURES_SIO_COM2 |\r
+    B_BOARD_FEATURES_2_C0_MEMORY_SLOT |\r
+    V_BOARD_FEATURES_SLEEP_S3 |\r
+    B_BOARD_FEATURES_PS2WAKEFROMS5 |\r
+    B_BOARD_FEATURES_NO_MINIPCIE |\r
+    B_BOARD_FEATURES_VERB_TABLE2,\r
+    V_DEFAULT_SUBSYSTEM_DEVICE_ID_KT,\r
+    0xD626,\r
+    EFI_SIGNATURE_64('K','T','P','N','T','1','0','N')\r
+  },\r
+\r
+  {\r
+       KT_ITX_LOEM_AA,\r
+    KT_ITX_LOEM_ID,\r
+    B_BOARD_FEATURES_FORM_FACTOR_ATX |\r
+    B_BOARD_FEATURES_SIO_COM2 |\r
+    B_BOARD_FEATURES_2_C0_MEMORY_SLOT |\r
+    V_BOARD_FEATURES_SLEEP_S3 |\r
+    B_BOARD_FEATURES_PS2WAKEFROMS5 |\r
+    B_BOARD_FEATURES_NO_MINIPCIE |\r
+    B_BOARD_FEATURES_VERB_TABLE2,\r
+    V_DEFAULT_SUBSYSTEM_DEVICE_ID_KT,\r
+    0xD626,\r
+    EFI_SIGNATURE_64('K','T','P','N','T','1','0','N')\r
+  }\r
+};\r
+\r
+UINTN mBoardIdDecodeTableSize = sizeof (mBoardIdDecodeTable) /\r
+                                sizeof (mBoardIdDecodeTable[0]);\r
+\r
+\r

diff --git a/Vlv2TbltDevicePkg/PlatformDxe/BoardIdDecode.h b/Vlv2TbltDevicePkg/PlatformDxe/BoardIdDecode.h
new file mode 100644 (file)
index 0000000..8240cd8
--- /dev/null
+++ b/Vlv2TbltDevicePkg/PlatformDxe/BoardIdDecode.h
@@ -0,0 +1,66 @@
+/*++\r
+\r
+  Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+Module Name:\r
+\r
+  BoardIdDecode.h\r
+\r
+Abstract:\r
+\r
+  Header file for Platform Initialization Driver.\r
+\r
+Revision History\r
+\r
+++*/\r
+\r
+//\r
+// Board AA# and Board ID\r
+//\r
+#define DEFAULT_BOARD_AA                  "FFFFFF"\r
+\r
+//\r
+// Mount Washington (LVDS) LOEM\r
+//\r
+#define MW_ITX_MPCIE_LVDS_LOEM_AA         "E93081"\r
+#define MW_ITX_MPCIE_LVDS_LOEM_ID         3\r
+\r
+//\r
+// Mount Washington (LVDS) Channel\r
+//\r
+#define MW_ITX_MPCIE_LVDS_CHANNEL_AA      "E93080"\r
+#define MW_ITX_MPCIE_LVDS_CHANNEL_ID      3\r
+\r
+//\r
+// Mount Washington Channel\r
+//\r
+#define MW_ITX_MPCIE_CHANNEL_AA           "E93082"\r
+#define MW_ITX_MPCIE_CHANNEL_ID           1\r
+\r
+//\r
+// Kinston (mPCIe + LVDS) LOEM\r
+//\r
+#define KT_ITX_MPCIE_LVDS_LOEM_AA         "E93085"\r
+#define KT_ITX_MPCIE_LVDS_LOEM_ID         2\r
+\r
+//\r
+// Kinston (LVDS) Channel\r
+//\r
+#define KT_ITX_CHANNEL_AA                 "E93083"\r
+#define KT_ITX_CHANNEL_ID                 0\r
+\r
+//\r
+// Kinston LOEM\r
+//\r
+#define KT_ITX_LOEM_AA                    "E93084"\r
+#define KT_ITX_LOEM_ID                    0\r
+\r

diff --git a/Vlv2TbltDevicePkg/PlatformDxe/ClockControl.c b/Vlv2TbltDevicePkg/PlatformDxe/ClockControl.c
new file mode 100644 (file)
index 0000000..cc6ca3c
--- /dev/null
+++ b/Vlv2TbltDevicePkg/PlatformDxe/ClockControl.c
@@ -0,0 +1,207 @@
+/** @file\r
+\r
+  Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+Module Name:\r
+\r
+\r
+  ClockControl.c\r
+\r
+Abstract:\r
+\r
+  Sets platform/SKU specific clock routing information.\r
+\r
+\r
+\r
+--*/\r
+\r
+#include "PlatformDxe.h"\r
+#include <Protocol/CK505ClockPlatformInfo.h>\r
+\r
+//\r
+// Default clock routing informtion (All On)\r
+//\r
+EFI_CLOCK_PLATFORM_INFO mDefClockPolicy = {NULL, 0, NULL, 0, NULL, 0};\r
+\r
+//\r
+// Clock Settings\r
+//\r
+// Static clock table.\r
+//  This should be used to define any clock settings that are static\r
+//  (Always On or Always Off).  Dynamic clocks should be set to enabled\r
+//  in this table.\r
+//\r
+EFI_STATIC_SIGNALS mAtxStaticClocks[] = {\r
+  {SrcClk8,   Enabled,  All},\r
+  {SrcClk7,   Enabled,  All},\r
+  {SrcClk6,   Enabled,  All},\r
+  {SrcClk5,   Enabled,  All},\r
+  {SrcClk4,   Enabled,  All},\r
+  {SrcClk3,   Enabled,  All},\r
+  {SrcClk2,   Enabled,  All},\r
+  {SrcClk1,   Enabled,  All},\r
+  {SrcClk0,   Enabled,  All},\r
+  {Ref0,      Enabled,  All},\r
+  {Dot96,     Enabled,  All},\r
+  {Usb48,     Enabled,  All},\r
+  {PciClkF5,  Enabled,  All},\r
+  {PciClk0,   Enabled,  All},\r
+  {PciClk2,   Enabled,  All},\r
+  {PciClk3,   Enabled,  All},\r
+  {PciClk4,   Disabled,  All},\r
+  {Cr_B,   EnabledWithSwitch,  All},\r
+};\r
+\r
+//\r
+// ClockSxInfo Table\r
+//  This is a list of clocks that need to be set to a known state when the\r
+//  system enters S4 or S5.\r
+//\r
+EFI_STATIC_SIGNALS mAtxSxClocks[] = {\r
+  {SaveClockConfiguration, Disabled, All}\r
+};\r
+\r
+//\r
+// ATX settings structure\r
+//\r
+EFI_CLOCK_PLATFORM_INFO mAtxClockSettings = {\r
+  mAtxStaticClocks,\r
+  sizeof(mAtxStaticClocks) / sizeof(mAtxStaticClocks[0]),\r
+  mAtxSxClocks,\r
+  sizeof(mAtxSxClocks) / sizeof(mAtxSxClocks[0])\r
+};\r
+\r
+#if defined( RVP_SUPPORT ) && RVP_SUPPORT\r
+//\r
+// RVP Clock Settings\r
+//\r
+// Static clock table.\r
+//  This should be used to define any clock settings that are static\r
+//  (Always On or Always Off).  Dynamic clocks should be set to enabled\r
+//  in this table.\r
+//\r
+//UPSD_TBD Check with Jan if any porting required.\r
+//\r
+EFI_STATIC_SIGNALS mRvpStaticClocks[] = {\r
+  {SrcClk11,  Enabled,  All},     // Not used/not present but leave coding enabled\r
+  {SrcClk10,  Enabled,  All},     // Not used/not present but leave coding enabled\r
+  {SrcClk9,   Enabled,  All},     // Not used/not present but leave coding enabled\r
+  {SrcClk8,   Enabled,  All},     // ICHSATAII\r
+  {SrcClk7,   Enabled,  All},     // DPL_REFSSCLKIN\r
+  {SrcClk6,   Enabled,  All},     // 100M_MCH\r
+  {SrcClk5,   Enabled,  All},     // Mini-PCIe  //TODO PNV: Need to check ICH GPIO38:\r
+                                                // 0: turn on; 1: turn off\r
+  {SrcClk4,   Enabled,  All},     // ICHSATA\r
+  {SrcClk3,   Enabled,  All},     // 100M_ICH\r
+  {SrcClk2,   Enabled,  All},     // 100M_LAN\r
+  {SrcClk1,   Enabled,  All},     // 25M_LAN\r
+  {SrcClk0,   Enabled,  All},     // 96M_DREF\r
+  {Ref0,      Enabled,  All},\r
+  {Dot96,     Enabled,  All},\r
+  {Usb48,     Enabled,  All},\r
+  {PciClkF5,  Enabled,  All},     // 33M_ICH\r
+  {PciClk0,   Enabled,  All},     // 33M_RISER\r
+  {PciClk1,   Enabled,  All},     // 33M_RISER\r
+  {PciClk2,   Enabled,  All},     // VDD_Clock\r
+  {PciClk3,   Enabled,  All},     // 33M_S1\r
+  {PciClk4,   Enabled,  All},     // 33M_PA\r
+};\r
+\r
+//\r
+// Dynamic clock table\r
+// This is used to determine if a clock should be left on or turned off based\r
+// on the presence of a device.  The bridge information is used so the bus\r
+// number for the device to be detected can be found.\r
+//\r
+\r
+//\r
+// ClockSxInfo Table\r
+// This is a list of clocks that need to be set to a known state when the\r
+// system enters S4 or S5.\r
+//\r
+EFI_STATIC_SIGNALS mRvpSxClocks[] = {\r
+  {SaveClockConfiguration, Disabled, All}\r
+};\r
+\r
+//\r
+// RVP settings structure\r
+//\r
+EFI_CLOCK_PLATFORM_INFO mRvpClockSettings = {\r
+  mRvpStaticClocks,\r
+  sizeof(mRvpStaticClocks) / sizeof(mRvpStaticClocks[0]),\r
+  0,  // No clocks will be turned off mRvpDynamicClocks,\r
+  0, // No clocks will be turned off sizeof(mRvpDynamicClocks) / sizeof(mRvpDynamicClocks[0]),\r
+  mRvpSxClocks,\r
+  sizeof(mRvpSxClocks) / sizeof(mRvpSxClocks[0])\r
+};\r
+#endif\r
+\r
+VOID\r
+InitializeClockRouting(\r
+  )\r
+{\r
+  EFI_STATUS                      Status;\r
+  UINTN                           BoardIdVarSize;\r
+  EFI_BOARD_FEATURES              BoardIdVar;\r
+  EFI_CLOCK_PLATFORM_INFO         *ClockPolicy;\r
+  EFI_HANDLE                      Handle;\r
+\r
+  ClockPolicy = &mDefClockPolicy;\r
+\r
+  //\r
+  // Do modifications based on board type\r
+  //\r
+  BoardIdVarSize = sizeof (EFI_BOARD_FEATURES);\r
+  Status = gRT->GetVariable (\r
+                  BOARD_FEATURES_NAME,\r
+                  &gEfiBoardFeaturesGuid,\r
+                  NULL,\r
+                  &BoardIdVarSize,\r
+                  &BoardIdVar\r
+                  );\r
+  if (!EFI_ERROR (Status)) {\r
+\r
+#if defined( RVP_SUPPORT ) && RVP_SUPPORT\r
+    if (BoardIdVar & B_BOARD_FEATURES_RVP) {\r
+      ClockPolicy = &mRvpClockSettings;\r
+    }\r
+#else\r
+\r
+    //\r
+    // Isolate board type information\r
+    //\r
+    BoardIdVar = BoardIdVar & (B_BOARD_FEATURES_FORM_FACTOR_ATX |\r
+                               B_BOARD_FEATURES_FORM_FACTOR_BTX |\r
+                               B_BOARD_FEATURES_FORM_FACTOR_MICRO_ATX |\r
+                               B_BOARD_FEATURES_FORM_FACTOR_MICRO_BTX);\r
+\r
+    if (BoardIdVar == B_BOARD_FEATURES_FORM_FACTOR_ATX ||\r
+        BoardIdVar == B_BOARD_FEATURES_FORM_FACTOR_MICRO_ATX) {\r
+      ClockPolicy = &mAtxClockSettings;\r
+    }\r
+\r
+#endif\r
+\r
+  }\r
+\r
+  Handle = NULL;\r
+  Status = gBS->InstallProtocolInterface (\r
+                  &Handle,\r
+                  &gEfiCk505ClockPlatformInfoGuid,\r
+                  EFI_NATIVE_INTERFACE,\r
+                  ClockPolicy\r
+                  );\r
+  ASSERT_EFI_ERROR(Status);\r
+\r
+}\r
+\r
+\r

diff --git a/Vlv2TbltDevicePkg/PlatformDxe/Configuration.h b/Vlv2TbltDevicePkg/PlatformDxe/Configuration.h
new file mode 100644 (file)
index 0000000..08bdf07
--- /dev/null
+++ b/Vlv2TbltDevicePkg/PlatformDxe/Configuration.h
@@ -0,0 +1,697 @@
+/*++\r
+\r
+  Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+Module Name:\r
+\r
+    Configuration.h\r
+\r
+Abstract:\r
+\r
+    Driver configuration include file\r
+\r
+\r
+--*/\r
+\r
+#ifndef _CONFIGURATION_H\r
+#define _CONFIGURATION_H\r
+\r
+#define EFI_NON_DEVICE_CLASS               0x00\r
+#define EFI_DISK_DEVICE_CLASS              0x01\r
+#define EFI_VIDEO_DEVICE_CLASS             0x02\r
+#define EFI_NETWORK_DEVICE_CLASS           0x04\r
+#define EFI_INPUT_DEVICE_CLASS             0x08\r
+#define EFI_ON_BOARD_DEVICE_CLASS          0x10\r
+#define EFI_OTHER_DEVICE_CLASS             0x20\r
+\r
+//\r
+// Processor labels\r
+//\r
+#define PROCESSOR_HT_MODE           0x0100\r
+#define PROCESSOR_FSB_MULTIPLIER    0x0101\r
+#define PROCESSOR_MULTIPLIER_OVERRIDE_CONTROL  0x0211\r
+\r
+//\r
+// Memory labels\r
+//\r
+#define MEMORY_SLOT1_SPEED          0x0200\r
+#define MEMORY_SLOT2_SPEED          0x0201\r
+#define MEMORY_SLOT3_SPEED          0x0202\r
+#define MEMORY_SLOT4_SPEED          0x0203\r
+#define END_MEMORY_SLOT_SPEED       0x020F\r
+#define PERFORMANCE_MEMORY_PROFILE_CONTROL  0x0210\r
+#define UCLK_RATIO_CONTROL          0x0212\r
+\r
+//\r
+// Language label\r
+//\r
+#define FRONT_PAGE_ITEM_LANGUAGE    0x300\r
+\r
+//\r
+// Boot Labels\r
+//\r
+#define BOOT_DEVICE_PRIORITY_BEGIN  0x0400\r
+#define BOOT_DEVICE_PRIORITY_END    0x0401\r
+#define BOOT_OPTICAL_DEVICE_BEGIN   0x0410\r
+#define BOOT_OPTICAL_DEVICE_END     0x0411\r
+#define BOOT_REMOVABLE_DEVICE_BEGIN 0x0420\r
+#define BOOT_REMOVABLE_DEVICE_END   0x0421\r
+#define BOOT_PXE_DEVICE_BEGIN       0x0430\r
+#define BOOT_PXE_DEVICE_END         0x0431\r
+#define BOOT_MENU_TYPE_BEGIN        0x0440\r
+#define BOOT_MENU_TYPE_END          0x0441\r
+#define BOOT_USB_DEVICE_BEGIN       0x0450\r
+#define BOOT_USB_DEVICE_END         0x0451\r
+#define BOOT_USB_FIRST_BEGIN        0x0460\r
+#define BOOT_USB_FIRST_END          0x0461\r
+#define BOOT_UEFI_BEGIN             0x0470\r
+#define BOOT_UEFI_END               0x0471\r
+#define BOOT_USB_UNAVAILABLE_BEGIN  0x0480\r
+#define BOOT_USB_UNAVAILABLE_END    0x0481\r
+#define BOOT_CD_UNAVAILABLE_BEGIN   0x0490\r
+#define BOOT_CD_UNAVAILABLE_END     0x0491\r
+#define BOOT_FDD_UNAVAILABLE_BEGIN  0x04A0\r
+#define BOOT_FDD_UNAVAILABLE_END    0x04A1\r
+#define BOOT_DEVICE_PRIORITY_DEFAULT_BEGIN  0x04B0\r
+#define BOOT_DEVICE_PRIORITY_DEFAULT_END    0x04B1\r
+#define BOOT_USB_OPT_LABEL_BEGIN    0x04C0\r
+#define BOOT_USB_OPT_LABEL_END      0x04C1\r
+\r
+#define VAR_EQ_ADMIN_NAME               0x0041  // A\r
+#define VAR_EQ_ADMIN_DECIMAL_NAME       L"65"\r
+#define VAR_EQ_VIEW_ONLY_NAME           0x0042  // B\r
+#define VAR_EQ_VIEW_ONLY_DECIMAL_NAME   L"66"\r
+#define VAR_EQ_CONFIG_MODE_NAME         0x0043  // C\r
+#define VAR_EQ_CONFIG_MODE_DECIMAL_NAME L"67"\r
+#define VAR_EQ_CPU_EE_NAME              0x0045  // E\r
+#define VAR_EQ_CPU_EE_DECIMAL_NAME  L"69"\r
+#define VAR_EQ_FLOPPY_MODE_NAME         0x0046  // F\r
+#define VAR_EQ_FLOPPY_MODE_DECIMAL_NAME L"70"\r
+#define VAR_EQ_HT_MODE_NAME             0x0048  // H\r
+#define VAR_EQ_HT_MODE_DECIMAL_NAME     L"72"\r
+#define VAR_EQ_AHCI_MODE_NAME           0x0049  // I\r
+#define VAR_EQ_AHCI_MODE_DECIMAL_NAME   L"73"\r
+#define VAR_EQ_CPU_LOCK_NAME            0x004C  // L\r
+#define VAR_EQ_CPU_LOCK_DECIMAL_NAME    L"76"\r
+#define VAR_EQ_NX_MODE_NAME             0x004E  // N\r
+#define VAR_EQ_NX_MODE_DECIMAL_NAME     L"78"\r
+#define VAR_EQ_RAID_MODE_NAME           0x0052  // R\r
+#define VAR_EQ_RAID_MODE_DECIMAL_NAME   L"82"\r
+#define VAR_EQ_1394_MODE_NAME           0x0054  // T\r
+#define VAR_EQ_1394_MODE_DECIMAL_NAME   L"84"\r
+#define VAR_EQ_USER_NAME                0x0055  // U\r
+#define VAR_EQ_USER_DECIMAL_NAME        L"85"\r
+#define VAR_EQ_VIDEO_MODE_NAME          0x0056  // V\r
+#define VAR_EQ_VIDEO_MODE_DECIMAL_NAME  L"86"\r
+#define VAR_EQ_LEGACY_FP_AUDIO_NAME     0x0057  // W\r
+#define VAR_EQ_LEGACY_FP_AUDIO_DECIMAL_NAME L"87"\r
+#define VAR_EQ_EM64T_CAPABLE_NAME       0x0058  // X\r
+#define VAR_EQ_EM64T_CAPABLE_DECIMAL_NAME L"88"\r
+#define VAR_EQ_BOARD_FORMFACTOR_NAME    0x0059  // Y\r
+#define VAR_EQ_BOARD_FORMFACTOR_DECIMAL_NAME L"89"\r
+#define VAR_EQ_UNCON_CPU_NAME           0x005B  // ??\r
+#define VAR_EQ_UNCON_CPU_DECIMAL_NAME   L"91"\r
+#define VAR_EQ_VAR_HIDE_NAME            0x005C  // ??\r
+#define VAR_EQ_VAR_HIDE_DECIMAL_NAME    L"92"\r
+#define VAR_EQ_ENERGY_LAKE_NAME         0x005D  // ??\r
+#define VAR_EQ_ENERGY_LAKE_DECIMAL_NAME L"93"\r
+#define VAR_EQ_TPM_MODE_NAME            0x005E  // ^\r
+#define VAR_EQ_TPM_MODE_DECIMAL_NAME    L"94"\r
+#define VAR_EQ_DISCRETE_SATA_NAME       0x005F  // ??\r
+#define VAR_EQ_DISCRETE_SATA_DECIMAL_NAME L"95"\r
+#define VAR_EQ_ROEM_SKU_NAME            0x0060  // ??\r
+#define VAR_EQ_ROEM_SKU_DECIMAL_NAME    L"96"\r
+#define VAR_EQ_AMTSOL_MODE_NAME         0x0061  // ??\r
+#define VAR_EQ_AMTSOL_MODE_DECIMAL_NAME L"97"\r
+#define VAR_EQ_NO_PEG_MODE_NAME         0x0062  // ??\r
+#define VAR_EQ_NO_PEG_MODE_DECIMAL_NAME L"98"\r
+#define VAR_EQ_SINGLE_PROCESSOR_MODE_NAME 0x0063  // ??\r
+#define VAR_EQ_SINGLE_PROCESSOR_MODE_DECIMAL_NAME L"99"\r
+#define VAR_EQ_FLOPPY_HIDE_NAME         0x0064  // ??\r
+#define VAR_EQ_FLOPPY_HIDE_DECIMAL_NAME L"100"\r
+#define VAR_EQ_SERIAL_HIDE_NAME         0x0065  // ??\r
+#define VAR_EQ_SERIAL_HIDE_DECIMAL_NAME L"101"\r
+#define VAR_EQ_GV3_CAPABLE_NAME         0x0066 // f\r
+#define VAR_EQ_GV3_CAPABLE_DECIMAL_NAME L"102"\r
+#define VAR_EQ_2_MEMORY_NAME            0x0067 // ??\r
+#define VAR_EQ_2_MEMORY_DECIMAL_NAME    L"103"\r
+#define VAR_EQ_2_SATA_NAME              0x0068 // ??\r
+#define VAR_EQ_2_SATA_DECIMAL_NAME      L"104"\r
+#define VAR_EQ_NEC_SKU_NAME            0x0069  // ??\r
+#define VAR_EQ_NEC_SKU_DECIMAL_NAME    L"105"\r
+#define VAR_EQ_AMT_MODE_NAME            0x006A  // ??\r
+#define VAR_EQ_AMT_MODE_DECIMAL_NAME    L"106"\r
+#define VAR_EQ_LCLX_SKU_NAME            0x006B  // ??\r
+#define VAR_EQ_LCLX_SKU_DECIMAL_NAME    L"107"\r
+#define VAR_EQ_VT_NAME                  0x006C\r
+#define VAR_EQ_VT_DECIMAL_NAME          L"108"\r
+#define VAR_EQ_LT_NAME                  0x006D\r
+#define VAR_EQ_LT_DECIMAL_NAME          L"109"\r
+#define VAR_EQ_ITK_BIOS_MOD_NAME         0x006E  // ??\r
+#define VAR_EQ_ITK_BIOS_MOD_DECIMAL_NAME L"110"\r
+#define VAR_EQ_HPET_NAME                0x006F\r
+#define VAR_EQ_HPET_DECIMAL_NAME        L"111"\r
+#define VAR_EQ_ADMIN_INSTALLED_NAME          0x0070  // ??\r
+#define VAR_EQ_ADMIN_INSTALLED_DECIMAL_NAME  L"112"\r
+#define VAR_EQ_USER_INSTALLED_NAME          0x0071  // ??\r
+#define VAR_EQ_USER_INSTALLED_DECIMAL_NAME  L"113"\r
+#define VAR_EQ_CPU_CMP_NAME             0x0072\r
+#define VAR_EQ_CPU_CMP_DECIMAL_NAME     L"114"\r
+#define VAR_EQ_LAN_MAC_ADDR_NAME          0x0073  // ??\r
+#define VAR_EQ_LAN_MAC_ADDR_DECIMAL_NAME  L"115"\r
+#define VAR_EQ_PARALLEL_HIDE_NAME         0x0074  // ??\r
+#define VAR_EQ_PARALLEL_HIDE_DECIMAL_NAME L"116"\r
+#define VAR_EQ_AFSC_SETUP_NAME          0x0075\r
+#define VAR_EQ_AFSC_SETUP_DECIMAL_NAME  L"117"\r
+#define VAR_EQ_MINICARD_MODE_NAME       0x0076  //\r
+#define VAR_EQ_MINICARD_MODE_DECIMAL_NAME   L"118"\r
+#define VAR_EQ_VIDEO_IGD_NAME          0x0077  //\r
+#define VAR_EQ_VIDEO_IGD_DECIMAL_NAME  L"119"\r
+#define VAR_EQ_ALWAYS_ENABLE_LAN_NAME            0x0078  //\r
+#define VAR_EQ_ALWAYS_ENABLE_LAN_DECIMAL_NAME    L"120"\r
+#define VAR_EQ_LEGACY_FREE_NAME          0x0079  //\r
+#define VAR_EQ_LEGACY_FREE_DECIMAL_NAME   L"121"\r
+#define VAR_EQ_CLEAR_CHASSIS_INSTRUSION_STATUS_NAME           0x007A\r
+#define VAR_EQ_CLEAR_CHASSIS_INSTRUSION_STATUS_DECIMAL_NAME  L"122"\r
+#define VAR_EQ_CPU_FSB_NAME            0x007B  //\r
+#define VAR_EQ_CPU_FSB_DECIMAL_NAME    L"123"\r
+#define VAR_EQ_SATA0_DEVICE_NAME            0x007C  //\r
+#define VAR_EQ_SATA0_DVICE_DECIMAL_NAME    L"124"\r
+#define VAR_EQ_SATA1_DEVICE_NAME            0x007D  //\r
+#define VAR_EQ_SATA1_DVICE_DECIMAL_NAME    L"125"\r
+#define VAR_EQ_SATA2_DEVICE_NAME            0x007E  //\r
+#define VAR_EQ_SATA2_DVICE_DECIMAL_NAME    L"126"\r
+#define VAR_EQ_SATA3_DEVICE_NAME            0x007F  //\r
+#define VAR_EQ_SATA3_DVICE_DECIMAL_NAME    L"127"\r
+#define VAR_EQ_SATA4_DEVICE_NAME            0x0080  //\r
+#define VAR_EQ_SATA4_DVICE_DECIMAL_NAME    L"128"\r
+#define VAR_EQ_SATA5_DEVICE_NAME            0x0081  //\r
+#define VAR_EQ_SATA5_DVICE_DECIMAL_NAME    L"129"\r
+#define VAR_EQ_TPM_STATUS_NAME              0x0082      // To indicate if TPM is enabled\r
+#define VAR_EQ_TPM_STATUS_DECIMAL_NAME     L"130"\r
+#define VAR_EQ_HECETA6E_PECI_CPU_NAME   0x0083\r
+#define VAR_EQ_HECETA6E_PECI_CPU_DECIMAL_NAME L"131"\r
+#define VAR_EQ_USB_2_NAME                   0x0084  //\r
+#define VAR_EQ_USB_2_DECIMAL_NAME          L"132"\r
+#define VAR_EQ_RVP_NAME                   0x0085  //\r
+#define VAR_EQ_RVP_DECIMAL_NAME          L"133"\r
+#define VAR_EQ_ECIR_NAME                    0x0086\r
+#define VAR_EQ_ECIR_DECIMAL_NAME           L"134"\r
+#define VAR_EQ_WAKONS5KB_NAME               0x0087\r
+#define VAR_EQ_WAKONS5KB_DECIMAL_NAME      L"135"\r
+#define VAR_EQ_HDAUDIOLINKBP_NAME           0x0088\r
+#define VAR_EQ_HDAUDIOLINKBP_DECIMAL_NAME  L"136"\r
+#define VAR_EQ_FINGERPRINT_NAME             0x0089\r
+#define VAR_EQ_FINGERPRINT_DECIMAL_NAME    L"137"\r
+#define VAR_EQ_BLUETOOTH_NAME               0x008A\r
+#define VAR_EQ_BLUETOOTH_DECIMAL_NAME      L"138"\r
+#define VAR_EQ_WLAN_NAME                    0x008B\r
+#define VAR_EQ_WLAN_DECIMAL_NAME           L"139"\r
+#define VAR_EQ_1_PATA_NAME                  0x008C\r
+#define VAR_EQ_1_PATA_DECIMAL_NAME         L"140"\r
+#define VAR_EQ_ACTIVE_PROCESSOR_CORE_NAME          0x008D\r
+#define VAR_EQ_ACTIVE_PROCESSOR_CORE_DECIMAL_NAME  L"141"\r
+#define VAR_EQ_TURBO_MODE_CAP_NAME          0x008E\r
+#define VAR_EQ_TURBO_MODE_CAP_DECIMAL_NAME  L"142"\r
+#define VAR_EQ_XE_MODE_CAP_NAME             0x008F\r
+#define VAR_EQ_XE_MODE_CAP_DECIMAL_NAME     L"143"\r
+#define VAR_EQ_NPI_QPI_VOLTAGE_NAME         0x0090\r
+#define VAR_EQ_NPI_QPI_VOLTAGE_DECIMAL_NAME L"144"\r
+#define VAR_EQ_PRE_PROD_NON_XE_NAME         0x0091\r
+#define VAR_EQ_PRE_PROD_NON_XE_DECIMAL_NAME L"145"\r
+#define VAR_EQ_2_C0_MEMORY_NAME            0x0092 // ??\r
+#define VAR_EQ_2_C0_MEMORY_DECIMAL_NAME    L"146"\r
+#define VAR_EQ_LVDS_NAME                    0x0093\r
+#define VAR_EQ_LVDS_DECIMAL_NAME            L"147"\r
+#define VAR_EQ_USB_OPTION_SHOW_NAME                    0x0094\r
+#define VAR_EQ_USB_OPTION_SHOW_DECIMAL_NAME            L"148"\r
+#define VAR_EQ_HDD_MASTER_INSTALLED_NAME      0x0095\r
+#define VAR_EQ_HDD_MASTER_INSTALLED_DECIMAL_NAME      L"149"\r
+#define VAR_EQ_HDD_USER_INSTALLED_NAME        0x0096\r
+#define VAR_EQ_HDD_USER_INSTALLED_DECIMAL_NAME       L"150"\r
+#define VAR_EQ_PS2_HIDE_NAME         0x0097  // ??\r
+#define VAR_EQ_PS2_HIDE_DECIMAL_NAME L"151"\r
+#define VAR_EQ_VIDEO_SLOT_NAME       0x0098\r
+#define VAR_EQ_VIDEO_SLOT_DECIMAL_NAME       L"152"\r
+#define VAR_EQ_HDMI_SLOT_NAME       0x0099\r
+#define VAR_EQ_HDMI_SLOT_DECIMAL_NAME       L"153"\r
+#define VAR_EQ_SERIAL2_HIDE_NAME         0x009a\r
+#define VAR_EQ_SERIAL2_HIDE_DECIMAL_NAME L"154"\r
+\r
+\r
+#define VAR_EQ_LVDS_WARNING_HIDE_NAME    0x009e\r
+#define VAR_EQ_LVDS_WARNING_HIDE_DECIMAL_NAME L"158"\r
+\r
+\r
+#define VAR_EQ_MSATA_HIDE_NAME    0x009f\r
+#define VAR_EQ_MSATA_HIDE_DECIMAL_NAME L"159"\r
+\r
+\r
+#define VAR_EQ_PCI_SLOT1_NAME    0x00a0\r
+#define VAR_EQ_PCI_SLOT1_DECIMAL_NAME L"160"\r
+#define VAR_EQ_PCI_SLOT2_NAME    0x00a1\r
+#define VAR_EQ_PCI_SLOT2_DECIMAL_NAME L"161"\r
+\r
+//\r
+// Generic Form Ids\r
+//\r
+#define ROOT_FORM_ID                    1\r
+\r
+//\r
+// Advance Page. Do not have to be sequential but have to be unique\r
+//\r
+#define CONFIGURATION_ROOT_FORM_ID          2\r
+#define BOOT_CONFIGURATION_ID               3\r
+#define ONBOARDDEVICE_CONFIGURATION_ID      4\r
+#define DRIVE_CONFIGURATION_ID              5\r
+#define FLOPPY_CONFIGURATION_ID             6\r
+#define EVENT_LOG_CONFIGURATION_ID          7\r
+#define VIDEO_CONFIGURATION_ID              8\r
+#define USB_CONFIGURATION_ID                9\r
+#define HARDWARE_MONITOR_CONFIGURATION_ID   10\r
+#define VIEW_EVENT_LOG_CONFIGURATION_ID     11\r
+#define MEMORY_OVERRIDE_ID                  12\r
+#define CHIPSET_CONFIGURATION_ID            13\r
+#define BURN_IN_MODE_ID                     14\r
+#define PCI_EXPRESS_ID                      15\r
+#define MANAGEMENT_CONFIGURATION_ID         16\r
+#define CPU_CONFIGURATION_ID                17\r
+#define PCI_CONFIGURATION_ID                18\r
+#define SECURITY_CONFIGURATION_ID           19\r
+#define ZIP_CONFIGURATION_ID                20\r
+#define AFSC_FAN_CONTROL_ID                 21\r
+#define VFR_FORMID_CSI                      22\r
+#define VFR_FORMID_MEMORY                   23\r
+#define VFR_FORMID_IOH                      24\r
+#define VFR_FORMID_CPU_CSI                  25\r
+#define VFR_FORMID_IOH_CONFIG               26\r
+#define VFR_FORMID_VTD                      27\r
+#define VFR_FORMID_PCIE_P0                  28\r
+#define VFR_FORMID_PCIE_P1                  29\r
+#define VFR_FORMID_PCIE_P2                  30\r
+#define VFR_FORMID_PCIE_P3                  31\r
+#define VFR_FORMID_PCIE_P4                  32\r
+#define VFR_FORMID_PCIE_P5                  33\r
+#define VFR_FORMID_PCIE_P6                  34\r
+#define VFR_FORMID_PCIE_P7                  35\r
+#define VFR_FORMID_PCIE_P8                  36\r
+#define VFR_FORMID_PCIE_P9                  37\r
+#define VFR_FORMID_PCIE_P10                 38\r
+#define VFR_FID_SKT0                        39\r
+#define VFR_FID_IOH0                        40\r
+#define VFR_FID_IOH_DEV_HIDE                41\r
+#define PROCESSOR_OVERRIDES_FORM_ID         42\r
+#define BUS_OVERRIDES_FORM_ID               43\r
+#define REF_OVERRIDES_FORM_ID               44\r
+#define MEMORY_INFORMATION_ID               45\r
+#define LVDS_WARNING_ID                     46\r
+#define LVDS_CONFIGURATION_ID               47\r
+#define PCI_SLOT_CONFIGURATION_ID           48\r
+#define HECETA_CONFIGURATION_ID             49\r
+#define LVDS_EXPERT_CONFIGURATION_ID        50\r
+#define PCI_SLOT_7_ID                       51\r
+#define PCI_SLOT_6_ID                       52\r
+#define PCI_SLOT_5_ID                       53\r
+#define PCI_SLOT_4_ID                       54\r
+#define PCI_SLOT_3_ID                       55\r
+#define PCI_SLOT_2_ID                       56\r
+#define PCI_SLOT_1_ID                       57\r
+#define BOOT_DISPLAY_ID                     58\r
+#define CPU_PWR_CONFIGURATION_ID            59\r
+\r
+#define FSC_CONFIGURATION_ID                60\r
+#define FSC_CPU_TEMPERATURE_FORM_ID         61\r
+#define FSC_VTT_VOLTAGE_FORM_ID             62\r
+#define FSC_FEATURES_CONTROL_ID             63\r
+#define FSC_FAN_CONFIGURATION_ID            64\r
+#define FSC_PROCESSOR_FAN_CONFIGURATION_ID  65\r
+#define FSC_FRONT_FAN_CONFIGURATION_ID      66\r
+#define FSC_REAR_FAN_CONFIGURATION_ID       67\r
+#define FSC_AUX_FAN_CONFIGURATION_ID        68\r
+#define FSC_12_VOLTAGE_FORM_ID              69\r
+#define FSC_5_VOLTAGE_FORM_ID               70\r
+#define FSC_3P3_VOLTAGE_FORM_ID             71\r
+#define FSC_2P5_VOLTAGE_FORM_ID             72\r
+#define FSC_VCC_VOLTAGE_FORM_ID             73\r
+#define FSC_PCH_TEMPERATURE_FORM_ID         74\r
+#define FSC_MEM_TEMPERATURE_FORM_ID         75\r
+#define FSC_VR_TEMPERATURE_FORM_ID          76\r
+#define FSC_3P3STANDBY_VOLTAGE_FORM_ID      77\r
+#define FSC_5BACKUP_VOLTAGE_FORM_ID         78\r
+#define ROOT_MAIN_FORM_ID                   79\r
+#define ROOT_BOOT_FORM_ID                   80\r
+#define ROOT_MAINTENANCE_ID                 81\r
+#define ROOT_POWER_FORM_ID                  82\r
+#define ROOT_SECURITY_FORM_ID               83\r
+#define ROOT_PERFORMANCE_FORM_ID            84\r
+#define ROOT_SYSTEM_SETUP_FORM_ID           85\r
+\r
+#define ADDITIONAL_SYSTEM_INFO_FORM_ID      86\r
+\r
+#define THERMAL_CONFIG_FORM_ID              87\r
+\r
+#define PCI_SLOT_CONFIG_LABEL_ID_1            0x300A\r
+#define PCI_SLOT_CONFIG_LABEL_ID_2            0x300B\r
+#define PCI_SLOT_CONFIG_LABEL_ID_3            0x300C\r
+#define PCI_SLOT_CONFIG_LABEL_ID_4            0x300D\r
+#define PCI_SLOT_CONFIG_LABEL_ID_5            0x300E\r
+#define PCI_SLOT_CONFIG_LABEL_ID_6            0x300F\r
+#define PCI_SLOT_CONFIG_LABEL_ID_7            0x3010\r
+#define PCI_SLOT_CONFIG_LABEL_ID_8            0x3011\r
+\r
+//\r
+// Advance Hardware Monitor Callback Keys. Do not have to be sequential but have to be unique\r
+//\r
+#define CONFIGURATION_HARDWARE_CALLBACK_KEY            0x2000\r
+#define ADVANCE_VIDEO_CALLBACK_KEY                     0x2001\r
+#define CONFIGURATION_FSC_CALLBACK_KEY                 0x2002\r
+#define CONFIGURATION_RESTORE_FAN_CONTROL_CALLBACK_KEY 0x2003\r
+#define CONFIGURATION_LVDS_CALLBACK_KEY                0x2004\r
+#define CONFIGURATION_PREDEFINED_EDID_CALLBACK_KEY     0x2005\r
+#define ADVANCE_LVDS_CALLBACK_KEY           0x2010\r
+\r
+//\r
+// Main Callback Keys. Do not have to be sequential but have to be unique\r
+//\r
+#define MAIN_LANGUAGE_CALLBACK_KEY          0x3000\r
+\r
+//\r
+// Power Hardware Monitor Callback Keys. Do not have to be sequential but have to be unique\r
+//\r
+#define POWER_HARDWARE_CALLBACK_KEY         0x4000\r
+\r
+//\r
+// Performance Callback Keys. Do not have to be sequential but have to be unique\r
+//\r
+#define PROCESSOR_OVERRIDES_CALLBACK_KEY 0x5000\r
+#define PERFORMANCE_CALLBACK_KEY         0x5001\r
+#define BUS_OVERRIDES_CALLBACK_KEY       0x5002\r
+#define MEMORY_CFG_CALLBACK_KEY          0x5003\r
+#define PERFORMANCE_STATUS_CALLBACK_KEY  0x5004\r
+#define MEMORY_RATIO_CALLBACK_KEY        0x5005\r
+#define MEMORY_MODE_CALLBACK_KEY         0x5006\r
+\r
+//\r
+// Security Callback Keys. Do not have to be sequential but have to be unique\r
+//\r
+#define SECURITY_SUPERVISOR_CALLBACK_KEY    0x1000\r
+#define SECURITY_USER_CALLBACK_KEY          0x1001\r
+#define SECURITY_CLEAR_ALL_CALLBACK_KEY     0x1002\r
+#define SECURITY_CLEAR_USER_CALLBACK_KEY    0x1004\r
+#define SECURITY_RESET_AMT_CALLBACK_KEY     0x1008\r
+#define SECURITY_CHANGE_VT_CALLBACK_KEY     0x1010\r
+#define SECURITY_MASTER_HDD_CALLBACK_KEY    0x1020\r
+#define SECURITY_USER_HDD_CALLBACK_KEY      0x1040\r
+\r
+//\r
+// Boot Callback Keys. Do not have to be sequential but have to be unique\r
+//\r
+#define BOOT_HYPERBOOT_CALLBACK_KEY                 0x6003\r
+#define BOOT_HYPERBOOT_CALLBACK_KEY_DISABLE         0x6004\r
+#define BOOT_HYPERBOOT_CALLBACK_KEY_USB             0x6005\r
+#define BOOT_HYPERBOOT_CALLBACK_KEY_DISABLE_USB_OPT 0x6006\r
+\r
+//\r
+// IDCC/Setup FSB Frequency Override Range\r
+//\r
+#define EFI_IDCC_FSB_MIN   133\r
+#define EFI_IDCC_FSB_MAX   240\r
+#define EFI_IDCC_FSB_STEP  1\r
+\r
+//\r
+// Reference voltage\r
+//\r
+#define EFI_REF_DAC_MIN     0\r
+#define EFI_REF_DAC_MAX     255\r
+#define EFI_GTLREF_DEF      170\r
+#define EFI_DDRREF_DEF      128\r
+#define EFI_DIMMREF_DEF     128\r
+\r
+//\r
+// Setup FSB Frequency Override Range\r
+//\r
+#define EFI_FSB_MIN       133\r
+#define EFI_FSB_MAX       240\r
+#define EFI_FSB_STEP      1\r
+#define EFI_FSB_AUTOMATIC 0\r
+#define EFI_FSB_MANUAL    1\r
+#define FSB_FREQ_ENTRY_COUNT ((EFI_FSB_MAX - EFI_FSB_MIN)/EFI_FSB_STEP) + 1\r
+#define FSB_FREQ_ENTRY_TYPE  UINT16_TYPE\r
+\r
+//\r
+// Setup processor multiplier range\r
+//\r
+#define EFI_PROC_MULT_MIN   5\r
+#define EFI_PROC_MULT_MAX   40\r
+#define EFI_PROC_MULT_STEP  1\r
+#define EFI_PROC_AUTOMATIC  0\r
+#define EFI_PROC_MANUAL     1\r
+#define PROC_MULT_ENTRY_COUNT ((EFI_PROC_MULT_MAX - EFI_PROC_MULT_MIN)/EFI_PROC_MULT_STEP) + 1\r
+#define PROC_MULT_ENTRY_TYPE  UINT8_TYPE\r
+\r
+//\r
+// PCI Express Definitions\r
+//\r
+#define EFI_PCIE_FREQ_DEF       0x0\r
+\r
+#define PCIE_FREQ_ENTRY_TYPE  UINT8_TYPE\r
+#define PCIE_FREQ_ENTRY_7       0x7\r
+#define PCIE_FREQ_ENTRY_6       0x6\r
+#define PCIE_FREQ_ENTRY_5       0x5\r
+#define PCIE_FREQ_ENTRY_4       0x4\r
+#define PCIE_FREQ_ENTRY_3       0x3\r
+#define PCIE_FREQ_ENTRY_2       0x2\r
+#define PCIE_FREQ_ENTRY_1       0x1\r
+#define PCIE_FREQ_ENTRY_0       0x0\r
+\r
+#define PCIE_FREQ_TRANSLATION_TABLE_ENTRIES 8\r
+#define PCIE_FREQ_TRANSLATION_TABLE     { PCIE_FREQ_ENTRY_0, \\r
+                                          PCIE_FREQ_ENTRY_1, \\r
+                                          PCIE_FREQ_ENTRY_2, \\r
+                                          PCIE_FREQ_ENTRY_3, \\r
+                                          PCIE_FREQ_ENTRY_4, \\r
+                                          PCIE_FREQ_ENTRY_5, \\r
+                                          PCIE_FREQ_ENTRY_6, \\r
+                                          PCIE_FREQ_ENTRY_7 }\r
+\r
+\r
+#define PCIE_FREQ_PRECISION     2\r
+#define PCIE_FREQ_VALUE_7       10924\r
+#define PCIE_FREQ_VALUE_6       10792\r
+#define PCIE_FREQ_VALUE_5       10660\r
+#define PCIE_FREQ_VALUE_4       10528\r
+#define PCIE_FREQ_VALUE_3       10396\r
+#define PCIE_FREQ_VALUE_2       10264\r
+#define PCIE_FREQ_VALUE_1       10132\r
+#define PCIE_FREQ_VALUE_0       10000\r
+\r
+#define PCIE_FREQ_VALUES      { PCIE_FREQ_VALUE_0, \\r
+                                PCIE_FREQ_VALUE_1, \\r
+                                PCIE_FREQ_VALUE_2, \\r
+                                PCIE_FREQ_VALUE_3, \\r
+                                PCIE_FREQ_VALUE_4, \\r
+                                PCIE_FREQ_VALUE_5, \\r
+                                PCIE_FREQ_VALUE_6, \\r
+                                PCIE_FREQ_VALUE_7 }\r
+\r
+//\r
+// Memory Frequency Definitions\r
+//\r
+#define MEMORY_REF_FREQ_ENTRY_DEF     0x08\r
+\r
+#define MEMORY_REF_FREQ_ENTRY_TYPE    UINT8_TYPE\r
+#define MEMORY_REF_FREQ_ENTRY_3       0x04\r
+#define MEMORY_REF_FREQ_ENTRY_2       0x00\r
+#define MEMORY_REF_FREQ_ENTRY_1       0x02\r
+#define MEMORY_REF_FREQ_ENTRY_0       0x01\r
+\r
+#define MEMORY_REF_FREQ_TRANSLATION_TABLE_ENTRIES 4\r
+#define MEMORY_REF_FREQ_TRANSLATION_TABLE     { MEMORY_REF_FREQ_ENTRY_0, \\r
+                                                MEMORY_REF_FREQ_ENTRY_1, \\r
+                                                MEMORY_REF_FREQ_ENTRY_2, \\r
+                                                MEMORY_REF_FREQ_ENTRY_3 }\r
+\r
+#define MEMORY_REF_FREQ_PRECISION     0\r
+#define MEMORY_REF_FREQ_VALUE_3       333\r
+#define MEMORY_REF_FREQ_VALUE_2       267\r
+#define MEMORY_REF_FREQ_VALUE_1       200\r
+#define MEMORY_REF_FREQ_VALUE_0       133\r
+\r
+#define MEMORY_REF_FREQ_VALUES      { MEMORY_REF_FREQ_VALUE_0, \\r
+                                      MEMORY_REF_FREQ_VALUE_1, \\r
+                                      MEMORY_REF_FREQ_VALUE_2, \\r
+                                      MEMORY_REF_FREQ_VALUE_3 }\r
+\r
+\r
+//\r
+// Memory Reference Frequency Definitions\r
+//\r
+\r
+#define MEMORY_FREQ_ENTRY_TYPE    UINT8_TYPE\r
+#define MEMORY_FREQ_ENTRY_3       0x4\r
+#define MEMORY_FREQ_ENTRY_2       0x3\r
+#define MEMORY_FREQ_ENTRY_1       0x2\r
+#define MEMORY_FREQ_ENTRY_0       0x1\r
+\r
+#define MEMORY_FREQ_TRANSLATION_TABLE_ENTRIES 4\r
+#define MEMORY_FREQ_TRANSLATION_TABLE     { MEMORY_FREQ_ENTRY_0, \\r
+                                            MEMORY_FREQ_ENTRY_1, \\r
+                                            MEMORY_FREQ_ENTRY_2, \\r
+                                            MEMORY_FREQ_ENTRY_3 }\r
+\r
+\r
+#define MEMORY_FREQ_MULT_PRECISION             2\r
+#define MEMORY_FREQ_MULT_333MHZ_VALUE_3        240\r
+#define MEMORY_FREQ_MULT_333MHZ_VALUE_2        200\r
+#define MEMORY_FREQ_MULT_333MHZ_VALUE_1        160\r
+#define MEMORY_FREQ_MULT_333MHZ_VALUE_0        120\r
+\r
+#define MEMORY_FREQ_MULT_266MHZ_VALUE_3        300\r
+#define MEMORY_FREQ_MULT_266MHZ_VALUE_2        250\r
+#define MEMORY_FREQ_MULT_266MHZ_VALUE_1        200\r
+#define MEMORY_FREQ_MULT_266MHZ_VALUE_0        150\r
+\r
+#define MEMORY_FREQ_MULT_200MHZ_VALUE_3        400\r
+#define MEMORY_FREQ_MULT_200MHZ_VALUE_2        333\r
+#define MEMORY_FREQ_MULT_200MHZ_VALUE_1        267\r
+#define MEMORY_FREQ_MULT_200MHZ_VALUE_0        200\r
+\r
+#define MEMORY_FREQ_MULT_133MHZ_VALUE_3        600\r
+#define MEMORY_FREQ_MULT_133MHZ_VALUE_2        500\r
+#define MEMORY_FREQ_MULT_133MHZ_VALUE_1        400\r
+#define MEMORY_FREQ_MULT_133MHZ_VALUE_0        300\r
+\r
+#define MEMORY_FREQ_MULT_333MHZ_VALUES      { MEMORY_FREQ_MULT_333MHZ_VALUE_0, \\r
+                                              MEMORY_FREQ_MULT_333MHZ_VALUE_1, \\r
+                                              MEMORY_FREQ_MULT_333MHZ_VALUE_2, \\r
+                                              MEMORY_FREQ_MULT_333MHZ_VALUE_3 }\r
+\r
+#define MEMORY_FREQ_MULT_266MHZ_VALUES      { MEMORY_FREQ_MULT_266MHZ_VALUE_0, \\r
+                                              MEMORY_FREQ_MULT_266MHZ_VALUE_1, \\r
+                                              MEMORY_FREQ_MULT_266MHZ_VALUE_2, \\r
+                                              MEMORY_FREQ_MULT_266MHZ_VALUE_3 }\r
+\r
+#define MEMORY_FREQ_MULT_200MHZ_VALUES      { MEMORY_FREQ_MULT_200MHZ_VALUE_0, \\r
+                                              MEMORY_FREQ_MULT_200MHZ_VALUE_1, \\r
+                                              MEMORY_FREQ_MULT_200MHZ_VALUE_2, \\r
+                                              MEMORY_FREQ_MULT_200MHZ_VALUE_3 }\r
+\r
+#define MEMORY_FREQ_MULT_133MHZ_VALUES      { MEMORY_FREQ_MULT_133MHZ_VALUE_0, \\r
+                                              MEMORY_FREQ_MULT_133MHZ_VALUE_1, \\r
+                                              MEMORY_FREQ_MULT_133MHZ_VALUE_2, \\r
+                                              MEMORY_FREQ_MULT_133MHZ_VALUE_3 }\r
+\r
+//\r
+// CAS Memory Timing Definitions\r
+//\r
+\r
+#define MEMORY_TCL_ENTRY_TYPE    UINT8_TYPE\r
+#define MEMORY_TCL_ENTRY_3       0x2\r
+#define MEMORY_TCL_ENTRY_2       0x1\r
+#define MEMORY_TCL_ENTRY_1       0x0\r
+#define MEMORY_TCL_ENTRY_0       0x3\r
+\r
+#define MEMORY_TCL_TRANSLATION_TABLE_ENTRIES 4\r
+#define MEMORY_TCL_TRANSLATION_TABLE     { MEMORY_TCL_ENTRY_0, \\r
+                                           MEMORY_TCL_ENTRY_1, \\r
+                                           MEMORY_TCL_ENTRY_2, \\r
+                                           MEMORY_TCL_ENTRY_3 }\r
+\r
+\r
+#define MEMORY_TCL_PRECISION     0\r
+#define MEMORY_TCL_VALUE_3       3\r
+#define MEMORY_TCL_VALUE_2       4\r
+#define MEMORY_TCL_VALUE_1       5\r
+#define MEMORY_TCL_VALUE_0       6\r
+\r
+#define MEMORY_TCL_VALUES      { MEMORY_TCL_VALUE_0, \\r
+                                 MEMORY_TCL_VALUE_1, \\r
+                                 MEMORY_TCL_VALUE_2, \\r
+                                 MEMORY_TCL_VALUE_3 }\r
+\r
+\r
+//\r
+// TRCD Memory Timing Definitions\r
+//\r
+\r
+#define MEMORY_TRCD_ENTRY_TYPE    UINT8_TYPE\r
+#define MEMORY_TRCD_ENTRY_3       0x0\r
+#define MEMORY_TRCD_ENTRY_2       0x1\r
+#define MEMORY_TRCD_ENTRY_1       0x2\r
+#define MEMORY_TRCD_ENTRY_0       0x3\r
+\r
+#define MEMORY_TRCD_TRANSLATION_TABLE_ENTRIES 4\r
+#define MEMORY_TRCD_TRANSLATION_TABLE     { MEMORY_TRCD_ENTRY_0, \\r
+                                            MEMORY_TRCD_ENTRY_1, \\r
+                                            MEMORY_TRCD_ENTRY_2, \\r
+                                            MEMORY_TRCD_ENTRY_3 }\r
+\r
+\r
+#define MEMORY_TRCD_PRECISION     0\r
+#define MEMORY_TRCD_VALUE_3       2\r
+#define MEMORY_TRCD_VALUE_2       3\r
+#define MEMORY_TRCD_VALUE_1       4\r
+#define MEMORY_TRCD_VALUE_0       5\r
+\r
+#define MEMORY_TRCD_VALUES      { MEMORY_TRCD_VALUE_0, \\r
+                                  MEMORY_TRCD_VALUE_1, \\r
+                                  MEMORY_TRCD_VALUE_2, \\r
+                                  MEMORY_TRCD_VALUE_3 }\r
+\r
+\r
+//\r
+// TRP Memory Timing Definitions\r
+//\r
+\r
+#define MEMORY_TRP_ENTRY_TYPE    UINT8_TYPE\r
+#define MEMORY_TRP_ENTRY_3       0x0\r
+#define MEMORY_TRP_ENTRY_2       0x1\r
+#define MEMORY_TRP_ENTRY_1       0x2\r
+#define MEMORY_TRP_ENTRY_0       0x3\r
+\r
+#define MEMORY_TRP_TRANSLATION_TABLE_ENTRIES 4\r
+#define MEMORY_TRP_TRANSLATION_TABLE     { MEMORY_TRP_ENTRY_0, \\r
+                                           MEMORY_TRP_ENTRY_1, \\r
+                                           MEMORY_TRP_ENTRY_2, \\r
+                                           MEMORY_TRP_ENTRY_3 }\r
+\r
+\r
+#define MEMORY_TRP_PRECISION     0\r
+#define MEMORY_TRP_VALUE_3       2\r
+#define MEMORY_TRP_VALUE_2       3\r
+#define MEMORY_TRP_VALUE_1       4\r
+#define MEMORY_TRP_VALUE_0       5\r
+\r
+#define MEMORY_TRP_VALUES      { MEMORY_TRP_VALUE_0, \\r
+                                 MEMORY_TRP_VALUE_1, \\r
+                                 MEMORY_TRP_VALUE_2, \\r
+                                 MEMORY_TRP_VALUE_3 }\r
+\r
+\r
+//\r
+// TRAS Memory Timing Definitions\r
+//\r
+#define MEMORY_TRAS_MIN     4\r
+#define MEMORY_TRAS_MAX     18\r
+#define MEMORY_TRAS_STEP    1\r
+#define MEMORY_TRAS_DEFAULT 13\r
+#define MEMORY_TRAS_COUNT ((MEMORY_TRAS_MAX - MEMORY_TRAS_MIN)/MEMORY_TRAS_STEP) + 1\r
+#define MEMORY_TRAS_TYPE  UINT8_TYPE\r
+\r
+//\r
+// Uncore Multiplier Definitions\r
+//\r
+#define UCLK_RATIO_MIN     12\r
+#define UCLK_RATIO_MAX     30\r
+#define UCLK_RATIO_DEFAULT 20\r
+\r
+#endif // #ifndef _CONFIGURATION_H\r

diff --git a/Vlv2TbltDevicePkg/PlatformDxe/ExI.c b/Vlv2TbltDevicePkg/PlatformDxe/ExI.c
new file mode 100644 (file)
index 0000000..2dad89f
--- /dev/null
+++ b/Vlv2TbltDevicePkg/PlatformDxe/ExI.c
@@ -0,0 +1,83 @@
+/** @file\r
+\r
+  Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+Module Name:\r
+\r
+\r
+  ExI.c\r
+\r
+Abstract:\r
+\r
+  ExI configuration based on setup option\r
+\r
+\r
+--*/\r
+\r
+\r
+#include "PlatformDxe.h"\r
+\r
+#define PchLpcPciCfg32(Register)  MmioRead32 (MmPciAddress (0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_LPC, 0, Register))\r
+\r
+//\r
+// Procedure: GetPmcBase\r
+//\r
+// Description: This function read content of B:D:F 0:31:0, offset 44h (for\r
+// PmcBase)\r
+//\r
+// Input: None\r
+//\r
+// Output:  32 bit PmcBase\r
+//\r
+UINT32\r
+GetPmcBase (\r
+  VOID\r
+  )\r
+{\r
+  return (PchLpcPciCfg32 (R_PCH_LPC_PMC_BASE) & B_PCH_LPC_PMC_BASE_BAR);\r
+}\r
+\r
+/**\r
+  Configure ExI.\r
+\r
+  @param ImageHandle    Pointer to the loaded image protocol for this driver\r
+  @param SystemTable    Pointer to the EFI System Table\r
+\r
+  @retval EFI_SUCCESS   The driver initializes correctly.\r
+**/\r
+VOID\r
+InitExI (\r
+  )\r
+{\r
+  EFI_STATUS                  Status;\r
+\r
+  SYSTEM_CONFIGURATION          SystemConfiguration;\r
+  UINTN       VarSize;\r
+\r
+  VarSize = sizeof(SYSTEM_CONFIGURATION);\r
+\r
+  Status = gRT->GetVariable(\r
+                  L"Setup",\r
+                  &gEfiNormalSetupGuid,\r
+                  NULL,\r
+                  &VarSize,\r
+                  &SystemConfiguration\r
+                  );\r
+\r
+  ASSERT_EFI_ERROR(Status);\r
+\r
+  if (SystemConfiguration.ExISupport == 1) {\r
+         MmioOr32 ((UINTN) (GetPmcBase() + R_PCH_PMC_MTPMC1), (UINT32) BIT0+BIT1+BIT2);\r
+  } else if (SystemConfiguration.ExISupport == 0) {\r
+    MmioAnd32 ((UINTN) (GetPmcBase() + R_PCH_PMC_MTPMC1), ~((UINT32) BIT0+BIT1+BIT2)); //clear bit 0,1,2\r
+  }\r
+}\r

diff --git a/Vlv2TbltDevicePkg/PlatformDxe/IchPlatformPolicy.c b/Vlv2TbltDevicePkg/PlatformDxe/IchPlatformPolicy.c
new file mode 100644 (file)
index 0000000..753eb54
--- /dev/null
+++ b/Vlv2TbltDevicePkg/PlatformDxe/IchPlatformPolicy.c
@@ -0,0 +1,496 @@
+/** @file
+
+  Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>
+                                                                                   
+
+  This program and the accompanying materials are licensed and made available under
+
+  the terms and conditions of the BSD License that accompanies this distribution.  
+
+  The full text of the license may be found at                                     
+
+  http://opensource.org/licenses/bsd-license.php.                                  
+
+                                                                                   
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            
+
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    
+
+                                                                                   
+
+
+Module Name:
+
+
+  PchPlatformPolicy.c
+
+Abstract:
+
+
+--*/
+
+#include "PlatformDxe.h"
+#include <Protocol/PchPlatformPolicy.h>
+#include <Protocol/VlvPlatformPolicy.h>
+#include <Library/PchPlatformLib.h>
+
+#include "AzaliaVerbTable.h"
+#include "Protocol/GlobalNvsArea.h"
+#include "Protocol/DxePchPolicyUpdateProtocol.h"
+
+#define MOBILE_PLATFORM 1
+#define DESKTOP_PLATFORM 2
+
+EFI_GUID                        gDxePchPolicyUpdateProtocolGuid = DXE_PCH_POLICY_UPDATE_PROTOCOL_GUID;
+DXE_PCH_POLICY_UPDATE_PROTOCOL  mDxePchPolicyUpdate = { 0 };
+
+/**
+
+  Updates the feature policies according to the setup variable.
+
+  @retval VOID
+
+**/
+VOID
+InitPchPlatformPolicy (
+  IN EFI_PLATFORM_INFO_HOB      *PlatformInfo
+  )
+{
+  DXE_PCH_PLATFORM_POLICY_PROTOCOL *DxePlatformPchPolicy;
+  EFI_STATUS                       Status;
+  EFI_GLOBAL_NVS_AREA_PROTOCOL     *GlobalNvsArea;
+  UINT8                            PortIndex;
+  EFI_HANDLE                       Handle;
+  PCH_STEPPING                     SocStepping = PchA0;
+  BOOLEAN                          ModifyVariable;
+
+  ModifyVariable = FALSE;
+  DEBUG ((EFI_D_INFO, "InitPchPlatformPolicy() - Start\n"));
+
+  Status  = gBS->LocateProtocol (&gDxePchPlatformPolicyProtocolGuid, NULL, (VOID **) &DxePlatformPchPolicy);
+  ASSERT_EFI_ERROR (Status);
+
+  //
+  //  Locate the Global NVS Protocol.
+  //
+  Status = gBS->LocateProtocol (
+                  &gEfiGlobalNvsAreaProtocolGuid,
+                  NULL,
+                  (VOID **) &GlobalNvsArea
+                  );
+  ASSERT_EFI_ERROR (Status);
+
+  //
+  // Update system information
+  //
+  DxePlatformPchPolicy->Revision  = DXE_PCH_PLATFORM_POLICY_PROTOCOL_REVISION_12;
+
+  //
+  // General initialization
+  //
+  DxePlatformPchPolicy->BusNumber = 0;
+
+  //
+  // VLV BIOS Spec Section 3.6 Flash Security Recommendation,
+  // Intel strongly recommends that BIOS sets the BIOS Interface Lock Down bit. Enabling this bit
+  // will mitigate malicious software attempts to replace the system BIOS option ROM with its own code.
+  // We always enable this as a platform policy.
+  //
+  DxePlatformPchPolicy->LockDownConfig->BiosInterface = PCH_DEVICE_ENABLE;
+  DxePlatformPchPolicy->LockDownConfig->BiosLock = mSystemConfiguration.SpiRwProtect;
+
+  //
+  // DeviceEnables
+  //
+  DxePlatformPchPolicy->DeviceEnabling->Lan = mSystemConfiguration.Lan;
+  DxePlatformPchPolicy->DeviceEnabling->Azalia        = mSystemConfiguration.PchAzalia;
+  DxePlatformPchPolicy->DeviceEnabling->Sata          = mSystemConfiguration.Sata;
+  DxePlatformPchPolicy->DeviceEnabling->Smbus         = PCH_DEVICE_ENABLE;
+  DxePlatformPchPolicy->DeviceEnabling->LpeEnabled    = mSystemConfiguration.Lpe;
+
+  DxePlatformPchPolicy->UsbConfig->Ehci1Usbr          = PCH_DEVICE_DISABLE;
+
+  DxePlatformPchPolicy->UsbConfig->UsbXhciLpmSupport =mSystemConfiguration.UsbXhciLpmSupport;
+
+  //
+  // Disable FFRD PR0 USB port2 for power saving since PR0 uses non-POR WWAN (but enable on PR0.3/PR0.5/PR1)
+  //
+  if ((PlatformInfo->BoardId == BOARD_ID_BL_FFRD) && (PlatformInfo->BoardRev == PR0))
+    if (mSystemConfiguration.PchUsbPort[2] !=0) {
+      mSystemConfiguration.PchUsbPort[2]=0;
+      ModifyVariable = TRUE;
+    }
+
+
+  if (ModifyVariable) {
+    Status = gRT->SetVariable (
+                    NORMAL_SETUP_NAME,
+                    &gEfiNormalSetupGuid,
+                    EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS,
+                    sizeof(SYSTEM_CONFIGURATION),
+                    &mSystemConfiguration
+                    );
+  }
+
+  SocStepping = PchStepping();
+  if (mSystemConfiguration.UsbAutoMode == 1) {   // auto mode is enabled
+    if (PchA0 == SocStepping) {
+       //
+      //  For A0, EHCI is enabled as default.
+      //
+      mSystemConfiguration.PchUsb20       = 1;
+      mSystemConfiguration.PchUsb30Mode   = 0;
+      mSystemConfiguration.UsbXhciSupport = 0;
+      DEBUG ((EFI_D_INFO, "EHCI is enabled as default. SOC 0x%x\n", SocStepping));
+    } else {
+       //
+      //  For A1 and later, XHCI is enabled as default.
+      //
+      mSystemConfiguration.PchUsb20       = 0;
+      mSystemConfiguration.PchUsb30Mode   = 1;
+      mSystemConfiguration.UsbXhciSupport = 1;
+      DEBUG ((EFI_D_INFO, "XHCI is enabled as default. SOC 0x%x\n", SocStepping));
+    }
+    //
+    //overwrite the setting
+    //
+    Status = gRT->SetVariable(
+                    NORMAL_SETUP_NAME,
+                    &gEfiNormalSetupGuid,
+                    EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS,
+                    sizeof(SYSTEM_CONFIGURATION),
+                    &mSystemConfiguration
+                    );
+  }
+
+  //
+  // USB Device 29 configuration
+  //
+  DxePlatformPchPolicy->UsbConfig->Usb20Settings[0].Enable = mSystemConfiguration.PchUsb20;
+  DxePlatformPchPolicy->UsbConfig->UsbPerPortCtl           = mSystemConfiguration.PchUsbPerPortCtl;
+  if (mSystemConfiguration.PchUsbPerPortCtl != PCH_DEVICE_DISABLE) {
+    for (PortIndex = 0; PortIndex < PCH_USB_MAX_PHYSICAL_PORTS; PortIndex++) {
+      DxePlatformPchPolicy->UsbConfig->PortSettings[PortIndex].Enable = mSystemConfiguration.PchUsbPort[PortIndex];
+    }
+  }
+
+  DxePlatformPchPolicy->UsbConfig->EhciDebug               = mSystemConfiguration.PchEhciDebug;
+
+  //
+  // xHCI (USB 3.0) related settings from setup variable
+  //
+  DxePlatformPchPolicy->UsbConfig->Usb30Settings.XhciStreams    = mSystemConfiguration.PchUsb30Streams;
+
+  DxePlatformPchPolicy->UsbConfig->Usb30Settings.Mode           = mSystemConfiguration.PchUsb30Mode;
+
+  //
+  // Remove XHCI Pre-Boot Driver setup option selection from end-user view and automate loading of USB 3.0 BIOS driver based on XhciMode selection
+  //
+  switch (mSystemConfiguration.PchUsb30Mode) {
+    case 0: // Disabled
+      DxePlatformPchPolicy->UsbConfig->Usb30Settings.PreBootSupport = 0;
+      break;
+    case 1: // Enabled
+      DxePlatformPchPolicy->UsbConfig->Usb30Settings.PreBootSupport = 1;
+      break;
+    case 2: // Auto
+      DxePlatformPchPolicy->UsbConfig->Usb30Settings.PreBootSupport = 0;
+      break;
+    case 3: // Smart Auto
+      DxePlatformPchPolicy->UsbConfig->Usb30Settings.PreBootSupport = 1;
+      break;
+    default:
+      DxePlatformPchPolicy->UsbConfig->Usb30Settings.PreBootSupport = mSystemConfiguration.UsbXhciSupport;
+      break;
+  }
+
+
+
+  DxePlatformPchPolicy->UsbConfig->UsbOtgSettings.Enable  = mSystemConfiguration.PchUsbOtg;
+
+  DxePlatformPchPolicy->UsbConfig->PortSettings[0].Dock   = PCH_DEVICE_DISABLE;
+  DxePlatformPchPolicy->UsbConfig->PortSettings[1].Dock   = PCH_DEVICE_DISABLE;
+  DxePlatformPchPolicy->UsbConfig->PortSettings[2].Dock   = PCH_DEVICE_DISABLE;
+  DxePlatformPchPolicy->UsbConfig->PortSettings[3].Dock   = PCH_DEVICE_DISABLE;
+
+  DxePlatformPchPolicy->UsbConfig->PortSettings[0].Panel  = PCH_USB_FRONT_PANEL;
+  DxePlatformPchPolicy->UsbConfig->PortSettings[1].Panel  = PCH_USB_FRONT_PANEL;
+  DxePlatformPchPolicy->UsbConfig->PortSettings[2].Panel  = PCH_USB_BACK_PANEL;
+  DxePlatformPchPolicy->UsbConfig->PortSettings[3].Panel  = PCH_USB_BACK_PANEL;
+
+  //
+  //
+  // Enable USB Topology control and program the topology setting for every USB port
+  // See Platform Design Guide for description of topologies
+  //
+  //
+  // Port 0: ~5.3", Port 1: ~4.9", Port 2: ~4.7", Port 3: ~8.0"
+  //
+  DxePlatformPchPolicy->UsbConfig->Usb20PortLength[0]  = 0x53;
+  DxePlatformPchPolicy->UsbConfig->Usb20PortLength[1]  = 0x49;
+  DxePlatformPchPolicy->UsbConfig->Usb20PortLength[2]  = 0x47;
+  DxePlatformPchPolicy->UsbConfig->Usb20PortLength[3]  = 0x80;
+
+  DxePlatformPchPolicy->UsbConfig->Usb20OverCurrentPins[0]  = PchUsbOverCurrentPin0;
+  DxePlatformPchPolicy->UsbConfig->Usb20OverCurrentPins[1]  = PchUsbOverCurrentPin0;
+  DxePlatformPchPolicy->UsbConfig->Usb20OverCurrentPins[2]  = PchUsbOverCurrentPin1;
+  DxePlatformPchPolicy->UsbConfig->Usb20OverCurrentPins[3]  = PchUsbOverCurrentPin1;
+
+  DxePlatformPchPolicy->UsbConfig->Usb30OverCurrentPins[0]  = PchUsbOverCurrentPinSkip;//PchUsbOverCurrentPin0;
+
+  DxePlatformPchPolicy->EhciPllCfgEnable = mSystemConfiguration.EhciPllCfgEnable;
+  DEBUG ((EFI_D_INFO, "InitPchPlatformPolicy() DxePlatformPchPolicy->EhciPllCfgEnable = 0x%x \n",DxePlatformPchPolicy->EhciPllCfgEnable));
+    DxePlatformPchPolicy->PciExpressConfig->PcieDynamicGating                                 = mSystemConfiguration.PcieDynamicGating;
+  for (PortIndex = 0; PortIndex < PCH_PCIE_MAX_ROOT_PORTS; PortIndex++) {
+    DxePlatformPchPolicy->PciExpressConfig->RootPort[PortIndex].Enable                        = mSystemConfiguration.IchPciExp[PortIndex];
+    DxePlatformPchPolicy->PciExpressConfig->RootPort[PortIndex].SlotImplemented               = PCH_DEVICE_ENABLE;
+    DxePlatformPchPolicy->PciExpressConfig->RootPort[PortIndex].FunctionNumber                = PortIndex;
+    DxePlatformPchPolicy->PciExpressConfig->RootPort[PortIndex].PhysicalSlotNumber            = PortIndex;
+    DxePlatformPchPolicy->PciExpressConfig->RootPort[PortIndex].Aspm                          = 4;
+    DxePlatformPchPolicy->PciExpressConfig->RootPort[PortIndex].PmSci                         = PCH_DEVICE_DISABLE;
+    DxePlatformPchPolicy->PciExpressConfig->RootPort[PortIndex].ExtSync                       = PCH_DEVICE_DISABLE;
+    DxePlatformPchPolicy->PciExpressConfig->RootPort[PortIndex].HotPlug                       = PCH_DEVICE_DISABLE;
+    DxePlatformPchPolicy->PciExpressConfig->RootPort[PortIndex].AdvancedErrorReporting        = PCH_DEVICE_DISABLE;
+    DxePlatformPchPolicy->PciExpressConfig->RootPort[PortIndex].UnsupportedRequestReport      = PCH_DEVICE_DISABLE;
+    DxePlatformPchPolicy->PciExpressConfig->RootPort[PortIndex].FatalErrorReport              = PCH_DEVICE_DISABLE;
+    DxePlatformPchPolicy->PciExpressConfig->RootPort[PortIndex].NoFatalErrorReport            = PCH_DEVICE_DISABLE;
+    DxePlatformPchPolicy->PciExpressConfig->RootPort[PortIndex].CorrectableErrorReport        = PCH_DEVICE_DISABLE;
+    DxePlatformPchPolicy->PciExpressConfig->RootPort[PortIndex].PmeInterrupt                  = 0;
+    DxePlatformPchPolicy->PciExpressConfig->RootPort[PortIndex].SystemErrorOnFatalError       = PCH_DEVICE_DISABLE;
+    DxePlatformPchPolicy->PciExpressConfig->RootPort[PortIndex].SystemErrorOnNonFatalError    = PCH_DEVICE_DISABLE;
+    DxePlatformPchPolicy->PciExpressConfig->RootPort[PortIndex].SystemErrorOnCorrectableError = PCH_DEVICE_DISABLE;
+    DxePlatformPchPolicy->PciExpressConfig->RootPort[PortIndex].CompletionTimeout             = PchPciECompletionTO_Default;
+  }
+
+  //
+  // SATA configuration
+  //
+  for (PortIndex = 0; PortIndex < PCH_AHCI_MAX_PORTS; PortIndex++) {
+    if (mSystemConfiguration.SataType == 0) {
+      DxePlatformPchPolicy->SataConfig->PortSettings[PortIndex].Enable   = PCH_DEVICE_ENABLE;
+      DxePlatformPchPolicy->SataConfig->LegacyMode                       = PCH_DEVICE_ENABLE;
+    } else {
+      DxePlatformPchPolicy->SataConfig->PortSettings[PortIndex].Enable   = PCH_DEVICE_ENABLE;
+      DxePlatformPchPolicy->SataConfig->LegacyMode                       = PCH_DEVICE_DISABLE;
+    }
+    if(mSystemConfiguration.Sata == 1){
+      DxePlatformPchPolicy->SataConfig->PortSettings[PortIndex].Enable   = PCH_DEVICE_ENABLE;
+    } else {
+      DxePlatformPchPolicy->SataConfig->PortSettings[PortIndex].Enable   = PCH_DEVICE_DISABLE;
+    }
+    if(0 == PortIndex){
+      DxePlatformPchPolicy->SataConfig->PortSettings[PortIndex].HotPlug    = PCH_DEVICE_DISABLE;
+    } else if(1 == PortIndex){
+      DxePlatformPchPolicy->SataConfig->PortSettings[PortIndex].HotPlug    = PCH_DEVICE_DISABLE;
+    }
+
+    DxePlatformPchPolicy->SataConfig->PortSettings[PortIndex].SpinUp     = PCH_DEVICE_DISABLE;
+    DxePlatformPchPolicy->SataConfig->PortSettings[PortIndex].MechSw     = PCH_DEVICE_DISABLE;
+  }
+  DxePlatformPchPolicy->SataConfig->RaidAlternateId                 = PCH_DEVICE_DISABLE;
+  DxePlatformPchPolicy->SataConfig->Raid0                           = PCH_DEVICE_ENABLE;
+  DxePlatformPchPolicy->SataConfig->Raid1                           = PCH_DEVICE_ENABLE;
+  DxePlatformPchPolicy->SataConfig->Raid10                          = PCH_DEVICE_ENABLE;
+  DxePlatformPchPolicy->SataConfig->Raid5                           = PCH_DEVICE_ENABLE;
+  DxePlatformPchPolicy->SataConfig->Irrt                            = PCH_DEVICE_ENABLE;
+  DxePlatformPchPolicy->SataConfig->OromUiBanner                    = PCH_DEVICE_ENABLE;
+  DxePlatformPchPolicy->SataConfig->HddUnlock                       = PCH_DEVICE_ENABLE;
+  DxePlatformPchPolicy->SataConfig->LedLocate                       = PCH_DEVICE_ENABLE;
+  DxePlatformPchPolicy->SataConfig->IrrtOnly                        = PCH_DEVICE_ENABLE;
+  DxePlatformPchPolicy->SataConfig->SalpSupport                     = PCH_DEVICE_ENABLE;
+  DxePlatformPchPolicy->SataConfig->TestMode                        = mSystemConfiguration.SataTestMode;
+
+  //
+  // AzaliaConfig
+  //
+  DxePlatformPchPolicy->AzaliaConfig->Pme       = mSystemConfiguration.AzaliaPme;
+  DxePlatformPchPolicy->AzaliaConfig->HdmiCodec = mSystemConfiguration.HdmiCodec;
+  DxePlatformPchPolicy->AzaliaConfig->DS        = mSystemConfiguration.AzaliaDs;
+  DxePlatformPchPolicy->AzaliaConfig->AzaliaVCi = mSystemConfiguration.AzaliaVCiEnable;
+
+  //
+  // Set LPSS configuration according to setup value.
+  //
+  DxePlatformPchPolicy->LpssConfig->LpssPciModeEnabled   = mSystemConfiguration.LpssPciModeEnabled;
+
+  DxePlatformPchPolicy->LpssConfig->Dma1Enabled    = mSystemConfiguration.LpssDma1Enabled;
+  DxePlatformPchPolicy->LpssConfig->I2C0Enabled    = mSystemConfiguration.LpssI2C0Enabled;
+  DxePlatformPchPolicy->LpssConfig->I2C1Enabled    = mSystemConfiguration.LpssI2C1Enabled;
+  DxePlatformPchPolicy->LpssConfig->I2C2Enabled    = mSystemConfiguration.LpssI2C2Enabled;
+  DxePlatformPchPolicy->LpssConfig->I2C3Enabled    = mSystemConfiguration.LpssI2C3Enabled;
+  DxePlatformPchPolicy->LpssConfig->I2C4Enabled    = mSystemConfiguration.LpssI2C4Enabled;
+  DxePlatformPchPolicy->LpssConfig->I2C5Enabled    = mSystemConfiguration.LpssI2C5Enabled;
+  DxePlatformPchPolicy->LpssConfig->I2C6Enabled    = mSystemConfiguration.LpssI2C6Enabled;
+
+  DxePlatformPchPolicy->LpssConfig->Dma0Enabled    = mSystemConfiguration.LpssDma0Enabled;;
+  DxePlatformPchPolicy->LpssConfig->Pwm0Enabled    = mSystemConfiguration.LpssPwm0Enabled;
+  DxePlatformPchPolicy->LpssConfig->Pwm1Enabled    = mSystemConfiguration.LpssPwm1Enabled;
+  DxePlatformPchPolicy->LpssConfig->Hsuart0Enabled = mSystemConfiguration.LpssHsuart0Enabled;
+  DxePlatformPchPolicy->LpssConfig->Hsuart1Enabled = mSystemConfiguration.LpssHsuart1Enabled;
+  DxePlatformPchPolicy->LpssConfig->SpiEnabled     = mSystemConfiguration.LpssSpiEnabled;
+
+  //
+  // Set SCC configuration according to setup value.
+  //
+  DxePlatformPchPolicy->SccConfig->SdioEnabled   = mSystemConfiguration.LpssSdioEnabled;
+  DxePlatformPchPolicy->SccConfig->SdcardEnabled = TRUE;
+  DxePlatformPchPolicy->SccConfig->SdCardSDR25Enabled = mSystemConfiguration.LpssSdCardSDR25Enabled;
+  DxePlatformPchPolicy->SccConfig->SdCardDDR50Enabled = mSystemConfiguration.LpssSdCardDDR50Enabled;
+  DxePlatformPchPolicy->SccConfig->HsiEnabled    = mSystemConfiguration.LpssMipiHsi;
+
+  if (mSystemConfiguration.eMMCBootMode== 1) {// Auto detection mode
+  //
+  // Silicon Stepping
+  //
+  switch (PchStepping()) {
+    case PchA0: // A0 and A1
+    case PchA1:
+      DEBUG ((EFI_D_ERROR, "Auto Detect: SOC A0/A1: SCC eMMC 4.41 Configuration\n"));
+      DxePlatformPchPolicy->SccConfig->eMMCEnabled            = 1;
+      DxePlatformPchPolicy->SccConfig->eMMC45Enabled          = 0;
+      DxePlatformPchPolicy->SccConfig->eMMC45DDR50Enabled     = 0;
+      DxePlatformPchPolicy->SccConfig->eMMC45HS200Enabled     = 0;
+      DxePlatformPchPolicy->SccConfig->eMMC45RetuneTimerValue = 0;
+      break;
+    case PchB0: // B0 and later
+    default:
+      DEBUG ((EFI_D_ERROR, "Auto Detect: SOC B0 and later: SCC eMMC 4.5 Configuration\n"));
+      DxePlatformPchPolicy->SccConfig->eMMCEnabled            = 0;
+      DxePlatformPchPolicy->SccConfig->eMMC45Enabled          = mSystemConfiguration.LpsseMMC45Enabled;
+      DxePlatformPchPolicy->SccConfig->eMMC45DDR50Enabled     = mSystemConfiguration.LpsseMMC45DDR50Enabled;
+      DxePlatformPchPolicy->SccConfig->eMMC45HS200Enabled     = mSystemConfiguration.LpsseMMC45HS200Enabled;
+      DxePlatformPchPolicy->SccConfig->eMMC45RetuneTimerValue = mSystemConfiguration.LpsseMMC45RetuneTimerValue;
+      break;
+  }
+ } else if (mSystemConfiguration.eMMCBootMode == 2) { // eMMC 4.41
+    DEBUG ((EFI_D_ERROR, "Force to SCC eMMC 4.41 Configuration\n"));
+    DxePlatformPchPolicy->SccConfig->eMMCEnabled            = 1;
+    DxePlatformPchPolicy->SccConfig->eMMC45Enabled          = 0;
+    DxePlatformPchPolicy->SccConfig->eMMC45DDR50Enabled     = 0;
+    DxePlatformPchPolicy->SccConfig->eMMC45HS200Enabled     = 0;
+    DxePlatformPchPolicy->SccConfig->eMMC45RetuneTimerValue = 0;
+
+ } else if (mSystemConfiguration.eMMCBootMode == 3) { // eMMC 4.5
+      DEBUG ((EFI_D_ERROR, "Force to eMMC 4.5 Configuration\n"));
+      DxePlatformPchPolicy->SccConfig->eMMCEnabled            = 0;
+      DxePlatformPchPolicy->SccConfig->eMMC45Enabled          = mSystemConfiguration.LpsseMMC45Enabled;
+      DxePlatformPchPolicy->SccConfig->eMMC45DDR50Enabled     = mSystemConfiguration.LpsseMMC45DDR50Enabled;
+      DxePlatformPchPolicy->SccConfig->eMMC45HS200Enabled     = mSystemConfiguration.LpsseMMC45HS200Enabled;
+      DxePlatformPchPolicy->SccConfig->eMMC45RetuneTimerValue = mSystemConfiguration.LpsseMMC45RetuneTimerValue;
+
+ } else { // Disable eMMC controllers
+      DEBUG ((EFI_D_ERROR, "Disable eMMC controllers\n"));
+      DxePlatformPchPolicy->SccConfig->eMMCEnabled            = 0;
+      DxePlatformPchPolicy->SccConfig->eMMC45Enabled          = 0;
+      DxePlatformPchPolicy->SccConfig->eMMC45DDR50Enabled     = 0;
+      DxePlatformPchPolicy->SccConfig->eMMC45HS200Enabled     = 0;
+      DxePlatformPchPolicy->SccConfig->eMMC45RetuneTimerValue = 0;
+ }
+
+  //
+  // Reserved SMBus Address
+  //
+  DxePlatformPchPolicy->SmbusConfig->NumRsvdSmbusAddresses  = 4;
+  DxePlatformPchPolicy->SmbusConfig->RsvdSmbusAddressTable  = mSmbusRsvdAddresses;
+
+  //
+  // MiscPm Configuration
+  //
+  DxePlatformPchPolicy->MiscPmConfig->WakeConfig.WolEnableOverride        = mSystemConfiguration.WakeOnLanS5;
+  DxePlatformPchPolicy->MiscPmConfig->SlpLanLowDc                         = mSystemConfiguration.SlpLanLowDc;
+  DxePlatformPchPolicy->MiscPmConfig->PowerResetStatusClear.MeWakeSts     = PCH_DEVICE_ENABLE;
+  DxePlatformPchPolicy->MiscPmConfig->PowerResetStatusClear.MeHrstColdSts = PCH_DEVICE_ENABLE;
+  DxePlatformPchPolicy->MiscPmConfig->PowerResetStatusClear.MeHrstWarmSts = PCH_DEVICE_ENABLE;
+
+  //
+  // Enable / disable serial IRQ according to setup value.
+  //
+  DxePlatformPchPolicy->SerialIrqConfig->SirqEnable = PCH_DEVICE_ENABLE;
+
+  //
+  // Set Serial IRQ Mode Select according to setup value.
+  //
+  DxePlatformPchPolicy->SerialIrqConfig->SirqMode = PchQuietMode;
+
+  //
+  // Program the default Sub System Vendor Device Id
+  //
+  DxePlatformPchPolicy->DefaultSvidSid->SubSystemVendorId = V_PCH_INTEL_VENDOR_ID;
+  DxePlatformPchPolicy->DefaultSvidSid->SubSystemId       = V_PCH_DEFAULT_SID;
+
+  mAzaliaVerbTable[9].VerbTableData = mAzaliaVerbTableData12;
+
+  DxePlatformPchPolicy->AzaliaConfig->AzaliaVerbTableNum  = sizeof (mAzaliaVerbTable) / sizeof (PCH_AZALIA_VERB_TABLE);
+  DxePlatformPchPolicy->AzaliaConfig->AzaliaVerbTable     = mAzaliaVerbTable;
+  DxePlatformPchPolicy->AzaliaConfig->ResetWaitTimer      = 300;
+
+  DxePlatformPchPolicy->IdleReserve = mSystemConfiguration.IdleReserve;
+  DxePlatformPchPolicy->AcpiHWRed = PCH_DEVICE_DISABLE;
+
+  //
+  // Install DxePchPolicyUpdateProtocol
+  //
+  Handle                        = NULL;
+
+  mDxePchPolicyUpdate.Revision  = DXE_PCH_POLICY_UPDATE_PROTOCOL_REVISION_1;
+
+  Status = gBS->InstallMultipleProtocolInterfaces (
+                  &Handle,
+                  &gDxePchPolicyUpdateProtocolGuid,
+                  &mDxePchPolicyUpdate,
+                  NULL
+                  );
+  ASSERT_EFI_ERROR (Status);
+
+  DEBUG ((EFI_D_INFO, "InitPchPlatformPolicy() - End\n"));
+}
+
+
+DXE_VLV_PLATFORM_POLICY_PROTOCOL mDxePlatformVlvPolicy;
+
+VOID
+InitVlvPlatformPolicy (
+  )
+{
+  DXE_VLV_PLATFORM_POLICY_PROTOCOL *DxePlatformVlvPolicy;
+  EFI_STATUS                      Status;
+  EFI_HANDLE                      Handle;
+
+  ZeroMem (&mDxePlatformVlvPolicy, sizeof(DXE_VLV_PLATFORM_POLICY_PROTOCOL));
+
+  DxePlatformVlvPolicy = &mDxePlatformVlvPolicy;
+
+
+  DxePlatformVlvPolicy->GraphicReserve00 = mSystemConfiguration.GraphicReserve00;
+  DxePlatformVlvPolicy->PavpMode = mSystemConfiguration.PavpMode;
+  DxePlatformVlvPolicy->GraphicReserve01 = 1;
+  DxePlatformVlvPolicy->GraphicReserve02 = mSystemConfiguration.GraphicReserve02;
+  DxePlatformVlvPolicy->GraphicReserve03 = 1;
+  DxePlatformVlvPolicy->GraphicReserve04 = 0;
+  DxePlatformVlvPolicy->GraphicReserve05 = mSystemConfiguration.GraphicReserve05;
+  DxePlatformVlvPolicy->IgdPanelFeatures.PFITStatus = mSystemConfiguration.PanelScaling;
+  
+  DxePlatformVlvPolicy->IgdPanelFeatures.LidStatus = 1;
+  DxePlatformVlvPolicy->IdleReserve = mSystemConfiguration.IdleReserve;
+
+  DxePlatformVlvPolicy->GraphicReserve06 = 1;
+
+  if ( (mSystemConfiguration.Lpe == 1) || mSystemConfiguration.Lpe == 2) {
+    DxePlatformVlvPolicy ->AudioTypeSupport = LPE_AUDIO ;
+  } else if ( mSystemConfiguration.PchAzalia == 1 ) {
+    DxePlatformVlvPolicy ->AudioTypeSupport = HD_AUDIO;
+  } else {
+    DxePlatformVlvPolicy ->AudioTypeSupport = NO_AUDIO;
+  }
+
+  Handle = NULL;
+  Status = gBS->InstallProtocolInterface (
+                  &Handle,
+                  &gDxeVlvPlatformPolicyGuid,
+                  EFI_NATIVE_INTERFACE,
+                  DxePlatformVlvPolicy
+                  );
+  ASSERT_EFI_ERROR(Status);
+
+}

diff --git a/Vlv2TbltDevicePkg/PlatformDxe/IchRegTable.c b/Vlv2TbltDevicePkg/PlatformDxe/IchRegTable.c
new file mode 100644 (file)
index 0000000..06d325c
--- /dev/null
+++ b/Vlv2TbltDevicePkg/PlatformDxe/IchRegTable.c
@@ -0,0 +1,141 @@
+/** @file\r
+\r
+  Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+Module Name:\r
+\r
+\r
+  IchRegTable.c\r
+\r
+Abstract:\r
+\r
+  Register initialization table for Ich.\r
+\r
+\r
+\r
+--*/\r
+\r
+#include <Library/EfiRegTableLib.h>\r
+#include "PlatformDxe.h"\r
+extern EFI_PLATFORM_INFO_HOB      mPlatformInfo;\r
+\r
+#define R_EFI_PCI_SVID 0x2C\r
+\r
+EFI_REG_TABLE mSubsystemIdRegs [] = {\r
+\r
+  //\r
+  // Program SVID and SID for PCI devices.\r
+  // Combine two 16 bit PCI_WRITE into one 32 bit PCI_WRITE in order to boost performance\r
+  //\r
+  PCI_WRITE (\r
+      MC_BUS, MC_DEV, MC_FUN, R_EFI_PCI_SVID, EfiPciWidthUint32,\r
+      V_PCH_DEFAULT_SVID_SID, OPCODE_FLAG_S3SAVE\r
+    ),\r
+\r
+  PCI_WRITE (\r
+      IGD_BUS, IGD_DEV, IGD_FUN_0, R_EFI_PCI_SVID, EfiPciWidthUint32,\r
+      V_PCH_DEFAULT_SVID_SID, OPCODE_FLAG_S3SAVE\r
+    ),\r
+\r
+  PCI_WRITE(\r
+      DEFAULT_PCI_BUS_NUMBER_PCH, 0, 0, R_EFI_PCI_SVID, EfiPciWidthUint32,\r
+      V_PCH_DEFAULT_SVID_SID, OPCODE_FLAG_S3SAVE\r
+    ),\r
+  PCI_WRITE (\r
+      DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_LPC, PCI_FUNCTION_NUMBER_PCH_LPC, R_PCH_LPC_SS, EfiPciWidthUint32,\r
+      V_PCH_DEFAULT_SVID_SID, OPCODE_FLAG_S3SAVE\r
+    ),\r
+  PCI_WRITE (\r
+      DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_SATA, PCI_FUNCTION_NUMBER_PCH_SATA, R_PCH_SATA_SS, EfiPciWidthUint32,\r
+      V_PCH_DEFAULT_SVID_SID, OPCODE_FLAG_S3SAVE\r
+    ),\r
+  PCI_WRITE (\r
+      DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_SMBUS, PCI_FUNCTION_NUMBER_PCH_SMBUS, R_PCH_SMBUS_SVID, EfiPciWidthUint32,\r
+      V_PCH_DEFAULT_SVID_SID, OPCODE_FLAG_S3SAVE\r
+    ),\r
+  PCI_WRITE (\r
+      DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_USB, PCI_FUNCTION_NUMBER_PCH_EHCI, R_PCH_EHCI_SVID, EfiPciWidthUint32,\r
+      V_PCH_DEFAULT_SVID_SID, OPCODE_FLAG_S3SAVE\r
+    ),\r
+  PCI_WRITE (\r
+      DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORTS, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_1, R_PCH_PCIE_SVID, EfiPciWidthUint32,\r
+      V_PCH_DEFAULT_SVID_SID, OPCODE_FLAG_S3SAVE\r
+    ),\r
+  PCI_WRITE (\r
+      DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORTS, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_2, R_PCH_PCIE_SVID, EfiPciWidthUint32,\r
+      V_PCH_DEFAULT_SVID_SID, OPCODE_FLAG_S3SAVE\r
+    ),\r
+  PCI_WRITE (\r
+      DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORTS, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_3, R_PCH_PCIE_SVID, EfiPciWidthUint32,\r
+      V_PCH_DEFAULT_SVID_SID, OPCODE_FLAG_S3SAVE\r
+    ),\r
+  PCI_WRITE (\r
+      DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORTS, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_4, R_PCH_PCIE_SVID, EfiPciWidthUint32,\r
+      V_PCH_DEFAULT_SVID_SID, OPCODE_FLAG_S3SAVE\r
+    ),\r
+  TERMINATE_TABLE\r
+};\r
+\r
+/**\r
+  Updates the mSubsystemIdRegs table, and processes it.  This should program\r
+  the Subsystem Vendor and Device IDs.\r
+\r
+  @retval Returns  VOID\r
+\r
+**/\r
+VOID\r
+InitializeSubsystemIds (\r
+  )\r
+{\r
+\r
+  EFI_REG_TABLE *RegTablePtr;\r
+  UINT32 SubsystemVidDid;\r
+  UINT32 SubsystemAudioVidDid;\r
+\r
+  SubsystemVidDid = mPlatformInfo.SsidSvid;\r
+  SubsystemAudioVidDid = mPlatformInfo.SsidSvid;\r
+\r
+  RegTablePtr = mSubsystemIdRegs;\r
+\r
+  //\r
+  // While we are not at the end of the table\r
+  //\r
+  while (RegTablePtr->Generic.OpCode != OP_TERMINATE_TABLE) {\r
+       //\r
+    // If the data to write is the original SSID\r
+    //\r
+    if (RegTablePtr->PciWrite.Data ==\r
+          ((V_PCH_DEFAULT_SID << 16) |\r
+           V_PCH_INTEL_VENDOR_ID)\r
+       ) {\r
+\r
+       //\r
+      // Then overwrite it to use the alternate SSID\r
+      //\r
+      RegTablePtr->PciWrite.Data = SubsystemVidDid;\r
+    }\r
+\r
+    //\r
+    // Go to next table entry\r
+    //\r
+    RegTablePtr++;\r
+    }\r
+\r
+  RegTablePtr = mSubsystemIdRegs;\r
+\r
+\r
+  //\r
+  // Program the SSVID/SSDID\r
+  //\r
+  ProcessRegTablePci (mSubsystemIdRegs, mPciRootBridgeIo, NULL);\r
+\r
+}\r

diff --git a/Vlv2TbltDevicePkg/PlatformDxe/IchTcoReset.c b/Vlv2TbltDevicePkg/PlatformDxe/IchTcoReset.c
new file mode 100644 (file)
index 0000000..7c21271
--- /dev/null
+++ b/Vlv2TbltDevicePkg/PlatformDxe/IchTcoReset.c
@@ -0,0 +1,216 @@
+/** @file\r
+\r
+  Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+Module Name:\r
+\r
+\r
+  IchTcoReset.c\r
+\r
+Abstract:\r
+  Implements the programming of events in TCO Reset\r
+\r
+\r
+--*/\r
+\r
+#include "PlatformDxe.h"\r
+#include <Protocol/TcoReset.h>\r
+#include <Protocol/HwWatchdogTimer.h>\r
+\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+EnableTcoReset (\r
+  IN      UINT32            *RcrbGcsSaveValue\r
+  );\r
+  \r
+EFI_STATUS\r
+EFIAPI\r
+DisableTcoReset (\r
+  OUT     UINT32    RcrbGcsRestoreValue\r
+  );\r
+\r
+EFI_TCO_RESET_PROTOCOL  mTcoResetProtocol = {\r
+  EnableTcoReset,\r
+  DisableTcoReset\r
+};\r
+\r
+/**\r
+\r
+  Enables the TCO timer to reset the system in case of a system hang.  This is\r
+  used when writing the clock registers.\r
+\r
+  @param RcrbGcsSaveValue   This is the value of the RCRB GCS register before it is\r
+                            changed by this procedure.  This will be used to restore\r
+                            the settings of this register in PpiDisableTcoReset.\r
+\r
+  @retval  EFI_STATUS\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+EnableTcoReset (\r
+  IN      UINT32            *RcrbGcsSaveValue\r
+  )\r
+{\r
+  UINT16          TmpWord;\r
+  UINT16          AcpiBase;\r
+  EFI_WATCHDOG_TIMER_DRIVER_PROTOCOL  *WatchdogTimerProtocol;\r
+  EFI_STATUS          Status;\r
+  UINTN           PbtnDisableInterval = 4;  //Default value\r
+\r
+  //\r
+  // Get Watchdog Timer protocol.\r
+  //\r
+  Status = gBS->LocateProtocol (\r
+                  &gEfiWatchdogTimerDriverProtocolGuid,\r
+                  NULL,\r
+                  (VOID **)&WatchdogTimerProtocol\r
+                  );\r
+\r
+  //\r
+  // If the protocol is present, shut off the Timer as we enter BDS\r
+  //\r
+  if (!EFI_ERROR(Status)) {\r
+    WatchdogTimerProtocol->RestartWatchdogTimer();\r
+    WatchdogTimerProtocol->AllowKnownReset(TRUE);\r
+  }\r
+\r
+  if (*RcrbGcsSaveValue == 0) {\r
+    PbtnDisableInterval = PcdGet32(PcdPBTNDisableInterval);\r
+  } else {\r
+    PbtnDisableInterval = *RcrbGcsSaveValue * 10 / 6;\r
+  }\r
+\r
+  //\r
+  // Read ACPI Base Address\r
+  //\r
+  AcpiBase = PchLpcPciCfg16(R_PCH_LPC_ACPI_BASE) & B_PCH_LPC_ACPI_BASE_BAR;\r
+\r
+  //\r
+  // Stop TCO if not already stopped\r
+  //\r
+  TmpWord = IoRead16(AcpiBase + R_PCH_TCO_CNT);\r
+  TmpWord |= B_PCH_TCO_CNT_TMR_HLT;\r
+  IoWrite16(AcpiBase + R_PCH_TCO_CNT, TmpWord);\r
+\r
+  //\r
+  // Clear second TCO status\r
+  //\r
+  IoWrite32(AcpiBase + R_PCH_TCO_STS, B_PCH_TCO_STS_SECOND_TO);\r
+\r
+  //\r
+  // Enable reboot on TCO timeout\r
+  //\r
+  *RcrbGcsSaveValue = MmioRead32 (PMC_BASE_ADDRESS + R_PCH_PMC_PM_CFG);\r
+  MmioAnd8 (PMC_BASE_ADDRESS + R_PCH_PMC_PM_CFG, (UINT8) ~B_PCH_PMC_PM_CFG_NO_REBOOT);\r
+\r
+  //\r
+  // Set TCO reload value (interval *.6s)\r
+  //\r
+  IoWrite32(AcpiBase + R_PCH_TCO_TMR, (UINT32)(PbtnDisableInterval<<16));\r
+\r
+  //\r
+  // Force TCO to load new value\r
+  //\r
+  IoWrite8(AcpiBase + R_PCH_TCO_RLD, 4);\r
+\r
+  //\r
+  // Clear second TCO status\r
+  //\r
+  IoWrite32(AcpiBase + R_PCH_TCO_STS, B_PCH_TCO_STS_SECOND_TO);\r
+\r
+  //\r
+  // Start TCO timer running\r
+  //\r
+  TmpWord = IoRead16(AcpiBase + R_PCH_TCO_CNT);\r
+  TmpWord &= ~(B_PCH_TCO_CNT_TMR_HLT);\r
+  IoWrite16(AcpiBase + R_PCH_TCO_CNT, TmpWord);\r
+\r
+  return EFI_SUCCESS;\r
+}\r
+\r
+/**\r
+  Disables the TCO timer.  This is used after writing the clock registers.\r
+\r
+  @param RcrbGcsRestoreValue   Value saved in PpiEnableTcoReset so that it can\r
+                               restored.\r
+\r
+  @retval EFI_STATUS\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+DisableTcoReset (\r
+  OUT     UINT32    RcrbGcsRestoreValue\r
+  )\r
+{\r
+  UINT16          TmpWord;\r
+  UINT16          AcpiBase;\r
+  EFI_WATCHDOG_TIMER_DRIVER_PROTOCOL  *WatchdogTimerProtocol;\r
+  EFI_STATUS          Status;\r
+\r
+  //\r
+  // Read ACPI Base Address\r
+  //\r
+  AcpiBase = PchLpcPciCfg16(R_PCH_LPC_ACPI_BASE) & B_PCH_LPC_ACPI_BASE_BAR;\r
+\r
+  //\r
+  // Stop the TCO timer\r
+  //\r
+  TmpWord = IoRead16(AcpiBase + R_PCH_TCO_CNT);\r
+  TmpWord |= B_PCH_TCO_CNT_TMR_HLT;\r
+  IoWrite16(AcpiBase + R_PCH_TCO_CNT, TmpWord);\r
+\r
+  //\r
+  // Get Watchdog Timer protocol.\r
+  //\r
+  Status = gBS->LocateProtocol (\r
+                  &gEfiWatchdogTimerDriverProtocolGuid,\r
+                  NULL,\r
+                  (VOID **)&WatchdogTimerProtocol\r
+                  );\r
+\r
+  //\r
+  // If the protocol is present, shut off the Timer as we enter BDS\r
+  //\r
+  if (!EFI_ERROR(Status)) {\r
+    WatchdogTimerProtocol->AllowKnownReset(FALSE);\r
+  }\r
+\r
+  return EFI_SUCCESS;\r
+}\r
+\r
+/**\r
+\r
+  Updates the feature policies according to the setup variable.\r
+\r
+  @retval Returns   VOID\r
+\r
+**/\r
+VOID\r
+InitTcoReset (\r
+  )\r
+{\r
+  EFI_HANDLE                        Handle;\r
+  EFI_STATUS                        Status;\r
+\r
+  Handle = NULL;\r
+  Status = gBS->InstallProtocolInterface (\r
+                  &Handle,\r
+                  &gEfiTcoResetProtocolGuid,\r
+                  EFI_NATIVE_INTERFACE,\r
+                  &mTcoResetProtocol\r
+                  );\r
+  ASSERT_EFI_ERROR(Status);\r
+\r
+}\r

diff --git a/Vlv2TbltDevicePkg/PlatformDxe/IdccInfo.c b/Vlv2TbltDevicePkg/PlatformDxe/IdccInfo.c
new file mode 100644 (file)
index 0000000..6993222
--- /dev/null
+++ b/Vlv2TbltDevicePkg/PlatformDxe/IdccInfo.c
@@ -0,0 +1,77 @@
+/** @file\r
+\r
+  Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+Module Name:\r
+\r
+\r
+  IdccInfo.c\r
+\r
+Abstract:\r
+\r
+  Platform information used by IDCC.\r
+\r
+Revision History\r
+\r
+--*/\r
+\r
+#include "PlatformDxe.h"\r
+\r
+#include <Guid/IdccData.h>\r
+\r
+extern EFI_GUID mPlatformDriverGuid;\r
+\r
+\r
+EFI_STATUS\r
+WriteIdccInfo (\r
+  )\r
+{\r
+  EFI_STATUS                Status;\r
+  EFI_DATA_HUB_PROTOCOL     *DataHub;\r
+  UINT8                     Ratio;\r
+  EFI_IDCC_PROCESSOR_RATIO  ProcRatio;\r
+\r
+  //\r
+  // Locate the data hub protocol\r
+  //\r
+  Status = gBS->LocateProtocol (\r
+                  &gEfiDataHubProtocolGuid,\r
+                  NULL,\r
+                  (VOID **) &DataHub\r
+                  );\r
+\r
+  //\r
+  // Find processor actual ratio\r
+  //\r
+  Ratio = 15; //Temporary - some dummy value.\r
+\r
+  //\r
+  // Fill in IDCC Type 5 structure\r
+  //\r
+  ProcRatio.IdccHeader.Type = EFI_IDCC_PROC_RATIO_TYPE;\r
+  ProcRatio.IdccHeader.RecordLength = sizeof(EFI_IDCC_PROCESSOR_RATIO);\r
+  ProcRatio.ProcessorRatio = Ratio;\r
+\r
+  //\r
+  // Write data to the data hub\r
+  //\r
+  Status = DataHub->LogData (\r
+                      DataHub,\r
+                      &gIdccDataHubGuid,\r
+                      &mPlatformDriverGuid,\r
+                      EFI_DATA_RECORD_CLASS_DATA,\r
+                      &ProcRatio,\r
+                      sizeof(EFI_IDCC_PROCESSOR_RATIO)\r
+                      );\r
+\r
+  return Status;\r
+}\r

diff --git a/Vlv2TbltDevicePkg/PlatformDxe/LegacySpeaker.c b/Vlv2TbltDevicePkg/PlatformDxe/LegacySpeaker.c
new file mode 100644 (file)
index 0000000..9ac816d
--- /dev/null
+++ b/Vlv2TbltDevicePkg/PlatformDxe/LegacySpeaker.c
@@ -0,0 +1,166 @@
+/** @file\r
+\r
+  Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+Module Name:\r
+\r
+ LegacySpeaker.c\r
+\r
+Abstract:\r
+\r
+  This file implements DXE for Legacy Speaker.\r
+\r
+--*/\r
+\r
+#include "LegacySpeaker.h"\r
+\r
+/**\r
+\r
+  This function will enable the speaker to generate beep\r
+\r
+  @retval EFI_STATUS\r
+\r
+**/\r
+EFI_STATUS\r
+TurnOnSpeaker (\r
+  )\r
+{\r
+  UINT8                   Data;\r
+  Data = IoRead8 (EFI_SPEAKER_CONTROL_PORT);\r
+  Data |= 0x03;\r
+  IoWrite8(EFI_SPEAKER_CONTROL_PORT, Data);\r
+  return EFI_SUCCESS;\r
+}\r
+\r
+/**\r
+\r
+  This function will stop beep from speaker.\r
+\r
+  @retval Status\r
+\r
+**/\r
+EFI_STATUS\r
+TurnOffSpeaker (\r
+  )\r
+{\r
+  UINT8                   Data;\r
+\r
+  Data = IoRead8 (EFI_SPEAKER_CONTROL_PORT);\r
+  Data &= 0xFC;\r
+  IoWrite8(EFI_SPEAKER_CONTROL_PORT, Data);\r
+  return EFI_SUCCESS;\r
+}\r
+\r
+/**\r
+  Generate beep sound based upon number of beeps and duration of the beep\r
+\r
+  @param NumberOfBeeps     Number of beeps which user want to produce\r
+  @param BeepDuration      Duration for speaker gate need to be enabled\r
+  @param TimeInterval      Interval between each beep\r
+\r
+  @retval      Does not return if the reset takes place.\r
+               EFI_INVALID_PARAMETER   If ResetType is invalid.\r
+\r
+**/\r
+EFI_STATUS\r
+OutputBeep (\r
+  IN     UINTN                              NumberOfBeep,\r
+  IN     UINTN                              BeepDuration,\r
+  IN     UINTN                              TimeInterval\r
+  )\r
+{\r
+  UINTN           Num;\r
+\r
+  for (Num=0; Num < NumberOfBeep; Num++) {\r
+    TurnOnSpeaker ();\r
+    //\r
+    // wait some time,at least 120us\r
+    //\r
+    gBS->Stall (BeepDuration);\r
+    TurnOffSpeaker();\r
+    gBS->Stall (TimeInterval);\r
+  }\r
+\r
+  return EFI_SUCCESS;\r
+}\r
+\r
+/**\r
+  This function will program the speaker tone frequency. The value should be with 64k\r
+  boundary since it takes only 16 bit value which gets programmed in two step IO opearattion\r
+\r
+  @param  Frequency     A value which should be 16 bit only.\r
+\r
+  @retval EFI_SUCESS\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI    \r
+ProgramToneFrequency (\r
+  IN EFI_SPEAKER_IF_PROTOCOL            * This,\r
+  IN  UINT16                            Frequency\r
+  )\r
+{\r
+  UINT8                   Data;\r
+\r
+  Data = 0xB6;\r
+  IoWrite8(EFI_TIMER_CONTROL_PORT, Data);\r
+\r
+  Data = (UINT8)(Frequency & 0x00FF);\r
+  IoWrite8(EFI_TIMER_2_PORT, Data);\r
+  Data = (UINT8)((Frequency & 0xFF00) >> 8);\r
+  IoWrite8(EFI_TIMER_2_PORT, Data);\r
+  return EFI_SUCCESS;\r
+}\r
+\r
+/**\r
+  This function will generate the beep for specified duration.\r
+\r
+  @param NumberOfBeeps     Number of beeps which user want to produce\r
+  @param BeepDuration      Duration for speaker gate need to be enabled\r
+  @param TimeInterval      Interval between each beep\r
+\r
+  @retval EFI_STATUS\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+GenerateBeepTone (\r
+  IN EFI_SPEAKER_IF_PROTOCOL            * This,\r
+  IN  UINTN                             NumberOfBeeps,\r
+  IN  UINTN                             BeepDuration,\r
+  IN  UINTN                             TimeInterval\r
+  )\r
+{\r
+\r
+  if ((NumberOfBeeps == 1) && (BeepDuration == 0) && (TimeInterval == 0)) {\r
+    TurnOnSpeaker ();\r
+    return EFI_SUCCESS;\r
+  }\r
+\r
+  if ((NumberOfBeeps == 0) && (BeepDuration == 0) && (TimeInterval == 0)) {\r
+    TurnOffSpeaker ();\r
+    return EFI_SUCCESS;\r
+  }\r
+\r
+  if (BeepDuration == 0) {\r
+    BeepDuration = EFI_DEFAULT_SHORT_BEEP_DURATION;\r
+  }\r
+\r
+  if (TimeInterval == 0) {\r
+    TimeInterval = EFI_DEFAULT_BEEP_TIME_INTERVAL;\r
+  }\r
+\r
+  OutputBeep (NumberOfBeeps, BeepDuration, TimeInterval);\r
+  return EFI_SUCCESS;\r
+\r
+\r
+}\r

diff --git a/Vlv2TbltDevicePkg/PlatformDxe/LegacySpeaker.h b/Vlv2TbltDevicePkg/PlatformDxe/LegacySpeaker.h
new file mode 100644 (file)
index 0000000..2075139
--- /dev/null
+++ b/Vlv2TbltDevicePkg/PlatformDxe/LegacySpeaker.h
@@ -0,0 +1,74 @@
+/*++\r
+\r
+  Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+Module Name:\r
+\r
+ LegacySpeaker.h\r
+\r
+Abstract:\r
+\r
+  Speaker enabling related data\r
+\r
+--*/\r
+\r
+#ifndef _DXE_LEGACY_SPEAKER_H\r
+#define _DXE_LEGACY_SPEAKER_H\r
+\r
+#include "PlatformDxe.h"\r
+\r
+//\r
+// Speaker Related Port Information\r
+//\r
+#define EFI_TIMER_COUNTER_PORT            0x40\r
+#define EFI_TIMER_CONTROL_PORT            0x43\r
+#define EFI_TIMER_2_PORT                  0x42\r
+#define EFI_SPEAKER_CONTROL_PORT          0x61\r
+\r
+#define EFI_SPEAKER_OFF_MASK              0xFC\r
+\r
+#define EFI_DEFAULT_BEEP_FREQUENCY        0x500\r
+\r
+//\r
+// Default Intervals/Beep Duration\r
+//\r
+#define EFI_DEFAULT_LONG_BEEP_DURATION    0x70000\r
+#define EFI_DEFAULT_SHORT_BEEP_DURATION   0x50000\r
+#define EFI_DEFAULT_BEEP_TIME_INTERVAL    0x20000\r
+\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+ProgramToneFrequency (\r
+  IN  EFI_SPEAKER_IF_PROTOCOL           * This,\r
+  IN  UINT16                            Frequency\r
+  );\r
+\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+GenerateBeepTone (\r
+  IN  EFI_SPEAKER_IF_PROTOCOL           * This,\r
+  IN  UINTN                             NumberOfBeeps,\r
+  IN  UINTN                             BeepDuration,\r
+  IN  UINTN                             TimeInterval\r
+  );\r
+\r
+EFI_STATUS\r
+TurnOnSpeaker (\r
+  );\r
+\r
+EFI_STATUS\r
+TurnOffSpeaker (\r
+  );\r
+\r
+#endif\r

diff --git a/Vlv2TbltDevicePkg/PlatformDxe/Observable/Observable.c b/Vlv2TbltDevicePkg/PlatformDxe/Observable/Observable.c
new file mode 100644 (file)
index 0000000..c67862c
--- /dev/null
+++ b/Vlv2TbltDevicePkg/PlatformDxe/Observable/Observable.c
@@ -0,0 +1,587 @@
+/*++\r
+  This file contains 'Framework Code' and is licensed as such\r
+  under the terms of your license agreement with Intel or your\r
+  vendor.  This file may not be modified, except as allowed by\r
+  additional terms of your license agreement.\r
+--*/\r
+/*++\r
+\r
+Copyright (c)  2010  - 2014, Intel Corporation. All rights reserved\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+\r
+Module Name:\r
+\r
+  Observable.c\r
+\r
+Abstract:\r
+\r
+  The following contains all of the implementation for the Observable protocol. The\r
+  protocol uses the observer design pattern to provide a way to publish events and\r
+  to subscribe to those events so that a callback will be performed at the time of\r
+  the event. The observables and subscribers are maintained by the static tree,\r
+  mObservableDb. The difference between this protocol and the existing event protocol\r
+  that exists within the EFI framework is that this protocol allows for parameters\r
+  to be passed to the subscribed callbacks that can contain up to date context.\r
+\r
+--*/\r
+\r
+#include "Observable.h"\r
+\r
+static OBS_TREE*                mObservableDb = NULL;\r
+static EFI_HANDLE               mObservableHandle = NULL;\r
+static OBS_OBSERVABLE_PROTOCOL  mObservable = {\r
+  AddObservable,\r
+  RemoveObservable,\r
+  Subscribe,\r
+  Unsubscribe,\r
+  Publish,\r
+  RemoveAllObservables\r
+};\r
+\r
+/** Install observable protocol.\r
+ *\r
+ * Install interface and initialize the observable protocol.\r
+ *\r
+ * @param   VOID          No parameters.\r
+ *\r
+ * @return  EFI_SUCCESS   Successfully installed and initialized the protocol.\r
+ **/\r
+EFI_STATUS\r
+InitializeObservableProtocol(\r
+  VOID\r
+  )\r
+{\r
+  EFI_STATUS  Status;\r
+\r
+  //\r
+  // Install protocol.\r
+  //\r
+  Status = gBS->InstallProtocolInterface (\r
+                  &mObservableHandle,\r
+                  &gObservableProtocolGuid,\r
+                  EFI_NATIVE_INTERFACE,\r
+                  &mObservable\r
+                  );\r
+\r
+  return Status;\r
+}\r
+\r
+/** Deletes a subscriber\r
+ *\r
+ * This function removes the subscriber pointed to by Head.\r
+ *\r
+ * @param   OBS_TREE*     Head    Points to the current subscriber.\r
+ *\r
+ * @return  OBS_TREE*     Returns the tree after successfully removing the subscriber.\r
+ **/\r
+OBS_LEAF*\r
+DeleteSubscriber(\r
+  OBS_LEAF* Head\r
+  )\r
+{\r
+  OBS_LEAF* Temp;\r
+\r
+  if (Head) {\r
+    Temp = Head;\r
+    Head = Head->Next;\r
+    gBS->FreePool(Temp);\r
+  }\r
+\r
+  return Head;\r
+}\r
+\r
+/** Finds and deletes all subscribers\r
+ *\r
+ * This function iterates recursively through the existing subscribers and delets them all.\r
+ *\r
+ * @param   OBS_TREE*     Head    Points to the current subscriber.\r
+ *\r
+ * @return  OBS_TREE*     Returns the tree after successfully removing the subscribers.\r
+ **/\r
+OBS_LEAF*\r
+DeleteAllSubscribers(\r
+  OBS_LEAF* Head\r
+  )\r
+{\r
+  if (Head) {\r
+    if (Head->Next) {\r
+      //\r
+      // We aren't at the end of the list yet.\r
+      //\r
+      Head->Next = DeleteAllSubscribers(Head->Next);\r
+    }\r
+\r
+    //\r
+    // At the end, so delete the subscriber.\r
+    //\r
+    Head = DeleteSubscriber(Head);\r
+  }\r
+\r
+  return Head;\r
+}\r
+\r
+/** Deletes an observable\r
+ *\r
+ * This function removes the observable pointed to by Head.\r
+ *\r
+ * @param   OBS_TREE*     Head    Points to the current observable.\r
+ *\r
+ * @return  OBS_TREE*     Returns the tree after successfully removing the observable.\r
+ **/\r
+OBS_TREE*\r
+DeleteObservable(\r
+  OBS_TREE* Head\r
+  )\r
+{\r
+  OBS_TREE* Temp;\r
+\r
+  if (Head) {\r
+    Temp = Head;\r
+    Head = Head->Next;\r
+    gBS->FreePool(Temp);\r
+  }\r
+\r
+  return Head;\r
+}\r
+\r
+/** Finds and deletes all observables\r
+ *\r
+ * This function iterates recursively through the existing observables database and, starting with\r
+ * the last most observable, deletes all of its subscribers, then deletes the observable itself.\r
+ *\r
+ * @param   OBS_TREE*     Head    Points to the current observable.\r
+ *\r
+ * @return  OBS_TREE*     Returns the tree after successfully removing the observables.\r
+ **/\r
+OBS_TREE*\r
+DeleteAllObservables(\r
+  OBS_TREE* Head\r
+  )\r
+{\r
+  if (Head) {\r
+    if (Head->Next) {\r
+      //\r
+      // We aren't at the end of the list yet.\r
+      //\r
+      Head->Next = DeleteAllObservables(Head->Next);\r
+    }\r
+\r
+    //\r
+    // This is the end of the list of observables.\r
+    //\r
+    Head->Leaf = DeleteAllSubscribers(Head->Leaf);\r
+\r
+    //\r
+    // Subscribers are deleted, so now delete the observable.\r
+    //\r
+    Head = DeleteObservable(Head);\r
+  }\r
+\r
+  return Head;\r
+}\r
+\r
+/** Finds and deletes observable\r
+ *\r
+ * This function iterates recursively through the existing observable database in order to find the one\r
+ * specified by ReferenceGuid so that it can be deleted. If the requested observable is found, before it\r
+ * is deleted, all of the subscribers that are listening to this observable are deleted.\r
+ *\r
+ * @param   OBS_TREE*     Head              Points to the current observable.\r
+ *          EFI_GUID      ReferenceGuid     Corresponds to the observable that we're looking for.\r
+ *\r
+ * @return  OBS_TREE*     Returns the tree after successfully removing (or not finding) the observable.\r
+ **/\r
+OBS_TREE*\r
+FindAndDeleteObservable(\r
+  OBS_TREE* Head,\r
+  EFI_GUID  ReferenceGuid\r
+  )\r
+{\r
+  if (Head) {\r
+    if (CompareMem(&(Head->ObservableGuid), &ReferenceGuid, sizeof(ReferenceGuid)) == 0) {\r
+      //\r
+      // We found the observable. Delete all of it's subscribers, first.\r
+      //\r
+      Head->Leaf = DeleteAllSubscribers(Head->Leaf);\r
+      //\r
+      // Now we can safely remove the observable.\r
+      //\r
+      Head = DeleteObservable(Head);\r
+    } else {\r
+      //\r
+      // Not found. Keep searching.\r
+      //\r
+      Head->Next = FindAndDeleteObservable(Head->Next, ReferenceGuid);\r
+    }\r
+  }\r
+\r
+  return Head;\r
+}\r
+\r
+/** Finds and deletes subscriber\r
+ *\r
+ * This function iterates recursively through the existing subscribers that are listening to the\r
+ * observable that was found when this function was called.\r
+ *\r
+ * @param   OBS_TREE*     Head              Points to the current subscriber.\r
+ *          OBS_CALLBACK  CallbackInterface This is the subscriber that is requested be removed.\r
+ *\r
+ * @return  OBS_TREE*     Returns the tree after successfully removing (or not finding) the subscriber.\r
+ **/\r
+OBS_LEAF*\r
+_FindAndDeleteSubscriber(\r
+  OBS_LEAF*     Head,\r
+  OBS_CALLBACK  CallbackInterface\r
+  )\r
+{\r
+  if (Head) {\r
+    if (Head->Observer == CallbackInterface) {\r
+      //\r
+      // Found it. Now let's delete it.\r
+      //\r
+      Head = DeleteSubscriber(Head);\r
+    } else {\r
+      //\r
+      // Not found. Keep searching.\r
+      //\r
+      Head->Next = _FindAndDeleteSubscriber(Head->Next, CallbackInterface);\r
+    }\r
+  }\r
+\r
+  return Head;\r
+}\r
+\r
+/** Finds and deletes subscriber\r
+ *\r
+ * This function iterates recursively through the existing observables database until it either finds\r
+ * a matching guid or reaches the end of the list. After finding a match, it calls a helper function,\r
+ * _FindAndDeleteSubscriber. At this point, all responsibility for finding and deleting the subscriber\r
+ * lies on the helper function.\r
+ *\r
+ * @param   OBS_TREE*     Head              Points to the current observable.\r
+ *          EFI_GUID      ReferenceGuid     Corresponds to the observable that we're looking for.\r
+ *          OBS_CALLBACK  CallbackInterface This is the subscriber that is requested be removed.\r
+ *\r
+ * @return  OBS_TREE*     Returns the tree after successfully removing (or not finding) the subscriber.\r
+ **/\r
+OBS_TREE*\r
+FindAndDeleteSubscriber(\r
+  IN  OUT OBS_TREE*     Head,\r
+  IN      EFI_GUID      ReferenceGuid,\r
+  IN      OBS_CALLBACK  CallbackInterface\r
+  )\r
+{\r
+  if (Head) {\r
+    if (CompareMem(&(Head->ObservableGuid), &ReferenceGuid, sizeof(ReferenceGuid)) == 0) {\r
+      //\r
+      // We found the observer that matches ReferenceGuid. Find and delete the subscriber that is\r
+      // listening to it.\r
+      //\r
+      Head->Leaf = _FindAndDeleteSubscriber(Head->Leaf, CallbackInterface);\r
+    } else {\r
+      //\r
+      // Not found. Keep searching.\r
+      //\r
+      Head->Next = FindAndDeleteSubscriber(Head->Next, ReferenceGuid, CallbackInterface);\r
+    }\r
+  }\r
+\r
+  return Head;\r
+}\r
+\r
+/** Remove all observables.\r
+ *\r
+ * Remove all observable guids and all interfaces subscribed to them.\r
+ *\r
+ * @param   VOID          No parameters.\r
+ *\r
+ * @return  EFI_SUCCESS   Successfully removed all observables and subscribed interfaces.\r
+ **/\r
+EFI_STATUS\r
+EFIAPI\r
+RemoveAllObservables(\r
+  VOID\r
+  )\r
+{\r
+  mObservableDb = DeleteAllObservables(mObservableDb);\r
+\r
+  return EFI_SUCCESS;\r
+}\r
+\r
+/** Subscribe an interface with an observable guid.\r
+ *\r
+ * Use this to register a callback function with a guid. The function provided by CallbackInterface will be executed\r
+ * whenever the appropriate observable instance specified by ReferenceGuid calls Publish.\r
+ *\r
+ * @param   EFI_GUID              ReferenceGuid       The observable guid that the callback interface will subscribe to.\r
+ *          OBS_CASLLBACK         CallbackInterface   A pointer to the function that is subscribing to the observable.\r
+ *\r
+ * @return  EFI_SUCCESS           Successfully subscribed the interface to the observable guid.\r
+ *          EFI_NOT_FOUND         No match could be found between the provided guid and existing observables.\r
+ *          EFI_OUT_OF_RESOURCES  Could not subscribe to this observer due to resource limitations.\r
+ *          EFI_INVALID_PARAMETER Interface is already subscribed to this observer.\r
+ **/\r
+EFI_STATUS\r
+EFIAPI\r
+Subscribe (\r
+  IN      EFI_GUID        ReferenceGuid,\r
+  IN      OBS_CALLBACK    CallbackInterface\r
+  )\r
+{\r
+  EFI_STATUS  Status    = EFI_SUCCESS;\r
+  OBS_TREE*   TempTree  = NULL;\r
+  OBS_LEAF*   Last      = NULL;\r
+  OBS_LEAF*   TempLeaf  = NULL;\r
+  OBS_LEAF*   NewLeaf   = NULL;\r
+  BOOLEAN     Found     = FALSE;\r
+\r
+  if (mObservableDb != NULL) {\r
+    //\r
+    // Find the observable guid that we're looking for.\r
+    //\r
+    for (TempTree = mObservableDb; TempTree != NULL; TempTree = TempTree->Next) {\r
+      if (CompareMem(&(TempTree->ObservableGuid), &ReferenceGuid, sizeof(ReferenceGuid)) == 0) {\r
+        Found = TRUE;\r
+        break;\r
+      }\r
+    }\r
+    if (Found) {\r
+      //\r
+      // Prepare to add a new leaf.\r
+      //\r
+      NewLeaf = AllocateZeroPool(sizeof(OBS_LEAF));\r
+      if (!NewLeaf) {\r
+        Status = EFI_OUT_OF_RESOURCES;\r
+      } else {\r
+        NewLeaf->Next = NULL;\r
+        NewLeaf->Observer = CallbackInterface;\r
+        //\r
+        // Go to the end of the list of observers.\r
+        //\r
+        if (TempTree->Leaf != NULL) {\r
+          //\r
+          // First check to see if this is a duplicate observer.\r
+          //\r
+          Found = FALSE;\r
+          TempLeaf = TempTree->Leaf;\r
+          do {\r
+            Last = TempLeaf;\r
+            if (TempLeaf->Observer == CallbackInterface) {\r
+              //\r
+              // It is, so let's abort this process.\r
+              //\r
+              Found = TRUE;\r
+              break;\r
+            }\r
+            TempLeaf = TempLeaf->Next;\r
+          } while (TempLeaf != NULL);\r
+          TempLeaf = Last;\r
+\r
+          //\r
+          // Check for duplicates.\r
+          //\r
+          if (Found) {\r
+            gBS->FreePool(NewLeaf);\r
+            Status = EFI_INVALID_PARAMETER;\r
+          } else {\r
+            //\r
+            // At this point, TempLeaf->Next will be the end of the list.\r
+            //\r
+            TempLeaf->Next = NewLeaf;\r
+          }\r
+        } else {\r
+          //\r
+          // There are no observers listening to this guid. Start a new list.\r
+          //\r
+          TempTree->Leaf = NewLeaf;\r
+        }\r
+      }\r
+    } else {\r
+      Status = EFI_NOT_FOUND;\r
+    }\r
+  } else {\r
+    Status = EFI_NOT_FOUND;\r
+  }\r
+\r
+  return Status;\r
+}\r
+\r
+/** Unsubscribe an interface with an observable guid.\r
+ *\r
+ * Use this to remove an interface from the callback list associated with an observable guid.\r
+ *\r
+ * @param   EFI_GUID                ReferenceGuid   The observable guid to unsubscribe the interface from.\r
+ *          OBS_NOTIFY_INTERFACE    NotifyCallback  A pointer to the interface that is being unsubscribed.\r
+ *\r
+ * @return  EFI_SUCCESS           Successfully unsubscribed the interface from the observable guid.\r
+ **/\r
+EFI_STATUS\r
+EFIAPI\r
+Unsubscribe (\r
+  IN      EFI_GUID        ReferenceGuid,\r
+  IN      OBS_CALLBACK    CallbackInterface\r
+  )\r
+{\r
+  mObservableDb = FindAndDeleteSubscriber(mObservableDb, ReferenceGuid, CallbackInterface);\r
+\r
+  return EFI_SUCCESS;\r
+}\r
+\r
+/** Notify observing functions.\r
+ *\r
+ * Use this to notify all functions who are subscribed to the guid specified by ReferenceGuid.\r
+ *\r
+ * @param   EFI_GUID          ReferenceGuid   The observable guid that contains the the list of interfaces to be notified.\r
+ *          VOID*             Data            Parameter context to be passed to the notification function.\r
+ *\r
+ * @return  EFI_SUCCESS       Successfully notified all observers listening to this guid.\r
+ *          EFI_NOT_FOUND     No match could be found between the provided guid and existing observables.\r
+ **/\r
+EFI_STATUS\r
+EFIAPI\r
+Publish (\r
+  IN      EFI_GUID                  ReferenceGuid,\r
+  IN  OUT VOID*                     Data\r
+  )\r
+{\r
+  EFI_STATUS  Status    = EFI_SUCCESS;\r
+  OBS_TREE*   TempTree  = NULL;\r
+  OBS_LEAF*   TempLeaf  = NULL;\r
+  BOOLEAN     Found     = FALSE;\r
+\r
+  if (mObservableDb != NULL) {\r
+    //\r
+    // Find the observable guid that we're looking for.\r
+    //\r
+    for (TempTree = mObservableDb; TempTree != NULL; TempTree = TempTree->Next) {\r
+      if (CompareMem(&(TempTree->ObservableGuid), &ReferenceGuid, sizeof(ReferenceGuid)) == 0) {\r
+        Found = TRUE;\r
+        break;\r
+      }\r
+    }\r
+    if (Found) {\r
+      //\r
+      // Notify every listener by performing each provided callback.\r
+      //\r
+      for (TempLeaf = TempTree->Leaf; TempLeaf != NULL; TempLeaf = TempLeaf->Next) {\r
+        if (TempLeaf->Observer != NULL) {\r
+          //\r
+          // Execute the callback.\r
+          //\r
+          TempLeaf->Observer(Data);\r
+        }\r
+      }\r
+    } else {\r
+      Status = EFI_NOT_FOUND;\r
+    }\r
+  } else {\r
+    Status = EFI_NOT_FOUND;\r
+  }\r
+\r
+  return Status;\r
+}\r
+\r
+/** Creates a new observable.\r
+ *\r
+ * Create a new observable that can be observed with the use of Subscribe function.\r
+ *\r
+ * @param   EFI_GUID              ReferenceGuid   The observable guid to add.\r
+ *\r
+ * @return  EFI_SUCCESS           Successfully added observable.\r
+ *          EFI_INVALID_PARAMETER Observable already exists.\r
+ **/\r
+EFI_STATUS\r
+EFIAPI\r
+AddObservable (\r
+  IN      EFI_GUID                  ReferenceGuid\r
+  )\r
+{\r
+  EFI_STATUS  Status    = EFI_SUCCESS;\r
+  OBS_TREE*   TempTree  = NULL;\r
+  OBS_TREE*   Last      = NULL;\r
+  OBS_TREE*   NewTree   = NULL;\r
+  BOOLEAN     Found     = FALSE;\r
+\r
+  if (mObservableDb != NULL) {\r
+    if (mObservableDb->Next != NULL) {\r
+      //\r
+      // Iterate to the end of the observable list while checking to see if we aren't creating a duplicate.\r
+      //\r
+      TempTree = mObservableDb->Next;\r
+      do {\r
+        Last = TempTree;\r
+        if (CompareMem(&(TempTree->ObservableGuid), &ReferenceGuid, sizeof(ReferenceGuid)) == 0) {\r
+          Found = TRUE;\r
+          break;\r
+        }\r
+        TempTree = TempTree->Next;\r
+      } while (TempTree != NULL);\r
+      TempTree = Last;\r
+    } else {\r
+      TempTree = mObservableDb;\r
+    }\r
+    if (Found) {\r
+      //\r
+      // Duplicate, so reject the parameter.\r
+      //\r
+      Status = EFI_INVALID_PARAMETER;\r
+    } else {\r
+      //\r
+      // TempTree->Next is our target. Prepare to add a new tree link.\r
+      //\r
+      NewTree = AllocateZeroPool(sizeof(OBS_TREE));\r
+      if (NewTree) {\r
+        NewTree->Next = NULL;\r
+        NewTree->Leaf = NULL;\r
+        CopyMem(&(NewTree->ObservableGuid), &ReferenceGuid, sizeof(ReferenceGuid));\r
+        TempTree->Next = NewTree;\r
+      } else {\r
+        Status = EFI_OUT_OF_RESOURCES;\r
+      }\r
+    }\r
+  } else {\r
+    //\r
+    // mObservableDb has not been created yet. Let's do that.\r
+    //\r
+    NewTree = AllocateZeroPool(sizeof(OBS_TREE));\r
+    if (NewTree) {\r
+      NewTree->Next = NULL;\r
+      NewTree->Leaf = NULL;\r
+      CopyMem(&(NewTree->ObservableGuid), &ReferenceGuid, sizeof(ReferenceGuid));\r
+      mObservableDb = NewTree;\r
+    } else {\r
+      Status = EFI_OUT_OF_RESOURCES;\r
+    }\r
+  }\r
+\r
+  return Status;\r
+}\r
+\r
+/** Remove an observable.\r
+ *\r
+ * Remove an observable so that it can no longer be subscribed to. In addition, unsubscribe any functions\r
+ * that are subscribed to this guid.\r
+ *\r
+ * @param   EFI_GUID              ReferenceGuid   The observable guid to remove.\r
+ *\r
+ * @return  EFI_SUCCESS           Successfully removed observable.\r
+ **/\r
+EFI_STATUS\r
+EFIAPI\r
+RemoveObservable (\r
+  IN      EFI_GUID        ReferenceGuid\r
+  )\r
+{\r
+  mObservableDb = FindAndDeleteObservable(mObservableDb, ReferenceGuid);\r
+\r
+  return EFI_SUCCESS;\r
+}\r

diff --git a/Vlv2TbltDevicePkg/PlatformDxe/Observable/Observable.h b/Vlv2TbltDevicePkg/PlatformDxe/Observable/Observable.h
new file mode 100644 (file)
index 0000000..a6bc62b
--- /dev/null
+++ b/Vlv2TbltDevicePkg/PlatformDxe/Observable/Observable.h
@@ -0,0 +1,142 @@
+/*++\r
+\r
+  Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+Module Name:\r
+\r
+  Observable.h\r
+\r
+Abstract:\r
+\r
+  Prototypes for Observable protocol implementation\r
+--*/\r
+\r
+#ifndef _OBSERVABLE_H_\r
+#define _OBSERVABLE_H_\r
+#include "PlatformDxe.h"\r
+#include "Protocol/Observable.h"\r
+\r
+//\r
+// Prototypes\r
+//\r
+\r
+/** Install observable protocol.\r
+ *\r
+ * Install interface and initialize the observable protocol.\r
+ *\r
+ * @param   VOID          No parameters.\r
+ *\r
+ * @return  EFI_SUCCESS   Successfully installed and initialized the protocol.\r
+ **/\r
+EFI_STATUS\r
+InitializeObservableProtocol(\r
+  VOID\r
+  );\r
+\r
+/** Remove all observables.\r
+ *\r
+ * Remove all observable guids and all interfaces subscribed to them.\r
+ *\r
+ * @param   VOID          No parameters.\r
+ *\r
+ * @return  EFI_SUCCESS   Successfully removed all observables and subscribed interfaces.\r
+ **/\r
+EFI_STATUS\r
+EFIAPI\r
+RemoveAllObservables(\r
+  VOID\r
+  );\r
+\r
+/** Subscribe an interface with an observable guid.\r
+ *\r
+ * Use this to register a callback function with a guid. The function provided by CallbackInterface will be executed\r
+ * whenever the appropriate observable instance specified by ReferenceGuid calls Publish.\r
+ *\r
+ * @param   EFI_GUID              ReferenceGuid       The observable guid that the callback interface will subscribe to.\r
+ *          OBS_CALLBACK          CallbackInterface   A pointer to the function that is subscribing to the observable.\r
+ *\r
+ * @return  EFI_SUCCESS           Successfully subscribed the interface to the observable guid.\r
+ *          EFI_NOT_FOUND         No match could be found between the provided guid and existing observables.\r
+ *          EFI_OUT_OF_RESOURCES  Could not subscribe to this observer due to resource limitations.\r
+ *          EFI_INVALID_PARAMETER Interface is already subscribed to this observer.\r
+ **/\r
+EFI_STATUS\r
+EFIAPI\r
+Subscribe (\r
+  IN      EFI_GUID        ReferenceGuid,\r
+  IN      OBS_CALLBACK    CallbackInterface\r
+  );\r
+\r
+/** Unsubscribe an interface with an observable guid.\r
+ *\r
+ * Use this to remove an interface from the callback list associated with an observable guid.\r
+ *\r
+ * @param   EFI_GUID              ReferenceGuid      The observable guid to unsubscribe the interface from.\r
+ *          OBS_CALLBACK          CallbackInterface  A pointer to the interface that is being unsubscribed.\r
+ *\r
+ * @return  EFI_SUCCESS           Successfully unsubscribed the interface from the observable guid.\r
+ **/\r
+EFI_STATUS\r
+EFIAPI\r
+Unsubscribe (\r
+  IN      EFI_GUID            ReferenceGuid,\r
+  IN      OBS_CALLBACK    CallbackInterface\r
+  );\r
+\r
+/** Notify observing functions.\r
+ *\r
+ * Use this to notify all functions who are subscribed to the guid specified by ReferenceGuid.\r
+ *\r
+ * @param   EFI_GUID          ReferenceGuid   The observable guid that contains the list of interfaces to be notified.\r
+ *          VOID*             Data            Parameter context to be passed to the subscribed function.\r
+ *\r
+ * @return  EFI_SUCCESS       Successfully notified all observers listening to this guid.\r
+ *          EFI_NOT_FOUND     No match could be found between the provided guid and existing observables.\r
+ **/\r
+EFI_STATUS\r
+EFIAPI\r
+Publish (\r
+  IN      EFI_GUID        ReferenceGuid,\r
+  IN  OUT VOID*           Data\r
+  );\r
+\r
+/** Creates a new observable.\r
+ *\r
+ * Create a new observable that can be observed with the use of Subscribe function.\r
+ *\r
+ * @param   EFI_GUID              ReferenceGuid   The observable guid to add.\r
+ *\r
+ * @return  EFI_SUCCESS           Successfully added observable.\r
+ *          EFI_INVALID_PARAMETER Observable already exists.\r
+ **/\r
+EFI_STATUS\r
+EFIAPI\r
+AddObservable (\r
+  IN      EFI_GUID        ReferenceGuid\r
+  );\r
+\r
+/** Remove an observable.\r
+ *\r
+ * Remove an observable so that it can no longer be subscribed to. In addition, unsubscribe any functions\r
+ * that are subscribed to this guid.\r
+ *\r
+ * @param   EFI_GUID              ReferenceGuid   The observable guid to remove.\r
+ *\r
+ * @return  EFI_SUCCESS           Successfully removed observable.\r
+ **/\r
+EFI_STATUS\r
+EFIAPI\r
+RemoveObservable (\r
+  IN      EFI_GUID        ReferenceGuid\r
+  );\r
+\r
+#endif\r

diff --git a/Vlv2TbltDevicePkg/PlatformDxe/PciBus.h b/Vlv2TbltDevicePkg/PlatformDxe/PciBus.h
new file mode 100644 (file)
index 0000000..89e31d2
--- /dev/null
+++ b/Vlv2TbltDevicePkg/PlatformDxe/PciBus.h
@@ -0,0 +1,384 @@
+/*++\r
+\r
+  Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+**/\r
+\r
+\r
+#ifndef _EFI_PCI_BUS_H_\r
+#define _EFI_PCI_BUS_H_\r
+\r
+#include <PiDxe.h>\r
+\r
+#include <Protocol/LoadedImage.h>\r
+#include <Protocol/PciHostBridgeResourceAllocation.h>\r
+#include <Protocol/PciIo.h>\r
+#include <Protocol/LoadFile2.h>\r
+#include <Protocol/PciRootBridgeIo.h>\r
+#include <Protocol/PciHotPlugRequest.h>\r
+#include <Protocol/DevicePath.h>\r
+#include <Protocol/PciPlatform.h>\r
+#include <Protocol/PciHotPlugInit.h>\r
+#include <Protocol/Decompress.h>\r
+#include <Protocol/BusSpecificDriverOverride.h>\r
+#include <Protocol/IncompatiblePciDeviceSupport.h>\r
+#include <Protocol/PciOverride.h>\r
+#include <Protocol/PciEnumerationComplete.h>\r
+\r
+#include <Library/DebugLib.h>\r
+#include <Library/UefiDriverEntryPoint.h>\r
+#include <Library/BaseLib.h>\r
+#include <Library/UefiLib.h>\r
+#include <Library/BaseMemoryLib.h>\r
+#include <Library/ReportStatusCodeLib.h>\r
+#include <Library/MemoryAllocationLib.h>\r
+#include <Library/UefiBootServicesTableLib.h>\r
+#include <Library/DevicePathLib.h>\r
+#include <Library/PcdLib.h>\r
+#include <Library/PeCoffLib.h>\r
+\r
+#include <IndustryStandard/Pci.h>\r
+#include <IndustryStandard/PeImage.h>\r
+#include <IndustryStandard/Acpi.h>\r
+\r
+typedef struct _PCI_IO_DEVICE              PCI_IO_DEVICE;\r
+typedef struct _PCI_BAR                    PCI_BAR;\r
+\r
+#define EFI_PCI_RID(Bus, Device, Function)  (((UINT32)Bus << 8) + ((UINT32)Device << 3) + (UINT32)Function)\r
+#define EFI_PCI_BUS_OF_RID(RID)             ((UINT32)RID >> 8)\r
+\r
+#define     EFI_PCI_IOV_POLICY_ARI           0x0001\r
+#define     EFI_PCI_IOV_POLICY_SRIOV         0x0002\r
+#define     EFI_PCI_IOV_POLICY_MRIOV         0x0004\r
+\r
+typedef enum {\r
+  PciBarTypeUnknown = 0,\r
+  PciBarTypeIo16,\r
+  PciBarTypeIo32,\r
+  PciBarTypeMem32,\r
+  PciBarTypePMem32,\r
+  PciBarTypeMem64,\r
+  PciBarTypePMem64,\r
+  PciBarTypeIo,\r
+  PciBarTypeMem,\r
+  PciBarTypeMaxType\r
+} PCI_BAR_TYPE;\r
+\r
+\r
+#define VGABASE1  0x3B0\r
+#define VGALIMIT1 0x3BB\r
+\r
+#define VGABASE2  0x3C0\r
+#define VGALIMIT2 0x3DF\r
+\r
+#define ISABASE   0x100\r
+#define ISALIMIT  0x3FF\r
+\r
+//\r
+// PCI BAR parameters\r
+//\r
+struct _PCI_BAR {\r
+  UINT64        BaseAddress;\r
+  UINT64        Length;\r
+  UINT64        Alignment;\r
+  PCI_BAR_TYPE  BarType;\r
+  BOOLEAN       Prefetchable;\r
+  UINT8         MemType;\r
+  UINT16        Offset;\r
+};\r
+\r
+//\r
+// defined in PCI Card Specification, 8.0\r
+//\r
+#define PCI_CARD_MEMORY_BASE_0                0x1C\r
+#define PCI_CARD_MEMORY_LIMIT_0               0x20\r
+#define PCI_CARD_MEMORY_BASE_1                0x24\r
+#define PCI_CARD_MEMORY_LIMIT_1               0x28\r
+#define PCI_CARD_IO_BASE_0_LOWER              0x2C\r
+#define PCI_CARD_IO_BASE_0_UPPER              0x2E\r
+#define PCI_CARD_IO_LIMIT_0_LOWER             0x30\r
+#define PCI_CARD_IO_LIMIT_0_UPPER             0x32\r
+#define PCI_CARD_IO_BASE_1_LOWER              0x34\r
+#define PCI_CARD_IO_BASE_1_UPPER              0x36\r
+#define PCI_CARD_IO_LIMIT_1_LOWER             0x38\r
+#define PCI_CARD_IO_LIMIT_1_UPPER             0x3A\r
+#define PCI_CARD_BRIDGE_CONTROL               0x3E\r
+\r
+#define PCI_CARD_PREFETCHABLE_MEMORY_0_ENABLE BIT8\r
+#define PCI_CARD_PREFETCHABLE_MEMORY_1_ENABLE BIT9\r
+\r
+#define PPB_BAR_0                             0\r
+#define PPB_BAR_1                             1\r
+#define PPB_IO_RANGE                          2\r
+#define PPB_MEM32_RANGE                       3\r
+#define PPB_PMEM32_RANGE                      4\r
+#define PPB_PMEM64_RANGE                      5\r
+#define PPB_MEM64_RANGE                       0xFF\r
+\r
+#define P2C_BAR_0                             0\r
+#define P2C_MEM_1                             1\r
+#define P2C_MEM_2                             2\r
+#define P2C_IO_1                              3\r
+#define P2C_IO_2                              4\r
+\r
+#define EFI_BRIDGE_IO32_DECODE_SUPPORTED      0x0001\r
+#define EFI_BRIDGE_PMEM32_DECODE_SUPPORTED    0x0002\r
+#define EFI_BRIDGE_PMEM64_DECODE_SUPPORTED    0x0004\r
+#define EFI_BRIDGE_IO16_DECODE_SUPPORTED      0x0008\r
+#define EFI_BRIDGE_PMEM_MEM_COMBINE_SUPPORTED 0x0010\r
+#define EFI_BRIDGE_MEM64_DECODE_SUPPORTED     0x0020\r
+#define EFI_BRIDGE_MEM32_DECODE_SUPPORTED     0x0040\r
+\r
+#define PCI_MAX_HOST_BRIDGE_NUM               0x0010\r
+\r
+//\r
+// Define option for attribute\r
+//\r
+#define EFI_SET_SUPPORTS    0\r
+#define EFI_SET_ATTRIBUTES  1\r
+\r
+#define PCI_IO_DEVICE_SIGNATURE               SIGNATURE_32 ('p', 'c', 'i', 'o')\r
+\r
+struct _PCI_IO_DEVICE {\r
+  UINT32                                    Signature;\r
+  EFI_HANDLE                                Handle;\r
+  EFI_PCI_IO_PROTOCOL                       PciIo;\r
+  LIST_ENTRY                                Link;\r
+\r
+  EFI_BUS_SPECIFIC_DRIVER_OVERRIDE_PROTOCOL PciDriverOverride;\r
+  EFI_DEVICE_PATH_PROTOCOL                  *DevicePath;\r
+  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL           *PciRootBridgeIo;\r
+  EFI_LOAD_FILE2_PROTOCOL                   LoadFile2;\r
+\r
+  //\r
+  // PCI configuration space header type\r
+  //\r
+  PCI_TYPE00                                Pci;\r
+\r
+  //\r
+  // Bus number, Device number, Function number\r
+  //\r
+  UINT8                                     BusNumber;\r
+  UINT8                                     DeviceNumber;\r
+  UINT8                                     FunctionNumber;\r
+\r
+  //\r
+  // BAR for this PCI Device\r
+  //\r
+  PCI_BAR                                   PciBar[PCI_MAX_BAR];\r
+\r
+  //\r
+  // The bridge device this pci device is subject to\r
+  //\r
+  PCI_IO_DEVICE                             *Parent;\r
+\r
+  //\r
+  // A linked list for children Pci Device if it is bridge device\r
+  //\r
+  LIST_ENTRY                                ChildList;\r
+\r
+  //\r
+  // TURE if the PCI bus driver creates the handle for this PCI device\r
+  //\r
+  BOOLEAN                                   Registered;\r
+\r
+  //\r
+  // TRUE if the PCI bus driver successfully allocates the resource required by\r
+  // this PCI device\r
+  //\r
+  BOOLEAN                                   Allocated;\r
+\r
+  //\r
+  // The attribute this PCI device currently set\r
+  //\r
+  UINT64                                    Attributes;\r
+\r
+  //\r
+  // The attributes this PCI device actually supports\r
+  //\r
+  UINT64                                    Supports;\r
+\r
+  //\r
+  // The resource decode the bridge supports\r
+  //\r
+  UINT32                                    Decodes;\r
+\r
+  //\r
+  // TRUE if the ROM image is from the PCI Option ROM BAR\r
+  //\r
+  BOOLEAN                                   EmbeddedRom;\r
+\r
+  //\r
+  // The OptionRom Size\r
+  //\r
+  UINT64                                    RomSize;\r
+\r
+  //\r
+  // The OptionRom Size\r
+  //\r
+  UINT64                                    RomBase;\r
+\r
+  //\r
+  // TRUE if all OpROM (in device or in platform specific position) have been processed\r
+  //\r
+  BOOLEAN                                   AllOpRomProcessed;\r
+\r
+  //\r
+  // TRUE if there is any EFI driver in the OptionRom\r
+  //\r
+  BOOLEAN                                   BusOverride;\r
+\r
+  //\r
+  // A list tracking reserved resource on a bridge device\r
+  //\r
+  LIST_ENTRY                                ReservedResourceList;\r
+\r
+  //\r
+  // A list tracking image handle of platform specific overriding driver\r
+  //\r
+  LIST_ENTRY                                OptionRomDriverList;\r
+\r
+  EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR         *ResourcePaddingDescriptors;\r
+  EFI_HPC_PADDING_ATTRIBUTES                PaddingAttributes;\r
+\r
+  BOOLEAN                                   IsPciExp;\r
+\r
+  //\r
+  // For SR-IOV\r
+  //\r
+  UINT8                                     PciExpressCapabilityOffset;\r
+  UINT32                                    AriCapabilityOffset;\r
+  UINT32                                    SrIovCapabilityOffset;\r
+  UINT32                                    MrIovCapabilityOffset;\r
+  PCI_BAR                                   VfPciBar[PCI_MAX_BAR];\r
+  UINT32                                    SystemPageSize;\r
+  UINT16                                    InitialVFs;\r
+  UINT16                                    ReservedBusNum;\r
+\r
+  //\r
+  // Per PCI to PCI Bridge spec, I/O window is 4K aligned,\r
+  // but some chipsets support non-stardard I/O window aligments less than 4K.\r
+  // This field is used to support this case.\r
+  //\r
+  UINT16                                    BridgeIoAlignment;\r
+};\r
+\r
+#define PCI_IO_DEVICE_FROM_PCI_IO_THIS(a) \\r
+  CR (a, PCI_IO_DEVICE, PciIo, PCI_IO_DEVICE_SIGNATURE)\r
+\r
+#define PCI_IO_DEVICE_FROM_PCI_DRIVER_OVERRIDE_THIS(a) \\r
+  CR (a, PCI_IO_DEVICE, PciDriverOverride, PCI_IO_DEVICE_SIGNATURE)\r
+\r
+#define PCI_IO_DEVICE_FROM_LINK(a) \\r
+  CR (a, PCI_IO_DEVICE, Link, PCI_IO_DEVICE_SIGNATURE)\r
+\r
+#define PCI_IO_DEVICE_FROM_LOAD_FILE2_THIS(a) \\r
+  CR (a, PCI_IO_DEVICE, LoadFile2, PCI_IO_DEVICE_SIGNATURE)\r
+\r
+\r
+\r
+//\r
+// Global Variables\r
+//\r
+extern EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL *gEfiIncompatiblePciDeviceSupport;\r
+extern EFI_DRIVER_BINDING_PROTOCOL                  gPciBusDriverBinding;\r
+extern EFI_COMPONENT_NAME_PROTOCOL                  gPciBusComponentName;\r
+extern EFI_COMPONENT_NAME2_PROTOCOL                 gPciBusComponentName2;\r
+extern BOOLEAN                                      gFullEnumeration;\r
+extern UINTN                                        gPciHostBridgeNumber;\r
+extern EFI_HANDLE                                   gPciHostBrigeHandles[PCI_MAX_HOST_BRIDGE_NUM];\r
+extern UINT64                                       gAllOne;\r
+extern UINT64                                       gAllZero;\r
+extern EFI_PCI_PLATFORM_PROTOCOL                    *gPciPlatformProtocol;\r
+extern EFI_PCI_OVERRIDE_PROTOCOL                    *gPciOverrideProtocol;\r
+extern BOOLEAN                                      mReserveIsaAliases;\r
+extern BOOLEAN                                      mReserveVgaAliases;\r
+\r
+/**\r
+  Macro that checks whether device is a GFX device.\r
+\r
+  @param  _p      Specified device.\r
+\r
+  @retval TRUE    Device is a a GFX device.\r
+  @retval FALSE   Device is not a a GFX device.\r
+\r
+**/\r
+#define IS_PCI_GFX(_p)     IS_CLASS2 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_OTHER)\r
+\r
+/**\r
+  Test to see if this driver supports ControllerHandle. Any ControllerHandle\r
+  than contains a gEfiPciRootBridgeIoProtocolGuid protocol can be supported.\r
+\r
+  @param  This                Protocol instance pointer.\r
+  @param  Controller          Handle of device to test.\r
+  @param  RemainingDevicePath Optional parameter use to pick a specific child.\r
+                              device to start.\r
+\r
+  @retval EFI_SUCCESS         This driver supports this device.\r
+  @retval EFI_ALREADY_STARTED This driver is already running on this device.\r
+  @retval other               This driver does not support this device.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+PciBusDriverBindingSupported (\r
+  IN EFI_DRIVER_BINDING_PROTOCOL    *This,\r
+  IN EFI_HANDLE                     Controller,\r
+  IN EFI_DEVICE_PATH_PROTOCOL       *RemainingDevicePath\r
+  );\r
+\r
+/**\r
+  Start this driver on ControllerHandle and enumerate Pci bus and start\r
+  all device under PCI bus.\r
+\r
+  @param  This                 Protocol instance pointer.\r
+  @param  Controller           Handle of device to bind driver to.\r
+  @param  RemainingDevicePath  Optional parameter use to pick a specific child.\r
+                               device to start.\r
+\r
+  @retval EFI_SUCCESS          This driver is added to ControllerHandle.\r
+  @retval EFI_ALREADY_STARTED  This driver is already running on ControllerHandle.\r
+  @retval other                This driver does not support this device.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+PciBusDriverBindingStart (\r
+  IN EFI_DRIVER_BINDING_PROTOCOL    *This,\r
+  IN EFI_HANDLE                     Controller,\r
+  IN EFI_DEVICE_PATH_PROTOCOL       *RemainingDevicePath\r
+  );\r
+\r
+/**\r
+  Stop this driver on ControllerHandle. Support stoping any child handles\r
+  created by this driver.\r
+\r
+  @param  This              Protocol instance pointer.\r
+  @param  Controller        Handle of device to stop driver on.\r
+  @param  NumberOfChildren  Number of Handles in ChildHandleBuffer. If number of\r
+                            children is zero stop the entire bus driver.\r
+  @param  ChildHandleBuffer List of Child Handles to Stop.\r
+\r
+  @retval EFI_SUCCESS       This driver is removed ControllerHandle.\r
+  @retval other             This driver was not removed from this device.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+PciBusDriverBindingStop (\r
+  IN  EFI_DRIVER_BINDING_PROTOCOL   *This,\r
+  IN  EFI_HANDLE                    Controller,\r
+  IN  UINTN                         NumberOfChildren,\r
+  IN  EFI_HANDLE                    *ChildHandleBuffer\r
+  );\r
+\r
+#endif\r

diff --git a/Vlv2TbltDevicePkg/PlatformDxe/PciDevice.c b/Vlv2TbltDevicePkg/PlatformDxe/PciDevice.c
new file mode 100644 (file)
index 0000000..16aaa18
--- /dev/null
+++ b/Vlv2TbltDevicePkg/PlatformDxe/PciDevice.c
@@ -0,0 +1,517 @@
+/** @file\r
+\r
+  Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+Module Name:\r
+\r
+\r
+  PciDevice.c\r
+\r
+Abstract:\r
+\r
+  Platform Initialization Driver.\r
+\r
+Revision History\r
+\r
+--*/\r
+\r
+#include "PlatformDxe.h"\r
+#include "Library/DxeServicesTableLib.h"\r
+#include "PciBus.h"\r
+#include "Guid/PciLanInfo.h"\r
+\r
+extern  VOID    *mPciLanInfo;\r
+extern  UINTN   mPciLanCount;\r
+\r
+extern  EFI_HANDLE  mImageHandle;\r
+extern  SYSTEM_CONFIGURATION    mSystemConfiguration;\r
+\r
+\r
+VOID       *mPciRegistration;\r
+#define NCR_VENDOR_ID  0x1000\r
+#define ATI_VENDOR_ID  0x1002\r
+#define INTEL_VENDOR_ID 0x8086\r
+#define ATI_RV423_ID   0x5548\r
+#define ATI_RV423_ID2  0x5d57\r
+#define ATI_RV380_ID   0x3e50\r
+#define ATI_RV370_ID   0x5b60\r
+#define SI_VENDOR_ID   0x1095\r
+#define SI_SISATA_ID   0x3114\r
+#define SI_SIRAID_PCIUNL 0x40\r
+#define INTEL_82573E_IDER 0x108D\r
+\r
+typedef struct {\r
+  UINT8               ClassCode;\r
+  UINT8               SubClassCode;\r
+  UINT16              VendorId;\r
+  UINT16              DeviceId;\r
+} BAD_DEVICE_TABLE;\r
+\r
+BAD_DEVICE_TABLE BadDeviceTable[] = {\r
+                    {(UINT8)PCI_CLASS_MASS_STORAGE,(UINT8)PCI_CLASS_MASS_STORAGE_SCSI,(UINT16)NCR_VENDOR_ID, (UINT16)0xffff}, // Any NCR cards\r
+                    {(UINT8)PCI_CLASS_MASS_STORAGE,(UINT8)PCI_CLASS_MASS_STORAGE_IDE,(UINT16)INTEL_VENDOR_ID, (UINT16)INTEL_82573E_IDER},  // Intel i82573E Tekoa GBit Lan IDE-R\r
+                    {(UINT8)0xff,(UINT8)0xff,(UINT16)0xffff,(UINT16)0xffff}\r
+                  };\r
+\r
+EFI_STATUS\r
+PciBusDriverHook (\r
+  )\r
+{\r
+  EFI_STATUS                Status;\r
+  EFI_EVENT                 FilterEvent;\r
+\r
+  //\r
+  // Register for callback to PCI I/O protocol\r
+  //\r
+  Status = gBS->CreateEvent (\r
+                  EVT_NOTIFY_SIGNAL,\r
+                  TPL_CALLBACK,\r
+                  PciBusEvent,\r
+                  NULL,\r
+                  &FilterEvent\r
+                  );\r
+  ASSERT_EFI_ERROR(Status);\r
+\r
+  //\r
+  // Register for protocol notifications on this event\r
+  //\r
+  Status = gBS->RegisterProtocolNotify (\r
+                  &gEfiPciIoProtocolGuid,\r
+                  FilterEvent,\r
+                  &mPciRegistration\r
+                  );\r
+  ASSERT_EFI_ERROR (Status);\r
+\r
+  return  EFI_SUCCESS;\r
+}\r
+\r
+VOID\r
+InitBadBars(\r
+  IN    EFI_PCI_IO_PROTOCOL           *PciIo,\r
+  IN    UINT16                        VendorId,\r
+  IN    UINT16                        DeviceId\r
+  )\r
+{\r
+\r
+  EFI_STATUS                          Status;\r
+  PCI_IO_DEVICE                       *PciIoDevice;\r
+  UINT64                              BaseAddress = 0;\r
+  UINT64                              TempBaseAddress = 0;\r
+  UINT8                               RevId = 0;\r
+  UINT32                              Bar;\r
+  UINT64                              IoSize;\r
+  UINT64                              MemSize;\r
+  UINTN                               MemSizeBits;\r
+\r
+\r
+  PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (PciIo);\r
+  switch ( VendorId) {\r
+    case ATI_VENDOR_ID:\r
+      //\r
+      //  ATI fix-ups. At this time all ATI cards in BadDeviceTable\r
+      //  have same problem in that OPROM BAR needs to be increased.\r
+      //\r
+      Bar = 0x30 ;\r
+      //\r
+      // Get original BAR address\r
+      //\r
+      Status = PciIo->Pci.Read (\r
+                            PciIo,\r
+                            EfiPciIoWidthUint32,\r
+                            Bar,\r
+                            1,\r
+                                (VOID *) &BaseAddress\r
+                            );\r
+      //\r
+      // Find BAR size\r
+      //\r
+      TempBaseAddress = 0xffffffff;\r
+      Status = PciIo->Pci.Write (\r
+                            PciIo,\r
+                            EfiPciIoWidthUint32,\r
+                            Bar,\r
+                            1,\r
+                                 (VOID *) &TempBaseAddress\r
+                            );\r
+      Status = PciIo->Pci.Read (\r
+                            PciIo,\r
+                            EfiPciIoWidthUint32,\r
+                            Bar,\r
+                            1,\r
+                                (VOID *) &TempBaseAddress\r
+                            );\r
+      TempBaseAddress &= 0xfffffffe;\r
+      MemSize = 1;\r
+      while ((TempBaseAddress & 0x01) == 0) {\r
+        TempBaseAddress = TempBaseAddress >> 1;\r
+        MemSize = MemSize << 1;\r
+      }\r
+\r
+      //\r
+      // Free up allocated memory memory and re-allocate with increased size.\r
+      //\r
+      Status = gDS->FreeMemorySpace (\r
+                      BaseAddress,\r
+                      MemSize\r
+                      );\r
+      //\r
+      // Force new alignment\r
+      //\r
+      MemSize = 0x8000000;\r
+      MemSizeBits = 28;\r
+\r
+      Status = gDS->AllocateMemorySpace (\r
+                      EfiGcdAllocateAnySearchBottomUp,\r
+                      EfiGcdMemoryTypeMemoryMappedIo,\r
+                      MemSizeBits,           // Alignment\r
+                      MemSize,\r
+                      &BaseAddress,\r
+                      mImageHandle,\r
+                      NULL\r
+                      );\r
+      Status = PciIo->Pci.Write (\r
+                            PciIo,\r
+                            EfiPciIoWidthUint32,\r
+                            Bar,\r
+                            1,\r
+                                 (VOID *) &BaseAddress\r
+                            );\r
+\r
+      break;\r
+    case    NCR_VENDOR_ID:\r
+#define MIN_NCR_IO_SIZE  0x800\r
+#define NCR_GRAN  11  // 2**11 = 0x800\r
+  //\r
+  // NCR SCSI cards like 8250S lie about IO needed. Assign as least 0x80.\r
+  //\r
+  for (Bar = 0x10; Bar < 0x28; Bar+= 4) {\r
+\r
+    Status = PciIo->Pci.Read (\r
+                          PciIo,\r
+                          EfiPciIoWidthUint32,\r
+                          Bar,\r
+                          1,\r
+                              (VOID *) &BaseAddress\r
+                          );\r
+    if (BaseAddress && 0x01) {\r
+      TempBaseAddress = 0xffffffff;\r
+      Status = PciIo->Pci.Write (\r
+                            PciIo,\r
+                            EfiPciIoWidthUint32,\r
+                            Bar,\r
+                            1,\r
+                                 (VOID *) &TempBaseAddress\r
+                            );\r
+      TempBaseAddress &= 0xfffffffc;\r
+      IoSize = 1;\r
+      while ((TempBaseAddress & 0x01) == 0) {\r
+        TempBaseAddress = TempBaseAddress >> 1;\r
+        IoSize = IoSize << 1;\r
+      }\r
+      if (IoSize < MIN_NCR_IO_SIZE) {\r
+        Status = gDS->FreeIoSpace (\r
+                        BaseAddress,\r
+                        IoSize\r
+                        );\r
+\r
+        Status = gDS->AllocateIoSpace (\r
+                        EfiGcdAllocateAnySearchTopDown,\r
+                        EfiGcdIoTypeIo,\r
+                        NCR_GRAN,           // Alignment\r
+                        MIN_NCR_IO_SIZE,\r
+                        &BaseAddress,\r
+                        mImageHandle,\r
+                        NULL\r
+                        );\r
+        TempBaseAddress = BaseAddress + 1;\r
+        Status = PciIo->Pci.Write (\r
+                              PciIo,\r
+                              EfiPciIoWidthUint32,\r
+                              Bar,\r
+                              1,\r
+                                   (VOID *) &TempBaseAddress\r
+                              );\r
+      }\r
+    }\r
+  }\r
+\r
+      break;\r
+\r
+    case INTEL_VENDOR_ID:\r
+      if (DeviceId == INTEL_82573E_IDER) {\r
+        //\r
+        //  Tekoa i82573E IDE-R fix-ups. At this time A2 step and earlier parts do not\r
+        //  support any BARs except BAR0. Other BARS will actualy map to BAR0 so disable\r
+        //  them all for Control Blocks and Bus mastering ops as well as Secondary IDE\r
+        //  Controller.\r
+        //  All Tekoa A2 or earlier step chips for now.\r
+        //\r
+        Status = PciIo->Pci.Read (\r
+                              PciIo,\r
+                              EfiPciIoWidthUint8,\r
+                              PCI_REVISION_ID_OFFSET,\r
+                              1,\r
+                              &RevId\r
+                              );\r
+        if (RevId <= 0x02) {\r
+          for (Bar = 0x14; Bar < 0x24; Bar+= 4) {\r
+            //\r
+            // Maybe want to clean this up a bit later but for now just clear out the secondary\r
+            // Bars don't worry aboyut freeing up thge allocs.\r
+            //\r
+            TempBaseAddress = 0x0;\r
+            Status = PciIo->Pci.Write (\r
+                                  PciIo,\r
+                                  EfiPciIoWidthUint32,\r
+                                  Bar,\r
+                                  1,\r
+                                       (VOID *) &TempBaseAddress\r
+                                  );\r
+          } // end for\r
+        }\r
+        else\r
+        {\r
+               //\r
+          //Tekoa A3 or above:\r
+          //Clear bus master base address (PCI register 0x20)\r
+          //since Tekoa does not fully support IDE Bus Mastering\r
+          //\r
+          TempBaseAddress = 0x0;\r
+          Status = PciIo->Pci.Write (\r
+                                PciIo,\r
+                                EfiPciIoWidthUint32,\r
+                                0x20,\r
+                                1,\r
+                                     (VOID *) &TempBaseAddress\r
+                                );\r
+        }\r
+      }\r
+      break;\r
+\r
+    default:\r
+      break;\r
+  }\r
+  return;\r
+}\r
+\r
+VOID\r
+ProgramPciLatency(\r
+  IN    EFI_PCI_IO_PROTOCOL           *PciIo\r
+  )\r
+{\r
+  EFI_STATUS                          Status;\r
+\r
+  //\r
+  // Program Master Latency Timer\r
+  //\r
+  if (mSystemConfiguration.PciLatency != 0) {\r
+     Status = PciIo->Pci.Write (\r
+                           PciIo,\r
+                           EfiPciIoWidthUint8,\r
+                           PCI_LATENCY_TIMER_OFFSET,\r
+                           1,\r
+                           &mSystemConfiguration.PciLatency\r
+                           );\r
+  }\r
+  return;\r
+}\r
+\r
+/**\r
+During S5 shutdown, we need to program PME in all LAN devices.\r
+Here we identify LAN devices and save their bus/dev/func.\r
+\r
+**/\r
+VOID\r
+SavePciLanAddress(\r
+  IN EFI_PCI_IO_PROTOCOL    *PciIo\r
+  )\r
+{\r
+  EFI_STATUS        Status;\r
+  UINTN             PciSegment,\r
+                    PciBus,\r
+                    PciDevice,\r
+                    PciFunction;\r
+  VOID              *NewBuffer;\r
+  PCI_LAN_INFO      *x;\r
+\r
+  Status = PciIo->GetLocation (\r
+                    PciIo,\r
+                    &PciSegment,\r
+                    &PciBus,\r
+                    &PciDevice,\r
+                    &PciFunction\r
+                    );\r
+  if (EFI_ERROR (Status)) {\r
+    return;\r
+  }\r
+\r
+  mPciLanCount ++;\r
+  Status = gBS->AllocatePool (\r
+                  EfiBootServicesData,\r
+                  mPciLanCount * sizeof(PCI_LAN_INFO),\r
+                  &NewBuffer\r
+                  );\r
+  if (EFI_ERROR (Status)) {\r
+    return;\r
+  }\r
+\r
+  if (mPciLanCount > 1) {\r
+    //\r
+    // copy old data into new, larger buffer\r
+    //\r
+    gBS->CopyMem (\r
+           NewBuffer,\r
+           mPciLanInfo,\r
+           (mPciLanCount - 1) * sizeof(PCI_LAN_INFO)\r
+           );\r
+\r
+    //\r
+    // free the old memory buffer\r
+    //\r
+    gBS->FreePool (mPciLanInfo);\r
+\r
+  }\r
+\r
+  //\r
+  // init the new entry\r
+  //\r
+  x = (PCI_LAN_INFO *)NewBuffer + (mPciLanCount - 1);\r
+  x->PciBus = (UINT8)PciBus;\r
+  x->PciDevice = (UINT8)PciDevice;\r
+  x->PciFunction = (UINT8)PciFunction;\r
+\r
+  mPciLanInfo = NewBuffer;\r
+\r
+  return;\r
+}\r
+\r
+/**\r
+  @param  Event          the event that is signaled.\r
+  @param Context        not used here.\r
+\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+PciBusEvent (\r
+  IN EFI_EVENT    Event,\r
+  IN VOID*        Context\r
+  )\r
+{\r
+\r
+  EFI_STATUS                    Status;\r
+  UINTN                         BufferSize;\r
+  EFI_HANDLE                    Handle;\r
+  EFI_PCI_IO_PROTOCOL           *PciIo;\r
+  PCI_IO_DEVICE                 *PciIoDevice;\r
+  UINT64                        Supports;\r
+  UINTN                         Index;\r
+  UINT8                         mCacheLineSize = 0x10;\r
+\r
+  while (TRUE) {\r
+    BufferSize = sizeof (EFI_HANDLE);\r
+    Status = gBS->LocateHandle (\r
+                    ByRegisterNotify,\r
+                    NULL,\r
+                    mPciRegistration,\r
+                    &BufferSize,\r
+                    &Handle\r
+                    );\r
+    if (EFI_ERROR (Status)) {\r
+      //\r
+      // If no more notification events exist\r
+      //\r
+      return;\r
+    }\r
+\r
+    Status = gBS->HandleProtocol (\r
+                    Handle,\r
+                    &gEfiPciIoProtocolGuid,\r
+                    (void **)&PciIo\r
+                    );\r
+\r
+    PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (PciIo);\r
+\r
+    //\r
+    // Enable I/O for bridge so port 0x80 codes will come out\r
+    //\r
+    if (PciIoDevice->Pci.Hdr.VendorId == V_PCH_INTEL_VENDOR_ID)\r
+    {\r
+      Status = PciIo->Attributes(\r
+                        PciIo,\r
+                        EfiPciIoAttributeOperationSupported,\r
+                        0,\r
+                        &Supports\r
+                        );\r
+      Supports &= EFI_PCI_DEVICE_ENABLE;\r
+      Status = PciIo->Attributes (\r
+                        PciIo,\r
+                        EfiPciIoAttributeOperationEnable,\r
+                        Supports,\r
+                        NULL\r
+                        );\r
+      break;\r
+    }\r
+\r
+    //\r
+    // Program PCI Latency Timer\r
+    //\r
+    ProgramPciLatency(PciIo);\r
+\r
+    //\r
+    // Program Cache Line Size to 64 bytes (0x10 DWORDs)\r
+    //\r
+    Status = PciIo->Pci.Write (\r
+                          PciIo,\r
+                          EfiPciIoWidthUint8,\r
+                          PCI_CACHELINE_SIZE_OFFSET,\r
+                          1,\r
+                          &mCacheLineSize\r
+                          );\r
+\r
+    //\r
+    // If PCI LAN device, save bus/dev/func info\r
+    // so we can program PME during S5 shutdown\r
+    //\r
+    if (PciIoDevice->Pci.Hdr.ClassCode[2] == PCI_CLASS_NETWORK) {\r
+      SavePciLanAddress(PciIo);\r
+      break;\r
+    }\r
+\r
+    //\r
+    // Workaround for cards with bad BARs\r
+    //\r
+    Index = 0;\r
+    while (BadDeviceTable[Index].ClassCode != 0xff) {\r
+      if (BadDeviceTable[Index].DeviceId == 0xffff) {\r
+        if ((PciIoDevice->Pci.Hdr.ClassCode[2] == BadDeviceTable[Index].ClassCode) &&\r
+            (PciIoDevice->Pci.Hdr.ClassCode[1] == BadDeviceTable[Index].SubClassCode) &&\r
+            (PciIoDevice->Pci.Hdr.VendorId == BadDeviceTable[Index].VendorId)) {\r
+          InitBadBars(PciIo,BadDeviceTable[Index].VendorId,BadDeviceTable[Index].DeviceId);\r
+        }\r
+      } else {\r
+        if ((PciIoDevice->Pci.Hdr.ClassCode[2] == BadDeviceTable[Index].ClassCode) &&\r
+            (PciIoDevice->Pci.Hdr.ClassCode[1] == BadDeviceTable[Index].SubClassCode) &&\r
+            (PciIoDevice->Pci.Hdr.VendorId == BadDeviceTable[Index].VendorId) &&\r
+            (PciIoDevice->Pci.Hdr.DeviceId == BadDeviceTable[Index].DeviceId)) {\r
+\r
+          InitBadBars(PciIo,BadDeviceTable[Index].VendorId,BadDeviceTable[Index].DeviceId);\r
+        }\r
+      }\r
+      ++Index;\r
+    }\r
+      break;\r
+    }\r
+\r
+  return;\r
+}\r
+\r

diff --git a/Vlv2TbltDevicePkg/PlatformDxe/Platform.c b/Vlv2TbltDevicePkg/PlatformDxe/Platform.c
new file mode 100644 (file)
index 0000000..0f3a414
--- /dev/null
+++ b/Vlv2TbltDevicePkg/PlatformDxe/Platform.c
@@ -0,0 +1,1661 @@
+/** @file\r
+\r
+  Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+Module Name:\r
+\r
+\r
+  Platform.c\r
+\r
+Abstract:\r
+\r
+  Platform Initialization Driver.\r
+\r
+\r
+--*/\r
+\r
+#include "PlatformDxe.h"\r
+#include "Platform.h"\r
+#include "PchCommonDefinitions.h"\r
+#include <Protocol/UsbPolicy.h>\r
+#include <Protocol/PchPlatformPolicy.h>\r
+#include <Protocol/TpmMp.h>\r
+#include <Protocol/CpuIo2.h>\r
+#include <Library/S3BootScriptLib.h>\r
+#include <Guid/PciLanInfo.h>\r
+#include <Guid/ItkData.h>\r
+#include <Library/PciLib.h>\r
+#include <PlatformBootMode.h>\r
+#include <Guid/EventGroup.h>\r
+#include <Guid/Vlv2Variable.h>\r
+#include <Protocol/GlobalNvsArea.h>\r
+#include <Protocol/IgdOpRegion.h>\r
+#include <Library/PcdLib.h>\r
+\r
+//\r
+// VLV2 GPIO GROUP OFFSET\r
+//\r
+#define GPIO_SCORE_OFFSET      0x0000\r
+#define GPIO_NCORE_OFFSET      0x1000\r
+#define GPIO_SSUS_OFFSET       0x2000\r
+\r
+typedef struct {\r
+  UINT32 offset;\r
+  UINT32 val;\r
+} CFIO_PNP_INIT;\r
+\r
+GPIO_CONF_PAD_INIT mTB_BL_GpioInitData_SC_TRI_Exit_boot_Service[] =\r
+{\r
+//              Pad Name          GPIO Number     Used As   GPO Default  Function#     INT Capable   Interrupt Type   PULL H/L    MMIO Offset\r
+  GPIO_INIT_ITEM("LPC_CLKOUT0       GPIOC_47 "     ,TRISTS   ,NA           ,F0           ,             ,                ,NONE       ,0x47),\r
+  GPIO_INIT_ITEM("LPC_CLKOUT1       GPIOC_48 "     ,TRISTS   ,NA           ,F0           ,             ,                ,NONE       ,0x41),\r
+};\r
+\r
+\r
+EFI_GUID mSystemHiiExportDatabase = EFI_HII_EXPORT_DATABASE_GUID;\r
+EFI_GUID mPlatformDriverGuid = EFI_PLATFORM_DRIVER_GUID;\r
+SYSTEM_CONFIGURATION  mSystemConfiguration;\r
+SYSTEM_PASSWORDS      mSystemPassword;\r
+EFI_HANDLE            mImageHandle;\r
+BOOLEAN               mMfgMode = FALSE;\r
+VOID                  *mDxePlatformStringPack;\r
+UINT32                mPlatformBootMode = PLATFORM_NORMAL_MODE;\r
+extern CHAR16 gItkDataVarName[];\r
+\r
+\r
+EFI_PLATFORM_INFO_HOB      mPlatformInfo;\r
+EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *mPciRootBridgeIo;\r
+EFI_EVENT  mReadyToBootEvent;\r
+\r
+UINT8 mSmbusRsvdAddresses[] = PLATFORM_SMBUS_RSVD_ADDRESSES;\r
+UINT8 mNumberSmbusAddress = sizeof( mSmbusRsvdAddresses ) / sizeof( mSmbusRsvdAddresses[0] );\r
+UINT32 mSubsystemVidDid;\r
+UINT32 mSubsystemAudioVidDid;\r
+\r
+UINTN   mPciLanCount = 0;\r
+VOID    *mPciLanInfo = NULL;\r
+UINTN   SpiBase;\r
+\r
+static EFI_SPEAKER_IF_PROTOCOL mSpeakerInterface = {\r
+  ProgramToneFrequency,\r
+  GenerateBeepTone\r
+};\r
+\r
+EFI_USB_POLICY_PROTOCOL         mUsbPolicyData = {0};\r
+\r
+\r
+CFIO_PNP_INIT mTB_BL_GpioInitData_SC_TRI_S0ix_Exit_boot_Service[] =\r
+{\r
+  {0x410 ,0x20038e10},  //vlv.gpio.gpscore.cfio_regs_pad_lpc_clkout1_pconf0\r
+  {0x470 ,0x20038e10},  //vlv.gpio.gpscore.cfio_regs_pad_lpc_clkout0_pconf0\r
+  {0x560 ,0x20038e10},  //vlv.gpio.gpscore.cfio_regs_pad_ilb_serirq_pconf0\r
+  {0x450 ,0x20038e10},  //vlv.gpio.gpscore.cfio_regs_pad_lpc_frameb_pconf0\r
+  {0x480 ,0x20038e10},  //vlv.gpio.gpscore.cfio_regs_pad_lpc_clkrunb_pconf0\r
+  {0x420 ,0x20038e10},  //vlv.gpio.gpscore.cfio_regs_pad_lpc_ad3_pconf0\r
+  {0x430 ,0x20038e10},  //vlv.gpio.gpscore.cfio_regs_pad_lpc_ad2_pconf0\r
+  {0x440 ,0x20038e10},  //vlv.gpio.gpscore.cfio_regs_pad_lpc_ad1_pconf0\r
+  {0x460 ,0x20038e10},  //vlv.gpio.gpscore.cfio_regs_pad_lpc_ad0_pconf0\r
+  {0x418 ,0x00000006},  //vlv.gpio.gpscore.cfio_regs_pad_lpc_clkout1_pad_val\r
+  {0x478 ,0x00000006},  //vlv.gpio.gpscore.cfio_regs_pad_lpc_clkout0_pad_val\r
+  {0x568 ,0x00000006},  //vlv.gpio.gpscore.cfio_regs_pad_ilb_serirq_pad_val\r
+  {0x458 ,0x00000006},  //vlv.gpio.gpscore.cfio_regs_pad_lpc_frameb_pad_val\r
+  {0x488 ,0x00000006},  //vlv.gpio.gpscore.cfio_regs_pad_lpc_clkrunb_pad_val\r
+  {0x428 ,0x00000006},  //vlv.gpio.gpscore.cfio_regs_pad_lpc_ad3_pad_val\r
+  {0x438 ,0x00000006},  //vlv.gpio.gpscore.cfio_regs_pad_lpc_ad2_pad_val\r
+  {0x448 ,0x00000006},  //vlv.gpio.gpscore.cfio_regs_pad_lpc_ad1_pad_val\r
+  {0x468 ,0x00000006},  //vlv.gpio.gpscore.cfio_regs_pad_lpc_ad0_pad_val\r
+};\r
+\r
+VOID\r
+EfiOrMem (\r
+  IN VOID   *Destination,\r
+  IN VOID   *Source,\r
+  IN UINTN  Length\r
+  );\r
+\r
+#if defined(FIRMWARE_ID_BACKWARD_COMPATIBLE) && (FIRMWARE_ID_BACKWARD_COMPATIBLE != 0)\r
+STATIC\r
+VOID\r
+InitFirmwareId();\r
+#endif\r
+\r
+\r
+VOID\r
+InitializeClockRouting(\r
+  );\r
+\r
+VOID\r
+InitializeSlotInfo (\r
+  );\r
+\r
+#if defined(SENSOR_INFO_VAR_SUPPORT) && SENSOR_INFO_VAR_SUPPORT != 0\r
+VOID\r
+InitializeSensorInfoVariable (\r
+  );\r
+#endif\r
+\r
+VOID\r
+InitTcoReset (\r
+  );\r
+\r
+VOID\r
+InitExI ();\r
+\r
+VOID\r
+InitItk();\r
+\r
+VOID\r
+InitPlatformBootMode();\r
+\r
+VOID\r
+InitMfgAndConfigModeStateVar();\r
+\r
+VOID\r
+InitPchPlatformPolicy (\r
+  IN EFI_PLATFORM_INFO_HOB      *PlatformInfo\r
+  );\r
+\r
+VOID\r
+InitVlvPlatformPolicy (\r
+  );\r
+\r
+VOID\r
+InitSioPlatformPolicy(\r
+  );\r
+\r
+VOID\r
+PchInitBeforeBoot(\r
+  );\r
+\r
+VOID\r
+UpdateDVMTSetup(\r
+  );\r
+\r
+VOID\r
+InitPlatformUsbPolicy (\r
+  VOID\r
+  );\r
+\r
+VOID\r
+InitRC6Policy(\r
+  VOID\r
+  );\r
+\r
+\r
+VOID\r
+TristateLpcGpioConfig (\r
+  IN UINT32             Gpio_Mmio_Offset,\r
+  IN UINT32             Gpio_Pin_Num,\r
+  GPIO_CONF_PAD_INIT*   Gpio_Conf_Data\r
+  )\r
+\r
+{\r
+  UINT32    index;\r
+  UINT32    mmio_conf0;\r
+  UINT32    mmio_padval;\r
+  PAD_CONF0 conf0_val;\r
+  PAD_VAL   pad_val;\r
+\r
+  //\r
+  // GPIO WELL -- Memory base registers\r
+  //\r
+\r
+  //\r
+  // A0 BIOS Spec doesn't mention it although X0 does. comment out now.\r
+  // GPIO write 0x01001002 to IOBASE + Gpio_Mmio_Offset + 0x0900\r
+  //\r
+\r
+  for(index=0; index < Gpio_Pin_Num; index++)\r
+  {\r
+    //\r
+    // Calculate the MMIO Address for specific GPIO pin CONF0 register pointed by index.\r
+    //\r
+    mmio_conf0 = IO_BASE_ADDRESS + Gpio_Mmio_Offset + R_PCH_CFIO_PAD_CONF0 + Gpio_Conf_Data[index].offset * 16;\r
+    mmio_padval= IO_BASE_ADDRESS + Gpio_Mmio_Offset + R_PCH_CFIO_PAD_VAL   + Gpio_Conf_Data[index].offset * 16;\r
+\r
+#ifdef EFI_DEBUG\r
+    DEBUG ((EFI_D_INFO, "%s, ", Gpio_Conf_Data[index].pad_name));\r
+\r
+#endif\r
+    DEBUG ((EFI_D_INFO, "Usage = %d, Func# = %d, IntType = %d, Pull Up/Down = %d, MMIO Base = 0x%08x, ",\r
+      Gpio_Conf_Data[index].usage,\r
+      Gpio_Conf_Data[index].func,\r
+      Gpio_Conf_Data[index].int_type,\r
+      Gpio_Conf_Data[index].pull,\r
+      mmio_conf0));\r
+\r
+    //\r
+    // Step 1: PadVal Programming\r
+    //\r
+    pad_val.dw = MmioRead32(mmio_padval);\r
+\r
+    //\r
+    // Config PAD_VAL only for GPIO (Non-Native) Pin\r
+    //\r
+    if(Native != Gpio_Conf_Data[index].usage)\r
+    {\r
+      pad_val.dw &= ~0x6; // Clear bits 1:2\r
+      pad_val.dw |= (Gpio_Conf_Data[index].usage & 0x6);  // Set bits 1:2 according to PadVal\r
+\r
+        //\r
+        // set GPO default value\r
+        //\r
+        if(Gpio_Conf_Data[index].usage == GPO && Gpio_Conf_Data[index].gpod4 != NA)\r
+        {\r
+        pad_val.r.pad_val = Gpio_Conf_Data[index].gpod4;\r
+        }\r
+    }\r
+\r
+\r
+    DEBUG ((EFI_D_INFO, "Set PAD_VAL = 0x%08x, ", pad_val.dw));\r
+\r
+    MmioWrite32(mmio_padval, pad_val.dw);\r
+\r
+    //\r
+    // Step 2: CONF0 Programming\r
+    // Read GPIO default CONF0 value, which is assumed to be default value after reset.\r
+    //\r
+    conf0_val.dw = MmioRead32(mmio_conf0);\r
+\r
+    //\r
+    // Set Function #\r
+    //\r
+    conf0_val.r.Func_Pin_Mux = Gpio_Conf_Data[index].func;\r
+\r
+    if(GPO == Gpio_Conf_Data[index].usage)\r
+    {\r
+      //\r
+      // If used as GPO, then internal pull need to be disabled\r
+      //\r
+      conf0_val.r.Pull_assign = 0;  // Non-pull\r
+    }\r
+    else\r
+    {\r
+      //\r
+      // Set PullUp / PullDown\r
+      //\r
+      if(P_20K_H == Gpio_Conf_Data[index].pull)\r
+      {\r
+        conf0_val.r.Pull_assign = 0x1;  // PullUp\r
+        conf0_val.r.Pull_strength = 0x2;// 20K\r
+      }\r
+      else if(P_20K_L == Gpio_Conf_Data[index].pull)\r
+      {\r
+        conf0_val.r.Pull_assign = 0x2;  // PullDown\r
+        conf0_val.r.Pull_strength = 0x2;// 20K\r
+      }\r
+      else if(P_NONE == Gpio_Conf_Data[index].pull)\r
+      {\r
+        conf0_val.r.Pull_assign = 0;   // Non-pull\r
+      }\r
+      else\r
+      {\r
+        ASSERT(FALSE);  // Invalid value\r
+      }\r
+    }\r
+\r
+    //\r
+    // Set INT Trigger Type\r
+    //\r
+    conf0_val.dw &= ~0x0f000000;  // Clear bits 27:24\r
+\r
+    //\r
+    // Set INT Trigger Type\r
+    //\r
+    if(TRIG_ == Gpio_Conf_Data[index].int_type)\r
+    {\r
+      //\r
+      // Interrupt not capable, clear bits 27:24\r
+      //\r
+    }\r
+    else\r
+    {\r
+      conf0_val.dw |= (Gpio_Conf_Data[index].int_type & 0x0f)<<24;\r
+    }\r
+\r
+    DEBUG ((EFI_D_INFO, "Set CONF0 = 0x%08x\n", conf0_val.dw));\r
+\r
+    //\r
+    // Write back the targeted GPIO config value according to platform (board) GPIO setting\r
+    //\r
+    MmioWrite32 (mmio_conf0, conf0_val.dw);\r
+  }\r
+\r
+  // A0 BIOS Spec doesn't mention it although X0 does. comment out now.\r
+  // GPIO SCORE write 0x01001002 to IOBASE + 0x0900\r
+  //\r
+}\r
+\r
+VOID\r
+EFIAPI\r
+SpiBiosProtectionFunction(\r
+  EFI_EVENT Event,\r
+  VOID      *Context\r
+  )\r
+{\r
+\r
+  UINTN                             mPciD31F0RegBase;\r
+  UINTN                             BiosFlaLower = 0;\r
+  UINTN                             BiosFlaLimit = 0x7fffff;\r
+\r
+  BiosFlaLower = PcdGet32(PcdFlashMicroCodeAddress)-PcdGet32(PcdFlashAreaBaseAddress);\r
+\r
+\r
+  mPciD31F0RegBase = MmPciAddress (0,\r
+                         DEFAULT_PCI_BUS_NUMBER_PCH,\r
+                         PCI_DEVICE_NUMBER_PCH_LPC,\r
+                         PCI_FUNCTION_NUMBER_PCH_LPC,\r
+                         0\r
+                       );\r
+  SpiBase          = MmioRead32(mPciD31F0RegBase + R_PCH_LPC_SPI_BASE) & B_PCH_LPC_SPI_BASE_BAR;\r
+\r
+  //\r
+  //Set SMM_BWP, WPD and LE bit\r
+  //\r
+  MmioOr32 ((UINTN) (SpiBase + R_PCH_SPI_BCR), (UINT8) B_PCH_SPI_BCR_SMM_BWP);\r
+  MmioAnd32 ((UINTN) (SpiBase + R_PCH_SPI_BCR), (UINT8)(~B_PCH_SPI_BCR_BIOSWE));\r
+  MmioOr32 ((UINTN) (SpiBase + R_PCH_SPI_BCR), (UINT8) B_PCH_SPI_BCR_BLE);\r
+\r
+  //\r
+  //First check if FLOCKDN or PR0FLOCKDN is set. No action if either of them set already.\r
+  //\r
+  if( (MmioRead16(SpiBase + R_PCH_SPI_HSFS) & B_PCH_SPI_HSFS_FLOCKDN) != 0 ||\r
+      (MmioRead32(SpiBase + R_PCH_SPI_IND_LOCK)& B_PCH_SPI_IND_LOCK_PR0) != 0) {\r
+    //\r
+    //Already locked. we could take no action here\r
+    //\r
+    DEBUG((EFI_D_INFO, "PR0 already locked down. Stop configuring PR0.\n"));\r
+    return;\r
+  }\r
+\r
+  //\r
+  //Set PR0\r
+  //\r
+  MmioOr32((UINTN)(SpiBase + R_PCH_SPI_PR0),\r
+    B_PCH_SPI_PR0_RPE|B_PCH_SPI_PR0_WPE|\\r
+    (B_PCH_SPI_PR0_PRB_MASK&(BiosFlaLower>>12))|(B_PCH_SPI_PR0_PRL_MASK&(BiosFlaLimit>>12)<<16));\r
+\r
+  //\r
+  //Lock down PR0\r
+  //\r
+  MmioOr16 ((UINTN) (SpiBase + R_PCH_SPI_HSFS), (UINT16) (B_PCH_SPI_HSFS_FLOCKDN));\r
+\r
+  //\r
+  // Verify if it's really locked.\r
+  //\r
+  if ((MmioRead16 (SpiBase + R_PCH_SPI_HSFS) & B_PCH_SPI_HSFS_FLOCKDN) == 0) {\r
+    DEBUG((EFI_D_ERROR, "Failed to lock down PR0.\n"));\r
+  }\r
+\r
+  return;\r
+\r
+}\r
+\r
+VOID\r
+EFIAPI\r
+InitPciDevPME (\r
+  EFI_EVENT  Event,\r
+  VOID       *Context\r
+  )\r
+{\r
+  UINTN                  VarSize;\r
+  EFI_STATUS             Status;\r
+\r
+  VarSize = sizeof(SYSTEM_CONFIGURATION);\r
+  Status = gRT->GetVariable(\r
+                  NORMAL_SETUP_NAME,\r
+                  &gEfiNormalSetupGuid,\r
+                  NULL,\r
+                  &VarSize,\r
+                  &mSystemConfiguration\r
+                  );\r
+\r
+  //\r
+  //Program HDA PME_EN\r
+  //\r
+  PchAzaliaPciCfg32Or (R_PCH_HDA_PCS, B_PCH_HDA_PCS_PMEE);\r
+\r
+  //\r
+  //Program SATA PME_EN\r
+  //\r
+  PchSataPciCfg32Or (R_PCH_SATA_PMCS, B_PCH_SATA_PMCS_PMEE);\r
+\r
+  DEBUG ((EFI_D_INFO, "InitPciDevPME mSystemConfiguration.EhciPllCfgEnable = 0x%x \n",mSystemConfiguration.EhciPllCfgEnable));\r
+ if (mSystemConfiguration.EhciPllCfgEnable != 1) {\r
+  //\r
+  //Program EHCI PME_EN\r
+  //\r
+  PchMmPci32Or (\r
+    0,\r
+    0,\r
+    PCI_DEVICE_NUMBER_PCH_USB,\r
+    PCI_FUNCTION_NUMBER_PCH_EHCI,\r
+    R_PCH_EHCI_PWR_CNTL_STS,\r
+    B_PCH_EHCI_PWR_CNTL_STS_PME_EN\r
+    );\r
+ }\r
+   {\r
+     UINTN                 EhciPciMmBase;\r
+     UINT32                Buffer32 = 0;\r
+\r
+    EhciPciMmBase = MmPciAddress (0,\r
+                      0,\r
+                      PCI_DEVICE_NUMBER_PCH_USB,\r
+                      PCI_FUNCTION_NUMBER_PCH_EHCI,\r
+                      0\r
+                    );\r
+    DEBUG ((EFI_D_INFO, "ConfigureAdditionalPm() EhciPciMmBase = 0x%x \n",EhciPciMmBase));\r
+    Buffer32 = MmioRead32(EhciPciMmBase + R_PCH_EHCI_PWR_CNTL_STS);\r
+    DEBUG ((EFI_D_INFO, "ConfigureAdditionalPm() R_PCH_EHCI_PWR_CNTL_STS = 0x%x \n",Buffer32));\r
+  }\r
+}\r
+\r
+#if defined SUPPORT_LVDS_DISPLAY && SUPPORT_LVDS_DISPLAY\r
+\r
+#endif\r
+\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+TristateLpcGpioS0i3Config (\r
+  UINT32             Gpio_Mmio_Offset,\r
+  UINT32             Gpio_Pin_Num,\r
+  CFIO_PNP_INIT*   Gpio_Conf_Data\r
+  )\r
+{\r
+\r
+  UINT32         index;\r
+  UINT32         mmio_reg;\r
+  UINT32         mmio_val;\r
+\r
+    DEBUG ((DEBUG_INFO, "TristateLpcGpioS0i3Config\n"));\r
+\r
+    for(index=0; index < Gpio_Pin_Num; index++)\r
+    {\r
+      mmio_reg = IO_BASE_ADDRESS + Gpio_Mmio_Offset + Gpio_Conf_Data[index].offset;\r
+\r
+      MmioWrite32(mmio_reg, Gpio_Conf_Data[index].val);\r
+      mmio_val = 0;\r
+      mmio_val = MmioRead32(mmio_reg);\r
+\r
+      DEBUG ((EFI_D_INFO, "Set MMIO=0x%08x  PAD_VAL = 0x%08x,\n", mmio_reg, mmio_val));\r
+    }\r
+\r
+     return EFI_SUCCESS;\r
+}\r
+\r
+\r
+EFI_BOOT_SCRIPT_SAVE_PROTOCOL *mBootScriptSave;\r
+\r
+/**\r
+  Event Notification during exit boot service to enabel ACPI mode\r
+\r
+   Disable SW SMI Timer, SMI from USB & Intel Specific USB 2\r
+\r
+   Clear all ACPI event status and disable all ACPI events\r
+   Disable PM sources except power button\r
+   Clear status bits\r
+\r
+   Guarantee day-of-month alarm is invalid (ACPI 5.0 Section 4.8.2.4 "Real Time Clock Alarm")\r
+\r
+   Update EC to disable SMI and enable SCI\r
+\r
+   Enable SCI\r
+\r
+   Enable PME_B0_EN in GPE0a_EN\r
+\r
+  @param Event  - EFI Event Handle\r
+  @param Context - Pointer to Notify Context\r
+\r
+  @retval  Nothing\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+EnableAcpiCallback (\r
+  IN EFI_EVENT        Event,\r
+  IN VOID             *Context\r
+  )\r
+{\r
+  UINT32  RegData32;\r
+  UINT16  Pm1Cnt;\r
+  UINT16  AcpiBase;\r
+  UINT32  Gpe0aEn;\r
+\r
+  AcpiBase = MmioRead16 (\r
+               PchPciDeviceMmBase (DEFAULT_PCI_BUS_NUMBER_PCH,\r
+               PCI_DEVICE_NUMBER_PCH_LPC,\r
+               PCI_FUNCTION_NUMBER_PCH_LPC) + R_PCH_LPC_ACPI_BASE\r
+               ) & B_PCH_LPC_ACPI_BASE_BAR;\r
+\r
+  DEBUG ((EFI_D_INFO, "EnableAcpiCallback: AcpiBase = %x\n", AcpiBase));\r
+\r
+  //\r
+  // Disable SW SMI Timer, SMI from USB & Intel Specific USB 2\r
+  //\r
+  RegData32 = IoRead32(AcpiBase + R_PCH_SMI_EN);\r
+  RegData32 &= ~(B_PCH_SMI_EN_SWSMI_TMR | B_PCH_SMI_EN_LEGACY_USB2 | B_PCH_SMI_EN_INTEL_USB2);\r
+  IoWrite32(AcpiBase + R_PCH_SMI_EN, RegData32);\r
+\r
+  RegData32 = IoRead32(AcpiBase + R_PCH_SMI_STS);\r
+  RegData32 |= B_PCH_SMI_STS_SWSMI_TMR;\r
+  IoWrite32(AcpiBase + R_PCH_SMI_STS, RegData32);\r
+\r
+  //\r
+  // Disable PM sources except power button\r
+  // power button is enabled only for PCAT. Disabled it on Tablet platform\r
+  //\r
+\r
+  IoWrite16(AcpiBase + R_PCH_ACPI_PM1_EN, B_PCH_ACPI_PM1_EN_PWRBTN);\r
+  IoWrite16(AcpiBase + R_PCH_ACPI_PM1_STS, 0xffff);\r
+\r
+  //\r
+  // Guarantee day-of-month alarm is invalid (ACPI 5.0 Section 4.8.2.4 "Real Time Clock Alarm")\r
+  // Clear Status D reg VM bit, Date of month Alarm to make Data in CMOS RAM is no longer Valid\r
+  //\r
+  IoWrite8 (PCAT_RTC_ADDRESS_REGISTER, RTC_ADDRESS_REGISTER_D);\r
+  IoWrite8 (PCAT_RTC_DATA_REGISTER, 0x0);\r
+\r
+  RegData32 = IoRead32(AcpiBase + R_PCH_ALT_GP_SMI_EN);\r
+  RegData32 &= ~(BIT7);\r
+  IoWrite32((AcpiBase + R_PCH_ALT_GP_SMI_EN), RegData32);\r
+\r
+  //\r
+  // Enable SCI\r
+  //\r
+  Pm1Cnt = IoRead16(AcpiBase + R_PCH_ACPI_PM1_CNT);\r
+  Pm1Cnt |= B_PCH_ACPI_PM1_CNT_SCI_EN;\r
+  IoWrite16(AcpiBase + R_PCH_ACPI_PM1_CNT, Pm1Cnt);\r
+\r
+  IoWrite8(0x80, 0xA0);        //SW_SMI_ACPI_ENABLE\r
+\r
+  //\r
+  // Enable PME_B0_EN in GPE0a_EN\r
+  // Caution: Enable PME_B0_EN must be placed after enabling SCI.\r
+  // Otherwise, USB PME could not be handled as SMI event since no handler is there.\r
+  //\r
+  Gpe0aEn = IoRead32 (AcpiBase + R_PCH_ACPI_GPE0a_EN);\r
+  Gpe0aEn |= B_PCH_ACPI_GPE0a_EN_PME_B0;\r
+  IoWrite32(AcpiBase + R_PCH_ACPI_GPE0a_EN, Gpe0aEn);\r
+\r
+}\r
+\r
+/**\r
+\r
+  Routine Description:\r
+\r
+  This is the standard EFI driver point for the Driver. This\r
+  driver is responsible for setting up any platform specific policy or\r
+  initialization information.\r
+\r
+  @param ImageHandle    Handle for the image of this driver.\r
+  @param SystemTable    Pointer to the EFI System Table.\r
+\r
+  @retval EFI_SUCCESS   Policy decisions set.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+InitializePlatform (\r
+  IN EFI_HANDLE         ImageHandle,\r
+  IN EFI_SYSTEM_TABLE   *SystemTable\r
+  )\r
+{\r
+  EFI_STATUS                          Status;\r
+  UINTN                               VarSize;\r
+  EFI_HANDLE                          Handle = NULL;\r
+\r
+  EFI_EVENT                           mEfiExitBootServicesEvent;\r
+\r
+  //\r
+mImageHandle = ImageHandle;\r
+\r
+  Status = gBS->InstallProtocolInterface (\r
+                  &Handle,\r
+                  &gEfiSpeakerInterfaceProtocolGuid,\r
+                  EFI_NATIVE_INTERFACE,\r
+                  &mSpeakerInterface\r
+                  );\r
+\r
+  Status = gBS->LocateProtocol (\r
+                  &gEfiPciRootBridgeIoProtocolGuid,\r
+                  NULL,\r
+                  (VOID **) &mPciRootBridgeIo\r
+                  );\r
+  ASSERT_EFI_ERROR (Status);\r
+\r
+  VarSize = sizeof(EFI_PLATFORM_INFO_HOB);\r
+  Status = gRT->GetVariable(\r
+                  L"PlatformInfo",\r
+                  &gEfiVlv2VariableGuid,\r
+                  NULL,\r
+                  &VarSize,\r
+                  &mPlatformInfo\r
+                  );\r
+\r
+  //\r
+  // Initialize Product Board ID variable\r
+  //\r
+  InitMfgAndConfigModeStateVar();\r
+  InitPlatformBootMode();\r
+\r
+  //\r
+  // Install Observable protocol\r
+  //\r
+  InitializeObservableProtocol();\r
+\r
+\r
+  VarSize = sizeof(SYSTEM_CONFIGURATION);\r
+  Status = gRT->GetVariable(\r
+                  NORMAL_SETUP_NAME,\r
+                  &gEfiNormalSetupGuid,\r
+                  NULL,\r
+                  &VarSize,\r
+                  &mSystemConfiguration\r
+                  );\r
+\r
+\r
+  Status = EfiCreateEventReadyToBootEx (\r
+             TPL_CALLBACK,\r
+             ReadyToBootFunction,\r
+             NULL,\r
+             &mReadyToBootEvent\r
+             );\r
+\r
+  //\r
+  // Create a ReadyToBoot Event to run the PME init process\r
+  //\r
+  Status = EfiCreateEventReadyToBootEx (\r
+             TPL_CALLBACK,\r
+             InitPciDevPME,\r
+             NULL,\r
+             &mReadyToBootEvent\r
+             );\r
+  //\r
+  // Create a ReadyToBoot Event to run enable PR0 and lock down\r
+  //\r
+  if(mSystemConfiguration.SpiRwProtect==1) {\r
+    Status = EfiCreateEventReadyToBootEx (\r
+               TPL_CALLBACK,\r
+               SpiBiosProtectionFunction,\r
+               NULL,\r
+               &mReadyToBootEvent\r
+               );\r
+  }\r
+\r
+  ReportStatusCodeEx (\r
+    EFI_PROGRESS_CODE,\r
+    EFI_COMPUTING_UNIT_CHIPSET | EFI_CU_PLATFORM_DXE_STEP1,\r
+    0,\r
+    &gEfiCallerIdGuid,\r
+    NULL,\r
+    NULL,\r
+    0\r
+    );\r
+\r
+#if defined(SENSOR_INFO_VAR_SUPPORT) && SENSOR_INFO_VAR_SUPPORT != 0\r
+  //\r
+  // Initialize Sensor Info variable\r
+  //\r
+  InitializeSensorInfoVariable();\r
+#endif\r
+  InitPchPlatformPolicy(&mPlatformInfo);\r
+  InitVlvPlatformPolicy();\r
+\r
+  //\r
+  //  Add usb policy\r
+  //\r
+  InitPlatformUsbPolicy();\r
+  InitSioPlatformPolicy();\r
+  InitializeClockRouting();\r
+  InitializeSlotInfo();\r
+  InitTcoReset();\r
+\r
+  //\r
+  //Init ExI\r
+  //\r
+  InitExI();\r
+\r
+  ReportStatusCodeEx (\r
+    EFI_PROGRESS_CODE,\r
+    EFI_COMPUTING_UNIT_CHIPSET | EFI_CU_PLATFORM_DXE_STEP2,\r
+    0,\r
+    &gEfiCallerIdGuid,\r
+    NULL,\r
+    NULL,\r
+    0\r
+    );\r
+\r
+  //\r
+  // Install PCI Bus Driver Hook\r
+  //\r
+  PciBusDriverHook();\r
+\r
+  InitItk();\r
+\r
+  ReportStatusCodeEx (\r
+    EFI_PROGRESS_CODE,\r
+    EFI_COMPUTING_UNIT_CHIPSET | EFI_CU_PLATFORM_DXE_STEP3,\r
+    0,\r
+    &gEfiCallerIdGuid,\r
+    NULL,\r
+    NULL,\r
+    0\r
+    );\r
+\r
+\r
+  //\r
+  // Initialize Password States and Callbacks\r
+  //\r
+  PchInitBeforeBoot();\r
+\r
+#if defined SUPPORT_LVDS_DISPLAY && SUPPORT_LVDS_DISPLAY\r
+\r
+#endif\r
+\r
+#if defined(FIRMWARE_ID_BACKWARD_COMPATIBLE) && (FIRMWARE_ID_BACKWARD_COMPATIBLE != 0)\r
+  //\r
+  // Re-write Firmware ID if it is changed\r
+  //\r
+  InitFirmwareId();\r
+#endif\r
+\r
+  ReportStatusCodeEx (\r
+    EFI_PROGRESS_CODE,\r
+    EFI_COMPUTING_UNIT_CHIPSET | EFI_CU_PLATFORM_DXE_STEP4,\r
+    0,\r
+    &gEfiCallerIdGuid,\r
+    NULL,\r
+    NULL,\r
+    0\r
+    );\r
+\r
+\r
+  Status = gBS->CreateEventEx (\r
+                  EVT_NOTIFY_SIGNAL,\r
+                  TPL_NOTIFY,\r
+                  EnableAcpiCallback,\r
+                  NULL,\r
+                  &gEfiEventExitBootServicesGuid,\r
+                  &mEfiExitBootServicesEvent\r
+                  );\r
+\r
+\r
+//\r
+// Tristae Lpc pins at last moment\r
+//\r
+if (mSystemConfiguration.TristateLpc == 1)\r
+{\r
+}\r
+\r
+  return EFI_SUCCESS;\r
+}\r
+\r
+/**\r
+  Source Or Destination with Length bytes.\r
+\r
+  @param[in] Destination   Target memory\r
+  @param[in] Source        Source memory\r
+  @param[in] Length        Number of bytes\r
+\r
+  @retval None\r
+\r
+**/\r
+VOID\r
+EfiOrMem (\r
+  IN VOID   *Destination,\r
+  IN VOID   *Source,\r
+  IN UINTN  Length\r
+  )\r
+{\r
+  CHAR8 *Destination8;\r
+  CHAR8 *Source8;\r
+\r
+  if (Source < Destination) {\r
+    Destination8  = (CHAR8 *) Destination + Length - 1;\r
+    Source8       = (CHAR8 *) Source + Length - 1;\r
+    while (Length--) {\r
+      *(Destination8--) |= *(Source8--);\r
+    }\r
+  } else {\r
+    Destination8  = (CHAR8 *) Destination;\r
+    Source8       = (CHAR8 *) Source;\r
+    while (Length--) {\r
+      *(Destination8++) |= *(Source8++);\r
+    }\r
+  }\r
+}\r
+\r
+VOID\r
+PchInitBeforeBoot()\r
+{\r
+  //\r
+  // Saved SPI Opcode menu to fix EFI variable unable to write after S3 resume.\r
+  //\r
+  S3BootScriptSaveMemWrite (\r
+                         EfiBootScriptWidthUint32,\r
+                         (UINTN)(SPI_BASE_ADDRESS + (R_PCH_SPI_OPMENU0)),\r
+                         1,\r
+                         (VOID *)(UINTN)(SPI_BASE_ADDRESS + (R_PCH_SPI_OPMENU0)));\r
+\r
+  S3BootScriptSaveMemWrite (\r
+                         EfiBootScriptWidthUint32,\r
+                         (UINTN)(SPI_BASE_ADDRESS + (R_PCH_SPI_OPMENU1)),\r
+                         1,\r
+                         (VOID *)(UINTN)(SPI_BASE_ADDRESS + (R_PCH_SPI_OPMENU1)));\r
+\r
+  S3BootScriptSaveMemWrite (\r
+                         EfiBootScriptWidthUint16,\r
+                         (UINTN)(SPI_BASE_ADDRESS + R_PCH_SPI_OPTYPE),\r
+                         1,\r
+                         (VOID *)(UINTN)(SPI_BASE_ADDRESS + R_PCH_SPI_OPTYPE));\r
+\r
+  S3BootScriptSaveMemWrite (\r
+                         EfiBootScriptWidthUint16,\r
+                         (UINTN)(SPI_BASE_ADDRESS + R_PCH_SPI_PREOP),\r
+                         1,\r
+                         (VOID *)(UINTN)(SPI_BASE_ADDRESS + R_PCH_SPI_PREOP));\r
+\r
+  //\r
+  // Saved MTPMC_1 for S3 resume.\r
+  //\r
+  S3BootScriptSaveMemWrite (\r
+                         EfiBootScriptWidthUint32,\r
+                         (UINTN)(PMC_BASE_ADDRESS + R_PCH_PMC_MTPMC1),\r
+                         1,\r
+                         (VOID *)(UINTN)(PMC_BASE_ADDRESS + R_PCH_PMC_MTPMC1));\r
+  return;\r
+}\r
+\r
+VOID\r
+EFIAPI\r
+ReadyToBootFunction (\r
+  EFI_EVENT  Event,\r
+  VOID       *Context\r
+  )\r
+{\r
+  EFI_STATUS                      Status;\r
+  EFI_ISA_ACPI_PROTOCOL           *IsaAcpi;\r
+  EFI_ISA_ACPI_DEVICE_ID          IsaDevice;\r
+  UINTN                           Size;\r
+  UINT16                          State;\r
+  EFI_TPM_MP_DRIVER_PROTOCOL      *TpmMpDriver;\r
+  EFI_CPU_IO_PROTOCOL             *CpuIo;\r
+  UINT8                           Data;\r
+  UINT8                           ReceiveBuffer [64];\r
+  UINT32                          ReceiveBufferSize;\r
+\r
+  UINT8 TpmForceClearCommand [] =              {0x00, 0xC1,\r
+                                                0x00, 0x00, 0x00, 0x0A,\r
+                                                0x00, 0x00, 0x00, 0x5D};\r
+  UINT8 TpmPhysicalPresenceCommand [] =        {0x00, 0xC1,\r
+                                                0x00, 0x00, 0x00, 0x0C,\r
+                                                0x40, 0x00, 0x00, 0x0A,\r
+                                                0x00, 0x00};\r
+  UINT8 TpmPhysicalDisableCommand [] =         {0x00, 0xC1,\r
+                                                0x00, 0x00, 0x00, 0x0A,\r
+                                                0x00, 0x00, 0x00, 0x70};\r
+  UINT8 TpmPhysicalEnableCommand [] =          {0x00, 0xC1,\r
+                                                0x00, 0x00, 0x00, 0x0A,\r
+                                                0x00, 0x00, 0x00, 0x6F};\r
+  UINT8 TpmPhysicalSetDeactivatedCommand [] =  {0x00, 0xC1,\r
+                                                0x00, 0x00, 0x00, 0x0B,\r
+                                                0x00, 0x00, 0x00, 0x72,\r
+                                                0x00};\r
+  UINT8 TpmSetOwnerInstallCommand [] =         {0x00, 0xC1,\r
+                                                0x00, 0x00, 0x00, 0x0B,\r
+                                                0x00, 0x00, 0x00, 0x71,\r
+                                                0x00};\r
+\r
+  Size = sizeof(UINT16);\r
+  Status = gRT->GetVariable (\r
+                  VAR_EQ_FLOPPY_MODE_DECIMAL_NAME,\r
+                  &gEfiNormalSetupGuid,\r
+                  NULL,\r
+                  &Size,\r
+                  &State\r
+                  );\r
+\r
+  //\r
+  // Disable Floppy Controller if needed\r
+  //\r
+  Status = gBS->LocateProtocol (&gEfiIsaAcpiProtocolGuid, NULL, (VOID **) &IsaAcpi);\r
+  if (!EFI_ERROR(Status) && (State == 0x00)) {\r
+    IsaDevice.HID = EISA_PNP_ID(0x604);\r
+    IsaDevice.UID = 0;\r
+    Status = IsaAcpi->EnableDevice(IsaAcpi, &IsaDevice, FALSE);\r
+  }\r
+\r
+  //\r
+  // save LAN info to a variable\r
+  //\r
+  if (NULL != mPciLanInfo) {\r
+    gRT->SetVariable (\r
+           L"PciLanInfo",\r
+           &gEfiPciLanInfoGuid,\r
+           EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS,\r
+           mPciLanCount * sizeof(PCI_LAN_INFO),\r
+           mPciLanInfo\r
+           );\r
+  }\r
+\r
+  if (NULL != mPciLanInfo) {\r
+    gBS->FreePool (mPciLanInfo);\r
+    mPciLanInfo = NULL;\r
+  }\r
+  \r
+\r
+  //\r
+  // Handle ACPI OS TPM requests here\r
+  //\r
+  Status = gBS->LocateProtocol (\r
+                  &gEfiCpuIoProtocolGuid,\r
+                  NULL,\r
+                  (VOID **)&CpuIo\r
+                  );\r
+  Status = gBS->LocateProtocol (\r
+                  &gEfiTpmMpDriverProtocolGuid,\r
+                  NULL,\r
+                  (VOID **)&TpmMpDriver\r
+                  );\r
+  if (!EFI_ERROR (Status))\r
+  {\r
+    Data = ReadCmosBank1Byte (CpuIo, ACPI_TPM_REQUEST);\r
+\r
+    //\r
+    // Clear pending ACPI TPM request indicator\r
+    //\r
+    WriteCmosBank1Byte (CpuIo, ACPI_TPM_REQUEST, 0x00);\r
+    if (Data != 0)\r
+    {\r
+      WriteCmosBank1Byte (CpuIo, ACPI_TPM_LAST_REQUEST, Data);\r
+\r
+      //\r
+      // Assert Physical Presence for these commands\r
+      //\r
+      TpmPhysicalPresenceCommand [11] = 0x20;\r
+      ReceiveBufferSize = sizeof(ReceiveBuffer);\r
+      Status = TpmMpDriver->Transmit (\r
+                              TpmMpDriver, TpmPhysicalPresenceCommand,\r
+                              sizeof (TpmPhysicalPresenceCommand),\r
+                              ReceiveBuffer, &ReceiveBufferSize\r
+                              );\r
+      //\r
+      // PF PhysicalPresence = TRUE\r
+      //\r
+      TpmPhysicalPresenceCommand [11] = 0x08;\r
+      ReceiveBufferSize = sizeof(ReceiveBuffer);\r
+      Status = TpmMpDriver->Transmit (\r
+                              TpmMpDriver, TpmPhysicalPresenceCommand,\r
+                              sizeof (TpmPhysicalPresenceCommand),\r
+                              ReceiveBuffer,\r
+                              &ReceiveBufferSize\r
+                              );\r
+      if (Data == 0x01)\r
+      {\r
+        //\r
+        // TPM_PhysicalEnable\r
+        //\r
+        ReceiveBufferSize = sizeof(ReceiveBuffer);\r
+        Status = TpmMpDriver->Transmit (\r
+                                TpmMpDriver, TpmPhysicalEnableCommand,\r
+                                sizeof (TpmPhysicalEnableCommand),\r
+                                ReceiveBuffer, &ReceiveBufferSize\r
+                                );\r
+      }\r
+      if (Data == 0x02)\r
+      {\r
+        //\r
+        // TPM_PhysicalDisable\r
+        //\r
+        ReceiveBufferSize = sizeof(ReceiveBuffer);\r
+        Status = TpmMpDriver->Transmit (\r
+                                TpmMpDriver, TpmPhysicalDisableCommand,\r
+                                sizeof (TpmPhysicalDisableCommand),\r
+                                ReceiveBuffer,\r
+                                &ReceiveBufferSize\r
+                                );\r
+      }\r
+      if (Data == 0x03)\r
+      {\r
+        //\r
+        // TPM_PhysicalSetDeactivated=FALSE\r
+        //\r
+        ReceiveBufferSize = sizeof(ReceiveBuffer);\r
+        TpmPhysicalSetDeactivatedCommand [10] = 0x00;\r
+        Status = TpmMpDriver->Transmit (\r
+                                TpmMpDriver,\r
+                                TpmPhysicalSetDeactivatedCommand,\r
+                                sizeof (TpmPhysicalSetDeactivatedCommand),\r
+                                ReceiveBuffer, &ReceiveBufferSize\r
+                                );\r
+        gRT->ResetSystem (EfiResetWarm, EFI_SUCCESS, 0, NULL);\r
+      }\r
+      if (Data == 0x04)\r
+      {\r
+        //\r
+        // TPM_PhysicalSetDeactivated=TRUE\r
+        //\r
+        ReceiveBufferSize = sizeof(ReceiveBuffer);\r
+        TpmPhysicalSetDeactivatedCommand [10] = 0x01;\r
+        Status = TpmMpDriver->Transmit (\r
+                                TpmMpDriver,\r
+                                TpmPhysicalSetDeactivatedCommand,\r
+                                sizeof (TpmPhysicalSetDeactivatedCommand),\r
+                                ReceiveBuffer,\r
+                                &ReceiveBufferSize\r
+                                );\r
+        gRT->ResetSystem (\r
+               EfiResetWarm,\r
+               EFI_SUCCESS,\r
+               0,\r
+               NULL\r
+               );\r
+      }\r
+      if (Data == 0x05)\r
+      {\r
+        //\r
+        // TPM_ForceClear\r
+        //\r
+        ReceiveBufferSize = sizeof(ReceiveBuffer);\r
+        Status = TpmMpDriver->Transmit (\r
+                                TpmMpDriver,\r
+                                TpmForceClearCommand,\r
+                                sizeof (TpmForceClearCommand),\r
+                                ReceiveBuffer,\r
+                                &ReceiveBufferSize\r
+                                );\r
+        gRT->ResetSystem (\r
+               EfiResetWarm,\r
+               EFI_SUCCESS,\r
+               0,\r
+               NULL\r
+               );\r
+      }\r
+      if (Data == 0x06)\r
+      {\r
+        //\r
+        // TPM_PhysicalEnable\r
+        //\r
+        ReceiveBufferSize = sizeof(ReceiveBuffer);\r
+        Status = TpmMpDriver->Transmit (\r
+                                TpmMpDriver,\r
+                                TpmPhysicalEnableCommand,\r
+                                sizeof (TpmPhysicalEnableCommand),\r
+                                ReceiveBuffer,\r
+                                &ReceiveBufferSize\r
+                                );\r
+        //\r
+        // TPM_PhysicalSetDeactivated=FALSE\r
+        //\r
+        ReceiveBufferSize = sizeof(ReceiveBuffer);\r
+        TpmPhysicalSetDeactivatedCommand [10] = 0x00;\r
+        Status = TpmMpDriver->Transmit (\r
+                                TpmMpDriver,\r
+                                TpmPhysicalSetDeactivatedCommand,\r
+                                sizeof (TpmPhysicalSetDeactivatedCommand),\r
+                                ReceiveBuffer,\r
+                                &ReceiveBufferSize\r
+                                );\r
+        gRT->ResetSystem (\r
+               EfiResetWarm,\r
+               EFI_SUCCESS,\r
+               0,\r
+               NULL\r
+               );\r
+      }\r
+      if (Data == 0x07)\r
+      {\r
+        //\r
+        // TPM_PhysicalSetDeactivated=TRUE\r
+        //\r
+        ReceiveBufferSize = sizeof(ReceiveBuffer);\r
+        TpmPhysicalSetDeactivatedCommand [10] = 0x01;\r
+        Status = TpmMpDriver->Transmit (\r
+                                TpmMpDriver,\r
+                                TpmPhysicalSetDeactivatedCommand,\r
+                                sizeof (TpmPhysicalSetDeactivatedCommand),\r
+                                ReceiveBuffer,\r
+                                &ReceiveBufferSize\r
+                                );\r
+        //\r
+        // TPM_PhysicalDisable\r
+        //\r
+        ReceiveBufferSize = sizeof(ReceiveBuffer);\r
+        Status = TpmMpDriver->Transmit (\r
+                                TpmMpDriver,\r
+                                TpmPhysicalDisableCommand,\r
+                                sizeof (TpmPhysicalDisableCommand),\r
+                                ReceiveBuffer,\r
+                                &ReceiveBufferSize\r
+                                );\r
+        gRT->ResetSystem (\r
+               EfiResetWarm,\r
+               EFI_SUCCESS,\r
+               0,\r
+               NULL\r
+               );\r
+      }\r
+      if (Data == 0x08)\r
+      {\r
+        //\r
+        // TPM_SetOwnerInstall=TRUE\r
+        //\r
+        ReceiveBufferSize = sizeof(ReceiveBuffer);\r
+        TpmSetOwnerInstallCommand [10] = 0x01;\r
+        Status = TpmMpDriver->Transmit (\r
+                                TpmMpDriver,\r
+                                TpmSetOwnerInstallCommand,\r
+                                sizeof (TpmSetOwnerInstallCommand),\r
+                                ReceiveBuffer,\r
+                                &ReceiveBufferSize\r
+                                );\r
+      }\r
+      if (Data == 0x09)\r
+      {\r
+        //\r
+        // TPM_SetOwnerInstall=FALSE\r
+        //\r
+        ReceiveBufferSize = sizeof(ReceiveBuffer);\r
+        TpmSetOwnerInstallCommand [10] = 0x00;\r
+        Status = TpmMpDriver->Transmit (\r
+                                TpmMpDriver,\r
+                                TpmSetOwnerInstallCommand,\r
+                                sizeof (TpmSetOwnerInstallCommand),\r
+                                ReceiveBuffer,\r
+                                &ReceiveBufferSize\r
+                                );\r
+      }\r
+      if (Data == 0x0A)\r
+      {\r
+        //\r
+        // TPM_PhysicalEnable\r
+        //\r
+        ReceiveBufferSize = sizeof(ReceiveBuffer);\r
+        Status = TpmMpDriver->Transmit (\r
+                                TpmMpDriver,\r
+                                TpmPhysicalEnableCommand,\r
+                                sizeof (TpmPhysicalEnableCommand),\r
+                                ReceiveBuffer,\r
+                                &ReceiveBufferSize\r
+                                );\r
+        //\r
+        // TPM_PhysicalSetDeactivated=FALSE\r
+        //\r
+        ReceiveBufferSize = sizeof(ReceiveBuffer);\r
+        TpmPhysicalSetDeactivatedCommand [10] = 0x00;\r
+        Status = TpmMpDriver->Transmit (\r
+                                TpmMpDriver,\r
+                                TpmPhysicalSetDeactivatedCommand,\r
+                                sizeof (TpmPhysicalSetDeactivatedCommand),\r
+                                ReceiveBuffer,\r
+                                &ReceiveBufferSize\r
+                                );\r
+        //\r
+        // Do TPM_SetOwnerInstall=TRUE on next reboot\r
+        //\r
+\r
+        WriteCmosBank1Byte (CpuIo, ACPI_TPM_REQUEST, 0xF0);\r
+\r
+        gRT->ResetSystem (\r
+               EfiResetWarm,\r
+               EFI_SUCCESS,\r
+               0,\r
+               NULL\r
+               );\r
+      }\r
+      if (Data == 0x0B)\r
+      {\r
+        //\r
+        // TPM_SetOwnerInstall=FALSE\r
+        //\r
+        ReceiveBufferSize = sizeof(ReceiveBuffer);\r
+        TpmSetOwnerInstallCommand [10] = 0x00;\r
+        Status = TpmMpDriver->Transmit (\r
+                                TpmMpDriver,\r
+                                TpmSetOwnerInstallCommand,\r
+                                sizeof (TpmSetOwnerInstallCommand),\r
+                                ReceiveBuffer,\r
+                                &ReceiveBufferSize\r
+                                );\r
+        //\r
+        // TPM_PhysicalSetDeactivated=TRUE\r
+        //\r
+        ReceiveBufferSize = sizeof(ReceiveBuffer);\r
+        TpmPhysicalSetDeactivatedCommand [10] = 0x01;\r
+        Status = TpmMpDriver->Transmit (\r
+                                TpmMpDriver,\r
+                                TpmPhysicalSetDeactivatedCommand,\r
+                                sizeof (TpmPhysicalSetDeactivatedCommand),\r
+                                ReceiveBuffer,\r
+                                &ReceiveBufferSize\r
+                                );\r
+        //\r
+        // TPM_PhysicalDisable\r
+        //\r
+        ReceiveBufferSize = sizeof(ReceiveBuffer);\r
+        Status = TpmMpDriver->Transmit (\r
+                                TpmMpDriver,\r
+                                TpmPhysicalDisableCommand,\r
+                                sizeof (TpmPhysicalDisableCommand),\r
+                                ReceiveBuffer,\r
+                                &ReceiveBufferSize\r
+                                );\r
+        gRT->ResetSystem (\r
+               EfiResetWarm,\r
+               EFI_SUCCESS,\r
+               0,\r
+               NULL\r
+               );\r
+      }\r
+      if (Data == 0x0E)\r
+      {\r
+        //\r
+        // TPM_ForceClear\r
+        //\r
+        ReceiveBufferSize = sizeof(ReceiveBuffer);\r
+        Status = TpmMpDriver->Transmit (\r
+                                TpmMpDriver,\r
+                                TpmForceClearCommand,\r
+                                sizeof (TpmForceClearCommand),\r
+                                ReceiveBuffer,\r
+                                &ReceiveBufferSize\r
+                                );\r
+        //\r
+        // TPM_PhysicalEnable\r
+        //\r
+        ReceiveBufferSize = sizeof(ReceiveBuffer);\r
+        Status = TpmMpDriver->Transmit (\r
+                                TpmMpDriver,\r
+                                TpmPhysicalEnableCommand,\r
+                                sizeof (TpmPhysicalEnableCommand),\r
+                                ReceiveBuffer,\r
+                                &ReceiveBufferSize\r
+                                );\r
+        //\r
+        // TPM_PhysicalSetDeactivated=FALSE\r
+        //\r
+        ReceiveBufferSize = sizeof(ReceiveBuffer);\r
+        TpmPhysicalSetDeactivatedCommand [10] = 0x00;\r
+        Status = TpmMpDriver->Transmit (\r
+                                TpmMpDriver,\r
+                                TpmPhysicalSetDeactivatedCommand,\r
+                                sizeof (TpmPhysicalSetDeactivatedCommand),\r
+                                ReceiveBuffer,\r
+                                &ReceiveBufferSize\r
+                                );\r
+        gRT->ResetSystem (\r
+               EfiResetWarm,\r
+               EFI_SUCCESS,\r
+               0,\r
+               NULL\r
+               );\r
+      }\r
+      if (Data == 0xF0)\r
+      {\r
+        //\r
+        // Second part of ACPI TPM request 0x0A: OEM custom TPM_SetOwnerInstall=TRUE\r
+        //\r
+        ReceiveBufferSize = sizeof(ReceiveBuffer);\r
+        TpmSetOwnerInstallCommand [10] = 0x01;\r
+        Status = TpmMpDriver->Transmit (\r
+                                TpmMpDriver,\r
+                                TpmSetOwnerInstallCommand,\r
+                                sizeof (TpmSetOwnerInstallCommand),\r
+                                ReceiveBuffer,\r
+                                &ReceiveBufferSize\r
+                                );\r
+        WriteCmosBank1Byte (CpuIo, ACPI_TPM_LAST_REQUEST, 0x0A);\r
+      }\r
+      //\r
+      // Deassert Physical Presence\r
+      //\r
+      TpmPhysicalPresenceCommand [11] = 0x10;\r
+      ReceiveBufferSize = sizeof(ReceiveBuffer);\r
+      Status = TpmMpDriver->Transmit (\r
+                              TpmMpDriver,\r
+                              TpmPhysicalPresenceCommand,\r
+                              sizeof (TpmPhysicalPresenceCommand),\r
+                              ReceiveBuffer,\r
+                              &ReceiveBufferSize\r
+                              );\r
+    }\r
+  }\r
+\r
+  return;\r
+}\r
+\r
+/**\r
+\r
+  Initializes manufacturing and config mode setting.\r
+\r
+**/\r
+VOID\r
+InitMfgAndConfigModeStateVar()\r
+{\r
+  EFI_PLATFORM_SETUP_ID           *BootModeBuffer;\r
+  VOID                            *HobList;\r
+  UINT16                          State;\r
+\r
+  //\r
+  // Variable initialization\r
+  //\r
+  State = FALSE;\r
+\r
+  HobList = GetFirstGuidHob(&gEfiPlatformBootModeGuid);\r
+  if (HobList != NULL) {\r
+    BootModeBuffer = GET_GUID_HOB_DATA (HobList);\r
+\r
+      //\r
+      // Check if in Manufacturing mode\r
+      //\r
+      if ( !CompareMem (\r
+              &BootModeBuffer->SetupName,\r
+              MANUFACTURE_SETUP_NAME,\r
+              StrSize (MANUFACTURE_SETUP_NAME)\r
+              ) ) {\r
+        mMfgMode = TRUE;\r
+      }\r
+\r
+      //\r
+      // Check if in safe mode\r
+      //\r
+      if ( !CompareMem (\r
+              &BootModeBuffer->SetupName,\r
+              SAFE_SETUP_NAME,\r
+              StrSize (SAFE_SETUP_NAME)\r
+              ) ) {\r
+        State = TRUE;\r
+      }\r
+  }\r
+\r
+}\r
+\r
+/**\r
+\r
+  Initializes manufacturing and config mode setting.\r
+\r
+**/\r
+VOID\r
+InitPlatformBootMode()\r
+{\r
+  EFI_PLATFORM_SETUP_ID           *BootModeBuffer;\r
+  VOID                            *HobList;\r
+\r
+  HobList = GetFirstGuidHob(&gEfiPlatformBootModeGuid);\r
+  if (HobList != NULL) {\r
+    BootModeBuffer = GET_GUID_HOB_DATA (HobList);\r
+    mPlatformBootMode = BootModeBuffer->PlatformBootMode;\r
+  }\r
+}\r
+\r
+/**\r
+\r
+  Initializes ITK.\r
+\r
+**/\r
+VOID\r
+InitItk(\r
+  )\r
+{\r
+  EFI_STATUS                          Status;\r
+  UINT16                              ItkModBiosState;\r
+  UINT8                               Value;\r
+  UINTN                               DataSize;\r
+  UINT32                              Attributes;\r
+\r
+  //\r
+  // Setup local variable according to ITK variable\r
+  //\r
+  //\r
+  // Read ItkBiosModVar to determine if BIOS has been modified by ITK\r
+  // If ItkBiosModVar = 0 or if variable hasn't been initialized then BIOS has not been modified by ITK modified\r
+  // Set local variable VAR_EQ_ITK_BIOS_MOD_DECIMAL_NAME=0 if BIOS has not been modified by ITK\r
+  //\r
+  DataSize = sizeof (Value);\r
+  Status = gRT->GetVariable (\r
+                  ITK_BIOS_MOD_VAR_NAME,\r
+                  &gItkDataVarGuid,\r
+                  &Attributes,\r
+                  &DataSize,\r
+                  &Value\r
+                  );\r
+  if (Status == EFI_NOT_FOUND) {\r
+    //\r
+    // Variable not found, hasn't been initialized, intialize to 0\r
+    //\r
+    Value=0x00;\r
+  //\r
+  // Write variable to flash.\r
+  //\r
+  gRT->SetVariable (\r
+         ITK_BIOS_MOD_VAR_NAME,\r
+         &gItkDataVarGuid,\r
+         EFI_VARIABLE_RUNTIME_ACCESS |\r
+         EFI_VARIABLE_NON_VOLATILE |\r
+         EFI_VARIABLE_BOOTSERVICE_ACCESS,\r
+         sizeof (Value),\r
+         &Value\r
+         );\r
+\r
+}\r
+  if ( (!EFI_ERROR (Status)) || (Status == EFI_NOT_FOUND) ) {\r
+    if (Value == 0x00) {\r
+      ItkModBiosState = 0x00;\r
+    } else {\r
+      ItkModBiosState = 0x01;\r
+    }\r
+    gRT->SetVariable (\r
+           VAR_EQ_ITK_BIOS_MOD_DECIMAL_NAME,\r
+           &gEfiNormalSetupGuid,\r
+           EFI_VARIABLE_BOOTSERVICE_ACCESS,\r
+           2,\r
+           (void *)&ItkModBiosState\r
+           );\r
+  }\r
+}\r
+\r
+#if defined(FIRMWARE_ID_BACKWARD_COMPATIBLE) && (FIRMWARE_ID_BACKWARD_COMPATIBLE != 0)\r
+\r
+/**\r
+\r
+  Initializes the BIOS FIRMWARE ID from the FIRMWARE_ID build variable.\r
+\r
+**/\r
+STATIC\r
+VOID\r
+InitFirmwareId(\r
+  )\r
+{\r
+  EFI_STATUS   Status;\r
+  CHAR16       FirmwareIdNameWithPassword[] = FIRMWARE_ID_NAME_WITH_PASSWORD;\r
+\r
+  //\r
+  // First try writing the variable without a password in case we are\r
+  // upgrading from a BIOS without password protection on the FirmwareId\r
+  //\r
+  Status = gRT->SetVariable(\r
+                  (CHAR16 *)&gFirmwareIdName,\r
+                  &gFirmwareIdGuid,\r
+                  EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS |\r
+                  EFI_VARIABLE_RUNTIME_ACCESS,\r
+                  sizeof( FIRMWARE_ID ) - 1,\r
+                  FIRMWARE_ID\r
+                  );\r
+\r
+  if (Status == EFI_INVALID_PARAMETER) {\r
+\r
+    //\r
+    // Since setting the firmware id without the password failed,\r
+    // a password must be required.\r
+    //\r
+    Status = gRT->SetVariable(\r
+                    (CHAR16 *)&FirmwareIdNameWithPassword,\r
+                    &gFirmwareIdGuid,\r
+                    EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS |\r
+                    EFI_VARIABLE_RUNTIME_ACCESS,\r
+                    sizeof( FIRMWARE_ID ) - 1,\r
+                    FIRMWARE_ID\r
+                    );\r
+  }\r
+}\r
+#endif\r
+\r
+VOID\r
+UpdateDVMTSetup(\r
+  )\r
+{\r
+    //\r
+  // Workaround to support IIA bug.\r
+  // IIA request to change option value to 4, 5 and 7 relatively\r
+  // instead of 1, 2, and 3 which follow Lakeport Specs.\r
+  // Check option value, temporary hardcode GraphicsDriverMemorySize\r
+  // Option value to fulfill IIA requirment. So that user no need to\r
+  // load default and update setupvariable after update BIOS.\r
+  //   Option value hardcoded as: 1 to 4, 2 to 5, 3 to 7.\r
+  // *This is for broadwater and above product only.\r
+  //\r
+\r
+  SYSTEM_CONFIGURATION        SystemConfiguration;\r
+  UINTN                       VarSize;\r
+  EFI_STATUS                  Status;\r
+\r
+  VarSize = sizeof(SYSTEM_CONFIGURATION);\r
+  Status = gRT->GetVariable(\r
+                  NORMAL_SETUP_NAME,\r
+                  &gEfiNormalSetupGuid,\r
+                  NULL,\r
+                  &VarSize,\r
+                  &SystemConfiguration\r
+                  );\r
+\r
+  if((SystemConfiguration.GraphicsDriverMemorySize < 4) && !EFI_ERROR(Status) ) {\r
+    switch (SystemConfiguration.GraphicsDriverMemorySize){\r
+      case 1:\r
+        SystemConfiguration.GraphicsDriverMemorySize = 4;\r
+        break;\r
+      case 2:\r
+        SystemConfiguration.GraphicsDriverMemorySize = 5;\r
+        break;\r
+      case 3:\r
+        SystemConfiguration.GraphicsDriverMemorySize = 7;\r
+        break;\r
+      default:\r
+        break;\r
+     }\r
+\r
+    Status = gRT->SetVariable (\r
+                    NORMAL_SETUP_NAME,\r
+                    &gEfiNormalSetupGuid,\r
+                    EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS,\r
+                    sizeof(SYSTEM_CONFIGURATION),\r
+                    &SystemConfiguration\r
+                    );\r
+  }\r
+}\r
+\r
+VOID\r
+InitPlatformUsbPolicy (\r
+  VOID\r
+  )\r
+\r
+{\r
+  EFI_HANDLE              Handle;\r
+  EFI_STATUS              Status;\r
+\r
+  Handle = NULL;\r
+\r
+  mUsbPolicyData.Version                       = (UINT8)USB_POLICY_PROTOCOL_REVISION_2;\r
+  mUsbPolicyData.UsbMassStorageEmulationType   = mSystemConfiguration.UsbBIOSINT13DeviceEmulation;\r
+  if(mUsbPolicyData.UsbMassStorageEmulationType == 3) {\r
+    mUsbPolicyData.UsbEmulationSize = mSystemConfiguration.UsbBIOSINT13DeviceEmulationSize;\r
+  } else {\r
+    mUsbPolicyData.UsbEmulationSize = 0;\r
+  }\r
+  mUsbPolicyData.UsbZipEmulationType         = mSystemConfiguration.UsbZipEmulation;\r
+  mUsbPolicyData.UsbOperationMode              = HIGH_SPEED;\r
+\r
+  //\r
+  //  Some chipset need Period smi, 0 = LEGACY_PERIOD_UN_SUPP\r
+  //\r
+  mUsbPolicyData.USBPeriodSupport      = LEGACY_PERIOD_UN_SUPP;\r
+\r
+  //\r
+  //  Some platform need legacyfree, 0 = LEGACY_FREE_UN_SUPP\r
+  //\r
+  mUsbPolicyData.LegacyFreeSupport    = LEGACY_FREE_UN_SUPP;\r
+\r
+  //\r
+  //  Set Code base , TIANO_CODE_BASE =0x01, ICBD =0x00\r
+  //\r
+  mUsbPolicyData.CodeBase    = (UINT8)ICBD_CODE_BASE;\r
+\r
+  //\r
+  //  Some chispet 's LpcAcpibase are diffrent,set by platform or chipset,\r
+  //  default is Ich  acpibase =0x040. acpitimerreg=0x08.\r
+  mUsbPolicyData.LpcAcpiBase     = 0x40;\r
+  mUsbPolicyData.AcpiTimerReg    = 0x08;\r
+\r
+  //\r
+  //  Set for reduce usb post time\r
+  //\r
+  mUsbPolicyData.UsbTimeTue           = 0x00;\r
+  mUsbPolicyData.InternelHubExist     = 0x00;  //TigerPoint doesn't have RMH\r
+  mUsbPolicyData.EnumWaitPortStableStall    = 100;\r
+\r
+\r
+  Status = gBS->InstallProtocolInterface (\r
+                  &Handle,\r
+                  &gUsbPolicyGuid,\r
+                  EFI_NATIVE_INTERFACE,\r
+                  &mUsbPolicyData\r
+                  );\r
+  ASSERT_EFI_ERROR(Status);\r
+\r
+}\r
+\r
+UINT8\r
+ReadCmosBank1Byte (\r
+  IN  EFI_CPU_IO_PROTOCOL             *CpuIo,\r
+  IN  UINT8                           Index\r
+  )\r
+{\r
+  UINT8                               Data;\r
+\r
+  CpuIo->Io.Write (CpuIo, EfiCpuIoWidthUint8, 0x72, 1, &Index);\r
+  CpuIo->Io.Read (CpuIo, EfiCpuIoWidthUint8, 0x73, 1, &Data);\r
+  return Data;\r
+}\r
+\r
+VOID\r
+WriteCmosBank1Byte (\r
+  IN  EFI_CPU_IO_PROTOCOL             *CpuIo,\r
+  IN  UINT8                           Index,\r
+  IN  UINT8                           Data\r
+  )\r
+{\r
+  CpuIo->Io.Write (\r
+              CpuIo,\r
+              EfiCpuIoWidthUint8,\r
+              0x72,\r
+              1,\r
+              &Index\r
+              );\r
+  CpuIo->Io.Write (\r
+              CpuIo,\r
+              EfiCpuIoWidthUint8,\r
+              0x73,\r
+              1,\r
+              &Data\r
+              );\r
+}\r
+\r

diff --git a/Vlv2TbltDevicePkg/PlatformDxe/PlatformDxe.h b/Vlv2TbltDevicePkg/PlatformDxe/PlatformDxe.h
new file mode 100644 (file)
index 0000000..42197ca
--- /dev/null
+++ b/Vlv2TbltDevicePkg/PlatformDxe/PlatformDxe.h
@@ -0,0 +1,719 @@
+/*++\r
+\r
+  Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+\r
+Module Name:\r
+\r
+  PlatformDxe.h\r
+\r
+Abstract:\r
+\r
+  Header file for Platform Initialization Driver.\r
+\r
+\r
+\r
+++*/\r
+\r
+#ifndef _PLATFORM_DRIVER_H\r
+#define _PLATFORM_DRIVER_H\r
+\r
+#include <PiDxe.h>\r
+#include <Library/BaseLib.h>\r
+#include <Library/DebugLib.h>\r
+#include <Library/UefiLib.h>\r
+#include <Library/UefiDriverEntryPoint.h>\r
+#include <Library/PcdLib.h>\r
+#include <Library/HobLib.h>\r
+#include <Library/MemoryAllocationLib.h>\r
+#include <Library/UefiBootServicesTableLib.h>\r
+#include <Library/BaseMemoryLib.h>\r
+#include <Library/UefiRuntimeServicesTableLib.h>\r
+#include <Library/IoLib.h>\r
+#include <Library/ReportStatusCodeLib.h>\r
+#include <Library/HobLib.h>\r
+#include <Library/EfiRegTableLib.h>\r
+#include <Library/Tpm2CommandLib.h>\r
+#include <Library/Tpm2DeviceLib.h>\r
+#include <Library/BaseCryptLib.h>\r
+#include <Protocol/GlobalNvsArea.h>\r
+#include <Protocol/PciRootBridgeIo.h>\r
+#include <Protocol/IsaAcpi.h>\r
+#include <Framework/FrameworkInternalFormRepresentation.h>\r
+#include <Protocol/FrameworkHii.h>\r
+#include <Protocol/FrameworkFormCallback.h>\r
+#include <Protocol/CpuIo.h>\r
+#include <Protocol/BootScriptSave.h>\r
+#include <Framework/BootScript.h>\r
+#include <Guid/GlobalVariable.h>\r
+#include <Guid/BoardFeatures.h>\r
+#include <Guid/DataHubRecords.h>\r
+#include <Protocol/DataHub.h>\r
+#include <Protocol/PciIo.h>\r
+#include <Protocol/Speaker.h>\r
+#include <IndustryStandard/Pci22.h>\r
+#include <Guid/SetupVariable.h>\r
+#include <Guid/PlatformInfo.h>\r
+#include "Configuration.h"\r
+#define _EFI_H_    //skip efi.h\r
+#include "PchAccess.h"\r
+#include "VlvAccess.h"\r
+#include "BoardIdDecode.h"\r
+#include "PlatformBaseAddresses.h"\r
+#include "SetupMode.h"\r
+#include "PlatformBootMode.h"\r
+#include "CpuType.h"\r
+\r
+#define PCAT_RTC_ADDRESS_REGISTER   0x74\r
+#define PCAT_RTC_DATA_REGISTER      0x75\r
+\r
+#define RTC_ADDRESS_SECOND_ALARM    0x01\r
+#define RTC_ADDRESS_MINUTE_ALARM    0x03\r
+#define RTC_ADDRESS_HOUR_ALARM      0x05\r
+\r
+#define RTC_ADDRESS_REGISTER_A      0x0A\r
+#define RTC_ADDRESS_REGISTER_B      0x0B\r
+#define RTC_ADDRESS_REGISTER_C      0x0C\r
+#define RTC_ADDRESS_REGISTER_D      0x0D\r
+\r
+#define B_RTC_ALARM_INT_ENABLE      0x20\r
+#define B_RTC_ALARM_INT_STATUS      0x20\r
+\r
+#define B_RTC_DATE_ALARM_MASK       0x3F\r
+\r
+//\r
+// Default CPU Alternate Duty Cycle (255=100%, 0=0%)\r
+//\r
+#define DEF_CPU_ALT_DUTY_CYCLE 0xFF\r
+\r
+#define MAX_ONBOARD_SATA_DEVICE 2\r
+\r
+#define DXE_DEVICE_ENABLED  1\r
+#define DXE_DEVICE_DISABLED 0\r
+\r
+#define AZALIA_MAX_LOOP_TIME  0x10000\r
+\r
+//\r
+// Platform driver GUID\r
+//\r
+#define EFI_PLATFORM_DRIVER_GUID \\r
+  { 0x056E7324, 0xA718, 0x465b, 0x9A, 0x84, 0x22, 0x8F, 0x06, 0x64, 0x2B, 0x4F }\r
+\r
+#define PASSWORD_MAX_SIZE               20\r
+#define PLATFORM_NORMAL_MODE          0x01\r
+#define PLATFORM_SAFE_MODE            0x02\r
+#define PLATFORM_RECOVERY_MODE        0x04\r
+#define PLATFORM_MANUFACTURING_MODE   0x08\r
+#define PLATFORM_BACK_TO_BIOS_MODE    0x10\r
+\r
+#define EFI_OEM_SPECIFIC      0x8000\r
+#define EFI_CU_PLATFORM_DXE_INIT                     (EFI_OEM_SPECIFIC | 0x00000011)\r
+#define EFI_CU_PLATFORM_DXE_STEP1                    (EFI_OEM_SPECIFIC | 0x00000012)\r
+#define EFI_CU_PLATFORM_DXE_STEP2                    (EFI_OEM_SPECIFIC | 0x00000013)\r
+#define EFI_CU_PLATFORM_DXE_STEP3                    (EFI_OEM_SPECIFIC | 0x00000014)\r
+#define EFI_CU_PLATFORM_DXE_STEP4                    (EFI_OEM_SPECIFIC | 0x00000015)\r
+#define EFI_CU_PLATFORM_DXE_INIT_DONE                (EFI_OEM_SPECIFIC | 0x00000016)\r
+\r
+\r
+#define EFI_SECTION_STRING                  0x1C\r
+#define EFI_FORWARD_DECLARATION(x) typedef struct _##x x\r
+#define PREFIX_BLANK                        0x04\r
+\r
+#pragma pack(1)\r
+\r
+typedef UINT64 EFI_BOARD_FEATURES;\r
+\r
+//\r
+//BUGBUG: should remove these EDK hii definition once Hii transtion is done\r
+//\r
+typedef UINT16  STRING_REF;\r
+typedef UINT16  EFI_FORM_LABEL;\r
+\r
+typedef enum {\r
+  EfiUserPassword,\r
+  EfiAdminPassword\r
+} EFI_PASSWORD_TYPE;\r
+\r
+typedef struct {\r
+  CHAR16            TempPassword[PASSWORD_MAX_SIZE];\r
+  CHAR16            EncodedPassword[PASSWORD_MAX_SIZE];\r
+  VOID              *PasswordLocation;\r
+  EFI_PASSWORD_TYPE PasswordType;\r
+} EFI_PASSWORD_DATA;\r
+\r
+typedef struct {\r
+  CHAR8 AaNumber[7];\r
+  UINT8 BoardId;\r
+  EFI_BOARD_FEATURES Features;\r
+  UINT16 SubsystemDeviceId;\r
+  UINT16 AudioSubsystemDeviceId;\r
+  UINT64 AcpiOemTableId;\r
+} BOARD_ID_DECODE;\r
+\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *EFI_FORM_ROUTINE) (\r
+  SYSTEM_CONFIGURATION *SetupBuffer\r
+  );\r
+\r
+typedef struct{\r
+  UINT16 DeviceNumber;\r
+  UINT16 FunctionNumber;\r
+}PCI_DEVICE_FUNC_INFO;\r
+\r
+typedef struct{\r
+  CHAR16 PortNumber[4];\r
+  STRING_REF SataDeviceInfoStringId;\r
+}SATA_DEVICE_STRING_INFO;\r
+\r
+typedef struct {\r
+  UINT16  Signature;\r
+  UINT8   Size;\r
+  UINT32  EntryPoint;\r
+  UINT8   Reserve[17];\r
+  UINT16  PciDataOff;\r
+  UINT16  ExpansionOff;\r
+} PNP_OPTION_ROM_HEADER;\r
+\r
+typedef struct {\r
+  UINT32  Signature;\r
+  UINT8   Revision;\r
+  UINT8   Length;\r
+  UINT16  NextHeader;\r
+  UINT8   Reserve;\r
+  UINT8   CheckSum;\r
+  UINT32  DeviceId;\r
+  UINT16  ManufactureStrOff;\r
+  UINT16  ProductStrOff;\r
+} PNP_EXPANSION_HEADER;\r
+\r
+typedef struct {\r
+  BOOLEAN                         Enable;\r
+  UINT8                           VerbTableNum;\r
+  UINT16                          CodecSSID;\r
+  EFI_PHYSICAL_ADDRESS            HDABar;\r
+  EFI_PHYSICAL_ADDRESS            UpperHDABar;\r
+  UINT8                           SDIPresent;\r
+  BOOLEAN                         Pme;\r
+  BOOLEAN                         LegacyFrontPanelAudio;\r
+  BOOLEAN                         HighDefinitionFrontPanelAudio;\r
+} EFI_AZALIA_S3;\r
+\r
+//\r
+//following structs are from R8. Remove them once R8->R9 transition is done\r
+//\r
+typedef struct {\r
+  CHAR16      *OptionString;  // Passed in string to generate a token for in a truly dynamic form creation\r
+  STRING_REF  StringToken;    // This is used when creating a single op-code without generating a StringToken (have one already)\r
+  UINT16      Value;\r
+  UINT8       Flags;\r
+  UINT16      Key;\r
+} IFR_OPTION;\r
+\r
+\r
+\r
+typedef struct {\r
+  UINT8   Number;\r
+  UINT32  HorizontalResolution;\r
+  UINT32  VerticalResolution;\r
+} PANEL_RESOLUTION;\r
+\r
+#pragma pack()\r
+\r
+//\r
+// Prototypes\r
+//\r
+EFI_STATUS\r
+EFIAPI\r
+EfiMain (\r
+  IN EFI_HANDLE         ImageHandle,\r
+  IN EFI_SYSTEM_TABLE   *SystemTable\r
+  );\r
+\r
+EFI_STATUS\r
+ProcessEventLog (\r
+  );\r
+\r
+EFI_STATUS\r
+FindDataRecords (\r
+  );\r
+\r
+EFI_STATUS\r
+ProcessPasswords(\r
+  );\r
+\r
+VOID\r
+MemorySetup(\r
+  );\r
+\r
+\r
+UINTN\r
+EfiValueToString (\r
+  IN  OUT CHAR16  *Buffer,\r
+  IN  INT64       Value,\r
+  IN  UINTN       Flags,\r
+  IN  UINTN       Width\r
+  );\r
+\r
+VOID\r
+EFIAPI\r
+ReadyToBootFunction (\r
+  EFI_EVENT  Event,\r
+  VOID       *Context\r
+  );\r
+\r
+VOID\r
+InstallHiiDataAndGetSettings(\r
+  IN EFI_HII_STRING_PACK            *StringPack,\r
+      //\r
+  ... // 0 or more of => IN EFI_HII_IFR_PACK *IfrPack,\r
+      // Terminate list with NULL\r
+      //\r
+  );\r
+\r
+EFI_STATUS\r
+ReadOrInitSetupVariable(\r
+  IN UINTN         RequiredVariableSize,\r
+  IN UINTN         RequiredPasswordSize,\r
+  IN VOID          *DefaultData,\r
+  IN VOID          *MfgDefaultData,\r
+  OUT VOID         *SetupVariableData,\r
+  OUT VOID         *SystemPassword\r
+  );\r
+\r
+VOID\r
+EfiLogicalOrMem(\r
+  IN VOID   *Destination,\r
+  IN VOID   *Source,\r
+  IN UINTN  Length\r
+  );\r
+\r
+EFI_STATUS\r
+GetStringFromToken (\r
+  IN      EFI_GUID                  *ProducerGuid,\r
+  IN      STRING_REF                Token,\r
+  OUT     CHAR16                    **String\r
+  );\r
+\r
+UINT32\r
+ConvertBase2ToRaw (\r
+  IN  EFI_EXP_BASE2_DATA             *Data);\r
+\r
+UINT32\r
+ConvertBase10ToRaw (\r
+  IN  EFI_EXP_BASE10_DATA             *Data);\r
+\r
+CHAR16 *\r
+GetStringById (\r
+  IN  STRING_REF   Id,\r
+  EFI_HII_HANDLE   StringPackHandle\r
+  );\r
+\r
+VOID\r
+EFIAPI\r
+SetupDataFilter (\r
+  IN EFI_EVENT    Event,\r
+  IN VOID*        Context\r
+  );\r
+\r
+VOID\r
+EFIAPI\r
+IdeDataFilter (\r
+  IN EFI_EVENT    Event,\r
+  IN VOID*        Context\r
+  );\r
+\r
+VOID\r
+EFIAPI\r
+UpdateAhciRaidDiskInfo (\r
+  IN EFI_EVENT    Event,\r
+  IN VOID*        Context\r
+  );\r
+\r
+VOID\r
+EFIAPI\r
+EventLogFilter (\r
+  IN EFI_EVENT    Event,\r
+  IN VOID*        Context\r
+  );\r
+\r
+VOID\r
+SwapEntries (\r
+  IN  CHAR8 *Data\r
+  );\r
+\r
+VOID\r
+AsciiToUnicode (\r
+  IN    CHAR8     *AsciiString,\r
+  IN    CHAR16    *UnicodeString\r
+  );\r
+\r
+UINT16\r
+ConfigModeStateGet();\r
+\r
+VOID\r
+SetSkus();\r
+\r
+VOID\r
+CPUSetupItems();\r
+\r
+EFI_STATUS\r
+SecurityDriverCallback (\r
+  IN EFI_FORM_CALLBACK_PROTOCOL       *This,\r
+  IN UINT16                           KeyValue,\r
+  IN EFI_IFR_DATA_ARRAY               *Data,\r
+  OUT EFI_HII_CALLBACK_PACKET         **Packet\r
+  );\r
+\r
+VOID\r
+SetPasswordState (\r
+  );\r
+\r
+VOID\r
+EncodePassword (\r
+  IN  CHAR16                      *Password\r
+  );\r
+\r
+VOID\r
+EFIAPI\r
+PciBusEvent (\r
+  IN EFI_EVENT    Event,\r
+  IN VOID*        Context\r
+  );\r
+VOID\r
+AsfInitialize(\r
+  );\r
+\r
+VOID\r
+InitializeAsf (\r
+  );\r
+\r
+UINT8\r
+ReadCmosBank1Byte (\r
+  IN  EFI_CPU_IO_PROTOCOL             *CpuIo,\r
+  IN  UINT8                           Index\r
+  );\r
+\r
+VOID\r
+WriteCmosBank1Byte (\r
+  IN  EFI_CPU_IO_PROTOCOL             *CpuIo,\r
+  IN  UINT8                           Index,\r
+  IN  UINT8                           Data\r
+  );\r
+\r
+VOID\r
+InitializeBoardId (\r
+  );\r
+\r
+EFI_STATUS\r
+InstallBootCallbackRoutine(\r
+  );\r
+\r
+EFI_STATUS\r
+InstallConfigurationCallbackRoutine(\r
+  );\r
+\r
+EFI_STATUS\r
+InstallPerformanceCallbackRoutine(\r
+  );\r
+\r
+EFI_STATUS\r
+InstallSecurityCallbackRoutine (\r
+  );\r
+\r
+EFI_STATUS\r
+InstallMainCallbackRoutine (\r
+  );\r
+\r
+EFI_STATUS\r
+MemoryConfigurationUpdate (\r
+  UINT16                *Key,\r
+  EFI_FORM_LABEL        *Label,\r
+  UINT16                *OpcodeCount,\r
+  UINT8                 **OpcodeData,\r
+  EFI_FORM_ROUTINE      *Routine\r
+  );\r
+\r
+EFI_STATUS\r
+MemoryConfigurationCallbackRoutine (\r
+  SYSTEM_CONFIGURATION  *SetupBuffer\r
+  );\r
+\r
+EFI_STATUS\r
+MemoryConfigurationCalculateSpeed(\r
+  SYSTEM_CONFIGURATION  *SetupBuffer\r
+  );\r
+\r
+VOID\r
+UpdateMemoryString(\r
+  IN  STRING_REF                  TokenToUpdate,\r
+  IN  CHAR16                      *NewString\r
+  );\r
+\r
+VOID\r
+InitFeaturePolicy (\r
+  IN EFI_PLATFORM_INFO_HOB      *PlatformInfo\r
+  );\r
+\r
+VOID\r
+InitializeSetupVarHide (\r
+  );\r
+\r
+VOID\r
+PreparePCIePCISlotInformation(\r
+  VOID\r
+  );\r
+\r
+\r
+EFI_STATUS\r
+BootConfigurationUpdate (\r
+  IN  OUT SYSTEM_CONFIGURATION  *SystemConfiguration\r
+  );\r
+\r
+EFI_STATUS\r
+InitializeBootConfiguration(\r
+  VOID\r
+  );\r
+\r
+UINT16\r
+GetStringSize(\r
+  IN      CHAR16 *ThisString\r
+  );\r
+\r
+UINT16\r
+GetDriveCount (\r
+  IN      STRING_REF *BootMap\r
+  );\r
+\r
+CHAR16 *\r
+GetBootString (\r
+  IN      STRING_REF    Id,\r
+      OUT UINTN        *Length\r
+  );\r
+\r
+EFI_STATUS\r
+BootCfgCreateTwoOptionOneOf(\r
+  IN      UINT16                QuestionId,\r
+  IN      EFI_FORM_LABEL        Label,\r
+  IN      STRING_REF            OptionPrompt,\r
+  IN      STRING_REF            OptionHelp,\r
+  IN      STRING_REF            OptionOneString,\r
+  IN      STRING_REF            OptionTwoString,\r
+  IN      UINT8                 OptionOneFlags,\r
+  IN      UINT8                 OptionTwoFlags,\r
+  IN      UINT16                KeyValueOne,\r
+  IN      UINT16                KeyValueTwo\r
+  );\r
+\r
+EFI_STATUS\r
+ReplaceOpcodeWithText(\r
+  IN      STRING_REF            OptionPrompt,\r
+  IN      STRING_REF            OptionHelp,\r
+  IN      STRING_REF            OptionOneString,\r
+  IN      EFI_FORM_LABEL        Label\r
+  );\r
+\r
+EFI_STATUS\r
+CreateDriveBootOrderOpcode(\r
+  IN      VOID                 *Data,\r
+  IN      STRING_REF           *BootMap,\r
+  IN      EFI_FORM_LABEL        Label,\r
+  IN      UINT16                QuestionId,\r
+  IN      STRING_REF            OptionOneString,\r
+  IN      STRING_REF            OptionTwoString\r
+  );\r
+\r
+VOID\r
+SetHyperBootCfgFlags(\r
+  IN  OUT SYSTEM_CONFIGURATION *SystemConfiguration\r
+  );\r
+\r
+VOID\r
+GetHyperBootCfgFlags(\r
+  IN  OUT SYSTEM_CONFIGURATION *SystemConfiguration\r
+  );\r
+\r
+VOID\r
+PrepareBootCfgForHyperBoot(\r
+  IN  OUT SYSTEM_CONFIGURATION *SystemConfiguration\r
+  );\r
+\r
+BOOLEAN\r
+BootCfgChanged(\r
+  IN      SYSTEM_CONFIGURATION *SystemConfiguration\r
+  );\r
+\r
+EFI_STATUS\r
+InsertOpcodeAtIndex(\r
+  IN      SYSTEM_CONFIGURATION *SystemConfiguration,\r
+  IN  OUT IFR_OPTION           *OptionList,\r
+  IN      IFR_OPTION            IfrOption,\r
+  IN      UINT16                OptionCount\r
+  );\r
+\r
+VOID\r
+ConfigureBootOrderStrings(\r
+  IN      SYSTEM_CONFIGURATION *SystemConfiguration\r
+  );\r
+\r
+VOID\r
+InitializeAllBootStrings(\r
+  VOID\r
+  );\r
+\r
+VOID\r
+SaveUsbCfgSettings(\r
+  IN  OUT SYSTEM_CONFIGURATION *SystemConfiguration\r
+  );\r
+\r
+VOID\r
+RestoreUsbCfgSettings(\r
+  IN  OUT SYSTEM_CONFIGURATION *SystemConfiguration\r
+  );\r
+\r
+EFI_STATUS\r
+UpdateBootDevicePriority(\r
+  IN  OUT SYSTEM_CONFIGURATION *SystemConfiguration\r
+  );\r
+\r
+EFI_STATUS\r
+DisableHyperBoot(\r
+  IN  OUT SYSTEM_CONFIGURATION *SystemConfiguration\r
+  );\r
+\r
+BOOLEAN\r
+CheckForUserPassword(\r
+  VOID\r
+  );\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+HyperBootPasswordCallback(\r
+  IN  OUT VOID*  Data\r
+  );\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+HyperBootF9Callback (\r
+  IN VOID*  Data\r
+  );\r
+\r
+EFI_STATUS\r
+InstallHiiEvents(\r
+  VOID\r
+  );\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+ProgramToneFrequency (\r
+  IN  EFI_SPEAKER_IF_PROTOCOL           *This,\r
+  IN  UINT16                            Frequency\r
+  );\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+GenerateBeepTone (\r
+  IN  EFI_SPEAKER_IF_PROTOCOL           *This,\r
+  IN  UINTN                             NumberOfBeeps,\r
+  IN  UINTN                             BeepDuration,\r
+  IN  UINTN                             TimeInterval\r
+  );\r
+\r
+EFI_STATUS\r
+InitializeObservableProtocol();\r
+\r
+EFI_STATUS\r
+PciBusDriverHook();\r
+\r
+typedef struct _GOP_DISPLAY_BRIGHTNESS_PROTOCOL GOP_DISPLAY_BRIGHTNESS_PROTOCOL;\r
+\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *GET_MAXIMUM_BRIGHTNESS_LEVEL) (\r
+  IN  GOP_DISPLAY_BRIGHTNESS_PROTOCOL *This,\r
+  OUT UINT32 *MaxBrightnessLevel\r
+  );\r
+\r
+\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *GET_CURRENT_BRIGHTNESS_LEVEL) (\r
+  IN  GOP_DISPLAY_BRIGHTNESS_PROTOCOL *This,\r
+  OUT UINT32 *MaxBrightnessLevel\r
+  );\r
+\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *SET_BRIGHTNESS_LEVEL) (\r
+  IN  GOP_DISPLAY_BRIGHTNESS_PROTOCOL *This,\r
+  IN  UINT32  BrightnessLevel\r
+  );\r
+\r
+struct _GOP_DISPLAY_BRIGHTNESS_PROTOCOL {\r
+  UINT32  Revision;\r
+  GET_MAXIMUM_BRIGHTNESS_LEVEL GetMaxBrightnessLevel;\r
+  GET_CURRENT_BRIGHTNESS_LEVEL GetCurrentBrightnessLevel;\r
+  SET_BRIGHTNESS_LEVEL SetBrightnessLevel;\r
+};\r
+\r
+//\r
+// Global externs\r
+//\r
+extern UINT8 MaintenanceBin[];\r
+extern UINT8 MainBin[];\r
+extern UINT8 ConfigurationBin[];\r
+extern UINT8 MemoryConfigurationBin[];\r
+extern UINT8 PerformanceBin[];\r
+extern UINT8 SecurityBin[];\r
+extern UINT8 BootBin[];\r
+extern UINT8 PowerBin[];\r
+extern UINT8 SystemSetupBin[];\r
+\r
+extern VOID                 *mDxePlatformStringPack;\r
+extern EFI_HII_PROTOCOL     *mHii;\r
+extern SYSTEM_CONFIGURATION mSystemConfiguration;\r
+extern FRAMEWORK_EFI_HII_HANDLE       mMaintenanceHiiHandle;\r
+extern FRAMEWORK_EFI_HII_HANDLE       mMainHiiHandle;\r
+extern FRAMEWORK_EFI_HII_HANDLE       mConfigurationHiiHandle;\r
+extern FRAMEWORK_EFI_HII_HANDLE       mPerformanceHiiHandle;\r
+extern FRAMEWORK_EFI_HII_HANDLE       mPowerHiiHandle;\r
+extern FRAMEWORK_EFI_HII_HANDLE       mBootHiiHandle;\r
+extern FRAMEWORK_EFI_HII_HANDLE       mSecurityHiiHandle;\r
+\r
+extern SYSTEM_PASSWORDS     mSystemPassword;\r
+extern EFI_PASSWORD_DATA    mAdminPassword;\r
+extern EFI_PASSWORD_DATA    mUserPassword;\r
+\r
+extern EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *mPciRootBridgeIo;\r
+\r
+//\r
+//extern EFI_REG_TABLE mSubsystemIdRegs[];\r
+//\r
+extern UINT32 mSubsystemVidDid;\r
+extern UINT32 mSubsystemAudioVidDid;\r
+\r
+extern UINT8 mBoardIdIndex;\r
+extern BOOLEAN mFoundAANum;\r
+extern EFI_BOARD_FEATURES mBoardFeatures;\r
+extern UINT16 mSubsystemDeviceId;\r
+extern UINT16 mSubsystemAudioDeviceId;\r
+extern BOARD_ID_DECODE mBoardIdDecodeTable[];\r
+extern UINTN mBoardIdDecodeTableSize;\r
+\r
+extern UINT8 mSmbusRsvdAddresses[];\r
+extern UINT8 mNumberSmbusAddress;\r
+extern BOOLEAN mMfgMode;\r
+extern UINT32 mPlatformBootMode;\r
+extern CHAR8 BoardAaNumber[];\r
+\r
+extern EFI_GUID gEfiGlobalNvsAreaProtocolGuid;\r
+#endif\r

diff --git a/Vlv2TbltDevicePkg/PlatformDxe/PlatformDxe.inf b/Vlv2TbltDevicePkg/PlatformDxe/PlatformDxe.inf
new file mode 100644 (file)
index 0000000..6fa0700
--- /dev/null
+++ b/Vlv2TbltDevicePkg/PlatformDxe/PlatformDxe.inf
@@ -0,0 +1,145 @@
+#/*++\r
+#\r
+#  Copyright (c)  1999  - 2014, Intel Corporation. All rights reserved\r
+#                                                                                  \r\r
+# This program and the accompanying materials are licensed and made available under\r\r
+# the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+# The full text of the license may be found at                                     \r\r
+# http://opensource.org/licenses/bsd-license.php.                                  \r\r
+#                                                                                  \r\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+#                                                                                  \r\r
+#\r
+#  Module Name:\r
+#\r
+#    PlatformBB.inf\r
+#\r
+#  Abstract:\r
+#\r
+#    Component description file for platform DXE driver\r
+#  ------------------------------------------------------------------------------\r
+#  Rev   Date<MM/DD/YYYY>    Name    Description\r
+#  ------------------------------------------------------------------------------\r
+#  R01     <04/22/2011>       LB     Update code for SIO83627UHG support.\r
+#  ------------------------------------------------------------------------------\r
+#\r
+#--*/\r
+\r
+[defines]\r
+  INF_VERSION                    = 0x00010005\r
+  BASE_NAME                      = PlatformDxe\r
+  FILE_GUID                      = 056E7324-A718-465b-9A84-228F06642B4F\r
+  MODULE_TYPE                    = DXE_DRIVER\r
+  VERSION_STRING                 = 1.0\r
+  PI_SPECIFICATION_VERSION       = 0x0001000A\r
+  ENTRY_POINT                    = InitializePlatform\r
+\r
+[sources.common]\r
+  BoardId.c\r
+  BoardIdDecode.c\r
+  ClockControl.c\r
+  Platform.c\r
+  IchRegTable.c\r
+  IdccInfo.c\r
+  SioPlatformPolicy.c\r
+  IchPlatformPolicy.c\r
+  PciDevice.c\r
+  SlotConfig.c\r
+  IchTcoReset.c\r
+  SensorVar.c\r
+  LegacySpeaker.c\r
+  Observable/Observable.c\r
+  ExI.c\r
+\r
+[Packages]\r
+  MdePkg/MdePkg.dec\r
+  MdeModulePkg/MdeModulePkg.dec\r
+  IntelFrameworkPkg/IntelFrameworkPkg.dec\r
+  IntelFrameworkModulePkg/IntelFrameworkModulePkg.dec\r
+  Vlv2TbltDevicePkg/PlatformPkg.dec\r
+  Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec\r
+  SecurityPkg/SecurityPkg.dec\r
+  CryptoPkg/CryptoPkg.dec\r
+\r
+[LibraryClasses]\r
+  BaseLib\r
+  BaseMemoryLib\r
+  MemoryAllocationLib\r
+  UefiBootServicesTableLib\r
+  UefiDriverEntryPoint\r
+  UefiRuntimeServicesTableLib\r
+  DxeServicesTableLib\r
+  PchPlatformLib\r
+\r
+  DebugLib\r
+  HiiLib\r
+  PrintLib\r
+  UefiLib\r
+  S3BootScriptLib\r
+  ReportStatusCodeLib\r
+  EfiRegTableLib\r
+  BiosIdLib\r
+  BaseCryptLib\r
+\r
+[Guids]\r
+  gEfiBiosIdGuid\r
+  gEfiPlatformBootModeGuid\r
+  gEfiBoardFeaturesGuid\r
+  gItkDataVarGuid\r
+  gDmiDataGuid\r
+  gIdccDataHubGuid\r
+  gEfiPciLanInfoGuid\r
+  gEfiNormalSetupGuid\r
+  gEfiGlobalVariableGuid\r
+  gEfiEventExitBootServicesGuid\r
+  gEfiVlv2VariableGuid\r
+  gEfiSecureBootEnableDisableGuid\r
+\r
+[Protocols]\r
+  gEfiPciRootBridgeIoProtocolGuid    # CONSUMES  ## GUID\r
+  gEfiVariableArchProtocolGuid\r
+  gEfiVariableWriteArchProtocolGuid\r
+  gEfiHiiConfigAccessProtocolGuid\r
+  gEfiBootScriptSaveProtocolGuid\r
+  gEfiCpuIoProtocolGuid\r
+  gEfiDevicePathProtocolGuid\r
+  gEfiDiskInfoProtocolGuid\r
+  gEfiPs2PolicyProtocolGuid\r
+  gEfiIsaAcpiProtocolGuid\r
+  gEfiDataHubProtocolGuid\r
+  gEfiPciIoProtocolGuid\r
+  gDxePchPlatformPolicyProtocolGuid\r
+  gEfiTpmMpDriverProtocolGuid\r
+  gEfiLpcWpce791PolicyProtocolGuid\r
+  gUsbPolicyGuid\r
+  gEfiSpeakerInterfaceProtocolGuid\r
+  gDxeVlvPlatformPolicyGuid\r
+  gEfiSmbiosSlotPopulationGuid\r
+  gObservableProtocolGuid\r
+  gEfiCk505ClockPlatformInfoGuid\r
+  gEfiLpcWpc83627PolicyProtocolGuid\r
+  gEfiTcoResetProtocolGuid\r
+  gEfiWatchdogTimerDriverProtocolGuid\r
+  gEfiPlatformIdeInitProtocolGuid\r
+  gEfiGlobalNvsAreaProtocolGuid\r
+  gEfiCpuIo2ProtocolGuid\r
+  gIgdOpRegionProtocolGuid\r
+\r
+[Pcd.common]\r
+  gPlatformModuleTokenSpaceGuid.PcdPBTNDisableInterval\r
+  gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress\r
+  gPlatformModuleTokenSpaceGuid.PcdFlashAreaBaseAddress\r
+  gPlatformModuleTokenSpaceGuid.PcdFlashMicroCodeAddress\r
+  gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdFastPS2Detection\r
+\r
+[Depex]\r
+  gEfiPciRootBridgeIoProtocolGuid     AND\r
+  gEfiVariableArchProtocolGuid        AND\r
+  gEfiVariableWriteArchProtocolGuid   AND\r
+  gEfiBootScriptSaveProtocolGuid      AND\r
+  gEfiCpuIoProtocolGuid               AND\r
+  gDxePchPlatformPolicyProtocolGuid   AND\r
+  gEfiGlobalNvsAreaProtocolGuid\r
+\r
+\r

diff --git a/Vlv2TbltDevicePkg/PlatformDxe/SensorVar.c b/Vlv2TbltDevicePkg/PlatformDxe/SensorVar.c
new file mode 100644 (file)
index 0000000..27f742b
--- /dev/null
+++ b/Vlv2TbltDevicePkg/PlatformDxe/SensorVar.c
@@ -0,0 +1,117 @@
+/** @file\r
+\r
+  Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+Module Name:\r
+\r
+\r
+  SensorVar.c\r
+\r
+Abstract:\r
+\r
+  Initialization for the Sensor Info variable.\r
+\r
+Revision History\r
+\r
+--*/\r
+\r
+#include "PlatformDxe.h"\r
+#include "Guid/SensorInfoVariable.h"\r
+\r
+//\r
+// Sensor Information (board specific)\r
+//\r
+\r
+#define TEMPERATURE_SENSORS_COUNT       4\r
+#define VOLTAGE_SENSORS_COUNT           6\r
+#define FAN_SENSORS_COUNT               4\r
+#define FAN_CONTROLLERS_COUNT           3\r
+\r
+TYPEDEF_TEMP_SENSOR_SECTION(TEMPERATURE_SENSORS_COUNT);\r
+TYPEDEF_VOLT_SENSOR_SECTION(VOLTAGE_SENSORS_COUNT);\r
+TYPEDEF_FAN_SENSOR_SECTION(FAN_SENSORS_COUNT);\r
+TYPEDEF_FAN_CONTROLLER_SECTION(FAN_CONTROLLERS_COUNT);\r
+TYPEDEF_SENSOR_INFO_VAR;\r
+\r
+SENSOR_INFO_VAR               mSensorInfoData =\r
+{\r
+         //\r
+    // Temperature Sensors\r
+    //\r
+    TEMPERATURE_SENSORS_COUNT,\r
+    {\r
+        { 0, 3, CPU_CORE_TEMPERATURE,            TRUE  },\r
+        { 0, 1, MOTHERBOARD_AMBIENT_TEMPERATURE, FALSE },\r
+        { 0, 2, VR_TEMPERATURE,                  FALSE },\r
+        { 0, 0, IOH_TEMPERATURE,                 FALSE }\r
+    },\r
+\r
+    //\r
+    // Voltage Sensors\r
+    //\r
+    VOLTAGE_SENSORS_COUNT,\r
+    {\r
+        { 0, 0, PLUS_12_VOLTS       },\r
+        { 0, 1, PLUS_5_VOLTS        },\r
+        { 0, 2, PLUS_3P3_VOLTS      },\r
+        { 0, 3, MCH_VCC_VOLTAGE     },\r
+        { 0, 4, CPU_1_VCCP_VOLTAGE  },\r
+        { 0, 5, CPU_VTT_VOLTAGE     }\r
+    },\r
+\r
+    //\r
+    // Fan Speed Sensors\r
+    //\r
+    FAN_SENSORS_COUNT,\r
+    {\r
+        { 0, 0, CPU_COOLING_FAN,    FAN_4WIRE,         0 },\r
+        { 0, 1, AUX_COOLING_FAN,    FAN_4WIRE,         1 },\r
+        { 0, 2, CHASSIS_INLET_FAN,  FAN_3WIRE_VOLTAGE, 1 },\r
+        { 0, 3, CHASSIS_OUTLET_FAN, FAN_3WIRE_VOLTAGE, 2 }\r
+    },\r
+\r
+    //\r
+    // Fan Speed Controllers\r
+    //\r
+    FAN_CONTROLLERS_COUNT,\r
+    {\r
+        { 0, 0, CPU_COOLING_FAN,     { 0, 0xff, 0xff, 0xff } },\r
+        { 0, 1, CHASSIS_COOLING_FAN, { 1,    2, 0xff, 0xff } },\r
+        { 0, 2, CHASSIS_COOLING_FAN, { 3, 0xff, 0xff, 0xff } }\r
+    }\r
+};\r
+\r
+/**\r
+\r
+  Write the Sensor Info variable if it does not already exist.\r
+\r
+**/\r
+VOID\r
+InitializeSensorInfoVariable (\r
+  )\r
+{\r
+  //\r
+  // Set the Sensor Info variable.  If it already exists and the data matches,\r
+  // the variable driver will simply return without writing; otherwise, the\r
+  // driver will write the variable.\r
+  //\r
+  gRT->SetVariable (\r
+         gEfiSensorInfoVarNameWithPassword,\r
+         &gEfiSensorInfoVarGuid,\r
+         EFI_VARIABLE_NON_VOLATILE |\r
+         EFI_VARIABLE_BOOTSERVICE_ACCESS |\r
+         EFI_VARIABLE_RUNTIME_ACCESS,\r
+         sizeof (SENSOR_INFO_VAR),\r
+         &mSensorInfoData\r
+         );\r
+}\r
+\r

diff --git a/Vlv2TbltDevicePkg/PlatformDxe/SioPlatformPolicy.c b/Vlv2TbltDevicePkg/PlatformDxe/SioPlatformPolicy.c
new file mode 100644 (file)
index 0000000..da00627
--- /dev/null
+++ b/Vlv2TbltDevicePkg/PlatformDxe/SioPlatformPolicy.c
@@ -0,0 +1,87 @@
+/** @file\r
+\r
+  Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+Module Name:\r
+\r
+\r
+  SioPlatformPolicy.c\r
+\r
+Abstract:\r
+\r
+  Sio Platform Policy Setting.\r
+\r
+\r
+--*/\r
+\r
+#include "PlatformDxe.h"\r
+#include <Protocol/LpcWpc83627Policy.h>\r
+\r
+\r
+EFI_WPC83627_POLICY_PROTOCOL  mSio83627PolicyData = {\r
+  { EFI_WPC83627_COM1_ENABLE,       // Com1\r
+    EFI_WPC83627_LPT1_ENABLE,       // Lpt1\r
+    EFI_WPC83627_FDD_DISABLE,       // Floppy\r
+    EFI_WPC83627_FDD_WRITE_ENABLE,  // FloppyWriteProtect\r
+    EFI_WPC83627_RESERVED_DEFAULT,  // Port80\r
+    EFI_WPC83627_ECIR_DISABLE,      // CIR\r
+    EFI_WPC83627_PS2_KBC_ENABLE,    // Ps2Keyboard\r
+    EFI_WPC83627_RESERVED_DEFAULT,  // Ps2Mouse\r
+    EFI_WPC83627_COM2_ENABLE,       // Com2\r
+    EFI_WPC83627_COM3_ENABLE,       // Com3\r
+    EFI_WPC83627_COM4_ENABLE,       // Com4\r
+    EFI_WPC83627_RESERVED_DEFAULT,  // Dac\r
+    0x00                            // Rsvd\r
+    },\r
+  LptModeEcp,                       // LptMode\r
+};\r
+\r
+/**\r
+\r
+  Publish the platform SIO policy setting.\r
+\r
+  @retval EFI_SUCCESS\r
+\r
+**/\r
+VOID\r
+InitSioPlatformPolicy(\r
+  )\r
+{\r
+\r
+  EFI_HANDLE              Handle;\r
+  EFI_STATUS              Status;\r
+\r
+  Handle = NULL;\r
+\r
+  if((mSystemConfiguration.Serial) || (mBoardFeatures & B_BOARD_FEATURES_SIO_NO_COM1)) {\r
+    mSio83627PolicyData.DeviceEnables.Com1 = EFI_WPC83627_COM1_DISABLE;\r
+  }\r
+\r
+  if((mSystemConfiguration.Serial2) || ((mBoardFeatures & B_BOARD_FEATURES_SIO_COM2)==0)) {\r
+    mSio83627PolicyData.DeviceEnables.Com2 = EFI_WPC83627_COM2_DISABLE;\r
+  }\r
+\r
+  mSio83627PolicyData.LptMode = mSystemConfiguration.ParallelMode;\r
+  if((!mSystemConfiguration.Parallel) || (mBoardFeatures & B_BOARD_FEATURES_SIO_NO_PARALLEL)) {\r
+    mSio83627PolicyData.DeviceEnables.Lpt1 = EFI_WPC83627_LPT1_DISABLE;\r
+  }\r
+\r
+  Status = gBS->InstallProtocolInterface (\r
+                  &Handle,\r
+                  &gEfiLpcWpc83627PolicyProtocolGuid,\r
+                  EFI_NATIVE_INTERFACE,\r
+                  &mSio83627PolicyData\r
+                  );\r
+  ASSERT_EFI_ERROR(Status);\r
+\r
+}\r
+\r

diff --git a/Vlv2TbltDevicePkg/PlatformDxe/SlotConfig.c b/Vlv2TbltDevicePkg/PlatformDxe/SlotConfig.c
new file mode 100644 (file)
index 0000000..c0c7526
--- /dev/null
+++ b/Vlv2TbltDevicePkg/PlatformDxe/SlotConfig.c
@@ -0,0 +1,153 @@
+/** @file\r
+\r
+  Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+Module Name:\r
+\r
+  SlotConfig.c\r
+\r
+Abstract:\r
+\r
+  Sets platform/SKU specific expansion slot information.\r
+\r
+\r
+\r
+--*/\r
+#include "SlotConfig.h"\r
+\r
+//\r
+// Implementation\r
+//\r
+VOID\r
+InitializeSlotInfo (\r
+  )\r
+{\r
+  UINT16                              BusSaveState;\r
+  UINT16                              Vendor;\r
+  UINT8                               CurrentBus;\r
+  UINTN                               i;\r
+  UINTN                               j;\r
+  EFI_HANDLE                          Handle;\r
+  EFI_STATUS                          Status;\r
+  BOOLEAN                             RunNext;\r
+\r
+  //\r
+  // Loop through the slot table and see if any slots have cards in them\r
+  //\r
+  for (i = 0; i < mSlotBridgeTableSize; i++) {\r
+    //\r
+    // Initialize variable\r
+    //\r
+    RunNext = FALSE;\r
+\r
+    //\r
+    // Hide mini PCIe slots per SKU\r
+    //\r
+    for (j = 0; j < mSlotInformation.NumberOfEntries; j++) {\r
+      if (mSlotInformation.SlotEntries[j].SmbiosSlotId == mSlotBridgeTable[i].SmbiosSlotId) {\r
+        if ((mSlotInformation.SlotEntries[j].SmbiosSlotId == 0x02) &&\r
+            (mBoardFeatures & B_BOARD_FEATURES_NO_MINIPCIE)\r
+          ) {\r
+          mSlotInformation.SlotEntries[j].Disabled = TRUE;\r
+          RunNext = TRUE;\r
+        }\r
+        break;\r
+      }\r
+    }\r
+\r
+    if (RunNext) {\r
+      //\r
+      // Skip slot device detection since the slot is disabled.\r
+      //\r
+      continue;\r
+    }\r
+\r
+    //\r
+    // Check to see if the bridge has a bus number and assign one if not\r
+    //\r
+    BusSaveState = MmPci16 (\r
+      0,\r
+      mSlotBridgeTable[i].Bus,\r
+      mSlotBridgeTable[i].Dev,\r
+      mSlotBridgeTable[i].Function,\r
+      PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET\r
+                            );\r
+    if (BusSaveState == 0) {\r
+      //\r
+      // Assign temp bus number\r
+      //\r
+      MmPci16 (\r
+        0,\r
+        mSlotBridgeTable[i].Bus,\r
+        mSlotBridgeTable[i].Dev,\r
+        mSlotBridgeTable[i].Function,\r
+        PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET\r
+        ) = DEF_BUS_CONFIG;\r
+      CurrentBus = DEF_BUS;\r
+    } else if (BusSaveState == 0xFFFF) {\r
+      //\r
+      // Bridge is disabled so continue with next entry in the table\r
+      //\r
+      continue;\r
+    } else {\r
+      //\r
+      // Use existing bus number\r
+      //\r
+      CurrentBus = (UINT8) BusSaveState & 0xFF;\r
+    }\r
+\r
+    //\r
+    // Check to see if a device is behind the bridge\r
+    //\r
+    Vendor = MmPci16 (\r
+               0,\r
+               CurrentBus,\r
+               mSlotBridgeTable[i].TargetDevice,\r
+               0,\r
+               0\r
+               );\r
+    if (Vendor != 0xFFFF) {\r
+      //\r
+      // Device found so make sure the slot is marked that way\r
+      //\r
+      for (j = 0; j < mSlotInformation.NumberOfEntries; j++) {\r
+        if (mSlotInformation.SlotEntries[j].SmbiosSlotId == mSlotBridgeTable[i].SmbiosSlotId) {\r
+          mSlotInformation.SlotEntries[j].InUse = TRUE;\r
+          break;\r
+        }\r
+      }\r
+    }\r
+\r
+    //\r
+    // Restore previous bus information\r
+    //\r
+    if (BusSaveState == 0) {\r
+      MmPci16 (\r
+        0,\r
+        mSlotBridgeTable[i].Bus,\r
+        mSlotBridgeTable[i].Dev,\r
+        mSlotBridgeTable[i].Function,\r
+        PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET\r
+        ) = 0;\r
+    }\r
+  }\r
+\r
+  Handle = NULL;\r
+  Status = gBS->InstallProtocolInterface (\r
+                  &Handle,\r
+                  &gEfiSmbiosSlotPopulationGuid,\r
+                  EFI_NATIVE_INTERFACE,\r
+                  &mSlotInformation\r
+                  );\r
+  ASSERT_EFI_ERROR(Status);\r
+\r
+}\r

diff --git a/Vlv2TbltDevicePkg/PlatformDxe/SlotConfig.h b/Vlv2TbltDevicePkg/PlatformDxe/SlotConfig.h
new file mode 100644 (file)
index 0000000..97380db
--- /dev/null
+++ b/Vlv2TbltDevicePkg/PlatformDxe/SlotConfig.h
@@ -0,0 +1,85 @@
+/*++\r
+\r
+  Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+Module Name:\r
+\r
+  SlotConfig.c\r
+\r
+Abstract:\r
+\r
+  Sets platform/SKU specific expansion slot information.\r
+\r
+\r
+\r
+\r
+--*/\r
+\r
+#include "PlatformDxe.h"\r
+#include <Protocol/SmbiosSlotPopulation.h>\r
+#include <IndustryStandard/Pci22.h>\r
+\r
+\r
+//\r
+// Default bus number for the bridge\r
+//\r
+#define DEF_BUS_CONFIG  0x0101\r
+#define DEF_BUS         0x01\r
+\r
+//\r
+// Data structures for slot information\r
+//\r
+typedef struct {\r
+  UINT16  SmbiosSlotId;\r
+  UINT8   Bus;\r
+  UINT8   Dev;\r
+  UINT8   Function;\r
+  UINT8   TargetDevice;\r
+} EFI_PCI_SLOT_BRIDGE_INFO;\r
+\r
+//\r
+// Product specific bridge to slot routing information\r
+//\r
+EFI_PCI_SLOT_BRIDGE_INFO mSlotBridgeTable[] = {\r
+  {\r
+    0x01,             //PCIe x1 ICH (Bridge B0:D28:F1)\r
+    DEFAULT_PCI_BUS_NUMBER_PCH,\r
+    PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORTS,\r
+    PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_2,\r
+    0\r
+  }\r
+};\r
+\r
+UINTN mSlotBridgeTableSize =\r
+  sizeof(mSlotBridgeTable) / sizeof(EFI_PCI_SLOT_BRIDGE_INFO);\r
+\r
+//\r
+// Slot entry table for IBX RVP\r
+//\r
+EFI_SMBIOS_SLOT_ENTRY mSlotEntries[] = {\r
+  {0x06, FALSE, TRUE},    // PCIe x16 Slot 1 (NOT USED)\r
+  {0x04, FALSE, TRUE},    // PCIe x16 Slot 2 (NOT USED)\r
+  {0x03, FALSE, TRUE},    // PCIe x4 Slot (NOT USED)\r
+  {0x02, FALSE, FALSE},   // Mini PCIe x1 Slot\r
+  {0x15, FALSE, TRUE},    // PCIe x1 Slot 2 (NOT USED)\r
+  {0x16, FALSE, TRUE},    // PCIe x1 Slot 3 (NOT USED)\r
+  {0x07, FALSE, FALSE},   // PCI Slot 1\r
+  {0x18, FALSE, TRUE},    // PCI Slot 2 (NOT USED)\r
+  {0x17, FALSE, TRUE},    // PCI Slot 3 (NOT USED)\r
+};\r
+\r
+EFI_SMBIOS_SLOT_POPULATION_INFO mSlotInformation = {\r
+  sizeof(mSlotEntries) / sizeof(EFI_SMBIOS_SLOT_ENTRY),\r
+  mSlotEntries\r
+};\r
+\r
+\r

diff --git a/Vlv2TbltDevicePkg/PlatformGopPolicy/PlatformGopPolicy.c b/Vlv2TbltDevicePkg/PlatformGopPolicy/PlatformGopPolicy.c
new file mode 100644 (file)
index 0000000..59c73c6
--- /dev/null
+++ b/Vlv2TbltDevicePkg/PlatformGopPolicy/PlatformGopPolicy.c
@@ -0,0 +1,196 @@
+/*++\r
+\r
+Copyright (c)  1999  - 2014, Intel Corporation. All rights reserved\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+--*/\r
+\r
+/** @file\r
+**/\r
+\r
+#include <Library/BaseMemoryLib.h>\r
+#include <Library/DebugLib.h>\r
+#include <Protocol/FirmwareVolume2.h>\r
+#include <Protocol/PlatformGopPolicy.h>\r
+\r
+#include <Guid/SetupVariable.h>\r
+#include <SetupMode.h>\r
+#include <Library/UefiRuntimeServicesTableLib.h>\r
+\r
+EFI_BOOT_SERVICES   *gBS;\r
+\r
+\r
+PLATFORM_GOP_POLICY_PROTOCOL  mPlatformGOPPolicy;\r
+\r
+//\r
+// Function implementations\r
+//\r
+\r
+/**\r
+  The function will excute with as the platform policy, and gives\r
+  the Platform Lid Status. IBV/OEM can customize this code for their specific\r
+  policy action.\r
+\r
+  @param CurrentLidStatus  Gives the current LID Status\r
+\r
+  @retval EFI_SUCCESS.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+GetPlatformLidStatus (\r
+   OUT LID_STATUS *CurrentLidStatus\r
+)\r
+{\r
+  *CurrentLidStatus = LidOpen;\r
+\r
+  return EFI_SUCCESS;\r
+}\r
+\r
+/**\r
+  The function will excute and gives the Video Bios Table Size and Address.\r
+\r
+  @param VbtAddress  Gives the Physical Address of Video BIOS Table\r
+\r
+  @param VbtSize     Gives the Size of Video BIOS Table\r
+\r
+  @retval EFI_STATUS.\r
+\r
+**/\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+GetVbtData (\r
+   OUT EFI_PHYSICAL_ADDRESS *VbtAddress,\r
+   OUT UINT32 *VbtSize\r
+)\r
+{\r
+  EFI_STATUS                    Status;\r
+  UINTN                         FvProtocolCount;\r
+  EFI_HANDLE                    *FvHandles;\r
+  EFI_FIRMWARE_VOLUME2_PROTOCOL  *Fv;\r
+  UINTN                         Index;\r
+  UINT32                        AuthenticationStatus;\r
+\r
+  UINT8                         *Buffer;\r
+  UINTN                         VbtBufferSize;\r
+\r
+  Buffer = 0;\r
+  FvHandles       = NULL;\r
+\r
+  if (VbtAddress == NULL || VbtSize == NULL){\r
+    return EFI_INVALID_PARAMETER;\r
+  }\r
+  Status = gBS->LocateHandleBuffer (\r
+                  ByProtocol,\r
+                  &gEfiFirmwareVolume2ProtocolGuid,\r
+                  NULL,\r
+                  &FvProtocolCount,\r
+                  &FvHandles\r
+                  );\r
+\r
+  if (!EFI_ERROR (Status)) {\r
+    for (Index = 0; Index < FvProtocolCount; Index++) {\r
+      Status = gBS->HandleProtocol (\r
+                      FvHandles[Index],\r
+                      &gEfiFirmwareVolume2ProtocolGuid,\r
+                      (VOID **) &Fv\r
+                      );\r
+      VbtBufferSize = 0;\r
+      Status = Fv->ReadSection (\r
+                     Fv,\r
+                     &gBmpImageGuid,\r
+                     EFI_SECTION_RAW,\r
+                     0,\r
+                    (void **)&Buffer,\r
+                     &VbtBufferSize,\r
+                     &AuthenticationStatus\r
+                     );\r
+\r
+      if (!EFI_ERROR (Status)) {\r
+        *VbtAddress = (EFI_PHYSICAL_ADDRESS)(UINTN)Buffer;\r
+        *VbtSize = (UINT32)VbtBufferSize;\r
+        Status = EFI_SUCCESS;\r
+        break;\r
+      }\r
+    }\r
+  } else {\r
+    Status = EFI_NOT_FOUND;\r
+  }\r
+\r
+  if (FvHandles != NULL) {\r
+    gBS->FreePool (FvHandles);\r
+    FvHandles = NULL;\r
+  }\r
+\r
+  return Status;\r
+}\r
+\r
+/**\r
+  Entry point for the Platform GOP Policy Driver.\r
+\r
+  @param ImageHandle       Image handle of this driver.\r
+  @param SystemTable       Global system service table.\r
+\r
+  @retval EFI_SUCCESS           Initialization complete.\r
+  @retval EFI_OUT_OF_RESOURCES  Do not have enough resources to initialize the driver.\r
+\r
+**/\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+PlatformGOPPolicyEntryPoint (\r
+  IN EFI_HANDLE       ImageHandle,\r
+  IN EFI_SYSTEM_TABLE *SystemTable\r
+  )\r
+\r
+{\r
+  EFI_STATUS  Status = EFI_SUCCESS;\r
+  SYSTEM_CONFIGURATION          SystemConfiguration;\r
+  UINTN       VarSize;\r
+\r
+\r
+  gBS = SystemTable->BootServices;\r
+\r
+  gBS->SetMem (\r
+         &mPlatformGOPPolicy,\r
+         sizeof (PLATFORM_GOP_POLICY_PROTOCOL),\r
+         0\r
+         );\r
+\r
+  mPlatformGOPPolicy.Revision                = PLATFORM_GOP_POLICY_PROTOCOL_REVISION_01;\r
+  mPlatformGOPPolicy.GetPlatformLidStatus    = GetPlatformLidStatus;\r
+  mPlatformGOPPolicy.GetVbtData              = GetVbtData;\r
+\r
+  //\r
+  // Install protocol to allow access to this Policy.\r
+  //\r
+  VarSize = sizeof(SYSTEM_CONFIGURATION);\r
+  Status = gRT->GetVariable(\r
+                  L"Setup",\r
+                  &gEfiNormalSetupGuid,\r
+                  NULL,\r
+                  &VarSize,\r
+                  &SystemConfiguration\r
+                  );\r
+  ASSERT_EFI_ERROR(Status);\r
+  if (SystemConfiguration.GOPEnable == 1)\r
+  {\r
+  Status = gBS->InstallMultipleProtocolInterfaces (\r
+                  &ImageHandle,\r
+                  &gPlatformGOPPolicyGuid,\r
+                  &mPlatformGOPPolicy,\r
+                  NULL\r
+                  );\r
+  }\r
+\r
+  return Status;\r
+}\r

diff --git a/Vlv2TbltDevicePkg/PlatformGopPolicy/PlatformGopPolicy.inf b/Vlv2TbltDevicePkg/PlatformGopPolicy/PlatformGopPolicy.inf
new file mode 100644 (file)
index 0000000..6fcf93b
--- /dev/null
+++ b/Vlv2TbltDevicePkg/PlatformGopPolicy/PlatformGopPolicy.inf
@@ -0,0 +1,56 @@
+#\r
+#\r
+# Copyright (c)  1999  - 2014, Intel Corporation. All rights reserved\r
+#                                                                                  \r\r
+# This program and the accompanying materials are licensed and made available under\r\r
+# the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+# The full text of the license may be found at                                     \r\r
+# http://opensource.org/licenses/bsd-license.php.                                  \r\r
+#                                                                                  \r\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+#                                                                                  \r\r
+#\r
+#\r
+##\r
+\r
+\r
+[Defines]\r
+  INF_VERSION                    = 0x00010005\r
+  BASE_NAME                      = PlatformGOPPolicy\r
+  FILE_GUID                      = 9737D7CA-D869-45e5-A5EF-75D9438688DE\r
+  MODULE_TYPE                    = DXE_DRIVER\r
+  VERSION_STRING                 = 1.0\r
+  ENTRY_POINT                    = PlatformGOPPolicyEntryPoint\r
+\r
+#\r
+# The following information is for reference only and not required by the build tools.\r
+#\r
+#  VALID_ARCHITECTURES           = IA32\r
+#\r
+\r
+[Sources.common]\r
+  PlatformGopPolicy.c\r
+\r
+[Packages]\r
+  MdePkg/MdePkg.dec\r
+  IntelFrameworkPkg/IntelFrameworkPkg.dec\r
+  Vlv2TbltDevicePkg/PlatformPkg.dec\r
+[LibraryClasses]\r
+  BaseLib\r
+  DebugLib\r
+  UefiDriverEntryPoint\r
+  UefiRuntimeServicesTableLib\r
+#  DxeKscLib\r
+\r
+[Guids]\r
+  gBmpImageGuid\r
+  gEfiNormalSetupGuid\r
+\r
+[Protocols]\r
+  gEfiCpuIoProtocolGuid\r
+  gEfiFirmwareVolume2ProtocolGuid\r
+  gPlatformGOPPolicyGuid\r
+\r
+[Depex]\r
+  gEfiCpuIoProtocolGuid AND gEfiVariableArchProtocolGuid\r

diff --git a/Vlv2TbltDevicePkg/PlatformInfoDxe/PlatformInfoDxe.c b/Vlv2TbltDevicePkg/PlatformInfoDxe/PlatformInfoDxe.c
new file mode 100644 (file)
index 0000000..6bf2762
--- /dev/null
+++ b/Vlv2TbltDevicePkg/PlatformInfoDxe/PlatformInfoDxe.c
@@ -0,0 +1,161 @@
+/** @file\r
+\r
+  Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+Module Name:\r
+\r
+  PlatformInfoDxe.c\r
+\r
+Abstract:\r
+  Platform Info driver to public platform related HOB data\r
+\r
+--*/\r
+\r
+#include "PlatformInfoDxe.h"\r
+\r
+/**\r
+  Entry point for the driver.\r
+\r
+  This routine get the platform HOB data from PEI and publish\r
+  as Platform Info variable that can be accessed during boot service and\r
+  runtime.\r
+\r
+  @param ImageHandle    Image Handle.\r
+  @param SystemTable    EFI System Table.\r
+\r
+  @retval Status        Function execution status.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+PlatformInfoInit (\r
+  IN EFI_HANDLE                         ImageHandle,\r
+  IN EFI_SYSTEM_TABLE                   *SystemTable\r
+  )\r
+{\r
+  EFI_STATUS                  Status;\r
+  EFI_PLATFORM_INFO_HOB       *PlatformInfoHobPtr;\r
+  EFI_PEI_HOB_POINTERS        GuidHob;\r
+  EFI_PLATFORM_INFO_HOB       TmpHob;\r
+  UINTN                       VarSize;\r
+  EFI_OS_SELECTION_HOB        *OsSlectionHobPtr;\r
+  UINT8                       Selection;\r
+  SYSTEM_CONFIGURATION        SystemConfiguration;\r
+  UINT8                       *LpssDataHobPtr;\r
+  UINT8                       *LpssDataVarPtr;\r
+  UINTN                       i;\r
+\r
+  VarSize = sizeof(SYSTEM_CONFIGURATION);\r
+  Status = gRT->GetVariable(\r
+                  NORMAL_SETUP_NAME,\r
+                  &gEfiNormalSetupGuid,\r
+                  NULL,\r
+                  &VarSize,\r
+                  &SystemConfiguration\r
+                  );\r
+\r
+  VarSize = sizeof(Selection);\r
+  Status = gRT->GetVariable(\r
+                  L"OsSelection",\r
+                  &gOsSelectionVariableGuid,\r
+                  NULL,\r
+                  &VarSize,\r
+                  &Selection\r
+                  );\r
+\r
+  if (EFI_ERROR(Status)) {\r
+    Selection = SystemConfiguration.ReservedO;\r
+    Status = gRT->SetVariable (\r
+                    L"OsSelection",\r
+                    &gOsSelectionVariableGuid,\r
+                    EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS | EFI_VARIABLE_NON_VOLATILE,\r
+                    sizeof(Selection),\r
+                    &Selection\r
+                    );\r
+  }\r
+\r
+  GuidHob.Raw = GetHobList ();\r
+  if (GuidHob.Raw != NULL) {\r
+    if ((GuidHob.Raw = GetNextGuidHob (&gOsSelectionVariableGuid, GuidHob.Raw)) != NULL) {\r
+      OsSlectionHobPtr = GET_GUID_HOB_DATA (GuidHob.Guid);\r
+\r
+      if (OsSlectionHobPtr->OsSelectionChanged) {\r
+        SystemConfiguration.ReservedO = OsSlectionHobPtr->OsSelection;\r
+\r
+        //\r
+        // Load Audio default configuration\r
+        //\r
+        SystemConfiguration.Lpe         = OsSlectionHobPtr->Lpe;\r
+        SystemConfiguration.PchAzalia   = OsSlectionHobPtr->PchAzalia;\r
+\r
+        //\r
+        // Load LPSS and SCC default configurations\r
+        //\r
+        LpssDataHobPtr = &OsSlectionHobPtr->LpssData.LpssPciModeEnabled;\r
+        LpssDataVarPtr = &SystemConfiguration.LpssPciModeEnabled;\r
+        for (i = 0; i < sizeof(EFI_PLATFORM_LPSS_DATA); i++) {\r
+          *LpssDataVarPtr = *LpssDataHobPtr;\r
+          LpssDataVarPtr++;\r
+          LpssDataHobPtr++;\r
+        }\r
+\r
+        SystemConfiguration.GOPEnable = TRUE;\r
+\r
+        Status = gRT->SetVariable (\r
+                        NORMAL_SETUP_NAME,\r
+                        &gEfiNormalSetupGuid,\r
+                        EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS | EFI_VARIABLE_NON_VOLATILE,\r
+                        sizeof(SYSTEM_CONFIGURATION),\r
+                        &SystemConfiguration\r
+                        );\r
+        ASSERT_EFI_ERROR (Status);\r
+      }\r
+    }\r
+  }\r
+\r
+  GuidHob.Raw = GetHobList ();\r
+  if (GuidHob.Raw == NULL) {\r
+       return EFI_NOT_FOUND;\r
+  }\r
+\r
+  if ((GuidHob.Raw = GetNextGuidHob (&gEfiPlatformInfoGuid, GuidHob.Raw)) != NULL) {\r
+    PlatformInfoHobPtr = GET_GUID_HOB_DATA (GuidHob.Guid);\r
+    VarSize = sizeof(EFI_PLATFORM_INFO_HOB);\r
+    Status = gRT->GetVariable(\r
+                    L"PlatformInfo",\r
+                    &gEfiVlv2VariableGuid,\r
+                    NULL,\r
+                    &VarSize,\r
+                    &TmpHob\r
+                    );\r
+\r
+    if (EFI_ERROR(Status) || CompareMem (&TmpHob, PlatformInfoHobPtr, VarSize)) {\r
+\r
+      //\r
+      // Write the Platform Info to volatile memory\r
+      //\r
+      Status = gRT->SetVariable(\r
+                      L"PlatformInfo",\r
+                      &gEfiVlv2VariableGuid,\r
+                      EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS | EFI_VARIABLE_NON_VOLATILE,\r
+                      sizeof(EFI_PLATFORM_INFO_HOB),\r
+                      PlatformInfoHobPtr\r
+                      );\r
+      if (EFI_ERROR(Status)) {\r
+        return Status;\r
+      }\r
+    }\r
+  }\r
+\r
+  return EFI_SUCCESS;\r
+}\r
+\r

diff --git a/Vlv2TbltDevicePkg/PlatformInfoDxe/PlatformInfoDxe.h b/Vlv2TbltDevicePkg/PlatformInfoDxe/PlatformInfoDxe.h
new file mode 100644 (file)
index 0000000..717d0c9
--- /dev/null
+++ b/Vlv2TbltDevicePkg/PlatformInfoDxe/PlatformInfoDxe.h
@@ -0,0 +1,35 @@
+/*++\r
+\r
+  Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+Module Name:\r
+  PlatformInfoDxe.h\r
+\r
+Abstract:\r
+  Platform Info Driver.\r
+\r
+--*/\r
+\r
+#ifndef _PLATFORM_INFO_DRIVER_H_\r
+#define _PLATFORM_INFO_DRIVER_H_\r
+\r
+#include <PiDxe.h>\r
+#include <Library/HobLib.h>\r
+#include <Guid/PlatformInfo.h>\r
+#include <Guid/GlobalVariable.h>\r
+#include <Library/UefiRuntimeServicesTableLib.h>\r
+#include <Guid/Vlv2Variable.h>\r
+#include <Library/BaseMemoryLib.h>\r
+#include <SetupMode.h>\r
+#include <Guid/OsSelection.h>\r
+#include <Guid/SetupVariable.h>\r
+#endif\r

diff --git a/Vlv2TbltDevicePkg/PlatformInfoDxe/PlatformInfoDxe.inf b/Vlv2TbltDevicePkg/PlatformInfoDxe/PlatformInfoDxe.inf
new file mode 100644 (file)
index 0000000..e507d49
--- /dev/null
+++ b/Vlv2TbltDevicePkg/PlatformInfoDxe/PlatformInfoDxe.inf
@@ -0,0 +1,57 @@
+#\r
+#\r
+# Copyright (c)  1999  - 2014, Intel Corporation. All rights reserved\r
+#                                                                                  \r\r
+# This program and the accompanying materials are licensed and made available under\r\r
+# the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+# The full text of the license may be found at                                     \r\r
+# http://opensource.org/licenses/bsd-license.php.                                  \r\r
+#                                                                                  \r\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+#                                                                                  \r\r
+#\r
+#\r
+#  Module Name:\r
+#\r
+#   PlatformInfoDxe.inf\r
+#\r
+#  Abstract:\r
+#\r
+#\r
+--*/\r
+\r
+\r
+[defines]\r
+  INF_VERSION                    = 0x00010005\r
+  BASE_NAME                      = PlatformInfoDxe\r
+  FILE_GUID                      = 025F738B-4EBD-4d55-B728-5F421B601F1F\r
+  MODULE_TYPE                    = DXE_DRIVER\r
+  VERSION_STRING                 = 1.0\r
+  ENTRY_POINT                    = PlatformInfoInit\r
+\r
+[sources]\r
+  PlatformInfoDxe.c\r
+  PlatformInfoDxe.h\r
+\r
+[Guids]\r
+  gEfiAcpiVariableGuid                     # ALWAYS_CONSUMED\r
+  gEfiPlatformInfoGuid                     # ALWAYS_CONSUMED\r
+  gEfiVlv2VariableGuid\r
+  gEfiNormalSetupGuid\r
+  gOsSelectionVariableGuid\r
+\r
+[Packages]\r
+  MdePkg/MdePkg.dec\r
+  MdeModulePkg/MdeModulePkg.dec\r
+  Vlv2TbltDevicePkg/PlatformPkg.dec\r
+  Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec\r
+\r
+[LibraryClasses]\r
+  HobLib\r
+  UefiRuntimeServicesTableLib\r
+  UefiDriverEntryPoint\r
+  BaseMemoryLib\r
+\r
+[Depex]\r
+  gEfiVariableArchProtocolGuid AND gEfiVariableWriteArchProtocolGuid\r

diff --git a/Vlv2TbltDevicePkg/PlatformInitPei/BootMode.c b/Vlv2TbltDevicePkg/PlatformInitPei/BootMode.c
new file mode 100644 (file)
index 0000000..174d8e9
--- /dev/null
+++ b/Vlv2TbltDevicePkg/PlatformInitPei/BootMode.c
@@ -0,0 +1,426 @@
+/** @file\r
+\r
+  Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+Module Name:\r
+\r
+\r
+  BootMode.c\r
+\r
+Abstract:\r
+\r
+  EFI PEIM to provide the platform support functionality on the Thurley.\r
+\r
+\r
+--*/\r
+\r
+#include "PlatformEarlyInit.h"\r
+\r
+\r
+#define NORMALMODE        0\r
+#define RECOVERYMODE      1\r
+#define SAFEMODE          2\r
+#define MANUFACTURINGMODE 3\r
+\r
+#define GPIO_SSUS_OFFSET    0x2000\r
+#define PMU_PWRBTN_B_OFFSET 0x88\r
+\r
+EFI_PEI_PPI_DESCRIPTOR  mPpiListRecoveryBootMode = {\r
+  (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),\r
+  &gEfiPeiBootInRecoveryModePpiGuid,\r
+  NULL\r
+};\r
+\r
+/**\r
+  Return the setting of the Bios configuration jumper\r
+\r
+  @param  VOID\r
+\r
+  @retval RECOVERYMODE       jumper set to recovery mode\r
+  @retval SAFEMODE           jumper set to config mode\r
+  @retval NORMALMODE         jumper in normal mode\r
+\r
+**/\r
+UINTN\r
+GetConfigJumper(\r
+    IN CONST EFI_PEI_SERVICES           **PeiServices,\r
+    IN OUT EFI_PLATFORM_INFO_HOB *PlatformInfoHob\r
+ )\r
+{\r
+  //\r
+  // Do the Forced recovery detection based on logic chart above\r
+  //\r
+  if (IsRecoveryJumper(PeiServices, PlatformInfoHob)) {\r
+    return RECOVERYMODE;\r
+  } else {\r
+    return NORMALMODE;\r
+  }\r
+}\r
+\r
+BOOLEAN\r
+CheckIfRecoveryMode(\r
+  IN CONST EFI_PEI_SERVICES           **PeiServices,\r
+  IN OUT EFI_PLATFORM_INFO_HOB *PlatformInfoHob\r
+ )\r
+{\r
+  if (GetConfigJumper(PeiServices, PlatformInfoHob) == RECOVERYMODE) {\r
+    return TRUE;\r
+  }\r
+  return FALSE;\r
+}\r
+\r
+BOOLEAN\r
+CheckIfSafeMode(\r
+  IN CONST EFI_PEI_SERVICES           **PeiServices,\r
+  IN OUT EFI_PLATFORM_INFO_HOB *PlatformInfoHob\r
+ )\r
+{\r
+  if (GetConfigJumper(PeiServices, PlatformInfoHob) == SAFEMODE) {\r
+    return TRUE;\r
+  }\r
+  return FALSE;\r
+}\r
+\r
+BOOLEAN\r
+CheckIfManufacturingMode (\r
+  IN CONST EFI_PEI_SERVICES  **PeiServices\r
+ )\r
+{\r
+  EFI_STATUS                  Status;\r
+  EFI_PEI_READ_ONLY_VARIABLE2_PPI  *Variable;\r
+  UINT32                      Attributes;\r
+  UINTN                       DataSize;\r
+  CHAR16                      VarName[] = MFGMODE_VARIABLE_NAME;\r
+  UINT8                       MfgMode;\r
+\r
+  Status = (*PeiServices)->LocatePpi (\r
+                             PeiServices,\r
+                             &gEfiPeiReadOnlyVariable2PpiGuid,\r
+                             0,\r
+                             NULL,\r
+                             (void **)&Variable\r
+                             );\r
+  ASSERT_EFI_ERROR (Status);\r
+\r
+  //\r
+  // Check if SW MMJ mode\r
+  //\r
+  Attributes = (EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS);\r
+  DataSize = sizeof (MFG_MODE_VAR);\r
+\r
+  Status = Variable->GetVariable (\r
+                       Variable,\r
+                       VarName,\r
+                       &gMfgModeVariableGuid,\r
+                       &Attributes,\r
+                       &DataSize,\r
+                       &MfgMode\r
+                       );\r
+  if (!(EFI_ERROR (Status))) {\r
+    return TRUE;\r
+  }\r
+  return FALSE;\r
+}\r
+\r
+EFI_STATUS\r
+UpdateBootMode (\r
+  IN CONST EFI_PEI_SERVICES                       **PeiServices,\r
+  IN OUT EFI_PLATFORM_INFO_HOB                    *PlatformInfoHob\r
+  )\r
+{\r
+  EFI_STATUS                        Status;\r
+  EFI_BOOT_MODE                     BootMode;\r
+  UINT16                            SleepType;\r
+  CHAR16                            *strBootMode;\r
+  PEI_CAPSULE_PPI                   *Capsule;\r
+  EFI_PEI_READ_ONLY_VARIABLE2_PPI   *Variable;\r
+  SYSTEM_CONFIGURATION              SystemConfiguration;\r
+  UINTN                             VarSize;\r
+  volatile UINT32                   GpioValue;\r
+  BOOLEAN                           IsFirstBoot;\r
+  UINT32                            Data32;\r
+\r
+  Status = (*PeiServices)->GetBootMode(\r
+                             PeiServices,\r
+                             &BootMode\r
+                             );\r
+  ASSERT_EFI_ERROR (Status);\r
+  if (BootMode  == BOOT_IN_RECOVERY_MODE){\r
+    return Status;\r
+  }\r
+  GetWakeupEventAndSaveToHob (PeiServices);\r
+\r
+  //\r
+  // Let's assume things are OK if not told otherwise\r
+  //\r
+  BootMode = BOOT_WITH_FULL_CONFIGURATION;\r
+\r
+  //\r
+  // When this boot is WDT reset, the system needs booting with CrashDump function eanbled.\r
+  //\r
+  Data32 = IoRead32 (ACPI_BASE_ADDRESS + R_PCH_TCO_STS);\r
+\r
+  //\r
+  // Check Power Button, click the power button, the system will boot in fast boot mode,\r
+  // if it is pressed and hold for a second, it will boot in FullConfiguration/setup mode.\r
+  //\r
+  GpioValue = MmioRead32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + PMU_PWRBTN_B_OFFSET);    // The value of GPIOS_16 (PMU_PWRBTN_B)\r
+  if (((GpioValue & BIT0) != 0)&&((Data32 & B_PCH_TCO_STS_SECOND_TO) != B_PCH_TCO_STS_SECOND_TO)){\r
+    IsFirstBoot = PcdGetBool(PcdBootState);\r
+    if (!IsFirstBoot){\r
+      VarSize = sizeof (SYSTEM_CONFIGURATION);\r
+      ZeroMem (&SystemConfiguration, sizeof (SYSTEM_CONFIGURATION));\r
+\r
+      Status = (*PeiServices)->LocatePpi (\r
+                                 PeiServices,\r
+                                 &gEfiPeiReadOnlyVariable2PpiGuid,\r
+                                 0,\r
+                                 NULL,\r
+                                          (void **)&Variable\r
+                                 );\r
+      ASSERT_EFI_ERROR (Status);\r
+\r
+      //\r
+      // Use normal setup default from NVRAM variable,\r
+      // the Platform Mode (manufacturing/safe/normal) is handle in PeiGetVariable.\r
+      //\r
+      VarSize = sizeof(SYSTEM_CONFIGURATION);\r
+      Status = Variable->GetVariable (\r
+                           Variable,\r
+                           L"Setup",\r
+                           &gEfiSetupVariableGuid,\r
+                           NULL,\r
+                           &VarSize,\r
+                           &SystemConfiguration\r
+                           );\r
+\r
+      if (SystemConfiguration.FastBoot == 1) {\r
+            BootMode = BOOT_WITH_MINIMAL_CONFIGURATION;\r
+      }\r
+    }\r
+  }\r
+\r
+  //\r
+  // Check if we need to boot in forced recovery mode\r
+  //\r
+  if (CheckIfRecoveryMode(PeiServices, PlatformInfoHob)) {\r
+    BootMode  = BOOT_IN_RECOVERY_MODE;\r
+  }\r
+\r
+  if (BootMode  == BOOT_IN_RECOVERY_MODE) {\r
+    Status = (*PeiServices)->InstallPpi (\r
+                               PeiServices,\r
+                               &mPpiListRecoveryBootMode\r
+                               );\r
+    ASSERT_EFI_ERROR (Status);\r
+  } else {\r
+    if (GetSleepTypeAfterWakeup (PeiServices, &SleepType)) {\r
+      switch (SleepType) {\r
+        case V_PCH_ACPI_PM1_CNT_S3:\r
+          BootMode = BOOT_ON_S3_RESUME;\r
+\r
+          //\r
+          // Determine if we're in capsule update mode\r
+          //\r
+          Status = (*PeiServices)->LocatePpi (\r
+                                     PeiServices,\r
+                                     &gPeiCapsulePpiGuid,\r
+                                     0,\r
+                                     NULL,\r
+                                     (void **)&Capsule\r
+                                     );\r
+\r
+          if (Status == EFI_SUCCESS) {\r
+            if (Capsule->CheckCapsuleUpdate ((EFI_PEI_SERVICES**)PeiServices) == EFI_SUCCESS) {\r
+              BootMode = BOOT_ON_FLASH_UPDATE;\r
+            }\r
+          }\r
+\r
+          break;\r
+\r
+        case V_PCH_ACPI_PM1_CNT_S4:\r
+          BootMode = BOOT_ON_S4_RESUME;\r
+          break;\r
+\r
+        case V_PCH_ACPI_PM1_CNT_S5:\r
+          BootMode = BOOT_ON_S5_RESUME;\r
+          break;\r
+      } // switch (SleepType)\r
+    }\r
+\r
+    //\r
+    // Check for Safe Mode\r
+    //\r
+  }\r
+\r
+  switch (BootMode) {\r
+    case BOOT_WITH_FULL_CONFIGURATION:\r
+      strBootMode = L"BOOT_WITH_FULL_CONFIGURATION";\r
+      break;\r
+    case BOOT_WITH_MINIMAL_CONFIGURATION:\r
+      strBootMode = L"BOOT_WITH_MINIMAL_CONFIGURATION";\r
+      break;\r
+    case BOOT_ASSUMING_NO_CONFIGURATION_CHANGES:\r
+      strBootMode = L"BOOT_ASSUMING_NO_CONFIGURATION_CHANGES";\r
+      break;\r
+    case BOOT_WITH_FULL_CONFIGURATION_PLUS_DIAGNOSTICS:\r
+      strBootMode = L"BOOT_WITH_FULL_CONFIGURATION_PLUS_DIAGNOSTICS";\r
+      break;\r
+    case BOOT_WITH_DEFAULT_SETTINGS:\r
+      strBootMode = L"BOOT_WITH_DEFAULT_SETTINGS";\r
+      break;\r
+    case BOOT_ON_S4_RESUME:\r
+      strBootMode = L"BOOT_ON_S4_RESUME";\r
+      break;\r
+    case BOOT_ON_S5_RESUME:\r
+      strBootMode = L"BOOT_ON_S5_RESUME";\r
+      break;\r
+    case BOOT_ON_S2_RESUME:\r
+      strBootMode = L"BOOT_ON_S2_RESUME";\r
+      break;\r
+    case BOOT_ON_S3_RESUME:\r
+      strBootMode = L"BOOT_ON_S3_RESUME";\r
+      break;\r
+    case BOOT_ON_FLASH_UPDATE:\r
+      strBootMode = L"BOOT_ON_FLASH_UPDATE";\r
+      break;\r
+    case BOOT_IN_RECOVERY_MODE:\r
+      strBootMode = L"BOOT_IN_RECOVERY_MODE";\r
+      break;\r
+    default:\r
+      strBootMode = L"Unknown boot mode";\r
+  } // switch (BootMode)\r
+\r
+  DEBUG ((EFI_D_ERROR, "Setting BootMode to %s\n", strBootMode));\r
+  Status = (*PeiServices)->SetBootMode(\r
+                             PeiServices,\r
+                             BootMode\r
+                             );\r
+  ASSERT_EFI_ERROR (Status);\r
+\r
+  return Status;\r
+}\r
+\r
+/**\r
+  Get sleep type after wakeup\r
+\r
+  @param PeiServices        Pointer to the PEI Service Table.\r
+  @param SleepType          Sleep type to be returned.\r
+\r
+  @retval TRUE              A wake event occured without power failure.\r
+  @retval FALSE             Power failure occured or not a wakeup.\r
+\r
+**/\r
+BOOLEAN\r
+GetSleepTypeAfterWakeup (\r
+  IN  CONST EFI_PEI_SERVICES          **PeiServices,\r
+  OUT UINT16                    *SleepType\r
+  )\r
+{\r
+  UINT16  Pm1Sts;\r
+  UINT16  Pm1Cnt;\r
+  UINT16  GenPmCon1;\r
+  GenPmCon1 = MmioRead16 (PMC_BASE_ADDRESS + R_PCH_PMC_GEN_PMCON_1);\r
+\r
+  //\r
+  // Read the ACPI registers\r
+  //\r
+  Pm1Sts  = IoRead16 (ACPI_BASE_ADDRESS + R_PCH_ACPI_PM1_STS);\r
+  Pm1Cnt  = IoRead16 (ACPI_BASE_ADDRESS + R_PCH_ACPI_PM1_CNT);\r
+\r
+  if ((GenPmCon1 & (B_PCH_PMC_GEN_PMCON_SUS_PWR_FLR | B_PCH_PMC_GEN_PMCON_GEN_RST_STS)) ||\r
+     (Pm1Sts & B_PCH_ACPI_PM1_STS_PRBTNOR)) {\r
+    //\r
+    // If power failure indicator, then don't attempt s3 resume.\r
+    // Clear PM1_CNT of S3 and set it to S5 as we just had a power failure, and memory has\r
+    // lost already.  This is to make sure no one will use PM1_CNT to check for S3 after\r
+    // power failure.\r
+    //\r
+    if ((Pm1Cnt & B_PCH_ACPI_PM1_CNT_SLP_TYP) == V_PCH_ACPI_PM1_CNT_S3) {\r
+      Pm1Cnt = ((Pm1Cnt & ~B_PCH_ACPI_PM1_CNT_SLP_TYP) | V_PCH_ACPI_PM1_CNT_S5);\r
+      IoWrite16 (ACPI_BASE_ADDRESS + R_PCH_ACPI_PM1_CNT, Pm1Cnt);\r
+    }\r
+    //\r
+    // Clear Wake Status (WAK_STS)\r
+    //\r
+    IoWrite16 ((ACPI_BASE_ADDRESS + R_PCH_ACPI_PM1_STS), B_PCH_ACPI_PM1_STS_WAK);\r
+   }\r
+  //\r
+  // Get sleep type if a wake event occurred and there is no power failure\r
+  //\r
+  if ((Pm1Cnt & B_PCH_ACPI_PM1_CNT_SLP_TYP) == V_PCH_ACPI_PM1_CNT_S3) {\r
+    *SleepType = Pm1Cnt & B_PCH_ACPI_PM1_CNT_SLP_TYP;\r
+    return TRUE;\r
+  } else if ((Pm1Cnt & B_PCH_ACPI_PM1_CNT_SLP_TYP) == V_PCH_ACPI_PM1_CNT_S4){\r
+    *SleepType = Pm1Cnt & B_PCH_ACPI_PM1_CNT_SLP_TYP;\r
+    return TRUE;\r
+  }\r
+  return FALSE;\r
+}\r
+\r
+VOID\r
+SetPlatformBootMode (\r
+  IN CONST EFI_PEI_SERVICES             **PeiServices,\r
+  IN OUT EFI_PLATFORM_INFO_HOB *PlatformInfoHob\r
+  )\r
+{\r
+  EFI_PLATFORM_SETUP_ID       PlatformSetupId;\r
+\r
+  ZeroMem(&PlatformSetupId, sizeof (EFI_PLATFORM_SETUP_ID));\r
+\r
+  CopyMem (&PlatformSetupId.SetupGuid,\r
+           &gEfiNormalSetupGuid,\r
+           sizeof (EFI_GUID));\r
+\r
+  if (CheckIfRecoveryMode(PeiServices, PlatformInfoHob)) {\r
+    //\r
+    // Recovery mode\r
+    //\r
+    CopyMem (&PlatformSetupId.SetupName,\r
+             SAFE_SETUP_NAME,\r
+             StrSize (SAFE_SETUP_NAME));\r
+    PlatformSetupId.PlatformBootMode = PLATFORM_RECOVERY_MODE;\r
+  } else if (CheckIfSafeMode(PeiServices, PlatformInfoHob)) {\r
+    //\r
+    // Safe mode also called config mode or maintenace mode.\r
+    //\r
+    CopyMem (&PlatformSetupId.SetupName,\r
+             SAFE_SETUP_NAME,\r
+             StrSize (SAFE_SETUP_NAME));\r
+    PlatformSetupId.PlatformBootMode = PLATFORM_SAFE_MODE;\r
+\r
+  } else if(0) { // else if (CheckIfManufacturingMode(PeiServices)) {\r
+    //\r
+    // Manufacturing mode\r
+    //\r
+    CopyMem (&PlatformSetupId.SetupName,\r
+             MANUFACTURE_SETUP_NAME,\r
+             StrSize (MANUFACTURE_SETUP_NAME));\r
+    PlatformSetupId.PlatformBootMode = PLATFORM_MANUFACTURING_MODE;\r
+\r
+  } else {\r
+    //\r
+    // Default to normal mode.\r
+    //\r
+    CopyMem (&PlatformSetupId.SetupName,\r
+             &NORMAL_SETUP_NAME,\r
+             StrSize (NORMAL_SETUP_NAME));\r
+    PlatformSetupId.PlatformBootMode = PLATFORM_NORMAL_MODE;\r
+  }\r
+\r
+  BuildGuidDataHob (\r
+    &gEfiPlatformBootModeGuid,\r
+    &PlatformSetupId,\r
+    sizeof (EFI_PLATFORM_SETUP_ID)\r
+    );\r
+  return;\r
+}\r

diff --git a/Vlv2TbltDevicePkg/PlatformInitPei/CpuInitPeim.c b/Vlv2TbltDevicePkg/PlatformInitPei/CpuInitPeim.c
new file mode 100644 (file)
index 0000000..f75bace
--- /dev/null
+++ b/Vlv2TbltDevicePkg/PlatformInitPei/CpuInitPeim.c
@@ -0,0 +1,49 @@
+/** @file\r
+\r
+  Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+Module Name:\r
+\r
+\r
+    CpuInitPeim.c\r
+\r
+Abstract:\r
+\r
+    Functions for LpcSio initilization\r
+    It is needed for early onboard LAN controller disable/enable in platform setup.\r
+\r
+--*/\r
+\r
+#include "PlatformEarlyInit.h"\r
+\r
+\r
+EFI_STATUS\r
+PlatformCpuInit (\r
+  IN CONST EFI_PEI_SERVICES            **PeiServices,\r
+  IN SYSTEM_CONFIGURATION        *SystemConfiguration,\r
+  IN EFI_PLATFORM_CPU_INFO       *PlatformCpuInfo\r
+  )\r
+{\r
+  BOOLEAN                     ResetRequired;\r
+\r
+  //\r
+  // Variable initialization\r
+  //\r
+  ResetRequired = FALSE;\r
+\r
+\r
+  if (ResetRequired) {\r
+    CpuOnlyReset(PeiServices);\r
+  }\r
+\r
+  return EFI_SUCCESS;\r
+}\r

diff --git a/Vlv2TbltDevicePkg/PlatformInitPei/Dimm.c b/Vlv2TbltDevicePkg/PlatformInitPei/Dimm.c
new file mode 100644 (file)
index 0000000..e4dd2d6
--- /dev/null
+++ b/Vlv2TbltDevicePkg/PlatformInitPei/Dimm.c
@@ -0,0 +1,324 @@
+/** @file\r
+\r
+  Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+Module Name:\r
+\r
+\r
+  Dimm.c\r
+\r
+Abstract:\r
+\r
+  PPI for reading SPD modules on DIMMs.\r
+\r
+--*/\r
+\r
+\r
+//\r
+// Header Files\r
+//\r
+#include "Platformearlyinit.h"\r
+\r
+#define DIMM_SOCKETS     4  // Total number of DIMM sockets allowed on\r
+                            //   the platform\r
+#define DIMM_SEGMENTS    1  // Total number of Segments Per DIMM.\r
+#define MEMORY_CHANNELS  2  // Total number of memory channels\r
+                            //   populated on the system board\r
+//\r
+// Prototypes\r
+//\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+GetDimmState (\r
+  IN      EFI_PEI_SERVICES        **PeiServices,\r
+  IN      PEI_PLATFORM_DIMM_PPI   *This,\r
+  IN      UINT8                   Dimm,\r
+  OUT     PEI_PLATFORM_DIMM_STATE *State\r
+  );\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+SetDimmState (\r
+  IN      EFI_PEI_SERVICES        **PeiServices,\r
+  IN      PEI_PLATFORM_DIMM_PPI   *This,\r
+  IN      UINT8                   Dimm,\r
+  IN      PEI_PLATFORM_DIMM_STATE *State\r
+  );\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+ReadSpd (\r
+  IN      EFI_PEI_SERVICES      **PeiServices,\r
+  IN      PEI_PLATFORM_DIMM_PPI *This,\r
+  IN      UINT8                 Dimm,\r
+  IN      UINT8                 Offset,\r
+  IN      UINTN                 Count,\r
+  IN OUT  UINT8                 *Buffer\r
+  );\r
+\r
+static PEI_PLATFORM_DIMM_PPI mGchDimmPpi = {\r
+  DIMM_SOCKETS,\r
+  DIMM_SEGMENTS,\r
+  MEMORY_CHANNELS,\r
+  GetDimmState,\r
+  SetDimmState,\r
+  ReadSpd\r
+};\r
+\r
+static EFI_PEI_PPI_DESCRIPTOR mPpiPlatformDimm = {\r
+  (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),\r
+  &gPeiPlatformDimmPpiGuid,\r
+  &mGchDimmPpi\r
+};\r
+\r
+\r
+//\r
+// Functions\r
+//\r
+\r
+/**\r
+  This function returns the current state of a single DIMM.  Present indicates\r
+  that the DIMM slot is physically populated.  Disabled indicates that the DIMM\r
+  should not be used.\r
+\r
+  @param PeiServices   PEI services table pointer\r
+  @param This          PPI pointer\r
+  @param Dimm          DIMM to read from\r
+  @param State         Pointer to a return buffer to be updated with the current state\r
+                       of the DIMM\r
+\r
+  @retval EFI_SUCCESS         The function completed successfully.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+GetDimmState (\r
+  IN      EFI_PEI_SERVICES        **PeiServices,\r
+  IN      PEI_PLATFORM_DIMM_PPI   *This,\r
+  IN      UINT8                   Dimm,\r
+  OUT     PEI_PLATFORM_DIMM_STATE *State\r
+  )\r
+{\r
+  EFI_STATUS                    Status;\r
+  UINT8                         Buffer;\r
+\r
+  PEI_ASSERT (PeiServices, (Dimm < This->DimmSockets));\r
+\r
+  //\r
+  // A failure here does not necessarily mean that no DIMM is present.\r
+  // Read a single byte.  All we care about is the return status.\r
+  //\r
+  Status = ReadSpd (\r
+             PeiServices,\r
+             This,\r
+             Dimm,\r
+             0,\r
+             1,\r
+             &Buffer\r
+             );\r
+\r
+  if (EFI_ERROR (Status)) {\r
+    State->Present = 0;\r
+  } else {\r
+    State->Present = 1;\r
+  }\r
+\r
+  //\r
+  // BUGBUG: Update to check platform variable when it is available\r
+  //\r
+  State->Disabled = 0;\r
+  State->Reserved = 0;\r
+\r
+  return EFI_SUCCESS;\r
+}\r
+\r
+/**\r
+\r
+  This function updates the state of a single DIMM.\r
+\r
+  @param PeiServices          PEI services table pointer\r
+  @param This                 PPI pointer\r
+  @param Dimm                 DIMM to set state for\r
+  @param State                Pointer to the state information to set.\r
+\r
+  @retval EFI_SUCCESS         The function completed successfully.\r
+  @retval EFI_UNSUPPORTED     The function is not supported.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+SetDimmState (\r
+  IN      EFI_PEI_SERVICES        **PeiServices,\r
+  IN      PEI_PLATFORM_DIMM_PPI   *This,\r
+  IN      UINT8                   Dimm,\r
+  IN      PEI_PLATFORM_DIMM_STATE *State\r
+  )\r
+{\r
+  return EFI_UNSUPPORTED;\r
+}\r
+\r
+/**\r
+  This function reads SPD information from a DIMM.\r
+\r
+  PeiServices   PEI services table pointer\r
+  This          PPI pointer\r
+  Dimm          DIMM to read from\r
+  Offset        Offset in DIMM\r
+  Count         Number of bytes\r
+  Buffer        Return buffer\r
+\r
+  @param EFI_SUCCESS              The function completed successfully.\r
+  @param EFI_DEVICE_ERROR         The DIMM being accessed reported a device error,\r
+                                  does not have an SPD module, or is not installed in\r
+                                  the system.\r
+  @retval EFI_TIMEOUT             Time out trying to read the SPD module.\r
+  @retval EFI_INVALID_PARAMETER   A parameter was outside the legal limits.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+ReadSpd (\r
+  IN      EFI_PEI_SERVICES      **PeiServices,\r
+  IN      PEI_PLATFORM_DIMM_PPI *This,\r
+  IN      UINT8                 Dimm,\r
+  IN      UINT8                 Offset,\r
+  IN      UINTN                 Count,\r
+  IN OUT  UINT8                 *Buffer\r
+  )\r
+{\r
+  EFI_STATUS                Status;\r
+  PEI_SMBUS_PPI             *Smbus;\r
+  UINTN                     Index;\r
+  UINTN                     Index1;\r
+  EFI_SMBUS_DEVICE_ADDRESS  SlaveAddress;\r
+  EFI_SMBUS_DEVICE_COMMAND  Command;\r
+  UINTN                     Length;\r
+\r
+  Status = (**PeiServices).LocatePpi (\r
+                             PeiServices,\r
+                             &gPeiSmbusPpiGuid,   // GUID\r
+                             0,                   // INSTANCE\r
+                             NULL,                // EFI_PEI_PPI_DESCRIPTOR\r
+                             &Smbus               // PPI\r
+                             );\r
+  ASSERT_PEI_ERROR (PeiServices, Status);\r
+\r
+  switch (Dimm) {\r
+  case 0:\r
+    SlaveAddress.SmbusDeviceAddress = SMBUS_ADDR_CH_A_1 >> 1;\r
+    break;\r
+  case 1:\r
+    SlaveAddress.SmbusDeviceAddress = SMBUS_ADDR_CH_A_2 >> 1;\r
+    break;\r
+  case 2:\r
+    SlaveAddress.SmbusDeviceAddress = SMBUS_ADDR_CH_B_1 >> 1;\r
+    break;\r
+  case 3:\r
+    SlaveAddress.SmbusDeviceAddress = SMBUS_ADDR_CH_B_2 >> 1;\r
+    break;\r
+  default:\r
+    return EFI_INVALID_PARAMETER;\r
+  }\r
+\r
+  Index = Count % 4;\r
+  if (Index != 0) {\r
+    //\r
+    // read the first serveral bytes to speed up following reading\r
+    //\r
+    for (Index1 = 0; Index1 < Index; Index1++) {\r
+      Length = 1;\r
+      Command = Offset + Index1;\r
+      Status = Smbus->Execute (\r
+                        PeiServices,\r
+                        Smbus,\r
+                        SlaveAddress,\r
+                        Command,\r
+                        EfiSmbusReadByte,\r
+                        FALSE,\r
+                        &Length,\r
+                        &Buffer[Index1]\r
+                        );\r
+      if (EFI_ERROR(Status)) {\r
+        return Status;\r
+      }\r
+    }\r
+  }\r
+\r
+  //\r
+  // Now collect all the remaining bytes on 4 bytes block\r
+  //\r
+  for (; Index < Count; Index += 2) {\r
+    Command = Index + Offset;\r
+    Length = 2;\r
+    Status = Smbus->Execute (\r
+                      PeiServices,\r
+                      Smbus,\r
+                      SlaveAddress,\r
+                      Command,\r
+                      EfiSmbusReadWord,\r
+                      FALSE,\r
+                      &Length,\r
+                      &Buffer[Index]\r
+                      );\r
+    if (EFI_ERROR(Status)) {\r
+      return Status;\r
+    }\r
+\r
+    Index += 2;\r
+    Command = Index + Offset;\r
+    Length = 2;\r
+    Status = Smbus->Execute (\r
+                      PeiServices,\r
+                      Smbus,\r
+                      SlaveAddress,\r
+                      Command,\r
+                      EfiSmbusReadWord,\r
+                      FALSE,\r
+                      &Length,\r
+                      &Buffer[Index]\r
+                      );\r
+    if (EFI_ERROR(Status)) {\r
+      return Status;\r
+    }\r
+  }\r
+  return EFI_SUCCESS;\r
+}\r
+\r
+/**\r
+  This function initializes the PEIM.  It simply installs the DIMM PPI.\r
+\r
+  @param FfsHeader       Not used by this function\r
+  @param PeiServices     Pointer to PEI services table\r
+\r
+  @retval EFI_SUCCESS    The function completed successfully.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+PeimInitializeDimm (\r
+  IN EFI_PEI_SERVICES           **PeiServices,\r
+  IN EFI_PEI_NOTIFY_DESCRIPTOR  *NotifyDescriptor,\r
+  IN VOID                       *SmbusPpi\r
+  )\r
+{\r
+  EFI_STATUS                    Status;\r
+\r
+  Status = (**PeiServices).InstallPpi (\r
+                             PeiServices,\r
+                             &mPpiPlatformDimm\r
+                             );\r
+  ASSERT_PEI_ERROR (PeiServices, Status);\r
+\r
+  return EFI_SUCCESS;\r
+}\r
+\r

diff --git a/Vlv2TbltDevicePkg/PlatformInitPei/FlashMap.c b/Vlv2TbltDevicePkg/PlatformInitPei/FlashMap.c
new file mode 100644 (file)
index 0000000..282faa8
--- /dev/null
+++ b/Vlv2TbltDevicePkg/PlatformInitPei/FlashMap.c
@@ -0,0 +1,148 @@
+/** @file\r
+\r
+  Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+\r
+\r
+Module Name:\r
+\r
+  FlashMap.c\r
+\r
+Abstract:\r
+\r
+  Build GUIDed HOBs for platform specific flash map.\r
+\r
+--*/\r
+\r
+#include "Efi.h"\r
+#include "Pei.h"\r
+#include "PeiLib.h"\r
+#include "PeiLib.h"\r
+#include "EfiFlashMap.h"\r
+#include EFI_PROTOCOL_CONSUMER (FirmwareVolumeBlock)\r
+#include EFI_GUID_DEFINITION (FlashMapHob)\r
+#include EFI_GUID_DEFINITION (SystemNvDataGuid)\r
+#include EFI_GUID_DEFINITION (FirmwareFileSystem)\r
+\r
+EFI_GUID                            mFvBlockGuid      = EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL_GUID;\r
+EFI_GUID                            mFfsGuid          = EFI_FIRMWARE_FILE_SYSTEM_GUID;\r
+EFI_GUID                            mSystemDataGuid   = EFI_SYSTEM_NV_DATA_HOB_GUID;\r
+\r
+static EFI_FLASH_AREA_DATA          mFlashAreaData[]  = {\r
+       //\r
+  // Variable area\r
+  //\r
+  { FixedPcdGet32 (PcdFlashNvStorageVariableBase),\r
+    FixedPcdGet32 (PcdFlashNvStorageVariableSize),\r
+    EFI_FLASH_AREA_SUBFV | EFI_FLASH_AREA_MEMMAPPED_FV,\r
+    EFI_FLASH_AREA_EFI_VARIABLES },\r
+\r
+  //\r
+  // Boot block 2nd part\r
+  //\r
+  { FixedPcdGet32 (PcdFlashFvRecovery2Base),\r
+    FixedPcdGet32 (PcdFlashFvRecovery2Size),\r
+    EFI_FLASH_AREA_SUBFV | EFI_FLASH_AREA_MEMMAPPED_FV,\r
+    EFI_FLASH_AREA_FTW_BACKUP },\r
+\r
+  //\r
+  // Recovery FV\r
+  //\r
+  { FixedPcdGet32 (PcdFlashFvRecoveryBase),\r
+    FixedPcdGet32 (PcdFlashFvRecoverySize),\r
+    EFI_FLASH_AREA_FV | EFI_FLASH_AREA_MEMMAPPED_FV,\r
+    EFI_FLASH_AREA_RECOVERY_BIOS },\r
+\r
+  //\r
+  // Main FV\r
+  //\r
+  { FixedPcdGet32 (PcdFlashFvMainBase),\r
+    FixedPcdGet32 (PcdFlashFvMainSize),\r
+    EFI_FLASH_AREA_FV | EFI_FLASH_AREA_MEMMAPPED_FV,\r
+    EFI_FLASH_AREA_MAIN_BIOS }\r
+\r
+};\r
+\r
+#define NUM_FLASH_AREA_DATA (sizeof (mFlashAreaData) / sizeof (mFlashAreaData[0]))\r
+\r
+/**\r
+  Build GUID HOBs for platform specific flash map.\r
+\r
+  @param FfsHeader     Pointer this FFS file header.\r
+  @param PeiServices   General purpose services available to every PEIM.\r
+\r
+  @retval EFI_SUCCESS   Guid HOBs for platform flash map is built.\r
+  @retval Otherwise     Failed to build the Guid HOB data.\r
+\r
+**/\r
+EFI_STATUS\r
+PeimInitializeFlashMap (\r
+  IN EFI_FFS_FILE_HEADER       *FfsHeader,\r
+  IN EFI_PEI_SERVICES          **PeiServices\r
+  )\r
+{\r
+  UINTN                         Index;\r
+  EFI_FLASH_AREA_HOB_DATA       FlashHobData;\r
+\r
+  //\r
+  // Build flash area entries as GUIDed HOBs.\r
+  //\r
+  for (Index = 0; Index < NUM_FLASH_AREA_DATA; Index++) {\r
+    ZeroMem(&FlashHobData, sizeof (EFI_FLASH_AREA_HOB_DATA));\r
+\r
+    FlashHobData.AreaType               = mFlashAreaData[Index].AreaType;\r
+    FlashHobData.NumberOfEntries        = 1;\r
+    FlashHobData.SubAreaData.Attributes = mFlashAreaData[Index].Attributes;\r
+    FlashHobData.SubAreaData.Base       = (EFI_PHYSICAL_ADDRESS) (UINTN) mFlashAreaData[Index].Base;\r
+    FlashHobData.SubAreaData.Length     = (EFI_PHYSICAL_ADDRESS) (UINTN) mFlashAreaData[Index].Length;\r
+\r
+    switch (FlashHobData.AreaType) {\r
+    case EFI_FLASH_AREA_RECOVERY_BIOS:\r
+    case EFI_FLASH_AREA_MAIN_BIOS:\r
+      CopyMem (\r
+        &FlashHobData.AreaTypeGuid,\r
+        &mFfsGuid,\r
+        sizeof (EFI_GUID)\r
+        );\r
+      CopyMem (\r
+        &FlashHobData.SubAreaData.FileSystem,\r
+        &mFvBlockGuid,\r
+        sizeof (EFI_GUID)\r
+        );\r
+      break;\r
+\r
+    case EFI_FLASH_AREA_GUID_DEFINED:\r
+      CopyMem (\r
+        &FlashHobData.AreaTypeGuid,\r
+        &mSystemDataGuid,\r
+        sizeof (EFI_GUID)\r
+        );\r
+      CopyMem (\r
+        &FlashHobData.SubAreaData.FileSystem,\r
+        &mFvBlockGuid,\r
+        sizeof (EFI_GUID)\r
+        );\r
+      break;\r
+\r
+    default:\r
+      break;\r
+    }\r
+\r
+    PeiBuildHobGuidData(PeiServices,\r
+                        &gEfiFlashMapHobGuid,\r
+                        &FlashHobData,\r
+                        sizeof (EFI_FLASH_AREA_HOB_DATA)\r
+                        );\r
+  }\r
+  return EFI_SUCCESS;\r
+}\r
+\r

diff --git a/Vlv2TbltDevicePkg/PlatformInitPei/LegacySpeaker.c b/Vlv2TbltDevicePkg/PlatformInitPei/LegacySpeaker.c
new file mode 100644 (file)
index 0000000..7ec276b
--- /dev/null
+++ b/Vlv2TbltDevicePkg/PlatformInitPei/LegacySpeaker.c
@@ -0,0 +1,173 @@
+/** @file\r
+\r
+  Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+Module Name:\r
+\r
+\r
+ LegacySpeaker.c\r
+\r
+Abstract:\r
+\r
+  This file implements PEIM for Legacy Speaker. This file is valid for platforms both\r
+  on IA32 and Itanium Product Family\r
+\r
+--*/\r
+\r
+#include "PlatformEarlyInit.h"\r
+\r
+EFI_STATUS\r
+OutputBeep (\r
+  IN  CONST EFI_PEI_SERVICES  **PeiServices,\r
+  IN  UINTN             NumberOfBeep,\r
+  IN  UINTN             BeepDuration,\r
+  IN  UINTN             TimerInterval\r
+  );\r
+\r
+/**\r
+  This function will enable the speaker to generate beep\r
+\r
+  @param PeiServices     PeiServices to locate PPI\r
+\r
+  @retval EFI_STATUS\r
+\r
+**/\r
+EFI_STATUS\r
+TurnOnSpeaker (\r
+  IN  CONST EFI_PEI_SERVICES    **PeiServices\r
+  )\r
+{\r
+  UINT8                   Data;\r
+  Data = IoRead8 (EFI_SPEAKER_CONTROL_PORT);\r
+  Data |= 0x03;\r
+  IoWrite8(EFI_SPEAKER_CONTROL_PORT, Data);\r
+  return EFI_SUCCESS;\r
+}\r
+\r
+/**\r
+  This function will stop beep from speaker.\r
+\r
+  @param  PeiServices     PeiServices to locate PPI\r
+\r
+  @retval Status\r
+\r
+**/\r
+EFI_STATUS\r
+TurnOffSpeaker (\r
+  IN  CONST EFI_PEI_SERVICES    **PeiServices\r
+  )\r
+{\r
+  UINT8                   Data;\r
+\r
+  Data = IoRead8 (EFI_SPEAKER_CONTROL_PORT);\r
+  Data &= 0xFC;\r
+  IoWrite8(EFI_SPEAKER_CONTROL_PORT, Data);\r
+  return EFI_SUCCESS;\r
+}\r
+\r
+\r
+EFI_STATUS\r
+OutputBeep (\r
+  IN  CONST EFI_PEI_SERVICES  **PeiServices,\r
+  IN  UINTN             NumberOfBeep,\r
+  IN  UINTN             BeepDuration,\r
+  IN  UINTN             TimeInterval\r
+  )\r
+{\r
+  UINTN           Num;\r
+  EFI_PEI_STALL_PPI*  StallPpi;\r
+\r
+  (**PeiServices).LocatePpi (PeiServices, &gEfiPeiStallPpiGuid, 0, NULL, (void **)&StallPpi);\r
+\r
+  for (Num=0; Num < NumberOfBeep; Num++) {\r
+    TurnOnSpeaker (PeiServices);\r
+    StallPpi->Stall(PeiServices, StallPpi, BeepDuration);\r
+    TurnOffSpeaker(PeiServices);\r
+    StallPpi->Stall(PeiServices, StallPpi, TimeInterval);\r
+  }\r
+\r
+  return EFI_SUCCESS;\r
+}\r
+\r
+/**\r
+  This function will program the speaker tone frequency. The value should be with 64k\r
+  boundary since it takes only 16 bit value which gets programmed in two step IO opearattion\r
+\r
+  Frequency     - A value which should be 16 bit only.\r
+\r
+  EFI_SUCESS\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+ProgramToneFrequency (\r
+  IN  CONST EFI_PEI_SERVICES                  **PeiServices,\r
+  IN  UINT16                            Frequency\r
+  )\r
+{\r
+  UINT8                   Data;\r
+\r
+  Data = 0xB6;\r
+  IoWrite8(EFI_TIMER_CONTROL_PORT, Data);\r
+\r
+  Data = (UINT8)(Frequency & 0x00FF);\r
+  IoWrite8(EFI_TIMER_2_PORT, Data);\r
+  Data = (UINT8)((Frequency & 0xFF00) >> 8);\r
+  IoWrite8(EFI_TIMER_2_PORT, Data);\r
+  return EFI_SUCCESS;\r
+}\r
+\r
+/**\r
+  This function will generate the beep for specified duration.\r
+\r
+  @param  PeiServices       PeiServices to locate various PPIs\r
+  @param  NumberOfBeeps     Number of beeps which user want to produce\r
+  @param  BeepDuration      Duration for speaker gate need to be enabled\r
+  @param  TimeInterval      Interval between each beep\r
+\r
+  @retval EFI_STATUS\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+GenerateBeepTone (\r
+  IN  CONST EFI_PEI_SERVICES                  **PeiServices,\r
+  IN  UINTN                             NumberOfBeeps,\r
+  IN  UINTN                             BeepDuration,\r
+  IN  UINTN                             TimeInterval\r
+  )\r
+{\r
+\r
+  if ((NumberOfBeeps == 1) && (BeepDuration == 0) && (TimeInterval == 0)) {\r
+    TurnOnSpeaker (PeiServices);\r
+    return EFI_SUCCESS;\r
+  }\r
+\r
+  if ((NumberOfBeeps == 0) && (BeepDuration == 0) && (TimeInterval == 0)) {\r
+    TurnOffSpeaker (PeiServices);\r
+    return EFI_SUCCESS;\r
+  }\r
+\r
+  if (BeepDuration == 0) {\r
+    BeepDuration = EFI_DEFAULT_SHORT_BEEP_DURATION;\r
+  }\r
+\r
+  if (TimeInterval == 0) {\r
+    TimeInterval = EFI_DEFAULT_BEEP_TIME_INTERVAL;\r
+  }\r
+\r
+  OutputBeep (PeiServices, NumberOfBeeps, BeepDuration, TimeInterval);\r
+  return EFI_SUCCESS;\r
+\r
+\r
+}\r
+\r

diff --git a/Vlv2TbltDevicePkg/PlatformInitPei/LegacySpeaker.h b/Vlv2TbltDevicePkg/PlatformInitPei/LegacySpeaker.h
new file mode 100644 (file)
index 0000000..7f806a7
--- /dev/null
+++ b/Vlv2TbltDevicePkg/PlatformInitPei/LegacySpeaker.h
@@ -0,0 +1,76 @@
+/*++\r
+\r
+  Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+\r
+Module Name:\r
+\r
+ LegacySpeaker.h\r
+\r
+Abstract:\r
+\r
+  Speaker enabling related data\r
+\r
+--*/\r
+\r
+#ifndef _PEI_LEGACY_SPEAKER_H\r
+#define _PEI_LEGACY_SPEAKER_H\r
+\r
+\r
+//\r
+// Speaker Related Port Information\r
+//\r
+#define EFI_TIMER_COUNTER_PORT            0x40\r
+#define EFI_TIMER_CONTROL_PORT            0x43\r
+#define EFI_TIMER_2_PORT                  0x42\r
+#define EFI_SPEAKER_CONTROL_PORT          0x61\r
+\r
+#define EFI_SPEAKER_OFF_MASK              0xFC\r
+\r
+#define EFI_DEFAULT_BEEP_FREQUENCY        0x500\r
+\r
+//\r
+// Default Intervals/Beep Duration\r
+//\r
+#define EFI_DEFAULT_LONG_BEEP_DURATION    0x70000\r
+#define EFI_DEFAULT_SHORT_BEEP_DURATION   0x50000\r
+#define EFI_DEFAULT_BEEP_TIME_INTERVAL    0x20000\r
+\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+ProgramToneFrequency (\r
+  IN  CONST EFI_PEI_SERVICES  **PeiServices,\r
+  IN  UINT16 Frequency\r
+  );\r
+\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+GenerateBeepTone (\r
+  IN  CONST EFI_PEI_SERVICES                  **PeiServices,\r
+  IN  UINTN                             NumberOfBeeps,\r
+  IN  UINTN                             BeepDuration,\r
+  IN  UINTN                             TimeInterval\r
+  );\r
+\r
+EFI_STATUS\r
+TurnOnSpeaker (\r
+  IN  CONST EFI_PEI_SERVICES  **PeiServices\r
+  );\r
+\r
+EFI_STATUS\r
+TurnOffSpeaker (\r
+  IN  CONST EFI_PEI_SERVICES  **PeiServices\r
+  );\r
+\r
+#endif\r

diff --git a/Vlv2TbltDevicePkg/PlatformInitPei/MchInit.c b/Vlv2TbltDevicePkg/PlatformInitPei/MchInit.c
new file mode 100644 (file)
index 0000000..4cad67c
--- /dev/null
+++ b/Vlv2TbltDevicePkg/PlatformInitPei/MchInit.c
@@ -0,0 +1,77 @@
+/** @file\r
+\r
+  Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+Module Name:\r
+\r
+\r
+    MchInit.c\r
+\r
+Abstract:\r
+\r
+\r
+--*/\r
+\r
+\r
+#include "PlatformEarlyInit.h"\r
+\r
+#define PSE_PAGE_SIZE 0x400000   // 4MB\r
+\r
+extern  BOOLEAN ImageInMemory;\r
+\r
+\r
+VOID\r
+EfiCommonLibEnablePsePaging (\r
+  IN UINT32   PDBR\r
+  );\r
+\r
+VOID\r
+EfiCommonLibDisablePsePaging (\r
+  );\r
+\r
+/**\r
+\r
+  Initialize the MCH Thermal Sensor\r
+\r
+**/\r
+VOID\r
+InitMchThermalSensor()\r
+{\r
+}\r
+\r
+/**\r
+\r
+  Programs and enables the CRID for MCH and ICH\r
+\r
+**/\r
+VOID\r
+ProgramMchCRID(\r
+  IN CONST EFI_PEI_SERVICES            **PeiServices\r
+  )\r
+{\r
+}\r
+\r
+/**\r
+\r
+  Initialize the GPIO IO selection, GPIO USE selection, and GPIO signal inversion registers\r
+\r
+**/\r
+VOID\r
+MchInit (\r
+  IN CONST EFI_PEI_SERVICES          **PeiServices\r
+  )\r
+{\r
+\r
+  return;\r
+}\r
+\r
+\r

diff --git a/Vlv2TbltDevicePkg/PlatformInitPei/MemoryCallback.c b/Vlv2TbltDevicePkg/PlatformInitPei/MemoryCallback.c
new file mode 100644 (file)
index 0000000..31cc88a
--- /dev/null
+++ b/Vlv2TbltDevicePkg/PlatformInitPei/MemoryCallback.c
@@ -0,0 +1,345 @@
+/** @file\r
+\r
+  Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+Module Name:\r
+\r
+  MemoryCallback.c\r
+\r
+Abstract:\r
+\r
+  EFI 2.0 PEIM to provide the platform support functionality on the Bridgeport.\r
+\r
+--*/\r
+\r
+#include "PlatformEarlyInit.h"\r
+\r
+\r
+VOID\r
+UpdateDefaultSetupValue (\r
+  IN  EFI_PLATFORM_INFO_HOB       *PlatformInfo\r
+  )\r
+{\r
+return;\r
+}\r
+\r
+/**\r
+  PEI termination callback.\r
+\r
+  @param PeiServices         General purpose services available to every PEIM.\r
+  @param NotifyDescriptor    Not uesed.\r
+  @param Ppi                 Not uesed.\r
+\r
+  @retval EFI_SUCCESS        If the interface could be successfully\r
+                             installed.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI    \r
+EndOfPeiPpiNotifyCallback (\r
+  IN CONST EFI_PEI_SERVICES           **PeiServices,\r
+  IN EFI_PEI_NOTIFY_DESCRIPTOR  *NotifyDescriptor,\r
+  IN VOID                       *Ppi\r
+  )\r
+{\r
+  EFI_STATUS                  Status;\r
+  UINT64                      MemoryTop;\r
+  UINT64                      LowUncableBase;\r
+  EFI_PLATFORM_INFO_HOB       *PlatformInfo;\r
+  UINT32                      HecBaseHigh;\r
+  EFI_BOOT_MODE               BootMode;\r
+  EFI_PEI_HOB_POINTERS        Hob;\r
+\r
+  Status = (*PeiServices)->GetBootMode(\r
+                             PeiServices,\r
+                             &BootMode\r
+                             );\r
+\r
+  ASSERT_EFI_ERROR (Status);\r
+\r
+  //\r
+  // Set the some PCI and chipset range as UC\r
+  // And align to 1M at leaset\r
+  //\r
+  Hob.Raw = GetFirstGuidHob (&gEfiPlatformInfoGuid);\r
+  ASSERT (Hob.Raw != NULL);\r
+  PlatformInfo = GET_GUID_HOB_DATA(Hob.Raw);\r
+\r
+  UpdateDefaultSetupValue (PlatformInfo);\r
+\r
+  DEBUG ((EFI_D_ERROR, "Memory TOLM: %X\n", PlatformInfo->MemData.MemTolm));\r
+  DEBUG ((EFI_D_ERROR, "PCIE OSBASE: %lX\n", PlatformInfo->PciData.PciExpressBase));\r
+  DEBUG (\r
+    (EFI_D_ERROR,\r
+    "PCIE   BASE: %lX     Size : %X\n",\r
+    PlatformInfo->PciData.PciExpressBase,\r
+    PlatformInfo->PciData.PciExpressSize)\r
+    );\r
+  DEBUG (\r
+    (EFI_D_ERROR,\r
+    "PCI32  BASE: %X     Limit: %X\n",\r
+    PlatformInfo->PciData.PciResourceMem32Base,\r
+    PlatformInfo->PciData.PciResourceMem32Limit)\r
+    );\r
+  DEBUG (\r
+    (EFI_D_ERROR,\r
+    "PCI64  BASE: %lX     Limit: %lX\n",\r
+    PlatformInfo->PciData.PciResourceMem64Base,\r
+    PlatformInfo->PciData.PciResourceMem64Limit)\r
+    );\r
+  DEBUG ((EFI_D_ERROR, "UC    START: %lX     End  : %lX\n", PlatformInfo->MemData.MemMir0, PlatformInfo->MemData.MemMir1));\r
+\r
+  LowUncableBase = PlatformInfo->MemData.MemMaxTolm;\r
+  LowUncableBase &= (0x0FFF00000);\r
+  MemoryTop = (0x100000000);\r
+\r
+  if (BootMode != BOOT_ON_S3_RESUME) {\r
+    //\r
+    // In BIOS, HECBASE will be always below 4GB\r
+    //\r
+    HecBaseHigh = (UINT32) RShiftU64 (PlatformInfo->PciData.PciExpressBase, 28);\r
+    ASSERT (HecBaseHigh < 16);\r
+  }\r
+\r
+  return Status;\r
+}\r
+\r
+/**\r
+  Install Firmware Volume Hob's once there is main memory\r
+\r
+  @param PeiServices       General purpose services available to every PEIM.\r
+  @param NotifyDescriptor  Notify that this module published.\r
+  @param Ppi               PPI that was installed.\r
+\r
+  @retval EFI_SUCCESS     The function completed successfully.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+MemoryDiscoveredPpiNotifyCallback (\r
+  IN CONST EFI_PEI_SERVICES           **PeiServices,\r
+  IN EFI_PEI_NOTIFY_DESCRIPTOR  *NotifyDescriptor,\r
+  IN VOID                       *Ppi\r
+  )\r
+{\r
+  EFI_STATUS                  Status;\r
+  EFI_BOOT_MODE               BootMode;\r
+  EFI_CPUID_REGISTER          FeatureInfo;\r
+  UINT8                       CpuAddressWidth;\r
+  UINT16                      Pm1Cnt;\r
+  EFI_PEI_HOB_POINTERS        Hob;\r
+  EFI_PLATFORM_INFO_HOB       *PlatformInfo;\r
+  UINT32                      RootComplexBar;\r
+  UINT32                      PmcBase;\r
+  UINT32                      IoBase;\r
+  UINT32                      IlbBase;\r
+  UINT32                      SpiBase;\r
+  UINT32                      MphyBase;\r
+\r
+  //\r
+  // Get Platform Info HOB\r
+  //\r
+  Hob.Raw = GetFirstGuidHob (&gEfiPlatformInfoGuid);\r
+  ASSERT (Hob.Raw != NULL);\r
+  PlatformInfo = GET_GUID_HOB_DATA(Hob.Raw);\r
+\r
+  Status = (*PeiServices)->GetBootMode (PeiServices, &BootMode);\r
+\r
+  //\r
+  // Check if user wants to turn off in PEI phase\r
+  //\r
+  if ((BootMode != BOOT_ON_S3_RESUME) && (BootMode != BOOT_ON_FLASH_UPDATE)) {\r
+    CheckPowerOffNow();\r
+  } else {\r
+    Pm1Cnt  = IoRead16 (ACPI_BASE_ADDRESS + R_PCH_ACPI_PM1_CNT);\r
+    Pm1Cnt &= ~B_PCH_ACPI_PM1_CNT_SLP_TYP;\r
+    IoWrite16 (ACPI_BASE_ADDRESS + R_PCH_ACPI_PM1_CNT, Pm1Cnt);\r
+  }\r
+\r
+  #ifndef MINNOW2_FSP_BUILD\r
+  //\r
+  // Set PEI cache mode here\r
+  //\r
+  SetPeiCacheMode (PeiServices);\r
+  #endif\r
+\r
+  //\r
+  //  Pulish memory tyoe info\r
+  //\r
+  PublishMemoryTypeInfo ();\r
+\r
+  //\r
+  // Work done if on a S3 resume\r
+  //\r
+  if (BootMode == BOOT_ON_S3_RESUME) {\r
+    //\r
+    //Program the side band packet register to send a sideband message to Punit\r
+    //To indicate that DRAM has been initialized and PUNIT FW base address in memory.\r
+    //\r
+    return EFI_SUCCESS;\r
+  }\r
+\r
+  RootComplexBar = MmPci32( 0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_LPC, 0, R_PCH_LPC_RCBA ) & B_PCH_LPC_RCBA_BAR;\r
+  BuildResourceDescriptorHob (\r
+    EFI_RESOURCE_MEMORY_MAPPED_IO,\r
+    (EFI_RESOURCE_ATTRIBUTE_PRESENT | EFI_RESOURCE_ATTRIBUTE_INITIALIZED | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE),\r
+    RootComplexBar,\r
+    0x1000\r
+    );\r
+  DEBUG ((EFI_D_INFO, "RootComplexBar     : 0x%x\n", RootComplexBar));\r
+\r
+  PmcBase = MmPci32( 0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_LPC, 0, R_PCH_LPC_PMC_BASE ) & B_PCH_LPC_PMC_BASE_BAR;\r
+  BuildResourceDescriptorHob (\r
+    EFI_RESOURCE_MEMORY_MAPPED_IO,\r
+    (EFI_RESOURCE_ATTRIBUTE_PRESENT | EFI_RESOURCE_ATTRIBUTE_INITIALIZED | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE),\r
+    PmcBase,\r
+    0x1000\r
+    );\r
+  DEBUG ((EFI_D_INFO, "PmcBase            : 0x%x\n", PmcBase));\r
+\r
+  IoBase = MmPci32( 0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_LPC, 0, R_PCH_LPC_IO_BASE ) & B_PCH_LPC_IO_BASE_BAR;\r
+  BuildResourceDescriptorHob (\r
+    EFI_RESOURCE_MEMORY_MAPPED_IO,\r
+    (EFI_RESOURCE_ATTRIBUTE_PRESENT | EFI_RESOURCE_ATTRIBUTE_INITIALIZED | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE),\r
+    IoBase,\r
+    0x4000\r
+    );\r
+  DEBUG ((EFI_D_INFO, "IoBase             : 0x%x\n", IoBase));\r
+\r
+  IlbBase = MmPci32( 0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_LPC, 0, R_PCH_LPC_ILB_BASE ) & B_PCH_LPC_ILB_BASE_BAR;\r
+  BuildResourceDescriptorHob (\r
+    EFI_RESOURCE_MEMORY_MAPPED_IO,\r
+    (EFI_RESOURCE_ATTRIBUTE_PRESENT | EFI_RESOURCE_ATTRIBUTE_INITIALIZED | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE),\r
+    IlbBase,\r
+    0x1000\r
+    );\r
+  DEBUG ((EFI_D_INFO, "IlbBase            : 0x%x\n", IlbBase));\r
+\r
+  SpiBase = MmPci32( 0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_LPC, 0, R_PCH_LPC_SPI_BASE ) & B_PCH_LPC_SPI_BASE_BAR;\r
+  BuildResourceDescriptorHob (\r
+    EFI_RESOURCE_MEMORY_MAPPED_IO,\r
+    (EFI_RESOURCE_ATTRIBUTE_PRESENT | EFI_RESOURCE_ATTRIBUTE_INITIALIZED | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE),\r
+    SpiBase,\r
+    0x1000\r
+    );\r
+  DEBUG ((EFI_D_INFO, "SpiBase            : 0x%x\n", SpiBase));\r
+\r
+  MphyBase = MmPci32( 0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_LPC, 0, R_PCH_LPC_MPHY_BASE ) & B_PCH_LPC_MPHY_BASE_BAR;\r
+  BuildResourceDescriptorHob (\r
+    EFI_RESOURCE_MEMORY_MAPPED_IO,\r
+    (EFI_RESOURCE_ATTRIBUTE_PRESENT | EFI_RESOURCE_ATTRIBUTE_INITIALIZED | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE),\r
+    MphyBase,\r
+    0x100000\r
+    );\r
+  DEBUG ((EFI_D_INFO, "MphyBase           : 0x%x\n", MphyBase));\r
+\r
+  //\r
+  // Local APIC\r
+  //\r
+  BuildResourceDescriptorHob (\r
+    EFI_RESOURCE_MEMORY_MAPPED_IO,\r
+    (EFI_RESOURCE_ATTRIBUTE_PRESENT | EFI_RESOURCE_ATTRIBUTE_INITIALIZED | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE),\r
+    LOCAL_APIC_ADDRESS,\r
+    0x1000\r
+  );\r
+  DEBUG ((EFI_D_INFO, "LOCAL_APIC_ADDRESS : 0x%x\n", LOCAL_APIC_ADDRESS));\r
+\r
+  //\r
+  // IO APIC\r
+  //\r
+  BuildResourceDescriptorHob (\r
+    EFI_RESOURCE_MEMORY_MAPPED_IO,\r
+    (EFI_RESOURCE_ATTRIBUTE_PRESENT | EFI_RESOURCE_ATTRIBUTE_INITIALIZED | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE),\r
+    IO_APIC_ADDRESS,\r
+    0x1000\r
+  );\r
+  DEBUG ((EFI_D_INFO, "IO_APIC_ADDRESS    : 0x%x\n", IO_APIC_ADDRESS));\r
+\r
+  //\r
+  // Adding the PCIE Express area to the E820 memory table as type 2 memory.\r
+  //\r
+  BuildResourceDescriptorHob (\r
+    EFI_RESOURCE_MEMORY_MAPPED_IO,\r
+    (EFI_RESOURCE_ATTRIBUTE_PRESENT | EFI_RESOURCE_ATTRIBUTE_INITIALIZED | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE),\r
+    PlatformInfo->PciData.PciExpressBase,\r
+    PlatformInfo->PciData.PciExpressSize\r
+    );\r
+  DEBUG ((EFI_D_INFO, "PciExpressBase     : 0x%x\n", PlatformInfo->PciData.PciExpressBase));\r
+\r
+  //\r
+  // Adding the Flashpart to the E820 memory table as type 2 memory.\r
+  //\r
+  BuildResourceDescriptorHob (\r
+    EFI_RESOURCE_FIRMWARE_DEVICE,\r
+    (EFI_RESOURCE_ATTRIBUTE_PRESENT | EFI_RESOURCE_ATTRIBUTE_INITIALIZED | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE),\r
+    FixedPcdGet32 (PcdFlashAreaBaseAddress),\r
+    FixedPcdGet32 (PcdFlashAreaSize)\r
+    );\r
+  DEBUG ((EFI_D_INFO, "FLASH_BASE_ADDRESS : 0x%x\n", FixedPcdGet32 (PcdFlashAreaBaseAddress)));\r
+\r
+  //\r
+  // Create a CPU hand-off information\r
+  //\r
+  CpuAddressWidth = 32;\r
+  AsmCpuid (EFI_CPUID_EXTENDED_FUNCTION, &FeatureInfo.RegEax, &FeatureInfo.RegEbx, &FeatureInfo.RegEcx, &FeatureInfo.RegEdx);\r
+  if (FeatureInfo.RegEax >= EFI_CPUID_VIRT_PHYS_ADDRESS_SIZE) {\r
+    AsmCpuid (EFI_CPUID_VIRT_PHYS_ADDRESS_SIZE, &FeatureInfo.RegEax, &FeatureInfo.RegEbx, &FeatureInfo.RegEcx, &FeatureInfo.RegEdx);\r
+    CpuAddressWidth = (UINT8) (FeatureInfo.RegEax & 0xFF);\r
+  }\r
+\r
+  BuildCpuHob(CpuAddressWidth, 16);\r
+  ASSERT_EFI_ERROR (Status);\r
+\r
+  return Status;\r
+\r
+}\r
+\r
+\r
+EFI_STATUS\r
+ValidateFvHeader (\r
+  IN EFI_FIRMWARE_VOLUME_HEADER            *FwVolHeader\r
+  )\r
+{\r
+  UINT16  *Ptr;\r
+  UINT16  HeaderLength;\r
+  UINT16  Checksum;\r
+\r
+  //\r
+  // Verify the header revision, header signature, length\r
+  // Length of FvBlock cannot be 2**64-1\r
+  // HeaderLength cannot be an odd number\r
+  //\r
+  if ((FwVolHeader->Revision != EFI_FVH_REVISION) ||\r
+      (FwVolHeader->Signature != EFI_FVH_SIGNATURE) ||\r
+      (FwVolHeader->FvLength == ((UINT64) -1)) ||\r
+      ((FwVolHeader->HeaderLength & 0x01) != 0)\r
+      ) {\r
+    return EFI_NOT_FOUND;\r
+  }\r
+\r
+  //\r
+  // Verify the header checksum\r
+  //\r
+  HeaderLength  = (UINT16) (FwVolHeader->HeaderLength / 2);\r
+  Ptr           = (UINT16 *) FwVolHeader;\r
+  Checksum      = 0;\r
+  while (HeaderLength > 0) {\r
+    Checksum = *Ptr++;\r
+    HeaderLength--;\r
+  }\r
+\r
+  if (Checksum != 0) {\r
+    return EFI_NOT_FOUND;\r
+  }\r
+\r
+  return EFI_SUCCESS;\r
+}\r

diff --git a/Vlv2TbltDevicePkg/PlatformInitPei/MemoryPeim.c b/Vlv2TbltDevicePkg/PlatformInitPei/MemoryPeim.c
new file mode 100644 (file)
index 0000000..9592b07
--- /dev/null
+++ b/Vlv2TbltDevicePkg/PlatformInitPei/MemoryPeim.c
@@ -0,0 +1,369 @@
+/** @file\r
+\r
+  Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+Module Name:\r
+\r
+\r
+  MemoryPeim.c\r
+\r
+Abstract:\r
+\r
+  Tiano PEIM to provide the platform support functionality.\r
+  This file implements the Platform Memory Range PPI\r
+\r
+--*/\r
+\r
+#include "PlatformEarlyInit.h"\r
+\r
+//\r
+// Need min. of 48MB PEI phase\r
+//\r
+#define  PEI_MIN_MEMORY_SIZE               (6 * 0x800000)\r
+#define  PEI_RECOVERY_MIN_MEMORY_SIZE      (6 * 0x800000)\r
+\r
+//\r
+// This is the memory needed for PEI to start up DXE.\r
+//\r
+// Over-estimating this size will lead to higher fragmentation\r
+// of main memory.  Under-estimation of this will cause catastrophic\r
+// failure of PEI to load DXE.  Generally, the failure may only be\r
+// realized during capsule updates.\r
+//\r
+#define PRERESERVED_PEI_MEMORY ( \\r
+  EFI_SIZE_TO_PAGES (3 * 0x800000)   /* PEI Core memory based stack          */ \\r
+  )\r
+\r
+EFI_MEMORY_TYPE_INFORMATION mDefaultMemoryTypeInformation[] = {\r
+  { EfiACPIReclaimMemory,       0x40  },    // 0x40 pages = 256k for ASL\r
+  { EfiACPIMemoryNVS,           0x100 },    // 0x100 pages = 1 MB for S3, SMM, HII, etc\r
+  { EfiReservedMemoryType,      0x600 },    // 48k for BIOS Reserved\r
+  { EfiMemoryMappedIO,          0     },\r
+  { EfiMemoryMappedIOPortSpace, 0     },\r
+  { EfiPalCode,                 0     },\r
+  { EfiRuntimeServicesCode,     0x200 },\r
+  { EfiRuntimeServicesData,     0x100 },\r
+  { EfiLoaderCode,              0x100 },\r
+  { EfiLoaderData,              0x100 },\r
+  { EfiBootServicesCode,        0x800 },\r
+  { EfiBootServicesData,        0x2500},\r
+  { EfiConventionalMemory,      0     },\r
+  { EfiUnusableMemory,          0     },\r
+  { EfiMaxMemoryType,           0     }\r
+};\r
+\r
+STATIC\r
+EFI_STATUS\r
+GetMemorySize (\r
+  IN  CONST EFI_PEI_SERVICES    **PeiServices,\r
+  OUT UINT64              *LowMemoryLength,\r
+  OUT UINT64              *HighMemoryLength\r
+  );\r
+\r
+\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+SetPeiCacheMode (\r
+  IN  CONST EFI_PEI_SERVICES    **PeiServices\r
+  )\r
+{\r
+  EFI_STATUS              Status;\r
+  PEI_CACHE_PPI           *CachePpi;\r
+\r
+  EFI_BOOT_MODE           BootMode;\r
+  UINT64                  MemoryLength;\r
+  UINT64                  MemOverflow;\r
+  UINT64                  MemoryLengthUc;\r
+  UINT64                  MaxMemoryLength;\r
+  UINT64                  LowMemoryLength;\r
+  UINT64                  HighMemoryLength;\r
+  UINT8                   Index;\r
+  MTRR_SETTINGS           MtrrSetting;\r
+\r
+  //\r
+  // Load Cache PPI\r
+  //\r
+  Status = (**PeiServices).LocatePpi (\r
+             PeiServices,\r
+             &gPeiCachePpiGuid,    // GUID\r
+             0,                    // Instance\r
+             NULL,                 // EFI_PEI_PPI_DESCRIPTOR\r
+             (void **)&CachePpi             // PPI\r
+             );\r
+  if (!EFI_ERROR(Status)) {\r
+    //\r
+    // Clear the CAR Settings (Default Cache Type => UC)\r
+    //\r
+    DEBUG ((EFI_D_INFO, "Reset cache attribute and disable CAR. \n"));\r
+    CachePpi->ResetCache(\r
+                (EFI_PEI_SERVICES**)PeiServices,\r
+                CachePpi\r
+                );\r
+ }\r
+\r
+\r
+  //\r
+  // Variable initialization\r
+  //\r
+  LowMemoryLength = 0;\r
+  HighMemoryLength = 0;\r
+  MemoryLengthUc = 0;\r
+\r
+  Status = (*PeiServices)->GetBootMode (\r
+                             PeiServices,\r
+                             &BootMode\r
+                             );\r
+\r
+  //\r
+  // Determine memory usage\r
+  //\r
+  GetMemorySize (\r
+    PeiServices,\r
+    &LowMemoryLength,\r
+    &HighMemoryLength\r
+    );\r
+\r
+  LowMemoryLength  = (EFI_PHYSICAL_ADDRESS)MmPci32( 0, 0, 2, 0, 0x70);\r
+  LowMemoryLength   &=  0xFFF00000ULL;\r
+\r
+  MaxMemoryLength = LowMemoryLength;\r
+\r
+  //\r
+  // Round up to nearest 256MB with high memory and 64MB w/o high memory\r
+  //\r
+  if (HighMemoryLength != 0 ) {\r
+    MemOverflow = (LowMemoryLength & 0x0fffffff);\r
+    if (MemOverflow != 0) {\r
+      MaxMemoryLength = LowMemoryLength + (0x10000000 - MemOverflow);\r
+    }\r
+  } else {\r
+    MemOverflow = (LowMemoryLength & 0x03ffffff);\r
+    if (MemOverflow != 0) {\r
+      MaxMemoryLength = LowMemoryLength + (0x4000000 - MemOverflow);\r
+    }\r
+  }\r
+\r
+  ZeroMem (&MtrrSetting, sizeof(MTRR_SETTINGS));\r
+  for (Index = 0; Index < 2; Index++) {\r
+    MtrrSetting.Fixed.Mtrr[Index]=0x0606060606060606;\r
+   }\r
+  for (Index = 2; Index < 11; Index++) {\r
+    MtrrSetting.Fixed.Mtrr[Index]=0x0505050505050505;\r
+   }\r
+\r
+  //\r
+  // Cache the flash area to improve the boot performance in PEI phase\r
+  //\r
+  Index = 0;\r
+  MtrrSetting.Variables.Mtrr[0].Base = (FixedPcdGet32 (PcdFlashAreaBaseAddress) | CacheWriteProtected);\r
+  MtrrSetting.Variables.Mtrr[0].Mask = ((~((UINT64)(FixedPcdGet32 (PcdFlashAreaSize) - 1))) & MTRR_LIB_CACHE_VALID_ADDRESS) | MTRR_LIB_CACHE_MTRR_ENABLED;\r
+  Index ++;\r
+\r
+  MemOverflow =0;\r
+  while (MaxMemoryLength > MemOverflow){\r
+    MtrrSetting.Variables.Mtrr[Index].Base = (MemOverflow & MTRR_LIB_CACHE_VALID_ADDRESS) | CacheWriteBack;\r
+    MemoryLength = MaxMemoryLength - MemOverflow;\r
+    MemoryLength = GetPowerOfTwo64 (MemoryLength);\r
+    MtrrSetting.Variables.Mtrr[Index].Mask = ((~(MemoryLength - 1)) & MTRR_LIB_CACHE_VALID_ADDRESS) | MTRR_LIB_CACHE_MTRR_ENABLED;\r
+\r
+    MemOverflow += MemoryLength;\r
+    Index++;\r
+  }\r
+\r
+  MemoryLength = LowMemoryLength;\r
+\r
+  while (MaxMemoryLength != MemoryLength) {\r
+    MemoryLengthUc = GetPowerOfTwo64 (MaxMemoryLength - MemoryLength);\r
+\r
+    MtrrSetting.Variables.Mtrr[Index].Base = ((MaxMemoryLength - MemoryLengthUc) & MTRR_LIB_CACHE_VALID_ADDRESS) | CacheUncacheable;\r
+    MtrrSetting.Variables.Mtrr[Index].Mask= ((~(MemoryLengthUc   - 1)) & MTRR_LIB_CACHE_VALID_ADDRESS) | MTRR_LIB_CACHE_MTRR_ENABLED;\r
+    MaxMemoryLength -= MemoryLengthUc;\r
+    Index++;\r
+  }\r
+\r
+  MemOverflow =0x100000000;\r
+  while (HighMemoryLength > 0) {\r
+    MtrrSetting.Variables.Mtrr[Index].Base = (MemOverflow & MTRR_LIB_CACHE_VALID_ADDRESS) | CacheWriteBack;\r
+    MemoryLength = HighMemoryLength;\r
+    MemoryLength = GetPowerOfTwo64 (MemoryLength);\r
+\r
+    if (MemoryLength > MemOverflow){\r
+      MemoryLength = MemOverflow;\r
+    }\r
+\r
+    MtrrSetting.Variables.Mtrr[Index].Mask = ((~(MemoryLength - 1)) & MTRR_LIB_CACHE_VALID_ADDRESS) | MTRR_LIB_CACHE_MTRR_ENABLED;\r
+\r
+    MemOverflow += MemoryLength;\r
+    HighMemoryLength -= MemoryLength;\r
+    Index++;\r
+  }\r
+\r
+\r
+  for (Index = 0; Index < MTRR_NUMBER_OF_VARIABLE_MTRR; Index++) {\r
+    if (MtrrSetting.Variables.Mtrr[Index].Base == 0){\r
+      break;\r
+    }\r
+    DEBUG ((EFI_D_INFO, "Base=%lx, Mask=%lx\n",MtrrSetting.Variables.Mtrr[Index].Base ,MtrrSetting.Variables.Mtrr[Index].Mask));\r
+  }\r
+\r
+  //\r
+  // set FE/E bits for IA32_MTRR_DEF_TYPE\r
+  //\r
+  MtrrSetting.MtrrDefType |=  3 <<10;\r
+\r
+  MtrrSetAllMtrrs(&MtrrSetting);\r
+\r
+\r
+\r
+  return EFI_SUCCESS;\r
+}\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+SetDxeCacheMode (\r
+  IN  CONST EFI_PEI_SERVICES    **PeiServices\r
+  )\r
+{\r
+  //\r
+  // This is not needed for now.\r
+  //\r
+  return EFI_SUCCESS;\r
+}\r
+\r
+STATIC\r
+EFI_STATUS\r
+GetMemorySize (\r
+  IN  CONST EFI_PEI_SERVICES    **PeiServices,\r
+  OUT UINT64              *LowMemoryLength,\r
+  OUT UINT64              *HighMemoryLength\r
+  )\r
+{\r
+  EFI_STATUS              Status;\r
+  EFI_PEI_HOB_POINTERS    Hob;\r
+\r
+  *HighMemoryLength = 0;\r
+  *LowMemoryLength = 0x100000;\r
+\r
+  //\r
+  // Get the HOB list for processing\r
+  //\r
+  Status = (*PeiServices)->GetHobList (PeiServices, (void **)&Hob.Raw);\r
+  if (EFI_ERROR(Status)) {\r
+    return Status;\r
+  }\r
+\r
+  //\r
+  // Collect memory ranges\r
+  //\r
+  while (!END_OF_HOB_LIST (Hob)) {\r
+    if (Hob.Header->HobType == EFI_HOB_TYPE_RESOURCE_DESCRIPTOR) {\r
+      if (Hob.ResourceDescriptor->ResourceType == EFI_RESOURCE_SYSTEM_MEMORY) {\r
+        //\r
+        // Need memory above 1MB to be collected here\r
+        //\r
+        if (Hob.ResourceDescriptor->PhysicalStart >= 0x100000 &&\r
+            Hob.ResourceDescriptor->PhysicalStart < (EFI_PHYSICAL_ADDRESS) 0x100000000) {\r
+          *LowMemoryLength += (UINT64) (Hob.ResourceDescriptor->ResourceLength);\r
+        } else if (Hob.ResourceDescriptor->PhysicalStart >= (EFI_PHYSICAL_ADDRESS) 0x100000000) {\r
+          *HighMemoryLength += (UINT64) (Hob.ResourceDescriptor->ResourceLength);\r
+        }\r
+      }\r
+    }\r
+    Hob.Raw = GET_NEXT_HOB (Hob);\r
+  }\r
+\r
+  return EFI_SUCCESS;\r
+}\r
+\r
+\r
+/**\r
+  Publish Memory Type Information.\r
+\r
+  @param  NULL\r
+\r
+  @retval EFI_SUCCESS    Success.\r
+  @retval Others         Errors have occurred.\r
+**/\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+PublishMemoryTypeInfo (\r
+  void\r
+  )\r
+{\r
+  EFI_STATUS                      Status;\r
+  EFI_PEI_READ_ONLY_VARIABLE2_PPI *Variable;\r
+  UINTN                           DataSize;\r
+  EFI_MEMORY_TYPE_INFORMATION     MemoryData[EfiMaxMemoryType + 1];\r
+\r
+  Status = PeiServicesLocatePpi (\r
+             &gEfiPeiReadOnlyVariable2PpiGuid,\r
+             0,\r
+             NULL,\r
+            (void **)&Variable\r
+             );\r
+  if (EFI_ERROR(Status)) {\r
+    DEBUG((EFI_D_ERROR, "WARNING: Locating Pei variable failed 0x%x \n", Status));\r
+    DEBUG((EFI_D_ERROR, "Build Hob from default\n"));\r
+    //\r
+    // Build the default GUID'd HOB for DXE\r
+    //\r
+    BuildGuidDataHob (\r
+      &gEfiMemoryTypeInformationGuid,\r
+      mDefaultMemoryTypeInformation,\r
+      sizeof (mDefaultMemoryTypeInformation)\r
+      );\r
+\r
+    return Status;\r
+  }\r
+\r
+\r
+  DataSize = sizeof (MemoryData);\r
+\r
+  //\r
+  // This variable is saved in BDS stage. Now read it back\r
+  //\r
+  Status = Variable->GetVariable (\r
+                       Variable,\r
+                       EFI_MEMORY_TYPE_INFORMATION_VARIABLE_NAME,\r
+                       &gEfiMemoryTypeInformationGuid,\r
+                       NULL,\r
+                       &DataSize,\r
+                       &MemoryData\r
+                       );\r
+  if (EFI_ERROR (Status)) {\r
+       //\r
+    //build default\r
+    //\r
+    DEBUG((EFI_D_ERROR, "Build Hob from default\n"));\r
+    BuildGuidDataHob (\r
+      &gEfiMemoryTypeInformationGuid,\r
+      mDefaultMemoryTypeInformation,\r
+      sizeof (mDefaultMemoryTypeInformation)\r
+      );\r
+\r
+  } else {\r
+       //\r
+    // Build the GUID'd HOB for DXE from variable\r
+    //\r
+    DEBUG((EFI_D_ERROR, "Build Hob from variable \n"));\r
+    BuildGuidDataHob (\r
+      &gEfiMemoryTypeInformationGuid,\r
+      MemoryData,\r
+      DataSize\r
+      );\r
+  }\r
+\r
+  return Status;\r
+}\r
+\r

diff --git a/Vlv2TbltDevicePkg/PlatformInitPei/PchInitPeim.c b/Vlv2TbltDevicePkg/PlatformInitPei/PchInitPeim.c
new file mode 100644 (file)
index 0000000..30f87c1
--- /dev/null
+++ b/Vlv2TbltDevicePkg/PlatformInitPei/PchInitPeim.c
@@ -0,0 +1,813 @@
+/** @file\r
+\r
+  Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+\r
+Module Name:\r
+\r
+  PchInitPeim.c\r
+\r
+Abstract:\r
+\r
+  Do Early PCH platform initialization.\r
+\r
+\r
+--*/\r
+\r
+#include "PlatformEarlyInit.h"\r
+#include "Ppi/PchPlatformPolicy.h"\r
+#include "PchRegs.h"\r
+#include <Ppi/PchUsbPolicy.h>\r
+#include "Ppi/PchInit.h"\r
+#include <Library/PcdLib.h>\r
+\r
+EFI_GUID  gPchPlatformPolicyPpiGuid = PCH_PLATFORM_POLICY_PPI_GUID;\r
+\r
+#define MC_PMSTS_OFFSET                 0xC\r
+\r
+#define DEFAULT_BUS_INFO                0x2020\r
+\r
+\r
+#define PCI_LPC_BASE    (0x8000F800)\r
+#define PCI_LPC_REG(x)  (PCI_LPC_BASE + (x))\r
+#define PCIEX_BASE_ADDRESS                        0xE0000000\r
+#define PciD31F0RegBase                           PCIEX_BASE_ADDRESS + (UINT32) (31 << 15)\r
+\r
+VOID\r
+PchPolicySetupInit (\r
+  IN CONST EFI_PEI_SERVICES **PeiServices,\r
+  IN SYSTEM_CONFIGURATION   *SystemConfiguration\r
+  );\r
+\r
+VOID\r
+PchInitInterrupt (\r
+  IN SYSTEM_CONFIGURATION  *SystemConfiguration\r
+  );\r
+\r
+#ifndef __GNUC__\r
+#pragma warning (push)\r
+#pragma warning (disable : 4245)\r
+#pragma warning (pop)\r
+#endif\r
+\r
+UINT8\r
+ReadCmosBank1Byte (\r
+  IN UINT8                      Address\r
+  )\r
+{\r
+  UINT8                           Data;\r
+\r
+  IoWrite8(R_PCH_RTC_EXT_INDEX, Address);\r
+  Data = IoRead8 (R_PCH_RTC_EXT_TARGET);\r
+  return Data;\r
+}\r
+\r
+VOID\r
+WriteCmosBank1Byte (\r
+  IN UINT8                     Address,\r
+  IN UINT8                     Data\r
+  )\r
+{\r
+  IoWrite8(R_PCH_RTC_EXT_INDEX, Address);\r
+  IoWrite8(R_PCH_RTC_EXT_TARGET, Data);\r
+}\r
+\r
+/**\r
+  Turn off system if needed.\r
+\r
+  @param PeiServices Pointer to PEI Services\r
+  @param CpuIo       Pointer to CPU I/O Protocol\r
+\r
+  @retval None.\r
+\r
+**/\r
+VOID\r
+CheckPowerOffNow (\r
+  VOID\r
+  )\r
+{\r
+  UINT16  Pm1Sts;\r
+\r
+  //\r
+  // Read and check the ACPI registers\r
+  //\r
+  Pm1Sts = IoRead16 (ACPI_BASE_ADDRESS + R_PCH_ACPI_PM1_STS);\r
+  if ((Pm1Sts & B_PCH_ACPI_PM1_STS_PWRBTN) == B_PCH_ACPI_PM1_STS_PWRBTN) {\r
+    IoWrite16 (ACPI_BASE_ADDRESS + R_PCH_ACPI_PM1_STS, B_PCH_ACPI_PM1_STS_PWRBTN);\r
+    IoWrite16 (ACPI_BASE_ADDRESS + R_PCH_ACPI_PM1_CNT, V_PCH_ACPI_PM1_CNT_S5);\r
+    IoWrite16 (ACPI_BASE_ADDRESS + R_PCH_ACPI_PM1_CNT, V_PCH_ACPI_PM1_CNT_S5 + B_PCH_ACPI_PM1_CNT_SLP_EN);\r
+\r
+    //\r
+    // Should not return\r
+    //\r
+    CpuDeadLoop();\r
+  }\r
+}\r
+\r
+VOID\r
+ClearPowerState (\r
+  IN SYSTEM_CONFIGURATION        *SystemConfiguration\r
+  )\r
+{\r
+  UINT8   Data8;\r
+  UINT16  Data16;\r
+  UINT32  Data32;\r
+\r
+  //\r
+  // Check for PowerState option for AC power loss and program the chipset\r
+  //\r
+\r
+  //\r
+  // Clear PWROK (Set to Clear)\r
+  //\r
+  MmioOr32 (PMC_BASE_ADDRESS + R_PCH_PMC_GEN_PMCON_1, B_PCH_PMC_GEN_PMCON_PWROK_FLR);\r
+\r
+  //\r
+  // Clear Power Failure Bit (Set to Clear)\r
+  //\r
+  // TODO: Check if it is OK to clear here\r
+  //\r
+\r
+  MmioOr32 (PMC_BASE_ADDRESS + R_PCH_PMC_GEN_PMCON_1, B_PCH_PMC_GEN_PMCON_SUS_PWR_FLR);\r
+\r
+  //\r
+  // Clear the GPE and PM enable\r
+  //\r
+  IoWrite16 (ACPI_BASE_ADDRESS + R_PCH_ACPI_PM1_EN, (UINT16) 0x00);\r
+  IoWrite32 (ACPI_BASE_ADDRESS + R_PCH_ACPI_GPE0a_EN, (UINT32) 0x00);\r
+\r
+  //\r
+  // Halt the TCO timer\r
+  //\r
+  Data16 = IoRead16 (ACPI_BASE_ADDRESS + R_PCH_TCO_CNT);\r
+  Data16 |= B_PCH_TCO_CNT_TMR_HLT;\r
+  IoWrite16 (ACPI_BASE_ADDRESS + R_PCH_TCO_CNT, Data16);\r
+\r
+  //\r
+  // if NMI_NOW_STS is set\r
+  // NMI NOW bit is "Write '1' to clear"\r
+  //\r
+  Data8 = MmioRead8(ILB_BASE_ADDRESS + R_PCH_ILB_GNMI);\r
+  if ((Data8 & B_PCH_ILB_GNMI_NMINS) == B_PCH_ILB_GNMI_NMINS) {\r
+    MmioOr8 (ILB_BASE_ADDRESS + R_PCH_ILB_GNMI, B_PCH_ILB_GNMI_NMIN);\r
+  }\r
+\r
+  //\r
+  // Before we clear the TO status bit here we need to save the results in a CMOS bit for later use.\r
+  //\r
+  Data32 = IoRead32 (ACPI_BASE_ADDRESS + R_PCH_TCO_STS);\r
+  if ((Data32 & B_PCH_TCO_STS_SECOND_TO) == B_PCH_TCO_STS_SECOND_TO)\r
+  {\r
+#if (defined(HW_WATCHDOG_TIMER_SUPPORT) && (HW_WATCHDOG_TIMER_SUPPORT != 0))\r
+    WriteCmosBank1Byte (\r
+      EFI_CMOS_PERFORMANCE_FLAGS,\r
+      ReadCmosBank1Byte (EFI_CMOS_PERFORMANCE_FLAGS) | B_CMOS_TCO_WDT_RESET\r
+      );\r
+#endif\r
+  }\r
+}\r
+\r
+/*++\r
+\r
+  Clear any SMI status or wake status left over from boot.\r
+\r
+**/\r
+VOID\r
+ClearSmiAndWake (\r
+  VOID\r
+  )\r
+{\r
+  UINT16  Pm1Sts;\r
+  UINT32  Gpe0Sts;\r
+  UINT32  SmiSts;\r
+\r
+  //\r
+  // Read the ACPI registers\r
+  //\r
+  Pm1Sts  = IoRead16 (ACPI_BASE_ADDRESS + R_PCH_ACPI_PM1_STS);\r
+  Gpe0Sts = IoRead32 (ACPI_BASE_ADDRESS + R_PCH_ACPI_GPE0a_STS);\r
+  SmiSts  = IoRead32 (ACPI_BASE_ADDRESS + R_PCH_SMI_STS);\r
+\r
+  //\r
+  // Register Wake up reason for S4.  This information is used to notify\r
+  // WinXp of wake up reason because S4 wake up path doesn't keep SCI.\r
+  // This is important for Viiv(Quick resume) platform.\r
+  //\r
+\r
+  //\r
+  // First Clear CMOS S4 Wake up flag.\r
+  //\r
+  WriteCmosBank1Byte(CMOS_S4_WAKEUP_FLAG_ADDRESS, 0);\r
+\r
+  //\r
+  // Check wake up reason and set CMOS accordingly.  Currently checks\r
+  // Power button, USB, PS/2.\r
+  // Note : PS/2 wake up is using GPI13 (IO_PME).  This must be changed depending\r
+  // on board design.\r
+  //\r
+  if ((Pm1Sts & B_PCH_ACPI_PM1_STS_PWRBTN) || (Gpe0Sts & (B_PCH_ACPI_GPE0a_STS_CORE_GPIO | B_PCH_ACPI_GPE0a_STS_SUS_GPIO))) {\r
+    WriteCmosBank1Byte(CMOS_S4_WAKEUP_FLAG_ADDRESS, 1);\r
+  }\r
+\r
+  //\r
+  // Clear any SMI or wake state from the boot\r
+  //\r
+  Pm1Sts = (B_PCH_ACPI_PM1_STS_PRBTNOR | B_PCH_ACPI_PM1_STS_PWRBTN);\r
+\r
+  Gpe0Sts |=\r
+    (\r
+      B_PCH_ACPI_GPE0a_STS_CORE_GPIO |\r
+      B_PCH_ACPI_GPE0a_STS_SUS_GPIO |\r
+      B_PCH_ACPI_GPE0a_STS_PME_B0 |\r
+      B_PCH_ACPI_GPE0a_STS_BATLOW |\r
+      B_PCH_ACPI_GPE0a_STS_PCI_EXP |\r
+      B_PCH_ACPI_GPE0a_STS_GUNIT_SCI |\r
+      B_PCH_ACPI_GPE0a_STS_PUNIT_SCI |\r
+      B_PCH_ACPI_GPE0a_STS_SWGPE |\r
+      B_PCH_ACPI_GPE0a_STS_HOT_PLUG\r
+    );\r
+\r
+  SmiSts |=\r
+    (\r
+      B_PCH_SMI_STS_SMBUS |\r
+      B_PCH_SMI_STS_PERIODIC |\r
+      B_PCH_SMI_STS_TCO |\r
+      B_PCH_SMI_STS_SWSMI_TMR |\r
+      B_PCH_SMI_STS_APM |\r
+      B_PCH_SMI_STS_ON_SLP_EN |\r
+      B_PCH_SMI_STS_BIOS\r
+    );\r
+\r
+  //\r
+  // Write them back\r
+  //\r
+  IoWrite16 (ACPI_BASE_ADDRESS + R_PCH_ACPI_PM1_STS, Pm1Sts);\r
+  IoWrite32 (ACPI_BASE_ADDRESS + R_PCH_ACPI_GPE0a_STS, Gpe0Sts);\r
+  IoWrite32 (ACPI_BASE_ADDRESS + R_PCH_SMI_STS, SmiSts);\r
+}\r
+\r
+/**\r
+  Issue PCI-E Secondary Bus Reset\r
+\r
+  @param Bus  Bus number of the bridge\r
+  @param Dev  Devices number of the bridge\r
+  @param Fun  Function number of the bridge\r
+\r
+  @retval EFI_SUCCESS\r
+\r
+**/\r
+EFI_STATUS\r
+PcieSecondaryBusReset (\r
+  IN CONST EFI_PEI_SERVICES  **PeiServices,\r
+  IN UINT8             Bus,\r
+  IN UINT8             Dev,\r
+  IN UINT8             Fun\r
+  )\r
+{\r
+  EFI_PEI_STALL_PPI   *PeiStall;\r
+  EFI_STATUS          Status;\r
+\r
+  Status = (**PeiServices).LocatePpi (\r
+                             PeiServices,\r
+                             &gEfiPeiStallPpiGuid,\r
+                             0,\r
+                             NULL,\r
+                    (void **)&PeiStall\r
+                             );\r
+  ASSERT_EFI_ERROR (Status);\r
+\r
+  //\r
+  // Issue secondary bus reset\r
+  //\r
+  MmPci16Or(0, Bus, Dev, Fun, PCI_BRIDGE_CONTROL_REGISTER_OFFSET, EFI_PCI_BRIDGE_CONTROL_RESET_SECONDARY_BUS);\r
+\r
+  //\r
+  // Wait 1ms\r
+  //\r
+  PeiStall->Stall (PeiServices, PeiStall, 1000);\r
+\r
+\r
+  //\r
+  // Clear the reset bit\r
+  // Note: The PCIe spec suggests 100ms delay between clearing this bit and accessing\r
+  // the device's config space. Since we will not access the config space until we enter DXE\r
+  // we don't put delay expressly here.\r
+  //\r
+  MmPci16And(0, Bus, Dev, Fun, PCI_BRIDGE_CONTROL_REGISTER_OFFSET, ~(EFI_PCI_BRIDGE_CONTROL_RESET_SECONDARY_BUS));\r
+\r
+  return EFI_SUCCESS;\r
+}\r
+\r
+/**\r
+  Provide hard reset PPI service.\r
+  To generate full hard reset, write 0x0E to ICH RESET_GENERATOR_PORT (0xCF9).\r
+\r
+  @param PeiServices        General purpose services available to every PEIM.\r
+\r
+  @retval Not return        System reset occured.\r
+  @retval EFI_DEVICE_ERROR  Device error, could not reset the system.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+IchReset (\r
+  IN CONST EFI_PEI_SERVICES          **PeiServices\r
+  )\r
+{\r
+  IoWrite8 (\r
+    R_PCH_RST_CNT,\r
+    V_PCH_RST_CNT_HARDSTARTSTATE\r
+    );\r
+\r
+  IoWrite8 (\r
+    R_PCH_RST_CNT,\r
+    V_PCH_RST_CNT_HARDRESET\r
+    );\r
+\r
+  //\r
+  // System reset occured, should never reach at this line.\r
+  //\r
+  ASSERT_EFI_ERROR (EFI_DEVICE_ERROR);\r
+  CpuDeadLoop();\r
+\r
+  return EFI_DEVICE_ERROR;\r
+}\r
+\r
+VOID\r
+PchPlatformLpcInit (\r
+  IN  CONST EFI_PEI_SERVICES          **PeiServices,\r
+  IN SYSTEM_CONFIGURATION       *SystemConfiguration\r
+  )\r
+{\r
+  EFI_BOOT_MODE BootMode;\r
+  UINT8         Data8;\r
+  UINT16                Data16;\r
+\r
+  (*PeiServices)->GetBootMode(PeiServices, &BootMode);\r
+\r
+  if ((BootMode != BOOT_ON_S3_RESUME)) {\r
+\r
+    //\r
+    // Clear all pending SMI. On S3 clear power button enable so it wll not generate an SMI\r
+    //\r
+    ClearSmiAndWake ();\r
+  }\r
+\r
+  ClearPowerState (SystemConfiguration);\r
+\r
+  //\r
+  // Need to set and clear SET bit (RTC_REGB Bit 7) as requested by the ICH EDS\r
+  // early in POST after each power up directly after coin-cell battery insertion.\r
+  // This is to avoid the UIP bit (RTC_REGA Bit 7) from stuck at "1".\r
+  // The UIP bit status may be polled by software (i.e ME FW) during POST.\r
+  //\r
+  if (MmioRead8 (PMC_BASE_ADDRESS + R_PCH_PMC_GEN_PMCON_1) & B_PCH_PMC_GEN_PMCON_RTC_PWR_STS) {\r
+       //\r
+    // Set and clear SET bit in RTC_REGB\r
+    //\r
+    IoWrite8(R_PCH_RTC_INDEX, R_PCH_RTC_REGISTERB);\r
+    Data8 = IoRead8(R_PCH_RTC_TARGET);\r
+    Data8 |= B_PCH_RTC_REGISTERB_SET;\r
+    IoWrite8(R_PCH_RTC_TARGET, Data8);\r
+\r
+    IoWrite8(R_PCH_RTC_INDEX, R_PCH_RTC_REGISTERB);\r
+    Data8 &= (~B_PCH_RTC_REGISTERB_SET);\r
+    IoWrite8(R_PCH_RTC_TARGET, Data8);\r
+\r
+    //\r
+    // Clear the UIP bit in RTC_REGA\r
+    //\r
+    IoWrite8(R_PCH_RTC_INDEX, R_PCH_RTC_REGISTERA);\r
+    IoWrite8(R_PCH_RTC_TARGET, 0x00);\r
+  }\r
+\r
+  //\r
+  // Disable SERR NMI and IOCHK# NMI in port 61\r
+  //\r
+  Data8 = IoRead8 (R_PCH_NMI_SC);\r
+  IoWrite8(R_PCH_NMI_SC, (UINT8) (Data8 | B_PCH_NMI_SC_PCI_SERR_EN | B_PCH_NMI_SC_IOCHK_NMI_EN));\r
+\r
+  //\r
+  // Enable Bus Master, I/O, Mem, and SERR on LPC bridge\r
+  //\r
+  Data16 = PchLpcPciCfg16 (R_PCH_LPC_COMMAND);\r
+  MmioWrite16 (\r
+    MmPciAddress (0,\r
+      DEFAULT_PCI_BUS_NUMBER_PCH,\r
+      PCI_DEVICE_NUMBER_PCH_LPC,\r
+      PCI_FUNCTION_NUMBER_PCH_LPC,\r
+      R_PCH_LPC_COMMAND\r
+    ),\r
+    (Data16 |\r
+     B_PCH_LPC_COMMAND_IOSE |\r
+     B_PCH_LPC_COMMAND_MSE |\r
+     B_PCH_LPC_COMMAND_BME |\r
+     B_PCH_LPC_COMMAND_SERR_EN)\r
+  );\r
+\r
+  //\r
+  // Set Stretch S4 to 1-2s per marketing request.\r
+  // Note: This register is powered by RTC well.\r
+  //\r
+  MmioAndThenOr8 (\r
+    PMC_BASE_ADDRESS + R_PCH_PMC_GEN_PMCON_1 ,\r
+    (UINT8) (~B_PCH_PMC_GEN_PMCON_SLP_S4_MAW),\r
+    (UINT8) (B_PCH_PMC_GEN_PMCON_SLP_S4_ASE | V_PCH_PMC_GEN_PMCON_SLP_S4_MAW_4S)\r
+    );\r
+\r
+}\r
+\r
+#define V_PCH_ILB_IRQE_UARTIRQEN_IRQ3             BIT3 // UART IRQ3 Enable\r
+\r
+VOID\r
+UARTInit (\r
+  IN SYSTEM_CONFIGURATION        *SystemConfiguration\r
+  )\r
+{\r
+  if (0) { // for fix cr4 issue\r
+    //\r
+    // Program and enable PMC Base.\r
+    //\r
+    IoWrite32 (0xCF8,  PCI_LPC_REG(R_PCH_LPC_PMC_BASE));\r
+    IoWrite32 (0xCFC,  (PMC_BASE_ADDRESS | B_PCH_LPC_PMC_BASE_EN));\r
+\r
+    if( (SystemConfiguration->PcuUart1 == 1) &&\r
+        (SystemConfiguration->LpssHsuart0Enabled == 0)){\r
+      //\r
+      // Enable COM1 for debug message output.\r
+      //\r
+      MmioOr32 (PMC_BASE_ADDRESS + R_PCH_PMC_GEN_PMCON_1, BIT24);\r
+\r
+      //\r
+      //Enable internal UART3 port(COM1)\r
+      //\r
+      MmioOr8 (ILB_BASE_ADDRESS + R_PCH_ILB_IRQE, (UINT8) V_PCH_ILB_IRQE_UARTIRQEN_IRQ3);\r
+      MmioOr32 (IO_BASE_ADDRESS + 0x0520, 0x01); // UART3_RXD-L\r
+      MmioOr32 (IO_BASE_ADDRESS + 0x0530, 0x01); // UART3_TXD-0\r
+      MmioOr8 (PciD31F0RegBase + R_PCH_LPC_UART_CTRL, (UINT8) B_PCH_LPC_UART_CTRL_COM1_EN);\r
+    } else {\r
+       //\r
+      //Disable UART3(COM1)\r
+      //\r
+      MmioAnd8 (ILB_BASE_ADDRESS + R_PCH_ILB_IRQE, (UINT8) ~V_PCH_ILB_IRQE_UARTIRQEN_IRQ3);\r
+      MmioAnd32 (IO_BASE_ADDRESS + 0x0520, ~(UINT32)0x07);\r
+      MmioAnd32 (IO_BASE_ADDRESS + 0x0530, ~(UINT32)0x07);\r
+      MmioAnd8 (PciD31F0RegBase + R_PCH_LPC_UART_CTRL, (UINT8) ~B_PCH_LPC_UART_CTRL_COM1_EN);\r
+\r
+\r
+      if (SystemConfiguration->LpssHsuart0Enabled == 1){\r
+        //\r
+        //Valleyview BIOS Specification Vol2,17.2\r
+        //LPSS_UART1 ¨C set each pad PAD_CONF0.Func_Pin_Mux to function 1:\r
+        //\r
+        MmioAnd8 (IO_BASE_ADDRESS + 0x0090, (UINT8)~0x07);\r
+        MmioOr8 (IO_BASE_ADDRESS + 0x0090, 0x01);\r
+        MmioAnd8 (IO_BASE_ADDRESS + 0x00D0, (UINT8)~0x07);\r
+        MmioOr8 (IO_BASE_ADDRESS + 0x00D0, 0x01);\r
+\r
+      }\r
+    }\r
+\r
+\r
+    DEBUG ((EFI_D_ERROR, "EnableInternalUart\n"));\r
+  } else {\r
+       //\r
+    // If SIO UART interface selected\r
+    //Disable internal UART port(COM1)\r
+    //\r
+    if (0) {; // For fix CR4 issue\r
+      MmioAnd8 (ILB_BASE_ADDRESS + R_PCH_ILB_IRQE, (UINT8) ~V_PCH_ILB_IRQE_UARTIRQEN_IRQ3);\r
+      MmioAnd8 (IO_BASE_ADDRESS + 0x0090, (UINT8)~0x07);\r
+      MmioAnd8 (IO_BASE_ADDRESS + 0x00D0, (UINT8)~0x07);\r
+      MmioAnd8 (PciD31F0RegBase + R_PCH_LPC_UART_CTRL, (UINT8) ~B_PCH_LPC_UART_CTRL_COM1_EN);\r
+\r
+    }\r
+  }\r
+}\r
+\r
+VOID\r
+IchRcrbInit (\r
+  IN CONST EFI_PEI_SERVICES            **PeiServices,\r
+  IN SYSTEM_CONFIGURATION        *SystemConfiguration\r
+  )\r
+{\r
+  UINT8                           LpcRevisionID;\r
+  EFI_PLATFORM_CPU_INFO           *PlatformCpuInfo;\r
+  EFI_PEI_HOB_POINTERS            Hob;\r
+  EFI_BOOT_MODE                   BootMode;\r
+\r
+  //\r
+  // Get Platform Info HOB\r
+  //\r
+  Hob.Raw = GetFirstGuidHob (&gEfiPlatformCpuInfoGuid);\r
+  ASSERT (Hob.Raw != NULL);\r
+  PlatformCpuInfo = GET_GUID_HOB_DATA(Hob.Raw);\r
+\r
+  (*PeiServices)->GetBootMode(PeiServices, &BootMode);\r
+\r
+  //\r
+  // If not recovery or flash update boot path. set the BIOS interface lock down bit.\r
+  // It locks the top swap bit and BIOS boot strap bits from being changed.\r
+  //\r
+  if ((BootMode != BOOT_IN_RECOVERY_MODE) && (BootMode != BOOT_ON_FLASH_UPDATE)) {\r
+    MmioOr8 (RCBA_BASE_ADDRESS + R_PCH_RCRB_GCS, B_PCH_RCRB_GCS_BILD);\r
+  }\r
+\r
+  //\r
+  // Disable the Watchdog timer expiration from causing a system reset\r
+  //\r
+  MmioOr8 (PMC_BASE_ADDRESS + R_PCH_PMC_PM_CFG, B_PCH_PMC_PM_CFG_NO_REBOOT);\r
+\r
+  //\r
+  // Initial RCBA according to the PeiRCBA table\r
+  //\r
+  LpcRevisionID = PchLpcPciCfg8 (R_PCH_LPC_RID_CC);\r
+\r
+  if ((BootMode == BOOT_ON_S3_RESUME)) {\r
+    //\r
+    // We are resuming from S3\r
+    // Enable HPET if enabled in Setup\r
+    // ICH Config register Offset 0x3404 bit 7 (Enable) = 1,\r
+    // Bit 1:0 (Mem I/O address) = 0 (0xFED00000)\r
+    //\r
+    MmioOr8 (R_PCH_PCH_HPET + R_PCH_PCH_HPET_GCFG, B_PCH_PCH_HPET_GCFG_EN);\r
+\r
+  }\r
+\r
+}\r
+\r
+\r
+EFI_STATUS\r
+PlatformPchInit (\r
+  IN SYSTEM_CONFIGURATION        *SystemConfiguration,\r
+  IN CONST EFI_PEI_SERVICES      **PeiServices,\r
+  IN UINT16                      PlatformType\r
+  )\r
+{\r
+  IchRcrbInit (PeiServices, SystemConfiguration);\r
+\r
+  //\r
+  // PCH Policy Initialization based on Setup variable.\r
+  //\r
+  PchPolicySetupInit (PeiServices, SystemConfiguration);\r
+\r
+  UARTInit(SystemConfiguration);\r
+\r
+  PchPlatformLpcInit (PeiServices, SystemConfiguration);\r
+\r
+  return EFI_SUCCESS;\r
+}\r
+\r
+/**\r
+\r
+  Returns the state of A16 inversion\r
+\r
+  @retval TRUE    A16 is inverted\r
+  @retval FALSE   A16 is not inverted\r
+\r
+**/\r
+BOOLEAN\r
+IsA16Inverted (\r
+  )\r
+{\r
+  UINT8  Data;\r
+  Data = MmioRead8 (RCBA_BASE_ADDRESS + R_PCH_RCRB_GCS);\r
+  return (Data & B_PCH_RCRB_GCS_TS) ? TRUE : FALSE;\r
+}\r
+\r
+VOID\r
+PchPolicySetupInit (\r
+  IN CONST EFI_PEI_SERVICES **PeiServices,\r
+  IN SYSTEM_CONFIGURATION   *SystemConfiguration\r
+  )\r
+{\r
+  EFI_STATUS                  Status;\r
+  EFI_PEI_PPI_DESCRIPTOR      *PchPlatformPolicyPpiDesc;\r
+  PCH_PLATFORM_POLICY_PPI     *PchPlatformPolicyPpi;\r
+  PCH_HPET_CONFIG             *HpetConfig;\r
+  PCH_PCIE_CONFIG             *PcieConfig;\r
+  UINT8                       Index;\r
+  PCH_IOAPIC_CONFIG           *IoApicConfig;\r
+  PCH_LPSS_CONFIG             *LpssConfig;\r
+  UINT32                      SpiHsfsReg;\r
+  UINT32                      SpiFdodReg;\r
+\r
+//\r
+// Disable codec ALC-262\r
+//\r
+  UINT32                      IoBase;\r
+\r
+  //\r
+  // Install Pch Platform Policy PPI. As we depend on Pch Init PPI so we are executed after\r
+  // PchInit PEIM. Thus we can insure PCH Initialization is performed when we install the Pch Platform Policy PPI,\r
+  // as PchInit PEIM registered a notification function on our policy PPI.\r
+  //\r
+  // --cr-- For better code structure / modularity, we should use a notification function on Pch Init PPI to perform\r
+  // actions that depend on PchInit PEIM's initialization.\r
+  //\r
+  //Todo: confirm if we need update to PCH_PLATFORM_POLICY_PPI_REVISION_5\r
+  //\r
+  DEBUG ((EFI_D_ERROR, "PchPolicySetupInit() - Start\n"));\r
+\r
+  Status = (*PeiServices)->AllocatePool (PeiServices, sizeof (EFI_PEI_PPI_DESCRIPTOR), (void **)&PchPlatformPolicyPpiDesc);\r
+  ASSERT_EFI_ERROR (Status);\r
+\r
+  Status = (*PeiServices)->AllocatePool (PeiServices, sizeof (PCH_PLATFORM_POLICY_PPI), (void **)&PchPlatformPolicyPpi);\r
+  ASSERT_EFI_ERROR (Status);\r
+\r
+  Status = (*PeiServices)->AllocatePool (PeiServices, sizeof (PCH_HPET_CONFIG), (void **)&HpetConfig);\r
+  ASSERT_EFI_ERROR (Status);\r
+\r
+  Status = (*PeiServices)->AllocatePool (PeiServices, sizeof (PCH_PCIE_CONFIG), (void **)&PcieConfig);\r
+  ASSERT_EFI_ERROR (Status);\r
+\r
+  Status = (*PeiServices)->AllocatePool (PeiServices, sizeof (PCH_IOAPIC_CONFIG), (void **)&IoApicConfig);\r
+  ASSERT_EFI_ERROR (Status);\r
+\r
+  Status = (*PeiServices)->AllocatePool (PeiServices, sizeof (PCH_LPSS_CONFIG), (void **)&LpssConfig);\r
+  ASSERT_EFI_ERROR (Status);\r
+\r
+  PchPlatformPolicyPpi->Revision                = PCH_PLATFORM_POLICY_PPI_REVISION_1;\r
+  PchPlatformPolicyPpi->BusNumber               = DEFAULT_PCI_BUS_NUMBER_PCH;\r
+  PchPlatformPolicyPpi->SpiBase                 = SPI_BASE_ADDRESS;\r
+  PchPlatformPolicyPpi->PmcBase                 = PMC_BASE_ADDRESS;\r
+  PchPlatformPolicyPpi->IoBase                  = IO_BASE_ADDRESS;\r
+  PchPlatformPolicyPpi->IlbBase                 = ILB_BASE_ADDRESS;\r
+  PchPlatformPolicyPpi->PUnitBase               = PUNIT_BASE_ADDRESS;\r
+  PchPlatformPolicyPpi->MphyBase                = MPHY_BASE_ADDRESS;\r
+  PchPlatformPolicyPpi->Rcba                    = RCBA_BASE_ADDRESS;\r
+  PchPlatformPolicyPpi->AcpiBase                = ACPI_BASE_ADDRESS;\r
+  PchPlatformPolicyPpi->GpioBase                = GPIO_BASE_ADDRESS;\r
+  PchPlatformPolicyPpi->SataMode                = SystemConfiguration->SataType;\r
+  PchPlatformPolicyPpi->EnableRmh               = SystemConfiguration->PchUsbRmh;\r
+\r
+  PchPlatformPolicyPpi->EhciPllCfgEnable        = SystemConfiguration->EhciPllCfgEnable;\r
+\r
+\r
+  PchPlatformPolicyPpi->HpetConfig              = HpetConfig;\r
+  PchPlatformPolicyPpi->PcieConfig              = PcieConfig;\r
+  PchPlatformPolicyPpi->IoApicConfig            = IoApicConfig;\r
+\r
+  PchPlatformPolicyPpi->HpetConfig->Enable      = SystemConfiguration->Hpet;\r
+  PchPlatformPolicyPpi->HpetConfig->Base        = HPET_BASE_ADDRESS;\r
+  PchPlatformPolicyPpi->IoApicConfig->IoApicId  = 0x01;\r
+\r
+  //\r
+  // Set LPSS configuration according to setup value.\r
+  //\r
+  PchPlatformPolicyPpi->LpssConfig->LpssPciModeEnabled   = SystemConfiguration->LpssPciModeEnabled;\r
+\r
+  PchPlatformPolicyPpi->LpssConfig->Dma1Enabled    = SystemConfiguration->LpssDma1Enabled;\r
+  PchPlatformPolicyPpi->LpssConfig->I2C0Enabled    = SystemConfiguration->LpssI2C0Enabled;\r
+  PchPlatformPolicyPpi->LpssConfig->I2C1Enabled    = SystemConfiguration->LpssI2C1Enabled;\r
+  PchPlatformPolicyPpi->LpssConfig->I2C2Enabled    = SystemConfiguration->LpssI2C2Enabled;\r
+  PchPlatformPolicyPpi->LpssConfig->I2C3Enabled    = SystemConfiguration->LpssI2C3Enabled;\r
+  PchPlatformPolicyPpi->LpssConfig->I2C4Enabled    = SystemConfiguration->LpssI2C4Enabled;\r
+  PchPlatformPolicyPpi->LpssConfig->I2C5Enabled    = SystemConfiguration->LpssI2C5Enabled;\r
+  PchPlatformPolicyPpi->LpssConfig->I2C6Enabled    = SystemConfiguration->LpssI2C6Enabled;\r
+\r
+  PchPlatformPolicyPpi->LpssConfig->Dma0Enabled    = SystemConfiguration->LpssDma0Enabled;;\r
+  PchPlatformPolicyPpi->LpssConfig->Pwm0Enabled    = SystemConfiguration->LpssPwm0Enabled;\r
+  PchPlatformPolicyPpi->LpssConfig->Pwm1Enabled    = SystemConfiguration->LpssPwm1Enabled;\r
+  PchPlatformPolicyPpi->LpssConfig->Hsuart0Enabled = SystemConfiguration->LpssHsuart0Enabled;\r
+  PchPlatformPolicyPpi->LpssConfig->Hsuart1Enabled = SystemConfiguration->LpssHsuart1Enabled;\r
+  PchPlatformPolicyPpi->LpssConfig->SpiEnabled     = SystemConfiguration->LpssSpiEnabled;\r
+\r
+\r
+  for (Index = 0; Index < PCH_PCIE_MAX_ROOT_PORTS; Index++) {\r
+    PchPlatformPolicyPpi->PcieConfig->PcieSpeed[Index] = SystemConfiguration->PcieRootPortSpeed[Index];\r
+  }\r
+\r
+  SpiHsfsReg = MmioRead32 (SPI_BASE_ADDRESS + R_PCH_SPI_HSFS);\r
+  if ((SpiHsfsReg & B_PCH_SPI_HSFS_FDV) == B_PCH_SPI_HSFS_FDV) {\r
+    MmioWrite32 (SPI_BASE_ADDRESS + R_PCH_SPI_FDOC, V_PCH_SPI_FDOC_FDSS_FSDM);\r
+    SpiFdodReg = MmioRead32 (SPI_BASE_ADDRESS + R_PCH_SPI_FDOD);\r
+    if (SpiFdodReg == V_PCH_SPI_FDBAR_FLVALSIG) {\r
+    }\r
+  //\r
+  // Disable codec ALC-262\r
+  //\r
+  if (SystemConfiguration->DisableCodec262 == 1) {\r
+      IoBase = MmioRead32 (MmPciAddress (0,\r
+                        PchPlatformPolicyPpi->BusNumber,\r
+                        PCI_DEVICE_NUMBER_PCH_LPC,\r
+                        PCI_FUNCTION_NUMBER_PCH_LPC,\r
+                        0\r
+                      ) + R_PCH_LPC_IO_BASE) & B_PCH_LPC_IO_BASE_BAR;\r
+      MmioAnd32 ((UINTN) (IoBase + 0x270), (UINT32) (~0x07));\r
+  }\r
+  }\r
+\r
+  PchPlatformPolicyPpiDesc->Flags = EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST;\r
+  PchPlatformPolicyPpiDesc->Guid = &gPchPlatformPolicyPpiGuid;\r
+  PchPlatformPolicyPpiDesc->Ppi = PchPlatformPolicyPpi;\r
+\r
+  //\r
+  // Install PCH Platform Policy PPI\r
+  //\r
+  Status = (**PeiServices).InstallPpi (\r
+              PeiServices,\r
+              PchPlatformPolicyPpiDesc\r
+              );\r
+  ASSERT_EFI_ERROR (Status);\r
+\r
+  DEBUG ((EFI_D_ERROR, "PchPolicySetupInit() - End\n"));\r
+}\r
+\r
+EFI_STATUS\r
+InstallPeiPchUsbPolicy (\r
+  IN CONST  EFI_PEI_SERVICES  **PeiServices\r
+  )\r
+{\r
+  EFI_STATUS              Status = EFI_SUCCESS;\r
+\r
+  EFI_PEI_PPI_DESCRIPTOR  *PeiPchUsbPolicyPpiDesc;\r
+  PCH_USB_POLICY_PPI      *PeiPchUsbPolicyPpi;\r
+  PCH_USB_CONFIG          *UsbConfig;\r
+  EFI_PLATFORM_INFO_HOB   PlatformInfo;\r
+\r
+  //\r
+  // Allocate descriptor and PPI structures.  Since these are dynamically updated\r
+  // we cannot do a global variable PPI.\r
+  //\r
+  Status = (*PeiServices)->AllocatePool (PeiServices, sizeof (EFI_PEI_PPI_DESCRIPTOR), (void **)&PeiPchUsbPolicyPpiDesc);\r
+\r
+\r
+  Status = (*PeiServices)->AllocatePool (PeiServices, sizeof (PCH_USB_POLICY_PPI), (void **)&PeiPchUsbPolicyPpi);\r
+\r
+\r
+\r
+  Status = (*PeiServices)->AllocatePool (PeiServices, sizeof (PCH_USB_CONFIG), (void **)&UsbConfig);\r
+\r
+\r
+  //\r
+  // Initiate PCH USB policy.\r
+  //\r
+  PeiPchUsbPolicyPpi->Revision = PCH_USB_POLICY_PPI_REVISION_1;\r
+  UsbConfig->Usb20Settings[0].Enable  = PCH_DEVICE_ENABLE;\r
+  UsbConfig->UsbPerPortCtl            = PCH_DEVICE_DISABLE;\r
+  UsbConfig->Ehci1Usbr                = PCH_DEVICE_DISABLE;\r
+\r
+  //\r
+  // Initialize PlatformInfo HOB\r
+  //\r
+  ZeroMem (&PlatformInfo, sizeof(PlatformInfo));\r
+  MultiPlatformInfoInit(PeiServices, &PlatformInfo);\r
+\r
+  UsbConfig->Usb20OverCurrentPins[0] = PchUsbOverCurrentPin0;\r
+\r
+  UsbConfig->Usb20OverCurrentPins[1] = PchUsbOverCurrentPin0;\r
+\r
+  UsbConfig->Usb20OverCurrentPins[2] = PchUsbOverCurrentPin1;\r
+\r
+  UsbConfig->Usb20OverCurrentPins[3] = PchUsbOverCurrentPin1;\r
+\r
+\r
+  //\r
+  // Enable USB Topology control and program the topology setting for every USB port\r
+  // See Platform Design Guide for description of topologies\r
+  //\r
+    //\r
+    // Port 0: ~10.9", Port 1: ~10.1", Port 2: ~11.2", Port 3: ~11.5", Port 4: ~3.7", Port 5: ~2.7", Port 6: ~4.1"\r
+    // Port 7: ~4.5", Port 8: ~10.7", Port 9: ~10.5", Port 10: ~4.2", Port 11: ~4.3", Port 12: ~3.1", Port 13: ~2.9"\r
+    //\r
+\r
+    //\r
+    // Port 0: ~3.5", Port 1: ~4.1", Port 2: ~4.6", Port 3: ~4.6", Port 4: ~12.5", Port 5: ~12", Port 6: ~5.1"\r
+    // Port 7: ~5.1", Port 8: ~4.1", Port 9: ~4.1", Port 10: ~14.5", Port 11: ~12.8", Port 12: ~12.9", Port 13: ~14.6"\r
+    //\r
+  UsbConfig->Usb20PortLength[0]  = 0x53;\r
+  UsbConfig->Usb20PortLength[1]  = 0x49;\r
+  UsbConfig->Usb20PortLength[2]  = 0x47;\r
+  UsbConfig->Usb20PortLength[3]  = 0x80;\r
+\r
+  PeiPchUsbPolicyPpi->Mode = EHCI_MODE;\r
+\r
+  PeiPchUsbPolicyPpi->EhciMemBaseAddr = PcdGet32(PcdPeiIchEhciControllerMemoryBaseAddress);\r
+\r
+  PeiPchUsbPolicyPpi->EhciMemLength   = (UINT32) 0x400 * PchEhciControllerMax;\r
+\r
+  PeiPchUsbPolicyPpi->UsbConfig       = UsbConfig;\r
+\r
+  PeiPchUsbPolicyPpiDesc->Flags       = EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST;\r
+\r
+  PeiPchUsbPolicyPpiDesc->Guid        = &gPchUsbPolicyPpiGuid;\r
+\r
+  PeiPchUsbPolicyPpiDesc->Ppi         = PeiPchUsbPolicyPpi;\r
+\r
+  //\r
+  // Install PCH USB Policy PPI\r
+  //\r
+  Status = (**PeiServices).InstallPpi (PeiServices, PeiPchUsbPolicyPpiDesc);\r
+\r
+  return Status;\r
+}\r

diff --git a/Vlv2TbltDevicePkg/PlatformInitPei/PlatformEarlyInit.c b/Vlv2TbltDevicePkg/PlatformInitPei/PlatformEarlyInit.c
new file mode 100644 (file)
index 0000000..1a12c53
--- /dev/null
+++ b/Vlv2TbltDevicePkg/PlatformInitPei/PlatformEarlyInit.c
@@ -0,0 +1,1034 @@
+/** @file\r
+\r
+  Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+\r
+Module Name:\r
+\r
+  PlatformEarlyInit.c\r
+\r
+Abstract:\r
+\r
+  Do platform specific PEI stage initializations.\r
+\r
+--*/\r
+\r
+\r
+#include "PlatformEarlyInit.h"\r
+\r
+#ifdef __GNUC__\r
+#pragma GCC push_options\r
+#pragma GCC optimize ("O0")\r
+#else\r
+#pragma optimize ("", off)\r
+#endif\r
+\r
+\r
+\r
+static EFI_PEI_STALL_PPI  mStallPpi = {\r
+  PEI_STALL_RESOLUTION,\r
+  Stall\r
+};\r
+\r
+static EFI_PEI_PPI_DESCRIPTOR mInstallStallPpi = {\r
+  EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,\r
+  &gEfiPeiStallPpiGuid,\r
+  &mStallPpi\r
+};\r
+\r
+//\r
+// The reserved SMBus addresses are defined in PlatformDxe.h file.\r
+//\r
+static UINT8 mSmbusRsvdAddresses[] = PLATFORM_SMBUS_RSVD_ADDRESSES;\r
+static PEI_SMBUS_POLICY_PPI         mSmbusPolicyPpi = {\r
+  SMBUS_BASE_ADDRESS,\r
+  SMBUS_BUS_DEV_FUNC,\r
+  PLATFORM_NUM_SMBUS_RSVD_ADDRESSES,\r
+  mSmbusRsvdAddresses\r
+};\r
+\r
+static EFI_PEI_PPI_DESCRIPTOR       mInstallSmbusPolicyPpi = {\r
+  EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,\r
+  &gPeiSmbusPolicyPpiGuid,\r
+  &mSmbusPolicyPpi\r
+};\r
+static PEI_SPEAKER_IF_PPI    mSpeakerInterfacePpi = {\r
+  ProgramToneFrequency,\r
+  GenerateBeepTone\r
+};\r
+\r
+static EFI_PEI_PPI_DESCRIPTOR       mInstallSpeakerInterfacePpi = {\r
+  EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,\r
+  &gPeiSpeakerInterfacePpiGuid,\r
+  &mSpeakerInterfacePpi\r
+};\r
+\r
+static EFI_PEI_RESET_PPI            mResetPpi = { IchReset };\r
+\r
+\r
+static EFI_PEI_FIND_FV_PPI mEfiFindFvPpi = {\r
+  (EFI_PEI_FIND_FV_FINDFV)FindFv\r
+};\r
+\r
+static EFI_PEI_PPI_DESCRIPTOR       mPpiList[] = {\r
+  {\r
+    EFI_PEI_PPI_DESCRIPTOR_PPI,\r
+    &gEfiPeiMasterBootModePpiGuid,\r
+    NULL\r
+  },\r
+  {\r
+    EFI_PEI_PPI_DESCRIPTOR_PPI,\r
+    &gEfiPeiResetPpiGuid,\r
+    &mResetPpi\r
+  },\r
+  {\r
+    (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),\r
+    &gEfiFindFvPpiGuid,\r
+    &mEfiFindFvPpi\r
+  }\r
+};\r
+\r
+static EFI_PEI_NOTIFY_DESCRIPTOR    mNotifyList[] = {\r
+  {\r
+    EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK,\r
+    &gEfiEndOfPeiSignalPpiGuid,\r
+    (EFI_PEIM_NOTIFY_ENTRY_POINT)EndOfPeiPpiNotifyCallback\r
+  },\r
+  {\r
+    (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK| EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),\r
+    &gEfiPeiMemoryDiscoveredPpiGuid,\r
+    (EFI_PEIM_NOTIFY_ENTRY_POINT)MemoryDiscoveredPpiNotifyCallback\r
+  }\r
+\r
+};\r
+\r
+\r
+/**\r
+\r
+  Parse the status registers for figuring out the wake-up event and save it into\r
+  an GUID HOB which will be referenced later. However, modification is required\r
+  to meet the chipset register definition and the practical hardware design. Thus,\r
+  this is just an example.\r
+\r
+\r
+  @param PeiServices    pointer to the PEI Service Table\r
+  @param EFI_SUCCESS    Always return Success\r
+\r
+  @retval None\r
+\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+GetWakeupEventAndSaveToHob (\r
+  IN CONST EFI_PEI_SERVICES   **PeiServices\r
+  )\r
+{\r
+  UINT16  Pm1Sts;\r
+  UINTN   Gpe0Sts;\r
+  UINTN   WakeEventData;\r
+\r
+  //\r
+  // Read the ACPI registers\r
+  //\r
+  Pm1Sts  = IoRead16 (ACPI_BASE_ADDRESS + R_PCH_ACPI_PM1_STS);\r
+  Gpe0Sts = IoRead32 (ACPI_BASE_ADDRESS + R_PCH_ACPI_GPE0a_STS);\r
+\r
+  //\r
+  // Figure out the wake-up event\r
+  //\r
+  if ((Pm1Sts & B_PCH_ACPI_PM1_STS_PWRBTN) != 0) {\r
+    WakeEventData = SMBIOS_WAKEUP_TYPE_POWER_SWITCH;\r
+  } else if (((Pm1Sts & B_PCH_ACPI_PM1_STS_WAK) != 0)) {\r
+    WakeEventData = SMBIOS_WAKEUP_TYPE_PCI_PME;\r
+  } else if (Gpe0Sts != 0) {\r
+    WakeEventData = SMBIOS_WAKEUP_TYPE_OTHERS;\r
+  } else {\r
+    WakeEventData = SMBIOS_WAKEUP_TYPE_UNKNOWN;\r
+  }\r
+\r
+  DEBUG ((EFI_D_ERROR, "ACPI Wake Status Register: %04x\n", Pm1Sts));\r
+\r
+  return EFI_SUCCESS;\r
+}\r
+\r
+EFI_STATUS\r
+GetSetupVariable (\r
+  IN CONST EFI_PEI_SERVICES                **PeiServices,\r
+  IN   SYSTEM_CONFIGURATION          *SystemConfiguration\r
+  )\r
+{\r
+  UINTN                        VariableSize;\r
+  EFI_STATUS                   Status;\r
+  EFI_PEI_READ_ONLY_VARIABLE2_PPI   *Variable;\r
+\r
+  VariableSize = sizeof (SYSTEM_CONFIGURATION);\r
+  ZeroMem (SystemConfiguration, sizeof (SYSTEM_CONFIGURATION));\r
+\r
+  Status = (*PeiServices)->LocatePpi (\r
+                             PeiServices,\r
+                             &gEfiPeiReadOnlyVariable2PpiGuid,\r
+                             0,\r
+                             NULL,\r
+                                      (void **)&Variable\r
+                             );\r
+  ASSERT_EFI_ERROR (Status);\r
+\r
+  //\r
+  // Use normal setup default from NVRAM variable,\r
+  // the Platform Mode (manufacturing/safe/normal) is handle in PeiGetVariable.\r
+  //\r
+  VariableSize = sizeof(SYSTEM_CONFIGURATION);\r
+  Status = Variable->GetVariable (\r
+                       Variable,\r
+                       L"Setup",\r
+                       &gEfiSetupVariableGuid,\r
+                       NULL,\r
+                       &VariableSize,\r
+                       SystemConfiguration\r
+                       );\r
+  ASSERT_EFI_ERROR(Status);\r
+  return Status;\r
+}\r
+\r
+EFI_STATUS\r
+VlvPolicyInit (\r
+  IN CONST EFI_PEI_SERVICES             **PeiServices,\r
+  IN SYSTEM_CONFIGURATION         *SystemConfiguration\r
+  )\r
+{\r
+  EFI_STATUS                      Status;\r
+  EFI_PEI_PPI_DESCRIPTOR          *mVlvPolicyPpiDesc;\r
+  VLV_POLICY_PPI                   *mVlvPolicyPpi;\r
+\r
+  Status = (*PeiServices)->AllocatePool(\r
+                             PeiServices,\r
+                             sizeof (EFI_PEI_PPI_DESCRIPTOR),\r
+                             (void **)&mVlvPolicyPpiDesc\r
+                             );\r
+  ASSERT_EFI_ERROR (Status);\r
+\r
+  Status = (*PeiServices)->AllocatePool(\r
+                             PeiServices,\r
+                             sizeof (VLV_POLICY_PPI),\r
+                             (void **)&mVlvPolicyPpi\r
+                             );\r
+  ASSERT_EFI_ERROR (Status);\r
+\r
+  //\r
+  // Initialize PPI\r
+  //\r
+  (*PeiServices)->SetMem ((VOID *)mVlvPolicyPpi, sizeof (VLV_POLICY_PPI), 0);\r
+  mVlvPolicyPpiDesc->Flags = EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST;\r
+  mVlvPolicyPpiDesc->Guid = &gVlvPolicyPpiGuid;\r
+  mVlvPolicyPpiDesc->Ppi = mVlvPolicyPpi;\r
+  mVlvPolicyPpi->GtConfig.PrimaryDisplay = SystemConfiguration->PrimaryVideoAdaptor;\r
+  mVlvPolicyPpi->GtConfig.IgdDvmt50PreAlloc = SystemConfiguration->IgdDvmt50PreAlloc;\r
+  mVlvPolicyPpi->GtConfig.ApertureSize = SystemConfiguration->IgdApertureSize;\r
+  mVlvPolicyPpi->GtConfig.GttSize = SystemConfiguration->GTTSize;\r
+  if (SystemConfiguration->PrimaryVideoAdaptor != 2) {\r
+    mVlvPolicyPpi->GtConfig.InternalGraphics = SystemConfiguration->Igd;\r
+  } else {\r
+    mVlvPolicyPpi->GtConfig.InternalGraphics = 0;\r
+  }\r
+\r
+\r
+  mVlvPolicyPpi->GtConfig.IgdTurboEn = 1;\r
+\r
+\r
+  mVlvPolicyPpi->PlatformData.FastBoot = SystemConfiguration->FastBoot;\r
+  mVlvPolicyPpi->PlatformData.DynSR = 1;\r
+  DEBUG ((EFI_D_ERROR, "Setup Option ISPEn: 0x%x\n", SystemConfiguration->ISPEn));\r
+  mVlvPolicyPpi->ISPEn                      = SystemConfiguration->ISPEn;\r
+  DEBUG ((EFI_D_ERROR, "Setup Option ISPDevSel: 0x%x\n", SystemConfiguration->ISPDevSel));\r
+  mVlvPolicyPpi->ISPPciDevConfig            = SystemConfiguration->ISPDevSel;\r
+  if (SystemConfiguration->ISPEn == 0) {\r
+    mVlvPolicyPpi->ISPPciDevConfig          = 0;\r
+    DEBUG ((EFI_D_ERROR, "Update Setup Option ISPDevSel: 0x%x\n", mVlvPolicyPpi->ISPPciDevConfig));\r
+  }\r
+  Status = (*PeiServices)->InstallPpi(\r
+                             PeiServices,\r
+                             mVlvPolicyPpiDesc\r
+                             );\r
+  ASSERT_EFI_ERROR (Status);\r
+\r
+  return EFI_SUCCESS;\r
+}\r
+\r
+\r
+EFI_STATUS\r
+ConfigureSoCGpio (\r
+  IN SYSTEM_CONFIGURATION  *SystemConfiguration\r
+  )\r
+{\r
+\r
+    DEBUG ((EFI_D_ERROR, "ConfigureSoCGpio------------start\n"));\r
+    if (SystemConfiguration->eMMCBootMode== 1) {// Auto detection mode\r
+     DEBUG ((EFI_D_ERROR, "Auto detection mode------------start\n"));\r
+\r
+     //\r
+     //Silicon Steppings\r
+     //\r
+     switch (PchStepping()) {\r
+       case PchA0:  // SOC A0 and A1\r
+       case PchA1:\r
+         DEBUG ((EFI_D_ERROR, "SOC A0/A1: eMMC 4.41 GPIO Configuration\n"));\r
+         SystemConfiguration->LpsseMMCEnabled            = 1;\r
+         SystemConfiguration->LpsseMMC45Enabled          = 0;\r
+         break;\r
+       case PchB0:  // SOC B0 and later\r
+       default:\r
+         DEBUG ((EFI_D_ERROR, "SOC B0 and later: eMMC 4.5 GPIO Configuration\n"));\r
+         SystemConfiguration->LpsseMMCEnabled            = 0;\r
+         SystemConfiguration->LpsseMMC45Enabled          = 1;\r
+         break;\r
+     }\r
+    } else if (SystemConfiguration->eMMCBootMode == 2) { // eMMC 4.41\r
+        DEBUG ((EFI_D_ERROR, "Force to eMMC 4.41 GPIO Configuration\n"));\r
+        SystemConfiguration->LpsseMMCEnabled            = 1;\r
+        SystemConfiguration->LpsseMMC45Enabled          = 0;\r
+    } else if (SystemConfiguration->eMMCBootMode == 3) { // eMMC 4.5\r
+         DEBUG ((EFI_D_ERROR, "Force to eMMC 4.5 GPIO Configuration\n"));\r
+         SystemConfiguration->LpsseMMCEnabled            = 0;\r
+         SystemConfiguration->LpsseMMC45Enabled          = 1;\r
+\r
+    } else { // Disable eMMC controllers\r
+         DEBUG ((EFI_D_ERROR, "Disable eMMC GPIO controllers\n"));\r
+         SystemConfiguration->LpsseMMCEnabled            = 0;\r
+         SystemConfiguration->LpsseMMC45Enabled          = 0;\r
+    }\r
+\r
+  /*\r
+  20.1.1  EMMC\r
+  SDMMC1_CLK -         write 0x2003ED01 to IOBASE + 0x03E0\r
+  SDMMC1_CMD -        write 0x2003EC81 to IOBASE + 0x0390\r
+  SDMMC1_D0 -           write 0x2003EC81 to IOBASE + 0x03D0\r
+  SDMMC1_D1 -           write 0x2003EC81 to IOBASE + 0x0400\r
+  SDMMC1_D2 -           write 0x2003EC81 to IOBASE + 0x03B0\r
+  SDMMC1_D3_CD_B - write 0x2003EC81 to IOBASE + 0x0360\r
+  MMC1_D4_SD_WE -   write 0x2003EC81 to IOBASE + 0x0380\r
+  MMC1_D5 -                write 0x2003EC81 to IOBASE + 0x03C0\r
+  MMC1_D6 -                write 0x2003EC81 to IOBASE + 0x0370\r
+  MMC1_D7 -                write 0x2003EC81 to IOBASE + 0x03F0\r
+  MMC1_RESET_B -       write 0x2003ED01 to IOBASE + 0x0330\r
+  */\r
+  if (SystemConfiguration->LpsseMMCEnabled== 1) {\r
+    MmioWrite32 (IO_BASE_ADDRESS + 0x03E0, 0x2003ED01); //EMMC 4.41\r
+    MmioWrite32 (IO_BASE_ADDRESS + 0x0390, 0x2003EC81);\r
+    MmioWrite32 (IO_BASE_ADDRESS + 0x03D0, 0x2003EC81);\r
+    MmioWrite32 (IO_BASE_ADDRESS + 0x0400, 0x2003EC81);\r
+    MmioWrite32 (IO_BASE_ADDRESS + 0x03B0, 0x2003EC81);\r
+    MmioWrite32 (IO_BASE_ADDRESS + 0x0360, 0x2003EC81);\r
+    MmioWrite32 (IO_BASE_ADDRESS + 0x0380, 0x2003EC81);\r
+    MmioWrite32 (IO_BASE_ADDRESS + 0x03C0, 0x2003EC81);\r
+    MmioWrite32 (IO_BASE_ADDRESS + 0x0370, 0x2003EC81);\r
+    MmioWrite32 (IO_BASE_ADDRESS + 0x03F0, 0x2003EC81);\r
+    MmioWrite32 (IO_BASE_ADDRESS + 0x0330, 0x2003ED01);\r
+  }\r
+\r
+  /*\r
+  eMMC 4.5 controller\r
+  SDMMC1_CLK -         write 0x2003ED03 to IOBASE + 0x03E0\r
+  SDMMC1_CMD -        write 0x2003EC83 to IOBASE + 0x0390\r
+  SDMMC1_D0 -           write 0x2003EC83 to IOBASE + 0x03D0\r
+  SDMMC1_D1 -           write 0x2003EC83 to IOBASE + 0x0400\r
+  SDMMC1_D2 -           write 0x2003EC83 to IOBASE + 0x03B0\r
+  SDMMC1_D3_CD_B -  write 0x2003EC83 to IOBASE + 0x0360\r
+  MMC1_D4_SD_WE -   write 0x2003EC83 to IOBASE + 0x0380\r
+  MMC1_D5 -                write 0x2003EC83 to IOBASE + 0x03C0\r
+  MMC1_D6 -                write 0x2003EC83 to IOBASE + 0x0370\r
+  MMC1_D7 -                write 0x2003EC83 to IOBASE + 0x03F0\r
+  MMC1_RESET_B -       write 0x2003ED03 to IOBASE + 0x0330\r
+  */\r
+  if (SystemConfiguration->LpsseMMC45Enabled== 1) {\r
+    MmioWrite32 (IO_BASE_ADDRESS + 0x03E0, 0x2003ED03); // EMMC 4.5\r
+    MmioWrite32 (IO_BASE_ADDRESS + 0x0390, 0x2003EC83);\r
+    MmioWrite32 (IO_BASE_ADDRESS + 0x03D0, 0x2003EC83);\r
+    MmioWrite32 (IO_BASE_ADDRESS + 0x0400, 0x2003EC83);\r
+    MmioWrite32 (IO_BASE_ADDRESS + 0x03B0, 0x2003EC83);\r
+    MmioWrite32 (IO_BASE_ADDRESS + 0x0360, 0x2003EC83);\r
+    MmioWrite32 (IO_BASE_ADDRESS + 0x0380, 0x2003EC83);\r
+    MmioWrite32 (IO_BASE_ADDRESS + 0x03C0, 0x2003EC83);\r
+    MmioWrite32 (IO_BASE_ADDRESS + 0x0370, 0x2003EC83);\r
+    MmioWrite32 (IO_BASE_ADDRESS + 0x03F0, 0x2003EC83);\r
+    MmioWrite32 (IO_BASE_ADDRESS + 0x0330, 0x2003ED03);\r
+\r
+  }\r
+\r
+//\r
+// Change GPIOC_0 setting to allow MMIO access under Android.\r
+//\r
+  IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SC_USE_SEL,\r
+           (IoRead32(GPIO_BASE_ADDRESS + R_PCH_GPIO_SC_USE_SEL) & (UINT32)~BIT0));\r
+  DEBUG ((EFI_D_ERROR, "ConfigureSoCGpio------------end\n"));\r
+  return EFI_SUCCESS;\r
+}\r
+\r
+EFI_STATUS\r
+MeasuredBootInit (\r
+  IN CONST EFI_PEI_SERVICES        **PeiServices,\r
+  IN SYSTEM_CONFIGURATION           *SystemConfiguration\r
+  )\r
+{\r
+  if (SystemConfiguration->MeasuredBootEnable) {\r
+    PcdSetBool (PcdMeasuredBootEnable, TRUE);\r
+  } else {\r
+    PcdSetBool (PcdMeasuredBootEnable, FALSE);\r
+  }\r
+\r
+  return EFI_SUCCESS;\r
+}\r
+\r
+\r
+EFI_STATUS\r
+ConfigureLpssAndSccGpio (\r
+  IN SYSTEM_CONFIGURATION        *SystemConfiguration,\r
+  IN EFI_PLATFORM_INFO_HOB       *PlatformInfo\r
+  )\r
+{\r
+  /*One time configuration to each GPIO controller PSB_CONF register should be done before starting pad configuration:\r
+  GPIO SCORE -  write 0x01001002 to IOBASE + 0x0700\r
+  GPIO NCORE -  write 0x01001002 to IOBASE + 0x0F00\r
+  GPIO SSUS -    write 0x01001002 to IOBASE + 0x1700\r
+  */\r
+    DEBUG ((EFI_D_ERROR, "ConfigureLpssAndSccGpio------------start\n"));\r
+\r
+  /*\r
+  19.1.1  PWM0\r
+  PWM0 - write 0x2003CD01 to IOBASE + 0x00A0\r
+  19.1.2  PWM1\r
+  PWM0 - write 0x2003CD01 to IOBASE + 0x00B0\r
+  */\r
+  if (SystemConfiguration->LpssPwm0Enabled== 1) {\r
+    MmioWrite32 (IO_BASE_ADDRESS + 0x00A0, 0x2003CD01);\r
+  } else if (SystemConfiguration->LpssPwm0Enabled== 0) {\r
+    MmioWrite32 (IO_BASE_ADDRESS + 0x00A0, 0x2003CD00);\r
+  }\r
+\r
+  if (SystemConfiguration->LpssPwm1Enabled== 1) {\r
+    MmioWrite32 (IO_BASE_ADDRESS + 0x00B0, 0x2003CC01);\r
+  } else if (SystemConfiguration->LpssPwm1Enabled== 0) {\r
+    MmioWrite32 (IO_BASE_ADDRESS + 0x00B0, 0x2003CD00);\r
+  }\r
+\r
+  /*\r
+  19.1.3  UART1\r
+  UART1_RXD-L -     write 0x2003CC81 to IOBASE + 0x0020\r
+  UART1_TXD-0 -     write 0x2003CC81 to IOBASE + 0x0010\r
+  UART1_RTS_B-1 - write 0x2003CC81 to IOBASE + 0x0000\r
+  UART1_CTS_B-H - write 0x2003CC81 to IOBASE + 0x0040\r
+  */\r
+  if (SystemConfiguration->LpssHsuart0Enabled== 1) {\r
+    MmioWrite32 (IO_BASE_ADDRESS + 0x0020, 0x2003CC81); // uart1\r
+    MmioWrite32 (IO_BASE_ADDRESS + 0x0010, 0x2003CC81);\r
+  if (SystemConfiguration->LpssHsuart0FlowControlEnabled== 0) {\r
+    DEBUG ((EFI_D_ERROR, "LpssHsuart0FlowControlEnabled[0]\n"));\r
+    MmioWrite32 (IO_BASE_ADDRESS + 0x0000, 0x2003CC80);\r
+    MmioWrite32 (IO_BASE_ADDRESS + 0x0040, 0x2003CC80);\r
+  } else {\r
+    DEBUG ((EFI_D_ERROR, "LpssHsuart0FlowControlEnabled[1]\n"));\r
+    MmioWrite32 (IO_BASE_ADDRESS + 0x0000, 0x2003CC81);\r
+    MmioWrite32 (IO_BASE_ADDRESS + 0x0040, 0x2003CC01);//W/A HSD 4752617 0x2003CC81\r
+    }\r
+  } else if (SystemConfiguration->LpssHsuart0Enabled== 0) {\r
+    MmioWrite32 (IO_BASE_ADDRESS + 0x0020, 0x2003CC80); // uart1\r
+    MmioWrite32 (IO_BASE_ADDRESS + 0x0010, 0x2003CC80);\r
+  }\r
+\r
+\r
+  /*\r
+  19.1.4  UART2\r
+  UART2_RTS_B-1 -  write 0x2003CC81 to IOBASE + 0x0090\r
+  UART2_CTS_B-H - write 0x2003CC81 to IOBASE + 0x0080\r
+  UART2_RXD-H -    write 0x2003CC81 to IOBASE + 0x0060\r
+  UART2_TXD-0 -     write 0x2003CC81 to IOBASE + 0x0070\r
+  */\r
+  if (SystemConfiguration->LpssHsuart1Enabled== 1) {\r
+    MmioWrite32 (IO_BASE_ADDRESS + 0x0060, 0x2003CC81);\r
+    MmioWrite32 (IO_BASE_ADDRESS + 0x0070, 0x2003CC81);\r
+\r
+  if (SystemConfiguration->LpssHsuart1FlowControlEnabled== 0) {\r
+    DEBUG ((EFI_D_ERROR, "LpssHsuart1FlowControlEnabled[0]\n"));\r
+    MmioWrite32 (IO_BASE_ADDRESS + 0x0090, 0x2003CC80); // UART2_RTS_B\r
+    MmioWrite32 (IO_BASE_ADDRESS + 0x0080, 0x2003CC80); // UART2_CTS_B\r
+  } else {\r
+    DEBUG ((EFI_D_ERROR, "LpssHsuart1FlowControlEnabled[1]\n"));\r
+    MmioWrite32 (IO_BASE_ADDRESS + 0x0090, 0x2003CC81); // uart2\r
+    MmioWrite32 (IO_BASE_ADDRESS + 0x0080, 0x2003CC01); //W/A HSD 4752617 0x2003CC81\r
+  }\r
+  } else if (SystemConfiguration->LpssHsuart1Enabled== 0) {\r
+  MmioWrite32 (IO_BASE_ADDRESS + 0x0060, 0x2003CC80);\r
+  MmioWrite32 (IO_BASE_ADDRESS + 0x0070, 0x2003CC80);\r
+  }\r
+\r
+  /*\r
+  19.1.5  SPI\r
+  SPI1_CS0_B - write 0x2003CC81 to IOBASE + 0x0110\r
+  SPI1_CLK -     write 0x2003CD01 to IOBASE + 0x0100\r
+  SPI1_MOSI -   write 0x2003CC81 to IOBASE + 0x0130\r
+  SPI1_MISO -   write 0x2003CC81 to IOBASE + 0x0120\r
+  */\r
+  if (SystemConfiguration->LpssSpiEnabled== 1) {\r
+    MmioWrite32 (IO_BASE_ADDRESS + 0x0110, 0x2003CC81); // SPI\r
+    MmioWrite32 (IO_BASE_ADDRESS + 0x0100, 0x2003CD01);\r
+    MmioWrite32 (IO_BASE_ADDRESS + 0x0130, 0x2003CC81);\r
+    MmioWrite32 (IO_BASE_ADDRESS + 0x0120, 0x2003CC81);\r
+  } else if (SystemConfiguration->LpssSpiEnabled== 0) {\r
+    MmioWrite32 (IO_BASE_ADDRESS + 0x0110, 0x2003cc80);\r
+    MmioWrite32 (IO_BASE_ADDRESS + 0x0100, 0x2003cc80);\r
+    MmioWrite32 (IO_BASE_ADDRESS + 0x0130, 0x2003cc80);\r
+    MmioWrite32 (IO_BASE_ADDRESS + 0x0120, 0x2003cc80);\r
+  }\r
+\r
+  /*\r
+  19.1.6  I2C0\r
+  I2C0_SDA-OD-O -    write 0x2003CC81 to IOBASE + 0x0210\r
+  I2C0_SCL-OD-O -    write 0x2003CC81 to IOBASE + 0x0200\r
+  */\r
+  if (SystemConfiguration->LpssI2C0Enabled== 1) {\r
+    MmioWrite32 (IO_BASE_ADDRESS + 0x0210, 0x2003C881);\r
+    MmioWrite32 (IO_BASE_ADDRESS + 0x0200, 0x2003C881);\r
+  }\r
+  /*\r
+  19.1.7  I2C1\r
+  I2C1_SDA-OD-O/I - write 0x2003CC81 to IOBASE + 0x01F0\r
+  I2C1_SCL-OD-O/I - write 0x2003CC81 to IOBASE + 0x01E0\r
+  */\r
+\r
+  if (SystemConfiguration->LpssI2C1Enabled== 1) {\r
+    MmioWrite32 (IO_BASE_ADDRESS + 0x01F0, 0x2003C881);\r
+    MmioWrite32 (IO_BASE_ADDRESS + 0x01E0, 0x2003C881);\r
+  }\r
+  /*\r
+  19.1.8  I2C2\r
+  I2C2_SDA-OD-O/I - write 0x2003CC81 to IOBASE + 0x01D0\r
+  I2C2_SCL-OD-O/I - write 0x2003CC81 to IOBASE + 0x01B0\r
+  */\r
+  if (SystemConfiguration->LpssI2C2Enabled== 1) {\r
+    MmioWrite32 (IO_BASE_ADDRESS + 0x01D0, 0x2003C881);\r
+    MmioWrite32 (IO_BASE_ADDRESS + 0x01B0, 0x2003C881);\r
+  }\r
+  /*\r
+  19.1.9  I2C3\r
+  I2C3_SDA-OD-O/I - write 0x2003CC81 to IOBASE + 0x0190\r
+  I2C3_SCL-OD-O/I - write 0x2003CC81 to IOBASE + 0x01C0\r
+  */\r
+  if (SystemConfiguration->LpssI2C3Enabled== 1) {\r
+    MmioWrite32 (IO_BASE_ADDRESS + 0x0190, 0x2003C881);\r
+    MmioWrite32 (IO_BASE_ADDRESS + 0x01C0, 0x2003C881);\r
+  }\r
+  /*\r
+  19.1.10 I2C4\r
+  I2C4_SDA-OD-O/I - write 0x2003CC81 to IOBASE + 0x01A0\r
+  I2C4_SCL-OD-O/I - write 0x2003CC81 to IOBASE + 0x0170\r
+  */\r
+  if (SystemConfiguration->LpssI2C4Enabled== 1) {\r
+    MmioWrite32 (IO_BASE_ADDRESS + 0x01A0, 0x2003C881);\r
+    MmioWrite32 (IO_BASE_ADDRESS + 0x0170, 0x2003C881);\r
+  }\r
+  /*\r
+  19.1.11 I2C5\r
+  I2C5_SDA-OD-O/I - write 0x2003CC81 to IOBASE + 0x0150\r
+  I2C5_SCL-OD-O/I - write 0x2003CC81 to IOBASE + 0x0140\r
+  */\r
+  //touch 1.7M support on i2c5(from 0) need 2k PULL-UP.\r
+  if (SystemConfiguration->LpssI2C5Enabled== 1) {\r
+    MmioWrite32 (IO_BASE_ADDRESS + 0x0150, 0x2003C881);\r
+    MmioWrite32 (IO_BASE_ADDRESS + 0x0140, 0x2003C881);\r
+  } else if(SystemConfiguration->LpssI2C5Enabled== 0) {\r
+    MmioWrite32 (IO_BASE_ADDRESS + 0x0150, 0x2003C880);\r
+    MmioWrite32 (IO_BASE_ADDRESS + 0x0140, 0x2003C880);\r
+  }\r
+  /*\r
+  19.1.12 I2C6\r
+  I2C6_SDA-OD-O/I - write 0x2003CC81 to IOBASE + 0x0180\r
+  I2C6_SCL-OD-O/I -  write 0x2003CC81 to IOBASE + 0x0160\r
+  */\r
+  if (SystemConfiguration->LpssI2C6Enabled== 1) {\r
+    MmioWrite32 (IO_BASE_ADDRESS + 0x0180, 0x2003C881);\r
+    MmioWrite32 (IO_BASE_ADDRESS + 0x0160, 0x2003C881);\r
+  } else if (SystemConfiguration->LpssI2C6Enabled== 0) {\r
+    MmioWrite32 (IO_BASE_ADDRESS + 0x0180, 0x2003C880);\r
+    MmioWrite32 (IO_BASE_ADDRESS + 0x0160, 0x2003C880);\r
+  }\r
+\r
+\r
+  /*\r
+  20.1.2  SDIO\r
+  SDMMC2_CLK -  write 0x2003ED01 to IOBASE + 0x0320\r
+  SDMMC2_CMD - write 0x2003EC81 to IOBASE + 0x0300\r
+  SDMMC2_D0 -    write 0x2003EC81 to IOBASE + 0x0350\r
+  SDMMC2_D1 -    write 0x2003EC81 to IOBASE + 0x02F0\r
+  SDMMC2_D2 -    write 0x2003EC81 to IOBASE + 0x0340\r
+  SDMMC2_D3_CD_B - write 0x2003EC81 to IOBASE + 0x0310\r
+  */\r
+  if (SystemConfiguration->LpssSdioEnabled== 1) {\r
+    MmioWrite32 (IO_BASE_ADDRESS + 0x0320, 0x2003ED01);//SDIO\r
+    MmioWrite32 (IO_BASE_ADDRESS + 0x0300, 0x2003EC81);\r
+    MmioWrite32 (IO_BASE_ADDRESS + 0x0350, 0x2003EC81);\r
+    MmioWrite32 (IO_BASE_ADDRESS + 0x02F0, 0x2003EC81);\r
+    MmioWrite32 (IO_BASE_ADDRESS + 0x0340, 0x2003EC81);\r
+    MmioWrite32 (IO_BASE_ADDRESS + 0x0310, 0x2003EC81);\r
+  }\r
+\r
+  /*\r
+  20.1.3  SD Card\r
+  SDMMC3_1P8_EN - write 0x2003CD01 to IOBASE + 0x03F0\r
+  SDMMC3_CD_B -    write 0x2003CC81 to IOBASE + 0x03A0\r
+  SDMMC3_CLK -       write 0x2003CD01 to IOBASE + 0x02B0\r
+  SDMMC3_CMD -      write 0x2003CC81 to IOBASE + 0x02C0\r
+  SDMMC3_D0 -         write 0x2003CC81 to IOBASE + 0x02E0\r
+  SDMMC3_D1 -         write 0x2003CC81 to IOBASE + 0x0290\r
+  SDMMC3_D2 -         write 0x2003CC81 to IOBASE + 0x02D0\r
+  SDMMC3_D3 -         write 0x2003CC81 to IOBASE + 0x02A0\r
+  SDMMC3_PWR_EN_B - write 0x2003CC81 to IOBASE + 0x0690\r
+  SDMMC3_WP -            write 0x2003CC82 to IOBASE + 0x0160\r
+  */\r
+  if (SystemConfiguration->LpssSdcardEnabled == 1) {\r
+    if (!((PlatformInfo->BoardId == BOARD_ID_BL_FFRD && PlatformInfo->BoardRev== PR11) && (SystemConfiguration->CfioPnpSettings == 1))) {\r
+      MmioWrite32 (IO_BASE_ADDRESS + 0x05F0, 0x2003CD01);//SDCARD\r
+      MmioWrite32 (IO_BASE_ADDRESS + 0x02B0, 0x2003CD01);\r
+      MmioWrite32 (IO_BASE_ADDRESS + 0x02C0, 0x2003CC81);\r
+      MmioWrite32 (IO_BASE_ADDRESS + 0x02E0, 0x2003CC81);\r
+      MmioWrite32 (IO_BASE_ADDRESS + 0x0290, 0x2003CC81);\r
+      MmioWrite32 (IO_BASE_ADDRESS + 0x02D0, 0x2003CC81);\r
+      MmioWrite32 (IO_BASE_ADDRESS + 0x02A0, 0x2003CC81);\r
+      MmioWrite32 (IO_BASE_ADDRESS + 0x0690, 0x2003CC81);\r
+      MmioWrite32 (IO_BASE_ADDRESS + 0x0650, 0x2003CC82); //GPIOC_7 set to WP Pin\r
+     }\r
+  }\r
+\r
+\r
+     DEBUG ((EFI_D_ERROR, "ConfigureLpssAndSccGpio------------end\n"));\r
+    return EFI_SUCCESS;\r
+}\r
+\r
+EFI_STATUS\r
+ConfigureLpeGpio (\r
+  IN SYSTEM_CONFIGURATION  *SystemConfiguration\r
+  )\r
+{\r
+  DEBUG ((EFI_D_ERROR, "ConfigureLpeGpio------------start\n"));\r
+\r
+  if (SystemConfiguration->PchAzalia == 0) {\r
+    MmioAndThenOr32 (IO_BASE_ADDRESS + 0x220, (UINT32)~(0x7), (UINT32) (0x01));\r
+    MmioAndThenOr32 (IO_BASE_ADDRESS + 0x250, (UINT32)~(0x7), (UINT32) (0x01));\r
+    MmioAndThenOr32 (IO_BASE_ADDRESS + 0x240, (UINT32)~(0x7), (UINT32) (0x01));\r
+    MmioAndThenOr32 (IO_BASE_ADDRESS + 0x260, (UINT32)~(0x7), (UINT32) (0x01));\r
+    MmioAndThenOr32 (IO_BASE_ADDRESS + 0x270, (UINT32)~(0x7), (UINT32) (0x01));\r
+    MmioAndThenOr32 (IO_BASE_ADDRESS + 0x230, (UINT32)~(0x7), (UINT32) (0x01));\r
+    MmioAndThenOr32 (IO_BASE_ADDRESS + 0x280, (UINT32)~(0x7), (UINT32) (0x01));\r
+    MmioAndThenOr32 (IO_BASE_ADDRESS + 0x540, (UINT32)~(0x7), (UINT32) (0x01));\r
+  }\r
+\r
+  DEBUG ((EFI_D_ERROR, "ConfigureLpeGpio------------end\n"));\r
+\r
+  return EFI_SUCCESS;\r
+}\r
+\r
+EFI_STATUS\r
+ConfigureSciSmiGpioRout (\r
+  IN EFI_PLATFORM_INFO_HOB       *PlatformInfo)\r
+{\r
+       UINT32  GPI_Routing;\r
+\r
+       GPI_Routing = MmioRead32 (PMC_BASE_ADDRESS + R_PCH_PMC_GPI_ROUT);\r
+\r
+       //\r
+       // For FAB3, Route GPIO_CORE 0 to cause Runtime SCI, GPIO_SUS 0 to cause Wake SCI and GPIO_SUS 7 to cause EXTSMI\r
+       //\r
+       if(PlatformInfo->BoardRev == 3) {\r
+       GPI_Routing = GPI_Routing & 0xfffc3ffc;\r
+       GPI_Routing = GPI_Routing | 0x00024002;\r
+       }\r
+\r
+       //\r
+       // For FAB2/1, Route GPIO_CORE 7 to cause Runtime SCI, GPIO_SUS 0 to cause Wake SCI and GPIO_SUS 7 to cause EXTSMI\r
+       //\r
+       else {\r
+       GPI_Routing = GPI_Routing & 0x3fff3ffc;\r
+       GPI_Routing = GPI_Routing | 0x80004002;\r
+       }\r
+       MmioWrite32((PMC_BASE_ADDRESS + R_PCH_PMC_GPI_ROUT), GPI_Routing);\r
+\r
+       return EFI_SUCCESS;\r
+}\r
+\r
+EFI_STATUS\r
+ConfigureMipiCsi (\r
+  VOID)\r
+{\r
+         //\r
+    //Configure the platform clock for MIPI-CSI usage\r
+    //PLT_CLK0\r
+    //\r
+    MmioAndThenOr32 (IO_BASE_ADDRESS + 0x6a0, (UINT32)~(0x7), (UINT32) (0x01));\r
+\r
+    //\r
+    //PLT_CLK1\r
+    //\r
+    MmioAndThenOr32 (IO_BASE_ADDRESS + 0x570, (UINT32)~(0x7), (UINT32) (0x01));\r
+\r
+    //\r
+    //PLT_CLK2\r
+    //\r
+    MmioAndThenOr32 (IO_BASE_ADDRESS + 0x5B0, (UINT32)~(0x7), (UINT32) (0x01));\r
+\r
+    return EFI_SUCCESS;\r
+}\r
+\r
+EFI_STATUS\r
+ConfigureUSBULPI (\r
+  VOID)\r
+{\r
+         //\r
+    //Configure USB ULPI\r
+    //USB_ULPI_0_CLK\r
+    //\r
+    MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x338, (UINT32)~(0x7), (UINT32) (GPI));\r
+    MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x330, (UINT32)~(0x187), (UINT32) (0x101));\r
+\r
+    //\r
+    //USB_ULPI_0_DATA0\r
+    //\r
+    MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x388, (UINT32)~(0x7), (UINT32) (GPI));\r
+    MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x380, (UINT32)~(0x187), (UINT32) (0x101));\r
+\r
+    //\r
+    //USB_ULPI_0_DATA1\r
+    //\r
+    MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x368, (UINT32)~(0x7), (UINT32) (GPI));\r
+    MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x360, (UINT32)~(0x187), (UINT32) (0x101));\r
+\r
+    //\r
+    //USB_ULPI_0_DATA2\r
+    //\r
+    MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x318, (UINT32)~(0x7), (UINT32) (GPI));\r
+    MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x310, (UINT32)~(0x187), (UINT32) (0x101));\r
+\r
+    //\r
+    //USB_ULPI_0_DATA3\r
+    //\r
+    MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x378, (UINT32)~(0x7), (UINT32) (GPI));\r
+    MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x370, (UINT32)~(0x187), (UINT32) (0x101));\r
+\r
+    //\r
+    //USB_ULPI_0_DATA4\r
+    //\r
+    MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x308, (UINT32)~(0x7), (UINT32) (GPI));\r
+    MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x300, (UINT32)~(0x187), (UINT32) (0x101));\r
+\r
+    //\r
+    //USB_ULPI_0_DATA5\r
+    //\r
+    MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x398, (UINT32)~(0x7), (UINT32) (GPI));\r
+    MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x390, (UINT32)~(0x187), (UINT32) (0x101));\r
+\r
+    //\r
+    //USB_ULPI_0_DATA6\r
+    //\r
+    MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x328, (UINT32)~(0x7), (UINT32) (GPI));\r
+    MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x320, (UINT32)~(0x187), (UINT32) (0x101));\r
+\r
+    //\r
+    //USB_ULPI_0_DATA7\r
+    //\r
+    MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x3a8, (UINT32)~(0x7), (UINT32) (GPI));\r
+    MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x3a0, (UINT32)~(0x187), (UINT32) (0x101));\r
+\r
+    //\r
+    //USB_ULPI_0_DIR\r
+    //\r
+    MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x348, (UINT32)~(0x7), (UINT32) (GPI));\r
+    MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x340, (UINT32)~(0x187), (UINT32) (0x81));\r
+\r
+    //\r
+    //USB_ULPI_0_NXT\r
+    //\r
+    MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x358, (UINT32)~(0x7), (UINT32) (GPI));\r
+    MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x350, (UINT32)~(0x187), (UINT32) (0x101));\r
+\r
+    //\r
+    //USB_ULPI_0_STP\r
+    //\r
+    MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x3b8, (UINT32)~(0x7), (UINT32) (GPI));\r
+    MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x3b0, (UINT32)~(0x187), (UINT32) (0x81));\r
+\r
+    //\r
+    //USB_ULPI_0_REFCLK\r
+    //\r
+    MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x288, (UINT32)~(0x7), (UINT32) (GPI));\r
+    MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x280, (UINT32)~(0x187), (UINT32) (0x101));\r
+\r
+    return EFI_SUCCESS;\r
+}\r
+\r
+EFI_STATUS\r
+DisableRTD3 (\r
+  VOID)\r
+{\r
+         //\r
+    //Disable RTD3\r
+    //\r
+    MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x210, (UINT32)~(0x0f000007), (UINT32) (0x00));\r
+    MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x1e0, (UINT32)~(0x0f000007), (UINT32) (0x00));\r
+\r
+    return EFI_SUCCESS;\r
+}\r
+\r
+/**\r
+  Platform specific initializations in stage1.\r
+\r
+  @param FfsHeader         Pointer to the PEIM FFS file header.\r
+  @param PeiServices       General purpose services available to every PEIM.\r
+\r
+  @retval EFI_SUCCESS       Operation completed successfully.\r
+  @retval Otherwise         Platform initialization failed.\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+PlatformEarlyInitEntry (\r
+\r
+  IN       EFI_PEI_FILE_HANDLE  FileHandle,\r
+  IN CONST EFI_PEI_SERVICES    **PeiServices\r
+  )\r
+{\r
+  EFI_STATUS                  Status;\r
+  SYSTEM_CONFIGURATION        SystemConfiguration;\r
+  EFI_PLATFORM_INFO_HOB       *PlatformInfo;\r
+  EFI_PEI_HOB_POINTERS        Hob;\r
+  EFI_PLATFORM_CPU_INFO       PlatformCpuInfo;\r
+\r
+  //\r
+  // Initialize SmbusPolicy PPI\r
+  //\r
+  Status = (*PeiServices)->InstallPpi(PeiServices, &mInstallSmbusPolicyPpi);\r
+  ASSERT_EFI_ERROR (Status);\r
+\r
+  //\r
+  // Initialize Stall PPIs\r
+  //\r
+  Status = (*PeiServices)->InstallPpi (PeiServices, &mInstallStallPpi);\r
+  ASSERT_EFI_ERROR (Status);\r
+\r
+  //\r
+  // Initialize platform PPIs\r
+  //\r
+  Status = (*PeiServices)->InstallPpi (PeiServices, &mInstallSpeakerInterfacePpi);\r
+  ASSERT_EFI_ERROR (Status);\r
+\r
+  //\r
+  // Variable initialization\r
+  //\r
+  ZeroMem(&PlatformCpuInfo, sizeof(EFI_PLATFORM_CPU_INFO));\r
+\r
+  //\r
+  // Set the some PCI and chipset range as UC\r
+  // And align to 1M at leaset\r
+  //\r
+  Hob.Raw = GetFirstGuidHob (&gEfiPlatformInfoGuid);\r
+  ASSERT (Hob.Raw != NULL);\r
+  PlatformInfo = GET_GUID_HOB_DATA(Hob.Raw);\r
+\r
+  //\r
+  // Initialize PlatformInfo HOB\r
+  //\r
+  MultiPlatformInfoInit(PeiServices, PlatformInfo);\r
+\r
+  //\r
+  // Do basic MCH init\r
+  //\r
+  MchInit (PeiServices);\r
+\r
+  //\r
+  // Set the new boot mode\r
+  //\r
+  Status = UpdateBootMode (PeiServices, PlatformInfo);\r
+  ASSERT_EFI_ERROR (Status);\r
+\r
+  SetPlatformBootMode (PeiServices, PlatformInfo);\r
+\r
+  //\r
+  // Get setup variable. This can only be done after BootMode is updated\r
+  //\r
+  GetSetupVariable (PeiServices, &SystemConfiguration);\r
+\r
+  CheckOsSelection(PeiServices, &SystemConfiguration);\r
+\r
+  //\r
+  // Update PlatformInfo HOB according to setup variable\r
+  //\r
+  PlatformInfoUpdate(PeiServices, PlatformInfo, &SystemConfiguration);\r
+\r
+  InitializePlatform (PeiServices, PlatformInfo, &SystemConfiguration);\r
+\r
+  //\r
+  // Initialize VlvPolicy PPI\r
+  //\r
+  Status = VlvPolicyInit (PeiServices, &SystemConfiguration);\r
+  ASSERT_EFI_ERROR (Status);\r
+\r
+  //\r
+  // Soc specific GPIO setting\r
+  //\r
+  ConfigureSoCGpio(&SystemConfiguration);\r
+\r
+  //\r
+  //  Baylake Board specific.\r
+  //\r
+  if (PlatformInfo->BoardId == BOARD_ID_BL_RVP  ||\r
+      PlatformInfo->BoardId == BOARD_ID_BL_FFRD ||\r
+           PlatformInfo->BoardId == BOARD_ID_BL_FFRD8 ||\r
+      PlatformInfo->BoardId == BOARD_ID_BL_RVP_DDR3L ||\r
+      PlatformInfo->BoardId == BOARD_ID_BL_STHI ||\r
+      PlatformInfo->BoardId == BOARD_ID_BB_RVP ||\r
+      PlatformInfo->BoardId == BOARD_ID_BS_RVP ||\r
+      PlatformInfo->BoardId == BOARD_ID_MINNOW2 ||\r
+      PlatformInfo->BoardId == BOARD_ID_CVH) {\r
+    ConfigureLpssAndSccGpio(&SystemConfiguration, PlatformInfo);\r
+\r
+  }\r
+\r
+\r
+  //\r
+  //  Configure LPE\r
+  //  Alpine Valley and Bayley Bay board specific\r
+  //\r
+  ConfigureLpeGpio(&SystemConfiguration);\r
+\r
+  //\r
+  //  Bayley Bay Board specific.\r
+  //\r
+  ConfigureSciSmiGpioRout(PlatformInfo);\r
+  if (SystemConfiguration.LpssI2C3Enabled == 1) {\r
+    ConfigureMipiCsi();\r
+  }\r
+\r
+\r
+  //\r
+  // Do basic CPU init\r
+  //\r
+  Status = PlatformCpuInit (PeiServices, &SystemConfiguration, &PlatformCpuInfo);\r
+\r
+  //\r
+  // Perform basic SSA related platform initialization\r
+  //\r
+  PlatformSsaInit (&SystemConfiguration,PeiServices);\r
+\r
+\r
+  //\r
+  // Do basic PCH init\r
+  //\r
+  Status = PlatformPchInit (&SystemConfiguration, PeiServices, PlatformInfo->PlatformType);\r
+  ASSERT_EFI_ERROR (Status);\r
+\r
+  //\r
+  // Initialize platform PPIs\r
+  //\r
+  Status = (*PeiServices)->InstallPpi (PeiServices, &mPpiList[0]);\r
+  ASSERT_EFI_ERROR (Status);\r
+\r
+  if (PlatformInfo->BoardId != BOARD_ID_CVH) {\r
+    InstallPlatformClocksNotify (PeiServices);\r
+    InstallPlatformSysCtrlGPIONotify(PeiServices);\r
+  }\r
+\r
+  //\r
+  // Initialize platform PPIs\r
+  //\r
+  Status = (*PeiServices)->NotifyPpi(PeiServices, &mNotifyList[0]);\r
+  ASSERT_EFI_ERROR (Status);\r
+\r
+  //\r
+  // Initialize Measured Boot\r
+  //\r
+  Status = MeasuredBootInit (PeiServices, &SystemConfiguration);\r
+  ASSERT_EFI_ERROR (Status);\r
+\r
+  return Status;\r
+}\r
+\r
+/**\r
+\r
+  Return the mainblockcompact Fv.\r
+\r
+  @param FvNumber    Our enumeration of the firmware volumes we care about.\r
+\r
+  @param FvAddress  Base Address of the memory containing the firmware volume\r
+\r
+  @retval EFI_SUCCESS\r
+  @retval EFI_NOT_FOUND\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+FindFv (\r
+  IN EFI_PEI_FIND_FV_PPI          *This,\r
+  IN CONST EFI_PEI_SERVICES             **PeiServices,\r
+  IN OUT UINT8                    *FvNumber,\r
+  OUT EFI_FIRMWARE_VOLUME_HEADER  **FVAddress\r
+  )\r
+{\r
+       //\r
+  // At present, we only have one Fv to search\r
+  //\r
+  if (*FvNumber == 0) {\r
+    *FvNumber = 1;\r
+    *FVAddress = (EFI_FIRMWARE_VOLUME_HEADER *)(UINTN)FixedPcdGet32 (PcdFlashFvMainBase);\r
+    return EFI_SUCCESS;\r
+  }\r
+  else if (*FvNumber == 1) {\r
+    *FvNumber = 2;\r
+    *FVAddress = (EFI_FIRMWARE_VOLUME_HEADER *)(UINTN)FixedPcdGet32 (PcdFlashFvRecovery2Base);\r
+    return EFI_SUCCESS;\r
+  }\r
+  else { // Not the one Fv we care about\r
+    return EFI_NOT_FOUND;\r
+  }\r
+}\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+CpuOnlyReset (\r
+  IN CONST EFI_PEI_SERVICES   **PeiServices\r
+  )\r
+{\r
+//  MsgBus32Write(CDV_UNIT_PUNIT, PUNIT_CPU_RST, 0x01)\r
+#ifdef __GNUC__\r
+  __asm__\r
+  (\r
+   "xorl %ecx, %ecx\n"\r
+   "1:hlt; hlt; hlt\n"\r
+   "jmp 1b\n"\r
+  );\r
+#else\r
+  _asm {\r
+    xor   ecx, ecx\r
+  HltLoop:\r
+    hlt\r
+    hlt\r
+    hlt\r
+    loop  HltLoop\r
+  }\r
+#endif\r
+  //\r
+  // If we get here we need to mark it as a failure.\r
+  //\r
+  return EFI_UNSUPPORTED;\r
+}\r
+\r
+\r
+#ifdef __GNUC__\r
+#pragma GCC pop_options\r
+#else\r
+#pragma optimize ("", on)\r
+#endif\r

diff --git a/Vlv2TbltDevicePkg/PlatformInitPei/PlatformEarlyInit.h b/Vlv2TbltDevicePkg/PlatformInitPei/PlatformEarlyInit.h
new file mode 100644 (file)
index 0000000..c2cdfa3
--- /dev/null
+++ b/Vlv2TbltDevicePkg/PlatformInitPei/PlatformEarlyInit.h
@@ -0,0 +1,1502 @@
+/*++\r
+\r
+  Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+Module Name:\r
+\r
+  PlatformEarlyInit.h\r
+\r
+Abstract:\r
+\r
+  Platform Early Stage header file\r
+\r
+\r
+\r
+--*/\r
+\r
+/*++\r
+ This file contains an 'Intel Peripheral Driver' and is\r
+ licensed for Intel CPUs and chipsets under the terms of your\r
+ license agreement with Intel or your vendor.  This file may\r
+ be modified by the user, subject to additional terms of the\r
+ license agreement\r
+--*/\r
+\r
+#ifndef _EFI_PLATFORM_EARLY_INIT_H_\r
+#define _EFI_PLATFORM_EARLY_INIT_H_\r
+\r
+#define EFI_FORWARD_DECLARATION(x) typedef struct _##x x\r
+#include <FrameworkPei.h>\r
+#include "PlatformBaseAddresses.h"\r
+#include "PchAccess.h"\r
+#include "VlvAccess.h"\r
+#include "SetupMode.h"\r
+#include "PlatformBootMode.h"\r
+#include "Platform.h"\r
+#include "LegacySpeaker.h"\r
+\r
+#include <Ppi/Stall.h>\r
+#include <Guid/PlatformInfo.h>\r
+#include <Guid/SetupVariable.h>\r
+#include <Ppi/AtaController.h>\r
+#include <Ppi/FindFv.h>\r
+#include <Ppi/BootInRecoveryMode.h>\r
+#include <Ppi/ReadOnlyVariable2.h>\r
+#include <Ppi/Capsule.h>\r
+#include <Guid/EfiVpdData.h>\r
+#include <Library/DebugLib.h>\r
+#include <Library/BaseMemoryLib.h>\r
+#include <Library/PcdLib.h>\r
+#include <Library/IoLib.h>\r
+#include <Library/HobLib.h>\r
+#include <Library/BaseLib.h>\r
+#include <Library/PeiServicesLib.h>\r
+#include <Library/MtrrLib.h>\r
+#include <Library/CpuIA32.h>\r
+\r
+#include <IndustryStandard/Pci22.h>\r
+#include <Ppi/Speaker.h>\r
+#include <Guid/FirmwareFileSystem.h>\r
+#include <Guid/MemoryTypeInformation.h>\r
+#include <Ppi/Cache.h>\r
+#include <Ppi/Smbus.h>\r
+#include <Library/PchPlatformLib.h>\r
+#include <Ppi/SmbusPolicy.h>\r
+#include <Ppi/Reset.h>\r
+#include <Ppi/EndOfPeiPhase.h>\r
+#include <Ppi/MemoryDiscovered.h>\r
+#include <Ppi/VlvPolicy.h>\r
+#include <Guid/GlobalVariable.h>\r
+#include <Ppi/RecoveryModule.h>\r
+#include <Ppi/DeviceRecoveryModule.h>\r
+#include <Guid/Capsule.h>\r
+#include <Guid/RecoveryDevice.h>\r
+#include <Ppi/MasterBootMode.h>\r
+#include <Guid/PlatformCpuInfo.h>\r
+#include <Guid/OsSelection.h>\r
+\r
+#define SMC_LAN_ON       0x46\r
+#define SMC_LAN_OFF    0x47\r
+#define SMC_DEEP_S3_STS    0xB2\r
+\r
+\r
+\r
+\r
+//\r
+// Wake Event Types\r
+//\r
+#define SMBIOS_WAKEUP_TYPE_RESERVED           0x00\r
+#define SMBIOS_WAKEUP_TYPE_OTHERS             0x01\r
+#define SMBIOS_WAKEUP_TYPE_UNKNOWN            0x02\r
+#define SMBIOS_WAKEUP_TYPE_APM_TIMER          0x03\r
+#define SMBIOS_WAKEUP_TYPE_MODEM_RING         0x04\r
+#define SMBIOS_WAKEUP_TYPE_LAN_REMOTE         0x05\r
+#define SMBIOS_WAKEUP_TYPE_POWER_SWITCH       0x06\r
+#define SMBIOS_WAKEUP_TYPE_PCI_PME            0x07\r
+#define SMBIOS_WAKEUP_TYPE_AC_POWER_RESTORED  0x08\r
+\r
+#define EFI_CPUID_VIRT_PHYS_ADDRESS_SIZE       0x80000008\r
+\r
+//\r
+// Defines for stall ppi\r
+//\r
+#define PEI_STALL_RESOLUTION  1\r
+\r
+//\r
+// Used in PEI memory test routines\r
+//\r
+#define MEMORY_TEST_COVER_SPAN  0x40000\r
+#define MEMORY_TEST_PATTERN     0x5A5A5A5A\r
+\r
+#define EFI_LOW_BEEP_FREQUENCY            0x31B\r
+#define EFI_HIGH_BEEP_FREQUENCY           0x254\r
+\r
+//\r
+// General Purpose Constants\r
+//\r
+#define ICH_ACPI_TIMER_MAX_VALUE  0x1000000 //The timer is 24 bit overflow\r
+\r
+\r
+\r
+//\r
+//\r
+//              GPIO Register Settings for ValleyFalls (Tablet)\r
+//\r
+//\r
+//                   IO Space configyuration registers\r
+// Field Descriptions:\r
+//    USE: Defines the pin's usage model:  GPIO (G) or Native (N) mode.\r
+//    I/O: Defines whether GPIOs are inputs (I) or outputs (O).\r
+//         (Note:  Only meaningful for pins used as GPIOs.)\r
+//    LVL: This field gives you the initial value for "output" GPIO's.\r
+//         (Note: The output level is dependent upon whether the pin is inverted.)\r
+//    TPE: Defines whether Trigger Positive Edge Enable.\r
+//    TNE: Defines whether Trigger Negative Edge Enable.\r
+//    WAKE_EN: only support in SUS community\r
+//         (Note:  Only affects the level sent to the GPE logic and does not\r
+//         affect the level read through the GPIO registers.)\r
+//\r
+//\r
+//                    Memory spcae configuration registers\r
+//\r
+// Field Descriptions:\r
+//   PAD releated:\r
+//    PAD_CONF0\r
+//      PAD_CONF1\r
+//      PAD_VAL\r
+//      PAD_DFT\r
+//\r
+// Notes:\r
+//    1. N = Native , G = GPIO , I = Input, O = Output, - = BOTH/NOT SURE\r
+//\r
+// Signal          UsedAs                       USE     I/O      LVL     TPE     TNE   PCONF0   PCONF1   PVAL  PDFT\r
+// -------------------------------------------------------------------------------------------------------------------------\r
+// GPIO0           UART1_RXD-L                   N       I        -       -       -     cd29h    -         -     -\r
+// GPIO1           UART1_TXD-0                   N       O        -       -       -     cd29h    -         -     -\r
+// *GPIO2           UART1_RTS_B-1                N       I        -       -       -     cca9h    -         -     -\r
+// *GPIO3           UART1_CTS_B-H                N       O        -       -       -     cca9h    -         -     -\r
+\r
+// GPIO4           I2C1_SDA-OD-O                 N       -        -       -       -     cca9h    -         -     -\r
+// GPIO5           I2C1_SCL-OD-O                 N       -        -       -       -     cca9h    -         -     -\r
+// GPIO6           I2S_SYSCLK-0                  N       O        -       -       -     8d51h    -         -     -\r
+// GPIO7           I2S_L_R-0 (SP)                N       O        -       -       -     8cd1h    -         -     -\r
+// GPIO8           I2S_DATA_OUT-0                N       O        -       -       -     8cd1h    -         -     -\r
+// GPIO9           I2S_SDATA_IN-L                N       I        -       -       -     8cd1h    -         -     -\r
+\r
+// GPIO10          PCM_CLK-0                     N       O        -       -       -     8d51h    -         -     -\r
+// GPIO11          PCM_FSYNC-0 (SP)              N       O        -       -       -     8cd1h    -         -     -\r
+// GPIO12          PCM_DATA_OUT-0 (SP)           N       O        -       -       -     8cd1h    -         -     -\r
+// GPIO13          PCM_DATA_IN-L                 N       I        -       -       -     8d51h    -         -     -\r
+\r
+// GPIO14          SATA_GP0                      N       -        -       -       -      -       -         -     -\r
+// GPIO15          I2C2_SDA-OD-O/I               N       -        -       -       -     ccaah    -         -     -\r
+\r
+// GPIO16          SATA_LEDN                     N       O        -       -       -      -       -         -     -\r
+// GPIO17          UART2_RTS_B-1                 N       I        -       -       -     cd2ah    -         -     -\r
+// GPIO18          UART2_CTS_B-H                 N       O        -       -       -     ccaah    -         -     -\r
+// GPIO19          UART2_RXD-H                   N       I        -       -       -     ccaah    -         -     -\r
+\r
+// GPIO20          I2C2_SCL-OD-O/I               N       -        -       -       -     ccaah    -         -     -\r
+// GPIO21          **PCIE_CLKREQ4B               N       -        -       -       -      -       -         -     -\r
+// GPIO22          UART2_TXD-0                   N       O        -       -       -     ccaah    -         -     -\r
+// GPIO23          FLEX_CLK_SE1                  N       -        -       -       -      -       -         -     -\r
+\r
+// GPIO24          SPI0_SCK-0                    N       O        -       -       -     8d02h    -         -     -\r
+// GPIO25          SPI0_CS-1                     N       O        -       -       -     8d02h    -         -     -\r
+// GPIO26          SPI0_MOSI-0                   N       O        -       -       -     8d02h    -         -     -\r
+// GPIO27          SPI0_MISO-L                   N       I        -       -       -     8d02h    -         -     -\r
+\r
+// GPIO28          UART3_RXD-L                   N       I        -       -       -      -       -         -     -\r
+// GPIO29          UART3_TXD-0                   N       O        -       -       -      -       -         -     -\r
+// GPIO30          UART4_RXD-L                   N       I        -       -       -      -       -         -     -\r
+// GPIO31          UART4_TXD-0                   N       O        -       -       -      -       -         -     -\r
+\r
+// GPIO32          SDMMC1_CLK                    N       -        -       -       -     208d51h   -         -     -\r
+// GPIO33          SDMMC1_D0                     N       -        -       -       -     8cd1h     -         -     -\r
+// GPIO34          SDMMC1_D1                     N       -        -       -       -     8cd1h     -         -     -\r
+// GPIO35          SDMMC1_D2                     N       -        -       -       -     8cd1h     -         -     -\r
+// GPIO36          SDMMC1_D3_CD_B                N       -        -       -       -     8cd1h     -         -     -\r
+// GPIO37          MMC1_D4_SD_WE                 N       -        -       -       -     8cd1h     -         -     -\r
+// GPIO38          MMC1_D5                       N       -        -       -       -     8cd1h     -         -     -\r
+// GPIO39          MMC1_D6                       N       -        -       -       -     8cd1h     -         -     -\r
+// GPIO40          MMC1_D7                       N       -        -       -       -     8cd1h     -         -     -\r
+// GPIO41          SDMMC1_CMD                    N       -        -       -       -     8cd1h     -         -     -\r
+// GPIO42          MMC1_RESET_B                  N       -        -       -       -     208d51h   -         -     -\r
+\r
+// GPIO43          SDMMC2_CLK                    N       -        -       -       -     208d51h   -         -     -\r
+// GPIO44          SDMMC2_D0                     N       -        -       -       -     8cd1h     -         -     -\r
+// GPIO45          SDMMC2_D1                     N       -        -       -       -     8cd1h     -         -     -\r
+// GPIO46          SDMMC2_D2                     N       -        -       -       -     8cd1h     -         -     -\r
+// GPIO47          SDMMC2_D3_CD_B                N       -        -       -       -     8cd1h     -         -     -\r
+// GPIO48          SDMMC2_CMD                    N       -        -       -       -     8cd1h     -         -     -\r
+\r
+// GPIO49          SDMMC3_CLK                    N       -        -       -       -     8d51h      -         -     -\r
+// GPIO50          SDMMC3_D0                     N       -        -       -       -     8cd1h      -         -     -\r
+// GPIO51          SDMMC3_D1                     N       -        -       -       -      8cd1h      -         -     -\r
+// GPIO52          SDMMC3_D2                     N       -        -       -       -      8cd1h      -         -     -\r
+// GPIO53          SDMMC3_D3                     N       -        -       -       -      8cd1h      -         -     -\r
+// GPIO54          SDMMC3_CD_B                   N       -        -       -       -      cca9h      -         -     -\r
+// GPIO55          SDMMC3_CMD                    N       -        -       -       -      8cd1h      -         -     -\r
+// GPIO56          SDMMC3_1P8_EN                 N       -        -       -       -      cd29h   -         -     -\r
+\r
+// GPIO57            LPC_AD0                     N       -        -       -       -      -       -         -     -\r
+// GPIO58            LPC_AD1                     N       -        -       -       -      -       -         -     -\r
+// GPIO59            LPC_AD2                     N       -        -       -       -      -       -         -     -\r
+// GPIO60            LPC_AD3                     N       -        -       -       -      -       -         -     -\r
+// GPIO61            LPC_FRAMEB                  N       O        -       -       -      -       -         -     -\r
+// GPIO62            LPC_CLKOUT0                 N       O        -       -       -      -       -         -     -\r
+// GPIO63            LPC_CLKOUT1                 N       O        -       -       -      -       -         -     -\r
+// GPIO64            LPC_CLKRUNB                 N       -        -       -       -      -       -         -     -\r
+\r
+// GPIO65            SMB_DATA                    N       -        -       -       -      -       -         -     -\r
+// GPIO66            SMB_CLK                     N       -        -       -       -      -       -         -     -\r
+// GPIO67            SMB_ALERTB                  N       -        -       -       -      -       -         -     -\r
+\r
+// GPIO68            ILB_SEIRQ                   N       -       -        -       -      -       -         -     -\r
+// GPIO69            SPKR                        N       O       -        -       -      -       -         -     -\r
+\r
+//SUS WELL\r
+\r
+//GPIO_SUS0             BT_WAKEUP_VLV               N       O       -        -       -    CCA8h       -         -     -\r
+//GPIO_SUS1             BT_CLOCK_REQ                N       O       -        -       -    CCA8h       -         -     -\r
+//GPIO_SUS2             WIFI_PWR_EN                 N       O       -        -       -    CCA8h       -         -     -\r
+//GPIO_SUS3             SD_CARD_PWR_EN              N       O       -        -       -    CD28h       -         -     -\r
+//GPIO_SUS4             GPIO_SUS4                   N       O       -        -       -    CD28h       -         -     -\r
+//GPIO_SUS5             GPIO_SUS5                   N       O       -        -       -    CD28h       -         -     -\r
+//GPIO_SUS6             SUSPWRDNACK                 N       O       -        -       -    8850h       -         -     -\r
+//GPIO_SUS7             PMU_SLP_DDRVTT_B            N       O       -        -       -    8850h       -         -     -\r
+//GPIO_SUS8             PMU_WAKE_B                  N       O       -        -       -    CCA8h       -         -     -\r
+//GPIO_SUS9             PMU_PWRBTN_B                N       O       -        -       -    CCA8h       -         -     -\r
+//GPIO_SUS10            PMU_WAKE_LAN_B              N       O       -        -       -    CCA8h       -         -     -\r
+//GPIO_SUS11            SUS_STAT_B                  N       O       -        -       -    C828h       -         -     -\r
+//GPIO_SUS12            GPIO_SUS12                  N       O       -        -       -    C828h      -         -     -\r
+//GPIO_SUS13            USB_OC0_B-20K,H             N       O       -        -       -    CCA8h       -         -     -\r
+//GPIO_SUS14            GPIO_SUS14                  N       O       -        -       -    CCA8h       -         -     -\r
+//GPIO_SUS15            SPI_CS1_B-20K,H             N       O       -        -       -    8C80h       -         -     -\r
+//GPIO_SUS16            PMU_SUSCLK                  N       O       -        -       -    C828h       -         -     -\r
+//\r
+\r
+\r
+#define VF_TAB_GPIO_USE_SEL_VAL_0_31        0x00000000\r
+#define VF_TAB_GPIO_USE_SEL_VAL_32_63       0x00000000\r
+#define VF_TAB_GPIO_USE_SEL_VAL_64_70       0x00000000\r
+#define VF_TAB_GPIO_USE_SEL_VAL_SUS         0x00000000\r
+\r
+//\r
+//1010 --00 0100 01-- 0101 --0- 0001 1010\r
+//\r
+#define VF_TAB_GPIO_IO_SEL_VAL_0_31         0x00000000 // BIT30 | BIT28 | BIT27 | BIT19 | BIT17 | BIT13 | BIT9 | BIT2 | BIT0\r
+#define VF_TAB_GPIO_IO_SEL_VAL_32_63        0x00000000\r
+#define VF_TAB_GPIO_IO_SEL_VAL_64_70        0x00000000\r
+#define VF_TAB_GPIO_IO_SEL_VAL_SUS          0x00000000\r
+\r
+\r
+#define VF_TAB_GPIO_LVL_VAL_0_31            0x00000000\r
+#define VF_TAB_GPIO_LVL_VAL_32_63           0x00000000\r
+#define VF_TAB_GPIO_LVL_VAL_64_70           0x00000000\r
+#define VF_TAB_GPIO_LVL_VAL_SUS             0x00000000\r
+\r
+#define VF_TAB_GPIO_TPE_VAL_0_31            0x00000000\r
+#define VF_TAB_GPIO_TPE_VAL_SUS             0x00000000\r
+\r
+#define VF_TAB_GPIO_TNE_VAL_0_31            0x00000000\r
+#define VF_TAB_GPIO_TNE_VAL_SUS             0x00000000\r
+\r
+#define VF_TAB_GPIO_TS_VAL_0_31             0x00000000\r
+#define VF_TAB_GPIO_TS_VAL_SUS              0x00000000\r
+\r
+\r
+//\r
+// Memory space registers\r
+//\r
+\r
+//\r
+// CONF0\r
+//\r
+#define  VF_TAB_PAD_CONF0_GPIO0  0xcd29\r
+#define  VF_TAB_PAD_CONF0_GPIO1  0xcd29\r
+#define  VF_TAB_PAD_CONF0_GPIO2  0xcca9\r
+#define  VF_TAB_PAD_CONF0_GPIO3  0xcca9\r
+#define  VF_TAB_PAD_CONF0_GPIO4  0xcca9\r
+#define  VF_TAB_PAD_CONF0_GPIO5  0xcca9\r
+#define  VF_TAB_PAD_CONF0_GPIO6  0x8d51\r
+#define  VF_TAB_PAD_CONF0_GPIO7  0x8cd1\r
+#define  VF_TAB_PAD_CONF0_GPIO8  0x8cd1\r
+#define  VF_TAB_PAD_CONF0_GPIO9  0x8cd1\r
+#define  VF_TAB_PAD_CONF0_GPIO10  0x8d51\r
+#define  VF_TAB_PAD_CONF0_GPIO11  0x8cd1\r
+#define  VF_TAB_PAD_CONF0_GPIO12  0x8cd1\r
+#define  VF_TAB_PAD_CONF0_GPIO13  0x8d51\r
+#define  VF_TAB_PAD_CONF0_GPIO14  0xCCA8\r
+#define  VF_TAB_PAD_CONF0_GPIO15  0xccaa\r
+#define  VF_TAB_PAD_CONF0_GPIO16  0xC828\r
+#define  VF_TAB_PAD_CONF0_GPIO17  0xcd2a\r
+#define  VF_TAB_PAD_CONF0_GPIO18  0xccaa\r
+#define  VF_TAB_PAD_CONF0_GPIO19  0xccaa\r
+#define  VF_TAB_PAD_CONF0_GPIO20  0xccaa\r
+#define  VF_TAB_PAD_CONF0_GPIO21  0xCCA9\r
+#define  VF_TAB_PAD_CONF0_GPIO22  0xccaa\r
+#define  VF_TAB_PAD_CONF0_GPIO23  0xCD2A\r
+#define  VF_TAB_PAD_CONF0_GPIO24  0x8d02\r
+#define  VF_TAB_PAD_CONF0_GPIO25  0x8d02\r
+#define  VF_TAB_PAD_CONF0_GPIO26  0x8d02\r
+#define  VF_TAB_PAD_CONF0_GPIO27  0x8d02\r
+#define  VF_TAB_PAD_CONF0_GPIO28  0x8D02\r
+#define  VF_TAB_PAD_CONF0_GPIO29  0x8D02\r
+#define  VF_TAB_PAD_CONF0_GPIO30  0x8D00\r
+#define  VF_TAB_PAD_CONF0_GPIO31  0xCD2A\r
+#define  VF_TAB_PAD_CONF0_GPIO32  0x208d51\r
+#define  VF_TAB_PAD_CONF0_GPIO33  0x8cd1\r
+#define  VF_TAB_PAD_CONF0_GPIO34  0x8cd1\r
+#define  VF_TAB_PAD_CONF0_GPIO35  0x8cd1\r
+#define  VF_TAB_PAD_CONF0_GPIO36  0x8cd1\r
+#define  VF_TAB_PAD_CONF0_GPIO37  0x8cd1\r
+#define  VF_TAB_PAD_CONF0_GPIO38  0x8cd1\r
+#define  VF_TAB_PAD_CONF0_GPIO39  0x8cd1\r
+#define  VF_TAB_PAD_CONF0_GPIO40  0x8cd1\r
+#define  VF_TAB_PAD_CONF0_GPIO41  0x8cd1\r
+#define  VF_TAB_PAD_CONF0_GPIO42  0x208d51\r
+#define  VF_TAB_PAD_CONF0_GPIO43  0x208d51\r
+#define  VF_TAB_PAD_CONF0_GPIO44  0x8cd1\r
+#define  VF_TAB_PAD_CONF0_GPIO45  0x8cd1\r
+#define  VF_TAB_PAD_CONF0_GPIO46  0x8cd1\r
+#define  VF_TAB_PAD_CONF0_GPIO47  0x8cd1\r
+#define  VF_TAB_PAD_CONF0_GPIO48  0x8cd1\r
+#define  VF_TAB_PAD_CONF0_GPIO49  0x8d51\r
+#define  VF_TAB_PAD_CONF0_GPIO50  0x8cd1\r
+#define  VF_TAB_PAD_CONF0_GPIO51  0x8cd1\r
+#define  VF_TAB_PAD_CONF0_GPIO52  0x8cd1\r
+#define  VF_TAB_PAD_CONF0_GPIO53  0x8cd1\r
+#define  VF_TAB_PAD_CONF0_GPIO54  0xcca9\r
+#define  VF_TAB_PAD_CONF0_GPIO55  0x8cd1\r
+#define  VF_TAB_PAD_CONF0_GPIO56  0xcd29\r
+#define  VF_TAB_PAD_CONF0_GPIO57  0x8C80\r
+#define  VF_TAB_PAD_CONF0_GPIO58  0x8C80\r
+#define  VF_TAB_PAD_CONF0_GPIO59  0x8C80\r
+#define  VF_TAB_PAD_CONF0_GPIO60  0x8C80\r
+#define  VF_TAB_PAD_CONF0_GPIO61  0x8800\r
+#define  VF_TAB_PAD_CONF0_GPIO62  0x8D00\r
+#define  VF_TAB_PAD_CONF0_GPIO63  0x8800\r
+#define  VF_TAB_PAD_CONF0_GPIO64  0x8800\r
+#define  VF_TAB_PAD_CONF0_GPIO65  0xC828\r
+#define  VF_TAB_PAD_CONF0_GPIO66  0xC828\r
+#define  VF_TAB_PAD_CONF0_GPIO67  0xC828\r
+#define  VF_TAB_PAD_CONF0_GPIO68  0xCCA8\r
+#define  VF_TAB_PAD_CONF0_GPIO69  0xC828\r
+#define  VF_TAB_PAD_CONF0_GPIO70  0xCCA8\r
+\r
+\r
+\r
+//\r
+// PAD_CONF1\r
+//\r
+#define  VF_TAB_PAD_CONF1_GPIO0  0x20002\r
+#define  VF_TAB_PAD_CONF1_GPIO1  0x20002\r
+#define  VF_TAB_PAD_CONF1_GPIO2  0x20002\r
+#define  VF_TAB_PAD_CONF1_GPIO3  0x20002\r
+#define  VF_TAB_PAD_CONF1_GPIO4  0x20002\r
+#define  VF_TAB_PAD_CONF1_GPIO5  0x20002\r
+#define  VF_TAB_PAD_CONF1_GPIO6  0x1F000F\r
+#define  VF_TAB_PAD_CONF1_GPIO7  0x1F000F\r
+#define  VF_TAB_PAD_CONF1_GPIO8  0x1F000F\r
+#define  VF_TAB_PAD_CONF1_GPIO9  0x1F000F\r
+#define  VF_TAB_PAD_CONF1_GPIO10  0x1F000F\r
+#define  VF_TAB_PAD_CONF1_GPIO11  0x1F000F\r
+#define  VF_TAB_PAD_CONF1_GPIO12  0x1F000F\r
+#define  VF_TAB_PAD_CONF1_GPIO13  0x1F000F\r
+#define  VF_TAB_PAD_CONF1_GPIO14  0x20002\r
+#define  VF_TAB_PAD_CONF1_GPIO15  0x20002\r
+#define  VF_TAB_PAD_CONF1_GPIO16  0x20002\r
+#define  VF_TAB_PAD_CONF1_GPIO17  0x20002\r
+#define  VF_TAB_PAD_CONF1_GPIO18  0x20002\r
+#define  VF_TAB_PAD_CONF1_GPIO19  0x20002\r
+#define  VF_TAB_PAD_CONF1_GPIO20  0x20002\r
+#define  VF_TAB_PAD_CONF1_GPIO21  0x20002\r
+#define  VF_TAB_PAD_CONF1_GPIO22  0x20002\r
+#define  VF_TAB_PAD_CONF1_GPIO23  0x20002\r
+#define  VF_TAB_PAD_CONF1_GPIO24  0x00000\r
+#define  VF_TAB_PAD_CONF1_GPIO25  0x00000\r
+#define  VF_TAB_PAD_CONF1_GPIO26  0x00000\r
+#define  VF_TAB_PAD_CONF1_GPIO27  0x00000\r
+#define  VF_TAB_PAD_CONF1_GPIO28  0x00000\r
+#define  VF_TAB_PAD_CONF1_GPIO29  0x00000\r
+#define  VF_TAB_PAD_CONF1_GPIO30  0x00000\r
+#define  VF_TAB_PAD_CONF1_GPIO31  0x20002\r
+#define  VF_TAB_PAD_CONF1_GPIO32  0x00000\r
+#define  VF_TAB_PAD_CONF1_GPIO33  0x00000\r
+#define  VF_TAB_PAD_CONF1_GPIO34  0x00000\r
+#define  VF_TAB_PAD_CONF1_GPIO35  0x00000\r
+#define  VF_TAB_PAD_CONF1_GPIO36  0x00000\r
+#define  VF_TAB_PAD_CONF1_GPIO37  0x00000\r
+#define  VF_TAB_PAD_CONF1_GPIO38  0x00000\r
+#define  VF_TAB_PAD_CONF1_GPIO39  0x00000\r
+#define  VF_TAB_PAD_CONF1_GPIO40  0x00000\r
+#define  VF_TAB_PAD_CONF1_GPIO41  0x00000\r
+#define  VF_TAB_PAD_CONF1_GPIO42  0x00000\r
+#define  VF_TAB_PAD_CONF1_GPIO43  0x00000\r
+#define  VF_TAB_PAD_CONF1_GPIO44  0x00000\r
+#define  VF_TAB_PAD_CONF1_GPIO45  0x00000\r
+#define  VF_TAB_PAD_CONF1_GPIO46  0x00000\r
+#define  VF_TAB_PAD_CONF1_GPIO47  0x00000\r
+#define  VF_TAB_PAD_CONF1_GPIO48  0x00000\r
+#define  VF_TAB_PAD_CONF1_GPIO49  0x00000\r
+#define  VF_TAB_PAD_CONF1_GPIO50  0x00000\r
+#define  VF_TAB_PAD_CONF1_GPIO51  0x00000\r
+#define  VF_TAB_PAD_CONF1_GPIO52  0x00000\r
+#define  VF_TAB_PAD_CONF1_GPIO53  0x00000\r
+#define  VF_TAB_PAD_CONF1_GPIO54  0x20002\r
+#define  VF_TAB_PAD_CONF1_GPIO55  0x00000\r
+#define  VF_TAB_PAD_CONF1_GPIO56  0x20002\r
+#define  VF_TAB_PAD_CONF1_GPIO57  0x00000\r
+#define  VF_TAB_PAD_CONF1_GPIO58  0x00000\r
+#define  VF_TAB_PAD_CONF1_GPIO59  0x00000\r
+#define  VF_TAB_PAD_CONF1_GPIO60  0x00000\r
+#define  VF_TAB_PAD_CONF1_GPIO61  0x00000\r
+#define  VF_TAB_PAD_CONF1_GPIO62  0x00000\r
+#define  VF_TAB_PAD_CONF1_GPIO63  0x00000\r
+#define  VF_TAB_PAD_CONF1_GPIO64  0x00000\r
+#define  VF_TAB_PAD_CONF1_GPIO65  0x20002\r
+#define  VF_TAB_PAD_CONF1_GPIO66  0x20002\r
+#define  VF_TAB_PAD_CONF1_GPIO67  0x20002\r
+#define  VF_TAB_PAD_CONF1_GPIO68  0x20002\r
+#define  VF_TAB_PAD_CONF1_GPIO69  0x20002\r
+#define  VF_TAB_PAD_CONF1_GPIO70  0x20002\r
+\r
+\r
+//\r
+// PAD_VAL\r
+//\r
+#define  VF_TAB_PAD_VAL_GPIO0  0x2\r
+#define  VF_TAB_PAD_VAL_GPIO1  0x2\r
+#define  VF_TAB_PAD_VAL_GPIO2  0x2\r
+#define  VF_TAB_PAD_VAL_GPIO3  0x2\r
+#define  VF_TAB_PAD_VAL_GPIO4  0x2\r
+#define  VF_TAB_PAD_VAL_GPIO5  0x2\r
+#define  VF_TAB_PAD_VAL_GPIO6  0x2\r
+#define  VF_TAB_PAD_VAL_GPIO7  0x2\r
+#define  VF_TAB_PAD_VAL_GPIO8  0x2\r
+#define  VF_TAB_PAD_VAL_GPIO9  0x2\r
+#define  VF_TAB_PAD_VAL_GPIO10  0x2\r
+#define  VF_TAB_PAD_VAL_GPIO11  0x2\r
+#define  VF_TAB_PAD_VAL_GPIO12  0x2\r
+#define  VF_TAB_PAD_VAL_GPIO13  0x2\r
+#define  VF_TAB_PAD_VAL_GPIO14  0x2\r
+#define  VF_TAB_PAD_VAL_GPIO15  0x2\r
+#define  VF_TAB_PAD_VAL_GPIO16  0x4\r
+#define  VF_TAB_PAD_VAL_GPIO17  0x2\r
+#define  VF_TAB_PAD_VAL_GPIO18  0x2\r
+#define  VF_TAB_PAD_VAL_GPIO19  0x2\r
+#define  VF_TAB_PAD_VAL_GPIO20  0x2\r
+#define  VF_TAB_PAD_VAL_GPIO21  0x2\r
+#define  VF_TAB_PAD_VAL_GPIO22  0x2\r
+#define  VF_TAB_PAD_VAL_GPIO23  0x2\r
+#define  VF_TAB_PAD_VAL_GPIO24  0x2\r
+#define  VF_TAB_PAD_VAL_GPIO25  0x2\r
+#define  VF_TAB_PAD_VAL_GPIO26  0x2\r
+#define  VF_TAB_PAD_VAL_GPIO27  0x2\r
+#define  VF_TAB_PAD_VAL_GPIO28  0x2\r
+#define  VF_TAB_PAD_VAL_GPIO29  0x2\r
+#define  VF_TAB_PAD_VAL_GPIO30  0x2\r
+#define  VF_TAB_PAD_VAL_GPIO31  0x2\r
+#define  VF_TAB_PAD_VAL_GPIO32  0x2\r
+#define  VF_TAB_PAD_VAL_GPIO33  0x2\r
+#define  VF_TAB_PAD_VAL_GPIO34  0x2\r
+#define  VF_TAB_PAD_VAL_GPIO35  0x2\r
+#define  VF_TAB_PAD_VAL_GPIO36  0x2\r
+#define  VF_TAB_PAD_VAL_GPIO37  0x2\r
+#define  VF_TAB_PAD_VAL_GPIO38  0x2\r
+#define  VF_TAB_PAD_VAL_GPIO39  0x2\r
+#define  VF_TAB_PAD_VAL_GPIO40  0x2\r
+#define  VF_TAB_PAD_VAL_GPIO41  0x2\r
+#define  VF_TAB_PAD_VAL_GPIO42  0x2\r
+#define  VF_TAB_PAD_VAL_GPIO43  0x2\r
+#define  VF_TAB_PAD_VAL_GPIO44  0x2\r
+#define  VF_TAB_PAD_VAL_GPIO45  0x2\r
+#define  VF_TAB_PAD_VAL_GPIO46  0x2\r
+#define  VF_TAB_PAD_VAL_GPIO47  0x2\r
+#define  VF_TAB_PAD_VAL_GPIO48  0x2\r
+#define  VF_TAB_PAD_VAL_GPIO49  0x2\r
+#define  VF_TAB_PAD_VAL_GPIO50  0x2\r
+#define  VF_TAB_PAD_VAL_GPIO51  0x2\r
+#define  VF_TAB_PAD_VAL_GPIO52  0x2\r
+#define  VF_TAB_PAD_VAL_GPIO53  0x2\r
+#define  VF_TAB_PAD_VAL_GPIO54  0x2\r
+#define  VF_TAB_PAD_VAL_GPIO55  0x2\r
+#define  VF_TAB_PAD_VAL_GPIO56  0x2\r
+#define  VF_TAB_PAD_VAL_GPIO57  0x2\r
+#define  VF_TAB_PAD_VAL_GPIO58  0x2\r
+#define  VF_TAB_PAD_VAL_GPIO59  0x2\r
+#define  VF_TAB_PAD_VAL_GPIO60  0x2\r
+#define  VF_TAB_PAD_VAL_GPIO61  0x4\r
+#define  VF_TAB_PAD_VAL_GPIO62  0x2\r
+#define  VF_TAB_PAD_VAL_GPIO63  0x2\r
+#define  VF_TAB_PAD_VAL_GPIO64  0x2\r
+#define  VF_TAB_PAD_VAL_GPIO65  0x2\r
+#define  VF_TAB_PAD_VAL_GPIO66  0x2\r
+#define  VF_TAB_PAD_VAL_GPIO67  0x0\r
+#define  VF_TAB_PAD_VAL_GPIO68  0x2\r
+#define  VF_TAB_PAD_VAL_GPIO69  0x4\r
+#define  VF_TAB_PAD_VAL_GPIO70  0x2\r
+\r
+\r
+//\r
+// PAD_DFT\r
+//\r
+#define  VF_TAB_PAD_DFT_GPIO0  0xC\r
+#define  VF_TAB_PAD_DFT_GPIO1  0xC\r
+#define  VF_TAB_PAD_DFT_GPIO2  0xC\r
+#define  VF_TAB_PAD_DFT_GPIO3  0xC\r
+#define  VF_TAB_PAD_DFT_GPIO4  0xC\r
+#define  VF_TAB_PAD_DFT_GPIO5  0xC\r
+#define  VF_TAB_PAD_DFT_GPIO6  0xC\r
+#define  VF_TAB_PAD_DFT_GPIO7  0xC\r
+#define  VF_TAB_PAD_DFT_GPIO8  0xC\r
+#define  VF_TAB_PAD_DFT_GPIO9  0xC\r
+#define  VF_TAB_PAD_DFT_GPIO10  0xC\r
+#define  VF_TAB_PAD_DFT_GPIO11  0xC\r
+#define  VF_TAB_PAD_DFT_GPIO12  0xC\r
+#define  VF_TAB_PAD_DFT_GPIO13  0xC\r
+#define  VF_TAB_PAD_DFT_GPIO14  0xC\r
+#define  VF_TAB_PAD_DFT_GPIO15  0xC\r
+#define  VF_TAB_PAD_DFT_GPIO16  0xC\r
+#define  VF_TAB_PAD_DFT_GPIO17  0xC\r
+#define  VF_TAB_PAD_DFT_GPIO18  0xC\r
+#define  VF_TAB_PAD_DFT_GPIO19  0xC\r
+#define  VF_TAB_PAD_DFT_GPIO20  0xC\r
+#define  VF_TAB_PAD_DFT_GPIO21  0xC\r
+#define  VF_TAB_PAD_DFT_GPIO22  0xC\r
+#define  VF_TAB_PAD_DFT_GPIO23  0xC\r
+#define  VF_TAB_PAD_DFT_GPIO24  0xC\r
+#define  VF_TAB_PAD_DFT_GPIO25  0xC\r
+#define  VF_TAB_PAD_DFT_GPIO26  0xC\r
+#define  VF_TAB_PAD_DFT_GPIO27  0xC\r
+#define  VF_TAB_PAD_DFT_GPIO28  0xC\r
+#define  VF_TAB_PAD_DFT_GPIO29  0xC\r
+#define  VF_TAB_PAD_DFT_GPIO30  0xC\r
+#define  VF_TAB_PAD_DFT_GPIO31  0xC\r
+#define  VF_TAB_PAD_DFT_GPIO32  0xC\r
+#define  VF_TAB_PAD_DFT_GPIO33  0xC\r
+#define  VF_TAB_PAD_DFT_GPIO34  0xC\r
+#define  VF_TAB_PAD_DFT_GPIO35  0xC\r
+#define  VF_TAB_PAD_DFT_GPIO36  0xC\r
+#define  VF_TAB_PAD_DFT_GPIO37  0xC\r
+#define  VF_TAB_PAD_DFT_GPIO38  0xC\r
+#define  VF_TAB_PAD_DFT_GPIO39  0xC\r
+#define  VF_TAB_PAD_DFT_GPIO40  0xC\r
+#define  VF_TAB_PAD_DFT_GPIO41  0xC\r
+#define  VF_TAB_PAD_DFT_GPIO42  0xC\r
+#define  VF_TAB_PAD_DFT_GPIO43  0xC\r
+#define  VF_TAB_PAD_DFT_GPIO44  0xC\r
+#define  VF_TAB_PAD_DFT_GPIO45  0xC\r
+#define  VF_TAB_PAD_DFT_GPIO46  0xC\r
+#define  VF_TAB_PAD_DFT_GPIO47  0xC\r
+#define  VF_TAB_PAD_DFT_GPIO48  0xC\r
+#define  VF_TAB_PAD_DFT_GPIO49  0xC\r
+#define  VF_TAB_PAD_DFT_GPIO50  0xC\r
+#define  VF_TAB_PAD_DFT_GPIO51  0xC\r
+#define  VF_TAB_PAD_DFT_GPIO52  0xC\r
+#define  VF_TAB_PAD_DFT_GPIO53  0xC\r
+#define  VF_TAB_PAD_DFT_GPIO54  0xC\r
+#define  VF_TAB_PAD_DFT_GPIO55  0xC\r
+#define  VF_TAB_PAD_DFT_GPIO56  0xC\r
+#define  VF_TAB_PAD_DFT_GPIO57  0xC\r
+#define  VF_TAB_PAD_DFT_GPIO58  0xC\r
+#define  VF_TAB_PAD_DFT_GPIO59  0xC\r
+#define  VF_TAB_PAD_DFT_GPIO60  0xC\r
+#define  VF_TAB_PAD_DFT_GPIO61  0xC\r
+#define  VF_TAB_PAD_DFT_GPIO62  0xC\r
+#define  VF_TAB_PAD_DFT_GPIO63  0xC\r
+#define  VF_TAB_PAD_DFT_GPIO64  0xC\r
+#define  VF_TAB_PAD_DFT_GPIO65  0xC\r
+#define  VF_TAB_PAD_DFT_GPIO66  0xC\r
+#define  VF_TAB_PAD_DFT_GPIO67  0xC\r
+#define  VF_TAB_PAD_DFT_GPIO68  0xC\r
+#define  VF_TAB_PAD_DFT_GPIO69  0xC\r
+#define  VF_TAB_PAD_DFT_GPIO70  0xC\r
+\r
+\r
+//\r
+//SUS WELL\r
+//\r
+\r
+//\r
+// CONF0\r
+//\r
+#define  VF_TAB_PAD_CONF0_GPIO_SUS0  0xCCA8\r
+#define  VF_TAB_PAD_CONF0_GPIO_SUS1  0xCCA8\r
+#define  VF_TAB_PAD_CONF0_GPIO_SUS2  0xCCA8\r
+#define  VF_TAB_PAD_CONF0_GPIO_SUS3  0xCD28\r
+#define  VF_TAB_PAD_CONF0_GPIO_SUS4  0xCD28\r
+#define  VF_TAB_PAD_CONF0_GPIO_SUS5  0xCD28\r
+#define  VF_TAB_PAD_CONF0_GPIO_SUS6  0x8850\r
+#define  VF_TAB_PAD_CONF0_GPIO_SUS7  0x8850\r
+#define  VF_TAB_PAD_CONF0_GPIO_SUS8  0xCCA8\r
+#define  VF_TAB_PAD_CONF0_GPIO_SUS9  0xCCA8\r
+#define  VF_TAB_PAD_CONF0_GPIO_SUS10  0xCCA8\r
+#define  VF_TAB_PAD_CONF0_GPIO_SUS11  0xC828\r
+#define  VF_TAB_PAD_CONF0_GPIO_SUS12  0xC828\r
+#define  VF_TAB_PAD_CONF0_GPIO_SUS13  0xCCA8\r
+#define  VF_TAB_PAD_CONF0_GPIO_SUS14  0xCCA8\r
+#define  VF_TAB_PAD_CONF0_GPIO_SUS15  0x8C80\r
+#define  VF_TAB_PAD_CONF0_GPIO_SUS16  0xC828\r
+\r
+//\r
+// CONF1\r
+//\r
+#define  VF_TAB_PAD_CONF1_GPIO_SUS0  0\r
+#define  VF_TAB_PAD_CONF1_GPIO_SUS1  0\r
+#define  VF_TAB_PAD_CONF1_GPIO_SUS2  0\r
+#define  VF_TAB_PAD_CONF1_GPIO_SUS3  0\r
+#define  VF_TAB_PAD_CONF1_GPIO_SUS4  0\r
+#define  VF_TAB_PAD_CONF1_GPIO_SUS5  0\r
+#define  VF_TAB_PAD_CONF1_GPIO_SUS6  0\r
+#define  VF_TAB_PAD_CONF1_GPIO_SUS7  0\r
+#define  VF_TAB_PAD_CONF1_GPIO_SUS8  0\r
+#define  VF_TAB_PAD_CONF1_GPIO_SUS9  0\r
+#define  VF_TAB_PAD_CONF1_GPIO_SUS10  0\r
+#define  VF_TAB_PAD_CONF1_GPIO_SUS11  0\r
+#define  VF_TAB_PAD_CONF1_GPIO_SUS12  0\r
+#define  VF_TAB_PAD_CONF1_GPIO_SUS13  0\r
+#define  VF_TAB_PAD_CONF1_GPIO_SUS14  0\r
+#define  VF_TAB_PAD_CONF1_GPIO_SUS15  0\r
+#define  VF_TAB_PAD_CONF1_GPIO_SUS16  0\r
+\r
+//\r
+// PAD_VAL\r
+//\r
+#define  VF_TAB_PAD_VAL_GPIO_SUS0  0\r
+#define  VF_TAB_PAD_VAL_GPIO_SUS1  0\r
+#define  VF_TAB_PAD_VAL_GPIO_SUS2  0\r
+#define  VF_TAB_PAD_VAL_GPIO_SUS3  0\r
+#define  VF_TAB_PAD_VAL_GPIO_SUS4  0\r
+#define  VF_TAB_PAD_VAL_GPIO_SUS5  0\r
+#define  VF_TAB_PAD_VAL_GPIO_SUS6  0\r
+#define  VF_TAB_PAD_VAL_GPIO_SUS7  0\r
+#define  VF_TAB_PAD_VAL_GPIO_SUS8  0\r
+#define  VF_TAB_PAD_VAL_GPIO_SUS9  0\r
+#define  VF_TAB_PAD_VAL_GPIO_SUS10  0\r
+#define  VF_TAB_PAD_VAL_GPIO_SUS11  0\r
+#define  VF_TAB_PAD_VAL_GPIO_SUS12  0\r
+#define  VF_TAB_PAD_VAL_GPIO_SUS13  0\r
+#define  VF_TAB_PAD_VAL_GPIO_SUS14  0\r
+#define  VF_TAB_PAD_VAL_GPIO_SUS15  0\r
+#define  VF_TAB_PAD_VAL_GPIO_SUS16  0\r
+\r
+//\r
+// PAD_DFT\r
+//\r
+#define  VF_TAB_PAD_DFT_GPIO_SUS0  0\r
+#define  VF_TAB_PAD_DFT_GPIO_SUS1  0\r
+#define  VF_TAB_PAD_DFT_GPIO_SUS2  0\r
+#define  VF_TAB_PAD_DFT_GPIO_SUS3  0\r
+#define  VF_TAB_PAD_DFT_GPIO_SUS4  0\r
+#define  VF_TAB_PAD_DFT_GPIO_SUS5  0\r
+#define  VF_TAB_PAD_DFT_GPIO_SUS6  0\r
+#define  VF_TAB_PAD_DFT_GPIO_SUS7  0\r
+#define  VF_TAB_PAD_DFT_GPIO_SUS8  0\r
+#define  VF_TAB_PAD_DFT_GPIO_SUS9  0\r
+#define  VF_TAB_PAD_DFT_GPIO_SUS10  0\r
+#define  VF_TAB_PAD_DFT_GPIO_SUS11  0\r
+#define  VF_TAB_PAD_DFT_GPIO_SUS12  0\r
+#define  VF_TAB_PAD_DFT_GPIO_SUS13  0\r
+#define  VF_TAB_PAD_DFT_GPIO_SUS14  0\r
+#define  VF_TAB_PAD_DFT_GPIO_SUS15  0\r
+#define  VF_TAB_PAD_DFT_GPIO_SUS16  0\r
+\r
+\r
+//\r
+//\r
+//              GPIO Register Settings for ValleyFalls (Netbook)\r
+//\r
+//\r
+//                   IO Space configyuration registers\r
+// Field Descriptions:\r
+//    USE: Defines the pin's usage model:  GPIO (G) or Native (N) mode.\r
+//    I/O: Defines whether GPIOs are inputs (I) or outputs (O).\r
+//         (Note:  Only meaningful for pins used as GPIOs.)\r
+//    LVL: This field gives you the initial value for "output" GPIO's.\r
+//         (Note: The output level is dependent upon whether the pin is inverted.)\r
+//    TPE: Defines whether Trigger Positive Edge Enable.\r
+//    TNE: Defines whether Trigger Negative Edge Enable.\r
+//    WAKE_EN: only support in SUS community\r
+//         (Note:  Only affects the level sent to the GPE logic and does not\r
+//         affect the level read through the GPIO registers.)\r
+//\r
+//\r
+//                    Memory spcae configuration registers\r
+//\r
+// Field Descriptions:\r
+//   PAD releated:\r
+//    PAD_CONF0\r
+//      PAD_CONF1\r
+//      PAD_VAL\r
+//      PAD_DFT\r
+//\r
+// Notes:\r
+//    1. N = Native , G = GPIO , I = Input, O = Output, - = BOTH/NOT SURE\r
+//\r
+// Signal          UsedAs                       USE     I/O      LVL     TPE     TNE   PCONF0   PCONF1   PVAL  PDFT\r
+// -------------------------------------------------------------------------------------------------------------------------\r
+// GPIO0           UART1_RXD-L                   N       I        -       -       -     cd29h    -         -     -\r
+// GPIO1           UART1_TXD-0                   N       O        -       -       -     cd29h    -         -     -\r
+// *GPIO2           UART1_RTS_B-1                N       I        -       -       -     cca9h    -         -     -\r
+// *GPIO3           UART1_CTS_B-H                N       O        -       -       -     cca9h    -         -     -\r
+\r
+// GPIO4           NMI_B-H                       G       -        -       -       -     cca9h    -         -     -\r
+// GPIO5           GPIO_D5                       G       -        -       -       -     cca9h    -         -     -\r
+// GPIO6           GPIO_D6                       G       O        -       -       -     8d51h    -         -     -\r
+// GPIO7           GPIO_D7                       G       O        -       -       -     8cd1h    -         -     -\r
+// GPIO8           GPIO_D8                       G       O        -       -       -     8cd1h    -         -     -\r
+// GPIO9           GPIO_D9                       G       I        -       -       -     8cd1h    -         -     -\r
+\r
+// GPIO10          GPIO_D10                      G       O        -       -       -     8d51h    -         -     -\r
+// GPIO11          GPIO_D11                      G       O        -       -       -     8cd1h    -         -     -\r
+// GPIO12          GPIO_D12                      G       O        -       -       -     8cd1h    -         -     -\r
+// GPIO13          GPIO_D13                      G       I        -       -       -     8d51h    -         -     -\r
+\r
+// GPIO14          SATA_GP0                      N       -        -       -       -      -       -         -     -\r
+// GPIO15          SATA_GP1-L                    N       -        -       -       -     ccaah    -         -     -\r
+\r
+// GPIO16          SATA_LEDN-OD-O                N       O        -       -       -      -       -         -     -\r
+// GPIO17          PCIE_CLKREQ0B-20K,H           N       I        -       -       -     cd2ah    -         -     -\r
+// GPIO18          PCIE_CLKREQ1B-20K,H           N       O        -       -       -     ccaah    -         -     -\r
+// GPIO19          PCIE_CLKREQ2B-20K,H           N       I        -       -       -     ccaah    -         -     -\r
+// GPIO20          PCIE_CLKREQ3B-20K,H           N       -        -       -       -     ccaah    -         -     -\r
+// GPIO21          PCIE_CLKREQ4B-20K,H           N       -        -       -       -      -       -         -     -\r
+// GPIO22          FLEX_CLK_SE0-20K,L            N       O        -       -       -     ccaah    -         -     -\r
+// GPIO23          FLEX_CLK_SE1-20K,L            N       -        -       -       -      -       -         -     -\r
+\r
+// GPIO24          HDA_RSTB                      N       O        -       -       -     8d02h    -         -     -\r
+// GPIO25          HDA_SYNC                      N       O        -       -       -     8d02h    -         -     -\r
+// GPIO26          HDA_CLK                       N       O        -       -       -     8d02h    -         -     -\r
+// GPIO27          HDA_SDO                       N       I        -       -       -     8d02h    -         -     -\r
+// GPIO28          HDA_SDI0                      N       I        -       -       -      -       -         -     -\r
+// GPIO29          HDA_SDI1                      N       O        -       -       -      -       -         -     -\r
+// GPIO30          HDA_DOCKRSTB                  N       I        -       -       -      -       -         -     -\r
+// GPIO31          HDA_DOCKENB                   N       O        -       -       -      -       -         -     -\r
+\r
+// GPIO32          SDMMC1_CLK                    N       -        -       -       -     208d51h   -         -     -\r
+// GPIO33          SDMMC1_D0                     N       -        -       -       -     8cd1h     -         -     -\r
+// GPIO34          SDMMC1_D1                     N       -        -       -       -     8cd1h     -         -     -\r
+// GPIO35          SDMMC1_D2                     N       -        -       -       -     8cd1h     -         -     -\r
+// GPIO36          SDMMC1_D3_CD_B                N       -        -       -       -     8cd1h     -         -     -\r
+// GPIO37          MMC1_D4_SD_WE                 N       -        -       -       -     8cd1h     -         -     -\r
+// GPIO38          MMC1_D5                       N       -        -       -       -     8cd1h     -         -     -\r
+// GPIO39          MMC1_D6                       N       -        -       -       -     8cd1h     -         -     -\r
+// GPIO40          MMC1_D7                       N       -        -       -       -     8cd1h     -         -     -\r
+// GPIO41          SDMMC1_CMD                    N       -        -       -       -     8cd1h     -         -     -\r
+// GPIO42          MMC1_RESET_B                  N       -        -       -       -     208d51h   -         -     -\r
+\r
+// GPIO43          SDMMC2_CLK                    N       -        -       -       -     208d51h   -         -     -\r
+// GPIO44          SDMMC2_D0                     N       -        -       -       -     8cd1h     -         -     -\r
+// GPIO45          SDMMC2_D1                     N       -        -       -       -     8cd1h     -         -     -\r
+// GPIO46          SDMMC2_D2                     N       -        -       -       -     8cd1h     -         -     -\r
+// GPIO47          SDMMC2_D3_CD_B                N       -        -       -       -     8cd1h     -         -     -\r
+// GPIO48          SDMMC2_CMD                    N       -        -       -       -     8cd1h     -         -     -\r
+\r
+// GPIO49          SDMMC3_CLK                    N       -        -       -       -     8d51h      -         -     -\r
+// GPIO50          SDMMC3_D0                     N       -        -       -       -     8cd1h      -         -     -\r
+// GPIO51          SDMMC3_D1                     N       -        -       -       -      8cd1h      -         -     -\r
+// GPIO52          SDMMC3_D2                     N       -        -       -       -      8cd1h      -         -     -\r
+// GPIO53          SDMMC3_D3                     N       -        -       -       -      8cd1h      -         -     -\r
+// GPIO54          SDMMC3_CD_B                   N       -        -       -       -      cca9h      -         -     -\r
+// GPIO55          SDMMC3_CMD                    N       -        -       -       -      8cd1h      -         -     -\r
+// GPIO56          SDMMC3_1P8_EN                 N       -        -       -       -      cd29h   -         -     -\r
+\r
+// GPIO57          LPC_AD0                     N       -        -       -       -      -       -         -     -\r
+// GPIO58          LPC_AD1                     N       -        -       -       -      -       -         -     -\r
+// GPIO59          LPC_AD2                     N       -        -       -       -      -       -         -     -\r
+// GPIO60          LPC_AD3                     N       -        -       -       -      -       -         -     -\r
+// GPIO61          LPC_FRAMEB                  N       O        -       -       -      -       -         -     -\r
+// GPIO62          LPC_CLKOUT0                 N       O        -       -       -      -       -         -     -\r
+// GPIO63          LPC_CLKOUT1                 N       O        -       -       -      -       -         -     -\r
+// GPIO64          LPC_CLKRUNB                 N       -        -       -       -      -       -         -     -\r
+\r
+// GPIO65          SMB_DATA                    N       -        -       -       -      -       -         -     -\r
+// GPIO66          SMB_CLK                     N       -        -       -       -      -       -         -     -\r
+// GPIO67          SMB_ALERTB                  N       -        -       -       -      -       -         -     -\r
+\r
+// GPIO68          ILB_SEIRQ                   N       -       -        -       -      -       -         -     -\r
+// GPIO69          SPKR                        N       O       -        -       -      -       -         -     -\r
+\r
+//SUS WELL\r
+\r
+\r
+//GPIO_SUS0             GPIO_SUS0                   N       O       -        -       -     CCA8h       -         -     -\r
+//GPIO_SUS1             GPIO_SUS1                   N       O       -        -       -     CCA8h       -         -     -\r
+//GPIO_SUS2             GPIO_SUS2                   N       O       -        -       -     CCA8h       -         -     -\r
+//GPIO_SUS3             GPIO_SUS3                   N       O       -        -       -     CD28h       -         -     -\r
+//GPIO_SUS4             GPIO_SUS4                   N       O       -        -       -     CD28h       -         -     -\r
+//GPIO_SUS5             GPIO_SUS5                   N       O       -        -       -     CD28h       -         -     -\r
+//GPIO_SUS6             SUSPWRDNACK-0               N       O       -        -       -     8850h       -         -     -\r
+//GPIO_SUS7             PMU_SLP_DDRVTT_B-0          N       O       -        -       -     8850h       -         -     -\r
+//GPIO_SUS8             PMU_WAKE_B-20K,H            N       O       -        -       -     CCA8h       -         -     -\r
+//GPIO_SUS9             PMU_PWRBTN_B-20K,H          N       O       -        -       -     CCA8h       -         -     -\r
+//GPIO_SUS10            PMU_WAKE_LAN_B-20K,H        N       O       -        -       -     CCA8h       -         -     -\r
+//GPIO_SUS11            SUS_STAT_B-1                N       O       -        -       -     C828h       -         -     -\r
+//GPIO_SUS12            PMU_SUSCLK-0                N       O       -        -       -     C828h       -         -     -\r
+//GPIO_SUS13            USB_OC0_B-20K,H             N       O       -        -       -     CCA8h       -         -     -\r
+//GPIO_SUS14            USB_OC1_B-20K,H             N       O       -        -       -     CCA8h       -         -     -\r
+//GPIO_SUS15            SPI_CS1_B-20K,H             N       O       -        -       -     8C80h       -         -     -\r
+//GPIO_SUS16            SPI_CS1_B-20K,H             N       O       -        -       -     C828h       -         -     -\r
+//\r
+\r
+#define VF_NET_GPIO_USE_SEL_VAL_0_31        0x00000000\r
+#define VF_NET_GPIO_USE_SEL_VAL_32_63       0x00000000\r
+#define VF_NET_GPIO_USE_SEL_VAL_64_70       0x00000000\r
+#define VF_NET_GPIO_USE_SEL_VAL_SUS         0x00000000\r
+\r
+//\r
+//1010 --00 0100 01-- 0101 --0- 0001 1010\r
+//\r
+#define VF_NET_GPIO_IO_SEL_VAL_0_31         0x00000000 // BIT30 | BIT28 | BIT27 | BIT19 | BIT17 | BIT13 | BIT9 | BIT2 | BIT0\r
+#define VF_NET_GPIO_IO_SEL_VAL_32_63        0x00000000\r
+#define VF_NET_GPIO_IO_SEL_VAL_64_70        0x00000000\r
+#define VF_NET_GPIO_IO_SEL_VAL_SUS          0x00000000\r
+\r
+\r
+#define VF_NET_GPIO_LVL_VAL_0_31            0x00000000\r
+#define VF_NET_GPIO_LVL_VAL_32_63           0x00000000\r
+#define VF_NET_GPIO_LVL_VAL_64_70           0x00000000\r
+#define VF_NET_GPIO_LVL_VAL_SUS             0x00000000\r
+\r
+#define VF_NET_GPIO_TPE_VAL_0_31            0x00000000\r
+#define VF_NET_GPIO_TPE_VAL_SUS             0x00000000\r
+\r
+#define VF_NET_GPIO_TNE_VAL_0_31            0x00000000\r
+#define VF_NET_GPIO_TNE_VAL_SUS             0x00000000\r
+\r
+#define VF_NET_GPIO_TS_VAL_0_31             0x00000000\r
+#define VF_NET_GPIO_TS_VAL_SUS              0x00000000\r
+\r
+\r
+//\r
+// Memory space registers\r
+//\r
+\r
+\r
+//\r
+// CONF0\r
+//\r
+#define  VF_NET_PAD_CONF0_GPIO0  0xcd29\r
+#define  VF_NET_PAD_CONF0_GPIO1  0xcd29\r
+#define  VF_NET_PAD_CONF0_GPIO2  0xcca9\r
+#define  VF_NET_PAD_CONF0_GPIO3  0xcca9\r
+#define  VF_NET_PAD_CONF0_GPIO4  0xcca8\r
+#define  VF_NET_PAD_CONF0_GPIO5  0xcca8\r
+#define  VF_NET_PAD_CONF0_GPIO6  0x8d50\r
+#define  VF_NET_PAD_CONF0_GPIO7  0x8cd0\r
+#define  VF_NET_PAD_CONF0_GPIO8  0x8cd0\r
+#define  VF_NET_PAD_CONF0_GPIO9  0x8cd0\r
+#define  VF_NET_PAD_CONF0_GPIO10  0x8d50\r
+#define  VF_NET_PAD_CONF0_GPIO11  0x8cd0\r
+#define  VF_NET_PAD_CONF0_GPIO12  0x8cd0\r
+#define  VF_NET_PAD_CONF0_GPIO13  0x8d50\r
+#define  VF_NET_PAD_CONF0_GPIO14  0xCCA8\r
+#define  VF_NET_PAD_CONF0_GPIO15  0xccaa\r
+#define  VF_NET_PAD_CONF0_GPIO16  0xC828\r
+#define  VF_NET_PAD_CONF0_GPIO17  0xcd2a\r
+#define  VF_NET_PAD_CONF0_GPIO18  0xccaa\r
+#define  VF_NET_PAD_CONF0_GPIO19  0xccaa\r
+#define  VF_NET_PAD_CONF0_GPIO20  0xccaa\r
+#define  VF_NET_PAD_CONF0_GPIO21  0xCCA9\r
+#define  VF_NET_PAD_CONF0_GPIO22  0xccaa\r
+#define  VF_NET_PAD_CONF0_GPIO23  0xCD2A\r
+#define  VF_NET_PAD_CONF0_GPIO24  0x8d02\r
+#define  VF_NET_PAD_CONF0_GPIO25  0x8d02\r
+#define  VF_NET_PAD_CONF0_GPIO26  0x8d02\r
+#define  VF_NET_PAD_CONF0_GPIO27  0x8d02\r
+#define  VF_NET_PAD_CONF0_GPIO28  0x8D02\r
+#define  VF_NET_PAD_CONF0_GPIO29  0x8D02\r
+#define  VF_NET_PAD_CONF0_GPIO30  0x8D00\r
+#define  VF_NET_PAD_CONF0_GPIO31  0xCD2A\r
+#define  VF_NET_PAD_CONF0_GPIO32  0x208d51\r
+#define  VF_NET_PAD_CONF0_GPIO33  0x8cd1\r
+#define  VF_NET_PAD_CONF0_GPIO34  0x8cd1\r
+#define  VF_NET_PAD_CONF0_GPIO35  0x8cd1\r
+#define  VF_NET_PAD_CONF0_GPIO36  0x8cd1\r
+#define  VF_NET_PAD_CONF0_GPIO37  0x8cd1\r
+#define  VF_NET_PAD_CONF0_GPIO38  0x8cd1\r
+#define  VF_NET_PAD_CONF0_GPIO39  0x8cd1\r
+#define  VF_NET_PAD_CONF0_GPIO40  0x8cd1\r
+#define  VF_NET_PAD_CONF0_GPIO41  0x8cd1\r
+#define  VF_NET_PAD_CONF0_GPIO42  0x208d51\r
+#define  VF_NET_PAD_CONF0_GPIO43  0x208d51\r
+#define  VF_NET_PAD_CONF0_GPIO44  0x8cd1\r
+#define  VF_NET_PAD_CONF0_GPIO45  0x8cd1\r
+#define  VF_NET_PAD_CONF0_GPIO46  0x8cd1\r
+#define  VF_NET_PAD_CONF0_GPIO47  0x8cd1\r
+#define  VF_NET_PAD_CONF0_GPIO48  0x8cd1\r
+#define  VF_NET_PAD_CONF0_GPIO49  0x8d51\r
+#define  VF_NET_PAD_CONF0_GPIO50  0x8cd1\r
+#define  VF_NET_PAD_CONF0_GPIO51  0x8cd1\r
+#define  VF_NET_PAD_CONF0_GPIO52  0x8cd1\r
+#define  VF_NET_PAD_CONF0_GPIO53  0x8cd1\r
+#define  VF_NET_PAD_CONF0_GPIO54  0xcca9\r
+#define  VF_NET_PAD_CONF0_GPIO55  0x8cd1\r
+#define  VF_NET_PAD_CONF0_GPIO56  0xcd29\r
+#define  VF_NET_PAD_CONF0_GPIO57  0x8C80\r
+#define  VF_NET_PAD_CONF0_GPIO58  0x8C80\r
+#define  VF_NET_PAD_CONF0_GPIO59  0x8C80\r
+#define  VF_NET_PAD_CONF0_GPIO60  0x8C80\r
+#define  VF_NET_PAD_CONF0_GPIO61  0x8800\r
+#define  VF_NET_PAD_CONF0_GPIO62  0x8D00\r
+#define  VF_NET_PAD_CONF0_GPIO63  0x8800\r
+#define  VF_NET_PAD_CONF0_GPIO64  0x8800\r
+#define  VF_NET_PAD_CONF0_GPIO65  0xC828\r
+#define  VF_NET_PAD_CONF0_GPIO66  0xC828\r
+#define  VF_NET_PAD_CONF0_GPIO67  0xC828\r
+#define  VF_NET_PAD_CONF0_GPIO68  0xCCA8\r
+#define  VF_NET_PAD_CONF0_GPIO69  0xC828\r
+#define  VF_NET_PAD_CONF0_GPIO70  0xCCA8\r
+\r
+\r
+\r
+\r
+//\r
+// PAD_CONF1\r
+//\r
+#define  VF_NET_PAD_CONF1_GPIO0  0x20002\r
+#define  VF_NET_PAD_CONF1_GPIO1  0x20002\r
+#define  VF_NET_PAD_CONF1_GPIO2  0x20002\r
+#define  VF_NET_PAD_CONF1_GPIO3  0x20002\r
+#define  VF_NET_PAD_CONF1_GPIO4  0x20002\r
+#define  VF_NET_PAD_CONF1_GPIO5  0x20002\r
+#define  VF_NET_PAD_CONF1_GPIO6  0x1F000F\r
+#define  VF_NET_PAD_CONF1_GPIO7  0x1F000F\r
+#define  VF_NET_PAD_CONF1_GPIO8  0x1F000F\r
+#define  VF_NET_PAD_CONF1_GPIO9  0x1F000F\r
+#define  VF_NET_PAD_CONF1_GPIO10  0x1F000F\r
+#define  VF_NET_PAD_CONF1_GPIO11  0x1F000F\r
+#define  VF_NET_PAD_CONF1_GPIO12  0x1F000F\r
+#define  VF_NET_PAD_CONF1_GPIO13  0x1F000F\r
+#define  VF_NET_PAD_CONF1_GPIO14  0x20002\r
+#define  VF_NET_PAD_CONF1_GPIO15  0x20002\r
+#define  VF_NET_PAD_CONF1_GPIO16  0x20002\r
+#define  VF_NET_PAD_CONF1_GPIO17  0x20002\r
+#define  VF_NET_PAD_CONF1_GPIO18  0x20002\r
+#define  VF_NET_PAD_CONF1_GPIO19  0x20002\r
+#define  VF_NET_PAD_CONF1_GPIO20  0x20002\r
+#define  VF_NET_PAD_CONF1_GPIO21  0x20002\r
+#define  VF_NET_PAD_CONF1_GPIO22  0x20002\r
+#define  VF_NET_PAD_CONF1_GPIO23  0x20002\r
+#define  VF_NET_PAD_CONF1_GPIO24  0x00000\r
+#define  VF_NET_PAD_CONF1_GPIO25  0x00000\r
+#define  VF_NET_PAD_CONF1_GPIO26  0x00000\r
+#define  VF_NET_PAD_CONF1_GPIO27  0x00000\r
+#define  VF_NET_PAD_CONF1_GPIO28  0x00000\r
+#define  VF_NET_PAD_CONF1_GPIO29  0x00000\r
+#define  VF_NET_PAD_CONF1_GPIO30  0x00000\r
+#define  VF_NET_PAD_CONF1_GPIO31  0x20002\r
+#define  VF_NET_PAD_CONF1_GPIO32  0x00000\r
+#define  VF_NET_PAD_CONF1_GPIO33  0x00000\r
+#define  VF_NET_PAD_CONF1_GPIO34  0x00000\r
+#define  VF_NET_PAD_CONF1_GPIO35  0x00000\r
+#define  VF_NET_PAD_CONF1_GPIO36  0x00000\r
+#define  VF_NET_PAD_CONF1_GPIO37  0x00000\r
+#define  VF_NET_PAD_CONF1_GPIO38  0x00000\r
+#define  VF_NET_PAD_CONF1_GPIO39  0x00000\r
+#define  VF_NET_PAD_CONF1_GPIO40  0x00000\r
+#define  VF_NET_PAD_CONF1_GPIO41  0x00000\r
+#define  VF_NET_PAD_CONF1_GPIO42  0x00000\r
+#define  VF_NET_PAD_CONF1_GPIO43  0x00000\r
+#define  VF_NET_PAD_CONF1_GPIO44  0x00000\r
+#define  VF_NET_PAD_CONF1_GPIO45  0x00000\r
+#define  VF_NET_PAD_CONF1_GPIO46  0x00000\r
+#define  VF_NET_PAD_CONF1_GPIO47  0x00000\r
+#define  VF_NET_PAD_CONF1_GPIO48  0x00000\r
+#define  VF_NET_PAD_CONF1_GPIO49  0x00000\r
+#define  VF_NET_PAD_CONF1_GPIO50  0x00000\r
+#define  VF_NET_PAD_CONF1_GPIO51  0x00000\r
+#define  VF_NET_PAD_CONF1_GPIO52  0x00000\r
+#define  VF_NET_PAD_CONF1_GPIO53  0x00000\r
+#define  VF_NET_PAD_CONF1_GPIO54  0x20002\r
+#define  VF_NET_PAD_CONF1_GPIO55  0x00000\r
+#define  VF_NET_PAD_CONF1_GPIO56  0x20002\r
+#define  VF_NET_PAD_CONF1_GPIO57  0x00000\r
+#define  VF_NET_PAD_CONF1_GPIO58  0x00000\r
+#define  VF_NET_PAD_CONF1_GPIO59  0x00000\r
+#define  VF_NET_PAD_CONF1_GPIO60  0x00000\r
+#define  VF_NET_PAD_CONF1_GPIO61  0x00000\r
+#define  VF_NET_PAD_CONF1_GPIO62  0x00000\r
+#define  VF_NET_PAD_CONF1_GPIO63  0x00000\r
+#define  VF_NET_PAD_CONF1_GPIO64  0x00000\r
+#define  VF_NET_PAD_CONF1_GPIO65  0x20002\r
+#define  VF_NET_PAD_CONF1_GPIO66  0x20002\r
+#define  VF_NET_PAD_CONF1_GPIO67  0x20002\r
+#define  VF_NET_PAD_CONF1_GPIO68  0x20002\r
+#define  VF_NET_PAD_CONF1_GPIO69  0x20002\r
+#define  VF_NET_PAD_CONF1_GPIO70  0x20002\r
+\r
+\r
+\r
+//\r
+// PAD_VAL\r
+//\r
+#define  VF_NET_PAD_VAL_GPIO0  0x2\r
+#define  VF_NET_PAD_VAL_GPIO1  0x2\r
+#define  VF_NET_PAD_VAL_GPIO2  0x2\r
+#define  VF_NET_PAD_VAL_GPIO3  0x2\r
+#define  VF_NET_PAD_VAL_GPIO4  0x2\r
+#define  VF_NET_PAD_VAL_GPIO5  0x2\r
+#define  VF_NET_PAD_VAL_GPIO6  0x2\r
+#define  VF_NET_PAD_VAL_GPIO7  0x2\r
+#define  VF_NET_PAD_VAL_GPIO8  0x2\r
+#define  VF_NET_PAD_VAL_GPIO9  0x2\r
+#define  VF_NET_PAD_VAL_GPIO10  0x2\r
+#define  VF_NET_PAD_VAL_GPIO11  0x2\r
+#define  VF_NET_PAD_VAL_GPIO12  0x2\r
+#define  VF_NET_PAD_VAL_GPIO13  0x2\r
+#define  VF_NET_PAD_VAL_GPIO14  0x2\r
+#define  VF_NET_PAD_VAL_GPIO15  0x2\r
+#define  VF_NET_PAD_VAL_GPIO16  0x4\r
+#define  VF_NET_PAD_VAL_GPIO17  0x2\r
+#define  VF_NET_PAD_VAL_GPIO18  0x2\r
+#define  VF_NET_PAD_VAL_GPIO19  0x2\r
+#define  VF_NET_PAD_VAL_GPIO20  0x2\r
+#define  VF_NET_PAD_VAL_GPIO21  0x2\r
+#define  VF_NET_PAD_VAL_GPIO22  0x2\r
+#define  VF_NET_PAD_VAL_GPIO23  0x2\r
+#define  VF_NET_PAD_VAL_GPIO24  0x2\r
+#define  VF_NET_PAD_VAL_GPIO25  0x2\r
+#define  VF_NET_PAD_VAL_GPIO26  0x2\r
+#define  VF_NET_PAD_VAL_GPIO27  0x2\r
+#define  VF_NET_PAD_VAL_GPIO28  0x2\r
+#define  VF_NET_PAD_VAL_GPIO29  0x2\r
+#define  VF_NET_PAD_VAL_GPIO30  0x2\r
+#define  VF_NET_PAD_VAL_GPIO31  0x2\r
+#define  VF_NET_PAD_VAL_GPIO32  0x2\r
+#define  VF_NET_PAD_VAL_GPIO33  0x2\r
+#define  VF_NET_PAD_VAL_GPIO34  0x2\r
+#define  VF_NET_PAD_VAL_GPIO35  0x2\r
+#define  VF_NET_PAD_VAL_GPIO36  0x2\r
+#define  VF_NET_PAD_VAL_GPIO37  0x2\r
+#define  VF_NET_PAD_VAL_GPIO38  0x2\r
+#define  VF_NET_PAD_VAL_GPIO39  0x2\r
+#define  VF_NET_PAD_VAL_GPIO40  0x2\r
+#define  VF_NET_PAD_VAL_GPIO41  0x2\r
+#define  VF_NET_PAD_VAL_GPIO42  0x2\r
+#define  VF_NET_PAD_VAL_GPIO43  0x2\r
+#define  VF_NET_PAD_VAL_GPIO44  0x2\r
+#define  VF_NET_PAD_VAL_GPIO45  0x2\r
+#define  VF_NET_PAD_VAL_GPIO46  0x2\r
+#define  VF_NET_PAD_VAL_GPIO47  0x2\r
+#define  VF_NET_PAD_VAL_GPIO48  0x2\r
+#define  VF_NET_PAD_VAL_GPIO49  0x2\r
+#define  VF_NET_PAD_VAL_GPIO50  0x2\r
+#define  VF_NET_PAD_VAL_GPIO51  0x2\r
+#define  VF_NET_PAD_VAL_GPIO52  0x2\r
+#define  VF_NET_PAD_VAL_GPIO53  0x2\r
+#define  VF_NET_PAD_VAL_GPIO54  0x2\r
+#define  VF_NET_PAD_VAL_GPIO55  0x2\r
+#define  VF_NET_PAD_VAL_GPIO56  0x2\r
+#define  VF_NET_PAD_VAL_GPIO57  0x2\r
+#define  VF_NET_PAD_VAL_GPIO58  0x2\r
+#define  VF_NET_PAD_VAL_GPIO59  0x2\r
+#define  VF_NET_PAD_VAL_GPIO60  0x2\r
+#define  VF_NET_PAD_VAL_GPIO61  0x4\r
+#define  VF_NET_PAD_VAL_GPIO62  0x2\r
+#define  VF_NET_PAD_VAL_GPIO63  0x2\r
+#define  VF_NET_PAD_VAL_GPIO64  0x2\r
+#define  VF_NET_PAD_VAL_GPIO65  0x2\r
+#define  VF_NET_PAD_VAL_GPIO66  0x2\r
+#define  VF_NET_PAD_VAL_GPIO67  0x0\r
+#define  VF_NET_PAD_VAL_GPIO68  0x2\r
+#define  VF_NET_PAD_VAL_GPIO69  0x4\r
+#define  VF_NET_PAD_VAL_GPIO70  0x2\r
+\r
+\r
+//\r
+// PAD_DFT\r
+//\r
+#define  VF_NET_PAD_DFT_GPIO0  0xC\r
+#define  VF_NET_PAD_DFT_GPIO1  0xC\r
+#define  VF_NET_PAD_DFT_GPIO2  0xC\r
+#define  VF_NET_PAD_DFT_GPIO3  0xC\r
+#define  VF_NET_PAD_DFT_GPIO4  0xC\r
+#define  VF_NET_PAD_DFT_GPIO5  0xC\r
+#define  VF_NET_PAD_DFT_GPIO6  0xC\r
+#define  VF_NET_PAD_DFT_GPIO7  0xC\r
+#define  VF_NET_PAD_DFT_GPIO8  0xC\r
+#define  VF_NET_PAD_DFT_GPIO9  0xC\r
+#define  VF_NET_PAD_DFT_GPIO10  0xC\r
+#define  VF_NET_PAD_DFT_GPIO11  0xC\r
+#define  VF_NET_PAD_DFT_GPIO12  0xC\r
+#define  VF_NET_PAD_DFT_GPIO13  0xC\r
+#define  VF_NET_PAD_DFT_GPIO14  0xC\r
+#define  VF_NET_PAD_DFT_GPIO15  0xC\r
+#define  VF_NET_PAD_DFT_GPIO16  0xC\r
+#define  VF_NET_PAD_DFT_GPIO17  0xC\r
+#define  VF_NET_PAD_DFT_GPIO18  0xC\r
+#define  VF_NET_PAD_DFT_GPIO19  0xC\r
+#define  VF_NET_PAD_DFT_GPIO20  0xC\r
+#define  VF_NET_PAD_DFT_GPIO21  0xC\r
+#define  VF_NET_PAD_DFT_GPIO22  0xC\r
+#define  VF_NET_PAD_DFT_GPIO23  0xC\r
+#define  VF_NET_PAD_DFT_GPIO24  0xC\r
+#define  VF_NET_PAD_DFT_GPIO25  0xC\r
+#define  VF_NET_PAD_DFT_GPIO26  0xC\r
+#define  VF_NET_PAD_DFT_GPIO27  0xC\r
+#define  VF_NET_PAD_DFT_GPIO28  0xC\r
+#define  VF_NET_PAD_DFT_GPIO29  0xC\r
+#define  VF_NET_PAD_DFT_GPIO30  0xC\r
+#define  VF_NET_PAD_DFT_GPIO31  0xC\r
+#define  VF_NET_PAD_DFT_GPIO32  0xC\r
+#define  VF_NET_PAD_DFT_GPIO33  0xC\r
+#define  VF_NET_PAD_DFT_GPIO34  0xC\r
+#define  VF_NET_PAD_DFT_GPIO35  0xC\r
+#define  VF_NET_PAD_DFT_GPIO36  0xC\r
+#define  VF_NET_PAD_DFT_GPIO37  0xC\r
+#define  VF_NET_PAD_DFT_GPIO38  0xC\r
+#define  VF_NET_PAD_DFT_GPIO39  0xC\r
+#define  VF_NET_PAD_DFT_GPIO40  0xC\r
+#define  VF_NET_PAD_DFT_GPIO41  0xC\r
+#define  VF_NET_PAD_DFT_GPIO42  0xC\r
+#define  VF_NET_PAD_DFT_GPIO43  0xC\r
+#define  VF_NET_PAD_DFT_GPIO44  0xC\r
+#define  VF_NET_PAD_DFT_GPIO45  0xC\r
+#define  VF_NET_PAD_DFT_GPIO46  0xC\r
+#define  VF_NET_PAD_DFT_GPIO47  0xC\r
+#define  VF_NET_PAD_DFT_GPIO48  0xC\r
+#define  VF_NET_PAD_DFT_GPIO49  0xC\r
+#define  VF_NET_PAD_DFT_GPIO50  0xC\r
+#define  VF_NET_PAD_DFT_GPIO51  0xC\r
+#define  VF_NET_PAD_DFT_GPIO52  0xC\r
+#define  VF_NET_PAD_DFT_GPIO53  0xC\r
+#define  VF_NET_PAD_DFT_GPIO54  0xC\r
+#define  VF_NET_PAD_DFT_GPIO55  0xC\r
+#define  VF_NET_PAD_DFT_GPIO56  0xC\r
+#define  VF_NET_PAD_DFT_GPIO57  0xC\r
+#define  VF_NET_PAD_DFT_GPIO58  0xC\r
+#define  VF_NET_PAD_DFT_GPIO59  0xC\r
+#define  VF_NET_PAD_DFT_GPIO60  0xC\r
+#define  VF_NET_PAD_DFT_GPIO61  0xC\r
+#define  VF_NET_PAD_DFT_GPIO62  0xC\r
+#define  VF_NET_PAD_DFT_GPIO63  0xC\r
+#define  VF_NET_PAD_DFT_GPIO64  0xC\r
+#define  VF_NET_PAD_DFT_GPIO65  0xC\r
+#define  VF_NET_PAD_DFT_GPIO66  0xC\r
+#define  VF_NET_PAD_DFT_GPIO67  0xC\r
+#define  VF_NET_PAD_DFT_GPIO68  0xC\r
+#define  VF_NET_PAD_DFT_GPIO69  0xC\r
+#define  VF_NET_PAD_DFT_GPIO70  0xC\r
+\r
+//\r
+// PCONF0\r
+//\r
+#define  VF_NET_PAD_CONF0_GPIO_SUS0  0xCCA8\r
+#define  VF_NET_PAD_CONF0_GPIO_SUS1  0xCCA8\r
+#define  VF_NET_PAD_CONF0_GPIO_SUS2  0xCCA8\r
+#define  VF_NET_PAD_CONF0_GPIO_SUS3  0xCD28\r
+#define  VF_NET_PAD_CONF0_GPIO_SUS4  0xCD28\r
+#define  VF_NET_PAD_CONF0_GPIO_SUS5  0xCD28\r
+#define  VF_NET_PAD_CONF0_GPIO_SUS6  0x8850\r
+#define  VF_NET_PAD_CONF0_GPIO_SUS7  0x8850\r
+#define  VF_NET_PAD_CONF0_GPIO_SUS8  0xCCA8\r
+#define  VF_NET_PAD_CONF0_GPIO_SUS9  0xCCA8\r
+#define  VF_NET_PAD_CONF0_GPIO_SUS10  0xCCA8\r
+#define  VF_NET_PAD_CONF0_GPIO_SUS11  0xC828\r
+#define  VF_NET_PAD_CONF0_GPIO_SUS12  0xC828\r
+#define  VF_NET_PAD_CONF0_GPIO_SUS13  0xCCA8\r
+#define  VF_NET_PAD_CONF0_GPIO_SUS14  0xCCA8\r
+#define  VF_NET_PAD_CONF0_GPIO_SUS15  0x8C80\r
+#define  VF_NET_PAD_CONF0_GPIO_SUS16  0xC828\r
+\r
+//\r
+// PCONF1\r
+//\r
+#define  VF_NET_PAD_CONF1_GPIO_SUS0  0\r
+#define  VF_NET_PAD_CONF1_GPIO_SUS1  0\r
+#define  VF_NET_PAD_CONF1_GPIO_SUS2  0\r
+#define  VF_NET_PAD_CONF1_GPIO_SUS3  0\r
+#define  VF_NET_PAD_CONF1_GPIO_SUS4  0\r
+#define  VF_NET_PAD_CONF1_GPIO_SUS5  0\r
+#define  VF_NET_PAD_CONF1_GPIO_SUS6  0\r
+#define  VF_NET_PAD_CONF1_GPIO_SUS7  0\r
+#define  VF_NET_PAD_CONF1_GPIO_SUS8  0\r
+#define  VF_NET_PAD_CONF1_GPIO_SUS9  0\r
+#define  VF_NET_PAD_CONF1_GPIO_SUS10  0\r
+#define  VF_NET_PAD_CONF1_GPIO_SUS11  0\r
+#define  VF_NET_PAD_CONF1_GPIO_SUS12  0\r
+#define  VF_NET_PAD_CONF1_GPIO_SUS13  0\r
+#define  VF_NET_PAD_CONF1_GPIO_SUS14  0\r
+#define  VF_NET_PAD_CONF1_GPIO_SUS15  0\r
+#define  VF_NET_PAD_CONF1_GPIO_SUS16  0\r
+\r
+\r
+#define  VF_NET_PAD_VAL_GPIO_SUS0  0\r
+#define  VF_NET_PAD_VAL_GPIO_SUS1  0\r
+#define  VF_NET_PAD_VAL_GPIO_SUS2  0\r
+#define  VF_NET_PAD_VAL_GPIO_SUS3  0\r
+#define  VF_NET_PAD_VAL_GPIO_SUS4  0\r
+#define  VF_NET_PAD_VAL_GPIO_SUS5  0\r
+#define  VF_NET_PAD_VAL_GPIO_SUS6  0\r
+#define  VF_NET_PAD_VAL_GPIO_SUS7  0\r
+#define  VF_NET_PAD_VAL_GPIO_SUS8  0\r
+#define  VF_NET_PAD_VAL_GPIO_SUS9  0\r
+#define  VF_NET_PAD_VAL_GPIO_SUS10  0\r
+#define  VF_NET_PAD_VAL_GPIO_SUS11  0\r
+#define  VF_NET_PAD_VAL_GPIO_SUS12  0\r
+#define  VF_NET_PAD_VAL_GPIO_SUS13  0\r
+#define  VF_NET_PAD_VAL_GPIO_SUS14  0\r
+#define  VF_NET_PAD_VAL_GPIO_SUS15  0\r
+#define  VF_NET_PAD_VAL_GPIO_SUS16  0\r
+\r
+\r
+#define  VF_NET_PAD_DFT_GPIO_SUS0  0\r
+#define  VF_NET_PAD_DFT_GPIO_SUS1  0\r
+#define  VF_NET_PAD_DFT_GPIO_SUS2  0\r
+#define  VF_NET_PAD_DFT_GPIO_SUS3  0\r
+#define  VF_NET_PAD_DFT_GPIO_SUS4  0\r
+#define  VF_NET_PAD_DFT_GPIO_SUS5  0\r
+#define  VF_NET_PAD_DFT_GPIO_SUS6  0\r
+#define  VF_NET_PAD_DFT_GPIO_SUS7  0\r
+#define  VF_NET_PAD_DFT_GPIO_SUS8  0\r
+#define  VF_NET_PAD_DFT_GPIO_SUS9  0\r
+#define  VF_NET_PAD_DFT_GPIO_SUS10  0\r
+#define  VF_NET_PAD_DFT_GPIO_SUS11  0\r
+#define  VF_NET_PAD_DFT_GPIO_SUS12  0\r
+#define  VF_NET_PAD_DFT_GPIO_SUS13  0\r
+#define  VF_NET_PAD_DFT_GPIO_SUS14  0\r
+#define  VF_NET_PAD_DFT_GPIO_SUS15  0\r
+#define  VF_NET_PAD_DFT_GPIO_SUS16  0\r
+\r
+\r
+//\r
+// Function Prototypes\r
+//\r
+EFI_STATUS\r
+PlatformPchInit (\r
+  IN SYSTEM_CONFIGURATION        *SystemConfiguration,\r
+  IN CONST EFI_PEI_SERVICES      **PeiServices,\r
+  IN UINT16                      PlatformType\r
+  );\r
+\r
+EFI_STATUS\r
+PlatformCpuInit (\r
+  IN CONST EFI_PEI_SERVICES            **PeiServices,\r
+  IN SYSTEM_CONFIGURATION        *SystemConfiguration,\r
+  IN EFI_PLATFORM_CPU_INFO       *PlatformCpuInfo\r
+  );\r
+\r
+EFI_STATUS\r
+PeimInitializeFlashMap (\r
+  IN EFI_FFS_FILE_HEADER        *FfsHeader,\r
+  IN CONST EFI_PEI_SERVICES           **PeiServices\r
+  );\r
+\r
+EFI_STATUS\r
+PeimInstallFlashMapPpi (\r
+  IN EFI_FFS_FILE_HEADER        *FfsHeader,\r
+  IN CONST EFI_PEI_SERVICES           **PeiServices\r
+  );\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+IchReset (\r
+  IN CONST EFI_PEI_SERVICES           **PeiServices\r
+  )\r
+;\r
+\r
+BOOLEAN\r
+GetSleepTypeAfterWakeup (\r
+  IN  CONST EFI_PEI_SERVICES          **PeiServices,\r
+  OUT UINT16                    *SleepType\r
+  );\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+GetWakeupEventAndSaveToHob (\r
+  IN CONST EFI_PEI_SERVICES   **PeiServices\r
+  )\r
+;\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+MemoryDiscoveredPpiNotifyCallback (\r
+  IN CONST EFI_PEI_SERVICES           **PeiServices,\r
+  IN EFI_PEI_NOTIFY_DESCRIPTOR  *NotifyDescriptor,\r
+  IN VOID                       *Ppi\r
+  )\r
+;\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+PeiGetVariable (\r
+  IN CONST EFI_PEI_SERVICES             **PeiServices,\r
+  IN CHAR16                       *VariableName,\r
+  IN EFI_GUID                     * VendorGuid,\r
+  OUT UINT32                      *Attributes OPTIONAL,\r
+  IN OUT UINTN                    *DataSize,\r
+  OUT VOID                        *Data\r
+  )\r
+;\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+PeiGetNextVariableName (\r
+  IN CONST EFI_PEI_SERVICES             **PeiServices,\r
+  IN OUT UINTN                    *VariableNameSize,\r
+  IN OUT CHAR16                   *VariableName,\r
+  IN OUT EFI_GUID                 *VendorGuid\r
+  )\r
+;\r
+\r
+EFI_STATUS\r
+UpdateBootMode (\r
+  IN CONST EFI_PEI_SERVICES                       **PeiServices,\r
+  IN OUT EFI_PLATFORM_INFO_HOB                    *PlatformInfoHob\r
+  );\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+EndOfPeiPpiNotifyCallback (\r
+  IN CONST EFI_PEI_SERVICES           **PeiServices,\r
+  IN EFI_PEI_NOTIFY_DESCRIPTOR  *NotifyDescriptor,\r
+  IN VOID                       *Ppi\r
+  );\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+PeimInitializeRecovery (\r
+  IN CONST EFI_PEI_SERVICES     **PeiServices\r
+  )\r
+;\r
+\r
+VOID\r
+CheckPowerOffNow (\r
+  VOID\r
+  );\r
+\r
+VOID\r
+IchGpioInit (\r
+  IN UINT16                     PlatformType,\r
+  IN SYSTEM_CONFIGURATION       *SystemConfiguration\r
+  );\r
+\r
+EFI_STATUS\r
+PcieSecondaryBusReset (\r
+  IN CONST EFI_PEI_SERVICES  **PeiServices,\r
+  IN UINT8             Bus,\r
+  IN UINT8             Dev,\r
+  IN UINT8             Fun\r
+  );\r
+\r
+VOID\r
+SetPlatformBootMode (\r
+  IN CONST EFI_PEI_SERVICES             **PeiServices,\r
+  IN OUT EFI_PLATFORM_INFO_HOB *PlatformInfoHob\r
+  );\r
+\r
+BOOLEAN\r
+CheckIfJumperSetForRecovery(\r
+  VOID\r
+  );\r
+\r
+EFI_STATUS\r
+EFIAPI    \r
+FindFv (\r
+  IN EFI_PEI_FIND_FV_PPI              *This,\r
+  IN CONST EFI_PEI_SERVICES             **PeiServices,\r
+  IN OUT UINT8                    *FvNumber,\r
+  OUT EFI_FIRMWARE_VOLUME_HEADER  **FVAddress\r
+  );\r
+\r
+BOOLEAN\r
+IsA16Inverted (\r
+  );\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+CpuOnlyReset (\r
+  IN CONST EFI_PEI_SERVICES   **PeiServices\r
+  );\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+InitLan (\r
+  IN CONST EFI_PEI_SERVICES          **PeiServices,\r
+  IN SYSTEM_CONFIGURATION      *Buffer\r
+  );\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+Stall (\r
+  IN CONST EFI_PEI_SERVICES     **PeiServices,\r
+  IN CONST EFI_PEI_STALL_PPI    *This,\r
+  IN UINTN                      Microseconds\r
+  );\r
+\r
+EFI_STATUS\r
+MultiPlatformInfoInit (\r
+  IN CONST EFI_PEI_SERVICES          **PeiServices,\r
+  IN OUT EFI_PLATFORM_INFO_HOB *PlatformInfoHob\r
+  );\r
+\r
+BOOLEAN\r
+IsRecoveryJumper (\r
+  IN CONST EFI_PEI_SERVICES    **PeiServices,\r
+    IN OUT EFI_PLATFORM_INFO_HOB *PlatformInfoHob\r
+);\r
+\r
+EFI_STATUS\r
+CheckOsSelection (\r
+  IN CONST EFI_PEI_SERVICES          **PeiServices,\r
+  IN SYSTEM_CONFIGURATION            *SystemConfiguration\r
+  );\r
+\r
+EFI_STATUS\r
+PlatformInfoUpdate (\r
+  IN CONST EFI_PEI_SERVICES          **PeiServices,\r
+  IN OUT EFI_PLATFORM_INFO_HOB *PlatformInfoHob,\r
+  IN SYSTEM_CONFIGURATION      *SystemConfiguration\r
+  );\r
+\r
+VOID\r
+PlatformSsaInit (\r
+IN SYSTEM_CONFIGURATION        *SystemConfiguration,\r
+IN CONST EFI_PEI_SERVICES      **PeiServices\r
+  );\r
+\r
+EFI_STATUS\r
+InitializePlatform (\r
+  IN CONST EFI_PEI_SERVICES             **PeiServices,\r
+  IN EFI_PLATFORM_INFO_HOB        *PlatformInfoHob,\r
+  IN SYSTEM_CONFIGURATION         *SystemConfiguration\r
+);\r
+\r
+VOID\r
+MchInit (\r
+IN CONST EFI_PEI_SERVICES                     **PeiServices\r
+  );\r
+\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+SetPeiCacheMode (\r
+  IN  CONST EFI_PEI_SERVICES    **PeiServices\r
+  );\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+SetDxeCacheMode (\r
+  IN  CONST EFI_PEI_SERVICES    **PeiServices\r
+  );\r
+\r
+EFI_STATUS\r
+GPIO_initialization (\r
+  IN EFI_PEI_SERVICES                   **PeiServices,\r
+  IN EFI_PEI_NOTIFY_DESCRIPTOR          *NotifyDescriptor,\r
+  IN VOID                               *SmbusPpi\r
+  );\r
+\r
+\r
+BOOLEAN\r
+IsRtcUipAlwaysSet (\r
+  IN CONST EFI_PEI_SERVICES       **PeiServices\r
+  );\r
+\r
+\r
+\r
+EFI_STATUS\r
+InitPchUsb (\r
+  IN CONST EFI_PEI_SERVICES  **PeiServices\r
+  );\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+PublishMemoryTypeInfo (\r
+  void\r
+  );\r
+\r
+\r
+#endif\r

diff --git a/Vlv2TbltDevicePkg/PlatformInitPei/PlatformInfoInit.c b/Vlv2TbltDevicePkg/PlatformInitPei/PlatformInfoInit.c
new file mode 100644 (file)
index 0000000..48d69a3
--- /dev/null
+++ b/Vlv2TbltDevicePkg/PlatformInitPei/PlatformInfoInit.c
@@ -0,0 +1,186 @@
+/** @file\r
+\r
+  Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+Module Name:\r
+\r
+  PlatformInfoInit.c\r
+\r
+Abstract:\r
+  Platform Info Driver.\r
+\r
+--*/\r
+\r
+#include "PlatformEarlyInit.h"\r
+\r
+#define LEN_64M       0x4000000\r
+\r
+//\r
+// Default PCI32 resource size\r
+//\r
+#define RES_MEM32_MIN_LEN   0x38000000\r
+\r
+#define RES_IO_BASE   0x0D00\r
+#define RES_IO_LIMIT  0xFFFF\r
+\r
+#define MemoryCeilingVariable   L"MemCeil."\r
+\r
+EFI_STATUS\r
+CheckOsSelection (\r
+  IN CONST EFI_PEI_SERVICES          **PeiServices,\r
+  IN SYSTEM_CONFIGURATION            *SystemConfiguration\r
+  )\r
+{\r
+  EFI_STATUS                   Status;\r
+  EFI_PEI_READ_ONLY_VARIABLE2_PPI   *Variable;\r
+  UINTN                        VariableSize;\r
+  EFI_OS_SELECTION_HOB         *OsSelectionHob;\r
+  UINT8                        OsSelection;\r
+  UINT8                        *LpssDataHobPtr;\r
+  UINT8                        *LpssDataVarPtr;\r
+  UINTN                        i;\r
+\r
+  Status = (*PeiServices)->LocatePpi (\r
+                             PeiServices,\r
+                             &gEfiPeiReadOnlyVariable2PpiGuid,\r
+                             0,\r
+                             NULL,\r
+                                      (void **)&Variable\r
+                             );\r
+  if (!EFI_ERROR(Status)) {\r
+    VariableSize = sizeof (OsSelection);\r
+    Status = Variable->GetVariable (\r
+                         Variable,\r
+                         L"OsSelection",\r
+                         &gOsSelectionVariableGuid,\r
+                         NULL,\r
+                         &VariableSize,\r
+                         &OsSelection\r
+                         );\r
+\r
+    if (!EFI_ERROR(Status) && (SystemConfiguration->ReservedO != OsSelection)) {\r
+      //\r
+      // Build HOB for OsSelection\r
+      //\r
+      OsSelectionHob = BuildGuidHob (&gOsSelectionVariableGuid, sizeof (EFI_OS_SELECTION_HOB));\r
+      ASSERT (OsSelectionHob != NULL);\r
+\r
+      OsSelectionHob->OsSelectionChanged = TRUE;\r
+      OsSelectionHob->OsSelection        = OsSelection;\r
+      SystemConfiguration->ReservedO   = OsSelectionHob->OsSelection;\r
+\r
+      //\r
+      // Load LPSS and SCC defalut configurations\r
+      //\r
+      OsSelectionHob->LpssData.LpsseMMCEnabled            = FALSE;\r
+      OsSelectionHob->LpssData.LpssSdioEnabled            = TRUE;\r
+      OsSelectionHob->LpssData.LpssSdcardEnabled          = TRUE;\r
+      OsSelectionHob->LpssData.LpssSdCardSDR25Enabled     = FALSE;\r
+      OsSelectionHob->LpssData.LpssSdCardDDR50Enabled     = TRUE;\r
+      OsSelectionHob->LpssData.LpssMipiHsi                = FALSE;\r
+      OsSelectionHob->LpssData.LpsseMMC45Enabled          = TRUE;\r
+      OsSelectionHob->LpssData.LpsseMMC45DDR50Enabled     = TRUE;\r
+      OsSelectionHob->LpssData.LpsseMMC45HS200Enabled     = FALSE;\r
+      OsSelectionHob->LpssData.LpsseMMC45RetuneTimerValue = 8;\r
+      OsSelectionHob->LpssData.eMMCBootMode               = 1;     // Auto Detect\r
+\r
+\r
+      SystemConfiguration->Lpe       = OsSelectionHob->Lpe;\r
+      SystemConfiguration->PchAzalia = SystemConfiguration->PchAzalia;\r
+      LpssDataHobPtr = &OsSelectionHob->LpssData.LpssPciModeEnabled;\r
+      LpssDataVarPtr = &SystemConfiguration->LpssPciModeEnabled;\r
+\r
+      for (i = 0; i < sizeof(EFI_PLATFORM_LPSS_DATA); i++) {\r
+        *LpssDataVarPtr = *LpssDataHobPtr;\r
+        LpssDataVarPtr++;\r
+        LpssDataHobPtr++;\r
+      }\r
+    }\r
+  }\r
+\r
+  return EFI_SUCCESS;\r
+}\r
+\r
+\r
+EFI_STATUS\r
+PlatformInfoUpdate (\r
+  IN CONST EFI_PEI_SERVICES          **PeiServices,\r
+  IN OUT EFI_PLATFORM_INFO_HOB *PlatformInfoHob,\r
+  IN SYSTEM_CONFIGURATION      *SystemConfiguration\r
+  )\r
+{\r
+  EFI_STATUS                   Status;\r
+  EFI_PEI_READ_ONLY_VARIABLE2_PPI   *Variable;\r
+  UINTN                        VariableSize;\r
+  UINT32                       MemoryCeiling;\r
+\r
+  //\r
+  // Checking PCI32 resource from previous boot to determine the memory ceiling\r
+  //\r
+  Status = (*PeiServices)->LocatePpi (\r
+                             PeiServices,\r
+                             &gEfiPeiReadOnlyVariable2PpiGuid,\r
+                             0,\r
+                             NULL,\r
+                                      (void **)&Variable\r
+                             );\r
+  if (!EFI_ERROR(Status)) {\r
+    //\r
+    // Get the memory ceiling\r
+    //\r
+    VariableSize = sizeof(MemoryCeiling);\r
+    Status = Variable->GetVariable (\r
+                         Variable,\r
+                         MemoryCeilingVariable,\r
+                         &gEfiGlobalVariableGuid,\r
+                         NULL,\r
+                         &VariableSize,\r
+                         &MemoryCeiling\r
+                         );\r
+    if(!EFI_ERROR(Status)) {\r
+      //\r
+      // Set the new PCI32 resource Base if the variable available\r
+      //\r
+      PlatformInfoHob->PciData.PciResourceMem32Base = MemoryCeiling;\r
+      PlatformInfoHob->MemData.MemMaxTolm = MemoryCeiling;\r
+      PlatformInfoHob->MemData.MemTolm = MemoryCeiling;\r
+\r
+      //\r
+      // Platform PCI MMIO Size in unit of 1MB\r
+      //\r
+      PlatformInfoHob->MemData.MmioSize = 0x1000 - (UINT16)(PlatformInfoHob->MemData.MemMaxTolm >> 20);\r
+    }\r
+  }\r
+\r
+  return EFI_SUCCESS;\r
+}\r
+\r
+/**\r
+  Initialize the platform related info hob according to the\r
+  pre-determine value or setup option\r
+\r
+  @retval EFI_SUCCESS    Memory initialization completed successfully.\r
+  @retval Others         All other error conditions encountered result in an ASSERT.\r
+**/\r
+EFI_STATUS\r
+InitializePlatform (\r
+  IN CONST EFI_PEI_SERVICES       **PeiServices,\r
+  IN EFI_PLATFORM_INFO_HOB        *PlatformInfoHob,\r
+  IN SYSTEM_CONFIGURATION         *SystemConfiguration\r
+)\r
+{\r
+//\r
+// -- cchew10 need to update here.\r
+//\r
+  return EFI_SUCCESS;\r
+}\r
+\r

diff --git a/Vlv2TbltDevicePkg/PlatformInitPei/PlatformInitPei.inf b/Vlv2TbltDevicePkg/PlatformInitPei/PlatformInitPei.inf
new file mode 100644 (file)
index 0000000..fc517ef
--- /dev/null
+++ b/Vlv2TbltDevicePkg/PlatformInitPei/PlatformInitPei.inf
@@ -0,0 +1,122 @@
+#\r
+#\r
+# Copyright (c)  1999  - 2014, Intel Corporation. All rights reserved\r
+#                                                                                  \r\r
+# This program and the accompanying materials are licensed and made available under\r\r
+# the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+# The full text of the license may be found at                                     \r\r
+# http://opensource.org/licenses/bsd-license.php.                                  \r\r
+#                                                                                  \r\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+#                                                                                  \r\r
+#\r
+#\r
+#  Module Name:\r
+#\r
+#    PlatformEarlyInit.inf\r
+#\r
+#  Abstract:\r
+#\r
+#    Component description file for PlatformEarlyInit module\r
+#\r
+#--*/\r
+\r
+[defines]\r
+INF_VERSION                               = 0x00010005\r
+BASE_NAME                                         = PlatformEarlyInit\r
+FILE_GUID                                         = 0A5EA2E1-BE0B-44a0-A775-F429C9A018A0\r
+MODULE_TYPE                               = PEIM\r
+VERSION_STRING                            = 1.0\r
+PI_SPECIFICATION_VERSION          = 0x0001000A\r
+ENTRY_POINT                               = PlatformEarlyInitEntry\r
+\r
+[sources.common]\r
+  BootMode.c\r
+  CpuInitPeim.c\r
+  PchInitPeim.c\r
+  MchInit.c\r
+  MemoryCallback.c\r
+  MemoryPeim.c\r
+  PlatformEarlyInit.c\r
+  PlatformEarlyInit.h\r
+  PlatformInfoInit.c\r
+  LegacySpeaker.c\r
+  LegacySpeaker.h\r
+  Stall.c\r
+  PlatformSsaInitPeim.c\r
+\r
+[Packages]\r
+  MdePkg/MdePkg.dec\r
+  MdeModulePkg/MdeModulePkg.dec\r
+  Vlv2TbltDevicePkg/PlatformPkg.dec\r
+  IntelFrameworkPkg/IntelFrameworkPkg.dec\r
+  Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec\r
+  IA32FamilyCpuPkg/IA32FamilyCpuPkg.dec\r
+  UefiCpuPkg/UefiCpuPkg.dec\r
+  Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec\r
+  IntelFrameworkModulePkg/IntelFrameworkModulePkg.dec\r
+\r
+[LibraryClasses]\r
+  PeimEntryPoint\r
+  DebugLib\r
+  HobLib\r
+  IoLib\r
+#  PeiKscLib\r
+  MultiPlatformLib\r
+  PcdLib\r
+  PchPlatformLib\r
+  MtrrLib\r
+\r
+[Ppis]\r
+  gEfiPeiStallPpiGuid\r
+  gPeiSpeakerInterfacePpiGuid\r
+  gEfiPeiMemoryDiscoveredPpiGuid\r
+  gVlvPolicyPpiGuid\r
+  gEfiPeiReadOnlyVariable2PpiGuid\r
+  gEfiPeiResetPpiGuid\r
+  gEfiEndOfPeiSignalPpiGuid\r
+  gPeiSmbusPolicyPpiGuid\r
+  gEfiFindFvPpiGuid\r
+  gPeiCapsulePpiGuid\r
+  gEfiPeiBootInRecoveryModePpiGuid\r
+  gEfiPeiRecoveryModulePpiGuid\r
+  gEfiPeiDeviceRecoveryModulePpiGuid\r
+  gPeiCachePpiGuid\r
+  gEfiPeiMasterBootModePpiGuid\r
+  gEfiPeiSmbusPpiGuid\r
+  gPchInitPpiGuid\r
+  gPchUsbPolicyPpiGuid\r
+\r
+[Guids]\r
+  gEfiSetupVariableGuid\r
+  gEfiPlatformInfoGuid\r
+  gEfiPlatformBootModeGuid\r
+  gEfiPlatformCpuInfoGuid\r
+  gEfiGlobalVariableGuid\r
+  gRecoveryOnFatFloppyDiskGuid\r
+  gRecoveryOnFatUsbDiskGuid\r
+  gRecoveryOnFatIdeDiskGuid\r
+  gRecoveryOnDataCdGuid\r
+  gMfgModeVariableGuid\r
+  gEfiNormalSetupGuid\r
+  gEfiMemoryTypeInformationGuid\r
+  gOsSelectionVariableGuid\r
+\r
+[Pcd.common]\r
+  gPlatformModuleTokenSpaceGuid.PcdFlashFvMainBase\r
+  gPlatformModuleTokenSpaceGuid.PcdFlashFvMainSize\r
+  gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress\r
+  gEfiIchTokenSpaceGuid.PcdPeiIchEhciControllerMemoryBaseAddress\r
+\r
+  gPlatformModuleTokenSpaceGuid.PcdFlashAreaBaseAddress\r
+  gPlatformModuleTokenSpaceGuid.PcdFlashAreaSize\r
+  gPlatformModuleTokenSpaceGuid.PcdFlashFvRecovery2Base\r
+  gPlatformModuleTokenSpaceGuid.PcdFlashFvRecovery2Size\r
+\r
+[Pcd]\r
+  gEfiVLVTokenSpaceGuid.PcdMeasuredBootEnable\r
+  gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdBootState\r
+\r
+[Depex]\r
+  gEfiPeiReadOnlyVariable2PpiGuid  AND gPeiCachePpiGuid\r

diff --git a/Vlv2TbltDevicePkg/PlatformInitPei/PlatformSsaInitPeim.c b/Vlv2TbltDevicePkg/PlatformInitPei/PlatformSsaInitPeim.c
new file mode 100644 (file)
index 0000000..c2cffb8
--- /dev/null
+++ b/Vlv2TbltDevicePkg/PlatformInitPei/PlatformSsaInitPeim.c
@@ -0,0 +1,63 @@
+/** @file\r
+\r
+  Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+Module Name:\r
+\r
+\r
+  PlatformSsaInitPeim.c\r
+\r
+Abstract:\r
+\r
+\r
+--*/\r
+\r
+#include "PlatformEarlyInit.h"\r
+\r
+/**\r
+  Perform SSA related platform initialization.\r
+\r
+**/\r
+VOID\r
+PlatformSsaInit (\r
+  IN SYSTEM_CONFIGURATION        *SystemConfiguration,\r
+  IN CONST EFI_PEI_SERVICES          **PeiServices\r
+  )\r
+{\r
+\r
+  DEBUG ((EFI_D_ERROR, "PlatformSsaInit() - Start\n"));\r
+  DEBUG ((EFI_D_ERROR, "PlatformSsaInit() - SystemConfiguration->ISPDevSel 0x%x\n",SystemConfiguration->ISPDevSel));\r
+  if(SystemConfiguration->ISPDevSel == 0x02)\r
+  {\r
+    //\r
+    // Device 3 Interrupt Route\r
+    //\r
+    MmioWrite16 (\r
+      (ILB_BASE_ADDRESS + R_PCH_ILB_D3IR),\r
+      V_PCH_ILB_DXXIR_IAR_PIRQH   // For IUNIT\r
+    );\r
+    MmioRead16(ILB_BASE_ADDRESS + R_PCH_ILB_D3IR); // Read Posted Writes Register\r
+    DEBUG ((EFI_D_ERROR, "PlatformSsaInit() - Device 3 Interrupt Route Done\n"));\r
+  }\r
+\r
+  //\r
+  // Device 2 Interrupt Route\r
+  //\r
+  MmioWrite16 (\r
+    (ILB_BASE_ADDRESS + R_PCH_ILB_D2IR),\r
+    V_PCH_ILB_DXXIR_IAR_PIRQA   // For IGD\r
+  );\r
+  MmioRead16(ILB_BASE_ADDRESS + R_PCH_ILB_D2IR); // Read Posted Writes Register\r
+  DEBUG ((EFI_D_ERROR, "PlatformSsaInit() - Device 2 Interrupt Route Done\n"));\r
+\r
+  return;\r
+}\r

diff --git a/Vlv2TbltDevicePkg/PlatformInitPei/Recovery.c b/Vlv2TbltDevicePkg/PlatformInitPei/Recovery.c
new file mode 100644 (file)
index 0000000..a29d8c5
--- /dev/null
+++ b/Vlv2TbltDevicePkg/PlatformInitPei/Recovery.c
@@ -0,0 +1,366 @@
+/** @file\r
+\r
+  Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+Module Name:\r
+\r
+\r
+  Recovery.c\r
+\r
+Abstract:\r
+\r
+  Tiano PEIM to provide the platform recovery functionality.\r
+\r
+--*/\r
+\r
+#include "PlatformEarlyInit.h"\r
+\r
+#define PEI_FVMAIN_COMPACT_GUID \\r
+  {0x4A538818, 0x5AE0, 0x4eb2, 0xB2, 0xEB, 0x48, 0x8b, 0x23, 0x65, 0x70, 0x22};\r
+\r
+EFI_GUID FvMainCompactFileGuid = PEI_FVMAIN_COMPACT_GUID;\r
+\r
+//\r
+// Required Service\r
+//\r
+EFI_STATUS\r
+EFIAPI\r
+PlatformRecoveryModule (\r
+  IN CONST EFI_PEI_SERVICES                       **PeiServices,\r
+  IN EFI_PEI_RECOVERY_MODULE_PPI          *This\r
+  );\r
+\r
+//\r
+// Module globals\r
+//\r
+\r
+typedef struct {\r
+  EFI_GUID  CapsuleGuid;\r
+  UINT32    HeaderSize;\r
+  UINT32    Flags;\r
+  UINT32    CapsuleImageSize;\r
+  UINT32    SequenceNumber;\r
+  EFI_GUID  InstanceId;\r
+  UINT32    OffsetToSplitInformation;\r
+  UINT32    OffsetToCapsuleBody;\r
+  UINT32    OffsetToOemDefinedHeader;\r
+  UINT32    OffsetToAuthorInformation;\r
+  UINT32    OffsetToRevisionInformation;\r
+  UINT32    OffsetToShortDescription;\r
+  UINT32    OffsetToLongDescription;\r
+  UINT32    OffsetToApplicableDevices;\r
+} OLD_EFI_CAPSULE_HEADER;\r
+\r
+\r
+static EFI_PEI_RECOVERY_MODULE_PPI mRecoveryPpi = {\r
+  PlatformRecoveryModule\r
+};\r
+\r
+static EFI_PEI_PPI_DESCRIPTOR mRecoveryPpiList = {\r
+  (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),\r
+  &gEfiPeiRecoveryModulePpiGuid,\r
+  &mRecoveryPpi\r
+};\r
+\r
+/**\r
+  Provide the functionality of the Recovery Module.\r
+\r
+  @param PeiServices  General purpose services available to every PEIM.\r
+\r
+  @retval Status      EFI_SUCCESS if the interface could be successfully\r
+                      installed\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+PeimInitializeRecovery (\r
+  IN CONST EFI_PEI_SERVICES     **PeiServices\r
+  )\r
+{\r
+  EFI_STATUS  Status;\r
+\r
+  Status = (*PeiServices)->InstallPpi (\r
+                             PeiServices,\r
+                             &mRecoveryPpiList\r
+                             );\r
+\r
+  return Status;\r
+}\r
+\r
+/**\r
+  Provide the functionality of the Ea Recovery Module.\r
+\r
+  @param PeiServices         General purpose services available to every PEIM.\r
+  @param This                Pointer to PEI_RECOVERY_MODULE_INTERFACE.\r
+\r
+  @retval EFI_SUCCESS        If the interface could be successfully\r
+                             installed.\r
+  @retval EFI_UNSUPPORTED    Not supported.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+PlatformRecoveryModule (\r
+  IN CONST EFI_PEI_SERVICES               **PeiServices,\r
+  IN EFI_PEI_RECOVERY_MODULE_PPI          *This\r
+  )\r
+{\r
+  EFI_STATUS                            Status;\r
+  EFI_PEI_DEVICE_RECOVERY_MODULE_PPI    *DeviceRecoveryModule;\r
+  UINTN                                 NumberOfImageProviders;\r
+  BOOLEAN                               ProviderAvailable;\r
+  UINTN                                 NumberRecoveryCapsules;\r
+  UINTN                                 RecoveryCapsuleSize;\r
+  EFI_GUID                              DeviceId;\r
+  BOOLEAN                               ImageFound;\r
+  EFI_PHYSICAL_ADDRESS                  Address;\r
+  VOID                                  *Buffer;\r
+  OLD_EFI_CAPSULE_HEADER                *CapsuleHeader;\r
+  EFI_PEI_HOB_POINTERS                  Hob;\r
+  EFI_PEI_HOB_POINTERS                  HobOld;\r
+  EFI_HOB_CAPSULE_VOLUME                *CapsuleHob;\r
+  BOOLEAN                               HobUpdate;\r
+  EFI_FIRMWARE_VOLUME_HEADER            *FvHeader;\r
+  UINTN                                 Index;\r
+  BOOLEAN                                FoundFvMain;\r
+  BOOLEAN                                FoundCapsule;\r
+  static EFI_GUID mEfiCapsuleHeaderGuid = EFI_CAPSULE_GUID;\r
+  EFI_PEI_STALL_PPI                      *StallPpi;\r
+\r
+  (*PeiServices)->ReportStatusCode (\r
+                    PeiServices,\r
+                    EFI_PROGRESS_CODE,\r
+                    EFI_SOFTWARE_PEI_MODULE | EFI_SW_PEIM_PC_RECOVERY_BEGIN,\r
+                    0,\r
+                    NULL,\r
+                    NULL\r
+                    );\r
+\r
+  Status = (**PeiServices).LocatePpi (\r
+              PeiServices,\r
+              &gEfiPeiStallPpiGuid,\r
+              0,\r
+              NULL,\r
+              &StallPpi\r
+              );\r
+  ASSERT_EFI_ERROR (Status);\r
+\r
+  StallPpi->Stall(\r
+              PeiServices,\r
+              StallPpi,\r
+              5000000\r
+              );\r
+\r
+\r
+  Index = 0;\r
+\r
+  Status                  = EFI_SUCCESS;\r
+  HobUpdate               = FALSE;\r
+\r
+  ProviderAvailable       = TRUE;\r
+  ImageFound              = FALSE;\r
+  NumberOfImageProviders  = 0;\r
+\r
+  DeviceRecoveryModule    = NULL;\r
+\r
+  FoundCapsule = FALSE;\r
+  FoundFvMain = FALSE;\r
+\r
+  DEBUG ((EFI_D_ERROR | EFI_D_LOAD, "Recovery Entry\n"));\r
+\r
+  //\r
+  // Search the platform for some recovery capsule if the DXE IPL\r
+  // discovered a recovery condition and has requested a load.\r
+  //\r
+  while (ProviderAvailable == TRUE) {\r
+\r
+    Status = (*PeiServices)->LocatePpi (\r
+                               PeiServices,\r
+                               &gEfiPeiDeviceRecoveryModulePpiGuid,\r
+                               Index,\r
+                               NULL,\r
+                               &DeviceRecoveryModule\r
+                               );\r
+\r
+    if (!EFI_ERROR (Status)) {\r
+      DEBUG ((EFI_D_INFO | EFI_D_LOAD, "Device Recovery PPI located\n"));\r
+      NumberOfImageProviders++;\r
+\r
+      Status = DeviceRecoveryModule->GetNumberRecoveryCapsules (\r
+                                       (EFI_PEI_SERVICES**)PeiServices,\r
+                                       DeviceRecoveryModule,\r
+                                       &NumberRecoveryCapsules\r
+                                       );\r
+\r
+      DEBUG ((EFI_D_INFO | EFI_D_LOAD, "Number Of Recovery Capsules: %d\n", NumberRecoveryCapsules));\r
+\r
+      if (NumberRecoveryCapsules == 0) {\r
+        Index++;\r
+      } else {\r
+        break;\r
+      }\r
+    } else {\r
+      ProviderAvailable = FALSE;\r
+    }\r
+  }\r
+\r
+  //\r
+  // If there is an image provider, get the capsule ID\r
+  //\r
+  if (ProviderAvailable) {\r
+    RecoveryCapsuleSize = 0;\r
+\r
+    Status = DeviceRecoveryModule->GetRecoveryCapsuleInfo (\r
+                                    (EFI_PEI_SERVICES**)PeiServices,\r
+                                    DeviceRecoveryModule,\r
+                                    0,\r
+                                    &RecoveryCapsuleSize,\r
+                                    &DeviceId\r
+                                    );\r
+\r
+    if (EFI_ERROR (Status)) {\r
+      return Status;\r
+    }\r
+\r
+    DEBUG ((EFI_D_INFO | EFI_D_LOAD, "Recovery Capsule Size: %d\n", RecoveryCapsuleSize));\r
+\r
+    //\r
+    // Only support the 2 capsule types known\r
+    // Future enhancement is to rank-order the selection\r
+    //\r
+    if ((!CompareGuid (&DeviceId, &gRecoveryOnFatIdeDiskGuid)) &&\r
+        (!CompareGuid (&DeviceId, &gRecoveryOnFatFloppyDiskGuid)) &&\r
+        (!CompareGuid (&DeviceId, &gRecoveryOnDataCdGuid)) &&\r
+       (!CompareGuid (&DeviceId, &gRecoveryOnFatUsbDiskGuid))\r
+        ) {\r
+      return EFI_UNSUPPORTED;\r
+    }\r
+\r
+    Buffer  = NULL;\r
+    Status = (*PeiServices)->AllocatePages (\r
+                               PeiServices,\r
+                               EfiBootServicesCode,\r
+                               (RecoveryCapsuleSize - 1) / 0x1000 + 1,\r
+                               &Address\r
+                               );\r
+\r
+    DEBUG ((EFI_D_INFO | EFI_D_LOAD, "AllocatePage Returns: %r\n", Status));\r
+\r
+    if (EFI_ERROR(Status)) {\r
+      return Status;\r
+    }\r
+\r
+    Buffer = (UINT8 *) (UINTN) Address;\r
+\r
+    (*PeiServices)->ReportStatusCode (\r
+                      PeiServices,\r
+                      EFI_PROGRESS_CODE,\r
+                      EFI_SOFTWARE_PEI_MODULE | EFI_SW_PEIM_PC_CAPSULE_LOAD,\r
+                      0,\r
+                      NULL,\r
+                      NULL\r
+                      );\r
+\r
+    Status = DeviceRecoveryModule->LoadRecoveryCapsule (\r
+                                     (EFI_PEI_SERVICES**)PeiServices,\r
+                                     DeviceRecoveryModule,\r
+                                     0,\r
+                                     Buffer\r
+                                     );\r
+\r
+    DEBUG ((EFI_D_INFO | EFI_D_LOAD, "LoadRecoveryCapsule Returns: %r\n", Status));\r
+\r
+    if (EFI_ERROR (Status)) {\r
+      return Status;\r
+    }\r
+\r
+    //\r
+    // Update FV Hob if found\r
+    //\r
+    Status = (*PeiServices)->GetHobList (PeiServices, &Hob.Raw);\r
+    HobOld.Raw  = Hob.Raw;\r
+    while (!END_OF_HOB_LIST (Hob)) {\r
+      if (Hob.Header->HobType == EFI_HOB_TYPE_FV) {\r
+        DEBUG ((EFI_D_INFO | EFI_D_LOAD, "Hob FV Length: %x\n", Hob.FirmwareVolume->Length));\r
+        //\r
+        // BUGBUG Why is it a FV hob if it is greater than 0x50000?\r
+        //\r
+        if (Hob.FirmwareVolume->Length > 0x50000) {\r
+          HobUpdate = TRUE;\r
+          //\r
+          // This looks like the Hob we are interested in\r
+          //\r
+          DEBUG ((EFI_D_INFO | EFI_D_LOAD, "Hob Updated\n"));\r
+          Hob.FirmwareVolume->BaseAddress = (UINTN) Buffer;\r
+          Hob.FirmwareVolume->Length      = RecoveryCapsuleSize;\r
+        }\r
+      }\r
+      Hob.Raw = GET_NEXT_HOB (Hob);\r
+    }\r
+\r
+    FvHeader = (EFI_FIRMWARE_VOLUME_HEADER *)Buffer;\r
+    CapsuleHeader = (OLD_EFI_CAPSULE_HEADER *)Buffer;\r
+\r
+    //\r
+    // Check if top of file is a capsule\r
+    //\r
+    if (CompareGuid ((EFI_GUID *)CapsuleHeader, &mEfiCapsuleHeaderGuid)) {\r
+      FoundCapsule = TRUE;\r
+    } else if (FvHeader->Signature == EFI_FVH_SIGNATURE) {\r
+       //\r
+      // Assume the Firmware volume is a "FVMAIN" image\r
+      //\r
+      FoundFvMain = TRUE;\r
+    }\r
+\r
+    if (FoundFvMain) {\r
+      //\r
+      // build FV Hob if it is not built before\r
+      //\r
+      if (!HobUpdate) {\r
+        DEBUG ((EFI_D_INFO | EFI_D_LOAD, "FV Hob is not found, Build FV Hob then..\n"));\r
+\r
+       BuildFvHob (\r
+         (UINTN)FvHeader,\r
+         FvHeader->FvLength\r
+          );\r
+      }\r
+    }\r
+\r
+    if (FoundCapsule) {\r
+      //\r
+      // Build capsule hob\r
+      //\r
+      Status = (*PeiServices)->CreateHob (\r
+                                 PeiServices,\r
+                                 EFI_HOB_TYPE_CV,\r
+                                 sizeof (EFI_HOB_CAPSULE_VOLUME),\r
+                                 &CapsuleHob\r
+                                 );\r
+      if (EFI_ERROR (Status)) {\r
+        return Status;\r
+      }\r
+      CapsuleHob->BaseAddress = (UINT64)((UINTN)CapsuleHeader + (UINTN)CapsuleHeader->OffsetToCapsuleBody);\r
+      CapsuleHob->Length = (UINT64)((UINTN)CapsuleHeader->CapsuleImageSize -(UINTN)CapsuleHeader->OffsetToCapsuleBody);\r
+      (*PeiServices)->ReportStatusCode (\r
+                        PeiServices,\r
+                        EFI_PROGRESS_CODE,\r
+                        EFI_SOFTWARE_PEI_MODULE | EFI_SW_PEIM_PC_CAPSULE_START,\r
+                        0,\r
+                        NULL,\r
+                        NULL\r
+                        );\r
+    }\r
+  }\r
+  DEBUG ((EFI_D_INFO | EFI_D_LOAD, "Recovery Module Returning: %r\n", Status));\r
+  return Status;\r
+}\r

diff --git a/Vlv2TbltDevicePkg/PlatformInitPei/Stall.c b/Vlv2TbltDevicePkg/PlatformInitPei/Stall.c
new file mode 100644 (file)
index 0000000..46df63a
--- /dev/null
+++ b/Vlv2TbltDevicePkg/PlatformInitPei/Stall.c
@@ -0,0 +1,96 @@
+/** @file\r
+\r
+  Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+\r
+\r
+Module Name:\r
+\r
+  Stall.c\r
+\r
+Abstract:\r
+\r
+  Produce Stall Ppi.\r
+\r
+--*/\r
+\r
+\r
+#include "PlatformEarlyInit.h"\r
+\r
+\r
+/**\r
+\r
+  Waits for at least the given number of microseconds.\r
+\r
+  @param PeiServices     General purpose services available to every PEIM.\r
+  @param This            PPI instance structure.\r
+  @param Microseconds    Desired length of time to wait.\r
+\r
+  @retval EFI_SUCCESS    If the desired amount of time was passed.\r
+\r
+*/\r
+EFI_STATUS\r
+EFIAPI\r
+Stall (\r
+  IN CONST EFI_PEI_SERVICES   **PeiServices,\r
+  IN CONST EFI_PEI_STALL_PPI      *This,\r
+  IN UINTN              Microseconds\r
+  )\r
+{\r
+  UINTN   Ticks;\r
+  UINTN   Counts;\r
+  UINT32  CurrentTick;\r
+  UINT32  OriginalTick;\r
+  UINT32  RemainingTick;\r
+\r
+  if (Microseconds == 0) {\r
+    return EFI_SUCCESS;\r
+  }\r
+\r
+  OriginalTick = IoRead32 (ACPI_BASE_ADDRESS + R_PCH_ACPI_PM1_TMR);\r
+  OriginalTick &= (V_PCH_ACPI_PM1_TMR_MAX_VAL - 1);\r
+  CurrentTick = OriginalTick;\r
+\r
+  //\r
+  // The timer frequency is 3.579545MHz, so 1 ms corresponds to 3.58 clocks\r
+  //\r
+  Ticks = Microseconds * 358 / 100 + OriginalTick + 1;\r
+\r
+  //\r
+  // The loops needed for timer overflow\r
+  //\r
+  Counts = (UINTN)RShiftU64((UINT64)Ticks, 24);\r
+\r
+  //\r
+  // Remaining clocks within one loop\r
+  //\r
+  RemainingTick = Ticks & 0xFFFFFF;\r
+\r
+  //\r
+  // Do not intend to use TMROF_STS bit of register PM1_STS, because this add extra\r
+  // one I/O operation, and may generate SMI\r
+  //\r
+  while (Counts != 0) {\r
+    CurrentTick = IoRead32 (ACPI_BASE_ADDRESS + R_PCH_ACPI_PM1_TMR) & B_PCH_ACPI_PM1_TMR_VAL;\r
+    if (CurrentTick <= OriginalTick) {\r
+      Counts--;\r
+    }\r
+    OriginalTick = CurrentTick;\r
+  }\r
+\r
+  while ((RemainingTick > CurrentTick) && (OriginalTick <= CurrentTick)) {\r
+    OriginalTick  = CurrentTick;\r
+    CurrentTick   = IoRead32 (ACPI_BASE_ADDRESS + R_PCH_ACPI_PM1_TMR) & B_PCH_ACPI_PM1_TMR_VAL;\r
+  }\r
+\r
+  return EFI_SUCCESS;\r
+}\r

diff --git a/Vlv2TbltDevicePkg/PlatformPei/BootMode.c b/Vlv2TbltDevicePkg/PlatformPei/BootMode.c
new file mode 100644 (file)
index 0000000..4d933a0
--- /dev/null
+++ b/Vlv2TbltDevicePkg/PlatformPei/BootMode.c
@@ -0,0 +1,403 @@
+/** @file\r
+\r
+  Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+Module Name:\r
+\r
+\r
+  BootMode.c\r
+\r
+Abstract:\r
+\r
+  EFI PEIM to provide the platform support functionality on the Thurley.\r
+\r
+\r
+--*/\r
+#include "CommonHeader.h"\r
+#include "Platform.h"\r
+#include "PlatformBaseAddresses.h"\r
+#include "PchAccess.h"\r
+#include "PlatformBootMode.h"\r
+#include <Guid/SetupVariable.h>\r
+\r
+#include <Guid/BootState.h>\r
+\r
+//\r
+// Priority of our boot modes, highest priority first\r
+//\r
+EFI_BOOT_MODE mBootModePriority[] = {\r
+  BOOT_IN_RECOVERY_MODE,\r
+  BOOT_WITH_DEFAULT_SETTINGS,\r
+  BOOT_ON_FLASH_UPDATE,\r
+  BOOT_ON_S2_RESUME,\r
+  BOOT_ON_S3_RESUME,\r
+  BOOT_ON_S4_RESUME,\r
+  BOOT_WITH_MINIMAL_CONFIGURATION,\r
+  BOOT_ASSUMING_NO_CONFIGURATION_CHANGES,\r
+  BOOT_WITH_FULL_CONFIGURATION_PLUS_DIAGNOSTICS,\r
+  BOOT_WITH_FULL_CONFIGURATION,\r
+  BOOT_ON_S5_RESUME\r
+};\r
+\r
+EFI_PEI_NOTIFY_DESCRIPTOR mCapsuleNotifyList[1] = {\r
+  {\r
+    (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),\r
+    &gPeiCapsulePpiGuid,\r
+    CapsulePpiNotifyCallback\r
+  }\r
+};\r
+\r
+BOOLEAN\r
+GetSleepTypeAfterWakeup (\r
+  IN  CONST EFI_PEI_SERVICES          **PeiServices,\r
+  OUT UINT16                    *SleepType\r
+  );\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+CapsulePpiNotifyCallback (\r
+  IN EFI_PEI_SERVICES           **PeiServices,\r
+  IN EFI_PEI_NOTIFY_DESCRIPTOR  *NotifyDescriptor,\r
+  IN VOID                       *Ppi\r
+  )\r
+{\r
+  EFI_STATUS      Status;\r
+  EFI_BOOT_MODE   BootMode;\r
+  PEI_CAPSULE_PPI *Capsule;\r
+\r
+  Status = (*PeiServices)->GetBootMode((const EFI_PEI_SERVICES **)PeiServices, &BootMode);\r
+  ASSERT_EFI_ERROR (Status);\r
+\r
+  if (BootMode == BOOT_ON_S3_RESUME) {\r
+    //\r
+    // Determine if we're in capsule update mode\r
+    //\r
+    Status = (*PeiServices)->LocatePpi ((const EFI_PEI_SERVICES **)PeiServices,\r
+                                        &gPeiCapsulePpiGuid,\r
+                                        0,\r
+                                        NULL,\r
+                                        (VOID **)&Capsule\r
+                                        );\r
+\r
+    if (Status == EFI_SUCCESS) {\r
+      if (Capsule->CheckCapsuleUpdate ((EFI_PEI_SERVICES**)PeiServices) == EFI_SUCCESS) {\r
+        BootMode = BOOT_ON_FLASH_UPDATE;\r
+        Status = (*PeiServices)->SetBootMode((const EFI_PEI_SERVICES **)PeiServices, BootMode);\r
+        ASSERT_EFI_ERROR (Status);\r
+      }\r
+    }\r
+  }\r
+\r
+  return Status;\r
+}\r
+\r
+/**\r
+  Check CMOS register bit to determine if previous boot was successful\r
+\r
+  @param PeiServices    pointer to the PEI Service Table\r
+\r
+  @retval TRUE          - Previous Boot was success\r
+  @retval FALSE         - Previous Boot wasn't success\r
+\r
+**/\r
+BOOLEAN\r
+IsPreviousBootSuccessful(\r
+  IN CONST EFI_PEI_SERVICES   **PeiServices\r
+\r
+  )\r
+{\r
+  EFI_STATUS                      Status;\r
+  BOOLEAN                         BootState;\r
+  UINTN                           DataSize;\r
+  CHAR16                          VarName[] = BOOT_STATE_VARIABLE_NAME;\r
+  EFI_PEI_READ_ONLY_VARIABLE2_PPI *PeiVar;\r
+\r
+  Status = (**PeiServices).LocatePpi (\r
+                             PeiServices,\r
+                             &gEfiPeiReadOnlyVariable2PpiGuid,\r
+                             0,\r
+                             NULL,\r
+                                (void **)&PeiVar\r
+                             );\r
+  ASSERT_EFI_ERROR (Status);\r
+\r
+  //\r
+  // Get last Boot State Variable to confirm that it is not a first boot .\r
+  //\r
+\r
+  DataSize = sizeof (BOOLEAN);\r
+  Status = PeiVar->GetVariable (\r
+                     PeiVar,\r
+                     VarName,\r
+                     &gEfiBootStateGuid,\r
+                     NULL,\r
+                     &DataSize,\r
+                     &BootState\r
+                     );\r
+  if (EFI_ERROR (Status) || (BootState == TRUE)) {\r
+    return FALSE;\r
+  }\r
+\r
+  DEBUG ((EFI_D_INFO, "Previous boot cycle successfully completed handover to OS\n"));\r
+  return TRUE;\r
+}\r
+#ifdef NOCS_S3_SUPPORT\r
+EFI_STATUS\r
+UpdateBootMode (\r
+  IN CONST EFI_PEI_SERVICES     **PeiServices\r
+  )\r
+{\r
+  EFI_STATUS      Status;\r
+  EFI_BOOT_MODE   BootMode;\r
+  UINT16          SleepType;\r
+  CHAR16          *strBootMode;\r
+\r
+  Status = (*PeiServices)->GetBootMode(PeiServices, &BootMode);\r
+  ASSERT_EFI_ERROR (Status);\r
+  if (BootMode  == BOOT_IN_RECOVERY_MODE){\r
+    return Status;\r
+  }\r
+\r
+  //\r
+  // Let's assume things are OK if not told otherwise\r
+  //\r
+  BootMode = BOOT_WITH_FULL_CONFIGURATION;\r
+\r
+  if (GetSleepTypeAfterWakeup (PeiServices, &SleepType)) {\r
+    switch (SleepType) {\r
+      case V_PCH_ACPI_PM1_CNT_S3:\r
+        BootMode = BOOT_ON_S3_RESUME;\r
+        Status = (*PeiServices)->NotifyPpi (PeiServices, &mCapsuleNotifyList[0]);\r
+        ASSERT_EFI_ERROR (Status);\r
+        break;\r
+\r
+      case V_PCH_ACPI_PM1_CNT_S4:\r
+        BootMode = BOOT_ON_S4_RESUME;\r
+        break;\r
+\r
+      case V_PCH_ACPI_PM1_CNT_S5:\r
+        BootMode = BOOT_ON_S5_RESUME;\r
+        break;\r
+    } // switch (SleepType)\r
+  }\r
+\r
+  if (IsFastBootEnabled (PeiServices) && IsPreviousBootSuccessful (PeiServices)) {\r
+    DEBUG ((EFI_D_INFO, "Prioritizing Boot mode to BOOT_WITH_MINIMAL_CONFIGURATION\n"));\r
+    PrioritizeBootMode (&BootMode, BOOT_WITH_MINIMAL_CONFIGURATION);\r
+  }\r
+\r
+  switch (BootMode) {\r
+    case BOOT_WITH_FULL_CONFIGURATION:\r
+      strBootMode = L"BOOT_WITH_FULL_CONFIGURATION";\r
+      break;\r
+    case BOOT_WITH_MINIMAL_CONFIGURATION:\r
+      strBootMode = L"BOOT_WITH_MINIMAL_CONFIGURATION";\r
+      break;\r
+    case BOOT_ASSUMING_NO_CONFIGURATION_CHANGES:\r
+      strBootMode = L"BOOT_ASSUMING_NO_CONFIGURATION_CHANGES";\r
+      break;\r
+    case BOOT_WITH_FULL_CONFIGURATION_PLUS_DIAGNOSTICS:\r
+      strBootMode = L"BOOT_WITH_FULL_CONFIGURATION_PLUS_DIAGNOSTICS";\r
+      break;\r
+    case BOOT_WITH_DEFAULT_SETTINGS:\r
+      strBootMode = L"BOOT_WITH_DEFAULT_SETTINGS";\r
+      break;\r
+    case BOOT_ON_S4_RESUME:\r
+      strBootMode = L"BOOT_ON_S4_RESUME";\r
+      break;\r
+    case BOOT_ON_S5_RESUME:\r
+      strBootMode = L"BOOT_ON_S5_RESUME";\r
+      break;\r
+    case BOOT_ON_S2_RESUME:\r
+      strBootMode = L"BOOT_ON_S2_RESUME";\r
+      break;\r
+    case BOOT_ON_S3_RESUME:\r
+      strBootMode = L"BOOT_ON_S3_RESUME";\r
+\r
+      break;\r
+    case BOOT_ON_FLASH_UPDATE:\r
+      strBootMode = L"BOOT_ON_FLASH_UPDATE";\r
+      break;\r
+    case BOOT_IN_RECOVERY_MODE:\r
+      strBootMode = L"BOOT_IN_RECOVERY_MODE";\r
+      break;\r
+    default:\r
+      strBootMode = L"Unknown boot mode";\r
+  } // switch (BootMode)\r
+\r
+  DEBUG ((EFI_D_ERROR, "Setting BootMode to %s\n", strBootMode));\r
+  Status = (*PeiServices)->SetBootMode(PeiServices, BootMode);\r
+  ASSERT_EFI_ERROR (Status);\r
+\r
+  return Status;\r
+}\r
+#endif\r
+\r
+/**\r
+  Get sleep type after wakeup\r
+\r
+  @param PeiServices       Pointer to the PEI Service Table.\r
+  @param SleepType         Sleep type to be returned.\r
+\r
+  @retval TRUE              A wake event occured without power failure.\r
+  @retval FALSE             Power failure occured or not a wakeup.\r
+\r
+**/\r
+BOOLEAN\r
+GetSleepTypeAfterWakeup (\r
+  IN  CONST EFI_PEI_SERVICES          **PeiServices,\r
+  OUT UINT16                    *SleepType\r
+  )\r
+{\r
+  UINT16  Pm1Sts;\r
+  UINT16  Pm1Cnt;\r
+  UINT16  GenPmCon1;\r
+  //\r
+  // VLV BIOS Specification 0.6.2 - Section 18.4, "Power Failure Consideration"\r
+  //\r
+  // When the SUS_PWR_FLR bit is set, it indicates the SUS well power is lost.\r
+  // This bit is in the SUS Well and defaults to 1\92b1 based on RSMRST# assertion (not cleared by any type of reset).\r
+  // System BIOS should follow cold boot path if SUS_PWR_FLR (PBASE + 0x20[14]),\r
+  // GEN_RST_STS (PBASE + 0x20[9]) or PWRBTNOR_STS (ABASE + 0x00[11]) is set to 1\92b1\r
+  // regardless of the value in the SLP_TYP (ABASE + 0x04[12:10]) field.\r
+  //\r
+  GenPmCon1 = MmioRead16 (PMC_BASE_ADDRESS + R_PCH_PMC_GEN_PMCON_1);\r
+\r
+  //\r
+  // Read the ACPI registers\r
+  //\r
+  Pm1Sts  = IoRead16 (ACPI_BASE_ADDRESS + R_PCH_ACPI_PM1_STS);\r
+  Pm1Cnt  = IoRead16 (ACPI_BASE_ADDRESS + R_PCH_ACPI_PM1_CNT);\r
+\r
+  if ((GenPmCon1 & (B_PCH_PMC_GEN_PMCON_SUS_PWR_FLR | B_PCH_PMC_GEN_PMCON_GEN_RST_STS)) ||\r
+     (Pm1Sts & B_PCH_ACPI_PM1_STS_PRBTNOR)) {\r
+         //\r
+    // If power failure indicator, then don't attempt s3 resume.\r
+    // Clear PM1_CNT of S3 and set it to S5 as we just had a power failure, and memory has\r
+    // lost already.  This is to make sure no one will use PM1_CNT to check for S3 after\r
+    // power failure.\r
+         //\r
+    if ((Pm1Cnt & B_PCH_ACPI_PM1_CNT_SLP_TYP) == V_PCH_ACPI_PM1_CNT_S3) {\r
+      Pm1Cnt = ((Pm1Cnt & ~B_PCH_ACPI_PM1_CNT_SLP_TYP) | V_PCH_ACPI_PM1_CNT_S5);\r
+      IoWrite16 (ACPI_BASE_ADDRESS + R_PCH_ACPI_PM1_CNT, Pm1Cnt);\r
+    }\r
+         //\r
+    // Clear Wake Status (WAK_STS)\r
+    //\r
+  }\r
+  //\r
+  // Get sleep type if a wake event occurred and there is no power failure\r
+  //\r
+  if ((Pm1Cnt & B_PCH_ACPI_PM1_CNT_SLP_TYP) == V_PCH_ACPI_PM1_CNT_S3) {\r
+    *SleepType = Pm1Cnt & B_PCH_ACPI_PM1_CNT_SLP_TYP;\r
+    return TRUE;\r
+  } else if ((Pm1Cnt & B_PCH_ACPI_PM1_CNT_SLP_TYP) == V_PCH_ACPI_PM1_CNT_S4) {\r
+    *SleepType = Pm1Cnt & B_PCH_ACPI_PM1_CNT_SLP_TYP;\r
+    return TRUE;\r
+  }\r
+  return FALSE;\r
+}\r
+\r
+BOOLEAN\r
+EFIAPI\r
+IsFastBootEnabled (\r
+  IN CONST EFI_PEI_SERVICES           **PeiServices\r
+  )\r
+{\r
+  EFI_STATUS                      Status;\r
+  EFI_PEI_READ_ONLY_VARIABLE2_PPI *PeiReadOnlyVarPpi;\r
+  UINTN                           VarSize;\r
+  SYSTEM_CONFIGURATION            SystemConfiguration;\r
+  BOOLEAN                         FastBootEnabledStatus;\r
+\r
+  FastBootEnabledStatus = FALSE;\r
+  Status = (**PeiServices).LocatePpi (\r
+                             PeiServices,\r
+                             &gEfiPeiReadOnlyVariable2PpiGuid,\r
+                             0,\r
+                             NULL,\r
+                             (void **)&PeiReadOnlyVarPpi\r
+                             );\r
+  if (Status == EFI_SUCCESS) {\r
+    VarSize = sizeof (SYSTEM_CONFIGURATION);\r
+    Status = PeiReadOnlyVarPpi->GetVariable (\r
+                                  PeiReadOnlyVarPpi,\r
+                                  PLATFORM_SETUP_VARIABLE_NAME,\r
+                                  &gEfiSetupVariableGuid,\r
+                                  NULL,\r
+                                  &VarSize,\r
+                                  &SystemConfiguration\r
+                                  );\r
+    if (Status == EFI_SUCCESS) {\r
+      if (SystemConfiguration.FastBoot != 0) {\r
+        FastBootEnabledStatus = TRUE;\r
+      }\r
+    }\r
+  }\r
+\r
+  return FastBootEnabledStatus;\r
+}\r
+\r
+/**\r
+  Given the current boot mode, and a proposed new boot mode, determine\r
+  which has priority. If the new boot mode has higher priority, then\r
+  make it the current boot mode.\r
+\r
+  @param CurrentBootMode    pointer to current planned boot mode\r
+  @param NewBootMode        proposed boot mode\r
+\r
+  @retval EFI_NOT_FOUND      if either boot mode is not recognized\r
+  @retval EFI_SUCCESS        if both boot mode values were recognized and\r
+                             were processed.\r
+**/\r
+EFI_STATUS\r
+PrioritizeBootMode (\r
+  IN OUT EFI_BOOT_MODE    *CurrentBootMode,\r
+  IN EFI_BOOT_MODE        NewBootMode\r
+  )\r
+{\r
+  UINT32 CurrentIndex;\r
+  UINT32 NewIndex;\r
+\r
+  //\r
+  // Find the position of the current boot mode in our priority array\r
+  //\r
+  for ( CurrentIndex = 0;\r
+        CurrentIndex < sizeof (mBootModePriority) / sizeof (mBootModePriority[0]);\r
+        CurrentIndex++) {\r
+    if (mBootModePriority[CurrentIndex] == *CurrentBootMode) {\r
+      break;\r
+    }\r
+  }\r
+  if (CurrentIndex >= sizeof (mBootModePriority) / sizeof (mBootModePriority[0])) {\r
+    return EFI_NOT_FOUND;\r
+  }\r
+\r
+  //\r
+  // Find the position of the new boot mode in our priority array\r
+  //\r
+  for ( NewIndex = 0;\r
+        NewIndex < sizeof (mBootModePriority) / sizeof (mBootModePriority[0]);\r
+        NewIndex++) {\r
+    if (mBootModePriority[NewIndex] == NewBootMode) {\r
+      //\r
+      // If this new boot mode occurs before the current boot mode in the\r
+      // priority array, then take it.\r
+      //\r
+      if (NewIndex < CurrentIndex) {\r
+        *CurrentBootMode = NewBootMode;\r
+      }\r
+      return EFI_SUCCESS;\r
+    }\r
+  }\r
+  return EFI_NOT_FOUND;\r
+}\r

diff --git a/Vlv2TbltDevicePkg/PlatformPei/CommonHeader.h b/Vlv2TbltDevicePkg/PlatformPei/CommonHeader.h
new file mode 100644 (file)
index 0000000..19e26ac
--- /dev/null
+++ b/Vlv2TbltDevicePkg/PlatformPei/CommonHeader.h
@@ -0,0 +1,65 @@
+/*++\r
+\r
+  Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+**/\r
+\r
+#ifndef __COMMON_HEADER_H_\r
+#define __COMMON_HEADER_H_\r
+\r
+\r
+\r
+#include <FrameworkPei.h>\r
+\r
+#include <IndustryStandard/SmBus.h>\r
+#include <IndustryStandard/Pci22.h>\r
+#include <Ppi/AtaController.h>\r
+#include <Guid/Capsule.h>\r
+#include <Ppi/Cache.h>\r
+#include <Ppi/MasterBootMode.h>\r
+#include <Guid/MemoryTypeInformation.h>\r
+#include <Guid/RecoveryDevice.h>\r
+#include <Ppi/ReadOnlyVariable2.h>\r
+#include <Ppi/FvLoadFile.h>\r
+#include <Ppi/DeviceRecoveryModule.h>\r
+#include <Ppi/Capsule.h>\r
+#include <Ppi/Reset.h>\r
+#include <Ppi/Stall.h>\r
+#include <Ppi/BootInRecoveryMode.h>\r
+#include <Guid/FirmwareFileSystem2.h>\r
+#include <Ppi/MemoryDiscovered.h>\r
+#include <Ppi/RecoveryModule.h>\r
+#include <Ppi/Smbus2.h>\r
+#include <Ppi/FirmwareVolumeInfo.h>\r
+#include <Ppi/EndOfPeiPhase.h>\r
+#include <Library/DebugLib.h>\r
+#include <Library/PeimEntryPoint.h>\r
+#include <Library/BaseLib.h>\r
+#include <Library/PeiServicesLib.h>\r
+#include <Library/BaseMemoryLib.h>\r
+#include <Library/HobLib.h>\r
+#include <Library/PciCf8Lib.h>\r
+#include <Library/IoLib.h>\r
+#include <Library/PciLib.h>\r
+#include <Library/ReportStatusCodeLib.h>\r
+#include <Library/PcdLib.h>\r
+#include <Library/SmbusLib.h>\r
+#include <Library/TimerLib.h>\r
+#include <Library/PrintLib.h>\r
+#include <Library/ResetSystemLib.h>\r
+#include <Library/MemoryAllocationLib.h>\r
+#include <Library/PerformanceLib.h>\r
+#include <Library/CacheMaintenanceLib.h>\r
+#include <Library/MtrrLib.h>\r
+\r
+\r
+#endif\r

diff --git a/Vlv2TbltDevicePkg/PlatformPei/MemoryCallback.c b/Vlv2TbltDevicePkg/PlatformPei/MemoryCallback.c
new file mode 100644 (file)
index 0000000..82954d3
--- /dev/null
+++ b/Vlv2TbltDevicePkg/PlatformPei/MemoryCallback.c
@@ -0,0 +1,160 @@
+/** @file\r
+\r
+  Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+\r
+  This file includes a memory call back function notified when MRC is done,\r
+  following action is performed in this file,\r
+    1. ICH initialization after MRC.\r
+    2. SIO initialization.\r
+    3. Install ResetSystem and FinvFv PPI.\r
+    4. Set MTRR for PEI\r
+    5. Create FV HOB and Flash HOB\r
+\r
+\r
+**/\r
+\r
+\r
+#include "CommonHeader.h"\r
+#include "Platform.h"\r
+#include <Ppi/Cache.h>\r
+#include <Library/BaseCryptLib.h>\r
+#include <Library/PciLib.h>\r
+#include "VlvAccess.h"\r
+\r
+\r
+EFI_PEI_PPI_DESCRIPTOR  mPpiListRecoveryBootMode[] = {\r
+{ (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),\r
+  &gEfiPeiBootInRecoveryModePpiGuid,\r
+  NULL\r
+}\r
+};\r
+\r
+#if 0\r
+STATIC\r
+EFI_STATUS\r
+GetMemorySize (\r
+  IN  CONST EFI_PEI_SERVICES    **PeiServices,\r
+  OUT UINT64              *LowMemoryLength,\r
+  OUT UINT64              *HighMemoryLength\r
+  )\r
+{\r
+  EFI_STATUS              Status;\r
+  EFI_PEI_HOB_POINTERS    Hob;\r
+\r
+  *HighMemoryLength = 0;\r
+  *LowMemoryLength = 0x100000;\r
+  //\r
+  // Get the HOB list for processing\r
+  //\r
+  Status = (*PeiServices)->GetHobList (PeiServices, (void **)&Hob.Raw);\r
+  if (EFI_ERROR(Status)) {\r
+    return Status;\r
+  }\r
+\r
+  //\r
+  // Collect memory ranges\r
+  //\r
+  while (!END_OF_HOB_LIST (Hob)) {\r
+    if (Hob.Header->HobType == EFI_HOB_TYPE_RESOURCE_DESCRIPTOR) {\r
+      if (Hob.ResourceDescriptor->ResourceType == EFI_RESOURCE_SYSTEM_MEMORY) {\r
+        //\r
+        // Need memory above 1MB to be collected here\r
+        //\r
+        if (Hob.ResourceDescriptor->PhysicalStart >= 0x100000 &&\r
+            Hob.ResourceDescriptor->PhysicalStart < (EFI_PHYSICAL_ADDRESS) 0x100000000) {\r
+          *LowMemoryLength += (UINT64) (Hob.ResourceDescriptor->ResourceLength);\r
+        } else if (Hob.ResourceDescriptor->PhysicalStart >= (EFI_PHYSICAL_ADDRESS) 0x100000000) {\r
+          *HighMemoryLength += (UINT64) (Hob.ResourceDescriptor->ResourceLength);\r
+        }\r
+      }\r
+    }\r
+    Hob.Raw = GET_NEXT_HOB (Hob);\r
+  }\r
+\r
+  return EFI_SUCCESS;\r
+}\r
+\r
+#endif\r
+/**\r
+  This function will be called when MRC is done.\r
+\r
+  @param  PeiServices General purpose services available to every PEIM.\r
+  @param  NotifyDescriptor Information about the notify event..\r
+  @param  Ppi The notify context.\r
+\r
+  @retval EFI_SUCCESS If the function completed successfully.\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+MemoryDiscoveredPpiNotifyCallback (\r
+  IN EFI_PEI_SERVICES           **PeiServices,\r
+  IN EFI_PEI_NOTIFY_DESCRIPTOR  *NotifyDescriptor,\r
+  IN VOID                       *Ppi\r
+  )\r
+{\r
+\r
+  EFI_STATUS       Status;\r
+  EFI_BOOT_MODE    BootMode;\r
+  UINT32           Pages;\r
+  VOID*            Memory;\r
+  UINTN            Size;\r
+\r
+  //\r
+  // Allocate LM memory and configure PDM if enabled by user.\r
+  // ConfigureLM(PeiServices);\r
+  //\r
+  Status = (*PeiServices)->GetBootMode (\r
+                             (const EFI_PEI_SERVICES **)PeiServices,\r
+                             &BootMode\r
+                             );\r
+\r
+  if (BootMode != BOOT_ON_S3_RESUME) {\r
+    Size = (PcdGet32 (PcdFlashFvRecovery2Base) - PcdGet32 (PcdFlashFvMainBase)) + FixedPcdGet32(PcdFlashFvRecovery2Size);\r
+    Pages=  Size/0x1000;\r
+\r
+    Memory = AllocatePages ( Pages );\r
+    CopyMem(Memory , (VOID *) FixedPcdGet32(PcdFlashFvMainBase) , Size);\r
+\r
+    //\r
+    // We don't verify just load\r
+    //\r
+    PeiServicesInstallFvInfoPpi (\r
+      NULL,\r
+      (VOID *) ((UINTN) Memory + (PcdGet32 (PcdFlashFvRecovery2Base) - PcdGet32 (PcdFlashFvMainBase))),\r
+      PcdGet32 (PcdFlashFvRecovery2Size),\r
+      NULL,\r
+      NULL\r
+      );\r
+\r
+    PeiServicesInstallFvInfoPpi (\r
+      NULL,\r
+      (VOID *)  Memory,\r
+      PcdGet32 (PcdFlashFvMainSize),\r
+      NULL,\r
+      NULL\r
+      );\r
+\r
+  }\r
+\r
+  if (BootMode == BOOT_ON_S3_RESUME) {\r
+    PeiServicesInstallFvInfoPpi (\r
+    NULL,\r
+    (VOID *) (UINTN) (PcdGet32 (PcdFlashFvRecovery2Base)),\r
+    PcdGet32 (PcdFlashFvRecovery2Size),\r
+    NULL,\r
+    NULL\r
+    );\r
+  }\r
+\r
+  return EFI_SUCCESS;\r
+}\r

diff --git a/Vlv2TbltDevicePkg/PlatformPei/Platform.c b/Vlv2TbltDevicePkg/PlatformPei/Platform.c
new file mode 100644 (file)
index 0000000..1dab9ca
--- /dev/null
+++ b/Vlv2TbltDevicePkg/PlatformPei/Platform.c
@@ -0,0 +1,1063 @@
+/** @file\r
+\r
+  Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+\r
+Module Name:\r
+\r
+**/\r
+\r
+#include "CommonHeader.h"\r
+\r
+#include "Platform.h"\r
+#include <Library/PciCf8Lib.h>\r
+#include "PlatformBaseAddresses.h"\r
+#include "PchAccess.h"\r
+#include <Guid/PlatformInfo.h>\r
+#include "Platform.h"\r
+#include "PchCommonDefinitions.h"\r
+#include <Ppi/MfgMemoryTest.h>\r
+#include <Guid/SetupVariable.h>\r
+#include <Guid/Vlv2Variable.h>\r
+\r
+//\r
+// Start::Alpine Valley platform\r
+//\r
+enum {\r
+  SMBUS_READ_BYTE,\r
+  SMBUS_WRITE_BYTE,\r
+  SMBUS_READ_BLOCK,\r
+  SMBUS_WRITE_BLOCK\r
+};\r
+\r
+#define EC_BASE           0xE0000000\r
+\r
+//\r
+// DEVICE 0 (Memroy Controller Hub)\r
+//\r
+#define MC_BUS              0x00\r
+#define MC_DEV              0x00\r
+#define MC_FUN              0x00\r
+#define MC_DEV_FUN          (MC_DEV << 3)\r
+#define MC_BUS_DEV_FUN      ((MC_BUS << 8) + MC_DEV_FUN)\r
+\r
+//\r
+// SysCtl SMBus address and block size\r
+//\r
+#define AV_SC_SMBUS_ADDRESS            0x60\r
+#define AV_SC_BYTE_LEN                 1\r
+#define AV_SC_BLOCK_LEN                4\r
+#define AV_SC_SMBUS_WRCMD           1\r
+#define AV_SC_SMBUS_RDCMD           0\r
+\r
+//\r
+// SysCtl registers offset\r
+//\r
+#define AV_SC_REG_PLATFORM_ID               24  // 0x18\r
+#define AV_SC_REG_BOARD_ID                  28  // 0x1C\r
+#define AV_SC_REG_FAB_ID                    32  // 0x20\r
+#define AV_SC_REG_ECO_ID                    68  // 0x44\r
+#define AV_SC_REG_DDR_DAUGHTER_CARD_ID      144 // 0x90\r
+#define AV_SC_REG_SODIMM_CONFIG             36\r
+\r
+//\r
+// ID values\r
+//\r
+#define AV_SC_PLATFORM_ID_TABLET   0\r
+#define AV_SC_PLATFORM_ID_NETBOOK  2\r
+#define AV_SC_PLATFORM_ID_INTERPOSER 3 // Configuration TBD\r
+#define AV_SC_BOARD_ID_AV_SVP      1492\r
+\r
+#define BUS_TRIES                 3       // How many times to retry on Bus Errors\r
+\r
+#define GTT_SIZE_1MB        1\r
+#define GTT_SIZE_2MB        2\r
+\r
+#define PciCfg16Read( PciExpressBase, Bus, Device, Function, Register ) \\r
+  MmioRead16(PciExpressBase + \\r
+    (UINTN)(Bus << 20) + \\r
+    (UINTN)(Device << 15) + \\r
+    (UINTN)(Function << 12) + \\r
+    (UINTN)(Register))\r
+#define PciCfg16Write( PciExpressBase, Bus, Device, Function, Register, Data ) \\r
+    MmioWrite16(PciExpressBase + \\r
+      (UINTN)(Bus << 20) + \\r
+      (UINTN)(Device << 15) + \\r
+      (UINTN)(Function << 12) + \\r
+      (UINTN)(Register), \\r
+      (UINT16)Data)\r
+\r
+\r
+//\r
+//Memory Test Manufacturing mode\r
+//\r
+UINT32 DataPatternForMemoryTest[] = {\r
+    0x55555555, 0xAAAAAAAA, 0x55555510, 0x555555EF, 0x55555510, 0x555555EF, 0x55555510, 0x555555EF,\r
+    0x55555555, 0xAAAAAAAA, 0x55551055, 0x5555EF55, 0x55551055, 0x5555EF55, 0x55551055, 0x5555EF55,\r
+    0x55555555, 0xAAAAAAAA, 0x55105555, 0x55EF5555, 0x55105555, 0x55EF5555, 0x55105555, 0x55EF5555,\r
+    0x55555555, 0xAAAAAAAA, 0x10555555, 0xEF555555, 0x10555555, 0xEF555555, 0x10555555, 0xEF555555\r
+};\r
+#define DATA_PATTERN_ARRAY_SIZE (sizeof(DataPatternForMemoryTest) / sizeof(UINT32))\r
+\r
+//\r
+//Memory Test Manufacturing mode\r
+//\r
+//\r
+// The global indicator, the FvFileLoader callback will modify it to TRUE after loading PEIM into memory\r
+//\r
+BOOLEAN ImageInMemory = FALSE;\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+Stall (\r
+  IN CONST EFI_PEI_SERVICES   **PeiServices,\r
+  IN CONST EFI_PEI_STALL_PPI      *This,\r
+  IN UINTN              Microseconds\r
+  );\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+MfgMemoryTest (\r
+  IN  CONST EFI_PEI_SERVICES                   **PeiServices,\r
+  IN  PEI_MFG_MEMORY_TEST_PPI           *This,\r
+  IN  UINT32                             BeginAddress,\r
+  IN  UINT32                             MemoryLength\r
+  );\r
+\r
+static EFI_PEI_STALL_PPI  mStallPpi = {\r
+  PEI_STALL_RESOLUTION,\r
+  Stall\r
+};\r
+\r
+static PEI_MFG_MEMORY_TEST_PPI mPeiMfgMemoryTestPpi = {\r
+  MfgMemoryTest\r
+};\r
+\r
+static EFI_PEI_PPI_DESCRIPTOR mInstallStallPpi[] = {\r
+  {\r
+  EFI_PEI_PPI_DESCRIPTOR_PPI,\r
+  &gEfiPeiStallPpiGuid,\r
+  &mStallPpi\r
+  },\r
+  {\r
+    EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,\r
+    &gPeiMfgMemoryTestPpiGuid,\r
+    &mPeiMfgMemoryTestPpi\r
+  }\r
+ };\r
+\r
+EFI_PEI_NOTIFY_DESCRIPTOR mMemoryDiscoveredNotifyList[1] = {\r
+  {\r
+    (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),\r
+    &gEfiPeiMemoryDiscoveredPpiGuid,\r
+    MemoryDiscoveredPpiNotifyCallback\r
+  }\r
+};\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+InstallMonoStatusCode (\r
+  IN EFI_FFS_FILE_HEADER       *FfsHeader,\r
+  IN CONST EFI_PEI_SERVICES          **PeiServices\r
+  );\r
+\r
+\r
+EFI_STATUS\r
+ReadPlatformIds (\r
+  IN CONST EFI_PEI_SERVICES             **PeiServices,\r
+  IN OUT EFI_PLATFORM_INFO_HOB          *PlatformInfoHob\r
+  );\r
+\r
+//\r
+// Start::Alpine Valley platform\r
+//\r
+EFI_STATUS\r
+PeiSmbusExec (\r
+  UINT16 SmbusBase,\r
+  UINT8 SlvAddr,\r
+  UINT8 Operation,\r
+  UINT8 Offset,\r
+  UINT8 *Length,\r
+  UINT8 *Buffer\r
+  );\r
+\r
+/**\r
+  This routine attempts to acquire the SMBus\r
+\r
+  @retval FAILURE as failed\r
+  @retval SUCCESS as passed\r
+\r
+**/\r
+EFI_STATUS\r
+AcquireBus (\r
+    UINT16     SmbusBase\r
+  )\r
+{\r
+  UINT8 StsReg;\r
+\r
+  StsReg  = 0;\r
+  StsReg  = (UINT8)IoRead8(SmbusBase + R_PCH_SMBUS_HSTS);\r
+  if (StsReg & B_PCH_SMBUS_IUS) {\r
+    return EFI_DEVICE_ERROR;\r
+  } else if (StsReg & B_PCH_SMBUS_HBSY) {\r
+    //\r
+    // Clear Status Register and exit\r
+    //\r
+    // Wait for HSTS.HBSY to be clear\r
+         //\r
+    do { StsReg = (UINT8) IoRead8(SmbusBase+R_PCH_SMBUS_HSTS); } while ((StsReg & B_PCH_SMBUS_HBSY) != 0);\r
+\r
+         //\r
+    // Clear all status bits\r
+         //\r
+    IoWrite8(SmbusBase+R_PCH_SMBUS_HSTS, 0xFE);\r
+    return EFI_SUCCESS;\r
+  } else {\r
+    //\r
+    // Clear out any odd status information (Will Not Clear In Use)\r
+    //\r
+    IoWrite8(SmbusBase+R_PCH_SMBUS_HSTS, StsReg);\r
+    return EFI_SUCCESS;\r
+  }\r
+}\r
+//\r
+// End::Alpine Valley platform\r
+//\r
+\r
+/**\r
+  This function checks the memory range in PEI.\r
+\r
+  @param  PeiServices     Pointer to PEI Services.\r
+  @param  This            Pei memory test PPI pointer.\r
+  @param  BeginAddress    Beginning of the memory address to be checked.\r
+  @param  MemoryLength    Bytes of memory range to be checked.\r
+  @param  Operation       Type of memory check operation to be performed.\r
+  @param  ErrorAddress    Return the address of the error memory address.\r
+\r
+  @retval  EFI_SUCCESS         The operation completed successfully.\r
+  @retval  EFI_DEVICE_ERROR    Memory test failed. It's not safe to use this range of memory.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+MfgMemoryTest (\r
+  IN  CONST EFI_PEI_SERVICES                   **PeiServices,\r
+  IN  PEI_MFG_MEMORY_TEST_PPI           *This,\r
+  IN  UINT32                             BeginAddress,\r
+  IN  UINT32                             MemoryLength\r
+  )\r
+{\r
+  UINT32 i;\r
+  UINT32 memAddr;\r
+  UINT32 readData;\r
+  UINT32 xorData;\r
+  UINT32 TestFlag = 0;\r
+  memAddr = BeginAddress;\r
+\r
+  //\r
+  //Output Message for MFG\r
+  //\r
+  DEBUG ((EFI_D_ERROR, "MFGMODE SET\n"));\r
+\r
+  //\r
+  //Writting the pattern in defined location.\r
+  //\r
+  while (memAddr < (BeginAddress+MemoryLength)) {\r
+    for (i = 0; i < DATA_PATTERN_ARRAY_SIZE; i++) {\r
+      if (memAddr > (BeginAddress+MemoryLength -4)) {\r
+        memAddr = memAddr + 4;\r
+        break;\r
+      }\r
+      *((volatile UINT32*) memAddr) = DataPatternForMemoryTest[i];\r
+      memAddr = memAddr + 4;\r
+    }\r
+  }\r
+\r
+  //\r
+  //Verify the pattern.\r
+  //\r
+  memAddr = BeginAddress;\r
+  while (memAddr < (BeginAddress+MemoryLength)) {\r
+  for (i = 0; i < DATA_PATTERN_ARRAY_SIZE; i++) {\r
+    if (memAddr > (BeginAddress+MemoryLength -4)) {\r
+      memAddr = memAddr + 4;\r
+      break;\r
+    }\r
+    readData = *((volatile UINT32*) memAddr);\r
+    xorData = readData ^ DataPatternForMemoryTest[i];\r
+\r
+         //\r
+    // If xorData is nonzero, this particular memAddr has a failure.\r
+         //\r
+    if (xorData != 0x00000000) {\r
+      DEBUG ((EFI_D_ERROR, "Expected value....: %x\n", DataPatternForMemoryTest[i]));\r
+      DEBUG ((EFI_D_ERROR, "ReadData value....: %x\n", readData));\r
+      DEBUG ((EFI_D_ERROR, "Pattern failure at....: %x\n", memAddr));\r
+      TestFlag = 1;\r
+    }\r
+    memAddr = memAddr + 4;\r
+    }\r
+  }\r
+  if (TestFlag) {\r
+    return EFI_DEVICE_ERROR;\r
+  }\r
+\r
+  //\r
+  //Output Message for MFG\r
+  //\r
+  DEBUG ((EFI_D_ERROR, "MFGMODE MEMORY TEST PASSED\n"));\r
+  return EFI_SUCCESS;\r
+}\r
+\r
+BOOLEAN\r
+IsRtcUipAlwaysSet (\r
+  IN CONST EFI_PEI_SERVICES       **PeiServices\r
+  )\r
+{\r
+\r
+  EFI_PEI_STALL_PPI *StallPpi;\r
+  UINTN             Count;\r
+\r
+  (**PeiServices).LocatePpi (PeiServices, &gEfiPeiStallPpiGuid, 0, NULL, (void **)&StallPpi);\r
+\r
+  for (Count = 0; Count < 500; Count++) { // Maximum waiting approximates to 1.5 seconds (= 3 msec * 500)\r
+    IoWrite8 (R_PCH_RTC_INDEX2, R_PCH_RTC_REGISTERA);\r
+    if ((IoRead8 (R_PCH_RTC_TARGET2) & B_PCH_RTC_REGISTERA_UIP) == 0) {\r
+      return FALSE;\r
+    }\r
+\r
+    StallPpi->Stall (PeiServices, StallPpi, 3000);\r
+  }\r
+\r
+  return TRUE;\r
+}\r
+\r
+EFI_STATUS\r
+RtcPowerFailureHandler (\r
+  IN CONST EFI_PEI_SERVICES       **PeiServices\r
+  )\r
+{\r
+\r
+  UINT16          DataUint16;\r
+  UINT8           DataUint8;\r
+  BOOLEAN         RtcUipIsAlwaysSet;\r
+  DataUint16        = MmioRead16 (PMC_BASE_ADDRESS + R_PCH_PMC_GEN_PMCON_1);\r
+  RtcUipIsAlwaysSet = IsRtcUipAlwaysSet (PeiServices);\r
+  if ((DataUint16 & B_PCH_PMC_GEN_PMCON_RTC_PWR_STS) || (RtcUipIsAlwaysSet)) {\r
+    //\r
+    // Execute the sequence below. This will ensure that the RTC state machine has been initialized.\r
+    //\r
+    // Step 1.\r
+    // BIOS clears this bit by writing a '0' to it.\r
+    //\r
+    if (DataUint16 & B_PCH_PMC_GEN_PMCON_RTC_PWR_STS) {\r
+      //\r
+      // Set to invalid date in order to reset the time to\r
+      // BIOS build time later in the boot (SBRUN.c file).\r
+      //\r
+      IoWrite8 (R_PCH_RTC_INDEX2, R_PCH_RTC_YEAR);\r
+      IoWrite8 (R_PCH_RTC_TARGET2, 0x0FF);\r
+      IoWrite8 (R_PCH_RTC_INDEX2, R_PCH_RTC_MONTH);\r
+      IoWrite8 (R_PCH_RTC_TARGET2, 0x0FF);\r
+      IoWrite8 (R_PCH_RTC_INDEX2, R_PCH_RTC_DAYOFMONTH);\r
+      IoWrite8 (R_PCH_RTC_TARGET2, 0x0FF);\r
+      IoWrite8 (R_PCH_RTC_INDEX2, R_PCH_RTC_DAYOFWEEK);\r
+      IoWrite8 (R_PCH_RTC_TARGET2, 0x0FF);\r
+\r
+      IoWrite8 (R_PCH_RTC_INDEX2, R_PCH_RTC_SECONDSALARM);\r
+      IoWrite8 (R_PCH_RTC_TARGET2, 0x00);\r
+      IoWrite8 (R_PCH_RTC_INDEX2, R_PCH_RTC_MINUTESALARM);\r
+      IoWrite8 (R_PCH_RTC_TARGET2, 0x00);\r
+      IoWrite8 (R_PCH_RTC_INDEX2, R_PCH_RTC_HOURSALARM);\r
+      IoWrite8 (R_PCH_RTC_TARGET2, 0x00);\r
+    }\r
+\r
+    //\r
+    // Step 2.\r
+    // Set RTC Register 0Ah[6:4] to '110' or '111'.\r
+    //\r
+    IoWrite8 (R_PCH_RTC_INDEX2, R_PCH_RTC_REGISTERA);\r
+    IoWrite8 (R_PCH_RTC_TARGET2, (V_PCH_RTC_REGISTERA_DV_DIV_RST1 | V_PCH_RTC_REGISTERA_RS_976P5US));\r
+\r
+    //\r
+    // Step 3.\r
+    // Set RTC Register 0Bh[7].\r
+    //\r
+    IoWrite8 (R_PCH_RTC_INDEX2, R_PCH_RTC_REGISTERB);\r
+    DataUint8 = (IoRead8 (R_PCH_RTC_TARGET2) | B_PCH_RTC_REGISTERB_SET);\r
+    IoWrite8 (R_PCH_RTC_INDEX2, R_PCH_RTC_REGISTERB);\r
+    IoWrite8 (R_PCH_RTC_TARGET2, DataUint8);\r
+\r
+    //\r
+    // Step 4.\r
+    // Set RTC Register 0Ah[6:4] to '010'.\r
+    //\r
+    IoWrite8 (R_PCH_RTC_INDEX2, R_PCH_RTC_REGISTERA);\r
+    IoWrite8 (R_PCH_RTC_TARGET2, (V_PCH_RTC_REGISTERA_DV_NORM_OP | V_PCH_RTC_REGISTERA_RS_976P5US));\r
+\r
+    //\r
+    // Step 5.\r
+    // Clear RTC Register 0Bh[7].\r
+    //\r
+    IoWrite8 (R_PCH_RTC_INDEX2, R_PCH_RTC_REGISTERB);\r
+    DataUint8 = (IoRead8 (R_PCH_RTC_TARGET2) & (UINT8)~B_PCH_RTC_REGISTERB_SET);\r
+    IoWrite8 (R_PCH_RTC_INDEX2, R_PCH_RTC_REGISTERB);\r
+    IoWrite8 (R_PCH_RTC_TARGET2, DataUint8);\r
+  }\r
+\r
+  return EFI_SUCCESS;\r
+}\r
+\r
+\r
+VOID\r
+PchBaseInit (\r
+  VOID\r
+  )\r
+{\r
+  //\r
+  // Program ACPI Power Management I/O Space Base Address\r
+  //\r
+  MmioWrite16 (\r
+    MmPciAddress (0,\r
+      DEFAULT_PCI_BUS_NUMBER_PCH,\r
+      PCI_DEVICE_NUMBER_PCH_LPC,\r
+      PCI_FUNCTION_NUMBER_PCH_LPC,\r
+      R_PCH_LPC_ACPI_BASE\r
+    ),\r
+    (UINT16)((ACPI_BASE_ADDRESS & B_PCH_LPC_ACPI_BASE_BAR) | B_PCH_LPC_ACPI_BASE_EN)\r
+  );\r
+\r
+  //\r
+  // Program GPIO Base Address\r
+  //\r
+  MmioWrite16 (\r
+    MmPciAddress (0,\r
+      DEFAULT_PCI_BUS_NUMBER_PCH,\r
+      PCI_DEVICE_NUMBER_PCH_LPC,\r
+      PCI_FUNCTION_NUMBER_PCH_LPC,\r
+      R_PCH_LPC_GPIO_BASE\r
+    ),\r
+    (UINT16)((GPIO_BASE_ADDRESS & B_PCH_LPC_GPIO_BASE_BAR) | B_PCH_LPC_GPIO_BASE_EN)\r
+  );\r
+\r
+  //\r
+  // Set PMC Base Address\r
+  //\r
+  MmioWrite32 (\r
+    MmPciAddress (0,\r
+      DEFAULT_PCI_BUS_NUMBER_PCH,\r
+      PCI_DEVICE_NUMBER_PCH_LPC,\r
+      PCI_FUNCTION_NUMBER_PCH_LPC,\r
+      R_PCH_LPC_PMC_BASE\r
+    ),\r
+    (UINT32)((PMC_BASE_ADDRESS & B_PCH_LPC_PMC_BASE_BAR) | B_PCH_LPC_PMC_BASE_EN)\r
+  );\r
+\r
+  //\r
+  // Set IO Base Address\r
+  //\r
+  MmioWrite32 (\r
+    MmPciAddress (0,\r
+      DEFAULT_PCI_BUS_NUMBER_PCH,\r
+      PCI_DEVICE_NUMBER_PCH_LPC,\r
+      PCI_FUNCTION_NUMBER_PCH_LPC,\r
+      R_PCH_LPC_IO_BASE\r
+    ),\r
+    (UINT32)((IO_BASE_ADDRESS & B_PCH_LPC_IO_BASE_BAR) | B_PCH_LPC_IO_BASE_EN)\r
+  );\r
+\r
+  //\r
+  // Set ILB Base Address\r
+  //\r
+  MmioWrite32 (\r
+    MmPciAddress (0,\r
+      DEFAULT_PCI_BUS_NUMBER_PCH,\r
+      PCI_DEVICE_NUMBER_PCH_LPC,\r
+      PCI_FUNCTION_NUMBER_PCH_LPC,\r
+      R_PCH_LPC_ILB_BASE\r
+    ),\r
+    (UINT32)((ILB_BASE_ADDRESS & B_PCH_LPC_ILB_BASE_BAR) | B_PCH_LPC_ILB_BASE_EN)\r
+  );\r
+\r
+  //\r
+  // Set PUnit Base Address\r
+  //\r
+  MmioWrite32 (\r
+    MmPciAddress (0,\r
+      DEFAULT_PCI_BUS_NUMBER_PCH,\r
+      PCI_DEVICE_NUMBER_PCH_LPC,\r
+      PCI_FUNCTION_NUMBER_PCH_LPC,\r
+      R_PCH_LPC_PUNIT_BASE\r
+    ),\r
+    (UINT32)((PUNIT_BASE_ADDRESS & B_PCH_LPC_PUNIT_BASE_BAR) | B_PCH_LPC_PUNIT_BASE_EN)\r
+  );\r
+\r
+  //\r
+  // Set SPI Base Address\r
+  //\r
+  MmioWrite32 (\r
+    MmPciAddress (0,\r
+      DEFAULT_PCI_BUS_NUMBER_PCH,\r
+      PCI_DEVICE_NUMBER_PCH_LPC,\r
+      PCI_FUNCTION_NUMBER_PCH_LPC,\r
+      R_PCH_LPC_SPI_BASE\r
+    ),\r
+    (UINT32)((SPI_BASE_ADDRESS & B_PCH_LPC_SPI_BASE_BAR) | B_PCH_LPC_SPI_BASE_EN)\r
+  );\r
+\r
+  //\r
+  // Set Root Complex Base Address\r
+  //\r
+  MmioWrite32 (\r
+    MmPciAddress (0,\r
+      DEFAULT_PCI_BUS_NUMBER_PCH,\r
+      PCI_DEVICE_NUMBER_PCH_LPC,\r
+      PCI_FUNCTION_NUMBER_PCH_LPC,\r
+      R_PCH_LPC_RCBA\r
+    ),\r
+    (UINT32)((RCBA_BASE_ADDRESS & B_PCH_LPC_RCBA_BAR) | B_PCH_LPC_RCBA_EN)\r
+  );\r
+\r
+  //\r
+  // Set MPHY Base Address\r
+  //\r
+  MmioWrite32 (\r
+    MmPciAddress (0,\r
+      DEFAULT_PCI_BUS_NUMBER_PCH,\r
+      PCI_DEVICE_NUMBER_PCH_LPC,\r
+      PCI_FUNCTION_NUMBER_PCH_LPC,\r
+      R_PCH_LPC_MPHY_BASE\r
+    ),\r
+    (UINT32)((MPHY_BASE_ADDRESS & B_PCH_LPC_MPHY_BASE_BAR) | B_PCH_LPC_MPHY_BASE_EN)\r
+  );\r
+  MmioWrite16 (\r
+    MmPciAddress (0,\r
+      DEFAULT_PCI_BUS_NUMBER_PCH,\r
+      PCI_DEVICE_NUMBER_PCH_SMBUS,\r
+      PCI_FUNCTION_NUMBER_PCH_SMBUS,\r
+      R_PCH_SMBUS_BASE\r
+    ),\r
+    (UINT16)(SMBUS_BASE_ADDRESS & B_PCH_SMBUS_BASE_BAR)\r
+  );\r
+\r
+  MmioOr8 (\r
+    MmPciAddress (0,\r
+      DEFAULT_PCI_BUS_NUMBER_PCH,\r
+      PCI_DEVICE_NUMBER_PCH_SMBUS,\r
+      PCI_FUNCTION_NUMBER_PCH_SMBUS,\r
+      R_PCH_SMBUS_PCICMD\r
+    ),\r
+    B_PCH_SMBUS_PCICMD_IOSE\r
+  );\r
+\r
+}\r
+\r
+/**\r
+  This is the entrypoint of PEIM\r
+\r
+  @param  FileHandle  Handle of the file being invoked.\r
+  @param  PeiServices Describes the list of possible PEI Services.\r
+\r
+  @retval EFI_SUCCESS if it completed successfully.\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+PeiInitPlatform (\r
+  IN       EFI_PEI_FILE_HANDLE  FileHandle,\r
+  IN CONST EFI_PEI_SERVICES     **PeiServices\r
+  )\r
+{\r
+  UINTN                            SmbusRegBase;\r
+  EFI_PLATFORM_INFO_HOB            PlatformInfo;\r
+  EFI_STATUS                       Status= EFI_SUCCESS;\r
+  EFI_PEI_READ_ONLY_VARIABLE2_PPI  *Variable = NULL;\r
+  UINTN                            VariableSize;\r
+  SYSTEM_CONFIGURATION             SystemConfiguration;\r
+  UINT32                           GGC = 0;\r
+\r
+  EFI_PEI_PPI_DESCRIPTOR          *mVlvMmioPolicyPpiDesc;\r
+  VLV_MMIO_POLICY_PPI             *mVlvMmioPolicyPpi;\r
+\r
+  ZeroMem (&PlatformInfo, sizeof(PlatformInfo));\r
+\r
+  Status =  InstallMonoStatusCode(FileHandle, PeiServices);\r
+  ASSERT_EFI_ERROR (Status);\r
+\r
+\r
+  //\r
+  // Initialize Stall PPIs\r
+  //\r
+  Status = (*PeiServices)->InstallPpi (PeiServices, &mInstallStallPpi[0]);\r
+  ASSERT_EFI_ERROR (Status);\r
+\r
+  Status = (*PeiServices)->NotifyPpi (PeiServices, &mMemoryDiscoveredNotifyList[0]);\r
+  ASSERT_EFI_ERROR (Status);\r
+  SmbusRegBase = PchPciDeviceMmBase (\r
+                   DEFAULT_PCI_BUS_NUMBER_PCH,\r
+                   PCI_DEVICE_NUMBER_PCH_SMBUS,\r
+                   PCI_FUNCTION_NUMBER_PCH_SMBUS\r
+                   );\r
+  //\r
+  // Since PEI has no PCI enumerator, set the BAR & I/O space enable ourselves\r
+  //\r
+  MmioAndThenOr32 (SmbusRegBase + R_PCH_SMBUS_BASE, B_PCH_SMBUS_BASE_BAR, SMBUS_BASE_ADDRESS);\r
+\r
+  MmioOr8 (SmbusRegBase + R_PCH_SMBUS_PCICMD, B_PCH_SMBUS_PCICMD_IOSE);\r
+\r
+  PchBaseInit();\r
+\r
+  //\r
+  //Todo: confirm if we need program 8254\r
+  //\r
+  // Setting 8254\r
+  // Program timer 1 as refresh timer\r
+  //\r
+  IoWrite8 (0x43, 0x54);\r
+  IoWrite8 (0x41, 0x12);\r
+\r
+  //\r
+  // RTC power failure handling\r
+  //\r
+  RtcPowerFailureHandler (PeiServices);\r
+\r
+\r
+  PchMmPci32( 0, 0, 2, 0, 0x50) = 0x210;\r
+\r
+  VariableSize = sizeof (SYSTEM_CONFIGURATION);\r
+  ZeroMem (&SystemConfiguration, VariableSize);\r
+\r
+  //\r
+  // Obtain variable services\r
+  //\r
+  Status = (*PeiServices)->LocatePpi(\r
+                             PeiServices,\r
+                             &gEfiPeiReadOnlyVariable2PpiGuid,\r
+                             0,\r
+                             NULL,\r
+                             (void **)&Variable\r
+                             );\r
+  ASSERT_EFI_ERROR(Status);\r
+  Status = Variable->GetVariable (\r
+                       Variable,\r
+                       L"Setup",\r
+                       &gEfiSetupVariableGuid,\r
+                       NULL,\r
+                       &VariableSize,\r
+                       &SystemConfiguration\r
+                                          );\r
+  ASSERT_EFI_ERROR(Status);\r
+  if (EFI_ERROR (Status)) {\r
+    GGC = ((2 << 3) | 0x200);\r
+    PciCfg16Write(EC_BASE, 0, 2, 0, 0x50, GGC);\r
+    GGC = PciCfg16Read(EC_BASE, 0, 2, 0, 0x50);\r
+    DEBUG((EFI_D_INFO , "GGC: 0x%08x GMSsize:0x%08x\n", GGC, (GGC & (BIT7|BIT6|BIT5|BIT4|BIT3))>>3));\r
+  } else {\r
+    if (SystemConfiguration.Igd == 1 && SystemConfiguration.PrimaryVideoAdaptor != 2) {\r
+      GGC = (SystemConfiguration.IgdDvmt50PreAlloc << 3) |\r
+            (SystemConfiguration.GTTSize == GTT_SIZE_1MB ? 0x100: 0x200);\r
+      PciCfg16Write(EC_BASE, 0, 2, 0, 0x50, GGC);\r
+      GGC = PciCfg16Read(EC_BASE, 0, 2, 0, 0x50);\r
+      DEBUG((EFI_D_INFO , "GGC: 0x%08x GMSsize:0x%08x\n", GGC, (GGC & (BIT7|BIT6|BIT5|BIT4|BIT3))>>3));\r
+    }\r
+  }\r
+\r
+  //\r
+  // Initialize PlatformInfo HOB\r
+  //\r
+  Status = ReadPlatformIds(PeiServices, &PlatformInfo);\r
+  ASSERT_EFI_ERROR (Status);\r
+\r
+  //\r
+  // 0 -> Disable , 1 -> Enable\r
+  //\r
+  if(SystemConfiguration.CfioPnpSettings == 1) {\r
+    DEBUG((EFI_D_INFO, "CheckCfioPnpSettings: CFIO Pnp Settings Enabled\n"));\r
+    PlatformInfo.CfioEnabled = 1;\r
+  } else {\r
+    DEBUG((EFI_D_INFO, "CheckCfioPnpSettings: CFIO Pnp Settings Disabled\n"));\r
+    PlatformInfo.CfioEnabled = 0;\r
+  }\r
+\r
+  //\r
+  // Build HOB for PlatformInfo\r
+  //\r
+  BuildGuidDataHob (\r
+    &gEfiPlatformInfoGuid,\r
+    &PlatformInfo,\r
+    sizeof (EFI_PLATFORM_INFO_HOB)\r
+    );\r
+\r
+\r
+  //\r
+  // Set the new boot mode for MRC\r
+  //\r
+#ifdef NOCS_S3_SUPPORT\r
+  Status = UpdateBootMode (PeiServices);\r
+  ASSERT_EFI_ERROR (Status);\r
+#endif\r
+\r
+  DEBUG((EFI_D_INFO, "Setup MMIO size ... \n\n"));\r
+\r
+  //\r
+  // Setup MMIO size\r
+  //\r
+  Status = (*PeiServices)->AllocatePool(\r
+                             PeiServices,\r
+                             sizeof (EFI_PEI_PPI_DESCRIPTOR),\r
+                             (void **)&mVlvMmioPolicyPpiDesc\r
+                             );\r
+  ASSERT_EFI_ERROR (Status);\r
+  Status = (*PeiServices)->AllocatePool(\r
+                             PeiServices,\r
+                             sizeof (VLV_MMIO_POLICY_PPI),\r
+                             (void **)&mVlvMmioPolicyPpi\r
+                             );\r
+  ASSERT_EFI_ERROR (Status);\r
+  (*PeiServices)->SetMem (\r
+                    (VOID *)mVlvMmioPolicyPpi,\r
+                    sizeof (VLV_MMIO_POLICY_PPI),\r
+                    0\r
+                    );\r
+  mVlvMmioPolicyPpiDesc->Flags = EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST;\r
+  mVlvMmioPolicyPpiDesc->Guid = &gVlvMmioPolicyPpiGuid;\r
+  mVlvMmioPolicyPpiDesc->Ppi = mVlvMmioPolicyPpi;\r
+  switch (SystemConfiguration.MmioSize) {\r
+    case 0:      // 768MB\r
+      mVlvMmioPolicyPpi->MmioSize = 0x300;\r
+      break;\r
+    case 1:      // 1GB\r
+      mVlvMmioPolicyPpi->MmioSize = 0x400;\r
+      break;\r
+    case 2:      // 1.25GB\r
+      mVlvMmioPolicyPpi->MmioSize = 0x500;\r
+      break;\r
+    case 3:      // 1.5GB\r
+      mVlvMmioPolicyPpi->MmioSize = 0x600;\r
+      break;\r
+    case 4:      // 2GB\r
+      mVlvMmioPolicyPpi->MmioSize = 0x800;\r
+      break;\r
+    default:\r
+      mVlvMmioPolicyPpi->MmioSize = 0x800;\r
+      break;\r
+  }\r
+  Status = (*PeiServices)->InstallPpi(\r
+                             PeiServices,\r
+                             mVlvMmioPolicyPpiDesc\r
+                             );\r
+  ASSERT_EFI_ERROR (Status);\r
+\r
+  return Status;\r
+}\r
+\r
+EFI_STATUS\r
+ReadPlatformIds (\r
+  IN CONST EFI_PEI_SERVICES             **PeiServices,\r
+  IN OUT EFI_PLATFORM_INFO_HOB          *PlatformInfoHob\r
+  )\r
+{\r
+  {\r
+    EFI_STATUS                      Status = EFI_SUCCESS;\r
+    UINT8                           FabId = 0;\r
+    UINTN                           DataSize;\r
+    EFI_PLATFORM_INFO_HOB           TmpHob;\r
+    EFI_PEI_READ_ONLY_VARIABLE2_PPI *PeiVar;\r
+\r
+    Status = (**PeiServices).LocatePpi (\r
+                               PeiServices,\r
+                               &gEfiPeiReadOnlyVariable2PpiGuid,\r
+                               0,\r
+                               NULL,\r
+                               (void **)&PeiVar\r
+                               );\r
+    ASSERT_EFI_ERROR (Status);\r
+\r
+    DataSize = sizeof (EFI_PLATFORM_INFO_HOB);\r
+    Status = PeiVar->GetVariable (\r
+                       PeiVar,\r
+                       L"PlatformInfo",\r
+                       &gEfiVlv2VariableGuid,\r
+                       NULL,\r
+                       &DataSize,\r
+                       &TmpHob\r
+                                          );\r
+\r
+    if (Status == EFI_SUCCESS) {\r
+      PlatformInfoHob->BoardId        = TmpHob.BoardId;\r
+      PlatformInfoHob->MemCfgID       = TmpHob.MemCfgID;\r
+      PlatformInfoHob->BoardRev       = TmpHob.BoardRev;\r
+      PlatformInfoHob->PlatformFlavor = TmpHob.PlatformFlavor;\r
+      return Status;\r
+    }\r
+\r
+\r
+    PlatformInfoHob->BoardId    = BOARD_ID_MINNOW2;\r
+    DEBUG ((EFI_D_INFO,  "I'm Minnow2!\n"));\r
+\r
+    PlatformInfoHob->MemCfgID   = 0;\r
+    PlatformInfoHob->BoardRev   = FabId + 1;   // FabId = 0 means FAB1 (BoardRev = 1), FabId = 1 means FAB2 (BoardRev = 2)...\r
+    PlatformInfoHob->PlatformFlavor = FlavorMobile;\r
+  }\r
+\r
+  return EFI_SUCCESS;\r
+}\r
+\r
+//\r
+// Start::Alpine Valley platform\r
+//\r
+/**\r
+  This routine reads SysCtl registers\r
+\r
+  @param SmbusBase   SMBUS Base Address\r
+  @param SlvAddr     Targeted Smbus Slave device address\r
+  @param Operation   Which SMBus protocol will be used\r
+  @param Offset      Offset of the register\r
+  @param  Length     Number of bytes\r
+  @param  Buffer     Buffer contains values read from registers\r
+\r
+  @retval SUCCESS as passed\r
+  @retval Others as failed\r
+\r
+**/\r
+EFI_STATUS\r
+PeiSmbusExec (\r
+  UINT16 SmbusBase,\r
+  UINT8 SlvAddr,\r
+  UINT8 Operation,\r
+  UINT8 Offset,\r
+  UINT8 *Length,\r
+  UINT8 *Buffer\r
+  )\r
+{\r
+  EFI_STATUS  Status=EFI_SUCCESS;\r
+  UINT8       AuxcReg;\r
+  UINT8       SmbusOperation = 0;\r
+  UINT8       StsReg;\r
+  UINT8       SlvAddrReg;\r
+  UINT8       HostCmdReg;\r
+  UINT8       BlockCount = 0;\r
+  BOOLEAN     BufferTooSmall;\r
+  UINT8       Index;\r
+  UINT8       *CallBuffer;\r
+  UINT8          RetryCount = BUS_TRIES;\r
+\r
+  //\r
+  // MrcSmbusExec supports byte and block read.\r
+  // Only allow Byte or block access\r
+  //\r
+  if (!((*Length  == AV_SC_BYTE_LEN) || (*Length == AV_SC_BLOCK_LEN))) {\r
+    return EFI_INVALID_PARAMETER;\r
+  }\r
+\r
+  //\r
+  // See if its ok to use the bus based upon INUSE_STS bit.\r
+  //\r
+  Status = AcquireBus (SmbusBase);\r
+  ASSERT_EFI_ERROR(Status);\r
+\r
+  CallBuffer = Buffer;\r
+\r
+  //\r
+  //SmbStatus Bits of interest\r
+  //[6] = IUS (In Use Status)\r
+  //[4] = FAIL\r
+  //[3] = BERR (Bus Error = transaction collision)\r
+  //[2] = DERR (Device Error = Illegal Command Field, Unclaimed Cycle, Host Device Timeout, CRC Error)\r
+  //[1] = INTR (Successful completion of last command)\r
+  //[0] = HOST BUSY\r
+  //\r
+  //\r
+  // This is the main operation loop.  If the operation results in a Smbus\r
+  // collision with another master on the bus, it attempts the requested\r
+  // transaction again at least BUS_TRIES attempts.\r
+  //\r
+  while (RetryCount--) {\r
+    //\r
+    // Operation Specifics (pre-execution)\r
+    //\r
+    Status          = EFI_SUCCESS;\r
+    SlvAddrReg      = SlvAddr;\r
+    HostCmdReg      = Offset;\r
+    AuxcReg         = 0;\r
+\r
+       switch (Operation) {\r
+\r
+       case SMBUS_WRITE_BYTE:\r
+    IoWrite8 (SmbusBase+R_PCH_SMBUS_HD0, CallBuffer[0]);\r
+               SmbusOperation = V_PCH_SMBUS_SMB_CMD_BYTE_DATA;\r
+       break;\r
+\r
+    case SMBUS_READ_BYTE:\r
+      SmbusOperation = V_PCH_SMBUS_SMB_CMD_BYTE_DATA;\r
+               SlvAddrReg |= B_PCH_SMBUS_RW_SEL_READ;\r
+      if (*Length < 1) {\r
+        Status = EFI_INVALID_PARAMETER;\r
+      }\r
+       *Length = 1;\r
+       break;\r
+\r
+    case SMBUS_WRITE_BLOCK:\r
+      SmbusOperation  = V_PCH_SMBUS_SMB_CMD_BLOCK;\r
+      IoWrite8 (SmbusBase+R_PCH_SMBUS_HD0, *(UINT8 *) Length);\r
+       BlockCount = (UINT8) (*Length);\r
+       if ((*Length < 1) || (*Length > 32)) {\r
+        Status = EFI_INVALID_PARAMETER;\r
+        break;\r
+       }\r
+       AuxcReg |= B_PCH_SMBUS_E32B;\r
+       break;\r
+\r
+    case SMBUS_READ_BLOCK:\r
+      SmbusOperation = V_PCH_SMBUS_SMB_CMD_BLOCK;\r
+       SlvAddrReg |= B_PCH_SMBUS_RW_SEL_READ;\r
+       if ((*Length < 1) || (*Length > 32)) {\r
+        Status = EFI_INVALID_PARAMETER;\r
+        break;\r
+       }\r
+       AuxcReg |= B_PCH_SMBUS_E32B;\r
+       break;\r
+\r
+    default:\r
+       Status = EFI_INVALID_PARAMETER;\r
+       break;\r
+    }\r
+\r
+    //\r
+    // Set Auxiliary Control register\r
+    //\r
+    IoWrite8 (SmbusBase+R_PCH_SMBUS_AUXC, AuxcReg);\r
+\r
+    //\r
+    // Reset the pointer of the internal buffer\r
+    //\r
+    IoRead8 (SmbusBase+R_PCH_SMBUS_HCTL);\r
+\r
+    //\r
+    // Now that the 32 byte buffer is turned on, we can write th block data\r
+    // into it\r
+    //\r
+    if (Operation == SMBUS_WRITE_BLOCK) {\r
+      for (Index = 0; Index < BlockCount; Index++) {\r
+        //\r
+        // Write next byte\r
+        //\r
+        IoWrite8 (SmbusBase+R_PCH_SMBUS_HBD, CallBuffer[Index]);\r
+      }\r
+    }\r
+\r
+    //\r
+    // Set SMBus slave address for the device to read\r
+    //\r
+    IoWrite8(SmbusBase+R_PCH_SMBUS_TSA, SlvAddrReg);\r
+\r
+    //\r
+    //\r
+    // Set Command register for the offset to read\r
+    //\r
+    IoWrite8(SmbusBase+R_PCH_SMBUS_HCMD, HostCmdReg );\r
+\r
+    //\r
+    // Set Control Register to Set "operation command" protocol and start bit\r
+    //\r
+    IoWrite8(SmbusBase+R_PCH_SMBUS_HCTL, (UINT8) (SmbusOperation + B_PCH_SMBUS_START));\r
+\r
+    //\r
+    // Wait for IO to complete\r
+    //\r
+       do { StsReg = (UINT8) IoRead8(SmbusBase+0); } while ((StsReg & (BIT4|BIT3|BIT2|BIT1)) == 0);\r
+\r
+         if (StsReg & B_PCH_SMBUS_DERR) {\r
+      Status = EFI_DEVICE_ERROR;\r
+      break;\r
+    } else if (StsReg & B_PCH_SMBUS_BERR) {\r
+      //\r
+      // Clear the Bus Error for another try\r
+      //\r
+      Status = EFI_DEVICE_ERROR;\r
+      IoWrite8(SmbusBase+R_PCH_SMBUS_HSTS, B_PCH_SMBUS_BERR);\r
+\r
+      //\r
+      // Clear Status Registers\r
+      //\r
+      IoWrite8(SmbusBase+R_PCH_SMBUS_HSTS, B_PCH_SMBUS_HSTS_ALL);\r
+      IoWrite8(SmbusBase+R_PCH_SMBUS_AUXS, B_PCH_SMBUS_CRCE);\r
+\r
+      continue;\r
+    }\r
+\r
+    //\r
+    // successfull completion\r
+    // Operation Specifics (post-execution)\r
+    //\r
+    switch (Operation) {\r
+\r
+    case SMBUS_READ_BYTE:\r
+      CallBuffer[0] = (UINT8)(IoRead8 (SmbusBase+R_PCH_SMBUS_HD0));\r
+      break;\r
+\r
+    case SMBUS_WRITE_BLOCK:\r
+      IoWrite8(SmbusBase+R_PCH_SMBUS_HSTS, B_PCH_SMBUS_BYTE_DONE_STS);\r
+      break;\r
+\r
+    case SMBUS_READ_BLOCK:\r
+      BufferTooSmall = FALSE;\r
+\r
+      //\r
+      // Find out how many bytes will be in the block\r
+      //\r
+      BlockCount = (UINT8)(IoRead8 (SmbusBase+R_PCH_SMBUS_HD0));\r
+      if (*Length < BlockCount) {\r
+        BufferTooSmall = TRUE;\r
+      } else {\r
+        for (Index = 0; Index < BlockCount; Index++) {\r
+          //\r
+          // Read the byte\r
+          //\r
+          CallBuffer[Index] = (UINT8)IoRead8 (SmbusBase+R_PCH_SMBUS_HBD);\r
+        }\r
+      }\r
+\r
+      *Length = BlockCount;\r
+      if (BufferTooSmall) {\r
+        Status = EFI_BUFFER_TOO_SMALL;\r
+      }\r
+      break;\r
+\r
+    default:\r
+      break;\r
+    };\r
+\r
+    if ((StsReg & B_PCH_SMBUS_BERR) && (Status == EFI_SUCCESS)) {\r
+      //\r
+      // Clear the Bus Error for another try\r
+      //\r
+      Status = EFI_DEVICE_ERROR;\r
+      IoWrite8(SmbusBase+R_PCH_SMBUS_HSTS, B_PCH_SMBUS_BERR);\r
+\r
+      continue;\r
+    } else {\r
+      break;\r
+    }\r
+  }\r
+\r
+  //\r
+  // Clear Status Registers and exit\r
+  //\r
+  IoWrite8(SmbusBase+R_PCH_SMBUS_HSTS, B_PCH_SMBUS_HSTS_ALL);\r
+  IoWrite8(SmbusBase+R_PCH_SMBUS_AUXS, B_PCH_SMBUS_CRCE);\r
+  IoWrite8(SmbusBase+R_PCH_SMBUS_AUXC, 0);\r
+  return Status;\r
+}\r
+//\r
+// End::Alpine Valley platform\r
+//\r
+\r

diff --git a/Vlv2TbltDevicePkg/PlatformPei/Platform.h b/Vlv2TbltDevicePkg/PlatformPei/Platform.h
new file mode 100644 (file)
index 0000000..12e4b65
--- /dev/null
+++ b/Vlv2TbltDevicePkg/PlatformPei/Platform.h
@@ -0,0 +1,216 @@
+/*++\r
+\r
+  Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+\r
+**/\r
+\r
+\r
+#ifndef __PEI_PLATFORM_H__\r
+#define __PEI_PLATFORM_H__\r
+\r
+#define PEI_STALL_RESOLUTION            1\r
+#define STALL_PEIM_SIGNATURE   SIGNATURE_32('p','p','u','s')\r
+\r
+typedef struct {\r
+  UINT32                      Signature;\r
+  EFI_FFS_FILE_HEADER         *FfsHeader;\r
+  EFI_PEI_NOTIFY_DESCRIPTOR   StallNotify;\r
+} STALL_CALLBACK_STATE_INFORMATION;\r
+\r
+#define STALL_PEIM_FROM_THIS(a) CR (a, STALL_CALLBACK_STATE_INFORMATION, StallNotify, STALL_PEIM_SIGNATURE)\r
+\r
+#ifdef NOCS_S3_SUPPORT\r
+\r
+/**\r
+  Peform the boot mode determination logic\r
+  If the box is closed, then\r
+  1. If it's first time to boot, it's boot with full config .\r
+  2. If the ChassisIntrution is selected, force to be a boot with full config\r
+  3. Otherwise it's boot with no change.\r
+\r
+  @param  PeiServices General purpose services available to every PEIM.\r
+  @param  BootMode The detected boot mode.\r
+\r
+  @retval EFI_SUCCESS if the boot mode could be set\r
+**/\r
+EFI_STATUS\r
+UpdateBootMode (\r
+  IN CONST EFI_PEI_SERVICES     **PeiServices\r
+  );\r
+#endif\r
+\r
+/**\r
+  This function reset the entire platform, including all processor and devices, and\r
+  reboots the system.\r
+\r
+  @param  PeiServices General purpose services available to every PEIM.\r
+\r
+  @retval EFI_SUCCESS if it completed successfully.\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+ResetSystem (\r
+  IN CONST EFI_PEI_SERVICES          **PeiServices\r
+  );\r
+\r
+/**\r
+  This function will be called when MRC is done.\r
+\r
+  @param  PeiServices        General purpose services available to every PEIM.\r
+  @param  NotifyDescriptor   Information about the notify event..\r
+  @param  Ppi                The notify context.\r
+\r
+  @retval EFI_SUCCESS        If the function completed successfully.\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+MemoryDiscoveredPpiNotifyCallback (\r
+  IN EFI_PEI_SERVICES                     **PeiServices,\r
+  IN EFI_PEI_NOTIFY_DESCRIPTOR            *NotifyDescriptor,\r
+  IN VOID                                 *Ppi\r
+  );\r
+\r
+/**\r
+  This is the callback function notified by FvFileLoader PPI, it depends on FvFileLoader PPI to load\r
+  the PEIM into memory.\r
+\r
+  @param  PeiServices       General purpose services available to every PEIM.\r
+  @param  NotifyDescriptor  The context of notification.\r
+  @param  Ppi               The notify PPI.\r
+\r
+  @retval EFI_SUCCESS       if it completed successfully.\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+FvFileLoaderPpiNotifyCallback (\r
+  IN EFI_PEI_SERVICES           **PeiServices,\r
+  IN EFI_PEI_NOTIFY_DESCRIPTOR  *NotifyDescriptor,\r
+  IN VOID                       *Ppi\r
+  );\r
+\r
+/**\r
+  This function provides a blocking stall for reset at least the given number of microseconds\r
+  stipulated in the final argument.\r
+\r
+  @param  PeiServices    General purpose services available to every PEIM.\r
+  @param  this Pointer   to the local data for the interface.\r
+  @param  Microseconds   number of microseconds for which to stall.\r
+\r
+  @retval EFI_SUCCESS    the function provided at least the required stall.\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+Stall (\r
+  IN CONST EFI_PEI_SERVICES   **PeiServices,\r
+  IN CONST EFI_PEI_STALL_PPI  *This,\r
+  IN UINTN                    Microseconds\r
+  );\r
+\r
+/**\r
+  This function initialize recovery functionality by installing the recovery PPI.\r
+\r
+  @param  PeiServices  General purpose services available to every PEIM.\r
+\r
+  @retval EFI_SUCCESS  If the interface could be successfully installed.\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+InitializeRecovery (\r
+  IN EFI_PEI_SERVICES     **PeiServices\r
+  );\r
+\r
+/**\r
+  This function\r
+    1. Calling MRC to initialize memory.\r
+    2. Install EFI Memory.\r
+    3. Capsule coalesce if capsule boot mode.\r
+    4. Create HOB of system memory.\r
+\r
+  @param  PeiServices Pointer to the PEI Service Table\r
+\r
+  @retval EFI_SUCCESS If it completes successfully.\r
+\r
+**/\r
+EFI_STATUS\r
+MemoryInit (\r
+  IN EFI_PEI_SERVICES          **PeiServices\r
+  );\r
+\r
+/**\r
+  This function provides the implementation of AtaController PPI Enable Channel function.\r
+\r
+  @param  PeiServices General purpose services available to every PEIM.\r
+  @param  this Pointer to the local data for the interface.\r
+  @param  ChannelMask This parameter is used to specify primary or slavery IDE channel.\r
+\r
+  @retval EFI_SUCCESS  Procedure returned successfully.\r
+**/\r
+EFI_STATUS\r
+EnableAtaChannel (\r
+  IN EFI_PEI_SERVICES               **PeiServices,\r
+  IN PEI_ATA_CONTROLLER_PPI         *This,\r
+  IN UINT8                          ChannelMask\r
+  );\r
+\r
+/**\r
+  This function provides the implementation of AtaController PPI Get IDE channel Register Base Address\r
+\r
+  @param  PeiServices      General purpose services available to every PEIM.\r
+  @param  this             Pointer to the local data for the interface.\r
+  @param  IdeRegsBaseAddr  Pointer to IDE_REGS_BASE_ADDR struct, which is used to record\r
+                           IDE Command and Control regeisters Base Address.\r
+\r
+  @retval EFI_SUCCESS  Procedure returned successfully.\r
+**/\r
+EFI_STATUS\r
+GetIdeRegsBaseAddr (\r
+  IN EFI_PEI_SERVICES               **PeiServices,\r
+  IN PEI_ATA_CONTROLLER_PPI         *This,\r
+  IN IDE_REGS_BASE_ADDR             *IdeRegsBaseAddr\r
+  );\r
+\r
+/**\r
+  This function provides the implementation to properly setup both LM & PDM functionality.\r
+\r
+  @param  PeiServices      General purpose services available to every PEIM.\r
+\r
+  @retval EFI_SUCCESS  Procedure returned successfully.\r
+\r
+**/\r
+EFI_STATUS\r
+ConfigureLM(\r
+  IN EFI_PEI_SERVICES **PeiServices\r
+  );\r
+\r
+#include <Ppi/VlvMmioPolicy.h>\r
+\r
+BOOLEAN\r
+EFIAPI\r
+IsFastBootEnabled (\r
+  IN CONST EFI_PEI_SERVICES **PeiServices\r
+  );\r
+\r
+EFI_STATUS\r
+PrioritizeBootMode (\r
+  IN OUT EFI_BOOT_MODE    *CurrentBootMode,\r
+  IN EFI_BOOT_MODE        NewBootMode\r
+  );\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+CapsulePpiNotifyCallback (\r
+  IN EFI_PEI_SERVICES           **PeiServices,\r
+  IN EFI_PEI_NOTIFY_DESCRIPTOR  *NotifyDescriptor,\r
+  IN VOID                       *Ppi\r
+  );\r
+#endif\r

diff --git a/Vlv2TbltDevicePkg/PlatformPei/PlatformPei.inf b/Vlv2TbltDevicePkg/PlatformPei/PlatformPei.inf
new file mode 100644 (file)
index 0000000..af8bb19
--- /dev/null
+++ b/Vlv2TbltDevicePkg/PlatformPei/PlatformPei.inf
@@ -0,0 +1,136 @@
+#\r
+#\r
+# Copyright (c)  1999  - 2014, Intel Corporation. All rights reserved\r
+#                                                                                  \r\r
+# This program and the accompanying materials are licensed and made available under\r\r
+# the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+# The full text of the license may be found at                                     \r\r
+# http://opensource.org/licenses/bsd-license.php.                                  \r\r
+#                                                                                  \r\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+#                                                                                  \r\r
+#\r
+# This PEIM includes 3 parts, pre memory initialization, MRC\r
+#  wrapper and post memory initialization.\r
+#  On pre memory, following action is performed,\r
+#  1. Initizluize GMCH.\r
+#  2. Detect boot mode.\r
+#  3. Detect video adapter to determine whether we need pre allocated\r
+#  memory.\r
+#\r
+#  After that MRC wrapper calls MRC to initialize memory and install a PPI\r
+#  notify to do post memory\r
+#  initialization. MRC wrapper performance following actions,\r
+#  1. Install EFI Memory.\r
+#  2. Capsule coalesce if capsule boot mode.\r
+#  3. Create HOB of system memory.\r
+#  Note: MRC supports 3 kinds of chipsets including Lakeport, Glenwood and Mukilteo,\r
+#   so please don't define MACRO MUKILTEO_SUPPORT on Lakeport here.\r
+#\r
+#  On post memory, following action is performed,\r
+#  1. TC initialization after MRC.\r
+#  2. SIO initialization.\r
+#  3. Install ResetSystem and FinvFv PPI, relocate Stall to memory on\r
+#   recovery boot mode.\r
+#  4. Set MTRR for PEI\r
+#  5. Create FV HOB and Flash HOB\r
+#  6. Install RecoveryModule and AtaController PPI if on recovery boot mode.\r
+#\r
+#  This PEIM does not have any register access directly, it depends on\r
+#  IntelTCLib, TCAccess libraries to access Chipset\r
+#  registers.\r
+#\r
+#  Platform.c - Provide main flow and entrypoint of PEIM.\r
+#  MemoryCallback.c - Includes a memory call back function notified when\r
+#     MRC is done.\r
+#\r
+#\r
+\r
+[Defines]\r
+  INF_VERSION                    = 0x00010005\r
+  BASE_NAME                      = PlatformPeim\r
+  FILE_GUID                      = 9618C0DC-50A4-496c-994F-7241F282ED01\r
+  MODULE_TYPE                    = PEIM\r
+  VERSION_STRING                 = 1.0\r
+  ENTRY_POINT                    = PeiInitPlatform\r
+  PI_SPECIFICATION_VERSION        = 0x0001000A\r
+\r
+[sources.common]\r
+  Platform.c\r
+  Platform.h\r
+  MemoryCallback.c\r
+  CommonHeader.h\r
+  Stall.c\r
+  BootMode.c\r
+\r
+\r
+[Packages]\r
+  MdePkg/MdePkg.dec\r
+  MdeModulePkg/MdeModulePkg.dec\r
+  Vlv2TbltDevicePkg/PlatformPkg.dec\r
+  IntelFrameworkPkg/IntelFrameworkPkg.dec\r
+  Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec\r
+  IA32FamilyCpuPkg/IA32FamilyCpuPkg.dec\r
+  UefiCpuPkg/UefiCpuPkg.dec\r
+  CryptoPkg/CryptoPkg.dec\r
+  EdkCompatibilityPkg/EdkCompatibilityPkg.dec\r
+\r
+[LibraryClasses]\r
+  PeimEntryPoint\r
+  DebugLib\r
+  HobLib\r
+  IoLib\r
+  MultiPlatformLib\r
+  MtrrLib\r
+  PerformanceLib\r
+  MonoStatusCodeLib\r
+  BaseCryptLib\r
+  PciLib\r
+\r
+[Ppis]\r
+  gEfiPeiStallPpiGuid\r
+  gPeiSpeakerInterfacePpiGuid\r
+  gEfiPeiMemoryDiscoveredPpiGuid\r
+  gVlvPolicyPpiGuid\r
+  gEfiPeiReadOnlyVariable2PpiGuid\r
+  gEfiPeiResetPpiGuid\r
+  gEfiEndOfPeiSignalPpiGuid\r
+  gEfiFindFvPpiGuid\r
+  gPeiCapsulePpiGuid\r
+  gEfiPeiBootInRecoveryModePpiGuid\r
+  gEfiPeiRecoveryModulePpiGuid\r
+  gEfiPeiDeviceRecoveryModulePpiGuid\r
+  gPeiCachePpiGuid\r
+  gEfiPeiMasterBootModePpiGuid\r
+  gEfiPeiSmbusPpiGuid\r
+  gPeiMfgMemoryTestPpiGuid\r
+  gPeiSha256HashPpiGuid\r
+  gVlvMmioPolicyPpiGuid\r
+\r
+[Guids]\r
+  gEfiSetupVariableGuid\r
+  gEfiPlatformInfoGuid\r
+  gEfiPlatformBootModeGuid\r
+  gEfiPlatformCpuInfoGuid\r
+  gEfiGlobalVariableGuid\r
+  gRecoveryOnFatFloppyDiskGuid\r
+  gRecoveryOnFatUsbDiskGuid\r
+  gRecoveryOnFatIdeDiskGuid\r
+  gRecoveryOnDataCdGuid\r
+  gMfgModeVariableGuid\r
+  gEfiNormalSetupGuid\r
+  gEfiBootStateGuid\r
+  gEfiVlv2VariableGuid\r
+\r
+[Pcd.common]\r
+  gPlatformModuleTokenSpaceGuid.PcdFlashFvMainBase\r
+  gPlatformModuleTokenSpaceGuid.PcdFlashFvMainSize\r
+  gPlatformModuleTokenSpaceGuid.PcdFlashFvRecovery2Base\r
+  gPlatformModuleTokenSpaceGuid.PcdFlashFvRecovery2Size\r
+  gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress\r
+  gPlatformModuleTokenSpaceGuid.PcdFlashAreaBaseAddress\r
+  gPlatformModuleTokenSpaceGuid.PcdFlashAreaSize\r
+[Depex]\r
+  TRUE\r
+\r

diff --git a/Vlv2TbltDevicePkg/PlatformPei/Stall.c b/Vlv2TbltDevicePkg/PlatformPei/Stall.c
new file mode 100644 (file)
index 0000000..8c2ab99
--- /dev/null
+++ b/Vlv2TbltDevicePkg/PlatformPei/Stall.c
@@ -0,0 +1,95 @@
+/** @file\r
+\r
+  Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+\r
+Module Name:\r
+\r
+  Stall.c\r
+\r
+Abstract:\r
+\r
+  Produce Stall Ppi.\r
+\r
+--*/\r
+\r
+\r
+#include "CommonHeader.h"\r
+#include "PlatformBaseAddresses.h"\r
+#include "PchRegs.h"\r
+\r
+/**\r
+  Waits for at least the given number of microseconds.\r
+\r
+  @param PeiServices     General purpose services available to every PEIM.\r
+  @param This            PPI instance structure.\r
+  @param Microseconds    Desired length of time to wait.\r
+\r
+  @retval EFI_SUCCESS    If the desired amount of time was passed.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+Stall (\r
+  IN CONST EFI_PEI_SERVICES   **PeiServices,\r
+  IN CONST EFI_PEI_STALL_PPI      *This,\r
+  IN UINTN              Microseconds\r
+  )\r
+{\r
+  UINTN   Ticks;\r
+  UINTN   Counts;\r
+  UINT32  CurrentTick;\r
+  UINT32  OriginalTick;\r
+  UINT32  RemainingTick;\r
+\r
+  if (Microseconds == 0) {\r
+    return EFI_SUCCESS;\r
+  }\r
+\r
+  OriginalTick = IoRead32 (ACPI_BASE_ADDRESS + R_PCH_ACPI_PM1_TMR);\r
+  OriginalTick &= (V_PCH_ACPI_PM1_TMR_MAX_VAL - 1);\r
+  CurrentTick = OriginalTick;\r
+\r
+  //\r
+  // The timer frequency is 3.579545MHz, so 1 ms corresponds to 3.58 clocks\r
+  //\r
+  Ticks = Microseconds * 358 / 100 + OriginalTick + 1;\r
+\r
+  //\r
+  // The loops needed for timer overflow\r
+  //\r
+  Counts = (UINTN)RShiftU64((UINT64)Ticks, 24);\r
+\r
+  //\r
+  // Remaining clocks within one loop\r
+  //\r
+  RemainingTick = Ticks & 0xFFFFFF;\r
+\r
+  //\r
+  // Do not intend to use TMROF_STS bit of register PM1_STS, because this add extra\r
+  // one I/O operation, and may generate SMI\r
+  //\r
+  while (Counts != 0) {\r
+    CurrentTick = IoRead32 (ACPI_BASE_ADDRESS + R_PCH_ACPI_PM1_TMR) & B_PCH_ACPI_PM1_TMR_VAL;\r
+    if (CurrentTick <= OriginalTick) {\r
+      Counts--;\r
+    }\r
+    OriginalTick = CurrentTick;\r
+  }\r
+\r
+  while ((RemainingTick > CurrentTick) && (OriginalTick <= CurrentTick)) {\r
+    OriginalTick  = CurrentTick;\r
+    CurrentTick   = IoRead32 (ACPI_BASE_ADDRESS + R_PCH_ACPI_PM1_TMR) & B_PCH_ACPI_PM1_TMR_VAL;\r
+  }\r
+\r
+  return EFI_SUCCESS;\r
+}\r

diff --git a/Vlv2TbltDevicePkg/PlatformPkg.dec b/Vlv2TbltDevicePkg/PlatformPkg.dec
new file mode 100644 (file)
index 0000000..378cb53
--- /dev/null
+++ b/Vlv2TbltDevicePkg/PlatformPkg.dec
@@ -0,0 +1,208 @@
+#/** @file\r
+# Platform Package\r
+#\r
+# This package provides platform specific modules.\r
+# Copyright (c) 2009  - 2014, Intel Corporation. All rights reserved.<BR>\r
+#                                                                                  \r\r
+# This program and the accompanying materials are licensed and made available under\r\r
+# the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+# The full text of the license may be found at                                     \r\r
+# http://opensource.org/licenses/bsd-license.php.                                  \r\r
+#                                                                                  \r\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+#                                                                                  \r\r
+#\r
+#\r
+#**/\r
+\r
+[Defines]\r
+  DEC_SPECIFICATION              = 0x00010005\r
+  PACKAGE_NAME                   = PlatformPkg\r
+  PACKAGE_GUID                   = 463B3B00-0D18-4a5f-90C0-D5B851D2574B\r
+  PACKAGE_VERSION                = 0.1\r
+\r
+[Includes]\r
+  .\r
+  Include\r
+  Include/Library\r
+\r
+[Ppis]\r
+  gPeiSpeakerInterfacePpiGuid  = { 0x30ac275e, 0xbb30, 0x4b84, { 0xa1, 0xcd, 0x0a, 0xf1, 0x32, 0x2c, 0x89, 0xc0 }}\r
+  gPeiUsbControllerPpiGuid     = { 0x3BC1F6DE, 0x693E, 0x4547, { 0xA3, 0x00, 0x21, 0x82, 0x3C, 0xA4, 0x20, 0xB2 }}\r
+  gPeiMfgMemoryTestPpiGuid     = { 0xab294a92, 0xeaf5, 0x4cf3, { 0xab, 0x2b, 0x2d, 0x4b, 0xed, 0x4d, 0xb6, 0x3d }}\r
+  gPeiSha256HashPpiGuid        = { 0x950e191b, 0x8524, 0x4f51, { 0x80, 0xa1, 0x5c, 0x4f, 0x1b, 0x03, 0xf3, 0x5c }}\r
+\r
+[Guids]\r
+  gEfiPlatformBootModeGuid                = { 0xce845704, 0x1683, 0x4d38, { 0xa4, 0xf9, 0x7d, 0x0b, 0x50, 0x77, 0x57, 0x93 } }\r
+  gEfiPlatformInfoGuid                    = { 0x1e2acc41, 0xe26a, 0x483d, { 0xaf, 0xc7, 0xa0, 0x56, 0xc3, 0x4e, 0x08, 0x7b } }\r
+  gEfiMemoryConfigDataGuid                = { 0x80dbd530, 0xb74c, 0x4f11, { 0x8c, 0x03, 0x41, 0x86, 0x65, 0x53, 0x28, 0x31 } }\r
+  gPlatformModuleTokenSpaceGuid           = { 0x69d13bf0, 0xaf91, 0x4d96, { 0xaa, 0x9f, 0x21, 0x84, 0xc5, 0xce, 0x3b, 0xc0 } }\r
+  gEfiSerialPortTokenSpaceGuid            = { 0x5fad2389, 0x2bc7, 0x4bd2, { 0x83, 0xd3, 0x42, 0x9f, 0xb6, 0xae, 0xa3, 0x3f } }\r
+  gEfiIchTokenSpaceGuid                   = { 0xe38c11e3, 0x968f, 0x47b8, { 0xac, 0xef, 0xac, 0xc0, 0x69, 0x3d, 0xb9, 0xff } }\r
+  gEfiPchTokenSpaceGuid                   = { 0x89a1b278, 0xa1a1, 0x4df7, { 0xb1, 0x37, 0xde, 0x5a, 0xd7, 0xc4, 0x79, 0x13 } }\r
+  gEfiSioVariableGuid                     = { 0x560bf58a, 0x1e0d, 0x4d7e, { 0x95, 0x3f, 0x29, 0x80, 0xa2, 0x61, 0xe0, 0x31 } }\r
+  gProcessorProducerGuid                  = { 0x1bf06aea, 0x5bec, 0x4a8d, { 0x95, 0x76, 0x74, 0x9b, 0x09, 0x56, 0x2d, 0x30 } }\r
+  gEfiPowerOnHobGuid                      = { 0x0468a601, 0xc535, 0x46fd, { 0xa9, 0x5d, 0xbb, 0xab, 0x99, 0x1b, 0x17, 0x8c } }\r
+  gEfiPlatformCpuInfoGuid                 = { 0xbb9c7ab7, 0xb8d9, 0x4bf3, { 0x9c, 0x29, 0x9b, 0xf3, 0x41, 0xe2, 0x17, 0xbc } }\r
+  gEfiBiosIdGuid                          = { 0xC3E36D09, 0x8294, 0x4b97, { 0xA8, 0x57, 0xD5, 0x28, 0x8F, 0xE3, 0x3E, 0x28 } }\r
+  gEfiPlatformBootModeGuid                = { 0xce845704, 0x1683, 0x4d38, { 0xa4, 0xf9, 0x7d, 0x0b, 0x50, 0x77, 0x57, 0x93 } }\r
+  gEfiBoardFeaturesGuid                   = { 0x94b9e8ae, 0x8877, 0x479a, { 0x98, 0x42, 0xf5, 0x97, 0x4b, 0x82, 0xce, 0xd3 } }\r
+  gItkDataVarGuid                         = { 0x3812723d, 0x7e48, 0x4e29, { 0xbc, 0x27, 0xf5, 0xa3, 0x9a, 0xc9, 0x4e, 0xf1 } }\r
+  gDmiDataGuid                            = { 0x70e56c5e, 0x280c, 0x44b0, { 0xa4, 0x97, 0x09, 0x68, 0x1a, 0xbc, 0x37, 0x5e } }\r
+  gIdccDataHubGuid                        = { 0x788e1d9f, 0x1eab, 0x47d2, { 0xa2, 0xf3, 0x78, 0xca, 0xe8, 0x7d, 0x60, 0x12 } }\r
+  gEfiSetupVariableGuid                   = { 0xec87d643, 0xeba4, 0x4bb5, { 0xa1, 0xe5, 0x3f, 0x3e, 0x36, 0xb2, 0x0d, 0xa9 } }\r
+  gEfiPlatformInfoGuid                    = { 0x1e2acc41, 0xe26a, 0x483d, { 0xaf, 0xc7, 0xa0, 0x56, 0xc3, 0x4e, 0x08, 0x7b } }\r
+  gMfgModeVariableGuid                    = { 0xEF14FD78, 0x0793, 0x4e2b, { 0xAC, 0x6D, 0x06, 0x28, 0x47, 0xE0, 0x17, 0x91 } }\r
+  gEfiAcpiTableStorageGuid                = { 0x7e374e25, 0x8e01, 0x4fee, { 0x87, 0xf2, 0x39, 0x0c, 0x23, 0xc6, 0x06, 0xcd } }\r
+  gACPIOSFRMfgStringVariableGuid          = { 0x72234213, 0x0fd7, 0x48a1, { 0xa5, 0x9f, 0xb4, 0x1b, 0xc1, 0x07, 0xfb, 0xcd } }\r
+  gACPIOSFRRefDataBlockVariableGuid       = { 0x72234213, 0x0fd7, 0x48a1, { 0xa5, 0x9f, 0xb4, 0x1b, 0xc1, 0x07, 0xfb, 0xcd } }\r
+  gACPIOSFRModelStringVariableGuid        = { 0xca1bcad9, 0xe021, 0x4547, { 0xa1, 0xb0, 0x5b, 0x22, 0xc7, 0xf6, 0x87, 0xf4 } }\r
+  gEfiAcpiTableStorageGuid                = { 0x7e374e25, 0x8e01, 0x4fee, { 0x87, 0xf2, 0x39, 0x0c, 0x23, 0xc6, 0x06, 0xcd } }\r
+  gEfiPciLanInfoGuid                      = { 0x0d9a1427, 0xe02a, 0x437d, { 0x92, 0x6b, 0xaa, 0x52, 0x1f, 0xd7, 0x22, 0xba } }\r
+  gEfiNormalSetupGuid                     = { 0xec87d643, 0xeba4, 0x4bb5, { 0xa1, 0xe5, 0x3f, 0x3e, 0x36, 0xb2, 0x0d, 0xa9 } }\r
+  gFirmwareIdGuid                         = { 0x5e559c23, 0x1faa, 0x4ae1, { 0x8d, 0x4a, 0xc6, 0xcf, 0x02, 0x6c, 0x76, 0x6f } }\r
+  gBmpImageGuid                           = { 0x878AC2CC, 0x5343, 0x46F2, { 0xB5, 0x63, 0x51, 0xF8, 0x9D, 0xAF, 0x56, 0xBA } }\r
+  gOsSelectionVariableGuid                = { 0x86843f56, 0x675d, 0x40a5, { 0x95, 0x30, 0xbc, 0x85, 0x83, 0x72, 0xf1, 0x03 } }\r
+\r
+[Protocols]\r
+  gEfiActiveBiosProtocolGuid              = { 0xebbe2d1b, 0x1647, 0x4bda, { 0xab, 0x9a, 0x78, 0x63, 0xe3, 0x96, 0xd4, 0x1a } }\r
+  gEfiPlatformCpuProtocolGuid             = { 0xbd26cdc9, 0xa092, 0x462a, { 0x87, 0x7a, 0x5a, 0xb6, 0xad, 0xce, 0x48, 0x12 } }\r
+  gDxePchPlatformPolicyProtocolGuid       = { 0x4b0165a9, 0x61d6, 0x4e23, { 0xa0, 0xb5, 0x3e, 0xc7, 0x9c, 0x2e, 0x30, 0xd5 } }\r
+  gEfiTpmMpDriverProtocolGuid             = { 0xde161cfe, 0x1e60, 0x42a1, { 0x8c, 0xc3, 0xee, 0x7e, 0xf0, 0x73, 0x52, 0x12 } }\r
+  gEfiLpcWpce791PolicyProtocolGuid        = { 0xab2bee2f, 0xc1a6, 0x4399, { 0x85, 0x3d, 0xc0, 0x7c, 0x77, 0x4f, 0xfd, 0x0d } }\r
+  gUsbPolicyGuid                          = { 0xf617b358, 0x12cf, 0x414a, { 0xa0, 0x69, 0x60, 0x67, 0x7b, 0xda, 0x13, 0xb4 } }\r
+  gEfiSpeakerInterfaceProtocolGuid        = { 0x400b4476, 0x3081, 0x11d6, { 0x87, 0xed, 0x00, 0x06, 0x29, 0x45, 0xc3, 0xb9 } }\r
+  gDxeVlvPlatformPolicyGuid               = { 0x5bab88ba, 0xe0e2, 0x4674, { 0xb6, 0xad, 0xb8, 0x12, 0xf6, 0x88, 0x1c, 0xd6 } }\r
+  gEfiSmbiosSlotPopulationGuid            = { 0xef7bf7d6, 0xf8ff, 0x4a76, { 0x82, 0x47, 0xc0, 0xd0, 0xd1, 0xcc, 0x49, 0xc0 } }\r
+  gObservableProtocolGuid                 = { 0xe227c522, 0xd5fe, 0x4a53, { 0x87, 0xb1, 0x0f, 0xbe, 0x57, 0x0f, 0x98, 0xe9 } }\r
+  gEfiCk505ClockPlatformInfoGuid          = { 0x3c485ea4, 0x449a, 0x46ce, { 0xbb, 0x08, 0x2a, 0x33, 0x6e, 0xa9, 0x6b, 0x4e } }\r
+  gEfiLpcWpc83627PolicyProtocolGuid       = { 0xd3ecc567, 0x9fd5, 0x44c1, { 0x86, 0xcf, 0x5d, 0xa7, 0xa2, 0x4f, 0x4b, 0x5d } }\r
+  gEfiTcoResetProtocolGuid                = { 0xa6a79162, 0xe325, 0x4c30, { 0xbc, 0xc3, 0x59, 0x37, 0x30, 0x64, 0xef, 0xb3 } }\r
+  gEfiWatchdogTimerDriverProtocolGuid     = { 0xd5b06d16, 0x2ea1, 0x4def, { 0x98, 0xd0, 0xa0, 0x5d, 0x40, 0x72, 0x84, 0x17 } }\r
+  gEfiPlatformIdeInitProtocolGuid         = { 0x377c66a3, 0x8fe7, 0x4ee8, { 0x85, 0xb8, 0xf1, 0xa2, 0x82, 0x56, 0x9e, 0x3b } }\r
+  gEfiPciPlatformProtocolGuid             = { 0x07d75280, 0x27d4, 0x4d69, { 0x90, 0xd0, 0x56, 0x43, 0xe2, 0x38, 0xb3, 0x41 } }\r
+  gEnhancedSpeedstepProtocolGuid          = { 0x91a1ddcf, 0x5374, 0x4939, { 0x89, 0x51, 0xd7, 0x29, 0x3f, 0x1a, 0x78, 0x6f } }\r
+  gEfiAcpiSupportProtocolGuid             = { 0xdbff9d55, 0x89b7, 0x46da, { 0xbd, 0xdf, 0x67, 0x7d, 0x3d, 0xc0, 0x24, 0x1d } }\r
+  gEfiAcpiS3SaveProtocolGuid              = { 0x125f2de1, 0xfb85, 0x440c, { 0xa5, 0x4c, 0x4d, 0x99, 0x35, 0x8a, 0x8d, 0x38 } }\r
+  gEfiCpuIoProtocolGuid                   = { 0xB0732526, 0x38C8, 0x4b40, { 0x88, 0x77, 0x61, 0xC7, 0xB0, 0x6A, 0xAC, 0x45 } }\r
+  gPlatformGOPPolicyGuid                  = { 0xec2e931b, 0x3281, 0x48a5, { 0x81, 0x07, 0xdf, 0x8a, 0x8b, 0xed, 0x3c, 0x5d } }\r
+  gEfiGopDisplayBrightnessProtocolGuid    = { 0x6ff23f1d, 0x877c, 0x4b1b, { 0x93, 0xfc, 0xf1, 0x42, 0xb2, 0xee, 0xa6, 0xa7 } }\r
+  gEfiUsbKeyboardConnectGuid              = { 0xad9c4381, 0x1ede, 0x430c, { 0x8d, 0x42, 0x23, 0x76, 0x7c, 0x46, 0x5d, 0x52 } }\r
+\r
+\r
+[PcdsFixedAtBuild]\r
+  gPlatformModuleTokenSpaceGuid.PcdFlashNvStorageBase|0xFFF60000|UINT32|0x20000007\r
+  gPlatformModuleTokenSpaceGuid.PcdFlashNvStorageSize|0x00010000|UINT32|0x20000008\r
+  gPlatformModuleTokenSpaceGuid.PcdFlashNvStorageEventLogBase|0xFFF6C000|UINT32|0x30000007\r
+  gPlatformModuleTokenSpaceGuid.PcdFlashNvStorageEventLogSize|0x00002000|UINT32|0x30000008\r
+  gPlatformModuleTokenSpaceGuid.PcdFlashFvRecoveryBase|0xFFF80000|UINT32|0x20000004\r
+  gPlatformModuleTokenSpaceGuid.PcdFlashFvRecoverySize|0x00080000|UINT32|0x20000005\r
+  gPlatformModuleTokenSpaceGuid.PcdFlashFvShellBase|0xFFF50000|UINT32|0x20000009\r
+  gPlatformModuleTokenSpaceGuid.PcdFlashFvShellSize|0x00000000|UINT32|0x20000010\r
+  gPlatformModuleTokenSpaceGuid.PcdFlashFvMainBase|0xFF800000|UINT32|0x20000001\r
+  gPlatformModuleTokenSpaceGuid.PcdFlashFvMainSize|0x00500000|UINT32|0x20000002\r
+  gPlatformModuleTokenSpaceGuid.PcdFlashAreaBaseAddress|0xFF800000|UINT32|0x10000001\r
+  gPlatformModuleTokenSpaceGuid.PcdFlashAreaSize|0x00800000|UINT32|0x10000002\r
+  gPlatformModuleTokenSpaceGuid.PcdFlashTestMenuBase|0xFF000000|UINT32|0x20000011\r
+  gPlatformModuleTokenSpaceGuid.PcdFlashTestMenuSize|0x00010000|UINT32|0x20000012\r
+  gPlatformModuleTokenSpaceGuid.PcdFlashFvRecovery2Base|0xFFFA0000|UINT32|0x20000013\r
+  gPlatformModuleTokenSpaceGuid.PcdFlashFvRecovery2Size|0x00040000|UINT32|0x20000014\r
+  gPlatformModuleTokenSpaceGuid.PcdFlashMicroCodeAddress|0xFFF90000|UINT32|0x20000015\r
+  gPlatformModuleTokenSpaceGuid.PcdFlashMicroCodeSize|0x00002000|UINT32|0x20000016\r
+  gPlatformModuleTokenSpaceGuid.PcdFlashMicroCode2Address|0xFFF92000|UINT32|0x20000017\r
+  gPlatformModuleTokenSpaceGuid.PcdFlashMicroCode2Size|0x0000C800|UINT32|0x20000018\r
+  gPlatformModuleTokenSpaceGuid.PcdIFWISigBaseAddress|0x0F00|UINT32|0x20000019\r
+  gPlatformModuleTokenSpaceGuid.PcdPBTNDisableInterval|0x01F4|UINT32|0x2000001A\r
+  gPlatformModuleTokenSpaceGuid.PcdTouchAttributes|2|UINT32|0x20000020\r
+  gPlatformModuleTokenSpaceGuid.PcdTouchCIDString|"I2C05\\S004A"|VOID*|0x20000021\r
+  gPlatformModuleTokenSpaceGuid.PcdFullIconFile             |{ 0x69, 0x00, 0x39, 0x82, 0x30, 0xa6, 0x4b, 0x4c, 0x85, 0xfc, 0x95, 0xe9, 0x49, 0xc9, 0xf0, 0x76 }|VOID*|0x20000022\r
+  gPlatformModuleTokenSpaceGuid.PcdSimpleIconFile           |{ 0x4b, 0xf7, 0xee, 0x4b, 0x30, 0xa3, 0x49, 0x67, 0xa4, 0xad, 0xa4, 0xb1, 0xca, 0xe4, 0x4b, 0x0d }|VOID*|0x20000023\r
+  gPlatformModuleTokenSpaceGuid.PcdCapitalLetterKeyboardFile|{ 0x82, 0x38, 0x75, 0xd8, 0x83, 0xa2, 0x4c, 0x37, 0xb6, 0xea, 0x04, 0xac, 0xc3, 0x06, 0x0f, 0x07 }|VOID*|0x20000024\r
+  gPlatformModuleTokenSpaceGuid.PcdSmallLetterKeyboardFile  |{ 0x4c, 0x66, 0x39, 0xa2, 0x09, 0x0e, 0x4d, 0xc9, 0x9f, 0x55, 0x0f, 0xcb, 0x72, 0x60, 0x26, 0x11 }|VOID*|0x20000025\r
+  gPlatformModuleTokenSpaceGuid.PcdDigitKeyboardFile        |{ 0x3f, 0xfe, 0x2c, 0x17, 0x92, 0x5d, 0x49, 0x7d, 0x87, 0x0a, 0x46, 0x14, 0xe4, 0x58, 0xd8, 0x5e }|VOID*|0x20000026\r
+  gPlatformModuleTokenSpaceGuid.PcdSimpleKeyboardFile       |{ 0x5c, 0xd4, 0xfc, 0x98, 0xbf, 0x79, 0x41, 0x10, 0xa2, 0xd3, 0x87, 0xbe, 0x82, 0xd0, 0x90, 0x52 }|VOID*|0x20000027\r
+\r
+  gPlatformModuleTokenSpaceGuid.PcdFlashSpidOffset|0x1000|UINT32|0x2000002A\r
+  gPlatformModuleTokenSpaceGuid.PcdFlashSpidSize|0x00001000|UINT32|0x2000002B\r
+  gPlatformModuleTokenSpaceGuid.PcdFlashEmOffset|0x3000|UINT32|0x2000002C\r
+  gPlatformModuleTokenSpaceGuid.PcdFlashEmSize|0x1000|UINT32|0x2000002D\r
+\r
+  gEfiSerialPortTokenSpaceGuid.PcdSerialRegisterBase|0x3f8|UINT64|0x00000001\r
+  gEfiSerialPortTokenSpaceGuid.PcdSerialBoudRate|115200|UINT32|0x00000002\r
+\r
+  gEfiPchTokenSpaceGuid.PcdPchAcpiIoPortBaseAddress|0x400|UINT16|0x0000000B\r
+\r
+   ## FFS filename to find the shell application.\r
+  gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdShellFile|{ 0xB7, 0xD6, 0x7A, 0xC5, 0x15, 0x05, 0xA8, 0x40, 0x9D, 0x21, 0x55, 0x16, 0x52, 0x85, 0x4E, 0x37 }|VOID*|0x40000004\r
+\r
+  gEfiIchTokenSpaceGuid.PcdPeiIchUhciControllerIoPortBaseAddress|0x4000|UINT16|0x30000017\r
+  gEfiIchTokenSpaceGuid.PcdPeiIchEhciControllerMemoryBaseAddress|0xFD000000|UINT32|0x30000019\r
+\r
+\r
+  gPlatformModuleTokenSpaceGuid.PcdRamLogBaseAddress|0x20000|UINT32|0x00000013\r
+  gPlatformModuleTokenSpaceGuid.PcdRamLogBaseLength|0x80000|UINT32|0x00000014\r
+  gPlatformModuleTokenSpaceGuid.PcdRamLogBaseCarAddress|0xFEF86000|UINT32|0x00000015\r
+  gPlatformModuleTokenSpaceGuid.PcdRamLogBaseCarLength|0x2000|UINT32|0x00000016\r
+\r
+\r
+  #Pcd for Flash Update tool\r
+  gPlatformModuleTokenSpaceGuid.PcdFlashChipBase|0xFF800000|UINT32|0x40000001\r
+  gPlatformModuleTokenSpaceGuid.PcdFlashChipSize|0x00800000|UINT32|0x40000002\r
+  gPlatformModuleTokenSpaceGuid.PcdFlashDescriptorBase|0xFF800000|UINT32|0x40000003\r
+  gPlatformModuleTokenSpaceGuid.PcdFlashDescriptorSize|0x00001000|UINT32|0x40000004\r
+  gPlatformModuleTokenSpaceGuid.PcdTxeRomBase|0xFF801000|UINT32|0x40000009\r
+  gPlatformModuleTokenSpaceGuid.PcdTxeRomSize|0x004FF000|UINT32|0x4000000A\r
+  gPlatformModuleTokenSpaceGuid.PcdBiosRomBase|0xFFD00000|UINT32|0x4000000B\r
+  gPlatformModuleTokenSpaceGuid.PcdBiosRomSize|0x00300000|UINT32|0x4000000C\r
+\r
+[PcdsFeatureFlag]\r
+  ## This PCD specifies whether StatusCode is reported via ISA Serial port.\r
+  gEfiSerialPortTokenSpaceGuid.PcdStatusCodeUseIsaSerial|TRUE|BOOLEAN|0x00000020\r
+\r
+  ## This PCD specifies whether StatusCode is reported via USB Serial port.\r
+  gEfiSerialPortTokenSpaceGuid.PcdStatusCodeUseUsbSerial|TRUE|BOOLEAN|0x00000021\r
+\r
+  ## This PCD specifies whether StatusCode is reported via RAM.\r
+  gEfiSerialPortTokenSpaceGuid.PcdStatusCodeUseRam|FALSE|BOOLEAN|0x00000022\r
+\r
+  ## Platform BDS PCD to control whether to dispatch additional option rom, e.g.: PXE, AHCI\r
+  gPlatformModuleTokenSpaceGuid.PcdBdsDispatchAdditionalOprom|TRUE|BOOLEAN|0x00000024\r
+\r
+  #new added feature for BIOS usb recovery\r
+  gEfiIchTokenSpaceGuid.PcdEhciRecoveryEnabled|TRUE|BOOLEAN|0x00000026\r
+\r
+[PcdsDynamic,PcdsDynamicEx]\r
+  gPlatformModuleTokenSpaceGuid.PcdInConfigMode|FALSE|BOOLEAN|0x80000001\r
+  gPlatformModuleTokenSpaceGuid.PcdConnectUSBKeyboardonWaitForKeyStroke|FALSE|BOOLEAN|0x80000002\r
+  gPlatformModuleTokenSpaceGuid.PcdEnableWatchdogSwSmiInputValue|0|UINT8|0x80000003\r
+#\r
+#device firmware update support\r
+#\r
+#I2C and SPI support\r
+[Protocols]\r
+\r
+  gEfiMmioDeviceProtocolGuid = { 0x24486226, 0xf8c2, 0x41f5, { 0xb9, 0xdd, 0x78, 0x3e, 0x9e, 0x56, 0xde, 0xa0 } }\r
+  gEfiI2cBusConfigurationManagementProtocolGuid = { 0x75032015, 0xd156, 0x423e, { 0xbf, 0xa3, 0x7a, 0x65, 0xab, 0xa4, 0x71, 0x5 } }\r
+  gEfiI2cAcpiProtocolGuid = { 0xf30c2915, 0x5782, 0x4e6a, { 0xa8, 0x46, 0x5, 0xba, 0xbc, 0xe7, 0xb6, 0xa0 } }\r
+  gEfiI2cMasterProtocolGuid = { 0x578c315a, 0x68cf, 0x4e81, { 0xb5, 0xc6, 0x22, 0xdb, 0x40, 0xd0, 0x10, 0xbc } }\r
+  gEfiI2cHostProtocolGuid = { 0x70b221af, 0xfdff, 0x4fde, { 0x99, 0x68, 0x1a, 0xf6, 0x23, 0xa9, 0x56, 0xd9 } }\r
+  gEfiI2cBusProtocolGuid = { 0x9fa1b225, 0x3346, 0x461b, { 0xa0, 0x69, 0xed, 0x1, 0xb6, 0x73, 0xd2, 0x40 } }\r
+  gEfiI2cSlaveProtocolGuid = { 0xf2c1910e, 0xf5c9, 0x4b72, { 0xb2, 0x43, 0x6d, 0x59, 0x9, 0x6a, 0x79, 0xf0 } }\r
+\r
+#  gEfiSpiAcpiProtocolGuid = { 0x9f49a879, 0x3d71, 0x42b3, { 0xa0, 0xad, 0xdd, 0xb1, 0xf3, 0x30, 0x10, 0xa3 } }\r
+#  gEfiSpiHostProtocolGuid = { 0x951b65e5, 0x8872, 0x41ed, { 0xad, 0x1d, 0xd5, 0x68, 0x1f, 0x4a, 0xf0, 0x33 } }\r
+#  gEfiSpiBusProtocolGuid =  { 0x137b3044, 0xf6d7, 0x473e, { 0xa6, 0x25, 0x9f, 0xb9, 0x25, 0x5, 0xc1, 0x80 } }\r
+\r
+#  gLpssDummyProtocolGuid = { 0xaf4cc162, 0xd41c, 0x455a, { 0xab, 0x45, 0x6d, 0xbc, 0xc1, 0xcd, 0x32, 0xf3 } }\r
+  gEfiSpiProtocolGuid               = { 0x1156efc6, 0xea32, 0x4396, { 0xb5, 0xd5, 0x26, 0x93, 0x2e, 0x83, 0xc3, 0x13 }}\r
+  gEfiGpioOperationProtocolGuid     = { 0x38DDFE8F, 0x8991, 0x44AA, { 0x98, 0x89, 0x83, 0xF4, 0x91, 0x84, 0x65, 0xB0 }}\r
+  gEfiEsrtOperationProtocolGuid     = { 0x4549AB47, 0x6E60, 0x4293, { 0xB9, 0x1D, 0x31, 0xB6, 0x10, 0xAD, 0x80, 0x56 }}\r
+\r
+[Guids]\r
+  gEfiFwDisplayCapsuleGuid       = { 0x3b8c8162, 0x188c, 0x46a4, { 0xae, 0xc9, 0xbe, 0x43, 0xf1, 0xd6, 0x56, 0x97 } }\r
+  gEfiFirmwareClassGuid          = { 0xb122a262, 0x3551, 0x4f48, { 0x88, 0x92, 0x55, 0xf6, 0xc0, 0x61, 0x42, 0x90 } }\r
+  gEfiDFUVerGuid                 = { 0x0dc73aed, 0xcbf6, 0x4a25, { 0xa6, 0x8d, 0x59, 0xc8, 0x0f, 0x44, 0xc7, 0xc3 } }\r
+  gEfiEsrtTableGuid              = { 0xb122a263, 0x3661, 0x4f68, { 0x99, 0x29, 0x78, 0xf8, 0xb0, 0xd6, 0x21, 0x80 } }\r
+  gEfiCapsuleCrashLogVarGuid     = { 0xf3ff1468, 0x04ba, 0x4966, { 0x9f, 0xb2, 0xe4, 0xa7, 0x90, 0x05, 0x46, 0x50 } }\r
+  gEfiCapsuleCrashGuid           = { 0x0e1d2972, 0x65af, 0x4ac1, { 0xbf, 0xa3, 0xce, 0xf4, 0xab, 0x0c, 0x38, 0xfe } }\r

diff --git a/Vlv2TbltDevicePkg/PlatformPkg.fdf b/Vlv2TbltDevicePkg/PlatformPkg.fdf
new file mode 100644 (file)
index 0000000..f7c04e5
--- /dev/null
+++ b/Vlv2TbltDevicePkg/PlatformPkg.fdf
@@ -0,0 +1,1105 @@
+#/** @file
+# FDF file of Platform.
+#
+# Copyright (c) 2008  - 2014, Intel Corporation. All rights reserved.<BR>
+#                                                                                  
+# This program and the accompanying materials are licensed and made available under
+# the terms and conditions of the BSD License that accompanies this distribution.  
+# The full text of the license may be found at                                     
+# http://opensource.org/licenses/bsd-license.php.                                  
+#                                                                                  
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    
+#                                                                                  
+#
+#**/
+
+[Defines]
+DEFINE FLASH_BASE       = 0xFFD00000     #The base address of the 3Mb FLASH Device.
+DEFINE FLASH_SIZE       = 0x00300000     #The flash size in bytes of the 3Mb FLASH Device.
+DEFINE FLASH_BLOCK_SIZE = 0x1000        #The block size in bytes of the 3Mb FLASH Device.
+DEFINE FLASH_NUM_BLOCKS = 0x300           #The number of blocks in 3Mb FLASH Device.
+DEFINE FLASH_AREA_BASE_ADDRESS                                = 0xFF800000
+DEFINE FLASH_AREA_SIZE                                        = 0x00800000
+
+
+DEFINE FLASH_REGION_VPD_OFFSET                                = 0x00000000
+DEFINE FLASH_REGION_VPD_SIZE                                  = 0x0003E000
+
+DEFINE FLASH_REGION_NVSTORAGE_SUBREGION_NV_FTW_WORKING_OFFSET = 0x0003E000
+DEFINE FLASH_REGION_NVSTORAGE_SUBREGION_NV_FTW_WORKING_SIZE   = 0x00002000
+
+
+DEFINE FLASH_REGION_NVSTORAGE_SUBREGION_NV_FTW_SPARE_OFFSET   = 0x00040000
+DEFINE FLASH_REGION_NVSTORAGE_SUBREGION_NV_FTW_SPARE_SIZE     = 0x00040000
+
+!if $(MINNOW2_FSP_BUILD) == TRUE
+DEFINE FLASH_REGION_FSPBIN_OFFSET                             = 0x000B0000
+DEFINE FLASH_REGION_FSPBIN_SIZE                               = 0x00048000
+DEFINE FLASH_REGION_FSPBIN_BASE                               = 0xFFDB0000
+
+DEFINE FLASH_REGION_AZALIABIN_OFFSET                          = 0x000F8000
+DEFINE FLASH_REGION_AZALIABIN_SIZE                            = 0x00008000
+DEFINE FLASH_REGION_AZALIABIN_BASE                            = 0xFFDF8000
+
+!endif
+
+DEFINE FLASH_REGION_VLVMICROCODE_OFFSET                       = 0x00100000
+DEFINE FLASH_REGION_VLVMICROCODE_SIZE                         = 0x00030000
+DEFINE FLASH_REGION_VLVMICROCODE_BASE                         = 0xFFE00000
+
+!if $(TARGET) == RELEASE
+DEFINE FLASH_REGION_FVMAIN_OFFSET                             = 0x00170000
+DEFINE FLASH_REGION_FVMAIN_SIZE                               = 0x0012d000
+!else
+!if $(SOURCE_DEBUG_ENABLE) == TRUE
+DEFINE FLASH_REGION_FVMAIN_OFFSET                             = 0x00130000
+DEFINE FLASH_REGION_FVMAIN_SIZE                               = 0x00176000
+!else
+DEFINE FLASH_REGION_FVMAIN_OFFSET                             = 0x00140000
+DEFINE FLASH_REGION_FVMAIN_SIZE                               = 0x00166000
+!endif
+!endif
+
+!if $(TARGET) == RELEASE
+DEFINE FLASH_REGION_FV_RECOVERY2_OFFSET                       = 0x0029d000
+DEFINE FLASH_REGION_FV_RECOVERY2_SIZE                         = 0x00021000
+
+DEFINE FLASH_REGION_FV_RECOVERY_OFFSET                        = 0x002D0000
+DEFINE FLASH_REGION_FV_RECOVERY_SIZE                          = 0x00030000
+!else
+
+!if $(SOURCE_DEBUG_ENABLE) == TRUE
+DEFINE FLASH_REGION_FV_RECOVERY2_OFFSET                       = 0x002A6000
+DEFINE FLASH_REGION_FV_RECOVERY2_SIZE                         = 0x0002D000
+!else
+DEFINE FLASH_REGION_FV_RECOVERY2_OFFSET                       = 0x002A6000
+DEFINE FLASH_REGION_FV_RECOVERY2_SIZE                         = 0x0002D000
+!endif
+
+
+DEFINE FLASH_REGION_FV_RECOVERY_OFFSET                        = 0x002D3000
+DEFINE FLASH_REGION_FV_RECOVERY_SIZE                          = 0x0002D000
+!endif
+
+################################################################################
+#
+# FD Section
+# The [FD] Section is made up of the definition statements and a
+# description of what goes into  the Flash Device Image.  Each FD section
+# defines one flash "device" image.  A flash device image may be one of
+# the following: Removable media bootable image (like a boot floppy
+# image,) an Option ROM image (that would be "flashed" into an add-in
+# card,) a System "Flash"  image (that would be burned into a system's
+# flash) or an Update ("Capsule") image that will be used to update and
+# existing system flash.
+#
+################################################################################
+[FD.Vlv]
+BaseAddress   = $(FLASH_BASE)|gPlatformModuleTokenSpaceGuid.PcdFlashAreaBaseAddress #The base address of the 3Mb FLASH Device.
+Size          = $(FLASH_SIZE)|gPlatformModuleTokenSpaceGuid.PcdFlashAreaSize        #The flash size in bytes of the 3Mb FLASH Device.
+ErasePolarity = 1
+BlockSize     = $(FLASH_BLOCK_SIZE)          #The block size in bytes of the 3Mb FLASH Device.
+NumBlocks     = $(FLASH_NUM_BLOCKS)          #The number of blocks in 3Mb FLASH Device.
+
+#
+#Flash location override based on actual flash map
+#
+SET gPlatformModuleTokenSpaceGuid.PcdFlashAreaBaseAddress            = $(FLASH_AREA_BASE_ADDRESS)
+SET gPlatformModuleTokenSpaceGuid.PcdFlashAreaSize                   = $(FLASH_AREA_SIZE)
+
+!if $(MINNOW2_FSP_BUILD) == TRUE
+# put below PCD value setting into dsc file
+#SET gFspWrapperTokenSpaceGuid.PcdCpuMicrocodePatchAddress                = $(FLASH_REGION_VLVMICROCODE_BASE)
+#SET gFspWrapperTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize             = $(FLASH_REGION_VLVMICROCODE_SIZE)
+#SET gFspWrapperTokenSpaceGuid.PcdFlashMicroCodeOffset                    = 0x60
+#SET gFspWrapperTokenSpaceGuid.PcdFlashCodeCacheAddress                   = $(FLASH_AREA_BASE_ADDRESS)
+#SET gFspWrapperTokenSpaceGuid.PcdFlashCodeCacheSize                      = $(FLASH_AREA_SIZE)
+#SET gFspWrapperTokenSpaceGuid.PcdFlashFvFspBase                          = $(FLASH_REGION_FSPBIN_BASE)
+#SET gFspWrapperTokenSpaceGuid.PcdFlashFvFspSize                          = $(FLASH_REGION_FSPBIN_SIZE)
+
+!endif
+################################################################################
+#
+# Following are lists of FD Region layout which correspond to the locations of different
+# images within the flash device.
+#
+# Regions must be defined in ascending order and may not overlap.
+#
+# A Layout Region start with a eight digit hex offset (leading "0x" required) followed by
+# the pipe "|" character, followed by the size of the region, also in hex with the leading
+# "0x" characters. Like:
+# Offset|Size
+# PcdOffsetCName|PcdSizeCName
+# RegionType <FV, DATA, or FILE>
+# Fv Size can be adjusted; FVMAIN_COMPACT can be reduced to 0x120000, and FV_RECOVERY can be enlarged to 0x80000
+#
+################################################################################
+$(FLASH_REGION_VPD_OFFSET)|$(FLASH_REGION_VPD_SIZE)
+gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
+#NV_VARIABLE_STORE
+DATA = {
+  ## This is the EFI_FIRMWARE_VOLUME_HEADER
+  # ZeroVector []
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  # FileSystemGuid: gEfiSystemNvDataFvGuid         =
+  #  { 0xFFF12B8D, 0x7696, 0x4C8B, { 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50 }}
+  0x8D, 0x2B, 0xF1, 0xFF, 0x96, 0x76, 0x8B, 0x4C,
+  0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50,
+  # FvLength: 0x80000
+  0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00,
+  #Signature "_FVH"       #Attributes
+  0x5f, 0x46, 0x56, 0x48, 0xff, 0xfe, 0x04, 0x00,
+  #HeaderLength #CheckSum #ExtHeaderOffset #Reserved #Revision
+  0x48, 0x00, 0x2A, 0x09, 0x00, 0x00, 0x00, 0x02,
+  #Blockmap[0]: 7 Blocks * 0x10000 Bytes / Block
+  0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00,
+  #Blockmap[1]: End
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  ## This is the VARIABLE_STORE_HEADER
+!if $(SECURE_BOOT_ENABLE) == TRUE
+  #Signature: gEfiAuthenticatedVariableGuid =
+  #  { 0xaaf32c78, 0x947b, 0x439a, { 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92 }}
+  0x78, 0x2c, 0xf3, 0xaa, 0x7b, 0x94, 0x9a, 0x43,
+  0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92,
+!else
+  #Signature: gEfiVariableGuid =
+  #  { 0xddcf3616, 0x3275, 0x4164, { 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d }}
+  0x16, 0x36, 0xcf, 0xdd, 0x75, 0x32, 0x64, 0x41,
+  0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d,
+!endif
+  #Size: 0x3E000 (gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize) - 0x48 (size of EFI_FIRMWARE_VOLUME_HEADER) = 0x03DFB8
+  # This can speed up the Variable Dispatch a bit.
+  0xB8, 0xDF, 0x03, 0x00,
+  #FORMATTED: 0x5A #HEALTHY: 0xFE #Reserved: UINT16 #Reserved1: UINT32
+  0x5A, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+}
+
+
+$(FLASH_REGION_NVSTORAGE_SUBREGION_NV_FTW_WORKING_OFFSET)|$(FLASH_REGION_NVSTORAGE_SUBREGION_NV_FTW_WORKING_SIZE)
+gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
+#NV_FTW_WORKING
+DATA = {
+  # EFI_FAULT_TOLERANT_WORKING_BLOCK_HEADER->Signature = gEdkiiWorkingBlockSignatureGuid         =
+  #  { 0x9e58292b, 0x7c68, 0x497d, { 0xa0, 0xce, 0x65,  0x0, 0xfd, 0x9f, 0x1b, 0x95 }}
+  0x2B, 0x29, 0x58, 0x9E, 0x68, 0x7C, 0x7D, 0x49,
+  0xA0, 0xCE, 0x65, 0x0,  0xFD, 0x9F, 0x1B, 0x95,
+
+  # Crc:UINT32            #WorkingBlockValid:1, WorkingBlockInvalid:1, Reserved
+  0xE2, 0x33, 0xF2, 0x3,  0xFE, 0xFF, 0xFF, 0xFF,
+  # WriteQueueSize: UINT64 #Size: 0x2000 - 0x20 (FTW_WORKING_HEADER) = 0x1FE0
+  0xE0, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+}
+
+$(FLASH_REGION_NVSTORAGE_SUBREGION_NV_FTW_SPARE_OFFSET)|$(FLASH_REGION_NVSTORAGE_SUBREGION_NV_FTW_SPARE_SIZE)
+gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
+
+!if $(MINNOW2_FSP_BUILD) == TRUE
+
+  $(FLASH_REGION_FSPBIN_OFFSET)|$(FLASH_REGION_FSPBIN_SIZE)
+  gFspWrapperTokenSpaceGuid.PcdFlashFvFspBase|gFspWrapperTokenSpaceGuid.PcdFlashFvFspSize
+  FILE = Vlv2MiscBinariesPkg/FspBinary/FvFsp.bin
+
+
+  $(FLASH_REGION_AZALIABIN_OFFSET)|$(FLASH_REGION_AZALIABIN_SIZE)
+  FILE = Vlv2TbltDevicePkg/FspAzaliaConfigData/AzaliaConfig.bin
+
+!endif
+  #
+  # CPU Microcodes
+  #
+
+$(FLASH_REGION_VLVMICROCODE_OFFSET)|$(FLASH_REGION_VLVMICROCODE_SIZE)
+gPlatformModuleTokenSpaceGuid.PcdFlashMicroCodeAddress|gPlatformModuleTokenSpaceGuid.PcdFlashMicroCodeSize
+FV = MICROCODE_FV
+
+  #
+  # Main Block
+  #
+$(FLASH_REGION_FVMAIN_OFFSET)|$(FLASH_REGION_FVMAIN_SIZE)
+gPlatformModuleTokenSpaceGuid.PcdFlashFvMainBase|gPlatformModuleTokenSpaceGuid.PcdFlashFvMainSize
+FV = FVMAIN_COMPACT
+
+  #
+  # FV Recovery#2
+  #
+$(FLASH_REGION_FV_RECOVERY2_OFFSET)|$(FLASH_REGION_FV_RECOVERY2_SIZE)
+gPlatformModuleTokenSpaceGuid.PcdFlashFvRecovery2Base|gPlatformModuleTokenSpaceGuid.PcdFlashFvRecovery2Size
+FV = FVRECOVERY2
+
+  #
+  # FV Recovery
+  #
+$(FLASH_REGION_FV_RECOVERY_OFFSET)|$(FLASH_REGION_FV_RECOVERY_SIZE)
+gPlatformModuleTokenSpaceGuid.PcdFlashFvRecoveryBase|gPlatformModuleTokenSpaceGuid.PcdFlashFvRecoverySize
+FV = FVRECOVERY
+
+################################################################################
+#
+# FV Section
+#
+# [FV] section is used to define what components or modules are placed within a flash
+# device file.  This section also defines order the components and modules are positioned
+# within the image.  The [FV] section consists of define statements, set statements and
+# module statements.
+#
+################################################################################
+[FV.MICROCODE_FV]
+BlockSize          = $(FLASH_BLOCK_SIZE)
+FvAlignment        = 16
+ERASE_POLARITY     = 1
+MEMORY_MAPPED      = TRUE
+STICKY_WRITE       = TRUE
+LOCK_CAP           = TRUE
+LOCK_STATUS        = FALSE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP  = TRUE
+WRITE_STATUS       = TRUE
+WRITE_LOCK_CAP     = TRUE
+WRITE_LOCK_STATUS  = TRUE
+READ_DISABLED_CAP  = TRUE
+READ_ENABLED_CAP   = TRUE
+READ_STATUS        = TRUE
+READ_LOCK_CAP      = TRUE
+READ_LOCK_STATUS   = TRUE
+
+FILE RAW = 197DB236-F856-4924-90F8-CDF12FB875F3 {
+  $(OUTPUT_DIRECTORY)\$(TARGET)_$(TOOL_CHAIN_TAG)\$(DXE_ARCHITECTURE)\MicrocodeUpdates.bin
+}
+
+################################################################################
+#
+# FV Section
+#
+# [FV] section is used to define what components or modules are placed within a flash
+# device file.  This section also defines order the components and modules are positioned
+# within the image.  The [FV] section consists of define statements, set statements and
+# module statements.
+#
+################################################################################
+[FV.FVRECOVERY2]
+BlockSize          = $(FLASH_BLOCK_SIZE)
+FvAlignment        = 16         #FV alignment and FV attributes setting.
+ERASE_POLARITY     = 1
+MEMORY_MAPPED      = TRUE
+STICKY_WRITE       = TRUE
+LOCK_CAP           = TRUE
+LOCK_STATUS        = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP  = TRUE
+WRITE_STATUS       = TRUE
+WRITE_LOCK_CAP     = TRUE
+WRITE_LOCK_STATUS  = TRUE
+READ_DISABLED_CAP  = TRUE
+READ_ENABLED_CAP   = TRUE
+READ_STATUS        = TRUE
+READ_LOCK_CAP      = TRUE
+READ_LOCK_STATUS   = TRUE
+FvNameGuid         = B73FE497-B92E-416e-8326-45AD0D270092
+
+
+
+INF $(PLATFORM_PACKAGE)/PlatformInitPei/PlatformInitPei.inf
+
+!if $(MINNOW2_FSP_BUILD) == FALSE
+INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/PchSmbusArpDisabled.inf
+INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/VlvInitPeim.inf
+INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/PchInitPeim.inf
+INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/PchSpiPeim.inf
+INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/PeiSmmAccess.inf
+INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/PeiSmmControl.inf
+INF UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume2Pei.inf
+INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/MpS3.inf
+INF EdkCompatibilityPkg/Compatibility/AcpiVariableHobOnSmramReserveHobThunk/AcpiVariableHobOnSmramReserveHobThunk.inf
+!endif
+
+INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/PiSmmCommunicationPei.inf
+!if $(TPM_ENABLED) == TRUE
+INF SecurityPkg/Tcg/TrEEConfig/TrEEConfigPei.inf
+INF SecurityPkg/Tcg/TcgPei/TcgPei.inf
+INF SecurityPkg/Tcg/PhysicalPresencePei/PhysicalPresencePei.inf
+!endif
+INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
+
+!if $(ACPI50_ENABLE) == TRUE
+ INF MdeModulePkg/Universal/Acpi/FirmwarePerformanceDataTablePei/FirmwarePerformancePei.inf
+!endif
+!if $(PERFORMANCE_ENABLE) == TRUE
+INF MdeModulePkg/Universal/ReportStatusCodeRouter/Pei/ReportStatusCodeRouterPei.inf
+!endif
+
+[FV.FVRECOVERY]
+BlockSize          = $(FLASH_BLOCK_SIZE)
+FvAlignment        = 16         #FV alignment and FV attributes setting.
+ERASE_POLARITY     = 1
+MEMORY_MAPPED      = TRUE
+STICKY_WRITE       = TRUE
+LOCK_CAP           = TRUE
+LOCK_STATUS        = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP  = TRUE
+WRITE_STATUS       = TRUE
+WRITE_LOCK_CAP     = TRUE
+WRITE_LOCK_STATUS  = TRUE
+READ_DISABLED_CAP  = TRUE
+READ_ENABLED_CAP   = TRUE
+READ_STATUS        = TRUE
+READ_LOCK_CAP      = TRUE
+READ_LOCK_STATUS   = TRUE
+FvNameGuid         = B73FE497-B92E-416e-8326-45AD0D270091
+
+
+!if $(MINNOW2_FSP_BUILD) == TRUE
+INF IntelFspWrapperPkg/FspWrapperSecCore/FspWrapperSecCore.inf
+!else
+INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/SecCore.inf
+!endif
+
+INF MdeModulePkg/Core/Pei/PeiMain.inf
+!if $(MINNOW2_FSP_BUILD) == TRUE
+INF Vlv2TbltDevicePkg/FspSupport/BootModePei/BootModePei.inf
+INF IntelFspWrapperPkg/FspInitPei/FspInitPei.inf
+!endif
+INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/CpuPeim.inf
+INF MdeModulePkg/Universal/FaultTolerantWritePei/FaultTolerantWritePei.inf
+!if $(SECURE_BOOT_ENABLE) == TRUE
+INF SecurityPkg/VariableAuthenticated/Pei/VariablePei.inf
+!else
+INF MdeModulePkg/Universal/Variable/Pei/VariablePei.inf
+!endif
+
+INF $(PLATFORM_PACKAGE)/PlatformPei/PlatformPei.inf
+
+!if $(MINNOW2_FSP_BUILD) == FALSE
+INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/SeCUma.inf
+!endif
+
+!if $(SOURCE_DEBUG_ENABLE) == TRUE
+  INF  SourceLevelDebugPkg/DebugAgentPei/DebugAgentPei.inf
+!endif
+
+
+!if $(CAPSULE_ENABLE) == TRUE
+INF  MdeModulePkg/Universal/CapsulePei/CapsulePei.inf
+INF  MdeModulePkg/Universal/CapsulePei/CapsuleX64.inf
+!endif
+
+!if $(MINNOW2_FSP_BUILD) == FALSE
+!if $(PCIESC_ENABLE) == TRUE
+INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/PchEarlyInitPeim.inf
+!endif
+INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/MemoryInit.inf
+!endif
+
+INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf
+
+[FV.FVMAIN]
+BlockSize          = $(FLASH_BLOCK_SIZE)
+FvAlignment        = 16
+ERASE_POLARITY     = 1
+MEMORY_MAPPED      = TRUE
+STICKY_WRITE       = TRUE
+LOCK_CAP           = TRUE
+LOCK_STATUS        = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP  = TRUE
+WRITE_STATUS       = TRUE
+WRITE_LOCK_CAP     = TRUE
+WRITE_LOCK_STATUS  = TRUE
+READ_DISABLED_CAP  = TRUE
+READ_ENABLED_CAP   = TRUE
+READ_STATUS        = TRUE
+READ_LOCK_CAP      = TRUE
+READ_LOCK_STATUS   = TRUE
+FvNameGuid         = A881D567-6CB0-4eee-8435-2E72D33E45B5
+
+APRIORI DXE {
+  INF  MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
+  INF  MdeModulePkg/Universal/ReportStatusCodeRouter/RuntimeDxe/ReportStatusCodeRouterRuntimeDxe.inf
+  INF  MdeModulePkg/Universal/StatusCodeHandler/RuntimeDxe/StatusCodeHandlerRuntimeDxe.inf
+  }
+
+FILE FREEFORM = C3E36D09-8294-4b97-A857-D5288FE33E28 {
+    SECTION RAW = $(OUTPUT_DIRECTORY)/$(TARGET)_$(TOOL_CHAIN_TAG)/$(DXE_ARCHITECTURE)/BiosId.bin
+  }
+
+  #
+  # EDK II Related Platform codes
+  #
+
+  !if $(MINNOW2_FSP_BUILD) == TRUE
+  INF IntelFspWrapperPkg/FspNotifyDxe/FspNotifyDxe.inf
+  !endif
+
+INF MdeModulePkg/Core/Dxe/DxeMain.inf
+INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
+!if $(ACPI50_ENABLE) == TRUE
+INF  MdeModulePkg/Universal/Acpi/FirmwarePerformanceDataTableDxe/FirmwarePerformanceDxe.inf
+INF  MdeModulePkg/Universal/Acpi/FirmwarePerformanceDataTableSmm/FirmwarePerformanceSmm.inf
+!endif
+
+
+INF IntelFrameworkModulePkg/Universal/CpuIoDxe/CpuIoDxe.inf
+INF UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.inf
+INF MdeModulePkg/Universal/ReportStatusCodeRouter/RuntimeDxe/ReportStatusCodeRouterRuntimeDxe.inf
+INF MdeModulePkg/Universal/StatusCodeHandler/RuntimeDxe/StatusCodeHandlerRuntimeDxe.inf
+INF MdeModulePkg/Universal/ReportStatusCodeRouter/Smm/ReportStatusCodeRouterSmm.inf
+INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
+INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/MpCpu.inf
+INF $(PLATFORM_PACKAGE)/Metronome/Metronome.inf
+INF IntelFrameworkModulePkg/Universal/BdsDxe/BdsDxe.inf
+INF MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
+INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
+INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
+INF IntelFrameworkModulePkg/Universal/Acpi/AcpiS3SaveDxe/AcpiS3SaveDxe.inf
+
+!if $(SECURE_BOOT_ENABLE)
+INF SecurityPkg/VariableAuthenticated/RuntimeDxe/VariableSmmRuntimeDxe.inf
+INF SecurityPkg/VariableAuthenticated/RuntimeDxe/VariableSmm.inf
+INF $(PLATFORM_PACKAGE)/FvbRuntimeDxe/FvbSmm.inf
+INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteSmm.inf
+INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/PchSpiSmm.inf
+INF SecurityPkg/VariableAuthenticated/SecureBootConfigDxe/SecureBootConfigDxe.inf
+!else
+INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableSmmRuntimeDxe.inf
+INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableSmm.inf
+INF $(PLATFORM_PACKAGE)/FvbRuntimeDxe/FvbSmm.inf
+INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteSmm.inf
+INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/PchSpiSmm.inf
+!endif
+
+INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
+
+INF MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf
+INF PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcatRealTimeClockRuntimeDxe.inf
+INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
+INF $(PLATFORM_PACKAGE)/FvbRuntimeDxe/FvbRuntimeDxe.inf
+
+
+INF $(PLATFORM_PACKAGE)/PlatformSetupDxe/PlatformSetupDxe.inf
+
+!if $(DATAHUB_ENABLE) == TRUE
+INF IntelFrameworkModulePkg/Universal/DataHubDxe/DataHubDxe.inf
+!endif
+INF IntelFrameworkModulePkg/Universal/StatusCode/DatahubStatusCodeHandlerDxe/DatahubStatusCodeHandlerDxe.inf
+INF MdeModulePkg/Universal/MemoryTest/NullMemoryTestDxe/NullMemoryTestDxe.inf
+
+INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/Dptf.inf
+
+  #
+  # EDK II Related Silicon codes
+  #
+INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/PchS3SupportDxe.inf
+
+!if $(USE_HPET_TIMER) == TRUE
+INF PcAtChipsetPkg/HpetTimerDxe/HpetTimerDxe.inf
+!else
+INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/SmartTimer.inf
+!endif
+INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/SmmControl.inf
+
+INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/PchSmbusDxe.inf
+
+INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/IntelPchLegacyInterrupt.inf
+INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/PchReset.inf
+
+!if $(MINNOW2_FSP_BUILD) == FALSE
+INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/PchInitDxe.inf
+!endif
+INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/PchSmiDispatcher.inf
+!if $(PCIESC_ENABLE) == TRUE
+INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/PchPcieSmm.inf
+!endif
+
+INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/PchSpiRuntime.inf
+INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/PchPolicyInitDxe.inf
+INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/PchBiosWriteProtect.inf
+INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/SmmAccess.inf
+INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/PciHostBridge.inf
+!if $(MINNOW2_FSP_BUILD) == FALSE
+INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/VlvInitDxe.inf
+!else
+INF IntelFrameworkModulePkg/Universal/LegacyRegionDxe/LegacyRegionDxe.inf
+INF Vlv2TbltDevicePkg/VlvPlatformInitDxe/VlvPlatformInitDxe.inf
+!endif
+!if $(TPM_ENABLED) == TRUE
+INF SecurityPkg/Tcg/TcgConfigDxe/TcgConfigDxe.inf
+INF SecurityPkg/Tcg/TcgDxe/TcgDxe.inf
+INF RuleOverride = DRIVER_ACPITABLE SecurityPkg/Tcg/TcgSmm/TcgSmm.inf
+!endif
+
+#
+# EDK II Related Platform codes
+#
+INF $(PLATFORM_PACKAGE)/PlatformSmm/PlatformSmm.inf
+INF $(PLATFORM_PACKAGE)/PlatformInfoDxe/PlatformInfoDxe.inf
+INF $(PLATFORM_PACKAGE)/PlatformCpuInfoDxe/PlatformCpuInfoDxe.inf
+INF $(PLATFORM_PACKAGE)/PlatformDxe/PlatformDxe.inf
+INF $(PLATFORM_PACKAGE)/PciPlatform/PciPlatform.inf
+INF $(PLATFORM_PACKAGE)/SaveMemoryConfig/SaveMemoryConfig.inf
+INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/PlatformCpuPolicy.inf
+INF $(PLATFORM_PACKAGE)/PpmPolicy/PpmPolicy.inf
+INF $(PLATFORM_PACKAGE)/SmramSaveInfoHandlerSmm/SmramSaveInfoHandlerSmm.inf
+!if $(GOP_DRIVER_ENABLE) == TRUE
+ INF $(PLATFORM_PACKAGE)/PlatformGopPolicy/PlatformGopPolicy.inf
+ FILE DRIVER = FF0C8745-3270-4439-B74F-3E45F8C77064 {
+  SECTION DXE_DEPEX_EXP = {gPlatformGOPPolicyGuid}
+  SECTION PE32 = Vlv2MiscBinariesPkg/GOP/7.2.1011/RELEASE_VS2008x86/$(DXE_ARCHITECTURE)/IntelGopDriver.efi
+  SECTION UI = "IntelGopDriver"
+}
+!endif
+
+INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/PnpDxe.inf
+  #
+  # SMM
+  #
+INF MdeModulePkg/Core/PiSmmCore/PiSmmIpl.inf
+INF MdeModulePkg/Core/PiSmmCore/PiSmmCore.inf
+INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/PiSmmCpuDxeSmm.inf
+
+INF UefiCpuPkg/CpuIo2Smm/CpuIo2Smm.inf
+INF MdeModulePkg/Universal/LockBox/SmmLockBox/SmmLockBox.inf
+INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/PiSmmCommunicationSmm.inf
+INF $(PLATFORM_PACKAGE)/SmmSwDispatch2OnSmmSwDispatchThunk/SmmSwDispatch2OnSmmSwDispatchThunk.inf
+INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/PowerManagement2.inf
+# INF Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/Dts/Smm/DigitalThermalSensor.inf
+  #
+  # ACPI
+  #
+INF MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/BootScriptExecutorDxe.inf
+INF $(PLATFORM_PACKAGE)/BootScriptSaveDxe/BootScriptSaveDxe.inf
+INF IntelFrameworkModulePkg/Universal/Acpi/AcpiSupportDxe/AcpiSupportDxe.inf
+INF RuleOverride = ACPITABLE2 Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/PowerManagement/AcpiTables/PowerManagementAcpiTables.inf
+
+INF RuleOverride = ACPITABLE $(PLATFORM_RC_PACKAGE)/AcpiTablesPCAT/AcpiTables.inf
+
+INF $(PLATFORM_PACKAGE)/AcpiPlatform/AcpiPlatform.inf
+
+  #
+  # PCI
+  #
+INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
+
+INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/ISPDxe.inf
+
+
+#
+# ISA
+#
+INF $(PLATFORM_PACKAGE)/Wpce791/Wpce791.inf
+INF IntelFrameworkModulePkg/Bus/Isa/IsaBusDxe/IsaBusDxe.inf
+INF IntelFrameworkModulePkg/Bus/Isa/IsaIoDxe/IsaIoDxe.inf
+!if $(SOURCE_DEBUG_ENABLE) != TRUE
+INF  IntelFrameworkModulePkg/Bus/Isa/IsaSerialDxe/IsaSerialDxe.inf
+!endif
+INF IntelFrameworkModulePkg/Bus/Isa/Ps2MouseDxe/Ps2MouseDxe.inf
+INF IntelFrameworkModulePkg/Bus/Isa/Ps2KeyboardDxe/Ps2keyboardDxe.inf
+
+#
+# SDIO
+#
+INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/MmcHost.inf
+INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/MmcMediaDevice.inf
+#
+# IDE/SCSI/AHCI
+#
+INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
+
+INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
+
+INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
+!if $(SATA_ENABLE) == TRUE
+INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/SataController.inf
+#
+
+#
+INF MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf
+INF MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf
+!if $(SCSI_ENABLE) == TRUE
+INF MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf
+INF MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf
+!endif
+#
+!endif
+# Console
+#
+INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
+INF Vlv2TbltDevicePkg/Override/MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
+INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf
+INF IntelFrameworkModulePkg/Universal/Console/VgaClassDxe/VgaClassDxe.inf
+INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
+INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
+INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
+INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
+  #
+  # USB
+  #
+!if $(USB_ENABLE) == TRUE
+INF MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf
+INF MdeModulePkg/Bus/Pci/UhciDxe/UhciDxe.inf
+INF MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
+INF MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf
+INF MdeModulePkg/Bus/Usb/UsbMouseDxe/UsbMouseDxe.inf
+INF MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
+INF MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf
+!endif
+
+  #
+  #  ECP
+  #
+INF EdkCompatibilityPkg/Compatibility/LegacyRegion2OnLegacyRegionThunk/LegacyRegion2OnLegacyRegionThunk.inf
+INF EdkCompatibilityPkg/Compatibility/SmmBaseOnSmmBase2Thunk/SmmBaseOnSmmBase2Thunk.inf
+INF EdkCompatibilityPkg/Compatibility/SmmBaseHelper/SmmBaseHelper.inf
+INF EdkCompatibilityPkg/Compatibility/SmmAccess2OnSmmAccessThunk/SmmAccess2OnSmmAccessThunk.inf
+INF EdkCompatibilityPkg/Compatibility/SmmControl2OnSmmControlThunk/SmmControl2OnSmmControlThunk.inf
+INF EdkCompatibilityPkg/Compatibility/FvOnFv2Thunk/FvOnFv2Thunk.inf
+  #
+  # SMBIOS
+  #
+INF MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf
+INF $(PLATFORM_PACKAGE)/SmBiosMiscDxe/SmBiosMiscDxe.inf
+
+INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/SmbiosMemory.inf
+
+  #
+  # Legacy Modules
+  #
+INF PcAtChipsetPkg/8259InterruptControllerDxe/8259.inf
+
+#
+# FAT file system
+#
+FILE DRIVER = 961578FE-B6B7-44c3-AF35-6BC705CD2B1F {
+    SECTION PE32 = FatBinPkg/EnhancedFatDxe/$(EDK_DXE_ARCHITECTURE)/Fat.efi
+  }
+#
+# UEFI Shell
+#
+FILE APPLICATION = PCD(gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdShellFile) {
+    SECTION PE32 = EdkShellBinPkg/FullShell/$(EDK_DXE_ARCHITECTURE)/Shell_Full.efi
+  }
+
+
+
+!if $(GOP_DRIVER_ENABLE) == TRUE
+FILE FREEFORM = 878AC2CC-5343-46F2-B563-51F89DAF56BA {
+  SECTION RAW = Vlv2MiscBinariesPkg/GOP/7.2.1011/VBT/MNW2/Vbt.bin
+  SECTION UI = "IntelGopVbt"
+}
+!endif
+
+#
+# Network Modules
+#
+!if $(NETWORK_ENABLE) == TRUE
+  FILE DRIVER = 22DE1691-D65D-456a-993E-A253DD1F308C {
+    SECTION PE32 = Vlv2MiscBinariesPkg/UNDI/RtkUndiDxe/$(DXE_ARCHITECTURE)/RtkUndiDxe.efi
+    SECTION UI = "UNDI"
+  }
+  INF  MdeModulePkg/Universal/Network/SnpDxe/SnpDxe.inf
+  INF  MdeModulePkg/Universal/Network/DpcDxe/DpcDxe.inf
+  INF  MdeModulePkg/Universal/Network/MnpDxe/MnpDxe.inf
+  INF  MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf
+  INF  MdeModulePkg/Universal/Network/Ip4Dxe/Ip4Dxe.inf
+  INF  MdeModulePkg/Universal/Network/Ip4ConfigDxe/Ip4ConfigDxe.inf
+  INF  MdeModulePkg/Universal/Network/Udp4Dxe/Udp4Dxe.inf
+  INF  MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Dxe.inf
+  INF  MdeModulePkg/Universal/Network/Mtftp4Dxe/Mtftp4Dxe.inf
+  !if $(NETWORK_IP6_ENABLE) == TRUE
+  INF  NetworkPkg/Ip6Dxe/Ip6Dxe.inf
+  INF  NetworkPkg/Dhcp6Dxe/Dhcp6Dxe.inf
+  INF  NetworkPkg/IpSecDxe/IpSecDxe.inf
+  INF  NetworkPkg/Udp6Dxe/Udp6Dxe.inf
+  INF  NetworkPkg/Mtftp6Dxe/Mtftp6Dxe.inf
+  !endif
+  !if $(NETWORK_IP6_ENABLE) == TRUE
+  INF  NetworkPkg/UefiPxeBcDxe/UefiPxeBcDxe.inf
+  INF  NetworkPkg/TcpDxe/TcpDxe.inf
+  !else
+  INF  MdeModulePkg/Universal/Network/UefiPxeBcDxe/UefiPxeBcDxe.inf
+  INF  MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf
+  !endif
+  !if $(NETWORK_VLAN_ENABLE) == TRUE
+  INF  MdeModulePkg/Universal/Network/VlanConfigDxe/VlanConfigDxe.inf
+  !endif
+  !if $(NETWORK_ISCSI_ENABLE) == TRUE
+  !if $(NETWORK_IP6_ENABLE) == TRUE
+    INF  NetworkPkg/IScsiDxe/IScsiDxe.inf
+  !else
+    INF  MdeModulePkg/Universal/Network/IScsiDxe/IScsiDxe.inf
+  !endif
+  !endif
+!endif
+
+[FV.FVMAIN_COMPACT]
+BlockSize          = $(FLASH_BLOCK_SIZE)
+FvAlignment        = 16
+ERASE_POLARITY     = 1
+MEMORY_MAPPED      = TRUE
+STICKY_WRITE       = TRUE
+LOCK_CAP           = TRUE
+LOCK_STATUS        = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP  = TRUE
+WRITE_STATUS       = TRUE
+WRITE_LOCK_CAP     = TRUE
+WRITE_LOCK_STATUS  = TRUE
+READ_DISABLED_CAP  = TRUE
+READ_ENABLED_CAP   = TRUE
+READ_STATUS        = TRUE
+READ_LOCK_CAP      = TRUE
+READ_LOCK_STATUS   = TRUE
+
+
+
+FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 {
+!if $(LZMA_ENABLE) == TRUE
+# LZMA Compress
+       SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
+          SECTION FV_IMAGE = FVMAIN
+       }
+!else
+!if $(DXE_COMPRESS_ENABLE) == TRUE
+# Tiano Compress
+       SECTION GUIDED A31280AD-481E-41B6-95E8-127F4C984779 PROCESSING_REQUIRED = TRUE {
+          SECTION FV_IMAGE = FVMAIN
+       }
+!else
+# No Compress
+       SECTION COMPRESS PI_NONE {
+          SECTION FV_IMAGE = FVMAIN
+       }
+!endif
+!endif
+     }
+
+[FV.SETUP_DATA]
+BlockSize          = $(FLASH_BLOCK_SIZE)
+#NumBlocks         = 0x10
+FvAlignment        = 16
+ERASE_POLARITY     = 1
+MEMORY_MAPPED      = TRUE
+STICKY_WRITE       = TRUE
+LOCK_CAP           = TRUE
+LOCK_STATUS        = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP  = TRUE
+WRITE_STATUS       = TRUE
+WRITE_LOCK_CAP     = TRUE
+WRITE_LOCK_STATUS  = TRUE
+READ_DISABLED_CAP  = TRUE
+READ_ENABLED_CAP   = TRUE
+READ_STATUS        = TRUE
+READ_LOCK_CAP      = TRUE
+READ_LOCK_STATUS   = TRUE
+
+
+[FV.Update_Data]
+BlockSize          = $(FLASH_BLOCK_SIZE)
+FvAlignment        = 16
+ERASE_POLARITY     = 1
+MEMORY_MAPPED      = TRUE
+STICKY_WRITE       = TRUE
+LOCK_CAP           = TRUE
+LOCK_STATUS        = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP  = TRUE
+WRITE_STATUS       = TRUE
+WRITE_LOCK_CAP     = TRUE
+WRITE_LOCK_STATUS  = TRUE
+READ_DISABLED_CAP  = TRUE
+READ_ENABLED_CAP   = TRUE
+READ_STATUS        = TRUE
+READ_LOCK_CAP      = TRUE
+READ_LOCK_STATUS   = TRUE
+
+FILE RAW = 88888888-8888-8888-8888-888888888888 {
+       FD = Vlv
+     }
+
+[FV.BiosUpdateCargo]
+BlockSize          = $(FLASH_BLOCK_SIZE)
+FvAlignment        = 16
+ERASE_POLARITY     = 1
+MEMORY_MAPPED      = TRUE
+STICKY_WRITE       = TRUE
+LOCK_CAP           = TRUE
+LOCK_STATUS        = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP  = TRUE
+WRITE_STATUS       = TRUE
+WRITE_LOCK_CAP     = TRUE
+WRITE_LOCK_STATUS  = TRUE
+READ_DISABLED_CAP  = TRUE
+READ_ENABLED_CAP   = TRUE
+READ_STATUS        = TRUE
+READ_LOCK_CAP      = TRUE
+READ_LOCK_STATUS   = TRUE
+
+
+
+[FV.BiosUpdate]
+BlockSize          = $(FLASH_BLOCK_SIZE)
+FvAlignment        = 16
+ERASE_POLARITY     = 1
+MEMORY_MAPPED      = TRUE
+STICKY_WRITE       = TRUE
+LOCK_CAP           = TRUE
+LOCK_STATUS        = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP  = TRUE
+WRITE_STATUS       = TRUE
+WRITE_LOCK_CAP     = TRUE
+WRITE_LOCK_STATUS  = TRUE
+READ_DISABLED_CAP  = TRUE
+READ_ENABLED_CAP   = TRUE
+READ_STATUS        = TRUE
+READ_LOCK_CAP      = TRUE
+READ_LOCK_STATUS   = TRUE
+
+[Capsule.Capsule_Boot]
+#
+# gEfiCapsuleGuid supported by platform
+# { 0x3B6686BD, 0x0D76, 0x4030, { 0xB7, 0x0E, 0xB5, 0x51, 0x9E, 0x2F, 0xC5, 0xA0 }}
+#
+CAPSULE_GUID  = 3B6686BD-0D76-4030-B70E-B5519E2FC5A0
+CAPSULE_FLAGS = PersistAcrossReset
+CAPSULE_HEADER_SIZE = 0x20
+
+FV = BiosUpdate
+
+[Capsule.Capsule_Reset]
+#
+# gEfiCapsuleGuid supported by platform
+# { 0x3B6686BD, 0x0D76, 0x4030, { 0xB7, 0x0E, 0xB5, 0x51, 0x9E, 0x2F, 0xC5, 0xA0 }}
+#
+CAPSULE_GUID  = 3B6686BD-0D76-4030-B70E-B5519E2FC5A0
+CAPSULE_FLAGS = PersistAcrossReset
+CAPSULE_HEADER_SIZE = 0x20
+
+FV = BiosUpdate
+
+################################################################################
+#
+# Rules are use with the [FV] section's module INF type to define
+# how an FFS file is created for a given INF file. The following Rule are the default
+# rules for the different module type. User can add the customized rules to define the
+# content of the FFS file.
+#
+################################################################################
+[Rule.Common.SEC]
+  FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED {
+    PE32  PE32    Align = 8       $(INF_OUTPUT)/$(MODULE_NAME).efi
+    RAW BIN       Align = 16      |.com
+  }
+
+[Rule.Common.SEC.BINARY]
+  FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED {
+    PE32  PE32    Align = 8       |.efi
+    RAW BIN       Align = 16      |.com
+  }
+
+[Rule.Common.PEI_CORE]
+  FILE PEI_CORE = $(NAMED_GUID)            {
+    PE32       PE32    Align = Auto      $(INF_OUTPUT)/$(MODULE_NAME).efi
+    UI       STRING="$(MODULE_NAME)" Optional
+    VERSION  STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
+  }
+
+[Rule.Common.PEIM]
+  FILE PEIM = $(NAMED_GUID) {
+     PEI_DEPEX PEI_DEPEX Optional        $(INF_OUTPUT)/$(MODULE_NAME).depex
+     PE32        PE32   Align = Auto     $(INF_OUTPUT)/$(MODULE_NAME).efi
+     UI        STRING="$(MODULE_NAME)" Optional
+     VERSION   STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
+  }
+
+[Rule.Common.PEIM.BINARY]
+  FILE PEIM = $(NAMED_GUID) {
+     PEI_DEPEX PEI_DEPEX Optional        |.depex
+     PE32        PE32   Align = Auto     |.efi
+     UI        STRING="$(MODULE_NAME)" Optional
+     VERSION   STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
+  }
+
+[Rule.Common.PEIM.BIOSID]
+  FILE PEIM = $(NAMED_GUID) {
+     RAW       BIN                       BiosId.bin
+     PEI_DEPEX PEI_DEPEX Optional        $(INF_OUTPUT)/$(MODULE_NAME).depex
+     PE32        PE32   Align = Auto     $(INF_OUTPUT)/$(MODULE_NAME).efi
+     UI        STRING="$(MODULE_NAME)" Optional
+     VERSION   STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
+  }
+
+[Rule.Common.USER_DEFINED.APINIT]
+  FILE RAW = $(NAMED_GUID) Fixed Align=4K {
+     RAW SEC_BIN |.com
+     }
+#cjia 2011-07-21
+[Rule.Common.USER_DEFINED.LEGACY16]
+  FILE FREEFORM = $(NAMED_GUID) {
+     UI  STRING="$(MODULE_NAME)" Optional
+     RAW BIN |.bin
+     }
+#cjia
+
+[Rule.Common.USER_DEFINED.ASM16]
+  FILE FREEFORM = $(NAMED_GUID) {
+     UI  STRING="$(MODULE_NAME)" Optional
+     RAW BIN |.com
+   }
+
+[Rule.Common.DXE_CORE]
+  FILE DXE_CORE = $(NAMED_GUID) {
+    PE32      PE32                     $(INF_OUTPUT)/$(MODULE_NAME).efi
+    UI        STRING="$(MODULE_NAME)" Optional
+    VERSION   STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
+  }
+
+[Rule.Common.UEFI_DRIVER]
+  FILE DRIVER = $(NAMED_GUID) {
+    DXE_DEPEX DXE_DEPEX Optional       $(INF_OUTPUT)/$(MODULE_NAME).depex
+    PE32      PE32                     $(INF_OUTPUT)/$(MODULE_NAME).efi
+    UI        STRING="$(MODULE_NAME)" Optional
+    VERSION   STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
+  }
+
+[Rule.Common.UEFI_DRIVER.BINARY]
+  FILE DRIVER = $(NAMED_GUID) {
+    DXE_DEPEX DXE_DEPEX Optional       |.depex
+    PE32      PE32                     |.efi
+    UI        STRING="$(MODULE_NAME)" Optional
+    VERSION   STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
+  }
+
+[Rule.Common.UEFI_DRIVER.NATIVE_BINARY]
+  FILE DRIVER = $(NAMED_GUID) {
+    DXE_DEPEX DXE_DEPEX Optional      $(WORKSPACE)/$(PLATFORM_PACKAGE)/IntelGopDepex/IntelGopDriver.depex
+    PE32      PE32                    |.efi
+    UI        STRING="$(MODULE_NAME)" Optional
+    VERSION   STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
+  }
+
+[Rule.Common.DXE_DRIVER]
+  FILE DRIVER = $(NAMED_GUID) {
+    DXE_DEPEX DXE_DEPEX Optional       $(INF_OUTPUT)/$(MODULE_NAME).depex
+    PE32      PE32                     $(INF_OUTPUT)/$(MODULE_NAME).efi
+    UI        STRING="$(MODULE_NAME)" Optional
+    VERSION   STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
+  }
+
+[Rule.Common.DXE_DRIVER.BINARY]
+  FILE DRIVER = $(NAMED_GUID) {
+    DXE_DEPEX DXE_DEPEX Optional       |.depex
+    PE32      PE32                     |.efi
+    UI        STRING="$(MODULE_NAME)" Optional
+    VERSION   STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
+  }
+
+[Rule.Common.DXE_DRIVER.DRIVER_ACPITABLE]
+  FILE DRIVER = $(NAMED_GUID) {
+    DXE_DEPEX DXE_DEPEX Optional       $(INF_OUTPUT)/$(MODULE_NAME).depex
+    PE32      PE32                     $(INF_OUTPUT)/$(MODULE_NAME).efi
+    UI        STRING="$(MODULE_NAME)" Optional
+    VERSION   STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
+    RAW ACPI  Optional                |.acpi
+    RAW ASL   Optional                |.aml
+  }
+
+[Rule.Common.DXE_RUNTIME_DRIVER]
+  FILE DRIVER = $(NAMED_GUID) {
+    DXE_DEPEX DXE_DEPEX Optional       $(INF_OUTPUT)/$(MODULE_NAME).depex
+    PE32      PE32                     $(INF_OUTPUT)/$(MODULE_NAME).efi
+    UI        STRING="$(MODULE_NAME)" Optional
+    VERSION   STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
+  }
+
+[Rule.Common.DXE_RUNTIME_DRIVER.BINARY]
+  FILE DRIVER = $(NAMED_GUID) {
+    DXE_DEPEX DXE_DEPEX Optional       |.depex
+    PE32      PE32                     |.efi
+    UI        STRING="$(MODULE_NAME)" Optional
+    VERSION   STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
+  }
+
+[Rule.Common.DXE_SMM_DRIVER]
+  FILE SMM = $(NAMED_GUID) {
+    DXE_DEPEX DXE_DEPEX Optional       $(INF_OUTPUT)/$(MODULE_NAME).depex
+    PE32      PE32                     $(INF_OUTPUT)/$(MODULE_NAME).efi
+    UI        STRING="$(MODULE_NAME)" Optional
+    VERSION   STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
+  }
+
+[Rule.Common.DXE_SMM_DRIVER.BINARY]
+  FILE SMM = $(NAMED_GUID) {
+    SMM_DEPEX SMM_DEPEX                |.depex
+    PE32      PE32                     |.efi
+    UI        STRING="$(MODULE_NAME)" Optional
+    VERSION   STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
+  }
+
+[Rule.Common.DXE_SMM_DRIVER.DRIVER_ACPITABLE]
+  FILE SMM = $(NAMED_GUID) {
+    DXE_DEPEX DXE_DEPEX Optional       $(INF_OUTPUT)/$(MODULE_NAME).depex
+    PE32      PE32                     $(INF_OUTPUT)/$(MODULE_NAME).efi
+    UI        STRING="$(MODULE_NAME)" Optional
+    VERSION   STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
+    RAW ACPI  Optional                |.acpi
+    RAW ASL   Optional                |.aml
+  }
+
+[Rule.Common.SMM_CORE]
+  FILE SMM_CORE = $(NAMED_GUID) {
+    DXE_DEPEX DXE_DEPEX Optional       $(INF_OUTPUT)/$(MODULE_NAME).depex
+    PE32      PE32                     $(INF_OUTPUT)/$(MODULE_NAME).efi
+    UI        STRING="$(MODULE_NAME)" Optional
+    VERSION   STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
+  }
+
+[Rule.Common.SMM_CORE.BINARY]
+  FILE SMM_CORE = $(NAMED_GUID) {
+    DXE_DEPEX DXE_DEPEX Optional       |.depex
+    PE32      PE32                     |.efi
+    UI        STRING="$(MODULE_NAME)" Optional
+    VERSION   STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
+  }
+
+[Rule.Common.UEFI_APPLICATION]
+  FILE APPLICATION = $(NAMED_GUID) {
+    DXE_DEPEX DXE_DEPEX Optional       $(INF_OUTPUT)/$(MODULE_NAME).depex
+    PE32      PE32                     $(INF_OUTPUT)/$(MODULE_NAME).efi
+    UI        STRING="$(MODULE_NAME)" Optional
+    VERSION   STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
+  }
+
+[Rule.Common.UEFI_APPLICATION.UI]
+  FILE APPLICATION = $(NAMED_GUID) {
+    PE32      PE32                     $(INF_OUTPUT)/$(MODULE_NAME).efi
+    UI        STRING="Enter Setup"
+    VERSION   STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
+  }
+
+[Rule.Common.USER_DEFINED]
+  FILE FREEFORM = $(NAMED_GUID) {
+    UI  STRING="$(MODULE_NAME)" Optional
+    RAW BIN                |.bin
+  }
+
+[Rule.Common.USER_DEFINED.ACPITABLE]
+  FILE FREEFORM = $(NAMED_GUID) {
+    RAW ACPI  Optional            |.acpi
+    RAW ASL   Optional            |.aml
+  }
+
+[Rule.Common.USER_DEFINED.ACPITABLE2]
+  FILE FREEFORM = $(NAMED_GUID) {
+    RAW ASL   Optional            |.aml
+  }
+
+[Rule.Common.ACPITABLE]
+  FILE FREEFORM = $(NAMED_GUID) {
+    RAW ACPI  Optional            |.acpi
+    RAW ASL   Optional            |.aml
+  }
+

diff --git a/Vlv2TbltDevicePkg/PlatformPkgConfig.dsc b/Vlv2TbltDevicePkg/PlatformPkgConfig.dsc
new file mode 100644 (file)
index 0000000..ec24fed
--- /dev/null
+++ b/Vlv2TbltDevicePkg/PlatformPkgConfig.dsc
@@ -0,0 +1,96 @@
+#/** @file\r
+# platform configuration file.\r
+#\r
+# Copyright (c) 2012  - 2014, Intel Corporation. All rights reserved.<BR>\r
+#                                                                                  \r\r
+# This program and the accompanying materials are licensed and made available under\r\r
+# the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+# The full text of the license may be found at                                     \r\r
+# http://opensource.org/licenses/bsd-license.php.                                  \r\r
+#                                                                                  \r\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+#                                                                                  \r\r
+#\r
+#**/\r
+\r
+#\r
+# TRUE is ENABLE. FASLE is DISABLE.\r
+#\r
+\r
+#\r
+# FSP selection\r
+#\r
+DEFINE MINNOW2_FSP_BUILD = FALSE\r
+\r
+\r
+DEFINE SCSI_ENABLE = TRUE\r
+\r
+\r
+#\r
+# To enable extra configuration for clk gen\r
+#\r
+DEFINE CLKGEN_CONFIG_EXTRA_ENABLE=TRUE\r
+\r
+#\r
+# Feature selection\r
+#\r
+\r
+#\r
+# Select system timer which is used to produce Timer Arch Protocol:\r
+# TRUE  - HPET timer is used.\r
+# FALSE - 8254 timer is used.\r
+#\r
+DEFINE USE_HPET_TIMER = FALSE\r
+\r
+#\r
+# Feature selection\r
+#\r
+\r
+DEFINE TPM_ENABLED = FALSE\r
+\r
+DEFINE ACPI50_ENABLE = TRUE\r
+DEFINE PERFORMANCE_ENABLE = FALSE\r
+\r
+\r
+DEFINE LFMA_ENABLE = FALSE              # Load module at fixed address feature\r
+DEFINE DXE_COMPRESS_ENABLE = TRUE\r
+DEFINE DXE_CRC32_SECTION_ENABLE = TRUE\r
+DEFINE SSE2_ENABLE = FALSE\r
+\r
+DEFINE SECURE_BOOT_ENABLE = TRUE\r
+DEFINE USER_IDENTIFICATION_ENABLE = FALSE\r
+DEFINE VARIABLE_INFO_ENABLE = FALSE\r
+DEFINE S3_ENABLE = TRUE\r
+DEFINE CAPSULE_ENABLE = FALSE\r
+DEFINE CAPSULE_RESET_ENABLE = TRUE\r
+\r
+DEFINE GOP_DRIVER_ENABLE = TRUE\r
+DEFINE DATAHUB_ENABLE = TRUE\r
+DEFINE DATAHUB_STATUS_CODE_ENABLE = TRUE\r
+DEFINE USB_ENABLE = TRUE\r
+\r
+DEFINE ISA_SERIAL_STATUS_CODE_ENABLE = TRUE\r
+DEFINE USB_SERIAL_STATUS_CODE_ENABLE = FALSE\r
+DEFINE RAM_SERIAL_STATUS_CODE_ENABLE = FALSE\r
+\r
+DEFINE ENBDT_S3_SUPPORT = TRUE\r
+\r
+DEFINE LZMA_ENABLE = TRUE\r
+DEFINE S4_ENABLE = TRUE\r
+DEFINE NETWORK_ENABLE = TRUE\r
+DEFINE NETWORK_IP6_ENABLE = TRUE\r
+DEFINE NETWORK_ISCSI_ENABLE = FALSE\r
+DEFINE NETWORK_VLAN_ENABLE = FALSE\r
+\r
+DEFINE SATA_ENABLE       = TRUE\r
+DEFINE PCIESC_ENABLE     = TRUE\r
+\r
+#\r
+# Enable source level debug default\r
+#\r
+DEFINE SOURCE_DEBUG_ENABLE     = FALSE\r
+\r
+\r
+\r
+\r

diff --git a/Vlv2TbltDevicePkg/PlatformPkgGcc.fdf b/Vlv2TbltDevicePkg/PlatformPkgGcc.fdf
new file mode 100644 (file)
index 0000000..a9f62dc
--- /dev/null
+++ b/Vlv2TbltDevicePkg/PlatformPkgGcc.fdf
@@ -0,0 +1,1037 @@
+#/** @file
+# FDF file of Platform.
+#
+# Copyright (c) 2008  - 2014, Intel Corporation. All rights reserved.<BR>
+#                                                                                  
+# This program and the accompanying materials are licensed and made available under
+# the terms and conditions of the BSD License that accompanies this distribution.  
+# The full text of the license may be found at                                     
+# http://opensource.org/licenses/bsd-license.php.                                  
+#                                                                                  
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    
+#                                                                                  
+#
+#**/
+
+[Defines]
+DEFINE FLASH_BASE       = 0xFFD00000     #The base address of the 3Mb FLASH Device.
+DEFINE FLASH_SIZE       = 0x00300000     #The flash size in bytes of the 3Mb FLASH Device.
+DEFINE FLASH_BLOCK_SIZE = 0x1000        #The block size in bytes of the 3Mb FLASH Device.
+DEFINE FLASH_NUM_BLOCKS = 0x300           #The number of blocks in 3Mb FLASH Device.
+DEFINE FLASH_AREA_BASE_ADDRESS                                = 0xFF800000
+DEFINE FLASH_AREA_SIZE                                        = 0x00800000
+
+
+DEFINE FLASH_REGION_VPD_OFFSET                                = 0x00000000
+DEFINE FLASH_REGION_VPD_SIZE                                  = 0x0003E000
+
+DEFINE FLASH_REGION_NVSTORAGE_SUBREGION_NV_FTW_WORKING_OFFSET = 0x0003E000
+DEFINE FLASH_REGION_NVSTORAGE_SUBREGION_NV_FTW_WORKING_SIZE   = 0x00002000
+
+
+DEFINE FLASH_REGION_NVSTORAGE_SUBREGION_NV_FTW_SPARE_OFFSET   = 0x00040000
+DEFINE FLASH_REGION_NVSTORAGE_SUBREGION_NV_FTW_SPARE_SIZE     = 0x00040000
+
+!if $(MINNOW2_FSP_BUILD) == TRUE
+DEFINE FLASH_REGION_FSPBIN_OFFSET                             = 0x000B0000
+DEFINE FLASH_REGION_FSPBIN_SIZE                               = 0x00048000
+DEFINE FLASH_REGION_FSPBIN_BASE                               = 0xFFDB0000
+
+DEFINE FLASH_REGION_AZALIABIN_OFFSET                          = 0x000F8000
+DEFINE FLASH_REGION_AZALIABIN_SIZE                            = 0x00008000
+DEFINE FLASH_REGION_AZALIABIN_BASE                            = 0xFFDF8000
+
+!endif
+
+DEFINE FLASH_REGION_VLVMICROCODE_OFFSET                       = 0x00100000
+DEFINE FLASH_REGION_VLVMICROCODE_SIZE                         = 0x00030000
+DEFINE FLASH_REGION_VLVMICROCODE_BASE                         = 0xFFE00000
+
+DEFINE FLASH_REGION_FVMAIN_OFFSET                             = 0x00130000
+DEFINE FLASH_REGION_FVMAIN_SIZE                               = 0x0016C000
+
+
+DEFINE FLASH_REGION_FV_RECOVERY2_OFFSET                       = 0x0029C000
+DEFINE FLASH_REGION_FV_RECOVERY2_SIZE                         = 0x0002F000
+
+DEFINE FLASH_REGION_FV_RECOVERY_OFFSET                         = 0x002CB000
+DEFINE FLASH_REGION_FV_RECOVERY_SIZE                           = 0x00035000
+
+################################################################################
+#
+# FD Section
+# The [FD] Section is made up of the definition statements and a
+# description of what goes into  the Flash Device Image.  Each FD section
+# defines one flash "device" image.  A flash device image may be one of
+# the following: Removable media bootable image (like a boot floppy
+# image,) an Option ROM image (that would be "flashed" into an add-in
+# card,) a System "Flash"  image (that would be burned into a system's
+# flash) or an Update ("Capsule") image that will be used to update and
+# existing system flash.
+#
+################################################################################
+[FD.Vlv]
+BaseAddress   = $(FLASH_BASE)|gPlatformModuleTokenSpaceGuid.PcdFlashAreaBaseAddress #The base address of the 3Mb FLASH Device.
+Size          = $(FLASH_SIZE)|gPlatformModuleTokenSpaceGuid.PcdFlashAreaSize        #The flash size in bytes of the 3Mb FLASH Device.
+ErasePolarity = 1
+BlockSize     = $(FLASH_BLOCK_SIZE)          #The block size in bytes of the 3Mb FLASH Device.
+NumBlocks     = $(FLASH_NUM_BLOCKS)          #The number of blocks in 3Mb FLASH Device.
+
+#
+#Flash location override based on actual flash map
+#
+SET gPlatformModuleTokenSpaceGuid.PcdFlashAreaBaseAddress            = $(FLASH_AREA_BASE_ADDRESS)
+SET gPlatformModuleTokenSpaceGuid.PcdFlashAreaSize                   = $(FLASH_AREA_SIZE)
+
+!if $(MINNOW2_FSP_BUILD) == TRUE
+# put below PCD value setting into dsc file
+#SET gFspWrapperTokenSpaceGuid.PcdCpuMicrocodePatchAddress                = $(FLASH_REGION_VLVMICROCODE_BASE)
+#SET gFspWrapperTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize             = $(FLASH_REGION_VLVMICROCODE_SIZE)
+#SET gFspWrapperTokenSpaceGuid.PcdFlashMicroCodeOffset                    = 0x60
+#SET gFspWrapperTokenSpaceGuid.PcdFlashCodeCacheAddress                   = $(FLASH_AREA_BASE_ADDRESS)
+#SET gFspWrapperTokenSpaceGuid.PcdFlashCodeCacheSize                      = $(FLASH_AREA_SIZE)
+#SET gFspWrapperTokenSpaceGuid.PcdFlashFvFspBase                          = $(FLASH_REGION_FSPBIN_BASE)
+#SET gFspWrapperTokenSpaceGuid.PcdFlashFvFspSize                          = $(FLASH_REGION_FSPBIN_SIZE)
+
+!endif
+################################################################################
+#
+# Following are lists of FD Region layout which correspond to the locations of different
+# images within the flash device.
+#
+# Regions must be defined in ascending order and may not overlap.
+#
+# A Layout Region start with a eight digit hex offset (leading "0x" required) followed by
+# the pipe "|" character, followed by the size of the region, also in hex with the leading
+# "0x" characters. Like:
+# Offset|Size
+# PcdOffsetCName|PcdSizeCName
+# RegionType <FV, DATA, or FILE>
+# Fv Size can be adjusted; FVMAIN_COMPACT can be reduced to 0x120000, and FV_RECOVERY can be enlarged to 0x80000
+#
+################################################################################
+# Since the Fce tool don't have gcc version, we can't handle default variable in Linux, 
+# so we hardcode the default value of variable here.
+# Please note that we MUST update the binary once the default value is changed. 
+$(FLASH_REGION_VPD_OFFSET)|$(FLASH_REGION_VPD_SIZE)
+gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
+FILE = $(WORKSPACE)/Vlv2TbltDevicePkg/Stitch/Gcc/NvStorageVariable.bin
+
+$(FLASH_REGION_NVSTORAGE_SUBREGION_NV_FTW_WORKING_OFFSET)|$(FLASH_REGION_NVSTORAGE_SUBREGION_NV_FTW_WORKING_SIZE)
+gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
+FILE = $(WORKSPACE)/Vlv2TbltDevicePkg/Stitch/Gcc/NvStorageFtwWorking.bin
+
+$(FLASH_REGION_NVSTORAGE_SUBREGION_NV_FTW_SPARE_OFFSET)|$(FLASH_REGION_NVSTORAGE_SUBREGION_NV_FTW_SPARE_SIZE)
+gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
+FILE = $(WORKSPACE)/Vlv2TbltDevicePkg/Stitch/Gcc/NvStorageFtwSpare.bin
+
+!if $(MINNOW2_FSP_BUILD) == TRUE
+
+  $(FLASH_REGION_FSPBIN_OFFSET)|$(FLASH_REGION_FSPBIN_SIZE)
+  gFspWrapperTokenSpaceGuid.PcdFlashFvFspBase|gFspWrapperTokenSpaceGuid.PcdFlashFvFspSize
+  FILE = Vlv2MiscBinariesPkg/FspBinary/FvFsp.bin
+
+
+  $(FLASH_REGION_AZALIABIN_OFFSET)|$(FLASH_REGION_AZALIABIN_SIZE)
+  FILE = Vlv2TbltDevicePkg/FspAzaliaConfigData/AzaliaConfig.bin
+
+!endif
+  #
+  # CPU Microcodes
+  #
+
+$(FLASH_REGION_VLVMICROCODE_OFFSET)|$(FLASH_REGION_VLVMICROCODE_SIZE)
+gPlatformModuleTokenSpaceGuid.PcdFlashMicroCodeAddress|gPlatformModuleTokenSpaceGuid.PcdFlashMicroCodeSize
+FV = MICROCODE_FV
+
+  #
+  # Main Block
+  #
+$(FLASH_REGION_FVMAIN_OFFSET)|$(FLASH_REGION_FVMAIN_SIZE)
+gPlatformModuleTokenSpaceGuid.PcdFlashFvMainBase|gPlatformModuleTokenSpaceGuid.PcdFlashFvMainSize
+FV = FVMAIN_COMPACT
+
+  #
+  # FV Recovery#2
+  #
+$(FLASH_REGION_FV_RECOVERY2_OFFSET)|$(FLASH_REGION_FV_RECOVERY2_SIZE)
+gPlatformModuleTokenSpaceGuid.PcdFlashFvRecovery2Base|gPlatformModuleTokenSpaceGuid.PcdFlashFvRecovery2Size
+FV = FVRECOVERY2
+
+  #
+  # FV Recovery
+  #
+$(FLASH_REGION_FV_RECOVERY_OFFSET)|$(FLASH_REGION_FV_RECOVERY_SIZE)
+gPlatformModuleTokenSpaceGuid.PcdFlashFvRecoveryBase|gPlatformModuleTokenSpaceGuid.PcdFlashFvRecoverySize
+FV = FVRECOVERY
+
+################################################################################
+#
+# FV Section
+#
+# [FV] section is used to define what components or modules are placed within a flash
+# device file.  This section also defines order the components and modules are positioned
+# within the image.  The [FV] section consists of define statements, set statements and
+# module statements.
+#
+################################################################################
+[FV.MICROCODE_FV]
+BlockSize          = $(FLASH_BLOCK_SIZE)
+FvAlignment        = 16
+ERASE_POLARITY     = 1
+MEMORY_MAPPED      = TRUE
+STICKY_WRITE       = TRUE
+LOCK_CAP           = TRUE
+LOCK_STATUS        = FALSE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP  = TRUE
+WRITE_STATUS       = TRUE
+WRITE_LOCK_CAP     = TRUE
+WRITE_LOCK_STATUS  = TRUE
+READ_DISABLED_CAP  = TRUE
+READ_ENABLED_CAP   = TRUE
+READ_STATUS        = TRUE
+READ_LOCK_CAP      = TRUE
+READ_LOCK_STATUS   = TRUE
+
+FILE RAW = 197DB236-F856-4924-90F8-CDF12FB875F3 {
+  $(OUTPUT_DIRECTORY)/$(TARGET)_$(TOOL_CHAIN_TAG)/$(DXE_ARCHITECTURE)/MicrocodeUpdates.bin
+}
+
+################################################################################
+#
+# FV Section
+#
+# [FV] section is used to define what components or modules are placed within a flash
+# device file.  This section also defines order the components and modules are positioned
+# within the image.  The [FV] section consists of define statements, set statements and
+# module statements.
+#
+################################################################################
+[FV.FVRECOVERY2]
+BlockSize          = $(FLASH_BLOCK_SIZE)
+FvAlignment        = 16         #FV alignment and FV attributes setting.
+ERASE_POLARITY     = 1
+MEMORY_MAPPED      = TRUE
+STICKY_WRITE       = TRUE
+LOCK_CAP           = TRUE
+LOCK_STATUS        = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP  = TRUE
+WRITE_STATUS       = TRUE
+WRITE_LOCK_CAP     = TRUE
+WRITE_LOCK_STATUS  = TRUE
+READ_DISABLED_CAP  = TRUE
+READ_ENABLED_CAP   = TRUE
+READ_STATUS        = TRUE
+READ_LOCK_CAP      = TRUE
+READ_LOCK_STATUS   = TRUE
+FvNameGuid         = B73FE497-B92E-416e-8326-45AD0D270092
+
+
+
+INF $(PLATFORM_PACKAGE)/PlatformInitPei/PlatformInitPei.inf
+
+!if $(MINNOW2_FSP_BUILD) == FALSE
+INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/PchSmbusArpDisabled.inf
+INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/VlvInitPeim.inf
+INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/PchInitPeim.inf
+INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/PchSpiPeim.inf
+INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/PeiSmmAccess.inf
+INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/PeiSmmControl.inf
+INF UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume2Pei.inf
+INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/MpS3.inf
+INF EdkCompatibilityPkg/Compatibility/AcpiVariableHobOnSmramReserveHobThunk/AcpiVariableHobOnSmramReserveHobThunk.inf
+!endif
+
+INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/PiSmmCommunicationPei.inf
+!if $(TPM_ENABLED) == TRUE
+INF SecurityPkg/Tcg/TrEEConfig/TrEEConfigPei.inf
+INF SecurityPkg/Tcg/TcgPei/TcgPei.inf
+INF SecurityPkg/Tcg/PhysicalPresencePei/PhysicalPresencePei.inf
+!endif
+INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
+
+!if $(ACPI50_ENABLE) == TRUE
+ INF MdeModulePkg/Universal/Acpi/FirmwarePerformanceDataTablePei/FirmwarePerformancePei.inf
+!endif
+!if $(PERFORMANCE_ENABLE) == TRUE
+INF MdeModulePkg/Universal/ReportStatusCodeRouter/Pei/ReportStatusCodeRouterPei.inf
+!endif
+
+[FV.FVRECOVERY]
+BlockSize          = $(FLASH_BLOCK_SIZE)
+FvAlignment        = 16         #FV alignment and FV attributes setting.
+ERASE_POLARITY     = 1
+MEMORY_MAPPED      = TRUE
+STICKY_WRITE       = TRUE
+LOCK_CAP           = TRUE
+LOCK_STATUS        = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP  = TRUE
+WRITE_STATUS       = TRUE
+WRITE_LOCK_CAP     = TRUE
+WRITE_LOCK_STATUS  = TRUE
+READ_DISABLED_CAP  = TRUE
+READ_ENABLED_CAP   = TRUE
+READ_STATUS        = TRUE
+READ_LOCK_CAP      = TRUE
+READ_LOCK_STATUS   = TRUE
+FvNameGuid         = B73FE497-B92E-416e-8326-45AD0D270091
+
+
+!if $(MINNOW2_FSP_BUILD) == TRUE
+INF IntelFspWrapperPkg/FspWrapperSecCore/FspWrapperSecCore.inf
+!else
+INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/SecCore.inf
+!endif
+
+INF MdeModulePkg/Core/Pei/PeiMain.inf
+!if $(MINNOW2_FSP_BUILD) == TRUE
+INF Vlv2TbltDevicePkg/FspSupport/BootModePei/BootModePei.inf
+INF IntelFspWrapperPkg/FspInitPei/FspInitPei.inf
+!endif
+INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/CpuPeim.inf
+INF MdeModulePkg/Universal/FaultTolerantWritePei/FaultTolerantWritePei.inf
+!if $(SECURE_BOOT_ENABLE) == TRUE
+INF SecurityPkg/VariableAuthenticated/Pei/VariablePei.inf
+!else
+INF MdeModulePkg/Universal/Variable/Pei/VariablePei.inf
+!endif
+
+INF $(PLATFORM_PACKAGE)/PlatformPei/PlatformPei.inf
+
+!if $(MINNOW2_FSP_BUILD) == FALSE
+INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/SeCUma.inf
+!endif
+
+!if $(SOURCE_DEBUG_ENABLE) == TRUE
+  INF  SourceLevelDebugPkg/DebugAgentPei/DebugAgentPei.inf
+!endif
+
+
+!if $(CAPSULE_ENABLE) == TRUE
+INF  MdeModulePkg/Universal/CapsulePei/CapsulePei.inf
+INF  MdeModulePkg/Universal/CapsulePei/CapsuleX64.inf
+!endif
+
+!if $(MINNOW2_FSP_BUILD) == FALSE
+!if $(PCIESC_ENABLE) == TRUE
+INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/PchEarlyInitPeim.inf
+!endif
+INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/MemoryInit.inf
+!endif
+
+INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf
+
+[FV.FVMAIN]
+BlockSize          = $(FLASH_BLOCK_SIZE)
+FvAlignment        = 16
+ERASE_POLARITY     = 1
+MEMORY_MAPPED      = TRUE
+STICKY_WRITE       = TRUE
+LOCK_CAP           = TRUE
+LOCK_STATUS        = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP  = TRUE
+WRITE_STATUS       = TRUE
+WRITE_LOCK_CAP     = TRUE
+WRITE_LOCK_STATUS  = TRUE
+READ_DISABLED_CAP  = TRUE
+READ_ENABLED_CAP   = TRUE
+READ_STATUS        = TRUE
+READ_LOCK_CAP      = TRUE
+READ_LOCK_STATUS   = TRUE
+FvNameGuid         = A881D567-6CB0-4eee-8435-2E72D33E45B5
+
+APRIORI DXE {
+  INF  MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
+  INF  MdeModulePkg/Universal/ReportStatusCodeRouter/RuntimeDxe/ReportStatusCodeRouterRuntimeDxe.inf
+  INF  MdeModulePkg/Universal/StatusCodeHandler/RuntimeDxe/StatusCodeHandlerRuntimeDxe.inf
+  }
+
+FILE FREEFORM = C3E36D09-8294-4b97-A857-D5288FE33E28 {
+    SECTION RAW = $(OUTPUT_DIRECTORY)/$(TARGET)_$(TOOL_CHAIN_TAG)/$(DXE_ARCHITECTURE)/BiosId.bin
+  }
+
+  #
+  # EDK II Related Platform codes
+  #
+
+  !if $(MINNOW2_FSP_BUILD) == TRUE
+  INF IntelFspWrapperPkg/FspNotifyDxe/FspNotifyDxe.inf
+  !endif
+
+INF MdeModulePkg/Core/Dxe/DxeMain.inf
+INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
+!if $(ACPI50_ENABLE) == TRUE
+INF  MdeModulePkg/Universal/Acpi/FirmwarePerformanceDataTableDxe/FirmwarePerformanceDxe.inf
+INF  MdeModulePkg/Universal/Acpi/FirmwarePerformanceDataTableSmm/FirmwarePerformanceSmm.inf
+!endif
+
+
+INF IntelFrameworkModulePkg/Universal/CpuIoDxe/CpuIoDxe.inf
+INF UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.inf
+INF MdeModulePkg/Universal/ReportStatusCodeRouter/RuntimeDxe/ReportStatusCodeRouterRuntimeDxe.inf
+INF MdeModulePkg/Universal/StatusCodeHandler/RuntimeDxe/StatusCodeHandlerRuntimeDxe.inf
+INF MdeModulePkg/Universal/ReportStatusCodeRouter/Smm/ReportStatusCodeRouterSmm.inf
+INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
+INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/MpCpu.inf
+INF $(PLATFORM_PACKAGE)/Metronome/Metronome.inf
+INF IntelFrameworkModulePkg/Universal/BdsDxe/BdsDxe.inf
+INF MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
+INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
+INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
+INF IntelFrameworkModulePkg/Universal/Acpi/AcpiS3SaveDxe/AcpiS3SaveDxe.inf
+
+!if $(SECURE_BOOT_ENABLE)
+INF SecurityPkg/VariableAuthenticated/RuntimeDxe/VariableSmmRuntimeDxe.inf
+INF SecurityPkg/VariableAuthenticated/RuntimeDxe/VariableSmm.inf
+INF $(PLATFORM_PACKAGE)/FvbRuntimeDxe/FvbSmm.inf
+INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteSmm.inf
+INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/PchSpiSmm.inf
+INF SecurityPkg/VariableAuthenticated/SecureBootConfigDxe/SecureBootConfigDxe.inf
+!else
+INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableSmmRuntimeDxe.inf
+INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableSmm.inf
+INF $(PLATFORM_PACKAGE)/FvbRuntimeDxe/FvbSmm.inf
+INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteSmm.inf
+INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/PchSpiSmm.inf
+!endif
+
+INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
+
+INF MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf
+INF PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcatRealTimeClockRuntimeDxe.inf
+INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
+INF $(PLATFORM_PACKAGE)/FvbRuntimeDxe/FvbRuntimeDxe.inf
+
+
+INF $(PLATFORM_PACKAGE)/PlatformSetupDxe/PlatformSetupDxe.inf
+
+!if $(DATAHUB_ENABLE) == TRUE
+INF IntelFrameworkModulePkg/Universal/DataHubDxe/DataHubDxe.inf
+!endif
+INF IntelFrameworkModulePkg/Universal/StatusCode/DatahubStatusCodeHandlerDxe/DatahubStatusCodeHandlerDxe.inf
+INF MdeModulePkg/Universal/MemoryTest/NullMemoryTestDxe/NullMemoryTestDxe.inf
+
+INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/Dptf.inf
+
+  #
+  # EDK II Related Silicon codes
+  #
+INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/PchS3SupportDxe.inf
+
+!if $(USE_HPET_TIMER) == TRUE
+INF PcAtChipsetPkg/HpetTimerDxe/HpetTimerDxe.inf
+!else
+INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/SmartTimer.inf
+!endif
+INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/SmmControl.inf
+
+INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/PchSmbusDxe.inf
+
+INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/IntelPchLegacyInterrupt.inf
+INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/PchReset.inf
+
+!if $(MINNOW2_FSP_BUILD) == FALSE
+INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/PchInitDxe.inf
+!endif
+INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/PchSmiDispatcher.inf
+!if $(PCIESC_ENABLE) == TRUE
+INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/PchPcieSmm.inf
+!endif
+
+INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/PchSpiRuntime.inf
+INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/PchPolicyInitDxe.inf
+INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/PchBiosWriteProtect.inf
+INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/SmmAccess.inf
+INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/PciHostBridge.inf
+!if $(MINNOW2_FSP_BUILD) == FALSE
+INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/VlvInitDxe.inf
+!else
+INF IntelFrameworkModulePkg/Universal/LegacyRegionDxe/LegacyRegionDxe.inf
+INF Vlv2TbltDevicePkg/VlvPlatformInitDxe/VlvPlatformInitDxe.inf
+!endif
+!if $(TPM_ENABLED) == TRUE
+INF SecurityPkg/Tcg/TcgConfigDxe/TcgConfigDxe.inf
+INF SecurityPkg/Tcg/TcgDxe/TcgDxe.inf
+INF RuleOverride = DRIVER_ACPITABLE SecurityPkg/Tcg/TcgSmm/TcgSmm.inf
+!endif
+
+#
+# EDK II Related Platform codes
+#
+INF $(PLATFORM_PACKAGE)/PlatformSmm/PlatformSmm.inf
+INF $(PLATFORM_PACKAGE)/PlatformInfoDxe/PlatformInfoDxe.inf
+INF $(PLATFORM_PACKAGE)/PlatformCpuInfoDxe/PlatformCpuInfoDxe.inf
+INF $(PLATFORM_PACKAGE)/PlatformDxe/PlatformDxe.inf
+INF $(PLATFORM_PACKAGE)/PciPlatform/PciPlatform.inf
+INF $(PLATFORM_PACKAGE)/SaveMemoryConfig/SaveMemoryConfig.inf
+INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/PlatformCpuPolicy.inf
+INF $(PLATFORM_PACKAGE)/PpmPolicy/PpmPolicy.inf
+INF $(PLATFORM_PACKAGE)/SmramSaveInfoHandlerSmm/SmramSaveInfoHandlerSmm.inf
+!if $(GOP_DRIVER_ENABLE) == TRUE
+ INF $(PLATFORM_PACKAGE)/PlatformGopPolicy/PlatformGopPolicy.inf
+ FILE DRIVER = FF0C8745-3270-4439-B74F-3E45F8C77064 {
+  SECTION DXE_DEPEX_EXP = {gPlatformGOPPolicyGuid}
+  SECTION PE32 = Vlv2MiscBinariesPkg/GOP/7.2.1011/RELEASE_VS2008x86/$(DXE_ARCHITECTURE)/IntelGopDriver.efi
+  SECTION UI = "IntelGopDriver"
+}
+!endif
+
+INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/PnpDxe.inf
+  #
+  # SMM
+  #
+INF MdeModulePkg/Core/PiSmmCore/PiSmmIpl.inf
+INF MdeModulePkg/Core/PiSmmCore/PiSmmCore.inf
+INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/PiSmmCpuDxeSmm.inf
+
+INF UefiCpuPkg/CpuIo2Smm/CpuIo2Smm.inf
+INF MdeModulePkg/Universal/LockBox/SmmLockBox/SmmLockBox.inf
+INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/PiSmmCommunicationSmm.inf
+INF $(PLATFORM_PACKAGE)/SmmSwDispatch2OnSmmSwDispatchThunk/SmmSwDispatch2OnSmmSwDispatchThunk.inf
+INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/PowerManagement2.inf
+# INF Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/Dts/Smm/DigitalThermalSensor.inf
+  #
+  # ACPI
+  #
+INF MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/BootScriptExecutorDxe.inf
+INF $(PLATFORM_PACKAGE)/BootScriptSaveDxe/BootScriptSaveDxe.inf
+INF IntelFrameworkModulePkg/Universal/Acpi/AcpiSupportDxe/AcpiSupportDxe.inf
+INF RuleOverride = ACPITABLE2 Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/PowerManagement/AcpiTables/PowerManagementAcpiTables.inf
+
+INF RuleOverride = ACPITABLE $(PLATFORM_RC_PACKAGE)/AcpiTablesPCAT/AcpiTables.inf
+
+INF $(PLATFORM_PACKAGE)/AcpiPlatform/AcpiPlatform.inf
+
+  #
+  # PCI
+  #
+INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
+
+INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/ISPDxe.inf
+
+
+#
+# ISA
+#
+INF $(PLATFORM_PACKAGE)/Wpce791/Wpce791.inf
+INF IntelFrameworkModulePkg/Bus/Isa/IsaBusDxe/IsaBusDxe.inf
+INF IntelFrameworkModulePkg/Bus/Isa/IsaIoDxe/IsaIoDxe.inf
+!if $(SOURCE_DEBUG_ENABLE) != TRUE
+INF  IntelFrameworkModulePkg/Bus/Isa/IsaSerialDxe/IsaSerialDxe.inf
+!endif
+INF IntelFrameworkModulePkg/Bus/Isa/Ps2MouseDxe/Ps2MouseDxe.inf
+INF IntelFrameworkModulePkg/Bus/Isa/Ps2KeyboardDxe/Ps2keyboardDxe.inf
+
+#
+# SDIO
+#
+INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/MmcHost.inf
+INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/MmcMediaDevice.inf
+#
+# IDE/SCSI/AHCI
+#
+INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
+
+INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
+
+INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
+!if $(SATA_ENABLE) == TRUE
+INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/SataController.inf
+#
+
+#
+INF MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf
+INF MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf
+!if $(SCSI_ENABLE) == TRUE
+INF MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf
+INF MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf
+!endif
+#
+!endif
+# Console
+#
+INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
+INF Vlv2TbltDevicePkg/Override/MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
+INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf
+INF IntelFrameworkModulePkg/Universal/Console/VgaClassDxe/VgaClassDxe.inf
+INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
+INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
+INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
+INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
+  #
+  # USB
+  #
+!if $(USB_ENABLE) == TRUE
+INF MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf
+INF MdeModulePkg/Bus/Pci/UhciDxe/UhciDxe.inf
+INF MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
+INF MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf
+INF MdeModulePkg/Bus/Usb/UsbMouseDxe/UsbMouseDxe.inf
+INF MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
+INF MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf
+!endif
+
+  #
+  #  ECP
+  #
+INF EdkCompatibilityPkg/Compatibility/LegacyRegion2OnLegacyRegionThunk/LegacyRegion2OnLegacyRegionThunk.inf
+INF EdkCompatibilityPkg/Compatibility/SmmBaseOnSmmBase2Thunk/SmmBaseOnSmmBase2Thunk.inf
+INF EdkCompatibilityPkg/Compatibility/SmmBaseHelper/SmmBaseHelper.inf
+INF EdkCompatibilityPkg/Compatibility/SmmAccess2OnSmmAccessThunk/SmmAccess2OnSmmAccessThunk.inf
+INF EdkCompatibilityPkg/Compatibility/SmmControl2OnSmmControlThunk/SmmControl2OnSmmControlThunk.inf
+INF EdkCompatibilityPkg/Compatibility/FvOnFv2Thunk/FvOnFv2Thunk.inf
+  #
+  # SMBIOS
+  #
+INF MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf
+INF $(PLATFORM_PACKAGE)/SmBiosMiscDxe/SmBiosMiscDxe.inf
+
+INF RuleOverride = BINARY $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/SmbiosMemory.inf
+
+  #
+  # Legacy Modules
+  #
+INF PcAtChipsetPkg/8259InterruptControllerDxe/8259.inf
+
+#
+# FAT file system
+#
+FILE DRIVER = 961578FE-B6B7-44c3-AF35-6BC705CD2B1F {
+    SECTION PE32 = FatBinPkg/EnhancedFatDxe/$(EDK_DXE_ARCHITECTURE)/Fat.efi
+  }
+#
+# UEFI Shell
+#
+FILE APPLICATION = PCD(gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdShellFile) {
+#    SECTION PE32 = EdkShellBinPkg/FullShell/$(EDK_DXE_ARCHITECTURE)/Shell_Full.efi
+   SECTION PE32 = EdkShellBinPkg/MinimumShell/$(EDK_DXE_ARCHITECTURE)/Shell.efi
+  }
+
+
+
+!if $(GOP_DRIVER_ENABLE) == TRUE
+FILE FREEFORM = 878AC2CC-5343-46F2-B563-51F89DAF56BA {
+  SECTION RAW = Vlv2MiscBinariesPkg/GOP/7.2.1011/VBT/MNW2/Vbt.bin
+  SECTION UI = "IntelGopVbt"
+}
+!endif
+
+#
+# Network Modules
+#
+!if $(NETWORK_ENABLE) == TRUE
+  FILE DRIVER = 22DE1691-D65D-456a-993E-A253DD1F308C {
+    SECTION PE32 = Vlv2MiscBinariesPkg/UNDI/RtkUndiDxe/$(DXE_ARCHITECTURE)/RtkUndiDxe.efi
+    SECTION UI = "UNDI"
+  }
+  INF  MdeModulePkg/Universal/Network/SnpDxe/SnpDxe.inf
+  INF  MdeModulePkg/Universal/Network/DpcDxe/DpcDxe.inf
+  INF  MdeModulePkg/Universal/Network/MnpDxe/MnpDxe.inf
+  INF  MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf
+  INF  MdeModulePkg/Universal/Network/Ip4Dxe/Ip4Dxe.inf
+  INF  MdeModulePkg/Universal/Network/Ip4ConfigDxe/Ip4ConfigDxe.inf
+  INF  MdeModulePkg/Universal/Network/Udp4Dxe/Udp4Dxe.inf
+  INF  MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Dxe.inf
+  INF  MdeModulePkg/Universal/Network/Mtftp4Dxe/Mtftp4Dxe.inf
+  !if $(NETWORK_IP6_ENABLE) == TRUE
+  INF  NetworkPkg/Ip6Dxe/Ip6Dxe.inf
+  INF  NetworkPkg/Dhcp6Dxe/Dhcp6Dxe.inf
+  INF  NetworkPkg/IpSecDxe/IpSecDxe.inf
+  INF  NetworkPkg/Udp6Dxe/Udp6Dxe.inf
+  INF  NetworkPkg/Mtftp6Dxe/Mtftp6Dxe.inf
+  !endif
+  !if $(NETWORK_IP6_ENABLE) == TRUE
+  INF  NetworkPkg/UefiPxeBcDxe/UefiPxeBcDxe.inf
+  INF  NetworkPkg/TcpDxe/TcpDxe.inf
+  !else
+  INF  MdeModulePkg/Universal/Network/UefiPxeBcDxe/UefiPxeBcDxe.inf
+  INF  MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf
+  !endif
+  !if $(NETWORK_VLAN_ENABLE) == TRUE
+  INF  MdeModulePkg/Universal/Network/VlanConfigDxe/VlanConfigDxe.inf
+  !endif
+  !if $(NETWORK_ISCSI_ENABLE) == TRUE
+  !if $(NETWORK_IP6_ENABLE) == TRUE
+    INF  NetworkPkg/IScsiDxe/IScsiDxe.inf
+  !else
+    INF  MdeModulePkg/Universal/Network/IScsiDxe/IScsiDxe.inf
+  !endif
+  !endif
+!endif
+
+[FV.FVMAIN_COMPACT]
+BlockSize          = $(FLASH_BLOCK_SIZE)
+FvAlignment        = 16
+ERASE_POLARITY     = 1
+MEMORY_MAPPED      = TRUE
+STICKY_WRITE       = TRUE
+LOCK_CAP           = TRUE
+LOCK_STATUS        = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP  = TRUE
+WRITE_STATUS       = TRUE
+WRITE_LOCK_CAP     = TRUE
+WRITE_LOCK_STATUS  = TRUE
+READ_DISABLED_CAP  = TRUE
+READ_ENABLED_CAP   = TRUE
+READ_STATUS        = TRUE
+READ_LOCK_CAP      = TRUE
+READ_LOCK_STATUS   = TRUE
+
+
+
+FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 {
+!if $(LZMA_ENABLE) == TRUE
+# LZMA Compress
+       SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
+          SECTION FV_IMAGE = FVMAIN
+       }
+!else
+!if $(DXE_COMPRESS_ENABLE) == TRUE
+# Tiano Compress
+       SECTION GUIDED A31280AD-481E-41B6-95E8-127F4C984779 PROCESSING_REQUIRED = TRUE {
+          SECTION FV_IMAGE = FVMAIN
+       }
+!else
+# No Compress
+       SECTION COMPRESS PI_NONE {
+          SECTION FV_IMAGE = FVMAIN
+       }
+!endif
+!endif
+     }
+
+[FV.SETUP_DATA]
+BlockSize          = $(FLASH_BLOCK_SIZE)
+#NumBlocks         = 0x10
+FvAlignment        = 16
+ERASE_POLARITY     = 1
+MEMORY_MAPPED      = TRUE
+STICKY_WRITE       = TRUE
+LOCK_CAP           = TRUE
+LOCK_STATUS        = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP  = TRUE
+WRITE_STATUS       = TRUE
+WRITE_LOCK_CAP     = TRUE
+WRITE_LOCK_STATUS  = TRUE
+READ_DISABLED_CAP  = TRUE
+READ_ENABLED_CAP   = TRUE
+READ_STATUS        = TRUE
+READ_LOCK_CAP      = TRUE
+READ_LOCK_STATUS   = TRUE
+
+
+[FV.Update_Data]
+BlockSize          = $(FLASH_BLOCK_SIZE)
+FvAlignment        = 16
+ERASE_POLARITY     = 1
+MEMORY_MAPPED      = TRUE
+STICKY_WRITE       = TRUE
+LOCK_CAP           = TRUE
+LOCK_STATUS        = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP  = TRUE
+WRITE_STATUS       = TRUE
+WRITE_LOCK_CAP     = TRUE
+WRITE_LOCK_STATUS  = TRUE
+READ_DISABLED_CAP  = TRUE
+READ_ENABLED_CAP   = TRUE
+READ_STATUS        = TRUE
+READ_LOCK_CAP      = TRUE
+READ_LOCK_STATUS   = TRUE
+
+FILE RAW = 88888888-8888-8888-8888-888888888888 {
+       FD = Vlv
+     }
+
+[FV.BiosUpdateCargo]
+BlockSize          = $(FLASH_BLOCK_SIZE)
+FvAlignment        = 16
+ERASE_POLARITY     = 1
+MEMORY_MAPPED      = TRUE
+STICKY_WRITE       = TRUE
+LOCK_CAP           = TRUE
+LOCK_STATUS        = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP  = TRUE
+WRITE_STATUS       = TRUE
+WRITE_LOCK_CAP     = TRUE
+WRITE_LOCK_STATUS  = TRUE
+READ_DISABLED_CAP  = TRUE
+READ_ENABLED_CAP   = TRUE
+READ_STATUS        = TRUE
+READ_LOCK_CAP      = TRUE
+READ_LOCK_STATUS   = TRUE
+
+
+
+[FV.BiosUpdate]
+BlockSize          = $(FLASH_BLOCK_SIZE)
+FvAlignment        = 16
+ERASE_POLARITY     = 1
+MEMORY_MAPPED      = TRUE
+STICKY_WRITE       = TRUE
+LOCK_CAP           = TRUE
+LOCK_STATUS        = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP  = TRUE
+WRITE_STATUS       = TRUE
+WRITE_LOCK_CAP     = TRUE
+WRITE_LOCK_STATUS  = TRUE
+READ_DISABLED_CAP  = TRUE
+READ_ENABLED_CAP   = TRUE
+READ_STATUS        = TRUE
+READ_LOCK_CAP      = TRUE
+READ_LOCK_STATUS   = TRUE
+
+[Capsule.Capsule_Boot]
+#
+# gEfiCapsuleGuid supported by platform
+# { 0x3B6686BD, 0x0D76, 0x4030, { 0xB7, 0x0E, 0xB5, 0x51, 0x9E, 0x2F, 0xC5, 0xA0 }}
+#
+CAPSULE_GUID  = 3B6686BD-0D76-4030-B70E-B5519E2FC5A0
+CAPSULE_FLAGS = PersistAcrossReset
+CAPSULE_HEADER_SIZE = 0x20
+
+FV = BiosUpdate
+
+[Capsule.Capsule_Reset]
+#
+# gEfiCapsuleGuid supported by platform
+# { 0x3B6686BD, 0x0D76, 0x4030, { 0xB7, 0x0E, 0xB5, 0x51, 0x9E, 0x2F, 0xC5, 0xA0 }}
+#
+CAPSULE_GUID  = 3B6686BD-0D76-4030-B70E-B5519E2FC5A0
+CAPSULE_FLAGS = PersistAcrossReset
+CAPSULE_HEADER_SIZE = 0x20
+
+FV = BiosUpdate
+
+################################################################################
+#
+# Rules are use with the [FV] section's module INF type to define
+# how an FFS file is created for a given INF file. The following Rule are the default
+# rules for the different module type. User can add the customized rules to define the
+# content of the FFS file.
+#
+################################################################################
+[Rule.Common.SEC]
+  FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED {
+    PE32  PE32    Align = 8       $(INF_OUTPUT)/$(MODULE_NAME).efi
+    RAW BIN       Align = 16      |.com
+  }
+
+[Rule.Common.SEC.BINARY]
+  FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED {
+    PE32  PE32    Align = 8       |.efi
+    RAW BIN       Align = 16      |.com
+  }
+
+[Rule.Common.PEI_CORE]
+  FILE PEI_CORE = $(NAMED_GUID)            {
+    PE32       PE32    Align = Auto      $(INF_OUTPUT)/$(MODULE_NAME).efi
+    UI       STRING="$(MODULE_NAME)" Optional
+    VERSION  STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
+  }
+
+[Rule.Common.PEIM]
+  FILE PEIM = $(NAMED_GUID) {
+     PEI_DEPEX PEI_DEPEX Optional        $(INF_OUTPUT)/$(MODULE_NAME).depex
+     PE32        PE32   Align = Auto     $(INF_OUTPUT)/$(MODULE_NAME).efi
+     UI        STRING="$(MODULE_NAME)" Optional
+     VERSION   STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
+  }
+
+[Rule.Common.PEIM.BINARY]
+  FILE PEIM = $(NAMED_GUID) {
+     PEI_DEPEX PEI_DEPEX Optional        |.depex
+     PE32        PE32   Align = Auto     |.efi
+     UI        STRING="$(MODULE_NAME)" Optional
+     VERSION   STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
+  }
+
+[Rule.Common.PEIM.BIOSID]
+  FILE PEIM = $(NAMED_GUID) {
+     RAW       BIN                       BiosId.bin
+     PEI_DEPEX PEI_DEPEX Optional        $(INF_OUTPUT)/$(MODULE_NAME).depex
+     PE32        PE32   Align = Auto     $(INF_OUTPUT)/$(MODULE_NAME).efi
+     UI        STRING="$(MODULE_NAME)" Optional
+     VERSION   STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
+  }
+
+[Rule.Common.USER_DEFINED.APINIT]
+  FILE RAW = $(NAMED_GUID) Fixed Align=4K {
+     RAW SEC_BIN |.com
+     }
+#cjia 2011-07-21
+[Rule.Common.USER_DEFINED.LEGACY16]
+  FILE FREEFORM = $(NAMED_GUID) {
+     UI  STRING="$(MODULE_NAME)" Optional
+     RAW BIN |.bin
+     }
+#cjia
+
+[Rule.Common.USER_DEFINED.ASM16]
+  FILE FREEFORM = $(NAMED_GUID) {
+     UI  STRING="$(MODULE_NAME)" Optional
+     RAW BIN |.com
+   }
+
+[Rule.Common.DXE_CORE]
+  FILE DXE_CORE = $(NAMED_GUID) {
+    PE32      PE32                     $(INF_OUTPUT)/$(MODULE_NAME).efi
+    UI        STRING="$(MODULE_NAME)" Optional
+    VERSION   STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
+  }
+
+[Rule.Common.UEFI_DRIVER]
+  FILE DRIVER = $(NAMED_GUID) {
+    DXE_DEPEX DXE_DEPEX Optional       $(INF_OUTPUT)/$(MODULE_NAME).depex
+    PE32      PE32                     $(INF_OUTPUT)/$(MODULE_NAME).efi
+    UI        STRING="$(MODULE_NAME)" Optional
+    VERSION   STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
+  }
+
+[Rule.Common.UEFI_DRIVER.BINARY]
+  FILE DRIVER = $(NAMED_GUID) {
+    DXE_DEPEX DXE_DEPEX Optional       |.depex
+    PE32      PE32                     |.efi
+    UI        STRING="$(MODULE_NAME)" Optional
+    VERSION   STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
+  }
+
+[Rule.Common.UEFI_DRIVER.NATIVE_BINARY]
+  FILE DRIVER = $(NAMED_GUID) {
+    DXE_DEPEX DXE_DEPEX Optional      $(WORKSPACE)/$(PLATFORM_PACKAGE)/IntelGopDepex/IntelGopDriver.depex
+    PE32      PE32                    |.efi
+    UI        STRING="$(MODULE_NAME)" Optional
+    VERSION   STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
+  }
+
+[Rule.Common.DXE_DRIVER]
+  FILE DRIVER = $(NAMED_GUID) {
+    DXE_DEPEX DXE_DEPEX Optional       $(INF_OUTPUT)/$(MODULE_NAME).depex
+    PE32      PE32                     $(INF_OUTPUT)/$(MODULE_NAME).efi
+    UI        STRING="$(MODULE_NAME)" Optional
+    VERSION   STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
+  }
+
+[Rule.Common.DXE_DRIVER.BINARY]
+  FILE DRIVER = $(NAMED_GUID) {
+    DXE_DEPEX DXE_DEPEX Optional       |.depex
+    PE32      PE32                     |.efi
+    UI        STRING="$(MODULE_NAME)" Optional
+    VERSION   STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
+  }
+
+[Rule.Common.DXE_DRIVER.DRIVER_ACPITABLE]
+  FILE DRIVER = $(NAMED_GUID) {
+    DXE_DEPEX DXE_DEPEX Optional       $(INF_OUTPUT)/$(MODULE_NAME).depex
+    PE32      PE32                     $(INF_OUTPUT)/$(MODULE_NAME).efi
+    UI        STRING="$(MODULE_NAME)" Optional
+    VERSION   STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
+    RAW ACPI  Optional                |.acpi
+    RAW ASL   Optional                |.aml
+  }
+
+[Rule.Common.DXE_RUNTIME_DRIVER]
+  FILE DRIVER = $(NAMED_GUID) {
+    DXE_DEPEX DXE_DEPEX Optional       $(INF_OUTPUT)/$(MODULE_NAME).depex
+    PE32      PE32                     $(INF_OUTPUT)/$(MODULE_NAME).efi
+    UI        STRING="$(MODULE_NAME)" Optional
+    VERSION   STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
+  }
+
+[Rule.Common.DXE_RUNTIME_DRIVER.BINARY]
+  FILE DRIVER = $(NAMED_GUID) {
+    DXE_DEPEX DXE_DEPEX Optional       |.depex
+    PE32      PE32                     |.efi
+    UI        STRING="$(MODULE_NAME)" Optional
+    VERSION   STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
+  }
+
+[Rule.Common.DXE_SMM_DRIVER]
+  FILE SMM = $(NAMED_GUID) {
+    DXE_DEPEX DXE_DEPEX Optional       $(INF_OUTPUT)/$(MODULE_NAME).depex
+    PE32      PE32                     $(INF_OUTPUT)/$(MODULE_NAME).efi
+    UI        STRING="$(MODULE_NAME)" Optional
+    VERSION   STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
+  }
+
+[Rule.Common.DXE_SMM_DRIVER.BINARY]
+  FILE SMM = $(NAMED_GUID) {
+    SMM_DEPEX SMM_DEPEX                |.depex
+    PE32      PE32                     |.efi
+    UI        STRING="$(MODULE_NAME)" Optional
+    VERSION   STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
+  }
+
+[Rule.Common.DXE_SMM_DRIVER.DRIVER_ACPITABLE]
+  FILE SMM = $(NAMED_GUID) {
+    DXE_DEPEX DXE_DEPEX Optional       $(INF_OUTPUT)/$(MODULE_NAME).depex
+    PE32      PE32                     $(INF_OUTPUT)/$(MODULE_NAME).efi
+    UI        STRING="$(MODULE_NAME)" Optional
+    VERSION   STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
+    RAW ACPI  Optional                |.acpi
+    RAW ASL   Optional                |.aml
+  }
+
+[Rule.Common.SMM_CORE]
+  FILE SMM_CORE = $(NAMED_GUID) {
+    DXE_DEPEX DXE_DEPEX Optional       $(INF_OUTPUT)/$(MODULE_NAME).depex
+    PE32      PE32                     $(INF_OUTPUT)/$(MODULE_NAME).efi
+    UI        STRING="$(MODULE_NAME)" Optional
+    VERSION   STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
+  }
+
+[Rule.Common.SMM_CORE.BINARY]
+  FILE SMM_CORE = $(NAMED_GUID) {
+    DXE_DEPEX DXE_DEPEX Optional       |.depex
+    PE32      PE32                     |.efi
+    UI        STRING="$(MODULE_NAME)" Optional
+    VERSION   STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
+  }
+
+[Rule.Common.UEFI_APPLICATION]
+  FILE APPLICATION = $(NAMED_GUID) {
+    DXE_DEPEX DXE_DEPEX Optional       $(INF_OUTPUT)/$(MODULE_NAME).depex
+    PE32      PE32                     $(INF_OUTPUT)/$(MODULE_NAME).efi
+    UI        STRING="$(MODULE_NAME)" Optional
+    VERSION   STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
+  }
+
+[Rule.Common.UEFI_APPLICATION.UI]
+  FILE APPLICATION = $(NAMED_GUID) {
+    PE32      PE32                     $(INF_OUTPUT)/$(MODULE_NAME).efi
+    UI        STRING="Enter Setup"
+    VERSION   STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
+  }
+
+[Rule.Common.USER_DEFINED]
+  FILE FREEFORM = $(NAMED_GUID) {
+    UI  STRING="$(MODULE_NAME)" Optional
+    RAW BIN                |.bin
+  }
+
+[Rule.Common.USER_DEFINED.ACPITABLE]
+  FILE FREEFORM = $(NAMED_GUID) {
+    RAW ACPI  Optional            |.acpi
+    RAW ASL   Optional            |.aml
+  }
+
+[Rule.Common.USER_DEFINED.ACPITABLE2]
+  FILE FREEFORM = $(NAMED_GUID) {
+    RAW ASL   Optional            |.aml
+  }
+
+[Rule.Common.ACPITABLE]
+  FILE FREEFORM = $(NAMED_GUID) {
+    RAW ACPI  Optional            |.acpi
+    RAW ASL   Optional            |.aml
+  }
+

diff --git a/Vlv2TbltDevicePkg/PlatformPkgGccX64.dsc b/Vlv2TbltDevicePkg/PlatformPkgGccX64.dsc
new file mode 100644 (file)
index 0000000..7963855
--- /dev/null
+++ b/Vlv2TbltDevicePkg/PlatformPkgGccX64.dsc
@@ -0,0 +1,1492 @@
+#/** @file
+# Platform description.
+#
+# Copyright (c) 2012  - 2014, Intel Corporation. All rights reserved.<BR>
+#                                                                                  
+# This program and the accompanying materials are licensed and made available under
+# the terms and conditions of the BSD License that accompanies this distribution.  
+# The full text of the license may be found at                                     
+# http://opensource.org/licenses/bsd-license.php.                                  
+#                                                                                  
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    
+#                                                                                  
+#
+#**/
+
+################################################################################
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+################################################################################
+[Defines]
+  PLATFORM_NAME                       = Vlv2TbltDevicePkg
+  PLATFORM_GUID                       = 465B0A0B-7AC1-443b-8F67-7B8DEC145F90
+  PLATFORM_VERSION                    = 0.1
+  DSC_SPECIFICATION                   = 0x00010005
+
+  #
+  # Set platform specific package/folder name, same as passed from PREBUILD script.
+  # PLATFORM_PACKAGE would be the same as PLATFORM_NAME as well as package build folder
+  # DEFINE only takes effect at R9 DSC and FDF.
+  #
+  DEFINE      PLATFORM_PACKAGE                = Vlv2TbltDevicePkg
+  DEFINE      PLATFORM_RC_PACKAGE             = Vlv2DeviceRefCodePkg
+  DEFINE      PLATFORM_BINARY_PACKAGE         = Vlv2BinaryPkg
+  OUTPUT_DIRECTORY                    = Build/$(PLATFORM_PACKAGE)
+  SUPPORTED_ARCHITECTURES             = IA32|X64
+  BUILD_TARGETS                       = DEBUG|RELEASE
+  SKUID_IDENTIFIER                    = DEFAULT
+
+  DEFINE CPU_ARCH                 =ValleyView2
+  DEFINE PROJECT_SC_FAMILY        =IntelPch
+  DEFINE PROJECT_SC_ROOT          =../$(PLATFORM_RC_PACKAGE)/ValleyView2Soc/SouthCluster
+  DEFINE PROJECT_VLV_ROOT          =../$(PLATFORM_RC_PACKAGE)/ValleyView2Soc/NorthCluster
+
+  DEFINE RC_BINARY_RELEASE        = TRUE
+  #
+  # Platform On/Off features are defined here
+  #
+  #
+  # Platform Support:: Set only one token except Crestview Hills
+  #
+  #   3.BayleyBay
+  #     ENBDT_PF_ENABLE  = TRUE
+  #
+  !include $(PLATFORM_PACKAGE)/AutoPlatformCFG.txt
+  !include $(PLATFORM_PACKAGE)/PlatformPkgConfig.dsc
+
+!if $(X64_CONFIG) == TRUE
+  DEFINE      DXE_ARCHITECTURE        = X64
+  DEFINE      EDK_DXE_ARCHITECTURE    = X64
+  DEFINE      UNDI_DXE_ARCHITECTURE   = 64
+!else
+  DEFINE      DXE_ARCHITECTURE        = IA32
+  DEFINE      EDK_DXE_ARCHITECTURE    = Ia32
+  DEFINE      UNDI_DXE_ARCHITECTURE   = 32
+!endif
+
+  FLASH_DEFINITION                    = $(PLATFORM_PACKAGE)/PlatformPkgGcc.fdf
+!if $(LFMA_ENABLE) == TRUE
+  FIX_LOAD_TOP_MEMORY_ADDRESS         = 0xFFFFFFFFFFFFFFFF
+  DEFINE   TOP_MEMORY_ADDRESS         = 0xFFFFFFFFFFFFFFFF
+!else
+  FIX_LOAD_TOP_MEMORY_ADDRESS         = 0x0
+  DEFINE   TOP_MEMORY_ADDRESS         = 0x0
+!endif
+
+  DEFINE   PLATFORM_PCIEXPRESS_BASE   = 0E0000000
+
+
+################################################################################
+#
+# SKU Identification section - list of all SKU IDs supported by this
+#                              Platform.
+#
+################################################################################
+[SkuIds]
+  0|DEFAULT              # The entry: 0|DEFAULT is reserved and always required.
+
+################################################################################
+#
+# Library Class section - list of all Library Classes needed by this Platform.
+#
+################################################################################
+[LibraryClasses.common]
+  #
+  # Entry point
+  #
+  PeiCoreEntryPoint|MdePkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.inf
+  PeimEntryPoint|MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf
+  DxeCoreEntryPoint|MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf
+  UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf
+  UefiApplicationEntryPoint|MdePkg/Library/UefiApplicationEntryPoint/UefiApplicationEntryPoint.inf
+  DxeSmmDriverEntryPoint|IntelFrameworkPkg/Library/DxeSmmDriverEntryPoint/DxeSmmDriverEntryPoint.inf
+
+  #
+  # Basic
+  #
+  BaseLib|MdePkg/Library/BaseLib/BaseLib.inf
+!if $(SSE2_ENABLE) == TRUE
+  BaseMemoryLib|MdePkg/Library/BaseMemoryLibSse2/BaseMemoryLibSse2.inf
+!else
+  BaseMemoryLib|MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf
+!endif
+  PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf
+  CpuLib|MdePkg/Library/BaseCpuLib/BaseCpuLib.inf
+  IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf
+  PciLib|MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf
+  PciCf8Lib|MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf
+  PciExpressLib|MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf
+  CacheMaintenanceLib|MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf
+  PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
+  PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf
+!if $(RC_BINARY_RELEASE) == TRUE
+  PchPlatformLib|Vlv2TbltDevicePkg/Library/PchPlatformLib/PchPlatformLib.inf
+!endif
+  #
+  # UEFI & PI
+  #
+  UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf
+  UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf
+  UefiRuntimeLib|MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf
+  UefiLib|MdePkg/Library/UefiLib/UefiLib.inf
+  HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf
+  UefiHiiServicesLib|MdeModulePkg/Library/UefiHiiServicesLib/UefiHiiServicesLib.inf
+  DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf
+  UefiDecompressLib|IntelFrameworkModulePkg/Library/BaseUefiTianoCustomDecompressLib/BaseUefiTianoCustomDecompressLib.inf
+  PeiServicesTablePointerLib|MdePkg/Library/PeiServicesTablePointerLibIdt/PeiServicesTablePointerLibIdt.inf
+  PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf
+  DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
+  DxeServicesTableLib|MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf
+  UefiCpuLib|UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.inf
+  UefiUsbLib|MdePkg/Library/UefiUsbLib/UefiUsbLib.inf
+  GenericBdsLib|$(PLATFORM_PACKAGE)/Override/IntelFrameworkModulePkg/Library/GenericBdsLib/GenericBdsLib.inf
+  PlatformBdsLib|$(PLATFORM_PACKAGE)/Library/PlatformBdsLib/PlatformBdsLib.inf
+  NetLib|MdeModulePkg/Library/DxeNetLib/DxeNetLib.inf
+  DpcLib|MdeModulePkg/Library/DxeDpcLib/DxeDpcLib.inf
+  FlashDeviceLib|$(PLATFORM_PACKAGE)/Library/FlashDeviceLib/FlashDeviceLib.inf
+  #
+  # Framework
+  #
+!if $(S3_ENABLE) == TRUE
+  S3BootScriptLib|MdeModulePkg/Library/PiDxeS3BootScriptLib/DxeS3BootScriptLib.inf
+!else
+  S3BootScriptLib|MdePkg/Library/BaseS3BootScriptLibNull/BaseS3BootScriptLibNull.inf
+!endif
+  S3IoLib|MdePkg/Library/BaseS3IoLib/BaseS3IoLib.inf
+  S3PciLib|MdePkg/Library/BaseS3PciLib/BaseS3PciLib.inf
+
+  #
+  # Generic Modules
+  #
+!if $(USB_ENABLE) == TRUE
+  UefiUsbLib|MdePkg/Library/UefiUsbLib/UefiUsbLib.inf
+!endif
+!if $(SCSI_ENABLE) == TRUE
+  UefiScsiLib|MdePkg/Library/UefiScsiLib/UefiScsiLib.inf
+!endif
+!if $(NETWORK_ENABLE) == TRUE
+  NetLib|MdeModulePkg/Library/DxeNetLib/DxeNetLib.inf
+  IpIoLib|MdeModulePkg/Library/DxeIpIoLib/DxeIpIoLib.inf
+  UdpIoLib|MdeModulePkg/Library/DxeUdpIoLib/DxeUdpIoLib.inf
+  TcpIoLib|MdeModulePkg/Library/DxeTcpIoLib/DxeTcpIoLib.inf
+  DpcLib|MdeModulePkg/Library/DxeDpcLib/DxeDpcLib.inf
+!endif
+!if $(S3_ENABLE) == TRUE
+  S3Lib|IntelFrameworkModulePkg/Library/PeiS3Lib/PeiS3Lib.inf
+!endif
+
+  OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.inf
+!if $(CAPSULE_ENABLE) == TRUE
+ CapsuleLib|IntelFrameworkModulePkg/Library/DxeCapsuleLib/DxeCapsuleLib.inf
+!else
+  CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf
+!endif
+  LanguageLib|EdkCompatibilityPkg/Compatibility/Library/UefiLanguageLib/UefiLanguageLib.inf
+  SynchronizationLib|MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf
+  SecurityManagementLib|MdeModulePkg/Library/DxeSecurityManagementLib/DxeSecurityManagementLib.inf
+  IoApicLib|PcAtChipsetPkg/Library/BaseIoApicLib/BaseIoApicLib.inf
+  DebugPrintErrorLevelLib|MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.inf
+
+  #
+  # CPU
+  #
+  MtrrLib|UefiCpuPkg/Library/MtrrLib/MtrrLib.inf
+  LocalApicLib|UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.inf
+  CpuExceptionHandlerLib|MdeModulePkg/Library/CpuExceptionHandlerLibNull/CpuExceptionHandlerLibNull.inf
+
+  #
+  # ICH
+  #
+  SmbusLib|$(PLATFORM_PACKAGE)/Library/SmbusLib/SmbusLib.inf
+  SmmLib|$(PLATFORM_PACKAGE)/Library/PchSmmLib/PchSmmLib.inf
+
+  #
+  # Platform
+  #
+  TimerLib|$(PLATFORM_PACKAGE)/Library/IntelPchAcpiTimerLib/IntelPchAcpiTimerLib.inf
+  ResetSystemLib|$(PLATFORM_PACKAGE)/Library/ResetSystemLib/ResetSystemLib.inf
+
+  PlatformCmosLib|$(PLATFORM_PACKAGE)/Library/PlatformCmosLib/PlatformCmosLib.inf
+
+  #
+  # Misc
+  #
+  MonoStatusCodeLib|$(PLATFORM_PACKAGE)/MonoStatusCode/MonoStatusCode.inf
+!if $(TARGET) == RELEASE
+  DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf
+  SerialPortLib|MdePkg/Library/BaseSerialPortLibNull/BaseSerialPortLibNull.inf
+!else
+  DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf
+  SerialPortLib|MdePkg/Library/BaseSerialPortLibNull/BaseSerialPortLibNull.inf
+!endif
+
+  PerformanceLib|MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibNull.inf
+  PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
+!if $(TPM_ENABLED) == TRUE
+  TpmCommLib|SecurityPkg/Library/TpmCommLib/TpmCommLib.inf
+  Tpm12CommandLib|SecurityPkg/Library/Tpm12CommandLib/Tpm12CommandLib.inf
+  Tpm12DeviceLib|SecurityPkg/Library/Tpm12DeviceLibDTpm/Tpm12DeviceLibDTpm.inf
+
+!endif
+
+!if $(SOURCE_DEBUG_ENABLE) == TRUE
+  PeCoffExtraActionLib|SourceLevelDebugPkg/Library/PeCoffExtraActionLibDebug/PeCoffExtraActionLibDebug.inf
+  DebugCommunicationLib|SourceLevelDebugPkg/Library/DebugCommunicationLibSerialPort/DebugCommunicationLibSerialPort.inf
+  PlatformHookLib|MdeModulePkg/Library/BasePlatformHookLibNull/BasePlatformHookLibNull.inf
+  SerialPortLib|MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.inf
+!else
+  PeCoffExtraActionLib|MdePkg/Library/BasePeCoffExtraActionLibNull/BasePeCoffExtraActionLibNull.inf
+  DebugAgentLib|MdeModulePkg/Library/DebugAgentLibNull/DebugAgentLibNull.inf
+!endif
+
+  #
+  # CryptLib
+  #
+!if $(TPM_ENABLED) == TRUE
+  IntrinsicLib|CryptoPkg/Library/IntrinsicLib/IntrinsicLib.inf
+  OpensslLib|CryptoPkg/Library/OpensslLib/OpensslLib.inf
+!endif
+
+ BiosIdLib|$(PLATFORM_PACKAGE)/Library/BiosIdLib/BiosIdLib.inf
+ CpuIA32Lib|$(PLATFORM_PACKAGE)/Library/CpuIA32Lib/CpuIA32Lib.inf
+
+  StallSmmLib|$(PLATFORM_PACKAGE)/Library/StallSmmLib/StallSmmLib.inf
+
+ !if $(SECURE_BOOT_ENABLE) == TRUE
+   OpensslLib|CryptoPkg/Library/OpensslLib/OpensslLib.inf
+   IntrinsicLib|CryptoPkg/Library/IntrinsicLib/IntrinsicLib.inf
+   PlatformSecureLib|SecurityPkg/Library/PlatformSecureLibNull/PlatformSecureLibNull.inf
+ !endif
+!if $(RC_BINARY_RELEASE) == TRUE
+  I2cLib|Vlv2TbltDevicePkg/Library/I2CLib/I2CLibNull.inf
+!endif
+  ShellCEntryLib|ShellPkg/Library/UefiShellCEntryLib/UefiShellCEntryLib.inf
+  ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf
+  FileHandleLib|ShellPkg/Library/UefiFileHandleLib/UefiFileHandleLib.inf
+  SortLib|ShellPkg/Library/UefiSortLib/UefiSortLib.inf
+
+  TpmMeasurementLib|SecurityPkg/Library/DxeTpmMeasurementLib/DxeTpmMeasurementLib.inf
+  TrEEPhysicalPresenceLib|SecurityPkg/Library/DxeTrEEPhysicalPresenceLib/DxeTrEEPhysicalPresenceLib.inf
+  Tpm2CommandLib|SecurityPkg/Library/Tpm2CommandLib/Tpm2CommandLib.inf
+!if $(MINNOW2_FSP_BUILD) == TRUE
+  FspApiLib|IntelFspWrapperPkg/Library/BaseFspApiLib/BaseFspApiLib.inf
+  FspPlatformInfoLib|IntelFspWrapperPkg/Library/BaseFspPlatformInfoLibSample/BaseFspPlatformInfoLibSample.inf
+  FspPlatformSecLib|Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecLibVlv2/FspPlatformSecLibVlv2.inf
+  FspHobProcessLib|Vlv2TbltDevicePkg/FspSupport/Library/PeiFspHobProcessLibVlv2/FspHobProcessLibVlv2.inf
+!endif
+
+[LibraryClasses.IA32.SEC]
+!if $(PERFORMANCE_ENABLE) == TRUE
+  PerformanceLib|MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibNull.inf
+!endif
+  DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf
+  PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
+
+[LibraryClasses.IA32.PEIM, LibraryClasses.IA32.PEI_CORE, LibraryClasses.IA32.SEC]
+  #
+  # PEI phase common
+  #
+
+  PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
+  HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf
+  MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf
+  ReportStatusCodeLib|MdeModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf
+  ExtractGuidedSectionLib|MdePkg/Library/PeiExtractGuidedSectionLib/PeiExtractGuidedSectionLib.inf
+  MultiPlatformLib|$(PLATFORM_PACKAGE)/Library/MultiPlatformLib/MultiPlatformLib.inf
+  BaseCryptLib|CryptoPkg/Library/BaseCryptLib/PeiCryptLib.inf
+
+
+!if $(PERFORMANCE_ENABLE) == TRUE
+  PerformanceLib|MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanceLib.inf
+  TimerLib|PerformancePkg/Library/TscTimerLib/PeiTscTimerLib.inf
+!endif
+
+!if $(TARGET) == RELEASE
+  DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf
+  SerialPortLib|MdePkg/Library/BaseSerialPortLibNull/BaseSerialPortLibNull.inf
+!else
+  DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf
+  SerialPortLib|MdePkg/Library/BaseSerialPortLibNull/BaseSerialPortLibNull.inf
+!endif
+
+  LockBoxLib|MdeModulePkg/Library/SmmLockBoxLib/SmmLockBoxPeiLib.inf
+  HashLib|SecurityPkg/Library/HashLibBaseCryptoRouter/HashLibBaseCryptoRouterPei.inf
+  PeCoffExtraActionLib|MdePkg/Library/BasePeCoffExtraActionLibNull/BasePeCoffExtraActionLibNull.inf
+  DebugAgentLib|MdeModulePkg/Library/DebugAgentLibNull/DebugAgentLibNull.inf
+
+ !if $(MINNOW2_FSP_BUILD) == TRUE
+ PlatformFspLib|Vlv2TbltDevicePkg/Library/PlatformFspLib/PlatformFspLib.inf
+ !endif
+
+
+
+[LibraryClasses.X64]
+  #
+  # DXE phase common
+  #
+  HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
+  PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
+  MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
+  ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeReportStatusCodeLib.inf
+  ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf
+
+  TcgPhysicalPresenceLib|SecurityPkg/Library/DxeTcgPhysicalPresenceLib/DxeTcgPhysicalPresenceLib.inf
+!if $(TPM_ENABLED) == TRUE
+  BaseCryptLib|CryptoPkg/Library/BaseCryptLib/BaseCryptLib.inf
+!endif
+
+  LockBoxLib|MdeModulePkg/Library/SmmLockBoxLib/SmmLockBoxDxeLib.inf
+  EfiRegTableLib|$(PLATFORM_PACKAGE)/Library/EfiRegTableLib/EfiRegTableLib.inf
+
+!if $(SECURE_BOOT_ENABLE) == TRUE
+  BaseCryptLib|CryptoPkg/Library/BaseCryptLib/BaseCryptLib.inf
+!endif
+
+  HashLib|SecurityPkg/Library/HashLibBaseCryptoRouter/HashLibBaseCryptoRouterDxe.inf
+
+[LibraryClasses.X64.DXE_DRIVER]
+  DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf
+  PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
+  PerformanceLib|MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibNull.inf
+  CustomizedDisplayLib|MdeModulePkg/Library/CustomizedDisplayLib/CustomizedDisplayLib.inf
+!if $(PERFORMANCE_ENABLE) == TRUE
+  PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf
+  TimerLib|PerformancePkg/Library/TscTimerLib/DxeTscTimerLib.inf
+!endif
+
+!if $(SOURCE_DEBUG_ENABLE) == TRUE
+  DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/DxeDebugAgentLib.inf
+!endif
+
+[LibraryClasses.X64.DXE_CORE]
+  HobLib|MdePkg/Library/DxeCoreHobLib/DxeCoreHobLib.inf
+  MemoryAllocationLib|MdeModulePkg/Library/DxeCoreMemoryAllocationLib/DxeCoreMemoryAllocationLib.inf
+  PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
+!if $(PERFORMANCE_ENABLE) == TRUE
+  PerformanceLib|MdeModulePkg/Library/DxeCorePerformanceLib/DxeCorePerformanceLib.inf
+  TimerLib|PerformancePkg/Library/TscTimerLib/DxeTscTimerLib.inf
+!endif
+
+!if $(SOURCE_DEBUG_ENABLE) == TRUE
+  DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/DxeDebugAgentLib.inf
+!endif
+
+[LibraryClasses.X64.DXE_SMM_DRIVER]
+  SmmServicesTableLib|MdePkg/Library/SmmServicesTableLib/SmmServicesTableLib.inf
+  ReportStatusCodeLib|MdeModulePkg/Library/SmmReportStatusCodeLib/SmmReportStatusCodeLib.inf
+  MemoryAllocationLib|MdePkg/Library/SmmMemoryAllocationLib/SmmMemoryAllocationLib.inf
+  LockBoxLib|MdeModulePkg/Library/SmmLockBoxLib/SmmLockBoxSmmLib.inf
+  PerformanceLib|MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibNull.inf
+
+  BaseCryptLib|CryptoPkg/Library/BaseCryptLib/SmmCryptLib.inf
+  !if $(TARGET) != RELEASE
+  DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf
+  !endif
+
+!if $(SOURCE_DEBUG_ENABLE) == TRUE
+  DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/SmmDebugAgentLib.inf
+  TimerLib|$(PLATFORM_PACKAGE)/Library/IntelPchAcpiTimerLib/IntelPchAcpiTimerLib.inf
+!endif
+  CpuExceptionHandlerLib|UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmCpuExceptionHandlerLib.inf
+
+[LibraryClasses.X64.SMM_CORE]
+  MemoryAllocationLib|MdeModulePkg/Library/PiSmmCoreMemoryAllocationLib/PiSmmCoreMemoryAllocationLib.inf
+  SmmServicesTableLib|MdeModulePkg/Library/PiSmmCoreSmmServicesTableLib/PiSmmCoreSmmServicesTableLib.inf
+  ReportStatusCodeLib|MdeModulePkg/Library/SmmReportStatusCodeLib/SmmReportStatusCodeLib.inf
+  SmmCorePlatformHookLib|MdeModulePkg/Library/SmmCorePlatformHookLibNull/SmmCorePlatformHookLibNull.inf
+
+!if $(TPM_ENABLED) == TRUE
+  BaseCryptLib|CryptoPkg/Library/BaseCryptLib/SmmCryptLib.inf
+!endif
+
+  PerformanceLib|MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibNull.inf
+
+!if $(TARGET) != RELEASE
+      DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf
+!endif
+
+!if $(SOURCE_DEBUG_ENABLE) == TRUE
+  DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/DxeDebugAgentLib.inf
+  TimerLib|$(PLATFORM_PACKAGE)/Library/IntelPchAcpiTimerLib/IntelPchAcpiTimerLib.inf
+!endif
+
+[LibraryClasses.X64.DXE_RUNTIME_DRIVER]
+  ReportStatusCodeLib|MdeModulePkg/Library/RuntimeDxeReportStatusCodeLib/RuntimeDxeReportStatusCodeLib.inf
+!if $(SECURE_BOOT_ENABLE) == TRUE
+  BaseCryptLib|CryptoPkg/Library/BaseCryptLib/RuntimeCryptLib.inf
+!endif
+!if $(TPM_ENABLED) == TRUE
+  BaseCryptLib|CryptoPkg/Library/BaseCryptLib/RuntimeCryptLib.inf
+!endif
+
+!if $(SOURCE_DEBUG_ENABLE) == TRUE
+  DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/DxeDebugAgentLib.inf
+!endif
+
+[LibraryClasses.common.UEFI_DRIVER]
+  PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
+
+!if $(SOURCE_DEBUG_ENABLE) == TRUE
+  DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/DxeDebugAgentLib.inf
+!endif
+
+[LibraryClasses.X64.UEFI_APPLICATION]
+  PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
+
+!if $(SOURCE_DEBUG_ENABLE) == TRUE
+  DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/DxeDebugAgentLib.inf
+!endif
+
+
+################################################################################
+#
+# Library Section - list of all EDK/Framework libraries
+#
+################################################################################
+[Libraries.common]
+  EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/BaseLib/BaseLib.inf
+  EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/BaseMemoryLib/BaseMemoryLib.inf
+  EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/BasePrintLib/BasePrintLib.inf
+  EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/BaseDebugLibNull/BaseDebugLibNull.inf
+  EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf
+  EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf
+  EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/BasePciCf8Lib/BasePciCf8Lib.inf
+  EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/BasePciExpressLib/BasePciExpressLib.inf
+  EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/BasePciLibCf8/BasePciLibCf8.inf
+  EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf
+  EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf
+  EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/BasePeCoffLib/BasePeCoffLib.inf
+  EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/SmmRuntimeDxeReportStatusCodeLib/SmmRuntimeDxeReportStatusCodeLib.inf
+  EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/PeiHobLib/PeiHobLib.inf
+  EdkCompatibilityPkg/Foundation/Ppi/EdkPpiLib.inf
+  EdkCompatibilityPkg/Foundation/Library/Pei/PeiLib/PeiLib.inf
+  EdkCompatibilityPkg/Compatibility/Library/UefiLanguageLib/UefiLanguageLib.inf
+  EdkCompatibilityPkg/Foundation/Guid/EdkGuidLib.inf
+  EdkCompatibilityPkg/Foundation/Efi/Protocol/EfiProtocolLib.inf
+  EdkCompatibilityPkg/Foundation/Library/Dxe/EfiDriverLib/EfiDriverLib.inf
+  EdkCompatibilityPkg/Foundation/Protocol/EdkProtocolLib.inf
+  EdkCompatibilityPkg/Foundation/Framework/Protocol/EdkFrameworkProtocolLib.inf
+[Libraries.IA32]
+  EdkCompatibilityPkg/Foundation/Efi/Guid/EfiGuidLib.inf
+  EdkCompatibilityPkg/Foundation/Framework/Guid/EdkFrameworkGuidLib.inf
+  EdkCompatibilityPkg/Foundation/Library/EfiCommonLib/EfiCommonLib.inf
+  EdkCompatibilityPkg/Foundation/Cpu/Pentium/CpuIA32Lib/CpuIA32Lib.inf
+  EdkCompatibilityPkg/Foundation/Library/CompilerStub/CompilerStubLib.inf
+  EdkCompatibilityPkg/Foundation/Framework/Ppi/EdkFrameworkPpiLib.inf
+  EdkCompatibilityPkg/Foundation/Library/Pei/Hob/PeiHobLib.inf
+  EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/PeiServicesTablePointerLibMm7/PeiServicesTablePointerLibMm7.inf
+  EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf
+  EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/PeiServicesLib/PeiServicesLib.inf
+  EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf
+  EdkCompatibilityPkg/Foundation/Core/Dxe/ArchProtocol/ArchProtocolLib.inf
+
+  $(PLATFORM_PACKAGE)/Library/MultiPlatformLib/MultiPlatformLib.inf
+[Libraries.X64]
+
+  EdkCompatibilityPkg/Foundation/Efi/Guid/EfiGuidLib.inf
+  EdkCompatibilityPkg/Foundation/Framework/Guid/EdkFrameworkGuidLib.inf
+  EdkCompatibilityPkg/Foundation/Library/EfiCommonLib/EfiCommonLib.inf
+  EdkCompatibilityPkg/Foundation/Cpu/Pentium/CpuIA32Lib/CpuIA32Lib.inf
+  EdkCompatibilityPkg/Foundation/Library/CompilerStub/CompilerStubLib.inf
+  EdkCompatibilityPkg/Foundation/Framework/Ppi/EdkFrameworkPpiLib.inf
+  EdkCompatibilityPkg/Foundation/Core/Dxe/ArchProtocol/ArchProtocolLib.inf
+  EdkCompatibilityPkg/Foundation/Library/Dxe/Hob/HobLib.inf
+  EdkCompatibilityPkg/Foundation/Library/RuntimeDxe/EfiRuntimeLib/EfiRuntimeLib.inf
+  EdkCompatibilityPkg/Foundation/Library/Dxe/EfiIfrSupportLib/EfiIfrSupportLib.inf
+  EdkCompatibilityPkg/Foundation/Library/Dxe/Print/PrintLib.inf
+  EdkCompatibilityPkg/Foundation/Library/Dxe/EfiScriptLib/EfiScriptLib.inf
+  EdkCompatibilityPkg/Foundation/Library/Dxe/PrintLite/PrintLib.inf
+  EdkCompatibilityPkg/Foundation/Library/Dxe/GraphicsLite/Graphics.inf
+  EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf
+  EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/DxeMemoryAllocationLib/DxeMemoryAllocationLib.inf
+  EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/UefiLib/UefiLib.inf
+  EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/DxeHobLib/DxeHobLib.inf
+  EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf
+  EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/DxeReportStatusCodeLib/DxeReportStatusCodeLib.inf
+  EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/HiiLib/HiiLib.inf
+  EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/UefiDevicePathLib/UefiDevicePathLib.inf
+  EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/UefiDriverModelLib/UefiDriverModelLib.inf
+  EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/DxeServicesTableLib/DxeServicesTableLib.inf
+  EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/EdkDxeRuntimeDriverLib/EdkDxeRuntimeDriverLib.inf
+
+
+################################################################################
+#
+# Pcd Section - list of all EDK II PCD Entries defined by this Platform
+#
+################################################################################
+[PcdsFeatureFlag.common]
+!if $(MINI_BIOS_ENABLE) == FALSE
+  gPlatformModuleTokenSpaceGuid.PcdBdsDispatchAdditionalOprom|TRUE
+!else
+  gPlatformModuleTokenSpaceGuid.PcdBdsDispatchAdditionalOprom|FALSE
+!endif
+#
+# If PcdDxeIplSwitchToLongMode is TRUE, DxeIpl will load a 64-bit DxeCore and switch to long mode to hand over to DxeCore.
+#
+  gEfiMdeModulePkgTokenSpaceGuid.PcdDxeIplSwitchToLongMode|TRUE
+
+  gEfiMdeModulePkgTokenSpaceGuid.PcdBrowserGrayOutTextStatement|TRUE
+
+!if $(CAPSULE_RESET_ENABLE) == TRUE
+  gEfiMdeModulePkgTokenSpaceGuid.PcdSupportUpdateCapsuleReset|TRUE
+!else
+  gEfiMdeModulePkgTokenSpaceGuid.PcdSupportUpdateCapsuleReset|FALSE
+!endif
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFrameworkCompatibilitySupport|TRUE
+  gEfiCpuTokenSpaceGuid.PcdCpuSmmEnableBspElection|FALSE
+!if $(DATAHUB_STATUS_CODE_ENABLE) == TRUE
+  gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdStatusCodeUseDataHub|TRUE
+!else
+  gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdStatusCodeUseDataHub|FALSE
+!endif
+  gEfiMdeModulePkgTokenSpaceGuid.PcdPeiCoreImageLoaderSearchTeSectionFirst|FALSE
+!if $(TARGET) == RELEASE
+  gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|FALSE
+!else
+  gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|FALSE
+!endif
+  gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseMemory|FALSE
+!if $(ISA_SERIAL_STATUS_CODE_ENABLE) == TRUE
+  gEfiSerialPortTokenSpaceGuid.PcdStatusCodeUseIsaSerial|TRUE
+!else
+  gEfiSerialPortTokenSpaceGuid.PcdStatusCodeUseIsaSerial|FALSE
+!endif
+!if $(USB_SERIAL_STATUS_CODE_ENABLE) == TRUE
+  gEfiSerialPortTokenSpaceGuid.PcdStatusCodeUseUsbSerial|TRUE
+!else
+  gEfiSerialPortTokenSpaceGuid.PcdStatusCodeUseUsbSerial|FALSE
+!endif
+!if $(RAM_SERIAL_STATUS_CODE_ENABLE) == TRUE
+  gEfiSerialPortTokenSpaceGuid.PcdStatusCodeUseRam|TRUE
+!else
+  gEfiSerialPortTokenSpaceGuid.PcdStatusCodeUseRam|FALSE
+!endif
+
+
+  ## This PCD specifies whether PS2 keyboard does a extended verification during start.
+  gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdPs2KbdExtendedVerification|FALSE
+
+  ## This PCD specifies whether PS2 mouse does a extended verification during start.
+  gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdPs2MouseExtendedVerification|FALSE
+
+!if $(VARIABLE_INFO_ENABLE) == TRUE
+  gEfiMdeModulePkgTokenSpaceGuid.PcdVariableCollectStatistics|TRUE
+!else
+  gEfiMdeModulePkgTokenSpaceGuid.PcdVariableCollectStatistics|FALSE
+!endif
+
+  gEfiCpuTokenSpaceGuid.PcdCpuSmmBlockStartupThisAp|TRUE
+
+[PcdsFixedAtBuild.common]
+!if $(MINNOW2_FSP_BUILD) == TRUE
+# $(FLASH_REGION_VLVMICROCODE_BASE)
+  gFspWrapperTokenSpaceGuid.PcdCpuMicrocodePatchAddress|0xFFE00000
+# $(FLASH_REGION_VLVMICROCODE_SIZE)
+  gFspWrapperTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize|0x00030000
+  gFspWrapperTokenSpaceGuid.PcdFlashMicroCodeOffset|0x60
+# $(FLASH_AREA_BASE_ADDRESS)
+  gFspWrapperTokenSpaceGuid.PcdFlashCodeCacheAddress|0xFF800000
+# $(FLASH_AREA_SIZE)
+  gFspWrapperTokenSpaceGuid.PcdFlashCodeCacheSize|0x00800000
+# $(FLASH_REGION_FSPBIN_BASE)
+  gFspWrapperTokenSpaceGuid.PcdFlashFvFspBase|0xFFDB0000
+!endif
+
+!if $(PERFORMANCE_ENABLE) == TRUE
+!if $(MINNOW2_FSP_BUILD) == TRUE
+  # in FSP, when this got used, the memory already is up
+  gEfiCpuTokenSpaceGuid.PcdTemporaryRamBase|0x00080000
+!else
+  gEfiCpuTokenSpaceGuid.PcdTemporaryRamBase|0xFEF80000
+!endif
+  gEfiCpuTokenSpaceGuid.PcdTemporaryRamSize|0x00010000
+
+!else
+  !if $(MINNOW2_FSP_BUILD) == TRUE
+    gEfiCpuTokenSpaceGuid.PcdTemporaryRamBase|0x00080000
+  !else
+    gEfiCpuTokenSpaceGuid.PcdTemporaryRamBase|0xFEF80000
+  !endif
+  gEfiCpuTokenSpaceGuid.PcdTemporaryRamSize|0x00010000
+  gEfiCpuTokenSpaceGuid.PcdPeiTemporaryRamStackSize|0x3C00
+!endif
+
+
+!if $(SECURE_BOOT_ENABLE) == TRUE
+  gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x22000
+!else
+  gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x4000
+!endif
+  gEfiMdeModulePkgTokenSpaceGuid.PcdHwErrStorageSize|0x00000800
+  gEfiMdeModulePkgTokenSpaceGuid.PcdMaxHardwareErrorVariableSize|0x400
+  gEfiCpuTokenSpaceGuid.PcdCpuIEDRamSize|0x400000
+  gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdS3AcpiReservedMemorySize|0x10000
+  gEfiMdeModulePkgTokenSpaceGuid.PcdPeiCoreMaxPeimPerFv|50
+  gEfiMdeModulePkgTokenSpaceGuid.PcdSrIovSupport|FALSE
+  gEfiMdeModulePkgTokenSpaceGuid.PcdAriSupport|FALSE
+  gEfiMdeModulePkgTokenSpaceGuid.PcdPeiCoreMaxPpiSupported|128
+  gEfiCpuTokenSpaceGuid.PcdCpuSmmApSyncTimeout|1000
+!if $(S4_ENABLE) == TRUE
+  gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|TRUE
+!else
+  gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|FALSE
+!endif
+!if $(TARGET) == RELEASE
+  gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x0
+  gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x3
+!else
+  gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2F
+  gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07
+!endif
+!if $(PERFORMANCE_ENABLE) == TRUE
+  gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|0x1
+  gEfiMdeModulePkgTokenSpaceGuid.PcdMaxPeiPerformanceLogEntries|60
+!endif
+
+  gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdEbdaReservedMemorySize|0x10000
+  gEfiMdeModulePkgTokenSpaceGuid.PcdLoadModuleAtFixAddressEnable|$(TOP_MEMORY_ADDRESS)
+  gEfiMdeModulePkgTokenSpaceGuid.PcdBrowserSubtitleTextColor|0x0
+  gEfiMdeModulePkgTokenSpaceGuid.PcdBrowserFieldTextColor|0x01
+  gEfiCpuTokenSpaceGuid.PcdCpuIEDEnabled|TRUE
+  gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdBiosVideoCheckVbeEnable|TRUE
+  gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdBiosVideoCheckVgaEnable|TRUE
+
+!if $(SOURCE_DEBUG_ENABLE) == TRUE
+  gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x17
+  gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07
+  gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseHardwareFlowControl|FALSE
+!endif
+
+[PcdsFixedAtBuild.IA32.PEIM, PcdsFixedAtBuild.IA32.PEI_CORE, PcdsFixedAtBuild.IA32.SEC]
+!if $(TARGET) == RELEASE
+  gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x0
+  gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x3
+!else
+  gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2E
+  gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07
+!endif
+
+[PcdsPatchableInModule.common]
+  gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x803805c6
+  gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x$(PLATFORM_PCIEXPRESS_BASE)
+  gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdLegacyBiosCacheLegacyRegion|FALSE
+
+  ## This PCD specifies whether to use the optimized timing for best PS2 detection performance.
+  #  Note this PCD could be set to TRUE for best boot performance and set to FALSE for best device compatibility.
+  gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdFastPS2Detection|TRUE
+
+[PcdsDynamicHii.common.DEFAULT]
+  gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVariableGuid|0x0|5 # Variable: L"Timeout"
+  gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdHardwareErrorRecordLevel|L"HwErrRecSupport"|gEfiGlobalVariableGuid|0x0|1 # Variable: L"HwErrRecSupport"
+  gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdBootState|L"BootState"|gEfiBootStateGuid|0x0|TRUE
+
+[PcdsDynamicDefault.common.DEFAULT]
+  gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateDataPtr|0x0
+  !if $(TPM_ENABLED) == TRUE
+    gEfiSecurityPkgTokenSpaceGuid.PcdTpmInstanceGuid|{0x7b, 0x3a, 0xcd, 0x72, 0xA5, 0xFE, 0x5e, 0x4f, 0x91, 0x65, 0x4d, 0xd1, 0x21, 0x87, 0xbb, 0x13}
+  !endif
+
+  ## This PCD defines the video horizontal resolution.
+  #  This PCD could be set to 0 then video resolution could be at highest resolution.
+  gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution|0
+  ## This PCD defines the video vertical resolution.
+  #  This PCD could be set to 0 then video resolution could be at highest resolution.
+  gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution|0
+
+  ## This PCD defines the Console output column and the default value is 25 according to UEFI spec.
+  #  This PCD could be set to 0 then console output could be at max column and max row.
+  gEfiMdeModulePkgTokenSpaceGuid.PcdConOutRow|31
+  ## This PCD defines the Console output row and the default value is 80 according to UEFI spec.
+  #  This PCD could be set to 0 then console output could be at max column and max row.
+  gEfiMdeModulePkgTokenSpaceGuid.PcdConOutColumn|100
+
+  ## The PCD is used to specify the video horizontal resolution of text setup.
+  gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdSetupVideoHorizontalResolution|800
+  ## The PCD is used to specify the video vertical resolution of text setup.
+  gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdSetupVideoVerticalResolution|600
+  ## The PCD is used to specify the console output column of text setup.
+  gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdSetupConOutColumn|100
+  ## The PCD is used to specify the console output column of text setup.
+  gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdSetupConOutRow|31
+
+!if $(TPM_ENABLED) == TRUE
+  gEfiSecurityPkgTokenSpaceGuid.PcdTpmInitializationPolicy|1
+  gEfiSecurityPkgTokenSpaceGuid.PcdTpmScrtmPolicy|1
+!endif
+
+[PcdsDynamicExDefault.common.DEFAULT]
+  gEfiVLVTokenSpaceGuid.PcdTCSmbaIoBaseAddress|0x1040
+  gEfiVLVTokenSpaceGuid.PcdEmmcManufacturerId|0
+  gEfiVLVTokenSpaceGuid.PcdProductSerialNumber|0
+  gEfiVLVTokenSpaceGuid.PcdMeasuredBootEnable|TRUE
+  gEfiVLVTokenSpaceGuid.PcdFTPMErrorOccur|FALSE
+  gEfiVLVTokenSpaceGuid.PcdFTPMErrorSkip|FALSE
+  gEfiVLVTokenSpaceGuid.PcdFTPMCommand|0
+  gEfiVLVTokenSpaceGuid.PcdFTPMResponse|0
+  gEfiVLVTokenSpaceGuid.PcdFTPMNotRespond|FALSE
+  gEfiVLVTokenSpaceGuid.PcdFTPMStatus|0
+
+[Components.IA32]
+
+  $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/SecCore.inf
+
+  !if $(MINNOW2_FSP_BUILD) == TRUE
+  IntelFspWrapperPkg/FspWrapperSecCore/FspWrapperSecCore.inf {
+    !if $(TARGET) == DEBUG
+
+    <LibraryClasses>
+      DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
+    !endif
+  }
+  Vlv2TbltDevicePkg/FspSupport/BootModePei/BootModePei.inf
+  IntelFspWrapperPkg/FspInitPei/FspInitPei.inf {
+    !if $(TARGET) == DEBUG
+    <LibraryClasses>
+      DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
+    !endif
+  }
+  !endif
+
+  MdeModulePkg/Core/Pei/PeiMain.inf {
+!if $(TARGET) == DEBUG
+    <PcdsFixedAtBuild>
+      gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2E
+!endif
+    <PcdsPatchableInModule>
+      gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80000046
+    !if $(TARGET) == DEBUG
+  <LibraryClasses>  
+    DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
+    SerialPortLib|$(PLATFORM_PACKAGE)/Library/SerialPortLib/SerialPortLib.inf
+    !endif
+  }
+
+  $(PLATFORM_PACKAGE)/MonoStatusCode/MonoStatusCode.inf {
+!if $(TARGET) == DEBUG
+    <PcdsFixedAtBuild>
+      gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2E
+!endif
+  }
+  $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/MemoryInit.inf {
+    <PcdsPatchableInModule>
+      gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80000046
+  }
+
+!if $(RC_BINARY_RELEASE) == TRUE
+  $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/SeCUma.inf
+!endif
+
+!if $(RC_BINARY_RELEASE) == TRUE
+  $(PLATFORM_PACKAGE)/PlatformPei/PlatformPei.inf {
+    <BuildOptions>
+      *_*_IA32_CC_FLAGS      = -DRC_BINARY_RELEASE
+  !if $(TARGET) == DEBUG
+      <PcdsFixedAtBuild>
+        gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2E
+  !endif
+  }
+!endif
+
+!if $(SOURCE_DEBUG_ENABLE) == TRUE
+  SourceLevelDebugPkg/DebugAgentPei/DebugAgentPei.inf{
+    <LibraryClasses>
+      PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
+      DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/SecPeiDebugAgentLib.inf
+      PlatformHookLib|MdeModulePkg/Library/BasePlatformHookLibNull/BasePlatformHookLibNull.inf
+      SerialPortLib|MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.inf
+    }
+!endif
+
+
+!if $(TPM_ENABLED) == TRUE
+  SecurityPkg/Tcg/PhysicalPresencePei/PhysicalPresencePei.inf
+  SecurityPkg/Tcg/TcgPei/TcgPei.inf {
+    <LibraryClasses>
+      NULL|SecurityPkg/Library/HashInstanceLibSha1/HashInstanceLibSha1.inf
+      NULL|SecurityPkg/Library/HashInstanceLibSha256/HashInstanceLibSha256.inf
+      PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf
+}
+!endif
+
+ $(PLATFORM_PACKAGE)/PlatformInitPei/PlatformInitPei.inf {
+    <PcdsPatchableInModule>
+      gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x803805c6
+    <LibraryClasses>
+!if $(TARGET) != RELEASE
+      DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf
+!endif
+      PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf
+  }
+  $(PLATFORM_PACKAGE)/FvInfoPei/FvInfoPei.inf
+
+  $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/VlvInitPeim.inf
+!if $(PCIESC_ENABLE) == TRUE
+  $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/PchEarlyInitPeim.inf {
+    <PcdsPatchableInModule>
+      gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80000046
+  }
+!endif
+  $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/PchInitPeim.inf
+
+
+  $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/PchSmbusArpDisabled.inf
+  $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/PchSpiPeim.inf
+  $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/PeiSmmAccess.inf
+  $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/PeiSmmControl.inf
+  MdeModulePkg/Universal/PCD/Pei/Pcd.inf
+  $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/CpuPeim.inf
+  UefiCpuPkg/CpuIoPei/CpuIoPei.inf
+  UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume2Pei.inf
+  $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/MpS3.inf
+  EdkCompatibilityPkg/Compatibility/AcpiVariableHobOnSmramReserveHobThunk/AcpiVariableHobOnSmramReserveHobThunk.inf
+  $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/PiSmmCommunicationPei.inf
+!if $(CAPSULE_ENABLE) == TRUE
+  MdeModulePkg/Universal/CapsulePei/CapsulePei.inf
+!endif
+  MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf {
+    <LibraryClasses>
+!if $(LZMA_ENABLE) == TRUE
+    NULL|IntelFrameworkModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf
+!endif
+  }
+
+!if $(SECURE_BOOT_ENABLE) == TRUE
+ SecurityPkg/VariableAuthenticated/Pei/VariablePei.inf
+!else
+ MdeModulePkg/Universal/Variable/Pei/VariablePei.inf
+!endif
+ MdeModulePkg/Universal/FaultTolerantWritePei/FaultTolerantWritePei.inf
+
+!if $(TPM_ENABLED) == TRUE
+  SecurityPkg/Tcg/TrEEConfig/TrEEConfigPei.inf {
+    <LibraryClasses>
+      PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf
+  }
+!endif
+!if $(ACPI50_ENABLE) == TRUE
+  MdeModulePkg/Universal/Acpi/FirmwarePerformanceDataTablePei/FirmwarePerformancePei.inf{
+    <LibraryClasses>
+      TimerLib|$(PLATFORM_PACKAGE)/Library/IntelPchAcpiTimerLib/IntelPchAcpiTimerLib.inf
+  }
+
+!endif
+!if $(PERFORMANCE_ENABLE) == TRUE
+  MdeModulePkg/Universal/ReportStatusCodeRouter/Pei/ReportStatusCodeRouterPei.inf
+!endif
+[Components.X64]
+  !if $(MINNOW2_FSP_BUILD) == TRUE
+  IntelFspWrapperPkg/FspNotifyDxe/FspNotifyDxe.inf {
+    !if $(TARGET) == DEBUG
+    <PcdsPatchableInModule>
+      gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80000046
+    <LibraryClasses>
+      DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
+    !endif
+  }
+
+  !endif
+  #
+  # EDK II Related Platform codes
+  #
+  MdeModulePkg/Core/Dxe/DxeMain.inf {
+    <PcdsPatchableInModule>
+      gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80000046
+    <LibraryClasses>
+!if $(DXE_CRC32_SECTION_ENABLE) == TRUE
+      NULL|MdeModulePkg/Library/DxeCrc32GuidedSectionExtractLib/DxeCrc32GuidedSectionExtractLib.inf
+!endif
+!if $(LZMA_ENABLE) == TRUE
+      NULL|IntelFrameworkModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf
+!endif
+!if $(TARGET) != RELEASE
+      DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
+      SerialPortLib|$(PLATFORM_PACKAGE)/Library/SerialPortLib/SerialPortLib.inf 
+!endif
+  }
+  IntelFrameworkModulePkg/Universal/Acpi/AcpiS3SaveDxe/AcpiS3SaveDxe.inf {
+    <PcdsPatchableInModule>
+        gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0xF0000043
+    <PcdsFixedAtBuild>
+        gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x27
+    <LibraryClasses>
+    !if $(TARGET) != RELEASE
+          DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf
+    !endif
+       <BuildOptions>
+        ICC:*_*_*_CC_FLAGS = -D MDEPKG_NDEBUG
+        GCC:*_*_*_CC_FLAGS = -D MDEPKG_NDEBUG
+  }
+  MdeModulePkg/Universal/PCD/Dxe/Pcd.inf {
+    <LibraryClasses>
+      PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
+  }
+  IntelFrameworkModulePkg/Universal/CpuIoDxe/CpuIoDxe.inf
+  UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.inf
+!if $(PERFORMANCE_ENABLE) == TRUE
+  MdeModulePkg/Universal/ReportStatusCodeRouter/Pei/ReportStatusCodeRouterPei.inf
+!endif
+  MdeModulePkg/Universal/ReportStatusCodeRouter/RuntimeDxe/ReportStatusCodeRouterRuntimeDxe.inf
+  MdeModulePkg/Universal/StatusCodeHandler/RuntimeDxe/StatusCodeHandlerRuntimeDxe.inf  {
+    <LibraryClasses>
+!if $(TARGET) != RELEASE
+      DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf
+!endif
+  }
+
+!if $(CAPSULE_ENABLE) == TRUE
+  MdeModulePkg/Universal/CapsulePei/CapsuleX64.inf {
+    <LibraryClasses>
+    PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf
+    MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf
+    HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf
+  }
+!endif
+
+  MdeModulePkg/Universal/ReportStatusCodeRouter/Smm/ReportStatusCodeRouterSmm.inf
+  MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf{
+    <LibraryClasses>
+!if $(SECURE_BOOT_ENABLE) == TRUE
+      NULL|SecurityPkg/Library/DxeImageVerificationLib/DxeImageVerificationLib.inf
+!endif
+!if $(USER_IDENTIFICATION_ENABLE)
+      NULL|SecurityPkg/Library/DxeDeferImageLoadLib/DxeDeferImageLoadLib.inf
+!endif
+!if $(TPM_ENABLED) == TRUE
+      NULL|SecurityPkg/Library/DxeTpmMeasureBootLib/DxeTpmMeasureBootLib.inf
+!endif
+  }
+  $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/MpCpu.inf
+  $(PLATFORM_PACKAGE)/Metronome/Metronome.inf
+
+  IntelFrameworkModulePkg/Universal/BdsDxe/BdsDxe.inf{
+    <LibraryClasses>
+      OpensslLib|CryptoPkg/Library/OpensslLib/OpensslLib.inf
+      IntrinsicLib|CryptoPkg/Library/IntrinsicLib/IntrinsicLib.inf
+      BaseCryptLib|CryptoPkg/Library/BaseCryptLib/BaseCryptLib.inf
+      PlatformBdsLib|$(PLATFORM_PACKAGE)/Library/PlatformBdsLib/PlatformBdsLib.inf
+      DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
+      PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
+      SerialPortLib|$(PLATFORM_PACKAGE)/Library/SerialPortLib/SerialPortLib.inf
+  }
+
+  $(PLATFORM_PACKAGE)/UiApp/UiApp.inf
+
+  MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
+  MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
+  MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
+!if $(SECURE_BOOT_ENABLE) == TRUE
+  SecurityPkg/VariableAuthenticated/RuntimeDxe/VariableSmmRuntimeDxe.inf
+  SecurityPkg/VariableAuthenticated/RuntimeDxe/VariableSmm.inf{
+    <LibraryClasses>
+      PlatformSecureLib|SecurityPkg/Library/PlatformSecureLibNull/PlatformSecureLibNull.inf
+      SerialPortLib|$(PLATFORM_PACKAGE)/Library/SerialPortLib/SerialPortLib.inf
+  }
+  $(PLATFORM_PACKAGE)/FvbRuntimeDxe/FvbSmm.inf
+  MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteSmm.inf
+  $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/PchSpiSmm.inf
+  SecurityPkg/VariableAuthenticated/SecureBootConfigDxe/SecureBootConfigDxe.inf {
+    <LibraryClasses>
+      PlatformSecureLib|SecurityPkg/Library/PlatformSecureLibNull/PlatformSecureLibNull.inf
+    <BuildOptions>
+      #
+      # Specify GUID gEfiIfrBootMaintenanceGuid, to install Secure Boot Configuration menu
+      # into Boot Maintenance Manager menu
+      #
+      *_*_*_VFR_FLAGS   = -g b2dedc91-d59f-48d2-898a-12490c74a4e0
+  }
+ !else
+  MdeModulePkg/Universal/Variable/RuntimeDxe/VariableSmmRuntimeDxe.inf
+  MdeModulePkg/Universal/Variable/RuntimeDxe/VariableSmm.inf
+  $(PLATFORM_PACKAGE)/FvbRuntimeDxe/FvbSmm.inf
+  MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteSmm.inf
+  $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/PchSpiSmm.inf
+!endif
+   MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf {
+    <LibraryClasses>
+      FileHandleLib|ShellPkg/Library/UefiFileHandleLib/UefiFileHandleLib.inf
+  }
+
+  MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf
+  PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcatRealTimeClockRuntimeDxe.inf
+  MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
+
+  $(PLATFORM_PACKAGE)/FvbRuntimeDxe/FvbRuntimeDxe.inf
+
+  $(PLATFORM_PACKAGE)/PlatformSetupDxe/PlatformSetupDxe.inf
+
+!if $(DATAHUB_ENABLE) == TRUE
+  IntelFrameworkModulePkg/Universal/DataHubDxe/DataHubDxe.inf {
+    <PcdsFixedAtBuild>
+      gEfiMdePkgTokenSpaceGuid.PcdMaximumLinkedListLength|0
+  }
+!endif
+  IntelFrameworkModulePkg/Universal/StatusCode/DatahubStatusCodeHandlerDxe/DatahubStatusCodeHandlerDxe.inf
+  MdeModulePkg/Universal/MemoryTest/NullMemoryTestDxe/NullMemoryTestDxe.inf
+  $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/PchS3SupportDxe.inf
+  !if $(USE_HPET_TIMER) == TRUE
+    PcAtChipsetPkg/HpetTimerDxe/HpetTimerDxe.inf
+  !else
+  $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/SmartTimer.inf
+  !endif
+  $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/SmmControl.inf
+
+  $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/PchSmbusDxe.inf
+  $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/IntelPchLegacyInterrupt.inf
+  $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/PchReset.inf
+  $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/PchInitDxe.inf{
+    <PcdsPatchableInModule>
+        gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0xF0000043
+  }
+  $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/PchSmiDispatcher.inf
+
+!if $(PCIESC_ENABLE) == TRUE
+  $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/PchPcieSmm.inf
+!endif
+  $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/PchSpiRuntime.inf
+  $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/PchPolicyInitDxe.inf
+  $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/PchBiosWriteProtect.inf
+  $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/SmmAccess.inf
+  $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/PciHostBridge.inf
+  $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/VlvInitDxe.inf
+
+  IntelFrameworkModulePkg/Universal/LegacyRegionDxe/LegacyRegionDxe.inf
+
+  Vlv2TbltDevicePkg/VlvPlatformInitDxe/VlvPlatformInitDxe.inf{
+    <LibraryClasses>
+!if $(TARGET) != RELEASE
+      DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf
+!endif
+      PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
+  }
+
+  $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/Dptf.inf
+  $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/PnpDxe.inf
+
+!if $(TPM_ENABLED) == TRUE
+  SecurityPkg/Tcg/TrEEConfig/TrEEConfigPei.inf {
+    <LibraryClasses>
+      PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf
+  }
+
+  SecurityPkg/Tcg/TcgConfigDxe/TcgConfigDxe.inf {
+    <LibraryClasses>
+      PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
+    <BuildOptions>
+      #
+      # specify GUID gEfiIfrNotInTPVPageGuid, this page will not
+      # be showed in TPV page.
+      #
+      *_*_*_VFR_FLAGS   = -g e58809f8-fbc1-48e2-883a-a30fdc4b441e
+  }
+
+  SecurityPkg/Tcg/TcgDxe/TcgDxe.inf {
+    <LibraryClasses>
+      PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
+  }
+  SecurityPkg/Tcg/TcgSmm/TcgSmm.inf
+!endif
+  #
+  # EDK II Related Platform codes
+  #
+  $(PLATFORM_PACKAGE)/PlatformSmm/PlatformSmm.inf{
+    <LibraryClasses>
+    !if $(TARGET) != RELEASE
+          DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf
+    !endif
+          PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
+  }
+  $(PLATFORM_PACKAGE)/PlatformInfoDxe/PlatformInfoDxe.inf
+  $(PLATFORM_PACKAGE)/PlatformCpuInfoDxe/PlatformCpuInfoDxe.inf
+  $(PLATFORM_PACKAGE)/PlatformDxe/PlatformDxe.inf
+
+  $(PLATFORM_PACKAGE)/PciPlatform/PciPlatform.inf
+  $(PLATFORM_PACKAGE)/SaveMemoryConfig/SaveMemoryConfig.inf
+  $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/PlatformCpuPolicy.inf
+  $(PLATFORM_PACKAGE)/PpmPolicy/PpmPolicy.inf
+  $(PLATFORM_PACKAGE)/SmramSaveInfoHandlerSmm/SmramSaveInfoHandlerSmm.inf
+!if $(GOP_DRIVER_ENABLE) == TRUE
+  $(PLATFORM_PACKAGE)/PlatformGopPolicy/PlatformGopPolicy.inf
+
+!endif
+
+
+  #
+  # SMM
+  #
+  MdeModulePkg/Core/PiSmmCore/PiSmmIpl.inf
+  MdeModulePkg/Core/PiSmmCore/PiSmmCore.inf{
+     !if $(TARGET) != RELEASE
+    <LibraryClasses>
+           DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
+           SerialPortLib|$(PLATFORM_PACKAGE)/Library/SerialPortLib/SerialPortLib.inf
+     !endif
+  }
+  $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/PiSmmCpuDxeSmm.inf
+  UefiCpuPkg/CpuIo2Smm/CpuIo2Smm.inf
+  MdeModulePkg/Universal/LockBox/SmmLockBox/SmmLockBox.inf
+  $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/PiSmmCommunicationSmm.inf
+  $(PLATFORM_PACKAGE)/SmmSwDispatch2OnSmmSwDispatchThunk/SmmSwDispatch2OnSmmSwDispatchThunk.inf
+  $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/PowerManagement2.inf
+
+  #
+  # ACPI
+  #
+   MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/BootScriptExecutorDxe.inf {
+    <PcdsPatchableInModule>
+      gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0xF0000043
+    <PcdsFixedAtBuild>
+      gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x27
+    <LibraryClasses>
+      PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
+  }
+
+  $(PLATFORM_PACKAGE)/BootScriptSaveDxe/BootScriptSaveDxe.inf
+  IntelFrameworkModulePkg/Universal/Acpi/AcpiSupportDxe/AcpiSupportDxe.inf
+  Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/PowerManagement/AcpiTables/PowerManagementAcpiTables.inf
+
+  $(PLATFORM_RC_PACKAGE)/AcpiTablesPCAT/AcpiTables.inf
+
+  $(PLATFORM_PACKAGE)/AcpiPlatform/AcpiPlatform.inf
+
+  #
+  # PCI
+  #
+  MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
+
+
+  $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/ISPDxe.inf
+
+
+#
+# ISA
+#
+  $(PLATFORM_PACKAGE)/Wpce791/Wpce791.inf
+  IntelFrameworkModulePkg/Bus/Isa/IsaBusDxe/IsaBusDxe.inf
+  IntelFrameworkModulePkg/Bus/Isa/IsaIoDxe/IsaIoDxe.inf
+  IntelFrameworkModulePkg/Bus/Isa/IsaSerialDxe/IsaSerialDxe.inf
+  IntelFrameworkModulePkg/Bus/Isa/Ps2MouseDxe/Ps2MouseDxe.inf
+  IntelFrameworkModulePkg/Bus/Isa/Ps2KeyboardDxe/Ps2keyboardDxe.inf
+#
+# SDIO
+#
+  $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/MmcHost.inf
+  $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/MmcMediaDevice.inf
+!if $(ACPI50_ENABLE) == TRUE
+  MdeModulePkg/Universal/Acpi/FirmwarePerformanceDataTableDxe/FirmwarePerformanceDxe.inf {
+    <LibraryClasses>
+      TimerLib|$(PLATFORM_PACKAGE)/Library/IntelPchAcpiTimerLib/IntelPchAcpiTimerLib.inf
+  }
+  MdeModulePkg/Universal/Acpi/FirmwarePerformanceDataTableSmm/FirmwarePerformanceSmm.inf {
+    <LibraryClasses>
+      TimerLib|$(PLATFORM_PACKAGE)/Library/IntelPchAcpiTimerLib/IntelPchAcpiTimerLib.inf
+  }
+!endif
+
+#
+# IDE/SCSI/AHCI
+#
+  MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf
+  IntelFrameworkModulePkg/Bus/Pci/IdeBusDxe/IdeBusDxe.inf
+  MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
+  MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
+  MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
+!if $(SATA_ENABLE) == TRUE
+  $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/SataController.inf
+!endif
+  MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf
+!if $(SCSI_ENABLE) == TRUE
+  MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf
+  MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf
+!endif
+#
+# Console
+#
+  MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
+  Vlv2TbltDevicePkg/Override/MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
+  MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf
+  IntelFrameworkModulePkg/Universal/Console/VgaClassDxe/VgaClassDxe.inf
+  MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
+  MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
+  MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
+  MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
+
+  #
+  # USB
+  #
+!if $(USB_ENABLE) == TRUE
+  MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf
+  MdeModulePkg/Bus/Pci/UhciDxe/UhciDxe.inf
+  MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf
+  MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
+  MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf
+  MdeModulePkg/Bus/Usb/UsbMouseDxe/UsbMouseDxe.inf
+  MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
+
+!endif
+
+  #
+  #  ECP
+  #
+  EdkCompatibilityPkg/Compatibility/FrameworkHiiOnUefiHiiThunk/FrameworkHiiOnUefiHiiThunk.inf
+  EdkCompatibilityPkg/Compatibility/LegacyRegion2OnLegacyRegionThunk/LegacyRegion2OnLegacyRegionThunk.inf
+  EdkCompatibilityPkg/Compatibility/SmmBaseOnSmmBase2Thunk/SmmBaseOnSmmBase2Thunk.inf
+  EdkCompatibilityPkg/Compatibility/SmmBaseHelper/SmmBaseHelper.inf
+  EdkCompatibilityPkg/Compatibility/SmmAccess2OnSmmAccessThunk/SmmAccess2OnSmmAccessThunk.inf
+  EdkCompatibilityPkg/Compatibility/SmmControl2OnSmmControlThunk/SmmControl2OnSmmControlThunk.inf
+  EdkCompatibilityPkg/Compatibility/FrameworkSmmStatusCodeOnPiSmmStatusCodeThunk/FrameworkSmmStatusCodeOnPiSmmStatusCodeThunk.inf
+  EdkCompatibilityPkg/Compatibility/FvOnFv2Thunk/FvOnFv2Thunk.inf
+  #
+  # SMBIOS
+  #
+  MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf
+  $(PLATFORM_PACKAGE)/SmBiosMiscDxe/SmBiosMiscDxe.inf
+
+  $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/SmbiosMemory.inf
+  #
+  # CPU/FW Microde
+  #
+  Vlv2MiscBinariesPkg/Microcode/MicrocodeUpdates.inf {
+    <BuildOptions>
+      *_*_*_GENFW_FLAGS = -a 0x800 -p 0xFF
+  }
+
+
+  PcAtChipsetPkg/8259InterruptControllerDxe/8259.inf
+
+
+!if $(NETWORK_ENABLE) == TRUE
+  !if $(NETWORK_ISCSI_ENABLE) == TRUE
+    !if $(NETWORK_IP6_ENABLE) == TRUE
+      NetworkPkg/IScsiDxe/IScsiDxe.inf
+    !else
+      MdeModulePkg/Universal/Network/IScsiDxe/IScsiDxe.inf
+    !endif
+  !endif
+  !if $(NETWORK_VLAN_ENABLE) == TRUE
+    MdeModulePkg/Universal/Network/VlanConfigDxe/VlanConfigDxe.inf
+  !endif
+  !if $(CSM_ENABLE) == TRUE
+    IntelFrameworkModulePkg/Csm/BiosThunk/Snp16Dxe/Snp16Dxe.inf
+  !endif
+!endif
+
+!if $(NETWORK_ENABLE) == TRUE
+  #
+  # UEFI network modules
+  #
+    MdeModulePkg/Universal/Network/DpcDxe/DpcDxe.inf
+    MdeModulePkg/Universal/Network/SnpDxe/SnpDxe.inf
+
+    MdeModulePkg/Universal/Network/MnpDxe/MnpDxe.inf
+    MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf
+    MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Dxe.inf
+    MdeModulePkg/Universal/Network/Ip4ConfigDxe/Ip4ConfigDxe.inf
+    MdeModulePkg/Universal/Network/Ip4Dxe/Ip4Dxe.inf
+    MdeModulePkg/Universal/Network/Mtftp4Dxe/Mtftp4Dxe.inf
+    MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf {
+      <PcdsPatchableInModule>
+      gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80000000
+    }
+    MdeModulePkg/Universal/Network/Udp4Dxe/Udp4Dxe.inf
+    !if $(NETWORK_IP6_ENABLE) == TRUE
+      NetworkPkg/Ip6Dxe/Ip6Dxe.inf
+      NetworkPkg/Dhcp6Dxe/Dhcp6Dxe.inf
+      NetworkPkg/IpSecDxe/IpSecDxe.inf
+      NetworkPkg/TcpDxe/TcpDxe.inf
+      NetworkPkg/Udp6Dxe/Udp6Dxe.inf
+      NetworkPkg/Mtftp6Dxe/Mtftp6Dxe.inf
+    !endif
+    !if $(NETWORK_IP6_ENABLE) == TRUE
+      NetworkPkg/UefiPxeBcDxe/UefiPxeBcDxe.inf
+    !else
+      MdeModulePkg/Universal/Network/UefiPxeBcDxe/UefiPxeBcDxe.inf
+    !endif
+!endif
+
+  Vlv2TbltDevicePkg/Application/FirmwareUpdate/FirmwareUpdate.inf
+
+[BuildOptions]
+#
+# Define Build Options both for EDK and EDKII drivers.
+#
+
+#
+# Define token for different Platform
+#
+!if $(MINNOW2_FSP_BUILD) == TRUE
+  DEFINE MINNOW2_FSP_OPTION = -DMINNOW2_FSP_BUILD
+!else
+  DEFINE MINNOW2_FSP_OPTION =
+!endif
+
+!if $(ENBDT_PF_BUILD) == TRUE
+  DEFINE ENBDT_PF_ENABLE = -DENBDT_PF_ENABLE=1
+!else
+  DEFINE ENBDT_PF_ENABLE = -DENBDT_PF_ENABLE=0
+!endif
+
+
+!if $(CLKGEN_CONFIG_EXTRA_ENABLE) == TRUE
+  DEFINE CLKGEN_CONFIG_EXTRA_BUILD_OPTION = -DCLKGEN_CONFIG_EXTRA=1
+!else
+  DEFINE CLKGEN_CONFIG_EXTRA_BUILD_OPTION =
+!endif
+
+
+
+!if $(PCIESC_ENABLE) == TRUE
+  DEFINE PCIESC_SUPPORT_BUILD_OPTION = -DPCIESC_SUPPORT=1
+!else
+  DEFINE PCIESC_SUPPORT_BUILD_OPTION =
+!endif
+!if $(SATA_ENABLE) == TRUE
+  DEFINE SATA_SUPPORT_BUILD_OPTION = -DSATA_SUPPORT=1
+!else
+  DEFINE SATA_SUPPORT_BUILD_OPTION =
+!endif
+!if $(ENBDT_S3_SUPPORT) == TRUE
+  DEFINE ENBDT_S3_SUPPORT_OPTIONS = -DNOCS_S3_SUPPORT
+!else
+  DEFINE ENBDT_S3_SUPPORT_OPTIONS =
+!endif
+
+!if $(X64_CONFIG) == TRUE
+  DEFINE X64_BUILD_ENABLE = -DX64_BUILD_ENABLE=1
+!else
+  DEFINE X64_BUILD_ENABLE =
+!endif
+
+!if $(TPM_ENABLED) == TRUE
+  DEFINE DSC_TPM_BUILD_OPTIONS = -DTPM_ENABLED
+!else
+  DEFINE DSC_TPM_BUILD_OPTIONS =
+!endif
+
+
+  DEFINE EDK_EDKII_DSC_FEATURE_BUILD_OPTIONS = $(MINNOW2_FSP_OPTION) $(MINNOW2_BUILD_OPTION) $(ENBDT_PF_ENABLE) $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) $(CLKGEN_CONFIG_EXTRA_BUILD_OPTION) $(SYSCTL_X0_CONVERT_BOARD_OPTION) $(ENBDT_S3_SUPPORT_OPTIONS) $(SATA_SUPPORT_BUILD_OPTION) $(PCIESC_SUPPORT_BUILD_OPTION) $(DSC_FTPM_ERROR_WR_BUILD_OPTIONS) $(DSC_TPM_BUILD_OPTIONS) $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS)
+!if $(PERFORMANCE_ENABLE) == TRUE
+  DEFINE PDB_BUILD_OPTION = /Zi
+!endif
+
+!if $(SOURCE_DEBUG_ENABLE) == TRUE
+  MSFT:*_*_X64_GENFW_FLAGS  = --keepexceptiontable
+  GCC:*_*_X64_GENFW_FLAGS   = --keepexceptiontable
+  INTEL:*_*_X64_GENFW_FLAGS = --keepexceptiontable
+!if $(TARGET) == DEBUG
+  DEFINE SOURCE_LEVEL_DEBUG_BUILD_OPTIONS = /Od /Oy-
+!endif
+!else
+  DEFINE SOURCE_LEVEL_DEBUG_BUILD_OPTIONS =
+
+!endif
+
+[BuildOptions.Common.EDK]
+
+#
+# Define token for different Platform
+#
+!if $(ENBDT_PF_BUILD) == TRUE
+  DEFINE ENBDT_PF_ENABLE = -DENBDT_PF_ENABLE=1
+!else
+  DEFINE ENBDT_PF_ENABLE = -DENBDT_PF_ENABLE=0
+!endif
+
+!if $(PERFORMANCE_ENABLE) == TRUE
+  RELEASE_*_*_DLINK_FLAGS = -DEBUG
+!endif
+
+!if $(S3_ENABLE) == TRUE
+  DEFINE DSC_S3_BUILD_OPTIONS = -DEFI_S3_RESUME
+!else
+  DEFINE DSC_S3_BUILD_OPTIONS =
+!endif
+
+!if $(ENBDT_S3_SUPPORT) == TRUE
+  DEFINE ENBDT_S3_SUPPORT_OPTIONS = -DNOCS_S3_SUPPORT
+!else
+  DEFINE ENBDT_S3_SUPPORT_OPTIONS =
+!endif
+
+!if $(X64_CONFIG) == TRUE
+  DEFINE X64_BUILD_ENABLE = -DX64_BUILD_ENABLE=1
+!else
+  DEFINE X64_BUILD_ENABLE =
+!endif
+
+
+  DEFINE EDK_GLUE_LIB_DEBUG  =
+  DEFINE DEBUG_BUILD_OPTIONS = -D EFI_DEBUG -D DEBUG_MODE=1  /GL- $(EDK_GLUE_LIB_DEBUG) -DEDKII_GLUE_DebugPrintErrorLevel=(EFI_D_ERROR)
+  DEFINE EDK_DSC_FEATURE_BUILD_OPTIONS = $(DSC_S3_BUILD_OPTIONS) $(DSC_ACPI_BUILD_OPTIONS) $(DSC_SEC_BUILD_OPTIONS) $(DSC_FTPM_BUILD_OPTIONS) $(DSC_FTPM_ERROR_WR_BUILD_OPTIONS) $(DSC_TPM_BUILD_OPTIONS) $(SOFTSDV_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(QT_BUILD_OPTIONS) $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) -D$(PROJECT_SC_CHIPSET)
+
+  DEFINE EDK_DSC_OTHER_BUILD_OPTIONS = $(EDK_EDKII_DSC_FEATURE_BUILD_OPTIONS) $(SV_BUILD_OPTIONS) $(INTEL_FASTBOOT_BUILD_OPTION)
+  DEFINE EDK_DSC_GLOBAL_BUILD_OPTIONS = $(ENBDT_PF_ENABLE) $(EDK_DSC_FEATURE_BUILD_OPTIONS) $(EDK_DSC_OTHER_BUILD_OPTIONS) -D EFI_SPECIFICATION_VERSION=0x00020000  -D PI_SPECIFICATION_VERSION=0x00000009  -D TIANO_RELEASE_VERSION=0x00080006 -D SUPPORT_DEPRECATED_PCI_CFG_PPI -D CSM_SMMENTRY_PORT8DATA8 -D EDKII_GLUE_PciExpressBaseAddress=0x$(PLATFORM_PCIEXPRESS_BASE) -D MAX_VARIABLE_SIZE=0x2000 -D EFI_FIRMWARE_VENDOR="L/"INTEL/"" -D EFI_BUILD_VERSION="L/"EDKII/"" -DEFI_PEI_REPORT_STATUS_CODE_ON $(ENBDT_S3_SUPPORT_OPTIONS)
+
+  *_*_IA32_ASM_FLAGS         = -DEFI32 -D EDKII_GLUE_PciExpressBaseAddress=$(PLATFORM_PCIEXPRESS_BASE)h -DNOCS_S3_SUPPORT
+  DEBUG_*_IA32_CC_FLAGS      = -D EFI32 $(EDK_DSC_GLOBAL_BUILD_OPTIONS) $(DEBUG_BUILD_OPTIONS)
+  RELEASE_*_IA32_CC_FLAGS    = -D EFI32 $(EDK_DSC_GLOBAL_BUILD_OPTIONS)
+  DEBUG_*_IA32_VFRPP_FLAGS   = -D EFI32 $(EDK_DSC_GLOBAL_BUILD_OPTIONS) $(DEBUG_BUILD_OPTIONS)
+  RELEASE_*_IA32_VFRPP_FLAGS = -D EFI32 $(EDK_DSC_GLOBAL_BUILD_OPTIONS)
+  DEBUG_*_IA32_APP_FLAGS     = -D EFI32 $(EDK_DSC_GLOBAL_BUILD_OPTIONS) $(DEBUG_BUILD_OPTIONS)
+  RELEASE_*_IA32_APP_FLAGS   = -D EFI32 $(EDK_DSC_GLOBAL_BUILD_OPTIONS)
+  DEBUG_*_IA32_PP_FLAGS      = -D EFI32 $(EDK_DSC_GLOBAL_BUILD_OPTIONS) $(DEBUG_BUILD_OPTIONS)
+  RELEASE_*_IA32_PP_FLAGS    = -D EFI32 $(EDK_DSC_GLOBAL_BUILD_OPTIONS)
+  *_*_IA32_ASLPP_FLAGS       = -D EDKII_GLUE_PciExpressBaseAddress=0x$(PLATFORM_PCIEXPRESS_BASE)
+  *_*_IA32_ASLCC_FLAGS       = -D EDKII_GLUE_PciExpressBaseAddress=0x$(PLATFORM_PCIEXPRESS_BASE)
+  *_*_IA32_ASM16_FLAGS       = -D EDKII_GLUE_PciExpressBaseAddress=$(PLATFORM_PCIEXPRESS_BASE)h
+
+  *_*_X64_ASM_FLAGS          = -DEFIX64 -D EDKII_GLUE_PciExpressBaseAddress=$(PLATFORM_PCIEXPRESS_BASE)h -DNOCS_S3_SUPPORT
+  DEBUG_*_X64_CC_FLAGS       = -D EFIX64 $(EDK_DSC_GLOBAL_BUILD_OPTIONS) $(DEBUG_BUILD_OPTIONS)
+  RELEASE_*_X64_CC_FLAGS     = -D EFIX64 $(EDK_DSC_GLOBAL_BUILD_OPTIONS)
+  DEBUG_*_X64_VFRPP_FLAGS    = -D EFIX64 $(EDK_DSC_GLOBAL_BUILD_OPTIONS) $(DEBUG_BUILD_OPTIONS)
+  RELEASE_*_X64_VFRPP_FLAGS  = -D EFIX64 $(EDK_DSC_GLOBAL_BUILD_OPTIONS)
+  DEBUG_*_X64_APP_FLAGS      = -D EFIX64 $(EDK_DSC_GLOBAL_BUILD_OPTIONS) $(DEBUG_BUILD_OPTIONS)
+  RELEASE_*_X64_APP_FLAGS    = -D EFIX64 $(EDK_DSC_GLOBAL_BUILD_OPTIONS)
+  DEBUG_*_X64_PP_FLAGS       = -D EFIX64 $(EDK_DSC_GLOBAL_BUILD_OPTIONS) $(DEBUG_BUILD_OPTIONS)
+  RELEASE_*_X64_PP_FLAGS     = -D EFIX64 $(EDK_DSC_GLOBAL_BUILD_OPTIONS)
+  *_*_X64_ASLPP_FLAGS        = -D EDKII_GLUE_PciExpressBaseAddress=0x$(PLATFORM_PCIEXPRESS_BASE)
+  *_*_X64_ASLCC_FLAGS        = -D EDKII_GLUE_PciExpressBaseAddress=0x$(PLATFORM_PCIEXPRESS_BASE)
+  *_*_X64_ASM16_FLAGS        = -D EDKII_GLUE_PciExpressBaseAddress=$(PLATFORM_PCIEXPRESS_BASE)h
+ # *_*_*_BUILD_FLAGS = -s
+  *_*_*_VFR_FLAGS   = -c
+  *_*_*_BUILD_FLAGS = -c
+
+[BuildOptions.Common.EDKII]
+  *_*_IA32_ASM_FLAGS     = $(VP_BUILD_OPTIONS) -D EDKII_GLUE_PciExpressBaseAddress=$(PLATFORM_PCIEXPRESS_BASE)h -DNOCS_S3_SUPPORT
+
+  *_*_IA32_CC_FLAGS      = $(EDK_EDKII_DSC_FEATURE_BUILD_OPTIONS)
+  *_*_IA32_VFRPP_FLAGS   = $(EDK_EDKII_DSC_FEATURE_BUILD_OPTIONS)
+  *_*_IA32_APP_FLAGS     = $(EDK_EDKII_DSC_FEATURE_BUILD_OPTIONS)
+  *_*_IA32_PP_FLAGS      = $(EDK_EDKII_DSC_FEATURE_BUILD_OPTIONS)
+  *_*_IA32_ASLPP_FLAGS   = $(EDK_EDKII_DSC_FEATURE_BUILD_OPTIONS)
+
+  *_*_X64_CC_FLAGS       = $(EDK_EDKII_DSC_FEATURE_BUILD_OPTIONS) $(SOURCE_LEVEL_DEBUG_BUILD_OPTIONS)
+  *_*_X64_VFRPP_FLAGS    = $(EDK_EDKII_DSC_FEATURE_BUILD_OPTIONS)
+  *_*_X64_APP_FLAGS      = $(EDK_EDKII_DSC_FEATURE_BUILD_OPTIONS)
+  *_*_X64_PP_FLAGS       = $(EDK_EDKII_DSC_FEATURE_BUILD_OPTIONS)
+  *_*_X64_ASLPP_FLAGS    = $(EDK_EDKII_DSC_FEATURE_BUILD_OPTIONS)
+
+
+[Components.X64]
+ $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/SysFwUpdateCapsuleDxe.inf
+
+  $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/I2cBus.inf {
+    <PcdsPatchableInModule>
+      gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0xF0000043
+  }
+
+  $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/I2cHost.inf {
+    <PcdsPatchableInModule>
+      gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0xF0000043
+  }
+  $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/I2cPortA0Pio.inf {
+    <PcdsPatchableInModule>
+      gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x00000043
+  }
+
+  $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/I2cMmioDeviceDxe.inf {
+    <PcdsPatchableInModule>
+      gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x00000043
+  }

diff --git a/Vlv2TbltDevicePkg/PlatformPkgIA32.dsc b/Vlv2TbltDevicePkg/PlatformPkgIA32.dsc
new file mode 100644 (file)
index 0000000..113d282
--- /dev/null
+++ b/Vlv2TbltDevicePkg/PlatformPkgIA32.dsc
@@ -0,0 +1,1480 @@
+#/** @file
+# Platform description.
+#
+# Copyright (c) 2012  - 2014, Intel Corporation. All rights reserved.<BR>
+#                                                                                  
+# This program and the accompanying materials are licensed and made available under
+# the terms and conditions of the BSD License that accompanies this distribution.  
+# The full text of the license may be found at                                     
+# http://opensource.org/licenses/bsd-license.php.                                  
+#                                                                                  
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    
+#                                                                                  
+#
+#**/
+
+################################################################################
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+################################################################################
+[Defines]
+  PLATFORM_NAME                       = Vlv2TbltDevicePkg
+  PLATFORM_GUID                       = 465B0A0B-7AC1-443b-8F67-7B8DEC145F90
+  PLATFORM_VERSION                    = 0.1
+  DSC_SPECIFICATION                   = 0x00010005
+
+  #
+  # Set platform specific package/folder name, same as passed from PREBUILD script.
+  # PLATFORM_PACKAGE would be the same as PLATFORM_NAME as well as package build folder
+  # DEFINE only takes effect at R9 DSC and FDF.
+  #
+  DEFINE      PLATFORM_PACKAGE                = Vlv2TbltDevicePkg
+  DEFINE      PLATFORM_RC_PACKAGE             = Vlv2DeviceRefCodePkg
+  DEFINE      PLATFORM_BINARY_PACKAGE         = Vlv2BinaryPkg
+  OUTPUT_DIRECTORY                    = Build/$(PLATFORM_PACKAGE)
+  SUPPORTED_ARCHITECTURES             = IA32
+  BUILD_TARGETS                       = DEBUG|RELEASE
+  SKUID_IDENTIFIER                    = DEFAULT
+
+  DEFINE CPU_ARCH                 =ValleyView2
+  DEFINE PROJECT_SC_FAMILY        =IntelPch
+  DEFINE PROJECT_SC_ROOT          =../$(PLATFORM_RC_PACKAGE)/ValleyView2Soc/SouthCluster
+  DEFINE PROJECT_VLV_ROOT          =../$(PLATFORM_RC_PACKAGE)/ValleyView2Soc/NorthCluster
+
+  DEFINE RC_BINARY_RELEASE        = TRUE
+  #
+  # Platform On/Off features are defined here
+  #
+  #
+  # Platform Support:: Set only one token except Crestview Hills
+  #
+  #   3.BayleyBay
+  #     ENBDT_PF_ENABLE  = TRUE
+  #
+  !include $(PLATFORM_PACKAGE)/AutoPlatformCFG.txt
+  !include $(PLATFORM_PACKAGE)/PlatformPkgConfig.dsc
+
+!if $(X64_CONFIG) == TRUE
+  DEFINE      DXE_ARCHITECTURE        = X64
+  DEFINE      EDK_DXE_ARCHITECTURE    = X64
+  DEFINE      UNDI_DXE_ARCHITECTURE   = 64
+!else
+  DEFINE      DXE_ARCHITECTURE        = IA32
+  DEFINE      EDK_DXE_ARCHITECTURE    = Ia32
+  DEFINE      UNDI_DXE_ARCHITECTURE   = 32
+!endif
+
+  FLASH_DEFINITION                    = $(PLATFORM_PACKAGE)/PlatformPkg.fdf
+!if $(LFMA_ENABLE) == TRUE
+  FIX_LOAD_TOP_MEMORY_ADDRESS         = 0xFFFFFFFFFFFFFFFF
+  DEFINE   TOP_MEMORY_ADDRESS         = 0xFFFFFFFFFFFFFFFF
+!else
+  FIX_LOAD_TOP_MEMORY_ADDRESS         = 0x0
+  DEFINE   TOP_MEMORY_ADDRESS         = 0x0
+!endif
+
+  DEFINE   PLATFORM_PCIEXPRESS_BASE   = 0E0000000
+
+
+################################################################################
+#
+# SKU Identification section - list of all SKU IDs supported by this
+#                              Platform.
+#
+################################################################################
+[SkuIds]
+  0|DEFAULT              # The entry: 0|DEFAULT is reserved and always required.
+
+################################################################################
+#
+# Library Class section - list of all Library Classes needed by this Platform.
+#
+################################################################################
+[LibraryClasses.common]
+  #
+  # Entry point
+  #
+  PeiCoreEntryPoint|MdePkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.inf
+  PeimEntryPoint|MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf
+  DxeCoreEntryPoint|MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf
+  UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf
+  UefiApplicationEntryPoint|MdePkg/Library/UefiApplicationEntryPoint/UefiApplicationEntryPoint.inf
+  DxeSmmDriverEntryPoint|IntelFrameworkPkg/Library/DxeSmmDriverEntryPoint/DxeSmmDriverEntryPoint.inf
+
+  #
+  # Basic
+  #
+  BaseLib|MdePkg/Library/BaseLib/BaseLib.inf
+!if $(SSE2_ENABLE) == TRUE
+  BaseMemoryLib|MdePkg/Library/BaseMemoryLibSse2/BaseMemoryLibSse2.inf
+!else
+  BaseMemoryLib|MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf
+!endif
+  PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf
+  CpuLib|MdePkg/Library/BaseCpuLib/BaseCpuLib.inf
+  IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf
+  PciLib|MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf
+  PciCf8Lib|MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf
+  PciExpressLib|MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf
+  CacheMaintenanceLib|MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf
+  PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
+  PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf
+!if $(RC_BINARY_RELEASE) == TRUE
+  PchPlatformLib|Vlv2TbltDevicePkg/Library/PchPlatformLib/PchPlatformLib.inf
+!endif
+  #
+  # UEFI & PI
+  #
+  UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf
+  UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf
+  UefiRuntimeLib|MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf
+  UefiLib|MdePkg/Library/UefiLib/UefiLib.inf
+  HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf
+  UefiHiiServicesLib|MdeModulePkg/Library/UefiHiiServicesLib/UefiHiiServicesLib.inf
+  DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf
+  UefiDecompressLib|IntelFrameworkModulePkg/Library/BaseUefiTianoCustomDecompressLib/BaseUefiTianoCustomDecompressLib.inf
+  PeiServicesTablePointerLib|MdePkg/Library/PeiServicesTablePointerLibIdt/PeiServicesTablePointerLibIdt.inf
+  PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf
+  DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
+  DxeServicesTableLib|MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf
+  UefiCpuLib|UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.inf
+  UefiUsbLib|MdePkg/Library/UefiUsbLib/UefiUsbLib.inf
+  GenericBdsLib|$(PLATFORM_PACKAGE)/Override/IntelFrameworkModulePkg/Library/GenericBdsLib/GenericBdsLib.inf
+  PlatformBdsLib|$(PLATFORM_PACKAGE)/Library/PlatformBdsLib/PlatformBdsLib.inf
+  NetLib|MdeModulePkg/Library/DxeNetLib/DxeNetLib.inf
+  DpcLib|MdeModulePkg/Library/DxeDpcLib/DxeDpcLib.inf
+  FlashDeviceLib|$(PLATFORM_PACKAGE)/Library/FlashDeviceLib/FlashDeviceLib.inf
+  #
+  # Framework
+  #
+!if $(S3_ENABLE) == TRUE
+  S3BootScriptLib|MdeModulePkg/Library/PiDxeS3BootScriptLib/DxeS3BootScriptLib.inf
+!else
+  S3BootScriptLib|MdePkg/Library/BaseS3BootScriptLibNull/BaseS3BootScriptLibNull.inf
+!endif
+  S3IoLib|MdePkg/Library/BaseS3IoLib/BaseS3IoLib.inf
+  S3PciLib|MdePkg/Library/BaseS3PciLib/BaseS3PciLib.inf
+
+  #
+  # Generic Modules
+  #
+!if $(USB_ENABLE) == TRUE
+  UefiUsbLib|MdePkg/Library/UefiUsbLib/UefiUsbLib.inf
+!endif
+!if $(SCSI_ENABLE) == TRUE
+  UefiScsiLib|MdePkg/Library/UefiScsiLib/UefiScsiLib.inf
+!endif
+!if $(NETWORK_ENABLE) == TRUE
+  NetLib|MdeModulePkg/Library/DxeNetLib/DxeNetLib.inf
+  IpIoLib|MdeModulePkg/Library/DxeIpIoLib/DxeIpIoLib.inf
+  UdpIoLib|MdeModulePkg/Library/DxeUdpIoLib/DxeUdpIoLib.inf
+  TcpIoLib|MdeModulePkg/Library/DxeTcpIoLib/DxeTcpIoLib.inf
+  DpcLib|MdeModulePkg/Library/DxeDpcLib/DxeDpcLib.inf
+!endif
+!if $(S3_ENABLE) == TRUE
+  S3Lib|IntelFrameworkModulePkg/Library/PeiS3Lib/PeiS3Lib.inf
+!endif
+
+  OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.inf
+!if $(CAPSULE_ENABLE) == TRUE
+ CapsuleLib|IntelFrameworkModulePkg/Library/DxeCapsuleLib/DxeCapsuleLib.inf
+!else
+  CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf
+!endif
+  LanguageLib|EdkCompatibilityPkg/Compatibility/Library/UefiLanguageLib/UefiLanguageLib.inf
+  SynchronizationLib|MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf
+  SecurityManagementLib|MdeModulePkg/Library/DxeSecurityManagementLib/DxeSecurityManagementLib.inf
+  IoApicLib|PcAtChipsetPkg/Library/BaseIoApicLib/BaseIoApicLib.inf
+  DebugPrintErrorLevelLib|MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.inf
+
+  #
+  # CPU
+  #
+  MtrrLib|UefiCpuPkg/Library/MtrrLib/MtrrLib.inf
+  LocalApicLib|UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.inf
+  CpuExceptionHandlerLib|MdeModulePkg/Library/CpuExceptionHandlerLibNull/CpuExceptionHandlerLibNull.inf
+
+  #
+  # ICH
+  #
+  SmbusLib|$(PLATFORM_PACKAGE)/Library/SmbusLib/SmbusLib.inf
+  SmmLib|$(PLATFORM_PACKAGE)/Library/PchSmmLib/PchSmmLib.inf
+
+  #
+  # Platform
+  #
+  TimerLib|$(PLATFORM_PACKAGE)/Library/IntelPchAcpiTimerLib/IntelPchAcpiTimerLib.inf
+  ResetSystemLib|$(PLATFORM_PACKAGE)/Library/ResetSystemLib/ResetSystemLib.inf
+
+  PlatformCmosLib|$(PLATFORM_PACKAGE)/Library/PlatformCmosLib/PlatformCmosLib.inf
+
+  #
+  # Misc
+  #
+  MonoStatusCodeLib|$(PLATFORM_PACKAGE)/MonoStatusCode/MonoStatusCode.inf
+!if $(TARGET) == RELEASE
+  DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf
+  SerialPortLib|MdePkg/Library/BaseSerialPortLibNull/BaseSerialPortLibNull.inf
+!else
+  DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
+  SerialPortLib|$(PLATFORM_PACKAGE)/Library/SerialPortLib/SerialPortLib.inf
+!endif
+
+  PerformanceLib|MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibNull.inf
+  PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
+!if $(TPM_ENABLED) == TRUE
+  TpmCommLib|SecurityPkg/Library/TpmCommLib/TpmCommLib.inf
+  Tpm12CommandLib|SecurityPkg/Library/Tpm12CommandLib/Tpm12CommandLib.inf
+  Tpm12DeviceLib|SecurityPkg/Library/Tpm12DeviceLibDTpm/Tpm12DeviceLibDTpm.inf
+
+!endif
+
+!if $(SOURCE_DEBUG_ENABLE) == TRUE
+  PeCoffExtraActionLib|SourceLevelDebugPkg/Library/PeCoffExtraActionLibDebug/PeCoffExtraActionLibDebug.inf
+  DebugCommunicationLib|SourceLevelDebugPkg/Library/DebugCommunicationLibSerialPort/DebugCommunicationLibSerialPort.inf
+  PlatformHookLib|MdeModulePkg/Library/BasePlatformHookLibNull/BasePlatformHookLibNull.inf
+  SerialPortLib|MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.inf
+!else
+  PeCoffExtraActionLib|MdePkg/Library/BasePeCoffExtraActionLibNull/BasePeCoffExtraActionLibNull.inf
+  DebugAgentLib|MdeModulePkg/Library/DebugAgentLibNull/DebugAgentLibNull.inf
+!endif
+
+  #
+  # CryptLib
+  #
+!if $(TPM_ENABLED) == TRUE
+  IntrinsicLib|CryptoPkg/Library/IntrinsicLib/IntrinsicLib.inf
+  OpensslLib|CryptoPkg/Library/OpensslLib/OpensslLib.inf
+!endif
+
+ BiosIdLib|$(PLATFORM_PACKAGE)/Library/BiosIdLib/BiosIdLib.inf
+ CpuIA32Lib|$(PLATFORM_PACKAGE)/Library/CpuIA32Lib/CpuIA32Lib.inf
+
+  StallSmmLib|$(PLATFORM_PACKAGE)/Library/StallSmmLib/StallSmmLib.inf
+
+ !if $(SECURE_BOOT_ENABLE) == TRUE
+   OpensslLib|CryptoPkg/Library/OpensslLib/OpensslLib.inf
+   IntrinsicLib|CryptoPkg/Library/IntrinsicLib/IntrinsicLib.inf
+   PlatformSecureLib|SecurityPkg/Library/PlatformSecureLibNull/PlatformSecureLibNull.inf
+ !endif
+!if $(RC_BINARY_RELEASE) == TRUE
+  I2cLib|Vlv2TbltDevicePkg/Library/I2CLib/I2CLibNull.inf
+!endif
+  ShellCEntryLib|ShellPkg/Library/UefiShellCEntryLib/UefiShellCEntryLib.inf
+  ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf
+  FileHandleLib|ShellPkg/Library/UefiFileHandleLib/UefiFileHandleLib.inf
+  SortLib|ShellPkg/Library/UefiSortLib/UefiSortLib.inf
+
+  TpmMeasurementLib|SecurityPkg/Library/DxeTpmMeasurementLib/DxeTpmMeasurementLib.inf
+  TrEEPhysicalPresenceLib|SecurityPkg/Library/DxeTrEEPhysicalPresenceLib/DxeTrEEPhysicalPresenceLib.inf
+  Tpm2CommandLib|SecurityPkg/Library/Tpm2CommandLib/Tpm2CommandLib.inf
+!if $(MINNOW2_FSP_BUILD) == TRUE
+  FspApiLib|IntelFspWrapperPkg/Library/BaseFspApiLib/BaseFspApiLib.inf
+  FspPlatformInfoLib|IntelFspWrapperPkg/Library/BaseFspPlatformInfoLibSample/BaseFspPlatformInfoLibSample.inf
+  FspPlatformSecLib|Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecLibVlv2/FspPlatformSecLibVlv2.inf
+  FspHobProcessLib|Vlv2TbltDevicePkg/FspSupport/Library/PeiFspHobProcessLibVlv2/FspHobProcessLibVlv2.inf
+!endif
+
+[LibraryClasses.IA32.SEC]
+!if $(PERFORMANCE_ENABLE) == TRUE
+  PerformanceLib|MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibNull.inf
+!endif
+  DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf
+  PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
+
+[LibraryClasses.IA32.PEIM, LibraryClasses.IA32.PEI_CORE, LibraryClasses.IA32.SEC]
+  #
+  # PEI phase common
+  #
+
+  PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
+  HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf
+  MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf
+  ReportStatusCodeLib|MdeModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf
+  ExtractGuidedSectionLib|MdePkg/Library/PeiExtractGuidedSectionLib/PeiExtractGuidedSectionLib.inf
+  MultiPlatformLib|$(PLATFORM_PACKAGE)/Library/MultiPlatformLib/MultiPlatformLib.inf
+  BaseCryptLib|CryptoPkg/Library/BaseCryptLib/PeiCryptLib.inf
+
+
+!if $(PERFORMANCE_ENABLE) == TRUE
+  PerformanceLib|MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanceLib.inf
+  TimerLib|PerformancePkg/Library/TscTimerLib/PeiTscTimerLib.inf
+!endif
+
+!if $(TARGET) == RELEASE
+  DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf
+  SerialPortLib|MdePkg/Library/BaseSerialPortLibNull/BaseSerialPortLibNull.inf
+!else
+  DebugLib|IntelFrameworkModulePkg/Library/PeiDxeDebugLibReportStatusCode/PeiDxeDebugLibReportStatusCode.inf
+  SerialPortLib|$(PLATFORM_PACKAGE)/Library/SerialPortLib/SerialPortLib.inf
+!endif
+
+  LockBoxLib|MdeModulePkg/Library/SmmLockBoxLib/SmmLockBoxPeiLib.inf
+  HashLib|SecurityPkg/Library/HashLibBaseCryptoRouter/HashLibBaseCryptoRouterPei.inf
+  PeCoffExtraActionLib|MdePkg/Library/BasePeCoffExtraActionLibNull/BasePeCoffExtraActionLibNull.inf
+  DebugAgentLib|MdeModulePkg/Library/DebugAgentLibNull/DebugAgentLibNull.inf
+
+ !if $(MINNOW2_FSP_BUILD) == TRUE
+ PlatformFspLib|Vlv2TbltDevicePkg/Library/PlatformFspLib/PlatformFspLib.inf
+ !endif
+
+
+
+[LibraryClasses.IA32]
+  #
+  # DXE phase common
+  #
+  HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
+  PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
+  MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
+  ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeReportStatusCodeLib.inf
+  ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf
+
+  TcgPhysicalPresenceLib|SecurityPkg/Library/DxeTcgPhysicalPresenceLib/DxeTcgPhysicalPresenceLib.inf
+!if $(TPM_ENABLED) == TRUE
+  BaseCryptLib|CryptoPkg/Library/BaseCryptLib/BaseCryptLib.inf
+!endif
+
+  LockBoxLib|MdeModulePkg/Library/SmmLockBoxLib/SmmLockBoxDxeLib.inf
+  EfiRegTableLib|$(PLATFORM_PACKAGE)/Library/EfiRegTableLib/EfiRegTableLib.inf
+
+!if $(SECURE_BOOT_ENABLE) == TRUE
+  BaseCryptLib|CryptoPkg/Library/BaseCryptLib/BaseCryptLib.inf
+!endif
+
+  HashLib|SecurityPkg/Library/HashLibBaseCryptoRouter/HashLibBaseCryptoRouterDxe.inf
+
+[LibraryClasses.IA32.DXE_DRIVER]
+  DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf
+  PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
+  PerformanceLib|MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibNull.inf
+  CustomizedDisplayLib|MdeModulePkg/Library/CustomizedDisplayLib/CustomizedDisplayLib.inf
+!if $(PERFORMANCE_ENABLE) == TRUE
+  PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf
+  TimerLib|PerformancePkg/Library/TscTimerLib/DxeTscTimerLib.inf
+!endif
+
+!if $(SOURCE_DEBUG_ENABLE) == TRUE
+  DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/DxeDebugAgentLib.inf
+!endif
+
+[LibraryClasses.IA32.DXE_CORE]
+  HobLib|MdePkg/Library/DxeCoreHobLib/DxeCoreHobLib.inf
+  MemoryAllocationLib|MdeModulePkg/Library/DxeCoreMemoryAllocationLib/DxeCoreMemoryAllocationLib.inf
+  PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
+!if $(PERFORMANCE_ENABLE) == TRUE
+  PerformanceLib|MdeModulePkg/Library/DxeCorePerformanceLib/DxeCorePerformanceLib.inf
+  TimerLib|PerformancePkg/Library/TscTimerLib/DxeTscTimerLib.inf
+!endif
+
+!if $(SOURCE_DEBUG_ENABLE) == TRUE
+  DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/DxeDebugAgentLib.inf
+!endif
+
+[LibraryClasses.IA32.DXE_SMM_DRIVER]
+  SmmServicesTableLib|MdePkg/Library/SmmServicesTableLib/SmmServicesTableLib.inf
+  ReportStatusCodeLib|MdeModulePkg/Library/SmmReportStatusCodeLib/SmmReportStatusCodeLib.inf
+  MemoryAllocationLib|MdePkg/Library/SmmMemoryAllocationLib/SmmMemoryAllocationLib.inf
+  LockBoxLib|MdeModulePkg/Library/SmmLockBoxLib/SmmLockBoxSmmLib.inf
+  PerformanceLib|MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibNull.inf
+
+  BaseCryptLib|CryptoPkg/Library/BaseCryptLib/SmmCryptLib.inf
+  !if $(TARGET) != RELEASE
+  DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
+  !endif
+
+!if $(SOURCE_DEBUG_ENABLE) == TRUE
+  DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/SmmDebugAgentLib.inf
+  TimerLib|$(PLATFORM_PACKAGE)/Library/IntelPchAcpiTimerLib/IntelPchAcpiTimerLib.inf
+!endif
+  CpuExceptionHandlerLib|UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmCpuExceptionHandlerLib.inf
+
+[LibraryClasses.IA32.SMM_CORE]
+  MemoryAllocationLib|MdeModulePkg/Library/PiSmmCoreMemoryAllocationLib/PiSmmCoreMemoryAllocationLib.inf
+  SmmServicesTableLib|MdeModulePkg/Library/PiSmmCoreSmmServicesTableLib/PiSmmCoreSmmServicesTableLib.inf
+  ReportStatusCodeLib|MdeModulePkg/Library/SmmReportStatusCodeLib/SmmReportStatusCodeLib.inf
+  SmmCorePlatformHookLib|MdeModulePkg/Library/SmmCorePlatformHookLibNull/SmmCorePlatformHookLibNull.inf
+
+!if $(TPM_ENABLED) == TRUE
+  BaseCryptLib|CryptoPkg/Library/BaseCryptLib/SmmCryptLib.inf
+!endif
+
+  PerformanceLib|MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibNull.inf
+
+!if $(TARGET) != RELEASE
+      DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
+!endif
+
+!if $(SOURCE_DEBUG_ENABLE) == TRUE
+  DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/DxeDebugAgentLib.inf
+  TimerLib|$(PLATFORM_PACKAGE)/Library/IntelPchAcpiTimerLib/IntelPchAcpiTimerLib.inf
+!endif
+
+[LibraryClasses.IA32.DXE_RUNTIME_DRIVER]
+  ReportStatusCodeLib|MdeModulePkg/Library/RuntimeDxeReportStatusCodeLib/RuntimeDxeReportStatusCodeLib.inf
+!if $(SECURE_BOOT_ENABLE) == TRUE
+  BaseCryptLib|CryptoPkg/Library/BaseCryptLib/RuntimeCryptLib.inf
+!endif
+!if $(TPM_ENABLED) == TRUE
+  BaseCryptLib|CryptoPkg/Library/BaseCryptLib/RuntimeCryptLib.inf
+!endif
+
+!if $(SOURCE_DEBUG_ENABLE) == TRUE
+  DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/DxeDebugAgentLib.inf
+!endif
+
+[LibraryClasses.common.UEFI_DRIVER]
+  PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
+
+!if $(SOURCE_DEBUG_ENABLE) == TRUE
+  DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/DxeDebugAgentLib.inf
+!endif
+
+[LibraryClasses.IA32.UEFI_APPLICATION]
+  PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
+
+!if $(SOURCE_DEBUG_ENABLE) == TRUE
+  DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/DxeDebugAgentLib.inf
+!endif
+
+
+################################################################################
+#
+# Library Section - list of all EDK/Framework libraries
+#
+################################################################################
+[Libraries.common]
+  EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/BaseLib/BaseLib.inf
+  EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/BaseMemoryLib/BaseMemoryLib.inf
+  EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/BasePrintLib/BasePrintLib.inf
+  EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/BaseDebugLibNull/BaseDebugLibNull.inf
+  EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf
+  EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf
+  EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/BasePciCf8Lib/BasePciCf8Lib.inf
+  EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/BasePciExpressLib/BasePciExpressLib.inf
+  EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/BasePciLibCf8/BasePciLibCf8.inf
+  EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf
+  EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf
+  EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/BasePeCoffLib/BasePeCoffLib.inf
+  EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/SmmRuntimeDxeReportStatusCodeLib/SmmRuntimeDxeReportStatusCodeLib.inf
+  EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/PeiHobLib/PeiHobLib.inf
+  EdkCompatibilityPkg/Foundation/Ppi/EdkPpiLib.inf
+  EdkCompatibilityPkg/Foundation/Library/Pei/PeiLib/PeiLib.inf
+  EdkCompatibilityPkg/Compatibility/Library/UefiLanguageLib/UefiLanguageLib.inf
+  EdkCompatibilityPkg/Foundation/Guid/EdkGuidLib.inf
+  EdkCompatibilityPkg/Foundation/Efi/Protocol/EfiProtocolLib.inf
+  EdkCompatibilityPkg/Foundation/Library/Dxe/EfiDriverLib/EfiDriverLib.inf
+  EdkCompatibilityPkg/Foundation/Protocol/EdkProtocolLib.inf
+  EdkCompatibilityPkg/Foundation/Framework/Protocol/EdkFrameworkProtocolLib.inf
+[Libraries.IA32]
+  EdkCompatibilityPkg/Foundation/Efi/Guid/EfiGuidLib.inf
+  EdkCompatibilityPkg/Foundation/Framework/Guid/EdkFrameworkGuidLib.inf
+  EdkCompatibilityPkg/Foundation/Library/EfiCommonLib/EfiCommonLib.inf
+  EdkCompatibilityPkg/Foundation/Cpu/Pentium/CpuIA32Lib/CpuIA32Lib.inf
+  EdkCompatibilityPkg/Foundation/Library/CompilerStub/CompilerStubLib.inf
+  EdkCompatibilityPkg/Foundation/Framework/Ppi/EdkFrameworkPpiLib.inf
+  EdkCompatibilityPkg/Foundation/Library/Pei/Hob/PeiHobLib.inf
+  EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/PeiServicesTablePointerLibMm7/PeiServicesTablePointerLibMm7.inf
+  EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf
+  EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/PeiServicesLib/PeiServicesLib.inf
+  EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf
+  EdkCompatibilityPkg/Foundation/Core/Dxe/ArchProtocol/ArchProtocolLib.inf
+
+  $(PLATFORM_PACKAGE)/Library/MultiPlatformLib/MultiPlatformLib.inf
+[Libraries.IA32]
+
+  EdkCompatibilityPkg/Foundation/Efi/Guid/EfiGuidLib.inf
+  EdkCompatibilityPkg/Foundation/Framework/Guid/EdkFrameworkGuidLib.inf
+  EdkCompatibilityPkg/Foundation/Library/EfiCommonLib/EfiCommonLib.inf
+  EdkCompatibilityPkg/Foundation/Cpu/Pentium/CpuIA32Lib/CpuIA32Lib.inf
+  EdkCompatibilityPkg/Foundation/Library/CompilerStub/CompilerStubLib.inf
+  EdkCompatibilityPkg/Foundation/Framework/Ppi/EdkFrameworkPpiLib.inf
+  EdkCompatibilityPkg/Foundation/Core/Dxe/ArchProtocol/ArchProtocolLib.inf
+  EdkCompatibilityPkg/Foundation/Library/Dxe/Hob/HobLib.inf
+  EdkCompatibilityPkg/Foundation/Library/RuntimeDxe/EfiRuntimeLib/EfiRuntimeLib.inf
+  EdkCompatibilityPkg/Foundation/Library/Dxe/EfiIfrSupportLib/EfiIfrSupportLib.inf
+  EdkCompatibilityPkg/Foundation/Library/Dxe/Print/PrintLib.inf
+  EdkCompatibilityPkg/Foundation/Library/Dxe/EfiScriptLib/EfiScriptLib.inf
+  EdkCompatibilityPkg/Foundation/Library/Dxe/PrintLite/PrintLib.inf
+  EdkCompatibilityPkg/Foundation/Library/Dxe/GraphicsLite/Graphics.inf
+  EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf
+  EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/DxeMemoryAllocationLib/DxeMemoryAllocationLib.inf
+  EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/UefiLib/UefiLib.inf
+  EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/DxeHobLib/DxeHobLib.inf
+  EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf
+  EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/DxeReportStatusCodeLib/DxeReportStatusCodeLib.inf
+  EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/HiiLib/HiiLib.inf
+  EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/UefiDevicePathLib/UefiDevicePathLib.inf
+  EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/UefiDriverModelLib/UefiDriverModelLib.inf
+  EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/DxeServicesTableLib/DxeServicesTableLib.inf
+  EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/EdkDxeRuntimeDriverLib/EdkDxeRuntimeDriverLib.inf
+
+
+################################################################################
+#
+# Pcd Section - list of all EDK II PCD Entries defined by this Platform
+#
+################################################################################
+[PcdsFeatureFlag.common]
+!if $(MINI_BIOS_ENABLE) == FALSE
+  gPlatformModuleTokenSpaceGuid.PcdBdsDispatchAdditionalOprom|TRUE
+!else
+  gPlatformModuleTokenSpaceGuid.PcdBdsDispatchAdditionalOprom|FALSE
+!endif
+#
+# If PcdDxeIplSwitchToLongMode is TRUE, DxeIpl will load a 64-bit DxeCore and switch to long mode to hand over to DxeCore.
+#
+  gEfiMdeModulePkgTokenSpaceGuid.PcdDxeIplSwitchToLongMode|FALSE
+
+  gEfiMdeModulePkgTokenSpaceGuid.PcdBrowserGrayOutTextStatement|TRUE
+
+!if $(CAPSULE_RESET_ENABLE) == TRUE
+  gEfiMdeModulePkgTokenSpaceGuid.PcdSupportUpdateCapsuleReset|TRUE
+!else
+  gEfiMdeModulePkgTokenSpaceGuid.PcdSupportUpdateCapsuleReset|FALSE
+!endif
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFrameworkCompatibilitySupport|TRUE
+  gEfiCpuTokenSpaceGuid.PcdCpuSmmEnableBspElection|FALSE
+!if $(DATAHUB_STATUS_CODE_ENABLE) == TRUE
+  gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdStatusCodeUseDataHub|TRUE
+!else
+  gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdStatusCodeUseDataHub|FALSE
+!endif
+  gEfiMdeModulePkgTokenSpaceGuid.PcdPeiCoreImageLoaderSearchTeSectionFirst|FALSE
+!if $(TARGET) == RELEASE
+  gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|FALSE
+!else
+  gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|FALSE
+!endif
+  gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseMemory|FALSE
+!if $(ISA_SERIAL_STATUS_CODE_ENABLE) == TRUE
+  gEfiSerialPortTokenSpaceGuid.PcdStatusCodeUseIsaSerial|TRUE
+!else
+  gEfiSerialPortTokenSpaceGuid.PcdStatusCodeUseIsaSerial|FALSE
+!endif
+!if $(USB_SERIAL_STATUS_CODE_ENABLE) == TRUE
+  gEfiSerialPortTokenSpaceGuid.PcdStatusCodeUseUsbSerial|TRUE
+!else
+  gEfiSerialPortTokenSpaceGuid.PcdStatusCodeUseUsbSerial|FALSE
+!endif
+!if $(RAM_SERIAL_STATUS_CODE_ENABLE) == TRUE
+  gEfiSerialPortTokenSpaceGuid.PcdStatusCodeUseRam|TRUE
+!else
+  gEfiSerialPortTokenSpaceGuid.PcdStatusCodeUseRam|FALSE
+!endif
+
+
+  ## This PCD specifies whether PS2 keyboard does a extended verification during start.
+  gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdPs2KbdExtendedVerification|FALSE
+
+  ## This PCD specifies whether PS2 mouse does a extended verification during start.
+  gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdPs2MouseExtendedVerification|FALSE
+
+!if $(VARIABLE_INFO_ENABLE) == TRUE
+  gEfiMdeModulePkgTokenSpaceGuid.PcdVariableCollectStatistics|TRUE
+!else
+  gEfiMdeModulePkgTokenSpaceGuid.PcdVariableCollectStatistics|FALSE
+!endif
+
+  gEfiCpuTokenSpaceGuid.PcdCpuSmmBlockStartupThisAp|TRUE
+
+[PcdsFixedAtBuild.common]
+!if $(MINNOW2_FSP_BUILD) == TRUE
+# $(FLASH_REGION_VLVMICROCODE_BASE)
+  gFspWrapperTokenSpaceGuid.PcdCpuMicrocodePatchAddress|0xFFE00000
+# $(FLASH_REGION_VLVMICROCODE_SIZE)
+  gFspWrapperTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize|0x00030000
+  gFspWrapperTokenSpaceGuid.PcdFlashMicroCodeOffset|0x60
+# $(FLASH_AREA_BASE_ADDRESS)
+  gFspWrapperTokenSpaceGuid.PcdFlashCodeCacheAddress|0xFF800000
+# $(FLASH_AREA_SIZE)
+  gFspWrapperTokenSpaceGuid.PcdFlashCodeCacheSize|0x00800000
+# $(FLASH_REGION_FSPBIN_BASE)
+  gFspWrapperTokenSpaceGuid.PcdFlashFvFspBase|0xFFDB0000
+!endif
+
+!if $(PERFORMANCE_ENABLE) == TRUE
+!if $(MINNOW2_FSP_BUILD) == TRUE
+  # in FSP, when this got used, the memory already is up
+  gEfiCpuTokenSpaceGuid.PcdTemporaryRamBase|0x00080000
+!else
+  gEfiCpuTokenSpaceGuid.PcdTemporaryRamBase|0xFEF80000
+!endif
+  gEfiCpuTokenSpaceGuid.PcdTemporaryRamSize|0x00010000
+
+!else
+  !if $(MINNOW2_FSP_BUILD) == TRUE
+    gEfiCpuTokenSpaceGuid.PcdTemporaryRamBase|0x00080000
+  !else
+    gEfiCpuTokenSpaceGuid.PcdTemporaryRamBase|0xFEF80000
+  !endif
+  gEfiCpuTokenSpaceGuid.PcdTemporaryRamSize|0x00010000
+  gEfiCpuTokenSpaceGuid.PcdPeiTemporaryRamStackSize|0x3C00
+!endif
+
+
+!if $(SECURE_BOOT_ENABLE) == TRUE
+  gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x22000
+!else
+  gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x4000
+!endif
+  gEfiMdeModulePkgTokenSpaceGuid.PcdHwErrStorageSize|0x00000800
+  gEfiMdeModulePkgTokenSpaceGuid.PcdMaxHardwareErrorVariableSize|0x400
+  gEfiCpuTokenSpaceGuid.PcdCpuIEDRamSize|0x400000
+  gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdS3AcpiReservedMemorySize|0x10000
+  gEfiMdeModulePkgTokenSpaceGuid.PcdPeiCoreMaxPeimPerFv|50
+  gEfiMdeModulePkgTokenSpaceGuid.PcdSrIovSupport|FALSE
+  gEfiMdeModulePkgTokenSpaceGuid.PcdAriSupport|FALSE
+  gEfiMdeModulePkgTokenSpaceGuid.PcdPeiCoreMaxPpiSupported|128
+  gEfiCpuTokenSpaceGuid.PcdCpuSmmApSyncTimeout|1000
+!if $(S4_ENABLE) == TRUE
+  gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|TRUE
+!else
+  gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|FALSE
+!endif
+!if $(TARGET) == RELEASE
+  gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x0
+  gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x3
+!else
+  gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2F
+  gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07
+!endif
+!if $(PERFORMANCE_ENABLE) == TRUE
+  gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|0x1
+  gEfiMdeModulePkgTokenSpaceGuid.PcdMaxPeiPerformanceLogEntries|60
+!endif
+
+  gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdEbdaReservedMemorySize|0x10000
+  gEfiMdeModulePkgTokenSpaceGuid.PcdLoadModuleAtFixAddressEnable|$(TOP_MEMORY_ADDRESS)
+  gEfiMdeModulePkgTokenSpaceGuid.PcdBrowserSubtitleTextColor|0x0
+  gEfiMdeModulePkgTokenSpaceGuid.PcdBrowserFieldTextColor|0x01
+  gEfiCpuTokenSpaceGuid.PcdCpuIEDEnabled|TRUE
+  gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdBiosVideoCheckVbeEnable|TRUE
+  gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdBiosVideoCheckVgaEnable|TRUE
+
+!if $(SOURCE_DEBUG_ENABLE) == TRUE
+  gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x17
+  gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07
+  gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseHardwareFlowControl|FALSE
+!endif
+
+[PcdsFixedAtBuild.IA32.PEIM, PcdsFixedAtBuild.IA32.PEI_CORE, PcdsFixedAtBuild.IA32.SEC]
+!if $(TARGET) == RELEASE
+  gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x0
+  gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x3
+!else
+  gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2E
+  gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07
+!endif
+
+[PcdsPatchableInModule.common]
+  gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x803805c6
+  gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x$(PLATFORM_PCIEXPRESS_BASE)
+  gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdLegacyBiosCacheLegacyRegion|FALSE
+
+  ## This PCD specifies whether to use the optimized timing for best PS2 detection performance.
+  #  Note this PCD could be set to TRUE for best boot performance and set to FALSE for best device compatibility.
+  gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdFastPS2Detection|TRUE
+
+[PcdsDynamicHii.common.DEFAULT]
+  gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVariableGuid|0x0|5 # Variable: L"Timeout"
+  gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdHardwareErrorRecordLevel|L"HwErrRecSupport"|gEfiGlobalVariableGuid|0x0|1 # Variable: L"HwErrRecSupport"
+  gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdBootState|L"BootState"|gEfiBootStateGuid|0x0|TRUE
+
+[PcdsDynamicDefault.common.DEFAULT]
+  gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateDataPtr|0x0
+  !if $(TPM_ENABLED) == TRUE
+    gEfiSecurityPkgTokenSpaceGuid.PcdTpmInstanceGuid|{0x7b, 0x3a, 0xcd, 0x72, 0xA5, 0xFE, 0x5e, 0x4f, 0x91, 0x65, 0x4d, 0xd1, 0x21, 0x87, 0xbb, 0x13}
+  !endif
+
+  ## This PCD defines the video horizontal resolution.
+  #  This PCD could be set to 0 then video resolution could be at highest resolution.
+  gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution|0
+  ## This PCD defines the video vertical resolution.
+  #  This PCD could be set to 0 then video resolution could be at highest resolution.
+  gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution|0
+
+  ## This PCD defines the Console output column and the default value is 25 according to UEFI spec.
+  #  This PCD could be set to 0 then console output could be at max column and max row.
+  gEfiMdeModulePkgTokenSpaceGuid.PcdConOutRow|31
+  ## This PCD defines the Console output row and the default value is 80 according to UEFI spec.
+  #  This PCD could be set to 0 then console output could be at max column and max row.
+  gEfiMdeModulePkgTokenSpaceGuid.PcdConOutColumn|100
+
+  ## The PCD is used to specify the video horizontal resolution of text setup.
+  gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdSetupVideoHorizontalResolution|800
+  ## The PCD is used to specify the video vertical resolution of text setup.
+  gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdSetupVideoVerticalResolution|600
+  ## The PCD is used to specify the console output column of text setup.
+  gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdSetupConOutColumn|100
+  ## The PCD is used to specify the console output column of text setup.
+  gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdSetupConOutRow|31
+
+!if $(TPM_ENABLED) == TRUE
+  gEfiSecurityPkgTokenSpaceGuid.PcdTpmInitializationPolicy|1
+  gEfiSecurityPkgTokenSpaceGuid.PcdTpmScrtmPolicy|1
+!endif
+
+[PcdsDynamicExDefault.common.DEFAULT]
+  gEfiVLVTokenSpaceGuid.PcdTCSmbaIoBaseAddress|0x1040
+  gEfiVLVTokenSpaceGuid.PcdEmmcManufacturerId|0
+  gEfiVLVTokenSpaceGuid.PcdProductSerialNumber|0
+  gEfiVLVTokenSpaceGuid.PcdMeasuredBootEnable|TRUE
+  gEfiVLVTokenSpaceGuid.PcdFTPMErrorOccur|FALSE
+  gEfiVLVTokenSpaceGuid.PcdFTPMErrorSkip|FALSE
+  gEfiVLVTokenSpaceGuid.PcdFTPMCommand|0
+  gEfiVLVTokenSpaceGuid.PcdFTPMResponse|0
+  gEfiVLVTokenSpaceGuid.PcdFTPMNotRespond|FALSE
+  gEfiVLVTokenSpaceGuid.PcdFTPMStatus|0
+
+[Components.IA32]
+
+  $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/SecCore.inf
+
+  !if $(MINNOW2_FSP_BUILD) == TRUE
+  IntelFspWrapperPkg/FspWrapperSecCore/FspWrapperSecCore.inf {
+    !if $(TARGET) == DEBUG
+
+    <LibraryClasses>
+      DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
+    !endif
+  }
+  Vlv2TbltDevicePkg/FspSupport/BootModePei/BootModePei.inf
+  IntelFspWrapperPkg/FspInitPei/FspInitPei.inf {
+    !if $(TARGET) == DEBUG
+    <LibraryClasses>
+      DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
+    !endif
+  }
+  !endif
+
+  MdeModulePkg/Core/Pei/PeiMain.inf {
+!if $(TARGET) == DEBUG
+    <PcdsFixedAtBuild>
+      gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2E
+!endif
+    <PcdsPatchableInModule>
+      gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80000046
+  }
+
+  $(PLATFORM_PACKAGE)/MonoStatusCode/MonoStatusCode.inf {
+!if $(TARGET) == DEBUG
+    <PcdsFixedAtBuild>
+      gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2E
+!endif
+  }
+  $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/MemoryInit.inf {
+    <PcdsPatchableInModule>
+      gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80000046
+  }
+
+!if $(RC_BINARY_RELEASE) == TRUE
+  $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/SeCUma.inf
+!endif
+
+!if $(RC_BINARY_RELEASE) == TRUE
+  $(PLATFORM_PACKAGE)/PlatformPei/PlatformPei.inf {
+    <BuildOptions>
+      *_*_IA32_CC_FLAGS      = /DRC_BINARY_RELEASE
+  !if $(TARGET) == DEBUG
+      <PcdsFixedAtBuild>
+        gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2E
+  !endif
+  }
+!endif
+
+!if $(SOURCE_DEBUG_ENABLE) == TRUE
+  SourceLevelDebugPkg/DebugAgentPei/DebugAgentPei.inf{
+    <LibraryClasses>
+      PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
+      DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/SecPeiDebugAgentLib.inf
+      PlatformHookLib|MdeModulePkg/Library/BasePlatformHookLibNull/BasePlatformHookLibNull.inf
+      SerialPortLib|MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.inf
+    }
+!endif
+
+
+!if $(TPM_ENABLED) == TRUE
+  SecurityPkg/Tcg/PhysicalPresencePei/PhysicalPresencePei.inf
+  SecurityPkg/Tcg/TcgPei/TcgPei.inf {
+    <LibraryClasses>
+      NULL|SecurityPkg/Library/HashInstanceLibSha1/HashInstanceLibSha1.inf
+      NULL|SecurityPkg/Library/HashInstanceLibSha256/HashInstanceLibSha256.inf
+      PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf
+}
+!endif
+
+ $(PLATFORM_PACKAGE)/PlatformInitPei/PlatformInitPei.inf {
+    <PcdsPatchableInModule>
+      gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x803805c6
+    <LibraryClasses>
+!if $(TARGET) != RELEASE
+      DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
+!endif
+      PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf
+  }
+  $(PLATFORM_PACKAGE)/FvInfoPei/FvInfoPei.inf
+
+  $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/VlvInitPeim.inf
+!if $(PCIESC_ENABLE) == TRUE
+  $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/PchEarlyInitPeim.inf {
+    <PcdsPatchableInModule>
+      gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80000046
+  }
+!endif
+  $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/PchInitPeim.inf
+
+
+  $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/PchSmbusArpDisabled.inf
+  $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/PchSpiPeim.inf
+  $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/PeiSmmAccess.inf
+  $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/PeiSmmControl.inf
+  MdeModulePkg/Universal/PCD/Pei/Pcd.inf
+  $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/CpuPeim.inf
+  UefiCpuPkg/CpuIoPei/CpuIoPei.inf
+  UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume2Pei.inf
+  $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/MpS3.inf
+  EdkCompatibilityPkg/Compatibility/AcpiVariableHobOnSmramReserveHobThunk/AcpiVariableHobOnSmramReserveHobThunk.inf
+  $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/PiSmmCommunicationPei.inf
+!if $(CAPSULE_ENABLE) == TRUE
+  MdeModulePkg/Universal/CapsulePei/CapsulePei.inf
+!endif
+  MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf {
+    <LibraryClasses>
+!if $(LZMA_ENABLE) == TRUE
+    NULL|IntelFrameworkModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf
+!endif
+  }
+
+!if $(SECURE_BOOT_ENABLE) == TRUE
+ SecurityPkg/VariableAuthenticated/Pei/VariablePei.inf
+!else
+ MdeModulePkg/Universal/Variable/Pei/VariablePei.inf
+!endif
+ MdeModulePkg/Universal/FaultTolerantWritePei/FaultTolerantWritePei.inf
+
+!if $(TPM_ENABLED) == TRUE
+  SecurityPkg/Tcg/TrEEConfig/TrEEConfigPei.inf {
+    <LibraryClasses>
+      PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf
+  }
+!endif
+!if $(ACPI50_ENABLE) == TRUE
+  MdeModulePkg/Universal/Acpi/FirmwarePerformanceDataTablePei/FirmwarePerformancePei.inf{
+    <LibraryClasses>
+      TimerLib|$(PLATFORM_PACKAGE)/Library/IntelPchAcpiTimerLib/IntelPchAcpiTimerLib.inf
+  }
+
+!endif
+!if $(PERFORMANCE_ENABLE) == TRUE
+  MdeModulePkg/Universal/ReportStatusCodeRouter/Pei/ReportStatusCodeRouterPei.inf
+!endif
+[Components.IA32]
+  !if $(MINNOW2_FSP_BUILD) == TRUE
+  IntelFspWrapperPkg/FspNotifyDxe/FspNotifyDxe.inf {
+    !if $(TARGET) == DEBUG
+    <PcdsPatchableInModule>
+      gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80000046
+    <LibraryClasses>
+      DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
+    !endif
+  }
+
+  !endif
+  #
+  # EDK II Related Platform codes
+  #
+  MdeModulePkg/Core/Dxe/DxeMain.inf {
+    <PcdsPatchableInModule>
+      gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80000046
+    <LibraryClasses>
+!if $(DXE_CRC32_SECTION_ENABLE) == TRUE
+      NULL|MdeModulePkg/Library/DxeCrc32GuidedSectionExtractLib/DxeCrc32GuidedSectionExtractLib.inf
+!endif
+!if $(LZMA_ENABLE) == TRUE
+      NULL|IntelFrameworkModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf
+!endif
+!if $(TARGET) != RELEASE
+      DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
+!endif
+  }
+  IntelFrameworkModulePkg/Universal/Acpi/AcpiS3SaveDxe/AcpiS3SaveDxe.inf {
+    <PcdsPatchableInModule>
+        gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0xF0000043
+    <PcdsFixedAtBuild>
+        gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x27
+    <LibraryClasses>
+    !if $(TARGET) != RELEASE
+          DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
+    !endif
+       <BuildOptions>
+        ICC:*_*_*_CC_FLAGS = /D MDEPKG_NDEBUG
+        GCC:*_*_*_CC_FLAGS = -D MDEPKG_NDEBUG
+  }
+  MdeModulePkg/Universal/PCD/Dxe/Pcd.inf {
+    <LibraryClasses>
+      PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
+  }
+  IntelFrameworkModulePkg/Universal/CpuIoDxe/CpuIoDxe.inf
+  UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.inf
+!if $(PERFORMANCE_ENABLE) == TRUE
+  MdeModulePkg/Universal/ReportStatusCodeRouter/Pei/ReportStatusCodeRouterPei.inf
+!endif
+  MdeModulePkg/Universal/ReportStatusCodeRouter/RuntimeDxe/ReportStatusCodeRouterRuntimeDxe.inf
+  MdeModulePkg/Universal/StatusCodeHandler/RuntimeDxe/StatusCodeHandlerRuntimeDxe.inf  {
+    <LibraryClasses>
+!if $(TARGET) != RELEASE
+      DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
+!endif
+  }
+
+!if $(CAPSULE_ENABLE) == TRUE
+  MdeModulePkg/Universal/CapsulePei/CapsuleX64.inf {
+    <LibraryClasses>
+    PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf
+    MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf
+    HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf
+  }
+!endif
+
+  MdeModulePkg/Universal/ReportStatusCodeRouter/Smm/ReportStatusCodeRouterSmm.inf
+  MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf{
+    <LibraryClasses>
+!if $(SECURE_BOOT_ENABLE) == TRUE
+      NULL|SecurityPkg/Library/DxeImageVerificationLib/DxeImageVerificationLib.inf
+!endif
+!if $(USER_IDENTIFICATION_ENABLE)
+      NULL|SecurityPkg/Library/DxeDeferImageLoadLib/DxeDeferImageLoadLib.inf
+!endif
+!if $(TPM_ENABLED) == TRUE
+      NULL|SecurityPkg/Library/DxeTpmMeasureBootLib/DxeTpmMeasureBootLib.inf
+!endif
+  }
+  $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/MpCpu.inf
+  $(PLATFORM_PACKAGE)/Metronome/Metronome.inf
+
+  IntelFrameworkModulePkg/Universal/BdsDxe/BdsDxe.inf{
+    <LibraryClasses>
+      OpensslLib|CryptoPkg/Library/OpensslLib/OpensslLib.inf
+      IntrinsicLib|CryptoPkg/Library/IntrinsicLib/IntrinsicLib.inf
+      BaseCryptLib|CryptoPkg/Library/BaseCryptLib/BaseCryptLib.inf
+      PlatformBdsLib|$(PLATFORM_PACKAGE)/Library/PlatformBdsLib/PlatformBdsLib.inf
+      DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
+      PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
+      SerialPortLib|$(PLATFORM_PACKAGE)/Library/SerialPortLib/SerialPortLib.inf
+  }
+
+  $(PLATFORM_PACKAGE)/UiApp/UiApp.inf
+
+  MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
+  MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
+  MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
+!if $(SECURE_BOOT_ENABLE) == TRUE
+  SecurityPkg/VariableAuthenticated/RuntimeDxe/VariableSmmRuntimeDxe.inf
+  SecurityPkg/VariableAuthenticated/RuntimeDxe/VariableSmm.inf{
+    <LibraryClasses>
+      PlatformSecureLib|SecurityPkg/Library/PlatformSecureLibNull/PlatformSecureLibNull.inf
+      SerialPortLib|$(PLATFORM_PACKAGE)/Library/SerialPortLib/SerialPortLib.inf
+  }
+  $(PLATFORM_PACKAGE)/FvbRuntimeDxe/FvbSmm.inf
+  MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteSmm.inf
+  $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/PchSpiSmm.inf
+  SecurityPkg/VariableAuthenticated/SecureBootConfigDxe/SecureBootConfigDxe.inf {
+    <LibraryClasses>
+      PlatformSecureLib|SecurityPkg/Library/PlatformSecureLibNull/PlatformSecureLibNull.inf
+    <BuildOptions>
+      #
+      # Specify GUID gEfiIfrBootMaintenanceGuid, to install Secure Boot Configuration menu
+      # into Boot Maintenance Manager menu
+      #
+      *_*_*_VFR_FLAGS   = -g b2dedc91-d59f-48d2-898a-12490c74a4e0
+  }
+ !else
+  MdeModulePkg/Universal/Variable/RuntimeDxe/VariableSmmRuntimeDxe.inf
+  MdeModulePkg/Universal/Variable/RuntimeDxe/VariableSmm.inf
+  $(PLATFORM_PACKAGE)/FvbRuntimeDxe/FvbSmm.inf
+  MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteSmm.inf
+  $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/PchSpiSmm.inf
+!endif
+   MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf {
+    <LibraryClasses>
+      FileHandleLib|ShellPkg/Library/UefiFileHandleLib/UefiFileHandleLib.inf
+  }
+
+  MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf
+  PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcatRealTimeClockRuntimeDxe.inf
+  MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
+
+  $(PLATFORM_PACKAGE)/FvbRuntimeDxe/FvbRuntimeDxe.inf
+
+  $(PLATFORM_PACKAGE)/PlatformSetupDxe/PlatformSetupDxe.inf
+
+!if $(DATAHUB_ENABLE) == TRUE
+  IntelFrameworkModulePkg/Universal/DataHubDxe/DataHubDxe.inf {
+    <PcdsFixedAtBuild>
+      gEfiMdePkgTokenSpaceGuid.PcdMaximumLinkedListLength|0
+  }
+!endif
+  IntelFrameworkModulePkg/Universal/StatusCode/DatahubStatusCodeHandlerDxe/DatahubStatusCodeHandlerDxe.inf
+  MdeModulePkg/Universal/MemoryTest/NullMemoryTestDxe/NullMemoryTestDxe.inf
+  $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/PchS3SupportDxe.inf
+  !if $(USE_HPET_TIMER) == TRUE
+    PcAtChipsetPkg/HpetTimerDxe/HpetTimerDxe.inf
+  !else
+  $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/SmartTimer.inf
+  !endif
+  $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/SmmControl.inf
+
+  $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/PchSmbusDxe.inf
+  $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/IntelPchLegacyInterrupt.inf
+  $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/PchReset.inf
+  $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/PchInitDxe.inf{
+    <PcdsPatchableInModule>
+        gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0xF0000043
+  }
+  $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/PchSmiDispatcher.inf
+
+!if $(PCIESC_ENABLE) == TRUE
+  $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/PchPcieSmm.inf
+!endif
+  $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/PchSpiRuntime.inf
+  $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/PchPolicyInitDxe.inf
+  $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/PchBiosWriteProtect.inf
+  $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/SmmAccess.inf
+  $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/PciHostBridge.inf
+  $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/VlvInitDxe.inf
+
+  IntelFrameworkModulePkg/Universal/LegacyRegionDxe/LegacyRegionDxe.inf
+
+  Vlv2TbltDevicePkg/VlvPlatformInitDxe/VlvPlatformInitDxe.inf{
+    <LibraryClasses>
+!if $(TARGET) != RELEASE
+      DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
+!endif
+      PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
+  }
+
+  $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/Dptf.inf
+  $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/PnpDxe.inf
+
+!if $(TPM_ENABLED) == TRUE
+  SecurityPkg/Tcg/TrEEConfig/TrEEConfigPei.inf {
+    <LibraryClasses>
+      PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf
+  }
+
+  SecurityPkg/Tcg/TcgConfigDxe/TcgConfigDxe.inf {
+    <LibraryClasses>
+      PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
+    <BuildOptions>
+      #
+      # specify GUID gEfiIfrNotInTPVPageGuid, this page will not
+      # be showed in TPV page.
+      #
+      *_*_*_VFR_FLAGS   = -g e58809f8-fbc1-48e2-883a-a30fdc4b441e
+  }
+
+  SecurityPkg/Tcg/TcgDxe/TcgDxe.inf {
+    <LibraryClasses>
+      PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
+  }
+  SecurityPkg/Tcg/TcgSmm/TcgSmm.inf
+!endif
+  #
+  # EDK II Related Platform codes
+  #
+  $(PLATFORM_PACKAGE)/PlatformSmm/PlatformSmm.inf{
+    <LibraryClasses>
+    !if $(TARGET) != RELEASE
+          DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
+    !endif
+          PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
+  }
+  $(PLATFORM_PACKAGE)/PlatformInfoDxe/PlatformInfoDxe.inf
+  $(PLATFORM_PACKAGE)/PlatformCpuInfoDxe/PlatformCpuInfoDxe.inf
+  $(PLATFORM_PACKAGE)/PlatformDxe/PlatformDxe.inf
+
+  $(PLATFORM_PACKAGE)/PciPlatform/PciPlatform.inf
+  $(PLATFORM_PACKAGE)/SaveMemoryConfig/SaveMemoryConfig.inf
+  $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/PlatformCpuPolicy.inf
+  $(PLATFORM_PACKAGE)/PpmPolicy/PpmPolicy.inf
+  $(PLATFORM_PACKAGE)/SmramSaveInfoHandlerSmm/SmramSaveInfoHandlerSmm.inf
+!if $(GOP_DRIVER_ENABLE) == TRUE
+  $(PLATFORM_PACKAGE)/PlatformGopPolicy/PlatformGopPolicy.inf
+
+!endif
+
+
+  #
+  # SMM
+  #
+  MdeModulePkg/Core/PiSmmCore/PiSmmIpl.inf
+  MdeModulePkg/Core/PiSmmCore/PiSmmCore.inf
+  $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/PiSmmCpuDxeSmm.inf
+  UefiCpuPkg/CpuIo2Smm/CpuIo2Smm.inf
+  MdeModulePkg/Universal/LockBox/SmmLockBox/SmmLockBox.inf
+  $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/PiSmmCommunicationSmm.inf
+  $(PLATFORM_PACKAGE)/SmmSwDispatch2OnSmmSwDispatchThunk/SmmSwDispatch2OnSmmSwDispatchThunk.inf
+  $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/PowerManagement2.inf
+
+  #
+  # ACPI
+  #
+   MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/BootScriptExecutorDxe.inf {
+    <PcdsPatchableInModule>
+      gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0xF0000043
+    <PcdsFixedAtBuild>
+      gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x27
+    <LibraryClasses>
+      PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
+  }
+
+  $(PLATFORM_PACKAGE)/BootScriptSaveDxe/BootScriptSaveDxe.inf
+  IntelFrameworkModulePkg/Universal/Acpi/AcpiSupportDxe/AcpiSupportDxe.inf
+  Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/PowerManagement/AcpiTables/PowerManagementAcpiTables.inf
+
+  $(PLATFORM_RC_PACKAGE)/AcpiTablesPCAT/AcpiTables.inf
+
+  $(PLATFORM_PACKAGE)/AcpiPlatform/AcpiPlatform.inf
+
+  #
+  # PCI
+  #
+  MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
+
+
+  $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/ISPDxe.inf
+
+
+#
+# ISA
+#
+  $(PLATFORM_PACKAGE)/Wpce791/Wpce791.inf
+  IntelFrameworkModulePkg/Bus/Isa/IsaBusDxe/IsaBusDxe.inf
+  IntelFrameworkModulePkg/Bus/Isa/IsaIoDxe/IsaIoDxe.inf
+  IntelFrameworkModulePkg/Bus/Isa/IsaSerialDxe/IsaSerialDxe.inf
+  IntelFrameworkModulePkg/Bus/Isa/Ps2MouseDxe/Ps2MouseDxe.inf
+  IntelFrameworkModulePkg/Bus/Isa/Ps2KeyboardDxe/Ps2keyboardDxe.inf
+#
+# SDIO
+#
+  $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/MmcHost.inf
+  $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/MmcMediaDevice.inf
+!if $(ACPI50_ENABLE) == TRUE
+  MdeModulePkg/Universal/Acpi/FirmwarePerformanceDataTableDxe/FirmwarePerformanceDxe.inf {
+    <LibraryClasses>
+      TimerLib|$(PLATFORM_PACKAGE)/Library/IntelPchAcpiTimerLib/IntelPchAcpiTimerLib.inf
+  }
+  MdeModulePkg/Universal/Acpi/FirmwarePerformanceDataTableSmm/FirmwarePerformanceSmm.inf {
+    <LibraryClasses>
+      TimerLib|$(PLATFORM_PACKAGE)/Library/IntelPchAcpiTimerLib/IntelPchAcpiTimerLib.inf
+  }
+!endif
+
+#
+# IDE/SCSI/AHCI
+#
+  MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf
+  IntelFrameworkModulePkg/Bus/Pci/IdeBusDxe/IdeBusDxe.inf
+  MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
+  MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
+  MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
+!if $(SATA_ENABLE) == TRUE
+  $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/SataController.inf
+!endif
+  MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf
+!if $(SCSI_ENABLE) == TRUE
+  MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf
+  MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf
+!endif
+#
+# Console
+#
+  MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
+  Vlv2TbltDevicePkg/Override/MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
+  MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf
+  IntelFrameworkModulePkg/Universal/Console/VgaClassDxe/VgaClassDxe.inf
+  MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
+  MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
+  MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
+  MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
+
+  #
+  # USB
+  #
+!if $(USB_ENABLE) == TRUE
+  MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf
+  MdeModulePkg/Bus/Pci/UhciDxe/UhciDxe.inf
+  MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf
+  MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
+  MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf
+  MdeModulePkg/Bus/Usb/UsbMouseDxe/UsbMouseDxe.inf
+  MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
+
+!endif
+
+  #
+  #  ECP
+  #
+  EdkCompatibilityPkg/Compatibility/FrameworkHiiOnUefiHiiThunk/FrameworkHiiOnUefiHiiThunk.inf
+  EdkCompatibilityPkg/Compatibility/LegacyRegion2OnLegacyRegionThunk/LegacyRegion2OnLegacyRegionThunk.inf
+  EdkCompatibilityPkg/Compatibility/SmmBaseOnSmmBase2Thunk/SmmBaseOnSmmBase2Thunk.inf
+  EdkCompatibilityPkg/Compatibility/SmmBaseHelper/SmmBaseHelper.inf
+  EdkCompatibilityPkg/Compatibility/SmmAccess2OnSmmAccessThunk/SmmAccess2OnSmmAccessThunk.inf
+  EdkCompatibilityPkg/Compatibility/SmmControl2OnSmmControlThunk/SmmControl2OnSmmControlThunk.inf
+  EdkCompatibilityPkg/Compatibility/FrameworkSmmStatusCodeOnPiSmmStatusCodeThunk/FrameworkSmmStatusCodeOnPiSmmStatusCodeThunk.inf
+  EdkCompatibilityPkg/Compatibility/FvOnFv2Thunk/FvOnFv2Thunk.inf
+  #
+  # SMBIOS
+  #
+  MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf
+  $(PLATFORM_PACKAGE)/SmBiosMiscDxe/SmBiosMiscDxe.inf
+
+  $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/SmbiosMemory.inf
+  #
+  # CPU/FW Microde
+  #
+  Vlv2MiscBinariesPkg/Microcode/MicrocodeUpdates.inf {
+    <BuildOptions>
+      *_*_*_GENFW_FLAGS = -a 0x800 -p 0xFF
+  }
+
+
+  PcAtChipsetPkg/8259InterruptControllerDxe/8259.inf
+
+
+!if $(NETWORK_ENABLE) == TRUE
+  !if $(NETWORK_ISCSI_ENABLE) == TRUE
+    !if $(NETWORK_IP6_ENABLE) == TRUE
+      NetworkPkg/IScsiDxe/IScsiDxe.inf
+    !else
+      MdeModulePkg/Universal/Network/IScsiDxe/IScsiDxe.inf
+    !endif
+  !endif
+  !if $(NETWORK_VLAN_ENABLE) == TRUE
+    MdeModulePkg/Universal/Network/VlanConfigDxe/VlanConfigDxe.inf
+  !endif
+  !if $(CSM_ENABLE) == TRUE
+    IntelFrameworkModulePkg/Csm/BiosThunk/Snp16Dxe/Snp16Dxe.inf
+  !endif
+!endif
+
+!if $(NETWORK_ENABLE) == TRUE
+  #
+  # UEFI network modules
+  #
+    MdeModulePkg/Universal/Network/DpcDxe/DpcDxe.inf
+    MdeModulePkg/Universal/Network/SnpDxe/SnpDxe.inf
+
+    MdeModulePkg/Universal/Network/MnpDxe/MnpDxe.inf
+    MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf
+    MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Dxe.inf
+    MdeModulePkg/Universal/Network/Ip4ConfigDxe/Ip4ConfigDxe.inf
+    MdeModulePkg/Universal/Network/Ip4Dxe/Ip4Dxe.inf
+    MdeModulePkg/Universal/Network/Mtftp4Dxe/Mtftp4Dxe.inf
+    MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf {
+      <PcdsPatchableInModule>
+      gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80000000
+    }
+    MdeModulePkg/Universal/Network/Udp4Dxe/Udp4Dxe.inf
+    !if $(NETWORK_IP6_ENABLE) == TRUE
+      NetworkPkg/Ip6Dxe/Ip6Dxe.inf
+      NetworkPkg/Dhcp6Dxe/Dhcp6Dxe.inf
+      NetworkPkg/IpSecDxe/IpSecDxe.inf
+      NetworkPkg/TcpDxe/TcpDxe.inf
+      NetworkPkg/Udp6Dxe/Udp6Dxe.inf
+      NetworkPkg/Mtftp6Dxe/Mtftp6Dxe.inf
+    !endif
+    !if $(NETWORK_IP6_ENABLE) == TRUE
+      NetworkPkg/UefiPxeBcDxe/UefiPxeBcDxe.inf
+    !else
+      MdeModulePkg/Universal/Network/UefiPxeBcDxe/UefiPxeBcDxe.inf
+    !endif
+!endif
+
+  Vlv2TbltDevicePkg/Application/FirmwareUpdate/FirmwareUpdate.inf
+
+[BuildOptions]
+#
+# Define Build Options both for EDK and EDKII drivers.
+#
+
+#
+# Define token for different Platform
+#
+!if $(MINNOW2_FSP_BUILD) == TRUE
+  DEFINE MINNOW2_FSP_OPTION = /DMINNOW2_FSP_BUILD
+!else
+  DEFINE MINNOW2_FSP_OPTION =
+!endif
+
+!if $(ENBDT_PF_BUILD) == TRUE
+  DEFINE ENBDT_PF_ENABLE = /DENBDT_PF_ENABLE=1
+!else
+  DEFINE ENBDT_PF_ENABLE = /DENBDT_PF_ENABLE=0
+!endif
+
+
+!if $(CLKGEN_CONFIG_EXTRA_ENABLE) == TRUE
+  DEFINE CLKGEN_CONFIG_EXTRA_BUILD_OPTION = /DCLKGEN_CONFIG_EXTRA=1
+!else
+  DEFINE CLKGEN_CONFIG_EXTRA_BUILD_OPTION =
+!endif
+
+
+
+!if $(PCIESC_ENABLE) == TRUE
+  DEFINE PCIESC_SUPPORT_BUILD_OPTION = /DPCIESC_SUPPORT=1
+!else
+  DEFINE PCIESC_SUPPORT_BUILD_OPTION =
+!endif
+!if $(SATA_ENABLE) == TRUE
+  DEFINE SATA_SUPPORT_BUILD_OPTION = /DSATA_SUPPORT=1
+!else
+  DEFINE SATA_SUPPORT_BUILD_OPTION =
+!endif
+!if $(ENBDT_S3_SUPPORT) == TRUE
+  DEFINE ENBDT_S3_SUPPORT_OPTIONS = /DNOCS_S3_SUPPORT
+!else
+  DEFINE ENBDT_S3_SUPPORT_OPTIONS =
+!endif
+
+!if $(X64_CONFIG) == TRUE
+  DEFINE X64_BUILD_ENABLE = /DX64_BUILD_ENABLE=1
+!else
+  DEFINE X64_BUILD_ENABLE =
+!endif
+
+!if $(TPM_ENABLED) == TRUE
+  DEFINE DSC_TPM_BUILD_OPTIONS = /DTPM_ENABLED
+!else
+  DEFINE DSC_TPM_BUILD_OPTIONS =
+!endif
+
+
+  DEFINE EDK_EDKII_DSC_FEATURE_BUILD_OPTIONS = $(MINNOW2_FSP_OPTION) $(MINNOW2_BUILD_OPTION) $(ENBDT_PF_ENABLE) $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) $(CLKGEN_CONFIG_EXTRA_BUILD_OPTION) $(SYSCTL_X0_CONVERT_BOARD_OPTION) $(ENBDT_S3_SUPPORT_OPTIONS) $(SATA_SUPPORT_BUILD_OPTION) $(PCIESC_SUPPORT_BUILD_OPTION) $(DSC_FTPM_ERROR_WR_BUILD_OPTIONS) $(DSC_TPM_BUILD_OPTIONS) $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS)
+!if $(PERFORMANCE_ENABLE) == TRUE
+  DEFINE PDB_BUILD_OPTION = /Zi
+!endif
+
+!if $(SOURCE_DEBUG_ENABLE) == TRUE
+  MSFT:*_*_X64_GENFW_FLAGS  = --keepexceptiontable
+  GCC:*_*_X64_GENFW_FLAGS   = --keepexceptiontable
+  INTEL:*_*_X64_GENFW_FLAGS = --keepexceptiontable
+!if $(TARGET) == DEBUG
+  DEFINE SOURCE_LEVEL_DEBUG_BUILD_OPTIONS = /Od /Oy-
+!endif
+!else
+  DEFINE SOURCE_LEVEL_DEBUG_BUILD_OPTIONS =
+
+!endif
+
+[BuildOptions.Common.EDK]
+
+#
+# Define token for different Platform
+#
+!if $(ENBDT_PF_BUILD) == TRUE
+  DEFINE ENBDT_PF_ENABLE = /DENBDT_PF_ENABLE=1
+!else
+  DEFINE ENBDT_PF_ENABLE = /DENBDT_PF_ENABLE=0
+!endif
+
+!if $(PERFORMANCE_ENABLE) == TRUE
+  RELEASE_*_*_DLINK_FLAGS = /DEBUG
+!endif
+
+!if $(S3_ENABLE) == TRUE
+  DEFINE DSC_S3_BUILD_OPTIONS = /DEFI_S3_RESUME
+!else
+  DEFINE DSC_S3_BUILD_OPTIONS =
+!endif
+
+!if $(ENBDT_S3_SUPPORT) == TRUE
+  DEFINE ENBDT_S3_SUPPORT_OPTIONS = /DNOCS_S3_SUPPORT
+!else
+  DEFINE ENBDT_S3_SUPPORT_OPTIONS =
+!endif
+
+!if $(X64_CONFIG) == TRUE
+  DEFINE X64_BUILD_ENABLE = /DX64_BUILD_ENABLE=1
+!else
+  DEFINE X64_BUILD_ENABLE =
+!endif
+
+
+  DEFINE EDK_GLUE_LIB_DEBUG  =
+  DEFINE DEBUG_BUILD_OPTIONS = /D EFI_DEBUG /D DEBUG_MODE=1  /GL- $(EDK_GLUE_LIB_DEBUG) /DEDKII_GLUE_DebugPrintErrorLevel=(EFI_D_ERROR)
+  DEFINE EDK_DSC_FEATURE_BUILD_OPTIONS = $(DSC_S3_BUILD_OPTIONS) $(DSC_ACPI_BUILD_OPTIONS) $(DSC_SEC_BUILD_OPTIONS) $(DSC_FTPM_BUILD_OPTIONS) $(DSC_FTPM_ERROR_WR_BUILD_OPTIONS) $(DSC_TPM_BUILD_OPTIONS) $(SOFTSDV_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(QT_BUILD_OPTIONS) $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) /D$(PROJECT_SC_CHIPSET)
+
+  DEFINE EDK_DSC_OTHER_BUILD_OPTIONS = $(EDK_EDKII_DSC_FEATURE_BUILD_OPTIONS) $(SV_BUILD_OPTIONS) $(INTEL_FASTBOOT_BUILD_OPTION)
+  DEFINE EDK_DSC_GLOBAL_BUILD_OPTIONS = $(ENBDT_PF_ENABLE) $(EDK_DSC_FEATURE_BUILD_OPTIONS) $(EDK_DSC_OTHER_BUILD_OPTIONS) /D EFI_SPECIFICATION_VERSION=0x00020000  /D PI_SPECIFICATION_VERSION=0x00000009  /D TIANO_RELEASE_VERSION=0x00080006 /D SUPPORT_DEPRECATED_PCI_CFG_PPI /D CSM_SMMENTRY_PORT8DATA8 /D EDKII_GLUE_PciExpressBaseAddress=0x$(PLATFORM_PCIEXPRESS_BASE) /D MAX_VARIABLE_SIZE=0x2000 /D EFI_FIRMWARE_VENDOR="L/"INTEL/"" /D EFI_BUILD_VERSION="L/"EDKII/"" /DEFI_PEI_REPORT_STATUS_CODE_ON $(ENBDT_S3_SUPPORT_OPTIONS)
+
+  *_*_IA32_ASM_FLAGS         = /DEFI32 /D EDKII_GLUE_PciExpressBaseAddress=$(PLATFORM_PCIEXPRESS_BASE)h /DNOCS_S3_SUPPORT
+  DEBUG_*_IA32_CC_FLAGS      = /D EFI32 $(EDK_DSC_GLOBAL_BUILD_OPTIONS) $(DEBUG_BUILD_OPTIONS)
+  RELEASE_*_IA32_CC_FLAGS    = /D EFI32 $(EDK_DSC_GLOBAL_BUILD_OPTIONS)
+  DEBUG_*_IA32_VFRPP_FLAGS   = /D EFI32 $(EDK_DSC_GLOBAL_BUILD_OPTIONS) $(DEBUG_BUILD_OPTIONS)
+  RELEASE_*_IA32_VFRPP_FLAGS = /D EFI32 $(EDK_DSC_GLOBAL_BUILD_OPTIONS)
+  DEBUG_*_IA32_APP_FLAGS     = /D EFI32 $(EDK_DSC_GLOBAL_BUILD_OPTIONS) $(DEBUG_BUILD_OPTIONS)
+  RELEASE_*_IA32_APP_FLAGS   = /D EFI32 $(EDK_DSC_GLOBAL_BUILD_OPTIONS)
+  DEBUG_*_IA32_PP_FLAGS      = /D EFI32 $(EDK_DSC_GLOBAL_BUILD_OPTIONS) $(DEBUG_BUILD_OPTIONS)
+  RELEASE_*_IA32_PP_FLAGS    = /D EFI32 $(EDK_DSC_GLOBAL_BUILD_OPTIONS)
+  *_*_IA32_ASLPP_FLAGS       = /D EDKII_GLUE_PciExpressBaseAddress=0x$(PLATFORM_PCIEXPRESS_BASE)
+  *_*_IA32_ASLCC_FLAGS       = /D EDKII_GLUE_PciExpressBaseAddress=0x$(PLATFORM_PCIEXPRESS_BASE)
+  *_*_IA32_ASM16_FLAGS       = /D EDKII_GLUE_PciExpressBaseAddress=$(PLATFORM_PCIEXPRESS_BASE)h
+
+  *_*_X64_ASM_FLAGS          = /DEFIX64 /D EDKII_GLUE_PciExpressBaseAddress=$(PLATFORM_PCIEXPRESS_BASE)h /DNOCS_S3_SUPPORT
+  DEBUG_*_X64_CC_FLAGS       = /D EFIX64 $(EDK_DSC_GLOBAL_BUILD_OPTIONS) $(DEBUG_BUILD_OPTIONS)
+  RELEASE_*_X64_CC_FLAGS     = /D EFIX64 $(EDK_DSC_GLOBAL_BUILD_OPTIONS)
+  DEBUG_*_X64_VFRPP_FLAGS    = /D EFIX64 $(EDK_DSC_GLOBAL_BUILD_OPTIONS) $(DEBUG_BUILD_OPTIONS)
+  RELEASE_*_X64_VFRPP_FLAGS  = /D EFIX64 $(EDK_DSC_GLOBAL_BUILD_OPTIONS)
+  DEBUG_*_X64_APP_FLAGS      = /D EFIX64 $(EDK_DSC_GLOBAL_BUILD_OPTIONS) $(DEBUG_BUILD_OPTIONS)
+  RELEASE_*_X64_APP_FLAGS    = /D EFIX64 $(EDK_DSC_GLOBAL_BUILD_OPTIONS)
+  DEBUG_*_X64_PP_FLAGS       = /D EFIX64 $(EDK_DSC_GLOBAL_BUILD_OPTIONS) $(DEBUG_BUILD_OPTIONS)
+  RELEASE_*_X64_PP_FLAGS     = /D EFIX64 $(EDK_DSC_GLOBAL_BUILD_OPTIONS)
+  *_*_X64_ASLPP_FLAGS        = /D EDKII_GLUE_PciExpressBaseAddress=0x$(PLATFORM_PCIEXPRESS_BASE)
+  *_*_X64_ASLCC_FLAGS        = /D EDKII_GLUE_PciExpressBaseAddress=0x$(PLATFORM_PCIEXPRESS_BASE)
+  *_*_X64_ASM16_FLAGS        = /D EDKII_GLUE_PciExpressBaseAddress=$(PLATFORM_PCIEXPRESS_BASE)h
+ # *_*_*_BUILD_FLAGS = -s
+  *_*_*_VFR_FLAGS   = -c
+  *_*_*_BUILD_FLAGS = -c
+
+[BuildOptions.Common.EDKII]
+  *_*_IA32_ASM_FLAGS     = $(VP_BUILD_OPTIONS) /D EDKII_GLUE_PciExpressBaseAddress=$(PLATFORM_PCIEXPRESS_BASE)h /DNOCS_S3_SUPPORT
+
+  *_*_IA32_CC_FLAGS      = $(EDK_EDKII_DSC_FEATURE_BUILD_OPTIONS)
+  *_*_IA32_VFRPP_FLAGS   = $(EDK_EDKII_DSC_FEATURE_BUILD_OPTIONS)
+  *_*_IA32_APP_FLAGS     = $(EDK_EDKII_DSC_FEATURE_BUILD_OPTIONS)
+  *_*_IA32_PP_FLAGS      = $(EDK_EDKII_DSC_FEATURE_BUILD_OPTIONS)
+  *_*_IA32_ASLPP_FLAGS   = $(EDK_EDKII_DSC_FEATURE_BUILD_OPTIONS)
+
+  *_*_X64_CC_FLAGS       = $(EDK_EDKII_DSC_FEATURE_BUILD_OPTIONS) $(SOURCE_LEVEL_DEBUG_BUILD_OPTIONS)
+  *_*_X64_VFRPP_FLAGS    = $(EDK_EDKII_DSC_FEATURE_BUILD_OPTIONS)
+  *_*_X64_APP_FLAGS      = $(EDK_EDKII_DSC_FEATURE_BUILD_OPTIONS)
+  *_*_X64_PP_FLAGS       = $(EDK_EDKII_DSC_FEATURE_BUILD_OPTIONS)
+  *_*_X64_ASLPP_FLAGS    = $(EDK_EDKII_DSC_FEATURE_BUILD_OPTIONS)
+
+
+[Components.IA32]
+ $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/SysFwUpdateCapsuleDxe.inf
+
+  $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/I2cBus.inf {
+    <PcdsPatchableInModule>
+      gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0xF0000043
+  }
+
+  $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/I2cHost.inf {
+    <PcdsPatchableInModule>
+      gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0xF0000043
+  }
+  $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/I2cPortA0Pio.inf {
+    <PcdsPatchableInModule>
+      gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x00000043
+  }
+
+  $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/I2cMmioDeviceDxe.inf {
+    <PcdsPatchableInModule>
+      gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x00000043
+  }

diff --git a/Vlv2TbltDevicePkg/PlatformPkgX64.dsc b/Vlv2TbltDevicePkg/PlatformPkgX64.dsc
new file mode 100644 (file)
index 0000000..bbfe471
--- /dev/null
+++ b/Vlv2TbltDevicePkg/PlatformPkgX64.dsc
@@ -0,0 +1,1480 @@
+#/** @file
+# Platform description.
+#
+# Copyright (c) 2012  - 2014, Intel Corporation. All rights reserved.<BR>
+#                                                                                  
+# This program and the accompanying materials are licensed and made available under
+# the terms and conditions of the BSD License that accompanies this distribution.  
+# The full text of the license may be found at                                     
+# http://opensource.org/licenses/bsd-license.php.                                  
+#                                                                                  
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    
+#                                                                                  
+#
+#**/
+
+################################################################################
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+################################################################################
+[Defines]
+  PLATFORM_NAME                       = Vlv2TbltDevicePkg
+  PLATFORM_GUID                       = 465B0A0B-7AC1-443b-8F67-7B8DEC145F90
+  PLATFORM_VERSION                    = 0.1
+  DSC_SPECIFICATION                   = 0x00010005
+
+  #
+  # Set platform specific package/folder name, same as passed from PREBUILD script.
+  # PLATFORM_PACKAGE would be the same as PLATFORM_NAME as well as package build folder
+  # DEFINE only takes effect at R9 DSC and FDF.
+  #
+  DEFINE      PLATFORM_PACKAGE                = Vlv2TbltDevicePkg
+  DEFINE      PLATFORM_RC_PACKAGE             = Vlv2DeviceRefCodePkg
+  DEFINE      PLATFORM_BINARY_PACKAGE         = Vlv2BinaryPkg
+  OUTPUT_DIRECTORY                    = Build/$(PLATFORM_PACKAGE)
+  SUPPORTED_ARCHITECTURES             = IA32|X64
+  BUILD_TARGETS                       = DEBUG|RELEASE
+  SKUID_IDENTIFIER                    = DEFAULT
+
+  DEFINE CPU_ARCH                 =ValleyView2
+  DEFINE PROJECT_SC_FAMILY        =IntelPch
+  DEFINE PROJECT_SC_ROOT          =../$(PLATFORM_RC_PACKAGE)/ValleyView2Soc/SouthCluster
+  DEFINE PROJECT_VLV_ROOT          =../$(PLATFORM_RC_PACKAGE)/ValleyView2Soc/NorthCluster
+
+  DEFINE RC_BINARY_RELEASE        = TRUE
+  #
+  # Platform On/Off features are defined here
+  #
+  #
+  # Platform Support:: Set only one token except Crestview Hills
+  #
+  #   3.BayleyBay
+  #     ENBDT_PF_ENABLE  = TRUE
+  #
+  !include $(PLATFORM_PACKAGE)/AutoPlatformCFG.txt
+  !include $(PLATFORM_PACKAGE)/PlatformPkgConfig.dsc
+
+!if $(X64_CONFIG) == TRUE
+  DEFINE      DXE_ARCHITECTURE        = X64
+  DEFINE      EDK_DXE_ARCHITECTURE    = X64
+  DEFINE      UNDI_DXE_ARCHITECTURE   = 64
+!else
+  DEFINE      DXE_ARCHITECTURE        = IA32
+  DEFINE      EDK_DXE_ARCHITECTURE    = Ia32
+  DEFINE      UNDI_DXE_ARCHITECTURE   = 32
+!endif
+
+  FLASH_DEFINITION                    = $(PLATFORM_PACKAGE)/PlatformPkg.fdf
+!if $(LFMA_ENABLE) == TRUE
+  FIX_LOAD_TOP_MEMORY_ADDRESS         = 0xFFFFFFFFFFFFFFFF
+  DEFINE   TOP_MEMORY_ADDRESS         = 0xFFFFFFFFFFFFFFFF
+!else
+  FIX_LOAD_TOP_MEMORY_ADDRESS         = 0x0
+  DEFINE   TOP_MEMORY_ADDRESS         = 0x0
+!endif
+
+  DEFINE   PLATFORM_PCIEXPRESS_BASE   = 0E0000000
+
+
+################################################################################
+#
+# SKU Identification section - list of all SKU IDs supported by this
+#                              Platform.
+#
+################################################################################
+[SkuIds]
+  0|DEFAULT              # The entry: 0|DEFAULT is reserved and always required.
+
+################################################################################
+#
+# Library Class section - list of all Library Classes needed by this Platform.
+#
+################################################################################
+[LibraryClasses.common]
+  #
+  # Entry point
+  #
+  PeiCoreEntryPoint|MdePkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.inf
+  PeimEntryPoint|MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf
+  DxeCoreEntryPoint|MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf
+  UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf
+  UefiApplicationEntryPoint|MdePkg/Library/UefiApplicationEntryPoint/UefiApplicationEntryPoint.inf
+  DxeSmmDriverEntryPoint|IntelFrameworkPkg/Library/DxeSmmDriverEntryPoint/DxeSmmDriverEntryPoint.inf
+
+  #
+  # Basic
+  #
+  BaseLib|MdePkg/Library/BaseLib/BaseLib.inf
+!if $(SSE2_ENABLE) == TRUE
+  BaseMemoryLib|MdePkg/Library/BaseMemoryLibSse2/BaseMemoryLibSse2.inf
+!else
+  BaseMemoryLib|MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf
+!endif
+  PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf
+  CpuLib|MdePkg/Library/BaseCpuLib/BaseCpuLib.inf
+  IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf
+  PciLib|MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf
+  PciCf8Lib|MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf
+  PciExpressLib|MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf
+  CacheMaintenanceLib|MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf
+  PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
+  PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf
+!if $(RC_BINARY_RELEASE) == TRUE
+  PchPlatformLib|Vlv2TbltDevicePkg/Library/PchPlatformLib/PchPlatformLib.inf
+!endif
+  #
+  # UEFI & PI
+  #
+  UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf
+  UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf
+  UefiRuntimeLib|MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf
+  UefiLib|MdePkg/Library/UefiLib/UefiLib.inf
+  HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf
+  UefiHiiServicesLib|MdeModulePkg/Library/UefiHiiServicesLib/UefiHiiServicesLib.inf
+  DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf
+  UefiDecompressLib|IntelFrameworkModulePkg/Library/BaseUefiTianoCustomDecompressLib/BaseUefiTianoCustomDecompressLib.inf
+  PeiServicesTablePointerLib|MdePkg/Library/PeiServicesTablePointerLibIdt/PeiServicesTablePointerLibIdt.inf
+  PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf
+  DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
+  DxeServicesTableLib|MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf
+  UefiCpuLib|UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.inf
+  UefiUsbLib|MdePkg/Library/UefiUsbLib/UefiUsbLib.inf
+  GenericBdsLib|$(PLATFORM_PACKAGE)/Override/IntelFrameworkModulePkg/Library/GenericBdsLib/GenericBdsLib.inf
+  PlatformBdsLib|$(PLATFORM_PACKAGE)/Library/PlatformBdsLib/PlatformBdsLib.inf
+  NetLib|MdeModulePkg/Library/DxeNetLib/DxeNetLib.inf
+  DpcLib|MdeModulePkg/Library/DxeDpcLib/DxeDpcLib.inf
+  FlashDeviceLib|$(PLATFORM_PACKAGE)/Library/FlashDeviceLib/FlashDeviceLib.inf
+  #
+  # Framework
+  #
+!if $(S3_ENABLE) == TRUE
+  S3BootScriptLib|MdeModulePkg/Library/PiDxeS3BootScriptLib/DxeS3BootScriptLib.inf
+!else
+  S3BootScriptLib|MdePkg/Library/BaseS3BootScriptLibNull/BaseS3BootScriptLibNull.inf
+!endif
+  S3IoLib|MdePkg/Library/BaseS3IoLib/BaseS3IoLib.inf
+  S3PciLib|MdePkg/Library/BaseS3PciLib/BaseS3PciLib.inf
+
+  #
+  # Generic Modules
+  #
+!if $(USB_ENABLE) == TRUE
+  UefiUsbLib|MdePkg/Library/UefiUsbLib/UefiUsbLib.inf
+!endif
+!if $(SCSI_ENABLE) == TRUE
+  UefiScsiLib|MdePkg/Library/UefiScsiLib/UefiScsiLib.inf
+!endif
+!if $(NETWORK_ENABLE) == TRUE
+  NetLib|MdeModulePkg/Library/DxeNetLib/DxeNetLib.inf
+  IpIoLib|MdeModulePkg/Library/DxeIpIoLib/DxeIpIoLib.inf
+  UdpIoLib|MdeModulePkg/Library/DxeUdpIoLib/DxeUdpIoLib.inf
+  TcpIoLib|MdeModulePkg/Library/DxeTcpIoLib/DxeTcpIoLib.inf
+  DpcLib|MdeModulePkg/Library/DxeDpcLib/DxeDpcLib.inf
+!endif
+!if $(S3_ENABLE) == TRUE
+  S3Lib|IntelFrameworkModulePkg/Library/PeiS3Lib/PeiS3Lib.inf
+!endif
+
+  OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.inf
+!if $(CAPSULE_ENABLE) == TRUE
+ CapsuleLib|IntelFrameworkModulePkg/Library/DxeCapsuleLib/DxeCapsuleLib.inf
+!else
+  CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf
+!endif
+  LanguageLib|EdkCompatibilityPkg/Compatibility/Library/UefiLanguageLib/UefiLanguageLib.inf
+  SynchronizationLib|MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf
+  SecurityManagementLib|MdeModulePkg/Library/DxeSecurityManagementLib/DxeSecurityManagementLib.inf
+  IoApicLib|PcAtChipsetPkg/Library/BaseIoApicLib/BaseIoApicLib.inf
+  DebugPrintErrorLevelLib|MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.inf
+
+  #
+  # CPU
+  #
+  MtrrLib|UefiCpuPkg/Library/MtrrLib/MtrrLib.inf
+  LocalApicLib|UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.inf
+  CpuExceptionHandlerLib|MdeModulePkg/Library/CpuExceptionHandlerLibNull/CpuExceptionHandlerLibNull.inf
+
+  #
+  # ICH
+  #
+  SmbusLib|$(PLATFORM_PACKAGE)/Library/SmbusLib/SmbusLib.inf
+  SmmLib|$(PLATFORM_PACKAGE)/Library/PchSmmLib/PchSmmLib.inf
+
+  #
+  # Platform
+  #
+  TimerLib|$(PLATFORM_PACKAGE)/Library/IntelPchAcpiTimerLib/IntelPchAcpiTimerLib.inf
+  ResetSystemLib|$(PLATFORM_PACKAGE)/Library/ResetSystemLib/ResetSystemLib.inf
+
+  PlatformCmosLib|$(PLATFORM_PACKAGE)/Library/PlatformCmosLib/PlatformCmosLib.inf
+
+  #
+  # Misc
+  #
+  MonoStatusCodeLib|$(PLATFORM_PACKAGE)/MonoStatusCode/MonoStatusCode.inf
+!if $(TARGET) == RELEASE
+  DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf
+  SerialPortLib|MdePkg/Library/BaseSerialPortLibNull/BaseSerialPortLibNull.inf
+!else
+  DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
+  SerialPortLib|$(PLATFORM_PACKAGE)/Library/SerialPortLib/SerialPortLib.inf
+!endif
+
+  PerformanceLib|MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibNull.inf
+  PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
+!if $(TPM_ENABLED) == TRUE
+  TpmCommLib|SecurityPkg/Library/TpmCommLib/TpmCommLib.inf
+  Tpm12CommandLib|SecurityPkg/Library/Tpm12CommandLib/Tpm12CommandLib.inf
+  Tpm12DeviceLib|SecurityPkg/Library/Tpm12DeviceLibDTpm/Tpm12DeviceLibDTpm.inf
+
+!endif
+
+!if $(SOURCE_DEBUG_ENABLE) == TRUE
+  PeCoffExtraActionLib|SourceLevelDebugPkg/Library/PeCoffExtraActionLibDebug/PeCoffExtraActionLibDebug.inf
+  DebugCommunicationLib|SourceLevelDebugPkg/Library/DebugCommunicationLibSerialPort/DebugCommunicationLibSerialPort.inf
+  PlatformHookLib|MdeModulePkg/Library/BasePlatformHookLibNull/BasePlatformHookLibNull.inf
+  SerialPortLib|MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.inf
+!else
+  PeCoffExtraActionLib|MdePkg/Library/BasePeCoffExtraActionLibNull/BasePeCoffExtraActionLibNull.inf
+  DebugAgentLib|MdeModulePkg/Library/DebugAgentLibNull/DebugAgentLibNull.inf
+!endif
+
+  #
+  # CryptLib
+  #
+!if $(TPM_ENABLED) == TRUE
+  IntrinsicLib|CryptoPkg/Library/IntrinsicLib/IntrinsicLib.inf
+  OpensslLib|CryptoPkg/Library/OpensslLib/OpensslLib.inf
+!endif
+
+ BiosIdLib|$(PLATFORM_PACKAGE)/Library/BiosIdLib/BiosIdLib.inf
+ CpuIA32Lib|$(PLATFORM_PACKAGE)/Library/CpuIA32Lib/CpuIA32Lib.inf
+
+  StallSmmLib|$(PLATFORM_PACKAGE)/Library/StallSmmLib/StallSmmLib.inf
+
+ !if $(SECURE_BOOT_ENABLE) == TRUE
+   OpensslLib|CryptoPkg/Library/OpensslLib/OpensslLib.inf
+   IntrinsicLib|CryptoPkg/Library/IntrinsicLib/IntrinsicLib.inf
+   PlatformSecureLib|SecurityPkg/Library/PlatformSecureLibNull/PlatformSecureLibNull.inf
+ !endif
+!if $(RC_BINARY_RELEASE) == TRUE
+  I2cLib|Vlv2TbltDevicePkg/Library/I2CLib/I2CLibNull.inf
+!endif
+  ShellCEntryLib|ShellPkg/Library/UefiShellCEntryLib/UefiShellCEntryLib.inf
+  ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf
+  FileHandleLib|ShellPkg/Library/UefiFileHandleLib/UefiFileHandleLib.inf
+  SortLib|ShellPkg/Library/UefiSortLib/UefiSortLib.inf
+
+  TpmMeasurementLib|SecurityPkg/Library/DxeTpmMeasurementLib/DxeTpmMeasurementLib.inf
+  TrEEPhysicalPresenceLib|SecurityPkg/Library/DxeTrEEPhysicalPresenceLib/DxeTrEEPhysicalPresenceLib.inf
+  Tpm2CommandLib|SecurityPkg/Library/Tpm2CommandLib/Tpm2CommandLib.inf
+!if $(MINNOW2_FSP_BUILD) == TRUE
+  FspApiLib|IntelFspWrapperPkg/Library/BaseFspApiLib/BaseFspApiLib.inf
+  FspPlatformInfoLib|IntelFspWrapperPkg/Library/BaseFspPlatformInfoLibSample/BaseFspPlatformInfoLibSample.inf
+  FspPlatformSecLib|Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecLibVlv2/FspPlatformSecLibVlv2.inf
+  FspHobProcessLib|Vlv2TbltDevicePkg/FspSupport/Library/PeiFspHobProcessLibVlv2/FspHobProcessLibVlv2.inf
+!endif
+
+[LibraryClasses.IA32.SEC]
+!if $(PERFORMANCE_ENABLE) == TRUE
+  PerformanceLib|MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibNull.inf
+!endif
+  DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf
+  PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
+
+[LibraryClasses.IA32.PEIM, LibraryClasses.IA32.PEI_CORE, LibraryClasses.IA32.SEC]
+  #
+  # PEI phase common
+  #
+
+  PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
+  HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf
+  MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf
+  ReportStatusCodeLib|MdeModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf
+  ExtractGuidedSectionLib|MdePkg/Library/PeiExtractGuidedSectionLib/PeiExtractGuidedSectionLib.inf
+  MultiPlatformLib|$(PLATFORM_PACKAGE)/Library/MultiPlatformLib/MultiPlatformLib.inf
+  BaseCryptLib|CryptoPkg/Library/BaseCryptLib/PeiCryptLib.inf
+
+
+!if $(PERFORMANCE_ENABLE) == TRUE
+  PerformanceLib|MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanceLib.inf
+  TimerLib|PerformancePkg/Library/TscTimerLib/PeiTscTimerLib.inf
+!endif
+
+!if $(TARGET) == RELEASE
+  DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf
+  SerialPortLib|MdePkg/Library/BaseSerialPortLibNull/BaseSerialPortLibNull.inf
+!else
+  DebugLib|IntelFrameworkModulePkg/Library/PeiDxeDebugLibReportStatusCode/PeiDxeDebugLibReportStatusCode.inf
+  SerialPortLib|$(PLATFORM_PACKAGE)/Library/SerialPortLib/SerialPortLib.inf
+!endif
+
+  LockBoxLib|MdeModulePkg/Library/SmmLockBoxLib/SmmLockBoxPeiLib.inf
+  HashLib|SecurityPkg/Library/HashLibBaseCryptoRouter/HashLibBaseCryptoRouterPei.inf
+  PeCoffExtraActionLib|MdePkg/Library/BasePeCoffExtraActionLibNull/BasePeCoffExtraActionLibNull.inf
+  DebugAgentLib|MdeModulePkg/Library/DebugAgentLibNull/DebugAgentLibNull.inf
+
+ !if $(MINNOW2_FSP_BUILD) == TRUE
+ PlatformFspLib|Vlv2TbltDevicePkg/Library/PlatformFspLib/PlatformFspLib.inf
+ !endif
+
+
+
+[LibraryClasses.X64]
+  #
+  # DXE phase common
+  #
+  HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
+  PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
+  MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
+  ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeReportStatusCodeLib.inf
+  ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf
+
+  TcgPhysicalPresenceLib|SecurityPkg/Library/DxeTcgPhysicalPresenceLib/DxeTcgPhysicalPresenceLib.inf
+!if $(TPM_ENABLED) == TRUE
+  BaseCryptLib|CryptoPkg/Library/BaseCryptLib/BaseCryptLib.inf
+!endif
+
+  LockBoxLib|MdeModulePkg/Library/SmmLockBoxLib/SmmLockBoxDxeLib.inf
+  EfiRegTableLib|$(PLATFORM_PACKAGE)/Library/EfiRegTableLib/EfiRegTableLib.inf
+
+!if $(SECURE_BOOT_ENABLE) == TRUE
+  BaseCryptLib|CryptoPkg/Library/BaseCryptLib/BaseCryptLib.inf
+!endif
+
+  HashLib|SecurityPkg/Library/HashLibBaseCryptoRouter/HashLibBaseCryptoRouterDxe.inf
+
+[LibraryClasses.X64.DXE_DRIVER]
+  DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf
+  PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
+  PerformanceLib|MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibNull.inf
+  CustomizedDisplayLib|MdeModulePkg/Library/CustomizedDisplayLib/CustomizedDisplayLib.inf
+!if $(PERFORMANCE_ENABLE) == TRUE
+  PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf
+  TimerLib|PerformancePkg/Library/TscTimerLib/DxeTscTimerLib.inf
+!endif
+
+!if $(SOURCE_DEBUG_ENABLE) == TRUE
+  DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/DxeDebugAgentLib.inf
+!endif
+
+[LibraryClasses.X64.DXE_CORE]
+  HobLib|MdePkg/Library/DxeCoreHobLib/DxeCoreHobLib.inf
+  MemoryAllocationLib|MdeModulePkg/Library/DxeCoreMemoryAllocationLib/DxeCoreMemoryAllocationLib.inf
+  PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
+!if $(PERFORMANCE_ENABLE) == TRUE
+  PerformanceLib|MdeModulePkg/Library/DxeCorePerformanceLib/DxeCorePerformanceLib.inf
+  TimerLib|PerformancePkg/Library/TscTimerLib/DxeTscTimerLib.inf
+!endif
+
+!if $(SOURCE_DEBUG_ENABLE) == TRUE
+  DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/DxeDebugAgentLib.inf
+!endif
+
+[LibraryClasses.X64.DXE_SMM_DRIVER]
+  SmmServicesTableLib|MdePkg/Library/SmmServicesTableLib/SmmServicesTableLib.inf
+  ReportStatusCodeLib|MdeModulePkg/Library/SmmReportStatusCodeLib/SmmReportStatusCodeLib.inf
+  MemoryAllocationLib|MdePkg/Library/SmmMemoryAllocationLib/SmmMemoryAllocationLib.inf
+  LockBoxLib|MdeModulePkg/Library/SmmLockBoxLib/SmmLockBoxSmmLib.inf
+  PerformanceLib|MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibNull.inf
+
+  BaseCryptLib|CryptoPkg/Library/BaseCryptLib/SmmCryptLib.inf
+  !if $(TARGET) != RELEASE
+  DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
+  !endif
+
+!if $(SOURCE_DEBUG_ENABLE) == TRUE
+  DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/SmmDebugAgentLib.inf
+  TimerLib|$(PLATFORM_PACKAGE)/Library/IntelPchAcpiTimerLib/IntelPchAcpiTimerLib.inf
+!endif
+  CpuExceptionHandlerLib|UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmCpuExceptionHandlerLib.inf
+
+[LibraryClasses.X64.SMM_CORE]
+  MemoryAllocationLib|MdeModulePkg/Library/PiSmmCoreMemoryAllocationLib/PiSmmCoreMemoryAllocationLib.inf
+  SmmServicesTableLib|MdeModulePkg/Library/PiSmmCoreSmmServicesTableLib/PiSmmCoreSmmServicesTableLib.inf
+  ReportStatusCodeLib|MdeModulePkg/Library/SmmReportStatusCodeLib/SmmReportStatusCodeLib.inf
+  SmmCorePlatformHookLib|MdeModulePkg/Library/SmmCorePlatformHookLibNull/SmmCorePlatformHookLibNull.inf
+
+!if $(TPM_ENABLED) == TRUE
+  BaseCryptLib|CryptoPkg/Library/BaseCryptLib/SmmCryptLib.inf
+!endif
+
+  PerformanceLib|MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibNull.inf
+
+!if $(TARGET) != RELEASE
+      DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
+!endif
+
+!if $(SOURCE_DEBUG_ENABLE) == TRUE
+  DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/DxeDebugAgentLib.inf
+  TimerLib|$(PLATFORM_PACKAGE)/Library/IntelPchAcpiTimerLib/IntelPchAcpiTimerLib.inf
+!endif
+
+[LibraryClasses.X64.DXE_RUNTIME_DRIVER]
+  ReportStatusCodeLib|MdeModulePkg/Library/RuntimeDxeReportStatusCodeLib/RuntimeDxeReportStatusCodeLib.inf
+!if $(SECURE_BOOT_ENABLE) == TRUE
+  BaseCryptLib|CryptoPkg/Library/BaseCryptLib/RuntimeCryptLib.inf
+!endif
+!if $(TPM_ENABLED) == TRUE
+  BaseCryptLib|CryptoPkg/Library/BaseCryptLib/RuntimeCryptLib.inf
+!endif
+
+!if $(SOURCE_DEBUG_ENABLE) == TRUE
+  DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/DxeDebugAgentLib.inf
+!endif
+
+[LibraryClasses.common.UEFI_DRIVER]
+  PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
+
+!if $(SOURCE_DEBUG_ENABLE) == TRUE
+  DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/DxeDebugAgentLib.inf
+!endif
+
+[LibraryClasses.X64.UEFI_APPLICATION]
+  PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
+
+!if $(SOURCE_DEBUG_ENABLE) == TRUE
+  DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/DxeDebugAgentLib.inf
+!endif
+
+
+################################################################################
+#
+# Library Section - list of all EDK/Framework libraries
+#
+################################################################################
+[Libraries.common]
+  EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/BaseLib/BaseLib.inf
+  EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/BaseMemoryLib/BaseMemoryLib.inf
+  EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/BasePrintLib/BasePrintLib.inf
+  EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/BaseDebugLibNull/BaseDebugLibNull.inf
+  EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf
+  EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf
+  EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/BasePciCf8Lib/BasePciCf8Lib.inf
+  EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/BasePciExpressLib/BasePciExpressLib.inf
+  EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/BasePciLibCf8/BasePciLibCf8.inf
+  EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf
+  EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf
+  EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/BasePeCoffLib/BasePeCoffLib.inf
+  EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/SmmRuntimeDxeReportStatusCodeLib/SmmRuntimeDxeReportStatusCodeLib.inf
+  EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/PeiHobLib/PeiHobLib.inf
+  EdkCompatibilityPkg/Foundation/Ppi/EdkPpiLib.inf
+  EdkCompatibilityPkg/Foundation/Library/Pei/PeiLib/PeiLib.inf
+  EdkCompatibilityPkg/Compatibility/Library/UefiLanguageLib/UefiLanguageLib.inf
+  EdkCompatibilityPkg/Foundation/Guid/EdkGuidLib.inf
+  EdkCompatibilityPkg/Foundation/Efi/Protocol/EfiProtocolLib.inf
+  EdkCompatibilityPkg/Foundation/Library/Dxe/EfiDriverLib/EfiDriverLib.inf
+  EdkCompatibilityPkg/Foundation/Protocol/EdkProtocolLib.inf
+  EdkCompatibilityPkg/Foundation/Framework/Protocol/EdkFrameworkProtocolLib.inf
+[Libraries.IA32]
+  EdkCompatibilityPkg/Foundation/Efi/Guid/EfiGuidLib.inf
+  EdkCompatibilityPkg/Foundation/Framework/Guid/EdkFrameworkGuidLib.inf
+  EdkCompatibilityPkg/Foundation/Library/EfiCommonLib/EfiCommonLib.inf
+  EdkCompatibilityPkg/Foundation/Cpu/Pentium/CpuIA32Lib/CpuIA32Lib.inf
+  EdkCompatibilityPkg/Foundation/Library/CompilerStub/CompilerStubLib.inf
+  EdkCompatibilityPkg/Foundation/Framework/Ppi/EdkFrameworkPpiLib.inf
+  EdkCompatibilityPkg/Foundation/Library/Pei/Hob/PeiHobLib.inf
+  EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/PeiServicesTablePointerLibMm7/PeiServicesTablePointerLibMm7.inf
+  EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf
+  EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/PeiServicesLib/PeiServicesLib.inf
+  EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf
+  EdkCompatibilityPkg/Foundation/Core/Dxe/ArchProtocol/ArchProtocolLib.inf
+
+  $(PLATFORM_PACKAGE)/Library/MultiPlatformLib/MultiPlatformLib.inf
+[Libraries.X64]
+
+  EdkCompatibilityPkg/Foundation/Efi/Guid/EfiGuidLib.inf
+  EdkCompatibilityPkg/Foundation/Framework/Guid/EdkFrameworkGuidLib.inf
+  EdkCompatibilityPkg/Foundation/Library/EfiCommonLib/EfiCommonLib.inf
+  EdkCompatibilityPkg/Foundation/Cpu/Pentium/CpuIA32Lib/CpuIA32Lib.inf
+  EdkCompatibilityPkg/Foundation/Library/CompilerStub/CompilerStubLib.inf
+  EdkCompatibilityPkg/Foundation/Framework/Ppi/EdkFrameworkPpiLib.inf
+  EdkCompatibilityPkg/Foundation/Core/Dxe/ArchProtocol/ArchProtocolLib.inf
+  EdkCompatibilityPkg/Foundation/Library/Dxe/Hob/HobLib.inf
+  EdkCompatibilityPkg/Foundation/Library/RuntimeDxe/EfiRuntimeLib/EfiRuntimeLib.inf
+  EdkCompatibilityPkg/Foundation/Library/Dxe/EfiIfrSupportLib/EfiIfrSupportLib.inf
+  EdkCompatibilityPkg/Foundation/Library/Dxe/Print/PrintLib.inf
+  EdkCompatibilityPkg/Foundation/Library/Dxe/EfiScriptLib/EfiScriptLib.inf
+  EdkCompatibilityPkg/Foundation/Library/Dxe/PrintLite/PrintLib.inf
+  EdkCompatibilityPkg/Foundation/Library/Dxe/GraphicsLite/Graphics.inf
+  EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf
+  EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/DxeMemoryAllocationLib/DxeMemoryAllocationLib.inf
+  EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/UefiLib/UefiLib.inf
+  EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/DxeHobLib/DxeHobLib.inf
+  EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf
+  EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/DxeReportStatusCodeLib/DxeReportStatusCodeLib.inf
+  EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/HiiLib/HiiLib.inf
+  EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/UefiDevicePathLib/UefiDevicePathLib.inf
+  EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/UefiDriverModelLib/UefiDriverModelLib.inf
+  EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/DxeServicesTableLib/DxeServicesTableLib.inf
+  EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/EdkDxeRuntimeDriverLib/EdkDxeRuntimeDriverLib.inf
+
+
+################################################################################
+#
+# Pcd Section - list of all EDK II PCD Entries defined by this Platform
+#
+################################################################################
+[PcdsFeatureFlag.common]
+!if $(MINI_BIOS_ENABLE) == FALSE
+  gPlatformModuleTokenSpaceGuid.PcdBdsDispatchAdditionalOprom|TRUE
+!else
+  gPlatformModuleTokenSpaceGuid.PcdBdsDispatchAdditionalOprom|FALSE
+!endif
+#
+# If PcdDxeIplSwitchToLongMode is TRUE, DxeIpl will load a 64-bit DxeCore and switch to long mode to hand over to DxeCore.
+#
+  gEfiMdeModulePkgTokenSpaceGuid.PcdDxeIplSwitchToLongMode|TRUE
+
+  gEfiMdeModulePkgTokenSpaceGuid.PcdBrowserGrayOutTextStatement|TRUE
+
+!if $(CAPSULE_RESET_ENABLE) == TRUE
+  gEfiMdeModulePkgTokenSpaceGuid.PcdSupportUpdateCapsuleReset|TRUE
+!else
+  gEfiMdeModulePkgTokenSpaceGuid.PcdSupportUpdateCapsuleReset|FALSE
+!endif
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFrameworkCompatibilitySupport|TRUE
+  gEfiCpuTokenSpaceGuid.PcdCpuSmmEnableBspElection|FALSE
+!if $(DATAHUB_STATUS_CODE_ENABLE) == TRUE
+  gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdStatusCodeUseDataHub|TRUE
+!else
+  gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdStatusCodeUseDataHub|FALSE
+!endif
+  gEfiMdeModulePkgTokenSpaceGuid.PcdPeiCoreImageLoaderSearchTeSectionFirst|FALSE
+!if $(TARGET) == RELEASE
+  gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|FALSE
+!else
+  gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|FALSE
+!endif
+  gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseMemory|FALSE
+!if $(ISA_SERIAL_STATUS_CODE_ENABLE) == TRUE
+  gEfiSerialPortTokenSpaceGuid.PcdStatusCodeUseIsaSerial|TRUE
+!else
+  gEfiSerialPortTokenSpaceGuid.PcdStatusCodeUseIsaSerial|FALSE
+!endif
+!if $(USB_SERIAL_STATUS_CODE_ENABLE) == TRUE
+  gEfiSerialPortTokenSpaceGuid.PcdStatusCodeUseUsbSerial|TRUE
+!else
+  gEfiSerialPortTokenSpaceGuid.PcdStatusCodeUseUsbSerial|FALSE
+!endif
+!if $(RAM_SERIAL_STATUS_CODE_ENABLE) == TRUE
+  gEfiSerialPortTokenSpaceGuid.PcdStatusCodeUseRam|TRUE
+!else
+  gEfiSerialPortTokenSpaceGuid.PcdStatusCodeUseRam|FALSE
+!endif
+
+
+  ## This PCD specifies whether PS2 keyboard does a extended verification during start.
+  gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdPs2KbdExtendedVerification|FALSE
+
+  ## This PCD specifies whether PS2 mouse does a extended verification during start.
+  gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdPs2MouseExtendedVerification|FALSE
+
+!if $(VARIABLE_INFO_ENABLE) == TRUE
+  gEfiMdeModulePkgTokenSpaceGuid.PcdVariableCollectStatistics|TRUE
+!else
+  gEfiMdeModulePkgTokenSpaceGuid.PcdVariableCollectStatistics|FALSE
+!endif
+
+  gEfiCpuTokenSpaceGuid.PcdCpuSmmBlockStartupThisAp|TRUE
+
+[PcdsFixedAtBuild.common]
+!if $(MINNOW2_FSP_BUILD) == TRUE
+# $(FLASH_REGION_VLVMICROCODE_BASE)
+  gFspWrapperTokenSpaceGuid.PcdCpuMicrocodePatchAddress|0xFFE00000
+# $(FLASH_REGION_VLVMICROCODE_SIZE)
+  gFspWrapperTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize|0x00030000
+  gFspWrapperTokenSpaceGuid.PcdFlashMicroCodeOffset|0x60
+# $(FLASH_AREA_BASE_ADDRESS)
+  gFspWrapperTokenSpaceGuid.PcdFlashCodeCacheAddress|0xFF800000
+# $(FLASH_AREA_SIZE)
+  gFspWrapperTokenSpaceGuid.PcdFlashCodeCacheSize|0x00800000
+# $(FLASH_REGION_FSPBIN_BASE)
+  gFspWrapperTokenSpaceGuid.PcdFlashFvFspBase|0xFFDB0000
+!endif
+
+!if $(PERFORMANCE_ENABLE) == TRUE
+!if $(MINNOW2_FSP_BUILD) == TRUE
+  # in FSP, when this got used, the memory already is up
+  gEfiCpuTokenSpaceGuid.PcdTemporaryRamBase|0x00080000
+!else
+  gEfiCpuTokenSpaceGuid.PcdTemporaryRamBase|0xFEF80000
+!endif
+  gEfiCpuTokenSpaceGuid.PcdTemporaryRamSize|0x00010000
+
+!else
+  !if $(MINNOW2_FSP_BUILD) == TRUE
+    gEfiCpuTokenSpaceGuid.PcdTemporaryRamBase|0x00080000
+  !else
+    gEfiCpuTokenSpaceGuid.PcdTemporaryRamBase|0xFEF80000
+  !endif
+  gEfiCpuTokenSpaceGuid.PcdTemporaryRamSize|0x00010000
+  gEfiCpuTokenSpaceGuid.PcdPeiTemporaryRamStackSize|0x3C00
+!endif
+
+
+!if $(SECURE_BOOT_ENABLE) == TRUE
+  gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x22000
+!else
+  gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x4000
+!endif
+  gEfiMdeModulePkgTokenSpaceGuid.PcdHwErrStorageSize|0x00000800
+  gEfiMdeModulePkgTokenSpaceGuid.PcdMaxHardwareErrorVariableSize|0x400
+  gEfiCpuTokenSpaceGuid.PcdCpuIEDRamSize|0x400000
+  gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdS3AcpiReservedMemorySize|0x10000
+  gEfiMdeModulePkgTokenSpaceGuid.PcdPeiCoreMaxPeimPerFv|50
+  gEfiMdeModulePkgTokenSpaceGuid.PcdSrIovSupport|FALSE
+  gEfiMdeModulePkgTokenSpaceGuid.PcdAriSupport|FALSE
+  gEfiMdeModulePkgTokenSpaceGuid.PcdPeiCoreMaxPpiSupported|128
+  gEfiCpuTokenSpaceGuid.PcdCpuSmmApSyncTimeout|1000
+!if $(S4_ENABLE) == TRUE
+  gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|TRUE
+!else
+  gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|FALSE
+!endif
+!if $(TARGET) == RELEASE
+  gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x0
+  gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x3
+!else
+  gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2F
+  gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07
+!endif
+!if $(PERFORMANCE_ENABLE) == TRUE
+  gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|0x1
+  gEfiMdeModulePkgTokenSpaceGuid.PcdMaxPeiPerformanceLogEntries|60
+!endif
+
+  gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdEbdaReservedMemorySize|0x10000
+  gEfiMdeModulePkgTokenSpaceGuid.PcdLoadModuleAtFixAddressEnable|$(TOP_MEMORY_ADDRESS)
+  gEfiMdeModulePkgTokenSpaceGuid.PcdBrowserSubtitleTextColor|0x0
+  gEfiMdeModulePkgTokenSpaceGuid.PcdBrowserFieldTextColor|0x01
+  gEfiCpuTokenSpaceGuid.PcdCpuIEDEnabled|TRUE
+  gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdBiosVideoCheckVbeEnable|TRUE
+  gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdBiosVideoCheckVgaEnable|TRUE
+
+!if $(SOURCE_DEBUG_ENABLE) == TRUE
+  gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x17
+  gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07
+  gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseHardwareFlowControl|FALSE
+!endif
+
+[PcdsFixedAtBuild.IA32.PEIM, PcdsFixedAtBuild.IA32.PEI_CORE, PcdsFixedAtBuild.IA32.SEC]
+!if $(TARGET) == RELEASE
+  gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x0
+  gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x3
+!else
+  gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2E
+  gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07
+!endif
+
+[PcdsPatchableInModule.common]
+  gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x803805c6
+  gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x$(PLATFORM_PCIEXPRESS_BASE)
+  gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdLegacyBiosCacheLegacyRegion|FALSE
+
+  ## This PCD specifies whether to use the optimized timing for best PS2 detection performance.
+  #  Note this PCD could be set to TRUE for best boot performance and set to FALSE for best device compatibility.
+  gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdFastPS2Detection|TRUE
+
+[PcdsDynamicHii.common.DEFAULT]
+  gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVariableGuid|0x0|5 # Variable: L"Timeout"
+  gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdHardwareErrorRecordLevel|L"HwErrRecSupport"|gEfiGlobalVariableGuid|0x0|1 # Variable: L"HwErrRecSupport"
+  gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdBootState|L"BootState"|gEfiBootStateGuid|0x0|TRUE
+
+[PcdsDynamicDefault.common.DEFAULT]
+  gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateDataPtr|0x0
+  !if $(TPM_ENABLED) == TRUE
+    gEfiSecurityPkgTokenSpaceGuid.PcdTpmInstanceGuid|{0x7b, 0x3a, 0xcd, 0x72, 0xA5, 0xFE, 0x5e, 0x4f, 0x91, 0x65, 0x4d, 0xd1, 0x21, 0x87, 0xbb, 0x13}
+  !endif
+
+  ## This PCD defines the video horizontal resolution.
+  #  This PCD could be set to 0 then video resolution could be at highest resolution.
+  gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution|0
+  ## This PCD defines the video vertical resolution.
+  #  This PCD could be set to 0 then video resolution could be at highest resolution.
+  gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution|0
+
+  ## This PCD defines the Console output column and the default value is 25 according to UEFI spec.
+  #  This PCD could be set to 0 then console output could be at max column and max row.
+  gEfiMdeModulePkgTokenSpaceGuid.PcdConOutRow|31
+  ## This PCD defines the Console output row and the default value is 80 according to UEFI spec.
+  #  This PCD could be set to 0 then console output could be at max column and max row.
+  gEfiMdeModulePkgTokenSpaceGuid.PcdConOutColumn|100
+
+  ## The PCD is used to specify the video horizontal resolution of text setup.
+  gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdSetupVideoHorizontalResolution|800
+  ## The PCD is used to specify the video vertical resolution of text setup.
+  gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdSetupVideoVerticalResolution|600
+  ## The PCD is used to specify the console output column of text setup.
+  gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdSetupConOutColumn|100
+  ## The PCD is used to specify the console output column of text setup.
+  gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdSetupConOutRow|31
+
+!if $(TPM_ENABLED) == TRUE
+  gEfiSecurityPkgTokenSpaceGuid.PcdTpmInitializationPolicy|1
+  gEfiSecurityPkgTokenSpaceGuid.PcdTpmScrtmPolicy|1
+!endif
+
+[PcdsDynamicExDefault.common.DEFAULT]
+  gEfiVLVTokenSpaceGuid.PcdTCSmbaIoBaseAddress|0x1040
+  gEfiVLVTokenSpaceGuid.PcdEmmcManufacturerId|0
+  gEfiVLVTokenSpaceGuid.PcdProductSerialNumber|0
+  gEfiVLVTokenSpaceGuid.PcdMeasuredBootEnable|TRUE
+  gEfiVLVTokenSpaceGuid.PcdFTPMErrorOccur|FALSE
+  gEfiVLVTokenSpaceGuid.PcdFTPMErrorSkip|FALSE
+  gEfiVLVTokenSpaceGuid.PcdFTPMCommand|0
+  gEfiVLVTokenSpaceGuid.PcdFTPMResponse|0
+  gEfiVLVTokenSpaceGuid.PcdFTPMNotRespond|FALSE
+  gEfiVLVTokenSpaceGuid.PcdFTPMStatus|0
+
+[Components.IA32]
+
+  $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/SecCore.inf
+
+  !if $(MINNOW2_FSP_BUILD) == TRUE
+  IntelFspWrapperPkg/FspWrapperSecCore/FspWrapperSecCore.inf {
+    !if $(TARGET) == DEBUG
+
+    <LibraryClasses>
+      DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
+    !endif
+  }
+  Vlv2TbltDevicePkg/FspSupport/BootModePei/BootModePei.inf
+  IntelFspWrapperPkg/FspInitPei/FspInitPei.inf {
+    !if $(TARGET) == DEBUG
+    <LibraryClasses>
+      DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
+    !endif
+  }
+  !endif
+
+  MdeModulePkg/Core/Pei/PeiMain.inf {
+!if $(TARGET) == DEBUG
+    <PcdsFixedAtBuild>
+      gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2E
+!endif
+    <PcdsPatchableInModule>
+      gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80000046
+  }
+
+  $(PLATFORM_PACKAGE)/MonoStatusCode/MonoStatusCode.inf {
+!if $(TARGET) == DEBUG
+    <PcdsFixedAtBuild>
+      gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2E
+!endif
+  }
+  $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/MemoryInit.inf {
+    <PcdsPatchableInModule>
+      gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80000046
+  }
+
+!if $(RC_BINARY_RELEASE) == TRUE
+  $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/SeCUma.inf
+!endif
+
+!if $(RC_BINARY_RELEASE) == TRUE
+  $(PLATFORM_PACKAGE)/PlatformPei/PlatformPei.inf {
+    <BuildOptions>
+      *_*_IA32_CC_FLAGS      = /DRC_BINARY_RELEASE
+  !if $(TARGET) == DEBUG
+      <PcdsFixedAtBuild>
+        gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2E
+  !endif
+  }
+!endif
+
+!if $(SOURCE_DEBUG_ENABLE) == TRUE
+  SourceLevelDebugPkg/DebugAgentPei/DebugAgentPei.inf{
+    <LibraryClasses>
+      PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
+      DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/SecPeiDebugAgentLib.inf
+      PlatformHookLib|MdeModulePkg/Library/BasePlatformHookLibNull/BasePlatformHookLibNull.inf
+      SerialPortLib|MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.inf
+    }
+!endif
+
+
+!if $(TPM_ENABLED) == TRUE
+  SecurityPkg/Tcg/PhysicalPresencePei/PhysicalPresencePei.inf
+  SecurityPkg/Tcg/TcgPei/TcgPei.inf {
+    <LibraryClasses>
+      NULL|SecurityPkg/Library/HashInstanceLibSha1/HashInstanceLibSha1.inf
+      NULL|SecurityPkg/Library/HashInstanceLibSha256/HashInstanceLibSha256.inf
+      PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf
+}
+!endif
+
+ $(PLATFORM_PACKAGE)/PlatformInitPei/PlatformInitPei.inf {
+    <PcdsPatchableInModule>
+      gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x803805c6
+    <LibraryClasses>
+!if $(TARGET) != RELEASE
+      DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
+!endif
+      PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf
+  }
+  $(PLATFORM_PACKAGE)/FvInfoPei/FvInfoPei.inf
+
+  $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/VlvInitPeim.inf
+!if $(PCIESC_ENABLE) == TRUE
+  $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/PchEarlyInitPeim.inf {
+    <PcdsPatchableInModule>
+      gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80000046
+  }
+!endif
+  $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/PchInitPeim.inf
+
+
+  $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/PchSmbusArpDisabled.inf
+  $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/PchSpiPeim.inf
+  $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/PeiSmmAccess.inf
+  $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/PeiSmmControl.inf
+  MdeModulePkg/Universal/PCD/Pei/Pcd.inf
+  $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/CpuPeim.inf
+  UefiCpuPkg/CpuIoPei/CpuIoPei.inf
+  UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume2Pei.inf
+  $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/MpS3.inf
+  EdkCompatibilityPkg/Compatibility/AcpiVariableHobOnSmramReserveHobThunk/AcpiVariableHobOnSmramReserveHobThunk.inf
+  $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/IA32/PiSmmCommunicationPei.inf
+!if $(CAPSULE_ENABLE) == TRUE
+  MdeModulePkg/Universal/CapsulePei/CapsulePei.inf
+!endif
+  MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf {
+    <LibraryClasses>
+!if $(LZMA_ENABLE) == TRUE
+    NULL|IntelFrameworkModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf
+!endif
+  }
+
+!if $(SECURE_BOOT_ENABLE) == TRUE
+ SecurityPkg/VariableAuthenticated/Pei/VariablePei.inf
+!else
+ MdeModulePkg/Universal/Variable/Pei/VariablePei.inf
+!endif
+ MdeModulePkg/Universal/FaultTolerantWritePei/FaultTolerantWritePei.inf
+
+!if $(TPM_ENABLED) == TRUE
+  SecurityPkg/Tcg/TrEEConfig/TrEEConfigPei.inf {
+    <LibraryClasses>
+      PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf
+  }
+!endif
+!if $(ACPI50_ENABLE) == TRUE
+  MdeModulePkg/Universal/Acpi/FirmwarePerformanceDataTablePei/FirmwarePerformancePei.inf{
+    <LibraryClasses>
+      TimerLib|$(PLATFORM_PACKAGE)/Library/IntelPchAcpiTimerLib/IntelPchAcpiTimerLib.inf
+  }
+
+!endif
+!if $(PERFORMANCE_ENABLE) == TRUE
+  MdeModulePkg/Universal/ReportStatusCodeRouter/Pei/ReportStatusCodeRouterPei.inf
+!endif
+[Components.X64]
+  !if $(MINNOW2_FSP_BUILD) == TRUE
+  IntelFspWrapperPkg/FspNotifyDxe/FspNotifyDxe.inf {
+    !if $(TARGET) == DEBUG
+    <PcdsPatchableInModule>
+      gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80000046
+    <LibraryClasses>
+      DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
+    !endif
+  }
+
+  !endif
+  #
+  # EDK II Related Platform codes
+  #
+  MdeModulePkg/Core/Dxe/DxeMain.inf {
+    <PcdsPatchableInModule>
+      gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80000046
+    <LibraryClasses>
+!if $(DXE_CRC32_SECTION_ENABLE) == TRUE
+      NULL|MdeModulePkg/Library/DxeCrc32GuidedSectionExtractLib/DxeCrc32GuidedSectionExtractLib.inf
+!endif
+!if $(LZMA_ENABLE) == TRUE
+      NULL|IntelFrameworkModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf
+!endif
+!if $(TARGET) != RELEASE
+      DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
+!endif
+  }
+  IntelFrameworkModulePkg/Universal/Acpi/AcpiS3SaveDxe/AcpiS3SaveDxe.inf {
+    <PcdsPatchableInModule>
+        gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0xF0000043
+    <PcdsFixedAtBuild>
+        gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x27
+    <LibraryClasses>
+    !if $(TARGET) != RELEASE
+          DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
+    !endif
+       <BuildOptions>
+        ICC:*_*_*_CC_FLAGS = /D MDEPKG_NDEBUG
+        GCC:*_*_*_CC_FLAGS = -D MDEPKG_NDEBUG
+  }
+  MdeModulePkg/Universal/PCD/Dxe/Pcd.inf {
+    <LibraryClasses>
+      PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
+  }
+  IntelFrameworkModulePkg/Universal/CpuIoDxe/CpuIoDxe.inf
+  UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.inf
+!if $(PERFORMANCE_ENABLE) == TRUE
+  MdeModulePkg/Universal/ReportStatusCodeRouter/Pei/ReportStatusCodeRouterPei.inf
+!endif
+  MdeModulePkg/Universal/ReportStatusCodeRouter/RuntimeDxe/ReportStatusCodeRouterRuntimeDxe.inf
+  MdeModulePkg/Universal/StatusCodeHandler/RuntimeDxe/StatusCodeHandlerRuntimeDxe.inf  {
+    <LibraryClasses>
+!if $(TARGET) != RELEASE
+      DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
+!endif
+  }
+
+!if $(CAPSULE_ENABLE) == TRUE
+  MdeModulePkg/Universal/CapsulePei/CapsuleX64.inf {
+    <LibraryClasses>
+    PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf
+    MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf
+    HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf
+  }
+!endif
+
+  MdeModulePkg/Universal/ReportStatusCodeRouter/Smm/ReportStatusCodeRouterSmm.inf
+  MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf{
+    <LibraryClasses>
+!if $(SECURE_BOOT_ENABLE) == TRUE
+      NULL|SecurityPkg/Library/DxeImageVerificationLib/DxeImageVerificationLib.inf
+!endif
+!if $(USER_IDENTIFICATION_ENABLE)
+      NULL|SecurityPkg/Library/DxeDeferImageLoadLib/DxeDeferImageLoadLib.inf
+!endif
+!if $(TPM_ENABLED) == TRUE
+      NULL|SecurityPkg/Library/DxeTpmMeasureBootLib/DxeTpmMeasureBootLib.inf
+!endif
+  }
+  $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/MpCpu.inf
+  $(PLATFORM_PACKAGE)/Metronome/Metronome.inf
+
+  IntelFrameworkModulePkg/Universal/BdsDxe/BdsDxe.inf{
+    <LibraryClasses>
+      OpensslLib|CryptoPkg/Library/OpensslLib/OpensslLib.inf
+      IntrinsicLib|CryptoPkg/Library/IntrinsicLib/IntrinsicLib.inf
+      BaseCryptLib|CryptoPkg/Library/BaseCryptLib/BaseCryptLib.inf
+      PlatformBdsLib|$(PLATFORM_PACKAGE)/Library/PlatformBdsLib/PlatformBdsLib.inf
+      DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
+      PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
+      SerialPortLib|$(PLATFORM_PACKAGE)/Library/SerialPortLib/SerialPortLib.inf
+  }
+
+  $(PLATFORM_PACKAGE)/UiApp/UiApp.inf
+
+  MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
+  MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
+  MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
+!if $(SECURE_BOOT_ENABLE) == TRUE
+  SecurityPkg/VariableAuthenticated/RuntimeDxe/VariableSmmRuntimeDxe.inf
+  SecurityPkg/VariableAuthenticated/RuntimeDxe/VariableSmm.inf{
+    <LibraryClasses>
+      PlatformSecureLib|SecurityPkg/Library/PlatformSecureLibNull/PlatformSecureLibNull.inf
+      SerialPortLib|$(PLATFORM_PACKAGE)/Library/SerialPortLib/SerialPortLib.inf
+  }
+  $(PLATFORM_PACKAGE)/FvbRuntimeDxe/FvbSmm.inf
+  MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteSmm.inf
+  $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/PchSpiSmm.inf
+  SecurityPkg/VariableAuthenticated/SecureBootConfigDxe/SecureBootConfigDxe.inf {
+    <LibraryClasses>
+      PlatformSecureLib|SecurityPkg/Library/PlatformSecureLibNull/PlatformSecureLibNull.inf
+    <BuildOptions>
+      #
+      # Specify GUID gEfiIfrBootMaintenanceGuid, to install Secure Boot Configuration menu
+      # into Boot Maintenance Manager menu
+      #
+      *_*_*_VFR_FLAGS   = -g b2dedc91-d59f-48d2-898a-12490c74a4e0
+  }
+ !else
+  MdeModulePkg/Universal/Variable/RuntimeDxe/VariableSmmRuntimeDxe.inf
+  MdeModulePkg/Universal/Variable/RuntimeDxe/VariableSmm.inf
+  $(PLATFORM_PACKAGE)/FvbRuntimeDxe/FvbSmm.inf
+  MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteSmm.inf
+  $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/PchSpiSmm.inf
+!endif
+   MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf {
+    <LibraryClasses>
+      FileHandleLib|ShellPkg/Library/UefiFileHandleLib/UefiFileHandleLib.inf
+  }
+
+  MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf
+  PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcatRealTimeClockRuntimeDxe.inf
+  MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
+
+  $(PLATFORM_PACKAGE)/FvbRuntimeDxe/FvbRuntimeDxe.inf
+
+  $(PLATFORM_PACKAGE)/PlatformSetupDxe/PlatformSetupDxe.inf
+
+!if $(DATAHUB_ENABLE) == TRUE
+  IntelFrameworkModulePkg/Universal/DataHubDxe/DataHubDxe.inf {
+    <PcdsFixedAtBuild>
+      gEfiMdePkgTokenSpaceGuid.PcdMaximumLinkedListLength|0
+  }
+!endif
+  IntelFrameworkModulePkg/Universal/StatusCode/DatahubStatusCodeHandlerDxe/DatahubStatusCodeHandlerDxe.inf
+  MdeModulePkg/Universal/MemoryTest/NullMemoryTestDxe/NullMemoryTestDxe.inf
+  $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/PchS3SupportDxe.inf
+  !if $(USE_HPET_TIMER) == TRUE
+    PcAtChipsetPkg/HpetTimerDxe/HpetTimerDxe.inf
+  !else
+  $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/SmartTimer.inf
+  !endif
+  $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/SmmControl.inf
+
+  $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/PchSmbusDxe.inf
+  $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/IntelPchLegacyInterrupt.inf
+  $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/PchReset.inf
+  $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/PchInitDxe.inf{
+    <PcdsPatchableInModule>
+        gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0xF0000043
+  }
+  $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/PchSmiDispatcher.inf
+
+!if $(PCIESC_ENABLE) == TRUE
+  $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/PchPcieSmm.inf
+!endif
+  $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/PchSpiRuntime.inf
+  $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/PchPolicyInitDxe.inf
+  $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/PchBiosWriteProtect.inf
+  $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/SmmAccess.inf
+  $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/PciHostBridge.inf
+  $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/VlvInitDxe.inf
+
+  IntelFrameworkModulePkg/Universal/LegacyRegionDxe/LegacyRegionDxe.inf
+
+  Vlv2TbltDevicePkg/VlvPlatformInitDxe/VlvPlatformInitDxe.inf{
+    <LibraryClasses>
+!if $(TARGET) != RELEASE
+      DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
+!endif
+      PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
+  }
+
+  $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/Dptf.inf
+  $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/PnpDxe.inf
+
+!if $(TPM_ENABLED) == TRUE
+  SecurityPkg/Tcg/TrEEConfig/TrEEConfigPei.inf {
+    <LibraryClasses>
+      PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf
+  }
+
+  SecurityPkg/Tcg/TcgConfigDxe/TcgConfigDxe.inf {
+    <LibraryClasses>
+      PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
+    <BuildOptions>
+      #
+      # specify GUID gEfiIfrNotInTPVPageGuid, this page will not
+      # be showed in TPV page.
+      #
+      *_*_*_VFR_FLAGS   = -g e58809f8-fbc1-48e2-883a-a30fdc4b441e
+  }
+
+  SecurityPkg/Tcg/TcgDxe/TcgDxe.inf {
+    <LibraryClasses>
+      PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
+  }
+  SecurityPkg/Tcg/TcgSmm/TcgSmm.inf
+!endif
+  #
+  # EDK II Related Platform codes
+  #
+  $(PLATFORM_PACKAGE)/PlatformSmm/PlatformSmm.inf{
+    <LibraryClasses>
+    !if $(TARGET) != RELEASE
+          DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
+    !endif
+          PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
+  }
+  $(PLATFORM_PACKAGE)/PlatformInfoDxe/PlatformInfoDxe.inf
+  $(PLATFORM_PACKAGE)/PlatformCpuInfoDxe/PlatformCpuInfoDxe.inf
+  $(PLATFORM_PACKAGE)/PlatformDxe/PlatformDxe.inf
+
+  $(PLATFORM_PACKAGE)/PciPlatform/PciPlatform.inf
+  $(PLATFORM_PACKAGE)/SaveMemoryConfig/SaveMemoryConfig.inf
+  $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/PlatformCpuPolicy.inf
+  $(PLATFORM_PACKAGE)/PpmPolicy/PpmPolicy.inf
+  $(PLATFORM_PACKAGE)/SmramSaveInfoHandlerSmm/SmramSaveInfoHandlerSmm.inf
+!if $(GOP_DRIVER_ENABLE) == TRUE
+  $(PLATFORM_PACKAGE)/PlatformGopPolicy/PlatformGopPolicy.inf
+
+!endif
+
+
+  #
+  # SMM
+  #
+  MdeModulePkg/Core/PiSmmCore/PiSmmIpl.inf
+  MdeModulePkg/Core/PiSmmCore/PiSmmCore.inf
+  $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/PiSmmCpuDxeSmm.inf
+  UefiCpuPkg/CpuIo2Smm/CpuIo2Smm.inf
+  MdeModulePkg/Universal/LockBox/SmmLockBox/SmmLockBox.inf
+  $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/PiSmmCommunicationSmm.inf
+  $(PLATFORM_PACKAGE)/SmmSwDispatch2OnSmmSwDispatchThunk/SmmSwDispatch2OnSmmSwDispatchThunk.inf
+  $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/PowerManagement2.inf
+
+  #
+  # ACPI
+  #
+   MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/BootScriptExecutorDxe.inf {
+    <PcdsPatchableInModule>
+      gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0xF0000043
+    <PcdsFixedAtBuild>
+      gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x27
+    <LibraryClasses>
+      PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
+  }
+
+  $(PLATFORM_PACKAGE)/BootScriptSaveDxe/BootScriptSaveDxe.inf
+  IntelFrameworkModulePkg/Universal/Acpi/AcpiSupportDxe/AcpiSupportDxe.inf
+  Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/PowerManagement/AcpiTables/PowerManagementAcpiTables.inf
+
+  $(PLATFORM_RC_PACKAGE)/AcpiTablesPCAT/AcpiTables.inf
+
+  $(PLATFORM_PACKAGE)/AcpiPlatform/AcpiPlatform.inf
+
+  #
+  # PCI
+  #
+  MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
+
+
+  $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/ISPDxe.inf
+
+
+#
+# ISA
+#
+  $(PLATFORM_PACKAGE)/Wpce791/Wpce791.inf
+  IntelFrameworkModulePkg/Bus/Isa/IsaBusDxe/IsaBusDxe.inf
+  IntelFrameworkModulePkg/Bus/Isa/IsaIoDxe/IsaIoDxe.inf
+  IntelFrameworkModulePkg/Bus/Isa/IsaSerialDxe/IsaSerialDxe.inf
+  IntelFrameworkModulePkg/Bus/Isa/Ps2MouseDxe/Ps2MouseDxe.inf
+  IntelFrameworkModulePkg/Bus/Isa/Ps2KeyboardDxe/Ps2keyboardDxe.inf
+#
+# SDIO
+#
+  $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/MmcHost.inf
+  $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/MmcMediaDevice.inf
+!if $(ACPI50_ENABLE) == TRUE
+  MdeModulePkg/Universal/Acpi/FirmwarePerformanceDataTableDxe/FirmwarePerformanceDxe.inf {
+    <LibraryClasses>
+      TimerLib|$(PLATFORM_PACKAGE)/Library/IntelPchAcpiTimerLib/IntelPchAcpiTimerLib.inf
+  }
+  MdeModulePkg/Universal/Acpi/FirmwarePerformanceDataTableSmm/FirmwarePerformanceSmm.inf {
+    <LibraryClasses>
+      TimerLib|$(PLATFORM_PACKAGE)/Library/IntelPchAcpiTimerLib/IntelPchAcpiTimerLib.inf
+  }
+!endif
+
+#
+# IDE/SCSI/AHCI
+#
+  MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf
+  IntelFrameworkModulePkg/Bus/Pci/IdeBusDxe/IdeBusDxe.inf
+  MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
+  MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
+  MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
+!if $(SATA_ENABLE) == TRUE
+  $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/SataController.inf
+!endif
+  MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf
+!if $(SCSI_ENABLE) == TRUE
+  MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf
+  MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf
+!endif
+#
+# Console
+#
+  MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
+  Vlv2TbltDevicePkg/Override/MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
+  MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf
+  IntelFrameworkModulePkg/Universal/Console/VgaClassDxe/VgaClassDxe.inf
+  MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
+  MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
+  MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
+  MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
+
+  #
+  # USB
+  #
+!if $(USB_ENABLE) == TRUE
+  MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf
+  MdeModulePkg/Bus/Pci/UhciDxe/UhciDxe.inf
+  MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf
+  MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
+  MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf
+  MdeModulePkg/Bus/Usb/UsbMouseDxe/UsbMouseDxe.inf
+  MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
+
+!endif
+
+  #
+  #  ECP
+  #
+  EdkCompatibilityPkg/Compatibility/FrameworkHiiOnUefiHiiThunk/FrameworkHiiOnUefiHiiThunk.inf
+  EdkCompatibilityPkg/Compatibility/LegacyRegion2OnLegacyRegionThunk/LegacyRegion2OnLegacyRegionThunk.inf
+  EdkCompatibilityPkg/Compatibility/SmmBaseOnSmmBase2Thunk/SmmBaseOnSmmBase2Thunk.inf
+  EdkCompatibilityPkg/Compatibility/SmmBaseHelper/SmmBaseHelper.inf
+  EdkCompatibilityPkg/Compatibility/SmmAccess2OnSmmAccessThunk/SmmAccess2OnSmmAccessThunk.inf
+  EdkCompatibilityPkg/Compatibility/SmmControl2OnSmmControlThunk/SmmControl2OnSmmControlThunk.inf
+  EdkCompatibilityPkg/Compatibility/FrameworkSmmStatusCodeOnPiSmmStatusCodeThunk/FrameworkSmmStatusCodeOnPiSmmStatusCodeThunk.inf
+  EdkCompatibilityPkg/Compatibility/FvOnFv2Thunk/FvOnFv2Thunk.inf
+  #
+  # SMBIOS
+  #
+  MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf
+  $(PLATFORM_PACKAGE)/SmBiosMiscDxe/SmBiosMiscDxe.inf
+
+  $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/SmbiosMemory.inf
+  #
+  # CPU/FW Microde
+  #
+  Vlv2MiscBinariesPkg/Microcode/MicrocodeUpdates.inf {
+    <BuildOptions>
+      *_*_*_GENFW_FLAGS = -a 0x800 -p 0xFF
+  }
+
+
+  PcAtChipsetPkg/8259InterruptControllerDxe/8259.inf
+
+
+!if $(NETWORK_ENABLE) == TRUE
+  !if $(NETWORK_ISCSI_ENABLE) == TRUE
+    !if $(NETWORK_IP6_ENABLE) == TRUE
+      NetworkPkg/IScsiDxe/IScsiDxe.inf
+    !else
+      MdeModulePkg/Universal/Network/IScsiDxe/IScsiDxe.inf
+    !endif
+  !endif
+  !if $(NETWORK_VLAN_ENABLE) == TRUE
+    MdeModulePkg/Universal/Network/VlanConfigDxe/VlanConfigDxe.inf
+  !endif
+  !if $(CSM_ENABLE) == TRUE
+    IntelFrameworkModulePkg/Csm/BiosThunk/Snp16Dxe/Snp16Dxe.inf
+  !endif
+!endif
+
+!if $(NETWORK_ENABLE) == TRUE
+  #
+  # UEFI network modules
+  #
+    MdeModulePkg/Universal/Network/DpcDxe/DpcDxe.inf
+    MdeModulePkg/Universal/Network/SnpDxe/SnpDxe.inf
+
+    MdeModulePkg/Universal/Network/MnpDxe/MnpDxe.inf
+    MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf
+    MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Dxe.inf
+    MdeModulePkg/Universal/Network/Ip4ConfigDxe/Ip4ConfigDxe.inf
+    MdeModulePkg/Universal/Network/Ip4Dxe/Ip4Dxe.inf
+    MdeModulePkg/Universal/Network/Mtftp4Dxe/Mtftp4Dxe.inf
+    MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf {
+      <PcdsPatchableInModule>
+      gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80000000
+    }
+    MdeModulePkg/Universal/Network/Udp4Dxe/Udp4Dxe.inf
+    !if $(NETWORK_IP6_ENABLE) == TRUE
+      NetworkPkg/Ip6Dxe/Ip6Dxe.inf
+      NetworkPkg/Dhcp6Dxe/Dhcp6Dxe.inf
+      NetworkPkg/IpSecDxe/IpSecDxe.inf
+      NetworkPkg/TcpDxe/TcpDxe.inf
+      NetworkPkg/Udp6Dxe/Udp6Dxe.inf
+      NetworkPkg/Mtftp6Dxe/Mtftp6Dxe.inf
+    !endif
+    !if $(NETWORK_IP6_ENABLE) == TRUE
+      NetworkPkg/UefiPxeBcDxe/UefiPxeBcDxe.inf
+    !else
+      MdeModulePkg/Universal/Network/UefiPxeBcDxe/UefiPxeBcDxe.inf
+    !endif
+!endif
+
+  Vlv2TbltDevicePkg/Application/FirmwareUpdate/FirmwareUpdate.inf
+
+[BuildOptions]
+#
+# Define Build Options both for EDK and EDKII drivers.
+#
+
+#
+# Define token for different Platform
+#
+!if $(MINNOW2_FSP_BUILD) == TRUE
+  DEFINE MINNOW2_FSP_OPTION = /DMINNOW2_FSP_BUILD
+!else
+  DEFINE MINNOW2_FSP_OPTION =
+!endif
+
+!if $(ENBDT_PF_BUILD) == TRUE
+  DEFINE ENBDT_PF_ENABLE = /DENBDT_PF_ENABLE=1
+!else
+  DEFINE ENBDT_PF_ENABLE = /DENBDT_PF_ENABLE=0
+!endif
+
+
+!if $(CLKGEN_CONFIG_EXTRA_ENABLE) == TRUE
+  DEFINE CLKGEN_CONFIG_EXTRA_BUILD_OPTION = /DCLKGEN_CONFIG_EXTRA=1
+!else
+  DEFINE CLKGEN_CONFIG_EXTRA_BUILD_OPTION =
+!endif
+
+
+
+!if $(PCIESC_ENABLE) == TRUE
+  DEFINE PCIESC_SUPPORT_BUILD_OPTION = /DPCIESC_SUPPORT=1
+!else
+  DEFINE PCIESC_SUPPORT_BUILD_OPTION =
+!endif
+!if $(SATA_ENABLE) == TRUE
+  DEFINE SATA_SUPPORT_BUILD_OPTION = /DSATA_SUPPORT=1
+!else
+  DEFINE SATA_SUPPORT_BUILD_OPTION =
+!endif
+!if $(ENBDT_S3_SUPPORT) == TRUE
+  DEFINE ENBDT_S3_SUPPORT_OPTIONS = /DNOCS_S3_SUPPORT
+!else
+  DEFINE ENBDT_S3_SUPPORT_OPTIONS =
+!endif
+
+!if $(X64_CONFIG) == TRUE
+  DEFINE X64_BUILD_ENABLE = /DX64_BUILD_ENABLE=1
+!else
+  DEFINE X64_BUILD_ENABLE =
+!endif
+
+!if $(TPM_ENABLED) == TRUE
+  DEFINE DSC_TPM_BUILD_OPTIONS = /DTPM_ENABLED
+!else
+  DEFINE DSC_TPM_BUILD_OPTIONS =
+!endif
+
+
+  DEFINE EDK_EDKII_DSC_FEATURE_BUILD_OPTIONS = $(MINNOW2_FSP_OPTION) $(MINNOW2_BUILD_OPTION) $(ENBDT_PF_ENABLE) $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) $(CLKGEN_CONFIG_EXTRA_BUILD_OPTION) $(SYSCTL_X0_CONVERT_BOARD_OPTION) $(ENBDT_S3_SUPPORT_OPTIONS) $(SATA_SUPPORT_BUILD_OPTION) $(PCIESC_SUPPORT_BUILD_OPTION) $(DSC_FTPM_ERROR_WR_BUILD_OPTIONS) $(DSC_TPM_BUILD_OPTIONS) $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS)
+!if $(PERFORMANCE_ENABLE) == TRUE
+  DEFINE PDB_BUILD_OPTION = /Zi
+!endif
+
+!if $(SOURCE_DEBUG_ENABLE) == TRUE
+  MSFT:*_*_X64_GENFW_FLAGS  = --keepexceptiontable
+  GCC:*_*_X64_GENFW_FLAGS   = --keepexceptiontable
+  INTEL:*_*_X64_GENFW_FLAGS = --keepexceptiontable
+!if $(TARGET) == DEBUG
+  DEFINE SOURCE_LEVEL_DEBUG_BUILD_OPTIONS = /Od /Oy-
+!endif
+!else
+  DEFINE SOURCE_LEVEL_DEBUG_BUILD_OPTIONS =
+
+!endif
+
+[BuildOptions.Common.EDK]
+
+#
+# Define token for different Platform
+#
+!if $(ENBDT_PF_BUILD) == TRUE
+  DEFINE ENBDT_PF_ENABLE = /DENBDT_PF_ENABLE=1
+!else
+  DEFINE ENBDT_PF_ENABLE = /DENBDT_PF_ENABLE=0
+!endif
+
+!if $(PERFORMANCE_ENABLE) == TRUE
+  RELEASE_*_*_DLINK_FLAGS = /DEBUG
+!endif
+
+!if $(S3_ENABLE) == TRUE
+  DEFINE DSC_S3_BUILD_OPTIONS = /DEFI_S3_RESUME
+!else
+  DEFINE DSC_S3_BUILD_OPTIONS =
+!endif
+
+!if $(ENBDT_S3_SUPPORT) == TRUE
+  DEFINE ENBDT_S3_SUPPORT_OPTIONS = /DNOCS_S3_SUPPORT
+!else
+  DEFINE ENBDT_S3_SUPPORT_OPTIONS =
+!endif
+
+!if $(X64_CONFIG) == TRUE
+  DEFINE X64_BUILD_ENABLE = /DX64_BUILD_ENABLE=1
+!else
+  DEFINE X64_BUILD_ENABLE =
+!endif
+
+
+  DEFINE EDK_GLUE_LIB_DEBUG  =
+  DEFINE DEBUG_BUILD_OPTIONS = /D EFI_DEBUG /D DEBUG_MODE=1  /GL- $(EDK_GLUE_LIB_DEBUG) /DEDKII_GLUE_DebugPrintErrorLevel=(EFI_D_ERROR)
+  DEFINE EDK_DSC_FEATURE_BUILD_OPTIONS = $(DSC_S3_BUILD_OPTIONS) $(DSC_ACPI_BUILD_OPTIONS) $(DSC_SEC_BUILD_OPTIONS) $(DSC_FTPM_BUILD_OPTIONS) $(DSC_FTPM_ERROR_WR_BUILD_OPTIONS) $(DSC_TPM_BUILD_OPTIONS) $(SOFTSDV_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(QT_BUILD_OPTIONS) $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) /D$(PROJECT_SC_CHIPSET)
+
+  DEFINE EDK_DSC_OTHER_BUILD_OPTIONS = $(EDK_EDKII_DSC_FEATURE_BUILD_OPTIONS) $(SV_BUILD_OPTIONS) $(INTEL_FASTBOOT_BUILD_OPTION)
+  DEFINE EDK_DSC_GLOBAL_BUILD_OPTIONS = $(ENBDT_PF_ENABLE) $(EDK_DSC_FEATURE_BUILD_OPTIONS) $(EDK_DSC_OTHER_BUILD_OPTIONS) /D EFI_SPECIFICATION_VERSION=0x00020000  /D PI_SPECIFICATION_VERSION=0x00000009  /D TIANO_RELEASE_VERSION=0x00080006 /D SUPPORT_DEPRECATED_PCI_CFG_PPI /D CSM_SMMENTRY_PORT8DATA8 /D EDKII_GLUE_PciExpressBaseAddress=0x$(PLATFORM_PCIEXPRESS_BASE) /D MAX_VARIABLE_SIZE=0x2000 /D EFI_FIRMWARE_VENDOR="L/"INTEL/"" /D EFI_BUILD_VERSION="L/"EDKII/"" /DEFI_PEI_REPORT_STATUS_CODE_ON $(ENBDT_S3_SUPPORT_OPTIONS)
+
+  *_*_IA32_ASM_FLAGS         = /DEFI32 /D EDKII_GLUE_PciExpressBaseAddress=$(PLATFORM_PCIEXPRESS_BASE)h /DNOCS_S3_SUPPORT
+  DEBUG_*_IA32_CC_FLAGS      = /D EFI32 $(EDK_DSC_GLOBAL_BUILD_OPTIONS) $(DEBUG_BUILD_OPTIONS)
+  RELEASE_*_IA32_CC_FLAGS    = /D EFI32 $(EDK_DSC_GLOBAL_BUILD_OPTIONS)
+  DEBUG_*_IA32_VFRPP_FLAGS   = /D EFI32 $(EDK_DSC_GLOBAL_BUILD_OPTIONS) $(DEBUG_BUILD_OPTIONS)
+  RELEASE_*_IA32_VFRPP_FLAGS = /D EFI32 $(EDK_DSC_GLOBAL_BUILD_OPTIONS)
+  DEBUG_*_IA32_APP_FLAGS     = /D EFI32 $(EDK_DSC_GLOBAL_BUILD_OPTIONS) $(DEBUG_BUILD_OPTIONS)
+  RELEASE_*_IA32_APP_FLAGS   = /D EFI32 $(EDK_DSC_GLOBAL_BUILD_OPTIONS)
+  DEBUG_*_IA32_PP_FLAGS      = /D EFI32 $(EDK_DSC_GLOBAL_BUILD_OPTIONS) $(DEBUG_BUILD_OPTIONS)
+  RELEASE_*_IA32_PP_FLAGS    = /D EFI32 $(EDK_DSC_GLOBAL_BUILD_OPTIONS)
+  *_*_IA32_ASLPP_FLAGS       = /D EDKII_GLUE_PciExpressBaseAddress=0x$(PLATFORM_PCIEXPRESS_BASE)
+  *_*_IA32_ASLCC_FLAGS       = /D EDKII_GLUE_PciExpressBaseAddress=0x$(PLATFORM_PCIEXPRESS_BASE)
+  *_*_IA32_ASM16_FLAGS       = /D EDKII_GLUE_PciExpressBaseAddress=$(PLATFORM_PCIEXPRESS_BASE)h
+
+  *_*_X64_ASM_FLAGS          = /DEFIX64 /D EDKII_GLUE_PciExpressBaseAddress=$(PLATFORM_PCIEXPRESS_BASE)h /DNOCS_S3_SUPPORT
+  DEBUG_*_X64_CC_FLAGS       = /D EFIX64 $(EDK_DSC_GLOBAL_BUILD_OPTIONS) $(DEBUG_BUILD_OPTIONS)
+  RELEASE_*_X64_CC_FLAGS     = /D EFIX64 $(EDK_DSC_GLOBAL_BUILD_OPTIONS)
+  DEBUG_*_X64_VFRPP_FLAGS    = /D EFIX64 $(EDK_DSC_GLOBAL_BUILD_OPTIONS) $(DEBUG_BUILD_OPTIONS)
+  RELEASE_*_X64_VFRPP_FLAGS  = /D EFIX64 $(EDK_DSC_GLOBAL_BUILD_OPTIONS)
+  DEBUG_*_X64_APP_FLAGS      = /D EFIX64 $(EDK_DSC_GLOBAL_BUILD_OPTIONS) $(DEBUG_BUILD_OPTIONS)
+  RELEASE_*_X64_APP_FLAGS    = /D EFIX64 $(EDK_DSC_GLOBAL_BUILD_OPTIONS)
+  DEBUG_*_X64_PP_FLAGS       = /D EFIX64 $(EDK_DSC_GLOBAL_BUILD_OPTIONS) $(DEBUG_BUILD_OPTIONS)
+  RELEASE_*_X64_PP_FLAGS     = /D EFIX64 $(EDK_DSC_GLOBAL_BUILD_OPTIONS)
+  *_*_X64_ASLPP_FLAGS        = /D EDKII_GLUE_PciExpressBaseAddress=0x$(PLATFORM_PCIEXPRESS_BASE)
+  *_*_X64_ASLCC_FLAGS        = /D EDKII_GLUE_PciExpressBaseAddress=0x$(PLATFORM_PCIEXPRESS_BASE)
+  *_*_X64_ASM16_FLAGS        = /D EDKII_GLUE_PciExpressBaseAddress=$(PLATFORM_PCIEXPRESS_BASE)h
+ # *_*_*_BUILD_FLAGS = -s
+  *_*_*_VFR_FLAGS   = -c
+  *_*_*_BUILD_FLAGS = -c
+
+[BuildOptions.Common.EDKII]
+  *_*_IA32_ASM_FLAGS     = $(VP_BUILD_OPTIONS) /D EDKII_GLUE_PciExpressBaseAddress=$(PLATFORM_PCIEXPRESS_BASE)h /DNOCS_S3_SUPPORT
+
+  *_*_IA32_CC_FLAGS      = $(EDK_EDKII_DSC_FEATURE_BUILD_OPTIONS)
+  *_*_IA32_VFRPP_FLAGS   = $(EDK_EDKII_DSC_FEATURE_BUILD_OPTIONS)
+  *_*_IA32_APP_FLAGS     = $(EDK_EDKII_DSC_FEATURE_BUILD_OPTIONS)
+  *_*_IA32_PP_FLAGS      = $(EDK_EDKII_DSC_FEATURE_BUILD_OPTIONS)
+  *_*_IA32_ASLPP_FLAGS   = $(EDK_EDKII_DSC_FEATURE_BUILD_OPTIONS)
+
+  *_*_X64_CC_FLAGS       = $(EDK_EDKII_DSC_FEATURE_BUILD_OPTIONS) $(SOURCE_LEVEL_DEBUG_BUILD_OPTIONS)
+  *_*_X64_VFRPP_FLAGS    = $(EDK_EDKII_DSC_FEATURE_BUILD_OPTIONS)
+  *_*_X64_APP_FLAGS      = $(EDK_EDKII_DSC_FEATURE_BUILD_OPTIONS)
+  *_*_X64_PP_FLAGS       = $(EDK_EDKII_DSC_FEATURE_BUILD_OPTIONS)
+  *_*_X64_ASLPP_FLAGS    = $(EDK_EDKII_DSC_FEATURE_BUILD_OPTIONS)
+
+
+[Components.X64]
+ $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/SysFwUpdateCapsuleDxe.inf
+
+  $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/I2cBus.inf {
+    <PcdsPatchableInModule>
+      gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0xF0000043
+  }
+
+  $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/I2cHost.inf {
+    <PcdsPatchableInModule>
+      gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0xF0000043
+  }
+  $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/I2cPortA0Pio.inf {
+    <PcdsPatchableInModule>
+      gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x00000043
+  }
+
+  $(PLATFORM_BINARY_PACKAGE)/$(DXE_ARCHITECTURE)$(TARGET)/$(DXE_ARCHITECTURE)/I2cMmioDeviceDxe.inf {
+    <PcdsPatchableInModule>
+      gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x00000043
+  }

diff --git a/Vlv2TbltDevicePkg/PlatformSetupDxe/Boot.vfi b/Vlv2TbltDevicePkg/PlatformSetupDxe/Boot.vfi
new file mode 100644 (file)
index 0000000..c6c1523
--- /dev/null
+++ b/Vlv2TbltDevicePkg/PlatformSetupDxe/Boot.vfi
@@ -0,0 +1,77 @@
+//\r
+//\r
+// Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+//                                                                                  \r\r
+// This program and the accompanying materials are licensed and made available under\r\r
+// the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+// The full text of the license may be found at                                     \r\r
+// http://opensource.org/licenses/bsd-license.php.                                  \r\r
+//                                                                                  \r\r
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+//                                                                                  \r\r
+//\r
+//\r
+// Module Name:\r
+//\r
+//   Boot.vfi\r
+//\r
+// Abstract:\r
+//\r
+//   Driver Setup formset.\r
+//\r
+// Revision History:\r
+//\r
+// --*/\r
+\r
+\r
+form formid = BOOT_CONFIGURATION_FORM_ID,\r
+\r
+  title  = STRING_TOKEN(STR_BOOT_CONFIGURATION_TITLE);\r
+\r
+\r
+  oneof varid  = Setup.FastBoot,\r
+    prompt   = STRING_TOKEN(STR_FAST_BOOT_PROMPT),\r
+    help     = STRING_TOKEN(STR_FAST_BOOT_HELP),\r
+    option text = STRING_TOKEN(STR_DISABLE), value=0, flags= DEFAULT | RESET_REQUIRED;\r
+    option text = STRING_TOKEN(STR_ENABLE),  value=1, flags= MANUFACTURING | RESET_REQUIRED;\r
+  endoneof;\r
+\r
+  oneof varid  = Setup.SecureBoot,\r
+    prompt   = STRING_TOKEN(STR_SECURITY_BOOT_PROMPT),\r
+    help     = STRING_TOKEN(STR_SECURITY_BOOT_HELP),\r
+        option text = STRING_TOKEN(STR_DISABLE), value=0, flags= DEFAULT | MANUFACTURING | RESET_REQUIRED;\r
+        option text = STRING_TOKEN(STR_ENABLE),  value=1, flags= RESET_REQUIRED;\r
+  endoneof;\r
+\r
+\r
+  oneof varid  = Setup.QuietBoot,\r
+    prompt   = STRING_TOKEN(STR_QUIETBOOT_PROMPT),\r
+    help     = STRING_TOKEN(STR_QUIETBOOT_HELP),\r
+    option text = STRING_TOKEN(STR_DISABLE), value=0, flags=DEFAULT | MANUFACTURING | RESET_REQUIRED;\r
+    option text = STRING_TOKEN(STR_ENABLE),  value=1, flags=0 | RESET_REQUIRED;\r
+  endoneof;\r
+\r
+\r
+\r
+  oneof   varid   = Setup.LogBootTime,\r
+      prompt      = STRING_TOKEN(STR_LOG_BOOT_TIME_PROMPT),\r
+      help        = STRING_TOKEN(STR_LOG_BOOT_TIME_HELP),\r
+      option text = STRING_TOKEN(STR_DISABLE), value = 0, flags = 0 | RESET_REQUIRED;\r
+      option text = STRING_TOKEN(STR_ENABLE),  value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED;\r
+  endoneof;\r
+\r
+  suppressif ideqval Setup.LogBootTime == 0x00;\r
+    text\r
+      help   = STRING_TOKEN(STR_NULL_STRING),\r
+      text   = STRING_TOKEN(STR_LOG_BOOT_TIME_RECORD),\r
+      text   = STRING_TOKEN(STR_LOG_BOOT_TIME_VALUE),\r
+      flags  = 0,\r
+      key    = 0;\r
+  endif;\r
+\r
+endform;\r
+\r
+\r
+\r
+\r

diff --git a/Vlv2TbltDevicePkg/PlatformSetupDxe/Configuration.h b/Vlv2TbltDevicePkg/PlatformSetupDxe/Configuration.h
new file mode 100644 (file)
index 0000000..b4e0e51
--- /dev/null
+++ b/Vlv2TbltDevicePkg/PlatformSetupDxe/Configuration.h
@@ -0,0 +1,61 @@
+/*++\r
+\r
+  Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+\r
+Module Name:\r
+\r
+    Configuration.h\r
+\r
+Abstract:\r
+\r
+    Driver configuration include file\r
+\r
+Revision History:\r
+  ------------------------------------------------------------------------------\r
+  Rev   Date<MM/DD/YYYY>    Name    Description\r
+  ------------------------------------------------------------------------------\r
+\r
+  ------------------------------------------------------------------------------\r
+--*/\r
+\r
+#ifndef _CONFIGURATION_H\r
+#define _CONFIGURATION_H\r
+\r
+//\r
+// System Setup Page. Do not have to be sequential but have to be unique\r
+//\r
+#define ROOT_FORM_ID                        1\r
+#define ROOT_MAIN_FORM_ID                   2\r
+#define CPU_CONFIGURATION_FORM_ID           3\r
+#define CPU_PWR_CONFIGURATION_FORM_ID       4\r
+#define BOOT_CONFIGURATION_FORM_ID          5\r
+#define IGD_FORM_ID                         6\r
+#define SECURITY_CONFIGURATION_FORM_ID      7\r
+#define SOUTH_CLUSTER_FORM_ID               8\r
+#define DPTF_FORM_ID                        9\r
+#define PLATFORM_INFORMATION_FORM_ID        10\r
+#define DRIVE_CONFIGURATION_ID              11\r
+#define SENSOR_CONFIGURATION_ID             12\r
+#define LPSS_CONFIGURATION_ID               13\r
+#define UNCORE_FORM_ID                      14\r
+#define TPM_FORM_ID                         15\r
+#define THERMAL_FORM_ID                     16\r
+#define PASSWORD_SETTING_ID                 17\r
+#define LAN_OPTIONS_FORM_ID                 18\r
+#define AZALIA_OPTIONS_FORM_ID              19\r
+#define MISC_OPTIONS_FORM_ID                20\r
+#define USB_OPTIONS_FORM_ID                 21\r
+#define PCIE_DEVICE_OPTIONS_FORM_ID         22\r
+#define SYSTEM_COMPONENT_FORM_ID            23\r
+#define DEBUG_CONFIGURATION_FORM_ID         24\r
+#endif // #ifndef _CONFIGURATION_H\r

diff --git a/Vlv2TbltDevicePkg/PlatformSetupDxe/DebugConfig.vfi b/Vlv2TbltDevicePkg/PlatformSetupDxe/DebugConfig.vfi
new file mode 100644 (file)
index 0000000..7065ffd
--- /dev/null
+++ b/Vlv2TbltDevicePkg/PlatformSetupDxe/DebugConfig.vfi
@@ -0,0 +1,123 @@
+//\r
+//\r
+// Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+//                                                                                  \r\r
+// This program and the accompanying materials are licensed and made available under\r\r
+// the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+// The full text of the license may be found at                                     \r\r
+// http://opensource.org/licenses/bsd-license.php.                                  \r\r
+//                                                                                  \r\r
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+//                                                                                  \r\r
+//\r
+//\r
+//\r
+// Module Name:\r
+//\r
+//   DebugConfiguration.vfi\r
+//\r
+// Abstract:\r
+//\r
+//   Debug Configuration formset.\r
+//\r
+\r
+\r
+// --*/\r
+\r
+form formid = DEBUG_CONFIGURATION_FORM_ID,\r
+  title    = STRING_TOKEN(STR_DEBUG_CONFIGURATION_TITLE);\r
+\r
+\r
+  subtitle text = STRING_TOKEN(STR_NULL_STRING);\r
+  subtitle text = STRING_TOKEN(STR_ACPIMEMDBG_STRING);\r
+\r
+  //ACPI Memory Debug Switch\r
+    oneof varid   = Setup.ACPIMemDbg,\r
+      prompt      = STRING_TOKEN (STR_ACPIMEMDBG_SWTICH),\r
+      help        = STRING_TOKEN (STR_ACPIMEMDBG_SWTICH_HELP),\r
+      option text = STRING_TOKEN (STR_ENABLE),  value = 1, flags =  DEFAULT | MANUFACTURING | RESET_REQUIRED;\r
+      option text = STRING_TOKEN (STR_DISABLE), value = 0, flags =  RESET_REQUIRED;\r
+    endoneof;\r
+\r
+\r
+  subtitle text = STRING_TOKEN(STR_NULL_STRING);\r
+\r
+    oneof varid   = Setup.ExISupport,\r
+      prompt      = STRING_TOKEN(STR_EXISUPPORT_PROMPT),\r
+      help        = STRING_TOKEN(STR_EXISUPPORT_HELP),\r
+      option text = STRING_TOKEN(STR_ENABLE), value = 1, flags = RESET_REQUIRED;\r
+      option text = STRING_TOKEN(STR_DISABLE), value = 0, flags = DEFAULT | RESET_REQUIRED;\r
+    endoneof;\r
+ subtitle text = STRING_TOKEN(STR_WITT_CONFIGURATION_TITLE);\r
+\r
+  oneof varid   = Setup.WittEnable,\r
+    prompt      = STRING_TOKEN(STR_WITT_PROMPT),\r
+    help        = STRING_TOKEN(STR_WITT_HELP),\r
+    option text = STRING_TOKEN(STR_DISABLE), value = 0, flags = DEFAULT | RESET_REQUIRED;\r
+    option text = STRING_TOKEN(STR_ENABLE),  value = 1, flags = RESET_REQUIRED;\r
+  endoneof;\r
+\r
+  oneof varid   = Setup.UtsEnable,\r
+    prompt      = STRING_TOKEN(STR_UTS_PROMPT),\r
+    help        = STRING_TOKEN(STR_UTS_HELP),\r
+    option text = STRING_TOKEN(STR_DISABLE), value = 0, flags = DEFAULT | RESET_REQUIRED;\r
+    option text = STRING_TOKEN(STR_ENABLE),  value = 1, flags = RESET_REQUIRED;\r
+  endoneof;\r
+\r
+  //\r
+  //Lakemore Settings\r
+  //\r
+  subtitle text = STRING_TOKEN(STR_NULL_STRING);\r
+  subtitle text = STRING_TOKEN(STR_LM_INFORMATION_TITLE);\r
+\r
+    grayoutif ideqval Setup.PunitBIOSConfig == 0x1;\r
+      oneof varid   = Setup.LmMemSize,\r
+        prompt      = STRING_TOKEN (STR_LM_MEMORY_PROMPT),\r
+        help        = STRING_TOKEN (STR_LM_MEMORY_HELP),\r
+        option text = STRING_TOKEN (STR_LM_MEMORY_16MB),  value = 16384, flags = RESET_REQUIRED;\r
+        option text = STRING_TOKEN (STR_LM_MEMORY_8MB),   value = 8192,  flags = RESET_REQUIRED;\r
+        option text = STRING_TOKEN (STR_LM_MEMORY_1MB),   value = 1024,  flags = RESET_REQUIRED;\r
+        option text = STRING_TOKEN (STR_LM_MEMORY_128KB), value = 128,   flags = RESET_REQUIRED;\r
+        option text = STRING_TOKEN (STR_LM_MEMORY_0MB),   value = 0,     flags = DEFAULT | MANUFACTURING | RESET_REQUIRED;\r
+      endoneof;\r
+    endif;\r
+\r
+    oneof varid   = Setup.PunitBIOSConfig,\r
+      prompt      = STRING_TOKEN (STR_PUINT_BIOS_CONFIG_DISPLAY),\r
+      help        = STRING_TOKEN (STR_PUINT_BIOS_CONFIG_DISPLAY_HELP),\r
+      option text = STRING_TOKEN (STR_PUINT_BIOS_PDM),         value = 3,  flags = DEFAULT | MANUFACTURING | RESET_REQUIRED;\r
+      option text = STRING_TOKEN (STR_PUINT_BIOS_PERFORMANCE), value = 2,  flags = RESET_REQUIRED;\r
+      option text = STRING_TOKEN (STR_PUINT_BIOS_POWERSAVE),   value = 1,  flags = RESET_REQUIRED;\r
+         option text = STRING_TOKEN (STR_PUINT_BIOS_RESERVED),    value = 0,  flags = RESET_REQUIRED;\r
+    endoneof;\r
+\r
+    suppressif NOT ideqval Setup.PunitBIOSConfig == 0x3;\r
+      oneof varid   = Setup.PDMConfig,\r
+        prompt      = STRING_TOKEN (STR_PDM_OUTPUT_CONFIG_SWTICH),\r
+        help        = STRING_TOKEN (STR_PDM_OUTPUT_CONFIG_SWTICH_HELP),\r
+        option text = STRING_TOKEN (STR_DISABLE), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED;\r
+        option text = STRING_TOKEN (STR_PDM_OUTPUT_MEM), value = 1, flags = RESET_REQUIRED;\r
+        option text = STRING_TOKEN (STR_PDM_OUTPUT_IO),  value = 2, flags = RESET_REQUIRED;\r
+      endoneof;\r
+    endif;\r
+\r
+  subtitle text = STRING_TOKEN(STR_NULL_STRING);\r
+  oneof varid   = Setup.ENDBG2,\r
+    prompt      = STRING_TOKEN (STR_ENABLE_DBG2),\r
+    help        = STRING_TOKEN (STR_ENABLE_DBG2_HELP),\r
+    option text = STRING_TOKEN(STR_DISABLE), value = 0, flags = RESET_REQUIRED;\r
+    option text = STRING_TOKEN(STR_ENABLE),  value = 1, flags = DEFAULT | RESET_REQUIRED;\r
+  endoneof;\r
+\r
+  subtitle text = STRING_TOKEN(STR_NULL_STRING);\r
+\r
+  subtitle text = STRING_TOKEN(STR_NULL_STRING);\r
+  oneof varid = Setup.DisableCodec262,\r
+  prompt   = STRING_TOKEN(STR_CODEC262_DISABLED_PROMPT),\r
+  help     = STRING_TOKEN(STR_CODEC262_DISABLED_HELP),\r
+  option text = STRING_TOKEN(STR_YES), value = 1, flags = RESET_REQUIRED;\r
+  option text = STRING_TOKEN(STR_NO), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED;\r
+  endoneof;\r
+\r
+endform;\r

diff --git a/Vlv2TbltDevicePkg/PlatformSetupDxe/FwVersionStrings.uni b/Vlv2TbltDevicePkg/PlatformSetupDxe/FwVersionStrings.uni
new file mode 100644 (file)
index 0000000..767388c
Binary files /dev/null and b/Vlv2TbltDevicePkg/PlatformSetupDxe/FwVersionStrings.uni differ

diff --git a/Vlv2TbltDevicePkg/PlatformSetupDxe/Main.vfi b/Vlv2TbltDevicePkg/PlatformSetupDxe/Main.vfi
new file mode 100644 (file)
index 0000000..24bc297
--- /dev/null
+++ b/Vlv2TbltDevicePkg/PlatformSetupDxe/Main.vfi
@@ -0,0 +1,336 @@
+//\r
+//\r
+// Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+//                                                                                  \r\r
+// This program and the accompanying materials are licensed and made available under\r\r
+// the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+// The full text of the license may be found at                                     \r\r
+// http://opensource.org/licenses/bsd-license.php.                                  \r\r
+//                                                                                  \r\r
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+//                                                                                  \r\r
+//\r
+//\r
+//\r
+// Module Name:\r
+//\r
+//   Main.vfi\r
+//\r
+// Abstract:\r
+//\r
+//   Driver Setup formset.\r
+//\r
+// Revision History:\r
+//\r
+// --*/\r
+\r
+form formid = ROOT_MAIN_FORM_ID,\r
+\r
+  title    = STRING_TOKEN(STR_MAIN_TITLE);\r
+\r
+  subtitle text = STRING_TOKEN(STR_BIOS_INFORMATION_TITLE);\r
+\r
+  text\r
+    help   = STRING_TOKEN(STR_NULL_STRING),\r
+    text   = STRING_TOKEN(STR_IFWI_VERSION_STRING),\r
+    text   = STRING_TOKEN(STR_IFWI_VERSION_VALUE),\r
+    flags  = 0,\r
+    key    = 0;\r
+\r
+  text\r
+    help   = STRING_TOKEN(STR_NULL_STRING),\r
+    text   = STRING_TOKEN(STR_BIOS_VERSION_STRING),\r
+    text   = STRING_TOKEN(STR_BIOS_VERSION_VALUE),\r
+    flags  = 0,\r
+    key    = 0;\r
+\r
+  text\r
+    help   = STRING_TOKEN(STR_NULL_STRING),\r
+    text   = STRING_TOKEN(STR_BIOS_VENDOR_STRING),\r
+    text   = STRING_TOKEN(STR_BIOS_VENDOR_VALUE),\r
+    flags  = 0,\r
+    key    = 0;\r
+\r
+  text\r
+    help   = STRING_TOKEN(STR_NULL_STRING),\r
+    text   = STRING_TOKEN(STR_CORE_VERSION_STRING),\r
+    text   = STRING_TOKEN(STR_CORE_VERSION_VALUE),\r
+    flags  = 0,\r
+    key    = 0;\r
+\r
+  text\r
+    help   = STRING_TOKEN(STR_NULL_STRING),\r
+    text   = STRING_TOKEN(STR_BIOS_BUILD_TIME_STRING),\r
+    text   = STRING_TOKEN(STR_BIOS_BUILD_TIME_VALUE),\r
+    flags  = 0,\r
+    key    = 0;\r
+\r
+  subtitle text = STRING_TOKEN(STR_NULL_STRING);\r
+\r
+  subtitle text = STRING_TOKEN(STR_PROCESSOR_INFO_STRING);\r
+  text\r
+    help   = STRING_TOKEN(STR_NULL_STRING),\r
+    text   = STRING_TOKEN(STR_PROCESSOR_VERSION_STRING),\r
+    text   = STRING_TOKEN(STR_PROCESSOR_VERSION_VALUE),\r
+    flags  = 0,\r
+    key    = 0;\r
+\r
+  text\r
+    help   = STRING_TOKEN(STR_NULL_STRING),\r
+    text   = STRING_TOKEN(STR_PROCESSOR_SKU_STRING),\r
+    text   = STRING_TOKEN(STR_PROCESSOR_SKU_VALUE),\r
+    flags  = 0,\r
+    key    = 0;\r
+\r
+  text\r
+    help   = STRING_TOKEN(STR_NULL_STRING),\r
+    text   = STRING_TOKEN(STR_PROCESSOR_SPEED_STRING),\r
+    text   = STRING_TOKEN(STR_PROCESSOR_SPEED_VALUE),\r
+    flags  = 0,\r
+    key    = 0;\r
+\r
+  text\r
+    help   = STRING_TOKEN(STR_NULL_STRING),\r
+    text   = STRING_TOKEN(STR_PROCESSOR_ID_STRING),\r
+    text   = STRING_TOKEN(STR_PROCESSOR_ID_VALUE),\r
+    flags  = 0,\r
+    key    = 0;\r
+\r
+  text\r
+    help   = STRING_TOKEN(STR_NULL_STRING),\r
+    text   = STRING_TOKEN(STR_PROCESSOR_MICROCODE_STRING),\r
+    text   = STRING_TOKEN(STR_PROCESSOR_MICROCODE_VALUE),\r
+    flags  = 0,\r
+    key    = 0;\r
+\r
+  text\r
+    help   = STRING_TOKEN(STR_NULL_STRING),\r
+    text   = STRING_TOKEN(STR_PROCESSOR_CORE_STRING),\r
+    text   = STRING_TOKEN(STR_PROCESSOR_CORE_VALUE),\r
+    flags  = 0,\r
+    key    = 0;\r
+\r
+  text\r
+    help   = STRING_TOKEN(STR_NULL_STRING),\r
+    text   = STRING_TOKEN(STR_EM64T_CAPABILITY_STRING),\r
+    text   = STRING_TOKEN(STR_EM64T_CAPABILITY_VALUE),\r
+    flags  = 0,\r
+    key    = 0;\r
+\r
+  subtitle text = STRING_TOKEN(STR_NULL_STRING);\r
+\r
+  goto PLATFORM_INFORMATION_FORM_ID,\r
+    prompt = STRING_TOKEN(STR_PLATFORM_INFORMATION_TITLE),\r
+    help   = STRING_TOKEN(STR_PLATFORM_INFORMATION_HELP);\r
+\r
+  subtitle text = STRING_TOKEN(STR_NULL_STRING);\r
+  //\r
+  // Date and Time section\r
+  //\r
+  date    year varid  = Date.Year,    // Note that it is a member of NULL, so the RTC will be the system resource to retrieve and save from\r
+    prompt      = STRING_TOKEN(STR_DATE_PROMPT),\r
+    help        = STRING_TOKEN(STR_DATE_YEAR_HELP),\r
+    minimum     = 2003,\r
+    maximum     = 2100,\r
+    step        = 1,\r
+    default     = 2003,\r
+\r
+    month varid = Date.Month,    // Note that it is a member of NULL, so the RTC will be the system resource to retrieve and save from\r
+    prompt      = STRING_TOKEN(STR_DATE_PROMPT),\r
+    help        = STRING_TOKEN(STR_DATE_MONTH_HELP),\r
+    minimum     = 1,\r
+    maximum     = 12,\r
+    step        = 1,\r
+    default     = 1,\r
+\r
+    day varid   = Date.Day,          // Note that it is a member of NULL, so the RTC will be the system resource to retrieve and save from\r
+    prompt      = STRING_TOKEN(STR_DATE_PROMPT),\r
+    help        = STRING_TOKEN(STR_DATE_DAY_HELP),\r
+    minimum     = 1,\r
+    maximum     = 31,\r
+    step        = 0x1,\r
+    default     = 1,\r
+\r
+    // If the day is 31 AND months is any of the following 2, 4, 6, 9, 11\r
+    inconsistentif prompt = STRING_TOKEN(STR_ERROR_POPUP),\r
+      ideqval Date.Day == 31\r
+      AND\r
+      ideqvallist Date.Month == 2 4 6 9 11\r
+    endif\r
+\r
+    // If the day is 30 AND month is 2\r
+    inconsistentif prompt = STRING_TOKEN(STR_ERROR_POPUP),\r
+      ideqval Date.Day == 30\r
+      AND\r
+      ideqval Date.Month == 2\r
+    endif\r
+\r
+    // If the day is 29 AND month is 2 AND it year is NOT a leapyear\r
+    inconsistentif prompt = STRING_TOKEN(STR_ERROR_POPUP),\r
+      ideqval Date.Day == 0x29\r
+      AND\r
+      ideqval Date.Month == 2\r
+      AND\r
+      NOT\r
+      ideqvallist Date.Year == 2004 2008 2012 2016 2020 2024 2028 2032 2036 2040 2044 2048 2052 2056 2060 2064 2068 2072 2076 2080 2084 2088 2092 2096\r
+    endif\r
+\r
+  enddate;\r
+\r
+  time    hour varid  = Time.Hours,         // Note that it is a member of NULL, so the RTC will be the system resource to retrieve and save from\r
+    prompt      = STRING_TOKEN(STR_TIME_PROMPT),\r
+    help        = STRING_TOKEN(STR_TIME_HOUR_HELP),\r
+    minimum     = 0,\r
+    maximum     = 23,\r
+    step        = 1,\r
+    default     = 0,\r
+\r
+    minute varid  = Time.Minutes,       // Note that it is a member of NULL, so the RTC will be the system resource to retrieve and save from\r
+    prompt        = STRING_TOKEN(STR_TIME_PROMPT),\r
+    help          = STRING_TOKEN(STR_TIME_MINUTE_HELP),\r
+    minimum       = 0,\r
+    maximum       = 59,\r
+    step          = 1,\r
+    default       = 0,\r
+\r
+    second varid  = Time.Seconds,       // Note that it is a member of NULL, so the RTC will be the system resource to retrieve and save from\r
+    prompt        = STRING_TOKEN(STR_TIME_PROMPT),\r
+    help          = STRING_TOKEN(STR_TIME_SECOND_HELP),\r
+    minimum       = 0,\r
+    maximum       = 59,\r
+    step          = 1,\r
+    default       = 0,\r
+  endtime;\r
+\r
+endform;\r
+\r
+form formid = PLATFORM_INFORMATION_FORM_ID,\r
+\r
+  title    = STRING_TOKEN(STR_PLATFORM_INFORMATION_TITLE);\r
+\r
+  subtitle text = STRING_TOKEN(STR_NULL_STRING);\r
+\r
+  subtitle text = STRING_TOKEN(STR_PLATFORM_FIRMWARE_STRING);\r
+  text\r
+    help   = STRING_TOKEN(STR_NULL_STRING),\r
+    text   = STRING_TOKEN(STR_SOC_STRING),\r
+    text   = STRING_TOKEN(STR_SOC_VALUE),\r
+    flags  = 0,\r
+    key    = 0;\r
+\r
+  text\r
+    help   = STRING_TOKEN(STR_NULL_STRING),\r
+    text   = STRING_TOKEN(STR_MRC_VERSION_STRING),\r
+    text   = STRING_TOKEN(STR_MRC_VERSION_VALUE),\r
+    flags  = 0,\r
+    key    = 0;\r
+\r
+  text\r
+    help   = STRING_TOKEN(STR_NULL_STRING),\r
+    text   = STRING_TOKEN(STR_PUNIT_FW_STRING),\r
+    text   = STRING_TOKEN(STR_PUNIT_FW_VALUE),\r
+    flags  = 0,\r
+    key    = 0;\r
+\r
+  text\r
+    help   = STRING_TOKEN(STR_NULL_STRING),\r
+    text   = STRING_TOKEN(STR_PMC_FW_STRING),\r
+    text   = STRING_TOKEN(STR_PMC_FW_VALUE),\r
+    flags  = 0,\r
+    key    = 0;\r
+\r
+  text\r
+    help   = STRING_TOKEN(STR_NULL_STRING),\r
+    text   = STRING_TOKEN(STR_KSC_FW_STRING),\r
+    text   = STRING_TOKEN(STR_KSC_FW_VALUE),\r
+    flags  = 0,\r
+    key    = 0;\r
+\r
+  text\r
+    help   = STRING_TOKEN(STR_NULL_STRING),\r
+    text   = STRING_TOKEN(STR_SEC_VERSION_STRING),\r
+    text   = STRING_TOKEN(STR_SEC_VERSION_VALUE),\r
+    flags  = 0,\r
+    key    = 0;\r
+\r
+  suppressif ideqval Setup.GOPEnable == 0;\r
+  text\r
+    help   = STRING_TOKEN(STR_NULL_STRING),\r
+    text   = STRING_TOKEN(STR_GOP_STRING),\r
+    text   = STRING_TOKEN(STR_GOP_VALUE),\r
+    flags  = 0,\r
+    key    = 0;\r
+  endif;\r
+\r
+  suppressif ideqval Setup.GOPEnable == 1;\r
+  text\r
+    help   = STRING_TOKEN(STR_CHIP_IGD_VBIOS_REV_HELP),\r
+    text   = STRING_TOKEN(STR_CHIP_IGD_VBIOS_REV_NAME),\r
+    text   = STRING_TOKEN(STR_CHIP_IGD_VBIOS_REV_VALUE),\r
+    flags  = 0,\r
+    key    = 0;\r
+  endif;\r
+\r
+  text\r
+    help   = STRING_TOKEN(STR_CPU_FLAVOR_HELP),\r
+    text   = STRING_TOKEN(STR_CPU_FLAVOR_NAME),\r
+    text   = STRING_TOKEN(STR_CPU_FLAVOR_VALUE),\r
+    flags  = 0,\r
+    key    = 0;\r
+\r
+  text\r
+    help   = STRING_TOKEN(STR_BOARD_ID_HELP),\r
+    text   = STRING_TOKEN(STR_BOARD_ID_NAME),\r
+    text   = STRING_TOKEN(STR_BOARD_ID_VALUE),\r
+    flags  = 0,\r
+    key    = 0;\r
+\r
+  text\r
+    help   = STRING_TOKEN(STR_FAB_ID_HELP),\r
+    text   = STRING_TOKEN(STR_FAB_ID_STRING),\r
+    text   = STRING_TOKEN(STR_FAB_ID_VALUE),\r
+    flags  = 0,\r
+    key = 0;\r
+\r
+\r
+  subtitle text = STRING_TOKEN(STR_NULL_STRING);\r
+\r
+  subtitle text = STRING_TOKEN(STR_MEMORY_INFORMATION_STRING);\r
+  text\r
+    help   = STRING_TOKEN(STR_NULL_STRING),\r
+    text   = STRING_TOKEN(STR_TOTAL_MEMORY_SIZE_PROMPT),\r
+    text   = STRING_TOKEN(STR_TOTAL_MEMORY_SIZE_VALUE),\r
+    flags  = 0,\r
+    key    = 0;\r
+\r
+  text\r
+    help   = STRING_TOKEN(STR_NULL_STRING),\r
+    text   = STRING_TOKEN(STR_SYSTEM_MEMORY_SPEED_STRING),\r
+    text   = STRING_TOKEN(STR_SYSTEM_MEMORY_SPEED_VALUE),\r
+    flags  = 0,\r
+    key    = 0;\r
+\r
+  text\r
+    help   = STRING_TOKEN(STR_NULL_STRING),\r
+    text   = STRING_TOKEN(STR_PROCESSOR_L1_DATA_CACHE_STRING),\r
+    text   = STRING_TOKEN(STR_PROCESSOR_L1_DATA_CACHE_VALUE),\r
+    flags  = 0,\r
+    key    = 0;\r
+\r
+  text\r
+    help   = STRING_TOKEN(STR_NULL_STRING),\r
+    text   = STRING_TOKEN(STR_PROCESSOR_L1_INSTR_CACHE_STRING),\r
+    text   = STRING_TOKEN(STR_PROCESSOR_L1_INSTR_CACHE_VALUE),\r
+    flags  = 0,\r
+    key    = 0;\r
+\r
+  text\r
+    help   = STRING_TOKEN(STR_NULL_STRING),\r
+    text   = STRING_TOKEN(STR_PROCESSOR_L2_CACHE_STRING),\r
+    text   = STRING_TOKEN(STR_PROCESSOR_L2_CACHE_VALUE),\r
+    flags  = 0,\r
+    key    = 0;\r
+\r
+endform;\r
+\r

diff --git a/Vlv2TbltDevicePkg/PlatformSetupDxe/PlatformSetupDxe.c b/Vlv2TbltDevicePkg/PlatformSetupDxe/PlatformSetupDxe.c
new file mode 100644 (file)
index 0000000..1490e2c
--- /dev/null
+++ b/Vlv2TbltDevicePkg/PlatformSetupDxe/PlatformSetupDxe.c
@@ -0,0 +1,933 @@
+/** @file\r
+\r
+  Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+Module Name:\r
+\r
+**/\r
+\r
+#include "PlatformSetupDxe.h"\r
+#include "Guid/SetupVariable.h"\r
+\r
+#define EFI_CALLBACK_INFO_SIGNATURE SIGNATURE_32 ('C', 'l', 'b', 'k')\r
+#define EFI_CALLBACK_INFO_FROM_THIS(a)  CR (a, EFI_CALLBACK_INFO, ConfigAccess, EFI_CALLBACK_INFO_SIGNATURE)\r
+\r
+typedef struct {\r
+  UINTN                           Signature;\r
+  EFI_HANDLE                      DriverHandle;\r
+  EFI_HII_HANDLE                  RegisteredHandle;\r
+  SYSTEM_CONFIGURATION            FakeNvData;\r
+  SYSTEM_CONFIGURATION            BackupNvData;\r
+  EFI_HII_CONFIG_ROUTING_PROTOCOL *HiiConfigRouting;\r
+  EFI_HII_CONFIG_ACCESS_PROTOCOL  ConfigAccess;\r
+} EFI_CALLBACK_INFO;\r
+\r
+#pragma pack(1)\r
+\r
+//\r
+// HII specific Vendor Device Path definition.\r
+//\r
+typedef struct {\r
+  VENDOR_DEVICE_PATH             VendorDevicePath;\r
+  EFI_DEVICE_PATH_PROTOCOL       End;\r
+} HII_VENDOR_DEVICE_PATH;\r
+\r
+#pragma pack()\r
+\r
+//\r
+// uni string and Vfr Binary data.\r
+//\r
+extern UINT8  VfrBin[];\r
+extern UINT8  PlatformSetupDxeStrings[];\r
+\r
+EFI_HANDLE            mImageHandle;\r
+\r
+//\r
+// module global data\r
+//\r
+#define EFI_NORMAL_SETUP_GUID \\r
+  { 0xec87d643, 0xeba4, 0x4bb5, 0xa1, 0xe5, 0x3f, 0x3e, 0x36, 0xb2, 0xd, 0xa9 }\r
+\r
+EFI_GUID                     mNormalSetupGuid = EFI_NORMAL_SETUP_GUID;\r
+\r
+EFI_GUID                     mSystemConfigGuid = SYSTEM_CONFIGURATION_GUID;\r
+CHAR16                       mVariableName[] = L"Setup";\r
+CHAR16                       mSetupName[] = L"Setup";\r
+EFI_CALLBACK_INFO           *mCallbackInfo;\r
+BOOLEAN                      GlobalReset=FALSE;\r
+\r
+HII_VENDOR_DEVICE_PATH  mHiiVendorDevicePath = {\r
+  {\r
+    {\r
+      HARDWARE_DEVICE_PATH,\r
+      HW_VENDOR_DP,\r
+      {\r
+        (UINT8) (sizeof (VENDOR_DEVICE_PATH)),\r
+        (UINT8) ((sizeof (VENDOR_DEVICE_PATH)) >> 8)\r
+      }\r
+    },\r
+    EFI_CALLER_ID_GUID\r
+  },\r
+  {\r
+    END_DEVICE_PATH_TYPE,\r
+    END_ENTIRE_DEVICE_PATH_SUBTYPE,\r
+    {\r
+      (UINT8) (END_DEVICE_PATH_LENGTH),\r
+      (UINT8) ((END_DEVICE_PATH_LENGTH) >> 8)\r
+    }\r
+  }\r
+};\r
+\r
+/**\r
+  This function allows a caller to extract the current configuration for one\r
+  or more named elements from the target driver.\r
+\r
+  @param  This         Points to the EFI_HII_CONFIG_ACCESS_PROTOCOL.\r
+  @param  Request      A null-terminated Unicode string in <ConfigRequest> format.\r
+  @param  Progress     On return, points to a character in the Request string.\r
+                       Points to the string's null terminator if request was successful.\r
+                       Points to the most recent '&' before the first failing name/value\r
+                       pair (or the beginning of the string if the failure is in the\r
+                       first name/value pair) if the request was not successful.\r
+  @param  Results      A null-terminated Unicode string in <ConfigAltResp> format which\r
+                       has all values filled in for the names in the Request string.\r
+                       String to be allocated by the called function.\r
+\r
+  @retval EFI_SUCCESS            The Results is filled with the requested values.\r
+  @retval EFI_OUT_OF_RESOURCES   Not enough memory to store the results.\r
+  @retval EFI_INVALID_PARAMETER  Request is NULL, illegal syntax, or unknown name.\r
+  @retval EFI_NOT_FOUND          Routing data doesn't match any storage in this driver.\r
+\r
+**/\r
+\r
+VOID\r
+CheckSystemConfigLoad(SYSTEM_CONFIGURATION *SystemConfigPtr);\r
+\r
+VOID\r
+CheckSystemConfigSave(SYSTEM_CONFIGURATION *SystemConfigPtr);\r
+\r
+VOID\r
+ConfirmSecureBootTest();\r
+\r
+VOID\r
+LoadLpssDefaultValues (\r
+  IN EFI_CALLBACK_INFO                       *Private\r
+  )\r
+{\r
+  //\r
+  // Load LPSS and SCC defalut configurations for Android\r
+  //\r
+  Private->FakeNvData.LpsseMMCEnabled            = FALSE;\r
+  Private->FakeNvData.LpssSdioEnabled            = TRUE;\r
+  Private->FakeNvData.LpssSdcardEnabled          = TRUE;\r
+  Private->FakeNvData.LpssSdCardSDR25Enabled     = FALSE;\r
+  Private->FakeNvData.LpssSdCardDDR50Enabled     = TRUE;\r
+  Private->FakeNvData.LpssMipiHsi                = FALSE;\r
+  Private->FakeNvData.LpsseMMC45Enabled          = TRUE;\r
+  Private->FakeNvData.LpsseMMC45DDR50Enabled     = TRUE;\r
+  Private->FakeNvData.LpsseMMC45HS200Enabled     = FALSE;\r
+  Private->FakeNvData.LpsseMMC45RetuneTimerValue = 8;\r
+  Private->FakeNvData.eMMCBootMode               = 1;     // Auto Detect\r
+\r
+  Private->FakeNvData.GOPEnable = TRUE;\r
+  Private->FakeNvData.SecureBoot = TRUE;\r
+  Private->FakeNvData.UsbAutoMode = TRUE;\r
+  Private->FakeNvData.UsbXhciSupport = TRUE;\r
+  Private->FakeNvData.PchUsb30Mode = TRUE;\r
+  Private->FakeNvData.LegacyUSBBooting = FALSE;\r
+  Private->FakeNvData.PchUsb20 = FALSE;\r
+}\r
+\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+SystemConfigExtractConfig (\r
+  IN  CONST EFI_HII_CONFIG_ACCESS_PROTOCOL   *This,\r
+  IN  CONST EFI_STRING                       Request,\r
+  OUT EFI_STRING                             *Progress,\r
+  OUT EFI_STRING                             *Results\r
+  )\r
+{\r
+  EFI_STATUS                       Status;\r
+  EFI_CALLBACK_INFO                *Private;\r
+  EFI_HII_CONFIG_ROUTING_PROTOCOL  *HiiConfigRouting;\r
+  EFI_STRING                       ConfigRequestHdr;\r
+  EFI_STRING                       ConfigRequest;\r
+  BOOLEAN                          AllocatedRequest;\r
+  UINTN                            Size;\r
+  UINTN                            BufferSize;\r
+  VOID                             *SystemConfigPtr;\r
+\r
+\r
+  if (Progress == NULL || Results == NULL) {\r
+    return EFI_INVALID_PARAMETER;\r
+  }\r
+\r
+  *Progress = Request;\r
+  if ((Request != NULL) && !HiiIsConfigHdrMatch (Request, &mSystemConfigGuid, mVariableName)) {\r
+    return EFI_NOT_FOUND;\r
+  }\r
+\r
+  ConfigRequestHdr = NULL;\r
+  ConfigRequest    = NULL;\r
+  Size             = 0;\r
+  AllocatedRequest = FALSE;\r
+\r
+  Private          = EFI_CALLBACK_INFO_FROM_THIS (This);\r
+\r
+  SetupInfo();\r
+\r
+  HiiConfigRouting = Private->HiiConfigRouting;\r
+  ConfigRequest = Request;\r
+  if ((Request == NULL) || (StrStr (Request, L"OFFSET") == NULL)) {\r
+    //\r
+    // Request has no request element, construct full request string.\r
+    // Allocate and fill a buffer large enough to hold the <ConfigHdr> template\r
+    // followed by "&OFFSET=0&WIDTH=WWWWWWWWWWWWWWWW" followed by a Null-terminator\r
+    //\r
+    ConfigRequestHdr = HiiConstructConfigHdr (&mSystemConfigGuid, mVariableName, Private->DriverHandle);\r
+    Size = (StrLen (ConfigRequestHdr) + 32 + 1) * sizeof (CHAR16);\r
+    ConfigRequest = AllocateZeroPool (Size);\r
+    ASSERT (ConfigRequest != NULL);\r
+    AllocatedRequest = TRUE;\r
+    BufferSize = sizeof (SYSTEM_CONFIGURATION);\r
+    UnicodeSPrint (ConfigRequest, Size, L"%s&OFFSET=0&WIDTH=%016LX", ConfigRequestHdr, (UINT64)BufferSize);\r
+    FreePool (ConfigRequestHdr);\r
+  }\r
+  SystemConfigPtr = GetVariable(mSetupName, &mNormalSetupGuid);\r
+\r
+\r
+  if (SystemConfigPtr == NULL) {\r
+    ZeroMem(&Private->FakeNvData, sizeof(SYSTEM_CONFIGURATION));\r
+    ZeroMem(&Private->BackupNvData, sizeof(SYSTEM_CONFIGURATION));\r
+  } else {\r
+    CheckSystemConfigLoad(SystemConfigPtr);\r
+    CopyMem(&Private->FakeNvData, SystemConfigPtr, sizeof(SYSTEM_CONFIGURATION));\r
+    CopyMem(&Private->BackupNvData, SystemConfigPtr, sizeof(SYSTEM_CONFIGURATION));\r
+    FreePool(SystemConfigPtr);\r
+  }\r
+\r
+  //\r
+  // Convert buffer data to <ConfigResp> by helper function BlockToConfig()\r
+  //\r
+  Status = HiiConfigRouting->BlockToConfig (\r
+                               HiiConfigRouting,\r
+                               ConfigRequest,\r
+                               (UINT8 *) &Private->FakeNvData,\r
+                               sizeof (SYSTEM_CONFIGURATION),\r
+                               Results,\r
+                               Progress\r
+                               );\r
+\r
+  //\r
+  // Free the allocated config request string.\r
+  //\r
+  if (AllocatedRequest) {\r
+    FreePool (ConfigRequest);\r
+    ConfigRequest = NULL;\r
+  }\r
+\r
+  //\r
+  // Set Progress string to the original request string.\r
+  //\r
+  if (Request == NULL) {\r
+    *Progress = NULL;\r
+  } else if (StrStr (Request, L"OFFSET") == NULL) {\r
+    *Progress = Request + StrLen (Request);\r
+  }\r
+\r
+  return Status;\r
+}\r
+\r
+/**\r
+  This function processes the results of changes in configuration.\r
+\r
+  @param  This            Points to the EFI_HII_CONFIG_ACCESS_PROTOCOL.\r
+  @param  Configuration   A null-terminated Unicode string in <ConfigRequest> format.\r
+  @param  Progress        A pointer to a string filled in with the offset of the most\r
+                          recent '&' before the first failing name/value pair (or the\r
+                          beginning of the string if the failure is in the first\r
+                          name/value pair) or the terminating NULL if all was successful.\r
+\r
+  @retval EFI_SUCCESS            The Results is processed successfully.\r
+  @retval EFI_INVALID_PARAMETER  Configuration is NULL.\r
+  @retval EFI_NOT_FOUND          Routing data doesn't match any storage in this driver.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+SystemConfigRouteConfig (\r
+  IN  CONST EFI_HII_CONFIG_ACCESS_PROTOCOL   *This,\r
+  IN  CONST EFI_STRING                       Configuration,\r
+  OUT EFI_STRING                             *Progress\r
+  )\r
+{\r
+  EFI_CALLBACK_INFO                         *Private;\r
+  SYSTEM_CONFIGURATION                       *FakeNvData;\r
+\r
+  if (Configuration == NULL || Progress == NULL) {\r
+    return EFI_INVALID_PARAMETER;\r
+  }\r
+  *Progress = Configuration;\r
+\r
+  if (!HiiIsConfigHdrMatch (Configuration, &mSystemConfigGuid, mVariableName)) {\r
+    return EFI_NOT_FOUND;\r
+  }\r
+\r
+  *Progress = Configuration + StrLen (Configuration);\r
+  Private    = EFI_CALLBACK_INFO_FROM_THIS (This);\r
+  FakeNvData = &Private->FakeNvData;\r
+  if (!HiiGetBrowserData (&mSystemConfigGuid, mVariableName, sizeof (SYSTEM_CONFIGURATION), (UINT8 *) FakeNvData)) {\r
+    //\r
+    // FakeNvData can't be got from SetupBrowser, which doesn't need to be set.\r
+    //\r
+    return EFI_SUCCESS;\r
+  }\r
+\r
+  if (Private->FakeNvData.ReservedO != Private->BackupNvData.ReservedO) {\r
+    Private->BackupNvData.ReservedO = Private->FakeNvData.ReservedO;\r
+    LoadLpssDefaultValues (Private);\r
+\r
+    //\r
+    // Pass changed uncommitted data back to Form Browser\r
+    //\r
+    HiiSetBrowserData (&mSystemConfigGuid, mVariableName, sizeof (SYSTEM_CONFIGURATION), (UINT8 *) FakeNvData, NULL);\r
+  }\r
+\r
+  gRT->SetVariable(\r
+         mSetupName,\r
+         &mNormalSetupGuid,\r
+         EFI_VARIABLE_RUNTIME_ACCESS | EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS,\r
+         sizeof(SYSTEM_CONFIGURATION),\r
+         &Private->FakeNvData\r
+         );\r
+\r
+  CheckSystemConfigSave(&Private->FakeNvData);\r
+  return EFI_SUCCESS;\r
+}\r
+\r
+/**\r
+  This is the function that is called to provide results data to the driver.  This data\r
+  consists of a unique key which is used to identify what data is either being passed back\r
+  or being asked for.\r
+\r
+  @param  This           Points to the EFI_HII_CONFIG_ACCESS_PROTOCOL.\r
+  @param  Action         A null-terminated Unicode string in <ConfigRequest> format.\r
+  @param  KeyValue       A unique Goto OpCode callback value which record user's selection.\r
+                         0x100 <= KeyValue <0x500 : user select a controller item in the first page;\r
+                         KeyValue == 0x1234       : user select 'Refresh' in first page, or user select 'Go to Previous Menu' in second page\r
+                         KeyValue == 0x1235       : user select 'Pci device filter' in first page\r
+                         KeyValue == 0x1500       : user select 'order ... priority' item in second page\r
+                         KeyValue == 0x1800       : user select 'commint changes' in third page\r
+                         KeyValue == 0x2000       : user select 'Go to Previous Menu' in third page\r
+  @param  Type           The type of value for the question.\r
+  @param  Value          A pointer to the data being sent to the original exporting driver.\r
+  @param  ActionRequest  On return, points to the action requested by the callback function.\r
+\r
+  @retval EFI_SUCCESS    Always returned.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+SystemConfigCallback (\r
+  IN  CONST EFI_HII_CONFIG_ACCESS_PROTOCOL   *This,\r
+  IN  EFI_BROWSER_ACTION                     Action,\r
+  IN  EFI_QUESTION_ID                        KeyValue,\r
+  IN  UINT8                                  Type,\r
+  IN  EFI_IFR_TYPE_VALUE                     *Value,\r
+  OUT EFI_BROWSER_ACTION_REQUEST             *ActionRequest\r
+  )\r
+{\r
+  EFI_CALLBACK_INFO             *Private;\r
+  SYSTEM_CONFIGURATION          *FakeNvData;\r
+  SYSTEM_CONFIGURATION          *SetupData;\r
+  UINTN                         SizeOfNvStore;\r
+  EFI_INPUT_KEY                 Key;\r
+  CHAR16                        *StringBuffer1;\r
+  CHAR16                        *StringBuffer2;\r
+  CHAR16                        *StringBuffer3;\r
+  EFI_STATUS                    Status;\r
+  UINTN                         DataSize;\r
+  UINT8                         OsSelection;\r
+\r
+  StringBuffer1 = AllocateZeroPool (200 * sizeof (CHAR16));\r
+  ASSERT (StringBuffer1 != NULL);\r
+  StringBuffer2 = AllocateZeroPool (200 * sizeof (CHAR16));\r
+  ASSERT (StringBuffer2 != NULL);\r
+  StringBuffer3 = AllocateZeroPool (200 * sizeof (CHAR16));\r
+  ASSERT (StringBuffer3 != NULL);\r
+\r
+  switch (Action) {\r
+  case EFI_BROWSER_ACTION_CHANGING:\r
+  {\r
+    if (KeyValue == 0x1235) {\r
+      StrCpy (StringBuffer1, L"Will you disable PTT ? ");\r
+      StrCpy (StringBuffer2, L"Enter (YES)  /   Esc (NO)");\r
+\r
+      //\r
+      // Popup a menu to notice user\r
+      //\r
+      do {\r
+        CreatePopUp (EFI_LIGHTGRAY | EFI_BACKGROUND_BLUE, &Key, StringBuffer1, StringBuffer2, NULL);\r
+      } while ((Key.ScanCode != SCAN_ESC) && (Key.UnicodeChar != CHAR_CARRIAGE_RETURN));\r
+\r
+      //\r
+      // If the user hits the YES Response key,\r
+      //\r
+      if (Key.UnicodeChar == CHAR_CARRIAGE_RETURN) {\r
+\r
+      }\r
+    } else if (KeyValue == 0x1236) {\r
+      StrCpy (StringBuffer1, L"Will you revoke trust ? ");\r
+      StrCpy (StringBuffer2, L"Enter (YES)  /   Esc (NO)");\r
+\r
+      //\r
+      // Popup a menu to notice user\r
+      //\r
+      do {\r
+        CreatePopUp (EFI_LIGHTGRAY | EFI_BACKGROUND_BLUE, &Key, StringBuffer1, StringBuffer2, NULL);\r
+      } while ((Key.ScanCode != SCAN_ESC) && (Key.UnicodeChar != CHAR_CARRIAGE_RETURN));\r
+\r
+      //\r
+      // If the user hits the YES Response key,\r
+      //\r
+      if (Key.UnicodeChar == CHAR_CARRIAGE_RETURN) {\r
+\r
+      }\r
+        } else if (KeyValue == 0x1239) {\r
+          if (Value->u8 == 0x00) {\r
+       StrCpy (StringBuffer1, L"WARNING: SOC may be damaged due to high temperature");\r
+       StrCpy (StringBuffer2, L"when DPTF is disabled and IGD turbo is enabled.");\r
+       StrCpy (StringBuffer3, L"Press Enter/ESC to continue...");\r
+\r
+        //\r
+        // Popup a menu to notice user\r
+        //\r
+        do {\r
+          CreatePopUp (EFI_LIGHTGRAY | EFI_BACKGROUND_BLUE, &Key, StringBuffer1, StringBuffer2, StringBuffer3, NULL);\r
+        } while ((Key.ScanCode != SCAN_ESC) && (Key.UnicodeChar != CHAR_CARRIAGE_RETURN));\r
+    }\r
+    } else if (KeyValue == 0x1240) { // secure erase feature of eMMC\r
+           //\r
+      // Popup a menu to notice user\r
+      //\r
+      StrCpy (StringBuffer1, L"WARNING: All your data on the eMMC will be lost");\r
+      StrCpy (StringBuffer2, L"Do you really want to enable secure erase on eMMC?");\r
+      StrCpy (StringBuffer3, L"       Enter (YES)    /    Esc (NO)        ");\r
+\r
+      do {\r
+        CreatePopUp (EFI_LIGHTGRAY | EFI_BACKGROUND_BLUE, &Key, StringBuffer1, StringBuffer2, StringBuffer3,NULL);\r
+      } while ((Key.ScanCode != SCAN_ESC) && (Key.UnicodeChar != CHAR_CARRIAGE_RETURN));\r
+\r
+      //\r
+      // If the user hits the ESC Response key,\r
+      //\r
+      if (Key.ScanCode == SCAN_ESC) {\r
+        Private = EFI_CALLBACK_INFO_FROM_THIS (This);\r
+        FakeNvData = &Private->FakeNvData;\r
+\r
+        Status = HiiGetBrowserData (\r
+                              &mSystemConfigGuid,\r
+                                          mVariableName,\r
+                                          sizeof (SYSTEM_CONFIGURATION),\r
+                                          (UINT8 *) FakeNvData\r
+                                          );\r
+        if (!EFI_ERROR (Status)) {\r
+             FakeNvData->SecureErase = 0;\r
+             HiiSetBrowserData (\r
+               &mSystemConfigGuid,\r
+               mVariableName,\r
+               sizeof (SYSTEM_CONFIGURATION),\r
+               (UINT8 *) FakeNvData,\r
+               NULL\r
+               );\r
+        }\r
+        break;\r
+      }\r
+\r
+      //\r
+      // If the user hits the YES Response key\r
+      //\r
+      if (Key.UnicodeChar == CHAR_CARRIAGE_RETURN) {\r
+        //\r
+        // Save change\r
+        //\r
+        Private = EFI_CALLBACK_INFO_FROM_THIS (This);\r
+        FakeNvData = &Private->FakeNvData;\r
+\r
+        Status = HiiGetBrowserData (\r
+                              &mSystemConfigGuid,\r
+                                          mVariableName,\r
+                                          sizeof (SYSTEM_CONFIGURATION),\r
+                                         (UINT8 *) FakeNvData\r
+                                         );\r
+        if (!EFI_ERROR (Status)) {\r
+          Status = gRT->SetVariable (\r
+                          L"Setup",\r
+                          &mNormalSetupGuid,\r
+                          EFI_VARIABLE_RUNTIME_ACCESS | EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS,\r
+                          sizeof(SYSTEM_CONFIGURATION),\r
+                          &Private->FakeNvData\r
+                          );\r
+        }\r
+\r
+        //\r
+        // Reset system\r
+        //\r
+        gRT->ResetSystem(\r
+                          EfiResetCold,\r
+                                EFI_SUCCESS,\r
+                                0,\r
+                                NULL\r
+                                );\r
+\r
+    }\r
+\r
+\r
+    }\r
+    else if (KeyValue == 0xF001) {\r
+      //\r
+      // Popup a menu to notice user\r
+      //\r
+      StrCpy (StringBuffer1, L"Do you want to Commit Changes and Exit?");\r
+      StrCpy (StringBuffer2, L"         Enter (YES) / Esc (NO)        ");\r
+\r
+      do {\r
+        CreatePopUp (EFI_LIGHTGRAY | EFI_BACKGROUND_BLUE, &Key, StringBuffer1, StringBuffer2, NULL);\r
+      } while ((Key.ScanCode != SCAN_ESC) && (Key.UnicodeChar != CHAR_CARRIAGE_RETURN));\r
+\r
+      //\r
+      // If the user hits the YES Response key\r
+      //\r
+      if (Key.UnicodeChar == CHAR_CARRIAGE_RETURN) {\r
+        //\r
+        // Save change\r
+        //\r
+        Private = EFI_CALLBACK_INFO_FROM_THIS (This);\r
+        FakeNvData = &Private->FakeNvData;\r
+\r
+        Status = HiiGetBrowserData (\r
+                          &mSystemConfigGuid,\r
+                                  mVariableName,\r
+                                  sizeof (SYSTEM_CONFIGURATION),\r
+                                  (UINT8 *) FakeNvData\r
+                                  );\r
+        if (!EFI_ERROR (Status)) {\r
+          Status = gRT->SetVariable (\r
+                          L"Setup",\r
+                          &mNormalSetupGuid,\r
+                          EFI_VARIABLE_RUNTIME_ACCESS | EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS,\r
+                          sizeof(SYSTEM_CONFIGURATION),\r
+                          &Private->FakeNvData\r
+                          );\r
+        }\r
+\r
+               //\r
+               // Update Secure Boot configuration changes\r
+               //\r
+        CheckSystemConfigSave(FakeNvData);\r
+\r
+        //\r
+        // Reset system\r
+        //\r
+        if (GlobalReset == TRUE) {\r
+          //\r
+          // Issue full reset\r
+          //\r
+          IoWrite8 (\r
+            (UINTN) 0XCF9,\r
+            (UINT8) 0x02\r
+            );\r
+\r
+          IoWrite8 (\r
+            (UINTN) 0xCF9,\r
+            (UINT8) 0x0E\r
+            );\r
+        } else {\r
+               gRT->ResetSystem(\r
+                              EfiResetCold,\r
+                                  EFI_SUCCESS,\r
+                                  0,\r
+                                  NULL\r
+                                  );\r
+        }\r
+      }\r
+    } else if (KeyValue == 0xF002) {\r
+      //\r
+      // Popup a menu to notice user\r
+      //\r
+      StrCpy (StringBuffer1, L"Do you want to Discard Changes and Exit?");\r
+      StrCpy (StringBuffer2, L"         Enter (YES) / Esc (NO)         ");\r
+\r
+      do {\r
+        CreatePopUp (EFI_LIGHTGRAY | EFI_BACKGROUND_BLUE, &Key, StringBuffer1, StringBuffer2, NULL);\r
+      } while ((Key.ScanCode != SCAN_ESC) && (Key.UnicodeChar != CHAR_CARRIAGE_RETURN));\r
+\r
+      //\r
+      // If the user hits the YES Response key\r
+      //\r
+      if (Key.UnicodeChar == CHAR_CARRIAGE_RETURN) {\r
+        //\r
+        // Reset system\r
+        //\r
+        gRT->ResetSystem(EfiResetCold, EFI_SUCCESS, 0, NULL);\r
+      }\r
+    } else if (KeyValue == 0xF003) {\r
+      //\r
+      // Popup a menu to notice user\r
+      //\r
+      StrCpy (StringBuffer1, L"Do you want to load setup defaults and Exit?");\r
+      StrCpy (StringBuffer2, L"         Enter (YES) / Esc (NO)             ");\r
+\r
+      do {\r
+        CreatePopUp (EFI_LIGHTGRAY | EFI_BACKGROUND_BLUE, &Key, StringBuffer1, StringBuffer2, NULL);\r
+      } while ((Key.ScanCode != SCAN_ESC) && (Key.UnicodeChar != CHAR_CARRIAGE_RETURN));\r
+\r
+      //\r
+      // If the user hits the YES Response key\r
+      //\r
+      if (Key.UnicodeChar == CHAR_CARRIAGE_RETURN) {\r
+        //\r
+        // Load default\r
+        //\r
+        FakeNvData = AllocateZeroPool (sizeof(SYSTEM_CONFIGURATION));\r
+\r
+        if (FakeNvData == NULL) {\r
+          return EFI_OUT_OF_RESOURCES;\r
+        }\r
+\r
+        SizeOfNvStore = sizeof(SYSTEM_CONFIGURATION);\r
+        Status = gRT->GetVariable(\r
+                        L"SetupDefault",\r
+                        &mNormalSetupGuid,\r
+                        NULL,\r
+                        &SizeOfNvStore,\r
+                        FakeNvData\r
+                        );\r
+        if (!EFI_ERROR (Status)) {\r
+          if(SizeOfNvStore >= sizeof(SYSTEM_CONFIGURATION)) {\r
+            Status = gRT->SetVariable (\r
+                            L"Setup",\r
+                            &mNormalSetupGuid,\r
+                            EFI_VARIABLE_RUNTIME_ACCESS | EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS,\r
+                            sizeof(SYSTEM_CONFIGURATION),\r
+                            FakeNvData\r
+                            );\r
+          }\r
+        }\r
+\r
+        FreePool (FakeNvData);\r
+\r
+        DataSize = sizeof(OsSelection);\r
+        Status = gRT->GetVariable(\r
+                        L"OsSelection",\r
+                        &gOsSelectionVariableGuid,\r
+                        NULL,\r
+                        &DataSize,\r
+                        &OsSelection\r
+                        );\r
+\r
+        if (EFI_ERROR(Status) || (OsSelection != FakeNvData->ReservedO)) {\r
+          OsSelection = FakeNvData->ReservedO;\r
+          Status = gRT->SetVariable (\r
+                          L"OsSelection",\r
+                          &gOsSelectionVariableGuid,\r
+                          EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS | EFI_VARIABLE_NON_VOLATILE,\r
+                          sizeof(OsSelection),\r
+                          &OsSelection\r
+                          );\r
+        }\r
+\r
+        //\r
+        // Reset system\r
+        //\r
+        gRT->ResetSystem(\r
+                      EfiResetCold,\r
+                          EFI_SUCCESS,\r
+                          0,\r
+                          NULL\r
+                          );\r
+      }\r
+    } else if ((KeyValue == 0x123A) || (KeyValue == 0x123B) || (KeyValue == 0x123C)) {\r
+        StrCpy (StringBuffer1, L"WARNING: Enable or disable USB Controllers will ");\r
+        StrCpy (StringBuffer2, L"make global reset to restart system.");\r
+        StrCpy (StringBuffer3, L"Press Enter/ESC to continue...");\r
+        //\r
+        // Popup a menu to notice user\r
+        //\r
+        do {\r
+          CreatePopUp (EFI_LIGHTGRAY | EFI_BACKGROUND_BLUE, &Key, StringBuffer1, StringBuffer2, StringBuffer3, NULL);\r
+        } while ((Key.ScanCode != SCAN_ESC) && (Key.UnicodeChar != CHAR_CARRIAGE_RETURN));\r
+\r
+        FakeNvData = AllocateZeroPool (sizeof(SYSTEM_CONFIGURATION));\r
+        Status = HiiGetBrowserData (\r
+                          &mSystemConfigGuid,\r
+                                  mVariableName,\r
+                                  sizeof (SYSTEM_CONFIGURATION),\r
+                                  (UINT8 *) FakeNvData\r
+                                  );\r
+        //\r
+        // Get variable data\r
+        //\r
+        SizeOfNvStore = sizeof(SYSTEM_CONFIGURATION);\r
+        SetupData = AllocateZeroPool (sizeof(SYSTEM_CONFIGURATION));\r
+        Status = gRT->GetVariable(\r
+                        L"Setup",\r
+                        &mNormalSetupGuid,\r
+                        NULL,\r
+                        &SizeOfNvStore,\r
+                        SetupData\r
+                        );\r
+        if ((SetupData->UsbAutoMode != FakeNvData->UsbAutoMode) ||\r
+                  (SetupData->UsbXhciSupport != FakeNvData->UsbXhciSupport) ||\r
+                  (SetupData->PchUsb20 != FakeNvData->PchUsb20)) {\r
+          GlobalReset = TRUE;\r
+        } else {\r
+          GlobalReset = FALSE;\r
+        }\r
+\r
+    }\r
+  }\r
+  break;\r
+\r
+  default:\r
+    break;\r
+  }\r
+\r
+  FreePool (StringBuffer1);\r
+  FreePool (StringBuffer2);\r
+  FreePool (StringBuffer3);\r
+\r
+  //\r
+  // Workaround for Load Default for "DPTF Enable"\r
+  //\r
+  if (Action == EFI_BROWSER_ACTION_DEFAULT_STANDARD) {\r
+    if (KeyValue == 0x1239) {\r
+      return EFI_NOT_FOUND;\r
+    }\r
+  }\r
+\r
+  if (Action == EFI_BROWSER_ACTION_FORM_CLOSE) {\r
+    //\r
+    // Do nothing for UEFI OPEN/CLOSE Action\r
+    //\r
+    return EFI_SUCCESS;\r
+  }\r
+\r
+  Private = EFI_CALLBACK_INFO_FROM_THIS (This);\r
+  FakeNvData = &Private->FakeNvData;\r
+  if (!HiiGetBrowserData (&mSystemConfigGuid, mVariableName, sizeof (SYSTEM_CONFIGURATION), (UINT8 *) FakeNvData)) {\r
+    return EFI_NOT_FOUND;\r
+  }\r
+\r
+  if ((Action == EFI_BROWSER_ACTION_FORM_OPEN) && (Private->FakeNvData.ReservedO != Private->BackupNvData.ReservedO)) {\r
+    Private->BackupNvData.ReservedO = Private->FakeNvData.ReservedO;\r
+    LoadLpssDefaultValues (Private);\r
+  }\r
+\r
+  //\r
+  // When user selected the secure erase, set it to disable\r
+  //\r
+  if((KeyValue == 0x1240) && (Action == EFI_BROWSER_ACTION_CHANGED)) {\r
+    FakeNvData->SecureErase = 0;\r
+  }\r
+\r
+  if ((Action == EFI_BROWSER_ACTION_FORM_OPEN) || (Action == EFI_BROWSER_ACTION_CHANGED)) {\r
+    //\r
+    // If function 0 is disabled, function 1 ~ 7 also required to be disabled.\r
+    //\r
+    if (Private->FakeNvData.LpssDma0Enabled == 0) {\r
+      Private->FakeNvData.LpssHsuart0Enabled = 0;\r
+      Private->FakeNvData.LpssHsuart1Enabled = 0;\r
+      Private->FakeNvData.LpssPwm0Enabled    = 0;\r
+      Private->FakeNvData.LpssPwm1Enabled    = 0;\r
+      Private->FakeNvData.LpssSpiEnabled     = 0;\r
+    }\r
+\r
+\r
+    //\r
+    // If function 0 is disabled, function 1 ~ 7 also required to be disabled.\r
+    //\r
+    if (Private->FakeNvData.LpssDma1Enabled == 0) {\r
+      Private->FakeNvData.LpssI2C0Enabled = 0;\r
+      Private->FakeNvData.LpssI2C1Enabled = 0;\r
+      Private->FakeNvData.LpssI2C2Enabled = 0;\r
+      Private->FakeNvData.LpssI2C3Enabled = 0;\r
+      Private->FakeNvData.LpssI2C4Enabled = 0;\r
+      Private->FakeNvData.LpssI2C5Enabled = 0;\r
+      Private->FakeNvData.LpssI2C6Enabled = 0;\r
+    }\r
+  }\r
+\r
+\r
+  //\r
+  // Pass changed uncommitted data back to Form Browser\r
+  //\r
+  HiiSetBrowserData (&mSystemConfigGuid, mVariableName, sizeof (SYSTEM_CONFIGURATION), (UINT8 *) FakeNvData, NULL);\r
+\r
+  return EFI_SUCCESS;\r
+}\r
+\r
+\r
+/**\r
+  The driver Entry Point. The funciton will export a disk device class formset and\r
+  its callback function to hii database.\r
+\r
+  @param  ImageHandle    The firmware allocated handle for the EFI image.\r
+  @param  SystemTable    A pointer to the EFI System Table.\r
+\r
+  @retval EFI_SUCCESS    The entry point is executed successfully.\r
+  @retval other          Some error occurs when executing this entry point.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+PlatformSetupDxeInit (\r
+  IN EFI_HANDLE                   ImageHandle,\r
+  IN EFI_SYSTEM_TABLE             *SystemTable\r
+  )\r
+{\r
+  EFI_STATUS                  Status;\r
+  EFI_FORM_BROWSER2_PROTOCOL  *FormBrowser2;\r
+\r
+  mImageHandle = ImageHandle;\r
+\r
+  //\r
+  // There should only be one Form Configuration protocol\r
+  //\r
+  Status = gBS->LocateProtocol (\r
+                 &gEfiFormBrowser2ProtocolGuid,\r
+                 NULL,\r
+                 (VOID **) &FormBrowser2\r
+                 );\r
+  if (EFI_ERROR (Status)) {\r
+    return Status;\r
+  }\r
+\r
+  mCallbackInfo = AllocateZeroPool (sizeof (EFI_CALLBACK_INFO));\r
+  if (mCallbackInfo == NULL) {\r
+    return EFI_BAD_BUFFER_SIZE;\r
+  }\r
+\r
+  mCallbackInfo->Signature = EFI_CALLBACK_INFO_SIGNATURE;\r
+  mCallbackInfo->ConfigAccess.ExtractConfig = SystemConfigExtractConfig;\r
+  mCallbackInfo->ConfigAccess.RouteConfig   = SystemConfigRouteConfig;\r
+  mCallbackInfo->ConfigAccess.Callback      = SystemConfigCallback;\r
+\r
+  //\r
+  // Install Device Path Protocol and Config Access protocol to driver handle\r
+  // Install Platform Driver Override Protocol to driver handle\r
+  //\r
+  Status = gBS->InstallMultipleProtocolInterfaces (\r
+                  &mCallbackInfo->DriverHandle,\r
+                  &gEfiDevicePathProtocolGuid,\r
+                  &mHiiVendorDevicePath,\r
+                  &gEfiHiiConfigAccessProtocolGuid,\r
+                  &mCallbackInfo->ConfigAccess,\r
+                  NULL\r
+                  );\r
+  if (EFI_ERROR (Status)) {\r
+    goto Finish;\r
+  }\r
+\r
+  //\r
+  // Publish our HII data\r
+  //\r
+  mCallbackInfo->RegisteredHandle = HiiAddPackages (\r
+                                      &mSystemConfigGuid,\r
+                                      mCallbackInfo->DriverHandle,\r
+                                      VfrBin,\r
+                                      PlatformSetupDxeStrings,\r
+                                      NULL\r
+                                      );\r
+  if (mCallbackInfo->RegisteredHandle == NULL) {\r
+    Status = EFI_OUT_OF_RESOURCES;\r
+    goto Finish;\r
+  }\r
+\r
+  mHiiHandle = mCallbackInfo->RegisteredHandle;\r
+\r
+  //\r
+  // Locate ConfigRouting protocol\r
+  //\r
+  Status = gBS->LocateProtocol (\r
+                  &gEfiHiiConfigRoutingProtocolGuid,\r
+                  NULL,\r
+                  (VOID **) &mCallbackInfo->HiiConfigRouting\r
+                  );\r
+  if (EFI_ERROR (Status)) {\r
+    goto Finish;\r
+  }\r
+\r
+  //\r
+  // Clear all the globle variable\r
+  //\r
+  return EFI_SUCCESS;\r
+\r
+Finish:\r
+  if (mCallbackInfo->DriverHandle != NULL) {\r
+    gBS->UninstallMultipleProtocolInterfaces (\r
+           mCallbackInfo->DriverHandle,\r
+           &gEfiDevicePathProtocolGuid,\r
+           &mHiiVendorDevicePath,\r
+           &gEfiHiiConfigAccessProtocolGuid,\r
+           &mCallbackInfo->ConfigAccess,\r
+           NULL\r
+           );\r
+  }\r
+\r
+  if (mCallbackInfo->RegisteredHandle != NULL) {\r
+    HiiRemovePackages (mCallbackInfo->RegisteredHandle);\r
+  }\r
+\r
+  if (mCallbackInfo != NULL) {\r
+    FreePool (mCallbackInfo);\r
+  }\r
+\r
+  return Status;\r
+}\r
+\r
+/**\r
+  Unload its installed protocol.\r
+\r
+  @param[in]  ImageHandle       Handle that identifies the image to be unloaded.\r
+\r
+  @retval EFI_SUCCESS           The image has been unloaded.\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+PlatformSetupDxeUnload (\r
+  IN EFI_HANDLE  ImageHandle\r
+  )\r
+{\r
+  if (mCallbackInfo != NULL) {\r
+    if (mCallbackInfo->DriverHandle != NULL) {\r
+      gBS->UninstallMultipleProtocolInterfaces (\r
+             mCallbackInfo->DriverHandle,\r
+             &gEfiDevicePathProtocolGuid,\r
+             &mHiiVendorDevicePath,\r
+             &gEfiHiiConfigAccessProtocolGuid,\r
+             &mCallbackInfo->ConfigAccess,\r
+             NULL\r
+             );\r
+    }\r
+\r
+    if (mCallbackInfo->RegisteredHandle != NULL) {\r
+      HiiRemovePackages (mCallbackInfo->RegisteredHandle);\r
+    }\r
+\r
+    FreePool (mCallbackInfo);\r
+  }\r
+\r
+  return EFI_SUCCESS;\r
+}\r
+\r

diff --git a/Vlv2TbltDevicePkg/PlatformSetupDxe/PlatformSetupDxe.h b/Vlv2TbltDevicePkg/PlatformSetupDxe/PlatformSetupDxe.h
new file mode 100644 (file)
index 0000000..ebe5547
--- /dev/null
+++ b/Vlv2TbltDevicePkg/PlatformSetupDxe/PlatformSetupDxe.h
@@ -0,0 +1,102 @@
+/*++\r
+\r
+  Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+\r
+**/\r
+\r
+#ifndef _PLAT_OVER_MNGR_H_\r
+#define _PLAT_OVER_MNGR_H_\r
+\r
+#include <FrameworkDxe.h>\r
+\r
+#include <Protocol/HiiConfigAccess.h>\r
+#include <Protocol/HiiConfigRouting.h>\r
+#include <Protocol/HiiDatabase.h>\r
+#include <Protocol/FormBrowser2.h>\r
+#include <Protocol/LoadedImage.h>\r
+#include <Protocol/FirmwareVolume2.h>\r
+#include <Protocol/PciIo.h>\r
+#include <Protocol/BusSpecificDriverOverride.h>\r
+#include <Protocol/ComponentName2.h>\r
+#include <Protocol/ComponentName.h>\r
+#include <Protocol/DriverBinding.h>\r
+#include <Protocol/DevicePathToText.h>\r
+#include <Protocol/DevicePath.h>\r
+#include <Protocol/PlatformDriverOverride.h>\r
+#include <Protocol/DataHub.h>\r
+#include <Guid/MdeModuleHii.h>\r
+#include <Guid/VariableFormat.h>\r
+#include <Guid/DataHubRecords.h>\r
+\r
+#include <Library/BaseLib.h>\r
+#include <Library/DebugLib.h>\r
+#include <Library/UefiLib.h>\r
+#include <Library/PrintLib.h>\r
+#include <Library/UefiDriverEntryPoint.h>\r
+#include <Library/UefiBootServicesTableLib.h>\r
+#include <Library/UefiRuntimeServicesTableLib.h>\r
+#include <Library/BaseMemoryLib.h>\r
+#include <Library/MemoryAllocationLib.h>\r
+#include <Library/DevicePathLib.h>\r
+#include <Library/DxeServicesTableLib.h>\r
+#include <Library/HiiLib.h>\r
+#include <Library/BiosIdLib.h>\r
+#include <Library/CpuIA32.h>\r
+#include <Library/HobLib.h>\r
+#include <Guid/PlatformInfo.h>\r
+#include <IndustryStandard/Pci22.h>\r
+\r
+#include "Guid/SetupVariable.h"\r
+#include "Guid/OsSelection.h"\r
+\r
+#include <CpuType.h>\r
+#include <Guid/PlatformCpuInfo.h>\r
+#include <Protocol/SimpleTextIn.h>\r
+#include <Protocol/FrameworkFormBrowser.h>\r
+extern EFI_HII_HANDLE   mHiiHandle;\r
+\r
+UINT32\r
+ConvertBase10ToRaw (\r
+  IN  EFI_EXP_BASE10_DATA             *Data);\r
+\r
+UINT32\r
+ConvertBase2ToRaw (\r
+  IN  EFI_EXP_BASE2_DATA             *Data);\r
+\r
+EFI_STATUS\r
+GetStringFromToken (\r
+  IN      EFI_GUID                  *ProducerGuid,\r
+  IN      STRING_REF                Token,\r
+  OUT     CHAR16                    **String\r
+  );\r
+\r
+VOID\r
+SwapEntries (\r
+  IN  CHAR8 *Data\r
+  );\r
+\r
+VOID\r
+AsciiToUnicode (\r
+  IN    CHAR8     *AsciiString,\r
+  IN    CHAR16    *UnicodeString\r
+  );\r
+\r
+VOID\r
+EFIAPI\r
+SetupInfo (\r
+  );\r
+\r
+\r
+extern EFI_HANDLE mImageHandle;\r
+\r
+#endif\r

diff --git a/Vlv2TbltDevicePkg/PlatformSetupDxe/PlatformSetupDxe.inf b/Vlv2TbltDevicePkg/PlatformSetupDxe/PlatformSetupDxe.inf
new file mode 100644 (file)
index 0000000..9cd774b
--- /dev/null
+++ b/Vlv2TbltDevicePkg/PlatformSetupDxe/PlatformSetupDxe.inf
@@ -0,0 +1,145 @@
+#\r
+#\r
+# Copyright (c)  1999  - 2014, Intel Corporation. All rights reserved\r
+#                                                                                  \r\r
+# This program and the accompanying materials are licensed and made available under\r\r
+# the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+# The full text of the license may be found at                                     \r\r
+# http://opensource.org/licenses/bsd-license.php.                                  \r\r
+#                                                                                  \r\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+#                                                                                  \r\r
+#\r
+#\r
+#  This driver produces UEFI PLATFORM_DRIVER_OVERRIDE_PROTOCOL if this protocol doesn't exist.\r
+#  It doesn't install again if this protocol exists.\r
+#  It only implements one interface GetDriver of PLATFORM_DRIVER_OVERRIDE_PROTOCOL protocol\r
+#  and doesn't support other two interfaces GetDriverPath, DriverLoaded.\r
+#\r
+#  This driver also offers an UI interface in device manager to let user configure\r
+#  platform override protocol to override the default algorithm for matching\r
+#  drivers to controllers.\r
+#\r
+#  The main flow:\r
+#  1. It dynamicly locate all controller device path.\r
+#  2. It dynamicly locate all drivers which support binding protocol.\r
+#  3. It export and dynamicly update two menu to let user select the\r
+#     mapping between drivers to controllers.\r
+#  4. It save all the mapping info in NV variables for the following boot,\r
+#     which will be consumed by GetDriver API of the produced the platform override protocol.\r
+#\r
+#\r
+##\r
+\r
+[Defines]\r
+  INF_VERSION                    = 0x00010005\r
+  BASE_NAME                      = PlatformSetupDxe\r
+  FILE_GUID                      = C1A69A12-8653-4fde-A215-48FCD95288C3\r
+  MODULE_TYPE                    = DXE_DRIVER\r
+  VERSION_STRING                 = 1.0\r
+  ENTRY_POINT                    = PlatformSetupDxeInit\r
+  UNLOAD_IMAGE                   = PlatformSetupDxeUnload\r
+\r
+#\r
+# The following information is for reference only and not required by the build tools.\r
+#\r
+#  VALID_ARCHITECTURES           = IA32 X64 IPF EBC\r
+#\r
+\r
+[Sources]\r
+  VfrStrings.uni\r
+  FwVersionStrings.uni\r
+  Vfr.vfr\r
+  Main.vfi\r
+  Boot.vfi\r
+  PlatformSetupDxe.c\r
+  SetupInfoRecords.c\r
+  PlatformSetupDxe.h\r
+  Security.vfi\r
+  SouthClusterConfig.vfi\r
+  Thermal.vfi\r
+  SetupFunctions.c\r
+  UnCore.vfi\r
+  SystemComponent.vfi\r
+  DebugConfig.vfi\r
+  UqiList.uni\r
+\r
+[Packages]\r
+  MdePkg/MdePkg.dec\r
+  MdeModulePkg/MdeModulePkg.dec\r
+  IntelFrameworkPkg/IntelFrameworkPkg.dec\r
+  Vlv2TbltDevicePkg/PlatformPkg.dec\r
+  Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec    #for PchAccess.h\r
+  SecurityPkg/SecurityPkg.dec\r
+\r
+[LibraryClasses]\r
+  BaseLib\r
+  DebugLib\r
+  UefiLib\r
+  UefiDriverEntryPoint\r
+  UefiBootServicesTableLib\r
+  HiiLib\r
+  BaseMemoryLib\r
+  MemoryAllocationLib\r
+  DevicePathLib\r
+  DxeServicesTableLib\r
+  UefiRuntimeServicesTableLib\r
+  PrintLib\r
+  BiosIdLib\r
+  CpuIA32Lib\r
+  IoLib\r
+\r
+[Guids]\r
+  ##  This GUID C Name is not required for build since it is from UefiLib and not directly used by this module source.\r
+  ##  gEfiGlobalVariableGuid                      ## SOMETIMES_CONSUMED ## Variable:L"PlatformLang" this variable specifies the platform supported language string (RFC 4646 format)\r
+  ##  gEfiGlobalVariableGuid                      ## SOMETIMES_CONSUMED ## Variable:L"Lang" this variable specifies the platform supported language string (ISO 639-2 format)\r
+  ##\r
+  # There could be more than one variables, from PlatDriOver, PlatDriOver1, PlatDriOver2,...\r
+  #\r
+  # gEfiCallerIdGuid                            ## Private  ## Variable:L"PlatDriOver"\r
+  gEfiIfrTianoGuid                              ## CONSUMES ## Guid\r
+  gEfiProcessorSubClassGuid\r
+  gEfiMiscSubClassGuid\r
+  gEfiCacheSubClassGuid\r
+  gEfiMemorySubClassGuid\r
+  gEfiPlatformInfoGuid\r
+  gEfiNormalSetupGuid\r
+  gEfiSecureBootEnableDisableGuid\r
+  gOsSelectionVariableGuid\r
+  gEfiGlobalVariableGuid\r
+\r
+[Protocols]\r
+  gEfiComponentName2ProtocolGuid                ## SOMETIMES_CONSUMED (Get Driver Name if ComponentName2Protocol exists)\r
+  gEfiComponentNameProtocolGuid                 ## SOMETIMES_CONSUMED (Get Driver Name if ComponentNameProtocol exists and ComponentName2Protocol doesn't exist)\r
+  gEfiFirmwareVolume2ProtocolGuid               ## SOMETIMES_CONSUMED (Get Driver Name from EFI UI section if ComponentName2Protocol and ComponentNameProtocol don't exist)\r
+  gEfiPciIoProtocolGuid                         ## SOMETIMES_CONSUMED (Find the PCI device if PciIo protocol is installed)\r
+  gEfiPciRootBridgeIoProtocolGuid\r
+  gEfiBusSpecificDriverOverrideProtocolGuid     ## SOMETIMES_CONSUMED (Check whether the PCI device contains one or more efi drivers in its option rom by this protocol)\r
+\r
+  gEfiDriverBindingProtocolGuid                 ## SOMETIMES_CONSUMED\r
+  gEfiLoadedImageProtocolGuid                   ## SOMETIMES_CONSUMED\r
+  gEfiLoadedImageDevicePathProtocolGuid         ## SOMETIMES_CONSUMED (Show the drivers in the second page that support DriverBindingProtocol, LoadedImageProtocol and LoadedImageDevicePathProtocol)\r
+  gEfiDevicePathProtocolGuid                    ## SOMETIMES_CONSUMED (Show the controller device in the first page that support DevicePathProtocol)\r
+\r
+  gEfiFormBrowser2ProtocolGuid                  ## CONSUMED\r
+  gEfiHiiConfigRoutingProtocolGuid              ## CONSUMED\r
+  gEfiHiiConfigAccessProtocolGuid               ## PRODUCED\r
+  gEfiDevicePathToTextProtocolGuid              ## CONSUMED\r
+\r
+  gEfiDataHubProtocolGuid\r
+  gEfiLegacyBiosProtocolGuid\r
+  gEfiSimpleNetworkProtocolGuid\r
+\r
+  gEfiDiskInfoProtocolGuid                      ## CONSUMED\r
+  gEfiMpServiceProtocolGuid\r
+  gDxePchPlatformPolicyProtocolGuid\r
+  gEfiCpuIo2ProtocolGuid\r
+  gEfiTdtOperationProtocolGuid\r
+  gEfiSmbiosProtocolGuid                        ## PROTOCOL CONSUMES\r
+\r
+[Pcd.common]\r
+  gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress\r
+\r
+[Depex]\r
+  gEfiFormBrowser2ProtocolGuid AND gEfiHiiConfigRoutingProtocolGuid\r

diff --git a/Vlv2TbltDevicePkg/PlatformSetupDxe/Security.vfi b/Vlv2TbltDevicePkg/PlatformSetupDxe/Security.vfi
new file mode 100644 (file)
index 0000000..f4922ff
--- /dev/null
+++ b/Vlv2TbltDevicePkg/PlatformSetupDxe/Security.vfi
@@ -0,0 +1,96 @@
+//\r
+//\r
+// Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+//                                                                                  \r\r
+// This program and the accompanying materials are licensed and made available under\r\r
+// the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+// The full text of the license may be found at                                     \r\r
+// http://opensource.org/licenses/bsd-license.php.                                  \r\r
+//                                                                                  \r\r
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+//                                                                                  \r\r
+//\r
+//\r
+//\r
+// Module Name:\r
+//\r
+//   Security.vfi\r
+//\r
+// Abstract:\r
+//\r
+//   Driver Setup formset.\r
+//\r
+// --*/\r
+\r
+//\r
+// Security Configuration Form\r
+//\r
+\r
+\r
+form formid = SECURITY_CONFIGURATION_FORM_ID,\r
+  title    = STRING_TOKEN(STR_SECURITY_CONFIGURATION_TITLE);\r
+\r
+\r
+  subtitle text = STRING_TOKEN(STR_NULL_STRING);\r
+  //\r
+  //TPM related\r
+  //\r
+  subtitle text = STRING_TOKEN(STR_TPM_CONFIGURATION_PROMPT);\r
+  oneof   varid   = Setup.ETpm,\r
+    prompt      = STRING_TOKEN(STR_TPM_PROMPT),\r
+    help        = STRING_TOKEN(STR_TPM_HELP),\r
+      option text = STRING_TOKEN(STR_ENABLE), value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED;\r
+      option text = STRING_TOKEN(STR_DISABLE), value= 0, flags= RESET_REQUIRED;\r
+  endoneof;\r
+\r
+  oneof varid = Setup.MeasuredBootEnable,\r
+    prompt      = STRING_TOKEN(STR_MEASURED_BOOT_ENABLE_PROMPT),\r
+    help        = STRING_TOKEN(STR_MEASURED_BOOT_ENABLE_HELP),\r
+    option text = STRING_TOKEN(STR_DISABLE), value = 0, flags = RESET_REQUIRED;\r
+    option text = STRING_TOKEN(STR_ENABLE), value = 1, flags =  DEFAULT | MANUFACTURING | RESET_REQUIRED;\r
+  endoneof;\r
+\r
+  subtitle text = STRING_TOKEN(STR_NULL_STRING);\r
+\r
+  subtitle text = STRING_TOKEN(STR_PASSWORD_CONFIGURATION_SUBTITLE);\r
+\r
+  password varid  = Setup.AdminPassword,\r
+    prompt      = STRING_TOKEN(STR_ADMIN_PASSWORD),\r
+    help        = STRING_TOKEN(STR_ADMIN_PASSWORD_HELP),\r
+    flags       = 0,\r
+    minsize     = 0,\r
+    maxsize     = PASSWORD_MAX_SIZE,\r
+    encoding    = 1,\r
+  endpassword;\r
+\r
+  password varid  = Setup.UserPassword,\r
+    prompt      = STRING_TOKEN(STR_USER_PASSWORD),\r
+    help        = STRING_TOKEN(STR_USER_PASSWORD_HELP),\r
+    flags       = 0,\r
+    minsize     = 0,\r
+    maxsize     = PASSWORD_MAX_SIZE,\r
+    encoding    = 1,\r
+  endpassword;\r
+suppressif TRUE;\r
+  password varid  = Setup.AdminPassword,\r
+    prompt      = STRING_TOKEN(STR_CHANGE_ADMIN_PASSWORD),\r
+    help        = STRING_TOKEN(STR_CHANGE_ADMIN_PASSWORD_HELP),\r
+    flags       = 0,\r
+    minsize     = 0,\r
+    maxsize     = PASSWORD_MAX_SIZE,\r
+    encoding    = 1,\r
+  endpassword;\r
+\r
+  password varid  = Setup.UserPassword,\r
+    prompt      = STRING_TOKEN(STR_CHANGE_USER_PASSWORD),\r
+    help        = STRING_TOKEN(STR_CHANGE_USER_PASSWORD_HELP),\r
+    flags       = 0,\r
+    minsize     = 0,\r
+    maxsize     = PASSWORD_MAX_SIZE,\r
+    encoding    = 1,\r
+  endpassword;\r
+endif;\r
+\r
+endform;\r
+\r

diff --git a/Vlv2TbltDevicePkg/PlatformSetupDxe/SetupFunctions.c b/Vlv2TbltDevicePkg/PlatformSetupDxe/SetupFunctions.c
new file mode 100644 (file)
index 0000000..9d8d0a0
--- /dev/null
+++ b/Vlv2TbltDevicePkg/PlatformSetupDxe/SetupFunctions.c
@@ -0,0 +1,90 @@
+/** @file\r
+\r
+  Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+\r
+Module Name:\r
+\r
+    SetupFunctions.c\r
+\r
+Abstract:\r
+\r
+Revision History\r
+\r
+--*/\r
+\r
+#include "PlatformSetupDxe.h"\r
+\r
+VOID\r
+AsciiToUnicode (\r
+  IN    CHAR8     *AsciiString,\r
+  IN    CHAR16    *UnicodeString\r
+  )\r
+{\r
+  UINT8           Index;\r
+\r
+  Index = 0;\r
+  while (AsciiString[Index] != 0) {\r
+    UnicodeString[Index] = (CHAR16)AsciiString[Index];\r
+    Index++;\r
+  }\r
+}\r
+\r
+VOID\r
+SwapEntries (\r
+  IN  CHAR8 *Data\r
+  )\r
+{\r
+  UINT16  Index;\r
+  CHAR8   Temp8;\r
+\r
+  Index = 0;\r
+  while (Data[Index] != 0 && Data[Index+1] != 0) {\r
+    Temp8 = Data[Index];\r
+    Data[Index] = Data[Index+1];\r
+    Data[Index+1] = Temp8;\r
+    Index +=2;\r
+  }\r
+\r
+  return;\r
+}\r
+\r
+UINT32\r
+ConvertBase10ToRaw (\r
+  IN  EFI_EXP_BASE10_DATA             *Data)\r
+{\r
+  UINTN         Index;\r
+  UINT32        RawData;\r
+\r
+  RawData = Data->Value;\r
+  for (Index = 0; Index < (UINTN) Data->Exponent; Index++) {\r
+     RawData *= 10;\r
+  }\r
+\r
+  return  RawData;\r
+}\r
+\r
+UINT32\r
+ConvertBase2ToRaw (\r
+  IN  EFI_EXP_BASE2_DATA             *Data)\r
+{\r
+  UINTN         Index;\r
+  UINT32        RawData;\r
+\r
+  RawData = Data->Value;\r
+  for (Index = 0; Index < (UINTN) Data->Exponent; Index++) {\r
+     RawData <<= 1;\r
+  }\r
+\r
+  return  RawData;\r
+}\r
+\r

diff --git a/Vlv2TbltDevicePkg/PlatformSetupDxe/SetupInfoRecords.c b/Vlv2TbltDevicePkg/PlatformSetupDxe/SetupInfoRecords.c
new file mode 100644 (file)
index 0000000..99684e7
--- /dev/null
+++ b/Vlv2TbltDevicePkg/PlatformSetupDxe/SetupInfoRecords.c
@@ -0,0 +1,1865 @@
+/** @file\r
+\r
+  Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+\r
+Module Name:\r
+\r
+    SetupInfoRecords.c\r
+\r
+Abstract:\r
+\r
+    This is the filter driver to retrieve data hub entries.\r
+\r
+Revision History:\r
+--*/\r
+\r
+#include "PlatformSetupDxe.h"\r
+#include <Protocol/LegacyBios.h>\r
+#include <Protocol/PciRootBridgeIo.h>\r
+#include <Protocol/SimpleNetwork.h>\r
+#include <Protocol/DevicePath.h>\r
+#include <Protocol/DiskInfo.h>\r
+#include <Protocol/IdeControllerInit.h>\r
+#include <Protocol/MpService.h>\r
+#include <Protocol/PchPlatformPolicy.h>\r
+#include <Protocol/CpuIo2.h>\r
+#include <Protocol/Smbios.h>\r
+#include <IndustryStandard/SmBios.h>\r
+#include <Library/IoLib.h>\r
+#include <Library/I2CLib.h>\r
+#include <Guid/GlobalVariable.h>\r
+\r
+#include "Valleyview.h"\r
+#include "VlvAccess.h"\r
+#include "PchAccess.h"\r
+#include "SetupMode.h"\r
+#include "PchCommonDefinitions.h"\r
+#include <PlatformBaseAddresses.h>\r
+\r
+\r
+typedef struct {\r
+  UINT8  ID;\r
+  CHAR8  String[16];\r
+} VLV_REV;\r
+\r
+typedef struct {\r
+  UINT8 RevId;\r
+  CHAR8 String[16];\r
+} SB_REV;\r
+\r
+//\r
+// Silicon Steppings\r
+//\r
+SB_REV  SBRevisionTable[] = {\r
+  {V_PCH_LPC_RID_0, "(A0 Stepping)"},\r
+  {V_PCH_LPC_RID_1, "(A0 Stepping)"},\r
+  {V_PCH_LPC_RID_2, "(A1 Stepping)"},\r
+  {V_PCH_LPC_RID_3, "(A1 Stepping)"},\r
+  {V_PCH_LPC_RID_4, "(B0 Stepping)"},\r
+  {V_PCH_LPC_RID_5, "(B0 Stepping)"},\r
+  {V_PCH_LPC_RID_6, "(B1 Stepping)"},\r
+  {V_PCH_LPC_RID_7, "(B1 Stepping)"},\r
+  {V_PCH_LPC_RID_8, "(B2 Stepping)"},\r
+  {V_PCH_LPC_RID_9, "(B2 Stepping)"},\r
+  {V_PCH_LPC_RID_A, "(B3 Stepping)"},\r
+  {V_PCH_LPC_RID_B, "(B3 Stepping)"},\r
+  {V_PCH_LPC_RID_C, "(C0 Stepping)"},\r
+  {V_PCH_LPC_RID_D, "(C0 Stepping)"}\r
+};\r
+\r
+#define LEFT_JUSTIFY  0x01\r
+#define PREFIX_SIGN   0x02\r
+#define PREFIX_BLANK  0x04\r
+#define COMMA_TYPE    0x08\r
+#define LONG_TYPE     0x10\r
+#define PREFIX_ZERO   0x20\r
+\r
+#define ICH_REG_REV                 0x08\r
+#define MSR_IA32_PLATFORM_ID        0x17\r
+\r
+\r
+BOOLEAN                         mSetupInfoDone = FALSE;\r
+UINT8                           mUseProductKey = 0;\r
+EFI_EXP_BASE10_DATA             mProcessorFrequency;\r
+EFI_EXP_BASE10_DATA             mProcessorFsbFrequency;\r
+\r
+EFI_GUID                        mProcessorProducerGuid;\r
+EFI_HII_HANDLE                  mHiiHandle;\r
+EFI_PLATFORM_CPU_INFO           mPlatformCpuInfo;\r
+SYSTEM_CONFIGURATION            mSystemConfiguration;\r
+EFI_PLATFORM_INFO_HOB           *mPlatformInfo;\r
+\r
+\r
+#define memset SetMem\r
+\r
+UINT16                mMemorySpeed         = 0xffff;\r
+EFI_PHYSICAL_ADDRESS  mMemorySizeChannelASlot0  = 0;\r
+UINT16                mMemorySpeedChannelASlot0 = 0xffff;\r
+EFI_PHYSICAL_ADDRESS  mMemorySizeChannelASlot1  = 0;\r
+UINT16                mMemorySpeedChannelASlot1 = 0xffff;\r
+EFI_PHYSICAL_ADDRESS  mMemorySizeChannelBSlot0  = 0;\r
+UINT16                mMemorySpeedChannelBSlot0 = 0xffff;\r
+EFI_PHYSICAL_ADDRESS  mMemorySizeChannelBSlot1  = 0;\r
+UINT16                mMemorySpeedChannelBSlot1 = 0xffff;\r
+EFI_PHYSICAL_ADDRESS  mMemorySizeChannelCSlot0  = 0;\r
+UINT16                mMemorySpeedChannelCSlot0 = 0xffff;\r
+EFI_PHYSICAL_ADDRESS  mMemorySizeChannelCSlot1  = 0;\r
+UINT16                mMemorySpeedChannelCSlot1 = 0xffff;\r
+UINTN                 mMemoryMode          = 0xff;\r
+\r
+#define CHARACTER_NUMBER_FOR_VALUE  30\r
+  typedef struct {\r
+  EFI_STRING_TOKEN            MemoryDeviceLocator;\r
+  EFI_STRING_TOKEN            MemoryBankLocator;\r
+  EFI_STRING_TOKEN            MemoryManufacturer;\r
+  EFI_STRING_TOKEN            MemorySerialNumber;\r
+  EFI_STRING_TOKEN            MemoryAssetTag;\r
+  EFI_STRING_TOKEN            MemoryPartNumber;\r
+  EFI_INTER_LINK_DATA         MemoryArrayLink;\r
+  EFI_INTER_LINK_DATA         MemorySubArrayLink;\r
+  UINT16                      MemoryTotalWidth;\r
+  UINT16                      MemoryDataWidth;\r
+  UINT64                      MemoryDeviceSize;\r
+  EFI_MEMORY_FORM_FACTOR      MemoryFormFactor;\r
+  UINT8                       MemoryDeviceSet;\r
+  EFI_MEMORY_ARRAY_TYPE       MemoryType;\r
+  EFI_MEMORY_TYPE_DETAIL      MemoryTypeDetail;\r
+  UINT16                      MemorySpeed;\r
+  EFI_MEMORY_STATE            MemoryState;\r
+} EFI_MEMORY_ARRAY_LINK;\r
+\r
+\r
+typedef struct {\r
+  EFI_PHYSICAL_ADDRESS        MemoryArrayStartAddress;\r
+  EFI_PHYSICAL_ADDRESS        MemoryArrayEndAddress;\r
+  EFI_INTER_LINK_DATA         PhysicalMemoryArrayLink;\r
+  UINT16                      MemoryArrayPartitionWidth;\r
+} EFI_MEMORY_ARRAY_START_ADDRESS;\r
+\r
+\r
+typedef enum {\r
+  PCH_SATA_MODE_IDE = 0,\r
+  PCH_SATA_MODE_AHCI,\r
+  PCH_SATA_MODE_RAID,\r
+  PCH_SATA_MODE_MAX\r
+} PCH_SATA_MODE;\r
+\r
+/**\r
+  Acquire the string associated with the Index from smbios structure and return it.\r
+  The caller is responsible for free the string buffer.\r
+\r
+  @param OptionalStrStart   The start position to search the string\r
+  @param Index              The index of the string to extract\r
+  @param String             The string that is extracted\r
+\r
+  @retval EFI_SUCCESS       The function returns EFI_SUCCESS always.\r
+\r
+**/\r
+EFI_STATUS\r
+GetOptionalStringByIndex (\r
+  IN      CHAR8                   *OptionalStrStart,\r
+  IN      UINT8                   Index,\r
+  OUT     CHAR16                  **String\r
+  )\r
+{\r
+  UINTN          StrSize;\r
+\r
+  if (Index == 0) {\r
+    *String = AllocateZeroPool (sizeof (CHAR16));\r
+    return EFI_SUCCESS;\r
+  }\r
+\r
+  StrSize = 0;\r
+  do {\r
+    Index--;\r
+    OptionalStrStart += StrSize;\r
+    StrSize           = AsciiStrSize (OptionalStrStart);\r
+  } while (OptionalStrStart[StrSize] != 0 && Index != 0);\r
+\r
+  if ((Index != 0) || (StrSize == 1)) {\r
+    //\r
+    // Meet the end of strings set but Index is non-zero, or\r
+    // Find an empty string\r
+    //\r
+    return EFI_NOT_FOUND;\r
+  } else {\r
+    *String = AllocatePool (StrSize * sizeof (CHAR16));\r
+    AsciiStrToUnicodeStr (OptionalStrStart, *String);\r
+  }\r
+\r
+  return EFI_SUCCESS;\r
+}\r
+\r
+/**\r
+  VSPrint worker function that prints a Value as a decimal number in Buffer\r
+\r
+  @param Buffer  Location to place ascii decimal number string of Value.\r
+  @param Value   Decimal value to convert to a string in Buffer.\r
+  @param Flags   Flags to use in printing decimal string, see file header for details.\r
+  @param Width   Width of hex value.\r
+\r
+  Number of characters printed.\r
+\r
+**/\r
+UINTN\r
+EfiValueToString (\r
+  IN  OUT CHAR16  *Buffer,\r
+  IN  INT64       Value,\r
+  IN  UINTN       Flags,\r
+  IN  UINTN       Width\r
+  )\r
+{\r
+  CHAR16    TempBuffer[CHARACTER_NUMBER_FOR_VALUE];\r
+  CHAR16    *TempStr;\r
+  CHAR16    *BufferPtr;\r
+  UINTN     Count;\r
+  UINTN     ValueCharNum;\r
+  UINTN     Remainder;\r
+  CHAR16    Prefix;\r
+  UINTN     Index;\r
+  BOOLEAN   ValueIsNegative;\r
+  UINT64    TempValue;\r
+\r
+  TempStr         = TempBuffer;\r
+  BufferPtr       = Buffer;\r
+  Count           = 0;\r
+  ValueCharNum    = 0;\r
+  ValueIsNegative = FALSE;\r
+\r
+  if (Width > CHARACTER_NUMBER_FOR_VALUE - 1) {\r
+    Width = CHARACTER_NUMBER_FOR_VALUE - 1;\r
+  }\r
+\r
+  if (Value < 0) {\r
+    Value           = -Value;\r
+    ValueIsNegative = TRUE;\r
+  }\r
+\r
+  do {\r
+    TempValue = Value;\r
+    Value = (INT64)DivU64x32 ((UINT64)Value, 10);\r
+    Remainder = (UINTN)((UINT64)TempValue - 10 * Value);\r
+    *(TempStr++) = (CHAR16)(Remainder + '0');\r
+    ValueCharNum++;\r
+    Count++;\r
+    if ((Flags & COMMA_TYPE) == COMMA_TYPE) {\r
+      if (ValueCharNum % 3 == 0 && Value != 0) {\r
+        *(TempStr++) = ',';\r
+        Count++;\r
+      }\r
+    }\r
+  } while (Value != 0);\r
+\r
+  if (ValueIsNegative) {\r
+    *(TempStr++)    = '-';\r
+    Count++;\r
+  }\r
+\r
+  if ((Flags & PREFIX_ZERO) && !ValueIsNegative) {\r
+    Prefix = '0';\r
+  } else {\r
+    Prefix = ' ';\r
+  }\r
+\r
+  Index = Count;\r
+  if (!(Flags & LEFT_JUSTIFY)) {\r
+    for (; Index < Width; Index++) {\r
+      *(TempStr++) = Prefix;\r
+    }\r
+  }\r
+\r
+  //\r
+  // Reverse temp string into Buffer.\r
+  //\r
+  if (Width > 0 && (UINTN) (TempStr - TempBuffer) > Width) {\r
+    TempStr = TempBuffer + Width;\r
+  }\r
+  Index = 0;\r
+  while (TempStr != TempBuffer) {\r
+    *(BufferPtr++) = *(--TempStr);\r
+    Index++;\r
+  }\r
+\r
+  *BufferPtr = 0;\r
+  return Index;\r
+}\r
+\r
+static CHAR16 mHexStr[] = { L'0', L'1', L'2', L'3', L'4', L'5', L'6', L'7',\r
+                            L'8', L'9', L'A', L'B', L'C', L'D', L'E', L'F' };\r
+\r
+/**\r
+  VSPrint worker function that prints a Value as a hex number in Buffer\r
+\r
+  @param  Buffer  Location to place ascii hex string of Value.\r
+  @param  Value   Hex value to convert to a string in Buffer.\r
+  @param  Flags   Flags to use in printing Hex string, see file header for details.\r
+  @param  Width   Width of hex value.\r
+\r
+  @retval         Number of characters printed.\r
+\r
+**/\r
+UINTN\r
+EfiValueToHexStr (\r
+  IN  OUT CHAR16  *Buffer,\r
+  IN  UINT64      Value,\r
+  IN  UINTN       Flags,\r
+  IN  UINTN       Width\r
+  )\r
+{\r
+  CHAR16  TempBuffer[CHARACTER_NUMBER_FOR_VALUE];\r
+  CHAR16  *TempStr;\r
+  CHAR16  Prefix;\r
+  CHAR16  *BufferPtr;\r
+  UINTN   Count;\r
+  UINTN   Index;\r
+\r
+  TempStr   = TempBuffer;\r
+  BufferPtr = Buffer;\r
+\r
+  //\r
+  // Count starts at one since we will null terminate. Each iteration of the\r
+  // loop picks off one nibble. Oh yea TempStr ends up backwards\r
+  //\r
+  Count = 0;\r
+\r
+  if (Width > CHARACTER_NUMBER_FOR_VALUE - 1) {\r
+    Width = CHARACTER_NUMBER_FOR_VALUE - 1;\r
+  }\r
+\r
+  do {\r
+    Index = ((UINTN)Value & 0xf);\r
+    *(TempStr++) = mHexStr[Index];\r
+    Value = RShiftU64 (Value, 4);\r
+    Count++;\r
+  } while (Value != 0);\r
+\r
+  if (Flags & PREFIX_ZERO) {\r
+    Prefix = '0';\r
+  } else {\r
+    Prefix = ' ';\r
+  }\r
+\r
+  Index = Count;\r
+  if (!(Flags & LEFT_JUSTIFY)) {\r
+    for (; Index < Width; Index++) {\r
+      *(TempStr++) = Prefix;\r
+    }\r
+  }\r
+\r
+  //\r
+  // Reverse temp string into Buffer.\r
+  //\r
+  if (Width > 0 && (UINTN) (TempStr - TempBuffer) > Width) {\r
+    TempStr = TempBuffer + Width;\r
+  }\r
+  Index = 0;\r
+  while (TempStr != TempBuffer) {\r
+    *(BufferPtr++) = *(--TempStr);\r
+    Index++;\r
+  }\r
+\r
+  *BufferPtr = 0;\r
+  return Index;\r
+}\r
+\r
+/*++\r
+  Converts MAC address to Unicode string.\r
+  The value is 64-bit and the resulting string will be 12\r
+  digit hex number in pairs of digits separated by dashes.\r
+\r
+  @param  String    string that will contain the value\r
+  @param  MacAddr   add argument and description to function comment\r
+  @param  AddrSize  add argument and description to function comment\r
+\r
+**/\r
+CHAR16 *\r
+StrMacToString (\r
+  OUT CHAR16              *String,\r
+  IN  EFI_MAC_ADDRESS     *MacAddr,\r
+  IN  UINT32              AddrSize\r
+  )\r
+{\r
+  UINT32  i;\r
+\r
+  for (i = 0; i < AddrSize; i++) {\r
+\r
+    EfiValueToHexStr (\r
+      &String[2 * i],\r
+      MacAddr->Addr[i] & 0xFF,\r
+      PREFIX_ZERO,\r
+      2\r
+      );\r
+  }\r
+\r
+  //\r
+  // Terminate the string.\r
+  //\r
+  String[2 * AddrSize] = L'\0';\r
+\r
+  return String;\r
+}\r
+\r
+VOID UpdateLatestBootTime() {\r
+  UINTN                         VarSize;\r
+  EFI_STATUS                   Status;\r
+  UINT64                       TimeValue;\r
+  CHAR16                       Buffer[40];\r
+  if (mSystemConfiguration.LogBootTime != 1) {\r
+    return;\r
+  }\r
+  VarSize = sizeof(TimeValue);\r
+  Status = gRT->GetVariable(\r
+                  BOOT_TIME_NAME,\r
+                  &gEfiNormalSetupGuid,\r
+                  NULL,\r
+                  &VarSize,\r
+                  &TimeValue\r
+                                         );\r
+  if (EFI_ERROR(Status)) {\r
+    return;\r
+  }\r
+  UnicodeSPrint (Buffer, sizeof (Buffer), L"%d ms", (UINT32)TimeValue);\r
+  HiiSetString(mHiiHandle,STRING_TOKEN(STR_LOG_BOOT_TIME_VALUE), Buffer, NULL);\r
+}\r
+\r
+/**\r
+  Get Cache Type for the specified Cache. This function is invoked when there is data records\r
+  available in the Data Hub.\r
+\r
+  Get Cache Type function arguments:\r
+\r
+  @param  Instance        The instance number of the subclass with the same ProducerName..\r
+  @param  SubInstance     The instance number of the RecordType for the same Instance.\r
+  @param  CacheType       Cache type, see definition of EFI_CACHE_TYPE_DATA.\r
+\r
+  @retval EFI_STATUS\r
+\r
+**/\r
+EFI_STATUS\r
+GetCacheType(\r
+  IN  UINT16                            Instance,\r
+  IN  UINT16                            SubInstance,\r
+  IN  EFI_CACHE_TYPE_DATA*              CacheType)\r
+{\r
+  EFI_STATUS                  Status;\r
+  EFI_DATA_HUB_PROTOCOL       *DataHub;\r
+  EFI_DATA_RECORD_HEADER      *Record;\r
+  UINT64                      MonotonicCount;\r
+  EFI_CACHE_VARIABLE_RECORD*  CacheVariableRecord;\r
+  EFI_SUBCLASS_TYPE1_HEADER   *DataHeader;\r
+\r
+  Status = gBS->LocateProtocol (\r
+                  &gEfiDataHubProtocolGuid,\r
+                  NULL,\r
+                  (void **)&DataHub\r
+                  );\r
+  ASSERT_EFI_ERROR(Status);\r
+\r
+  //\r
+  // Get all available data records from data hub\r
+  //\r
+  MonotonicCount = 0;\r
+  Record = NULL;\r
+\r
+  do {\r
+    Status = DataHub->GetNextRecord (\r
+                           DataHub,\r
+                                               &MonotonicCount,\r
+                                               NULL,\r
+                                               &Record\r
+                                               );\r
+    if (!EFI_ERROR(Status)) {\r
+      if (Record->DataRecordClass == EFI_DATA_RECORD_CLASS_DATA) {\r
+        DataHeader  = (EFI_SUBCLASS_TYPE1_HEADER *)(Record + 1);\r
+\r
+        if(CompareGuid(&Record->DataRecordGuid, &gEfiCacheSubClassGuid) &&\r
+          (DataHeader->RecordType == CacheTypeRecordType) &&\r
+          (DataHeader->Instance == Instance) &&\r
+          (DataHeader->SubInstance == SubInstance)) {\r
+          CacheVariableRecord     = (EFI_CACHE_VARIABLE_RECORD  *)(DataHeader + 1);\r
+          if(CacheType){\r
+            *CacheType = CacheVariableRecord->CacheType;\r
+            return EFI_SUCCESS;\r
+          }\r
+        }\r
+      }\r
+    }\r
+  } while(!EFI_ERROR(Status) && (MonotonicCount != 0));\r
+\r
+  return EFI_NOT_FOUND;\r
+}\r
+\r
+/**\r
+  Setup data filter function. This function is invoked when there is data records\r
+  available in the Data Hub.\r
+\r
+\r
+  Standard event notification function arguments:\r
+  @param Event          The event that is signaled.\r
+  @param Context        Not used here.\r
+\r
+  @retval EFI_STATUS\r
+\r
+**/\r
+VOID\r
+PrepareSetupInformation (\r
+  )\r
+{\r
+\r
+  EFI_STATUS                  Status;\r
+  EFI_DATA_HUB_PROTOCOL       *DataHub;\r
+  EFI_DATA_RECORD_HEADER      *Record;\r
+  UINT8                       *SrcData;\r
+  UINT32                      SrcDataSize;\r
+  EFI_SUBCLASS_TYPE1_HEADER   *DataHeader;\r
+  CHAR16                      *NewString;\r
+  CHAR16                      *NewString2;\r
+  CHAR16                      *NewStringToken;\r
+  STRING_REF                  TokenToUpdate;\r
+  EFI_PROCESSOR_VERSION_DATA  *ProcessorVersion;\r
+  UINTN                       Index;\r
+  UINT16                      EeState;\r
+  UINTN                       DataOutput;\r
+\r
+  EFI_PROCESSOR_MICROCODE_REVISION_DATA   *CpuUcodeRevisionData;\r
+  EFI_MEMORY_ARRAY_START_ADDRESS          *MemoryArray;\r
+  EFI_MEMORY_ARRAY_LINK                   *MemoryArrayLink;\r
+  UINT64                      MonotonicCount;\r
+\r
+  CHAR16                      Version[100];         //Assuming that strings are < 100 UCHAR\r
+  CHAR16                      ReleaseDate[100];     //Assuming that strings are < 100 UCHAR\r
+  CHAR16                      ReleaseTime[100];     //Assuming that strings are < 100 UCHAR\r
+\r
+  NewString = AllocateZeroPool (0x100);\r
+  NewString2 = AllocateZeroPool (0x100);\r
+  SetMem(Version, sizeof(Version), 0);\r
+  SetMem(ReleaseDate, sizeof(ReleaseDate), 0);\r
+  SetMem(ReleaseTime, sizeof(ReleaseTime), 0);\r
+\r
+  //\r
+  // Initialize EE state for not to show EE related setup options\r
+  //\r
+  EeState = 0;\r
+\r
+  //\r
+  // Get the Data Hub Protocol. Assume only one instance\r
+  //\r
+  Status = gBS->LocateProtocol (&gEfiDataHubProtocolGuid, NULL, (void **)&DataHub);\r
+  ASSERT_EFI_ERROR(Status);\r
+\r
+  //\r
+  // Get all available data records from data hub\r
+  //\r
+  MonotonicCount = 0;\r
+  Record = NULL;\r
+\r
+  do {\r
+    Status = DataHub->GetNextRecord (DataHub, &MonotonicCount, NULL, &Record);\r
+    if (!EFI_ERROR(Status)) {\r
+      if (Record->DataRecordClass == EFI_DATA_RECORD_CLASS_DATA) {\r
+        DataHeader  = (EFI_SUBCLASS_TYPE1_HEADER *)(Record + 1);\r
+        SrcData     = (UINT8  *)(DataHeader + 1);\r
+        SrcDataSize = Record->RecordSize - Record->HeaderSize - sizeof (EFI_SUBCLASS_TYPE1_HEADER);\r
+\r
+        //\r
+        // Processor\r
+        //\r
+        if (CompareGuid(&Record->DataRecordGuid, &gEfiProcessorSubClassGuid)) {\r
+          CopyMem (&mProcessorProducerGuid, &Record->ProducerName, sizeof(EFI_GUID));\r
+          switch (DataHeader->RecordType) {\r
+            case ProcessorCoreFrequencyRecordType:\r
+              CopyMem(&mProcessorFrequency, SrcData, sizeof(EFI_EXP_BASE10_DATA));\r
+              Index = EfiValueToString (\r
+                                   NewString,\r
+                                               ConvertBase10ToRaw ((EFI_EXP_BASE10_DATA *)SrcData)/1000000000,\r
+                                               PREFIX_ZERO,\r
+                                               0\r
+                                               );\r
+              StrCat (NewString, L".");\r
+              EfiValueToString (\r
+                           NewString + Index + 1,\r
+                               ((ConvertBase10ToRaw ((EFI_EXP_BASE10_DATA *)SrcData)%1000000000)/10000000),\r
+                               PREFIX_ZERO,\r
+                               0\r
+                               );\r
+              StrCat (NewString, L" GHz");\r
+              TokenToUpdate = (STRING_REF)STR_PROCESSOR_SPEED_VALUE;\r
+              HiiSetString(mHiiHandle, TokenToUpdate, NewString, NULL);\r
+              break;\r
+\r
+            case ProcessorVersionRecordType:\r
+              ProcessorVersion = (EFI_PROCESSOR_VERSION_DATA *)SrcData;\r
+              NewStringToken = HiiGetPackageString(&mProcessorProducerGuid, *ProcessorVersion, NULL);\r
+              TokenToUpdate = (STRING_REF)STR_PROCESSOR_VERSION_VALUE;\r
+              HiiSetString(mHiiHandle, TokenToUpdate, NewStringToken, NULL);\r
+              break;\r
+            case CpuUcodeRevisionDataRecordType:\r
+              CpuUcodeRevisionData = (EFI_PROCESSOR_MICROCODE_REVISION_DATA *) SrcData;\r
+              if (CpuUcodeRevisionData->ProcessorMicrocodeRevisionNumber != 0) {\r
+                EfiValueToHexStr (\r
+                                 NewString,\r
+                  CpuUcodeRevisionData->ProcessorMicrocodeRevisionNumber,\r
+                  PREFIX_ZERO,\r
+                  8\r
+                                 );\r
+                TokenToUpdate = (STRING_REF)STR_PROCESSOR_MICROCODE_VALUE;\r
+                HiiSetString(mHiiHandle, TokenToUpdate, NewString, NULL);\r
+              }\r
+              break;\r
+            default:\r
+              break;\r
+          }\r
+\r
+        //\r
+        // Cache\r
+        //\r
+        } else if (CompareGuid(&Record->DataRecordGuid, &gEfiCacheSubClassGuid) &&\r
+                   (DataHeader->RecordType == CacheSizeRecordType)) {\r
+          if (DataHeader->SubInstance == EFI_CACHE_L1) {\r
+            EFI_CACHE_TYPE_DATA              CacheType;\r
+            if (EFI_SUCCESS == GetCacheType(DataHeader->Instance, DataHeader->SubInstance,&CacheType)){\r
+              if (CacheType == EfiCacheTypeData) {\r
+                TokenToUpdate = (STRING_REF)STR_PROCESSOR_L1_DATA_CACHE_VALUE;\r
+              } else if (CacheType == EfiCacheTypeInstruction) {\r
+                  TokenToUpdate = (STRING_REF)STR_PROCESSOR_L1_INSTR_CACHE_VALUE;\r
+              } else {\r
+                continue;\r
+              }\r
+            } else {\r
+              continue;\r
+            }\r
+          }\r
+          else if (DataHeader->SubInstance == EFI_CACHE_L2) {\r
+            TokenToUpdate = (STRING_REF)STR_PROCESSOR_L2_CACHE_VALUE;\r
+          } else {\r
+            continue;\r
+          }\r
+          if (ConvertBase2ToRaw((EFI_EXP_BASE2_DATA *)SrcData)) {\r
+            DataOutput = ConvertBase2ToRaw((EFI_EXP_BASE2_DATA *)SrcData) >> 10;\r
+            EfiValueToString (NewString, DataOutput, PREFIX_ZERO, 0);\r
+\r
+            StrCat (NewString, L" KB");\r
+            if (DataHeader->SubInstance == EFI_CACHE_L3) {\r
+              HiiSetString(mHiiHandle, TokenToUpdate, NewString, NULL);\r
+            } else if(DataHeader->SubInstance == EFI_CACHE_L2 && mPlatformCpuInfo.CpuPackage.CoresPerPhysicalPackage > 1){\r
+                         //\r
+              // Show XxL2 string\r
+                         //\r
+              EfiValueToString (\r
+                           NewString2,\r
+                mPlatformCpuInfo.CpuPackage.CoresPerPhysicalPackage,\r
+                PREFIX_ZERO,\r
+                0\r
+                               );\r
+              StrCat(NewString2, L"x ");\r
+              StrCat(NewString2, NewString);\r
+              HiiSetString(mHiiHandle, TokenToUpdate, NewString2, NULL);\r
+            } else {\r
+              HiiSetString(mHiiHandle, TokenToUpdate, NewString, NULL);\r
+            }\r
+          }\r
+\r
+        //\r
+        // Memory\r
+        //\r
+        } else if (CompareGuid(&Record->DataRecordGuid, &gEfiMemorySubClassGuid)) {\r
+          switch (DataHeader->RecordType) {\r
+            case EFI_MEMORY_ARRAY_LINK_RECORD_NUMBER:\r
+              MemoryArrayLink = (EFI_MEMORY_ARRAY_LINK *)SrcData;\r
+\r
+              if (MemoryArrayLink->MemorySpeed > 0) {\r
+                //\r
+                // Save the lowest speed memory module\r
+                //\r
+                if (MemoryArrayLink->MemorySpeed < mMemorySpeed) {\r
+                  mMemorySpeed = MemoryArrayLink->MemorySpeed;\r
+                }\r
+                switch (DataHeader->SubInstance) {\r
+                  case 1:\r
+                    mMemorySpeedChannelASlot0 = MemoryArrayLink->MemorySpeed;\r
+                    mMemorySizeChannelASlot0 = MemoryArrayLink->MemoryDeviceSize;\r
+                    break;\r
+                  case 2:\r
+                    mMemorySpeedChannelASlot1 = MemoryArrayLink->MemorySpeed;\r
+                    mMemorySizeChannelASlot1 = MemoryArrayLink->MemoryDeviceSize;\r
+                    break;\r
+                  case 3:\r
+                    mMemorySpeedChannelBSlot0 = MemoryArrayLink->MemorySpeed;\r
+                    mMemorySizeChannelBSlot0 = MemoryArrayLink->MemoryDeviceSize;\r
+                    break;\r
+                  case 4:\r
+                    mMemorySpeedChannelBSlot1 = MemoryArrayLink->MemorySpeed;\r
+                    mMemorySizeChannelBSlot1 = MemoryArrayLink->MemoryDeviceSize;\r
+                    break;\r
+                  case 5:\r
+                    mMemorySpeedChannelCSlot0 = MemoryArrayLink->MemorySpeed;\r
+                    mMemorySizeChannelCSlot0 = MemoryArrayLink->MemoryDeviceSize;\r
+                    break;\r
+                  case 6:\r
+                    mMemorySpeedChannelCSlot1 = MemoryArrayLink->MemorySpeed;\r
+                    mMemorySizeChannelCSlot1 = MemoryArrayLink->MemoryDeviceSize;\r
+                    break;\r
+                  default:\r
+                    break;\r
+                  }\r
+              }\r
+              break;\r
+\r
+            case EFI_MEMORY_ARRAY_START_ADDRESS_RECORD_NUMBER:\r
+              MemoryArray = (EFI_MEMORY_ARRAY_START_ADDRESS *)SrcData;\r
+              if (MemoryArray->MemoryArrayEndAddress - MemoryArray->MemoryArrayStartAddress) {\r
+               DataOutput = (UINTN)RShiftU64((MemoryArray->MemoryArrayEndAddress - MemoryArray->MemoryArrayStartAddress + 1), 20);\r
+               EfiValueToString (NewString, DataOutput / 1024, PREFIX_ZERO, 0);\r
+               if(DataOutput % 1024) {\r
+                 StrCat (NewString, L".");\r
+                 DataOutput = ((DataOutput % 1024) * 1000) / 1024;\r
+                 while(!(DataOutput % 10))\r
+                   DataOutput = DataOutput / 10;\r
+                  EfiValueToString (NewString2, DataOutput, PREFIX_ZERO, 0);\r
+                  StrCat (NewString, NewString2);\r
+                }\r
+                StrCat (NewString, L" GB");\r
+                TokenToUpdate = (STRING_REF)STR_TOTAL_MEMORY_SIZE_VALUE;\r
+                HiiSetString(mHiiHandle, TokenToUpdate, NewString, NULL);\r
+              }\r
+              break;\r
+\r
+            default:\r
+              break;\r
+          }\r
+        }\r
+      }\r
+    }\r
+  } while (!EFI_ERROR(Status) && (MonotonicCount != 0));\r
+\r
+  Status = GetBiosVersionDateTime (\r
+             Version,\r
+                        ReleaseDate,\r
+                        ReleaseTime\r
+                        );\r
+\r
+  DEBUG ((EFI_D_ERROR, "GetBiosVersionDateTime :%s %s %s \n", Version, ReleaseDate, ReleaseTime));\r
+  if (!EFI_ERROR (Status)) {\r
+    UINTN         Length = 0;\r
+    CHAR16        *BuildDateTime;\r
+\r
+    Length = StrLen(ReleaseDate) + StrLen(ReleaseTime);\r
+\r
+    BuildDateTime = AllocateZeroPool ((Length+2) * sizeof(CHAR16));\r
+    StrCpy (BuildDateTime, ReleaseDate);\r
+    StrCat (BuildDateTime, L" ");\r
+    StrCat (BuildDateTime, ReleaseTime);\r
+\r
+    TokenToUpdate = (STRING_REF)STR_BIOS_VERSION_VALUE;\r
+    DEBUG ((EFI_D_ERROR, "update STR_BIOS_VERSION_VALUE\n"));\r
+    HiiSetString(mHiiHandle, TokenToUpdate, Version, NULL);\r
+\r
+    TokenToUpdate = (STRING_REF)STR_BIOS_BUILD_TIME_VALUE;\r
+    DEBUG ((EFI_D_ERROR, "update STR_BIOS_BUILD_TIME_VALUE\n"));\r
+    HiiSetString(mHiiHandle, TokenToUpdate, BuildDateTime, NULL);\r
+  }\r
+\r
+  //\r
+  // Calculate and update memory speed display in Main Page\r
+  //\r
+  //\r
+  // Update the overall memory speed\r
+  //\r
+  if (mMemorySpeed != 0xffff) {\r
+    EfiValueToString (NewString, mMemorySpeed, PREFIX_ZERO, 0);\r
+    StrCat (NewString, L" MHz");\r
+\r
+    TokenToUpdate = (STRING_REF)STR_SYSTEM_MEMORY_SPEED_VALUE;\r
+    HiiSetString(mHiiHandle, TokenToUpdate, NewString, NULL);\r
+  }\r
+\r
+  gBS->FreePool(NewString);\r
+  gBS->FreePool(NewString2);\r
+\r
+  return;\r
+}\r
+\r
+/**\r
+\r
+  Routine Description: update the SETUP info for "Additional Information" which is SMBIOS info.\r
+\r
+  @retval EFI_STATUS\r
+\r
+**/\r
+EFI_STATUS\r
+UpdateAdditionalInformation (\r
+  )\r
+{\r
+  EFI_STATUS                      Status;\r
+  UINT64                          MonotonicCount;\r
+  EFI_DATA_HUB_PROTOCOL           *DataHub;\r
+  EFI_DATA_RECORD_HEADER          *Record;\r
+  EFI_SUBCLASS_TYPE1_HEADER       *DataHeader;\r
+  EFI_MISC_SYSTEM_MANUFACTURER    *SystemManufacturer;\r
+  UINTN                           Size;\r
+  EFI_SMBIOS_PROTOCOL             *Smbios;\r
+  EFI_SMBIOS_HANDLE               SmbiosHandle;\r
+  EFI_SMBIOS_TABLE_HEADER         *SmbiosRecord;\r
+  SMBIOS_TABLE_TYPE0              *Type0Record;\r
+  UINT8                           StrIndex;\r
+  CHAR16                          *BiosVersion = NULL;\r
+  CHAR16                          *IfwiVersion = NULL;\r
+  UINT16                          SearchIndex;\r
+  EFI_STRING_ID                   TokenToUpdate;\r
+\r
+  Status = gBS->LocateProtocol (\r
+                  &gEfiDataHubProtocolGuid,\r
+                  NULL,\r
+                  (void **)&DataHub\r
+                  );\r
+\r
+  ASSERT_EFI_ERROR(Status);\r
+\r
+  Size = 3;\r
+\r
+  MonotonicCount  = 0;\r
+  Record = NULL;\r
+  do {\r
+    Status = DataHub->GetNextRecord (\r
+                        DataHub,\r
+                        &MonotonicCount,\r
+                        NULL,\r
+                        &Record\r
+                        );\r
+    if (Record->DataRecordClass == EFI_DATA_RECORD_CLASS_DATA) {\r
+      DataHeader  = (EFI_SUBCLASS_TYPE1_HEADER *)(Record + 1);\r
+\r
+      if (CompareGuid(&Record->DataRecordGuid, &gEfiMiscSubClassGuid) &&\r
+          (DataHeader->RecordType == EFI_MISC_SYSTEM_MANUFACTURER_RECORD_NUMBER)) {\r
+        //\r
+        // System Information\r
+        //\r
+        SystemManufacturer = (EFI_MISC_SYSTEM_MANUFACTURER *)(DataHeader + 1);\r
+\r
+#if defined( RVP_SUPPORT ) && RVP_SUPPORT\r
+        //\r
+        // UUID  (System Information)\r
+        //\r
+        SMBIOSString = EfiLibAllocateZeroPool (0x100);\r
+        GuidToString ( &SystemManufacturer->SystemUuid, SMBIOSString, 0x00 );\r
+\r
+        TokenToUpdate = (STRING_REF)STR_SYSTEM_UUID_VALUE;\r
+        HiiSetString(mHiiHandle, TokenToUpdate, SMBIOSString, NULL);\r
+\r
+        gBS->FreePool(SMBIOSString);\r
+#endif\r
+      }\r
+    }\r
+  } while (!EFI_ERROR(Status) && (MonotonicCount != 0));\r
+\r
+  Status = gBS->LocateProtocol (\r
+                  &gEfiSmbiosProtocolGuid,\r
+                  NULL,\r
+                  (VOID **) &Smbios\r
+                  );\r
+  ASSERT_EFI_ERROR (Status);\r
+\r
+  SmbiosHandle = SMBIOS_HANDLE_PI_RESERVED;\r
+  do {\r
+    Status = Smbios->GetNext (\r
+                       Smbios,\r
+                       &SmbiosHandle,\r
+                       NULL,\r
+                       &SmbiosRecord,\r
+                       NULL\r
+                       );\r
+    if (SmbiosRecord->Type == EFI_SMBIOS_TYPE_BIOS_INFORMATION) {\r
+      Type0Record = (SMBIOS_TABLE_TYPE0 *) SmbiosRecord;\r
+      StrIndex = Type0Record->BiosVersion;\r
+      GetOptionalStringByIndex ((CHAR8*)((UINT8*)Type0Record + Type0Record->Hdr.Length), StrIndex, &BiosVersion);\r
+      TokenToUpdate = STRING_TOKEN (STR_BIOS_VERSION_VALUE);\r
+      for (SearchIndex = 0x0; SearchIndex < SMBIOS_STRING_MAX_LENGTH; SearchIndex++) {\r
+        if (BiosVersion[SearchIndex] == 0x0020) {\r
+          BiosVersion[SearchIndex] = 0x0000;\r
+          IfwiVersion = (CHAR16 *)(&BiosVersion[SearchIndex+1]);\r
+          break;\r
+        } else if (BiosVersion[SearchIndex] == 0x0000) {\r
+          break;\r
+        }\r
+      }\r
+      HiiSetString (mHiiHandle, TokenToUpdate, BiosVersion, NULL);\r
+\r
+      //\r
+      // Check IfwiVersion, to avoid no IFWI version in SMBIOS Type 0 strucntion\r
+      //\r
+      if(IfwiVersion) {\r
+        TokenToUpdate = STRING_TOKEN (STR_IFWI_VERSION_VALUE);\r
+        HiiSetString (mHiiHandle, TokenToUpdate, IfwiVersion, NULL);\r
+      }\r
+    }\r
+  } while (!EFI_ERROR(Status));\r
+\r
+  UpdateLatestBootTime();\r
+\r
+  return  EFI_SUCCESS;\r
+}\r
+\r
+VOID\r
+UpdateCPUInformation ()\r
+{\r
+  CHAR16                                                               Buffer[40];\r
+  UINT16                                FamilyId;\r
+  UINT8                                 Model;\r
+  UINT8                                 SteppingId;\r
+  UINT8                                 ProcessorType;\r
+  EFI_STATUS                            Status;\r
+  EFI_MP_SERVICES_PROTOCOL              *MpService;\r
+  UINTN                                 MaximumNumberOfCPUs;\r
+  UINTN                                 NumberOfEnabledCPUs;\r
+  UINT32                                                               Buffer32 = 0xFFFFFFFF;   // Keep buffer with unknown device\r
+\r
+  EfiCpuVersion (&FamilyId, &Model, &SteppingId, &ProcessorType);\r
+\r
+  //\r
+  //we need raw Model data\r
+  //\r
+  Model = Model & 0xf;\r
+\r
+  //\r
+  //Family/Model/Step\r
+  //\r
+  UnicodeSPrint (Buffer, sizeof (Buffer), L"%d/%d/%d", FamilyId,  Model, SteppingId);\r
+  HiiSetString(mHiiHandle,STRING_TOKEN(STR_PROCESSOR_ID_VALUE), Buffer, NULL);\r
+\r
+  Status = gBS->LocateProtocol (\r
+                  &gEfiMpServiceProtocolGuid,\r
+                  NULL,\r
+                  (void **)&MpService\r
+                  );\r
+  if (!EFI_ERROR (Status)) {\r
+    //\r
+    // Determine the number of processors\r
+    //\r
+    MpService->GetNumberOfProcessors (\r
+                 MpService,\r
+                 &MaximumNumberOfCPUs,\r
+                 &NumberOfEnabledCPUs\r
+                 );\r
+    UnicodeSPrint (Buffer, sizeof (Buffer), L"%d", MaximumNumberOfCPUs);\r
+    HiiSetString(mHiiHandle,STRING_TOKEN(STR_PROCESSOR_CORE_VALUE), Buffer, NULL);\r
+  }\r
+  //\r
+  // Update Mobile / Desktop / Tablet SKU\r
+  //\r
+  Buffer32 =(UINT32) RShiftU64 (EfiReadMsr (MSR_IA32_PLATFORM_ID), 50) & 0x07;\r
+\r
+  switch(Buffer32){\r
+      case 0x0:\r
+        UnicodeSPrint (Buffer, sizeof (Buffer), L"(%d) - ISG SKU SOC", Buffer32);\r
+        break;\r
+      case 0x01:\r
+        UnicodeSPrint (Buffer, sizeof (Buffer), L"(%d) - Mobile SKU SOC", Buffer32);\r
+        break;\r
+      case 0x02:\r
+        UnicodeSPrint (Buffer, sizeof (Buffer), L"(%d) - Desktop SKU SOC", Buffer32);\r
+        break;\r
+      case 0x03:\r
+        UnicodeSPrint (Buffer, sizeof (Buffer), L"(%d) - Mobile SKU SOC", Buffer32);\r
+        break;\r
+      default:\r
+        UnicodeSPrint (Buffer, sizeof (Buffer), L"(%d) - Unknown SKU SOC", Buffer32);\r
+        break;\r
+    }\r
+  HiiSetString(mHiiHandle,STRING_TOKEN(STR_PROCESSOR_SKU_VALUE), Buffer, NULL);\r
+\r
+}\r
+\r
+\r
+EFI_STATUS\r
+SearchChildHandle(\r
+  EFI_HANDLE Father,\r
+  EFI_HANDLE *Child\r
+  )\r
+{\r
+  EFI_STATUS                                                 Status;\r
+  UINTN                                                          HandleIndex;\r
+  EFI_GUID                                                     **ProtocolGuidArray = NULL;\r
+  UINTN                                                          ArrayCount;\r
+  UINTN                                                          ProtocolIndex;\r
+  UINTN                                                          OpenInfoCount;\r
+  UINTN                                                          OpenInfoIndex;\r
+  EFI_OPEN_PROTOCOL_INFORMATION_ENTRY  *OpenInfo = NULL;\r
+  UINTN                                                          mHandleCount;\r
+  EFI_HANDLE                                                 *mHandleBuffer= NULL;\r
+\r
+  //\r
+  // Retrieve the list of all handles from the handle database\r
+  //\r
+  Status = gBS->LocateHandleBuffer (\r
+                  AllHandles,\r
+                  NULL,\r
+                  NULL,\r
+                  &mHandleCount,\r
+                  &mHandleBuffer\r
+                  );\r
+\r
+  for (HandleIndex = 0; HandleIndex < mHandleCount; HandleIndex++)\r
+  {\r
+    //\r
+    // Retrieve the list of all the protocols on each handle\r
+    //\r
+    Status = gBS->ProtocolsPerHandle (\r
+                    mHandleBuffer[HandleIndex],\r
+                    &ProtocolGuidArray,\r
+                    &ArrayCount\r
+                    );\r
+    if (!EFI_ERROR (Status))\r
+    {\r
+      for (ProtocolIndex = 0; ProtocolIndex < ArrayCount; ProtocolIndex++)\r
+      {\r
+        Status = gBS->OpenProtocolInformation (\r
+                        mHandleBuffer[HandleIndex],\r
+                        ProtocolGuidArray[ProtocolIndex],\r
+                        &OpenInfo,\r
+                        &OpenInfoCount\r
+                        );\r
+        if (!EFI_ERROR (Status))\r
+        {\r
+          for (OpenInfoIndex = 0; OpenInfoIndex < OpenInfoCount; OpenInfoIndex++)\r
+          {\r
+            if(OpenInfo[OpenInfoIndex].AgentHandle == Father)\r
+            {\r
+              if ((OpenInfo[OpenInfoIndex].Attributes & EFI_OPEN_PROTOCOL_BY_CHILD_CONTROLLER) == EFI_OPEN_PROTOCOL_BY_CHILD_CONTROLLER)\r
+              {\r
+                *Child = mHandleBuffer[HandleIndex];\r
+                 Status = EFI_SUCCESS;\r
+                 goto TryReturn;\r
+              }\r
+            }\r
+          }\r
+          Status = EFI_NOT_FOUND;\r
+        }\r
+      }\r
+      if(OpenInfo != NULL)\r
+      {\r
+        FreePool(OpenInfo);\r
+        OpenInfo = NULL;\r
+      }\r
+    }\r
+    FreePool (ProtocolGuidArray);\r
+    ProtocolGuidArray = NULL;\r
+  }\r
+TryReturn:\r
+  if(OpenInfo != NULL)\r
+  {\r
+    FreePool (OpenInfo);\r
+    OpenInfo = NULL;\r
+  }\r
+  if(ProtocolGuidArray != NULL)\r
+  {\r
+    FreePool(ProtocolGuidArray);\r
+    ProtocolGuidArray = NULL;\r
+  }\r
+  if(mHandleBuffer != NULL)\r
+  {\r
+    FreePool (mHandleBuffer);\r
+    mHandleBuffer = NULL;\r
+  }\r
+  return Status;\r
+}\r
+\r
+EFI_STATUS\r
+JudgeHandleIsPCIDevice(\r
+  EFI_HANDLE    Handle,\r
+  UINT8            Device,\r
+  UINT8            Funs\r
+  )\r
+{\r
+  EFI_STATUS  Status;\r
+  EFI_DEVICE_PATH   *DPath;\r
+  EFI_DEVICE_PATH   *DevicePath;\r
+\r
+  Status = gBS->HandleProtocol (\r
+                  Handle,\r
+                  &gEfiDevicePathProtocolGuid,\r
+                  (VOID **) &DPath\r
+                  );\r
+  if(!EFI_ERROR(Status))\r
+  {\r
+    DevicePath = DPath;\r
+    while(!IsDevicePathEnd(DPath))\r
+    {\r
+      if((DPath->Type == HARDWARE_DEVICE_PATH) && (DPath->SubType == HW_PCI_DP))\r
+      {\r
+        PCI_DEVICE_PATH   *PCIPath;\r
+\r
+        PCIPath = (PCI_DEVICE_PATH*) DPath;\r
+        DPath = NextDevicePathNode(DPath);\r
+        if(IsDevicePathEnd(DPath) && (PCIPath->Device == Device) && (PCIPath->Function == Funs))\r
+        {\r
+          return EFI_SUCCESS;\r
+        }\r
+      }\r
+      else\r
+      {\r
+        DPath = NextDevicePathNode(DPath);\r
+      }\r
+    }\r
+  }\r
+  return EFI_UNSUPPORTED;\r
+}\r
+\r
+EFI_STATUS\r
+GetDriverName(\r
+  EFI_HANDLE   Handle,\r
+  CHAR16         *Name\r
+  )\r
+{\r
+  EFI_DRIVER_BINDING_PROTOCOL        *BindHandle = NULL;\r
+  EFI_STATUS                                        Status;\r
+  UINT32                                               Version;\r
+  UINT16                                               *Ptr;\r
+  Status = gBS->OpenProtocol(\r
+                  Handle,\r
+                  &gEfiDriverBindingProtocolGuid,\r
+                  (VOID**)&BindHandle,\r
+                  NULL,\r
+                  NULL,\r
+                  EFI_OPEN_PROTOCOL_GET_PROTOCOL\r
+                  );\r
+\r
+  if (EFI_ERROR(Status))\r
+  {\r
+    return EFI_NOT_FOUND;\r
+  }\r
+\r
+  Version = BindHandle->Version;\r
+  Ptr = (UINT16*)&Version;\r
+  UnicodeSPrint(Name, 40, L"%d.%d.%d", Version >> 24 , (Version >>16)& 0x0f ,*(Ptr));\r
+\r
+  return EFI_SUCCESS;\r
+}\r
+\r
+EFI_STATUS\r
+GetGOPDriverName(\r
+  CHAR16 *Name\r
+  )\r
+{\r
+  UINTN                         HandleCount;\r
+  EFI_HANDLE                *Handles= NULL;\r
+  UINTN                         Index;\r
+  EFI_STATUS                Status;\r
+  EFI_HANDLE                Child = 0;\r
+\r
+  Status = gBS->LocateHandleBuffer(\r
+                             ByProtocol,\r
+                             &gEfiDriverBindingProtocolGuid,\r
+                             NULL,\r
+                             &HandleCount,\r
+                             &Handles\r
+                  );\r
+  for (Index = 0; Index < HandleCount ; Index++)\r
+  {\r
+    Status = SearchChildHandle(Handles[Index], &Child);\r
+    if(!EFI_ERROR(Status))\r
+    {\r
+      Status = JudgeHandleIsPCIDevice(\r
+                 Child,\r
+                 0x02,\r
+                 0x00\r
+                 );\r
+      if(!EFI_ERROR(Status))\r
+      {\r
+        return GetDriverName(Handles[Index], Name);\r
+      }\r
+    }\r
+  }\r
+  return EFI_UNSUPPORTED;\r
+}\r
+\r
+EFI_STATUS\r
+UpdatePlatformInformation (\r
+  )\r
+{\r
+  UINT32                   MicroCodeVersion;\r
+  CHAR16                   Buffer[40];\r
+  UINT8                    IgdVBIOSRevH;\r
+  UINT8                    IgdVBIOSRevL;\r
+  UINT16                   EDX;\r
+  EFI_IA32_REGISTER_SET    RegSet;\r
+  EFI_LEGACY_BIOS_PROTOCOL *LegacyBios = NULL;\r
+  EFI_STATUS               Status;\r
+  UINT8                    CpuFlavor=0;\r
+  EFI_PEI_HOB_POINTERS     GuidHob;\r
+  EFI_PLATFORM_INFO_HOB    *mPlatformInfo=NULL;\r
+  UINTN                    NumHandles;\r
+  EFI_HANDLE                        *HandleBuffer;\r
+  UINTN                             Index;\r
+  DXE_PCH_PLATFORM_POLICY_PROTOCOL  *PchPlatformPolicy;\r
+  UINTN                             PciD31F0RegBase;\r
+  UINT8                             count;\r
+  UINT8                             Data8;\r
+  UINT8                             PIDData8;\r
+\r
+  CHAR16                            Name[40];\r
+  UINT32                            MrcVersion;\r
+\r
+  //\r
+  // Get the HOB list.  If it is not present, then ASSERT.\r
+  //\r
+  GuidHob.Raw = GetHobList ();\r
+  if (GuidHob.Raw != NULL) {\r
+    if ((GuidHob.Raw = GetNextGuidHob (&gEfiPlatformInfoGuid, GuidHob.Raw)) != NULL) {\r
+      mPlatformInfo = GET_GUID_HOB_DATA (GuidHob.Guid);\r
+    }\r
+  }\r
+\r
+  //\r
+  //VBIOS version\r
+  //\r
+  Status = gBS->LocateProtocol(\r
+                  &gEfiLegacyBiosProtocolGuid,\r
+                  NULL,\r
+                  (void **)&LegacyBios\r
+                  );\r
+  if (!EFI_ERROR (Status)) {\r
+  RegSet.X.AX = 0x5f01;\r
+  Status = LegacyBios->Int86 (LegacyBios, 0x10, &RegSet);\r
+  ASSERT_EFI_ERROR(Status);\r
+\r
+  //\r
+  // simulate AMI int15 (ax=5f01) handler\r
+  // check NbInt15.asm in AMI code for asm edition\r
+  //\r
+  EDX = (UINT16)((RegSet.E.EBX >> 16) & 0xffff);\r
+  IgdVBIOSRevH = (UINT8)(((EDX & 0x0F00) >> 4) | (EDX & 0x000F));\r
+  IgdVBIOSRevL = (UINT8)(((RegSet.X.BX & 0x0F00) >> 4) | (RegSet.X.BX & 0x000F));\r
+\r
+  if (IgdVBIOSRevH==0 && IgdVBIOSRevL==0){\r
+    HiiSetString(mHiiHandle, STRING_TOKEN(STR_CHIP_IGD_VBIOS_REV_VALUE), L"N/A", NULL);\r
+  } else {\r
+    UnicodeSPrint (Buffer, sizeof (Buffer), L"%02X%02X", IgdVBIOSRevH,IgdVBIOSRevL);\r
+    HiiSetString(mHiiHandle, STRING_TOKEN(STR_CHIP_IGD_VBIOS_REV_VALUE), Buffer, NULL);\r
+    }\r
+  }\r
+\r
+  Status = GetGOPDriverName(Name);\r
+\r
+  if (!EFI_ERROR(Status))\r
+  {\r
+    HiiSetString(mHiiHandle, STRING_TOKEN(STR_GOP_VALUE), Name, NULL);\r
+  }\r
+\r
+\r
+  //\r
+  // CpuFlavor\r
+  // ISG-DC Tablet        000\r
+  // VLV-QC Tablet        001\r
+  // VLV-QC Desktop       010\r
+  // VLV-QC Notebook      011\r
+  //\r
+  CpuFlavor = RShiftU64 (EfiReadMsr (MSR_IA32_PLATFORM_ID), 50) & 0x07;\r
+\r
+  switch(CpuFlavor){\r
+    case 0x0:\r
+      UnicodeSPrint (Buffer, sizeof (Buffer), L"%s (%01x)", L"VLV-DC Tablet", CpuFlavor);\r
+      break;\r
+    case 0x01:\r
+      UnicodeSPrint (Buffer, sizeof (Buffer), L"%s (%01x)", L"VLV-QC Notebook", CpuFlavor);\r
+      break;\r
+    case 0x02:\r
+      UnicodeSPrint (Buffer, sizeof (Buffer), L"%s (%01x)", L"VLV-QC Desktop", CpuFlavor);\r
+      break;\r
+    case 0x03:\r
+      UnicodeSPrint (Buffer, sizeof (Buffer), L"%s (%01x)", L"VLV-QC Notebook", CpuFlavor);\r
+      break;\r
+    default:\r
+      UnicodeSPrint (Buffer, sizeof (Buffer), L"%s (%01x)", L"Unknown CPU", CpuFlavor);\r
+      break;\r
+  }\r
+  HiiSetString(mHiiHandle,STRING_TOKEN(STR_CPU_FLAVOR_VALUE), Buffer, NULL);\r
+\r
+  if ( NULL != mPlatformInfo) {\r
+    //\r
+    //BoardId\r
+    //\r
+    switch(mPlatformInfo->BoardId){\r
+      case 0x2:\r
+        UnicodeSPrint (Buffer, sizeof (Buffer), L"BAY LAKE RVP(%02x)", mPlatformInfo->BoardId);\r
+        break;\r
+\r
+      case 0x4:\r
+        UnicodeSPrint (Buffer, sizeof (Buffer), L"BAY LAKE FFRD(%02x)", mPlatformInfo->BoardId);\r
+        break;\r
+\r
+      case 0x5:\r
+        UnicodeSPrint (Buffer, sizeof (Buffer), L"BAY ROCK RVP DDR3L (%02x)", mPlatformInfo->BoardId);\r
+        break;\r
+\r
+      case 0x20:\r
+        UnicodeSPrint (Buffer, sizeof (Buffer), L"BAYLEY BAY (%02x)", mPlatformInfo->BoardId);\r
+        break;\r
+\r
+      case 0x30:\r
+        UnicodeSPrint (Buffer, sizeof (Buffer), L"BAKER SPORT (%02x)", mPlatformInfo->BoardId);\r
+        break;\r
+\r
+      case 0x0:\r
+        UnicodeSPrint (Buffer, sizeof (Buffer), L"ALPINE VALLEY (%x)", mPlatformInfo->BoardId);\r
+        break;\r
+\r
+      case 0x3:\r
+        UnicodeSPrint (Buffer, sizeof (Buffer), L"BAY LAKE FFD8 (%x)", mPlatformInfo->BoardId);\r
+        break;\r
+\r
+      default:\r
+        UnicodeSPrint (Buffer, sizeof (Buffer), L"Unknown BOARD (%02x)", mPlatformInfo->BoardId);\r
+        break;\r
+    }\r
+    HiiSetString(mHiiHandle,STRING_TOKEN(STR_BOARD_ID_VALUE), Buffer, NULL);\r
+\r
+\r
+    //\r
+    // Get Board FAB ID Info from protocol, update into the NVS area.\r
+    // bit0~bit3 are for Fab ID, 0x0F means unknow FAB.\r
+    //\r
+    if(mPlatformInfo->BoardRev == 0x0F) {\r
+      UnicodeSPrint (Buffer, sizeof (Buffer), L"%s", L"Unknown FAB");\r
+      HiiSetString(mHiiHandle,STRING_TOKEN(STR_FAB_ID_VALUE), Buffer, NULL);\r
+    } else {\r
+      UnicodeSPrint (Buffer, sizeof (Buffer), L"%2x", mPlatformInfo->BoardRev);\r
+      HiiSetString(mHiiHandle,STRING_TOKEN(STR_FAB_ID_VALUE), Buffer, NULL);\r
+    }\r
+  }\r
+\r
+  //\r
+  //Update MRC Version\r
+  //\r
+  MrcVersion = 0x00000000;\r
+  MrcVersion &= 0xffff;\r
+  Index = EfiValueToString (Buffer, MrcVersion/100, PREFIX_ZERO, 0);\r
+  StrCat (Buffer, L".");\r
+  EfiValueToString (Buffer + Index + 1, (MrcVersion%100)/10, PREFIX_ZERO, 0);\r
+  EfiValueToString (Buffer + Index + 2, (MrcVersion%100)%10, PREFIX_ZERO, 0);\r
+  HiiSetString(mHiiHandle,STRING_TOKEN(STR_MRC_VERSION_VALUE), Buffer, NULL);\r
+\r
+  //\r
+  //Update Soc Version\r
+  //\r
+\r
+  //\r
+  // Retrieve all instances of PCH Platform Policy protocol\r
+  //\r
+  Status = gBS->LocateHandleBuffer (\r
+                  ByProtocol,\r
+                  &gDxePchPlatformPolicyProtocolGuid,\r
+                  NULL,\r
+                  &NumHandles,\r
+                  &HandleBuffer\r
+                  );\r
+  if (!EFI_ERROR (Status)) {\r
+    //\r
+    // Find the matching PCH Policy protocol\r
+    //\r
+    for (Index = 0; Index < NumHandles; Index++) {\r
+      Status = gBS->HandleProtocol (\r
+                      HandleBuffer[Index],\r
+                      &gDxePchPlatformPolicyProtocolGuid,\r
+                      (void **)&PchPlatformPolicy\r
+                      );\r
+      if (!EFI_ERROR (Status)) {\r
+        PciD31F0RegBase = MmPciAddress (\r
+                            0,\r
+                            PchPlatformPolicy->BusNumber,\r
+                            PCI_DEVICE_NUMBER_PCH_LPC,\r
+                            PCI_FUNCTION_NUMBER_PCH_LPC,\r
+                            0\r
+                            );\r
+\r
+         Data8 = MmioRead8 (PciD31F0RegBase + R_PCH_LPC_RID_CC);\r
+         count = sizeof (SBRevisionTable) / sizeof (SBRevisionTable[0]);\r
+         for (Index = 0; Index < count; Index++) {\r
+           if(Data8 == SBRevisionTable[Index].RevId) {\r
+              UnicodeSPrint (Buffer, sizeof (Buffer), L"%02x %a", Data8, SBRevisionTable[Index].String);\r
+              HiiSetString(mHiiHandle,STRING_TOKEN(STR_SOC_VALUE), Buffer, NULL);\r
+             break;\r
+           }\r
+         }\r
+        break;\r
+      }\r
+    }\r
+  }\r
+\r
+  //\r
+  // Microcode Revision\r
+  //\r
+  EfiWriteMsr (EFI_MSR_IA32_BIOS_SIGN_ID, 0);\r
+  EfiCpuid (EFI_CPUID_VERSION_INFO, NULL);\r
+  MicroCodeVersion = (UINT32) RShiftU64 (EfiReadMsr (EFI_MSR_IA32_BIOS_SIGN_ID), 32);\r
+  UnicodeSPrint (Buffer, sizeof (Buffer), L"%x", MicroCodeVersion);\r
+  HiiSetString(mHiiHandle,STRING_TOKEN(STR_PROCESSOR_MICROCODE_VALUE), Buffer, NULL);\r
+\r
+  //\r
+  // Punit Version\r
+  //\r
+  Data8 = 0;\r
+  UnicodeSPrint (Buffer, sizeof (Buffer), L"0x%x", Data8);\r
+  HiiSetString(mHiiHandle,STRING_TOKEN(STR_PUNIT_FW_VALUE), Buffer, NULL);\r
+\r
+  //\r
+  //  PMC Version\r
+  //\r
+  Data8 = (UINT8)((MmioRead32 (PMC_BASE_ADDRESS + R_PCH_PMC_PRSTS)>>16)&0x00FF);\r
+  PIDData8 = (UINT8)((MmioRead32 (PMC_BASE_ADDRESS + R_PCH_PMC_PRSTS)>>24)&0x00FF);\r
+  UnicodeSPrint (Buffer, sizeof (Buffer), L"0x%X_%X",PIDData8, Data8);\r
+  HiiSetString(mHiiHandle,STRING_TOKEN(STR_PMC_FW_VALUE), Buffer, NULL);\r
+\r
+  return EFI_SUCCESS;\r
+}\r
+\r
+/**\r
+\r
+  Update SATA Drivesize Strings for Setup and Boot order\r
+\r
+  @param NewString - pointer to string.\r
+  @param DeviceSpeed - speed of drive.\r
+\r
+**/\r
+VOID\r
+GetDeviceSpeedString (\r
+  CHAR16                      *NewString,\r
+  IN UINTN                    DeviceSpeed\r
+  )\r
+{\r
+  if (DeviceSpeed == 0x01) {\r
+    StrCat (NewString, L"1.5Gb/s");\r
+  } else if (DeviceSpeed == 0x02) {\r
+    StrCat (NewString, L"3.0Gb/s");\r
+  } else if (DeviceSpeed == 0x03) {\r
+    StrCat (NewString, L"6.0Gb/s");\r
+  } else if (DeviceSpeed == 0x0) {\r
+\r
+  }\r
+}\r
+\r
+UINT8\r
+GetChipsetSataPortSpeed (\r
+  UINTN PortNum\r
+  )\r
+{\r
+  UINT32                      DeviceSpeed;\r
+  UINT8                       DeviceConfigStatus;\r
+  UINT32                      IdeAhciBar;\r
+  EFI_PHYSICAL_ADDRESS        MemBaseAddress = 0;\r
+  UINT8                       FunNum;\r
+  EFI_STATUS                  Status;\r
+  UINT32                      DwordReg;\r
+\r
+\r
+  DeviceSpeed = 0x01; // generation 1\r
+\r
+\r
+  //\r
+  // Allocate the AHCI BAR\r
+  //\r
+    FunNum = PCI_FUNCTION_NUMBER_PCH_SATA;\r
+    MemBaseAddress = 0x0ffffffff;\r
+    Status = gDS->AllocateMemorySpace (\r
+                    EfiGcdAllocateMaxAddressSearchBottomUp,\r
+                    EfiGcdMemoryTypeMemoryMappedIo,\r
+                    N_PCH_SATA_ABAR_ALIGNMENT,  // 2^11: 2K Alignment\r
+                    V_PCH_SATA_ABAR_LENGTH,     // 2K Length\r
+                    &MemBaseAddress,\r
+                    mImageHandle,\r
+                    NULL\r
+                    );\r
+    IdeAhciBar = MmioRead32 (\r
+                   MmPciAddress (\r
+                                    0,\r
+                     0,\r
+                     PCI_DEVICE_NUMBER_PCH_SATA,\r
+                     FunNum,\r
+                     R_PCH_SATA_ABAR\r
+                     )\r
+                   );\r
+    IdeAhciBar &= 0xFFFFF800;\r
+    DeviceConfigStatus = 0;\r
+    if (IdeAhciBar == 0) {\r
+      DeviceConfigStatus = 1;\r
+      IdeAhciBar = (UINT32)MemBaseAddress;\r
+      MmioWrite32 (\r
+        MmPciAddress (0, 0, PCI_DEVICE_NUMBER_PCH_SATA, FunNum, R_PCH_SATA_ABAR),\r
+        IdeAhciBar\r
+        );\r
+      MmioOr16 (\r
+        MmPciAddress (0, 0, PCI_DEVICE_NUMBER_PCH_SATA, FunNum, R_PCH_SATA_COMMAND),\r
+        B_PCH_SATA_COMMAND_MSE\r
+        );\r
+    }\r
+\r
+    if (mSystemConfiguration.SataType == PCH_SATA_MODE_IDE){\r
+      //\r
+      // Program the "Ports Implemented Register"\r
+      //\r
+      MmioAndThenOr32 (IdeAhciBar + R_PCH_SATA_AHCI_PI, (UINT32)~(B_PCH_SATA_PORT0_IMPLEMENTED + B_PCH_SATA_PORT1_IMPLEMENTED), (UINT32)(B_PCH_SATA_PORT0_IMPLEMENTED + B_PCH_SATA_PORT1_IMPLEMENTED));\r
+      DwordReg = MmioRead32 (IdeAhciBar + R_PCH_SATA_AHCI_PI);\r
+    }\r
+\r
+    switch (PortNum)\r
+    {\r
+      case 0:\r
+        DeviceSpeed = *(volatile UINT32 *)(UINTN)(IdeAhciBar + R_PCH_SATA_AHCI_P0SSTS);\r
+        break;\r
+      case 1:\r
+        DeviceSpeed = *(volatile UINT32 *)(UINTN)(IdeAhciBar + R_PCH_SATA_AHCI_P1SSTS);\r
+        break;\r
+    }\r
+\r
+    if (MemBaseAddress) {\r
+      gDS->FreeMemorySpace (\r
+             MemBaseAddress,\r
+             V_PCH_SATA_ABAR_LENGTH\r
+             );\r
+    }\r
+\r
+  if (DeviceConfigStatus) {\r
+    IdeAhciBar = 0;\r
+    MmioWrite32 (\r
+      MmPciAddress (0, 0, PCI_DEVICE_NUMBER_PCH_SATA, FunNum, R_PCH_SATA_ABAR),\r
+      IdeAhciBar\r
+      );\r
+  }\r
+\r
+  DeviceSpeed = (UINT8)((DeviceSpeed >> 4) & 0x0F);\r
+\r
+  return (UINT8)DeviceSpeed;\r
+}\r
+\r
+/**\r
+\r
+  IDE data filter function.\r
+\r
+**/\r
+void\r
+IdeDataFilter (void)\r
+{\r
+  EFI_STATUS                  Status;\r
+  UINTN                       HandleCount;\r
+  EFI_HANDLE                  *HandleBuffer;\r
+  EFI_DISK_INFO_PROTOCOL      *DiskInfo;\r
+  EFI_DEVICE_PATH_PROTOCOL    *DevicePath, *DevicePathNode;\r
+  PCI_DEVICE_PATH             *PciDevicePath;\r
+  UINTN                       Index;\r
+  UINT8                       Index1;\r
+  UINT32                      BufferSize;\r
+  UINT32                      DriveSize;\r
+  UINT32                      IdeChannel;\r
+  UINT32                      IdeDevice;\r
+  EFI_ATA_IDENTIFY_DATA       *IdentifyDriveInfo;\r
+  CHAR16                      *NewString;\r
+  CHAR16                      SizeString[20];\r
+  STRING_REF                  NameToUpdate;\r
+  CHAR8                       StringBuffer[0x100];\r
+  UINT32                      DeviceSpeed;\r
+  UINTN                       PortNumber;\r
+\r
+  //\r
+  // Assume no line strings is longer than 256 bytes.\r
+  //\r
+  NewString = AllocateZeroPool (0x100);\r
+  PciDevicePath = NULL;\r
+\r
+  //\r
+  // Fill IDE Infomation\r
+  //\r
+  Status = gBS->LocateHandleBuffer (\r
+                  ByProtocol,\r
+                  &gEfiDiskInfoProtocolGuid,\r
+                  NULL,\r
+                  &HandleCount,\r
+                  &HandleBuffer\r
+                                 );\r
+\r
+  if (EFI_ERROR (Status)) {\r
+    return;\r
+  }\r
+\r
+  for (Index = 0; Index < HandleCount; Index++) {\r
+\r
+    Status = gBS->HandleProtocol (\r
+                    HandleBuffer[Index],\r
+                    &gEfiDevicePathProtocolGuid,\r
+                    (VOID*)&DevicePath\r
+                                   );\r
+    ASSERT_EFI_ERROR (Status);\r
+\r
+    DevicePathNode = DevicePath;\r
+    while (!IsDevicePathEnd (DevicePathNode) ) {\r
+      if  ((DevicePathType (DevicePathNode) == HARDWARE_DEVICE_PATH) &&\r
+           ( DevicePathSubType (DevicePathNode) == HW_PCI_DP)) {\r
+        PciDevicePath = (PCI_DEVICE_PATH *) DevicePathNode;\r
+        break;\r
+      }\r
+      DevicePathNode    = NextDevicePathNode (DevicePathNode);\r
+    }\r
+\r
+    if (PciDevicePath == NULL) {\r
+      continue;\r
+    }\r
+\r
+    //\r
+    // Check for onboard IDE\r
+    //\r
+    if (PciDevicePath->Device== PCI_DEVICE_NUMBER_PCH_SATA) {\r
+      Status = gBS->HandleProtocol (\r
+                         HandleBuffer[Index],\r
+                                         &gEfiDiskInfoProtocolGuid,\r
+                                         (void **)&DiskInfo\r
+                                         );\r
+      ASSERT_EFI_ERROR (Status);\r
+\r
+      Status = DiskInfo->WhichIde (\r
+                              DiskInfo,\r
+                           &IdeChannel,\r
+                           &IdeDevice\r
+                                                  );\r
+      ASSERT_EFI_ERROR (Status);\r
+\r
+      IdentifyDriveInfo = AllocatePool (sizeof(EFI_ATA_IDENTIFY_DATA));\r
+\r
+      BufferSize = sizeof(EFI_ATA_IDENTIFY_DATA);\r
+      Status = DiskInfo->Identify (\r
+                              DiskInfo,\r
+                           IdentifyDriveInfo,\r
+                           &BufferSize\r
+                           );\r
+      ASSERT_EFI_ERROR(Status);\r
+\r
+      //\r
+      // Onboard SATA Devices\r
+      //\r
+      if (PciDevicePath->Function == PCI_FUNCTION_NUMBER_PCH_SATA) {\r
+        if (IdeChannel == 0 && IdeDevice == 0) {\r
+          NameToUpdate = (STRING_REF)STR_SATA0_NAME;\r
+        } else if (IdeChannel == 1 && IdeDevice == 0) {\r
+          NameToUpdate = (STRING_REF)STR_SATA1_NAME;\r
+        } else {\r
+          continue;\r
+        }\r
+      } else {\r
+        continue;\r
+      }\r
+\r
+      ZeroMem(StringBuffer, sizeof(StringBuffer));\r
+      CopyMem(\r
+        StringBuffer,\r
+        (CHAR8 *)&IdentifyDriveInfo->ModelName,\r
+        sizeof(IdentifyDriveInfo->ModelName)\r
+        );\r
+      SwapEntries(StringBuffer);\r
+      AsciiToUnicode(StringBuffer, NewString);\r
+\r
+         //\r
+      // Chap it off after 16 characters\r
+         //\r
+      NewString[16] = 0;\r
+\r
+      //\r
+      // For HardDisk append the size. Otherwise display atapi\r
+      //\r
+      if ((IdentifyDriveInfo->config & 0x8000) == 00) {\r
+        //\r
+        // 48 bit address feature set is supported, get maximum capacity\r
+        //\r
+        if ((IdentifyDriveInfo->command_set_supported_83 & 0x0400) == 0) {\r
+        DriveSize = (((((IdentifyDriveInfo->user_addressable_sectors_hi << 16) +\r
+                      IdentifyDriveInfo->user_addressable_sectors_lo) / 1000) * 512) / 1000);\r
+        } else {\r
+          DriveSize    = IdentifyDriveInfo->maximum_lba_for_48bit_addressing[0];\r
+          for (Index1 = 1; Index1 < 4; Index1++) {\r
+            //\r
+            // Lower byte goes first: word[100] is the lowest word, word[103] is highest\r
+            //\r
+            DriveSize |= LShiftU64(IdentifyDriveInfo->maximum_lba_for_48bit_addressing[Index1], 16 * Index1);\r
+          }\r
+          DriveSize = (UINT32) DivU64x32(MultU64x32(DivU64x32(DriveSize, 1000), 512), 1000);\r
+        }\r
+\r
+        StrCat (NewString, L"(");\r
+        EfiValueToString (SizeString, DriveSize/1000, PREFIX_BLANK, 0);\r
+        StrCat (NewString, SizeString);\r
+        StrCat (NewString, L".");\r
+        EfiValueToString (SizeString, (DriveSize%1000)/100, PREFIX_BLANK, 0);\r
+        StrCat (NewString, SizeString);\r
+        StrCat (NewString, L"GB");\r
+      } else {\r
+        StrCat (NewString, L"(ATAPI");\r
+      }\r
+\r
+      //\r
+      // Update SPEED.\r
+      //\r
+      PortNumber = (IdeDevice << 1) + IdeChannel;\r
+      DeviceSpeed = GetChipsetSataPortSpeed(PortNumber);\r
+\r
+      if (DeviceSpeed) {\r
+        StrCat (NewString, L"-");\r
+        GetDeviceSpeedString( NewString, DeviceSpeed);\r
+      }\r
+\r
+      StrCat (NewString, L")");\r
+\r
+      HiiSetString(mHiiHandle, NameToUpdate, NewString, NULL);\r
+\r
+    }\r
+  }\r
+\r
+  if (HandleBuffer != NULL) {\r
+    gBS->FreePool (HandleBuffer);\r
+  }\r
+\r
+  gBS->FreePool(NewString);\r
+\r
+  return;\r
+}\r
+\r
+\r
+VOID\r
+EFIAPI\r
+SetupInfo (void)\r
+{\r
+  EFI_STATUS                  Status;\r
+  UINTN                       VarSize;\r
+  EFI_PEI_HOB_POINTERS        GuidHob;\r
+\r
+  if (mSetupInfoDone) {\r
+      return;\r
+  }\r
+\r
+  VarSize = sizeof(SYSTEM_CONFIGURATION);\r
+  Status = gRT->GetVariable(\r
+                  NORMAL_SETUP_NAME,\r
+                  &gEfiNormalSetupGuid,\r
+                  NULL,\r
+                  &VarSize,\r
+                  &mSystemConfiguration\r
+                                 );\r
+\r
+  ASSERT_EFI_ERROR (Status);\r
+\r
+  //\r
+  // Update HOB variable for PCI resource information\r
+  // Get the HOB list.  If it is not present, then ASSERT.\r
+  //\r
+  GuidHob.Raw = GetHobList ();\r
+  if (GuidHob.Raw != NULL) {\r
+    if ((GuidHob.Raw = GetNextGuidHob (&gEfiPlatformInfoGuid, GuidHob.Raw)) != NULL) {\r
+      mPlatformInfo = GET_GUID_HOB_DATA (GuidHob.Guid);\r
+    }\r
+  }\r
+\r
+\r
+  PrepareSetupInformation();\r
+  UpdateAdditionalInformation ();\r
+  UpdatePlatformInformation();\r
+  UpdateCPUInformation();\r
+  IdeDataFilter();\r
+  mSetupInfoDone = TRUE;\r
+\r
+  return;\r
+}\r
+\r
+\r
+#define EFI_SECURE_BOOT_MODE_NAME                   L"SecureBoot"\r
+\r
+VOID\r
+CheckSystemConfigLoad(SYSTEM_CONFIGURATION *SystemConfigPtr)\r
+{\r
+  EFI_STATUS              Status;\r
+  UINT8                   SecureBoot;\r
+  UINTN                   DataSize;\r
+\r
+\r
+  DataSize = sizeof(SecureBoot);\r
+  Status = gRT->GetVariable (\r
+                  EFI_SECURE_BOOT_MODE_NAME,\r
+                  &gEfiGlobalVariableGuid,\r
+                  NULL,\r
+                  &DataSize,\r
+                  &SecureBoot\r
+                  );\r
+\r
+  if (EFI_ERROR(Status)) {\r
+    SystemConfigPtr->SecureBoot = 0;\r
+  } else {\r
+    SystemConfigPtr->SecureBoot = SecureBoot;\r
+  }\r
+}\r
+\r
+\r
+//\r
+// "SecureBootEnable" variable for the Secure boot feature enable/disable.\r
+//\r
+#define EFI_SECURE_BOOT_ENABLE_NAME      L"SecureBootEnable"\r
+extern EFI_GUID gEfiSecureBootEnableDisableGuid;\r
+\r
+\r
+VOID\r
+CheckSystemConfigSave(SYSTEM_CONFIGURATION *SystemConfigPtr)\r
+{\r
+  EFI_STATUS              Status;\r
+  UINT8                   SecureBootCfg;\r
+  BOOLEAN                 SecureBootNotFound;\r
+  UINTN                   DataSize;\r
+\r
+\r
+    //\r
+    // Secure Boot configuration changes\r
+       //\r
+    DataSize = sizeof(SecureBootCfg);\r
+    SecureBootNotFound = FALSE;\r
+    Status = gRT->GetVariable (\r
+                    EFI_SECURE_BOOT_ENABLE_NAME,\r
+                    &gEfiSecureBootEnableDisableGuid,\r
+                    NULL,\r
+                    &DataSize,\r
+                    &SecureBootCfg\r
+                    );\r
+\r
+    if (EFI_ERROR(Status)) {\r
+      SecureBootNotFound = TRUE;\r
+    }\r
+    if (SecureBootNotFound) {\r
+      Status = gRT->GetVariable (\r
+                      EFI_SECURE_BOOT_ENABLE_NAME,\r
+                      &gEfiSecureBootEnableDisableGuid,\r
+                      NULL,\r
+                      &DataSize,\r
+                      &SecureBootCfg\r
+                      );\r
+      ASSERT_EFI_ERROR(Status);\r
+    }\r
+    if ((SecureBootCfg) != SystemConfigPtr->SecureBoot) {\r
+      SecureBootCfg = !SecureBootCfg;\r
+      Status = gRT->SetVariable (\r
+                      EFI_SECURE_BOOT_ENABLE_NAME,\r
+                      &gEfiSecureBootEnableDisableGuid,\r
+                      EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS,\r
+                      sizeof (UINT8),\r
+                      &SecureBootCfg\r
+                      );\r
+    }\r
+\r
+}\r
+\r
+VOID\r
+ConfirmSecureBootTest()\r
+{\r
+\r
+}\r
+\r

diff --git a/Vlv2TbltDevicePkg/PlatformSetupDxe/SouthClusterConfig.vfi b/Vlv2TbltDevicePkg/PlatformSetupDxe/SouthClusterConfig.vfi
new file mode 100644 (file)
index 0000000..e7e952f
--- /dev/null
+++ b/Vlv2TbltDevicePkg/PlatformSetupDxe/SouthClusterConfig.vfi
@@ -0,0 +1,918 @@
+//\r
+//\r
+// Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+//                                                                                  \r\r
+// This program and the accompanying materials are licensed and made available under\r\r
+// the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+// The full text of the license may be found at                                     \r\r
+// http://opensource.org/licenses/bsd-license.php.                                  \r\r
+//                                                                                  \r\r
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+//                                                                                  \r\r
+//\r
+//\r
+//\r
+// Module Name:\r
+//\r
+//   SourthClusterConfig.vfi\r
+//\r
+// Abstract:\r
+//\r
+//   Driver Setup formset.\r
+//\r
+//Revision History:\r
+//  ------------------------------------------------------------------------------\r
+//  Rev   Date<MM/DD/YYYY>    Name    Description\r
+//  ------------------------------------------------------------------------------\r
+\r
+// --*/\r
+\r
+//\r
+// South Cluster Configuration Form\r
+//\r
+\r
+form formid = SOUTH_CLUSTER_FORM_ID,\r
+  title    = STRING_TOKEN(STR_SOUTH_CLUSTER_TITLE);\r
+\r
+  subtitle text = STRING_TOKEN(STR_NULL_STRING);\r
+\r
+  //\r
+  // Jump to PCIe Configuration Form\r
+  //\r
+  goto PCIE_DEVICE_OPTIONS_FORM_ID,\r
+    prompt = STRING_TOKEN(STR_PCIE_OPTIONS_FORM_TITLE),\r
+    help = STRING_TOKEN(STR_PCIE_OPTIONS_FORM_HELP);\r
+\r
+  //\r
+  // Jump to USB Configuration Form\r
+  //\r
+  goto USB_OPTIONS_FORM_ID,\r
+    prompt = STRING_TOKEN(STR_USB_OPTIONS_FORM_TITLE),\r
+    help = STRING_TOKEN(STR_USB_OPTIONS_FORM_HELP);\r
+  //\r
+  // Jump to Azalia Configuration Form\r
+  //\r
+  goto AZALIA_OPTIONS_FORM_ID,\r
+    prompt = STRING_TOKEN(STR_AZALIA_OPTIONS_FORM_TITLE),\r
+    help   = STRING_TOKEN(STR_AZALIA_OPTIONS_FORM_HELP);\r
+\r
+  //\r
+  // Jump to Drive Configuration Form\r
+  //\r
+  goto DRIVE_CONFIGURATION_ID,\r
+    prompt = STRING_TOKEN(STR_IDE_FORM_TITLE),\r
+    help   = STRING_TOKEN(STR_IDE_FORM_HELP);\r
+  //\r
+  // Jump to LAN Configuration Form\r
+  //\r
+\r
+  //\r
+  // Jump to LPSS Configuration Form\r
+  //\r
+  goto LPSS_CONFIGURATION_ID,\r
+    prompt = STRING_TOKEN(STR_LPSS_SCC_FORM_TITLE),\r
+    help   = STRING_TOKEN(STR_LPSS_SCC_FORM_HELP);\r
+\r
+  //\r
+  // Jump to Misc Configuration Form\r
+  //\r
+  goto MISC_OPTIONS_FORM_ID,\r
+    prompt = STRING_TOKEN(STR_MISC_OPTION_FORM_TITLE),\r
+    help   = STRING_TOKEN(STR_MISC_OPTION_FORM_HELP);\r
+endform;\r
+\r
+form formid = PCIE_DEVICE_OPTIONS_FORM_ID,\r
+\r
+  title    = STRING_TOKEN(STR_PCIE_OPTIONS_FORM_TITLE);\r
+\r
+  subtitle text = STRING_TOKEN(STR_NULL_STRING);\r
+\r
+    oneof varid   = Setup.PcieRootPortSpeed[0],\r
+      prompt      = STRING_TOKEN (STR_PCIE_SPEED_PROMPT0),\r
+      help        = STRING_TOKEN (STR_PCIE_SPEED_HELP),\r
+      option text = STRING_TOKEN (STR_AUTO), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED;\r
+      option text = STRING_TOKEN (STR_GEN1), value = 1, flags = RESET_REQUIRED;\r
+      option text = STRING_TOKEN (STR_GEN2), value = 2, flags = RESET_REQUIRED;\r
+    endoneof;\r
+    oneof varid   = Setup.PcieRootPortSpeed[1],\r
+      prompt      = STRING_TOKEN (STR_PCIE_SPEED_PROMPT1),\r
+      help        = STRING_TOKEN (STR_PCIE_SPEED_HELP),\r
+      option text = STRING_TOKEN (STR_AUTO), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED;\r
+      option text = STRING_TOKEN (STR_GEN1), value = 1, flags = RESET_REQUIRED;\r
+      option text = STRING_TOKEN (STR_GEN2), value = 2, flags = RESET_REQUIRED;\r
+    endoneof;\r
+    oneof varid   = Setup.PcieRootPortSpeed[2],\r
+      prompt      = STRING_TOKEN (STR_PCIE_SPEED_PROMPT2),\r
+      help        = STRING_TOKEN (STR_PCIE_SPEED_HELP),\r
+      option text = STRING_TOKEN (STR_AUTO), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED;\r
+      option text = STRING_TOKEN (STR_GEN1), value = 1, flags = RESET_REQUIRED;\r
+      option text = STRING_TOKEN (STR_GEN2), value = 2, flags = RESET_REQUIRED;\r
+    endoneof;\r
+    oneof varid   = Setup.PcieRootPortSpeed[3],\r
+      prompt      = STRING_TOKEN (STR_PCIE_SPEED_PROMPT3),\r
+      help        = STRING_TOKEN (STR_PCIE_SPEED_HELP),\r
+      option text = STRING_TOKEN (STR_AUTO), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED;\r
+      option text = STRING_TOKEN (STR_GEN1), value = 1, flags = RESET_REQUIRED;\r
+      option text = STRING_TOKEN (STR_GEN2), value = 2, flags = RESET_REQUIRED;\r
+    endoneof;\r
+  //\r
+  //PCIe Port\r
+  //\r
+  oneof varid  = Setup.IchPciExp[0],\r
+    prompt   = STRING_TOKEN(STR_ICH_PCIERP1_PROMPT),\r
+    help     = STRING_TOKEN(STR_ICH_PCIERP_HELP),\r
+    option text = STRING_TOKEN(STR_ENABLE), value=1, flags=DEFAULT | MANUFACTURING | RESET_REQUIRED;\r
+    option text = STRING_TOKEN(STR_DISABLE), value=0, flags=0 | RESET_REQUIRED;\r
+  endoneof;\r
+\r
+  suppressif ideqval Setup.IchPciExp[0] == 0x0;\r
+    oneof varid    = Setup.IchPciExp[1],\r
+      prompt   = STRING_TOKEN(STR_ICH_PCIERP2_PROMPT),\r
+      help     = STRING_TOKEN(STR_ICH_PCIERP_HELP),\r
+      option text = STRING_TOKEN(STR_ENABLE), value=1, flags= RESET_REQUIRED;\r
+      option text = STRING_TOKEN(STR_DISABLE), value=0, flags= DEFAULT | MANUFACTURING | RESET_REQUIRED;\r
+    endoneof;\r
+  endif;\r
+\r
+  suppressif NOT ideqval Setup.IchPciExp[0] == 0x0;\r
+  text\r
+    help   = STRING_TOKEN(STR_ICH_PCIERP_HELP),\r
+    text   = STRING_TOKEN(STR_ICH_PCIERP2_PROMPT),\r
+    text   = STRING_TOKEN(STR_ICH_PCIERP_DISABLE_HELP),\r
+    flags  = 0,\r
+    key    = 0;\r
+  endif;\r
+\r
+  suppressif ideqval Setup.IchPciExp[0] == 0x0;\r
+    oneof varid    = Setup.IchPciExp[2],\r
+      prompt   = STRING_TOKEN(STR_ICH_PCIERP3_PROMPT),\r
+      help     = STRING_TOKEN(STR_ICH_PCIERP_HELP),\r
+      option text = STRING_TOKEN(STR_ENABLE), value=1, flags=DEFAULT | MANUFACTURING | RESET_REQUIRED;\r
+      option text = STRING_TOKEN(STR_DISABLE), value=0, flags=0 | RESET_REQUIRED;\r
+    endoneof;\r
+  endif;\r
+\r
+  suppressif NOT ideqval Setup.IchPciExp[0] == 0x0;\r
+  text\r
+    help   = STRING_TOKEN(STR_ICH_PCIERP_HELP),\r
+    text   = STRING_TOKEN(STR_ICH_PCIERP3_PROMPT),\r
+    text   = STRING_TOKEN(STR_ICH_PCIERP_DISABLE_HELP),\r
+    flags  = 0,\r
+    key    = 0;\r
+  endif;\r
+\r
+  suppressif ideqval Setup.IchPciExp[0] == 0x0;\r
+    oneof varid    = Setup.IchPciExp[3],\r
+      prompt   = STRING_TOKEN(STR_ICH_PCIERP4_PROMPT),\r
+      help     = STRING_TOKEN(STR_ICH_PCIERP_HELP),\r
+      option text = STRING_TOKEN(STR_ENABLE), value=1, flags= DEFAULT | MANUFACTURING | RESET_REQUIRED;\r
+      option text = STRING_TOKEN(STR_DISABLE), value=0, flags= 0 | RESET_REQUIRED;\r
+    endoneof;\r
+  endif;\r
+\r
+  suppressif NOT ideqval Setup.IchPciExp[0] == 0x0;\r
+  text\r
+    help   = STRING_TOKEN(STR_ICH_PCIERP_HELP),\r
+    text   = STRING_TOKEN(STR_ICH_PCIERP4_PROMPT),\r
+    text   = STRING_TOKEN(STR_ICH_PCIERP_DISABLE_HELP),\r
+    flags  = 0,\r
+    key    = 0;\r
+  endif;\r
+\r
+\r
+endform;\r
+\r
+form formid = USB_OPTIONS_FORM_ID,\r
+\r
+  title    = STRING_TOKEN(STR_USB_OPTIONS_FORM_TITLE);\r
+\r
+  subtitle text = STRING_TOKEN(STR_NULL_STRING);\r
+\r
+  oneof   varid   = Setup.UsbAutoMode,\r
+    questionid  = 0x123A,\r
+    prompt      = STRING_TOKEN(STR_USB_AUTO_MODE_PROMPT),\r
+    help        = STRING_TOKEN(STR_USB_AUTO_MODE_HELP),\r
+    flags       = INTERACTIVE,\r
+    option text = STRING_TOKEN(STR_ENABLE), value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED;\r
+    option text = STRING_TOKEN(STR_DISABLE), value = 0, flags =  RESET_REQUIRED;\r
+  endoneof;\r
+\r
+  subtitle text = STRING_TOKEN(STR_NULL_STRING);\r
+  //\r
+  //XHCI support\r
+  //\r
+  grayoutif ideqval Setup.UsbAutoMode == 0x1;\r
+       grayoutif ideqval Setup.PchUsb20 == 0x1;\r
+       oneof   varid   = Setup.UsbXhciSupport,\r
+         questionid  = 0x123B,\r
+       prompt      = STRING_TOKEN(STR_USB_XHCI_SUPPORT_PROMPT),\r
+       help        = STRING_TOKEN(STR_USB_XHCI_SUPPORT_HELP),\r
+       flags       = INTERACTIVE,\r
+       option text = STRING_TOKEN(STR_ENABLE), value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED;\r
+       option text = STRING_TOKEN(STR_DISABLE), value = 0, flags =  RESET_REQUIRED;\r
+       endoneof;\r
+\r
+      suppressif ideqval Setup.UsbXhciSupport == 0x0;\r
+       oneof   varid   = Setup.Hsic0,\r
+               prompt      = STRING_TOKEN(STR_USB_HSIC_0_PROMPT),\r
+               help        = STRING_TOKEN(STR_USB_HSIC_0_HELP),\r
+               option text = STRING_TOKEN(STR_ENABLE), value = 1, flags = RESET_REQUIRED;\r
+               option text = STRING_TOKEN(STR_DISABLE), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED;\r
+       endoneof;\r
+       endif;\r
+\r
+       oneof varid   = Setup.PchUsb30Mode,\r
+       prompt      = STRING_TOKEN(STR_PCH_USB30_MODE_PROMPT),\r
+       help        = STRING_TOKEN(STR_PCH_USB30_MODE_HELP),\r
+       option text = STRING_TOKEN(STR_ENABLE), value = 1, flags = DEFAULT | MANUFACTURING |RESET_REQUIRED;\r
+       option text = STRING_TOKEN(STR_DISABLE), value = 0, flags =  RESET_REQUIRED;\r
+       endoneof;\r
+\r
+       oneof   varid   = Setup.UsbXhciLpmSupport,\r
+       prompt      = STRING_TOKEN(STR_USB_XHCI_LPM_SUPPORT_PROMPT),\r
+       help        = STRING_TOKEN(STR_USB_XHCI_LPM_SUPPORT_HELP),\r
+\r
+       option text = STRING_TOKEN(STR_ENABLE), value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED;\r
+       option text = STRING_TOKEN(STR_DISABLE), value = 0, flags = RESET_REQUIRED;\r
+\r
+       endoneof;\r
+       endif;\r
+  endif;\r
+\r
+  subtitle text = STRING_TOKEN(STR_NULL_STRING);\r
+\r
+  oneof varid   = Setup.PchUsbOtg,\r
+    prompt      = STRING_TOKEN(STR_PCH_USB_OTG_PROMPT),\r
+    help        = STRING_TOKEN(STR_PCH_USB_OTG_HELP),\r
+    option text = STRING_TOKEN(STR_DISABLE), value = 0, flags = DEFAULT | MANUFACTURING |RESET_REQUIRED;\r
+    option text = STRING_TOKEN(STR_PCI_MODE_STRING), value = 1, flags =  RESET_REQUIRED;\r
+  endoneof;\r
+\r
+  oneof varid   = Setup.PchUsbVbusOn,\r
+    prompt      = STRING_TOKEN(STR_PCH_USB_VBUS_PROMPT),\r
+    help        = STRING_TOKEN(STR_PCH_USB_VBUS_HELP),\r
+    option text = STRING_TOKEN(STR_OFF), value = 0, flags = RESET_REQUIRED;\r
+    option text = STRING_TOKEN(STR_ON), value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED;\r
+    option text = STRING_TOKEN(STR_AUTO), value = 2, flags = RESET_REQUIRED;\r
+  endoneof;\r
+  subtitle text = STRING_TOKEN(STR_NULL_STRING);\r
+\r
+  //\r
+  //EHCI support\r
+  //\r
+  grayoutif ideqval Setup.UsbAutoMode == 0x1;\r
+    grayoutif ideqval Setup.UsbXhciSupport == 0x1;\r
+      oneof   varid   = Setup.PchUsb20,\r
+        questionid  = 0x123C,\r
+        prompt   = STRING_TOKEN(STR_PCH_USB21_PROMPT),\r
+        help     = STRING_TOKEN(STR_PCH_USB2_HELP),\r
+        flags    = INTERACTIVE,\r
+        option text = STRING_TOKEN(STR_ENABLE), value = 1, flags =  RESET_REQUIRED;\r
+        option text = STRING_TOKEN(STR_DISABLE), value= 0, flags= DEFAULT | MANUFACTURING |RESET_REQUIRED;\r
+      endoneof;\r
+\r
+      oneof varid  = Setup.PchUsbRmh,\r
+        prompt   = STRING_TOKEN(STR_PCH_USBRMH_PROMPT),\r
+        help     = STRING_TOKEN(STR_PCH_USBRMH_HELP),\r
+        option text = STRING_TOKEN(STR_DISABLE), value = 0, flags = RESET_REQUIRED;\r
+        option text = STRING_TOKEN(STR_ENABLE), value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED;\r
+      endoneof;\r
+\r
+      oneof varid  = Setup.PchEhciDebug,\r
+        prompt   = STRING_TOKEN(STR_PCH_USB_EHCIDEBUG_PROMPT),\r
+        help     = STRING_TOKEN(STR_PCH_USB_EHCIDEBUG_HELP),\r
+        option text = STRING_TOKEN(STR_DISABLE), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED;\r
+        option text = STRING_TOKEN(STR_ENABLE),  value = 1, flags = RESET_REQUIRED;\r
+      endoneof;\r
+\r
+      suppressif TRUE;\r
+        oneof varid   = Setup.EhciPllCfgEnable,\r
+        prompt      = STRING_TOKEN(STR_EHCI_PLL_CFG_PROMPT),\r
+        help        = STRING_TOKEN(STR_EHCI_PLL_CFG_RTD3_DIS_HELP),\r
+        option text = STRING_TOKEN(STR_ENABLE), value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED;\r
+        option text = STRING_TOKEN(STR_DISABLE), value = 0, flags = RESET_REQUIRED;\r
+        endoneof;\r
+      endif;\r
+    endif;\r
+\r
+    //\r
+    // Usb ports per-port disable control enable\r
+    //\r
+    oneof varid   = Setup.PchUsbPerPortCtl,\r
+      prompt      = STRING_TOKEN(STR_PCH_USB_PER_PORT_PROMPT),\r
+      help        = STRING_TOKEN(STR_PCH_USB_PER_PORT_HELP),\r
+      option text = STRING_TOKEN(STR_DISABLE), value = 0, flags = RESET_REQUIRED;\r
+      option text = STRING_TOKEN(STR_ENABLE), value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED;\r
+    endoneof;\r
+\r
+    suppressif ideqval Setup.PchUsbPerPortCtl == 0x0;\r
+      oneof varid  = Setup.PchUsbPort[0],\r
+      prompt   = STRING_TOKEN(STR_PCH_USB_PORT0_PROMPT),\r
+      help     = STRING_TOKEN(STR_PCH_USB_PORT_DIS_HELP),\r
+      option text = STRING_TOKEN(STR_DISABLE), value = 0, flags = RESET_REQUIRED;\r
+      option text = STRING_TOKEN(STR_ENABLE), value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED;\r
+      endoneof;\r
+\r
+      oneof varid  = Setup.PchUsbPort[1],\r
+      prompt   = STRING_TOKEN(STR_PCH_USB_PORT1_PROMPT),\r
+      help     = STRING_TOKEN(STR_PCH_USB_PORT_DIS_HELP),\r
+      option text = STRING_TOKEN(STR_DISABLE), value = 0, flags = RESET_REQUIRED;\r
+      option text = STRING_TOKEN(STR_ENABLE), value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED;\r
+      endoneof;\r
+\r
+      oneof varid  = Setup.PchUsbPort[2],\r
+      prompt   = STRING_TOKEN(STR_PCH_USB_PORT2_PROMPT),\r
+      help     = STRING_TOKEN(STR_PCH_USB_PORT_DIS_HELP),\r
+      option text = STRING_TOKEN(STR_DISABLE), value = 0, flags = RESET_REQUIRED;\r
+      option text = STRING_TOKEN(STR_ENABLE), value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED;\r
+      endoneof;\r
+\r
+      oneof varid  = Setup.PchUsbPort[3],\r
+      prompt   = STRING_TOKEN(STR_PCH_USB_PORT3_PROMPT),\r
+      help     = STRING_TOKEN(STR_PCH_USB_PORT_DIS_HELP),\r
+      option text = STRING_TOKEN(STR_DISABLE), value = 0, flags = RESET_REQUIRED;\r
+      option text = STRING_TOKEN(STR_ENABLE), value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED;\r
+      endoneof;\r
+    endif;\r
+\r
+\r
+  endif;\r
+\r
+endform;\r
+\r
+//\r
+// SATA Controller\r
+//\r
+form formid = DRIVE_CONFIGURATION_ID,\r
+\r
+  title    = STRING_TOKEN(STR_IDE_FORM_TITLE);\r
+\r
+  //\r
+  // Title on Drive Configuration Page\r
+  //\r
+  text\r
+    help   = STRING_TOKEN(STR_NULL_STRING),\r
+    text   = STRING_TOKEN(STR_IDE_FORM_TITLE),\r
+    text   = STRING_TOKEN(STR_NULL_STRING),\r
+    flags  = 0,\r
+    key    = 0;\r
+\r
+  subtitle text = STRING_TOKEN(STR_NULL_STRING);\r
+\r
+  subtitle text = STRING_TOKEN(STR_CHIPSET_SATA_STRING);\r
+\r
+  oneof varid   = Setup.Sata,\r
+    prompt      = STRING_TOKEN(STR_SATA_PROMPT),\r
+    help        = STRING_TOKEN(STR_SATA_HELP),\r
+    option text = STRING_TOKEN(STR_ENABLE), value=1, flags=DEFAULT | MANUFACTURING | RESET_REQUIRED;\r
+    option text = STRING_TOKEN(STR_DISABLE), value=0, flags=0 | RESET_REQUIRED;\r
+  endoneof;\r
+\r
+    oneof varid   = Setup.SataTestMode,\r
+      prompt      = STRING_TOKEN(STR_SATA_TEST_MODE_PROMPT),\r
+      help        = STRING_TOKEN(STR_SATA_TEST_MODE_HELP),\r
+      option text = STRING_TOKEN(STR_ENABLE), value = 1, flags = RESET_REQUIRED;\r
+      option text = STRING_TOKEN(STR_DISABLE), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED;\r
+    endoneof;\r
+\r
+  suppressif ideqval Setup.Sata == 0x00;\r
+    oneof varid   = Setup.SataType,\r
+      prompt      = STRING_TOKEN(STR_SATA_TYPE_PROMPT),\r
+      help        = STRING_TOKEN(STR_SATA_TYPE_HELP1),\r
+      option text = STRING_TOKEN(STR_SATA_IDE), value = 0, flags = RESET_REQUIRED;\r
+      option text = STRING_TOKEN(STR_SATA_AHCI), value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED;\r
+    endoneof;\r
+\r
+    text\r
+      help   = STRING_TOKEN(STR_NULL_STRING),\r
+      text   = STRING_TOKEN(STR_SATA0_STRING),\r
+      text   = STRING_TOKEN(STR_SATA0_NAME),\r
+      flags  = 0,\r
+      key    = 0;\r
+\r
+    text\r
+      help   = STRING_TOKEN(STR_NULL_STRING),\r
+      text   = STRING_TOKEN(STR_SATA1_STRING),\r
+      text   = STRING_TOKEN(STR_SATA1_NAME),\r
+      flags  = 0,\r
+      key    = 0;\r
+\r
+    suppressif ideqval Setup.SataType == 0x0;\r
+      oneof varid   = Setup.Sata0HotPlugCap,\r
+        prompt      = STRING_TOKEN(STR_SATA0_HOTPLUG_CAP_PROMPT),\r
+        help        = STRING_TOKEN(STR_SATA_HOTPLUG_CAP_HELP),\r
+        option text = STRING_TOKEN(STR_ENABLE), value= 1, flags=DEFAULT | MANUFACTURING | RESET_REQUIRED;\r
+        option text = STRING_TOKEN(STR_DISABLE), value=0, flags=0 | RESET_REQUIRED;\r
+      endoneof;\r
+\r
+      oneof varid   = Setup.Sata1HotPlugCap,\r
+        prompt      = STRING_TOKEN(STR_SATA1_HOTPLUG_CAP_PROMPT),\r
+        help        = STRING_TOKEN(STR_SATA_HOTPLUG_CAP_HELP),\r
+        option text = STRING_TOKEN(STR_ENABLE), value= 1, flags=DEFAULT | MANUFACTURING | RESET_REQUIRED;\r
+        option text = STRING_TOKEN(STR_DISABLE), value=0, flags=0 | RESET_REQUIRED;\r
+      endoneof;\r
+    endif;\r
+\r
+  endif;  //SATA enable\r
+\r
+endform;\r
+\r
+form formid = LPSS_CONFIGURATION_ID,\r
+\r
+  title    = STRING_TOKEN(STR_LPSS_SCC_FORM_TITLE);\r
+\r
+  subtitle text = STRING_TOKEN(STR_NULL_STRING);\r
+  oneof varid   = Setup.LpssPciModeEnabled,\r
+    prompt      = STRING_TOKEN(STR_LPSS_PCI_PROMPT),\r
+    help        = STRING_TOKEN(STR_LPSS_PCI_HELP),\r
+    option text = STRING_TOKEN(STR_ACPI_MODE), value=0, flags=DEFAULT | MANUFACTURING | RESET_REQUIRED;\r
+    option text = STRING_TOKEN(STR_PCI_MODE), value=1, flags=0| RESET_REQUIRED;\r
+  endoneof;\r
+  subtitle text = STRING_TOKEN(STR_NULL_STRING);\r
+\r
+  subtitle text = STRING_TOKEN(STR_SCC_SETTING_SUBTITLE);\r
+  oneof varid   = Setup.eMMCBootMode,\r
+    prompt      = STRING_TOKEN(STR_EMMC_BOOT_PROMPT),\r
+    help        = STRING_TOKEN(STR_EMMC_BOOT_HELP),\r
+    option text = STRING_TOKEN(STR_DISABLE), value=0, flags=0 | RESET_REQUIRED;\r
+    option text = STRING_TOKEN(STR_AUTO_DETECT), value=1, flags=DEFAULT | MANUFACTURING | RESET_REQUIRED;\r
+    option text = STRING_TOKEN(STR_EMMC_BOOT_41), value=2, flags=0 | RESET_REQUIRED;\r
+    option text = STRING_TOKEN(STR_EMMC_BOOT_45), value=3, flags=0 | RESET_REQUIRED;\r
+  endoneof;\r
+\r
+\r
+\r
+   oneof varid   = Setup.SecureErase,\r
+    questionid  = 0x1240,\r
+    prompt      = STRING_TOKEN(STR_SECURE_ERASE_PROMPT),\r
+    help        = STRING_TOKEN(STR_SECURE_ERASE_HELP),\r
+    flags       = INTERACTIVE,\r
+    option text = STRING_TOKEN(STR_DISABLE), value=0, flags= DEFAULT |MANUFACTURING | RESET_REQUIRED;\r
+    option text = STRING_TOKEN(STR_ENABLE), value=1, flags= RESET_REQUIRED;\r
+  endoneof;\r
+\r
+\r
+\r
+   subtitle text = STRING_TOKEN(STR_NULL_STRING);\r
+grayoutif NOT ideqval Setup.eMMCBootMode == 0x3;\r
+  oneof varid   = Setup.LpsseMMC45Enabled,\r
+    prompt      = STRING_TOKEN(STR_SCC_EMMC45_PROMPT),\r
+    help        = STRING_TOKEN(STR_SCC_EMMC45_HELP),\r
+    option text = STRING_TOKEN(STR_DISABLE), value=0, flags=0 | MANUFACTURING | RESET_REQUIRED;\r
+    option text = STRING_TOKEN(STR_ENABLE), value=1, flags=DEFAULT | RESET_REQUIRED;\r
+  endoneof;\r
+  oneof varid   = Setup.LpsseMMC45DDR50Enabled,\r
+    prompt      = STRING_TOKEN(STR_SCC_EMMC45_DDR50_PROMPT),\r
+    help        = STRING_TOKEN(STR_SCC_EMMC45_DDR50_HELP),\r
+    option text = STRING_TOKEN(STR_DISABLE), value=0, flags=0 | MANUFACTURING | RESET_REQUIRED;\r
+    option text = STRING_TOKEN(STR_ENABLE), value=1, flags=DEFAULT | RESET_REQUIRED;\r
+  endoneof;\r
+    oneof varid   = Setup.LpsseMMC45HS200Enabled,\r
+    prompt      = STRING_TOKEN(STR_SCC_EMMC45_HS200_PROMPT),\r
+    help        = STRING_TOKEN(STR_SCC_EMMC45_HS200_HELP),\r
+    option text = STRING_TOKEN(STR_DISABLE), value=0, flags=0 | MANUFACTURING | RESET_REQUIRED;\r
+    option text = STRING_TOKEN(STR_ENABLE), value=1, flags=DEFAULT| RESET_REQUIRED;\r
+  endoneof;\r
+\r
+  grayoutif ideqval Setup.LpsseMMC45DDR50Enabled == 0x1;\r
+  oneof varid  = Setup.LpsseMMC45RetuneTimerValue,\r
+    prompt = STRING_TOKEN(STR_SCC_EMMC45_RE_TUNE_TIMER_VALUE),\r
+    help   = STRING_TOKEN(STR_SCC_EMMC45_RE_TUNE_TIMER_VALUE_HELP),\r
+    option text = STRING_TOKEN(STR_EMMC45_TIMER_0), value = 0, flags = RESET_REQUIRED;\r
+    option text = STRING_TOKEN(STR_EMMC45_TIMER_1), value =1, flags = RESET_REQUIRED;\r
+    option text = STRING_TOKEN(STR_EMMC45_TIMER_2), value =2, flags = RESET_REQUIRED;\r
+    option text = STRING_TOKEN(STR_EMMC45_TIMER_3), value =3, flags = RESET_REQUIRED;\r
+    option text = STRING_TOKEN(STR_EMMC45_TIMER_4), value =4, flags = RESET_REQUIRED;\r
+    option text = STRING_TOKEN(STR_EMMC45_TIMER_5), value =5, flags = RESET_REQUIRED;\r
+    option text = STRING_TOKEN(STR_EMMC45_TIMER_6), value =6, flags = RESET_REQUIRED;\r
+    option text = STRING_TOKEN(STR_EMMC45_TIMER_7), value =7, flags = RESET_REQUIRED;\r
+    option text = STRING_TOKEN(STR_EMMC45_TIMER_8), value =8, flags = MANUFACTURING| DEFAULT|RESET_REQUIRED;\r
+    option text = STRING_TOKEN(STR_EMMC45_TIMER_9), value =9, flags = RESET_REQUIRED;\r
+    option text = STRING_TOKEN(STR_EMMC45_TIMER_10), value =10, flags = RESET_REQUIRED;\r
+    option text = STRING_TOKEN(STR_EMMC45_TIMER_11), value =11, flags = RESET_REQUIRED;\r
+    option text = STRING_TOKEN(STR_EMMC45_TIMER_12), value =12, flags = RESET_REQUIRED;\r
+    option text = STRING_TOKEN(STR_EMMC45_TIMER_13), value =13, flags = RESET_REQUIRED;\r
+    option text = STRING_TOKEN(STR_EMMC45_TIMER_14), value =14, flags = RESET_REQUIRED;\r
+    option text = STRING_TOKEN(STR_EMMC45_TIMER_15), value =15, flags = RESET_REQUIRED;\r
+  endoneof;\r
+  endif;    // grayoutif ideqval Setup.LpsseMMC45DDR50Enabled == 0x1;\r
+ endif;     // grayoutif NOT ideqval Setup.eMMCBootMode == 0x1;\r
+\r
+  subtitle text = STRING_TOKEN(STR_NULL_STRING);\r
+  subtitle text = STRING_TOKEN(STR_NULL_STRING);\r
+  oneof varid   = Setup.LpssSdioEnabled,\r
+    prompt      = STRING_TOKEN(STR_SCC_SDIO_PROMPT),\r
+    help        = STRING_TOKEN(STR_SCC_SDIO_HELP),\r
+    option text = STRING_TOKEN(STR_DISABLE), value=0, flags=0 | RESET_REQUIRED;\r
+    option text = STRING_TOKEN(STR_ENABLE), value=1, flags=DEFAULT | MANUFACTURING | RESET_REQUIRED;\r
+  endoneof;\r
+\r
+  oneof varid   = Setup.LpssSdcardEnabled,\r
+    prompt      = STRING_TOKEN(STR_SCC_SDCARD_PROMPT),\r
+    help        = STRING_TOKEN(STR_SCC_SDCARD_HELP),\r
+    option text = STRING_TOKEN(STR_DISABLE), value=0, flags=0 | RESET_REQUIRED;\r
+    option text = STRING_TOKEN(STR_ENABLE), value=1, flags= DEFAULT|MANUFACTURING | RESET_REQUIRED;\r
+  endoneof;\r
+\r
+\r
+grayoutif NOT ideqval Setup.LpssSdcardEnabled == 0x1;\r
+  grayoutif ideqval Setup.LpssSdCardDDR50Enabled == 0x1;\r
+  oneof varid   = Setup.LpssSdCardSDR25Enabled,\r
+    prompt      = STRING_TOKEN(STR_SCC_SD_SDR25_PROMPT),\r
+    help        = STRING_TOKEN(STR_SCC_SD_SDR25_HELP),\r
+    option text = STRING_TOKEN(STR_DISABLE), value=0, flags=DEFAULT | MANUFACTURING | RESET_REQUIRED;\r
+    option text = STRING_TOKEN(STR_ENABLE), value=1, flags=0 | RESET_REQUIRED;\r
+  endoneof;\r
+  endif; // grayoutif ideqval Setup.LpsseMMC45DDR50Enabled == 0x1;\r
+\r
+  grayoutif ideqval Setup.LpssSdCardSDR25Enabled == 0x1;\r
+    oneof varid   = Setup.LpssSdCardDDR50Enabled,\r
+    prompt      = STRING_TOKEN(STR_SCC_SD_DDR50_PROMPT),\r
+    help        = STRING_TOKEN(STR_SCC_SD_DDR50_HELP),\r
+    option text = STRING_TOKEN(STR_DISABLE), value=0, flags=DEFAULT | MANUFACTURING | RESET_REQUIRED;\r
+    option text = STRING_TOKEN(STR_ENABLE), value=1, flags=0 | RESET_REQUIRED;\r
+    endoneof;\r
+  endif; // grayoutif ideqval Setup.LpssSdCardSDR25Enabled == 0x1;\r
+\r
+  oneof varid   = Setup.SdCardRemovable,\r
+    prompt      = STRING_TOKEN(STR_SCC_SDCARD_REMOVABILITY),\r
+    help        = STRING_TOKEN(STR_SCC_SDCARD_REMOVABILITY_HELP),\r
+    option text = STRING_TOKEN(STR_SCC_SDCARD_NON_REMOVABLE), value=0, flags=0 | RESET_REQUIRED;\r
+    option text = STRING_TOKEN(STR_SCC_SDCARD_REMOVABLE), value=1, flags=DEFAULT | MANUFACTURING | RESET_REQUIRED;\r
+  endoneof;\r
+\r
+endif;     // grayoutif NOT ideqval Setup.LpssSdcardEnabled == 0x1;\r
+\r
+\r
+\r
+  subtitle text = STRING_TOKEN(STR_NULL_STRING);\r
+\r
+  subtitle text = STRING_TOKEN(STR_LPSS1_SETTING_SUBTITLE);\r
+\r
+  oneof varid   = Setup.LpssDma0Enabled,\r
+    prompt      = STRING_TOKEN(STR_LPSS_DMA1_PROMPT),\r
+    help        = STRING_TOKEN(STR_LPSS_DMA1_HELP),\r
+    flags       = INTERACTIVE,\r
+    option text = STRING_TOKEN(STR_DISABLE), value=0, flags=0 | RESET_REQUIRED;\r
+    option text = STRING_TOKEN(STR_ENABLE), value=1, flags= DEFAULT | MANUFACTURING | RESET_REQUIRED;\r
+  endoneof;\r
+\r
+  grayoutif ideqval Setup.LpssDma0Enabled == 0x00;\r
+  oneof varid   = Setup.LpssHsuart0Enabled,\r
+    prompt      = STRING_TOKEN(STR_LPSS_HSUART1_PROMPT),\r
+    help        = STRING_TOKEN(STR_LPSS_HSUART1_HELP_ENBDT_DEV_LIST),\r
+    option text = STRING_TOKEN(STR_DISABLE), value=0, flags= MANUFACTURING  | RESET_REQUIRED;\r
+    option text = STRING_TOKEN(STR_ENABLE), value=1, flags= 0 | DEFAULT | RESET_REQUIRED;\r
+  endoneof;\r
+  endif;\r
+\r
+  //Add control flow\r
+  grayoutif ideqval Setup.LpssHsuart0Enabled == 0x00;\r
+  oneof varid   = Setup.LpssHsuart0FlowControlEnabled,\r
+    prompt      = STRING_TOKEN(STR_LPSS_HSUART1_FLOWCONTROL_PROMPT),\r
+    help        = STRING_TOKEN(STR_LPSS_HSUART1_HELP_ENBDT_DEV_LIST),\r
+    option text = STRING_TOKEN(STR_DISABLE), value=0, flags=0 |DEFAULT | RESET_REQUIRED;\r
+    option text = STRING_TOKEN(STR_ENABLE), value=1, flags= MANUFACTURING  | RESET_REQUIRED;\r
+  endoneof;\r
+  endif;\r
+\r
+  grayoutif ideqval Setup.LpssDma0Enabled == 0x00;\r
+  oneof varid   = Setup.LpssHsuart1Enabled,\r
+    prompt      = STRING_TOKEN(STR_LPSS_HSUART2_PROMPT),\r
+    help        = STRING_TOKEN(STR_LPSS_HSUART2_HELP_ENBDT_DEV_LIST),\r
+    option text = STRING_TOKEN(STR_DISABLE), value=0, flags=MANUFACTURING  | RESET_REQUIRED;\r
+    option text = STRING_TOKEN(STR_ENABLE), value=1, flags= 0 | DEFAULT | RESET_REQUIRED;\r
+  endoneof;\r
+  endif;\r
+\r
+  //Add control flow\r
+  grayoutif ideqval Setup.LpssHsuart1Enabled == 0x00;\r
+  oneof varid   = Setup.LpssHsuart1FlowControlEnabled,\r
+    prompt      = STRING_TOKEN(STR_LPSS_HSUART2_FLOWCONTROL_PROMPT),\r
+    help        = STRING_TOKEN(STR_LPSS_HSUART1_HELP_ENBDT_DEV_LIST),\r
+    option text = STRING_TOKEN(STR_DISABLE), value=0, flags=0 |DEFAULT | RESET_REQUIRED;\r
+    option text = STRING_TOKEN(STR_ENABLE), value=1, flags= MANUFACTURING  | RESET_REQUIRED;\r
+  endoneof;\r
+  endif;\r
+\r
+\r
+  grayoutif ideqval Setup.LpssDma0Enabled == 0x00;\r
+  oneof varid   = Setup.LpssPwm0Enabled,\r
+    prompt      = STRING_TOKEN(STR_PWM1_PROMPT),\r
+    help        = STRING_TOKEN(STR_PWM1_HELP),\r
+    option text = STRING_TOKEN(STR_DISABLE), value=0, flags=MANUFACTURING  | RESET_REQUIRED;\r
+    option text = STRING_TOKEN(STR_ENABLE), value=1, flags= 0 | DEFAULT | RESET_REQUIRED;\r
+  endoneof;\r
+  endif;\r
+\r
+  grayoutif ideqval Setup.LpssDma0Enabled == 0x00;\r
+  oneof varid   = Setup.LpssPwm1Enabled,\r
+    prompt      = STRING_TOKEN(STR_PWM2_PROMPT),\r
+    help        = STRING_TOKEN(STR_PWM2_HELP),\r
+    option text = STRING_TOKEN(STR_DISABLE), value=0, flags=MANUFACTURING  | RESET_REQUIRED;\r
+    option text = STRING_TOKEN(STR_ENABLE), value=1, flags= 0 | DEFAULT | RESET_REQUIRED;\r
+  endoneof;\r
+  endif;\r
+\r
+  grayoutif ideqval Setup.LpssDma0Enabled == 0x00;\r
+  oneof varid   = Setup.LpssSpiEnabled,\r
+    prompt      = STRING_TOKEN(STR_LPSS_SPI_PROMPT),\r
+    help        = STRING_TOKEN(STR_LPSS_SPI_HELP),\r
+    option text = STRING_TOKEN(STR_DISABLE), value=0, flags=MANUFACTURING  | RESET_REQUIRED;\r
+    option text = STRING_TOKEN(STR_ENABLE), value=1, flags= 0 |DEFAULT | RESET_REQUIRED;\r
+  endoneof;\r
+  endif;\r
+\r
+  subtitle text = STRING_TOKEN(STR_NULL_STRING);\r
+\r
+  subtitle text = STRING_TOKEN(STR_LPSS2_SETTING_SUBTITLE);\r
+\r
+  oneof varid   = Setup.LpssDma1Enabled,\r
+    prompt      = STRING_TOKEN(STR_LPSS_DMA2_PROMPT),\r
+    help        = STRING_TOKEN(STR_LPSS_DMA2_HELP),\r
+    flags       = INTERACTIVE,\r
+    option text = STRING_TOKEN(STR_DISABLE), value=0, flags=0 |RESET_REQUIRED;\r
+    option text = STRING_TOKEN(STR_ENABLE), value=1, flags= DEFAULT | MANUFACTURING | RESET_REQUIRED;\r
+  endoneof;\r
+\r
+/*\r
+  grayoutif ideqval Setup.LpssDma1Enabled == 0x00;\r
+  oneof varid   = Setup.LpssI2C0Enabled,\r
+    prompt      = STRING_TOKEN(STR_LPSS_I2C1_PROMPT),\r
+    help        = STRING_TOKEN(STR_LPSS_I2C1_HELP_ENBDT_DEV_LIST),\r
+    option text = STRING_TOKEN(STR_DISABLE), value=0, flags=0 |DEFAULT |RESET_REQUIRED;\r
+    option text = STRING_TOKEN(STR_ENABLE), value=1, flags= MANUFACTURING | RESET_REQUIRED;\r
+  endoneof;\r
+  endif;\r
+\r
+\r
+  grayoutif ideqval Setup.LpssDma1Enabled == 0x00;\r
+  oneof varid   = Setup.LpssI2C1Enabled,\r
+    prompt      = STRING_TOKEN(STR_LPSS_I2C2_PROMPT),\r
+    help        = STRING_TOKEN(STR_LPSS_I2C2_HELP_ENBDT_DEV_LIST),\r
+    option text = STRING_TOKEN(STR_DISABLE), value=0, flags=0 |DEFAULT | RESET_REQUIRED;\r
+    option text = STRING_TOKEN(STR_ENABLE), value=1, flags= MANUFACTURING | RESET_REQUIRED;\r
+  endoneof;\r
+  endif;\r
+\r
+  grayoutif ideqval Setup.LpssDma1Enabled == 0x00;\r
+  oneof varid   = Setup.LpssI2C2Enabled,\r
+    prompt      = STRING_TOKEN(STR_LPSS_I2C3_PROMPT),\r
+    help        = STRING_TOKEN(STR_LPSS_I2C3_HELP_ENBDT_DEV_LIST),\r
+    option text = STRING_TOKEN(STR_DISABLE), value=0, flags=0 |DEFAULT | RESET_REQUIRED;\r
+    option text = STRING_TOKEN(STR_ENABLE), value=1, flags= MANUFACTURING | RESET_REQUIRED;\r
+  endoneof;\r
+  endif;\r
+\r
+  grayoutif ideqval Setup.LpssDma1Enabled == 0x00;\r
+  oneof varid   = Setup.LpssI2C3Enabled,\r
+    prompt      = STRING_TOKEN(STR_LPSS_I2C4_PROMPT),\r
+    help        = STRING_TOKEN(STR_LPSS_I2C4_HELP_ENBDT_DEV_LIST),\r
+    option text = STRING_TOKEN(STR_DISABLE), value=0, flags=0 |DEFAULT | RESET_REQUIRED;\r
+    option text = STRING_TOKEN(STR_ENABLE), value=1, flags= MANUFACTURING | RESET_REQUIRED;\r
+  endoneof;\r
+  endif;\r
+\r
+  grayoutif ideqval Setup.LpssDma1Enabled == 0x00;\r
+  oneof varid   = Setup.LpssI2C4Enabled,\r
+    prompt      = STRING_TOKEN(STR_LPSS_I2C5_PROMPT),\r
+    help        = STRING_TOKEN(STR_LPSS_I2C5_HELP_ENBDT_DEV_LIST),\r
+    option text = STRING_TOKEN(STR_DISABLE), value=0, flags=0 |DEFAULT | RESET_REQUIRED;\r
+    option text = STRING_TOKEN(STR_ENABLE), value=1, flags= MANUFACTURING | RESET_REQUIRED;\r
+  endoneof;\r
+  endif;\r
+*/\r
+  grayoutif ideqval Setup.LpssDma1Enabled == 0x00;\r
+  oneof varid   = Setup.LpssI2C5Enabled,\r
+    prompt      = STRING_TOKEN(STR_LPSS_I2C6_PROMPT),\r
+    help        = STRING_TOKEN(STR_LPSS_I2C6_HELP_ENBDT_DEV_LIST),\r
+    option text = STRING_TOKEN(STR_DISABLE), value=0, flags=0 |RESET_REQUIRED;\r
+    option text = STRING_TOKEN(STR_ENABLE), value=1, flags=  DEFAULT |MANUFACTURING | RESET_REQUIRED;\r
+  endoneof;\r
+  endif;\r
+\r
+  grayoutif ideqval Setup.LpssDma1Enabled == 0x00;\r
+  oneof varid   = Setup.LpssI2C6Enabled,\r
+    prompt      = STRING_TOKEN(STR_LPSS_I2C7_PROMPT),\r
+    help        = STRING_TOKEN(STR_LPSS_I2C7_HELP_ENBDT_DEV_LIST),\r
+    option text = STRING_TOKEN(STR_DISABLE), value=0, flags=0 |RESET_REQUIRED;\r
+    option text = STRING_TOKEN(STR_ENABLE), value=1, flags= DEFAULT | MANUFACTURING | RESET_REQUIRED;\r
+  endoneof;\r
+  endif;\r
+\r
+  subtitle text = STRING_TOKEN(STR_NULL_STRING);\r
+\r
+  subtitle text = STRING_TOKEN(STR_I2C_DEVICE_SETTING_SUBTITLE);\r
+\r
+  oneof varid   = Setup.I2CTouchAd,\r
+    prompt      = STRING_TOKEN(STR_I2C_TOUCH_PROMPT),\r
+    help        = STRING_TOKEN(STR_I2C_TOUCH_HELP),\r
+    option text = STRING_TOKEN(STR_AUTO), value=0, flags=DEFAULT | MANUFACTURING | RESET_REQUIRED;\r
+    option text = STRING_TOKEN(STR_I2C_FVP), value=0x4B, flags=0 | RESET_REQUIRED;\r
+    option text = STRING_TOKEN(STR_I2C_FFRD), value=0x4A, flags=0 | RESET_REQUIRED;\r
+  endoneof;\r
+\r
+ subtitle text = STRING_TOKEN(STR_NULL_STRING);\r
+\r
+ oneof varid = Setup.SAR1,\r
+    prompt         = STRING_TOKEN(STR_SAR_SENSOR_PROMPT),\r
+    help           = STRING_TOKEN(STR_SAR_SENSOR_HELP),\r
+    option text    = STRING_TOKEN(STR_ENABLE), value = 1, flags = DEFAULT | MANUFACTURING |RESET_REQUIRED;\r
+    option text    = STRING_TOKEN(STR_DISABLE), value = 0, flags = RESET_REQUIRED;\r
+  endoneof;\r
+endform;\r
+\r
+\r
+//\r
+//LAN Controller\r
+//\r
+form formid = LAN_OPTIONS_FORM_ID,\r
+\r
+  title    = STRING_TOKEN(STR_LAN_OPTIONS_FORM_TITLE);\r
+\r
+  subtitle text = STRING_TOKEN(STR_LAN_OPTIONS_FORM_TITLE);\r
+\r
+  oneof varid = Setup.Lan,\r
+    prompt   = STRING_TOKEN(STR_PCH_LAN_CONTROLLER),\r
+    help     = STRING_TOKEN(STR_PCH_LAN_CONTROLLER_HELP),\r
+    option text = STRING_TOKEN(STR_ENABLE), value = 1, flags = RESET_REQUIRED;\r
+    option text = STRING_TOKEN(STR_DISABLE), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED;\r
+  endoneof;\r
+\r
+  suppressif ideqval Setup.Lan == 0;\r
+    oneof varid = Setup.WakeOnLanS5,\r
+      prompt   = STRING_TOKEN(STR_PCH_LAN_WOL_PROMPT),\r
+      help     = STRING_TOKEN(STR_PCH_LAN_WOL_HELP),\r
+      option text = STRING_TOKEN(STR_ENABLE), value = 1, flags =  DEFAULT | MANUFACTURING | RESET_REQUIRED;\r
+      option text = STRING_TOKEN(STR_DISABLE), value = 0, flags = RESET_REQUIRED;\r
+    endoneof;\r
+\r
+    oneof varid = Setup.SlpLanLowDc,\r
+      prompt   = STRING_TOKEN(STR_PCH_SLP_LAN_LOW_DC_PROMPT),\r
+      help     = STRING_TOKEN(STR_PCH_SLP_LAN_LOW_DC_HELP),\r
+      option text = STRING_TOKEN(STR_ENABLE), value = 1, flags =  DEFAULT | MANUFACTURING | RESET_REQUIRED;\r
+      option text = STRING_TOKEN(STR_DISABLE), value = 0, flags = RESET_REQUIRED;\r
+    endoneof;\r
+\r
+    oneof varid = Setup.BootNetwork,\r
+      prompt   = STRING_TOKEN(STR_PCH_PXEROM_CONTROL),\r
+      help     = STRING_TOKEN(STR_PCH_PXEROM_CONTROL_HELP),\r
+      option text = STRING_TOKEN(STR_ENABLE), value = 1, flags =  RESET_REQUIRED;\r
+      option text = STRING_TOKEN(STR_DISABLE), value = 0, flags = DEFAULT | MANUFACTURING |RESET_REQUIRED;\r
+    endoneof;\r
+  endif;\r
+\r
+endform;\r
+\r
+//\r
+// Azalia Configuration\r
+//\r
+form formid = AZALIA_OPTIONS_FORM_ID,\r
+\r
+  title    = STRING_TOKEN(STR_AZALIA_OPTIONS_FORM_TITLE);\r
+\r
+  subtitle text = STRING_TOKEN(STR_AZALIA_OPTIONS_FORM_TITLE);\r
+  oneof varid   = Setup.Lpe,\r
+      prompt      = STRING_TOKEN(STR_LPE_PROMPT),\r
+      help        = STRING_TOKEN(STR_LPE_HELP),\r
+      option text = STRING_TOKEN(STR_DISABLE), value=0, flags=DEFAULT | MANUFACTURING | RESET_REQUIRED;\r
+      option text = STRING_TOKEN(STR_LPE_PCI_MODE), value=1, flags=0 | RESET_REQUIRED;\r
+      option text = STRING_TOKEN(STR_LPE_ACPI_MODE), value=2, flags=0 | RESET_REQUIRED;\r
+  endoneof;\r
+\r
+  subtitle text = STRING_TOKEN(STR_NULL_STRING);\r
+  suppressif ideqval Setup.AzaliaDs == 0x1;\r
+    oneof varid  = Setup.PchAzalia,\r
+      prompt   = STRING_TOKEN(STR_PCH_AZALIA_PROMPT),\r
+      help     = STRING_TOKEN(STR_PCH_AZALIA_HELP),\r
+      option text = STRING_TOKEN(STR_DISABLE), value = 0, flags = 0 | RESET_REQUIRED;\r
+      option text = STRING_TOKEN(STR_ENABLE), value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED;\r
+    endoneof;\r
+  endif;\r
+\r
+  suppressif ideqval Setup.AzaliaDs == 0x0;\r
+    text\r
+      help   = STRING_TOKEN(STR_PCH_AZALIA_DS_SUPPORT),\r
+      text   = STRING_TOKEN(STR_PCH_AZALIA_PROMPT),\r
+      text   = STRING_TOKEN(STR_ENABLE),\r
+      flags  = 0,\r
+      key    = 0;\r
+  endif;\r
+\r
+  suppressif ideqval Setup.PchAzalia == 0x0;\r
+    oneof varid  = Setup.AzaliaVCiEnable,\r
+      prompt   = STRING_TOKEN(STR_AZALIA_VC_PROMPT),\r
+      help     = STRING_TOKEN(STR_AZALIA_VC_HELP),\r
+      option text = STRING_TOKEN(STR_DISABLE), value = 0, flags = RESET_REQUIRED;\r
+      option text = STRING_TOKEN(STR_ENABLE), value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED;\r
+    endoneof;\r
+  endif;\r
+\r
+  suppressif ideqval Setup.PchAzalia == 0x0;\r
+    oneof varid  = Setup.AzaliaDs,\r
+      prompt   = STRING_TOKEN(STR_AZALIA_DS_PROMPT),\r
+      help     = STRING_TOKEN(STR_AZALIA_DS_HELP),\r
+      option text = STRING_TOKEN(STR_DISABLE), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED;\r
+      option text = STRING_TOKEN(STR_ENABLE), value = 1, flags = RESET_REQUIRED;\r
+    endoneof;\r
+  endif;\r
+\r
+  suppressif ideqval Setup.PchAzalia == 0x0;\r
+    oneof varid  = Setup.AzaliaPme,\r
+      prompt   = STRING_TOKEN(STR_AZALIA_PME_PROMPT),\r
+      help     = STRING_TOKEN(STR_AZALIA_PME_HELP),\r
+      option text = STRING_TOKEN(STR_DISABLE), value = 0, flags = RESET_REQUIRED;\r
+      option text = STRING_TOKEN(STR_ENABLE), value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED;\r
+    endoneof;\r
+\r
+    oneof varid  = Setup.HdmiCodec,\r
+      prompt   = STRING_TOKEN(STR_HDMI_CODEC_PROMPT),\r
+      help     = STRING_TOKEN(STR_HDMI_CODEC_HELP),\r
+      option text = STRING_TOKEN(STR_DISABLE), value = 0, flags = RESET_REQUIRED;\r
+      option text = STRING_TOKEN(STR_ENABLE), value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED;\r
+    endoneof;\r
+  endif;\r
+\r
+endform;\r
+\r
+//\r
+//  Misc Configuration\r
+//\r
+form formid = MISC_OPTIONS_FORM_ID,\r
+\r
+  title    = STRING_TOKEN(STR_MISC_OPTION_FORM_TITLE);\r
+\r
+  subtitle text = STRING_TOKEN(STR_MISC_OPTION_FORM_TITLE);\r
+  //\r
+  // HPET Disable/Enable\r
+  //\r
+  oneof   varid   = Setup.Hpet,\r
+    prompt      = STRING_TOKEN(STR_HPET_PROMPT),\r
+    help        = STRING_TOKEN(STR_HPET_HELP),\r
+    option text = STRING_TOKEN(STR_DISABLE), value=0x00, flags=RESET_REQUIRED;\r
+    option text = STRING_TOKEN(STR_ENABLE), value=0x01, flags=DEFAULT | RESET_REQUIRED;\r
+  endoneof;\r
+\r
+  oneof varid  = Setup.StateAfterG3,\r
+     prompt   = STRING_TOKEN(STR_STATE_AFTER_G3),\r
+     help     = STRING_TOKEN(STR_STATE_AFTER_G3_HELP),\r
+     option text = STRING_TOKEN(STR_S0_AFTER_G3_STRING), value = 0, flags = DEFAULT | RESET_REQUIRED;\r
+     option text = STRING_TOKEN(STR_S5_AFTER_G3_STRING), value = 1, flags = MANUFACTURING | RESET_REQUIRED;\r
+  endoneof;\r
+\r
+  oneof varid  = Setup.EnableClockSpreadSpec,\r
+     prompt   = STRING_TOKEN(STR_CLOCK_SPREAD_SPEC_ENABLE),\r
+     help     = STRING_TOKEN(STR_CLOCK_SPREAD_SPEC_ENABLE_HELP),\r
+     option text = STRING_TOKEN(STR_DISABLE), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED;\r
+     option text = STRING_TOKEN(STR_ENABLE), value = 1, flags = RESET_REQUIRED;\r
+  endoneof;\r
+\r
+\r
+  oneof varid  = Setup.UartInterface,\r
+    prompt   = STRING_TOKEN(STR_PCH_UART_SELECT),\r
+    help     = STRING_TOKEN(STR_PCH_UART_SELECT_HELP),\r
+    option text = STRING_TOKEN(STR_UART_SELECT_PCU), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED;\r
+    option text = STRING_TOKEN(STR_UART_SELECT_SIO), value = 1, flags = RESET_REQUIRED;\r
+  endoneof;\r
+\r
+  suppressif ideqval Setup.LpssHsuart0Enabled == 1 OR ideqval Setup.UartInterface == 1;\r
+    oneof varid  = Setup.PcuUart1,\r
+      prompt   = STRING_TOKEN(STR_PCU_UART_A),\r
+      help     = STRING_TOKEN(STR_PCU_UART_A_HELP),\r
+      option text = STRING_TOKEN(STR_DISABLE), value = 0, flags = RESET_REQUIRED;\r
+      option text = STRING_TOKEN(STR_ENABLE), value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED;\r
+    endoneof;\r
+  endif;\r
+\r
+  oneof varid = Setup.SpiRwProtect,\r
+    prompt         = STRING_TOKEN(STR_PCH_SPI_WP_PROMPT),\r
+    help           = STRING_TOKEN(STR_PCH_SPI_WP_HELP),\r
+    option text    = STRING_TOKEN(STR_PCH_SPI_WP_DISABLE), value = 0, flags = DEFAULT | MANUFACTURING |RESET_REQUIRED;\r
+    option text    = STRING_TOKEN(STR_PCH_SPI_WP_ENABLE), value = 1, flags = RESET_REQUIRED;\r
+  endoneof;\r
+\r
+  oneof varid = Setup.MmioSize,\r
+    prompt         = STRING_TOKEN(STR_MMIO_PROMPT),\r
+    help           = STRING_TOKEN(STR_MMIO_HELP),\r
+    option text    = STRING_TOKEN(STR_MMIO_0_75G_STRING), value = 0, flags = RESET_REQUIRED;\r
+    option text    = STRING_TOKEN(STR_MMIO_1G_STRING), value = 1, flags = RESET_REQUIRED;\r
+    option text    = STRING_TOKEN(STR_MMIO_1_25G_STRING), value = 2, flags = RESET_REQUIRED;\r
+    option text    = STRING_TOKEN(STR_MMIO_1_5G_STRING), value = 3, flags = RESET_REQUIRED;\r
+    option text    = STRING_TOKEN(STR_MMIO_2G_STRING), value = 4, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED;\r
+  endoneof;\r
+\r
+  oneof varid = Setup.PcieDynamicGating,\r
+    prompt         = STRING_TOKEN(STR_PCIEDYNCLK_PROMPT),\r
+    help           = STRING_TOKEN(STR_PCIEDYNCLK_HELP),\r
+    option text    = STRING_TOKEN(STR_DISABLE), value = 0, flags = DEFAULT | MANUFACTURING |RESET_REQUIRED;\r
+    option text    = STRING_TOKEN(STR_ENABLE), value = 1, flags = RESET_REQUIRED;\r
+  endoneof;\r
+\r
+  oneof varid = Setup.GpioWakeCapability,\r
+    prompt         = STRING_TOKEN(STR_GPIO_WAKE_CAPABILITY_ENABLE),\r
+    help           = STRING_TOKEN(STR_GPIO_WAKE_CAPABILITY_ENABLE_HELP),\r
+    option text    = STRING_TOKEN(STR_DISABLE), value = 0, flags = DEFAULT | MANUFACTURING |RESET_REQUIRED;\r
+    option text    = STRING_TOKEN(STR_ENABLE), value = 1, flags = RESET_REQUIRED;\r
+  endoneof;\r
+endform;\r

diff --git a/Vlv2TbltDevicePkg/PlatformSetupDxe/SystemComponent.vfi b/Vlv2TbltDevicePkg/PlatformSetupDxe/SystemComponent.vfi
new file mode 100644 (file)
index 0000000..e21f880
--- /dev/null
+++ b/Vlv2TbltDevicePkg/PlatformSetupDxe/SystemComponent.vfi
@@ -0,0 +1,86 @@
+//\r
+//\r
+// Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+//                                                                                  \r\r
+// This program and the accompanying materials are licensed and made available under\r\r
+// the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+// The full text of the license may be found at                                     \r\r
+// http://opensource.org/licenses/bsd-license.php.                                  \r\r
+//                                                                                  \r\r
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+//                                                                                  \r\r
+//\r
+//\r
+//\r
+// Module Name:\r
+//\r
+//   SystemComponent.vfr\r
+//\r
+// Abstract:\r
+//\r
+//   Driver Setup formset.\r
+//\r
+// Revision History:\r
+//   ------------------------------------------------------------------------------\r
+//   Rev   Date<MM/DD/YYYY>    Name    Description\r
+//   ------------------------------------------------------------------------------\r
+\r
+// --*/\r
+\r
+form formid = SYSTEM_COMPONENT_FORM_ID,\r
+\r
+  title  = STRING_TOKEN(STR_SYSTEM_COMPONENT_TITLE);\r
+/*\r
+  oneof   varid   = Setup.CRIDSettings,\r
+    prompt      = STRING_TOKEN(STR_CRID_PROMPT),\r
+    help        = STRING_TOKEN(STR_CRID_SETTING_HELP),\r
+    option text = STRING_TOKEN(STR_DISABLE), value = 0, flags = MANUFACTURING | DEFAULT | RESET_REQUIRED;\r
+    option text = STRING_TOKEN(STR_CRID_0_STRING),  value = 1, flags = RESET_REQUIRED;\r
+    option text = STRING_TOKEN(STR_CRID_1_STRING),  value = 2, flags = RESET_REQUIRED;\r
+    option text = STRING_TOKEN(STR_CRID_2_STRING),  value = 3, flags = RESET_REQUIRED;\r
+  endoneof;\r
+*/\r
+\r
+  subtitle text = STRING_TOKEN(STR_PNP_CONFIGURATION_TITLE);\r
+  oneof   varid   = Setup.PnpSettings,\r
+    prompt      = STRING_TOKEN(STR_PNP_SETTING_PROMPT),\r
+    help        = STRING_TOKEN(STR_PNP_SETTING_HELP),\r
+    option text = STRING_TOKEN(STR_DISABLE), value = 0, flags = RESET_REQUIRED;\r
+#if (PNP_DEBUG == 1)\r
+    option text = STRING_TOKEN(STR_PNP_POWER_STRING),  value = 1, flags = RESET_REQUIRED;\r
+    option text = STRING_TOKEN(STR_PNP_PERFORMANCE_STRING),  value = 2, flags = RESET_REQUIRED;\r
+#endif\r
+    option text = STRING_TOKEN(STR_PNP_POWER_PERFORMANCE_STRING), value = 3, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED;\r
+    option text = STRING_TOKEN(STR_PNP_POWER_PERFORMANCE_STRING_A0), value = 4, flags = 0 | RESET_REQUIRED;\r
+    option text = STRING_TOKEN(STR_PNP_POWER_PERFORMANCE_STRING_B0), value = 5, flags = 0 | RESET_REQUIRED;\r
+  endoneof;\r
+\r
+  oneof   varid   = Setup.CfioPnpSettings,\r
+    prompt      = STRING_TOKEN(STR_CFIO_PNP_SETTING_PROMPT),\r
+    help        = STRING_TOKEN(STR_CFIO_PNP_SETTING_HELP),\r
+    option text = STRING_TOKEN(STR_DISABLE), value = 0, flags = MANUFACTURING | DEFAULT | RESET_REQUIRED;\r
+    option text = STRING_TOKEN(STR_ENABLE), value = 1, flags = 0 | RESET_REQUIRED;\r
+  endoneof;\r
+ oneof   varid   = Setup.TristateLpc,\r
+    prompt      = STRING_TOKEN(STR_TRISTATE_LPC_PROMPT),\r
+    help        = STRING_TOKEN(STR_TRISTATE_LPC_HELP),\r
+    option text = STRING_TOKEN(STR_DISABLE), value = 0, flags = MANUFACTURING | DEFAULT | RESET_REQUIRED;\r
+    option text = STRING_TOKEN(STR_ENABLE), value = 1, flags = 0 | RESET_REQUIRED;\r
+  endoneof;\r
+\r
+\r
+\r
+\r
+\r
+\r
+  oneof varid   = Setup.PchFSAOn,\r
+    prompt      = STRING_TOKEN(STR_PCH_FSA_PROMPT),\r
+    help        = STRING_TOKEN(STR_PCH_FSA_HELP),\r
+    option text = STRING_TOKEN(STR_OFF), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED;\r
+    option text = STRING_TOKEN(STR_ON), value = 1, flags = RESET_REQUIRED;\r
+  endoneof;\r
+\r
+\r
+\r
+endform;\r

diff --git a/Vlv2TbltDevicePkg/PlatformSetupDxe/Thermal.vfi b/Vlv2TbltDevicePkg/PlatformSetupDxe/Thermal.vfi
new file mode 100644 (file)
index 0000000..a6531f9
--- /dev/null
+++ b/Vlv2TbltDevicePkg/PlatformSetupDxe/Thermal.vfi
@@ -0,0 +1,83 @@
+//\r
+//\r
+// Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+//                                                                                  \r\r
+// This program and the accompanying materials are licensed and made available under\r\r
+// the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+// The full text of the license may be found at                                     \r\r
+// http://opensource.org/licenses/bsd-license.php.                                  \r\r
+//                                                                                  \r\r
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+//                                                                                  \r\r
+//\r
+//\r
+//\r
+// Module Name:\r
+//\r
+//   DPTF.vfr\r
+//\r
+// Abstract:\r
+//\r
+//   Driver Setup formset.\r
+//\r
+// Revision History:\r
+//   ------------------------------------------------------------------------------\r
+//   Rev   Date<MM/DD/YYYY>    Name    Description\r
+//   ------------------------------------------------------------------------------\r
+\r
+// --*/\r
+\r
+form formid = THERMAL_FORM_ID,\r
+\r
+  title  = STRING_TOKEN(STR_THERMAL_TITLE);\r
+\r
+  subtitle text = STRING_TOKEN(STR_THERMAL_CONFIGURATION);\r
+\r
+\r
+  suppressif TRUE;\r
+    numeric varid = Setup.PassiveTc1Value,\r
+      prompt  = STRING_TOKEN (STR_ACPI_PASSIVE_TC1_VALUE),\r
+      help    = STRING_TOKEN (STR_ACPI_PASSIVE_TC1_VALUE_HELP),\r
+      flags   = 0 | RESET_REQUIRED,\r
+      minimum = 1,\r
+      maximum = 16,\r
+      step    = 1,\r
+      default = 1,\r
+    endnumeric;\r
+\r
+    numeric varid = Setup.PassiveTc2Value,\r
+      prompt  = STRING_TOKEN (STR_ACPI_PASSIVE_TC2_VALUE),\r
+      help    = STRING_TOKEN (STR_ACPI_PASSIVE_TC2_VALUE_HELP),\r
+      flags   = 0 | RESET_REQUIRED,\r
+      minimum = 1,\r
+      maximum = 16,\r
+      step    = 1,\r
+      default = 5,\r
+    endnumeric;\r
+\r
+    numeric varid = Setup.PassiveTspValue,\r
+      prompt  = STRING_TOKEN (STR_ACPI_PASSIVE_TSP_VALUE),\r
+      help    = STRING_TOKEN (STR_ACPI_PASSIVE_TSP_VALUE_HELP),\r
+      flags   = 0 | RESET_REQUIRED,\r
+      minimum = 2,\r
+      maximum = 50,\r
+      step    = 2,\r
+      default = 50,\r
+    endnumeric;\r
+  endif;\r
+\r
+  subtitle text = STRING_TOKEN(STR_NULL_STRING);\r
+\r
+  oneof varid    = Setup.DisableActiveTripPoints,\r
+        prompt      = STRING_TOKEN(STR_DATP_PROMPT),\r
+        help        = STRING_TOKEN(STR_DATP_HELP),\r
+        option text = STRING_TOKEN(STR_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED;\r
+        option text = STRING_TOKEN(STR_ENABLED),  value = 1, flags = RESET_REQUIRED;\r
+  endoneof;\r
+\r
+  subtitle text = STRING_TOKEN(STR_NULL_STRING);\r
+\r
+\r
+\r
+endform;\r

diff --git a/Vlv2TbltDevicePkg/PlatformSetupDxe/UnCore.vfi b/Vlv2TbltDevicePkg/PlatformSetupDxe/UnCore.vfi
new file mode 100644 (file)
index 0000000..2184a42
--- /dev/null
+++ b/Vlv2TbltDevicePkg/PlatformSetupDxe/UnCore.vfi
@@ -0,0 +1,240 @@
+//\r
+//\r
+// Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+//                                                                                  \r\r
+// This program and the accompanying materials are licensed and made available under\r\r
+// the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+// The full text of the license may be found at                                     \r\r
+// http://opensource.org/licenses/bsd-license.php.                                  \r\r
+//                                                                                  \r\r
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+//                                                                                  \r\r
+//\r
+//\r
+//\r
+// Module Name:\r
+//\r
+//   UncoreConfiguration.vfi\r
+//\r
+// Abstract:\r
+//\r
+//   Driver Setup formset.\r
+//\r
+\r
+\r
+// --*/\r
+\r
+form formid = UNCORE_FORM_ID,\r
+  title    = STRING_TOKEN(STR_UNCORE_CONFIGURATION_TITLE);\r
+\r
+  subtitle text = STRING_TOKEN(STR_GOP_TITLE);\r
+\r
+  oneof varid    = Setup.GOPEnable,\r
+    prompt   = STRING_TOKEN(STR_GOP_VBIOS_SWITCH),\r
+    help     = STRING_TOKEN(STR_GOP_VBIOS_SWITCH_HELP),\r
+    option text = STRING_TOKEN(STR_ENABLE), value =1, flags = MANUFACTURING | DEFAULT | RESET_REQUIRED;\r
+    option text = STRING_TOKEN(STR_DISABLE), value = 0, flags = RESET_REQUIRED;\r
+  endoneof;\r
+\r
+  oneof varid  = Setup.GOPBrightnessLevel,\r
+    prompt = STRING_TOKEN(STR_GOP_BRIGHTNESS_LEVEL),\r
+    help   = STRING_TOKEN(STR_GOP_BRIGHTNESS_LEVEL_HELP),\r
+    option text = STRING_TOKEN(STR_GOP_BRIGHT_20), value =2, flags = RESET_REQUIRED;\r
+    option text = STRING_TOKEN(STR_GOP_BRIGHT_40), value =3, flags = RESET_REQUIRED;\r
+    option text = STRING_TOKEN(STR_GOP_BRIGHT_60), value =4, flags = RESET_REQUIRED;\r
+    option text = STRING_TOKEN(STR_GOP_BRIGHT_80), value =5, flags = MANUFACTURING| DEFAULT| RESET_REQUIRED;\r
+    option text = STRING_TOKEN(STR_GOP_BRIGHT_100), value =6, flags = RESET_REQUIRED;\r
+    option text = STRING_TOKEN(STR_GOP_BRIGHT_120), value =7, flags = RESET_REQUIRED;\r
+    option text = STRING_TOKEN(STR_GOP_BRIGHT_140), value =8, flags = RESET_REQUIRED;\r
+    option text = STRING_TOKEN(STR_GOP_BRIGHT_160), value =9, flags = RESET_REQUIRED;\r
+    option text = STRING_TOKEN(STR_GOP_BRIGHT_180), value =10, flags = RESET_REQUIRED;\r
+    option text = STRING_TOKEN(STR_GOP_BRIGHT_200), value =11, flags = RESET_REQUIRED;\r
+    option text = STRING_TOKEN(STR_GOP_BRIGHT_220), value =12, flags = RESET_REQUIRED;\r
+    option text = STRING_TOKEN(STR_GOP_BRIGHT_240), value =13, flags = RESET_REQUIRED;\r
+    option text = STRING_TOKEN(STR_GOP_BRIGHT_255), value =14, flags = RESET_REQUIRED;\r
+  endoneof;\r
+  subtitle text = STRING_TOKEN(STR_NULL_STRING);\r
+  subtitle text = STRING_TOKEN(STR_IGD_TITLE);\r
+\r
+  suppressif ideqval Setup.PrimaryVideoAdaptor == 0x2;\r
+    oneof varid  = Setup.Igd,\r
+      prompt   = STRING_TOKEN (STR_IGD_PROMPT),\r
+      help     = STRING_TOKEN (STR_IGD_HELP),\r
+      option text = STRING_TOKEN(STR_DISABLE), value=0, flags=RESET_REQUIRED;\r
+      option text = STRING_TOKEN(STR_ENABLE),  value=1, flags=DEFAULT | MANUFACTURING | RESET_REQUIRED;\r
+    endoneof;\r
+  endif;\r
+\r
+  oneof varid    = Setup.PrimaryVideoAdaptor,\r
+    prompt   = STRING_TOKEN(STR_PRIMARY_DISPLAY),\r
+    help     = STRING_TOKEN(STR_PRIMARY_DISPLAY_HELP),\r
+    option text = STRING_TOKEN(STR_AUTOMATIC), value = 3, flags =   RESET_REQUIRED;\r
+    option text = STRING_TOKEN(STR_IGD_STRING), value = 0, flags =  DEFAULT |MANUFACTURING |RESET_REQUIRED;\r
+    option text = STRING_TOKEN(STR_PCI_STRING),  value = 2, flags = RESET_REQUIRED;\r
+  endoneof;\r
+\r
+\r
+  oneof varid = Setup.PavpMode,\r
+    prompt   = STRING_TOKEN(STR_PAVC_PROMPT),\r
+    help     = STRING_TOKEN(STR_PAVC_HELP),\r
+    option text = STRING_TOKEN(STR_DISABLE), value = 0, flags = RESET_REQUIRED;\r
+    option text = STRING_TOKEN(STR_PAVP_LITE_MODE), value = 1, flags = MANUFACTURING | DEFAULT | RESET_REQUIRED;\r
+    option text = STRING_TOKEN(STR_PAVP_SERPENT_MODE), value = 2, flags = RESET_REQUIRED;\r
+  endoneof;\r
+\r
+\r
+  oneof varid    = Setup.GTTSize,\r
+    prompt   = STRING_TOKEN(STR_GTT_SIZE),\r
+    help     = STRING_TOKEN(STR_GTT_SIZE_HELP),\r
+    option text = STRING_TOKEN(GTT_SIZE_1MB), value = 1, flags =  RESET_REQUIRED;\r
+    option text = STRING_TOKEN(GTT_SIZE_2MB), value = 2, flags =  DEFAULT | MANUFACTURING | RESET_REQUIRED;\r
+  endoneof;\r
+\r
+  oneof varid    = Setup.IgdApertureSize,\r
+    prompt   = STRING_TOKEN(STR_APERTURE_SIZE),\r
+    help     = STRING_TOKEN(STR_APERTURE_SIZE_HELP),\r
+    option text = STRING_TOKEN(APERTURE_SIZE_128MB), value = 1, flags =  RESET_REQUIRED;\r
+    option text = STRING_TOKEN(APERTURE_SIZE_256MB), value = 2, flags =  DEFAULT | MANUFACTURING | RESET_REQUIRED;\r
+    option text = STRING_TOKEN(APERTURE_SIZE_512MB), value = 3, flags =  RESET_REQUIRED;\r
+  endoneof;\r
+\r
+  oneof varid   = Setup.IgdDvmt50PreAlloc,\r
+    prompt  = STRING_TOKEN(STR_DVMT50_PRE_ALLOC),\r
+    help    = STRING_TOKEN(STR_DVMT50_PRE_ALLOC_HELP),\r
+//    option text = STRING_TOKEN(STR_DVMT50_PRE_ALLOC_32M), value = 1, flags = RESET_REQUIRED;\r
+    option text = STRING_TOKEN(STR_DVMT50_PRE_ALLOC_64M), value = 2, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED;\r
+    option text = STRING_TOKEN(STR_DVMT50_PRE_ALLOC_96M), value = 3, flags = RESET_REQUIRED;\r
+    option text = STRING_TOKEN(STR_DVMT50_PRE_ALLOC_128M), value = 4, flags = RESET_REQUIRED;\r
+    option text = STRING_TOKEN(STR_DVMT50_PRE_ALLOC_160M), value = 5, flags = RESET_REQUIRED;\r
+    option text = STRING_TOKEN(STR_DVMT50_PRE_ALLOC_192M), value = 6, flags = RESET_REQUIRED;\r
+    option text = STRING_TOKEN(STR_DVMT50_PRE_ALLOC_224M), value = 7, flags = RESET_REQUIRED;\r
+    option text = STRING_TOKEN(STR_DVMT50_PRE_ALLOC_256M), value = 8, flags = RESET_REQUIRED;\r
+    option text = STRING_TOKEN(STR_DVMT50_PRE_ALLOC_288M), value = 9, flags = RESET_REQUIRED;\r
+    option text = STRING_TOKEN(STR_DVMT50_PRE_ALLOC_320M), value = 10, flags = RESET_REQUIRED;\r
+    option text = STRING_TOKEN(STR_DVMT50_PRE_ALLOC_352M), value = 11, flags = RESET_REQUIRED;\r
+    option text = STRING_TOKEN(STR_DVMT50_PRE_ALLOC_384M), value = 12, flags = RESET_REQUIRED;\r
+    option text = STRING_TOKEN(STR_DVMT50_PRE_ALLOC_416M), value = 13, flags = RESET_REQUIRED;\r
+    option text = STRING_TOKEN(STR_DVMT50_PRE_ALLOC_448M), value = 14, flags = RESET_REQUIRED;\r
+    option text = STRING_TOKEN(STR_DVMT50_PRE_ALLOC_480M), value = 15, flags = RESET_REQUIRED;\r
+    option text = STRING_TOKEN(STR_DVMT50_PRE_ALLOC_512M), value = 16, flags = RESET_REQUIRED;\r
+  endoneof;\r
+\r
+  oneof   varid   = Setup.IgdDvmt50TotalAlloc,\r
+    prompt  = STRING_TOKEN(STR_DVMT50_DVMT ),\r
+    help    = STRING_TOKEN(STR_DVMT50_DVMT_HELP),\r
+    option text = STRING_TOKEN(STR_DVMT50_ALLOC_128), value = 1, flags = RESET_REQUIRED;\r
+    option text = STRING_TOKEN(STR_DVMT50_ALLOC_256), value = 2, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED;\r
+    option text = STRING_TOKEN(STR_DVMT50_ALLOC_MAX), value = 3, flags = RESET_REQUIRED;\r
+  endoneof;\r
+\r
+  //\r
+  //Igd Thermal\r
+  //\r
+\r
+  subtitle text = STRING_TOKEN(STR_NULL_STRING);\r
+\r
+  subtitle text = STRING_TOKEN(STR_IGD_LCD_CONTROL);\r
+\r
+  oneof varid    = Setup.LidStatus,\r
+    prompt   = STRING_TOKEN(STR_FORCE_LID_STATUS_PROMPT),\r
+    help     = STRING_TOKEN(STR_FORCE_LID_STATUS_ENBDT_HELP),\r
+    option text = STRING_TOKEN(STR_LID_STATUS__OFF_PROMPT), value = 0, flags = 0 | RESET_REQUIRED;\r
+    option text = STRING_TOKEN(STR_LID_STATUS__ON_PROMPT), value = 1, flags = 0 | RESET_REQUIRED;\r
+    option text = STRING_TOKEN(STR_LID_STATUS__AUTO_PROMPT), value = 2, flags = MANUFACTURING| DEFAULT| RESET_REQUIRED;\r
+  endoneof;\r
+\r
+  oneof varid    = Setup.IgdLcdIBia,\r
+    prompt   = STRING_TOKEN(STR_VIDEO_LCD_IBIA),\r
+    help     = STRING_TOKEN(STR_VIDEO_LCD_IBIAHLP),\r
+    option text = STRING_TOKEN(STR_VIDEO_LCD_IBIAA), value = 0, flags =MANUFACTURING| DEFAULT| RESET_REQUIRED;\r
+    option text = STRING_TOKEN(STR_VIDEO_LCD_IBIAD), value = 1, flags = 0| RESET_REQUIRED;\r
+    option text = STRING_TOKEN(STR_VIDEO_LCD_IBIAL1), value = 2, flags = 0| RESET_REQUIRED;\r
+    option text = STRING_TOKEN(STR_VIDEO_LCD_IBIAL2), value = 3, flags = 0| RESET_REQUIRED;\r
+    option text = STRING_TOKEN(STR_VIDEO_LCD_IBIAL3), value = 4, flags = 0| RESET_REQUIRED;\r
+    option text = STRING_TOKEN(STR_VIDEO_LCD_IBIAL4), value = 5, flags = 0| RESET_REQUIRED;\r
+    option text = STRING_TOKEN(STR_VIDEO_LCD_IBIAL5), value = 6, flags = 0| RESET_REQUIRED;\r
+  endoneof;\r
+\r
+  oneof varid  = Setup.AlsEnable,\r
+    prompt   = STRING_TOKEN (STR_ACPI_ALS_ENABLE),\r
+    help     = STRING_TOKEN (STR_ACPI_ALS_ENABLE_HELP),\r
+    option text = STRING_TOKEN(STR_DISABLE), value=0, flags=DEFAULT | MANUFACTURING | RESET_REQUIRED;\r
+    option text = STRING_TOKEN(STR_ENABLE),  value=1, flags=0 | RESET_REQUIRED;\r
+  endoneof;\r
+\r
+\r
+  oneof   varid   = Setup.IgdFlatPanel,\r
+    prompt      = STRING_TOKEN(STR_IGD_FLAT_PANEL_PROMPT),\r
+    help        = STRING_TOKEN(STR_IGD_FLAT_PANEL_HELP),\r
+    option text = STRING_TOKEN(STR_AUTOMATIC), value=0x00, flags=DEFAULT | RESET_REQUIRED;\r
+    option text = STRING_TOKEN(STR_640X480), value=0x01, flags=RESET_REQUIRED;\r
+    option text = STRING_TOKEN(STR_800X600), value=0x02, flags=RESET_REQUIRED;\r
+    option text = STRING_TOKEN(STR_1024X768), value=0x03, flags=RESET_REQUIRED;\r
+    option text = STRING_TOKEN(STR_1280X1024), value=0x04, flags=RESET_REQUIRED;\r
+    option text = STRING_TOKEN(STR_1366X768), value=0x05, flags=RESET_REQUIRED;\r
+    option text = STRING_TOKEN(STR_1680X1050), value=0x06, flags=RESET_REQUIRED;\r
+    option text = STRING_TOKEN(STR_1920X1200), value=0x07, flags=RESET_REQUIRED;\r
+    option text = STRING_TOKEN(STR_1280X800), value=0x08, flags=RESET_REQUIRED;\r
+  endoneof;\r
+\r
+  oneof   varid   = Setup.BootDisplayDevice,\r
+    prompt      = STRING_TOKEN(STR_BOOT_DISPLAY_DEVICE_PROMPT),\r
+    help        = STRING_TOKEN(STR_BOOT_DISPLAY_DEVICE_HELP),\r
+    option text = STRING_TOKEN(STR_AUTOMATIC), value=0x00, flags=DEFAULT | RESET_REQUIRED;\r
+    option text = STRING_TOKEN(STR_VGAPORT), value=0x01, flags=RESET_REQUIRED;\r
+    option text = STRING_TOKEN(STR_HDMIPORTB), value=0x02, flags=RESET_REQUIRED;\r
+    option text = STRING_TOKEN(STR_DPPORTB), value=0x03, flags=RESET_REQUIRED;\r
+    option text = STRING_TOKEN(STR_DPPORTC), value=0x04, flags=RESET_REQUIRED;\r
+    option text = STRING_TOKEN(STR_EDPPORTC), value=0x05, flags=RESET_REQUIRED;\r
+    option text = STRING_TOKEN(STR_DSIPORTA), value=0x06, flags=RESET_REQUIRED;\r
+    option text = STRING_TOKEN(STR_DSIPORTC), value=0x07, flags=RESET_REQUIRED;\r
+\r
+  endoneof;\r
+  //\r
+  //Pannel Scaling\r
+  //\r
+  oneof   varid   = Setup.PanelScaling,\r
+    prompt      = STRING_TOKEN(STR_PANNEL_SCALING_PROMPT),\r
+    help        = STRING_TOKEN(STR_PANNEL_SCALING_HELP),\r
+    option text = STRING_TOKEN(STR_AUTOMATIC), value=0x00, flags=DEFAULT | RESET_REQUIRED;\r
+    option text = STRING_TOKEN(STR_PANNEL_SCALING_STRETCH), value=0x01, flags=RESET_REQUIRED;\r
+    option text = STRING_TOKEN(STR_PANNEL_SCALING_CENTER), value=0x02, flags=RESET_REQUIRED;\r
+  endoneof;\r
+\r
+  //\r
+  //GMCH BLC Control\r
+  //\r
+  oneof   varid   = Setup.IgdLcdIGmchBlc,\r
+    prompt      = STRING_TOKEN(STR_VIDEO_LCD_IGMCHBLC_PROMPT),\r
+    help        = STRING_TOKEN(STR_VIDEO_LCD_IGMCHBLC_HELP),\r
+    option text = STRING_TOKEN(STR_VIDEO_LCD_IGMCHBLC1), value=0x00, flags=DEFAULT | RESET_REQUIRED;\r
+    option text = STRING_TOKEN(STR_VIDEO_LCD_IGMCHBLC2), value=0x01, flags=RESET_REQUIRED;\r
+    option text = STRING_TOKEN(STR_VIDEO_LCD_IGMCHBLC3), value=0x02, flags=RESET_REQUIRED;\r
+    option text = STRING_TOKEN(STR_VIDEO_LCD_IGMCHBLC4), value=0x03, flags=RESET_REQUIRED;\r
+  endoneof;\r
+\r
+  subtitle text = STRING_TOKEN(STR_NULL_STRING);\r
+  //\r
+  //ISP Configuration\r
+  //\r
+  subtitle text = STRING_TOKEN(STR_ISP_CONFIGURATION_TITLE);\r
+\r
+  oneof varid   = Setup.ISPEn,\r
+    prompt      = STRING_TOKEN(STR_ISP_ENABLED),\r
+    help        = STRING_TOKEN(STR_ISP_ENABLED_HELP),\r
+    option text = STRING_TOKEN(STR_ENABLE), value = 1, flags = DEFAULT | RESET_REQUIRED;\r
+    option text = STRING_TOKEN(STR_DISABLE), value = 0, flags = RESET_REQUIRED;\r
+  endoneof;\r
+\r
+  grayoutif ideqval Setup.ISPEn == 0;\r
+    oneof varid  = Setup.ISPDevSel,\r
+      prompt   = STRING_TOKEN (STR_ISP_PCICONFIGURATION_TITLE),\r
+      help     = STRING_TOKEN (STR_ISP_PCICONFIGURATION_HELP),\r
+      option text = STRING_TOKEN(STR_DISABLE), value = 0, flags = RESET_REQUIRED;\r
+      option text = STRING_TOKEN(STR_ISP_PCICONFIG_B0D2F0_TITLE), value = 1, flags = MANUFACTURING | DEFAULT | RESET_REQUIRED;\r
+      option text = STRING_TOKEN(STR_ISP_PCICONFIG_B0D3F0_TITLE), value = 2, flags = RESET_REQUIRED;\r
+   endoneof;\r
+  endif;\r
+\r
+endform;\r

diff --git a/Vlv2TbltDevicePkg/PlatformSetupDxe/UqiList.uni b/Vlv2TbltDevicePkg/PlatformSetupDxe/UqiList.uni
new file mode 100644 (file)
index 0000000..7ecc549
Binary files /dev/null and b/Vlv2TbltDevicePkg/PlatformSetupDxe/UqiList.uni differ

diff --git a/Vlv2TbltDevicePkg/PlatformSetupDxe/Vfr.vfr b/Vlv2TbltDevicePkg/PlatformSetupDxe/Vfr.vfr
new file mode 100644 (file)
index 0000000..6922ce2
--- /dev/null
+++ b/Vlv2TbltDevicePkg/PlatformSetupDxe/Vfr.vfr
@@ -0,0 +1,128 @@
+//\r
+//\r
+//\r
+// Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+//                                                                                  \r\r
+// This program and the accompanying materials are licensed and made available under\r\r
+// the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+// The full text of the license may be found at                                     \r\r
+// http://opensource.org/licenses/bsd-license.php.                                  \r\r
+//                                                                                  \r\r
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+//                                                                                  \r\r
+//\r
+//\r
+#include "Configuration.h"\r
+#include "PlatformSetupDxeStrDefs.h"\r
+#include "Guid/SetupVariable.h"\r
+\r
+formset\r
+  guid     = SYSTEM_CONFIGURATION_GUID,\r
+  title    = STRING_TOKEN(STR_SYSTEM_SETUP_TITLE),\r
+  help     = STRING_TOKEN(STR_SYSTEM_SETUP_HELP),\r
+  class    = 1,\r
+  subclass = 0,\r
+\r
+\r
+  varstore SYSTEM_CONFIGURATION, name = Setup, guid = SYSTEM_CONFIGURATION_GUID;\r
+  form formid = ROOT_FORM_ID,\r
+    title    = STRING_TOKEN(STR_SYSTEM_SETUP_TITLE);\r
+\r
+    //\r
+    // Jump to  2)Main Form\r
+    //\r
+    goto ROOT_MAIN_FORM_ID,\r
+      prompt = STRING_TOKEN(STR_MAIN_TITLE),\r
+      help   = STRING_TOKEN(STR_MAIN_HELP);\r
+\r
+    //\r
+    // Jump to  3)Uncore Configuration Form\r
+    //\r
+    goto UNCORE_FORM_ID,\r
+      prompt = STRING_TOKEN(STR_UNCORE_CONFIGURATION_TITLE),\r
+      help   = STRING_TOKEN(STR_UNCORE_CONFIGURATION_HELP);\r
+\r
+    //\r
+    // Jump to  4)South Cluster  Configuration Form\r
+    //\r
+    goto SOUTH_CLUSTER_FORM_ID,\r
+      prompt = STRING_TOKEN(STR_SOUTH_CLUSTER_TITLE),\r
+      help   = STRING_TOKEN(STR_SOUTH_CLUSTER_HELP);\r
+\r
+    // Jump to  5)Boot Form\r
+    //\r
+    goto BOOT_CONFIGURATION_FORM_ID,\r
+      prompt = STRING_TOKEN(STR_BOOT_CONFIGURATION_TITLE),\r
+      help   = STRING_TOKEN(STR_BOOT_CONFIGURATION_HELP);\r
+\r
+    //\r
+    // Jump to  6)Security Configuration Form\r
+    //\r
+    goto SECURITY_CONFIGURATION_FORM_ID,\r
+      prompt = STRING_TOKEN(STR_SECURITY_CONFIGURATION_TITLE),\r
+      help   = STRING_TOKEN(STR_SECURITY_CONFIGURATION_HELP);\r
+\r
+    //\r
+    // Jump to  7)Thermal Form\r
+    //\r
+    goto THERMAL_FORM_ID,\r
+      prompt = STRING_TOKEN(STR_THERMAL_TITLE),\r
+      help   = STRING_TOKEN(STR_THERMAL_HELP);\r
+\r
+    //\r
+    // Jump to 8) System Component Form\r
+    goto SYSTEM_COMPONENT_FORM_ID,\r
+      prompt = STRING_TOKEN(STR_SYSTEM_COMPONENT_TITLE),\r
+      help   = STRING_TOKEN(STR_SYSTEM_COMPONENT_HELP);\r
+\r
+    //\r
+    // Jump to  10)Debug Configuration Form\r
+    //\r
+#if (BYTI_PF_ENABLE == 0)\r
+    goto DEBUG_CONFIGURATION_FORM_ID,\r
+      prompt = STRING_TOKEN(STR_DEBUG_CONFIGURATION_TITLE),\r
+      help   = STRING_TOKEN(STR_DEBUG_CONFIGURATION_HELP);\r
+#endif\r
+\r
+    subtitle text = STRING_TOKEN(STR_NULL_STRING);\r
+    //\r
+    // Commit change and exit\r
+    //\r
+    text\r
+      help   = STRING_TOKEN(STR_COMMIT_CHANGE_AND_EXIT_HELP),\r
+      text   = STRING_TOKEN(STR_COMMIT_CHANGE_AND_EXIT_PROMPT),\r
+      text   = STRING_TOKEN(STR_COMMIT_CHANGE_AND_EXIT_PROMPT),\r
+      flags  = INTERACTIVE,\r
+      key    = 0xF001;\r
+\r
+    //\r
+    // Discard change and exit\r
+    //\r
+    text\r
+      help   = STRING_TOKEN(STR_DISCARD_CHANGE_AND_EXIT_HELP),\r
+      text   = STRING_TOKEN(STR_DISCARD_CHANGE_AND_EXIT_PROMPT),\r
+      text   = STRING_TOKEN(STR_DISCARD_CHANGE_AND_EXIT_PROMPT),\r
+      flags  = INTERACTIVE,\r
+      key    = 0xF002;\r
+\r
+    //\r
+    // Load default and exit\r
+    //\r
+    text\r
+      help   = STRING_TOKEN(STR_LOAD_DEFAULT_AND_EXIT_HELP),\r
+      text   = STRING_TOKEN(STR_LOAD_DEFAULT_AND_EXIT_PROMPT),\r
+      text   = STRING_TOKEN(STR_LOAD_DEFAULT_AND_EXIT_PROMPT),\r
+      flags  = INTERACTIVE,\r
+      key    = 0xF003;\r
+  endform;\r
+\r
+  #include "Main.vfi"\r
+  #include "UnCore.vfi"\r
+  #include "SouthClusterConfig.vfi"\r
+  #include "Boot.vfi"\r
+  #include "Security.vfi"\r
+  #include "Thermal.vfi"\r
+  #include "SystemComponent.vfi"\r
+  #include "DebugConfig.vfi"\r
+endformset;\r

diff --git a/Vlv2TbltDevicePkg/PlatformSetupDxe/VfrStrings.uni b/Vlv2TbltDevicePkg/PlatformSetupDxe/VfrStrings.uni
new file mode 100644 (file)
index 0000000..16d78f6
Binary files /dev/null and b/Vlv2TbltDevicePkg/PlatformSetupDxe/VfrStrings.uni differ

diff --git a/Vlv2TbltDevicePkg/PlatformSmm/Platform.c b/Vlv2TbltDevicePkg/PlatformSmm/Platform.c
new file mode 100644 (file)
index 0000000..d8bfeb4
--- /dev/null
+++ b/Vlv2TbltDevicePkg/PlatformSmm/Platform.c
@@ -0,0 +1,977 @@
+/** @file\r
+\r
+  Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+Module Name:\r
+\r
+    Platform.c\r
+\r
+Abstract:\r
+\r
+    This is a generic template for a child of the IchSmm driver.\r
+\r
+\r
+--*/\r
+\r
+#include "SmmPlatform.h"\r
+#include <Protocol/CpuIo2.h>\r
+\r
+\r
+//\r
+// Local variables\r
+//\r
+typedef struct {\r
+  UINT8     Device;\r
+  UINT8     Function;\r
+} EFI_PCI_BUS_MASTER;\r
+\r
+EFI_PCI_BUS_MASTER  mPciBm[] = {\r
+  { PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORTS, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_1 },\r
+  { PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORTS, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_2 },\r
+  { PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORTS, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_3 },\r
+  { PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORTS, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_4 },\r
+  { PCI_DEVICE_NUMBER_PCH_USB, PCI_FUNCTION_NUMBER_PCH_EHCI }\r
+};\r
+\r
+\r
+UINT16                                  mAcpiBaseAddr;\r
+SYSTEM_CONFIGURATION                    mSystemConfiguration;\r
+EFI_SMM_VARIABLE_PROTOCOL               *mSmmVariable;\r
+EFI_GLOBAL_NVS_AREA_PROTOCOL            *mGlobalNvsAreaPtr;\r
+\r
+UINT16                                                                                 mPM1_SaveState16;\r
+UINT32                                                                                 mGPE_SaveState32;\r
+\r
+BOOLEAN                                 mSetSmmVariableProtocolSmiAllowed = TRUE;\r
+\r
+\r
+//\r
+// Variables. Need to initialize this from Setup\r
+//\r
+BOOLEAN                                 mWakeOnLanS5Variable;\r
+BOOLEAN                                 mWakeOnRtcVariable;\r
+UINT8                                   mWakeupDay;\r
+UINT8                                   mWakeupHour;\r
+UINT8                                   mWakeupMinute;\r
+UINT8                                   mWakeupSecond;\r
+\r
+//\r
+// Use an enum. 0 is Stay Off, 1 is Last State, 2 is Stay On\r
+//\r
+UINT8                                   mAcLossVariable;\r
+\r
+\r
+static\r
+UINT8 mTco1Sources[] = {\r
+  IchnNmi\r
+};\r
+\r
+UINTN\r
+DevicePathSize (\r
+  IN EFI_DEVICE_PATH_PROTOCOL  *DevicePath\r
+  );\r
+\r
+VOID\r
+S4S5ProgClock();\r
+\r
+EFI_STATUS\r
+InitRuntimeScriptTable (\r
+  IN EFI_SYSTEM_TABLE  *SystemTable\r
+  );\r
+\r
+VOID\r
+S5SleepWakeOnRtcCallBack (\r
+  IN  EFI_HANDLE                    DispatchHandle,\r
+  IN  EFI_SMM_SX_DISPATCH_CONTEXT   *DispatchContext\r
+  );\r
+\r
+\r
+VOID\r
+EnableS5WakeOnRtc();\r
+\r
+UINT8\r
+HexToBcd(\r
+  UINT8 HexValue\r
+  );\r
+\r
+UINT8\r
+BcdToHex(\r
+  IN UINT8 BcdValue\r
+  );\r
+\r
+\r
+VOID\r
+CpuSmmSxWorkAround(\r
+  );\r
+\r
+/**\r
+  Initializes the SMM Handler Driver\r
+\r
+  @param ImageHandle\r
+  @param SystemTable\r
+\r
+  @retval None\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+InitializePlatformSmm (\r
+  IN EFI_HANDLE        ImageHandle,\r
+  IN EFI_SYSTEM_TABLE  *SystemTable\r
+  )\r
+{\r
+  EFI_STATUS                                Status;\r
+  UINT8                                     Index;\r
+  EFI_HANDLE                                Handle;\r
+  EFI_SMM_POWER_BUTTON_DISPATCH_CONTEXT     PowerButtonContext;\r
+  EFI_SMM_POWER_BUTTON_DISPATCH_PROTOCOL    *PowerButtonDispatch;\r
+  EFI_SMM_ICHN_DISPATCH_CONTEXT             IchnContext;\r
+  EFI_SMM_ICHN_DISPATCH_PROTOCOL            *IchnDispatch;\r
+  EFI_SMM_SX_DISPATCH_PROTOCOL              *SxDispatch;\r
+  EFI_SMM_SX_DISPATCH_CONTEXT               EntryDispatchContext;\r
+  EFI_SMM_SW_DISPATCH_PROTOCOL              *SwDispatch;\r
+  EFI_SMM_SW_DISPATCH_CONTEXT               SwContext;\r
+  UINTN                                     VarSize;\r
+  EFI_BOOT_MODE                             BootMode;\r
+\r
+  Handle = NULL;\r
+\r
+  //\r
+  //  Locate the Global NVS Protocol.\r
+  //\r
+  Status = gBS->LocateProtocol (\r
+                  &gEfiGlobalNvsAreaProtocolGuid,\r
+                  NULL,\r
+                  (void **)&mGlobalNvsAreaPtr\r
+                  );\r
+  ASSERT_EFI_ERROR (Status);\r
+\r
+\r
+  //\r
+  // Get the ACPI Base Address\r
+  //\r
+\r
+  mAcpiBaseAddr = PchLpcPciCfg16( R_PCH_LPC_ACPI_BASE ) & B_PCH_LPC_ACPI_BASE_BAR;\r
+\r
+  VarSize = sizeof(SYSTEM_CONFIGURATION);\r
+  Status = SystemTable->RuntimeServices->GetVariable(\r
+                          L"Setup",\r
+                          &gEfiSetupVariableGuid,\r
+                          NULL,\r
+                          &VarSize,\r
+                          &mSystemConfiguration\r
+                          );\r
+  if (!EFI_ERROR(Status)) {\r
+    mAcLossVariable = mSystemConfiguration.StateAfterG3;\r
+\r
+    //\r
+    // If LAN is disabled, WOL function should be disabled too.\r
+    //\r
+    if (mSystemConfiguration.Lan == 0x01){\r
+      mWakeOnLanS5Variable = mSystemConfiguration.WakeOnLanS5;\r
+    } else {\r
+      mWakeOnLanS5Variable = FALSE;\r
+    }\r
+\r
+    mWakeOnRtcVariable = mSystemConfiguration.WakeOnRtcS5;\r
+  }\r
+\r
+  BootMode = GetBootModeHob ();\r
+\r
+  //\r
+  // Get the Power Button protocol\r
+  //\r
+  Status = gBS->LocateProtocol(\r
+                  &gEfiSmmPowerButtonDispatchProtocolGuid,\r
+                  NULL,\r
+                  (void **)&PowerButtonDispatch\r
+                  );\r
+  ASSERT_EFI_ERROR(Status);\r
+\r
+  if (BootMode != BOOT_ON_FLASH_UPDATE) {\r
+    //\r
+    // Register for the power button event\r
+    //\r
+    PowerButtonContext.Phase = PowerButtonEntry;\r
+    Status = PowerButtonDispatch->Register(\r
+                                    PowerButtonDispatch,\r
+                                    PowerButtonCallback,\r
+                                    &PowerButtonContext,\r
+                                    &Handle\r
+                                    );\r
+    ASSERT_EFI_ERROR(Status);\r
+  }\r
+  //\r
+  // Get the Sx dispatch protocol\r
+  //\r
+  Status = gBS->LocateProtocol (\r
+                  &gEfiSmmSxDispatchProtocolGuid,\r
+                  NULL,\r
+                                  (void **)&SxDispatch\r
+                  );\r
+  ASSERT_EFI_ERROR(Status);\r
+\r
+  //\r
+  // Register entry phase call back function\r
+  //\r
+  EntryDispatchContext.Type  = SxS3;\r
+  EntryDispatchContext.Phase = SxEntry;\r
+\r
+  Status = SxDispatch->Register (\r
+                         SxDispatch,\r
+                           (EFI_SMM_SX_DISPATCH)SxSleepEntryCallBack,\r
+                         &EntryDispatchContext,\r
+                         &Handle\r
+                         );\r
+\r
+\r
+  EntryDispatchContext.Type  = SxS4;\r
+\r
+  Status = SxDispatch->Register (\r
+                         SxDispatch,\r
+                         S4S5CallBack,\r
+                         &EntryDispatchContext,\r
+                         &Handle\r
+                         );\r
+  ASSERT_EFI_ERROR(Status);\r
+\r
+\r
+  EntryDispatchContext.Type  = SxS5;\r
+\r
+  Status = SxDispatch->Register (\r
+                         SxDispatch,\r
+                         S4S5CallBack,\r
+                         &EntryDispatchContext,\r
+                         &Handle\r
+                         );\r
+  ASSERT_EFI_ERROR(Status);\r
+\r
+  Status = SxDispatch->Register (\r
+                         SxDispatch,\r
+                         S5SleepAcLossCallBack,\r
+                         &EntryDispatchContext,\r
+                         &Handle\r
+                         );\r
+  ASSERT_EFI_ERROR(Status);\r
+\r
+  //\r
+  //  Get the Sw dispatch protocol\r
+  //\r
+  Status = gBS->LocateProtocol (\r
+                  &gEfiSmmSwDispatchProtocolGuid,\r
+                  NULL,\r
+                                  (void **)&SwDispatch\r
+                  );\r
+  ASSERT_EFI_ERROR(Status);\r
+\r
+  //\r
+  // Register ACPI enable handler\r
+  //\r
+  SwContext.SwSmiInputValue = ACPI_ENABLE;\r
+  Status = SwDispatch->Register (\r
+                         SwDispatch,\r
+                         EnableAcpiCallback,\r
+                         &SwContext,\r
+                         &Handle\r
+                         );\r
+  ASSERT_EFI_ERROR(Status);\r
+\r
+  //\r
+  // Register ACPI disable handler\r
+  //\r
+  SwContext.SwSmiInputValue = ACPI_DISABLE;\r
+  Status = SwDispatch->Register (\r
+                         SwDispatch,\r
+                         DisableAcpiCallback,\r
+                         &SwContext,\r
+                         &Handle\r
+                         );\r
+  ASSERT_EFI_ERROR(Status);\r
+\r
+\r
+  //\r
+  // Register for SmmReadyToBootCallback\r
+  //\r
+  SwContext.SwSmiInputValue = SMI_SET_SMMVARIABLE_PROTOCOL;\r
+  Status = SwDispatch->Register(\r
+                         SwDispatch,\r
+                         SmmReadyToBootCallback,\r
+                         &SwContext,\r
+                         &Handle\r
+                         );\r
+  ASSERT_EFI_ERROR(Status);\r
+\r
+  //\r
+  // Get the ICHn protocol\r
+  //\r
+  Status = gBS->LocateProtocol(\r
+                  &gEfiSmmIchnDispatchProtocolGuid,\r
+                  NULL,\r
+                  (void **)&IchnDispatch\r
+                  );\r
+  ASSERT_EFI_ERROR(Status);\r
+\r
+  //\r
+  // Register for the events that may happen that we do not care.\r
+  // This is true for SMI related to TCO since TCO is enabled by BIOS WP\r
+  //\r
+  for (Index = 0; Index < sizeof(mTco1Sources)/sizeof(UINT8); Index++) {\r
+    IchnContext.Type = mTco1Sources[Index];\r
+    Status = IchnDispatch->Register(\r
+                             IchnDispatch,\r
+                             (EFI_SMM_ICHN_DISPATCH)DummyTco1Callback,\r
+                             &IchnContext,\r
+                             &Handle\r
+                             );\r
+    ASSERT_EFI_ERROR( Status );\r
+  }\r
+\r
+  //\r
+  // Lock TCO_EN bit.\r
+  //\r
+  IoWrite16( mAcpiBaseAddr + R_PCH_TCO_CNT, IoRead16( mAcpiBaseAddr + R_PCH_TCO_CNT ) | B_PCH_TCO_CNT_LOCK );\r
+\r
+  //\r
+  // Set to power on from G3 dependent on WOL instead of AC Loss variable in order to support WOL from G3 feature.\r
+  //\r
+  //\r
+  // Set wake from G3 dependent on AC Loss variable and Wake On LAN variable.\r
+  // This is because no matter how, if WOL enabled or AC Loss variable not disabled, the board needs to wake from G3 to program the LAN WOL settings.\r
+  // This needs to be done after LAN enable/disable so that the PWR_FLR state clear not impacted the WOL from G3 feature.\r
+  //\r
+  if (mAcLossVariable != 0x00) {\r
+    SetAfterG3On (TRUE);\r
+  } else {\r
+    SetAfterG3On (FALSE);\r
+  }\r
+\r
+\r
+\r
+\r
+  return EFI_SUCCESS;\r
+}\r
+\r
+VOID\r
+EFIAPI\r
+SmmReadyToBootCallback (\r
+  IN  EFI_HANDLE                    DispatchHandle,\r
+  IN  EFI_SMM_SW_DISPATCH_CONTEXT   *DispatchContext\r
+  )\r
+{\r
+  EFI_STATUS Status;\r
+\r
+  if (mSetSmmVariableProtocolSmiAllowed)\r
+  {\r
+       //\r
+    // It is okay to use gBS->LocateProtocol here because\r
+    // we are still in trusted execution.\r
+    //\r
+  Status = gBS->LocateProtocol(\r
+                  &gEfiSmmVariableProtocolGuid,\r
+                  NULL,\r
+                  (void **)&mSmmVariable\r
+                  );\r
+\r
+    ASSERT_EFI_ERROR(Status);\r
+\r
+    //\r
+    // mSetSmmVariableProtocolSmiAllowed will prevent this function from\r
+    // being executed more than 1 time.\r
+    //\r
+    mSetSmmVariableProtocolSmiAllowed = FALSE;\r
+  }\r
+\r
+}\r
+\r
+/**\r
+\r
+  @param DispatchHandle   The handle of this callback, obtained when registering\r
+  @param DispatchContext  The predefined context which contained sleep type and phase\r
+\r
+\r
+  @retval EFI_SUCCESS     Operation successfully performed\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI    \r
+SxSleepEntryCallBack (\r
+  IN  EFI_HANDLE                    DispatchHandle,\r
+  IN  EFI_SMM_SX_DISPATCH_CONTEXT   *DispatchContext\r
+  )\r
+{\r
+  EFI_STATUS              Status;\r
+\r
+  Status = SaveRuntimeScriptTable ();\r
+  if (EFI_ERROR(Status)) {\r
+    return Status;\r
+  }\r
+\r
+  //\r
+  // Workaround for S3 wake hang if C State is enabled\r
+  //\r
+  CpuSmmSxWorkAround();\r
+\r
+  return EFI_SUCCESS;\r
+}\r
+\r
+VOID\r
+CpuSmmSxWorkAround(\r
+  )\r
+{\r
+  UINT64           MsrValue;\r
+\r
+  MsrValue = AsmReadMsr64 (0xE2);\r
+\r
+  if (MsrValue & BIT15) {\r
+    return;\r
+  }\r
+\r
+  if (MsrValue & BIT10) {\r
+    MsrValue &= ~BIT10;\r
+    AsmWriteMsr64 (0xE2, MsrValue);\r
+  }\r
+}\r
+\r
+VOID\r
+ClearP2PBusMaster(\r
+  )\r
+{\r
+  UINT8             Command;\r
+  UINT8             Index;\r
+\r
+  for (Index = 0; Index < sizeof(mPciBm)/sizeof(EFI_PCI_BUS_MASTER); Index++) {\r
+    Command = MmioRead8 (\r
+                MmPciAddress (0,\r
+                  DEFAULT_PCI_BUS_NUMBER_PCH,\r
+                  mPciBm[Index].Device,\r
+                  mPciBm[Index].Function,\r
+                  PCI_COMMAND_OFFSET\r
+                )\r
+              );\r
+    Command &= ~EFI_PCI_COMMAND_BUS_MASTER;\r
+    MmioWrite8 (\r
+      MmPciAddress (0,\r
+        DEFAULT_PCI_BUS_NUMBER_PCH,\r
+        mPciBm[Index].Device,\r
+        mPciBm[Index].Function,\r
+        PCI_COMMAND_OFFSET\r
+      ),\r
+      Command\r
+    );\r
+  }\r
+}\r
+\r
+/**\r
+\r
+  Set the AC Loss to turn on or off.\r
+\r
+**/\r
+VOID\r
+SetAfterG3On (\r
+  BOOLEAN Enable\r
+  )\r
+{\r
+  UINT8             PmCon1;\r
+\r
+  //\r
+  // ICH handling portion\r
+  //\r
+  PmCon1 = MmioRead8 ( PMC_BASE_ADDRESS + R_PCH_PMC_GEN_PMCON_1 );\r
+  PmCon1 &= ~B_PCH_PMC_GEN_PMCON_AFTERG3_EN;\r
+  if (Enable) {\r
+    PmCon1 |= B_PCH_PMC_GEN_PMCON_AFTERG3_EN;\r
+  }\r
+  MmioWrite8 (PMC_BASE_ADDRESS + R_PCH_PMC_GEN_PMCON_1, PmCon1);\r
+\r
+}\r
+\r
+/**\r
+  When a power button event happens, it shuts off the machine\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+PowerButtonCallback (\r
+  IN  EFI_HANDLE                              DispatchHandle,\r
+  IN  EFI_SMM_POWER_BUTTON_DISPATCH_CONTEXT   *DispatchContext\r
+  )\r
+{\r
+  //\r
+  // Check what the state to return to after AC Loss. If Last State, then\r
+  // set it to Off.\r
+  //\r
+  UINT16  data16;\r
+\r
+  if (mWakeOnRtcVariable) {\r
+    EnableS5WakeOnRtc();\r
+  }\r
+\r
+  if (mAcLossVariable == 1) {\r
+    SetAfterG3On (TRUE);\r
+  }\r
+\r
+  ClearP2PBusMaster();\r
+\r
+  //\r
+  // Program clock chip\r
+  //\r
+  S4S5ProgClock();\r
+\r
+\r
+  data16 = (UINT16)(IoRead16(mAcpiBaseAddr + R_PCH_ACPI_GPE0a_EN));\r
+  data16 &= B_PCH_ACPI_GPE0a_EN_PCI_EXP;\r
+\r
+\r
+  //\r
+  // Clear Sleep SMI Status\r
+  //\r
+  IoWrite16 (mAcpiBaseAddr + R_PCH_SMI_STS,\r
+                (UINT16)(IoRead16 (mAcpiBaseAddr + R_PCH_SMI_STS) | B_PCH_SMI_STS_ON_SLP_EN));\r
+  //\r
+  // Clear Sleep Type Enable\r
+  //\r
+  IoWrite16 (mAcpiBaseAddr + R_PCH_SMI_EN,\r
+                (UINT16)(IoRead16 (mAcpiBaseAddr + R_PCH_SMI_EN) & (~B_PCH_SMI_EN_ON_SLP_EN)));\r
+\r
+  //\r
+  // Clear Power Button Status\r
+  //\r
+  IoWrite16(mAcpiBaseAddr + R_PCH_ACPI_PM1_STS, B_PCH_ACPI_PM1_STS_PWRBTN);\r
+\r
+  //\r
+  // Shut it off now!\r
+  //\r
+  IoWrite16(mAcpiBaseAddr + R_PCH_ACPI_PM1_CNT, V_PCH_ACPI_PM1_CNT_S5);\r
+  IoWrite16(mAcpiBaseAddr + R_PCH_ACPI_PM1_CNT, B_PCH_ACPI_PM1_CNT_SLP_EN | V_PCH_ACPI_PM1_CNT_S5);\r
+\r
+  //\r
+  // Should not return\r
+  //\r
+  CpuDeadLoop();\r
+}\r
+\r
+\r
+/**\r
+  @param DispatchHandle  - The handle of this callback, obtained when registering\r
+\r
+  @param DispatchContext - The predefined context which contained sleep type and phase\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+S5SleepAcLossCallBack (\r
+  IN  EFI_HANDLE                    DispatchHandle,\r
+  IN  EFI_SMM_SX_DISPATCH_CONTEXT   *DispatchContext\r
+  )\r
+{\r
+  //\r
+  // Check what the state to return to after AC Loss. If Last State, then\r
+  // set it to Off.\r
+  //\r
+  if (mAcLossVariable == 1) {\r
+    SetAfterG3On (TRUE);\r
+  }\r
+}\r
+\r
+/**\r
+\r
+  @param DispatchHandle   The handle of this callback, obtained when registering\r
+  @param DispatchContext  The predefined context which contained sleep type and phase\r
+\r
+  @retval Clears the Save State bit in the clock.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+S4S5CallBack (\r
+  IN  EFI_HANDLE                    DispatchHandle,\r
+  IN  EFI_SMM_SX_DISPATCH_CONTEXT   *DispatchContext\r
+  )\r
+{\r
+\r
+  UINT32        Data32;\r
+\r
+  //\r
+  // Enable/Disable USB Charging\r
+  //\r
+  if (mSystemConfiguration.UsbCharging == 0x01) {\r
+    Data32 = IoRead32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SC_LVL);\r
+    Data32 |= BIT8;\r
+    IoWrite32(GPIO_BASE_ADDRESS + R_PCH_GPIO_SC_LVL, Data32);\r
+  }\r
+\r
+}\r
+\r
+\r
+VOID\r
+S4S5ProgClock()\r
+{\r
+}\r
+\r
+/**\r
+  SMI handler to enable ACPI mode\r
+\r
+  Dispatched on reads from APM port with value 0xA0\r
+\r
+  Disables the SW SMI Timer.\r
+  ACPI events are disabled and ACPI event status is cleared.\r
+  SCI mode is then enabled.\r
+\r
+   Disable SW SMI Timer\r
+\r
+   Clear all ACPI event status and disable all ACPI events\r
+   Disable PM sources except power button\r
+   Clear status bits\r
+\r
+   Disable GPE0 sources\r
+   Clear status bits\r
+\r
+   Disable GPE1 sources\r
+   Clear status bits\r
+\r
+   Guarantee day-of-month alarm is invalid (ACPI 5.0 Section 4.8.2.4 "Real Time Clock Alarm")\r
+\r
+   Enable SCI\r
+\r
+  @param DispatchHandle  - EFI Handle\r
+  @param DispatchContext - Pointer to the EFI_SMM_SW_DISPATCH_CONTEXT\r
+\r
+  @retval Nothing\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+EnableAcpiCallback (\r
+  IN  EFI_HANDLE                    DispatchHandle,\r
+  IN  EFI_SMM_SW_DISPATCH_CONTEXT   *DispatchContext\r
+  )\r
+{\r
+  UINT32 SmiEn;\r
+  UINT16 Pm1Cnt;\r
+  UINT16 wordValue;\r
+  UINT32 RegData32;\r
+\r
+  //\r
+  // Disable SW SMI Timer\r
+  //\r
+  SmiEn = IoRead32(mAcpiBaseAddr + R_PCH_SMI_EN);\r
+  SmiEn &= ~B_PCH_SMI_STS_SWSMI_TMR;\r
+  IoWrite32(mAcpiBaseAddr + R_PCH_SMI_EN, SmiEn);\r
+\r
+  wordValue = IoRead16(mAcpiBaseAddr + R_PCH_ACPI_PM1_STS);\r
+  if(wordValue & B_PCH_ACPI_PM1_STS_WAK) {\r
+         IoWrite32((mAcpiBaseAddr + R_PCH_ACPI_GPE0a_EN), 0x0000);\r
+         IoWrite32((mAcpiBaseAddr + R_PCH_ACPI_GPE0a_STS), 0xffffffff);\r
+  }\r
+  else {\r
+               mPM1_SaveState16 = IoRead16(mAcpiBaseAddr + R_PCH_ACPI_PM1_EN);\r
+\r
+               //\r
+               // Disable PM sources except power button\r
+               //\r
+    // power button is enabled only for PCAT. Disabled it on Tablet platform\r
+    //\r
+    IoWrite16(mAcpiBaseAddr + R_PCH_ACPI_PM1_EN, B_PCH_ACPI_PM1_EN_PWRBTN);\r
+               IoWrite16(mAcpiBaseAddr + R_PCH_ACPI_PM1_STS, 0xffff);\r
+\r
+               mGPE_SaveState32 = IoRead16(mAcpiBaseAddr + R_PCH_ACPI_GPE0a_EN);\r
+               IoWrite32(mAcpiBaseAddr + R_PCH_ACPI_GPE0a_EN, 0x0000);\r
+               IoWrite32(mAcpiBaseAddr + R_PCH_ACPI_GPE0a_STS, 0xffffffff);\r
+\r
+  }\r
+\r
+  //\r
+  // Guarantee day-of-month alarm is invalid (ACPI 5.0 Section 4.8.2.4 "Real Time Clock Alarm")\r
+  // Clear Status D reg VM bit, Date of month Alarm to make Data in CMOS RAM is no longer Valid\r
+  //\r
+  IoWrite8 (PCAT_RTC_ADDRESS_REGISTER, RTC_ADDRESS_REGISTER_D);\r
+  IoWrite8 (PCAT_RTC_DATA_REGISTER, 0x0);\r
+\r
+\r
+       RegData32 = IoRead32(ACPI_BASE_ADDRESS + R_PCH_ALT_GP_SMI_EN);\r
+       RegData32 &= ~(BIT7);\r
+    IoWrite32((ACPI_BASE_ADDRESS + R_PCH_ALT_GP_SMI_EN), RegData32);\r
+\r
+\r
+  //\r
+  // Enable SCI\r
+  //\r
+  Pm1Cnt = IoRead16(mAcpiBaseAddr + R_PCH_ACPI_PM1_CNT);\r
+  Pm1Cnt |= B_PCH_ACPI_PM1_CNT_SCI_EN;\r
+  IoWrite16(mAcpiBaseAddr + R_PCH_ACPI_PM1_CNT, Pm1Cnt);\r
+\r
+\r
+}\r
+\r
+/**\r
+  SMI handler to disable ACPI mode\r
+\r
+  Dispatched on reads from APM port with value 0xA1\r
+\r
+  ACPI events are disabled and ACPI event status is cleared.\r
+  SCI mode is then disabled.\r
+   Clear all ACPI event status and disable all ACPI events\r
+   Disable PM sources except power button\r
+   Clear status bits\r
+   Disable GPE0 sources\r
+   Clear status bits\r
+   Disable GPE1 sources\r
+   Clear status bits\r
+   Disable SCI\r
+\r
+  @param DispatchHandle  - EFI Handle\r
+  @param DispatchContext - Pointer to the EFI_SMM_SW_DISPATCH_CONTEXT\r
+\r
+  @retval Nothing\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+DisableAcpiCallback (\r
+  IN  EFI_HANDLE                    DispatchHandle,\r
+  IN  EFI_SMM_SW_DISPATCH_CONTEXT   *DispatchContext\r
+  )\r
+{\r
+  UINT16 Pm1Cnt;\r
+\r
+  IoWrite16(mAcpiBaseAddr + R_PCH_ACPI_PM1_STS, 0xffff);\r
+  IoWrite16(mAcpiBaseAddr + R_PCH_ACPI_PM1_EN, mPM1_SaveState16);\r
+\r
+  IoWrite32(mAcpiBaseAddr + R_PCH_ACPI_GPE0a_STS, 0xffffffff);\r
+  IoWrite32(mAcpiBaseAddr + R_PCH_ACPI_GPE0a_EN, mGPE_SaveState32);\r
+\r
+  //\r
+  // Disable SCI\r
+  //\r
+  Pm1Cnt = IoRead16(mAcpiBaseAddr + R_PCH_ACPI_PM1_CNT);\r
+  Pm1Cnt &= ~B_PCH_ACPI_PM1_CNT_SCI_EN;\r
+  IoWrite16(mAcpiBaseAddr + R_PCH_ACPI_PM1_CNT, Pm1Cnt);\r
+\r
+}\r
+\r
+/**\r
+  When an unknown event happen.\r
+\r
+ @retval None\r
+\r
+**/\r
+VOID\r
+DummyTco1Callback (\r
+  IN  EFI_HANDLE                              DispatchHandle,\r
+  IN  EFI_SMM_ICHN_DISPATCH_CONTEXT           *DispatchContext\r
+  )\r
+{\r
+}\r
+\r
+UINTN\r
+DevicePathSize (\r
+  IN EFI_DEVICE_PATH_PROTOCOL  *DevicePath\r
+  )\r
+{\r
+  EFI_DEVICE_PATH_PROTOCOL     *Start;\r
+\r
+  if (DevicePath == NULL) {\r
+    return 0;\r
+  }\r
+\r
+  //\r
+  // Search for the end of the device path structure\r
+  //\r
+  Start = DevicePath;\r
+  while (!IsDevicePathEnd (DevicePath)) {\r
+    DevicePath = NextDevicePathNode (DevicePath);\r
+  }\r
+\r
+  //\r
+  // Compute the size and add back in the size of the end device path structure\r
+  //\r
+  return ((UINTN)DevicePath - (UINTN)Start) + sizeof(EFI_DEVICE_PATH_PROTOCOL);\r
+}\r
+\r
+/**\r
+\r
+  @param DispatchHandle   The handle of this callback, obtained when registering\r
+  @param DispatchContext  The predefined context which contained sleep type and phase\r
+\r
+**/\r
+VOID\r
+S5SleepWakeOnRtcCallBack (\r
+  IN  EFI_HANDLE                    DispatchHandle,\r
+  IN  EFI_SMM_SX_DISPATCH_CONTEXT   *DispatchContext\r
+  )\r
+{\r
+  EnableS5WakeOnRtc();\r
+}\r
+\r
+/**\r
+\r
+ @retval 1. Check Alarm interrupt is not set.\r
+         2. Clear Alarm interrupt.\r
+         2. Set RTC wake up date and time.\r
+         2. Enable RTC wake up alarm.\r
+         3. Enable ICH PM1 EN Bit 10(RTC_EN)\r
+\r
+**/\r
+VOID\r
+EnableS5WakeOnRtc()\r
+{\r
+  UINT8             CmosData;\r
+  UINTN             i;\r
+  EFI_STATUS        Status;\r
+  UINTN             VarSize;\r
+\r
+  //\r
+  // make sure EFI_SMM_VARIABLE_PROTOCOL is available\r
+  //\r
+  if (!mSmmVariable) {\r
+    return;\r
+  }\r
+\r
+  VarSize = sizeof(SYSTEM_CONFIGURATION);\r
+\r
+  //\r
+  // read the variable into the buffer\r
+  //\r
+  Status = mSmmVariable->SmmGetVariable(\r
+                           L"Setup",\r
+                           &gEfiSetupVariableGuid,\r
+                           NULL,\r
+                           &VarSize,\r
+                           &mSystemConfiguration\r
+                           );\r
+  if (EFI_ERROR(Status) || (!mSystemConfiguration.WakeOnRtcS5)) {\r
+    return;\r
+  }\r
+  mWakeupDay = HexToBcd((UINT8)mSystemConfiguration.RTCWakeupDate);\r
+  mWakeupHour = HexToBcd((UINT8)mSystemConfiguration.RTCWakeupTimeHour);\r
+  mWakeupMinute = HexToBcd((UINT8)mSystemConfiguration.RTCWakeupTimeMinute);\r
+  mWakeupSecond = HexToBcd((UINT8)mSystemConfiguration.RTCWakeupTimeSecond);\r
+\r
+  //\r
+  // Check RTC alarm interrupt is enabled.  If enabled, someone already\r
+  // grabbed RTC alarm.  Just return.\r
+  //\r
+  IoWrite8(PCAT_RTC_ADDRESS_REGISTER, RTC_ADDRESS_REGISTER_B);\r
+  if(IoRead8(PCAT_RTC_DATA_REGISTER) & B_RTC_ALARM_INT_ENABLE){\r
+    return;\r
+  }\r
+\r
+  //\r
+  // Set Date\r
+  //\r
+  IoWrite8(PCAT_RTC_ADDRESS_REGISTER, RTC_ADDRESS_REGISTER_D);\r
+  CmosData = IoRead8(PCAT_RTC_DATA_REGISTER);\r
+  CmosData &= ~(B_RTC_DATE_ALARM_MASK);\r
+  CmosData |= mWakeupDay ;\r
+  for(i = 0 ; i < 0xffff ; i++){\r
+    IoWrite8(PCAT_RTC_DATA_REGISTER, CmosData);\r
+    SmmStall(1);\r
+    if(((CmosData = IoRead8(PCAT_RTC_DATA_REGISTER)) & B_RTC_DATE_ALARM_MASK)\r
+         == mWakeupDay){\r
+      break;\r
+    }\r
+  }\r
+\r
+  //\r
+  // Set Second\r
+  //\r
+  IoWrite8(PCAT_RTC_ADDRESS_REGISTER, RTC_ADDRESS_SECOND_ALARM);\r
+  for(i = 0 ; i < 0xffff ; i++){\r
+    IoWrite8(PCAT_RTC_DATA_REGISTER, mWakeupSecond);\r
+    SmmStall(1);\r
+    if(IoRead8(PCAT_RTC_DATA_REGISTER) == mWakeupSecond){\r
+      break;\r
+    }\r
+  }\r
+\r
+  //\r
+  // Set Minute\r
+  //\r
+  IoWrite8(PCAT_RTC_ADDRESS_REGISTER, RTC_ADDRESS_MINUTE_ALARM);\r
+  for(i = 0 ; i < 0xffff ; i++){\r
+    IoWrite8(PCAT_RTC_DATA_REGISTER, mWakeupMinute);\r
+    SmmStall(1);\r
+    if(IoRead8(PCAT_RTC_DATA_REGISTER) == mWakeupMinute){\r
+      break;\r
+    }\r
+  }\r
+\r
+  //\r
+  // Set Hour\r
+  //\r
+  IoWrite8(PCAT_RTC_ADDRESS_REGISTER, RTC_ADDRESS_HOUR_ALARM);\r
+  for(i = 0 ; i < 0xffff ; i++){\r
+    IoWrite8(PCAT_RTC_DATA_REGISTER, mWakeupHour);\r
+    SmmStall(1);\r
+    if(IoRead8(PCAT_RTC_DATA_REGISTER) == mWakeupHour){\r
+      break;\r
+    }\r
+  }\r
+\r
+  //\r
+  // Wait for UIP to arm RTC alarm\r
+  //\r
+  IoWrite8(PCAT_RTC_ADDRESS_REGISTER, RTC_ADDRESS_REGISTER_A);\r
+  while (IoRead8(PCAT_RTC_DATA_REGISTER) & 0x80);\r
+\r
+  //\r
+  // Read RTC register 0C to clear pending RTC interrupts\r
+  //\r
+  IoWrite8(PCAT_RTC_ADDRESS_REGISTER, RTC_ADDRESS_REGISTER_C);\r
+  IoRead8(PCAT_RTC_DATA_REGISTER);\r
+\r
+  //\r
+  // Enable RTC Alarm Interrupt\r
+  //\r
+  IoWrite8(PCAT_RTC_ADDRESS_REGISTER, RTC_ADDRESS_REGISTER_B);\r
+  IoWrite8(PCAT_RTC_DATA_REGISTER, IoRead8(PCAT_RTC_DATA_REGISTER) | B_RTC_ALARM_INT_ENABLE);\r
+\r
+  //\r
+  // Clear ICH RTC Status\r
+  //\r
+  IoWrite16(mAcpiBaseAddr + R_PCH_ACPI_PM1_STS, B_PCH_ACPI_PM1_STS_RTC);\r
+\r
+  //\r
+  // Enable ICH RTC event\r
+  //\r
+  IoWrite16(mAcpiBaseAddr + R_PCH_ACPI_PM1_EN,\r
+              (UINT16)(IoRead16(mAcpiBaseAddr + R_PCH_ACPI_PM1_EN) | B_PCH_ACPI_PM1_EN_RTC));\r
+}\r
+\r
+UINT8\r
+HexToBcd(\r
+  IN UINT8 HexValue\r
+  )\r
+{\r
+  UINTN   HighByte;\r
+  UINTN   LowByte;\r
+\r
+  HighByte    = (UINTN)HexValue / 10;\r
+  LowByte     = (UINTN)HexValue % 10;\r
+\r
+  return ((UINT8)(LowByte + (HighByte << 4)));\r
+}\r
+\r
+UINT8\r
+BcdToHex(\r
+  IN UINT8 BcdValue\r
+  )\r
+{\r
+  UINTN   HighByte;\r
+  UINTN   LowByte;\r
+\r
+  HighByte    = (UINTN)((BcdValue >> 4) * 10);\r
+  LowByte     = (UINTN)(BcdValue & 0x0F);\r
+\r
+  return ((UINT8)(LowByte + HighByte));\r
+}\r
+\r

diff --git a/Vlv2TbltDevicePkg/PlatformSmm/PlatformSmm.inf b/Vlv2TbltDevicePkg/PlatformSmm/PlatformSmm.inf
new file mode 100644 (file)
index 0000000..69e0a5d
--- /dev/null
+++ b/Vlv2TbltDevicePkg/PlatformSmm/PlatformSmm.inf
@@ -0,0 +1,98 @@
+#\r
+#\r
+# Copyright (c)  1999  - 2014, Intel Corporation. All rights reserved\r
+#                                                                                  \r\r
+# This program and the accompanying materials are licensed and made available under\r\r
+# the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+# The full text of the license may be found at                                     \r\r
+# http://opensource.org/licenses/bsd-license.php.                                  \r\r
+#                                                                                  \r\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+#                                                                                  \r\r
+#\r
+#\r
+#  Module Name:\r
+#\r
+#   Platform.inf\r
+#\r
+#  Abstract:\r
+#\r
+#    Component description file for SMM Platform handler module\r
+#\r
+#--*/\r
+\r
+[Defines]\r
+  INF_VERSION                    = 0x00010005\r
+  BASE_NAME                      = PlatformSmm\r
+  FILE_GUID                      = 99C20A37-042A-46e2-80F4-E4027FDBC86F\r
+  MODULE_TYPE                    = DXE_SMM_DRIVER\r
+  VERSION_STRING                 = 1.0\r
+  ENTRY_POINT                    = InitializePlatformSmm\r
+  PI_SPECIFICATION_VERSION       = 0x0001000A\r
+\r
+#\r
+# The following information is for reference only and not required by the build tools.\r
+#\r
+#  VALID_ARCHITECTURES           = IA32 X64\r
+#\r
+\r
+[Sources]\r
+  S3Save.c\r
+  Platform.c\r
+\r
+[LibraryClasses]\r
+  UefiDriverEntryPoint\r
+  UefiBootServicesTableLib\r
+  DebugLib\r
+  IoLib\r
+  BaseLib\r
+  BaseMemoryLib\r
+  DevicePathLib\r
+  HobLib\r
+  S3BootScriptLib\r
+  StallSmmLib\r
+  PchPlatformLib\r
+\r
+[Guids]\r
+  gEfiSetupVariableGuid\r
+  gDmiDataGuid\r
+  gEfiAcpiVariableCompatiblityGuid\r
+  gEfiPciLanInfoGuid\r
+  gEfiPciLanInfoGuid\r
+\r
+[FeaturePcd]\r
+  gEfiMdeModulePkgTokenSpaceGuid.PcdDxeIplSwitchToLongMode\r
+\r
+[Protocols]\r
+  gEfiSmmBaseProtocolGuid\r
+  gEfiSmmIchnDispatchProtocolGuid\r
+  gEfiGlobalNvsAreaProtocolGuid\r
+  gEfiSmmSwDispatchProtocolGuid\r
+  gEfiSmmPowerButtonDispatchProtocolGuid\r
+  gEfiSmmSxDispatchProtocolGuid\r
+  gEfiSmmVariableProtocolGuid\r
+  gEfiCpuIo2ProtocolGuid\r
+\r
+[Packages]\r
+  MdePkg/MdePkg.dec\r
+  MdeModulePkg/MdeModulePkg.dec\r
+  IntelFrameworkPkg/IntelFrameworkPkg.dec\r
+  Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec\r
+  Vlv2TbltDevicePkg/PlatformPkg.dec\r
+  IntelFrameworkModulePkg/IntelFrameworkModulePkg.dec\r
+\r
+[Pcd.common]\r
+  gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress\r
+\r
+[Depex]\r
+  gEfiSmmBaseProtocolGuid                 AND\r
+  gEfiSmmAccess2ProtocolGuid               AND\r
+  gEfiSmmPowerButtonDispatchProtocolGuid  AND\r
+  gEfiSmmSxDispatchProtocolGuid           AND\r
+  gEfiSmmIchnDispatchProtocolGuid         AND\r
+  gEfiSmmSwDispatchProtocolGuid           AND\r
+  gEfiVariableArchProtocolGuid            AND\r
+  gEfiVariableWriteArchProtocolGuid       AND\r
+  gEfiGlobalNvsAreaProtocolGuid\r
+\r

diff --git a/Vlv2TbltDevicePkg/PlatformSmm/S3Save.c b/Vlv2TbltDevicePkg/PlatformSmm/S3Save.c
new file mode 100644 (file)
index 0000000..8c7112b
--- /dev/null
+++ b/Vlv2TbltDevicePkg/PlatformSmm/S3Save.c
@@ -0,0 +1,382 @@
+/** @file\r
+\r
+  Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+\r
+Module Name:\r
+\r
+    IchS3Save.c\r
+\r
+Abstract:\r
+\r
+    SMM S3 handler Driver implementation file\r
+\r
+Revision History\r
+\r
+**/\r
+#include "SmmPlatform.h"\r
+\r
+extern  UINT16                          mAcpiBaseAddr;\r
+EFI_PHYSICAL_ADDRESS                    mRuntimeScriptTableBase;\r
+\r
+EFI_STATUS\r
+InitRuntimeScriptTable (\r
+  IN EFI_SYSTEM_TABLE  *SystemTable\r
+  )\r
+{\r
+  EFI_STATUS        Status;\r
+  UINT32            VarAttrib;\r
+  UINTN             VarSize;\r
+  ACPI_VARIABLE_SET_COMPATIBILITY *AcpiVariableBase;\r
+\r
+  //\r
+  // Allocate runtime ACPI script table space. We need it to save some\r
+  // settings done by CSM, which runs after normal script table closed\r
+  //\r
+  Status = gBS->AllocatePages (\r
+                  AllocateAnyPages,\r
+                  EfiACPIReclaimMemory,\r
+                  1,\r
+                  &mRuntimeScriptTableBase\r
+                  );\r
+  if (EFI_ERROR(Status)) {\r
+    return EFI_OUT_OF_RESOURCES ;\r
+  }\r
+\r
+  //\r
+  // Save runtime script table base into global ACPI variable\r
+  //\r
+  VarAttrib = EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS\r
+              | EFI_VARIABLE_NON_VOLATILE;\r
+  VarSize   = sizeof (UINTN);\r
+  Status = SystemTable->RuntimeServices->GetVariable (\r
+                          ACPI_GLOBAL_VARIABLE,\r
+                          &gEfiAcpiVariableCompatiblityGuid,\r
+                          &VarAttrib,\r
+                          &VarSize,\r
+                          &AcpiVariableBase\r
+                          );\r
+  if (EFI_ERROR(Status)) {\r
+    return Status;\r
+  }\r
+\r
+  AcpiVariableBase->RuntimeScriptTableBase = mRuntimeScriptTableBase;\r
+\r
+  return EFI_SUCCESS;\r
+}\r
+\r
+EFI_STATUS\r
+SaveRuntimeScriptTable (\r
+  VOID\r
+  )\r
+{\r
+  SMM_PCI_IO_ADDRESS    PciAddress;\r
+  UINT32                Data32;\r
+  UINT16                Data16;\r
+  UINT8                 Data8;\r
+  UINT8                 Mask;\r
+  UINTN                 Index;\r
+  UINTN                 Offset;\r
+  UINT8                 RegTable[] = {\r
+\r
+         //\r
+    //Bus  ,   Dev,  Func,    DMI\r
+         //\r
+      0x00 ,  0x00,  0x00,\r
+\r
+         //\r
+    //00-1F, 20-3F, 40-5F, 60-7F, 80-9F, A0-BF, C0-DF, E0-FF\r
+         //\r
+      0x00 ,  0x08,  0x00,  0x00,  0x30,  0x00,  0x00,  0xa0,\r
+\r
+         //\r
+    //Bus  ,   Dev,  Func,    LPC device\r
+         //\r
+      0x00 ,  0x1F,  0x00,\r
+\r
+         //\r
+    //00-1F, 20-3F, 40-5F, 60-7F, 80-9F, A0-BF, C0-DF, E0-FF\r
+    //\r
+      0x00 ,  0x08,  0x00,  0x07,  0x00,  0x00,  0x90,  0x00,\r
+\r
+         //\r
+    //Bus  ,   Dev,  Func,    PCIE device\r
+        //\r
+      0x00 ,  0x1C,  0x00,\r
+\r
+         //\r
+    //00-1F, 20-3F, 40-5F, 60-7F, 80-9F, A0-BF, C0-DF, E0-FF\r
+    //\r
+      0xC0 ,  0x83,  0x30,  0x00,  0x00,  0x00,  0x00,  0x00,\r
+\r
+         //\r
+    //Bus  ,   Dev,  Func,    PCIE device\r
+    //\r
+         0x00 ,  0x1C,  0x00,\r
+\r
+         //\r
+    //00-1F, 20-3F, 40-5F, 60-7F, 80-9F, A0-BF, C0-DF, E0-FF\r
+    //\r
+      0x03 ,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,\r
+\r
+         //\r
+    //Bus  ,   Dev,  Func,    SATA device\r
+         //\r
+      0x00 ,  0x13,  0x00,\r
+\r
+         //\r
+    //00-1F, 20-3F, 40-5F, 60-7F, 80-9F, A0-BF, C0-DF, E0-FF\r
+    //\r
+      0xf4 ,  0xab,  0x27,  0x10,  0xf1,  0x1d,  0x00,  0x40,\r
+\r
+    //\r
+    //Bus  ,   Dev,  Func,    EHCI device\r
+    //\r
+     0x00 ,  0x1D,  0x00,\r
+\r
+    //\r
+    //00-1F, 20-3F, 40-5F, 60-7F, 80-9F, A0-BF, C0-DF, E0-FF\r
+    //\r
+     0x10 ,  0x88,  0x00,  0x00,  0x00,  0x00,  0x00,  0x80,\r
+\r
+    //\r
+    //Bus  ,   Dev,  Func,    SMBUS device\r
+    //\r
+     0x00 ,  0x1f,  0x03,\r
+\r
+    //\r
+    //00-1F, 20-3F, 40-5F, 60-7F, 80-9F, A0-BF, C0-DF, E0-FF\r
+    //\r
+      0x10 ,  0x89,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,\r
+\r
+    //\r
+    //Bus  ,   Dev,  Func,    SMBUS device\r
+    //\r
+      0x00 ,  0x1f,  0x03,\r
+\r
+    //\r
+    //00-1F, 20-3F, 40-5F, 60-7F, 80-9F, A0-BF, C0-DF, E0-FF\r
+    //\r
+      0x02 ,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,\r
+\r
+    //\r
+    //Bus  ,   Dev,  Func,    VGA bus1\r
+    //\r
+      0x01 ,  0x00,  0x00,\r
+\r
+    //\r
+    //00-1F, 20-3F, 40-5F, 60-7F, 80-9F, A0-BF, C0-DF, E0-FF\r
+    //\r
+      0x58 ,  0x81,  0x18,  0x01,  0xb0,  0x00,  0x00,  0x00,\r
+\r
+    //\r
+    //Bus  ,   Dev,  Func,    VGA bus1\r
+    //\r
+      0x01 ,  0x00,  0x00,\r
+\r
+    //\r
+    //00-1F, 20-3F, 40-5F, 60-7F, 80-9F, A0-BF, C0-DF, E0-FF\r
+    //\r
+      0x02 ,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,\r
+\r
+    //\r
+    //Bus  ,   Dev,  Func,    VGA bus1 function 1\r
+    //\r
+      0x01 ,  0x00,  0x01,\r
+\r
+    //\r
+    //00-1F, 20-3F, 40-5F, 60-7F, 80-9F, A0-BF, C0-DF, E0-FF\r
+    //\r
+      0x51 ,  0x80,  0x80,  0x01,  0x00,  0x00,  0x00,  0x00,\r
+\r
+    //\r
+    //Bus  ,   Dev,  Func,    VGA bus1 function 1\r
+    //\r
+      0x01 ,  0x00,  0x01,\r
+\r
+    //\r
+    //00-1F, 20-3F, 40-5F, 60-7F, 80-9F, A0-BF, C0-DF, E0-FF\r
+    //\r
+      0x02 ,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,\r
+\r
+    //\r
+    //Bus  ,   Dev,  Func,    IGD bus0 function 0\r
+    //\r
+      0x00 ,  0x02,  0x00,\r
+\r
+    //\r
+    //00-1F, 20-3F, 40-5F, 60-7F, 80-9F, A0-BF, C0-DF, E0-FF\r
+    //\r
+      0x42 ,  0x81,  0x00,  0x00,  0x00,  0x00,  0x20,  0x00,\r
+\r
+    //\r
+    //Bus  ,   Dev,  Func,    USB bus0 function 0\r
+    //\r
+      0x00 ,  0x16,  0x00,\r
+\r
+    //\r
+    //00-1F, 20-3F, 40-5F, 60-7F, 80-9F, A0-BF, C0-DF, E0-FF\r
+    //\r
+      0x32 ,  0x80,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,\r
+\r
+    //\r
+    //Bus  ,   Dev,  Func,    HD Audio bus0 function 0\r
+    //\r
+      0x00 ,  0x1B,  0x00,\r
+\r
+    //\r
+    //00-1F, 20-3F, 40-5F, 60-7F, 80-9F, A0-BF, C0-DF, E0-FF\r
+    //\r
+      0x00 ,  0x00,  0x00,  0x00,  0x00,  0x00,  0x02,  0x00,\r
+\r
+    //\r
+    //0xFF indicates the end of the table\r
+    //\r
+      0xFF\r
+ };\r
+\r
+  //\r
+  // These registers have to set in byte order\r
+  //\r
+  UINT8                 ExtReg[] = { 0x9E, 0x9D };  // SMRAM settings\r
+\r
+\r
+\r
+  //\r
+  // Save PCI-Host bridge settings (0, 0, 0). 0x90, 94 and 9c are changed by CSM\r
+  // and vital to S3 resume. That's why we put save code here\r
+  //\r
+  PciAddress.Bus      = 0;\r
+  PciAddress.Device   = 0;\r
+  PciAddress.Function = 0;\r
+  PciAddress.ExtendedRegister = 0;\r
+\r
+  for (Index = 0; Index < 2; Index++) {\r
+    //\r
+    // Read SRAM setting from Pci(0, 0, 0)\r
+    //\r
+    PciAddress.Register = ExtReg[Index];\r
+    Data8 = MmioRead8 (\r
+              MmPciAddress (0,\r
+                PciAddress.Bus,\r
+                PciAddress.Device,\r
+                PciAddress.Function,\r
+                PciAddress.Register\r
+              )\r
+            );\r
+\r
+    //\r
+    // Save latest settings to runtime script table\r
+    //\r
+    S3BootScriptSavePciCfgWrite(\r
+      S3BootScriptWidthUint8,\r
+      *(UINT64*)&PciAddress,\r
+      1,\r
+      &Data8\r
+      );\r
+  }\r
+\r
+\r
+  //\r
+  // Save PCI-Host bridge settings (0, 0, 0). 0x90, 94 and 9c are changed by CSM\r
+  // and vital to S3 resume. That's why we put save code here\r
+  //\r
+  Index = 0;\r
+  while (RegTable[Index] != 0xFF) {\r
+\r
+    PciAddress.Bus      = RegTable[Index++];\r
+    PciAddress.Device   = RegTable[Index++];\r
+    PciAddress.Function = RegTable[Index++];\r
+    PciAddress.Register = 0;\r
+    PciAddress.ExtendedRegister = 0;\r
+\r
+    Data16 = MmioRead16 (\r
+              MmPciAddress (0,\r
+                PciAddress.Bus,\r
+                PciAddress.Device,\r
+                PciAddress.Function,\r
+                PciAddress.Register\r
+              )\r
+            );\r
+\r
+    if (Data16 == 0xFFFF) {\r
+      Index+=8;\r
+      continue;\r
+    }\r
+\r
+    for (Offset = 0, Mask = 0x01; Offset < 256; Offset+=4, Mask<<=1) {\r
+\r
+      if (Mask == 0x00) {\r
+        Mask = 0x01;\r
+      }\r
+\r
+      if (RegTable[Index + Offset/32] & Mask ) {\r
+\r
+        PciAddress.Register = (UINT8)Offset;\r
+        Data32 = MmioRead32 (MmPciAddress (0, PciAddress.Bus, PciAddress.Device, PciAddress.Function, PciAddress.Register));\r
+\r
+        //\r
+        // Save latest settings to runtime script table\r
+        //\r
+        S3BootScriptSavePciCfgWrite (\r
+          S3BootScriptWidthUint32,\r
+          *(UINT64*)&PciAddress,\r
+          1,\r
+          &Data32\r
+        );\r
+      }\r
+    }\r
+\r
+    Index += 8;\r
+\r
+  }\r
+\r
+\r
+  //\r
+  // Save I/O ports to S3 script table\r
+  //\r
+\r
+  //\r
+  // Selftest KBC\r
+  //\r
+  Data8 = 0xAA;\r
+  S3BootScriptSaveIoWrite (\r
+    S3BootScriptWidthUint8,\r
+    0x64,\r
+    (UINTN)1,\r
+    &Data8\r
+    );\r
+\r
+  Data32 = IoRead32(mAcpiBaseAddr + R_PCH_SMI_EN);\r
+\r
+  S3BootScriptSaveIoWrite (\r
+      S3BootScriptWidthUint32,\r
+      (mAcpiBaseAddr + R_PCH_SMI_EN),\r
+      1,\r
+      &Data32\r
+      );\r
+\r
+  //\r
+  // Save B_ICH_TCO_CNT_LOCK so it will be done on S3 resume path.\r
+  //\r
+  Data16 = IoRead16(mAcpiBaseAddr + R_PCH_TCO_CNT);\r
+\r
+  S3BootScriptSaveIoWrite (\r
+      S3BootScriptWidthUint16,\r
+      mAcpiBaseAddr + R_PCH_TCO_CNT,\r
+      1,\r
+      &Data16\r
+      );\r
+\r
+\r
+  return EFI_SUCCESS;\r
+}\r

diff --git a/Vlv2TbltDevicePkg/PlatformSmm/SmmPlatform.h b/Vlv2TbltDevicePkg/PlatformSmm/SmmPlatform.h
new file mode 100644 (file)
index 0000000..0bf76dd
--- /dev/null
+++ b/Vlv2TbltDevicePkg/PlatformSmm/SmmPlatform.h
@@ -0,0 +1,245 @@
+/*++\r
+\r
+  Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+Module Name:\r
+\r
+  SmmPlatform.h\r
+\r
+Abstract:\r
+\r
+  Header file for\r
+\r
+++*/\r
+\r
+#ifndef _PLATFORM_H\r
+#define _PLATFORM_H\r
+\r
+#include <PiSmm.h>\r
+\r
+\r
+\r
+#include <Protocol/SmmBase.h>\r
+#include <Protocol/FirmwareVolume.h>\r
+#include <Protocol/SmmPowerButtonDispatch.h>\r
+#include <Protocol/SmmSxDispatch.h>\r
+#include <Protocol/SmmSwDispatch.h>\r
+#include <Protocol/SmmSwDispatch2.h>\r
+#include <Protocol/SmmIchnDispatch.h>\r
+#include <Protocol/SmmAccess.h>\r
+#include <Protocol/SmmVariable.h>\r
+#include <Protocol/PciRootBridgeIo.h>\r
+#include <Protocol/LoadedImage.h>\r
+#include "Protocol/GlobalNvsArea.h"\r
+#include <Guid/AcpiVariableCompatibility.h>\r
+#include <Guid/SetupVariable.h>\r
+#include <Guid/EfiVpdData.h>\r
+#include <Guid/PciLanInfo.h>\r
+#include <IndustryStandard/Pci22.h>\r
+\r
+#include "PchAccess.h"\r
+#include "PlatformBaseAddresses.h"\r
+\r
+#include <Library/UefiBootServicesTableLib.h>\r
+#include <Library/S3BootScriptLib.h>\r
+#include <Library/IoLib.h>\r
+#include <Library/DebugLib.h>\r
+#include <Library/HobLib.h>\r
+#include <Library/BaseLib.h>\r
+#include <Library/BaseMemoryLib.h>\r
+#include <Library/DevicePathLib.h>\r
+#include <Library/PcdLib.h>\r
+#include <Library/PchPlatformLib.h>\r
+#include <Library/StallSmmLib.h>\r
+\r
+\r
+\r
+typedef struct {\r
+  UINT8     Register;\r
+  UINT8     Function;\r
+  UINT8     Device;\r
+  UINT8     Bus;\r
+  UINT32    ExtendedRegister;\r
+} SMM_PCI_IO_ADDRESS;\r
+\r
+typedef struct {\r
+  CHAR8     BoardAaNumber[7];\r
+  UINTN     BoardFabNumber;\r
+} BOARD_AA_NUMBER_DECODE;\r
+\r
+//\r
+// BugBug -- Need to get these two values from acpi.h, but right now, they are\r
+//           declared in platform-specific variants of this file, so no easy\r
+//           way to pick-up the include file and work across platforms.\r
+//           Need these definitions to go into a file like common\acpi.h.\r
+//\r
+#define ACPI_ENABLE                 0xA0\r
+#define ACPI_DISABLE                0xA1\r
+\r
+#define APM_12_FUNCS                  0x50\r
+#define SMI_SET_SMMVARIABLE_PROTOCOL  0x51  // this is used in Cpu\Pentium\Smm\Base\SmmBase.c\r
+\r
+#define SMI_CMD_GET_MSEG_STATUS     0x70\r
+#define SMI_CMD_UPDATE_MSEG_SIZE    0x71\r
+#define SMI_CMD_LOAD_STM            0x72\r
+#define SMI_CMD_UNLOAD_STM          0x73\r
+#define SMI_CMD_GET_SMRAM_RANGES    0x74\r
+\r
+\r
+#define PCAT_RTC_ADDRESS_REGISTER   0x74\r
+#define PCAT_RTC_DATA_REGISTER      0x75\r
+\r
+#define RTC_ADDRESS_SECOND          0x00\r
+#define RTC_ADDRESS_SECOND_ALARM    0x01\r
+#define RTC_ADDRESS_MINUTE          0x02\r
+#define RTC_ADDRESS_MINUTE_ALARM    0x03\r
+#define RTC_ADDRESS_HOUR            0x04\r
+#define RTC_ADDRESS_HOUR_ALARM      0x05\r
+\r
+#define RTC_ADDRESS_REGISTER_A      0x0A\r
+#define RTC_ADDRESS_REGISTER_B      0x0B\r
+#define RTC_ADDRESS_REGISTER_C      0x0C\r
+#define RTC_ADDRESS_REGISTER_D      0x0D\r
+\r
+#define B_RTC_ALARM_INT_ENABLE      0x20\r
+#define B_RTC_ALARM_INT_STATUS      0x20\r
+\r
+#define B_RTC_DATE_ALARM_MASK       0x3F\r
+\r
+#define PCAT_CMOS_2_ADDRESS_REGISTER  0x72\r
+#define PCAT_CMOS_2_DATA_REGISTER     0x73\r
+\r
+#define EC_C_PORT                     0x66\r
+#define SMC_SMI_DISABLE               0xBC\r
+#define SMC_ENABLE_ACPI_MODE          0xAA  // Enable ACPI mode\r
+\r
+#define IO_MISC 156\r
+\r
+\r
+#define MAXIMUM_NUMBER_OF_PSTATES           12\r
+#define  ICH_SMM_DATA_PORT                  0xB3\r
+\r
+#define EFI_IA32_PMG_CST_CONFIG               0x000000E2\r
+#define   B_EFI_CST_CONTROL_LOCK                BIT15\r
+#define   B_EFI_IO_MWAIT_REDIRECTION_ENABLE     BIT10\r
+#define EFI_IA32_PMG_IO_CAPTURE_ADDR          0x000000E4\r
+\r
+extern EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *mPciRootBridgeIo;\r
+\r
+//\r
+// Callback function prototypes\r
+//\r
+VOID\r
+EFIAPI\r
+PowerButtonCallback (\r
+  IN  EFI_HANDLE                              DispatchHandle,\r
+  IN  EFI_SMM_POWER_BUTTON_DISPATCH_CONTEXT   *DispatchContext\r
+  );\r
+\r
+VOID\r
+S5SleepWakeOnLanCallBack (\r
+  IN  EFI_HANDLE                    DispatchHandle,\r
+  IN  EFI_SMM_SX_DISPATCH_CONTEXT   *DispatchContext\r
+  );\r
+\r
+VOID\r
+EFIAPI\r
+S5SleepAcLossCallBack (\r
+  IN  EFI_HANDLE                    DispatchHandle,\r
+  IN  EFI_SMM_SX_DISPATCH_CONTEXT   *DispatchContext\r
+  );\r
+\r
+\r
+VOID\r
+EFIAPI    \r
+S4S5CallBack (\r
+  IN  EFI_HANDLE                    DispatchHandle,\r
+  IN  EFI_SMM_SX_DISPATCH_CONTEXT   *DispatchContext\r
+  );\r
+\r
+VOID\r
+EFIAPI    \r
+EnableAcpiCallback (\r
+  IN  EFI_HANDLE                    DispatchHandle,\r
+  IN  EFI_SMM_SW_DISPATCH_CONTEXT   *DispatchContext\r
+  );\r
+\r
+VOID\r
+EFIAPI\r
+DisableAcpiCallback (\r
+  IN  EFI_HANDLE                    DispatchHandle,\r
+  IN  EFI_SMM_SW_DISPATCH_CONTEXT   *DispatchContext\r
+  );\r
+\r
+VOID\r
+EFIAPI\r
+SmmReadyToBootCallback (\r
+  IN  EFI_HANDLE                    DispatchHandle,\r
+  IN  EFI_SMM_SW_DISPATCH_CONTEXT   *DispatchContext\r
+  );\r
+\r
+VOID\r
+DummyTco1Callback (\r
+  IN  EFI_HANDLE                              DispatchHandle,\r
+  IN  EFI_SMM_ICHN_DISPATCH_CONTEXT           *DispatchContext\r
+  );\r
+\r
+\r
+VOID\r
+PerrSerrCallback (\r
+  IN  EFI_HANDLE                              DispatchHandle,\r
+  IN  EFI_SMM_ICHN_DISPATCH_CONTEXT           *DispatchContext\r
+  );\r
+\r
+VOID\r
+RiCallback (\r
+  IN  EFI_HANDLE                              DispatchHandle,\r
+  IN  EFI_SMM_ICHN_DISPATCH_CONTEXT           *DispatchContext\r
+  );\r
+\r
+\r
+VOID\r
+SetAfterG3On (\r
+  BOOLEAN Enable\r
+  );\r
+\r
+VOID\r
+TurnOffVregUsb (\r
+  );\r
+\r
+VOID\r
+PStateSupportCallback (\r
+  IN  EFI_HANDLE                              DispatchHandle,\r
+  IN  EFI_SMM_SW_DISPATCH_CONTEXT             *DispatchContext\r
+  );\r
+\r
+VOID\r
+PStateTransitionCallback (\r
+  IN  EFI_HANDLE                              DispatchHandle,\r
+  IN  EFI_SMM_SW_DISPATCH_CONTEXT             *DispatchContext\r
+  );\r
+\r
+EFI_STATUS\r
+EFIAPI    \r
+SxSleepEntryCallBack (\r
+  IN  EFI_HANDLE                    DispatchHandle,\r
+  IN  EFI_SMM_SX_DISPATCH_CONTEXT   *DispatchContext\r
+  );\r
+\r
+EFI_STATUS\r
+SaveRuntimeScriptTable (\r
+  VOID\r
+  );\r
+\r
+\r
+#endif\r
+\r

diff --git a/Vlv2TbltDevicePkg/PlatformSmm/SmmScriptSave.c b/Vlv2TbltDevicePkg/PlatformSmm/SmmScriptSave.c
new file mode 100644 (file)
index 0000000..09a6a8c
--- /dev/null
+++ b/Vlv2TbltDevicePkg/PlatformSmm/SmmScriptSave.c
@@ -0,0 +1,257 @@
+/** @file\r
+\r
+  Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+\r
+Module Name:\r
+\r
+\r
+    SmmScriptSave.c\r
+\r
+Abstract:\r
+\r
+    ScriptTableSave module at run time\r
+\r
+--*/\r
+\r
+#include "SmmScriptSave.h"\r
+\r
+//\r
+// internal functions\r
+//\r
+\r
+EFI_STATUS\r
+BootScriptIoWrite  (\r
+  IN EFI_SMM_SCRIPT_TABLE     *ScriptTable,\r
+  IN VA_LIST                  Marker\r
+  );\r
+\r
+EFI_STATUS\r
+BootScriptPciCfgWrite  (\r
+  IN EFI_SMM_SCRIPT_TABLE     *ScriptTable,\r
+  IN VA_LIST                  Marker\r
+  );\r
+\r
+VOID\r
+SmmCopyMem (\r
+  IN  UINT8    *Destination,\r
+  IN  UINT8    *Source,\r
+  IN  UINTN    ByteCount\r
+  );\r
+\r
+//\r
+// Function implementations\r
+//\r
+EFI_STATUS\r
+SmmBootScriptWrite (\r
+  IN OUT EFI_SMM_SCRIPT_TABLE    *ScriptTable,\r
+  IN UINTN                       Type,\r
+  IN UINT16                      OpCode,\r
+  ...\r
+  )\r
+{\r
+  EFI_STATUS    Status;\r
+  VA_LIST       Marker;\r
+\r
+  if (ScriptTable == NULL) {\r
+    return EFI_INVALID_PARAMETER;\r
+  }\r
+\r
+  //\r
+  // Build script according to opcode\r
+  //\r
+  switch ( OpCode ) {\r
+\r
+    case EFI_BOOT_SCRIPT_IO_WRITE_OPCODE:\r
+      VA_START(Marker, OpCode);\r
+      Status = BootScriptIoWrite (ScriptTable, Marker);\r
+      VA_END(Marker);\r
+      break;\r
+\r
+    case EFI_BOOT_SCRIPT_PCI_CONFIG_WRITE_OPCODE:\r
+      VA_START(Marker, OpCode);\r
+      Status = BootScriptPciCfgWrite(ScriptTable, Marker);\r
+      VA_END(Marker);\r
+      break;\r
+\r
+    default:\r
+      Status = EFI_SUCCESS;\r
+      break;\r
+  }\r
+\r
+  return Status;\r
+}\r
+\r
+\r
+EFI_STATUS\r
+SmmBootScriptCreateTable (\r
+  IN OUT EFI_SMM_SCRIPT_TABLE    *ScriptTable,\r
+  IN UINTN                       Type\r
+  )\r
+{\r
+  BOOT_SCRIPT_POINTERS          Script;\r
+  UINT8                         *Buffer;\r
+\r
+  if (ScriptTable == NULL) {\r
+    return EFI_INVALID_PARAMETER;\r
+  }\r
+\r
+  Buffer = (UINT8*) ((UINTN)(*ScriptTable));\r
+\r
+  //\r
+  // Fill Table Header\r
+  //\r
+  Script.Raw = Buffer;\r
+  Script.TableInfo->OpCode      = EFI_BOOT_SCRIPT_TABLE_OPCODE;\r
+  Script.TableInfo->Length      = sizeof(EFI_BOOT_SCRIPT_TABLE_HEADER);\r
+  Script.TableInfo->TableLength = sizeof(EFI_BOOT_SCRIPT_TABLE_HEADER);\r
+\r
+  //\r
+  // Update current table pointer\r
+  //\r
+  *ScriptTable = *ScriptTable + sizeof(EFI_BOOT_SCRIPT_TABLE_HEADER);\r
+  return EFI_SUCCESS;\r
+}\r
+\r
+\r
+EFI_STATUS\r
+SmmBootScriptCloseTable (\r
+  IN EFI_SMM_SCRIPT_TABLE        ScriptTableBase,\r
+  IN EFI_SMM_SCRIPT_TABLE        ScriptTablePtr,\r
+  IN UINTN                       Type\r
+  )\r
+{\r
+  BOOT_SCRIPT_POINTERS    Script;\r
+\r
+  //\r
+  // Add final "termination" node to script table\r
+  //\r
+  Script.Raw               = (UINT8*) ((UINTN)ScriptTablePtr);\r
+  Script.Terminate->OpCode = EFI_BOOT_SCRIPT_TERMINATE_OPCODE;\r
+  Script.Terminate->Length = sizeof (EFI_BOOT_SCRIPT_TERMINATE);\r
+  ScriptTablePtr          += sizeof (EFI_BOOT_SCRIPT_TERMINATE);\r
+\r
+\r
+  //\r
+  // Update Table Header\r
+  //\r
+  Script.Raw                    = (UINT8*) ((UINTN)ScriptTableBase);\r
+  Script.TableInfo->OpCode      = EFI_BOOT_SCRIPT_TABLE_OPCODE;\r
+  Script.TableInfo->Length      = sizeof (EFI_BOOT_SCRIPT_TABLE_HEADER);\r
+  Script.TableInfo->TableLength = (UINT32)(ScriptTablePtr - ScriptTableBase);\r
+\r
+  return EFI_SUCCESS;\r
+}\r
+\r
+\r
+EFI_STATUS\r
+BootScriptIoWrite  (\r
+  IN EFI_SMM_SCRIPT_TABLE     *ScriptTable,\r
+  IN VA_LIST                  Marker\r
+  )\r
+{\r
+  BOOT_SCRIPT_POINTERS    Script;\r
+  EFI_BOOT_SCRIPT_WIDTH   Width;\r
+  UINTN                   Address;\r
+  UINTN                   Count;\r
+  UINT8                   *Buffer;\r
+  UINTN                   NodeLength;\r
+  UINT8                   WidthInByte;\r
+\r
+  Width     = VA_ARG(Marker, EFI_BOOT_SCRIPT_WIDTH);\r
+  Address   = VA_ARG(Marker, UINTN);\r
+  Count     = VA_ARG(Marker, UINTN);\r
+  Buffer    = VA_ARG(Marker, UINT8*);\r
+\r
+  WidthInByte = (UINT8)(0x01 << (Width & 0x03));\r
+  Script.Raw  = (UINT8*) ((UINTN)(*ScriptTable));\r
+  NodeLength  = sizeof (EFI_BOOT_SCRIPT_IO_WRITE) + (WidthInByte * Count);\r
+\r
+  //\r
+  // Build script data\r
+  //\r
+  Script.IoWrite->OpCode  = EFI_BOOT_SCRIPT_IO_WRITE_OPCODE;\r
+  Script.IoWrite->Length  = (UINT8)(NodeLength);\r
+  Script.IoWrite->Width   = Width;\r
+  Script.IoWrite->Address = Address;\r
+  Script.IoWrite->Count   = (UINT32)Count;\r
+  SmmCopyMem (\r
+    (UINT8*)(Script.Raw + sizeof (EFI_BOOT_SCRIPT_IO_WRITE)),\r
+    Buffer,\r
+    WidthInByte * Count\r
+    );\r
+\r
+  //\r
+  // Update Script table pointer\r
+  //\r
+  *ScriptTable = *ScriptTable + NodeLength;\r
+  return EFI_SUCCESS;\r
+}\r
+\r
+\r
+EFI_STATUS\r
+BootScriptPciCfgWrite  (\r
+  IN EFI_SMM_SCRIPT_TABLE        *ScriptTable,\r
+  IN VA_LIST                     Marker\r
+  )\r
+{\r
+  BOOT_SCRIPT_POINTERS    Script;\r
+  EFI_BOOT_SCRIPT_WIDTH   Width;\r
+  UINT64                  Address;\r
+  UINTN                   Count;\r
+  UINT8                   *Buffer;\r
+  UINTN                   NodeLength;\r
+  UINT8                   WidthInByte;\r
+\r
+  Width     = VA_ARG(Marker, EFI_BOOT_SCRIPT_WIDTH);\r
+  Address   = VA_ARG(Marker, UINT64);\r
+  Count     = VA_ARG(Marker, UINTN);\r
+  Buffer    = VA_ARG(Marker, UINT8*);\r
+\r
+  WidthInByte = (UINT8)(0x01 << (Width & 0x03));\r
+  Script.Raw  = (UINT8*) ((UINTN)(*ScriptTable));\r
+  NodeLength  = sizeof (EFI_BOOT_SCRIPT_PCI_CONFIG_WRITE) + (WidthInByte * Count);\r
+\r
+  //\r
+  // Build script data\r
+  //\r
+  Script.PciWrite->OpCode  = EFI_BOOT_SCRIPT_PCI_CONFIG_WRITE_OPCODE;\r
+  Script.PciWrite->Length  = (UINT8)(NodeLength);\r
+  Script.PciWrite->Width   = Width;\r
+  Script.PciWrite->Address = Address;\r
+  Script.PciWrite->Count   = (UINT32)Count;\r
+  SmmCopyMem (\r
+    (UINT8*)(Script.Raw + sizeof (EFI_BOOT_SCRIPT_PCI_CONFIG_WRITE)),\r
+    Buffer,\r
+    WidthInByte * Count\r
+    );\r
+\r
+  //\r
+  // Update Script table pointer\r
+  //\r
+  *ScriptTable = *ScriptTable + NodeLength;\r
+  return EFI_SUCCESS;\r
+}\r
+\r
+VOID\r
+SmmCopyMem (\r
+  IN  UINT8    *Destination,\r
+  IN  UINT8    *Source,\r
+  IN  UINTN    ByteCount\r
+  )\r
+{\r
+  UINTN   Index;\r
+\r
+  for (Index = 0; Index < ByteCount; Index++, Destination++, Source++) {\r
+    *Destination = *Source;\r
+  }\r
+}\r

diff --git a/Vlv2TbltDevicePkg/PlatformSmm/SmmScriptSave.h b/Vlv2TbltDevicePkg/PlatformSmm/SmmScriptSave.h
new file mode 100644 (file)
index 0000000..e2e4bb6
--- /dev/null
+++ b/Vlv2TbltDevicePkg/PlatformSmm/SmmScriptSave.h
@@ -0,0 +1,55 @@
+/*++\r
+\r
+  Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+\r
+Module Name:\r
+\r
+    SmmScriptSave.h\r
+\r
+Abstract:\r
+\r
+  This is an implementation of the BootScript at run time.\r
+\r
+--*/\r
+\r
+#ifndef _RUNTIME_SCRIPT_SAVE_H\r
+#define _RUNTIME_SCRIPT_SAVE_H\r
+\r
+#include "Efi.h"\r
+#include "EfiBootScript.h"\r
+\r
+\r
+typedef EFI_PHYSICAL_ADDRESS     EFI_SMM_SCRIPT_TABLE;\r
+\r
+EFI_STATUS\r
+SmmBootScriptCreateTable (\r
+  IN OUT EFI_SMM_SCRIPT_TABLE    *ScriptTable,\r
+  IN UINTN                       Type\r
+  );\r
+\r
+EFI_STATUS\r
+SmmBootScriptWrite (\r
+  IN OUT EFI_SMM_SCRIPT_TABLE    *ScriptTable,\r
+  IN UINTN                       Type,\r
+  IN UINT16                      OpCode,\r
+  ...\r
+  );\r
+\r
+EFI_STATUS\r
+SmmBootScriptCloseTable (\r
+  IN EFI_SMM_SCRIPT_TABLE        ScriptTableBase,\r
+  IN EFI_SMM_SCRIPT_TABLE        ScriptTablePtr,\r
+  IN UINTN                       Type\r
+  );\r
+\r
+#endif\r

diff --git a/Vlv2TbltDevicePkg/PpmPolicy/PpmPolicy.c b/Vlv2TbltDevicePkg/PpmPolicy/PpmPolicy.c
new file mode 100644 (file)
index 0000000..2f8996b
--- /dev/null
+++ b/Vlv2TbltDevicePkg/PpmPolicy/PpmPolicy.c
@@ -0,0 +1,160 @@
+/** \r
+  Copyright (c) 2009 - 2013, Intel Corporation. All rights reserved.<BR>\r
+  This program and the accompanying materials\r
+  are licensed and made available under the terms and conditions of the BSD License\r
+  which accompanies this distribution.  The full text of the license may be found at\r
+  http://opensource.org/licenses/bsd-license.php\r
+\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+Module Name:\r
+\r
+\r
+  PpmPolicy.c\r
+\r
+Abstract:\r
+\r
+  This file is a wrapper for Intel PPM Platform Policy driver.\r
+  Get Setup Value to initilize Intel PPM DXE Platform Policy.\r
+\r
+--*/\r
+#include "PpmPolicy.h"\r
+#include <Protocol/MpService.h>\r
+#include <Library/BaseLib.h>\r
+#include <Library/DebugLib.h>\r
+#include <Library/CpuIA32.h>\r
+\r
+#include <PchRegs.h>\r
+#include <Library/PchPlatformLib.h>\r
+\r
+#define EFI_CPUID_FAMILY                      0x0F00\r
+#define EFI_CPUID_MODEL                       0x00F0\r
+#define EFI_CPUID_STEPPING                    0x000F\r
+\r
+\r
+\r
+EFI_STATUS \r
+EFIAPI\r
+PpmPolicyEntry(\r
+  IN EFI_HANDLE ImageHandle,\r
+  IN EFI_SYSTEM_TABLE *SystemTable\r
+)\r
+{\r
+  EFI_MP_SERVICES_PROTOCOL *MpService;\r
+  EFI_CPUID_REGISTER        Cpuid01 = { 0, 0, 0, 0};\r
+  EFI_HANDLE                Handle;\r
+  EFI_STATUS                Status;\r
+  UINTN                     CpuCount;\r
+  UINT64                    MaxRatio;\r
+  UINT8                     CPUMobileFeature;\r
+\r
+  PCH_STEPPING              Stepping;\r
+\r
+\r
+  gBS = SystemTable->BootServices;\r
+  pBS = SystemTable->BootServices;\r
+  pRS = SystemTable->RuntimeServices;\r
+\r
+  //\r
+  // Set PPM policy structure to known value\r
+  //\r
+  gBS->SetMem (&mDxePlatformPpmPolicy, sizeof(PPM_PLATFORM_POLICY_PROTOCOL), 0);\r
+\r
+  //\r
+  // Find the MpService Protocol\r
+  //\r
+  Status = pBS->LocateProtocol (&gEfiMpServiceProtocolGuid,\r
+                                NULL,\r
+                                (void **)&MpService\r
+                               );\r
+  ASSERT_EFI_ERROR (Status);\r
+\r
+  //\r
+  // Get processor count from MP service.\r
+  //\r
+  Status = MpService->GetNumberOfProcessors (MpService, &CpuCount, NULL);\r
+  ASSERT_EFI_ERROR (Status);\r
+\r
+  //\r
+  // Store the CPUID for use by SETUP items.\r
+  //\r
+  AsmCpuid (EFI_CPUID_VERSION_INFO, &Cpuid01.RegEax, &Cpuid01.RegEbx, &Cpuid01.RegEcx, &Cpuid01.RegEdx);\r
+  MaxRatio = ((RShiftU64 (AsmReadMsr64(EFI_MSR_IA32_PLATFORM_ID), 8)) & 0x1F);\r
+\r
+\r
+  mDxePlatformPpmPolicy.Revision                       = PPM_PLATFORM_POLICY_PROTOCOL_REVISION_4;\r
+\r
+  //Read CPU Mobile feature from PLATFORM_ID_MSR MSR(0x17) NOTFB_I_AM_NOT_MOBILE_FUSE_CLIAMC00H Bit 28\r
+  //Bit Description: { Disables Mobile features 0 = I am NOT a mobile part 1 = I am a mobile part (default)"}\r
+  CPUMobileFeature = ((RShiftU64 (AsmReadMsr64(EFI_MSR_IA32_PLATFORM_ID), 28)) & 0x1);\r
+\r
+  if (!EFI_ERROR(Status)) {\r
+    if (CPUMobileFeature == 1){//CPU mobile feature\r
+      mDxePlatformPpmPolicy.FunctionEnables.EnableGv       = ICH_DEVICE_ENABLE;\r
+      mDxePlatformPpmPolicy.FunctionEnables.EnableCx       = ICH_DEVICE_ENABLE;\r
+      mDxePlatformPpmPolicy.FunctionEnables.EnableCxe      = ICH_DEVICE_DISABLE;\r
+      mDxePlatformPpmPolicy.FunctionEnables.EnableTm       = ICH_DEVICE_ENABLE;\r
+      //MaxC7\r
+      mDxePlatformPpmPolicy.FunctionEnables.EnableC7       = ICH_DEVICE_ENABLE;\r
+      mDxePlatformPpmPolicy.FunctionEnables.EnableC6       = ICH_DEVICE_ENABLE;\r
+      mDxePlatformPpmPolicy.FunctionEnables.EnableC4       = ICH_DEVICE_ENABLE;\r
+       \r
+      \r
+    }else{//CPU desktop feature\r
+       mDxePlatformPpmPolicy.FunctionEnables.EnableGv       = ICH_DEVICE_DISABLE;\r
+       mDxePlatformPpmPolicy.FunctionEnables.EnableCx       = ICH_DEVICE_DISABLE;\r
+       mDxePlatformPpmPolicy.FunctionEnables.EnableCxe      = ICH_DEVICE_DISABLE;\r
+       mDxePlatformPpmPolicy.FunctionEnables.EnableTm       = ICH_DEVICE_DISABLE;\r
+       mDxePlatformPpmPolicy.FunctionEnables.EnableC4       = ICH_DEVICE_DISABLE;\r
+       mDxePlatformPpmPolicy.FunctionEnables.EnableC6       = ICH_DEVICE_DISABLE;\r
+       mDxePlatformPpmPolicy.FunctionEnables.EnableC7       = ICH_DEVICE_DISABLE;\r
+    }\r
+\r
+\r
+    mDxePlatformPpmPolicy.FunctionEnables.EnableProcHot  = ICH_DEVICE_ENABLE;\r
+    mDxePlatformPpmPolicy.FunctionEnables.TStatesEnable  = ICH_DEVICE_ENABLE;\r
+\r
+    \r
+    Stepping = PchStepping();\r
+    if (Stepping < PchB3) {\r
+      // If SoC is B0~B2 Stepping, disable the Turbo\r
+      mDxePlatformPpmPolicy.FunctionEnables.EnableTurboMode= ICH_DEVICE_DISABLE;\r
+    } else {\r
+      mDxePlatformPpmPolicy.FunctionEnables.EnableTurboMode= ICH_DEVICE_ENABLE;\r
+    }\r
+    \r
+    mDxePlatformPpmPolicy.FunctionEnables.EnableTm      = ICH_DEVICE_ENABLE;\r
+\r
+    mDxePlatformPpmPolicy.FunctionEnables.EnableCMP      = ICH_DEVICE_ENABLE;\r
+\r
+  } else {\r
+    mDxePlatformPpmPolicy.FunctionEnables.EnableGv       = ICH_DEVICE_ENABLE;\r
+    mDxePlatformPpmPolicy.FunctionEnables.EnableCx       = ICH_DEVICE_ENABLE;\r
+    mDxePlatformPpmPolicy.FunctionEnables.EnableCxe      = ICH_DEVICE_ENABLE;\r
+    mDxePlatformPpmPolicy.FunctionEnables.EnableTm      = ICH_DEVICE_ENABLE;\r
+    mDxePlatformPpmPolicy.FunctionEnables.EnableProcHot  = ICH_DEVICE_ENABLE;\r
+    mDxePlatformPpmPolicy.FunctionEnables.EnableCMP       = ICH_DEVICE_DISABLE;\r
+    mDxePlatformPpmPolicy.FunctionEnables.TStatesEnable  = ICH_DEVICE_ENABLE;\r
+    mDxePlatformPpmPolicy.FunctionEnables.EnableTurboMode= ICH_DEVICE_ENABLE;\r
+    mDxePlatformPpmPolicy.FunctionEnables.EnableC4       = ICH_DEVICE_ENABLE;\r
+    mDxePlatformPpmPolicy.FunctionEnables.EnableC6       = ICH_DEVICE_ENABLE;\r
+  }\r
+\r
+\r
+\r
+  mDxePlatformPpmPolicy.S3RestoreMsrSwSmiNumber                       = S3_RESTORE_MSR_SW_SMI;\r
+\r
+  Handle = NULL;\r
+  Status = gBS->InstallMultipleProtocolInterfaces (\r
+                                                  &Handle,\r
+                                                  &gPpmPlatformPolicyProtocolGuid,\r
+                                                  &mDxePlatformPpmPolicy,\r
+                                                  NULL\r
+                                                  );\r
+\r
+  ASSERT_EFI_ERROR (Status);\r
+\r
+  return EFI_SUCCESS;\r
+}\r

diff --git a/Vlv2TbltDevicePkg/PpmPolicy/PpmPolicy.h b/Vlv2TbltDevicePkg/PpmPolicy/PpmPolicy.h
new file mode 100644 (file)
index 0000000..cd3676b
--- /dev/null
+++ b/Vlv2TbltDevicePkg/PpmPolicy/PpmPolicy.h
@@ -0,0 +1,46 @@
+/** \r
+  Copyright (c) 2009 - 2013, Intel Corporation. All rights reserved.<BR>\r
+  This program and the accompanying materials\r
+  are licensed and made available under the terms and conditions of the BSD License\r
+  which accompanies this distribution.  The full text of the license may be found at\r
+  http://opensource.org/licenses/bsd-license.php\r
+\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+\r
+Module Name:\r
+\r
+  PpmPolicy.h\r
+\r
+Abstract:\r
+\r
+  Header file for the PpmPolicyInitDxe Driver.\r
+\r
+--*/\r
+#include <PiDxe.h>\r
+//\r
+// Driver Produced Protocol Prototypes\r
+//\r
+#include <Protocol/PpmPlatformPolicy.h>\r
+\r
+PPM_PLATFORM_POLICY_PROTOCOL    mDxePlatformPpmPolicy;\r
+\r
+// Function Definition\r
+#define  ICH_DEVICE_ENABLE       1\r
+#define  ICH_DEVICE_DISABLE      0\r
+\r
+EFI_BOOT_SERVICES     *gBS;\r
+EFI_BOOT_SERVICES     *pBS;\r
+EFI_RUNTIME_SERVICES  *pRS;\r
+\r
+#define POWER_STATE_SWITCH_SMI                       43\r
+#define ENABLE_C_STATE_IO_REDIRECTION_SMI            70\r
+#define DISABLE_C_STATE_IO_REDIRECTION_SMI           71\r
+#define ENABLE_SMI_C_STATE_COORDINATION_SMI          72\r
+#define DISABLE_SMI_C_STATE_COORDINATION_SMI         73\r
+#define ENABLE_P_STATE_HARDWARE_COORDINATION_SMI     74\r
+#define DISABLE_P_STATE_HARDWARE_COORDINATION_SMI    75\r
+#define S3_RESTORE_MSR_SW_SMI                        48\r
+#define ENABLE_C6_RESIDENCY_SMI                      76
\ No newline at end of file

diff --git a/Vlv2TbltDevicePkg/PpmPolicy/PpmPolicy.inf b/Vlv2TbltDevicePkg/PpmPolicy/PpmPolicy.inf
new file mode 100644 (file)
index 0000000..c5c6076
--- /dev/null
+++ b/Vlv2TbltDevicePkg/PpmPolicy/PpmPolicy.inf
@@ -0,0 +1,55 @@
+#/*++\r
+#\r
+#  Copyright (c)  1999  - 2014, Intel Corporation. All rights reserved\r
+#                                                                                  \r
+# This program and the accompanying materials are licensed and made available under\r
+# the terms and conditions of the BSD License that accompanies this distribution.  \r
+# The full text of the license may be found at                                     \r
+# http://opensource.org/licenses/bsd-license.php.                                  \r
+#                                                                                  \r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r
+#                     \r
+#\r
+#  Module Name:\r
+#\r
+#   PpmPolicy.inf\r
+#\r
+#  Abstract:\r
+#\r
+#    Implement platform power management policy\r
+#\r
+#--*/\r
+\r
+[defines]\r
+  INF_VERSION                    = 0x00010005\r
+  BASE_NAME                      = PpmPolicy\r
+  FILE_GUID                      = 2EE72E7C-FB9E-4318-B888-33A315C7A91D\r
+  MODULE_TYPE                    = DXE_DRIVER\r
+  VERSION_STRING                 = 1.0\r
+  ENTRY_POINT                    = PpmPolicyEntry\r
+\r
+[Sources]\r
+  PpmPolicy.c\r
+\r
+[Packages]\r
+  MdePkg/MdePkg.dec\r
+  Vlv2TbltDevicePkg/PlatformPkg.dec\r
+  IA32FamilyCpuPkg/IA32FamilyCpuPkg.dec #CpuConfigLib.h\r
+  Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec\r
+\r
+[LibraryClasses]\r
+  DebugLib\r
+  BaseLib\r
+  PchPlatformLib\r
+  UefiDriverEntryPoint\r
+\r
+[Protocols]\r
+  gEfiMpServiceProtocolGuid\r
+  gPpmPlatformPolicyProtocolGuid\r
+\r
+[Guids]\r
+  gEfiSetupVariableGuid\r
+\r
+[Depex]\r
+  gEfiMpServiceProtocolGuid\r

diff --git a/Vlv2TbltDevicePkg/SaveMemoryConfig/SaveMemoryConfig.c b/Vlv2TbltDevicePkg/SaveMemoryConfig/SaveMemoryConfig.c
new file mode 100644 (file)
index 0000000..dd3e5dc
--- /dev/null
+++ b/Vlv2TbltDevicePkg/SaveMemoryConfig/SaveMemoryConfig.c
@@ -0,0 +1,187 @@
+/** \r
+  Copyright (c) 2009 - 2013, Intel Corporation. All rights reserved.<BR>\r
+  This program and the accompanying materials\r
+  are licensed and made available under the terms and conditions of the BSD License\r
+  which accompanies this distribution.  The full text of the license may be found at\r
+  http://opensource.org/licenses/bsd-license.php\r
+\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+Module Name:\r
+\r
+  SaveMemoryConfig.c\r
+\r
+Abstract:\r
+  This is the driver that locates the MemoryConfigurationData HOB, if it\r
+  exists, and saves the data to nvRAM.\r
+\r
+ \r
+\r
+--*/\r
+\r
+#include "SaveMemoryConfig.h"\r
+\r
+CHAR16    EfiMemoryConfigVariable[] = L"MemoryConfig";\r
+\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+SaveMemoryConfigEntryPoint (\r
+  IN EFI_HANDLE         ImageHandle,\r
+  IN EFI_SYSTEM_TABLE   *SystemTable\r
+  )\r
+/*++\r
+\r
+  Routine Description:\r
+    This is the standard EFI driver point that detects whether there is a\r
+    MemoryConfigurationData HOB and, if so, saves its data to nvRAM.\r
+\r
+  Arguments:\r
+    ImageHandle   - Handle for the image of this driver\r
+    SystemTable   - Pointer to the EFI System Table\r
+\r
+  Returns:\r
+    EFI_SUCCESS   - if the data is successfully saved or there was no data\r
+    EFI_NOT_FOUND - if the HOB list could not be located.\r
+    EFI_UNLOAD_IMAGE - It is not success\r
+\r
+--*/\r
+{\r
+  EFI_STATUS                      Status=EFI_SUCCESS;\r
+  VOID                            *MemHobData;\r
+  VOID                            *VariableData;\r
+  UINTN                           BufferSize;\r
+  BOOLEAN                         MfgMode;\r
+  EFI_PLATFORM_SETUP_ID           *BootModeBuffer;\r
+  EFI_PLATFORM_INFO_HOB           *PlatformInfoHobPtr;\r
+  MEM_INFO_PROTOCOL               *MemInfoProtocol;\r
+  EFI_HANDLE                      Handle;\r
+  UINT8                                                                      Channel, Slot;\r
+  VOID                            *GuidHob;\r
+\r
+  VariableData   = NULL;\r
+  MfgMode        = FALSE;\r
+  Handle         = NULL;\r
+  BootModeBuffer = NULL;\r
+  MemHobData     = NULL;\r
+  PlatformInfoHobPtr = NULL;\r
+  BufferSize     = 0;\r
+\r
+  //\r
+  // Get Platform Info HOB\r
+  //\r
+  GuidHob = GetFirstGuidHob (&gEfiPlatformInfoGuid);\r
+  if (GuidHob == NULL) {\r
+    Status = EFI_NOT_FOUND;\r
+  }\r
+  ASSERT_EFI_ERROR (Status);\r
+\r
+  PlatformInfoHobPtr = GET_GUID_HOB_DATA (GuidHob);\r
+\r
+  //\r
+  // Get the BootMode guid hob\r
+  //\r
+  GuidHob = GetFirstGuidHob (&gEfiPlatformBootModeGuid);\r
+  if (GuidHob == NULL) {\r
+    Status = EFI_NOT_FOUND;\r
+  }\r
+  ASSERT_EFI_ERROR (Status);\r
+\r
+  BootModeBuffer = GET_GUID_HOB_DATA (GuidHob);\r
+\r
+\r
+  //\r
+  // Check whether in Manufacturing Mode\r
+  //\r
+  if (BootModeBuffer) {\r
+    if ( !CompareMem (   //EfiCompareMem\r
+            &BootModeBuffer->SetupName,\r
+            MANUFACTURE_SETUP_NAME,\r
+            StrSize (MANUFACTURE_SETUP_NAME)  //EfiStrSize\r
+            ) ) {\r
+      MfgMode = TRUE;\r
+    }\r
+  }\r
+\r
+  if (MfgMode) {\r
+    //\r
+    // Don't save Memory Configuration in Manufacturing Mode. Clear memory configuration.\r
+    //\r
+    Status = gRT->SetVariable (\r
+              EfiMemoryConfigVariable,\r
+              &gEfiVlv2VariableGuid,\r
+              EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS,\r
+              0,\r
+              NULL\r
+              );      \r
+  } else {\r
+\r
+    MemInfoProtocol = (MEM_INFO_PROTOCOL*)AllocateZeroPool(sizeof(MEM_INFO_PROTOCOL));\r
+    if (PlatformInfoHobPtr != NULL) {\r
+      MemInfoProtocol->MemInfoData.memSize  = 0;\r
+      for (Channel = 0; Channel < CH_NUM; Channel ++){\r
+        for (Slot = 0; Slot < DIMM_NUM; Slot ++){               \r
+          MemInfoProtocol->MemInfoData.dimmSize[Slot + (Channel * DIMM_NUM)] = PlatformInfoHobPtr->MemData.DimmSize[Slot];\r
+        }\r
+      }\r
+         MemInfoProtocol->MemInfoData.memSize       = PlatformInfoHobPtr->MemData.MemSize;        \r
+         MemInfoProtocol->MemInfoData.EccSupport    = PlatformInfoHobPtr->MemData.EccSupport;\r
+      MemInfoProtocol->MemInfoData.ddrFreq       = PlatformInfoHobPtr->MemData.DdrFreq;\r
+      MemInfoProtocol->MemInfoData.ddrType       = PlatformInfoHobPtr->MemData.DdrType;\r
+      if (MemInfoProtocol->MemInfoData.memSize == 0){\r
+        //\r
+        // We hardcode if MRC didn't fill these info in\r
+        //\r
+        MemInfoProtocol->MemInfoData.memSize     = 0x800; //per 1MB \r
+        MemInfoProtocol->MemInfoData.dimmSize[0] = 0x800;\r
+        MemInfoProtocol->MemInfoData.dimmSize[1] = 0;    \r
+        MemInfoProtocol->MemInfoData.EccSupport  = FALSE;\r
+        MemInfoProtocol->MemInfoData.ddrType     = 5; //DDRType_LPDDR3\r
+      }\r
+\r
+      Status = gBS->InstallMultipleProtocolInterfaces (\r
+             &Handle,\r
+             &gMemInfoProtocolGuid,\r
+             MemInfoProtocol,\r
+             NULL\r
+             );\r
+    }\r
+\r
+    Status = EFI_SUCCESS;\r
+    if (BOOT_WITH_MINIMAL_CONFIGURATION != GetBootModeHob()){\r
+      //\r
+      // Get the Memory Config guid hob\r
+      //\r
+      GuidHob = GetFirstGuidHob (&gEfiMemoryConfigDataGuid);\r
+      if (GuidHob == NULL) {\r
+        Status = EFI_NOT_FOUND;\r
+      }\r
+      ASSERT_EFI_ERROR (Status);\r
+      \r
+      MemHobData = GET_GUID_HOB_DATA (GuidHob);\r
+      BufferSize = GET_GUID_HOB_DATA_SIZE (GuidHob);\r
+\r
+      Status = gRT->GetVariable (\r
+                  EfiMemoryConfigVariable,\r
+                  &gEfiVlv2VariableGuid,\r
+                  NULL,\r
+                  &BufferSize,\r
+                  VariableData\r
+                  );\r
+      if (EFI_ERROR(Status) && (MemHobData != NULL)) {    \r
+        Status = gRT->SetVariable (\r
+                      EfiMemoryConfigVariable,\r
+                      &gEfiVlv2VariableGuid,\r
+                      (EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS),\r
+                      BufferSize,\r
+                      MemHobData\r
+                      );\r
+      } \r
+    }\r
+\r
+  } // if-else MfgMode\r
+\r
+  return EFI_SUCCESS;\r
+}\r

diff --git a/Vlv2TbltDevicePkg/SaveMemoryConfig/SaveMemoryConfig.h b/Vlv2TbltDevicePkg/SaveMemoryConfig/SaveMemoryConfig.h
new file mode 100644 (file)
index 0000000..80e7376
--- /dev/null
+++ b/Vlv2TbltDevicePkg/SaveMemoryConfig/SaveMemoryConfig.h
@@ -0,0 +1,72 @@
+/** \r
+  Copyright (c) 2009 - 2013, Intel Corporation. All rights reserved.<BR>\r
+  This program and the accompanying materials\r
+  are licensed and made available under the terms and conditions of the BSD License\r
+  which accompanies this distribution.  The full text of the license may be found at\r
+  http://opensource.org/licenses/bsd-license.php\r
+\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+Module Name:\r
+\r
+  SaveMemoryConfig.h\r
+\r
+Abstract:\r
+\r
+  Header file for Save Previous Memory Configuration Driver.\r
+\r
+ \r
+\r
+--*/\r
+\r
+\r
+#ifndef _SAVE_MEMORY_CONFIG_DRIVER_H\r
+#define _SAVE_MEMORY_CONFIG_DRIVER_H\r
+\r
+#include "Protocol/SetupMode.h"\r
+#include "Guid/PlatformInfo.h"\r
+#include "Library/HobLib.h"\r
+#include "Library/DebugLib.h"\r
+#include "Library/UefiBootServicesTableLib.h"\r
+#include "Library/BaseMemoryLib.h"\r
+#include "PlatformBootMode.h"\r
+#include "Library/BaseLib.h"\r
+#include "Library/UefiRuntimeServicesTableLib.h"\r
+#include "Guid/GlobalVariable.h"\r
+#include "Library/UefiLib.h"\r
+#include "Guid/HobList.h"\r
+#include "Guid/MemoryConfigData.h"\r
+#include "Protocol/MemInfo.h"\r
+#include "Library/MemoryAllocationLib.h"\r
+#include <Guid/Vlv2Variable.h>\r
+\r
+//\r
+// Prototypes\r
+//\r
+EFI_STATUS\r
+EFIAPI\r
+SaveMemoryConfigEntryPoint (\r
+  IN EFI_HANDLE         ImageHandle,\r
+  IN EFI_SYSTEM_TABLE   *SystemTable\r
+  )\r
+/*++\r
+  \r
+  Routine Description:\r
+    This is the standard EFI driver point that detects whether there is a\r
+    MemoryConfigurationData HOB and, if so, saves its data to nvRAM.\r
+\r
+  Arguments:\r
+    ImageHandle   - Handle for the image of this driver\r
+    SystemTable   - Pointer to the EFI System Table\r
+\r
+  Returns:\r
+    EFI_SUCCESS   - if the data is successfully saved or there was no data\r
+    EFI_NOT_FOUND - if the HOB list could not be located.\r
+    EFI_UNLOAD_IMAGE - It is not success\r
+    \r
+--*/\r
+;\r
+\r
+#endif\r

diff --git a/Vlv2TbltDevicePkg/SaveMemoryConfig/SaveMemoryConfig.inf b/Vlv2TbltDevicePkg/SaveMemoryConfig/SaveMemoryConfig.inf
new file mode 100644 (file)
index 0000000..bea0ca7
--- /dev/null
+++ b/Vlv2TbltDevicePkg/SaveMemoryConfig/SaveMemoryConfig.inf
@@ -0,0 +1,66 @@
+#/*++\r
+#\r
+#  Copyright (c)  1999  - 2014, Intel Corporation. All rights reserved\r
+#                                                                                  \r
+# This program and the accompanying materials are licensed and made available under\r
+# the terms and conditions of the BSD License that accompanies this distribution.  \r
+# The full text of the license may be found at                                     \r
+# http://opensource.org/licenses/bsd-license.php.                                  \r
+#                                                                                  \r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r
+#                     \r
+#\r
+#\r
+#\r
+#  Module Name:\r
+#\r
+#   SaveMemoryConfig.inf\r
+#\r
+#  Abstract:\r
+#\r
+#\r
+--*/\r
+\r
+[defines]\r
+  INF_VERSION                    = 0x00010005\r
+  BASE_NAME                      = SaveMemoryConfig\r
+  FILE_GUID                      = E0ECBEC9-B193-4351-A488-36A655F22F9F\r
+  MODULE_TYPE                    = DXE_DRIVER\r
+  VERSION_STRING                 = 1.0\r
+  ENTRY_POINT                    = SaveMemoryConfigEntryPoint\r
+\r
+[sources.common]\r
+  SaveMemoryConfig.c\r
+\r
+[Packages]\r
+  MdePkg/MdePkg.dec\r
+  Vlv2TbltDevicePkg/PlatformPkg.dec\r
+  Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec\r
+\r
+[LibraryClasses]\r
+  UefiDriverEntryPoint\r
+  UefiBootServicesTableLib\r
+  HobLib\r
+  DebugLib\r
+  UefiRuntimeServicesTableLib\r
+  UefiLib\r
+  BaseLib\r
+\r
+[Protocols]\r
+  gMemInfoProtocolGuid\r
+\r
+[Guids]\r
+  gEfiMemoryConfigDataGuid\r
+  gEfiPlatformInfoGuid\r
+  gEfiPlatformBootModeGuid\r
+  gEfiVlv2VariableGuid\r
+  #gEfiHobListGuid\r
+  #gEfiPlatformInfoGuid\r
+  #gEfiPlatformBootModeGuid\r
+  #gEfiGlobalVariableGuid\r
+  #gEfiMemoryConfigDataGuid\r
+\r
+[Depex]\r
+  gEfiVariableArchProtocolGuid AND\r
+  gEfiVariableWriteArchProtocolGuid\r

diff --git a/Vlv2TbltDevicePkg/SmBiosMiscDxe/CommonHeader.h b/Vlv2TbltDevicePkg/SmBiosMiscDxe/CommonHeader.h
new file mode 100644 (file)
index 0000000..4b7f70a
--- /dev/null
+++ b/Vlv2TbltDevicePkg/SmBiosMiscDxe/CommonHeader.h
@@ -0,0 +1,44 @@
+/**@file\r
+  Common header file shared by all source files.\r
+\r
+  This file includes package header files, library classes and protocol, PPI & GUID definitions.\r
+\r
+  Copyright (c) 2006  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+**/\r
+\r
+#ifndef __COMMON_HEADER_H_\r
+#define __COMMON_HEADER_H_\r
+\r
+\r
+\r
+#include <FrameworkDxe.h>\r
+#include <IndustryStandard/SmBios.h>\r
+#include <Protocol/Smbios.h>\r
+\r
+#include <Guid/DataHubRecords.h>\r
+#include <Guid/MdeModuleHii.h>\r
+\r
+#include <Library/DebugLib.h>\r
+#include <Library/BaseMemoryLib.h>\r
+#include <Library/UefiDriverEntryPoint.h>\r
+#include <Library/UefiBootServicesTableLib.h>\r
+#include <Library/DevicePathLib.h>\r
+#include <Library/HiiLib.h>\r
+#include <Library/BaseLib.h>\r
+#include <Library/MemoryAllocationLib.h>\r
+#include <Library/PcdLib.h>\r
+#include <Library/UefiLib.h>\r
+#include <PchRegs.h>\r
+#include <Library/PchPlatformLib.h>\r
+#include <Library/PrintLib.h>\r
+\r
+#endif\r

diff --git a/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscBaseBoardManufacturer.uni b/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscBaseBoardManufacturer.uni
new file mode 100644 (file)
index 0000000..5d23abd
Binary files /dev/null and b/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscBaseBoardManufacturer.uni differ

diff --git a/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscBaseBoardManufacturerData.c b/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscBaseBoardManufacturerData.c
new file mode 100644 (file)
index 0000000..a3bacec
--- /dev/null
+++ b/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscBaseBoardManufacturerData.c
@@ -0,0 +1,63 @@
+/** @file\r
+\r
+Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+\r
+Module Name:\r
+\r
+  MiscBaseBoardManufacturerData.c\r
+\r
+Abstract:\r
+\r
+  Static data of Base board manufacturer information.\r
+  Base board manufacturer information is Misc. subclass type 4 and SMBIOS type 2.\r
+\r
+\r
+**/\r
+\r
+\r
+#include "CommonHeader.h"\r
+\r
+#include "MiscSubclassDriver.h"\r
+\r
+//\r
+// Static (possibly build generated) Bios Vendor data.\r
+//\r
+MISC_SMBIOS_TABLE_DATA(EFI_MISC_BASE_BOARD_MANUFACTURER_DATA, MiscBaseBoardManufacturer)\r
+= {\r
+  STRING_TOKEN(STR_MISC_BASE_BOARD_MANUFACTURER),\r
+  STRING_TOKEN(STR_MISC_BASE_BOARD_PRODUCT_NAME),\r
+  STRING_TOKEN(STR_MISC_BASE_BOARD_VERSION),\r
+  STRING_TOKEN(STR_MISC_BASE_BOARD_SERIAL_NUMBER),\r
+  STRING_TOKEN(STR_MISC_BASE_BOARD_ASSET_TAG),\r
+  STRING_TOKEN(STR_MISC_BASE_BOARD_CHASSIS_LOCATION),\r
+  {                         // BaseBoardFeatureFlags\r
+    1,                      // Motherboard\r
+    0,                      // RequiresDaughterCard\r
+    0,                      // Removable\r
+    1,                      // Replaceable,\r
+    0,                      // HotSwappable\r
+    0,                      // Reserved\r
+  },\r
+  EfiBaseBoardTypeUnknown,  // BaseBoardType\r
+  {                         // BaseBoardChassisLink\r
+    EFI_MISC_SUBCLASS_GUID, // ProducerName\r
+    1,                      // Instance\r
+    1,                      // SubInstance\r
+  },\r
+  0,                        // BaseBoardNumberLinks\r
+  {                         // LinkN\r
+    EFI_MISC_SUBCLASS_GUID, // ProducerName\r
+    1,                      // Instance\r
+    1,                      // SubInstance\r
+  },\r
+};\r

diff --git a/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscBaseBoardManufacturerFunction.c b/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscBaseBoardManufacturerFunction.c
new file mode 100644 (file)
index 0000000..6570e7c
--- /dev/null
+++ b/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscBaseBoardManufacturerFunction.c
@@ -0,0 +1,232 @@
+/*++
+
+Copyright (c) 2009 - 2014, Intel Corporation. All rights reserved.<BR>
+                                                                                   
+  This program and the accompanying materials are licensed and made available under
+  the terms and conditions of the BSD License that accompanies this distribution.  
+  The full text of the license may be found at                                     
+  http://opensource.org/licenses/bsd-license.php.                                  
+                                                                                   
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    
+                                                                                   
+
+
+Module Name:
+
+  MiscBaseBoardManufacturerFunction.c
+
+Abstract:
+
+  BaseBoard manufacturer information boot time changes.
+  SMBIOS type 2.
+
+--*/
+
+
+#include "CommonHeader.h"
+#include "MiscSubclassDriver.h"
+#include <Library/NetLib.h>
+#include "Library/DebugLib.h"
+#include <Uefi/UefiBaseType.h>
+
+
+/**
+  This function makes boot time changes to the contents of the
+  MiscBaseBoardManufacturer (Type 2).
+
+  @param  RecordData                 Pointer to copy of RecordData from the Data Table.
+
+  @retval EFI_SUCCESS                All parameters were valid.
+  @retval EFI_UNSUPPORTED            Unexpected RecordType value.
+  @retval EFI_INVALID_PARAMETER      Invalid parameter was found.
+
+**/
+MISC_SMBIOS_TABLE_FUNCTION(MiscBaseBoardManufacturer)
+{
+  CHAR8                           *OptionalStrStart;
+  UINTN                           ManuStrLen;
+  UINTN                           ProductStrLen;
+  UINTN                           VerStrLen;
+  UINTN                           AssertTagStrLen;
+  UINTN                           SerialNumStrLen;
+  UINTN                           ChassisStrLen;
+  EFI_STATUS                      Status;
+  EFI_STRING                      Manufacturer;
+  EFI_STRING                      Product;
+  EFI_STRING                      Version;
+  EFI_STRING                      SerialNumber;
+  EFI_STRING                      AssertTag;
+  EFI_STRING                      Chassis;
+  STRING_REF                      TokenToGet;
+  EFI_SMBIOS_HANDLE               SmbiosHandle;
+  SMBIOS_TABLE_TYPE2              *SmbiosRecord;
+  EFI_MISC_BASE_BOARD_MANUFACTURER   *ForType2InputData;
+
+  CHAR16                          *MacStr; 
+  EFI_HANDLE                      *Handles;
+  UINTN                           BufferSize;
+
+  ForType2InputData = (EFI_MISC_BASE_BOARD_MANUFACTURER *)RecordData;
+
+  //
+  // First check for invalid parameters.
+  //
+  if (RecordData == NULL) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  TokenToGet = STRING_TOKEN (STR_MISC_BASE_BOARD_MANUFACTURER);
+  Manufacturer = SmbiosMiscGetString (TokenToGet);
+  ManuStrLen = StrLen(Manufacturer);
+  if (ManuStrLen > SMBIOS_STRING_MAX_LENGTH) {
+    return EFI_UNSUPPORTED;
+  }
+
+  TokenToGet = STRING_TOKEN (STR_MISC_BASE_BOARD_PRODUCT_NAME1);
+  Product = SmbiosMiscGetString (TokenToGet);
+  ProductStrLen = StrLen(Product);
+  if (ProductStrLen > SMBIOS_STRING_MAX_LENGTH) {
+    return EFI_UNSUPPORTED;
+  }
+  TokenToGet = STRING_TOKEN (STR_MISC_BASE_BOARD_VERSION);
+  Version = SmbiosMiscGetString (TokenToGet);
+  VerStrLen = StrLen(Version);
+  if (VerStrLen > SMBIOS_STRING_MAX_LENGTH) {
+    return EFI_UNSUPPORTED;
+  }
+              
+  //
+  //Get handle infomation
+  //
+  BufferSize = 0;
+  Handles = NULL;
+  Status = gBS->LocateHandle (
+                  ByProtocol, 
+                  &gEfiSimpleNetworkProtocolGuid,
+                  NULL,
+                  &BufferSize,
+                  Handles
+                  );
+
+  if (Status == EFI_BUFFER_TOO_SMALL) {
+       Handles = AllocateZeroPool(BufferSize);
+       if (Handles == NULL) {
+               return (EFI_OUT_OF_RESOURCES);
+       }
+       Status = gBS->LocateHandle(
+                       ByProtocol,
+                       &gEfiSimpleNetworkProtocolGuid,
+                       NULL,
+                       &BufferSize,
+                       Handles
+                       );
+ }
+                       
+  //
+  //Get the MAC string
+  //
+  Status = NetLibGetMacString (
+             *Handles,
+             NULL,
+             &MacStr
+             );
+  if (EFI_ERROR (Status)) {    
+    return Status;
+  }
+  SerialNumber = MacStr;    
+  SerialNumStrLen = StrLen(SerialNumber);
+  if (SerialNumStrLen > SMBIOS_STRING_MAX_LENGTH) {
+    return EFI_UNSUPPORTED;
+  }
+  DEBUG ((EFI_D_ERROR, "MAC Address: %S\n", MacStr)); 
+  
+  TokenToGet = STRING_TOKEN (STR_MISC_BASE_BOARD_ASSET_TAG);
+  AssertTag = SmbiosMiscGetString (TokenToGet);
+  AssertTagStrLen = StrLen(AssertTag);
+  if (AssertTagStrLen > SMBIOS_STRING_MAX_LENGTH) {
+    return EFI_UNSUPPORTED;
+  }
+
+  TokenToGet = STRING_TOKEN (STR_MISC_BASE_BOARD_CHASSIS_LOCATION);
+  Chassis = SmbiosMiscGetString (TokenToGet);
+  ChassisStrLen = StrLen(Chassis);
+  if (ChassisStrLen > SMBIOS_STRING_MAX_LENGTH) {
+    return EFI_UNSUPPORTED;
+  }
+
+
+  //
+  // Two zeros following the last string.
+  //
+  SmbiosRecord = AllocatePool(sizeof (SMBIOS_TABLE_TYPE2) + ManuStrLen + 1 + ProductStrLen + 1 + VerStrLen + 1 + SerialNumStrLen + 1 + AssertTagStrLen + 1 + ChassisStrLen +1 + 1);
+  ZeroMem(SmbiosRecord, sizeof (SMBIOS_TABLE_TYPE2) + ManuStrLen + 1 + ProductStrLen + 1 + VerStrLen + 1 + SerialNumStrLen + 1 + AssertTagStrLen + 1 + ChassisStrLen +1 + 1);
+
+  SmbiosRecord->Hdr.Type = EFI_SMBIOS_TYPE_BASEBOARD_INFORMATION;
+  SmbiosRecord->Hdr.Length = sizeof (SMBIOS_TABLE_TYPE2);
+
+  //
+  // Make handle chosen by smbios protocol.add automatically.
+  //
+  SmbiosRecord->Hdr.Handle = 0;
+
+  //
+  // Manu will be the 1st optional string following the formatted structure.
+  //
+  SmbiosRecord->Manufacturer = 1;
+
+  //
+  // ProductName will be the 2st optional string following the formatted structure.
+  //
+  SmbiosRecord->ProductName  = 2;
+
+  //
+  // Version will be the 3rd optional string following the formatted structure.
+  //
+  SmbiosRecord->Version = 3;
+
+  //
+  // SerialNumber will be the 4th optional string following the formatted structure.
+  //
+  SmbiosRecord->SerialNumber = 4;
+
+  //
+  // AssertTag will be the 5th optional string following the formatted structure.
+  //
+  SmbiosRecord->AssetTag = 5;
+
+  //
+  // LocationInChassis will be the 6th optional string following the formatted structure.
+  //
+  SmbiosRecord->LocationInChassis = 6;
+  SmbiosRecord->FeatureFlag = (*(BASE_BOARD_FEATURE_FLAGS*)&(ForType2InputData->BaseBoardFeatureFlags));
+  SmbiosRecord->ChassisHandle  = 0;
+  SmbiosRecord->BoardType      = (UINT8)ForType2InputData->BaseBoardType;
+  SmbiosRecord->NumberOfContainedObjectHandles = 0;
+
+  OptionalStrStart = (CHAR8 *)(SmbiosRecord + 1);
+
+  //
+  // Since we fill NumberOfContainedObjectHandles = 0 for simple, just after this filed to fill string
+  //
+  UnicodeStrToAsciiStr(Manufacturer, OptionalStrStart);
+  UnicodeStrToAsciiStr(Product, OptionalStrStart + ManuStrLen + 1);
+  UnicodeStrToAsciiStr(Version, OptionalStrStart + ManuStrLen + 1 + ProductStrLen + 1);
+  UnicodeStrToAsciiStr(SerialNumber, OptionalStrStart + ManuStrLen + 1 + ProductStrLen + 1 + VerStrLen + 1);
+  UnicodeStrToAsciiStr(AssertTag, OptionalStrStart + ManuStrLen + 1 + ProductStrLen + 1 + VerStrLen + 1 + SerialNumStrLen + 1);
+  UnicodeStrToAsciiStr(Chassis, OptionalStrStart + ManuStrLen + 1 + ProductStrLen + 1 + VerStrLen + 1 + SerialNumStrLen + 1 + AssertTagStrLen + 1);
+
+  //
+  // Now we have got the full smbios record, call smbios protocol to add this record.
+  //
+  SmbiosHandle = SMBIOS_HANDLE_PI_RESERVED;
+  Status = Smbios-> Add(
+                      Smbios,
+                      NULL,
+                      &SmbiosHandle,
+                      (EFI_SMBIOS_TABLE_HEADER *) SmbiosRecord
+                      );
+
+  FreePool(SmbiosRecord);
+  return Status;
+}

diff --git a/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscBiosVendor.uni b/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscBiosVendor.uni
new file mode 100644 (file)
index 0000000..e9fffae
Binary files /dev/null and b/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscBiosVendor.uni differ

diff --git a/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscBiosVendorData.c b/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscBiosVendorData.c
new file mode 100644 (file)
index 0000000..d18adad
--- /dev/null
+++ b/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscBiosVendorData.c
@@ -0,0 +1,106 @@
+/** @file\r
+\r
+Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+\r
+Module Name:\r
+\r
+  MiscBiosVendorData.c\r
+\r
+Abstract:\r
+\r
+  Static data of BIOS vendor information.\r
+  BIOS vendor information is Misc. subclass type 2 and SMBIOS type 0.\r
+\r
+\r
+**/\r
+\r
+\r
+#include "CommonHeader.h"\r
+\r
+#include "MiscSubclassDriver.h"\r
+\r
+//\r
+// Static (possibly build generated) Bios Vendor data.\r
+//\r
+MISC_SMBIOS_TABLE_DATA(EFI_MISC_BIOS_VENDOR_DATA, MiscBiosVendor)\r
+= {\r
+  STRING_TOKEN(STR_MISC_BIOS_VENDOR),       // BiosVendor\r
+  STRING_TOKEN(STR_MISC_BIOS_VERSION),      // BiosVersion\r
+  STRING_TOKEN(STR_MISC_BIOS_RELEASE_DATE), // BiosReleaseDate\r
+  0xF000, // BiosStartingAddress\r
+  {       // BiosPhysicalDeviceSize\r
+    1,    // Value\r
+    21 ,          // Exponent\r
+  },\r
+  {       // BiosCharacteristics1\r
+    0,    // Reserved1                         :2\r
+    0,    // Unknown                           :1\r
+    0,    // BiosCharacteristicsNotSupported   :1\r
+    0,    // IsaIsSupported                    :1\r
+    0,    // McaIsSupported                    :1\r
+    0,    // EisaIsSupported                   :1\r
+    1,    // PciIsSupported                    :1\r
+    0,    // PcmciaIsSupported                 :1\r
+    0,    // PlugAndPlayIsSupported            :1\r
+    0,    // ApmIsSupported                    :1\r
+    1,    // BiosIsUpgradable                  :1\r
+    1,    // BiosShadowingAllowed              :1\r
+    0,    // VlVesaIsSupported                 :1\r
+    0,    // EscdSupportIsAvailable            :1\r
+    1,    // BootFromCdIsSupported             :1\r
+    1,    // SelectableBootIsSupported         :1\r
+    0,    // RomBiosIsSocketed                 :1\r
+    0,    // BootFromPcmciaIsSupported         :1\r
+    1,    // EDDSpecificationIsSupported       :1\r
+    0,    // JapaneseNecFloppyIsSupported      :1\r
+    0,    // JapaneseToshibaFloppyIsSupported  :1\r
+    0,    // Floppy525_360IsSupported          :1\r
+    0,    // Floppy525_12IsSupported           :1\r
+    0,    // Floppy35_720IsSupported           :1\r
+    0,    // Floppy35_288IsSupported           :1\r
+    0,    // PrintScreenIsSupported            :1\r
+    1,    // Keyboard8042IsSupported           :1\r
+    1,    // SerialIsSupported                 :1\r
+    1,    // PrinterIsSupported                :1\r
+    1,    // CgaMonoIsSupported                :1\r
+    0,    // NecPc98                           :1\r
+\r
+//\r
+//BIOS Characteristics Extension Byte 1\r
+//\r
+    1,    // AcpiIsSupported                   :1\r
+    1,    // UsbLegacyIsSupported              :1\r
+    0,    // AgpIsSupported                    :1\r
+    0,    // I20BootIsSupported                :1\r
+    0,    // Ls120BootIsSupported              :1\r
+    1,    // AtapiZipDriveBootIsSupported      :1\r
+    0,    // Boot1394IsSupported               :1\r
+    0,    // SmartBatteryIsSupported           :1\r
+\r
+//\r
+//BIOS Characteristics Extension Byte 2\r
+//\r
+    1,    // BiosBootSpecIsSupported           :1\r
+    1,    // FunctionKeyNetworkBootIsSupported :1\r
+    0x1     // Reserved                          :19  Bit 2 is SMBiosIsTargContDistEnabled\r
+  },\r
+  {       // BiosCharacteristics2\r
+    0x0001,// BiosReserved                      :16  Bit 0 is BIOS Splash Screen\r
+    0,    // SystemReserved                    :16\r
+    0     // Reserved                          :32\r
+  },\r
+  0xFF,   // BiosMajorRelease;\r
+  0xFF,   // BiosMinorRelease;\r
+  0xFF,   // BiosEmbeddedFirmwareMajorRelease;\r
+  0xFF,   // BiosEmbeddedFirmwareMinorRelease;\r
+};\r

diff --git a/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscBiosVendorFunction.c b/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscBiosVendorFunction.c
new file mode 100644 (file)
index 0000000..33c14dc
--- /dev/null
+++ b/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscBiosVendorFunction.c
@@ -0,0 +1,341 @@
+/*++\r
+\r
+Copyright (c) 2009 - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+\r
+Module Name:\r
+\r
+  MiscBiosVendorFunction.c\r
+\r
+Abstract:\r
+\r
+  BIOS vendor information boot time changes.\r
+  Misc. subclass type 2.\r
+  SMBIOS type 0.\r
+\r
+--*/\r
+\r
+\r
+#include "CommonHeader.h"\r
+\r
+#include "MiscSubclassDriver.h"\r
+#include <Library/BiosIdLib.h>\r
+#include <Library/SpiFlash.H>\r
+\r
+EFI_SPI_PROTOCOL  *mSpiProtocol = NULL;\r
+\r
+\r
+/**\r
+  This function read the data from Spi Rom.\r
+\r
+  @param BaseAddress                The starting address of the read.\r
+  @param Byte                       The pointer to the destination buffer.\r
+  @param Length                     The number of bytes.\r
+  @param SpiRegionType              Spi Region Type.\r
+\r
+  @retval Status\r
+\r
+**/\r
+EFI_STATUS\r
+FlashRead (\r
+  IN  UINTN             BaseAddress,\r
+  IN  UINT8             *Byte,\r
+  IN  UINTN             Length,\r
+  IN  SPI_REGION_TYPE   SpiRegionType\r
+  )\r
+{\r
+  EFI_STATUS            Status = EFI_SUCCESS;\r
+  UINT32                SectorSize;\r
+  UINT32                SpiAddress;\r
+  UINT8                 Buffer[SECTOR_SIZE_4KB];\r
+\r
+  SpiAddress = (UINT32)(UINTN)(BaseAddress);\r
+  SectorSize = SECTOR_SIZE_4KB;\r
+\r
+  Status = mSpiProtocol->Execute (\r
+                           mSpiProtocol,\r
+                           SPI_READ,\r
+                           SPI_WREN,\r
+                           TRUE,\r
+                           TRUE,\r
+                           FALSE,\r
+                           (UINT32) SpiAddress,\r
+                           SectorSize,\r
+                           Buffer,\r
+                           SpiRegionType\r
+                           );\r
+\r
+  if (EFI_ERROR (Status)) {\r
+#ifdef _SHOW_LOG_\r
+    Print(L"Read SPI ROM Failed [%08x]\n", SpiAddress);\r
+#endif\r
+    return Status;\r
+  }\r
+\r
+  CopyMem (Byte, (void *)Buffer, Length);\r
+\r
+  return Status;\r
+}\r
+\r
+/**\r
+  This function returns the value & exponent to Base2 for a given\r
+  Hex value. This is used to calculate the BiosPhysicalDeviceSize.\r
+\r
+  @param Value                      The hex value which is to be converted into value-exponent form\r
+  @param Exponent                   The exponent out of the conversion\r
+\r
+  @retval EFI_SUCCESS               All parameters were valid and *Value & *Exponent have been set.\r
+  @retval EFI_INVALID_PARAMETER     Invalid parameter was found.\r
+\r
+**/\r
+EFI_STATUS\r
+GetValueExponentBase2(\r
+  IN OUT UINTN        *Value,\r
+  OUT    UINTN        *Exponent\r
+  )\r
+{\r
+  if ((Value == NULL) || (Exponent == NULL)) {\r
+    return EFI_INVALID_PARAMETER;\r
+  }\r
+\r
+  while ((*Value % 2) == 0) {\r
+    *Value=*Value/2;\r
+    (*Exponent)++;\r
+  }\r
+\r
+  return EFI_SUCCESS;\r
+}\r
+\r
+/**\r
+  Field Filling Function. Transform an EFI_EXP_BASE2_DATA to a byte, with '64k'\r
+  as the unit.\r
+\r
+  @param  Base2Data              Pointer to Base2_Data\r
+\r
+  @retval EFI_SUCCESS            Transform successfully.\r
+  @retval EFI_INVALID_PARAMETER  Invalid parameter was found.\r
+\r
+**/\r
+UINT16\r
+Base2ToByteWith64KUnit (\r
+  IN      EFI_EXP_BASE2_DATA  *Base2Data\r
+  )\r
+{\r
+  UINT16              Value;\r
+  UINT16              Exponent;\r
+\r
+  Value     = Base2Data->Value;\r
+  Exponent  = Base2Data->Exponent;\r
+  Exponent -= 16;\r
+  Value <<= Exponent;\r
+\r
+  return Value;\r
+}\r
+\r
+\r
+/**\r
+  This function makes boot time changes to the contents of the\r
+  MiscBiosVendor (Type 0).\r
+\r
+  @param  RecordData                 Pointer to copy of RecordData from the Data Table.\r
+\r
+  @retval EFI_SUCCESS                All parameters were valid.\r
+  @retval EFI_UNSUPPORTED            Unexpected RecordType value.\r
+  @retval EFI_INVALID_PARAMETER      Invalid parameter was found.\r
+\r
+**/\r
+MISC_SMBIOS_TABLE_FUNCTION(MiscBiosVendor)\r
+{\r
+  CHAR8                 *OptionalStrStart;\r
+  UINTN                 VendorStrLen;\r
+  UINTN                 VerStrLen;\r
+  UINTN                 DateStrLen;\r
+  CHAR16                *Version;\r
+  CHAR16                *ReleaseDate;\r
+  CHAR16                BiosVersion[100];         //Assuming that strings are < 100 UCHAR\r
+  CHAR16                BiosReleaseDate[100];     //Assuming that strings are < 100 UCHAR\r
+  CHAR16                BiosReleaseTime[100];     //Assuming that strings are < 100 UCHAR\r
+  EFI_STATUS            Status;\r
+  EFI_STRING            Char16String;\r
+  STRING_REF            TokenToGet;\r
+  STRING_REF            TokenToUpdate;\r
+  SMBIOS_TABLE_TYPE0    *SmbiosRecord;\r
+  EFI_SMBIOS_HANDLE     SmbiosHandle;\r
+  EFI_MISC_BIOS_VENDOR *ForType0InputData;\r
+  BIOS_ID_IMAGE         BiosIdImage;\r
+  UINT16                UVerStr[32];\r
+  UINTN                 LoopIndex;\r
+  UINTN                 CopyIndex;\r
+  MANIFEST_OEM_DATA     *IFWIVerStruct;\r
+  UINT8                 *Data8 = NULL;\r
+  UINT16                SpaceVer[2]={0x0020,0x0000};\r
+  UINT16                BIOSVersionTemp[100];\r
+\r
+  ForType0InputData        = (EFI_MISC_BIOS_VENDOR *)RecordData;\r
+\r
+  //\r
+  // First check for invalid parameters.\r
+  //\r
+  if (RecordData == NULL) {\r
+    return EFI_INVALID_PARAMETER;\r
+  }\r
+  GetBiosId (&BiosIdImage);\r
+\r
+  //\r
+  //  Add VLV2 BIOS Version and Release data\r
+  //\r
+  SetMem(BiosVersion, sizeof(BiosVersion), 0);\r
+  SetMem(BiosReleaseDate, sizeof(BiosReleaseDate), 0);\r
+  SetMem(BiosReleaseTime, sizeof(BiosReleaseTime), 0);\r
+  Status = GetBiosVersionDateTime (BiosVersion, BiosReleaseDate, BiosReleaseTime);\r
+  DEBUG ((EFI_D_ERROR, "GetBiosVersionDateTime :%s %s %s \n", BiosVersion, BiosReleaseDate, BiosReleaseTime));\r
+  if (StrLen (BiosVersion) > 0) {\r
+    TokenToUpdate = STRING_TOKEN (STR_MISC_BIOS_VERSION);\r
+    HiiSetString (mHiiHandle, TokenToUpdate, BiosVersion, NULL);\r
+  }\r
+\r
+  if (StrLen(BiosReleaseDate) > 0) {\r
+    TokenToUpdate = STRING_TOKEN (STR_MISC_BIOS_RELEASE_DATE);\r
+    HiiSetString (mHiiHandle, TokenToUpdate, BiosReleaseDate, NULL);\r
+  }\r
+\r
+  TokenToGet = STRING_TOKEN (STR_MISC_BIOS_VENDOR);\r
+  Char16String = SmbiosMiscGetString (TokenToGet);\r
+  VendorStrLen = StrLen(Char16String);\r
+  if (VendorStrLen > SMBIOS_STRING_MAX_LENGTH) {\r
+    return EFI_UNSUPPORTED;\r
+  }\r
+\r
+  TokenToGet = STRING_TOKEN (STR_MISC_BIOS_VERSION);\r
+  Version = SmbiosMiscGetString (TokenToGet);\r
+\r
+  ZeroMem (UVerStr, 2*32);\r
+  ZeroMem (BIOSVersionTemp, 2*100);\r
+  StrCat (BIOSVersionTemp,Version);\r
+  Data8 = AllocatePool (SECTOR_SIZE_4KB);\r
+  ZeroMem (Data8, SECTOR_SIZE_4KB);\r
+\r
+  Status = gBS->LocateProtocol (\r
+                  &gEfiSpiProtocolGuid,\r
+                  NULL,\r
+                 (VOID **)&mSpiProtocol\r
+                 );\r
+  if (!EFI_ERROR(Status)) {\r
+    //\r
+    // Get data form SPI ROM.\r
+    //\r
+    Status = FlashRead (\r
+               MEM_IFWIVER_START,\r
+               Data8,\r
+               SECTOR_SIZE_4KB,\r
+               EnumSpiRegionAll\r
+               );\r
+    if (!EFI_ERROR(Status)) {\r
+      for(LoopIndex = 0; LoopIndex <= SECTOR_SIZE_4KB; LoopIndex++) {\r
+        IFWIVerStruct = (MANIFEST_OEM_DATA *)(Data8 + LoopIndex);\r
+        if(IFWIVerStruct->Signature == SIGNATURE_32('$','F','U','D')) {\r
+          DEBUG ((EFI_D_ERROR, "the IFWI Length is:%d\n", IFWIVerStruct->IFWIVersionLen));\r
+          if(IFWIVerStruct->IFWIVersionLen < 32) {\r
+            for(CopyIndex = 0; CopyIndex < IFWIVerStruct->IFWIVersionLen; CopyIndex++) {\r
+              UVerStr[CopyIndex] = (UINT16)IFWIVerStruct->IFWIVersion[CopyIndex];\r
+            }\r
+            UVerStr[CopyIndex] = 0x0000;\r
+            DEBUG ((EFI_D_ERROR, "The IFWI Version is :%s,the IFWI Length is:%d\n", UVerStr,IFWIVerStruct->IFWIVersionLen));\r
+            StrCat(BIOSVersionTemp,SpaceVer);\r
+            StrCat(BIOSVersionTemp,UVerStr);\r
+            DEBUG ((EFI_D_ERROR, "The BIOS and IFWI Version is :%s\n", BIOSVersionTemp));\r
+          }\r
+          break;\r
+        }\r
+      }\r
+    }\r
+  }\r
+  FreePool(Data8);\r
+\r
+  VerStrLen = StrLen(BIOSVersionTemp);\r
+  if (VerStrLen > SMBIOS_STRING_MAX_LENGTH) {\r
+    return EFI_UNSUPPORTED;\r
+  }\r
+\r
+  TokenToGet = STRING_TOKEN (STR_MISC_BIOS_RELEASE_DATE);\r
+  ReleaseDate = SmbiosMiscGetString (TokenToGet);\r
+  DateStrLen = StrLen(ReleaseDate);\r
+  if (DateStrLen > SMBIOS_STRING_MAX_LENGTH) {\r
+    return EFI_UNSUPPORTED;\r
+  }\r
+\r
+  //\r
+  // Two zeros following the last string.\r
+  //\r
+  SmbiosRecord = AllocatePool(sizeof (SMBIOS_TABLE_TYPE0) + VendorStrLen + 1 + VerStrLen + 1 + DateStrLen + 1 + 1);\r
+  ZeroMem(SmbiosRecord, sizeof (SMBIOS_TABLE_TYPE0) + VendorStrLen + 1 + VerStrLen + 1 + DateStrLen + 1 + 1);\r
+\r
+  SmbiosRecord->Hdr.Type = EFI_SMBIOS_TYPE_BIOS_INFORMATION;\r
+  SmbiosRecord->Hdr.Length = sizeof (SMBIOS_TABLE_TYPE0);\r
+\r
+  //\r
+  // Make handle chosen by smbios protocol.add automatically.\r
+  //\r
+  SmbiosRecord->Hdr.Handle = 0;\r
+\r
+  //\r
+  // Vendor will be the 1st optional string following the formatted structure.\r
+  //\r
+  SmbiosRecord->Vendor = 1;\r
+\r
+  //\r
+  // Version will be the 2nd optional string following the formatted structure.\r
+  //\r
+  SmbiosRecord->BiosVersion = 2;\r
+  SmbiosRecord->BiosSegment = (UINT16)ForType0InputData->BiosStartingAddress;\r
+\r
+  //\r
+  // ReleaseDate will be the 3rd optional string following the formatted structure.\r
+  //\r
+  SmbiosRecord->BiosReleaseDate = 3;\r
+\r
+  //\r
+  // Tiger has no PCD value to indicate BIOS Size, just fill 0 for simply.\r
+  //\r
+  SmbiosRecord->BiosSize = 0;\r
+  SmbiosRecord->BiosCharacteristics = *(MISC_BIOS_CHARACTERISTICS*)(&ForType0InputData->BiosCharacteristics1);\r
+\r
+  //\r
+  // CharacterExtensionBytes also store in ForType0InputData->BiosCharacteristics1 later two bytes to save size.\r
+  //\r
+  SmbiosRecord->BIOSCharacteristicsExtensionBytes[0] = *((UINT8 *) &ForType0InputData->BiosCharacteristics1 + 4);\r
+  SmbiosRecord->BIOSCharacteristicsExtensionBytes[1] = *((UINT8 *) &ForType0InputData->BiosCharacteristics1 + 5);\r
+\r
+  SmbiosRecord->SystemBiosMajorRelease =  ForType0InputData->BiosMajorRelease;\r
+  SmbiosRecord->SystemBiosMinorRelease =  ForType0InputData->BiosMinorRelease;\r
+  SmbiosRecord->EmbeddedControllerFirmwareMajorRelease = ForType0InputData->BiosEmbeddedFirmwareMajorRelease;\r
+  SmbiosRecord->EmbeddedControllerFirmwareMinorRelease = ForType0InputData->BiosEmbeddedFirmwareMinorRelease;\r
+\r
+  OptionalStrStart = (CHAR8 *)(SmbiosRecord + 1);\r
+  UnicodeStrToAsciiStr(Char16String, OptionalStrStart);\r
+  UnicodeStrToAsciiStr(BIOSVersionTemp, OptionalStrStart + VendorStrLen + 1);\r
+  UnicodeStrToAsciiStr(ReleaseDate, OptionalStrStart + VendorStrLen + 1 + VerStrLen + 1);\r
+\r
+  //\r
+  // Now we have got the full smbios record, call smbios protocol to add this record.\r
+  //\r
+  SmbiosHandle = SMBIOS_HANDLE_PI_RESERVED;\r
+  Status = Smbios-> Add(\r
+                      Smbios,\r
+                      NULL,\r
+                      &SmbiosHandle,\r
+                      (EFI_SMBIOS_TABLE_HEADER *) SmbiosRecord\r
+                      );\r
+\r
+  FreePool(SmbiosRecord);\r
+  return Status;\r
+}\r

diff --git a/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscBootInformationData.c b/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscBootInformationData.c
new file mode 100644 (file)
index 0000000..43cad4b
--- /dev/null
+++ b/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscBootInformationData.c
@@ -0,0 +1,39 @@
+/** @file\r
+\r
+Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+\r
+Module Name:\r
+\r
+  MiscBootInformationData.c\r
+\r
+Abstract:\r
+\r
+  Static data of Boot information.\r
+  Boot information is Misc. subclass type 26 and SMBIOS type 32.\r
+\r
+\r
+**/\r
+\r
+\r
+#include "CommonHeader.h"\r
+\r
+#include "MiscSubclassDriver.h"\r
+\r
+//\r
+// Static (possibly build generated) Bios Vendor data.\r
+//\r
+MISC_SMBIOS_TABLE_DATA(EFI_MISC_BOOT_INFORMATION_STATUS_DATA, BootInformationStatus)\r
+= {\r
+  EfiBootInformationStatusNoError,  // BootInformationStatus\r
+  0                                 // BootInformationData\r
+};\r

diff --git a/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscBootInformationFunction.c b/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscBootInformationFunction.c
new file mode 100644 (file)
index 0000000..5a815c1
--- /dev/null
+++ b/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscBootInformationFunction.c
@@ -0,0 +1,87 @@
+/*++\r
+\r
+Copyright (c) 2009 - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+\r
+Module Name:\r
+\r
+  MiscBootInformationFunction.c\r
+\r
+Abstract:\r
+\r
+  boot information boot time changes.\r
+  SMBIOS type 32.\r
+\r
+--*/\r
+\r
+\r
+#include "CommonHeader.h"\r
+\r
+#include "MiscSubclassDriver.h"\r
+\r
+\r
+/**\r
+  This function makes boot time changes to the contents of the\r
+  MiscBootInformation (Type 32).\r
+\r
+  @param  RecordData                 Pointer to copy of RecordData from the Data Table.\r
+\r
+  @retval EFI_SUCCESS                All parameters were valid.\r
+  @retval EFI_UNSUPPORTED            Unexpected RecordType value.\r
+  @retval EFI_INVALID_PARAMETER      Invalid parameter was found.\r
+\r
+**/\r
+\r
+MISC_SMBIOS_TABLE_FUNCTION(BootInformationStatus)\r
+{\r
+  EFI_STATUS                         Status;\r
+  EFI_SMBIOS_HANDLE                  SmbiosHandle;\r
+  SMBIOS_TABLE_TYPE32                *SmbiosRecord;\r
+  EFI_MISC_BOOT_INFORMATION_STATUS*  ForType32InputData;\r
+\r
+  ForType32InputData = (EFI_MISC_BOOT_INFORMATION_STATUS *)RecordData;\r
+\r
+  //\r
+  // First check for invalid parameters.\r
+  //\r
+  if (RecordData == NULL) {\r
+    return EFI_INVALID_PARAMETER;\r
+  }\r
+\r
+  //\r
+  // Two zeros following the last string.\r
+  //\r
+  SmbiosRecord = AllocatePool(sizeof (SMBIOS_TABLE_TYPE32) + 1 + 1);\r
+  ZeroMem(SmbiosRecord, sizeof (SMBIOS_TABLE_TYPE32) + 1 + 1);\r
+\r
+  SmbiosRecord->Hdr.Type = EFI_SMBIOS_TYPE_SYSTEM_BOOT_INFORMATION;\r
+  SmbiosRecord->Hdr.Length = sizeof (SMBIOS_TABLE_TYPE32);\r
+\r
+  //\r
+  // Make handle chosen by smbios protocol.add automatically.\r
+  //\r
+  SmbiosRecord->Hdr.Handle = 0;\r
+  SmbiosRecord->BootStatus = (UINT8)ForType32InputData->BootInformationStatus;\r
+\r
+  //\r
+  // Now we have got the full smbios record, call smbios protocol to add this record.\r
+  //\r
+  SmbiosHandle = SMBIOS_HANDLE_PI_RESERVED;\r
+  Status = Smbios-> Add(\r
+                      Smbios,\r
+                      NULL,\r
+                      &SmbiosHandle,\r
+                      (EFI_SMBIOS_TABLE_HEADER *) SmbiosRecord\r
+                      );\r
+  FreePool(SmbiosRecord);\r
+  return Status;\r
+}\r

diff --git a/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscChassisManufacturer.uni b/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscChassisManufacturer.uni
new file mode 100644 (file)
index 0000000..f56d85a
Binary files /dev/null and b/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscChassisManufacturer.uni differ

diff --git a/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscChassisManufacturerData.c b/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscChassisManufacturerData.c
new file mode 100644 (file)
index 0000000..dc750cd
--- /dev/null
+++ b/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscChassisManufacturerData.c
@@ -0,0 +1,62 @@
+/** @file\r
+\r
+Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+\r
+Module Name:\r
+\r
+  MiscChassisManufacturerData.c\r
+\r
+Abstract:\r
+\r
+  Static data is Chassis Manufacturer information.\r
+  Chassis Manufacturer information is Misc. subclass type 5 and SMBIOS type 3.\r
+\r
+\r
+**/\r
+\r
+\r
+#include "CommonHeader.h"\r
+\r
+#include "MiscSubclassDriver.h"\r
+\r
+//\r
+// Static (possibly build generated) Chassis Manufacturer data.\r
+//\r
+MISC_SMBIOS_TABLE_DATA(EFI_MISC_CHASSIS_MANUFACTURER_DATA, MiscChassisManufacturer)\r
+= {\r
+  STRING_TOKEN(STR_MISC_CHASSIS_MANUFACTURER),  // ChassisManufactrurer\r
+  STRING_TOKEN(STR_MISC_CHASSIS_VERSION),       // ChassisVersion\r
+  STRING_TOKEN(STR_MISC_CHASSIS_SERIAL_NUMBER), // ChassisSerialNumber\r
+  STRING_TOKEN(STR_MISC_CHASSIS_ASSET_TAG),     // ChassisAssetTag\r
+  {                               // ChassisTypeStatus\r
+    EfiMiscChassisTypeUnknown,    // ChassisType\r
+    0,                            // ChassisLockPresent\r
+    0                             // Reserved\r
+  },\r
+  EfiChassisStateSafe,            // ChassisBootupState\r
+  EfiChassisStateSafe,            // ChassisPowerSupplyState\r
+  EfiChassisStateOther,           // ChassisThermalState\r
+  EfiChassisSecurityStatusOther,  // ChassisSecurityState\r
+  0,                              // ChassisOemDefined\r
+  0,                              // ChassisHeight\r
+  0,                              // ChassisNumberPowerCords\r
+  0,                              // ChassisElementCount\r
+  0,                              // ChassisElementRecordLength\r
+  {                               // ChassisElements\r
+    {0, 0, 0},                    // ChassisElementType\r
+    0,                            // ChassisElementStructure\r
+    EfiBaseBoardTypeUnknown,      // ChassisBaseBoard\r
+    0,                            // ChassisElementMinimum\r
+    0                             // ChassisElementMaximum\r
+  },\r
+};\r

diff --git a/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscChassisManufacturerFunction.c b/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscChassisManufacturerFunction.c
new file mode 100644 (file)
index 0000000..f503a2a
--- /dev/null
+++ b/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscChassisManufacturerFunction.c
@@ -0,0 +1,155 @@
+/*++\r
+\r
+Copyright (c) 2009 - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+\r
+Module Name:\r
+\r
+  MiscChassisManufacturerFunction.c\r
+\r
+Abstract:\r
+\r
+  Chassis manufacturer information boot time changes.\r
+  SMBIOS type 3.\r
+\r
+--*/\r
+\r
+\r
+#include "CommonHeader.h"\r
+\r
+#include "MiscSubclassDriver.h"\r
+\r
+/**\r
+  This function makes boot time changes to the contents of the\r
+  MiscChassisManufacturer (Type 3).\r
+\r
+  @param  RecordData                 Pointer to copy of RecordData from the Data Table.\r
+\r
+  @retval EFI_SUCCESS                All parameters were valid.\r
+  @retval EFI_UNSUPPORTED            Unexpected RecordType value.\r
+  @retval EFI_INVALID_PARAMETER      Invalid parameter was found.\r
+\r
+**/\r
+MISC_SMBIOS_TABLE_FUNCTION(MiscChassisManufacturer)\r
+{\r
+  CHAR8                           *OptionalStrStart;\r
+  UINTN                           ManuStrLen;\r
+  UINTN                           VerStrLen;\r
+  UINTN                           AssertTagStrLen;\r
+  UINTN                           SerialNumStrLen;\r
+  EFI_STATUS                      Status;\r
+  EFI_STRING                      Manufacturer;\r
+  EFI_STRING                      Version;\r
+  EFI_STRING                      SerialNumber;\r
+  EFI_STRING                      AssertTag;\r
+  STRING_REF                      TokenToGet;\r
+  EFI_SMBIOS_HANDLE               SmbiosHandle;\r
+  SMBIOS_TABLE_TYPE3              *SmbiosRecord;\r
+  EFI_MISC_CHASSIS_MANUFACTURER   *ForType3InputData;\r
+\r
+  ForType3InputData = (EFI_MISC_CHASSIS_MANUFACTURER *)RecordData;\r
+\r
+  //\r
+  // First check for invalid parameters.\r
+  //\r
+  if (RecordData == NULL) {\r
+    return EFI_INVALID_PARAMETER;\r
+  }\r
+\r
+  TokenToGet = STRING_TOKEN (STR_MISC_CHASSIS_MANUFACTURER);\r
+  Manufacturer = SmbiosMiscGetString (TokenToGet);\r
+  ManuStrLen = StrLen(Manufacturer);\r
+  if (ManuStrLen > SMBIOS_STRING_MAX_LENGTH) {\r
+    return EFI_UNSUPPORTED;\r
+  }\r
+\r
+  TokenToGet = STRING_TOKEN (STR_MISC_CHASSIS_VERSION);\r
+  Version = SmbiosMiscGetString (TokenToGet);\r
+  VerStrLen = StrLen(Version);\r
+  if (VerStrLen > SMBIOS_STRING_MAX_LENGTH) {\r
+    return EFI_UNSUPPORTED;\r
+  }\r
+\r
+  TokenToGet = STRING_TOKEN (STR_MISC_CHASSIS_SERIAL_NUMBER);\r
+  SerialNumber = SmbiosMiscGetString (TokenToGet);\r
+  SerialNumStrLen = StrLen(SerialNumber);\r
+  if (SerialNumStrLen > SMBIOS_STRING_MAX_LENGTH) {\r
+    return EFI_UNSUPPORTED;\r
+  }\r
+\r
+  TokenToGet = STRING_TOKEN (STR_MISC_CHASSIS_ASSET_TAG);\r
+  AssertTag = SmbiosMiscGetString (TokenToGet);\r
+  AssertTagStrLen = StrLen(AssertTag);\r
+  if (AssertTagStrLen > SMBIOS_STRING_MAX_LENGTH) {\r
+    return EFI_UNSUPPORTED;\r
+  }\r
+\r
+  //\r
+  // Two zeros following the last string.\r
+  //\r
+  SmbiosRecord = AllocatePool(sizeof (SMBIOS_TABLE_TYPE3) + ManuStrLen + 1  + VerStrLen + 1 + SerialNumStrLen + 1 + AssertTagStrLen + 1 + 1);\r
+  ZeroMem(SmbiosRecord, sizeof (SMBIOS_TABLE_TYPE3) + ManuStrLen + 1  + VerStrLen + 1 + SerialNumStrLen + 1 + AssertTagStrLen + 1 + 1);\r
+\r
+  SmbiosRecord->Hdr.Type = EFI_SMBIOS_TYPE_SYSTEM_ENCLOSURE;\r
+  SmbiosRecord->Hdr.Length = sizeof (SMBIOS_TABLE_TYPE3);\r
+\r
+  //\r
+  // Make handle chosen by smbios protocol.add automatically.\r
+  //\r
+  SmbiosRecord->Hdr.Handle = 0;\r
+\r
+  //\r
+  // Manu will be the 1st optional string following the formatted structure.\r
+  //\r
+  SmbiosRecord->Manufacturer = 1;\r
+  SmbiosRecord->Type = (UINT8)ForType3InputData->ChassisType.ChassisType;\r
+\r
+  //\r
+  // Version will be the 2nd optional string following the formatted structure.\r
+  //\r
+  SmbiosRecord->Version = 2;\r
+\r
+  //\r
+  // SerialNumber will be the 3rd optional string following the formatted structure.\r
+  //\r
+  SmbiosRecord->SerialNumber = 3;\r
+\r
+  //\r
+  // AssertTag will be the 4th optional string following the formatted structure.\r
+  //\r
+  SmbiosRecord->AssetTag = 4;\r
+  SmbiosRecord->BootupState = (UINT8)ForType3InputData->ChassisBootupState;\r
+  SmbiosRecord->PowerSupplyState = (UINT8)ForType3InputData->ChassisPowerSupplyState;\r
+  SmbiosRecord->ThermalState = (UINT8)ForType3InputData->ChassisThermalState;\r
+  SmbiosRecord->SecurityStatus = (UINT8)ForType3InputData->ChassisSecurityState;\r
+  CopyMem (SmbiosRecord->OemDefined,(UINT8*)&ForType3InputData->ChassisOemDefined, 4);\r
+\r
+  OptionalStrStart = (CHAR8 *)(SmbiosRecord + 1);\r
+  UnicodeStrToAsciiStr(Manufacturer, OptionalStrStart);\r
+  UnicodeStrToAsciiStr(Version, OptionalStrStart + ManuStrLen + 1);\r
+  UnicodeStrToAsciiStr(SerialNumber, OptionalStrStart + ManuStrLen + 1 + VerStrLen + 1);\r
+  UnicodeStrToAsciiStr(AssertTag, OptionalStrStart + ManuStrLen + 1 + VerStrLen + 1 + SerialNumStrLen + 1);\r
+\r
+  //\r
+  // Now we have got the full smbios record, call smbios protocol to add this record.\r
+  //\r
+  SmbiosHandle = SMBIOS_HANDLE_PI_RESERVED;\r
+  Status = Smbios-> Add(\r
+                      Smbios,\r
+                      NULL,\r
+                      &SmbiosHandle,\r
+                      (EFI_SMBIOS_TABLE_HEADER *) SmbiosRecord\r
+                      );\r
+\r
+  FreePool(SmbiosRecord);\r
+  return Status;\r
+}\r

diff --git a/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscMemoryDevice.uni b/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscMemoryDevice.uni
new file mode 100644 (file)
index 0000000..15b05b1
Binary files /dev/null and b/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscMemoryDevice.uni differ

diff --git a/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscMemoryDeviceData.c b/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscMemoryDeviceData.c
new file mode 100644 (file)
index 0000000..9c22ba8
--- /dev/null
+++ b/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscMemoryDeviceData.c
@@ -0,0 +1,50 @@
+/*++\r
+\r
+Copyright (c) 2006  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+\r
+Module Name:\r
+\r
+  MiscMemoryDeviceData.c\r
+\r
+Abstract:\r
+\r
+   Memory Device\r
+   Misc. subclass type 17.\r
+   SMBIOS type 17.\r
+\r
+--*/\r
+\r
+\r
+#include "CommonHeader.h"\r
+#include "MiscSubclassDriver.h"\r
+\r
+MISC_SMBIOS_TABLE_DATA(EFI_MEMORY_ARRAY_LINK_DATA, MiscMemoryDevice) = {\r
+       STRING_TOKEN (STR_MISC_MEM_DEV_LOCATOR0),        // Memory Device locator\r
+       STRING_TOKEN (STR_MISC_MEM_BANK_LOCATOR0),       // Memory Bank Locator\r
+       STRING_TOKEN (STR_MISC_MEM_MANUFACTURER),        // Memory manufacturer\r
+       STRING_TOKEN (STR_MISC_MEM_SERIAL_NO),           // Memory serial Number\r
+       STRING_TOKEN (STR_MISC_MEM_ASSET_TAG),           // Memory Asset Tag\r
+       STRING_TOKEN (STR_MISC_MEM_PART_NUMBER),         // Memory Part Number\r
+       0,                                                                                          // Memory Array Link\r
+       0,                                                      // Memory SubArray link\r
+       0,                                                      // UINT16 MemoryTotalWidth\r
+       0,                                                      // UINT16 MemoryDatawidth\r
+       0,                                                                                    // Memory Device Size\r
+       EfiMemoryFormFactorDip,           // Memory Form Factor\r
+    2,                        // UINT8 Memory Device type\r
+       EfiMemoryTypeDram,                          // Memory Type\r
+    0,                        // Memory Type Detail\r
+    0,                                                                             // Memory Speed\r
+       0                                                       // Memory State\r
+\r
+};\r

diff --git a/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscMemoryDeviceFunction.c b/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscMemoryDeviceFunction.c
new file mode 100644 (file)
index 0000000..0f3f4d6
--- /dev/null
+++ b/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscMemoryDeviceFunction.c
@@ -0,0 +1,324 @@
+/*++\r
+\r
+Copyright (c) 2006  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+\r
+Module Name:\r
+\r
+  MiscMemoryDeviceFunction.c\r
+\r
+Abstract:\r
+\r
+   Memory Device\r
+   Misc. subclass type 17.\r
+   SMBIOS type 17.\r
+\r
+--*/\r
+\r
+\r
+#include "CommonHeader.h"\r
+#include "MiscSubclassDriver.h"\r
+#include <Protocol/DataHub.h>\r
+#include <Guid/DataHubRecords.h>\r
+#include <Protocol/MemInfo.h>\r
+\r
+\r
+#define FREQ_800           0x00\r
+#define FREQ_1066          0x01\r
+#define FREQ_1333          0x02\r
+#define FREQ_1600          0x03\r
+\r
+#define MAX_SOCKETS  2\r
+#define EfiMemoryTypeDdr3  0x18\r
+\r
+enum {\r
+    DDRType_DDR3 = 0,\r
+    DDRType_DDR3L = 1,\r
+    DDRType_DDR3U = 2,\r
+    DDRType_DDR3All = 3,\r
+    DDRType_LPDDR2 = 4,\r
+    DDRType_LPDDR3 = 5,\r
+    DDRType_DDR4 = 6\r
+};\r
+\r
+\r
+typedef struct {\r
+  EFI_PHYSICAL_ADDRESS        MemoryArrayStartAddress;\r
+  EFI_PHYSICAL_ADDRESS        MemoryArrayEndAddress;\r
+  EFI_INTER_LINK_DATA         PhysicalMemoryArrayLink;\r
+  UINT16                      MemoryArrayPartitionWidth;\r
+} EFI_MEMORY_ARRAY_START_ADDRESS;\r
+\r
+/**\r
+  This function makes boot time changes to the contents of the\r
+  MiscBiosVendor (Type 0).\r
+\r
+  @param  RecordData                 Pointer to copy of RecordData from the Data Table.\r
+\r
+  @retval EFI_SUCCESS                All parameters were valid.\r
+  @retval EFI_UNSUPPORTED            Unexpected RecordType value.\r
+  @retval EFI_INVALID_PARAMETER      Invalid parameter was found.\r
+\r
+**/\r
+VOID\r
+GetType16Hndl (\r
+  IN  EFI_SMBIOS_PROTOCOL      *Smbios,\r
+  OUT  EFI_SMBIOS_HANDLE       *Handle\r
+  )\r
+{\r
+  EFI_STATUS                 Status;\r
+  EFI_SMBIOS_TYPE            RecordType;\r
+  EFI_SMBIOS_TABLE_HEADER    *Buffer;\r
+\r
+  *Handle = 0;\r
+   RecordType = EFI_SMBIOS_TYPE_PHYSICAL_MEMORY_ARRAY;\r
+\r
+    Status = Smbios->GetNext (\r
+                       Smbios,\r
+                       Handle,\r
+                       &RecordType,\r
+                       &Buffer,\r
+                       NULL\r
+                       );\r
+    if (!EFI_ERROR(Status)) {\r
+        return;\r
+      }\r
+  *Handle = 0xFFFF;\r
+}\r
+\r
+MISC_SMBIOS_TABLE_FUNCTION( MiscMemoryDevice )\r
+{\r
+    CHAR8                           *OptionalStrStart;\r
+    UINTN                           MemDeviceStrLen;\r
+    UINTN                           MemBankLocatorStrLen;\r
+    UINTN                           MemManufacturerStrLen;\r
+    UINTN                           MemSerialNumberStrLen;\r
+    UINTN                           MemAssetTagStrLen;\r
+    UINTN                           MemPartNumberStrLen;\r
+    CHAR16                          *MemDevice;\r
+    CHAR16                          *MemBankLocator;\r
+    CHAR16                          *MemManufacturer;\r
+    CHAR16                          *MemSerialNumber;\r
+    CHAR16                          *MemAssetTag;\r
+    CHAR16                          *MemPartNumber;\r
+    EFI_STATUS                      Status;\r
+    STRING_REF                      TokenToGet;\r
+    SMBIOS_TABLE_TYPE17             *SmbiosRecord;\r
+    EFI_SMBIOS_HANDLE               SmbiosHandle;\r
+    EFI_MEMORY_ARRAY_LINK_DATA      *ForType17InputData;\r
+    UINT16                          DdrFreq=0;\r
+    UINT16                          Type16Handle=0;\r
+    MEM_INFO_PROTOCOL               *MemInfoHob;\r
+    UINT8                           MemoryType;\r
+\r
+    UINT8                           Dimm;\r
+    UINT8                           NumSlots;\r
+    STRING_REF                      DevLocator[] = {\r
+      STRING_TOKEN(STR_MISC_MEM_DEV_LOCATOR0), STRING_TOKEN(STR_MISC_MEM_DEV_LOCATOR1)\r
+    };\r
+    STRING_REF                      BankLocator[] = {\r
+      STRING_TOKEN(STR_MISC_MEM_BANK_LOCATOR0), STRING_TOKEN(STR_MISC_MEM_BANK_LOCATOR1)\r
+    };\r
+\r
+    //\r
+    // First check for invalid parameters.\r
+    //\r
+    if (RecordData == NULL) {\r
+        return EFI_INVALID_PARAMETER;\r
+    }\r
+    ForType17InputData        = (EFI_MEMORY_ARRAY_LINK_DATA *)RecordData;\r
+\r
+    //\r
+    // Get Memory size parameters for each rank from the chipset registers\r
+    //\r
+    Status = gBS->LocateProtocol (\r
+                    &gMemInfoProtocolGuid,\r
+                    NULL,\r
+                    (void **)&MemInfoHob\r
+                    );\r
+    ASSERT_EFI_ERROR (Status);\r
+\r
+    NumSlots = (UINT8)(MAX_SOCKETS);\r
+\r
+    //\r
+    // Memory Freq\r
+    //\r
+    switch (MemInfoHob->MemInfoData.ddrFreq){\r
+        case FREQ_800:\r
+          DdrFreq = 800;\r
+          break;\r
+        case FREQ_1066:\r
+          DdrFreq = 1066;\r
+          break;\r
+        case FREQ_1333:\r
+          DdrFreq = 1333;\r
+          break;\r
+        case FREQ_1600:\r
+          DdrFreq = 1600;\r
+          break;\r
+        default:\r
+          DdrFreq = 0;\r
+          break;\r
+    }\r
+\r
+    //\r
+    // Memory Type\r
+    //\r
+    switch  (MemInfoHob->MemInfoData.ddrType) {\r
+        case DDRType_LPDDR2:\r
+          MemoryType  = EfiMemoryTypeDdr2;\r
+          break;\r
+        case DDRType_DDR3:\r
+        case DDRType_DDR3L:\r
+        case DDRType_DDR3U:\r
+        case DDRType_LPDDR3:\r
+          MemoryType = EfiMemoryTypeDdr3;\r
+          break;\r
+        default:\r
+          MemoryType = EfiMemoryTypeUnknown;\r
+          break;\r
+    }\r
+\r
+    for (Dimm = 0; Dimm < NumSlots; Dimm++) {\r
+    //\r
+    // Memory Device Locator\r
+    //\r
+    TokenToGet = DevLocator[Dimm];\r
+    MemDevice = SmbiosMiscGetString (TokenToGet);\r
+    MemDeviceStrLen = StrLen(MemDevice);\r
+    if (MemDeviceStrLen > SMBIOS_STRING_MAX_LENGTH) {\r
+      return EFI_UNSUPPORTED;\r
+    }\r
+\r
+    TokenToGet = DevLocator[Dimm];\r
+    MemDevice = SmbiosMiscGetString (TokenToGet);\r
+    MemDeviceStrLen = StrLen(MemDevice);\r
+    if (MemDeviceStrLen > SMBIOS_STRING_MAX_LENGTH) {\r
+      return EFI_UNSUPPORTED;\r
+    }\r
+\r
+    //\r
+    // Memory Bank Locator\r
+    //\r
+    TokenToGet = BankLocator[Dimm];\r
+    MemBankLocator = SmbiosMiscGetString (TokenToGet);\r
+    MemBankLocatorStrLen = StrLen(MemBankLocator);\r
+    if (MemBankLocatorStrLen > SMBIOS_STRING_MAX_LENGTH) {\r
+      return EFI_UNSUPPORTED;\r
+    }\r
+\r
+    //\r
+    // Memory Manufacturer\r
+    //\r
+    TokenToGet = STRING_TOKEN (STR_MISC_MEM_MANUFACTURER);\r
+    MemManufacturer = SmbiosMiscGetString (TokenToGet);\r
+    MemManufacturerStrLen = StrLen(MemManufacturer);\r
+    if (MemManufacturerStrLen > SMBIOS_STRING_MAX_LENGTH) {\r
+      return EFI_UNSUPPORTED;\r
+    }\r
+\r
+    //\r
+    // Memory Serial Number\r
+    //\r
+    TokenToGet = STRING_TOKEN (STR_MISC_MEM_SERIAL_NO);\r
+    MemSerialNumber = SmbiosMiscGetString (TokenToGet);\r
+    MemSerialNumberStrLen = StrLen(MemSerialNumber);\r
+    if (MemSerialNumberStrLen > SMBIOS_STRING_MAX_LENGTH) {\r
+      return EFI_UNSUPPORTED;\r
+    }\r
+\r
+    //\r
+    // Memory Asset Tag Number\r
+    //\r
+    TokenToGet = STRING_TOKEN (STR_MISC_MEM_ASSET_TAG);\r
+    MemAssetTag = SmbiosMiscGetString (TokenToGet);\r
+    MemAssetTagStrLen = StrLen(MemAssetTag);\r
+    if (MemAssetTagStrLen > SMBIOS_STRING_MAX_LENGTH) {\r
+      return EFI_UNSUPPORTED;\r
+    }\r
+\r
+    //\r
+    // Memory Part Number\r
+    //\r
+    TokenToGet = STRING_TOKEN (STR_MISC_MEM_PART_NUMBER);\r
+    MemPartNumber = SmbiosMiscGetString (TokenToGet);\r
+    MemPartNumberStrLen = StrLen(MemPartNumber);\r
+    if (MemPartNumberStrLen > SMBIOS_STRING_MAX_LENGTH) {\r
+      return EFI_UNSUPPORTED;\r
+    }\r
+\r
+    //\r
+    // Two zeros following the last string.\r
+    //\r
+    SmbiosRecord = AllocatePool(sizeof (SMBIOS_TABLE_TYPE17) + MemDeviceStrLen + 1 + MemBankLocatorStrLen + 1 + MemManufacturerStrLen + 1 + MemSerialNumberStrLen + 1 + MemAssetTagStrLen+1 + MemPartNumberStrLen + 1 + 1);\r
+    ZeroMem(SmbiosRecord, sizeof (SMBIOS_TABLE_TYPE17) +  MemDeviceStrLen + 1 + MemBankLocatorStrLen + 1 + MemManufacturerStrLen + 1 + MemSerialNumberStrLen + 1 + MemAssetTagStrLen+1 + MemPartNumberStrLen + 1 + 1);\r
+\r
+    SmbiosRecord->Hdr.Type = EFI_SMBIOS_TYPE_MEMORY_DEVICE;\r
+    SmbiosRecord->Hdr.Length = sizeof (SMBIOS_TABLE_TYPE17);\r
+\r
+    //\r
+    // Make handle chosen by smbios protocol.add automatically.\r
+    //\r
+    SmbiosRecord->Hdr.Handle = 0;\r
+\r
+    //\r
+    // Memory Array Handle will be the 3rd optional string following the formatted structure.\r
+    //\r
+    GetType16Hndl( Smbios, &Type16Handle);\r
+    SmbiosRecord->MemoryArrayHandle = Type16Handle;\r
+\r
+    //\r
+    // Memory Size\r
+    //\r
+    if ((MemInfoHob->MemInfoData.dimmSize[Dimm])!=0){\r
+    SmbiosRecord->TotalWidth = 32;\r
+    SmbiosRecord->DataWidth = 32;\r
+    SmbiosRecord->Size = MemInfoHob->MemInfoData.dimmSize[Dimm];\r
+    SmbiosRecord->Speed = DdrFreq;\r
+    SmbiosRecord->ConfiguredMemoryClockSpeed = DdrFreq;\r
+    SmbiosRecord->FormFactor = EfiMemoryFormFactorDimm;\r
+    }\r
+\r
+    SmbiosRecord->DeviceSet =(UINT8) ForType17InputData->MemoryDeviceSet;\r
+    SmbiosRecord->DeviceLocator= 1;\r
+    SmbiosRecord->BankLocator = 2;\r
+\r
+\r
+    SmbiosRecord->Manufacturer = 3;\r
+    SmbiosRecord->SerialNumber= 4;\r
+    SmbiosRecord->AssetTag= 5;\r
+    SmbiosRecord->PartNumber= 6;\r
+    SmbiosRecord->Attributes = (UINT8) ForType17InputData->MemoryState;\r
+    SmbiosRecord->MemoryType = MemoryType;\r
+\r
+    OptionalStrStart = (CHAR8 *)(SmbiosRecord + 1);\r
+    UnicodeStrToAsciiStr(MemDevice, OptionalStrStart);\r
+    UnicodeStrToAsciiStr(MemBankLocator, OptionalStrStart + MemDeviceStrLen + 1);\r
+    UnicodeStrToAsciiStr(MemManufacturer, OptionalStrStart + MemDeviceStrLen + 1 + MemBankLocatorStrLen + 1);\r
+    UnicodeStrToAsciiStr(MemSerialNumber, OptionalStrStart + MemDeviceStrLen + 1 + MemBankLocatorStrLen + 1 + MemManufacturerStrLen + 1);\r
+    UnicodeStrToAsciiStr(MemAssetTag, OptionalStrStart + MemDeviceStrLen + 1 + MemBankLocatorStrLen + 1 + MemManufacturerStrLen + 1 + MemSerialNumberStrLen + 1);\r
+    UnicodeStrToAsciiStr(MemPartNumber, OptionalStrStart + MemDeviceStrLen + 1 + MemBankLocatorStrLen + 1 + MemManufacturerStrLen + 1 + MemSerialNumberStrLen + 1+ MemAssetTagStrLen+1 );\r
+\r
+    //\r
+    // Now we have got the full smbios record, call smbios protocol to add this record.\r
+    //\r
+    SmbiosHandle = SMBIOS_HANDLE_PI_RESERVED;\r
+    Status = Smbios-> Add(\r
+                        Smbios,\r
+                        NULL,\r
+                        &SmbiosHandle,\r
+                        (EFI_SMBIOS_TABLE_HEADER *) SmbiosRecord\r
+                        );\r
+    FreePool(SmbiosRecord);\r
+    }\r
+    return Status;\r
+}\r

diff --git a/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscNumberOfInstallableLanguagesData.c b/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscNumberOfInstallableLanguagesData.c
new file mode 100644 (file)
index 0000000..311f747
--- /dev/null
+++ b/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscNumberOfInstallableLanguagesData.c
@@ -0,0 +1,43 @@
+/** @file\r
+\r
+Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+\r
+Module Name:\r
+\r
+  MiscNumberOfInstallableLanguagesData.c\r
+\r
+Abstract:\r
+\r
+  Static data of the Number of installable languages information.\r
+  Number of installable languages information is Misc. subclass type 11 and SMBIOS type 13.\r
+\r
+\r
+**/\r
+\r
+\r
+#include "CommonHeader.h"\r
+\r
+#include "MiscSubclassDriver.h"\r
+\r
+//\r
+// Static (possibly build generated) Bios Vendor data.\r
+//\r
+MISC_SMBIOS_TABLE_DATA(EFI_MISC_NUMBER_OF_INSTALLABLE_LANGUAGES_DATA, NumberOfInstallableLanguages)\r
+= {\r
+  1,    // NumberOfInstallableLanguages\r
+  {     // LanguageFlags\r
+    1,  // AbbreviatedLanguageFormat\r
+    0   // Reserved\r
+  },\r
+  STRING_TOKEN(STR_MISC_SYSTEM_LANGUAGE_EN_US)  // CurrentLanguageNumber\r
+};\r

diff --git a/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscNumberOfInstallableLanguagesFunction.c b/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscNumberOfInstallableLanguagesFunction.c
new file mode 100644 (file)
index 0000000..7cf3453
--- /dev/null
+++ b/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscNumberOfInstallableLanguagesFunction.c
@@ -0,0 +1,254 @@
+/*++\r
+\r
+Copyright (c) 2009 - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+\r
+Module Name:\r
+\r
+  MiscNumberOfInstallableLanguagesFunction.c\r
+\r
+Abstract:\r
+\r
+  This driver parses the mSmbiosMiscDataTable structure and reports\r
+  any generated data.\r
+\r
+--*/\r
+\r
+\r
+#include "CommonHeader.h"\r
+\r
+#include "MiscSubclassDriver.h"\r
+\r
+/**\r
+  Check whether the language is supported for given HII handle\r
+\r
+  @param   HiiHandle     The HII package list handle.\r
+  @param   Offset        The offest of current lanague in the supported languages.\r
+  @param   CurrentLang   The language code.\r
+\r
+  @retval  TRUE          Supported.\r
+  @retval  FALSE         Not Supported.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+CurrentLanguageMatch (\r
+  IN  EFI_HII_HANDLE                   HiiHandle,\r
+  OUT UINT16                           *Offset,\r
+  OUT CHAR8                            *CurrentLang\r
+  )\r
+{\r
+  CHAR8     *DefaultLang;\r
+  CHAR8     *BestLanguage;\r
+  CHAR8     *Languages;\r
+  CHAR8     *MatchLang;\r
+  CHAR8     *EndMatchLang;\r
+  UINTN     CompareLength;\r
+\r
+  Languages = HiiGetSupportedLanguages (HiiHandle);\r
+  if (Languages == NULL) {\r
+    return;\r
+  }\r
+\r
+  CurrentLang  = GetEfiGlobalVariable (L"PlatformLang");\r
+  DefaultLang  = (CHAR8 *) PcdGetPtr (PcdUefiVariableDefaultPlatformLang);\r
+  BestLanguage = GetBestLanguage (\r
+                   Languages,\r
+                   FALSE,\r
+                   (CurrentLang != NULL) ? CurrentLang : "",\r
+                   DefaultLang,\r
+                   NULL\r
+                   );\r
+  if (BestLanguage != NULL) {\r
+    //\r
+    // Find the best matching RFC 4646 language, compute the offset.\r
+    //\r
+    CompareLength = AsciiStrLen (BestLanguage);\r
+    for (MatchLang = Languages, (*Offset) = 0; MatchLang != '\0'; (*Offset)++) {\r
+      //\r
+      // Seek to the end of current match language.\r
+      //\r
+      for (EndMatchLang = MatchLang; *EndMatchLang != '\0' && *EndMatchLang != ';'; EndMatchLang++);\r
+\r
+      if ((EndMatchLang == MatchLang + CompareLength) && AsciiStrnCmp(MatchLang, BestLanguage, CompareLength) == 0) {\r
+        //\r
+        // Find the current best Language in the supported languages\r
+        //\r
+        break;\r
+      }\r
+      //\r
+      // best language match be in the supported language.\r
+      //\r
+      ASSERT (*EndMatchLang == ';');\r
+      MatchLang = EndMatchLang + 1;\r
+    }\r
+    FreePool (BestLanguage);\r
+  }\r
+\r
+  FreePool (Languages);\r
+  if (CurrentLang != NULL) {\r
+    FreePool (CurrentLang);\r
+  }\r
+  return ;\r
+}\r
+\r
+\r
+/**\r
+  Get next language from language code list (with separator ';').\r
+\r
+  @param  LangCode       Input: point to first language in the list. On\r
+                         Otput: point to next language in the list, or\r
+                                NULL if no more language in the list.\r
+  @param  Lang           The first language in the list.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+GetNextLanguage (\r
+  IN OUT CHAR8      **LangCode,\r
+  OUT CHAR8         *Lang\r
+  )\r
+{\r
+  UINTN  Index;\r
+  CHAR8  *StringPtr;\r
+\r
+  ASSERT (LangCode != NULL);\r
+  ASSERT (*LangCode != NULL);\r
+  ASSERT (Lang != NULL);\r
+\r
+  Index     = 0;\r
+  StringPtr = *LangCode;\r
+  while (StringPtr[Index] != 0 && StringPtr[Index] != ';') {\r
+    Index++;\r
+  }\r
+\r
+  CopyMem (Lang, StringPtr, Index);\r
+  Lang[Index] = 0;\r
+\r
+  if (StringPtr[Index] == ';') {\r
+    Index++;\r
+  }\r
+  *LangCode = StringPtr + Index;\r
+}\r
+\r
+/**\r
+  This function returns the number of supported languages on HiiHandle.\r
+\r
+  @param   HiiHandle    The HII package list handle.\r
+\r
+  @retval  The number of supported languages.\r
+\r
+**/\r
+UINT16\r
+EFIAPI\r
+GetSupportedLanguageNumber (\r
+  IN EFI_HII_HANDLE    HiiHandle\r
+  )\r
+{\r
+  CHAR8   *Lang;\r
+  CHAR8   *Languages;\r
+  CHAR8   *LanguageString;\r
+  UINT16  LangNumber;\r
+\r
+  Languages = HiiGetSupportedLanguages (HiiHandle);\r
+  if (Languages == NULL) {\r
+    return 0;\r
+  }\r
+\r
+  LangNumber = 0;\r
+  Lang = AllocatePool (AsciiStrSize (Languages));\r
+  if (Lang != NULL) {\r
+    LanguageString = Languages;\r
+    while (*LanguageString != 0) {\r
+      GetNextLanguage (&LanguageString, Lang);\r
+      LangNumber++;\r
+    }\r
+    FreePool (Lang);\r
+  }\r
+  FreePool (Languages);\r
+  return LangNumber;\r
+}\r
+\r
+\r
+/**\r
+  This function makes boot time changes to the contents of the\r
+  MiscNumberOfInstallableLanguages (Type 13).\r
+\r
+  @param  RecordData                 Pointer to copy of RecordData from the Data Table.\r
+\r
+  @retval EFI_SUCCESS                All parameters were valid.\r
+  @retval EFI_UNSUPPORTED            Unexpected RecordType value.\r
+  @retval EFI_INVALID_PARAMETER      Invalid parameter was found.\r
+\r
+**/\r
+MISC_SMBIOS_TABLE_FUNCTION(NumberOfInstallableLanguages)\r
+{\r
+  UINTN                                     LangStrLen;\r
+  CHAR8                                     CurrentLang[SMBIOS_STRING_MAX_LENGTH + 1];\r
+  CHAR8                                     *OptionalStrStart;\r
+  UINT16                                    Offset;\r
+  EFI_STATUS                                Status;\r
+  EFI_SMBIOS_HANDLE                         SmbiosHandle;\r
+  SMBIOS_TABLE_TYPE13                       *SmbiosRecord;\r
+  EFI_MISC_NUMBER_OF_INSTALLABLE_LANGUAGES  *ForType13InputData;\r
+\r
+  ForType13InputData = (EFI_MISC_NUMBER_OF_INSTALLABLE_LANGUAGES *)RecordData;\r
+\r
+  //\r
+  // First check for invalid parameters.\r
+  //\r
+  if (RecordData == NULL) {\r
+    return EFI_INVALID_PARAMETER;\r
+  }\r
+\r
+  ForType13InputData->NumberOfInstallableLanguages = GetSupportedLanguageNumber (mHiiHandle);\r
+\r
+  //\r
+  // Try to check if current langcode matches with the langcodes in installed languages\r
+  //\r
+  ZeroMem(CurrentLang, SMBIOS_STRING_MAX_LENGTH + 1);\r
+  CurrentLanguageMatch (mHiiHandle, &Offset, CurrentLang);\r
+  LangStrLen = AsciiStrLen(CurrentLang);\r
+\r
+  //\r
+  // Two zeros following the last string.\r
+  //\r
+  SmbiosRecord = AllocatePool(sizeof (SMBIOS_TABLE_TYPE13) + LangStrLen + 1 + 1);\r
+  ZeroMem(SmbiosRecord, sizeof (SMBIOS_TABLE_TYPE13) + LangStrLen + 1 + 1);\r
+\r
+  SmbiosRecord->Hdr.Type = EFI_SMBIOS_TYPE_BIOS_LANGUAGE_INFORMATION;\r
+  SmbiosRecord->Hdr.Length = sizeof (SMBIOS_TABLE_TYPE13);\r
+\r
+  //\r
+  // Make handle chosen by smbios protocol.add automatically.\r
+  //\r
+  SmbiosRecord->Hdr.Handle = 0;\r
+\r
+  SmbiosRecord->InstallableLanguages = (UINT8)ForType13InputData->NumberOfInstallableLanguages;\r
+  SmbiosRecord->Flags = (UINT8)ForType13InputData->LanguageFlags.AbbreviatedLanguageFormat;\r
+  SmbiosRecord->CurrentLanguages = 1;\r
+  OptionalStrStart = (CHAR8 *)(SmbiosRecord + 1);\r
+  AsciiStrCpy(OptionalStrStart, CurrentLang);\r
+\r
+  //\r
+  // Now we have got the full smbios record, call smbios protocol to add this record.\r
+  //\r
+  SmbiosHandle = SMBIOS_HANDLE_PI_RESERVED;\r
+  Status = Smbios-> Add(\r
+                      Smbios,\r
+                      NULL,\r
+                      &SmbiosHandle,\r
+                      (EFI_SMBIOS_TABLE_HEADER *) SmbiosRecord\r
+                      );\r
+  FreePool(SmbiosRecord);\r
+  return Status;\r
+}\r

diff --git a/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscOemString.uni b/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscOemString.uni
new file mode 100644 (file)
index 0000000..2162a79
Binary files /dev/null and b/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscOemString.uni differ

diff --git a/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscOemStringData.c b/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscOemStringData.c
new file mode 100644 (file)
index 0000000..294be04
--- /dev/null
+++ b/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscOemStringData.c
@@ -0,0 +1,39 @@
+/** @file\r
+\r
+Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+\r
+Module Name:\r
+\r
+    MiscOemStringData.c\r
+\r
+Abstract:\r
+\r
+  Static data of OEM String information.\r
+  OEM String information is Misc. subclass type 9 and SMBIOS type 11.\r
+\r
+\r
+**/\r
+\r
+\r
+#include "CommonHeader.h"\r
+\r
+#include "MiscSubclassDriver.h"\r
+\r
+//\r
+// Static (possibly build generated) Bios Vendor data.\r
+//\r
+MISC_SMBIOS_TABLE_DATA(EFI_MISC_OEM_STRING, MiscOemString) = {\r
+  STRING_TOKEN(STR_INTEL_ETK_VER)\r
+};\r
+MISC_SMBIOS_TABLE_DATA(EFI_MISC_OEM_STRING_DATA, OemString)\r
+= { STRING_TOKEN(STR_MISC_OEM_EN_US) };\r

diff --git a/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscOemStringFunction.c b/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscOemStringFunction.c
new file mode 100644 (file)
index 0000000..b53777c
--- /dev/null
+++ b/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscOemStringFunction.c
@@ -0,0 +1,94 @@
+/*++\r
+\r
+Copyright (c) 2009 - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+Module Name:\r
+\r
+  MiscOemStringFunction.c\r
+\r
+Abstract:\r
+\r
+  boot information boot time changes.\r
+  SMBIOS type 11.\r
+\r
+--*/\r
+\r
+\r
+#include "CommonHeader.h"\r
+\r
+#include "MiscSubclassDriver.h"\r
+\r
+/**\r
+  This function makes boot time changes to the contents of the\r
+  MiscOemString (Type 11).\r
+\r
+  @param  RecordData                 Pointer to copy of RecordData from the Data Table.\r
+\r
+  @retval EFI_SUCCESS                All parameters were valid.\r
+  @retval EFI_UNSUPPORTED            Unexpected RecordType value.\r
+  @retval EFI_INVALID_PARAMETER      Invalid parameter was found.\r
+\r
+**/\r
+MISC_SMBIOS_TABLE_FUNCTION(OemString)\r
+{\r
+  UINTN                    OemStrLen;\r
+  CHAR8                    *OptionalStrStart;\r
+  EFI_STATUS               Status;\r
+  EFI_STRING               OemStr;\r
+  STRING_REF               TokenToGet;\r
+  EFI_SMBIOS_HANDLE        SmbiosHandle;\r
+  SMBIOS_TABLE_TYPE11      *SmbiosRecord;\r
+\r
+  //\r
+  // First check for invalid parameters.\r
+  //\r
+  if (RecordData == NULL) {\r
+    return EFI_INVALID_PARAMETER;\r
+  }\r
+\r
+  TokenToGet = STRING_TOKEN (STR_MISC_OEM_EN_US);\r
+  OemStr = SmbiosMiscGetString (TokenToGet);\r
+  OemStrLen = StrLen(OemStr);\r
+  if (OemStrLen > SMBIOS_STRING_MAX_LENGTH) {\r
+    return EFI_UNSUPPORTED;\r
+  }\r
+\r
+  //\r
+  // Two zeros following the last string.\r
+  //\r
+  SmbiosRecord = AllocatePool(sizeof (SMBIOS_TABLE_TYPE11) + OemStrLen + 1 + 1);\r
+  ZeroMem(SmbiosRecord, sizeof (SMBIOS_TABLE_TYPE11) + OemStrLen + 1 + 1);\r
+\r
+  SmbiosRecord->Hdr.Type = EFI_SMBIOS_TYPE_OEM_STRINGS;\r
+  SmbiosRecord->Hdr.Length = sizeof (SMBIOS_TABLE_TYPE11);\r
+\r
+  //\r
+  // Make handle chosen by smbios protocol.add automatically.\r
+  //\r
+  SmbiosRecord->Hdr.Handle = 0;\r
+  SmbiosRecord->StringCount = 1;\r
+  OptionalStrStart = (CHAR8 *)(SmbiosRecord + 1);\r
+  UnicodeStrToAsciiStr(OemStr, OptionalStrStart);\r
+\r
+  //\r
+  // Now we have got the full smbios record, call smbios protocol to add this record.\r
+  //\r
+  SmbiosHandle = SMBIOS_HANDLE_PI_RESERVED;\r
+  Status = Smbios-> Add(\r
+                      Smbios,\r
+                      NULL,\r
+                      &SmbiosHandle,\r
+                      (EFI_SMBIOS_TABLE_HEADER *) SmbiosRecord\r
+                      );\r
+  FreePool(SmbiosRecord);\r
+  return Status;\r
+}\r

diff --git a/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscOemType0x90.uni b/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscOemType0x90.uni
new file mode 100644 (file)
index 0000000..3b49a6e
Binary files /dev/null and b/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscOemType0x90.uni differ

diff --git a/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscOemType0x90Data.c b/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscOemType0x90Data.c
new file mode 100644 (file)
index 0000000..f45650a
--- /dev/null
+++ b/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscOemType0x90Data.c
@@ -0,0 +1,41 @@
+/*++\r
+\r
+Copyright (c) 2012  - 2014, Intel Corporation.  All rights reserved.\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+\r
+\r
+Module Name:\r
+\r
+  MiscOemType0x90Data.c\r
+\r
+Abstract:\r
+\r
+  This file contains the Misc Oem Data (SMBIOS data type 0x90)\r
+\r
+--*/\r
+\r
+#include "CommonHeader.h"\r
+\r
+#include "MiscSubclassDriver.h"\r
+\r
+\r
+//\r
+// Static (possibly build generated) Oem data.\r
+//\r
+MISC_SMBIOS_TABLE_DATA(EFI_MISC_OEM_TYPE_0x90, MiscOemType0x90) = {\r
+\r
+STRING_TOKEN (STR_MISC_SEC_VERSION),\r
+STRING_TOKEN (STR_MISC_UCODE_VERSION),\r
+STRING_TOKEN (STR_MISC_GOP_VERSION),\r
+STRING_TOKEN (STR_MISC_PROCESSOR_STEPPING),\r
+\r
+};\r

diff --git a/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscOemType0x90Function.c b/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscOemType0x90Function.c
new file mode 100644 (file)
index 0000000..2d0bf8b
--- /dev/null
+++ b/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscOemType0x90Function.c
@@ -0,0 +1,452 @@
+/*++\r
+\r
+Copyright (c) 1999  - 2014, Intel Corporation.  All rights reserved.\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+\r
+\r
+Module Name:\r
+\r
+  MiscOemType0x88Function.c\r
+\r
+Abstract:\r
+\r
+  The function that processes the Smbios data type 0x88 before they\r
+  are submitted to Data Hub\r
+\r
+--*/\r
+\r
+#include "CommonHeader.h"\r
+\r
+#include "MiscSubclassDriver.h"\r
+#include <Library/PrintLib.h>\r
+#include <Library/CpuIA32.h>\r
+#include <Protocol/DxeSmmReadyToLock.h>\r
+\r
+\r
+VOID\r
+GetCPUStepping ( )\r
+{\r
+  CHAR16    Buffer[40];\r
+\r
+  UINT16                                FamilyId;\r
+  UINT8                                 Model;\r
+  UINT8                                 SteppingId;\r
+  UINT8                                 ProcessorType;\r
+\r
+\r
+  EfiCpuVersion (&FamilyId, &Model, &SteppingId, &ProcessorType);\r
+\r
+  //\r
+  //we need raw Model data\r
+  //\r
+  Model = Model & 0xf;\r
+\r
+  //\r
+  //Family/Model/Step\r
+  //\r
+  UnicodeSPrint (Buffer, sizeof (Buffer), L"%d/%d/%d", FamilyId,  Model, SteppingId);\r
+  HiiSetString(mHiiHandle,STRING_TOKEN(STR_MISC_PROCESSOR_STEPPING), Buffer, NULL);\r
+\r
+}\r
+\r
+EFI_STATUS\r
+SearchChildHandle(\r
+  EFI_HANDLE Father,\r
+  EFI_HANDLE *Child\r
+  )\r
+{\r
+  EFI_STATUS                                                 Status;\r
+  UINTN                                                          HandleIndex;\r
+  EFI_GUID                                                     **ProtocolGuidArray = NULL;\r
+  UINTN                                                          ArrayCount;\r
+  UINTN                                                          ProtocolIndex;\r
+  UINTN                                                          OpenInfoCount;\r
+  UINTN                                                          OpenInfoIndex;\r
+  EFI_OPEN_PROTOCOL_INFORMATION_ENTRY  *OpenInfo = NULL;\r
+  UINTN                                                          mHandleCount;\r
+  EFI_HANDLE                                                 *mHandleBuffer= NULL;\r
+\r
+  //\r
+  // Retrieve the list of all handles from the handle database\r
+  //\r
+  Status = gBS->LocateHandleBuffer (\r
+                  AllHandles,\r
+                  NULL,\r
+                  NULL,\r
+                  &mHandleCount,\r
+                  &mHandleBuffer\r
+                  );\r
+\r
+  for (HandleIndex = 0; HandleIndex < mHandleCount; HandleIndex++) {\r
+    //\r
+    // Retrieve the list of all the protocols on each handle\r
+    //\r
+    Status = gBS->ProtocolsPerHandle (\r
+                    mHandleBuffer[HandleIndex],\r
+                    &ProtocolGuidArray,\r
+                    &ArrayCount\r
+                    );\r
+    if (!EFI_ERROR (Status)) {\r
+      for (ProtocolIndex = 0; ProtocolIndex < ArrayCount; ProtocolIndex++) {\r
+        Status = gBS->OpenProtocolInformation (\r
+                        mHandleBuffer[HandleIndex],\r
+                        ProtocolGuidArray[ProtocolIndex],\r
+                        &OpenInfo,\r
+                        &OpenInfoCount\r
+                        );\r
+\r
+        if (!EFI_ERROR (Status)) {\r
+          for (OpenInfoIndex = 0; OpenInfoIndex < OpenInfoCount; OpenInfoIndex++) {\r
+            if(OpenInfo[OpenInfoIndex].AgentHandle == Father) {\r
+              if ((OpenInfo[OpenInfoIndex].Attributes & EFI_OPEN_PROTOCOL_BY_CHILD_CONTROLLER) == EFI_OPEN_PROTOCOL_BY_CHILD_CONTROLLER) {\r
+                *Child = mHandleBuffer[HandleIndex];\r
+                 Status = EFI_SUCCESS;\r
+                 goto TryReturn;\r
+              }\r
+            }\r
+          }\r
+          Status = EFI_NOT_FOUND;\r
+       }\r
+      }\r
+      if(OpenInfo != NULL) {\r
+        FreePool(OpenInfo);\r
+             OpenInfo = NULL;\r
+      }\r
+    }\r
+    if(ProtocolGuidArray != NULL) {\r
+    FreePool (ProtocolGuidArray);\r
+    ProtocolGuidArray = NULL;\r
+    }\r
+  }\r
+TryReturn:\r
+  if(OpenInfo != NULL) {\r
+    FreePool (OpenInfo);\r
+    OpenInfo = NULL;\r
+  }\r
+  if(ProtocolGuidArray != NULL) {\r
+    FreePool(ProtocolGuidArray);\r
+    ProtocolGuidArray = NULL;\r
+  }\r
+  if(mHandleBuffer != NULL) {\r
+    FreePool (mHandleBuffer);\r
+    mHandleBuffer = NULL;\r
+  }\r
+  return Status;\r
+}\r
+\r
+EFI_STATUS\r
+JudgeHandleIsPCIDevice(\r
+  EFI_HANDLE    Handle,\r
+  UINT8            Device,\r
+  UINT8            Funs\r
+  )\r
+{\r
+  EFI_STATUS  Status;\r
+  EFI_DEVICE_PATH   *DPath;\r
+  EFI_DEVICE_PATH   *DevicePath;\r
+\r
+  Status = gBS->HandleProtocol (\r
+                  Handle,\r
+                  &gEfiDevicePathProtocolGuid,\r
+                  (VOID **) &DPath\r
+                  );\r
+  if(!EFI_ERROR(Status)) {\r
+    DevicePath = DPath;\r
+    while(!IsDevicePathEnd(DPath)) {\r
+      if((DPath->Type == HARDWARE_DEVICE_PATH) && (DPath->SubType == HW_PCI_DP)) {\r
+        PCI_DEVICE_PATH   *PCIPath;\r
+        PCIPath = (PCI_DEVICE_PATH*) DPath;\r
+        DPath = NextDevicePathNode(DPath);\r
+\r
+        if(IsDevicePathEnd(DPath) && (PCIPath->Device == Device) && (PCIPath->Function == Funs)) {\r
+          return EFI_SUCCESS;\r
+        }\r
+      } else {\r
+        DPath = NextDevicePathNode(DPath);\r
+      }\r
+    }\r
+  }\r
+  return EFI_UNSUPPORTED;\r
+}\r
+\r
+EFI_STATUS\r
+GetDriverName(\r
+  EFI_HANDLE   Handle\r
+)\r
+{\r
+  EFI_DRIVER_BINDING_PROTOCOL        *BindHandle = NULL;\r
+  EFI_STATUS                         Status;\r
+  UINT32                             Version;\r
+  UINT16                             *Ptr;\r
+  CHAR16                             Buffer[40];\r
+  STRING_REF                  TokenToUpdate;\r
+  Status = gBS->OpenProtocol(\r
+                  Handle,\r
+                  &gEfiDriverBindingProtocolGuid,\r
+                  (VOID**)&BindHandle,\r
+                   NULL,\r
+                   NULL,\r
+                   EFI_OPEN_PROTOCOL_GET_PROTOCOL\r
+                   );\r
+\r
+  if (EFI_ERROR(Status)) {\r
+    return EFI_NOT_FOUND;\r
+  }\r
+\r
+  Version = BindHandle->Version;\r
+  Ptr = (UINT16*)&Version;\r
+  UnicodeSPrint(Buffer, sizeof (Buffer), L"%d.%d.%d", Version >> 24 , (Version >>16)& 0x0f ,*(Ptr));\r
+\r
+  TokenToUpdate = (STRING_REF)STR_MISC_GOP_VERSION;\r
+  HiiSetString(mHiiHandle, TokenToUpdate, Buffer, NULL);\r
+\r
+  return EFI_SUCCESS;\r
+}\r
+\r
+EFI_STATUS\r
+GetGOPDriverName()\r
+{\r
+  UINTN                         HandleCount;\r
+  EFI_HANDLE                *Handles= NULL;\r
+  UINTN                         Index;\r
+  EFI_STATUS                Status;\r
+  EFI_HANDLE                Child = 0;\r
+\r
+  Status = gBS->LocateHandleBuffer(\r
+                             ByProtocol,\r
+                             &gEfiDriverBindingProtocolGuid,\r
+                             NULL,\r
+                             &HandleCount,\r
+                             &Handles\r
+                  );\r
+\r
+  for (Index = 0; Index < HandleCount ; Index++) {\r
+    Status = SearchChildHandle(Handles[Index], &Child);\r
+    if(!EFI_ERROR(Status)) {\r
+      Status = JudgeHandleIsPCIDevice(Child, 0x02, 0x00);\r
+      if(!EFI_ERROR(Status)) {\r
+        return GetDriverName(Handles[Index]);\r
+      }\r
+    }\r
+  }\r
+  return EFI_UNSUPPORTED;\r
+}\r
+\r
+VOID\r
+GetUcodeVersion()\r
+{\r
+  UINT32                   MicroCodeVersion;\r
+  CHAR16                   Buffer[40];\r
+\r
+  //\r
+  // Microcode Revision\r
+  //\r
+  EfiWriteMsr (EFI_MSR_IA32_BIOS_SIGN_ID, 0);\r
+  EfiCpuid (EFI_CPUID_VERSION_INFO, NULL);\r
+  MicroCodeVersion = (UINT32) RShiftU64 (EfiReadMsr (EFI_MSR_IA32_BIOS_SIGN_ID), 32);\r
+  UnicodeSPrint (Buffer, sizeof (Buffer), L"%x", MicroCodeVersion);\r
+  HiiSetString(mHiiHandle,STRING_TOKEN(STR_MISC_UCODE_VERSION), Buffer, NULL);\r
+}\r
+\r
+/**\r
+  Publish the smbios OEM type 0x90.\r
+\r
+  @param Event   - Event whose notification function is being invoked (gEfiDxeSmmReadyToLockProtocolGuid).\r
+  @param Context - Pointer to the notification functions context, which is implementation dependent.\r
+\r
+  @retval None\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+AddSmbiosT0x90Callback (\r
+  IN EFI_EVENT  Event,\r
+  IN VOID       *Context\r
+  )\r
+{\r
+  EFI_STATUS            Status;\r
+  UINTN                 SECVerStrLen = 0;\r
+  UINTN                 uCodeVerStrLen = 0;\r
+  UINTN                 GOPStrLen = 0;\r
+  UINTN                 SteppingStrLen = 0;\r
+  SMBIOS_TABLE_TYPE90    *SmbiosRecord;\r
+  EFI_SMBIOS_HANDLE     SmbiosHandle;\r
+  EFI_MISC_OEM_TYPE_0x90  *ForType90InputData;\r
+  CHAR16                *SECVer;\r
+  CHAR16                *uCodeVer;\r
+  CHAR16                *GOPVer;\r
+  CHAR16                *Stepping;\r
+  STRING_REF            TokenToGet;\r
+  CHAR8                 *OptionalStrStart;\r
+  EFI_SMBIOS_PROTOCOL               *SmbiosProtocol;\r
+\r
+  ForType90InputData        = (EFI_MISC_OEM_TYPE_0x90 *)Context;\r
+\r
+  DEBUG ((EFI_D_INFO, "Executing SMBIOS T0x90 callback.\n"));\r
+\r
+  gBS->CloseEvent (Event);    // Unload this event.\r
+\r
+  //\r
+  // First check for invalid parameters.\r
+  //\r
+  if (Context == NULL) {\r
+    return EFI_INVALID_PARAMETER;\r
+  }\r
+\r
+  Status = gBS->LocateProtocol (\r
+                  &gEfiSmbiosProtocolGuid,\r
+                  NULL,\r
+                  (VOID *) &SmbiosProtocol\r
+                  );\r
+  ASSERT_EFI_ERROR (Status);\r
+\r
+  GetUcodeVersion();\r
+  GetGOPDriverName();\r
+  GetCPUStepping();\r
+\r
+  TokenToGet = STRING_TOKEN (STR_MISC_SEC_VERSION);\r
+  SECVer = SmbiosMiscGetString (TokenToGet);\r
+  SECVerStrLen = StrLen(SECVer);\r
+  if (SECVerStrLen > SMBIOS_STRING_MAX_LENGTH) {\r
+    return EFI_UNSUPPORTED;\r
+  }\r
+\r
+  TokenToGet = STRING_TOKEN (STR_MISC_UCODE_VERSION);\r
+  uCodeVer = SmbiosMiscGetString (TokenToGet);\r
+  uCodeVerStrLen = StrLen(uCodeVer);\r
+  if (uCodeVerStrLen > SMBIOS_STRING_MAX_LENGTH) {\r
+    return EFI_UNSUPPORTED;\r
+  }\r
+\r
+  TokenToGet = STRING_TOKEN (STR_MISC_GOP_VERSION);\r
+  GOPVer = SmbiosMiscGetString (TokenToGet);\r
+  GOPStrLen = StrLen(GOPVer);\r
+  if (GOPStrLen > SMBIOS_STRING_MAX_LENGTH) {\r
+    return EFI_UNSUPPORTED;\r
+  }\r
+\r
+  TokenToGet = STRING_TOKEN (STR_MISC_PROCESSOR_STEPPING);\r
+  Stepping = SmbiosMiscGetString (TokenToGet);\r
+  SteppingStrLen = StrLen(Stepping);\r
+\r
+\r
+  if (SteppingStrLen > SMBIOS_STRING_MAX_LENGTH) {\r
+    return EFI_UNSUPPORTED;\r
+  }\r
+\r
+  SmbiosRecord = AllocatePool(sizeof (SMBIOS_TABLE_TYPE90) + SECVerStrLen + 1 + uCodeVerStrLen + 1 + GOPStrLen + 1 + SteppingStrLen + 1 + 1);\r
+  ZeroMem(SmbiosRecord, sizeof (SMBIOS_TABLE_TYPE90) + SECVerStrLen + 1 + uCodeVerStrLen + 1 + GOPStrLen + 1 + SteppingStrLen + 1 + 1);\r
+\r
+  SmbiosRecord->Hdr.Type = EFI_SMBIOS_TYPE_FIRMWARE_VERSION_INFO;\r
+  SmbiosRecord->Hdr.Length = sizeof (SMBIOS_TABLE_TYPE90);\r
+\r
+  //\r
+  // Make handle chosen by smbios protocol.add automatically.\r
+  //\r
+  SmbiosRecord->Hdr.Handle = 0;\r
+\r
+  //\r
+  // SEC VERSION will be the 1st optional string following the formatted structure.\r
+  //\r
+  SmbiosRecord->SECVersion = 0;\r
+\r
+  //\r
+  // Microcode VERSION will be the 2nd optional string following the formatted structure.\r
+  //\r
+  SmbiosRecord->uCodeVersion = 2;\r
+\r
+  //\r
+  // GOP VERSION will be the 3rd optional string following the formatted structure.\r
+  //\r
+  SmbiosRecord->GOPVersion = 3;\r
+\r
+  //\r
+  // CPU Stepping will be the 4th optional string following the formatted structure.\r
+  //\r
+  SmbiosRecord->CpuStepping = 4;\r
+\r
+  OptionalStrStart = (CHAR8 *)(SmbiosRecord + 1);\r
+  UnicodeStrToAsciiStr(SECVer, OptionalStrStart);\r
+  UnicodeStrToAsciiStr(uCodeVer, OptionalStrStart + SECVerStrLen + 1);\r
+  UnicodeStrToAsciiStr(GOPVer, OptionalStrStart + SECVerStrLen + 1 + uCodeVerStrLen + 1);\r
+  UnicodeStrToAsciiStr(Stepping, OptionalStrStart + SECVerStrLen + 1 + uCodeVerStrLen + 1 + GOPStrLen + 1);\r
+\r
+  //\r
+  // Now we have got the full smbios record, call smbios protocol to add this record.\r
+  //\r
+  SmbiosHandle = SMBIOS_HANDLE_PI_RESERVED;\r
+  Status = SmbiosProtocol-> Add(\r
+                              SmbiosProtocol,\r
+                              NULL,\r
+                              &SmbiosHandle,\r
+                              (EFI_SMBIOS_TABLE_HEADER *) SmbiosRecord\r
+                              );\r
+\r
+  FreePool(SmbiosRecord);\r
+  return Status;\r
+}\r
+\r
+\r
+/**\r
+  This function makes boot time changes to the contents of the\r
+  MiscOemType0x90 (Type 0x90).\r
+\r
+  @param  RecordData                 Pointer to copy of RecordData from the Data Table.\r
+\r
+  @retval EFI_SUCCESS                All parameters were valid.\r
+  @retval EFI_UNSUPPORTED            Unexpected RecordType value.\r
+  @retval EFI_INVALID_PARAMETER      Invalid parameter was found.\r
+\r
+**/\r
+MISC_SMBIOS_TABLE_FUNCTION(MiscOemType0x90)\r
+{\r
+  EFI_STATUS                    Status;\r
+  static BOOLEAN                CallbackIsInstalledT0x90 = FALSE;\r
+  VOID                           *AddSmbiosT0x90CallbackNotifyReg;\r
+  EFI_EVENT                      AddSmbiosT0x90CallbackEvent;\r
+\r
+  //\r
+  // This callback will create a OEM Type 0x90 record.\r
+  //\r
+  if (CallbackIsInstalledT0x90 == FALSE) {\r
+    CallbackIsInstalledT0x90 = TRUE;           // Prevent more than 1 callback.\r
+    DEBUG ((EFI_D_INFO, "Create Smbios T0x90 callback.\n"));\r
+\r
+  //\r
+  // gEfiDxeSmmReadyToLockProtocolGuid is ready\r
+  //\r
+  Status = gBS->CreateEvent (\r
+                  EVT_NOTIFY_SIGNAL,\r
+                  TPL_CALLBACK,\r
+                  (EFI_EVENT_NOTIFY)AddSmbiosT0x90Callback,\r
+                  RecordData,\r
+                  &AddSmbiosT0x90CallbackEvent\r
+                  );\r
+\r
+  ASSERT_EFI_ERROR (Status);\r
+  if (EFI_ERROR (Status)) {\r
+    return Status;\r
+\r
+  }\r
+\r
+  Status = gBS->RegisterProtocolNotify (\r
+                  &gEfiDxeSmmReadyToLockProtocolGuid,\r
+                  AddSmbiosT0x90CallbackEvent,\r
+                  &AddSmbiosT0x90CallbackNotifyReg\r
+                  );\r
+\r
+  return Status;\r
+  }\r
+\r
+  return EFI_SUCCESS;\r
+\r
+}\r

diff --git a/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscOemType0x94.uni b/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscOemType0x94.uni
new file mode 100644 (file)
index 0000000..061ad6a
Binary files /dev/null and b/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscOemType0x94.uni differ

diff --git a/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscOemType0x94Data.c b/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscOemType0x94Data.c
new file mode 100644 (file)
index 0000000..94847d5
--- /dev/null
+++ b/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscOemType0x94Data.c
@@ -0,0 +1,59 @@
+/*++\r
+\r
+Copyright (c) 2012  - 2014, Intel Corporation.  All rights reserved.\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+\r
+\r
+Module Name:\r
+\r
+  MiscOemType0x94Data.c\r
+\r
+Abstract:\r
+\r
+  This file contains the Misc version Data (SMBIOS data type 0x94)\r
+\r
+--*/\r
+\r
+#include "CommonHeader.h"\r
+\r
+#include "MiscSubclassDriver.h"\r
+\r
+\r
+//\r
+// Static (possibly build generated) Oem data.\r
+//\r
+MISC_SMBIOS_TABLE_DATA(EFI_MISC_OEM_TYPE_0x94, MiscOemType0x94) = {\r
+\r
+STRING_TOKEN (STR_MISC_GOP_VERSION),\r
+STRING_TOKEN (STR_MISC_SEC_VERSION),\r
+STRING_TOKEN (STR_MISC_MRC_VERSION_VALUE),\r
+STRING_TOKEN (STR_MISC_UCODE_VERSION),\r
+STRING_TOKEN (STR_MISC_PUNIT_FW_VALUE),\r
+STRING_TOKEN (STR_MISC_PMC_FW_VALUE),\r
+STRING_TOKEN (STR_MISC_ULPMC_FW_VALUE),\r
+STRING_TOKEN (STR_MISC_SOC_VALUE),\r
+STRING_TOKEN (STR_MISC_BOARD_ID_VALUE),\r
+STRING_TOKEN (STR_MISC_FAB_ID_VALUE),\r
+STRING_TOKEN (STR_MISC_CPU_FLAVOR_VALUE),\r
+STRING_TOKEN (STR_MISC_BIOS_VERSION),\r
+STRING_TOKEN (STR_MISC_PMIC_VERSION),\r
+STRING_TOKEN (STR_MISC_TOUCH_VERSION),\r
+STRING_TOKEN (STR_MISC_SECURE_BOOT),\r
+STRING_TOKEN (STR_MISC_BOOT_MODE),\r
+STRING_TOKEN (STR_MISC_SPEED_STEP),\r
+STRING_TOKEN (STR_MISC_CPU_TURBO),\r
+STRING_TOKEN (STR_MISC_CSTATE),\r
+STRING_TOKEN (STR_MISC_GFX_TURBO),\r
+STRING_TOKEN (STR_MISC_S0IX_VALUE),\r
+STRING_TOKEN (STR_MISC_RC6_VALUE),\r
+\r
+};\r

diff --git a/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscOemType0x94Function.c b/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscOemType0x94Function.c
new file mode 100644 (file)
index 0000000..898fc7c
--- /dev/null
+++ b/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscOemType0x94Function.c
@@ -0,0 +1,1223 @@
+/*++\r
+\r
+Copyright (c) 1999  - 2014, Intel Corporation.  All rights reserved.\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+\r
+\r
+Module Name:\r
+\r
+  MiscOemType0x94Function.c\r
+\r
+Abstract:\r
+\r
+  The function that processes the Smbios data type 0x94.\r
+\r
+--*/\r
+\r
+#include "CommonHeader.h"\r
+\r
+#include "MiscSubclassDriver.h"\r
+#include <Protocol/DataHub.h>\r
+#include <Library/HiiLib.h>\r
+#include <Protocol/CpuIo2.h>\r
+#include <Library/PrintLib.h>\r
+#include <Protocol/PciRootBridgeIo.h>\r
+#include <Protocol/SimpleNetwork.h>\r
+#include <Protocol/DevicePath.h>\r
+#include <Protocol/DiskInfo.h>\r
+#include <Protocol/IdeControllerInit.h>\r
+#include <Protocol/MpService.h>\r
+#include <Protocol/PchPlatformPolicy.h>\r
+#include <Protocol/CpuIo2.h>\r
+#include <Protocol/I2cBus.h>\r
+\r
+#include <Library/IoLib.h>\r
+#include <Library/I2CLib.h>\r
+#include <Library/CpuIA32.h>\r
+#include <Library/UefiRuntimeServicesTableLib.h>\r
+#include <Guid/PlatformInfo.h>\r
+#include <Guid/SetupVariable.h>\r
+#include <Guid/Vlv2Variable.h>\r
+\r
+#include "Valleyview.h"\r
+#include "VlvAccess.h"\r
+#include "PchAccess.h"\r
+#include "SetupMode.h"\r
+#include "PchCommonDefinitions.h"\r
+#include <PlatformBaseAddresses.h>\r
+\r
+typedef struct {\r
+  UINT8 RevId;\r
+  CHAR8 String[16];\r
+} SB_REV;\r
+\r
+//\r
+// Silicon Steppings\r
+//\r
+SB_REV  SBRevisionTable[] = {\r
+  {V_PCH_LPC_RID_0, "(A0 Stepping)"},\r
+  {V_PCH_LPC_RID_1, "(A0 Stepping)"},\r
+  {V_PCH_LPC_RID_2, "(A1 Stepping)"},\r
+  {V_PCH_LPC_RID_3, "(A1 Stepping)"},\r
+  {V_PCH_LPC_RID_4, "(B0 Stepping)"},\r
+  {V_PCH_LPC_RID_5, "(B0 Stepping)"},\r
+  {V_PCH_LPC_RID_6, "(B1 Stepping)"},\r
+  {V_PCH_LPC_RID_7, "(B1 Stepping)"},\r
+  {V_PCH_LPC_RID_8, "(B2 Stepping)"},\r
+  {V_PCH_LPC_RID_9, "(B2 Stepping)"},\r
+  {V_PCH_LPC_RID_A, "(B3 Stepping)"},\r
+  {V_PCH_LPC_RID_B, "(B3 Stepping)"}\r
+};\r
+\r
+#define LEFT_JUSTIFY  0x01\r
+#define PREFIX_SIGN   0x02\r
+#define PREFIX_BLANK  0x04\r
+#define COMMA_TYPE    0x08\r
+#define LONG_TYPE     0x10\r
+#define PREFIX_ZERO   0x20\r
+\r
+#define ICH_REG_REV                 0x08\r
+#define MSR_IA32_PLATFORM_ID        0x17\r
+#define CHARACTER_NUMBER_FOR_VALUE  30\r
+\r
+\r
+UINT8  ReadBuffer[20];  //Version report length\r
+UINT8  WriteBuffer[22] = {0x40,0x01,0x14,0x00,0x06,0x51,0x02,0x07,0,0,0,0,0,0,0,0,0,0,0,0,0,0}; //Version request\r
+\r
+/**\r
+\r
+  VSPrint worker function that prints a Value as a decimal number in Buffer\r
+\r
+  @param Buffer  Location to place ascii decimal number string of Value.\r
+  @param Value   Decimal value to convert to a string in Buffer.\r
+  @param Flags   Flags to use in printing decimal string, see file header for details.\r
+  @param Width   Width of hex value.\r
+\r
+  @retval Number of characters printed.\r
+\r
+**/\r
+UINTN\r
+EfiValueToString (\r
+  IN  OUT CHAR16  *Buffer,\r
+  IN  INT64       Value,\r
+  IN  UINTN       Flags,\r
+  IN  UINTN       Width\r
+  )\r
+{\r
+  CHAR16    TempBuffer[CHARACTER_NUMBER_FOR_VALUE];\r
+  CHAR16    *TempStr;\r
+  CHAR16    *BufferPtr;\r
+  UINTN     Count;\r
+  UINTN     ValueCharNum;\r
+  UINTN     Remainder;\r
+  CHAR16    Prefix;\r
+  UINTN     Index;\r
+  BOOLEAN   ValueIsNegative;\r
+  UINT64    TempValue;\r
+\r
+  TempStr         = TempBuffer;\r
+  BufferPtr       = Buffer;\r
+  Count           = 0;\r
+  ValueCharNum    = 0;\r
+  ValueIsNegative = FALSE;\r
+\r
+  if (Width > CHARACTER_NUMBER_FOR_VALUE - 1) {\r
+    Width = CHARACTER_NUMBER_FOR_VALUE - 1;\r
+  }\r
+\r
+  if (Value < 0) {\r
+    Value           = -Value;\r
+    ValueIsNegative = TRUE;\r
+  }\r
+\r
+  do {\r
+    TempValue = Value;\r
+    Value = (INT64)DivU64x32 ((UINT64)Value, 10);\r
+    Remainder = (UINTN)((UINT64)TempValue - 10 * Value);\r
+    *(TempStr++) = (CHAR16)(Remainder + '0');\r
+    ValueCharNum++;\r
+    Count++;\r
+    if ((Flags & COMMA_TYPE) == COMMA_TYPE) {\r
+      if (ValueCharNum % 3 == 0 && Value != 0) {\r
+        *(TempStr++) = ',';\r
+        Count++;\r
+      }\r
+    }\r
+  } while (Value != 0);\r
+\r
+  if (ValueIsNegative) {\r
+    *(TempStr++)    = '-';\r
+    Count++;\r
+  }\r
+\r
+  if ((Flags & PREFIX_ZERO) && !ValueIsNegative) {\r
+    Prefix = '0';\r
+  } else {\r
+    Prefix = ' ';\r
+  }\r
+\r
+  Index = Count;\r
+  if (!(Flags & LEFT_JUSTIFY)) {\r
+    for (; Index < Width; Index++) {\r
+      *(TempStr++) = Prefix;\r
+    }\r
+  }\r
+\r
+  //\r
+  // Reverse temp string into Buffer.\r
+  //\r
+  if (Width > 0 && (UINTN) (TempStr - TempBuffer) > Width) {\r
+    TempStr = TempBuffer + Width;\r
+  }\r
+  Index = 0;\r
+  while (TempStr != TempBuffer) {\r
+    *(BufferPtr++) = *(--TempStr);\r
+    Index++;\r
+  }\r
+\r
+  *BufferPtr = 0;\r
+  return Index;\r
+}\r
+\r
+static CHAR16 mHexStr[] = { L'0', L'1', L'2', L'3', L'4', L'5', L'6', L'7',\r
+                            L'8', L'9', L'A', L'B', L'C', L'D', L'E', L'F' };\r
+/**\r
+  VSPrint worker function that prints a Value as a hex number in Buffer\r
+\r
+  @param Buffer   Location to place ascii hex string of Value.\r
+  @param Value    Hex value to convert to a string in Buffer.\r
+  @param Flags    Flags to use in printing Hex string, see file header for details.\r
+  @param Width    Width of hex value.\r
+\r
+  @retval Number of characters printed.\r
+\r
+**/\r
+UINTN\r
+EfiValueToHexStr (\r
+  IN  OUT CHAR16  *Buffer,\r
+  IN  UINT64      Value,\r
+  IN  UINTN       Flags,\r
+  IN  UINTN       Width\r
+  )\r
+{\r
+  CHAR16  TempBuffer[CHARACTER_NUMBER_FOR_VALUE];\r
+  CHAR16  *TempStr;\r
+  CHAR16  Prefix;\r
+  CHAR16  *BufferPtr;\r
+  UINTN   Count;\r
+  UINTN   Index;\r
+\r
+  TempStr   = TempBuffer;\r
+  BufferPtr = Buffer;\r
+\r
+  //\r
+  // Count starts at one since we will null terminate. Each iteration of the\r
+  // loop picks off one nibble. Oh yea TempStr ends up backwards\r
+  //\r
+  Count = 0;\r
+\r
+  if (Width > CHARACTER_NUMBER_FOR_VALUE - 1) {\r
+    Width = CHARACTER_NUMBER_FOR_VALUE - 1;\r
+  }\r
+\r
+  do {\r
+    Index = ((UINTN)Value & 0xf);\r
+    *(TempStr++) = mHexStr[Index];\r
+    Value = RShiftU64 (Value, 4);\r
+    Count++;\r
+  } while (Value != 0);\r
+\r
+  if (Flags & PREFIX_ZERO) {\r
+    Prefix = '0';\r
+  } else {\r
+    Prefix = ' ';\r
+  }\r
+\r
+  Index = Count;\r
+  if (!(Flags & LEFT_JUSTIFY)) {\r
+    for (; Index < Width; Index++) {\r
+      *(TempStr++) = Prefix;\r
+    }\r
+  }\r
+\r
+  //\r
+  // Reverse temp string into Buffer.\r
+  //\r
+  if (Width > 0 && (UINTN) (TempStr - TempBuffer) > Width) {\r
+    TempStr = TempBuffer + Width;\r
+  }\r
+  Index = 0;\r
+  while (TempStr != TempBuffer) {\r
+    *(BufferPtr++) = *(--TempStr);\r
+    Index++;\r
+  }\r
+\r
+  *BufferPtr = 0;\r
+  return Index;\r
+}\r
+\r
+/**\r
+  Converts MAC address to Unicode string.\r
+  The value is 64-bit and the resulting string will be 12\r
+  digit hex number in pairs of digits separated by dashes.\r
+\r
+  @param String - string that will contain the value\r
+  @param Val    - value to convert\r
+\r
+**/\r
+CHAR16 *\r
+StrMacToString (\r
+  OUT CHAR16              *String,\r
+  IN  EFI_MAC_ADDRESS     *MacAddr,\r
+  IN  UINT32              AddrSize\r
+  )\r
+{\r
+  UINT32  i;\r
+\r
+  for (i = 0; i < AddrSize; i++) {\r
+\r
+    EfiValueToHexStr (\r
+      &String[2 * i],\r
+      MacAddr->Addr[i] & 0xFF,\r
+      PREFIX_ZERO,\r
+      2\r
+      );\r
+  }\r
+\r
+  //\r
+  // Terminate the string.\r
+  //\r
+  String[2 * AddrSize] = L'\0';\r
+\r
+  return String;\r
+}\r
+\r
+\r
+\r
+EFI_STATUS\r
+TJudgeHandleIsPCIDevice(\r
+  EFI_HANDLE    Handle,\r
+  UINT8            Device,\r
+  UINT8            Funs\r
+)\r
+{\r
+  EFI_STATUS  Status;\r
+  EFI_DEVICE_PATH   *DPath;\r
+  EFI_DEVICE_PATH   *DevicePath;\r
+\r
+  Status = gBS->HandleProtocol (\r
+                  Handle,\r
+                  &gEfiDevicePathProtocolGuid,\r
+                  (VOID **) &DPath\r
+                  );\r
+  if(!EFI_ERROR(Status))\r
+  {\r
+    DevicePath = DPath;\r
+    while(!IsDevicePathEnd(DPath))\r
+    {\r
+      if((DPath->Type == HARDWARE_DEVICE_PATH) && (DPath->SubType == HW_PCI_DP))\r
+      {\r
+        PCI_DEVICE_PATH   *PCIPath;\r
+\r
+        PCIPath = (PCI_DEVICE_PATH*) DPath;\r
+        DPath = NextDevicePathNode(DPath);\r
+        if(IsDevicePathEnd(DPath) && (PCIPath->Device == Device) && (PCIPath->Function == Funs))\r
+        {\r
+          return EFI_SUCCESS;\r
+        }\r
+      }\r
+      else\r
+      {\r
+        DPath = NextDevicePathNode(DPath);\r
+      }\r
+    }\r
+  }\r
+  return EFI_UNSUPPORTED;\r
+}\r
+\r
+EFI_STATUS\r
+TSearchChildHandle(\r
+  EFI_HANDLE Father,\r
+  EFI_HANDLE *Child\r
+  )\r
+{\r
+  EFI_STATUS                                                 Status;\r
+  UINTN                                                          HandleIndex;\r
+  EFI_GUID                                                     **ProtocolGuidArray = NULL;\r
+  UINTN                                                          ArrayCount;\r
+  UINTN                                                          ProtocolIndex;\r
+  UINTN                                                          OpenInfoCount;\r
+  UINTN                                                          OpenInfoIndex;\r
+  EFI_OPEN_PROTOCOL_INFORMATION_ENTRY  *OpenInfo = NULL;\r
+  UINTN                                                          mHandleCount;\r
+  EFI_HANDLE                                                 *mHandleBuffer= NULL;\r
+\r
+  //\r
+  // Retrieve the list of all handles from the handle database\r
+  //\r
+  Status = gBS->LocateHandleBuffer (\r
+                  AllHandles,\r
+                  NULL,\r
+                  NULL,\r
+                  &mHandleCount,\r
+                  &mHandleBuffer\r
+                  );\r
+\r
+  for (HandleIndex = 0; HandleIndex < mHandleCount; HandleIndex++)\r
+  {\r
+    //\r
+    // Retrieve the list of all the protocols on each handle\r
+    //\r
+    Status = gBS->ProtocolsPerHandle (\r
+                    mHandleBuffer[HandleIndex],\r
+                    &ProtocolGuidArray,\r
+                    &ArrayCount\r
+                    );\r
+    if (!EFI_ERROR (Status))\r
+    {\r
+      for (ProtocolIndex = 0; ProtocolIndex < ArrayCount; ProtocolIndex++)\r
+      {\r
+        Status = gBS->OpenProtocolInformation (\r
+                        mHandleBuffer[HandleIndex],\r
+                        ProtocolGuidArray[ProtocolIndex],\r
+                        &OpenInfo,\r
+                        &OpenInfoCount\r
+                        );\r
+        if (!EFI_ERROR (Status))\r
+        {\r
+          for (OpenInfoIndex = 0; OpenInfoIndex < OpenInfoCount; OpenInfoIndex++)\r
+          {\r
+            if(OpenInfo[OpenInfoIndex].AgentHandle == Father)\r
+            {\r
+              if ((OpenInfo[OpenInfoIndex].Attributes & EFI_OPEN_PROTOCOL_BY_CHILD_CONTROLLER) == EFI_OPEN_PROTOCOL_BY_CHILD_CONTROLLER)\r
+              {\r
+                *Child = mHandleBuffer[HandleIndex];\r
+                 Status = EFI_SUCCESS;\r
+                 goto TryReturn;\r
+              }\r
+            }\r
+          }\r
+          Status = EFI_NOT_FOUND;\r
+        }\r
+      }\r
+      if(OpenInfo != NULL)\r
+      {\r
+        FreePool(OpenInfo);\r
+        OpenInfo = NULL;\r
+      }\r
+    }\r
+    FreePool (ProtocolGuidArray);\r
+    ProtocolGuidArray = NULL;\r
+  }\r
+TryReturn:\r
+  if(OpenInfo != NULL)\r
+  {\r
+    FreePool (OpenInfo);\r
+    OpenInfo = NULL;\r
+  }\r
+  if(ProtocolGuidArray != NULL)\r
+  {\r
+    FreePool(ProtocolGuidArray);\r
+    ProtocolGuidArray = NULL;\r
+  }\r
+  if(mHandleBuffer != NULL)\r
+  {\r
+    FreePool (mHandleBuffer);\r
+    mHandleBuffer = NULL;\r
+  }\r
+  return Status;\r
+}\r
+\r
+EFI_STATUS\r
+TGetDriverName(\r
+  EFI_HANDLE   Handle,\r
+  CHAR16         *Name\r
+)\r
+{\r
+  EFI_DRIVER_BINDING_PROTOCOL        *BindHandle = NULL;\r
+  EFI_STATUS                                        Status;\r
+  UINT32                                               Version;\r
+  UINT16                                               *Ptr;\r
+  Status = gBS->OpenProtocol(\r
+                  Handle,\r
+                  &gEfiDriverBindingProtocolGuid,\r
+                                   (VOID**)&BindHandle,\r
+                  NULL,\r
+                  NULL,\r
+                  EFI_OPEN_PROTOCOL_GET_PROTOCOL\r
+                  );\r
+\r
+  if (EFI_ERROR(Status))\r
+  {\r
+    return EFI_NOT_FOUND;\r
+  }\r
+\r
+  Version = BindHandle->Version;\r
+  Ptr = (UINT16*)&Version;\r
+  UnicodeSPrint(Name, 40, L"%d.%d.%d", Version >> 24 , (Version >>16)& 0x0f ,*(Ptr));\r
+  return EFI_SUCCESS;\r
+}\r
+\r
+EFI_STATUS\r
+TGetGOPDriverName(\r
+  CHAR16 *Name\r
+)\r
+{\r
+  UINTN                         HandleCount;\r
+  EFI_HANDLE                *Handles= NULL;\r
+  UINTN                         Index;\r
+  EFI_STATUS                Status;\r
+  EFI_HANDLE                Child = 0;\r
+\r
+  Status = gBS->LocateHandleBuffer(\r
+                             ByProtocol,\r
+                             &gEfiDriverBindingProtocolGuid,\r
+                             NULL,\r
+                             &HandleCount,\r
+                             &Handles\r
+                  );\r
+  for (Index = 0; Index < HandleCount ; Index++)\r
+  {\r
+    Status = TSearchChildHandle(Handles[Index], &Child);\r
+    if(!EFI_ERROR(Status))\r
+    {\r
+      Status = TJudgeHandleIsPCIDevice(Child, 0x02, 0x00);\r
+      if(!EFI_ERROR(Status))\r
+      {\r
+        return TGetDriverName(Handles[Index], Name);\r
+      }\r
+    }\r
+  }\r
+  return EFI_UNSUPPORTED;\r
+}\r
+\r
+EFI_STATUS\r
+TGetTouchFirmwareVersion(\r
+ )\r
+{\r
+ EFI_STATUS rc=EFI_SUCCESS;\r
+ UINTN      TouchVer = 0;\r
+ UINTN     Size = sizeof(UINTN);\r
+\r
+\r
+ CHAR16     Buffer[40];\r
+\r
+ rc = gRT->GetVariable(\r
+             L"TouchVer",\r
+             &gEfiVlv2VariableGuid,\r
+             NULL,\r
+             &Size,\r
+             &TouchVer\r
+             );\r
+ if(!EFI_ERROR(rc)){\r
+  UnicodeSPrint(Buffer, sizeof(Buffer), L"%02x.%02x", (TouchVer&0xFFFF)>>8,TouchVer&0xFF);\r
+  HiiSetString(mHiiHandle, STRING_TOKEN(STR_MISC_TOUCH_VERSION), Buffer, NULL);\r
+ }\r
+\r
+ return EFI_SUCCESS;\r
+}\r
+\r
+EFI_STATUS\r
+UpdatePlatformInformation (\r
+  )\r
+{\r
+  UINT32                   MicroCodeVersion;\r
+  CHAR16                   Buffer[40];\r
+  UINT8                    IgdVBIOSRevH;\r
+  UINT8                    IgdVBIOSRevL;\r
+  UINT16                   EDX;\r
+  EFI_IA32_REGISTER_SET    RegSet;\r
+  EFI_LEGACY_BIOS_PROTOCOL *LegacyBios = NULL;\r
+  EFI_STATUS               Status;\r
+  UINT8                    CpuFlavor=0;\r
+  EFI_PEI_HOB_POINTERS     GuidHob;\r
+  EFI_PLATFORM_INFO_HOB    *mPlatformInfo=NULL;\r
+  UINTN                    NumHandles;\r
+  EFI_HANDLE                        *HandleBuffer;\r
+  UINTN                             Index;\r
+  DXE_PCH_PLATFORM_POLICY_PROTOCOL  *PchPlatformPolicy;\r
+  UINTN                             PciD31F0RegBase;\r
+  UINT8                             count;\r
+  UINT8                             Data8;\r
+  UINT8                             Data8_1;\r
+\r
+  CHAR16                            Name[40];\r
+  UINT32                            MrcVersion;\r
+\r
+  UINT8                                        KscFwRevH =0;\r
+  UINT8                                        KscFwRevL =0;\r
+\r
+  //\r
+  // Get the HOB list.  If it is not present, then ASSERT.\r
+  //\r
+  GuidHob.Raw = GetHobList ();\r
+  if (GuidHob.Raw != NULL) {\r
+    if ((GuidHob.Raw = GetNextGuidHob (&gEfiPlatformInfoGuid, GuidHob.Raw)) != NULL) {\r
+      mPlatformInfo = GET_GUID_HOB_DATA (GuidHob.Guid);\r
+    }\r
+  }\r
+\r
+  //\r
+  //VBIOS version\r
+  //\r
+  Status = gBS->LocateProtocol(\r
+                  &gEfiLegacyBiosProtocolGuid,\r
+                  NULL,\r
+                  (VOID **)&LegacyBios\r
+                  );\r
+\r
+  RegSet.X.AX = 0x5f01;\r
+  Status = LegacyBios->Int86 (LegacyBios, 0x10, &RegSet);\r
+  ASSERT_EFI_ERROR(Status);\r
+\r
+  //\r
+  // simulate AMI int15 (ax=5f01) handler\r
+  // check NbInt15.asm in AMI code for asm edition\r
+  //\r
+  EDX = (UINT16)((RegSet.E.EBX >> 16) & 0xffff);\r
+  IgdVBIOSRevH = (UINT8)(((EDX & 0x0F00) >> 4) | (EDX & 0x000F));\r
+  IgdVBIOSRevL = (UINT8)(((RegSet.X.BX & 0x0F00) >> 4) | (RegSet.X.BX & 0x000F));\r
+\r
+  if (IgdVBIOSRevH==0 && IgdVBIOSRevL==0) {\r
+    HiiSetString(mHiiHandle, STRING_TOKEN(STR_CHIP_IGD_VBIOS_REV_VALUE), L"N/A", NULL);\r
+  } else {\r
+    UnicodeSPrint (Buffer, sizeof (Buffer), L"%02X%02X", IgdVBIOSRevH,IgdVBIOSRevL);\r
+    HiiSetString(mHiiHandle, STRING_TOKEN(STR_CHIP_IGD_VBIOS_REV_VALUE), Buffer, NULL);\r
+  }\r
+\r
+  Status = TGetGOPDriverName(Name);\r
+\r
+  if(!EFI_ERROR(Status))\r
+  {\r
+    HiiSetString(mHiiHandle, STRING_TOKEN(STR_MISC_GOP_VERSION), Name, NULL);\r
+  }\r
+\r
+  //\r
+  //CpuFlavor\r
+  //\r
+  //VLV\r
+  //VLV-DC Tablet        000\r
+  //VLV-QC Notebook      001\r
+  //VLV-QC Desktop       010\r
+  //\r
+  //CPU flavor\r
+  //\r
+  CpuFlavor = RShiftU64 (EfiReadMsr (MSR_IA32_PLATFORM_ID), 50) & 0x07;\r
+\r
+  switch(CpuFlavor){\r
+    case 0x0:\r
+        UnicodeSPrint (Buffer, sizeof (Buffer), L"%s (%01x)", L"VLV-DC Tablet", CpuFlavor);\r
+        break;\r
+    case 0x01:\r
+        UnicodeSPrint (Buffer, sizeof (Buffer), L"%s (%01x)", L"VLV-QC Notebook", CpuFlavor);\r
+        break;\r
+    case 0x02:\r
+        UnicodeSPrint (Buffer, sizeof (Buffer), L"%s (%01x)", L"VLV-QC Desktop", CpuFlavor);\r
+        break;\r
+    case 0x03:\r
+        UnicodeSPrint (Buffer, sizeof (Buffer), L"%s (%01x)", L"VLV-QC Notebook", CpuFlavor);\r
+        break;\r
+    default:\r
+        UnicodeSPrint (Buffer, sizeof (Buffer), L"%s (%01x)", L"Unknown CPU", CpuFlavor);\r
+        break;\r
+  }\r
+  HiiSetString(mHiiHandle,STRING_TOKEN(STR_MISC_CPU_FLAVOR_VALUE), Buffer, NULL);\r
+\r
+  if ( NULL != mPlatformInfo) {\r
+    //\r
+    // Board Id\r
+    //\r
+    UnicodeSPrint (Buffer, sizeof (Buffer), L"%x", mPlatformInfo->BoardId);\r
+    HiiSetString(mHiiHandle,STRING_TOKEN(STR_MISC_BOARD_ID_VALUE), Buffer, NULL);\r
+\r
+    //\r
+    // FAB ID\r
+    //\r
+    UnicodeSPrint (Buffer, sizeof (Buffer), L"%x", mPlatformInfo->BoardRev);\r
+    HiiSetString(mHiiHandle,STRING_TOKEN(STR_MISC_FAB_ID_VALUE), Buffer, NULL);\r
+  }\r
+\r
+  //\r
+  //Update MRC Version\r
+  //\r
+  MrcVersion = MmioRead32 (MmPciAddress (0, 0, 0, 0, 0xF0));\r
+  MrcVersion &= 0xffff;\r
+  Index = EfiValueToString (Buffer, MrcVersion/100, PREFIX_ZERO, 0);\r
+  StrCat (Buffer, L".");\r
+  EfiValueToString (Buffer + Index + 1, (MrcVersion%100)/10, PREFIX_ZERO, 0);\r
+  EfiValueToString (Buffer + Index + 2, (MrcVersion%100)%10, PREFIX_ZERO, 0);\r
+  HiiSetString(mHiiHandle,STRING_TOKEN(STR_MISC_MRC_VERSION_VALUE), Buffer, NULL);\r
+\r
+  //\r
+  //Update Soc Version\r
+  //\r
+\r
+  //\r
+  // Retrieve all instances of PCH Platform Policy protocol\r
+  //\r
+  Status = gBS->LocateHandleBuffer (\r
+                  ByProtocol,\r
+                  &gDxePchPlatformPolicyProtocolGuid,\r
+                  NULL,\r
+                  &NumHandles,\r
+                  &HandleBuffer\r
+                  );\r
+  if (!EFI_ERROR (Status)) {\r
+    //\r
+    // Find the matching PCH Policy protocol\r
+    //\r
+    for (Index = 0; Index < NumHandles; Index++) {\r
+      Status = gBS->HandleProtocol (\r
+                      HandleBuffer[Index],\r
+                      &gDxePchPlatformPolicyProtocolGuid,\r
+                      (VOID **) &PchPlatformPolicy\r
+                      );\r
+      if (!EFI_ERROR (Status)) {\r
+        PciD31F0RegBase = MmPciAddress (\r
+                            0,\r
+                            PchPlatformPolicy->BusNumber,\r
+                            PCI_DEVICE_NUMBER_PCH_LPC,\r
+                            PCI_FUNCTION_NUMBER_PCH_LPC,\r
+                            0\r
+                            );\r
+\r
+         Data8 = MmioRead8 (PciD31F0RegBase + R_PCH_LPC_RID_CC);\r
+         count = sizeof (SBRevisionTable) / sizeof (SBRevisionTable[0]);\r
+         for (Index = 0; Index < count; Index++) {\r
+           if(Data8 == SBRevisionTable[Index].RevId) {\r
+              UnicodeSPrint (Buffer, sizeof (Buffer), L"%02x %a", Data8, SBRevisionTable[Index].String);\r
+              HiiSetString(mHiiHandle,STRING_TOKEN(STR_MISC_SOC_VALUE), Buffer, NULL);\r
+             break;\r
+           }\r
+         }\r
+        break;\r
+      }\r
+    }\r
+  }\r
+\r
+  //\r
+  // Microcode Revision\r
+  //\r
+  EfiWriteMsr (EFI_MSR_IA32_BIOS_SIGN_ID, 0);\r
+  EfiCpuid (EFI_CPUID_VERSION_INFO, NULL);\r
+  MicroCodeVersion = (UINT32) RShiftU64 (EfiReadMsr (EFI_MSR_IA32_BIOS_SIGN_ID), 32);\r
+  UnicodeSPrint (Buffer, sizeof (Buffer), L"%x", MicroCodeVersion);\r
+  HiiSetString(mHiiHandle,STRING_TOKEN(STR_MISC_PROCESSOR_MICROCODE_VALUE), Buffer, NULL);\r
+\r
+\r
+  //\r
+  //Secure boot\r
+  //\r
+  Data8 = SystemConfiguration.SecureBoot;\r
+  UnicodeSPrint (Buffer, sizeof(Buffer), L"%x", Data8);\r
+  HiiSetString(mHiiHandle, STRING_TOKEN(STR_MISC_SECURE_BOOT), Buffer, NULL);\r
+\r
+  //\r
+  //Bootmode\r
+  //\r
+  BootMode = GetBootModeHob();\r
+  UnicodeSPrint (Buffer, sizeof(Buffer), L"%x", BootMode);\r
+  HiiSetString(mHiiHandle, STRING_TOKEN(STR_MISC_BOOT_MODE), Buffer, NULL);\r
+\r
+  //\r
+  //SpeedStep\r
+  //\r
+  Data8 = 1;\r
+  UnicodeSPrint (Buffer, sizeof(Buffer), L"%x", Data8);\r
+  HiiSetString(mHiiHandle, STRING_TOKEN(STR_MISC_SPEED_STEP), Buffer, NULL);\r
+\r
+  //\r
+  //CPU Turbo\r
+  //\r
+  Data8 = 2;\r
+  UnicodeSPrint (Buffer, sizeof(Buffer), L"%x", Data8);\r
+  HiiSetString(mHiiHandle, STRING_TOKEN(STR_MISC_CPU_TURBO), Buffer, NULL);\r
+\r
+  //\r
+  //CState\r
+  //\r
+  Data8 = 3;\r
+  UnicodeSPrint (Buffer, sizeof(Buffer), L"%x", Data8);\r
+  HiiSetString(mHiiHandle, STRING_TOKEN(STR_MISC_CSTATE), Buffer, NULL);\r
+\r
+  //\r
+  //GFX Turbo\r
+  //\r
+  Data8 = SystemConfiguration.IgdTurboEnabled;\r
+  UnicodeSPrint (Buffer, sizeof(Buffer), L"%x", Data8);\r
+  HiiSetString(mHiiHandle, STRING_TOKEN(STR_MISC_GFX_TURBO), Buffer, NULL);\r
+\r
+  Data8 = 0;\r
+  UnicodeSPrint (Buffer, sizeof(Buffer), L"%x", Data8);\r
+  HiiSetString(mHiiHandle, STRING_TOKEN(STR_MISC_S0IX_VALUE), Buffer, NULL);\r
+\r
+  //\r
+  //RC6\r
+  //\r
+  Data8 = 0; \r
+  UnicodeSPrint (Buffer, sizeof(Buffer), L"%x", Data8);\r
+  HiiSetString(mHiiHandle, STRING_TOKEN(STR_MISC_RC6_VALUE), Buffer, NULL);\r
+\r
+  //\r
+  // Punit Version\r
+  //\r
+  Data8 = 0;\r
+  UnicodeSPrint (Buffer, sizeof (Buffer), L"0x%x", Data8);\r
+  HiiSetString(mHiiHandle,STRING_TOKEN(STR_MISC_PUNIT_FW_VALUE), Buffer, NULL);\r
+\r
+  //\r
+  //  PMC Version\r
+  //\r
+  Data8 = (UINT8)((MmioRead32 (PMC_BASE_ADDRESS + R_PCH_PMC_PRSTS)>>16)&0x00FF);\r
+  Data8_1 = (UINT8)((MmioRead32 (PMC_BASE_ADDRESS + R_PCH_PMC_PRSTS)>>24)&0x00FF);\r
+  UnicodeSPrint (Buffer, sizeof (Buffer), L"0x%X_%X", Data8_1, Data8);\r
+  HiiSetString(mHiiHandle,STRING_TOKEN(STR_MISC_PMC_FW_VALUE), Buffer, NULL);\r
+\r
+  //\r
+  //PMIC Version\r
+  //\r
+  Status = ByteReadI2C(PMICI2cBus, PMICI2cAdd, PMICVendorOffset, 1, &Data8);\r
+  if(!EFI_ERROR(Status)){\r
+       Status = ByteReadI2C(PMICI2cBus, PMICI2cAdd, PMICRevOffset, 1, &Data8_1);\r
+       if(!EFI_ERROR(Status)){\r
+      UnicodeSPrint(Buffer, sizeof(Buffer), L"%02x.%02x", Data8, Data8_1);\r
+      HiiSetString(mHiiHandle, STRING_TOKEN(STR_MISC_PMIC_VERSION), Buffer, NULL);\r
+       }\r
+  }\r
+\r
+  TGetTouchFirmwareVersion();\r
+\r
+  return EFI_SUCCESS;\r
+}\r
+\r
+\r
+/**\r
+  Smbios OEM type 0x94 callback.\r
+\r
+  @param Event    Event whose notification function is being invoked.\r
+  @param Context  Pointer to the notification functions context, which is implementation dependent.\r
+\r
+  @retval None\r
+\r
+**/\r
+VOID\r
+AddSmbiosT0x94Callback (\r
+  IN EFI_EVENT  Event,\r
+  IN VOID       *Context\r
+  )\r
+{\r
+  EFI_STATUS            Status;\r
+  UINTN                 SECVerStrLen = 0;\r
+  UINTN                 uCodeVerStrLen = 0;\r
+  UINTN                 GOPStrLen = 0;\r
+  UINTN                 MRCVersionStrLen = 0;\r
+  UINTN                 PMCVersionStrLen = 0;\r
+  UINTN                 ULPMCVersionStrLen = 0;\r
+  UINTN                 PUNITVersionStrLen = 0;\r
+  UINTN                 SOCVersionStrLen = 0;\r
+  UINTN                 BOARDVersionStrLen = 0;\r
+  UINTN                 FABVersionStrLen = 0;\r
+  UINTN                 CPUFLAVORStrLen = 0;\r
+  UINTN                 BIOSVersionStrLen = 0;\r
+  UINTN                 PMICVersionStrLen = 0;\r
+  UINTN                 TOUCHVersionStrLen = 0;\r
+  UINTN                 SecureBootModeLen = 0;\r
+  UINTN                 BootModeLen = 0;\r
+  UINTN                 SpeedStepModeLen = 0;\r
+  UINTN                 MaxCStateLen = 0;\r
+  UINTN                 CpuTurboLen = 0;\r
+  UINTN                 GfxTurboLen = 0;\r
+  UINTN                 IdleReserveLen = 0;\r
+  UINTN                 RC6Len = 0;\r
+\r
+  SMBIOS_TABLE_TYPE94    *SmbiosRecord;\r
+  EFI_SMBIOS_HANDLE     SmbiosHandle;\r
+  EFI_MISC_OEM_TYPE_0x94  *ForType94InputData;\r
+  CHAR16                *SECVer;\r
+  CHAR16                *uCodeVer;\r
+  CHAR16                *GOPVer;\r
+  CHAR16                *MrcVer;\r
+  CHAR16                *PmcVer;\r
+  CHAR16                *UlpmcVer;\r
+  CHAR16                *PunitVer;\r
+  CHAR16                *SocVer;\r
+  CHAR16                *BoardVer;\r
+  CHAR16                *FabVer;\r
+  CHAR16                *CpuFlavor;\r
+  CHAR16                *BiosVer;\r
+  CHAR16                *PmicVer;\r
+  CHAR16                *TouchVer = L"15.16";\r
+  CHAR16                *SecureBootMode;\r
+  CHAR16                *BootMode;\r
+  CHAR16                *SpeedStepMode;\r
+  CHAR16                *MaxCState;\r
+  CHAR16                *CpuTurbo;\r
+  CHAR16                *GfxTurbo;\r
+  CHAR16                *IdleReserve;\r
+  CHAR16                *RC6;\r
+\r
+  UINTN                 RecordLen = 0;\r
+  UINTN                 StrIdx = 0;\r
+\r
+\r
+  STRING_REF            TokenToGet;\r
+  CHAR8                 *OptionalStrStart;\r
+  EFI_SMBIOS_PROTOCOL               *SmbiosProtocol;\r
+\r
+  ForType94InputData        = (EFI_MISC_OEM_TYPE_0x94 *)Context;\r
+\r
+  DEBUG ((EFI_D_INFO, "Executing SMBIOS T0x94 callback.\n"));\r
+\r
+  gBS->CloseEvent (Event);    // Unload this event.\r
+\r
+  //\r
+  // First check for invalid parameters.\r
+  //\r
+  if (Context == NULL) {\r
+    return;\r
+  }\r
+\r
+  UpdatePlatformInformation();\r
+\r
+  Status = gBS->LocateProtocol (\r
+                  &gEfiSmbiosProtocolGuid,\r
+                  NULL,\r
+                  (VOID **) &SmbiosProtocol\r
+                  );\r
+  ASSERT_EFI_ERROR (Status);\r
+\r
+  TokenToGet = STRING_TOKEN (STR_MISC_SEC_VERSION);\r
+  SECVer = SmbiosMiscGetString (TokenToGet);\r
+  SECVerStrLen = StrLen(SECVer);\r
+  if (SECVerStrLen > SMBIOS_STRING_MAX_LENGTH) {\r
+    return;\r
+  }\r
+\r
+  TokenToGet = STRING_TOKEN (STR_MISC_UCODE_VERSION);\r
+  uCodeVer = SmbiosMiscGetString (TokenToGet);\r
+  uCodeVerStrLen = StrLen(uCodeVer);\r
+  if (uCodeVerStrLen > SMBIOS_STRING_MAX_LENGTH) {\r
+    return;\r
+  }\r
+\r
+  TokenToGet = STRING_TOKEN (STR_MISC_GOP_VERSION);\r
+  GOPVer = SmbiosMiscGetString (TokenToGet);\r
+  GOPStrLen = StrLen(GOPVer);\r
+  if (GOPStrLen > SMBIOS_STRING_MAX_LENGTH) {\r
+    return;\r
+  }\r
+\r
+  TokenToGet = STRING_TOKEN (STR_MISC_MRC_VERSION_VALUE);\r
+  MrcVer = SmbiosMiscGetString (TokenToGet);\r
+  MRCVersionStrLen = StrLen(MrcVer);\r
+  if (MRCVersionStrLen > SMBIOS_STRING_MAX_LENGTH) {\r
+    return;\r
+  }\r
+\r
+  TokenToGet = STRING_TOKEN (STR_MISC_PMC_FW_VALUE);\r
+  PmcVer = SmbiosMiscGetString (TokenToGet);\r
+  PMCVersionStrLen = StrLen(PmcVer);\r
+  if (PMCVersionStrLen > SMBIOS_STRING_MAX_LENGTH) {\r
+    return;\r
+  }\r
+\r
+  TokenToGet = STRING_TOKEN (STR_MISC_ULPMC_FW_VALUE);\r
+  UlpmcVer = SmbiosMiscGetString (TokenToGet);\r
+  ULPMCVersionStrLen = StrLen(UlpmcVer);\r
+  if (ULPMCVersionStrLen > SMBIOS_STRING_MAX_LENGTH) {\r
+    return;\r
+  }\r
+\r
+  TokenToGet = STRING_TOKEN (STR_MISC_PUNIT_FW_VALUE);\r
+  PunitVer = SmbiosMiscGetString (TokenToGet);\r
+  PUNITVersionStrLen = StrLen(PunitVer);\r
+  if (PUNITVersionStrLen > SMBIOS_STRING_MAX_LENGTH) {\r
+    return;\r
+  }\r
+\r
+  TokenToGet = STRING_TOKEN (STR_MISC_SOC_VALUE);\r
+  SocVer = SmbiosMiscGetString (TokenToGet);\r
+  SOCVersionStrLen = StrLen(SocVer);\r
+  if (SOCVersionStrLen > SMBIOS_STRING_MAX_LENGTH) {\r
+    return;\r
+  }\r
+\r
+  TokenToGet = STRING_TOKEN (STR_MISC_BOARD_ID_VALUE);\r
+  BoardVer = SmbiosMiscGetString (TokenToGet);\r
+  BOARDVersionStrLen = StrLen(BoardVer);\r
+  if (BOARDVersionStrLen > SMBIOS_STRING_MAX_LENGTH) {\r
+    return;\r
+  }\r
+\r
+  TokenToGet = STRING_TOKEN (STR_MISC_FAB_ID_VALUE);\r
+  FabVer = SmbiosMiscGetString (TokenToGet);\r
+  FABVersionStrLen = StrLen(FabVer);\r
+  if (FABVersionStrLen > SMBIOS_STRING_MAX_LENGTH) {\r
+    return;\r
+  }\r
+\r
+  TokenToGet = STRING_TOKEN (STR_MISC_CPU_FLAVOR_VALUE);\r
+  CpuFlavor = SmbiosMiscGetString (TokenToGet);\r
+  CPUFLAVORStrLen = StrLen(CpuFlavor);\r
+  if (CPUFLAVORStrLen > SMBIOS_STRING_MAX_LENGTH) {\r
+    return;\r
+  }\r
+\r
+  TokenToGet = STRING_TOKEN (STR_MISC_BIOS_VERSION);\r
+  BiosVer = SmbiosMiscGetString (TokenToGet);\r
+  BIOSVersionStrLen = StrLen(BiosVer);\r
+  if (BIOSVersionStrLen > SMBIOS_STRING_MAX_LENGTH) {\r
+    return;\r
+  }\r
+\r
+  TokenToGet = STRING_TOKEN (STR_MISC_PMIC_VERSION);\r
+  PmicVer = SmbiosMiscGetString (TokenToGet);\r
+  PMICVersionStrLen = StrLen(PmicVer);\r
+  if (PMICVersionStrLen > SMBIOS_STRING_MAX_LENGTH) {\r
+    return;\r
+  }\r
+\r
+  TokenToGet = STRING_TOKEN (STR_MISC_TOUCH_VERSION);\r
+  TouchVer = SmbiosMiscGetString (TokenToGet);\r
+  TOUCHVersionStrLen = StrLen(TouchVer);\r
+  if (TOUCHVersionStrLen > SMBIOS_STRING_MAX_LENGTH) {\r
+    return;\r
+  }\r
+\r
+  TokenToGet = STRING_TOKEN (STR_MISC_SECURE_BOOT);\r
+  SecureBootMode = SmbiosMiscGetString(TokenToGet);\r
+  SecureBootModeLen = StrLen(SecureBootMode);\r
+  if (SecureBootModeLen > SMBIOS_STRING_MAX_LENGTH) {\r
+       return;\r
+  }\r
+\r
+  TokenToGet = STRING_TOKEN (STR_MISC_BOOT_MODE);\r
+  BootMode = SmbiosMiscGetString(TokenToGet);\r
+  BootModeLen = StrLen(BootMode);\r
+  if (BootModeLen > SMBIOS_STRING_MAX_LENGTH) {\r
+       return;\r
+  }\r
+\r
+  TokenToGet = STRING_TOKEN (STR_MISC_SPEED_STEP);\r
+  SpeedStepMode = SmbiosMiscGetString(TokenToGet);\r
+  SpeedStepModeLen = StrLen(SpeedStepMode);\r
+  if (SpeedStepModeLen > SMBIOS_STRING_MAX_LENGTH) {\r
+       return;\r
+  }\r
+\r
+  TokenToGet = STRING_TOKEN (STR_MISC_CPU_TURBO);\r
+  CpuTurbo = SmbiosMiscGetString(TokenToGet);\r
+  CpuTurboLen = StrLen(CpuTurbo);\r
+  if (CpuTurboLen > SMBIOS_STRING_MAX_LENGTH) {\r
+       return;\r
+  }\r
+\r
+  TokenToGet = STRING_TOKEN (STR_MISC_CSTATE);\r
+  MaxCState = SmbiosMiscGetString(TokenToGet);\r
+  MaxCStateLen = StrLen(MaxCState);\r
+  if (MaxCStateLen > SMBIOS_STRING_MAX_LENGTH) {\r
+       return;\r
+  }\r
+\r
+  TokenToGet = STRING_TOKEN (STR_MISC_GFX_TURBO);\r
+  GfxTurbo = SmbiosMiscGetString(TokenToGet);\r
+  GfxTurboLen = StrLen(GfxTurbo);\r
+  if (GfxTurboLen > SMBIOS_STRING_MAX_LENGTH) {\r
+       return;\r
+  }\r
+\r
+  TokenToGet = STRING_TOKEN (STR_MISC_S0IX_VALUE);\r
+  IdleReserve = SmbiosMiscGetString(TokenToGet);\r
+  IdleReserveLen = StrLen(IdleReserve);\r
+  if (S0ixLen > SMBIOS_STRING_MAX_LENGTH) {\r
+    return;\r
+  }\r
+\r
+  TokenToGet = STRING_TOKEN (STR_MISC_RC6_VALUE);\r
+  RC6 = SmbiosMiscGetString(TokenToGet);\r
+  RC6Len = StrLen(RC6);\r
+  if (RC6Len > SMBIOS_STRING_MAX_LENGTH) {\r
+    return;\r
+  }\r
+\r
+  RecordLen = sizeof (SMBIOS_TABLE_TYPE94) + SECVerStrLen + 1 + uCodeVerStrLen + 1 + GOPStrLen + 1 + PMCVersionStrLen + 1 + \\r
+                      TOUCHVersionStrLen + 1 + PMICVersionStrLen + 1 + BIOSVersionStrLen + 1 + CPUFLAVORStrLen + 1 + \\r
+                      BOARDVersionStrLen + 1 + FABVersionStrLen + 1 + PUNITVersionStrLen+ 1 + ULPMCVersionStrLen + 1 + \\r
+                      MRCVersionStrLen + 1 + SOCVersionStrLen + 1 + SecureBootModeLen + 1 + BootModeLen + 1 + \\r
+                      SpeedStepModeLen + 1 + CpuTurboLen + 1 + MaxCStateLen + 1 + GfxTurboLen + 1 + + RC6Len + 1 + 1;\r
+\r
+  SmbiosRecord = AllocatePool(RecordLen);\r
+\r
+  ZeroMem(SmbiosRecord, RecordLen);\r
+\r
+  SmbiosRecord->Hdr.Type = EFI_SMBIOS_TYPE_MISC_VERSION_INFO;\r
+  SmbiosRecord->Hdr.Length = sizeof (SMBIOS_TABLE_TYPE94);\r
+\r
+  //\r
+  // Make handle chosen by smbios protocol.add automatically.\r
+  //\r
+  SmbiosRecord->Hdr.Handle = 0;\r
+\r
+  SmbiosRecord->GopVersion = 1;\r
+\r
+  SmbiosRecord->SECVersion = 2;\r
+\r
+  SmbiosRecord->MRCVersion = 3;\r
+\r
+  SmbiosRecord->uCodeVersion = 4;\r
+\r
+  SmbiosRecord->PUnitVersion = 5;\r
+\r
+  SmbiosRecord->PMCVersion = 6;\r
+\r
+  SmbiosRecord->ULPMCVersion = 7;\r
+\r
+  SmbiosRecord->SoCVersion = 8;\r
+\r
+  SmbiosRecord->BoardVersion = 9;\r
+\r
+  SmbiosRecord->FabVersion = 10;\r
+\r
+  SmbiosRecord->CPUFlavor = 11;\r
+\r
+  SmbiosRecord->BiosVersion = 12;\r
+\r
+  SmbiosRecord->PmicVersion = 13;\r
+\r
+  SmbiosRecord->TouchVersion = 14;\r
+\r
+  SmbiosRecord->SecureBoot = 15;\r
+\r
+  SmbiosRecord->BootMode = 16;\r
+\r
+  SmbiosRecord->SpeedStepMode= 17;\r
+\r
+  SmbiosRecord->CPUTurboMode = 18;\r
+\r
+  SmbiosRecord->MaxCState = 19;\r
+\r
+  SmbiosRecord->GfxTurbo = 20;\r
+  SmbiosRecord->IdleReserve = 21;\r
+\r
+  SmbiosRecord->RC6 = 22;\r
+\r
+\r
+  OptionalStrStart = (CHAR8 *)(SmbiosRecord + 1);\r
+  UnicodeStrToAsciiStr(GOPVer, OptionalStrStart);\r
+  StrIdx +=  GOPStrLen + 1;\r
+\r
+  UnicodeStrToAsciiStr(SECVer, OptionalStrStart + StrIdx);\r
+  StrIdx +=  SECVerStrLen + 1;\r
+\r
+  UnicodeStrToAsciiStr(MrcVer, OptionalStrStart + StrIdx);\r
+  StrIdx +=  MRCVersionStrLen + 1;\r
+\r
+  UnicodeStrToAsciiStr(uCodeVer, OptionalStrStart + StrIdx);\r
+  StrIdx +=  uCodeVerStrLen + 1;\r
+\r
+  UnicodeStrToAsciiStr(PunitVer, OptionalStrStart + StrIdx);\r
+  StrIdx +=  PUNITVersionStrLen + 1;\r
+\r
+  UnicodeStrToAsciiStr(PmcVer, OptionalStrStart + StrIdx);\r
+  StrIdx +=  PMCVersionStrLen + 1;\r
+\r
+  UnicodeStrToAsciiStr(UlpmcVer, OptionalStrStart + StrIdx);\r
+  StrIdx +=  ULPMCVersionStrLen + 1;\r
+\r
+\r
+  UnicodeStrToAsciiStr(SocVer, OptionalStrStart + StrIdx);\r
+  StrIdx +=  SOCVersionStrLen +1;\r
+\r
+  UnicodeStrToAsciiStr(BoardVer, OptionalStrStart + StrIdx);\r
+  StrIdx +=  BOARDVersionStrLen + 1;\r
+\r
+  UnicodeStrToAsciiStr(FabVer, OptionalStrStart + StrIdx);\r
+  StrIdx +=  FABVersionStrLen + 1;\r
+\r
+  UnicodeStrToAsciiStr(CpuFlavor, OptionalStrStart + StrIdx);\r
+  StrIdx +=  CPUFLAVORStrLen + 1;\r
+\r
+  UnicodeStrToAsciiStr(BiosVer, OptionalStrStart + StrIdx);\r
+  StrIdx +=  BIOSVersionStrLen + 1;\r
+\r
+  UnicodeStrToAsciiStr(PmicVer, OptionalStrStart + StrIdx);\r
+  StrIdx +=  PMICVersionStrLen + 1;\r
+\r
+  UnicodeStrToAsciiStr(TouchVer, OptionalStrStart + StrIdx);\r
+  StrIdx +=  TOUCHVersionStrLen + 1;\r
+\r
+  UnicodeStrToAsciiStr(SecureBootMode, OptionalStrStart + StrIdx);\r
+  StrIdx +=  SecureBootModeLen + 1;\r
+\r
+  UnicodeStrToAsciiStr(BootMode, OptionalStrStart + StrIdx);\r
+  StrIdx +=  BootModeLen + 1;\r
+\r
+  UnicodeStrToAsciiStr(SpeedStepMode, OptionalStrStart + StrIdx);\r
+  StrIdx +=  SpeedStepModeLen + 1;\r
+\r
+  UnicodeStrToAsciiStr(CpuTurbo, OptionalStrStart + StrIdx);\r
+  StrIdx +=  CpuTurboLen + 1;\r
+\r
+  UnicodeStrToAsciiStr(MaxCState, OptionalStrStart + StrIdx);\r
+  StrIdx +=  MaxCStateLen + 1;\r
+\r
+  UnicodeStrToAsciiStr(GfxTurbo, OptionalStrStart + StrIdx);\r
+  StrIdx +=  GfxTurboLen + 1;\r
+\r
+  UnicodeStrToAsciiStr(IdleReserve, OptionalStrStart + StrIdx);\r
+  StrIdx +=  S0ixLen + 1;\r
+\r
+  UnicodeStrToAsciiStr(RC6, OptionalStrStart + StrIdx);\r
+  StrIdx +=  RC6Len + 1;\r
+\r
+  //\r
+  // Now we have got the full smbios record, call smbios protocol to add this record.\r
+  //\r
+  SmbiosHandle = SMBIOS_HANDLE_PI_RESERVED;\r
+  Status = SmbiosProtocol-> Add (\r
+                              SmbiosProtocol,\r
+                              NULL,\r
+                              &SmbiosHandle,\r
+                              (EFI_SMBIOS_TABLE_HEADER *) SmbiosRecord\r
+                              );\r
+\r
+  FreePool(SmbiosRecord);\r
+  return;\r
+}\r
+\r
+/**\r
+  This function makes boot time changes to the contents of the\r
+  MiscOemType0x94 (Type 0x94).\r
+\r
+  @param  RecordData                 Pointer to copy of RecordData from the Data Table.\r
+\r
+  @retval EFI_SUCCESS                All parameters were valid.\r
+  @retval EFI_UNSUPPORTED            Unexpected RecordType value.\r
+  @retval EFI_INVALID_PARAMETER      Invalid parameter was found.\r
+\r
+**/\r
+MISC_SMBIOS_TABLE_FUNCTION(MiscOemType0x94)\r
+{\r
+  EFI_STATUS                    Status;\r
+  EFI_EVENT                     AddSmbiosT0x94CallbackEvent;\r
+\r
+  Status = EfiCreateEventReadyToBootEx (\r
+             TPL_CALLBACK,\r
+             AddSmbiosT0x94Callback,\r
+             RecordData,\r
+             &AddSmbiosT0x94CallbackEvent\r
+             );\r
+\r
+  ASSERT_EFI_ERROR (Status);\r
+  return Status;\r
+\r
+}\r

diff --git a/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscOnboardDevice.uni b/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscOnboardDevice.uni
new file mode 100644 (file)
index 0000000..bc06bad
Binary files /dev/null and b/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscOnboardDevice.uni differ

diff --git a/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscOnboardDeviceData.c b/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscOnboardDeviceData.c
new file mode 100644 (file)
index 0000000..732e3d8
--- /dev/null
+++ b/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscOnboardDeviceData.c
@@ -0,0 +1,53 @@
+/** @file\r
+\r
+Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+\r
+Module Name:\r
+\r
+  MiscOnboardDeviceData.c\r
+\r
+Abstract:\r
+\r
+  Static data of Onboard device information .\r
+  The onboard device information is Misc. subclass type 8 and SMBIOS type 10.\r
+\r
+\r
+**/\r
+\r
+\r
+#include "CommonHeader.h"\r
+\r
+#include "MiscSubclassDriver.h"\r
+\r
+//\r
+// Static (possibly build generated) Bios Vendor data.\r
+//\r
+MISC_SMBIOS_TABLE_DATA(EFI_MISC_ONBOARD_DEVICE_DATA, MiscOnboardDeviceVideo) = {\r
+  STRING_TOKEN(STR_MISC_ONBOARD_DEVICE_VIDEO),  // OnBoardDeviceDescription\r
+  {                             // OnBoardDeviceStatus\r
+    EfiOnBoardDeviceTypeVideo,  // DeviceType\r
+    1,                          // DeviceEnabled\r
+    0                           // Reserved\r
+  },\r
+  0                             // OnBoardDevicePath\r
+};\r
+MISC_SMBIOS_TABLE_DATA(EFI_MISC_ONBOARD_DEVICE_DATA, MiscOnboardDeviceAudio) = {\r
+  STRING_TOKEN(STR_MISC_ONBOARD_DEVICE_AUDIO),    // OnBoardDeviceDescription\r
+  {                                 // OnBoardDeviceStatus\r
+    EfiOnBoardDeviceTypeSound,      // DeviceType\r
+    1,                              // DeviceEnabled\r
+    0                               // Reserved\r
+  },\r
+  0                                 // OnBoardDevicePath\r
+};\r
+\r

diff --git a/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscOnboardDeviceFunction.c b/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscOnboardDeviceFunction.c
new file mode 100644 (file)
index 0000000..ecf6e6e
--- /dev/null
+++ b/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscOnboardDeviceFunction.c
@@ -0,0 +1,140 @@
+/** @file\r
+\r
+Copyright (c) 1999  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+\r
+Module Name:\r
+\r
+  MiscOnboardDeviceFunction.c\r
+\r
+Abstract:\r
+\r
+  Create the device path for the Onboard device.\r
+  The Onboard device information is Misc. subclass type 8 and SMBIOS type 10.\r
+\r
+\r
+**/\r
+\r
+\r
+#include "CommonHeader.h"\r
+\r
+#include "MiscSubclassDriver.h"\r
+\r
+\r
+\r
+/**\r
+  This is a macro defined function, in fact, the function is\r
+  MiscOnboardDeviceFunction (RecordType, RecordLen, RecordData, LogRecordData)\r
+  This function makes boot time changes to the contents of the\r
+  MiscOnboardDevice structure.\r
+\r
+  @param  MiscOnboardDevice      The string which is used to create the function\r
+  The Arguments in fact:\r
+  @param  RecordType             Type of record to be processed from the Data\r
+                                 Table. mMiscSubclassDataTable[].RecordType\r
+  @param  RecordLen              Size of static RecordData from the Data Table.\r
+                                 mMiscSubclassDataTable[].RecordLen\r
+  @param  RecordData             Pointer to RecordData, which will be written to\r
+                                 the Data Hub\r
+  @param  LogRecordData          TRUE to log RecordData to Data Hub. FALSE when\r
+                                 there is no more data to log.\r
+\r
+  @retval EFI_SUCCESS            *RecordData and *LogRecordData have been set.\r
+  @retval EFI_UNSUPPORTED        Unexpected RecordType value.\r
+  @retval EFI_INVALID_PARAMETER  One of the following parameter conditions was\r
+                                 true: RecordLen was zero. RecordData was NULL.\r
+                                 LogRecordData was NULL.\r
+\r
+**/\r
+MISC_SMBIOS_TABLE_FUNCTION (\r
+  MiscOnboardDevice\r
+  )\r
+{\r
+  CHAR8                         *OptionalStrStart;\r
+  UINT8                         StatusAndType;\r
+  UINTN                         DescriptionStrLen;\r
+  EFI_STRING                    DeviceDescription;\r
+  STRING_REF                    TokenToGet;\r
+  EFI_STATUS                    Status;\r
+  EFI_SMBIOS_HANDLE             SmbiosHandle;\r
+  SMBIOS_TABLE_TYPE10           *SmbiosRecord;\r
+  EFI_MISC_ONBOARD_DEVICE       *ForType10InputData;\r
+\r
+  ForType10InputData = (EFI_MISC_ONBOARD_DEVICE *)RecordData;\r
+\r
+  //\r
+  // First check for invalid parameters.\r
+  //\r
+  if (RecordData == NULL) {\r
+    return EFI_INVALID_PARAMETER;\r
+  }\r
+\r
+  TokenToGet = 0;\r
+  switch (ForType10InputData->OnBoardDeviceDescription) {\r
+    case STR_MISC_ONBOARD_DEVICE_VIDEO:\r
+      TokenToGet = STRING_TOKEN (STR_MISC_ONBOARD_DEVICE_VIDEO);\r
+      break;\r
+    case STR_MISC_ONBOARD_DEVICE_AUDIO:\r
+      TokenToGet = STRING_TOKEN (STR_MISC_ONBOARD_DEVICE_AUDIO);\r
+      break;\r
+       default:\r
+       break;\r
+  }\r
+\r
+  DeviceDescription = SmbiosMiscGetString (TokenToGet);\r
+  DescriptionStrLen = StrLen(DeviceDescription);\r
+  if (DescriptionStrLen > SMBIOS_STRING_MAX_LENGTH) {\r
+    return EFI_UNSUPPORTED;\r
+  }\r
+\r
+  //\r
+  // Two zeros following the last string.\r
+  //\r
+  SmbiosRecord = AllocatePool(sizeof (SMBIOS_TABLE_TYPE10) + DescriptionStrLen + 1 + 1);\r
+  ZeroMem(SmbiosRecord, sizeof (SMBIOS_TABLE_TYPE10) + DescriptionStrLen + 1 + 1);\r
+\r
+  SmbiosRecord->Hdr.Type = EFI_SMBIOS_TYPE_ONBOARD_DEVICE_INFORMATION;\r
+  SmbiosRecord->Hdr.Length = sizeof (SMBIOS_TABLE_TYPE10);\r
+\r
+  //\r
+  // Make handle chosen by smbios protocol.add automatically.\r
+  //\r
+  SmbiosRecord->Hdr.Handle = 0;\r
+\r
+  //\r
+  // Status & Type: Bit 7 Devicen Status, Bits 6:0 Type of Device\r
+  //\r
+  StatusAndType = (UINT8) ForType10InputData->OnBoardDeviceStatus.DeviceType;\r
+  if (ForType10InputData->OnBoardDeviceStatus.DeviceEnabled != 0) {\r
+    StatusAndType |= 0x80;\r
+  } else {\r
+    StatusAndType &= 0x7F;\r
+  }\r
+\r
+  SmbiosRecord->Device[0].DeviceType = StatusAndType;\r
+  SmbiosRecord->Device[0].DescriptionString = 1;\r
+  OptionalStrStart = (CHAR8 *)(SmbiosRecord + 1);\r
+  UnicodeStrToAsciiStr(DeviceDescription, OptionalStrStart);\r
+\r
+  //\r
+  // Now we have got the full smbios record, call smbios protocol to add this record.\r
+  //\r
+  SmbiosHandle = SMBIOS_HANDLE_PI_RESERVED;\r
+  Status = Smbios-> Add(\r
+                      Smbios,\r
+                      NULL,\r
+                      &SmbiosHandle,\r
+                      (EFI_SMBIOS_TABLE_HEADER *) SmbiosRecord\r
+                      );\r
+  FreePool(SmbiosRecord);\r
+  return Status;\r
+}\r

diff --git a/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscPhysicalArray.uni b/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscPhysicalArray.uni
new file mode 100644 (file)
index 0000000..510ec40
Binary files /dev/null and b/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscPhysicalArray.uni differ

diff --git a/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscPhysicalArrayData.c b/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscPhysicalArrayData.c
new file mode 100644 (file)
index 0000000..43095e8
--- /dev/null
+++ b/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscPhysicalArrayData.c
@@ -0,0 +1,43 @@
+/*++\r
+\r
+Copyright (c) 2006  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+\r
+Module Name:\r
+\r
+  MiscPhysicalArrayData.c\r
+\r
+Abstract:\r
+\r
+  BIOS Physical Array static data.\r
+  SMBIOS type 16.\r
+\r
+--*/\r
+\r
+\r
+#include "CommonHeader.h"\r
+\r
+#include "MiscSubclassDriver.h"\r
+\r
+\r
+\r
+//\r
+// Static (possibly build generated) Physical Memory Array Dat.\r
+//\r
+MISC_SMBIOS_TABLE_DATA(EFI_MEMORY_ARRAY_LOCATION_DATA, MiscPhysicalMemoryArray) =\r
+{\r
+       EfiMemoryArrayLocationSystemBoard,                                              // Memory location\r
+       EfiMemoryArrayUseSystemMemory,                                              // Memory array use\r
+       EfiMemoryErrorCorrectionNone,                                               // Memory error correction\r
+       0,                                                      // Maximum Memory Capacity\r
+       0x01                                                                        // Number of Devices\r
+};\r

diff --git a/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscPhysicalArrayFunction.c b/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscPhysicalArrayFunction.c
new file mode 100644 (file)
index 0000000..8f035cc
--- /dev/null
+++ b/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscPhysicalArrayFunction.c
@@ -0,0 +1,106 @@
+/*++\r
+\r
+Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+\r
+Module Name:\r
+\r
+  MiscPhysicalArrayFunction.c\r
+\r
+Abstract:\r
+\r
+  BIOS system Physical Array boot time changes.\r
+  SMBIOS type 16.\r
+\r
+--*/\r
+\r
+\r
+#include "CommonHeader.h"\r
+#include "MiscSubclassDriver.h"\r
+\r
+\r
+\r
+/**\r
+  This function makes boot time changes to the contents of the\r
+  MiscPhysicalArrayFunction (Type 16).\r
+\r
+  @param  RecordData                 Pointer to copy of RecordData from the Data Table.\r
+\r
+  @retval EFI_SUCCESS                All parameters were valid.\r
+  @retval EFI_UNSUPPORTED            Unexpected RecordType value.\r
+  @retval EFI_INVALID_PARAMETER      Invalid parameter was found.\r
+\r
+**/\r
+\r
+MISC_SMBIOS_TABLE_FUNCTION(MiscPhysicalMemoryArray)\r
+{\r
+    EFI_STATUS                      Status;\r
+    EFI_SMBIOS_HANDLE               SmbiosHandle;\r
+    SMBIOS_TABLE_TYPE16             *SmbiosRecord;\r
+    EFI_MEMORY_ARRAY_LOCATION_DATA  *ForType16InputData;\r
+    UINT32                           TopOfMemory = 8 * 1024 * 1024;\r
+\r
+    //\r
+    // First check for invalid parameters.\r
+    //\r
+    if (RecordData == NULL) {\r
+    return EFI_INVALID_PARAMETER;\r
+    }\r
+\r
+    ForType16InputData = (EFI_MEMORY_ARRAY_LOCATION_DATA *)RecordData;\r
+\r
+    //\r
+    // Two zeros following the last string.\r
+    //\r
+    SmbiosRecord = AllocatePool(sizeof (SMBIOS_TABLE_TYPE16)  + 1);\r
+    ZeroMem(SmbiosRecord, sizeof (SMBIOS_TABLE_TYPE16)  + 1);\r
+\r
+    SmbiosRecord->Hdr.Type = EFI_SMBIOS_TYPE_PHYSICAL_MEMORY_ARRAY;\r
+    SmbiosRecord->Hdr.Length = sizeof (SMBIOS_TABLE_TYPE16);\r
+\r
+    //\r
+    // Make handle chosen by smbios protocol.add automatically.\r
+    //\r
+    SmbiosRecord->Hdr.Handle = 0;\r
+\r
+    //\r
+    // ReleaseDate will be the 3rd optional string following the formatted structure.\r
+    //\r
+    SmbiosRecord->Location = *(UINT8 *) &ForType16InputData ->MemoryArrayLocation;\r
+    SmbiosRecord->Use = *(UINT8 *) &ForType16InputData ->MemoryArrayUse;\r
+    SmbiosRecord->MemoryErrorCorrection = *(UINT8 *) &ForType16InputData->MemoryErrorCorrection;\r
+\r
+    //\r
+    // System does not provide the error information structure\r
+    //\r
+    SmbiosRecord->MemoryErrorInformationHandle = 0xFFFE;\r
+\r
+    //\r
+    // Maximum memory capacity\r
+    //\r
+    SmbiosRecord-> MaximumCapacity = TopOfMemory;\r
+    SmbiosRecord-> NumberOfMemoryDevices= 0x02;\r
+\r
+    //\r
+    // Now we have got the full smbios record, call smbios protocol to add this record.\r
+    //\r
+    SmbiosHandle = SMBIOS_HANDLE_PI_RESERVED;\r
+    Status = Smbios-> Add(\r
+                        Smbios,\r
+                        NULL,\r
+                       &SmbiosHandle,\r
+                       (EFI_SMBIOS_TABLE_HEADER *) SmbiosRecord\r
+                       );\r
+    FreePool(SmbiosRecord);\r
+    return Status;\r
+\r
+}\r

diff --git a/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscPortInternalConnectorDesignator.uni b/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscPortInternalConnectorDesignator.uni
new file mode 100644 (file)
index 0000000..c0e4b55
Binary files /dev/null and b/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscPortInternalConnectorDesignator.uni differ

diff --git a/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscPortInternalConnectorDesignatorData.c b/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscPortInternalConnectorDesignatorData.c
new file mode 100644 (file)
index 0000000..2bc4993
--- /dev/null
+++ b/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscPortInternalConnectorDesignatorData.c
@@ -0,0 +1,61 @@
+/** @file\r
+\r
+Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+\r
+Module Name:\r
+\r
+  MiscPortInternalConnectorDesignatorData.c\r
+\r
+Abstract:\r
+\r
+  Static data of Port internal connector designator information.\r
+  Port internal connector designator information is Misc. subclass type 6 and\r
+  SMBIOS type 8.\r
+\r
+\r
+**/\r
+\r
+\r
+#include "CommonHeader.h"\r
+\r
+#include "MiscSubclassDriver.h"\r
+\r
+//\r
+// Static (possibly build generated) Port connector designations\r
+//\r
+MISC_SMBIOS_TABLE_DATA(EFI_MISC_PORT_INTERNAL_CONNECTOR_DESIGNATOR_DATA, MiscPortIde1) = {\r
+  STRING_TOKEN(STR_MISC_PORT_INTERNAL_IDE1),\r
+  STRING_TOKEN(STR_MISC_PORT_EXTERNAL_IDE1),\r
+  EfiPortConnectorTypeOnboardIde,\r
+  EfiPortConnectorTypeNone,\r
+  EfiPortTypeOther,\r
+  0\r
+};\r
+\r
+MISC_SMBIOS_TABLE_DATA(EFI_MISC_PORT_INTERNAL_CONNECTOR_DESIGNATOR_DATA, MiscPortIde2) = {\r
+  STRING_TOKEN(STR_MISC_PORT_INTERNAL_IDE2),\r
+  STRING_TOKEN(STR_MISC_PORT_EXTERNAL_IDE2),\r
+  EfiPortConnectorTypeOnboardIde,\r
+  EfiPortConnectorTypeNone,\r
+  EfiPortTypeOther,\r
+  0\r
+};\r
+\r
+MISC_SMBIOS_TABLE_DATA(EFI_MISC_PORT_INTERNAL_CONNECTOR_DESIGNATOR_DATA, MiscPortAtxPower) = {\r
+  STRING_TOKEN(STR_MISC_PORT_INTERNAL_ATX_POWER),\r
+  STRING_TOKEN(STR_MISC_PORT_EXTERNAL_ATX_POWER),\r
+  EfiPortConnectorTypeOther,\r
+  EfiPortConnectorTypeNone,\r
+  EfiPortTypeOther,\r
+  0\r
+};\r

diff --git a/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscPortInternalConnectorDesignatorFunction.c b/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscPortInternalConnectorDesignatorFunction.c
new file mode 100644 (file)
index 0000000..81e7613
--- /dev/null
+++ b/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscPortInternalConnectorDesignatorFunction.c
@@ -0,0 +1,157 @@
+/** @file\r
+\r
+Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+\r
+Module Name:\r
+\r
+  MiscPortInternalConnectorDesignatorFunction.c\r
+\r
+Abstract:\r
+\r
+  Create the device path for the Port internal connector designator.\r
+  Port internal connector designator information is Misc. subclass type 6\r
+  and SMBIOS type 8.\r
+\r
+\r
+**/\r
+\r
+\r
+#include "CommonHeader.h"\r
+\r
+#include "MiscSubclassDriver.h"\r
+\r
+\r
+/**\r
+  This is a macro defined function, in fact, the function is\r
+  MiscPortInternalConnectorDesignatorFunction (RecordType, RecordLen, RecordData, LogRecordData)\r
+  This function makes boot time changes to the contents of the\r
+  MiscPortConnectorInformation.\r
+\r
+  @param  MiscPortInternalConnectorDesignator  The string which is used to create\r
+                                               the function\r
+  The Arguments in fact:\r
+  @param  RecordType                           Type of record to be processed from\r
+                                               the Data Table.\r
+                                               mMiscSubclassDataTable[].RecordType\r
+  @param  RecordLen                            Size of static RecordData from the\r
+                                               Data Table.\r
+                                               mMiscSubclassDataTable[].RecordLen\r
+  @param  RecordData                           Pointer to RecordData, which will be\r
+                                               written to the Data Hub\r
+  @param  LogRecordData                        TRUE to log RecordData to Data Hub.\r
+                                               FALSE when there is no more data to\r
+                                               log.\r
+\r
+  @retval EFI_SUCCESS                          *RecordData and *LogRecordData have\r
+                                               been set.\r
+  @retval EFI_UNSUPPORTED                      Unexpected RecordType value.\r
+  @retval EFI_INVALID_PARAMETER                One of the following parameter\r
+                                               conditions was true: RecordLen was\r
+                                               zero. RecordData was NULL.\r
+                                               LogRecordData was NULL.\r
+\r
+**/\r
+MISC_SMBIOS_TABLE_FUNCTION (\r
+  MiscPortInternalConnectorDesignator\r
+  )\r
+{\r
+  CHAR8                                        *OptionalStrStart;\r
+  UINTN                                        InternalRefStrLen;\r
+  UINTN                                        ExternalRefStrLen;\r
+  EFI_STRING                                   InternalRef;\r
+  EFI_STRING                                   ExternalRef;\r
+  STRING_REF                                   TokenForInternal;\r
+  STRING_REF                                   TokenForExternal;\r
+  EFI_STATUS                                   Status;\r
+  SMBIOS_TABLE_TYPE8                           *SmbiosRecord;\r
+  EFI_SMBIOS_HANDLE                            SmbiosHandle;\r
+  EFI_MISC_PORT_INTERNAL_CONNECTOR_DESIGNATOR  *ForType8InputData;\r
+\r
+  ForType8InputData = (EFI_MISC_PORT_INTERNAL_CONNECTOR_DESIGNATOR *)RecordData;\r
+\r
+  //\r
+  // First check for invalid parameters.\r
+  //\r
+  if (RecordData == NULL) {\r
+    return EFI_INVALID_PARAMETER;\r
+  }\r
+\r
+  TokenForInternal = 0;\r
+  TokenForExternal = 0;\r
+\r
+  switch (ForType8InputData->PortInternalConnectorDesignator) {\r
+\r
+    case STR_MISC_PORT_INTERNAL_IDE1:\r
+      TokenForInternal = STRING_TOKEN (STR_MISC_PORT_INTERNAL_IDE1);\r
+      TokenForExternal = STRING_TOKEN(STR_MISC_PORT_EXTERNAL_IDE1);\r
+      break;\r
+    case STR_MISC_PORT_INTERNAL_IDE2:\r
+      TokenForInternal = STRING_TOKEN (STR_MISC_PORT_INTERNAL_IDE2);\r
+      TokenForExternal = STRING_TOKEN(STR_MISC_PORT_EXTERNAL_IDE2);\r
+      break;\r
+    case STR_MISC_PORT_INTERNAL_ATX_POWER:\r
+      TokenForInternal = STRING_TOKEN (STR_MISC_PORT_INTERNAL_ATX_POWER);\r
+      TokenForExternal = STRING_TOKEN(STR_MISC_PORT_EXTERNAL_ATX_POWER);\r
+      break;\r
+    default:\r
+      break;\r
+  }\r
+\r
+  InternalRef = SmbiosMiscGetString (TokenForInternal);\r
+  InternalRefStrLen = StrLen(InternalRef);\r
+  if (InternalRefStrLen > SMBIOS_STRING_MAX_LENGTH) {\r
+    return EFI_UNSUPPORTED;\r
+  }\r
+\r
+  ExternalRef = SmbiosMiscGetString (TokenForExternal);\r
+  ExternalRefStrLen = StrLen(ExternalRef);\r
+  if (ExternalRefStrLen > SMBIOS_STRING_MAX_LENGTH) {\r
+    return EFI_UNSUPPORTED;\r
+  }\r
+\r
+  //\r
+  // Two zeros following the last string.\r
+  //\r
+  SmbiosRecord = AllocatePool(sizeof (SMBIOS_TABLE_TYPE8) + InternalRefStrLen + 1 + ExternalRefStrLen + 1 + 1);\r
+  ZeroMem(SmbiosRecord, sizeof (SMBIOS_TABLE_TYPE8) + InternalRefStrLen + 1 + ExternalRefStrLen + 1 + 1);\r
+\r
+  SmbiosRecord->Hdr.Type = EFI_SMBIOS_TYPE_PORT_CONNECTOR_INFORMATION;\r
+  SmbiosRecord->Hdr.Length = sizeof (SMBIOS_TABLE_TYPE8);\r
+\r
+  //\r
+  // Make handle chosen by smbios protocol.add automatically.\r
+  //\r
+  SmbiosRecord->Hdr.Handle = 0;\r
+  SmbiosRecord->InternalReferenceDesignator = 1;\r
+  SmbiosRecord->InternalConnectorType = (UINT8)ForType8InputData->PortInternalConnectorType;\r
+  SmbiosRecord->ExternalReferenceDesignator = 2;\r
+  SmbiosRecord->ExternalConnectorType = (UINT8)ForType8InputData->PortExternalConnectorType;\r
+  SmbiosRecord->PortType = (UINT8)ForType8InputData->PortType;\r
+\r
+  OptionalStrStart = (CHAR8 *)(SmbiosRecord + 1);\r
+  UnicodeStrToAsciiStr(InternalRef, OptionalStrStart);\r
+  UnicodeStrToAsciiStr(ExternalRef, OptionalStrStart + InternalRefStrLen + 1);\r
+\r
+  //\r
+  // Now we have got the full smbios record, call smbios protocol to add this record.\r
+  //\r
+  SmbiosHandle = SMBIOS_HANDLE_PI_RESERVED;\r
+  Status = Smbios-> Add(\r
+                      Smbios,\r
+                      NULL,\r
+                      &SmbiosHandle,\r
+                      (EFI_SMBIOS_TABLE_HEADER *) SmbiosRecord\r
+                      );\r
+  FreePool(SmbiosRecord);\r
+  return Status;\r
+}\r

diff --git a/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscProcessorCache.uni b/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscProcessorCache.uni
new file mode 100644 (file)
index 0000000..ee5736d
Binary files /dev/null and b/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscProcessorCache.uni differ

diff --git a/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscProcessorCacheData.c b/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscProcessorCacheData.c
new file mode 100644 (file)
index 0000000..aed07ba
--- /dev/null
+++ b/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscProcessorCacheData.c
@@ -0,0 +1,38 @@
+/*++\r
+\r
+Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+\r
+Module Name:\r
+\r
+  MiscBiosProcessorCache.c\r
+\r
+Abstract:\r
+\r
+  Processor cache static data.\r
+  Misc. subclass type 7.\r
+  SMBIOS type 7.\r
+\r
+--*/\r
+\r
+\r
+#include "CommonHeader.h"\r
+\r
+#include "MiscSubclassDriver.h"\r
+\r
+\r
+//\r
+// Static (possibly build generated) Processor cache data.\r
+//\r
+MISC_SMBIOS_TABLE_DATA(EFI_CACHE_VARIABLE_RECORD, MiscProcessorCache) = {\r
+0\r
+};\r

diff --git a/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscProcessorCacheFunction.c b/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscProcessorCacheFunction.c
new file mode 100644 (file)
index 0000000..cbed988
--- /dev/null
+++ b/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscProcessorCacheFunction.c
@@ -0,0 +1,202 @@
+/*++\r
+\r
+Copyright (c) 2006  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+\r
+Module Name:\r
+\r
+  MiscProcessorCacheFunction.c\r
+\r
+Abstract:\r
+\r
+  BIOS processor cache details.\r
+  Misc. subclass type 7.\r
+  SMBIOS type 7.\r
+\r
+--*/\r
+#include "CommonHeader.h"\r
+#include "MiscSubclassDriver.h"\r
+#include <Protocol/DataHub.h>\r
+#include <Guid/DataHubRecords.h>\r
+\r
+\r
+extern  SMBIOS_TABLE_TYPE7            *SmbiosRecordL1;\r
+extern  SMBIOS_TABLE_TYPE7            *SmbiosRecordL2;\r
+extern  SMBIOS_TABLE_TYPE7            *SmbiosRecordL3;\r
+\r
+\r
+UINT32\r
+ConvertBase2ToRaw (\r
+  IN  EFI_EXP_BASE2_DATA             *Data)\r
+{\r
+  UINTN         Index;\r
+  UINT32        RawData;\r
+\r
+  RawData = Data->Value;\r
+  for (Index = 0; Index < (UINTN) Data->Exponent; Index++) {\r
+     RawData <<= 1;\r
+  }\r
+\r
+  return  RawData;\r
+}\r
+\r
+\r
+MISC_SMBIOS_TABLE_FUNCTION(MiscProcessorCache)\r
+{\r
+       EFI_SMBIOS_HANDLE     SmbiosHandle;\r
+       SMBIOS_TABLE_TYPE7            *SmbiosRecordL1;\r
+       SMBIOS_TABLE_TYPE7            *SmbiosRecordL2;\r
+\r
+       EFI_CACHE_SRAM_TYPE_DATA      CacheSramType;\r
+       CHAR16                          *SocketDesignation;\r
+       CHAR8                           *OptionalStrStart;\r
+       UINTN                           SocketStrLen;\r
+       STRING_REF                      TokenToGet;\r
+       EFI_DATA_HUB_PROTOCOL           *DataHub;\r
+       UINT64                          MonotonicCount;\r
+       EFI_DATA_RECORD_HEADER          *Record;\r
+       EFI_SUBCLASS_TYPE1_HEADER       *DataHeader;\r
+       UINT8                           *SrcData;\r
+       UINT32                          SrcDataSize;\r
+       EFI_STATUS                      Status;\r
+\r
+       //\r
+       // Memory Device LOcator\r
+       //\r
+       DEBUG ((EFI_D_ERROR, "type 7\n"));\r
+\r
+       TokenToGet = STRING_TOKEN (STR_SOCKET_DESIGNATION);\r
+       SocketDesignation = SmbiosMiscGetString (TokenToGet);\r
+       SocketStrLen = StrLen(SocketDesignation);\r
+       if (SocketStrLen > SMBIOS_STRING_MAX_LENGTH) {\r
+       return EFI_UNSUPPORTED;\r
+       }\r
+\r
+       SmbiosRecordL1 = AllocatePool(sizeof (SMBIOS_TABLE_TYPE7) + 7 + 1 + 1);\r
+       ASSERT (SmbiosRecordL1 != NULL);\r
+       ZeroMem(SmbiosRecordL1, sizeof (SMBIOS_TABLE_TYPE7) + 7 + 1 + 1);\r
+\r
+       SmbiosRecordL2 = AllocatePool(sizeof (SMBIOS_TABLE_TYPE7) + 7 + 1 + 1);\r
+       ASSERT (SmbiosRecordL2 != NULL);\r
+       ZeroMem(SmbiosRecordL2, sizeof (SMBIOS_TABLE_TYPE7) + 7 + 1 + 1);\r
+\r
+       //\r
+       // Get the Data Hub Protocol. Assume only one instance\r
+       //\r
+       Status = gBS->LocateProtocol (\r
+                       &gEfiDataHubProtocolGuid,\r
+                       NULL,\r
+                       (VOID **)&DataHub\r
+                       );\r
+       ASSERT_EFI_ERROR(Status);\r
+\r
+       MonotonicCount = 0;\r
+       Record = NULL;\r
+\r
+       do {\r
+       Status = DataHub->GetNextRecord (\r
+                           DataHub,\r
+                           &MonotonicCount,\r
+                           NULL,\r
+                           &Record\r
+                           );\r
+               if (!EFI_ERROR(Status)) {\r
+                       if (Record->DataRecordClass == EFI_DATA_RECORD_CLASS_DATA) {\r
+                               DataHeader  = (EFI_SUBCLASS_TYPE1_HEADER *)(Record + 1);\r
+                               SrcData     = (UINT8  *)(DataHeader + 1);\r
+                               SrcDataSize = Record->RecordSize - Record->HeaderSize - sizeof (EFI_SUBCLASS_TYPE1_HEADER);\r
+                               if (CompareGuid(&Record->DataRecordGuid, &gEfiCacheSubClassGuid) && (DataHeader->RecordType == CacheSizeRecordType)) {\r
+                               if (DataHeader->SubInstance == EFI_CACHE_L1) {\r
+                                               SmbiosRecordL1->InstalledSize += (UINT16) (ConvertBase2ToRaw((EFI_EXP_BASE2_DATA *)SrcData) >> 10);\r
+                                               SmbiosRecordL1->MaximumCacheSize = SmbiosRecordL1->InstalledSize;\r
+                               }\r
+                                else if (DataHeader->SubInstance == EFI_CACHE_L2) {\r
+                                               SmbiosRecordL2->InstalledSize += (UINT16) (ConvertBase2ToRaw((EFI_EXP_BASE2_DATA *)SrcData) >> 10);\r
+                                               SmbiosRecordL2->MaximumCacheSize = SmbiosRecordL2->InstalledSize;\r
+                               } else {\r
+                                        continue;\r
+                               }\r
+                               }\r
+               }\r
+       }\r
+       } while (!EFI_ERROR(Status) && (MonotonicCount != 0));\r
+\r
+       //\r
+       //Filling SMBIOS type 7 information for different cache levels.\r
+       //\r
+\r
+       SmbiosRecordL1->Hdr.Type = EFI_SMBIOS_TYPE_CACHE_INFORMATION;\r
+       SmbiosRecordL1->Hdr.Length = (UINT8) sizeof (SMBIOS_TABLE_TYPE7);\r
+       SmbiosRecordL1->Hdr.Handle = 0;\r
+\r
+       SmbiosRecordL1->Associativity = CacheAssociativity8Way;\r
+       SmbiosRecordL1->SystemCacheType = CacheTypeUnknown;\r
+       SmbiosRecordL1->SocketDesignation = 0x01;\r
+       SmbiosRecordL1->CacheSpeed = 0;\r
+       SmbiosRecordL1->CacheConfiguration = 0x0180;\r
+       ZeroMem (&CacheSramType, sizeof (EFI_CACHE_SRAM_TYPE_DATA));\r
+       CacheSramType.Synchronous = 1;\r
+       CopyMem(&SmbiosRecordL1->SupportedSRAMType, &CacheSramType, 2);\r
+       CopyMem(&SmbiosRecordL1->CurrentSRAMType, &CacheSramType, 2);\r
+       SmbiosRecordL1->ErrorCorrectionType = EfiCacheErrorSingleBit;\r
+\r
+\r
+       SmbiosRecordL2->Hdr.Type = EFI_SMBIOS_TYPE_CACHE_INFORMATION;\r
+       SmbiosRecordL2->Hdr.Length = (UINT8) sizeof (SMBIOS_TABLE_TYPE7);\r
+       SmbiosRecordL2->Hdr.Handle = 0;\r
+\r
+       SmbiosRecordL2->Associativity = CacheAssociativity16Way;\r
+       SmbiosRecordL2->SystemCacheType = CacheTypeInstruction;\r
+       SmbiosRecordL2->SocketDesignation = 0x01;\r
+       SmbiosRecordL2->CacheSpeed = 0;\r
+       SmbiosRecordL2->CacheConfiguration = 0x0281;\r
+       ZeroMem (&CacheSramType, sizeof (EFI_CACHE_SRAM_TYPE_DATA));\r
+       CacheSramType.Synchronous = 1;\r
+       CopyMem(&SmbiosRecordL2->SupportedSRAMType, &CacheSramType, 2);\r
+       CopyMem(&SmbiosRecordL2->CurrentSRAMType, &CacheSramType, 2);\r
+       SmbiosRecordL2->ErrorCorrectionType = EfiCacheErrorSingleBit;\r
+\r
+\r
+\r
+       //\r
+       //Adding SMBIOS type 7 records to SMBIOS table.\r
+       //\r
+       SmbiosHandle = SMBIOS_HANDLE_PI_RESERVED;\r
+       OptionalStrStart = (CHAR8 *)(SmbiosRecordL1 + 1);\r
+       UnicodeStrToAsciiStr(SocketDesignation, OptionalStrStart);\r
+\r
+       Smbios-> Add(\r
+                  Smbios,\r
+                  NULL,\r
+                  &SmbiosHandle,\r
+                  (EFI_SMBIOS_TABLE_HEADER *) SmbiosRecordL1\r
+                  );\r
+\r
+       //\r
+       //VLV2 incorporates two SLM modules (quad cores) in the SoC. 2 cores share BIU/L2 cache\r
+       //\r
+       SmbiosRecordL2->InstalledSize = (SmbiosRecordL2->InstalledSize)/2;\r
+       SmbiosRecordL2->MaximumCacheSize = SmbiosRecordL2->InstalledSize;\r
+       SmbiosHandle = SMBIOS_HANDLE_PI_RESERVED;\r
+\r
+       OptionalStrStart = (CHAR8 *)(SmbiosRecordL2 + 1);\r
+       UnicodeStrToAsciiStr(SocketDesignation, OptionalStrStart);\r
+\r
+       Smbios-> Add(\r
+                  Smbios,\r
+                  NULL,\r
+                  &SmbiosHandle,\r
+                  (EFI_SMBIOS_TABLE_HEADER *) SmbiosRecordL2\r
+                  );\r
+\r
+       return EFI_SUCCESS;\r
+}\r

diff --git a/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscProcessorInformation.uni b/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscProcessorInformation.uni
new file mode 100644 (file)
index 0000000..f07d978
Binary files /dev/null and b/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscProcessorInformation.uni differ

diff --git a/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscProcessorInformationData.c b/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscProcessorInformationData.c
new file mode 100644 (file)
index 0000000..86ae858
--- /dev/null
+++ b/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscProcessorInformationData.c
@@ -0,0 +1,76 @@
+/*++\r
+\r
+Copyright (c) 2006  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+\r
+Module Name:\r
+\r
+  MiscOnboardDeviceData.c\r
+\r
+Abstract:\r
+\r
+  This driver parses the mMiscSubclassDataTable structure and reports\r
+  any generated data to smbios.\r
+\r
+--*/\r
+\r
+\r
+#include "CommonHeader.h"\r
+\r
+#include "MiscSubclassDriver.h"\r
+\r
+\r
+/*\r
+  EFI_PROCESSOR_CORE_FREQUENCY_LIST_DATA  ProcessorCoreFrequencyList;\r
+  EFI_PROCESSOR_FSB_FREQUENCY_LIST_DATA   ProcessorFsbFrequencyList;\r
+  EFI_PROCESSOR_SERIAL_NUMBER_DATA        ProcessorSerialNumber;\r
+  EFI_PROCESSOR_CORE_FREQUENCY_DATA       ProcessorCoreFrequency;\r
+  EFI_PROCESSOR_FSB_FREQUENCY_DATA        ProcessorFsbFrequency;\r
+  EFI_PROCESSOR_MAX_CORE_FREQUENCY_DATA   ProcessorMaxCoreFrequency;\r
+  EFI_PROCESSOR_MAX_FSB_FREQUENCY_DATA    ProcessorMaxFsbFrequency;\r
+  EFI_PROCESSOR_VERSION_DATA              ProcessorVersion;\r
+  EFI_PROCESSOR_MANUFACTURER_DATA         ProcessorManufacturer;\r
+  EFI_PROCESSOR_ID_DATA                   ProcessorId;\r
+  EFI_PROCESSOR_TYPE_DATA                 ProcessorType;\r
+  EFI_PROCESSOR_FAMILY_DATA               ProcessorFamily;\r
+  EFI_PROCESSOR_VOLTAGE_DATA              ProcessorVoltage;\r
+  EFI_PROCESSOR_APIC_BASE_ADDRESS_DATA    ProcessorApicBase;\r
+  EFI_PROCESSOR_APIC_ID_DATA              ProcessorApicId;\r
+  EFI_PROCESSOR_APIC_VERSION_NUMBER_DATA  ProcessorApicVersionNumber;\r
+  EFI_PROCESSOR_MICROCODE_REVISION_DATA   CpuUcodeRevisionData;\r
+  EFI_PROCESSOR_STATUS_DATA               ProcessorStatus;\r
+  EFI_PROCESSOR_SOCKET_TYPE_DATA          ProcessorSocketType;\r
+  EFI_PROCESSOR_SOCKET_NAME_DATA          ProcessorSocketName;\r
+  EFI_PROCESSOR_ASSET_TAG_DATA            ProcessorAssetTag;\r
+  EFI_PROCESSOR_HEALTH_STATUS             ProcessorHealthStatus;\r
+  EFI_PROCESSOR_PACKAGE_NUMBER_DATA       ProcessorPackageNumber;\r
+} EFI_CPU_VARIABLE_RECORD;\r
+*/\r
+\r
+\r
+// Static (possibly build generated) Bios Vendor data.\r
+//\r
+MISC_SMBIOS_TABLE_DATA(EFI_CPU_DATA_RECORD, MiscProcessorInformation) = {\r
+\r
+0,\r
+    /*\r
+    STRING_TOKEN (STR_MISC_SOCKET_NAME),                           // Processor Socket Name\r
+    STRING_TOKEN (STR_MISC_PROCESSOR_MAUFACTURER),                 // Processor Manufacturer\r
+    STRING_TOKEN (STR_MISC_PROCESSOR_VERSION),                 // Processor Version Information\r
+       STRING_TOKEN (STR_MISC_PROCESSOR_SERIAL_NUMBER),        // Serial Number\r
+       STRING_TOKEN (STR_MISC_ASSERT_TAG_DATA),                    // Processor Assert TAg Data\r
+    STRING_TOKEN (STR_MISC_PART_NUMBER)                            // Processor Part Numbe\r
+*/\r
+};\r
+\r
+\r
+\r

diff --git a/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscProcessorInformationFunction.c b/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscProcessorInformationFunction.c
new file mode 100644 (file)
index 0000000..005b43c
--- /dev/null
+++ b/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscProcessorInformationFunction.c
@@ -0,0 +1,455 @@
+/*++\r
+\r
+Copyright (c) 2006  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+\r
+Module Name:\r
+\r
+  MiscProcessorInformationFunction.c\r
+\r
+Abstract:\r
+\r
+  Onboard processor information boot time changes.\r
+  SMBIOS type 4.\r
+\r
+--*/\r
+\r
+#include "CommonHeader.h"\r
+\r
+#include "MiscSubclassDriver.h"\r
+\r
+#include <Protocol/MpService.h>\r
+#include <Protocol/DataHub.h>\r
+#include <Guid/DataHubRecords.h>\r
+#include <Library/CpuIA32.h>\r
+\r
+#define EfiProcessorFamilyIntelAtomProcessor    0x2B\r
+\r
+EFI_GUID                        mProcessorProducerGuid;\r
+\r
+\r
+/**\r
+  Get cache SMBIOS record handle.\r
+\r
+  @param  Smbios        Pointer to SMBIOS protocol instance.\r
+  @param  CacheLevel    Level of cache, starting from one.\r
+  @param  Handle        Returned record handle.\r
+\r
+**/\r
+\r
+VOID\r
+GetCacheHandle (\r
+  IN  EFI_SMBIOS_PROTOCOL      *Smbios,\r
+  IN  UINT8                    CacheLevel,\r
+  OUT  EFI_SMBIOS_HANDLE       *Handle\r
+  )\r
+{\r
+  UINT16                     CacheConfig;\r
+  EFI_STATUS                 Status;\r
+  EFI_SMBIOS_TYPE            RecordType;\r
+  EFI_SMBIOS_TABLE_HEADER    *Buffer;\r
+\r
+  *Handle = 0;\r
+  RecordType = EFI_SMBIOS_TYPE_CACHE_INFORMATION;\r
+\r
+  do {\r
+    Status = Smbios->GetNext (\r
+                       Smbios,\r
+                       Handle,\r
+                       &RecordType,\r
+                       &Buffer,\r
+                       NULL\r
+                       );\r
+    if (!EFI_ERROR(Status)) {\r
+      CacheConfig = *(UINT16*)((UINT8*)Buffer + 5);\r
+      if ((CacheConfig & 0x7) == (CacheLevel -1) ) {\r
+        return;\r
+      }\r
+    }\r
+  } while (!EFI_ERROR(Status));\r
+\r
+  *Handle = 0xFFFF;\r
+}\r
+\r
+\r
+/**\r
+  This function makes boot time changes to the contents of the\r
+  MiscProcessorInformation (Type 4).\r
+\r
+  @param  RecordData                 Pointer to copy of RecordData from the Data Table.\r
+\r
+  @retval EFI_SUCCESS                All parameters were valid.\r
+  @retval EFI_UNSUPPORTED            Unexpected RecordType value.\r
+  @retval EFI_INVALID_PARAMETER      Invalid parameter was found.\r
+\r
+**/\r
+UINT32\r
+ConvertBase10ToRaw (\r
+  IN  EFI_EXP_BASE10_DATA             *Data)\r
+{\r
+  UINTN         Index;\r
+  UINT32        RawData;\r
+\r
+  RawData = Data->Value;\r
+  for (Index = 0; Index < (UINTN) Data->Exponent; Index++) {\r
+     RawData *= 10;\r
+  }\r
+\r
+  return  RawData;\r
+}\r
+\r
+#define BSEL_CR_OVERCLOCK_CONTROL      0xCD\r
+#define        FUSE_BSEL_MASK                          0x03\r
+\r
+\r
+\r
+UINT16 miFSBFrequencyTable[4] = {\r
+  83,                  // 83.3MHz\r
+  100,          // 100MHz\r
+  133,          // 133MHz\r
+  117           // 116.7MHz\r
+};\r
+\r
+/**\r
+  Determine the processor core frequency\r
+\r
+  @param None\r
+\r
+  @retval Processor core frequency multiplied by 3\r
+\r
+\r
+**/\r
+UINT16\r
+DetermineiFsbFromMsr (\r
+  VOID\r
+  )\r
+{\r
+  //\r
+  // Determine the processor core frequency\r
+  //\r
+  UINT64       Temp;\r
+  Temp = (EfiReadMsr (BSEL_CR_OVERCLOCK_CONTROL)) & FUSE_BSEL_MASK;\r
+  return miFSBFrequencyTable[(UINT32)(Temp)];\r
+\r
+}\r
+\r
+MISC_SMBIOS_TABLE_FUNCTION (MiscProcessorInformation)\r
+{\r
+    CHAR8                           *OptionalStrStart;\r
+    EFI_STRING                      SerialNumber;\r
+    CHAR16                          *Version=NULL;\r
+    CHAR16                          *Manufacturer=NULL;\r
+    CHAR16                          *Socket=NULL;\r
+    CHAR16                          *AssetTag=NULL;\r
+    CHAR16                          *PartNumber=NULL;\r
+    UINTN                           SerialNumberStrLen=0;\r
+    UINTN                           VersionStrLen=0;\r
+    UINTN                           ManufacturerStrLen=0;\r
+    UINTN                           SocketStrLen=0;\r
+    UINTN                           AssetTagStrLen=0;\r
+    UINTN                           PartNumberStrLen=0;\r
+    UINTN                           ProcessorVoltage=0xAE;\r
+    UINT32                          Eax01;\r
+    UINT32                          Ebx01;\r
+    UINT32                          Ecx01;\r
+    UINT32                          Edx01;\r
+    STRING_REF                      TokenToGet;\r
+    EFI_STATUS                      Status;\r
+    EFI_SMBIOS_HANDLE               SmbiosHandle;\r
+    SMBIOS_TABLE_TYPE4              *SmbiosRecord;\r
+    EFI_CPU_DATA_RECORD             *ForType4InputData;\r
+    UINT16                          L1CacheHandle=0;\r
+    UINT16                          L2CacheHandle=0;\r
+    UINT16                          L3CacheHandle=0;\r
+    UINTN                           NumberOfEnabledProcessors=0 ;\r
+    UINTN                           NumberOfProcessors=0;\r
+    UINT64                          Frequency = 0;\r
+    EFI_MP_SERVICES_PROTOCOL        *MpService;\r
+    EFI_DATA_HUB_PROTOCOL           *DataHub;\r
+    UINT64                          MonotonicCount;\r
+    EFI_DATA_RECORD_HEADER          *Record;\r
+    EFI_SUBCLASS_TYPE1_HEADER       *DataHeader;\r
+    UINT8                           *SrcData;\r
+    UINT32                          SrcDataSize;\r
+    EFI_PROCESSOR_VERSION_DATA      *ProcessorVersion;\r
+    CHAR16                          *NewStringToken;\r
+    STRING_REF                      TokenToUpdate;\r
+    PROCESSOR_ID_DATA               *ProcessorId = NULL;\r
+\r
+\r
+    //\r
+    // First check for invalid parameters.\r
+    //\r
+    if (RecordData == NULL) {\r
+        return EFI_INVALID_PARAMETER;\r
+    }\r
+\r
+    ForType4InputData = (EFI_CPU_DATA_RECORD *)RecordData;\r
+\r
+    ProcessorId = AllocateZeroPool(sizeof(PROCESSOR_ID_DATA));\r
+    if (ProcessorId == NULL) {\r
+      return EFI_INVALID_PARAMETER;\r
+    }\r
+\r
+    //\r
+    // Get the Data Hub Protocol. Assume only one instance\r
+    //\r
+    Status = gBS->LocateProtocol (\r
+                    &gEfiDataHubProtocolGuid,\r
+                    NULL,\r
+                    (VOID **)&DataHub\r
+                    );\r
+    ASSERT_EFI_ERROR(Status);\r
+\r
+    MonotonicCount = 0;\r
+    Record = NULL;\r
+\r
+    do {\r
+      Status = DataHub->GetNextRecord (\r
+                          DataHub,\r
+                          &MonotonicCount,\r
+                          NULL,\r
+                          &Record\r
+                          );\r
+       if (!EFI_ERROR(Status)) {\r
+         if (Record->DataRecordClass == EFI_DATA_RECORD_CLASS_DATA) {\r
+\r
+            DataHeader  = (EFI_SUBCLASS_TYPE1_HEADER *)(Record + 1);\r
+            SrcData     = (UINT8  *)(DataHeader + 1);\r
+            SrcDataSize = Record->RecordSize - Record->HeaderSize - sizeof (EFI_SUBCLASS_TYPE1_HEADER);\r
+\r
+            //\r
+            // Processor\r
+            //\r
+            if (CompareGuid(&Record->DataRecordGuid, &gEfiProcessorSubClassGuid)) {\r
+              CopyMem (&mProcessorProducerGuid, &Record->ProducerName, sizeof(EFI_GUID));\r
+              switch (DataHeader->RecordType) {\r
+                case ProcessorVoltageRecordType:\r
+                  ProcessorVoltage = (((EFI_EXP_BASE10_DATA *)SrcData)->Value)/100 + 0x80;\r
+                  break;\r
+                case ProcessorCoreFrequencyRecordType:\r
+                  DEBUG ((EFI_D_ERROR, "ProcessorCoreFrequencyRecordType SrcData1 =%d\n", ConvertBase10ToRaw((EFI_EXP_BASE10_DATA *)SrcData)/1000000));\r
+                  Frequency = (ConvertBase10ToRaw((EFI_EXP_BASE10_DATA *)SrcData)/1000000);\r
+                  break;\r
+                case ProcessorVersionRecordType:\r
+                  ProcessorVersion = (EFI_PROCESSOR_VERSION_DATA *)SrcData;\r
+                  NewStringToken = HiiGetPackageString(&mProcessorProducerGuid, *ProcessorVersion, NULL);\r
+                  TokenToUpdate = (STRING_REF)STR_MISC_PROCESSOR_VERSION;\r
+                  HiiSetString(mHiiHandle, TokenToUpdate, NewStringToken, NULL);\r
+                  break;\r
+                default:\r
+                  break;\r
+              }\r
+            }\r
+          }\r
+        }\r
+    } while (!EFI_ERROR(Status) && (MonotonicCount != 0));\r
+\r
+    //\r
+    // Token to get for Socket Name\r
+    //\r
+    TokenToGet = STRING_TOKEN (STR_MISC_SOCKET_NAME);\r
+    Socket = SmbiosMiscGetString (TokenToGet);\r
+    SocketStrLen = StrLen(Socket);\r
+    if (SocketStrLen > SMBIOS_STRING_MAX_LENGTH) {\r
+         return EFI_UNSUPPORTED;\r
+    }\r
+\r
+    //\r
+    // Token to get for Processor Manufacturer\r
+    //\r
+    TokenToGet = STRING_TOKEN (STR_MISC_PROCESSOR_MAUFACTURER);\r
+    Manufacturer = SmbiosMiscGetString (TokenToGet);\r
+    ManufacturerStrLen = StrLen(Manufacturer);\r
+    if (ManufacturerStrLen > SMBIOS_STRING_MAX_LENGTH) {\r
+      return EFI_UNSUPPORTED;\r
+    }\r
+\r
+    //\r
+    // Token to get for Processor Version\r
+    //\r
+    TokenToGet = STRING_TOKEN (STR_MISC_PROCESSOR_VERSION);\r
+    Version = SmbiosMiscGetString (TokenToGet);\r
+    VersionStrLen = StrLen(Version);\r
+    if (VersionStrLen > SMBIOS_STRING_MAX_LENGTH) {\r
+        return EFI_UNSUPPORTED;\r
+    }\r
+\r
+    //\r
+    // Token to get for Serial Number\r
+    //\r
+    TokenToGet = STRING_TOKEN (STR_MISC_PROCESSOR_SERIAL_NUMBER);\r
+    SerialNumber = SmbiosMiscGetString (TokenToGet);\r
+    SerialNumberStrLen = StrLen(SerialNumber);\r
+    if (SerialNumberStrLen > SMBIOS_STRING_MAX_LENGTH) {\r
+        return EFI_UNSUPPORTED;\r
+    }\r
+\r
+    //\r
+    // Token to get for Assert Tag Information\r
+    //\r
+    TokenToGet = STRING_TOKEN (STR_MISC_ASSERT_TAG_DATA);\r
+    AssetTag = SmbiosMiscGetString (TokenToGet);\r
+    AssetTagStrLen = StrLen(AssetTag);\r
+    if (AssetTagStrLen > SMBIOS_STRING_MAX_LENGTH) {\r
+        return EFI_UNSUPPORTED;\r
+    }\r
+\r
+    //\r
+    // Token to get for part number Information\r
+    //\r
+    TokenToGet = STRING_TOKEN (STR_MISC_PART_NUMBER);\r
+    PartNumber = SmbiosMiscGetString (TokenToGet);\r
+    PartNumberStrLen = StrLen(PartNumber);\r
+    if (PartNumberStrLen > SMBIOS_STRING_MAX_LENGTH) {\r
+         return EFI_UNSUPPORTED;\r
+    }\r
+\r
+    //\r
+    // Two zeros following the last string.\r
+    //\r
+    SmbiosRecord = AllocateZeroPool(sizeof (SMBIOS_TABLE_TYPE4) + AssetTagStrLen + 1 + SocketStrLen + 1+ ManufacturerStrLen +1 + VersionStrLen+ 1+ SerialNumberStrLen + 1 + PartNumberStrLen+ 1 + 1);\r
+\r
+    SmbiosRecord->Hdr.Type = EFI_SMBIOS_TYPE_PROCESSOR_INFORMATION;\r
+    SmbiosRecord->Hdr.Length = sizeof (SMBIOS_TABLE_TYPE4);\r
+\r
+    //\r
+    // Make handle chosen by smbios protocol.add automatically.\r
+    //\r
+    SmbiosRecord->Hdr.Handle = 0;\r
+\r
+    SmbiosRecord-> Socket= 1;\r
+    SmbiosRecord -> ProcessorManufacture = 2;\r
+    SmbiosRecord -> ProcessorVersion = 3;\r
+    SmbiosRecord ->SerialNumber =4;\r
+\r
+    SmbiosRecord-> AssetTag= 5;\r
+    SmbiosRecord-> PartNumber= 6;\r
+\r
+    //\r
+    // Processor Type\r
+    //\r
+    ForType4InputData-> VariableRecord.ProcessorType= EfiCentralProcessor;\r
+    SmbiosRecord -> ProcessorType = ForType4InputData-> VariableRecord.ProcessorType;\r
+\r
+    //\r
+    // Processor Family\r
+    //\r
+    ForType4InputData-> VariableRecord.ProcessorFamily= EfiProcessorFamilyIntelAtomProcessor; //0x2B;;\r
+    SmbiosRecord -> ProcessorFamily = ForType4InputData-> VariableRecord.ProcessorFamily;\r
+    SmbiosRecord -> ExternalClock = DetermineiFsbFromMsr();\r
+\r
+    //\r
+    // Processor ID\r
+    //\r
+    AsmCpuid(0x001, &Eax01, &Ebx01, &Ecx01, &Edx01);\r
+    ProcessorId->Signature = *(PROCESSOR_SIGNATURE *)&Eax01;\r
+    ProcessorId->FeatureFlags = *(PROCESSOR_FEATURE_FLAGS *)&Edx01;\r
+    SmbiosRecord -> ProcessorId = *(PROCESSOR_ID_DATA *)ProcessorId;\r
+\r
+    //\r
+    // Processor Voltage\r
+    //\r
+    ForType4InputData-> VariableRecord.ProcessorVoltage= *(EFI_PROCESSOR_VOLTAGE_DATA *)&ProcessorVoltage;\r
+    SmbiosRecord -> Voltage = *(PROCESSOR_VOLTAGE *) &(ForType4InputData-> VariableRecord.ProcessorVoltage);\r
+\r
+    //\r
+    // Status\r
+    //\r
+    ForType4InputData-> VariableRecord.ProcessorHealthStatus= 0x41;//0x41;\r
+    SmbiosRecord -> Status = ForType4InputData-> VariableRecord.ProcessorHealthStatus;\r
+\r
+    //\r
+    // Processor Upgrade\r
+    //\r
+    SmbiosRecord -> ProcessorUpgrade = 0x008;\r
+\r
+    //\r
+    // Processor Family 2\r
+    //\r
+    SmbiosRecord -> ProcessorFamily2 = ForType4InputData-> VariableRecord.ProcessorFamily;\r
+\r
+    //\r
+    // Processor speed\r
+    //\r
+    SmbiosRecord-> CurrentSpeed = *(UINT16*) & Frequency;\r
+    SmbiosRecord-> MaxSpeed = *(UINT16*) & Frequency;\r
+\r
+    //\r
+    // Processor Characteristics\r
+    //\r
+    AsmCpuid(0x8000000, NULL, NULL, NULL, &Edx01);\r
+    Edx01= Edx01 >> 28;\r
+    Edx01 &= 0x01;\r
+    SmbiosRecord-> ProcessorCharacteristics= (UINT16)Edx01;\r
+\r
+    //\r
+    // Processor Core Count and Enabled core count\r
+    //\r
+    Status = gBS->LocateProtocol (\r
+                    &gEfiMpServiceProtocolGuid,\r
+                    NULL,\r
+                    (void **)&MpService\r
+                    );\r
+    if (!EFI_ERROR (Status)) {\r
+    //\r
+    // Determine the number of processors\r
+    //\r
+    MpService->GetNumberOfProcessors (\r
+                 MpService,\r
+                 &NumberOfProcessors,\r
+                 &NumberOfEnabledProcessors\r
+                 );\r
+    }\r
+    SmbiosRecord-> CoreCount= (UINT8)NumberOfProcessors;\r
+    SmbiosRecord-> EnabledCoreCount= (UINT8)NumberOfEnabledProcessors;\r
+    SmbiosRecord-> ThreadCount= (UINT8)NumberOfEnabledProcessors;\r
+    SmbiosRecord-> ProcessorCharacteristics = 0x2; // Unknown\r
+\r
+    //\r
+    // Processor Cache Handle\r
+    //\r
+    GetCacheHandle( Smbios,1, &L1CacheHandle);\r
+    GetCacheHandle( Smbios,2, &L2CacheHandle);\r
+    GetCacheHandle( Smbios,3, &L3CacheHandle);\r
+\r
+    //\r
+    // Updating Cache Handle Information\r
+    //\r
+    SmbiosRecord->L1CacheHandle  = L1CacheHandle;\r
+    SmbiosRecord->L2CacheHandle  = L2CacheHandle;\r
+    SmbiosRecord->L3CacheHandle  = L3CacheHandle;\r
+\r
+    OptionalStrStart = (CHAR8 *)(SmbiosRecord + 1);\r
+    UnicodeStrToAsciiStr(Socket, OptionalStrStart);\r
+    UnicodeStrToAsciiStr(Manufacturer, OptionalStrStart + SocketStrLen + 1);\r
+    UnicodeStrToAsciiStr(Version, OptionalStrStart + SocketStrLen + 1 + ManufacturerStrLen+ 1);\r
+    UnicodeStrToAsciiStr(SerialNumber, OptionalStrStart + SocketStrLen + 1 + VersionStrLen + 1 + ManufacturerStrLen + 1);\r
+    UnicodeStrToAsciiStr(AssetTag, OptionalStrStart + SerialNumberStrLen + 1 + VersionStrLen + 1 + ManufacturerStrLen + 1 + SocketStrLen + 1);\r
+    UnicodeStrToAsciiStr(PartNumber, OptionalStrStart + SerialNumberStrLen + 1 + VersionStrLen + 1 + ManufacturerStrLen + 1 + SocketStrLen + 1 + AssetTagStrLen + 1 );\r
+\r
+    //\r
+    // Now we have got the full Smbios record, call Smbios protocol to add this record.\r
+    //\r
+    SmbiosHandle = SMBIOS_HANDLE_PI_RESERVED;\r
+    Status = Smbios-> Add(\r
+                        Smbios,\r
+                        NULL,\r
+                        &SmbiosHandle,\r
+                        (EFI_SMBIOS_TABLE_HEADER *) SmbiosRecord\r
+                        );\r
+    if (EFI_ERROR (Status)) return Status;\r
+    FreePool(SmbiosRecord);\r
+    return Status;\r
+\r
+}\r
+\r

diff --git a/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscResetCapabilitiesData.c b/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscResetCapabilitiesData.c
new file mode 100644 (file)
index 0000000..903a34d
--- /dev/null
+++ b/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscResetCapabilitiesData.c
@@ -0,0 +1,48 @@
+/** @file\r
+\r
+Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+\r
+Module Name:\r
+\r
+    MiscResetCapabilitiesData.c\r
+\r
+Abstract:\r
+\r
+  Static data of Reset Capabilities information.\r
+  Reset Capabilities information is Misc. subclass type 17 and SMBIOS type 23.\r
+\r
+\r
+**/\r
+\r
+\r
+#include "CommonHeader.h"\r
+\r
+#include "MiscSubclassDriver.h"\r
+\r
+//\r
+// Static (possibly build generated) Bios Vendor data.\r
+//\r
+MISC_SMBIOS_TABLE_DATA(EFI_MISC_RESET_CAPABILITIES, MiscResetCapabilities)\r
+= {\r
+  {       // ResetCapabilities\r
+    0,    // Status\r
+    0,    // BootOption\r
+    0,    // BootOptionOnLimit\r
+    0,    // WatchdogTimerPresent\r
+    0     // Reserved\r
+  },\r
+  0xFFFF, // ResetCount\r
+  0xFFFF, // ResetLimit\r
+  0xFFFF, // ResetTimerInterval\r
+  0xFFFF  // ResetTimeout\r
+};\r

diff --git a/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscResetCapabilitiesFunction.c b/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscResetCapabilitiesFunction.c
new file mode 100644 (file)
index 0000000..1cf0f90
--- /dev/null
+++ b/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscResetCapabilitiesFunction.c
@@ -0,0 +1,90 @@
+/*++\r
+\r
+Copyright (c) 2009 - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+Module Name:\r
+\r
+  MiscResetCapabilitiesFunction.c\r
+\r
+Abstract:\r
+\r
+  ResetCapabilities.\r
+  SMBIOS type 23.\r
+\r
+--*/\r
+\r
+\r
+#include "CommonHeader.h"\r
+\r
+#include "MiscSubclassDriver.h"\r
+\r
+/**\r
+  This function makes boot time changes to the contents of the\r
+  MiscOemString (Type 11).\r
+\r
+  @param  RecordData                 Pointer to copy of RecordData from the Data Table.\r
+\r
+  @retval EFI_SUCCESS                All parameters were valid.\r
+  @retval EFI_UNSUPPORTED            Unexpected RecordType value.\r
+  @retval EFI_INVALID_PARAMETER      Invalid parameter was found.\r
+\r
+**/\r
+MISC_SMBIOS_TABLE_FUNCTION(MiscResetCapabilities)\r
+{\r
+  EFI_STATUS               Status;\r
+  EFI_SMBIOS_HANDLE        SmbiosHandle;\r
+  SMBIOS_TABLE_TYPE23      *SmbiosRecord;\r
+  EFI_MISC_RESET_CAPABILITIES   *ForType23InputData;\r
+\r
+  ForType23InputData = (EFI_MISC_RESET_CAPABILITIES *)RecordData;\r
+\r
+  //\r
+  // First check for invalid parameters.\r
+  //\r
+  if (RecordData == NULL) {\r
+    return EFI_INVALID_PARAMETER;\r
+  }\r
+\r
+\r
+  //\r
+  // Two zeros following the last string.\r
+  //\r
+  SmbiosRecord = AllocatePool(sizeof (SMBIOS_TABLE_TYPE23) + 1 + 1);\r
+  ZeroMem(SmbiosRecord, sizeof (SMBIOS_TABLE_TYPE23) + 1 + 1);\r
+\r
+  SmbiosRecord->Hdr.Type = EFI_SMBIOS_TYPE_SYSTEM_RESET;\r
+  SmbiosRecord->Hdr.Length = sizeof (SMBIOS_TABLE_TYPE23);\r
+\r
+  //\r
+  // Make handle chosen by smbios protocol.add automatically.\r
+  //\r
+  SmbiosRecord->Hdr.Handle    = 0;\r
+  SmbiosRecord->Capabilities  = *(UINT8*)&(ForType23InputData->ResetCapabilities);\r
+  SmbiosRecord->ResetCount    = (UINT16)ForType23InputData->ResetCount;\r
+  SmbiosRecord->ResetLimit    = (UINT16)ForType23InputData->ResetLimit;\r
+  SmbiosRecord->TimerInterval = (UINT16)ForType23InputData->ResetTimerInterval;\r
+  SmbiosRecord->Timeout       = (UINT16)ForType23InputData->ResetTimeout;\r
+\r
+  //\r
+  // Now we have got the full smbios record, call smbios protocol to add this record.\r
+  //\r
+  SmbiosHandle = SMBIOS_HANDLE_PI_RESERVED;\r
+  Status = Smbios-> Add(\r
+                      Smbios,\r
+                      NULL,\r
+                      &SmbiosHandle,\r
+                      (EFI_SMBIOS_TABLE_HEADER *) SmbiosRecord\r
+                      );\r
+  FreePool(SmbiosRecord);\r
+  return Status;\r
+}\r
+\r

diff --git a/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscSubclassDriver.h b/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscSubclassDriver.h
new file mode 100644 (file)
index 0000000..9e188c6
--- /dev/null
+++ b/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscSubclassDriver.h
@@ -0,0 +1,193 @@
+/** @file\r
+\r
+Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+\r
+Module Name:\r
+\r
+  MiscSubclassDriver.h\r
+\r
+Abstract:\r
+\r
+  Header file for MiscSubclass Driver.\r
+\r
+\r
+**/\r
+\r
+#ifndef _MISC_SUBCLASS_DRIVER_H\r
+#define _MISC_SUBCLASS_DRIVER_H\r
+\r
+\r
+#include "CommonHeader.h"\r
+\r
+extern UINT8  MiscSubclassStrings[];\r
+\r
+\r
+#define T14_FVI_STRING          "Driver/firmware version"\r
+#define EFI_SMBIOS_TYPE_FIRMWARE_VERSION_INFO 0x90\r
+#define EFI_SMBIOS_TYPE_MISC_VERSION_INFO 0x94\r
+#define TOUCH_ACPI_ID    "I2C05\\SFFFF\\400K"\r
+#define TOUCH_RESET_GPIO_MMIO  0xFED0C508\r
+#define EFI_SMBIOS_TYPE_SEC_INFO 0x83\r
+#define IntelIdentifer 0x6F725076\r
+\r
+//\r
+// Data table entry update function.\r
+//\r
+typedef EFI_STATUS (EFIAPI EFI_MISC_SMBIOS_DATA_FUNCTION) (\r
+  IN  VOID                 *RecordData,\r
+  IN  EFI_SMBIOS_PROTOCOL  *Smbios\r
+  );\r
+\r
+//\r
+// Data table entry definition.\r
+//\r
+typedef struct {\r
+  //\r
+  // intermediat input data for SMBIOS record\r
+  //\r
+  VOID                              *RecordData;\r
+  EFI_MISC_SMBIOS_DATA_FUNCTION     *Function;\r
+} EFI_MISC_SMBIOS_DATA_TABLE;\r
+\r
+//\r
+// Data Table extern definitions.\r
+//\r
+#define MISC_SMBIOS_TABLE_EXTERNS(NAME1, NAME2, NAME3) \\r
+extern NAME1 NAME2 ## Data; \\r
+extern EFI_MISC_SMBIOS_DATA_FUNCTION NAME3 ## Function\r
+\r
+\r
+//\r
+// Data Table entries\r
+//\r
+#define MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(NAME1, NAME2) \\r
+{ \\r
+  & NAME1 ## Data, \\r
+  & NAME2 ## Function \\r
+}\r
+\r
+//\r
+// Global definition macros.\r
+//\r
+#define MISC_SMBIOS_TABLE_DATA(NAME1, NAME2) \\r
+  NAME1 NAME2 ## Data\r
+\r
+#define MISC_SMBIOS_TABLE_FUNCTION(NAME2) \\r
+  EFI_STATUS EFIAPI NAME2 ## Function( \\r
+  IN  VOID                  *RecordData, \\r
+  IN  EFI_SMBIOS_PROTOCOL   *Smbios \\r
+  )\r
+\r
+#pragma pack(1)\r
+\r
+//\r
+// This is definition for SMBIOS Oem data type 0x90\r
+//\r
+typedef struct {\r
+  STRING_REF                         SECVersion;\r
+  STRING_REF                         uCodeVersion;\r
+  STRING_REF                         GOPVersion;\r
+  STRING_REF                         CpuStepping;\r
+} EFI_MISC_OEM_TYPE_0x90;\r
+\r
+//\r
+// This is definition for SMBIOS Oem data type 0x90\r
+//\r
+typedef struct {\r
+  SMBIOS_STRUCTURE          Hdr;\r
+  SMBIOS_TABLE_STRING       SECVersion;\r
+  SMBIOS_TABLE_STRING       uCodeVersion;\r
+  SMBIOS_TABLE_STRING       GOPVersion;\r
+  SMBIOS_TABLE_STRING       CpuStepping;\r
+} SMBIOS_TABLE_TYPE90;\r
+\r
+typedef struct {\r
+  STRING_REF                GopVersion;\r
+  STRING_REF                UCodeVersion;\r
+  STRING_REF                MRCVersion;\r
+  STRING_REF                SECVersion;\r
+  STRING_REF                ULPMCVersion;\r
+  STRING_REF                PMCVersion;\r
+  STRING_REF                PUnitVersion;\r
+  STRING_REF                SoCVersion;\r
+  STRING_REF                BoardVersion;\r
+  STRING_REF                FabVersion;\r
+  STRING_REF                CPUFlavor;\r
+  STRING_REF                BiosVersion;\r
+  STRING_REF                PmicVersion;\r
+  STRING_REF                TouchVersion;\r
+  STRING_REF                SecureBoot;\r
+  STRING_REF                BootMode;\r
+  STRING_REF                SpeedStepMode;\r
+  STRING_REF                CPUTurboMode;\r
+  STRING_REF                MaxCState;\r
+  STRING_REF                GfxTurbo;\r
+  STRING_REF                IdleReserve;\r
+  STRING_REF                RC6;\r
+}EFI_MISC_OEM_TYPE_0x94;\r
+\r
+typedef struct {\r
+  SMBIOS_STRUCTURE          Hdr;\r
+  SMBIOS_TABLE_STRING       GopVersion;\r
+  SMBIOS_TABLE_STRING       uCodeVersion;\r
+  SMBIOS_TABLE_STRING       MRCVersion;\r
+  SMBIOS_TABLE_STRING       SECVersion;\r
+  SMBIOS_TABLE_STRING       ULPMCVersion;\r
+  SMBIOS_TABLE_STRING       PMCVersion;\r
+  SMBIOS_TABLE_STRING       PUnitVersion;\r
+  SMBIOS_TABLE_STRING       SoCVersion;\r
+  SMBIOS_TABLE_STRING       BoardVersion;\r
+  SMBIOS_TABLE_STRING       FabVersion;\r
+  SMBIOS_TABLE_STRING       CPUFlavor;\r
+  SMBIOS_TABLE_STRING       BiosVersion;\r
+  SMBIOS_TABLE_STRING       PmicVersion;\r
+  SMBIOS_TABLE_STRING       TouchVersion;\r
+  SMBIOS_TABLE_STRING       SecureBoot;\r
+  SMBIOS_TABLE_STRING       BootMode;\r
+  SMBIOS_TABLE_STRING       SpeedStepMode;\r
+  SMBIOS_TABLE_STRING       CPUTurboMode;\r
+  SMBIOS_TABLE_STRING       MaxCState;\r
+  SMBIOS_TABLE_STRING       GfxTurbo;\r
+  SMBIOS_TABLE_STRING       IdleReserve;\r
+  SMBIOS_TABLE_STRING       RC6;\r
+}SMBIOS_TABLE_TYPE94;\r
+\r
+#pragma pack()\r
+//\r
+// Data Table Array\r
+//\r
+extern EFI_MISC_SMBIOS_DATA_TABLE mMiscSubclassDataTable[];\r
+\r
+//\r
+// Data Table Array Entries\r
+//\r
+extern UINTN                        mMiscSubclassDataTableEntries;\r
+extern EFI_HII_HANDLE               mHiiHandle;\r
+\r
+//\r
+// Prototypes\r
+//\r
+EFI_STATUS\r
+EFIAPI\r
+MiscSubclassDriverEntryPoint (\r
+  IN EFI_HANDLE         ImageHandle,\r
+  IN EFI_SYSTEM_TABLE   *SystemTable\r
+  );\r
+\r
+EFI_STRING\r
+EFIAPI\r
+SmbiosMiscGetString (\r
+  IN EFI_STRING_ID   StringId\r
+  );\r
+\r
+#endif\r

diff --git a/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscSubclassDriver.uni b/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscSubclassDriver.uni
new file mode 100644 (file)
index 0000000..2d0d141
Binary files /dev/null and b/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscSubclassDriver.uni differ

diff --git a/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscSubclassDriverDataTable.c b/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscSubclassDriverDataTable.c
new file mode 100644 (file)
index 0000000..3b77a75
--- /dev/null
+++ b/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscSubclassDriverDataTable.c
@@ -0,0 +1,103 @@
+/** @file\r
+\r
+Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+\r
+Module Name:\r
+\r
+  MiscSubclassDriverDataTable.c\r
+\r
+Abstract:\r
+\r
+  Create the mMiscSubclassDataTable structure, and it is used to report\r
+  any generate data to the DataHub.\r
+\r
+\r
+**/\r
+\r
+\r
+#include "CommonHeader.h"\r
+\r
+#include "MiscSubclassDriver.h"\r
+\r
+//\r
+// External definitions referenced by Data Table entries.\r
+//\r
+MISC_SMBIOS_TABLE_EXTERNS(EFI_MISC_BIOS_VENDOR_DATA, MiscBiosVendor, MiscBiosVendor);\r
+MISC_SMBIOS_TABLE_EXTERNS(EFI_MISC_SYSTEM_MANUFACTURER_DATA, MiscSystemManufacturer, MiscSystemManufacturer);\r
+MISC_SMBIOS_TABLE_EXTERNS(EFI_MISC_BASE_BOARD_MANUFACTURER_DATA, MiscBaseBoardManufacturer, MiscBaseBoardManufacturer);\r
+MISC_SMBIOS_TABLE_EXTERNS(EFI_MISC_CHASSIS_MANUFACTURER_DATA, MiscChassisManufacturer, MiscChassisManufacturer);\r
+MISC_SMBIOS_TABLE_EXTERNS(EFI_CACHE_VARIABLE_RECORD, MiscProcessorCache, MiscProcessorCache); //type 7\r
+MISC_SMBIOS_TABLE_EXTERNS(EFI_CPU_DATA_RECORD, MiscProcessorInformation, MiscProcessorInformation); //type 4\r
+MISC_SMBIOS_TABLE_EXTERNS(EFI_MEMORY_ARRAY_LOCATION_DATA, MiscPhysicalMemoryArray,MiscPhysicalMemoryArray);\r
+MISC_SMBIOS_TABLE_EXTERNS(EFI_MEMORY_ARRAY_LINK_DATA, MiscMemoryDevice, MiscMemoryDevice);\r
+\r
+MISC_SMBIOS_TABLE_EXTERNS(EFI_MISC_PORT_INTERNAL_CONNECTOR_DESIGNATOR_DATA, MiscPortIde1, MiscPortInternalConnectorDesignator);\r
+MISC_SMBIOS_TABLE_EXTERNS(EFI_MISC_PORT_INTERNAL_CONNECTOR_DESIGNATOR_DATA, MiscPortIde2, MiscPortInternalConnectorDesignator);\r
+MISC_SMBIOS_TABLE_EXTERNS(EFI_MISC_PORT_INTERNAL_CONNECTOR_DESIGNATOR_DATA, MiscPortAtxPower, MiscPortInternalConnectorDesignator);\r
+MISC_SMBIOS_TABLE_EXTERNS(EFI_MISC_SYSTEM_SLOT_DESIGNATION_DATA, MiscSystemSlotPCIEx16Slot1, MiscSystemSlotDesignation);\r
+MISC_SMBIOS_TABLE_EXTERNS(EFI_MISC_SYSTEM_SLOT_DESIGNATION_DATA, MiscSystemSlotPCIEx16Slot2, MiscSystemSlotDesignation);\r
+MISC_SMBIOS_TABLE_EXTERNS(EFI_MISC_SYSTEM_SLOT_DESIGNATION_DATA, MiscSystemSlotPCIEx4, MiscSystemSlotDesignation);\r
+MISC_SMBIOS_TABLE_EXTERNS(EFI_MISC_SYSTEM_SLOT_DESIGNATION_DATA, MiscSystemSlotPCIEx1Slot1, MiscSystemSlotDesignation);\r
+MISC_SMBIOS_TABLE_EXTERNS(EFI_MISC_SYSTEM_SLOT_DESIGNATION_DATA, MiscSystemSlotPCIEx1Slot2, MiscSystemSlotDesignation);\r
+MISC_SMBIOS_TABLE_EXTERNS(EFI_MISC_SYSTEM_SLOT_DESIGNATION_DATA, MiscSystemSlotPCIEx1Slot3, MiscSystemSlotDesignation);\r
+MISC_SMBIOS_TABLE_EXTERNS(EFI_MISC_SYSTEM_SLOT_DESIGNATION_DATA, MiscSystemSlotPCI1, MiscSystemSlotDesignation);\r
+MISC_SMBIOS_TABLE_EXTERNS(EFI_MISC_SYSTEM_SLOT_DESIGNATION_DATA, MiscSystemSlotPCI2, MiscSystemSlotDesignation);\r
+MISC_SMBIOS_TABLE_EXTERNS(EFI_MISC_SYSTEM_SLOT_DESIGNATION_DATA, MiscSystemSlotPCI3, MiscSystemSlotDesignation);\r
+MISC_SMBIOS_TABLE_EXTERNS(EFI_MISC_ONBOARD_DEVICE_DATA, MiscOnboardDeviceVideo, MiscOnboardDevice);\r
+MISC_SMBIOS_TABLE_EXTERNS(EFI_MISC_ONBOARD_DEVICE_DATA, MiscOnboardDeviceNetwork, MiscOnboardDevice);\r
+MISC_SMBIOS_TABLE_EXTERNS(EFI_MISC_ONBOARD_DEVICE_DATA, MiscOnboardDeviceAudio, MiscOnboardDevice);\r
+MISC_SMBIOS_TABLE_EXTERNS(EFI_MISC_NUMBER_OF_INSTALLABLE_LANGUAGES_DATA, NumberOfInstallableLanguages, NumberOfInstallableLanguages);\r
+MISC_SMBIOS_TABLE_EXTERNS(EFI_MISC_SYSTEM_LANGUAGE_STRING_DATA, SystemLanguageString, SystemLanguageString);\r
+MISC_SMBIOS_TABLE_EXTERNS(EFI_MISC_BOOT_INFORMATION_STATUS_DATA, BootInformationStatus, BootInformationStatus);\r
+\r
+//\r
+// Data Table.\r
+//\r
+EFI_MISC_SMBIOS_DATA_TABLE  mMiscSubclassDataTable[] = {\r
+  MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscBiosVendor, MiscBiosVendor),\r
+  MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscSystemManufacturer, MiscSystemManufacturer),\r
+  MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscBaseBoardManufacturer, MiscBaseBoardManufacturer),\r
+  MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscChassisManufacturer, MiscChassisManufacturer),\r
+  MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscProcessorCache, MiscProcessorCache),  //type 7\r
+  MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscProcessorInformation, MiscProcessorInformation),  //type 4\r
+  MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscPhysicalMemoryArray, MiscPhysicalMemoryArray),    //Type 16\r
+  MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscMemoryDevice, MiscMemoryDevice), //Type 17\r
+  MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscPortIde1, MiscPortInternalConnectorDesignator),\r
+  MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscPortIde2, MiscPortInternalConnectorDesignator),\r
+  MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscPortAtxPower, MiscPortInternalConnectorDesignator),\r
+  MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscSystemSlotPCIEx16Slot1, MiscSystemSlotDesignation),\r
+  MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscSystemSlotPCIEx16Slot2, MiscSystemSlotDesignation),\r
+  MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscSystemSlotPCIEx4, MiscSystemSlotDesignation),\r
+  MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscSystemSlotPCIEx1Slot1, MiscSystemSlotDesignation),\r
+  MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscSystemSlotPCIEx1Slot2, MiscSystemSlotDesignation),\r
+  MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscSystemSlotPCIEx1Slot3, MiscSystemSlotDesignation),\r
+  MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscSystemSlotPCI1, MiscSystemSlotDesignation),\r
+  MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscSystemSlotPCI2, MiscSystemSlotDesignation),\r
+  MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscSystemSlotPCI3, MiscSystemSlotDesignation),\r
+#if defined( ALWAYS_DISABLE_ONBOARD_VIDEO ) && \\r
+    ( ALWAYS_DISABLE_ONBOARD_VIDEO != 0 )\r
+  MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscOnboardDeviceNetwork, MiscOnboardDevice),\r
+  MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscOnboardDeviceAudio, MiscOnboardDevice),\r
+#else\r
+  MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscOnboardDeviceVideo, MiscOnboardDevice),\r
+  MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(MiscOnboardDeviceAudio, MiscOnboardDevice),\r
+#endif\r
+  MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(SystemLanguageString, SystemLanguageString),\r
+  MISC_SMBIOS_TABLE_ENTRY_DATA_AND_FUNCTION(BootInformationStatus, BootInformationStatus),\r
+};\r
+\r
+//\r
+// Number of Data Table entries.\r
+//\r
+UINTN mMiscSubclassDataTableEntries =\r
+        (sizeof mMiscSubclassDataTable) / sizeof(EFI_MISC_SMBIOS_DATA_TABLE);\r

diff --git a/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscSubclassDriverEntryPoint.c b/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscSubclassDriverEntryPoint.c
new file mode 100644 (file)
index 0000000..cae5a8e
--- /dev/null
+++ b/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscSubclassDriverEntryPoint.c
@@ -0,0 +1,174 @@
+/** @file\r
+\r
+Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+\r
+Module Name:\r
+\r
+  MiscSubclassDriverEntryPoint.c\r
+\r
+Abstract:\r
+\r
+  This driver parses the mMiscSubclassDataTable structure and reports\r
+  any generated data to the DataHub.\r
+\r
+\r
+**/\r
+\r
+\r
+#include "CommonHeader.h"\r
+\r
+#include "MiscSubclassDriver.h"\r
+#include <Protocol/HiiString.h>\r
+\r
+EFI_HII_HANDLE  mHiiHandle;\r
+EFI_HII_STRING_PROTOCOL  *mHiiString;\r
+\r
+\r
+EFI_STRING\r
+EFIAPI\r
+SmbiosMiscGetString (\r
+  IN EFI_STRING_ID   StringId\r
+  ){\r
+\r
+  EFI_STATUS  Status;\r
+  UINTN       StringSize;\r
+  CHAR16      TempString;\r
+  EFI_STRING  String;\r
+  String             = NULL;\r
+\r
+  //\r
+  // Retrieve the size of the string in the string package for the BestLanguage\r
+  //\r
+  StringSize = 0;\r
+  Status = mHiiString->GetString (\r
+                         mHiiString,\r
+                         "en-US",\r
+                         mHiiHandle,\r
+                         StringId,\r
+                         &TempString,\r
+                         &StringSize,\r
+                         NULL\r
+                         );\r
+  //\r
+  // If GetString() returns EFI_SUCCESS for a zero size,\r
+  // then there are no supported languages registered for HiiHandle.  If GetString()\r
+  // returns an error other than EFI_BUFFER_TOO_SMALL, then HiiHandle is not present\r
+  // in the HII Database\r
+  //\r
+  if (Status != EFI_BUFFER_TOO_SMALL) {\r
+    goto Error;\r
+  }\r
+\r
+  //\r
+  // Allocate a buffer for the return string\r
+  //\r
+  String = AllocateZeroPool (StringSize);\r
+  if (String == NULL) {\r
+    goto Error;\r
+  }\r
+\r
+  //\r
+  // Retrieve the string from the string package\r
+  //\r
+  Status = mHiiString->GetString (\r
+                         mHiiString,\r
+                         "en-US",\r
+                         mHiiHandle,\r
+                         StringId,\r
+                         String,\r
+                         &StringSize,\r
+                         NULL\r
+                         );\r
+  if (EFI_ERROR (Status)) {\r
+    //\r
+    // Free the buffer and return NULL if the supported languages can not be retrieved.\r
+    //\r
+    FreePool (String);\r
+    String = NULL;\r
+  }\r
+Error:\r
+\r
+  return String;\r
+}\r
+\r
+/**\r
+  Standard EFI driver point.  This driver parses the mMiscSubclassDataTable\r
+  structure and reports any generated data to the DataHub.\r
+\r
+  @param ImageHandle   - Handle for the image of this driver\r
+  @param SystemTable   - Pointer to the EFI System Table\r
+\r
+  @retval EFI_SUCCESS      - The data was successfully reported to the Data Hub.\r
+  @retval EFI_DEVICE_ERROR - Can not locate any protocols\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+MiscSubclassDriverEntryPoint (\r
+  IN EFI_HANDLE         ImageHandle,\r
+  IN EFI_SYSTEM_TABLE   *SystemTable\r
+  )\r
+{\r
+  UINTN                Index;\r
+  EFI_STATUS           EfiStatus;\r
+  EFI_SMBIOS_PROTOCOL  *Smbios;\r
+\r
+  //\r
+  // Retrieve the pointer to the UEFI HII String Protocol\r
+  //\r
+  EfiStatus = gBS->LocateProtocol (\r
+                     &gEfiHiiStringProtocolGuid,\r
+                     NULL,\r
+                     (VOID **) &mHiiString\r
+                     );\r
+  ASSERT_EFI_ERROR (EfiStatus);\r
+\r
+  EfiStatus = gBS->LocateProtocol(\r
+                     &gEfiSmbiosProtocolGuid,\r
+                     NULL,\r
+                     (VOID**)&Smbios\r
+                     );\r
+\r
+  if (EFI_ERROR(EfiStatus)) {\r
+    DEBUG((EFI_D_ERROR, "Could not locate SMBIOS protocol.  %r\n", EfiStatus));\r
+    return EfiStatus;\r
+  }\r
+\r
+  mHiiHandle = HiiAddPackages (\r
+                 &gEfiCallerIdGuid,\r
+                 NULL,\r
+                 MiscSubclassStrings,\r
+                 NULL\r
+                 );\r
+  ASSERT (mHiiHandle != NULL);\r
+\r
+  for (Index = 0; Index < mMiscSubclassDataTableEntries; ++Index) {\r
+    //\r
+    // If the entry have a function pointer, just log the data.\r
+    //\r
+    if (mMiscSubclassDataTable[Index].Function != NULL) {\r
+      EfiStatus = (*mMiscSubclassDataTable[Index].Function)(\r
+        mMiscSubclassDataTable[Index].RecordData,\r
+        Smbios\r
+        );\r
+\r
+      if (EFI_ERROR(EfiStatus)) {\r
+        DEBUG((EFI_D_ERROR, "Misc smbios store error.  Index=%d, ReturnStatus=%r\n", Index, EfiStatus));\r
+        return EfiStatus;\r
+      }\r
+    }\r
+  }\r
+\r
+  return EfiStatus;\r
+}\r
+\r

diff --git a/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscSystemLanguageString.uni b/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscSystemLanguageString.uni
new file mode 100644 (file)
index 0000000..763a11f
Binary files /dev/null and b/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscSystemLanguageString.uni differ

diff --git a/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscSystemLanguageStringData.c b/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscSystemLanguageStringData.c
new file mode 100644 (file)
index 0000000..6108697
--- /dev/null
+++ b/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscSystemLanguageStringData.c
@@ -0,0 +1,39 @@
+/** @file\r
+\r
+Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+\r
+Module Name:\r
+\r
+  MiscSystemLanguageStringData.c\r
+\r
+Abstract:\r
+\r
+  Static data of System language string information.\r
+  System language string information is Misc. subclass type 12 and SMBIOS type 13.\r
+\r
+\r
+**/\r
+\r
+\r
+#include "CommonHeader.h"\r
+\r
+#include "MiscSubclassDriver.h"\r
+\r
+//\r
+// Static (possibly build generated) Bios Vendor data.\r
+//\r
+MISC_SMBIOS_TABLE_DATA(EFI_MISC_SYSTEM_LANGUAGE_STRING_DATA, SystemLanguageString)\r
+= {\r
+  0,\r
+  STRING_TOKEN(STR_MISC_SYSTEM_LANGUAGE_EN_US)\r
+};\r

diff --git a/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscSystemLanguageStringFunction.c b/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscSystemLanguageStringFunction.c
new file mode 100644 (file)
index 0000000..c4494c3
--- /dev/null
+++ b/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscSystemLanguageStringFunction.c
@@ -0,0 +1,98 @@
+/*++\r
+\r
+Copyright (c) 2009 - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+Module Name:\r
+\r
+  MiscResetCapabilitiesFunction.c\r
+\r
+Abstract:\r
+\r
+  ResetCapabilities.\r
+  SMBIOS type 23.\r
+\r
+--*/\r
+\r
+\r
+#include "CommonHeader.h"\r
+\r
+#include "MiscSubclassDriver.h"\r
+/**\r
+  This function makes boot time changes to the contents of the\r
+  MiscOemString (Type 11).\r
+\r
+  @param  RecordData                 Pointer to copy of RecordData from the Data Table.\r
+\r
+  @retval EFI_SUCCESS                All parameters were valid.\r
+  @retval EFI_UNSUPPORTED            Unexpected RecordType value.\r
+  @retval EFI_INVALID_PARAMETER      Invalid parameter was found.\r
+\r
+**/\r
+\r
+MISC_SMBIOS_TABLE_FUNCTION(SystemLanguageString)\r
+{\r
+  EFI_STATUS               Status;\r
+  EFI_SMBIOS_HANDLE        SmbiosHandle;\r
+  SMBIOS_TABLE_TYPE13      *SmbiosRecord;\r
+  UINTN                    StrLeng;\r
+  CHAR8                    *OptionalStrStart;\r
+  EFI_STRING               Str;\r
+  STRING_REF               TokenToGet;\r
+\r
+\r
+  //\r
+  // First check for invalid parameters.\r
+  //\r
+  if (RecordData == NULL) {\r
+    return EFI_INVALID_PARAMETER;\r
+  }\r
+\r
+  TokenToGet = STRING_TOKEN (STR_MISC_SYSTEM_LANGUAGE_EN_US);\r
+  Str = SmbiosMiscGetString (TokenToGet);\r
+  StrLeng = StrLen(Str);\r
+  if (StrLeng > SMBIOS_STRING_MAX_LENGTH) {\r
+    return EFI_UNSUPPORTED;\r
+  }\r
+\r
+  //\r
+  // Two zeros following the last string.\r
+  //\r
+  SmbiosRecord = AllocatePool(sizeof (SMBIOS_TABLE_TYPE13) + StrLeng + 1 + 1);\r
+  ZeroMem(SmbiosRecord, sizeof (SMBIOS_TABLE_TYPE13) + StrLeng + 1 + 1);\r
+\r
+  SmbiosRecord->Hdr.Type = EFI_SMBIOS_TYPE_BIOS_LANGUAGE_INFORMATION;\r
+  SmbiosRecord->Hdr.Length = sizeof (SMBIOS_TABLE_TYPE13);\r
+\r
+  //\r
+  // Make handle chosen by smbios protocol.add automatically.\r
+  //\r
+  SmbiosRecord->Hdr.Handle    = 0;\r
+  SmbiosRecord->InstallableLanguages = 1;\r
+  SmbiosRecord->Flags   = 1;\r
+  SmbiosRecord->CurrentLanguages = 1;\r
+  OptionalStrStart = (CHAR8 *)(SmbiosRecord + 1);\r
+  UnicodeStrToAsciiStr(Str, OptionalStrStart);\r
+\r
+  //\r
+  // Now we have got the full smbios record, call smbios protocol to add this record.\r
+  //\r
+  SmbiosHandle = SMBIOS_HANDLE_PI_RESERVED;\r
+  Status = Smbios-> Add(\r
+                      Smbios,\r
+                      NULL,\r
+                      &SmbiosHandle,\r
+                      (EFI_SMBIOS_TABLE_HEADER *) SmbiosRecord\r
+                      );\r
+  FreePool(SmbiosRecord);\r
+  return Status;\r
+}\r
+\r

diff --git a/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscSystemManufacturer.uni b/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscSystemManufacturer.uni
new file mode 100644 (file)
index 0000000..cf563c8
Binary files /dev/null and b/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscSystemManufacturer.uni differ

diff --git a/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscSystemManufacturerData.c b/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscSystemManufacturerData.c
new file mode 100644 (file)
index 0000000..055eb29
--- /dev/null
+++ b/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscSystemManufacturerData.c
@@ -0,0 +1,53 @@
+/** @file\r
+\r
+Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+\r
+Module Name:\r
+\r
+  MiscSystemManufacturerData.c\r
+\r
+Abstract:\r
+\r
+  Static data of System manufacturer information.\r
+  System manufacturer information is Misc. subclass type 3 and SMBIOS type 1.\r
+\r
+\r
+**/\r
+\r
+\r
+#include "CommonHeader.h"\r
+\r
+#include "MiscSubclassDriver.h"\r
+\r
+//\r
+// Static (possibly build generated) System Manufacturer data.\r
+//\r
+MISC_SMBIOS_TABLE_DATA(EFI_MISC_SYSTEM_MANUFACTURER_DATA, MiscSystemManufacturer)\r
+= {\r
+  STRING_TOKEN(STR_MISC_SYSTEM_MANUFACTURER),  // SystemManufactrurer\r
+  STRING_TOKEN(STR_MISC_SYSTEM_PRODUCT_NAME),  // SystemProductName\r
+  STRING_TOKEN(STR_MISC_SYSTEM_VERSION),       // SystemVersion\r
+  STRING_TOKEN(STR_MISC_SYSTEM_SERIAL_NUMBER), // SystemSerialNumber\r
+  {                                            // SystemUuid\r
+       //\r
+    // Undefined GUID but can be programmed later.\r
+    //0xFFFFFFFF, 0xFFFF, 0xFFFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF\r
+\r
+    // Undefined GUID that cannot be programmed later.\r
+    //0x00000000, 0x0000, 0x0000, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00\r
+       // TODO Hard code here for WHCT test.\r
+       0xa5000288, 0x6462, 0x4524, 0x98, 0x6a, 0x9b, 0x77, 0x37, 0xe3, 0x15, 0xcf\r
+       //\r
+  },\r
+  EfiSystemWakeupTypePowerSwitch  // SystemWakeupType\r
+};\r

diff --git a/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscSystemManufacturerFunction.c b/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscSystemManufacturerFunction.c
new file mode 100644 (file)
index 0000000..ff08b5b
--- /dev/null
+++ b/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscSystemManufacturerFunction.c
@@ -0,0 +1,353 @@
+/*++
+
+Copyright (c) 2009 - 2014, Intel Corporation. All rights reserved.<BR>
+                                                                                   
+  This program and the accompanying materials are licensed and made available under
+  the terms and conditions of the BSD License that accompanies this distribution.  
+  The full text of the license may be found at                                     
+  http://opensource.org/licenses/bsd-license.php.                                  
+                                                                                   
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    
+                                                                                   
+
+
+Module Name:
+
+  MiscSystemManufacturerFunction.c
+
+Abstract:
+
+  This driver parses the mMiscSubclassDataTable structure and reports
+  any generated data.
+
+--*/
+
+
+#include "CommonHeader.h"
+#include "MiscSubclassDriver.h"
+#include <Protocol/DxeSmmReadyToLock.h>
+#include <Library/NetLib.h>
+#include "Library/DebugLib.h"
+#include <Uefi/UefiBaseType.h>
+
+/**
+
+  Publish the smbios type 1.
+
+  @param Event      Event whose notification function is being invoked (gEfiDxeSmmReadyToLockProtocolGuid).
+  @param Context    Pointer to the notification functions context, which is implementation dependent.
+
+  @retval None
+
+**/
+EFI_STATUS
+EFIAPI
+AddSmbiosManuCallback (
+  IN EFI_EVENT  Event,
+  IN VOID       *Context
+  )
+{
+
+  CHAR8                             *OptionalStrStart;
+  UINTN                             ManuStrLen;
+  UINTN                             VerStrLen;
+  UINTN                             PdNameStrLen;
+  UINTN                             SerialNumStrLen;
+  UINTN                             SkuNumberStrLen;
+  UINTN                                                FamilyNameStrLen;
+  EFI_STATUS                        Status;
+  EFI_STRING                        Manufacturer;
+  EFI_STRING                        ProductName;
+  EFI_STRING                        Version;
+  EFI_STRING                        SerialNumber;
+  EFI_STRING                        SkuNumber;
+  EFI_STRING                               FamilyName;
+  STRING_REF                        TokenToGet;
+  EFI_SMBIOS_HANDLE                 SmbiosHandle;
+  SMBIOS_TABLE_TYPE1                *SmbiosRecord;
+  EFI_MISC_SYSTEM_MANUFACTURER      *ForType1InputData;
+  EFI_SMBIOS_PROTOCOL               *Smbios;
+  CHAR16                            Buffer[40];
+  
+  CHAR16                          *MacStr; 
+  EFI_HANDLE                      *Handles;
+  UINTN                           BufferSize;
+
+  ForType1InputData = (EFI_MISC_SYSTEM_MANUFACTURER *)Context;
+
+  //
+  // First check for invalid parameters.
+  //
+  if (Context == NULL) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  Status = gBS->LocateProtocol (&gEfiSmbiosProtocolGuid, NULL, (VOID *) &Smbios);
+  ASSERT_EFI_ERROR (Status);
+
+  //
+  // Silicon Steppings
+  //
+  switch (PchStepping()) {
+    case PchA0:
+      UnicodeSPrint (Buffer, sizeof (Buffer),L"%s",L"MinnowBoard MAX A0 PLATFORM");
+      HiiSetString(mHiiHandle,STRING_TOKEN(STR_MISC_SYSTEM_PRODUCT_NAME), Buffer, NULL);
+      UnicodeSPrint (Buffer, sizeof (Buffer),L"%s",L"A0");
+      HiiSetString(mHiiHandle,STRING_TOKEN(STR_MISC_SYSTEM_VERSION), Buffer, NULL);
+      DEBUG ((EFI_D_ERROR, "A0 Stepping Detected\n"));
+      break;
+    case PchA1:
+      UnicodeSPrint (Buffer, sizeof (Buffer),L"%s",L"MinnowBoard MAX A1 PLATFORM");
+      HiiSetString(mHiiHandle,STRING_TOKEN(STR_MISC_SYSTEM_PRODUCT_NAME), Buffer, NULL);
+      UnicodeSPrint (Buffer, sizeof (Buffer),L"%s",L"A1");
+      HiiSetString(mHiiHandle,STRING_TOKEN(STR_MISC_SYSTEM_VERSION), Buffer, NULL);
+      DEBUG ((EFI_D_ERROR, "A1 Stepping Detected\n"));
+      break;
+    case PchB0:
+      UnicodeSPrint (Buffer, sizeof (Buffer),L"%s",L"MinnowBoard MAX B0 PLATFORM");
+      HiiSetString(mHiiHandle,STRING_TOKEN(STR_MISC_SYSTEM_PRODUCT_NAME), Buffer, NULL);
+      UnicodeSPrint (Buffer, sizeof (Buffer),L"%s",L"B0");
+      HiiSetString(mHiiHandle,STRING_TOKEN(STR_MISC_SYSTEM_VERSION), Buffer, NULL);
+      DEBUG ((EFI_D_ERROR, "B0 Stepping Detected\n"));
+      break;
+    case PchB1:
+      UnicodeSPrint (Buffer, sizeof (Buffer),L"%s",L"MinnowBoard MAX B1 PLATFORM");
+      HiiSetString(mHiiHandle,STRING_TOKEN(STR_MISC_SYSTEM_PRODUCT_NAME), Buffer, NULL);
+      UnicodeSPrint (Buffer, sizeof (Buffer),L"%s",L"B1");
+      HiiSetString(mHiiHandle,STRING_TOKEN(STR_MISC_SYSTEM_VERSION), Buffer, NULL);
+      DEBUG ((EFI_D_ERROR, "B1 Stepping Detected\n"));
+      break;
+    case PchB2:
+      UnicodeSPrint (Buffer, sizeof (Buffer),L"%s",L"MinnowBoard MAX B2 PLATFORM");
+      HiiSetString(mHiiHandle,STRING_TOKEN(STR_MISC_SYSTEM_PRODUCT_NAME), Buffer, NULL);
+      UnicodeSPrint (Buffer, sizeof (Buffer),L"%s",L"B2");
+      HiiSetString(mHiiHandle,STRING_TOKEN(STR_MISC_SYSTEM_VERSION), Buffer, NULL);
+      DEBUG ((EFI_D_ERROR, "B2 Stepping Detected\n"));
+      break;
+    case PchB3:
+      UnicodeSPrint (Buffer, sizeof (Buffer),L"%s",L"MinnowBoard MAX B3 PLATFORM");
+      HiiSetString(mHiiHandle,STRING_TOKEN(STR_MISC_SYSTEM_PRODUCT_NAME), Buffer, NULL);
+      UnicodeSPrint (Buffer, sizeof (Buffer),L"%s",L"B3");
+      HiiSetString(mHiiHandle,STRING_TOKEN(STR_MISC_SYSTEM_VERSION), Buffer, NULL);
+      DEBUG ((EFI_D_ERROR, "B3 Stepping Detected\n"));
+      break;
+    case PchC0:
+      UnicodeSPrint (Buffer, sizeof (Buffer),L"%s",L"MinnowBoard MAX C0 PLATFORM");
+      HiiSetString(mHiiHandle,STRING_TOKEN(STR_MISC_SYSTEM_PRODUCT_NAME), Buffer, NULL);
+      UnicodeSPrint (Buffer, sizeof (Buffer),L"%s",L"C0");
+      HiiSetString(mHiiHandle,STRING_TOKEN(STR_MISC_SYSTEM_VERSION), Buffer, NULL);
+      DEBUG ((EFI_D_ERROR, "C0 Stepping Detected\n"));
+      break;
+   case PchD0:
+      UnicodeSPrint (Buffer, sizeof (Buffer),L"%s",L"MinnowBoard MAX D0 PLATFORM");
+      HiiSetString(mHiiHandle,STRING_TOKEN(STR_MISC_SYSTEM_PRODUCT_NAME), Buffer, NULL);
+      UnicodeSPrint (Buffer, sizeof (Buffer),L"%s",L"D0");
+      HiiSetString(mHiiHandle,STRING_TOKEN(STR_MISC_SYSTEM_VERSION), Buffer, NULL);
+      DEBUG ((EFI_D_ERROR, "D0 Stepping Detected\n"));
+      break;
+    default:
+      DEBUG ((EFI_D_ERROR, "Unknow Stepping Detected\n"));
+      break;
+    }
+
+
+  TokenToGet = STRING_TOKEN (STR_MISC_SYSTEM_MANUFACTURER);
+  Manufacturer = SmbiosMiscGetString (TokenToGet);
+  ManuStrLen = StrLen(Manufacturer);
+  if (ManuStrLen > SMBIOS_STRING_MAX_LENGTH) {
+    return EFI_UNSUPPORTED;
+  }
+
+  TokenToGet = STRING_TOKEN (STR_MISC_SYSTEM_PRODUCT_NAME);
+  ProductName = SmbiosMiscGetString (TokenToGet);
+  PdNameStrLen = StrLen(ProductName);
+  if (PdNameStrLen > SMBIOS_STRING_MAX_LENGTH) {
+    return EFI_UNSUPPORTED;
+  }
+
+  TokenToGet = STRING_TOKEN (STR_MISC_SYSTEM_VERSION);
+  Version = SmbiosMiscGetString (TokenToGet);
+  VerStrLen = StrLen(Version);
+  if (VerStrLen > SMBIOS_STRING_MAX_LENGTH) {
+    return EFI_UNSUPPORTED;
+  }
+
+  //
+  //Get handle infomation
+  //
+  BufferSize = 0;
+  Handles = NULL;
+  Status = gBS->LocateHandle (
+                  ByProtocol, 
+                  &gEfiSimpleNetworkProtocolGuid,
+                  NULL,
+                  &BufferSize,
+                  Handles
+                  );
+
+  if (Status == EFI_BUFFER_TOO_SMALL) {
+       Handles = AllocateZeroPool(BufferSize);
+       if (Handles == NULL) {
+               return (EFI_OUT_OF_RESOURCES);
+       }
+       Status = gBS->LocateHandle(
+                       ByProtocol,
+                       &gEfiSimpleNetworkProtocolGuid,
+                       NULL,
+                       &BufferSize,
+                       Handles
+                       );
+ }
+                       
+  //
+  //Get the MAC string
+  //
+  Status = NetLibGetMacString (
+             *Handles,
+             NULL,
+             &MacStr
+             );
+  if (EFI_ERROR (Status)) {    
+    return Status;
+  }
+  SerialNumber = MacStr; 
+  SerialNumStrLen = StrLen(SerialNumber);
+  if (SerialNumStrLen > SMBIOS_STRING_MAX_LENGTH) {
+    return EFI_UNSUPPORTED;
+  }
+  TokenToGet = STRING_TOKEN (STR_MISC_SYSTEM_SKU_NUMBER);
+  SkuNumber = SmbiosMiscGetString (TokenToGet);
+  SkuNumberStrLen = StrLen(SkuNumber);
+  if (SkuNumberStrLen > SMBIOS_STRING_MAX_LENGTH) {
+    return EFI_UNSUPPORTED;
+  }
+  TokenToGet = STRING_TOKEN (STR_MISC_SYSTEM_FAMILY_NAME1);
+  FamilyName = SmbiosMiscGetString (TokenToGet);
+  FamilyNameStrLen = StrLen(FamilyName);
+  if (FamilyNameStrLen > SMBIOS_STRING_MAX_LENGTH) {
+    return EFI_UNSUPPORTED;
+  }
+
+  //
+  // Two zeros following the last string.
+  //
+  SmbiosRecord = AllocatePool(sizeof (SMBIOS_TABLE_TYPE1) + ManuStrLen + 1 + PdNameStrLen + 1 + VerStrLen + 1 + SerialNumStrLen + 1 + SkuNumberStrLen + 1 + FamilyNameStrLen + 1 + 1);
+  ZeroMem(SmbiosRecord, sizeof (SMBIOS_TABLE_TYPE1) + ManuStrLen + 1 + PdNameStrLen + 1 + VerStrLen + 1 + SerialNumStrLen + 1 + SkuNumberStrLen + 1 + FamilyNameStrLen + 1 + 1);
+
+  SmbiosRecord->Hdr.Type = EFI_SMBIOS_TYPE_SYSTEM_INFORMATION;
+  SmbiosRecord->Hdr.Length = sizeof (SMBIOS_TABLE_TYPE1);
+
+  //
+  // Make handle chosen by smbios protocol.add automatically.
+  //
+  SmbiosRecord->Hdr.Handle = 0;
+
+  //
+  // Manu will be the 1st optional string following the formatted structure.
+  //
+  SmbiosRecord->Manufacturer = 1;
+
+  //
+  // ProductName will be the 2nd optional string following the formatted structure.
+  //
+  SmbiosRecord->ProductName = 2;
+
+  //
+  // Version will be the 3rd optional string following the formatted structure.
+  //
+  SmbiosRecord->Version = 3;
+
+  //
+  // Version will be the 4th optional string following the formatted structure.
+  //
+  SmbiosRecord->SerialNumber = 4;
+
+  SmbiosRecord->SKUNumber= 5;
+  SmbiosRecord->Family= 6;
+
+  //
+  // Unique UUID
+  //
+  ForType1InputData->SystemUuid.Data1 = PcdGet32 (PcdProductSerialNumber);
+  ForType1InputData->SystemUuid.Data4[0] = PcdGet8 (PcdEmmcManufacturerId);
+
+  CopyMem ((UINT8 *) (&SmbiosRecord->Uuid),&ForType1InputData->SystemUuid,16);
+
+  SmbiosRecord->WakeUpType = (UINT8)ForType1InputData->SystemWakeupType;
+
+  OptionalStrStart = (CHAR8 *)(SmbiosRecord + 1);
+  UnicodeStrToAsciiStr(Manufacturer, OptionalStrStart);
+  UnicodeStrToAsciiStr(ProductName, OptionalStrStart + ManuStrLen + 1);
+  UnicodeStrToAsciiStr(Version, OptionalStrStart + ManuStrLen + 1 + PdNameStrLen + 1);
+  UnicodeStrToAsciiStr(SerialNumber, OptionalStrStart + ManuStrLen + 1 + PdNameStrLen + 1 + VerStrLen + 1);
+
+  UnicodeStrToAsciiStr(SkuNumber, OptionalStrStart + ManuStrLen + 1 + PdNameStrLen + 1 +  VerStrLen + 1 + SerialNumStrLen + 1);
+  UnicodeStrToAsciiStr(FamilyName, OptionalStrStart + ManuStrLen + 1 + PdNameStrLen + 1 + VerStrLen + 1 + SerialNumStrLen + 1 + SkuNumberStrLen +1);
+
+  //
+  // Now we have got the full smbios record, call smbios protocol to add this record.
+  //
+  SmbiosHandle = SMBIOS_HANDLE_PI_RESERVED;
+  Status = Smbios-> Add(
+                      Smbios,
+                      NULL,
+                      &SmbiosHandle,
+                      (EFI_SMBIOS_TABLE_HEADER *) SmbiosRecord
+                      );
+  FreePool(SmbiosRecord);
+  return Status;
+}
+
+/**
+  This function makes boot time changes to the contents of the
+  MiscSystemManufacturer (Type 1).
+
+  @param  RecordData                 Pointer to copy of RecordData from the Data Table.
+
+  @retval EFI_SUCCESS                All parameters were valid.
+  @retval EFI_UNSUPPORTED            Unexpected RecordType value.
+  @retval EFI_INVALID_PARAMETER      Invalid parameter was found.
+
+**/
+MISC_SMBIOS_TABLE_FUNCTION(MiscSystemManufacturer)
+{
+  EFI_STATUS                    Status;
+  static BOOLEAN                CallbackIsInstalledManu = FALSE;
+  VOID                           *AddSmbiosManuCallbackNotifyReg;
+  EFI_EVENT                      AddSmbiosManuCallbackEvent;
+
+
+  if (CallbackIsInstalledManu == FALSE) {
+    CallbackIsInstalledManu = TRUE;            // Prevent more than 1 callback.
+    DEBUG ((EFI_D_INFO, "Create Smbios Manu callback.\n"));
+
+  //
+  // gEfiDxeSmmReadyToLockProtocolGuid is ready
+  //
+  Status = gBS->CreateEvent (
+                  EVT_NOTIFY_SIGNAL,
+                  TPL_CALLBACK,
+                  (EFI_EVENT_NOTIFY)AddSmbiosManuCallback,
+                  RecordData,
+                  &AddSmbiosManuCallbackEvent
+                  );
+
+  ASSERT_EFI_ERROR (Status);
+  if (EFI_ERROR (Status)) {
+    return Status;
+
+  }
+
+  Status = gBS->RegisterProtocolNotify (
+                  &gEfiDxeSmmReadyToLockProtocolGuid,
+                  AddSmbiosManuCallbackEvent,
+                  &AddSmbiosManuCallbackNotifyReg
+                  );
+
+  return Status;
+  }
+
+  return EFI_SUCCESS;
+
+}

diff --git a/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscSystemOptionString.uni b/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscSystemOptionString.uni
new file mode 100644 (file)
index 0000000..696887a
Binary files /dev/null and b/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscSystemOptionString.uni differ

diff --git a/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscSystemOptionStringData.c b/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscSystemOptionStringData.c
new file mode 100644 (file)
index 0000000..8fbaa8a
--- /dev/null
+++ b/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscSystemOptionStringData.c
@@ -0,0 +1,36 @@
+/** @file\r
+\r
+Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+\r
+Module Name:\r
+\r
+  MiscSystemOptionStringData.c\r
+\r
+Abstract:\r
+\r
+  Static data of System option string.\r
+  System option string is Miscellaneous subclass type: 10 and SMBIOS type: 13.\r
+\r
+\r
+**/\r
+\r
+\r
+#include "CommonHeader.h"\r
+\r
+#include "MiscSubclassDriver.h"\r
+\r
+//\r
+// Static (possibly build generated) Bios Vendor data.\r
+//\r
+MISC_SMBIOS_TABLE_DATA(EFI_MISC_SYSTEM_OPTION_STRING_DATA, SystemOptionString)\r
+= { STRING_TOKEN(STR_MISC_SYSTEM_OPTION_EN_US) };\r

diff --git a/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscSystemOptionStringFunction.c b/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscSystemOptionStringFunction.c
new file mode 100644 (file)
index 0000000..414afd3
--- /dev/null
+++ b/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscSystemOptionStringFunction.c
@@ -0,0 +1,98 @@
+/*++\r
+\r
+Copyright (c) 2009 - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+\r
+Module Name:\r
+\r
+  MiscSystemOptionStringFunction.c\r
+\r
+Abstract:\r
+\r
+  BIOS system option string boot time changes.\r
+  SMBIOS type 12.\r
+\r
+--*/\r
+\r
+\r
+#include "CommonHeader.h"\r
+\r
+#include "MiscSubclassDriver.h"\r
+\r
+\r
+/**\r
+  This function makes boot time changes to the contents of the\r
+  MiscSystemOptionString (Type 12).\r
+\r
+  @param  RecordData                 Pointer to copy of RecordData from the Data Table.\r
+\r
+  @retval EFI_SUCCESS                All parameters were valid.\r
+  @retval EFI_UNSUPPORTED            Unexpected RecordType value.\r
+  @retval EFI_INVALID_PARAMETER      Invalid parameter was found.\r
+\r
+**/\r
+MISC_SMBIOS_TABLE_FUNCTION(SystemOptionString)\r
+{\r
+  CHAR8                             *OptionalStrStart;\r
+  UINTN                             OptStrLen;\r
+  EFI_STRING                        OptionString;\r
+  EFI_STATUS                        Status;\r
+  STRING_REF                        TokenToGet;\r
+  EFI_SMBIOS_HANDLE                 SmbiosHandle;\r
+  SMBIOS_TABLE_TYPE12               *SmbiosRecord;\r
+\r
+  //\r
+  // First check for invalid parameters.\r
+  //\r
+  if (RecordData == NULL) {\r
+    return EFI_INVALID_PARAMETER;\r
+  }\r
+\r
+  TokenToGet = STRING_TOKEN (STR_MISC_SYSTEM_OPTION_EN_US);\r
+  OptionString = SmbiosMiscGetString (TokenToGet);\r
+  OptStrLen = StrLen(OptionString);\r
+  if (OptStrLen > SMBIOS_STRING_MAX_LENGTH) {\r
+    return EFI_UNSUPPORTED;\r
+  }\r
+\r
+  //\r
+  // Two zeros following the last string.\r
+  //\r
+  SmbiosRecord = AllocatePool(sizeof (SMBIOS_TABLE_TYPE12) + OptStrLen + 1 + 1);\r
+  ZeroMem(SmbiosRecord, sizeof (SMBIOS_TABLE_TYPE12) + OptStrLen + 1 + 1);\r
+\r
+  SmbiosRecord->Hdr.Type = EFI_SMBIOS_TYPE_SYSTEM_CONFIGURATION_OPTIONS;\r
+  SmbiosRecord->Hdr.Length = sizeof (SMBIOS_TABLE_TYPE12);\r
+\r
+  //\r
+  // Make handle chosen by smbios protocol.add automatically.\r
+  //\r
+  SmbiosRecord->Hdr.Handle = 0;\r
+\r
+  SmbiosRecord->StringCount = 1;\r
+  OptionalStrStart = (CHAR8*) (SmbiosRecord + 1);\r
+  UnicodeStrToAsciiStr(OptionString, OptionalStrStart);\r
+\r
+  //\r
+  // Now we have got the full smbios record, call smbios protocol to add this record.\r
+  //\r
+  SmbiosHandle = SMBIOS_HANDLE_PI_RESERVED;\r
+  Status = Smbios-> Add(\r
+                      Smbios,\r
+                      NULL,\r
+                      &SmbiosHandle,\r
+                      (EFI_SMBIOS_TABLE_HEADER *) SmbiosRecord\r
+                      );\r
+\r
+  FreePool(SmbiosRecord);\r
+  return Status;\r
+}\r

diff --git a/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscSystemSlotDesignation.uni b/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscSystemSlotDesignation.uni
new file mode 100644 (file)
index 0000000..d5470b6
Binary files /dev/null and b/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscSystemSlotDesignation.uni differ

diff --git a/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscSystemSlotDesignationData.c b/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscSystemSlotDesignationData.c
new file mode 100644 (file)
index 0000000..17e69c2
--- /dev/null
+++ b/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscSystemSlotDesignationData.c
@@ -0,0 +1,251 @@
+/** @file\r
+\r
+Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+\r
+Module Name:\r
+\r
+    MiscSystemSlotDesignationData.c\r
+\r
+Abstract:\r
+\r
+  Static data of System Slot Designation.\r
+  System Slot Designation is Misc. subclass type 7 and SMBIOS type 9.\r
+\r
+\r
+**/\r
+\r
+\r
+#include "CommonHeader.h"\r
+\r
+#include "MiscSubclassDriver.h"\r
+\r
+\r
+//\r
+// Static (possibly build generated) Bios Vendor data.\r
+//\r
+MISC_SMBIOS_TABLE_DATA(EFI_MISC_SYSTEM_SLOT_DESIGNATION_DATA, MiscSystemSlotPCIEx16Slot1) = {\r
+  STRING_TOKEN(STR_MISC_SYSTEM_SLOT_PCIEX16_1),    // SlotDesignation\r
+  EfiSlotTypePciExpress,        // SlotType\r
+  EfiSlotDataBusWidth16xOrx16,  // SlotDataBusWidth\r
+  EfiSlotUsageAvailable,        // SlotUsage\r
+  EfiSlotLengthShort,           // SlotLength\r
+  0x06,                         // SlotId\r
+  {                             // SlotCharacteristics\r
+    0,                          // CharacteristicsUnknown  :1;\r
+    0,                          // Provides50Volts         :1;\r
+    1,                          // Provides33Volts         :1;\r
+    0,                          // SharedSlot              :1;\r
+    0,                          // PcCard16Supported       :1;\r
+    0,                          // CardBusSupported        :1;\r
+    0,                          // ZoomVideoSupported      :1;\r
+    0,                          // ModemRingResumeSupported:1;\r
+    0,                          // PmeSignalSupported      :1;\r
+    0,                          // HotPlugDevicesSupported :1;\r
+    0,                          // SmbusSignalSupported    :1;\r
+    0                           // Reserved                :21;\r
+  },\r
+  0                             // SlotDevicePath\r
+};\r
+\r
+MISC_SMBIOS_TABLE_DATA(EFI_MISC_SYSTEM_SLOT_DESIGNATION_DATA, MiscSystemSlotPCIEx16Slot2) = {\r
+  STRING_TOKEN(STR_MISC_SYSTEM_SLOT_PCIEX16_2),    // SlotDesignation\r
+  EfiSlotTypePciExpress,        // SlotType\r
+  EfiSlotDataBusWidth16xOrx16,  // SlotDataBusWidth\r
+  EfiSlotUsageAvailable,        // SlotUsage\r
+  EfiSlotLengthShort,           // SlotLength\r
+  0x04,                         // SlotId\r
+  {                             // SlotCharacteristics\r
+    0,                          // CharacteristicsUnknown  :1;\r
+    0,                          // Provides50Volts         :1;\r
+    1,                          // Provides33Volts         :1;\r
+    0,                          // SharedSlot              :1;\r
+    0,                          // PcCard16Supported       :1;\r
+    0,                          // CardBusSupported        :1;\r
+    0,                          // ZoomVideoSupported      :1;\r
+    0,                          // ModemRingResumeSupported:1;\r
+    0,                          // PmeSignalSupported      :1;\r
+    0,                          // HotPlugDevicesSupported :1;\r
+    0,                          // SmbusSignalSupported    :1;\r
+    0                           // Reserved                :21;\r
+  },\r
+  0                             // SlotDevicePath\r
+};\r
+\r
+MISC_SMBIOS_TABLE_DATA(EFI_MISC_SYSTEM_SLOT_DESIGNATION_DATA, MiscSystemSlotPCIEx4) = {\r
+  STRING_TOKEN(STR_MISC_SYSTEM_SLOT_PCIEX4),    // SlotDesignation\r
+  EfiSlotTypePciExpress,        // SlotType\r
+  EfiSlotDataBusWidth4xOrx4,  // SlotDataBusWidth\r
+  EfiSlotUsageAvailable,        // SlotUsage\r
+  EfiSlotLengthShort,           // SlotLength\r
+  0x03,                         // SlotId\r
+  {                             // SlotCharacteristics\r
+    0,                          // CharacteristicsUnknown  :1;\r
+    0,                          // Provides50Volts         :1;\r
+    1,                          // Provides33Volts         :1;\r
+    0,                          // SharedSlot              :1;\r
+    0,                          // PcCard16Supported       :1;\r
+    0,                          // CardBusSupported        :1;\r
+    0,                          // ZoomVideoSupported      :1;\r
+    0,                          // ModemRingResumeSupported:1;\r
+    0,                          // PmeSignalSupported      :1;\r
+    0,                          // HotPlugDevicesSupported :1;\r
+    0,                          // SmbusSignalSupported    :1;\r
+    0                           // Reserved                :21;\r
+  },\r
+  0                             // SlotDevicePath\r
+};\r
+\r
+MISC_SMBIOS_TABLE_DATA(EFI_MISC_SYSTEM_SLOT_DESIGNATION_DATA, MiscSystemSlotPCIEx1Slot1) = {\r
+  STRING_TOKEN(STR_MISC_SYSTEM_SLOT_PCIEX1_1),    // SlotDesignation\r
+  EfiSlotTypePciExpress,        // SlotType\r
+  EfiSlotDataBusWidth1xOrx1,    // SlotDataBusWidth\r
+  EfiSlotUsageAvailable,        // SlotUsage\r
+  EfiSlotLengthShort,           // SlotLength\r
+  0x02,                         // SlotId\r
+  {                             // SlotCharacteristics\r
+    0,                          // CharacteristicsUnknown  :1;\r
+    0,                          // Provides50Volts         :1;\r
+    1,                          // Provides33Volts         :1;\r
+    0,                          // SharedSlot              :1;\r
+    0,                          // PcCard16Supported       :1;\r
+    0,                          // CardBusSupported        :1;\r
+    0,                          // ZoomVideoSupported      :1;\r
+    0,                          // ModemRingResumeSupported:1;\r
+    1,                          // PmeSignalSupported      :1;\r
+    0,                          // HotPlugDevicesSupported :1;\r
+    1,                          // SmbusSignalSupported    :1;\r
+    0                           // Reserved                :21;\r
+  },\r
+  0                             // SlotDevicePath\r
+};\r
+\r
+MISC_SMBIOS_TABLE_DATA(EFI_MISC_SYSTEM_SLOT_DESIGNATION_DATA, MiscSystemSlotPCIEx1Slot2) = {\r
+  STRING_TOKEN(STR_MISC_SYSTEM_SLOT_PCIEX1_2),    // SlotDesignation\r
+  EfiSlotTypePciExpress,        // SlotType\r
+  EfiSlotDataBusWidth1xOrx1,    // SlotDataBusWidth\r
+  EfiSlotUsageAvailable,        // SlotUsage\r
+  EfiSlotLengthShort,           // SlotLength\r
+  0x15,                         // SlotId\r
+  {                             // SlotCharacteristics\r
+    0,                          // CharacteristicsUnknown  :1;\r
+    0,                          // Provides50Volts         :1;\r
+    1,                          // Provides33Volts         :1;\r
+    0,                          // SharedSlot              :1;\r
+    0,                          // PcCard16Supported       :1;\r
+    0,                          // CardBusSupported        :1;\r
+    0,                          // ZoomVideoSupported      :1;\r
+    0,                          // ModemRingResumeSupported:1;\r
+    1,                          // PmeSignalSupported      :1;\r
+    0,                          // HotPlugDevicesSupported :1;\r
+    1,                          // SmbusSignalSupported    :1;\r
+    0                           // Reserved                :21;\r
+  },\r
+  0                             // SlotDevicePath\r
+};\r
+\r
+MISC_SMBIOS_TABLE_DATA(EFI_MISC_SYSTEM_SLOT_DESIGNATION_DATA, MiscSystemSlotPCIEx1Slot3) = {\r
+  STRING_TOKEN(STR_MISC_SYSTEM_SLOT_PCIEX1_3),    // SlotDesignation\r
+  EfiSlotTypePciExpress,        // SlotType\r
+  EfiSlotDataBusWidth1xOrx1,    // SlotDataBusWidth\r
+  EfiSlotUsageAvailable,        // SlotUsage\r
+  EfiSlotLengthShort,           // SlotLength\r
+  0x16,                         // SlotId\r
+  {                             // SlotCharacteristics\r
+    0,                          // CharacteristicsUnknown  :1;\r
+    0,                          // Provides50Volts         :1;\r
+    1,                          // Provides33Volts         :1;\r
+    0,                          // SharedSlot              :1;\r
+    0,                          // PcCard16Supported       :1;\r
+    0,                          // CardBusSupported        :1;\r
+    0,                          // ZoomVideoSupported      :1;\r
+    0,                          // ModemRingResumeSupported:1;\r
+    1,                          // PmeSignalSupported      :1;\r
+    0,                          // HotPlugDevicesSupported :1;\r
+    1,                          // SmbusSignalSupported    :1;\r
+    0                           // Reserved                :21;\r
+  },\r
+  0                             // SlotDevicePath\r
+};\r
+\r
+MISC_SMBIOS_TABLE_DATA(EFI_MISC_SYSTEM_SLOT_DESIGNATION_DATA, MiscSystemSlotPCI1) = {\r
+  STRING_TOKEN(STR_MISC_SYSTEM_SLOT_PCI1),    // SlotDesignation\r
+  EfiSlotTypePci,               // SlotType\r
+  EfiSlotDataBusWidth32Bit,     // SlotDataBusWidth\r
+  EfiSlotUsageAvailable,        // SlotUsage\r
+  EfiSlotLengthLong ,           // SlotLength\r
+  0x07,                         // SlotId\r
+  {                             // SlotCharacteristics\r
+    0,                          // CharacteristicsUnknown  :1;\r
+    0,                          // Provides50Volts         :1;\r
+    1,                          // Provides33Volts         :1;\r
+    0,                          // SharedSlot              :1;\r
+    0,                          // PcCard16Supported       :1;\r
+    0,                          // CardBusSupported        :1;\r
+    0,                          // ZoomVideoSupported      :1;\r
+    0,                          // ModemRingResumeSupported:1;\r
+    1,                          // PmeSignalSupported      :1;\r
+    0,                          // HotPlugDevicesSupported :1;\r
+    1,                          // SmbusSignalSupported    :1;\r
+    0                           // Reserved                :21;\r
+  },\r
+  0                             // SlotDevicePath\r
+};\r
+\r
+MISC_SMBIOS_TABLE_DATA(EFI_MISC_SYSTEM_SLOT_DESIGNATION_DATA, MiscSystemSlotPCI2) = {\r
+  STRING_TOKEN(STR_MISC_SYSTEM_SLOT_PCI2),    // SlotDesignation\r
+  EfiSlotTypePci,               // SlotType\r
+  EfiSlotDataBusWidth32Bit,     // SlotDataBusWidth\r
+  EfiSlotUsageAvailable,        // SlotUsage\r
+  EfiSlotLengthLong ,           // SlotLength\r
+  0x18,                         // SlotId\r
+  {                             // SlotCharacteristics\r
+    0,                          // CharacteristicsUnknown  :1;\r
+    0,                          // Provides50Volts         :1;\r
+    1,                          // Provides33Volts         :1;\r
+    0,                          // SharedSlot              :1;\r
+    0,                          // PcCard16Supported       :1;\r
+    0,                          // CardBusSupported        :1;\r
+    0,                          // ZoomVideoSupported      :1;\r
+    0,                          // ModemRingResumeSupported:1;\r
+    1,                          // PmeSignalSupported      :1;\r
+    0,                          // HotPlugDevicesSupported :1;\r
+    1,                          // SmbusSignalSupported    :1;\r
+    0                           // Reserved                :21;\r
+  },\r
+  0                             // SlotDevicePath\r
+};\r
+\r
+MISC_SMBIOS_TABLE_DATA(EFI_MISC_SYSTEM_SLOT_DESIGNATION_DATA, MiscSystemSlotPCI3) = {\r
+  STRING_TOKEN(STR_MISC_SYSTEM_SLOT_PCI3),    // SlotDesignation\r
+  EfiSlotTypePci,               // SlotType\r
+  EfiSlotDataBusWidth32Bit,     // SlotDataBusWidth\r
+  EfiSlotUsageAvailable,        // SlotUsage\r
+  EfiSlotLengthLong ,           // SlotLength\r
+  0x17,                         // SlotId\r
+  {                             // SlotCharacteristics\r
+    0,                          // CharacteristicsUnknown  :1;\r
+    0,                          // Provides50Volts         :1;\r
+    1,                          // Provides33Volts         :1;\r
+    0,                          // SharedSlot              :1;\r
+    0,                          // PcCard16Supported       :1;\r
+    0,                          // CardBusSupported        :1;\r
+    0,                          // ZoomVideoSupported      :1;\r
+    0,                          // ModemRingResumeSupported:1;\r
+    1,                          // PmeSignalSupported      :1;\r
+    0,                          // HotPlugDevicesSupported :1;\r
+    1,                          // SmbusSignalSupported    :1;\r
+    0                           // Reserved                :21;\r
+  },\r
+  0                             // SlotDevicePath\r
+};\r
+\r

diff --git a/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscSystemSlotDesignationFunction.c b/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscSystemSlotDesignationFunction.c
new file mode 100644 (file)
index 0000000..30be4ad
--- /dev/null
+++ b/Vlv2TbltDevicePkg/SmBiosMiscDxe/MiscSystemSlotDesignationFunction.c
@@ -0,0 +1,132 @@
+/*++\r
+\r
+Copyright (c) 2009 - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+\r
+Module Name:\r
+\r
+  MiscSystemSlotDesignatorFunction.c\r
+\r
+Abstract:\r
+\r
+  BIOS system slot designator information boot time changes.\r
+  SMBIOS type 9.\r
+\r
+--*/\r
+\r
+#include "MiscSubclassDriver.h"\r
+\r
+/**\r
+  This function makes boot time changes to the contents of the\r
+  MiscSystemSlotDesignator structure (Type 9).\r
+\r
+  @param  RecordData                 Pointer to copy of RecordData from the Data Table.\r
+\r
+  @retval EFI_SUCCESS                All parameters were valid.\r
+  @retval EFI_UNSUPPORTED            Unexpected RecordType value.\r
+  @retval EFI_INVALID_PARAMETER      Invalid parameter was found.\r
+\r
+**/\r
+MISC_SMBIOS_TABLE_FUNCTION(MiscSystemSlotDesignation)\r
+{\r
+  CHAR8                              *OptionalStrStart;\r
+  UINTN                              SlotDesignationStrLen;\r
+  EFI_STATUS                         Status;\r
+  EFI_STRING                         SlotDesignation;\r
+  STRING_REF                         TokenToGet;\r
+  SMBIOS_TABLE_TYPE9                 *SmbiosRecord;\r
+  EFI_SMBIOS_HANDLE                  SmbiosHandle;\r
+  EFI_MISC_SYSTEM_SLOT_DESIGNATION*  ForType9InputData;\r
+\r
+  ForType9InputData = (EFI_MISC_SYSTEM_SLOT_DESIGNATION *)RecordData;\r
+\r
+  //\r
+  // First check for invalid parameters.\r
+  //\r
+  if (RecordData == NULL) {\r
+    return EFI_INVALID_PARAMETER;\r
+  }\r
+\r
+  TokenToGet = 0;\r
+  switch (ForType9InputData->SlotDesignation) {\r
+    case STR_MISC_SYSTEM_SLOT_PCIEX16_1:\r
+      TokenToGet = STRING_TOKEN (STR_MISC_SYSTEM_SLOT_PCIEX16_1);\r
+      break;\r
+    case STR_MISC_SYSTEM_SLOT_PCIEX16_2:\r
+      TokenToGet = STRING_TOKEN (STR_MISC_SYSTEM_SLOT_PCIEX16_2);\r
+      break;\r
+    case STR_MISC_SYSTEM_SLOT_PCIEX4:\r
+      TokenToGet = STRING_TOKEN (STR_MISC_SYSTEM_SLOT_PCIEX4);\r
+      break;\r
+    case STR_MISC_SYSTEM_SLOT_PCIEX1_1:\r
+      TokenToGet = STRING_TOKEN (STR_MISC_SYSTEM_SLOT_PCIEX1_1);\r
+      break;\r
+    case STR_MISC_SYSTEM_SLOT_PCIEX1_2:\r
+      TokenToGet = STRING_TOKEN (STR_MISC_SYSTEM_SLOT_PCIEX1_2);\r
+      break;\r
+    case STR_MISC_SYSTEM_SLOT_PCIEX1_3:\r
+      TokenToGet = STRING_TOKEN (STR_MISC_SYSTEM_SLOT_PCIEX1_3);\r
+      break;\r
+    case STR_MISC_SYSTEM_SLOT_PCI1:\r
+      TokenToGet = STRING_TOKEN (STR_MISC_SYSTEM_SLOT_PCI1);\r
+      break;\r
+    case STR_MISC_SYSTEM_SLOT_PCI2:\r
+      TokenToGet = STRING_TOKEN (STR_MISC_SYSTEM_SLOT_PCI2);\r
+      break;\r
+    case STR_MISC_SYSTEM_SLOT_PCI3:\r
+      TokenToGet = STRING_TOKEN (STR_MISC_SYSTEM_SLOT_PCI3);\r
+      break;\r
+    default:\r
+      break;\r
+  }\r
+\r
+  SlotDesignation = SmbiosMiscGetString (TokenToGet);\r
+  SlotDesignationStrLen = StrLen(SlotDesignation);\r
+  if (SlotDesignationStrLen > SMBIOS_STRING_MAX_LENGTH) {\r
+    return EFI_UNSUPPORTED;\r
+  }\r
+\r
+  //\r
+  // Two zeros following the last string.\r
+  //\r
+  SmbiosRecord = AllocatePool(sizeof (SMBIOS_TABLE_TYPE9) + SlotDesignationStrLen + 1 + 1);\r
+  ZeroMem(SmbiosRecord, sizeof (SMBIOS_TABLE_TYPE9) +SlotDesignationStrLen + 1 + 1);\r
+\r
+  SmbiosRecord->Hdr.Type = EFI_SMBIOS_TYPE_SYSTEM_SLOTS;\r
+  SmbiosRecord->Hdr.Length = sizeof (SMBIOS_TABLE_TYPE9);\r
+  SmbiosRecord->Hdr.Handle = 0;\r
+  SmbiosRecord->SlotDesignation = 1;\r
+  SmbiosRecord->SlotType = (UINT8)ForType9InputData->SlotType;\r
+  SmbiosRecord->SlotDataBusWidth = (UINT8)ForType9InputData->SlotDataBusWidth;\r
+  SmbiosRecord->CurrentUsage = (UINT8)ForType9InputData->SlotUsage;\r
+  SmbiosRecord->SlotLength = (UINT8)ForType9InputData->SlotLength;\r
+  SmbiosRecord->SlotID = ForType9InputData->SlotId;\r
+\r
+  //\r
+  // Slot Characteristics\r
+  //\r
+  CopyMem ((UINT8 *) &SmbiosRecord->SlotCharacteristics1,(UINT8 *) &ForType9InputData->SlotCharacteristics,2);\r
+  OptionalStrStart = (CHAR8 *)(SmbiosRecord + 1);\r
+  UnicodeStrToAsciiStr(SlotDesignation, OptionalStrStart);\r
+  //\r
+  // Now we have got the full smbios record, call smbios protocol to add this record.\r
+  //\r
+  SmbiosHandle = SMBIOS_HANDLE_PI_RESERVED;\r
+  Status = Smbios-> Add(\r
+                      Smbios,\r
+                      NULL,\r
+                      &SmbiosHandle,\r
+                      (EFI_SMBIOS_TABLE_HEADER *) SmbiosRecord\r
+                      );\r
+  FreePool(SmbiosRecord);\r
+  return Status;\r
+}\r

diff --git a/Vlv2TbltDevicePkg/SmBiosMiscDxe/SmBiosMiscDxe.inf b/Vlv2TbltDevicePkg/SmBiosMiscDxe/SmBiosMiscDxe.inf
new file mode 100644 (file)
index 0000000..842dda3
--- /dev/null
+++ b/Vlv2TbltDevicePkg/SmBiosMiscDxe/SmBiosMiscDxe.inf
@@ -0,0 +1,144 @@
+## @file
+# Component name for module MiscSubclass
+#
+# FIX ME!
+# Copyright (c) 2006  - 2014, Intel Corporation. All rights reserved.<BR>
+#                                                                                  
+# This program and the accompanying materials are licensed and made available under
+# the terms and conditions of the BSD License that accompanies this distribution.  
+# The full text of the license may be found at                                     
+# http://opensource.org/licenses/bsd-license.php.                                  
+#                                                                                  
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    
+#                                                                                  
+#
+#
+#
+##
+
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = MiscSubclass
+  FILE_GUID                      = 4EFFB560-B28B-4e57-9DAD-4344E32EA3BA
+  MODULE_TYPE                    = DXE_DRIVER
+  VERSION_STRING                 = 1.0
+  ENTRY_POINT                    = MiscSubclassDriverEntryPoint
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+#  VALID_ARCHITECTURES           = IA32 X64 IPF EBC
+#
+
+[Sources]
+  MiscBaseBoardManufacturer.uni
+  MiscBaseBoardManufacturerData.c
+  MiscBaseBoardManufacturerFunction.c
+  MiscBiosVendor.uni
+  MiscBiosVendorData.c
+  MiscBiosVendorFunction.c
+  MiscBootInformationData.c
+  MiscBootInformationFunction.c
+  MiscChassisManufacturer.uni
+  MiscChassisManufacturerData.c
+  MiscChassisManufacturerFunction.c
+  MiscNumberOfInstallableLanguagesData.c
+  MiscNumberOfInstallableLanguagesFunction.c
+  MiscOemString.uni
+  MiscOemStringData.c
+  MiscOemStringFunction.c
+  MiscOnboardDevice.uni
+  MiscOnboardDeviceData.c
+  MiscOnboardDeviceFunction.c
+  MiscPortInternalConnectorDesignator.uni
+  MiscPortInternalConnectorDesignatorData.c
+  MiscPortInternalConnectorDesignatorFunction.c
+  MiscResetCapabilitiesData.c
+  MiscResetCapabilitiesFunction.c
+  MiscSystemLanguageString.uni
+  MiscSystemLanguageStringData.c
+  MiscSystemLanguageStringFunction.c
+  MiscSystemManufacturer.uni
+  MiscSystemManufacturerData.c
+  MiscSystemManufacturerFunction.c
+  MiscSystemOptionString.uni
+  MiscSystemOptionStringData.c
+  MiscSystemOptionStringFunction.c
+  MiscSystemSlotDesignation.uni
+  MiscSystemSlotDesignationData.c
+  MiscSystemSlotDesignationFunction.c
+  MiscSubclassDriver.h
+  MiscSubclassDriver.uni
+  MiscSubclassDriverDataTable.c
+  MiscSubclassDriverEntryPoint.c
+  CommonHeader.h
+  MiscOemType0x90Function.c
+  MiscOemType0x90Data.c
+  MiscOemType0x90.uni
+  MiscProcessorInformation.uni
+  MiscProcessorInformationData.c
+  MiscProcessorInformationFunction.c
+  MiscProcessorCache.uni
+  MiscProcessorCacheData.c
+  MiscProcessorCacheFunction.c
+  MiscPhysicalArray.uni
+  MiscPhysicalArrayData.c
+  MiscPhysicalArrayFunction.c
+  MiscMemoryDevice.uni
+  MiscMemoryDeviceData.c
+  MiscMemoryDeviceFunction.c
+
+[Packages]
+  MdeModulePkg/MdeModulePkg.dec
+  Vlv2TbltDevicePkg/PlatformPkg.dec
+  MdePkg/MdePkg.dec
+  IntelFrameworkPkg/IntelFrameworkPkg.dec
+  Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec
+
+[LibraryClasses]
+  HiiLib
+  DevicePathLib
+  UefiBootServicesTableLib
+  UefiRuntimeServicesTableLib
+  UefiDriverEntryPoint
+  BaseMemoryLib
+  DebugLib
+  BaseLib
+  MemoryAllocationLib
+  PcdLib
+  UefiLib
+  BiosIdLib
+  PrintLib
+  CpuIA32Lib
+  PchPlatformLib
+  I2cLib
+  NetLib
+  
+[Guids]
+  gEfiProcessorSubClassGuid
+  gEfiCacheSubClassGuid
+  gEfiNormalSetupGuid
+  gEfiPlatformInfoGuid
+  gEfiVlv2VariableGuid
+
+[Protocols]
+  gEfiSmbiosProtocolGuid                        # PROTOCOL ALWAYS_CONSUMED
+  gEfiDxeSmmReadyToLockProtocolGuid             # PROTOCOL ALWAYS_CONSUMED
+  gEfiDataHubProtocolGuid
+  gEfiMpServiceProtocolGuid
+  gMemInfoProtocolGuid
+  gEfiTdtOperationProtocolGuid
+  gDxePchPlatformPolicyProtocolGuid
+  gEfiSpiProtocolGuid
+  gEfiSimpleNetworkProtocolGuid
+
+[Pcd]
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareReleaseDateString
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString
+  gEfiMdePkgTokenSpaceGuid.PcdUefiVariableDefaultPlatformLang
+  gEfiVLVTokenSpaceGuid.PcdEmmcManufacturerId
+  gEfiVLVTokenSpaceGuid.PcdProductSerialNumber
+
+[Depex]
+ gEfiSmbiosProtocolGuid AND gMemInfoProtocolGuid AND gEfiMpServiceProtocolGuid AND gEfiSimpleNetworkProtocolGuid

diff --git a/Vlv2TbltDevicePkg/SmmSwDispatch2OnSmmSwDispatchThunk/SmmSwDispatch2OnSmmSwDispatchThunk.c b/Vlv2TbltDevicePkg/SmmSwDispatch2OnSmmSwDispatchThunk/SmmSwDispatch2OnSmmSwDispatchThunk.c
new file mode 100644 (file)
index 0000000..c09c3d9
--- /dev/null
+++ b/Vlv2TbltDevicePkg/SmmSwDispatch2OnSmmSwDispatchThunk/SmmSwDispatch2OnSmmSwDispatchThunk.c
@@ -0,0 +1,464 @@
+/** @file\r
+  SMM SwDispatch2 Protocol on SMM SwDispatch Protocol Thunk driver.\r
+\r
+  Copyright (c) 2010 - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+**/\r
+\r
+#include <PiDxe.h>\r
+#include <FrameworkSmm.h>\r
+\r
+#include <Protocol/SmmSwDispatch2.h>\r
+#include <Protocol/SmmSwDispatch.h>\r
+#include <Protocol/SmmControl.h>\r
+#include <Protocol/SmmCpu.h>\r
+\r
+#include <Library/UefiBootServicesTableLib.h>\r
+#include <Library/UefiDriverEntryPoint.h>\r
+#include <Library/SmmServicesTableLib.h>\r
+#include <Library/BaseLib.h>\r
+#include <Library/IoLib.h>\r
+#include <Library/DebugLib.h>\r
+\r
+typedef struct {\r
+  LIST_ENTRY                     Link;\r
+  EFI_HANDLE                     DispatchHandle;\r
+  UINTN                          SwSmiInputValue;\r
+  UINTN                          DispatchFunction;\r
+} EFI_SMM_SW_DISPATCH2_THUNK_CONTEXT;\r
+\r
+/**\r
+  Register a child SMI source dispatch function for the specified software SMI.\r
+\r
+  This service registers a function (DispatchFunction) which will be called when the software\r
+  SMI source specified by RegisterContext->SwSmiCpuIndex is detected. On return,\r
+  DispatchHandle contains a unique handle which may be used later to unregister the function\r
+  using UnRegister().\r
+\r
+  @param[in]  This                  Pointer to the EFI_SMM_SW_DISPATCH2_PROTOCOL instance.\r
+  @param[in]  DispatchFunction      Function to register for handler when the specified software\r
+                                    SMI is generated.\r
+  @param[in, out]  RegisterContext  Pointer to the dispatch function's context.\r
+                                    The caller fills this context in before calling\r
+                                    the register function to indicate to the register\r
+                                    function which Software SMI input value the\r
+                                    dispatch function should be invoked for.\r
+  @param[out] DispatchHandle        Handle generated by the dispatcher to track the\r
+                                    function instance.\r
+\r
+  @retval EFI_SUCCESS            The dispatch function has been successfully\r
+                                 registered and the SMI source has been enabled.\r
+  @retval EFI_DEVICE_ERROR       The SW driver was unable to enable the SMI source.\r
+  @retval EFI_INVALID_PARAMETER  RegisterContext is invalid. The SW SMI input value\r
+                                 is not within valid range.\r
+  @retval EFI_OUT_OF_RESOURCES   There is not enough memory (system or SMM) to manage this\r
+                                 child.\r
+  @retval EFI_OUT_OF_RESOURCES   A unique software SMI value could not be assigned\r
+                                 for this dispatch.\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+SmmSwDispatch2Register (\r
+  IN  CONST EFI_SMM_SW_DISPATCH2_PROTOCOL  *This,\r
+  IN        EFI_SMM_HANDLER_ENTRY_POINT2   DispatchFunction,\r
+  IN  OUT   EFI_SMM_SW_REGISTER_CONTEXT    *RegisterContext,\r
+  OUT       EFI_HANDLE                     *DispatchHandle\r
+  );\r
+\r
+/**\r
+  Unregister a child SMI source dispatch function for the specified software SMI.\r
+\r
+  This service removes the handler associated with DispatchHandle so that it will no longer be\r
+  called in response to a software SMI.\r
+\r
+  @param[in] This                Pointer to the EFI_SMM_SW_DISPATCH2_PROTOCOL instance.\r
+  @param[in] DispatchHandle      Handle of dispatch function to deregister.\r
+\r
+  @retval EFI_SUCCESS            The dispatch function has been successfully unregistered.\r
+  @retval EFI_INVALID_PARAMETER  The DispatchHandle was not valid.\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+SmmSwDispatch2UnRegister (\r
+  IN CONST EFI_SMM_SW_DISPATCH2_PROTOCOL  *This,\r
+  IN       EFI_HANDLE                     DispatchHandle\r
+  );\r
+\r
+EFI_SMM_SW_DISPATCH2_PROTOCOL gSmmSwDispatch2 = {\r
+  SmmSwDispatch2Register,\r
+  SmmSwDispatch2UnRegister,\r
+  0 // MaximumSwiValue\r
+};\r
+\r
+EFI_SMM_SW_DISPATCH_PROTOCOL  *mSmmSwDispatch;\r
+UINT8                         mSmiTriggerRegister;\r
+UINT8                         mSmiDataRegister;\r
+\r
+EFI_SMM_CPU_PROTOCOL          *mSmmCpuProtocol;\r
+LIST_ENTRY                    mSmmSwDispatch2ThunkQueue = INITIALIZE_LIST_HEAD_VARIABLE (mSmmSwDispatch2ThunkQueue);\r
+\r
+/**\r
+  This function find SmmSwDispatch2Context by SwSmiInputValue.\r
+\r
+  @param SwSmiInputValue The SwSmiInputValue to indentify the SmmSwDispatch2 context\r
+\r
+  @return SmmSwDispatch2 context\r
+**/\r
+EFI_SMM_SW_DISPATCH2_THUNK_CONTEXT *\r
+FindSmmSwDispatch2ContextBySwSmiInputValue (\r
+  IN UINTN   SwSmiInputValue\r
+  )\r
+{\r
+  LIST_ENTRY                            *Link;\r
+  EFI_SMM_SW_DISPATCH2_THUNK_CONTEXT    *ThunkContext;\r
+\r
+  for (Link = mSmmSwDispatch2ThunkQueue.ForwardLink;\r
+    Link != &mSmmSwDispatch2ThunkQueue;\r
+    Link = Link->ForwardLink) {\r
+    ThunkContext = BASE_CR (\r
+                     Link,\r
+                     EFI_SMM_SW_DISPATCH2_THUNK_CONTEXT,\r
+                     Link\r
+                     );\r
+    if (ThunkContext->SwSmiInputValue == SwSmiInputValue) {\r
+      return ThunkContext;\r
+    }\r
+  }\r
+  return NULL;\r
+}\r
+\r
+/**\r
+  This function find SmmSwDispatch2Context by DispatchHandle.\r
+\r
+  @param DispatchHandle The DispatchHandle to indentify the SmmSwDispatch2Thunk context\r
+\r
+  @return SmmSwDispatch2Thunk context\r
+**/\r
+EFI_SMM_SW_DISPATCH2_THUNK_CONTEXT *\r
+FindSmmSwDispatch2ContextByDispatchHandle (\r
+  IN EFI_HANDLE   DispatchHandle\r
+  )\r
+{\r
+  LIST_ENTRY                            *Link;\r
+  EFI_SMM_SW_DISPATCH2_THUNK_CONTEXT    *ThunkContext;\r
+\r
+  for (Link = mSmmSwDispatch2ThunkQueue.ForwardLink;\r
+       Link != &mSmmSwDispatch2ThunkQueue;\r
+       Link = Link->ForwardLink) {\r
+    ThunkContext = BASE_CR (\r
+                     Link,\r
+                     EFI_SMM_SW_DISPATCH2_THUNK_CONTEXT,\r
+                     Link\r
+                     );\r
+    if (ThunkContext->DispatchHandle == DispatchHandle) {\r
+      return ThunkContext;\r
+    }\r
+  }\r
+  return NULL;\r
+}\r
+\r
+/**\r
+  Framework dispatch function for a Software SMI handler.\r
+\r
+  @param  DispatchHandle        The handle of this dispatch function.\r
+  @param  DispatchContext       The pointer to the dispatch function's context.\r
+                                The SwSmiInputValue field is filled in\r
+                                by the software dispatch driver prior to\r
+                                invoking this dispatch function.\r
+                                The dispatch function will only be called\r
+                                for input values for which it is registered.\r
+\r
+  @return None\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+FrameworkDispatchFunction (\r
+  IN  EFI_HANDLE                    DispatchHandle,\r
+  IN  EFI_SMM_SW_DISPATCH_CONTEXT   *DispatchContext\r
+  )\r
+{\r
+  EFI_SMM_SW_DISPATCH2_THUNK_CONTEXT    *ThunkContext;\r
+  EFI_SMM_HANDLER_ENTRY_POINT2          DispatchFunction;\r
+  EFI_SMM_SW_REGISTER_CONTEXT           RegisterContext;\r
+  EFI_SMM_SW_CONTEXT                    SwContext;\r
+  UINTN                                 Size;\r
+  UINTN                                 Index;\r
+  EFI_SMM_SAVE_STATE_IO_INFO            IoInfo;\r
+  EFI_STATUS                            Status;\r
+\r
+  //\r
+  // Search context\r
+  //\r
+  ThunkContext = FindSmmSwDispatch2ContextBySwSmiInputValue (DispatchContext->SwSmiInputValue);\r
+  ASSERT (ThunkContext != NULL);\r
+  if (ThunkContext == NULL) {\r
+    return ;\r
+  }\r
+\r
+  //\r
+  // Construct new context\r
+  //\r
+  RegisterContext.SwSmiInputValue = DispatchContext->SwSmiInputValue;\r
+  Size = sizeof(SwContext);\r
+  SwContext.CommandPort = IoRead8 (mSmiTriggerRegister);\r
+  SwContext.DataPort    = IoRead8 (mSmiDataRegister);\r
+\r
+  //\r
+  // Try to find which CPU trigger SWSMI\r
+  //\r
+  SwContext.SwSmiCpuIndex = 0;\r
+  for (Index = 0; Index < gSmst->NumberOfCpus; Index++) {\r
+    Status = mSmmCpuProtocol->ReadSaveState (\r
+                                mSmmCpuProtocol,\r
+                                sizeof(IoInfo),\r
+                                EFI_SMM_SAVE_STATE_REGISTER_IO,\r
+                                Index,\r
+                                &IoInfo\r
+                                );\r
+    if (EFI_ERROR (Status)) {\r
+      continue;\r
+    }\r
+    if (IoInfo.IoPort == mSmiTriggerRegister) {\r
+      //\r
+      // Great! Find it.\r
+      //\r
+      SwContext.SwSmiCpuIndex = Index;\r
+      break;\r
+    }\r
+  }\r
+\r
+  //\r
+  // Dispatch\r
+  //\r
+  DispatchFunction = (EFI_SMM_HANDLER_ENTRY_POINT2)ThunkContext->DispatchFunction;\r
+  DispatchFunction (\r
+    DispatchHandle,\r
+    &RegisterContext,\r
+    &SwContext,\r
+    &Size\r
+    );\r
+  return ;\r
+}\r
+\r
+/**\r
+  Register a child SMI source dispatch function for the specified software SMI.\r
+\r
+  This service registers a function (DispatchFunction) which will be called when the software\r
+  SMI source specified by RegisterContext->SwSmiCpuIndex is detected. On return,\r
+  DispatchHandle contains a unique handle which may be used later to unregister the function\r
+  using UnRegister().\r
+\r
+  @param[in]  This                  Pointer to the EFI_SMM_SW_DISPATCH2_PROTOCOL instance.\r
+  @param[in]  DispatchFunction      Function to register for handler when the specified software\r
+                                    SMI is generated.\r
+  @param[in, out]  RegisterContext  Pointer to the dispatch function's context.\r
+                                    The caller fills this context in before calling\r
+                                    the register function to indicate to the register\r
+                                    function which Software SMI input value the\r
+                                    dispatch function should be invoked for.\r
+  @param[out] DispatchHandle        Handle generated by the dispatcher to track the\r
+                                    function instance.\r
+\r
+  @retval EFI_SUCCESS            The dispatch function has been successfully\r
+                                 registered and the SMI source has been enabled.\r
+  @retval EFI_DEVICE_ERROR       The SW driver was unable to enable the SMI source.\r
+  @retval EFI_INVALID_PARAMETER  RegisterContext is invalid. The SW SMI input value\r
+                                 is not within valid range.\r
+  @retval EFI_OUT_OF_RESOURCES   There is not enough memory (system or SMM) to manage this\r
+                                 child.\r
+  @retval EFI_OUT_OF_RESOURCES   A unique software SMI value could not be assigned\r
+                                 for this dispatch.\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+SmmSwDispatch2Register (\r
+  IN  CONST EFI_SMM_SW_DISPATCH2_PROTOCOL  *This,\r
+  IN        EFI_SMM_HANDLER_ENTRY_POINT2   DispatchFunction,\r
+  IN  OUT   EFI_SMM_SW_REGISTER_CONTEXT    *RegisterContext,\r
+  OUT       EFI_HANDLE                     *DispatchHandle\r
+  )\r
+{\r
+  EFI_SMM_SW_DISPATCH2_THUNK_CONTEXT    *ThunkContext;\r
+  EFI_SMM_SW_DISPATCH_CONTEXT           DispatchContext;\r
+  EFI_STATUS                            Status;\r
+  UINTN                                 Index;\r
+\r
+  if (RegisterContext->SwSmiInputValue == (UINTN)-1) {\r
+    //\r
+    // If SwSmiInputValue is set to (UINTN) -1 then a unique value will be assigned and returned in the structure.\r
+    //\r
+    Status = EFI_NOT_FOUND;\r
+    for (Index = 1; Index < gSmmSwDispatch2.MaximumSwiValue; Index++) {\r
+      DispatchContext.SwSmiInputValue = Index;\r
+      Status = mSmmSwDispatch->Register (\r
+                                 mSmmSwDispatch,\r
+                                 FrameworkDispatchFunction,\r
+                                 &DispatchContext,\r
+                                 DispatchHandle\r
+                                 );\r
+      if (!EFI_ERROR (Status)) {\r
+        RegisterContext->SwSmiInputValue = Index;\r
+        break;\r
+      }\r
+    }\r
+    if (RegisterContext->SwSmiInputValue == (UINTN)-1) {\r
+      return EFI_OUT_OF_RESOURCES;\r
+    }\r
+  } else {\r
+    DispatchContext.SwSmiInputValue = RegisterContext->SwSmiInputValue;\r
+    Status = mSmmSwDispatch->Register (\r
+                               mSmmSwDispatch,\r
+                               FrameworkDispatchFunction,\r
+                               &DispatchContext,\r
+                               DispatchHandle\r
+                               );\r
+  }\r
+  if (!EFI_ERROR (Status)) {\r
+    //\r
+    // Register\r
+    //\r
+    Status = gSmst->SmmAllocatePool (\r
+                      EfiRuntimeServicesData,\r
+                      sizeof(*ThunkContext),\r
+                      (VOID **)&ThunkContext\r
+                      );\r
+    ASSERT_EFI_ERROR (Status);\r
+    if (EFI_ERROR (Status)) {\r
+      mSmmSwDispatch->UnRegister (mSmmSwDispatch, *DispatchHandle);\r
+      return EFI_OUT_OF_RESOURCES;\r
+    }\r
+\r
+    ThunkContext->SwSmiInputValue  = RegisterContext->SwSmiInputValue;\r
+    ThunkContext->DispatchFunction = (UINTN)DispatchFunction;\r
+    ThunkContext->DispatchHandle   = *DispatchHandle;\r
+    InsertTailList (&mSmmSwDispatch2ThunkQueue, &ThunkContext->Link);\r
+  }\r
+\r
+  return Status;\r
+}\r
+\r
+/**\r
+  Unregister a child SMI source dispatch function for the specified software SMI.\r
+\r
+  This service removes the handler associated with DispatchHandle so that it will no longer be\r
+  called in response to a software SMI.\r
+\r
+  @param[in] This                Pointer to the EFI_SMM_SW_DISPATCH2_PROTOCOL instance.\r
+  @param[in] DispatchHandle      Handle of dispatch function to deregister.\r
+\r
+  @retval EFI_SUCCESS            The dispatch function has been successfully unregistered.\r
+  @retval EFI_INVALID_PARAMETER  The DispatchHandle was not valid.\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+SmmSwDispatch2UnRegister (\r
+  IN CONST EFI_SMM_SW_DISPATCH2_PROTOCOL  *This,\r
+  IN       EFI_HANDLE                     DispatchHandle\r
+  )\r
+{\r
+  EFI_SMM_SW_DISPATCH2_THUNK_CONTEXT    *ThunkContext;\r
+  EFI_STATUS                            Status;\r
+\r
+  Status = mSmmSwDispatch->UnRegister (mSmmSwDispatch, DispatchHandle);\r
+  if (!EFI_ERROR (Status)) {\r
+    //\r
+    // Unregister\r
+    //\r
+    ThunkContext = FindSmmSwDispatch2ContextByDispatchHandle (DispatchHandle);\r
+    ASSERT (ThunkContext != NULL);\r
+    if (ThunkContext != NULL) {\r
+      RemoveEntryList (&ThunkContext->Link);\r
+      gSmst->SmmFreePool (ThunkContext);\r
+    }\r
+  }\r
+\r
+  return Status;\r
+}\r
+\r
+/**\r
+  Entry Point for this thunk driver.\r
+\r
+  @param[in] ImageHandle  Image handle of this driver.\r
+  @param[in] SystemTable  A Pointer to the EFI System Table.\r
+\r
+  @retval EFI_SUCCESS  The entry point is executed successfully.\r
+  @retval other        Some error occurred when executing this entry point.\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+SmmSwDispatch2ThunkMain (\r
+  IN EFI_HANDLE        ImageHandle,\r
+  IN EFI_SYSTEM_TABLE  *SystemTable\r
+  )\r
+{\r
+  EFI_STATUS               Status;\r
+  EFI_SMM_CONTROL_PROTOCOL *SmmControl;\r
+  EFI_SMM_CONTROL_REGISTER RegisterInfo;\r
+\r
+  //\r
+  // Locate Framework SMM SwDispatch Protocol\r
+  //\r
+  Status = gBS->LocateProtocol (\r
+                  &gEfiSmmSwDispatchProtocolGuid,\r
+                  NULL,\r
+                  (VOID **)&mSmmSwDispatch\r
+                  );\r
+  ASSERT_EFI_ERROR (Status);\r
+  gSmmSwDispatch2.MaximumSwiValue = mSmmSwDispatch->MaximumSwiValue;\r
+  if (gSmmSwDispatch2.MaximumSwiValue == 0x0) {\r
+    DEBUG ((EFI_D_ERROR, "BUGBUG: MaximumSwiValue is 0, work-around to make it 0xFF\n"));\r
+    gSmmSwDispatch2.MaximumSwiValue = 0xFF;\r
+  }\r
+\r
+  //\r
+  // Locate Framework SMM Control Protocol\r
+  //\r
+  Status = gBS->LocateProtocol (\r
+                  &gEfiSmmControlProtocolGuid,\r
+                  NULL,\r
+                  (VOID **)&SmmControl\r
+                  );\r
+\r
+  ASSERT_EFI_ERROR (Status);\r
+  Status = SmmControl->GetRegisterInfo (\r
+                         SmmControl,\r
+                         &RegisterInfo\r
+                         );\r
+  ASSERT_EFI_ERROR (Status);\r
+  mSmiTriggerRegister = RegisterInfo.SmiTriggerRegister;\r
+  mSmiDataRegister    = RegisterInfo.SmiDataRegister;\r
+\r
+  //\r
+  // Locate PI SMM CPU protocol\r
+  //\r
+  Status = gSmst->SmmLocateProtocol (\r
+                    &gEfiSmmCpuProtocolGuid,\r
+                    NULL,\r
+                    (VOID **)&mSmmCpuProtocol\r
+                    );\r
+  ASSERT_EFI_ERROR (Status);\r
+\r
+  //\r
+  // Publish PI SMM SwDispatch2 Protocol\r
+  //\r
+  ImageHandle = NULL;\r
+  Status = gSmst->SmmInstallProtocolInterface (\r
+                    &ImageHandle,\r
+                    &gEfiSmmSwDispatch2ProtocolGuid,\r
+                    EFI_NATIVE_INTERFACE,\r
+                    &gSmmSwDispatch2\r
+                    );\r
+  ASSERT_EFI_ERROR (Status);\r
+  return Status;\r
+}\r
+\r

diff --git a/Vlv2TbltDevicePkg/SmmSwDispatch2OnSmmSwDispatchThunk/SmmSwDispatch2OnSmmSwDispatchThunk.inf b/Vlv2TbltDevicePkg/SmmSwDispatch2OnSmmSwDispatchThunk/SmmSwDispatch2OnSmmSwDispatchThunk.inf
new file mode 100644 (file)
index 0000000..9663fc9
--- /dev/null
+++ b/Vlv2TbltDevicePkg/SmmSwDispatch2OnSmmSwDispatchThunk/SmmSwDispatch2OnSmmSwDispatchThunk.inf
@@ -0,0 +1,59 @@
+## @file\r
+#  Component description file for SMM SwDispatch2 Protocol on SMM SwDispatch Protocol Thunk driver.\r
+#\r
+#  Copyright (c) 2010 - 2014, Intel Corporation. All rights reserved.<BR>\r
+#                                                                                  \r\r
+# This program and the accompanying materials are licensed and made available under\r\r
+# the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+# The full text of the license may be found at                                     \r\r
+# http://opensource.org/licenses/bsd-license.php.                                  \r\r
+#                                                                                  \r\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+#                                                                                  \r\r
+#\r
+#\r
+#\r
+##\r
+\r
+[Defines]\r
+  INF_VERSION                    = 0x00010005\r
+  BASE_NAME                      = SmmSwDispatch2OnSmmSwDispatchThunk\r
+  FILE_GUID                      = 1410C6AC-9F4B-495b-9C23-8A5AEB0165E9\r
+  MODULE_TYPE                    = DXE_SMM_DRIVER\r
+  VERSION_STRING                 = 1.0\r
+  PI_SPECIFICATION_VERSION       = 0x0001000A\r
+  ENTRY_POINT                    = SmmSwDispatch2ThunkMain\r
+\r
+#\r
+# The following information is for reference only and not required by the build tools.\r
+#\r
+#  VALID_ARCHITECTURES           = IA32 X64\r
+#\r
+\r
+[Sources]\r
+  SmmSwDispatch2OnSmmSwDispatchThunk.c\r
+\r
+[Packages]\r
+  MdePkg/MdePkg.dec\r
+  IntelFrameworkPkg/IntelFrameworkPkg.dec\r
+\r
+[LibraryClasses]\r
+  UefiDriverEntryPoint\r
+  UefiBootServicesTableLib\r
+  SmmServicesTableLib\r
+  BaseLib\r
+  IoLib\r
+  DebugLib\r
+\r
+[Protocols]\r
+  gEfiSmmControlProtocolGuid               # PROTOCOL ALWAYS_CONSUMED\r
+  gEfiSmmSwDispatchProtocolGuid            # PROTOCOL ALWAYS_CONSUMED\r
+  gEfiSmmCpuProtocolGuid                   # PROTOCOL ALWAYS_CONSUMED\r
+  gEfiSmmSwDispatch2ProtocolGuid           # PROTOCOL ALWAYS_PRODUCED\r
+\r
+[Depex]\r
+  gEfiSmmSwDispatchProtocolGuid AND\r
+  gEfiSmmControlProtocolGuid AND\r
+  gEfiSmmCpuProtocolGuid\r
+\r

diff --git a/Vlv2TbltDevicePkg/SmramSaveInfoHandlerSmm/SmramSaveInfoHandlerSmm.c b/Vlv2TbltDevicePkg/SmramSaveInfoHandlerSmm/SmramSaveInfoHandlerSmm.c
new file mode 100644 (file)
index 0000000..a48de26
--- /dev/null
+++ b/Vlv2TbltDevicePkg/SmramSaveInfoHandlerSmm/SmramSaveInfoHandlerSmm.c
@@ -0,0 +1,182 @@
+/** @file\r
+  A helper driver to save information to SMRAM after SMRR is enabled.\r
+\r
+  This driver is for ECP platforms.\r
+\r
+  Copyright (c) 2010 - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+**/\r
+\r
+#include <PiSmm.h>\r
+#include <Library/DebugLib.h>\r
+#include <Library/UefiDriverEntryPoint.h>\r
+#include <Library/UefiRuntimeServicesTableLib.h>\r
+#include <Library/SmmServicesTableLib.h>\r
+#include <Library/BaseLib.h>\r
+#include <Library/BaseMemoryLib.h>\r
+#include <Library/IoLib.h>\r
+#include <Protocol/SmmSwDispatch.h>\r
+#include <Protocol/SmmReadyToLock.h>\r
+#include <Protocol/SmmControl.h>\r
+\r
+#define SMM_FROM_SMBASE_DRIVER        0x55\r
+#define SMM_FROM_CPU_DRIVER_SAVE_INFO 0x81\r
+\r
+#define EFI_SMRAM_CPU_NVS_HEADER_GUID \\r
+  { \\r
+    0x429501d9, 0xe447, 0x40f4, 0x86, 0x7b, 0x75, 0xc9, 0x3a, 0x1d, 0xb5, 0x4e \\r
+  }\r
+\r
+UINT8    mSmiDataRegister;\r
+BOOLEAN  mLocked = FALSE;\r
+EFI_GUID mSmramCpuNvsHeaderGuid = EFI_SMRAM_CPU_NVS_HEADER_GUID;\r
+\r
+/**\r
+  Dispatch function for a Software SMI handler.\r
+\r
+  @param  DispatchHandle        The handle of this dispatch function.\r
+  @param  DispatchContext       The pointer to the dispatch function's context.\r
+                                The SwSmiInputValue field is filled in\r
+                                by the software dispatch driver prior to\r
+                                invoking this dispatch function.\r
+                                The dispatch function will only be called\r
+                                for input values for which it is registered.\r
+\r
+  @return None\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+SmramSaveInfoHandler (\r
+  IN  EFI_HANDLE                    DispatchHandle,\r
+  IN  EFI_SMM_SW_DISPATCH_CONTEXT   *DispatchContext\r
+  )\r
+{\r
+  EFI_STATUS Status;\r
+  UINT64     VarData[3];\r
+  UINTN      VarSize;\r
+\r
+  ASSERT (DispatchContext != NULL);\r
+  ASSERT (DispatchContext->SwSmiInputValue == SMM_FROM_SMBASE_DRIVER);\r
+\r
+  if (!mLocked && IoRead8 (mSmiDataRegister) == SMM_FROM_CPU_DRIVER_SAVE_INFO) {\r
+    VarSize = sizeof (VarData);\r
+    Status = gRT->GetVariable (\r
+                    L"SmramCpuNvs",\r
+                    &mSmramCpuNvsHeaderGuid,\r
+                    NULL,\r
+                    &VarSize,\r
+                    VarData\r
+                    );\r
+    if (!EFI_ERROR (Status) && VarSize == sizeof (VarData)) {\r
+      CopyMem (\r
+        (VOID *)(UINTN)(VarData[0]),\r
+        (VOID *)(UINTN)(VarData[1]),\r
+        (UINTN)(VarData[2])\r
+        );\r
+    }\r
+  }\r
+}\r
+\r
+/**\r
+  Smm Ready To Lock event notification handler.\r
+\r
+  It sets a flag indicating that SMRAM has been locked.\r
+\r
+  @param[in] Protocol   Points to the protocol's unique identifier.\r
+  @param[in] Interface  Points to the interface instance.\r
+  @param[in] Handle     The handle on which the interface was installed.\r
+\r
+  @retval EFI_SUCCESS   Notification handler runs successfully.\r
+ **/\r
+EFI_STATUS\r
+EFIAPI\r
+SmmReadyToLockEventNotify (\r
+  IN CONST EFI_GUID  *Protocol,\r
+  IN VOID            *Interface,\r
+  IN EFI_HANDLE      Handle\r
+  )\r
+{\r
+  mLocked = TRUE;\r
+  return EFI_SUCCESS;\r
+}\r
+\r
+/**\r
+  Entry point function of this driver.\r
+\r
+  @param[in] ImageHandle  The firmware allocated handle for the EFI image.\r
+  @param[in] SystemTable  A pointer to the EFI System Table.\r
+\r
+  @retval EFI_SUCCESS     The entry point is executed successfully.\r
+  @retval other           Some error occurs when executing this entry point.\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+SmramSaveInfoHandlerSmmMain (\r
+  IN EFI_HANDLE        ImageHandle,\r
+  IN EFI_SYSTEM_TABLE  *SystemTable\r
+  )\r
+{\r
+  EFI_STATUS                    Status;\r
+  EFI_SMM_SW_DISPATCH_PROTOCOL  *SmmSwDispatch;\r
+  EFI_SMM_SW_DISPATCH_CONTEXT   SmmSwDispatchContext;\r
+  EFI_HANDLE                    DispatchHandle;\r
+  EFI_SMM_CONTROL_PROTOCOL      *SmmControl;\r
+  EFI_SMM_CONTROL_REGISTER      SmmControlRegister;\r
+  VOID                          *Registration;\r
+\r
+  //\r
+  // Get SMI data register\r
+  //\r
+  Status = SystemTable->BootServices->LocateProtocol (\r
+                                        &gEfiSmmControlProtocolGuid,\r
+                                        NULL,\r
+                                        (VOID **)&SmmControl\r
+                                        );\r
+  ASSERT_EFI_ERROR (Status);\r
+  Status = SmmControl->GetRegisterInfo (SmmControl, &SmmControlRegister);\r
+  ASSERT_EFI_ERROR (Status);\r
+  mSmiDataRegister = SmmControlRegister.SmiDataRegister;\r
+\r
+  //\r
+  // Register software SMI handler\r
+  //\r
+\r
+  Status = SystemTable->BootServices->LocateProtocol (\r
+                                        &gEfiSmmSwDispatchProtocolGuid,\r
+                                        NULL,\r
+                                        (VOID **)&SmmSwDispatch\r
+                                        );\r
+  ASSERT_EFI_ERROR (Status);\r
+\r
+  SmmSwDispatchContext.SwSmiInputValue = SMM_FROM_SMBASE_DRIVER;\r
+  Status = SmmSwDispatch->Register (\r
+                            SmmSwDispatch,\r
+                            &SmramSaveInfoHandler,\r
+                            &SmmSwDispatchContext,\r
+                            &DispatchHandle\r
+                            );\r
+  ASSERT_EFI_ERROR (Status);\r
+\r
+  //\r
+  // Register SMM Ready To Lock Protocol notification\r
+  //\r
+  Status = gSmst->SmmRegisterProtocolNotify (\r
+                    &gEfiSmmReadyToLockProtocolGuid,\r
+                    SmmReadyToLockEventNotify,\r
+                    &Registration\r
+                    );\r
+  ASSERT_EFI_ERROR (Status);\r
+\r
+  return Status;\r
+}\r
+\r

diff --git a/Vlv2TbltDevicePkg/SmramSaveInfoHandlerSmm/SmramSaveInfoHandlerSmm.inf b/Vlv2TbltDevicePkg/SmramSaveInfoHandlerSmm/SmramSaveInfoHandlerSmm.inf
new file mode 100644 (file)
index 0000000..82eec01
--- /dev/null
+++ b/Vlv2TbltDevicePkg/SmramSaveInfoHandlerSmm/SmramSaveInfoHandlerSmm.inf
@@ -0,0 +1,59 @@
+## @file\r
+#\r
+#  A helper driver to save information to SMRAM after SMRR is enabled.\r
+#\r
+#  Copyright (c) 2010 - 2014, Intel Corporation. All rights reserved.<BR>\r
+#                                                                                  \r\r
+# This program and the accompanying materials are licensed and made available under\r\r
+# the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+# The full text of the license may be found at                                     \r\r
+# http://opensource.org/licenses/bsd-license.php.                                  \r\r
+#                                                                                  \r\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+#                                                                                  \r\r
+#\r
+#\r
+#\r
+##\r
+\r
+[Defines]\r
+  INF_VERSION                    = 0x00010005\r
+  BASE_NAME                      = SmramSaveInfoHandlerSmm\r
+  FILE_GUID                      = 63296C52-01CF-4eea-A47C-782A14DA6894\r
+  MODULE_TYPE                    = DXE_SMM_DRIVER\r
+  VERSION_STRING                 = 1.0\r
+  PI_SPECIFICATION_VERSION       = 0x0001000A\r
+\r
+  ENTRY_POINT                    = SmramSaveInfoHandlerSmmMain\r
+\r
+#\r
+# The following information is for reference only and not required by the build tools.\r
+#\r
+#  VALID_ARCHITECTURES           = IA32 X64\r
+#\r
+\r
+[Sources.common]\r
+  SmramSaveInfoHandlerSmm.c\r
+\r
+[Packages]\r
+  MdePkg/MdePkg.dec\r
+  IntelFrameworkPkg/IntelFrameworkPkg.dec\r
+\r
+[LibraryClasses]\r
+  UefiDriverEntryPoint\r
+  UefiRuntimeServicesTableLib\r
+  SmmServicesTableLib\r
+  BaseLib\r
+  BaseMemoryLib\r
+  IoLib\r
+\r
+[Protocols]\r
+  gEfiSmmSwDispatchProtocolGuid      ## CONSUMED\r
+  gEfiSmmControlProtocolGuid         ## CONSUMED\r
+  gEfiSmmReadyToLockProtocolGuid     ## CONSUMED\r
+\r
+[Depex]\r
+  gEfiSmmSwDispatchProtocolGuid AND\r
+  gEfiSmmControlProtocolGuid\r
+\r

diff --git a/Vlv2TbltDevicePkg/Stitch/Gcc/NvStorageFtwSpare.bin b/Vlv2TbltDevicePkg/Stitch/Gcc/NvStorageFtwSpare.bin
new file mode 100644 (file)
index 0000000..7145947
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Stitch/Gcc/NvStorageFtwSpare.bin
@@ -0,0 +1 @@
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\ No newline at end of file

diff --git a/Vlv2TbltDevicePkg/Stitch/Gcc/NvStorageFtwWorking.bin b/Vlv2TbltDevicePkg/Stitch/Gcc/NvStorageFtwWorking.bin
new file mode 100644 (file)
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new file mode 100644 (file)
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diff --git a/Vlv2TbltDevicePkg/Stitch/IFWIHeader/IFWI_HEADER.bin b/Vlv2TbltDevicePkg/Stitch/IFWIHeader/IFWI_HEADER.bin
new file mode 100644 (file)
index 0000000..5c26f1e
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diff --git a/Vlv2TbltDevicePkg/Stitch/IFWIHeader/Vacant.bin b/Vlv2TbltDevicePkg/Stitch/IFWIHeader/Vacant.bin
new file mode 100644 (file)
index 0000000..cf2579e
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Stitch/IFWIHeader/Vacant.bin
@@ -0,0 +1 @@
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ÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿ
\ No newline at end of file

diff --git a/Vlv2TbltDevicePkg/Stitch/IFWIStitch.bat b/Vlv2TbltDevicePkg/Stitch/IFWIStitch.bat
new file mode 100644 (file)
index 0000000..a512e42
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Stitch/IFWIStitch.bat
@@ -0,0 +1,244 @@
+@REM @file\r
+@REM   Windows batch file to build BIOS ROM\r
+@REM\r
+@REM Copyright (c) 2006   - 2014, Intel Corporation. All rights reserved.<BR>\r
+@REM \r
+@REM   This program and the accompanying materials are licensed and made available under\r
+@REM   the terms and conditions of the BSD License that accompanies this distribution.\r
+@REM   The full text of the license may be found at\r
+@REM   http://opensource.org/licenses/bsd-license.php.\r
+@REM \r
+@REM   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+@REM   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+@REM\r
+\r
+@echo off\r
+SetLocal EnableDelayedExpansion EnableExtensions\r
+\r
+:: Set script defaults\r
+set exitCode=0\r
+set BackupRom=1\r
+set UpdateVBios=1\r
+set Stitch_Config=Stitch_Config.txt\r
+copy /y nul Stitching.log >nul\r
+\r
+:: Set default Suffix as:  YYYY_MM_DD_HHMM\r
+set hour=%time: =0%\r
+reg copy "HKCU\Control Panel\International" "HKCU\Control Panel\International_Temp" /f >nul\r
+reg add "HKCU\Control Panel\International" /v sShortDate /d "yyyy_MM_dd" /f >nul\r
+for /f "tokens=1" %%i in ("%date%") do set today=%%i\r
+reg copy "HKCU\Control Panel\International_Temp" "HKCU\Control Panel\International" /f >nul\r
+reg delete "HKCU\Control Panel\International_Temp" /f >nul\r
+set IFWI_Suffix=%today%_%hour:~0,2%%time:~3,2%\r
+\r
+:: Process input arguments\r
+if "%~1"=="?"       goto Usage\r
+if "%~1"=="/?"      goto Usage\r
+if /i "%~1"=="Help" goto Usage\r
+\r
+:OptLoop\r
+if /i "%~1"=="/nV" (\r
+    set UpdateVBios=0\r
+    shift\r
+    goto OptLoop\r
+)\r
+if /i "%~1"=="/nB" (\r
+    set BackupRom=0\r
+    shift\r
+    goto OptLoop\r
+)\r
+if /i "%~1"=="/B" (\r
+    if "%~2"==""  goto Usage\r
+    if not exist %~2 echo BIOS not found. & goto Usage\r
+    set BIOS_Names=%~2\r
+    set BIOS_File_Name=%~n2\r
+    shift & shift\r
+    goto OptLoop\r
+)\r
+if /i "%~1"=="/C" (\r
+    if "%~2"==""  goto Usage\r
+    if not exist %~2 echo ConfigFile not found. & goto Usage\r
+    set Stitch_Config=%~2\r
+    shift & shift\r
+    goto OptLoop\r
+)\r
+if /i "%~1"=="/S" (\r
+    if "%~2"==""  goto Usage\r
+    set IFWI_Suffix=%~2\r
+    shift & shift\r
+    goto OptLoop\r
+)\r
+\r
+if "%BIOS_File_Name:~0,4%"=="MNW2" (\r
+   set Stitch_Config= MNW2_Stitch_Config.txt\r
+)\r
+if "%BIOS_File_Name:~3,4%"=="MNW2" (\r
+   set Stitch_Config= MNW2_Stitch_Config.txt\r
+)\r
+\r
+:: if no rom specified by user, search in ./ for ROM files\r
+if "%BIOS_Names%"=="" (\r
+    set "BIOS_Names= "\r
+    for /f "tokens=*" %%i in ('dir /b *.rom') do set BIOS_Names=!BIOS_Names! %%i\r
+    if "!BIOS_Names!"==" " (\r
+        echo NO .ROM files found !!!\r
+        goto Usage\r
+    )\r
+)\r
+\r
+:: Parse the Stitch_Config File\r
+if not exist %Stitch_Config% (\r
+    echo Stitch Configuration File %Stitch_Config% not found.\r
+    goto ScriptFail\r
+)\r
+for /f "delims== tokens=1,2" %%i in (%Stitch_Config%) do (\r
+    if /i "%%i"=="HEADER"      set IFWI_HEADER=%%j\r
+    if /i "%%i"=="SEC_VERSION" set SEC_VERSION=%%j\r
+    if /i "%%i"=="Source" (\r
+        if /i "%%j"=="ALPHA" set Source_Prefix=A_\r
+        if /i "%%j"=="BF" set Source_Prefix=BF_\r
+        if /i "%%j"=="BE" set Source_Prefix=BE_\r
+        if /i "%%j"=="PV" set Source_Prefix=PV_\r
+        if /i "%%j"=="PR1" set Source_Prefix=PR1_\r
+    )\r
+)\r
+\r
+\r
+:: **********************************************************************\r
+:: The Main Stitching Loop\r
+:: **********************************************************************\r
+echo %date%  %time% >>Stitching.log 2>&1\r
+echo %date%  %time%\r
+echo.\r
+for %%i in (%BIOS_Names%) do (\r
+\r
+    REM  ----- Do NOT use :: for comments Inside of code blocks() -------\r
+    set BIOS_Rom=%%i\r
+    set BIOS_Name=%%~ni\r
+    set BIOS_Version=!BIOS_Name:~-7,7!\r
+\r
+    REM extract PlatformType from BIOS filename\r
+    set Platform_Type=!BIOS_Name:~0,4!\r
+\r
+    REM Special treat for BayLake FFD8\r
+    set Temp_Name=!BIOS_Name:~0,7!\r
+\r
+\r
+    REM Capitalize and validate the Platform_Type\r
+    if /i "!Platform_Type!"=="MNW2" (\r
+        set Platform_Type=MNW2\r
+    ) else (\r
+        echo Error - Unsupported PlatformType: !Platform_Type!\r
+        goto Usage\r
+    )\r
+\r
+\r
+    REM search BIOS_Name for Arch substring:  either IA32 or X64\r
+    if not "!BIOS_Name!"=="!BIOS_Name:_IA32_=!" (\r
+        set Arch=IA32\r
+    ) else if not "!BIOS_Name!"=="!BIOS_Name:_X64_=!" (\r
+        set Arch=X64\r
+    ) else (\r
+        echo Error:  Could not determine Architecture for !BIOS_Rom!\r
+        goto Usage\r
+    )\r
+    set IFWI_Prefix=!Platform_Type!_IFWI_%Source_Prefix%!Arch!_!!BIOS_Version!\r
+\r
+    REM search BIOS_Name for Build_Target substring: either R or D\r
+    if not "!BIOS_Name!"=="!BIOS_Name:_R_=!" (\r
+        set Build_Target=Release\r
+        set IFWI_Prefix=!IFWI_Prefix!_R\r
+    ) else if not "!BIOS_Name!"=="!BIOS_Name:_D_=!" (\r
+        set Build_Target=Debug\r
+        set IFWI_Prefix=!IFWI_Prefix!_D\r
+    ) else (\r
+        echo Error:  Could not determine Build Target for !BIOS_Rom!\r
+        goto Usage\r
+    )\r
+\r
+    REM Create a BIOS backup before Stitching\r
+    if %BackupRom% EQU 1 (\r
+        echo Creating backup of original BIOS rom.\r
+        copy /y !BIOS_Rom! !BIOS_Rom!.orig >nul\r
+    )\r
+\r
+    echo.  >>Stitching.log\r
+    echo ********** Stitching !BIOS_Rom! **********  >>Stitching.log\r
+    echo.  >>Stitching.log\r
+    echo.\r
+    echo Stitching IFWI for !BIOS_Rom! ...\r
+    echo ---------------------------------------------------------------------------\r
+    echo IFWI  Header: !IFWI_HEADER!.bin,   SEC version: !SEC_VERSION!,   \r
+    echo BIOS Version: !BIOS_Version!\r
+\r
+    echo Platform Type: !Platform_Type!,     IFWI Prefix: %BIOS_ID%\r
+    echo ---------------------------------------------------------------------------\r
+\r
+    echo -----------------------------\r
+    echo.\r
+    echo Generating IFWI... %BIOS_ID%.bin\r
+    echo.\r
+    copy /b/y IFWIHeader\!IFWI_HEADER!.bin + ..\..\Vlv2MiscBinariesPkg\SEC\!SEC_VERSION!\VLV_SEC_REGION.bin + IFWIHeader\Vacant.bin + !BIOS_Rom! %BIOS_ID%.bin\r
+    echo.\r
+    echo ===========================================================================\r
+)\r
+@echo off\r
+\r
+::**********************************************************************\r
+:: end of main loop\r
+::**********************************************************************\r
+\r
+echo.\r
+echo  -- All specified ROM files Stitched. --\r
+echo.\r
+goto Exit\r
+\r
+:Usage\r
+echo.\r
+echo **************************************************************************************************\r
+echo This Script is used to Stitch together BIOS, GOP Driver, Microcode Patch and TXE FW\r
+echo into a single Integrated Firmware Image (IFWI).\r
+echo.\r
+echo Usage: IFWIStitch.bat [flags] [/B BIOS.ROM] [/C Stitch_Config] [/S IFWI_Suffix]\r
+echo.\r
+echo    This script has NO Required arguments, so that the user can just double click from the GUI.\r
+echo    However, this requires that the BIOS.ROM file name is formatted correctly.\r
+echo.\r
+echo    /nG             Do NOT update the GOP driver.  (applies to all ROM files for this run)\r
+echo    /nV             Do NOT update the VBIOS.       (applies to all ROM files for this run)\r
+echo    /nM             Do NOT update the Microcode.   (applies to all ROM files for this run)\r
+echo    /nB             Do NOT backup BIOS.ROMs. (Default will backup to BIOS.ROM.Orig)\r
+echo.\r
+echo    BIOS.ROM:       A single BIOS ROM file to use for stitching\r
+echo                    (DEFAULT: ALL .ROM files inside the current directory)\r
+echo    Stitch_Config:  Text file containing version info of each FW component\r
+echo                    (DEFAULT: Stitch_Config.txt)\r
+echo    IFWI_Suffix:    Suffix to append to the end of the IFWI filename\r
+echo                    (DEFAULT: YYYY_MM_DD_HHMM)\r
+echo.\r
+echo Examples:\r
+echo    IFIWStitch.bat                                      : Stitch all ROMs with defaults\r
+echo    IFIWStitch.bat /B C:/MyRoms/testBIOS.rom            : Stitch single ROM with defaults\r
+echo    IFIWStitch.bat /B ../testBIOS.rom /S test123        : Stitch single ROM and add custom suffix\r
+echo    IFIWStitch.bat /nM /nB /B testBIOS.rom /S test456   : Stitch single ROM, keep uCode from .rom,\r
+echo                                                          don't create backup, and add custom suffix.\r
+echo ****************************************************************************************************\r
+pause\r
+exit /b 1\r
+\r
+:ScriptFail\r
+set exitCode=1\r
+\r
+:Exit\r
+echo  -- See Stitching.log for more info. --\r
+echo.\r
+echo %date%  %time%\r
+echo.\r
+if "%Platform_Type%"=="MNW2" (\r
+  echo .\r
+) else (\r
+  echo only support MNW2 for this project!\r
+pause\r
+)\r
+exit /b %exitCode%\r
+EndLocal\r

diff --git a/Vlv2TbltDevicePkg/Stitch/MNW2_Stitch_Config.txt b/Vlv2TbltDevicePkg/Stitch/MNW2_Stitch_Config.txt
new file mode 100644 (file)
index 0000000..5a0a2b4
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Stitch/MNW2_Stitch_Config.txt
@@ -0,0 +1,16 @@
+#\r
+# Copyright (c)  1999  - 2014, Intel Corporation. All rights reserved\r
+#\r
+# This program and the accompanying materials are licensed and made available under\r
+# the terms and conditions of the BSD License that accompanies this distribution.\r
+# The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php.\r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+#\r
+\r
+HEADER=IFWI_HEADER\r
+SEC_VERSION=1.0.2.1060v5\r
+\r

diff --git a/Vlv2TbltDevicePkg/UiApp/FrontPage.c b/Vlv2TbltDevicePkg/UiApp/FrontPage.c
new file mode 100644 (file)
index 0000000..e18a9fc
--- /dev/null
+++ b/Vlv2TbltDevicePkg/UiApp/FrontPage.c
@@ -0,0 +1,38 @@
+/** @file\r
+\r
+  Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+\r
+\r
+**/\r
+\r
+/**\r
+  The user Entry Point for Application. The user code starts with this function\r
+  as the real entry point for the image goes into a library that calls this\r
+  function.\r
+\r
+  @param[in] ImageHandle    The firmware allocated handle for the EFI image.\r
+  @param[in] SystemTable    A pointer to the EFI System Table.\r
+\r
+  @retval EFI_SUCCESS       The entry point is executed successfully.\r
+  @retval other             Some error occurs when executing this entry point.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+InitializeUserInterface (\r
+  IN EFI_HANDLE        ImageHandle,\r
+  IN EFI_SYSTEM_TABLE  *SystemTable\r
+  )\r
+{\r
+  return EFI_SUCCESS;\r
+}\r

diff --git a/Vlv2TbltDevicePkg/UiApp/UiApp.inf b/Vlv2TbltDevicePkg/UiApp/UiApp.inf
new file mode 100644 (file)
index 0000000..08b5584
--- /dev/null
+++ b/Vlv2TbltDevicePkg/UiApp/UiApp.inf
@@ -0,0 +1,37 @@
+#\r
+#\r
+# Copyright (c)  1999  - 2014, Intel Corporation. All rights reserved\r
+#                                                                                  \r\r
+# This program and the accompanying materials are licensed and made available under\r\r
+# the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+# The full text of the license may be found at                                     \r\r
+# http://opensource.org/licenses/bsd-license.php.                                  \r\r
+#                                                                                  \r\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+#                                                                                  \r\r
+#\r
+##\r
+\r
+[Defines]\r
+  INF_VERSION                    = 0x00010005\r
+  BASE_NAME                      = UiApp\r
+  FILE_GUID                      = 462CAA21-7614-4503-836E-8AB6F4662331\r
+  MODULE_TYPE                    = UEFI_APPLICATION\r
+  VERSION_STRING                 = 1.0\r
+  ENTRY_POINT                    = InitializeUserInterface\r
+\r
+#\r
+# The following information is for reference only and not required by the build tools.\r
+#\r
+#  VALID_ARCHITECTURES           = IA32 X64 IPF EBC\r
+#\r
+\r
+[Sources]\r
+  FrontPage.c\r
+\r
+[Packages]\r
+  MdePkg/MdePkg.dec\r
+\r
+[LibraryClasses]\r
+  UefiApplicationEntryPoint\r

diff --git a/Vlv2TbltDevicePkg/VlvPlatformInitDxe/IgdOpRegion.c b/Vlv2TbltDevicePkg/VlvPlatformInitDxe/IgdOpRegion.c
new file mode 100644 (file)
index 0000000..2200e6c
--- /dev/null
+++ b/Vlv2TbltDevicePkg/VlvPlatformInitDxe/IgdOpRegion.c
@@ -0,0 +1,938 @@
+\r
+/*++\r
+\r
+Copyright (c)  2011  - 2014, Intel Corporation. All rights reserved\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+\r
+Module Name:\r
+\r
+  IgdOpRegion.c\r
+\r
+Abstract:\r
+\r
+  This is part of the implementation of an Intel Graphics drivers OpRegion /\r
+  Software SCI interface between system BIOS, ASL code, and Graphics drivers.\r
+  The code in this file will load the driver and initialize the interface\r
+\r
+  Supporting Specifiction: OpRegion / Software SCI SPEC 0.70\r
+\r
+  Acronyms:\r
+    IGD:        Internal Graphics Device\r
+    NVS:        ACPI Non Volatile Storage\r
+    OpRegion:   ACPI Operational Region\r
+    VBT:        Video BIOS Table (OEM customizable data)\r
+\r
+--*/\r
+\r
+//\r
+// Include files\r
+//\r
+\r
+\r
+#include "IgdOpRegion.h"\r
+#include "VlvPlatformInit.h"\r
+#include <FrameworkDxe.h>\r
+#include <Uefi.h>\r
+#include <PchRegs.h>\r
+\r
+#include <Guid/DataHubRecords.h>\r
+\r
+#include <Protocol/IgdOpRegion.h>\r
+#include <Protocol/FrameworkHii.h>\r
+#include <Protocol/FirmwareVolume.h>\r
+#include <Protocol/PlatformGopPolicy.h>\r
+#include <Protocol/PciIo.h>\r
+#include <Protocol/CpuIo.h>\r
+#include <Protocol/GlobalNvsArea.h>\r
+#include <Protocol/DxeSmmReadyToLock.h>\r
+#include <Protocol/PciRootBridgeIo.h>\r
+\r
+#include <Library/MemoryAllocationLib.h>\r
+#include <Library/BaseLib.h>\r
+#include <Library/S3BootScriptLib.h>\r
+#include <Library/IoLib.h>\r
+#include <Library/DevicePathLib.h>\r
+#include <Protocol/DriverBinding.h>\r
+#include <Library/PrintLib.h>\r
+#include <Library/BaseMemoryLib.h>\r
+\r
+\r
+\r
+UINT8 gSVER[12] = "Intel";\r
+\r
+extern DXE_VLV_PLATFORM_POLICY_PROTOCOL  *DxePlatformSaPolicy;\r
+\r
+//\r
+// Global variables\r
+//\r
+\r
+IGD_OPREGION_PROTOCOL mIgdOpRegion;\r
+EFI_GUID              mMiscSubClass = EFI_MISC_SUBCLASS_GUID;\r
+EFI_EVENT             mConOutEvent;\r
+EFI_EVENT             mSetGOPverEvent;\r
+VOID                  *mConOutReg;\r
+\r
+#define DEFAULT_FORM_BUFFER_SIZE    0xFFFF\r
+#ifndef ECP_FLAG\r
+#if 0\r
+/**\r
+\r
+  Get the HII protocol interface\r
+\r
+  @param Hii     HII protocol interface\r
+\r
+  @retval        Status code\r
+\r
+**/\r
+static\r
+EFI_STATUS\r
+GetHiiInterface (\r
+  OUT     EFI_HII_PROTOCOL    **Hii\r
+  )\r
+{\r
+  EFI_STATUS  Status;\r
+\r
+  //\r
+  // There should only be one HII protocol\r
+  //\r
+  Status = gBS->LocateProtocol (\r
+                  &gEfiHiiProtocolGuid,\r
+                  NULL,\r
+                  (VOID **) Hii\r
+                  );\r
+\r
+  return Status;;\r
+}\r
+#endif\r
+#endif\r
+\r
+/**\r
+\r
+  Get VBT data.\r
+\r
+  @param[in] VbtFileBuffer    Pointer to VBT data buffer.\r
+\r
+  @retval EFI_SUCCESS      VBT data was returned.\r
+  @retval EFI_NOT_FOUND    VBT data not found.\r
+  @exception EFI_UNSUPPORTED  Invalid signature in VBT data.\r
+\r
+**/\r
+EFI_STATUS\r
+GetIntegratedIntelVbtPtr (\r
+  OUT VBIOS_VBT_STRUCTURE **VbtFileBuffer\r
+  )\r
+{\r
+  EFI_STATUS                    Status;\r
+  EFI_PHYSICAL_ADDRESS          VbtAddress = 0;\r
+  UINT32                        VbtSize = 0;\r
+  UINTN                         FvProtocolCount;\r
+  EFI_HANDLE                    *FvHandles;\r
+  EFI_FIRMWARE_VOLUME_PROTOCOL  *Fv;\r
+  UINTN                         Index;\r
+  UINT32                        AuthenticationStatus;\r
+\r
+  UINT8                         *Buffer;\r
+  UINTN                         VbtBufferSize = 0;\r
+\r
+  Buffer = 0;\r
+  FvHandles      = NULL;\r
+  *VbtFileBuffer = NULL;\r
+  Status = gBS->LocateHandleBuffer (\r
+                  ByProtocol,\r
+                  &gEfiFirmwareVolumeProtocolGuid,\r
+                  NULL,\r
+                  &FvProtocolCount,\r
+                  &FvHandles\r
+                  );\r
+\r
+  if (!EFI_ERROR (Status)) {\r
+    for (Index = 0; Index < FvProtocolCount; Index++) {\r
+      Status = gBS->HandleProtocol (\r
+                      FvHandles[Index],\r
+                      &gEfiFirmwareVolumeProtocolGuid,\r
+                      (VOID **) &Fv\r
+                      );\r
+      VbtBufferSize = 0;\r
+      Status = Fv->ReadSection (\r
+                     Fv,\r
+                     &gBmpImageGuid,\r
+                     EFI_SECTION_RAW,\r
+                     0,\r
+                    (void **)&Buffer,\r
+                     &VbtBufferSize,\r
+                     &AuthenticationStatus\r
+                     );\r
+\r
+      if (!EFI_ERROR (Status)) {\r
+        VbtAddress = (EFI_PHYSICAL_ADDRESS)(UINTN)Buffer;\r
+        VbtSize = (UINT32)VbtBufferSize;\r
+        Status = EFI_SUCCESS;\r
+        break;\r
+      }\r
+    }\r
+  } else {\r
+    Status = EFI_NOT_FOUND;\r
+  }\r
+\r
+  if (FvHandles != NULL) {\r
+    FreePool(FvHandles);\r
+    FvHandles = NULL;\r
+  }\r
+\r
+\r
+  //\r
+  // Check VBT signature\r
+  //\r
+  *VbtFileBuffer = (VBIOS_VBT_STRUCTURE *) (UINTN) VbtAddress;\r
+  if (*VbtFileBuffer != NULL) {\r
+    if ((*((UINT32 *) ((*VbtFileBuffer)->HeaderSignature))) != VBT_SIGNATURE) {\r
+      if (*VbtFileBuffer != NULL) {\r
+        *VbtFileBuffer = NULL;\r
+      }\r
+      return EFI_UNSUPPORTED;\r
+    }\r
+    //\r
+    // Check VBT size\r
+    //\r
+    if ((*VbtFileBuffer)->HeaderVbtSize > VbtBufferSize) {\r
+      (*VbtFileBuffer)->HeaderVbtSize = (UINT16) VbtBufferSize;\r
+    }\r
+  }\r
+\r
+  return EFI_SUCCESS;\r
+}\r
+\r
+//\r
+// Function implementations.\r
+//\r
+/**\r
+\r
+  Get a pointer to an uncompressed image of the Intel video BIOS.\r
+\r
+  Note: This function would only be called if the video BIOS at 0xC000 is\r
+        missing or not an Intel video BIOS.  It may not be an Intel video BIOS\r
+        if the Intel graphic contoller is considered a secondary adapter.\r
+\r
+\r
+  @param VBiosROMImage  Pointer to an uncompressed Intel video BIOS.  This pointer must\r
+                        be set to NULL if an uncompressed image of the Intel Video BIOS\r
+                        is not obtainable.\r
+\r
+\r
+  @retval EFI_SUCCESS   VBiosPtr is updated.\r
+\r
+**/\r
+EFI_STATUS\r
+GetIntegratedIntelVBiosPtr (\r
+  INTEL_VBIOS_OPTION_ROM_HEADER **VBiosImage\r
+  )\r
+{\r
+  EFI_HANDLE                  *HandleBuffer;\r
+  UINTN                       HandleCount;\r
+  UINTN                       Index;\r
+  INTEL_VBIOS_PCIR_STRUCTURE  *PcirBlockPtr;\r
+  EFI_STATUS                  Status;\r
+  EFI_PCI_IO_PROTOCOL         *PciIo;\r
+  INTEL_VBIOS_OPTION_ROM_HEADER *VBiosRomImage;\r
+\r
+  //\r
+  // Set as if an umcompressed Intel video BIOS image was not obtainable.\r
+  //\r
+  VBiosRomImage = NULL;\r
+  *VBiosImage = NULL;\r
+\r
+  //\r
+  // Get all PCI IO protocols\r
+  //\r
+  Status = gBS->LocateHandleBuffer (\r
+                  ByProtocol,\r
+                  &gEfiPciIoProtocolGuid,\r
+                  NULL,\r
+                  &HandleCount,\r
+                  &HandleBuffer\r
+                  );\r
+  ASSERT_EFI_ERROR (Status);\r
+\r
+  //\r
+  // Find the video BIOS by checking each PCI IO handle for an Intel video\r
+  // BIOS OPROM.\r
+  //\r
+  for (Index = 0; Index < HandleCount; Index++) {\r
+    Status = gBS->HandleProtocol (\r
+                    HandleBuffer[Index],\r
+                    &gEfiPciIoProtocolGuid,\r
+                    (void **)&PciIo\r
+                    );\r
+    ASSERT_EFI_ERROR (Status);\r
+\r
+    VBiosRomImage = PciIo->RomImage;\r
+\r
+    //\r
+    // If this PCI device doesn't have a ROM image, skip to the next device.\r
+    //\r
+    if (!VBiosRomImage) {\r
+      continue;\r
+    }\r
+\r
+    //\r
+    // Get pointer to PCIR structure\r
+    //\r
+    PcirBlockPtr = (INTEL_VBIOS_PCIR_STRUCTURE *)((UINT8 *) VBiosRomImage + VBiosRomImage->PcirOffset);\r
+\r
+    //\r
+    // Check if we have an Intel video BIOS OPROM.\r
+    //\r
+    if ((VBiosRomImage->Signature == OPTION_ROM_SIGNATURE) &&\r
+        (PcirBlockPtr->VendorId == IGD_VID) &&\r
+        (PcirBlockPtr->ClassCode[0] == 0x00) &&\r
+        (PcirBlockPtr->ClassCode[1] == 0x00) &&\r
+        (PcirBlockPtr->ClassCode[2] == 0x03)\r
+       ) {\r
+      //\r
+      // Found Intel video BIOS.\r
+      //\r
+      *VBiosImage = VBiosRomImage;\r
+      return EFI_SUCCESS;\r
+    }\r
+  }\r
+\r
+  //\r
+  // No Intel video BIOS found.\r
+  //\r
+\r
+  //\r
+  // Free any allocated buffers\r
+  //\r
+  return EFI_UNSUPPORTED;\r
+}\r
+\r
+EFI_STATUS\r
+SearchChildHandle(\r
+  EFI_HANDLE Father,\r
+  EFI_HANDLE *Child\r
+  )\r
+{\r
+  EFI_STATUS            Status;\r
+  UINTN                 HandleIndex;\r
+  EFI_GUID              **ProtocolGuidArray = NULL;\r
+  UINTN                 ArrayCount;\r
+  UINTN                 ProtocolIndex;\r
+  UINTN                 OpenInfoCount;\r
+  UINTN                 OpenInfoIndex;\r
+  EFI_OPEN_PROTOCOL_INFORMATION_ENTRY  *OpenInfo = NULL;\r
+  UINTN                 mHandleCount;\r
+  EFI_HANDLE            *mHandleBuffer= NULL;\r
+\r
+  //\r
+  // Retrieve the list of all handles from the handle database\r
+  //\r
+  Status = gBS->LocateHandleBuffer (\r
+                  AllHandles,\r
+                  NULL,\r
+                  NULL,\r
+                  &mHandleCount,\r
+                  &mHandleBuffer\r
+                  );\r
+\r
+  for (HandleIndex = 0; HandleIndex < mHandleCount; HandleIndex++) {\r
+    //\r
+    // Retrieve the list of all the protocols on each handle\r
+    //\r
+    Status = gBS->ProtocolsPerHandle (\r
+                    mHandleBuffer[HandleIndex],\r
+                    &ProtocolGuidArray,\r
+                    &ArrayCount\r
+                    );\r
+    if (!EFI_ERROR (Status)) {\r
+      for (ProtocolIndex = 0; ProtocolIndex < ArrayCount; ProtocolIndex++) {\r
+        Status = gBS->OpenProtocolInformation (\r
+                        mHandleBuffer[HandleIndex],\r
+                        ProtocolGuidArray[ProtocolIndex],\r
+                        &OpenInfo,\r
+                        &OpenInfoCount\r
+                        );\r
+        if (!EFI_ERROR (Status)) {\r
+          for (OpenInfoIndex = 0; OpenInfoIndex < OpenInfoCount; OpenInfoIndex++) {\r
+            if(OpenInfo[OpenInfoIndex].AgentHandle == Father) {\r
+              if ((OpenInfo[OpenInfoIndex].Attributes & EFI_OPEN_PROTOCOL_BY_CHILD_CONTROLLER) == EFI_OPEN_PROTOCOL_BY_CHILD_CONTROLLER) {\r
+                *Child = mHandleBuffer[HandleIndex];\r
+                Status = EFI_SUCCESS;\r
+                goto TryReturn;\r
+              }\r
+            }\r
+          }\r
+          Status = EFI_NOT_FOUND;\r
+        }\r
+      }\r
+      if(OpenInfo != NULL) {\r
+        FreePool(OpenInfo);\r
+        OpenInfo = NULL;\r
+      }\r
+    }\r
+    FreePool (ProtocolGuidArray);\r
+    ProtocolGuidArray = NULL;\r
+  }\r
+TryReturn:\r
+  if(OpenInfo != NULL) {\r
+    FreePool (OpenInfo);\r
+    OpenInfo = NULL;\r
+  }\r
+  if(ProtocolGuidArray != NULL) {\r
+    FreePool(ProtocolGuidArray);\r
+    ProtocolGuidArray = NULL;\r
+  }\r
+  if(mHandleBuffer != NULL) {\r
+    FreePool (mHandleBuffer);\r
+    mHandleBuffer = NULL;\r
+  }\r
+  return Status;\r
+}\r
+\r
+EFI_STATUS\r
+JudgeHandleIsPCIDevice(\r
+  EFI_HANDLE            Handle,\r
+  UINT8                 Device,\r
+  UINT8                 Funs\r
+  )\r
+{\r
+  EFI_STATUS  Status;\r
+  EFI_DEVICE_PATH   *DPath;\r
+  EFI_DEVICE_PATH   *DevicePath;\r
+\r
+  Status = gBS->HandleProtocol (\r
+                  Handle,\r
+                  &gEfiDevicePathProtocolGuid,\r
+                  (VOID **) &DPath\r
+                  );\r
+  if(!EFI_ERROR(Status)) {\r
+    DevicePath = DPath;\r
+    while(!IsDevicePathEnd(DPath)) {\r
+      if((DPath->Type == HARDWARE_DEVICE_PATH) && (DPath->SubType == HW_PCI_DP)) {\r
+        PCI_DEVICE_PATH   *PCIPath;\r
+\r
+        PCIPath = (PCI_DEVICE_PATH*) DPath;\r
+        DPath = NextDevicePathNode(DPath);\r
+        if(IsDevicePathEnd(DPath) && (PCIPath->Device == Device) && (PCIPath->Function == Funs)) {\r
+          return EFI_SUCCESS;\r
+        }\r
+      } else {\r
+        DPath = NextDevicePathNode(DPath);\r
+      }\r
+    }\r
+  }\r
+  return EFI_UNSUPPORTED;\r
+}\r
+\r
+EFI_STATUS\r
+GetDriverName(\r
+  EFI_HANDLE   Handle,\r
+  CHAR16         *GopVersion\r
+  )\r
+{\r
+  EFI_DRIVER_BINDING_PROTOCOL           *BindHandle = NULL;\r
+  EFI_STATUS                            Status;\r
+  UINT32                                Version;\r
+  UINT16                                *Ptr;\r
+\r
+  Status = gBS->OpenProtocol(\r
+                  Handle,\r
+                  &gEfiDriverBindingProtocolGuid,\r
+                  (VOID**)&BindHandle,\r
+                  NULL,\r
+                  NULL,\r
+                  EFI_OPEN_PROTOCOL_GET_PROTOCOL\r
+                  );\r
+  if (EFI_ERROR(Status)) {\r
+    return EFI_NOT_FOUND;\r
+  }\r
+\r
+  Version = BindHandle->Version;\r
+  Ptr = (UINT16*)&Version;\r
+  UnicodeSPrint(GopVersion, 40, L"7.0.%04d", *(Ptr));\r
+  return EFI_SUCCESS;\r
+}\r
+\r
+EFI_STATUS\r
+GetGOPDriverVersion(\r
+  CHAR16 *GopVersion\r
+  )\r
+{\r
+  UINTN                 HandleCount;\r
+  EFI_HANDLE            *Handles= NULL;\r
+  UINTN                 Index;\r
+  EFI_STATUS            Status;\r
+  EFI_HANDLE            Child = 0;\r
+\r
+  Status = gBS->LocateHandleBuffer(\r
+                  ByProtocol,\r
+                  &gEfiDriverBindingProtocolGuid,\r
+                  NULL,\r
+                  &HandleCount,\r
+                  &Handles\r
+                  );\r
+  for (Index = 0; Index < HandleCount ; Index++) {\r
+    Status = SearchChildHandle(Handles[Index], &Child);\r
+    if(!EFI_ERROR(Status)) {\r
+      Status = JudgeHandleIsPCIDevice(Child, 0x02, 0x00);\r
+      if(!EFI_ERROR(Status)) {\r
+        return GetDriverName(Handles[Index], GopVersion);\r
+      }\r
+    }\r
+  }\r
+  return EFI_UNSUPPORTED;\r
+}\r
+\r
+\r
+/**\r
+  Get Intel GOP driver version and copy it into IGD OpRegion GVER. This version\r
+  is picked up by IGD driver and displayed in CUI.\r
+\r
+  @param  Event             A pointer to the Event that triggered the callback.\r
+  @param  Context           A pointer to private data registered with the callback function.\r
+\r
+  @retval EFI_SUCCESS       Video BIOS VBT information returned.\r
+  @retval EFI_UNSUPPORTED   Could not find VBT information (*VBiosVbtPtr = NULL).\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+SetGOPVersionCallback (\r
+  IN EFI_EVENT Event,\r
+  IN VOID      *Context\r
+  )\r
+{\r
+  CHAR16                GopVersion[16] = {0};\r
+  EFI_STATUS            Status;\r
+\r
+  Status = GetGOPDriverVersion(GopVersion);\r
+  if(!EFI_ERROR(Status)) {\r
+    StrCpy((CHAR16*)&(mIgdOpRegion.OpRegion->Header.GOPV[0]), GopVersion);\r
+    return Status;\r
+  }\r
+  return EFI_UNSUPPORTED;\r
+}\r
+\r
+/**\r
+  Get Intel video BIOS VBT information (i.e. Pointer to VBT and VBT size).\r
+  The VBT (Video BIOS Table) is a block of customizable data that is built\r
+  within the video BIOS and edited by customers.\r
+\r
+  @param  Event             A pointer to the Event that triggered the callback.\r
+  @param  Context           A pointer to private data registered with the callback function.\r
+\r
+  @retval EFI_SUCCESS       Video BIOS VBT information returned.\r
+  @retval EFI_UNSUPPORTED   Could not find VBT information (*VBiosVbtPtr = NULL).\r
+\r
+**/\r
+EFI_STATUS\r
+GetVBiosVbtCallback (\r
+  IN EFI_EVENT Event,\r
+  IN VOID      *Context\r
+  )\r
+{\r
+  INTEL_VBIOS_PCIR_STRUCTURE    *PcirBlockPtr;\r
+  UINT16                        PciVenderId;\r
+  UINT16                        PciDeviceId;\r
+  INTEL_VBIOS_OPTION_ROM_HEADER *VBiosPtr;\r
+  VBIOS_VBT_STRUCTURE           *VBiosVbtPtr;\r
+  VBIOS_VBT_STRUCTURE           *VbtFileBuffer = NULL;\r
+\r
+  VBiosPtr = (INTEL_VBIOS_OPTION_ROM_HEADER *)(UINTN)(VBIOS_LOCATION_PRIMARY);\r
+  PcirBlockPtr = (INTEL_VBIOS_PCIR_STRUCTURE *)((UINT8 *)VBiosPtr + VBiosPtr->PcirOffset);\r
+  PciVenderId = PcirBlockPtr->VendorId;\r
+  PciDeviceId = PcirBlockPtr->DeviceId;\r
+\r
+  //\r
+  // If the video BIOS is not at 0xC0000 or it is not an Intel video BIOS get\r
+  // the integrated Intel video BIOS (must be uncompressed).\r
+  //\r
+  if ((VBiosPtr->Signature != OPTION_ROM_SIGNATURE) || (PciVenderId != IGD_VID) || (PciDeviceId != IGD_DID_VLV)) {\r
+    GetIntegratedIntelVBiosPtr (&VBiosPtr);\r
+\r
+    if(VBiosPtr) {\r
+      //\r
+      // Video BIOS found.\r
+      //\r
+      PcirBlockPtr = (INTEL_VBIOS_PCIR_STRUCTURE *)((UINT8 *)VBiosPtr + VBiosPtr->PcirOffset);\r
+      PciVenderId = PcirBlockPtr->VendorId;\r
+      if( (VBiosPtr->Signature != OPTION_ROM_SIGNATURE) || (PciVenderId != IGD_VID)) {\r
+        //\r
+        // Intel video BIOS not found.\r
+        //\r
+        VBiosVbtPtr = NULL;\r
+        return EFI_UNSUPPORTED;\r
+      }\r
+    } else {\r
+      //\r
+      // No Video BIOS found, try to get VBT from FV.\r
+      //\r
+      GetIntegratedIntelVbtPtr (&VbtFileBuffer);\r
+      if (VbtFileBuffer != NULL) {\r
+        //\r
+        // Video BIOS not found, use VBT from FV\r
+        //\r
+        DEBUG ((EFI_D_ERROR, "VBT data found\n"));\r
+        (gBS->CopyMem) (\r
+                mIgdOpRegion.OpRegion->VBT.GVD1,\r
+                VbtFileBuffer,\r
+                VbtFileBuffer->HeaderVbtSize\r
+                );\r
+        FreePool (VbtFileBuffer);\r
+        return EFI_SUCCESS;\r
+      }\r
+    }\r
+    if ((VBiosPtr == NULL) ) {\r
+      //\r
+      // Intel video BIOS not found.\r
+      //\r
+      VBiosVbtPtr = NULL;\r
+      return EFI_UNSUPPORTED;\r
+    }\r
+  }\r
+\r
+  DEBUG ((EFI_D_ERROR, "VBIOS found at 0x%X\n", VBiosPtr));\r
+  VBiosVbtPtr = (VBIOS_VBT_STRUCTURE *) ((UINT8 *) VBiosPtr + VBiosPtr->VbtOffset);\r
+\r
+  if ((*((UINT32 *) (VBiosVbtPtr->HeaderSignature))) != VBT_SIGNATURE) {\r
+    return EFI_UNSUPPORTED;\r
+  }\r
+\r
+  //\r
+  // Initialize Video BIOS version with its build number.\r
+  //\r
+  mIgdOpRegion.OpRegion->Header.VVER[0] = VBiosVbtPtr->CoreBlockBiosBuild[0];\r
+  mIgdOpRegion.OpRegion->Header.VVER[1] = VBiosVbtPtr->CoreBlockBiosBuild[1];\r
+  mIgdOpRegion.OpRegion->Header.VVER[2] = VBiosVbtPtr->CoreBlockBiosBuild[2];\r
+  mIgdOpRegion.OpRegion->Header.VVER[3] = VBiosVbtPtr->CoreBlockBiosBuild[3];\r
+  (gBS->CopyMem) (\r
+          mIgdOpRegion.OpRegion->VBT.GVD1,\r
+          VBiosVbtPtr,\r
+          VBiosVbtPtr->HeaderVbtSize\r
+          );\r
+\r
+  //\r
+  // Return final status\r
+  //\r
+  return EFI_SUCCESS;\r
+}\r
+\r
+/**\r
+  Graphics OpRegion / Software SCI driver installation function.\r
+\r
+  @param ImageHandle     Handle for this drivers loaded image protocol.\r
+  @param SystemTable     EFI system table.\r
+\r
+  @retval EFI_SUCCESS    The driver installed without error.\r
+  @retval EFI_ABORTED    The driver encountered an error and could not complete\r
+                         installation of the ACPI tables.\r
+\r
+**/\r
+EFI_STATUS\r
+IgdOpRegionInit (\r
+  void\r
+  )\r
+{\r
+  EFI_HANDLE                    Handle;\r
+  EFI_STATUS                    Status;\r
+  EFI_GLOBAL_NVS_AREA_PROTOCOL  *GlobalNvsArea;\r
+  UINT32                        DwordData;\r
+  EFI_CPU_IO_PROTOCOL           *CpuIo;\r
+  UINT16                        Data16;\r
+  UINT16                        AcpiBase;\r
+  VOID                          *gConOutNotifyReg;\r
+\r
+\r
+  //\r
+  //  Locate the Global NVS Protocol.\r
+  //\r
+  Status = gBS->LocateProtocol (\r
+                  &gEfiGlobalNvsAreaProtocolGuid,\r
+                  NULL,\r
+                  (void **)&GlobalNvsArea\r
+                  );\r
+  ASSERT_EFI_ERROR (Status);\r
+\r
+  //\r
+  // Allocate an ACPI NVS memory buffer as the IGD OpRegion, zero initialize\r
+  // the first 1K, and set the IGD OpRegion pointer in the Global NVS\r
+  // area structure.\r
+  //\r
+  Status = (gBS->AllocatePool) (\r
+                   EfiACPIMemoryNVS,\r
+                   sizeof (IGD_OPREGION_STRUC),\r
+                  (void **)&mIgdOpRegion.OpRegion\r
+                   );\r
+  ASSERT_EFI_ERROR (Status);\r
+  (gBS->SetMem) (\r
+          mIgdOpRegion.OpRegion,\r
+          sizeof (IGD_OPREGION_STRUC),\r
+          0\r
+          );\r
+  GlobalNvsArea->Area->IgdOpRegionAddress = (UINT32)(UINTN)(mIgdOpRegion.OpRegion);\r
+\r
+  //\r
+  // If IGD is disabled return\r
+  //\r
+  if (IgdMmPci32 (0) == 0xFFFFFFFF) {\r
+    return EFI_SUCCESS;\r
+  }\r
+\r
+  //\r
+  // Initialize OpRegion Header\r
+  //\r
+\r
+  (gBS->CopyMem) (\r
+          mIgdOpRegion.OpRegion->Header.SIGN,\r
+          HEADER_SIGNATURE,\r
+          sizeof(HEADER_SIGNATURE)\r
+          );\r
+\r
+\r
+  //\r
+  // Set OpRegion Size in KBs\r
+  //\r
+  mIgdOpRegion.OpRegion->Header.SIZE = HEADER_SIZE/1024;\r
+\r
+  //\r
+  // FIXME: Need to check Header OVER Field and the supported version.\r
+  //\r
+  mIgdOpRegion.OpRegion->Header.OVER = (UINT32) (LShiftU64 (HEADER_OPREGION_VER, 16) + LShiftU64 (HEADER_OPREGION_REV, 8));\r
+#ifdef ECP_FLAG\r
+  CopyMem(mIgdOpRegion.OpRegion->Header.SVER, gSVER, sizeof(gSVER));\r
+#else\r
+  gBS->CopyMem(\r
+         mIgdOpRegion.OpRegion->Header.SVER,\r
+         gSVER,\r
+         sizeof(gSVER)\r
+         );\r
+#endif\r
+  DEBUG ((EFI_D_ERROR, "System BIOS ID is %a\n", mIgdOpRegion.OpRegion->Header.SVER));\r
+\r
+\r
+  mIgdOpRegion.OpRegion->Header.MBOX = HEADER_MBOX_SUPPORT;\r
+\r
+  if( 1 == DxePlatformSaPolicy->IdleReserve) {\r
+    mIgdOpRegion.OpRegion->Header.PCON = (mIgdOpRegion.OpRegion->Header.PCON & 0xFFFC) | BIT1;\r
+  } else {\r
+    mIgdOpRegion.OpRegion->Header.PCON = (mIgdOpRegion.OpRegion->Header.PCON & 0xFFFC) | (BIT1 | BIT0);\r
+  }\r
+\r
+  //\r
+  //For graphics driver to identify if LPE Audio/HD Audio is enabled on the platform\r
+  //\r
+  mIgdOpRegion.OpRegion->Header.PCON &= AUDIO_TYPE_SUPPORT_MASK;\r
+  mIgdOpRegion.OpRegion->Header.PCON &= AUDIO_TYPE_FIELD_MASK;\r
+  if ( 1 == DxePlatformSaPolicy->AudioTypeSupport ) {\r
+    mIgdOpRegion.OpRegion->Header.PCON = HD_AUDIO_SUPPORT;\r
+    mIgdOpRegion.OpRegion->Header.PCON |= AUDIO_TYPE_FIELD_VALID;\r
+  }\r
+\r
+  //\r
+  // Initialize OpRegion Mailbox 1 (Public ACPI Methods).\r
+  //\r
+  //<TODO> The initial setting of mailbox 1 fields is implementation specific.\r
+  // Adjust them as needed many even coming from user setting in setup.\r
+  //\r
+  //Workaround to solve LVDS is off after entering OS in desktop platform\r
+  //\r
+  mIgdOpRegion.OpRegion->MBox1.CLID = DxePlatformSaPolicy->IgdPanelFeatures.LidStatus;\r
+\r
+  //\r
+  // Initialize OpRegion Mailbox 3 (ASLE Interrupt and Power Conservation).\r
+  //\r
+  //<TODO> The initial setting of mailbox 3 fields is implementation specific.\r
+  // Adjust them as needed many even coming from user setting in setup.\r
+  //\r
+\r
+  //\r
+  // Do not initialize TCHE. This field is written by the graphics driver only.\r
+  //\r
+\r
+  //\r
+  // The ALSI field is generally initialized by ASL code by reading the embedded controller.\r
+  //\r
+\r
+  mIgdOpRegion.OpRegion->MBox3.BCLP = BACKLIGHT_BRIGHTNESS;\r
+\r
+  mIgdOpRegion.OpRegion->MBox3.PFIT = (FIELD_VALID_BIT | PFIT_STRETCH);\r
+  if ( DxePlatformSaPolicy->IgdPanelFeatures.PFITStatus == 2) {\r
+       //\r
+    // Center\r
+    //\r
+    mIgdOpRegion.OpRegion->MBox3.PFIT = (FIELD_VALID_BIT | PFIT_CENTER);\r
+  } else if (DxePlatformSaPolicy->IgdPanelFeatures.PFITStatus == 1) {\r
+       //\r
+    // Stretch\r
+    //\r
+    mIgdOpRegion.OpRegion->MBox3.PFIT = (FIELD_VALID_BIT | PFIT_STRETCH);\r
+  } else {\r
+       //\r
+    // Auto\r
+    //\r
+    mIgdOpRegion.OpRegion->MBox3.PFIT = (FIELD_VALID_BIT | PFIT_SETUP_AUTO);\r
+  }\r
+\r
+  //\r
+  // Set Initial current Brightness\r
+  //\r
+  mIgdOpRegion.OpRegion->MBox3.CBLV = (INIT_BRIGHT_LEVEL | FIELD_VALID_BIT);\r
+\r
+  //\r
+  // <EXAMPLE> Create a static Backlight Brightness Level Duty cycle Mapping Table\r
+  // Possible 20 entries (example used 10), each 16 bits as follows:\r
+  // [15] = Field Valid bit, [14:08] = Level in Percentage (0-64h), [07:00] = Desired duty cycle (0 - FFh).\r
+  //\r
+  //                                             %            Brightness\r
+  mIgdOpRegion.OpRegion->MBox3.BCLM[0]   = ( (  0 << 8 ) + ( 0xFF - 0xFC ) + WORD_FIELD_VALID_BIT);\r
+  mIgdOpRegion.OpRegion->MBox3.BCLM[1]   = ( (  1 << 8 ) + ( 0xFF - 0xFC ) + WORD_FIELD_VALID_BIT);\r
+  mIgdOpRegion.OpRegion->MBox3.BCLM[2]   = ( ( 10 << 8 ) + ( 0xFF - 0xE5 ) + WORD_FIELD_VALID_BIT);\r
+  mIgdOpRegion.OpRegion->MBox3.BCLM[3]   = ( ( 19 << 8 ) + ( 0xFF - 0xCE ) + WORD_FIELD_VALID_BIT);\r
+  mIgdOpRegion.OpRegion->MBox3.BCLM[4]   = ( ( 28 << 8 ) + ( 0xFF - 0xB7 ) + WORD_FIELD_VALID_BIT);\r
+  mIgdOpRegion.OpRegion->MBox3.BCLM[5]   = ( ( 37 << 8 ) + ( 0xFF - 0xA0 ) + WORD_FIELD_VALID_BIT);\r
+  mIgdOpRegion.OpRegion->MBox3.BCLM[6]   = ( ( 46 << 8 ) + ( 0xFF - 0x89 ) + WORD_FIELD_VALID_BIT);\r
+  mIgdOpRegion.OpRegion->MBox3.BCLM[7]   = ( ( 55 << 8 ) + ( 0xFF - 0x72 ) + WORD_FIELD_VALID_BIT);\r
+  mIgdOpRegion.OpRegion->MBox3.BCLM[8]   = ( ( 64 << 8 ) + ( 0xFF - 0x5B ) + WORD_FIELD_VALID_BIT);\r
+  mIgdOpRegion.OpRegion->MBox3.BCLM[9]   = ( ( 73 << 8 ) + ( 0xFF - 0x44 ) + WORD_FIELD_VALID_BIT);\r
+  mIgdOpRegion.OpRegion->MBox3.BCLM[10]  = ( ( 82 << 8 ) + ( 0xFF - 0x2D ) + WORD_FIELD_VALID_BIT);\r
+  mIgdOpRegion.OpRegion->MBox3.BCLM[11]  = ( ( 91 << 8 ) + ( 0xFF - 0x16 ) + WORD_FIELD_VALID_BIT);\r
+  mIgdOpRegion.OpRegion->MBox3.BCLM[12]  = ( (100 << 8 ) + ( 0xFF - 0x00 ) + WORD_FIELD_VALID_BIT);\r
+\r
+  mIgdOpRegion.OpRegion->MBox3.PCFT = ((UINT32) GlobalNvsArea->Area->IgdPowerConservation) | BIT31;\r
+  //\r
+  // Create the notification and register callback function on the PciIo installation,\r
+  //\r
+  //\r
+  Status = gBS->CreateEvent (\r
+                  EVT_NOTIFY_SIGNAL,\r
+                  TPL_CALLBACK,\r
+                  (EFI_EVENT_NOTIFY)GetVBiosVbtCallback,\r
+                  NULL,\r
+                  &mConOutEvent\r
+                  );\r
+\r
+  ASSERT_EFI_ERROR (Status);\r
+  if (EFI_ERROR (Status)) {\r
+    return Status;\r
+\r
+  }\r
+\r
+  Status = gBS->RegisterProtocolNotify (\r
+#ifdef ECP_FLAG\r
+                  &gExitPmAuthProtocolGuid,\r
+#else\r
+                  &gEfiDxeSmmReadyToLockProtocolGuid,\r
+#endif\r
+                  mConOutEvent,\r
+                  &gConOutNotifyReg\r
+                  );\r
+\r
+  Status = gBS->CreateEvent (\r
+                  EVT_NOTIFY_SIGNAL,\r
+                  TPL_CALLBACK,\r
+                  (EFI_EVENT_NOTIFY)SetGOPVersionCallback,\r
+                  NULL,\r
+                  &mSetGOPverEvent\r
+                  );\r
+\r
+  ASSERT_EFI_ERROR (Status);\r
+  if (EFI_ERROR (Status)) {\r
+    return Status;\r
+  }\r
+\r
+  Status = gBS->RegisterProtocolNotify (\r
+                  &gEfiGraphicsOutputProtocolGuid,\r
+                  mSetGOPverEvent,\r
+                  &gConOutNotifyReg\r
+                  );\r
+\r
+\r
+  //\r
+  // Initialize hardware state:\r
+  //   Set ASLS Register to the OpRegion physical memory address.\r
+  //   Set SWSCI register bit 15 to a "1" to activate SCI interrupts.\r
+  //\r
+\r
+  IgdMmPci32 (IGD_ASLS_OFFSET) = (UINT32)(UINTN)(mIgdOpRegion.OpRegion);\r
+  IgdMmPci16AndThenOr (IGD_SWSCI_OFFSET, ~(BIT0), BIT15);\r
+\r
+  DwordData = IgdMmPci32 (IGD_ASLS_OFFSET);\r
+  S3BootScriptSavePciCfgWrite (\r
+    S3BootScriptWidthUint32,\r
+    (UINTN) (EFI_PCI_ADDRESS  (IGD_BUS, IGD_DEV, IGD_FUN_0, IGD_ASLS_OFFSET)),\r
+    1,\r
+    &DwordData\r
+    );\r
+\r
+\r
+  DwordData = IgdMmPci32 (IGD_SWSCI_OFFSET);\r
+  S3BootScriptSavePciCfgWrite (\r
+    S3BootScriptWidthUint32,\r
+    (UINTN) (EFI_PCI_ADDRESS  (IGD_BUS, IGD_DEV, IGD_FUN_0, IGD_SWSCI_OFFSET)),\r
+    1,\r
+    &DwordData\r
+    );\r
+\r
+  AcpiBase =  MmPci16 (\r
+                0,\r
+                DEFAULT_PCI_BUS_NUMBER_PCH,\r
+                PCI_DEVICE_NUMBER_PCH_LPC,\r
+                PCI_FUNCTION_NUMBER_PCH_LPC,\r
+                R_PCH_LPC_ACPI_BASE\r
+                ) & B_PCH_LPC_ACPI_BASE_BAR;\r
+\r
+  //\r
+  // Find the CPU I/O Protocol.  ASSERT if not found.\r
+  //\r
+  Status = gBS->LocateProtocol (\r
+                  &gEfiCpuIoProtocolGuid,\r
+                  NULL,\r
+                  (void **)&CpuIo\r
+                  );\r
+  ASSERT_EFI_ERROR (Status);\r
+\r
+  CpuIo->Io.Read (\r
+              CpuIo,\r
+              EfiCpuIoWidthUint16,\r
+              AcpiBase + R_PCH_ACPI_GPE0a_STS,\r
+              1,\r
+              &Data16\r
+              );\r
+  //\r
+  // Clear the B_PCH_ACPI_GPE0a_STS_GUNIT_SCI bit in R_PCH_ACPI_GPE0a_STS by writing a '1'.\r
+  //\r
+  Data16 |= B_PCH_ACPI_GPE0a_STS_GUNIT_SCI;\r
+\r
+  CpuIo->Io.Write (\r
+              CpuIo,\r
+              EfiCpuIoWidthUint16,\r
+              AcpiBase + R_PCH_ACPI_GPE0a_STS,\r
+              1,\r
+              &Data16\r
+              );\r
+\r
+  //\r
+  // Install OpRegion / Software SCI protocol\r
+  //\r
+  Handle = NULL;\r
+  Status = gBS->InstallMultipleProtocolInterfaces (\r
+                  &Handle,\r
+                  &gIgdOpRegionProtocolGuid,\r
+                  &mIgdOpRegion,\r
+                  NULL\r
+                  );\r
+  ASSERT_EFI_ERROR (Status);\r
+\r
+  //\r
+  // Return final status\r
+  //\r
+  return EFI_SUCCESS;\r
+}\r

diff --git a/Vlv2TbltDevicePkg/VlvPlatformInitDxe/IgdOpRegion.h b/Vlv2TbltDevicePkg/VlvPlatformInitDxe/IgdOpRegion.h
new file mode 100644 (file)
index 0000000..3cbaf53
--- /dev/null
+++ b/Vlv2TbltDevicePkg/VlvPlatformInitDxe/IgdOpRegion.h
@@ -0,0 +1,240 @@
+\r
+/*++\r
+\r
+Copyright (c)  1999  - 2014, Intel Corporation. All rights reserved\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+\r
+Module Name:\r
+\r
+  IgdOpRegion.h\r
+\r
+Abstract:\r
+\r
+  This is part of the implementation of an Intel Graphics drivers OpRegion /\r
+  Software SCI interface between system BIOS, ASL code, and Graphics drivers.\r
+\r
+  Supporting Specifiction: OpRegion / Software SCI SPEC 0.70\r
+\r
+  Acronyms:\r
+    IGD:        Internal Graphics Device\r
+    NVS:        ACPI Non Volatile Storage\r
+    OpRegion:   ACPI Operational Region\r
+    VBT:        Video BIOS Table (OEM customizable data)\r
+\r
+--*/\r
+\r
+#ifndef _IGD_OPREGION_H_\r
+#define _IGD_OPREGION_H_\r
+\r
+//\r
+// Statements that include other header files.\r
+//\r
+#include "VlvPlatformInit.h"\r
+#include "VlvCommonDefinitions.h"\r
+#include <Uefi/UefiInternalFormRepresentation.h>\r
+#include <FrameworkDxe.h>\r
+\r
+//\r
+//\r
+// OpRegion (Miscellaneous) #defines.\r
+//\r
+// OpRegion Header #defines.\r
+//\r
+\r
+#define HEADER_SIGNATURE    "IntelGraphicsMem"\r
+#define HEADER_SIZE         0x2000\r
+#define HEADER_OPREGION_VER 0x0200\r
+#define HEADER_OPREGION_REV 0x00\r
+\r
+//\r
+//For VLV Tablet, MailBOX2(SCI)is not supported.\r
+//\r
+#define HEADER_MBOX_SUPPORT (HD_MBOX4 + HD_MBOX3 + HD_MBOX1)\r
+#define HD_MBOX1            BIT0\r
+#define HD_MBOX2            BIT1\r
+#define HD_MBOX3            BIT2\r
+#define HD_MBOX4            BIT3\r
+#define HD_MBOX5            BIT4\r
+#define SVER_SIZE           32\r
+\r
+//\r
+//Audio Type support for VLV2 A0\r
+//\r
+#define AUDIO_TYPE_SUPPORT_MASK    0xFFFFFFF3\r
+#define NO_AUDIO_SUPPORT           (0<<2)\r
+#define HD_AUDIO_SUPPORT           (1<<2)\r
+#define LPE_AUDIO_SUPPORT          (2<<2)\r
+#define AUDIO_TYPE_FIELD_MASK      0xFFFFFFEF\r
+#define AUDIO_TYPE_FIELD_VALID     (1<<4)\r
+#define AUDIO_TYPE_FIELD_INVALID   (0<<4)\r
+\r
+//\r
+// OpRegion Mailbox 1 EQUates.\r
+//\r
+// OpRegion Mailbox 3 EQUates.\r
+//\r
+#define ALS_ENABLE            BIT0\r
+#define BLC_ENABLE            BIT1\r
+#define BACKLIGHT_BRIGHTNESS  0xFF\r
+#define FIELD_VALID_BIT       BIT31\r
+#define WORD_FIELD_VALID_BIT  BIT15\r
+#define PFIT_ENABLE           BIT2\r
+#define PFIT_OPRN_AUTO        0x00000000\r
+#define PFIT_OPRN_SCALING     0x00000007\r
+#define PFIT_OPRN_OFF         0x00000000\r
+#define PFIT_SETUP_AUTO       0\r
+#define PFIT_SETUP_SCALING    1\r
+#define PFIT_SETUP_OFF        2\r
+#define INIT_BRIGHT_LEVEL     0x64\r
+#define PFIT_STRETCH          6\r
+#define PFIT_CENTER           1\r
+\r
+//\r
+// GMCH PCI register access #defines.\r
+//\r
+\r
+#define IgdMmPci32(Register)            MmPci32   (0, IGD_BUS, IGD_DEV, IGD_FUN_0, Register)\r
+#define IgdMmPci16Or(Register, OrData)  MmPci16Or (0, IGD_BUS, IGD_DEV, IGD_FUN_0, Register, OrData)\r
+#define IgdMmPci16AndThenOr(Register,AndData,OrData) MmPci16AndThenOr (0, IGD_BUS, IGD_DEV, IGD_FUN_0, Register, AndData, OrData)\r
+\r
+//\r
+// Video BIOS / VBT #defines\r
+//\r
+#define IGD_DID_VLV             0x0F31\r
+#define OPTION_ROM_SIGNATURE    0xAA55\r
+#define VBIOS_LOCATION_PRIMARY  0xC0000\r
+\r
+#define VBT_SIGNATURE           SIGNATURE_32 ('$', 'V', 'B', 'T')\r
+\r
+//\r
+// Typedef stuctures\r
+//\r
+#pragma pack (1)\r
+typedef struct {\r
+  UINT16  Signature;    // 0xAA55\r
+  UINT8   Size512;\r
+  UINT8   Reserved[21];\r
+  UINT16  PcirOffset;\r
+  UINT16  VbtOffset;\r
+} INTEL_VBIOS_OPTION_ROM_HEADER;\r
+#pragma pack ()\r
+\r
+#pragma pack (1)\r
+typedef struct {\r
+  UINT32  Signature;  // "PCIR"\r
+  UINT16  VendorId;   // 0x8086\r
+  UINT16  DeviceId;\r
+  UINT16  Reserved0;\r
+  UINT16  Length;\r
+  UINT8   Revision;\r
+  UINT8   ClassCode[3];\r
+  UINT16  ImageLength;\r
+  UINT16  CodeRevision;\r
+  UINT8   CodeType;\r
+  UINT8   Indicator;\r
+  UINT16  Reserved1;\r
+} INTEL_VBIOS_PCIR_STRUCTURE;\r
+#pragma pack ()\r
+\r
+#pragma pack (1)\r
+typedef struct {\r
+  UINT8   HeaderSignature[20];\r
+  UINT16  HeaderVersion;\r
+  UINT16  HeaderSize;\r
+  UINT16  HeaderVbtSize;\r
+  UINT8   HeaderVbtCheckSum;\r
+  UINT8   HeaderReserved;\r
+  UINT32  HeaderOffsetVbtDataBlock;\r
+  UINT32  HeaderOffsetAim1;\r
+  UINT32  HeaderOffsetAim2;\r
+  UINT32  HeaderOffsetAim3;\r
+  UINT32  HeaderOffsetAim4;\r
+  UINT8   DataHeaderSignature[16];\r
+  UINT16  DataHeaderVersion;\r
+  UINT16  DataHeaderSize;\r
+  UINT16  DataHeaderDataBlockSize;\r
+  UINT8   CoreBlockId;\r
+  UINT16  CoreBlockSize;\r
+  UINT16  CoreBlockBiosSize;\r
+  UINT8   CoreBlockBiosType;\r
+  UINT8   CoreBlockReleaseStatus;\r
+  UINT8   CoreBlockHWSupported;\r
+  UINT8   CoreBlockIntegratedHW;\r
+  UINT8   CoreBlockBiosBuild[4];\r
+  UINT8   CoreBlockBiosSignOn[155];\r
+} VBIOS_VBT_STRUCTURE;\r
+#pragma pack ()\r
+\r
+//\r
+// Driver Private Function definitions\r
+//\r
+EFI_STATUS\r
+GetSVER (\r
+  OUT UINT8 *SVER\r
+  );\r
+\r
+/**\r
+  Acquire the string associated with the ProducerGuid and return it.\r
+\r
+  @param ProducerGuid  The Guid to search the HII database for\r
+  @param Token         The token value of the string to extract\r
+  @param String        The string that is extracted\r
+\r
+  @retval EFI_SUCCESS       The function completed successfully\r
+  @retval EFI_NOT_FOUND     The requested string was not found\r
+\r
+**/\r
+EFI_STATUS\r
+GetStringFromToken (\r
+  IN      EFI_GUID                  *ProducerGuid,\r
+  IN      STRING_REF                Token,\r
+  OUT     CHAR16                    **String\r
+  );\r
+\r
+/**\r
+\r
+  Graphics OpRegion / Software SCI driver installation function.\r
+\r
+  @param Void\r
+\r
+  @retval EFI_SUCCESS     The driver installed without error.\r
+  @retval EFI_ABORTED     The driver encountered an error and could not complete\r
+                          installation of the ACPI tables.\r
+**/\r
+EFI_STATUS\r
+IgdOpRegionInit (\r
+  void\r
+  );\r
+\r
+/**\r
+  Extract information pertaining to the HiiHandle\r
+\r
+  @param HiiHandle        Hii handle\r
+  @param ImageLength      For input, length of DefaultImage;\r
+                          For output, length of actually required\r
+\r
+  @param DefaultImage     Image buffer prepared by caller\r
+  @param Guid             Guid information about the form\r
+\r
+  @retval EFI_OUT_OF_RESOURCES     No enough buffer to allocate\r
+  @retval EFI_BUFFER_TOO_SMALL     DefualtImage has no enough ImageLength\r
+  @retval EFI_SUCCESS              Successfully extract data from Hii database.\r
+\r
+**/\r
+EFI_STATUS\r
+ExtractDataFromHiiHandle (\r
+  IN      EFI_HII_HANDLE      HiiHandle,\r
+  IN OUT  UINT16              *ImageLength,\r
+  OUT     UINT8               *DefaultImage,\r
+  OUT     EFI_GUID            *Guid\r
+  );\r
+#endif\r

diff --git a/Vlv2TbltDevicePkg/VlvPlatformInitDxe/VlvPlatformInit.c b/Vlv2TbltDevicePkg/VlvPlatformInitDxe/VlvPlatformInit.c
new file mode 100644 (file)
index 0000000..5e8d95a
--- /dev/null
+++ b/Vlv2TbltDevicePkg/VlvPlatformInitDxe/VlvPlatformInit.c
@@ -0,0 +1,292 @@
+\r
+/*++\r
+\r
+Copyright (c)  1999  - 2014, Intel Corporation. All rights reserved\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+\r
+Module Name:\r
+\r
+  VlvPlatformInit.c\r
+\r
+Abstract:\r
+\r
+  This is the driver that initializes the Intel ValleyView.\r
+\r
+--*/\r
+\r
+#include "VlvPlatformInit.h"\r
+#include <Protocol/VlvPlatformPolicy.h>\r
+\r
+extern DXE_VLV_PLATFORM_POLICY_PROTOCOL  *DxePlatformSaPolicy;\r
+UINT64            GTTMMADR;\r
+\r
+DXE_VLV_PLATFORM_POLICY_PROTOCOL  *DxePlatformSaPolicy;\r
+\r
+/**\r
+  "Poll Status" for GT Readiness\r
+\r
+ @param  Base             Base address of MMIO\r
+ @param  Offset           MMIO Offset\r
+ @param  Mask             Mask\r
+ @param  Result           Value to wait for\r
+\r
+ @retval None\r
+\r
+**/\r
+VOID\r
+PollGtReady_hang (\r
+  UINT64 Base,\r
+  UINT32 Offset,\r
+  UINT32 Mask,\r
+  UINT32 Result\r
+  )\r
+{\r
+  UINT32  GtStatus;\r
+\r
+  //\r
+  // Register read\r
+  //\r
+  GtStatus = MmioRead32 ((UINTN)Base+ Offset);\r
+\r
+  while (((GtStatus & Mask) != Result)) {\r
+\r
+    GtStatus = MmioRead32 ((UINTN)Base + Offset);\r
+  }\r
+\r
+}\r
+\r
+/**\r
+  Do Post GT PM Init Steps after VBIOS Initialization.\r
+\r
+  @param Event             A pointer to the Event that triggered the callback.\r
+  @param Context           A pointer to private data registered with the callback function.\r
+\r
+  @retval EFI_SUCCESS        GC_TODO\r
+\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI    \r
+PostPmInitCallBack (\r
+  IN EFI_EVENT Event,\r
+  IN VOID      *Context\r
+  )\r
+{\r
+  UINT64      OriginalGTTMMADR;\r
+  UINT32      LoGTBaseAddress;\r
+  UINT32      HiGTBaseAddress;\r
+\r
+  //\r
+  // Enable Bus Master, I/O and Memory access on 0:2:0\r
+  //\r
+  PciOr8 (PCI_LIB_ADDRESS(0, IGD_DEV, 0,IGD_R_CMD), (BIT2 | BIT1));\r
+\r
+  //\r
+  // only 32bit read/write is legal for device 0:2:0\r
+  //\r
+  OriginalGTTMMADR  = (UINT64) PciRead32 (PCI_LIB_ADDRESS(0, IGD_DEV, 0,IGD_R_GTTMMADR));\r
+  OriginalGTTMMADR  = LShiftU64 ((UINT64) PciRead32 (PCI_LIB_ADDRESS(0, IGD_DEV, 0,IGD_R_GTTMMADR + 4)), 32) | (OriginalGTTMMADR);\r
+\r
+  //\r
+  // 64bit GTTMADR does not work for S3 save script table since it is executed in PEIM phase\r
+  // Program temporarily 32bits GTTMMADR for POST and S3 resume\r
+  //\r
+  LoGTBaseAddress                   = (UINT32) (GTTMMADR & 0xFFFFFFFF);\r
+  HiGTBaseAddress                   = (UINT32) RShiftU64 ((GTTMMADR & 0xFFFFFFFF00000000), 32);\r
+  S3PciWrite32(PCI_LIB_ADDRESS(0, IGD_DEV, 0,IGD_R_GTTMMADR), LoGTBaseAddress);\r
+  S3PciWrite32(PCI_LIB_ADDRESS(0, IGD_DEV, 0,IGD_R_GTTMMADR+4), HiGTBaseAddress);\r
+\r
+\r
+\r
+  //\r
+  // Restore original GTTMMADR\r
+  //\r
+  LoGTBaseAddress                   = (UINT32) (OriginalGTTMMADR & 0xFFFFFFFF);\r
+  HiGTBaseAddress                   = (UINT32) RShiftU64 ((OriginalGTTMMADR & 0xFFFFFFFF00000000), 32);\r
+\r
+  S3PciWrite32(PCI_LIB_ADDRESS(0, IGD_DEV, 0,IGD_R_GTTMMADR), LoGTBaseAddress);\r
+  S3PciWrite32(PCI_LIB_ADDRESS(0, IGD_DEV, 0,IGD_R_GTTMMADR+4), HiGTBaseAddress);\r
+\r
+\r
+  //\r
+  // Lock the following registers, GGC, BDSM, BGSM\r
+  //\r
+  PciOr32 (PCI_LIB_ADDRESS(0, IGD_DEV, 0,IGD_MGGC_OFFSET), LockBit);\r
+  PciOr32 (PCI_LIB_ADDRESS(0, IGD_DEV, 0,IGD_BSM_OFFSET), LockBit);\r
+  PciOr32 (PCI_LIB_ADDRESS(0, IGD_DEV, 0,IGD_R_BGSM), LockBit);\r
+\r
+  gBS->CloseEvent (Event);\r
+\r
+  //\r
+  // Return final status\r
+  //\r
+  return EFI_SUCCESS;\r
+}\r
+\r
+/**\r
+\r
+  Routine Description:\r
+\r
+  Initialize GT Post Routines.\r
+\r
+  @param ImageHandle              Handle for the image of this driver\r
+  @param DxePlatformSaPolicy      SA DxePlatformPolicy protocol\r
+\r
+  @retval EFI_SUCCESS             GT POST initialization complete\r
+\r
+**/\r
+EFI_STATUS\r
+IgdPmHook (\r
+  IN EFI_HANDLE                      ImageHandle,\r
+  IN DXE_VLV_PLATFORM_POLICY_PROTOCOL *DxePlatformSaPolicy\r
+  )\r
+{\r
+\r
+  EFI_EVENT             mConOutEvent;\r
+  VOID                  *gConOutNotifyReg;\r
+\r
+  EFI_STATUS            Status;\r
+\r
+  EFI_PHYSICAL_ADDRESS  MemBaseAddress;\r
+  UINT32                LoGTBaseAddress;\r
+  UINT32                HiGTBaseAddress;\r
+\r
+  GTTMMADR    = 0;\r
+  Status      = EFI_SUCCESS;\r
+\r
+  //\r
+  // If device 0:2:0 (Internal Graphics Device, or GT) is enabled, then Program GTTMMADR,\r
+  //\r
+  if (PciRead16(PCI_LIB_ADDRESS(0, IGD_DEV, 0, IGD_R_VID))  != 0xFFFF) {\r
+\r
+    ASSERT (gDS!=NULL);\r
+\r
+    //\r
+    // Enable Bus Master, I/O and Memory access on 0:2:0\r
+    //\r
+    PciOr8(PCI_LIB_ADDRESS(0, IGD_DEV, 0, IGD_R_CMD), (BIT2 | BIT1 | BIT0));\r
+\r
+    //\r
+    // Means Allocate 4MB for GTTMADDR\r
+    //\r
+    MemBaseAddress = 0x0ffffffff;\r
+\r
+    Status = gDS->AllocateMemorySpace (\r
+                    EfiGcdAllocateMaxAddressSearchBottomUp,\r
+                    EfiGcdMemoryTypeMemoryMappedIo,\r
+                    GTT_MEM_ALIGN,\r
+                    GTTMMADR_SIZE_4MB,\r
+                    &MemBaseAddress,\r
+                    ImageHandle,\r
+                    NULL\r
+                    );\r
+    ASSERT_EFI_ERROR (Status);\r
+\r
+    //\r
+    // Program GT PM Settings if GTTMMADR allocation is Successful\r
+    //\r
+    GTTMMADR                          = (UINTN) MemBaseAddress;\r
+\r
+    LoGTBaseAddress                   = (UINT32) (MemBaseAddress & 0xFFFFFFFF);\r
+    HiGTBaseAddress                   = (UINT32) RShiftU64 ((MemBaseAddress & 0xFFFFFFFF00000000), 32);\r
+\r
+    PciWrite32 (PCI_LIB_ADDRESS(0, IGD_DEV, 0, IGD_R_GTTMMADR), LoGTBaseAddress);\r
+    PciWrite32 (PCI_LIB_ADDRESS(0, IGD_DEV, 0, IGD_R_GTTMMADR+4), HiGTBaseAddress);\r
+\r
+\r
+    S3PciRead32(PCI_LIB_ADDRESS(0, IGD_DEV, 0, IGD_R_GTTMMADR));\r
+\r
+\r
+    S3MmioRead32(IGD_R_GTTMMADR + 4);\r
+\r
+\r
+    S3PciRead8(PCI_LIB_ADDRESS(0, IGD_DEV, 0, IGD_R_CMD));\r
+\r
+    //\r
+    // Do POST GT PM Init Steps after VBIOS Initialization in DoPostPmInitCallBack\r
+    //\r
+    Status = gBS->CreateEvent (\r
+                    EVT_NOTIFY_SIGNAL,\r
+                    TPL_CALLBACK,\r
+                    (EFI_EVENT_NOTIFY)PostPmInitCallBack,\r
+                    NULL,\r
+                    &mConOutEvent\r
+                    );\r
+\r
+    ASSERT_EFI_ERROR (Status);\r
+    if (EFI_ERROR (Status)) {\r
+      return Status;\r
+    }\r
+\r
+\r
+    Status = gBS->RegisterProtocolNotify (\r
+                    &gEfiGraphicsOutputProtocolGuid,\r
+                    mConOutEvent,\r
+                    &gConOutNotifyReg\r
+                    );\r
+\r
+\r
+\r
+    MmioWrite64 (IGD_R_GTTMMADR, 0);\r
+\r
+    //\r
+    // Free allocated resources\r
+    //\r
+    gDS->FreeMemorySpace (\r
+           MemBaseAddress,\r
+           GTTMMADR_SIZE_4MB\r
+           );\r
+\r
+  }\r
+\r
+  return EFI_SUCCESS;\r
+}\r
+\r
+/**\r
+\r
+  This is the standard EFI driver point that detects\r
+  whether there is an ICH southbridge in the system\r
+  and if so, initializes the chip.\r
+\r
+  @param  ImageHandle             Handle for the image of this driver\r
+  @param  SystemTable             Pointer to the EFI System Table\r
+\r
+  @retval EFI_SUCCESS             The function completed successfully\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+VlvPlatformInitEntryPoint (\r
+  IN EFI_HANDLE       ImageHandle,\r
+  IN EFI_SYSTEM_TABLE *SystemTable\r
+  )\r
+{\r
+  EFI_STATUS                        Status;\r
+\r
+  Status = gBS->LocateProtocol (&gDxeVlvPlatformPolicyGuid, NULL, (void **)&DxePlatformSaPolicy);\r
+  ASSERT_EFI_ERROR (Status);\r
+\r
+  //\r
+  // GtPostInit Initialization\r
+  //\r
+  DEBUG ((EFI_D_ERROR, "Initializing GT PowerManagement and other GT POST related\n"));\r
+  IgdPmHook (ImageHandle, DxePlatformSaPolicy);\r
+\r
+  //\r
+  // IgdOpRegion Install Initialization\r
+  //\r
+  DEBUG ((EFI_D_ERROR, "Initializing IGD OpRegion\n"));\r
+  IgdOpRegionInit ();\r
+\r
+  return EFI_SUCCESS;\r
+}\r
+\r

diff --git a/Vlv2TbltDevicePkg/VlvPlatformInitDxe/VlvPlatformInit.h b/Vlv2TbltDevicePkg/VlvPlatformInitDxe/VlvPlatformInit.h
new file mode 100644 (file)
index 0000000..7f7ed59
--- /dev/null
+++ b/Vlv2TbltDevicePkg/VlvPlatformInitDxe/VlvPlatformInit.h
@@ -0,0 +1,70 @@
+\r
+/*++\r
+\r
+Copyright (c)  1999  - 2014, Intel Corporation. All rights reserved\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+\r
+Module Name:\r
+\r
+  VlvPlatformInit.h\r
+\r
+Abstract:\r
+\r
+  Header file for SA Initialization Driver.\r
+\r
+--*/\r
+\r
+#ifndef _VLV_PLATFORM_INIT_DXE_H_\r
+#define _VLV_PLATFORM_INIT_DXE_H_\r
+#include "PiDxe.h"\r
+\r
+#include <Protocol/VlvPlatformPolicy.h>\r
+\r
+#include "IgdOpRegion.h"\r
+\r
+#include <Library/DxeServicesTableLib.h>\r
+#include <Library/UefiBootServicesTableLib.h>\r
+#include <Library/UefiLib.h>\r
+#include "Library/DebugLib.h"\r
+#include "Library/S3IoLib.h"\r
+#include "Library/S3PciLib.h"\r
+#include "Library/IoLib.h"\r
+#include "Library/PciLib.h"\r
+#include "Library/S3BootScriptLib.h"\r
+\r
+//\r
+// GT RELATED EQUATES\r
+//\r
+#define GTT_MEM_ALIGN        22\r
+#define GTTMMADR_SIZE_4MB    0x400000\r
+\r
+#define IGD_BUS             0x00\r
+#define IGD_DEV                  0x02\r
+#define IGD_FUN_0                0x00\r
+\r
+#define IGD_R_VID                0x00\r
+#define IGD_R_CMD                0x04\r
+#define IGD_R_GTTMMADR           0x10\r
+\r
+#define IGD_R_BGSM               0x70\r
+#define LockBit                  BIT0\r
+\r
+#define IGD_VID             0x8086\r
+#define IGD_DID             0xA001\r
+#define IGD_MGGC_OFFSET     0x0050      //GMCH Graphics Control Register 0x50\r
+#define IGD_BSM_OFFSET      0x005C      //Base of Stolen Memory\r
+#define IGD_SWSCI_OFFSET    0x00E0      //Software SCI 0xE0 2\r
+#define IGD_ASLE_OFFSET     0x00E4      //System Display Event Register 0xE4 4\r
+#define IGD_ASLS_OFFSET     0x00FC      // ASL Storage\r
+\r
+#endif\r
+\r

diff --git a/Vlv2TbltDevicePkg/VlvPlatformInitDxe/VlvPlatformInitDxe.inf b/Vlv2TbltDevicePkg/VlvPlatformInitDxe/VlvPlatformInitDxe.inf
new file mode 100644 (file)
index 0000000..cea185f
--- /dev/null
+++ b/Vlv2TbltDevicePkg/VlvPlatformInitDxe/VlvPlatformInitDxe.inf
@@ -0,0 +1,79 @@
+#\r
+#\r
+#/*++\r
+#\r
+#  Copyright (c)  1999  - 2014, Intel Corporation. All rights reserved\r
+#                                                                                  \r\r
+# This program and the accompanying materials are licensed and made available under\r\r
+# the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+# The full text of the license may be found at                                     \r\r
+# http://opensource.org/licenses/bsd-license.php.                                  \r\r
+#                                                                                  \r\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+#                                                                                  \r\r
+#\r
+#  Module Name:\r
+#\r
+#    VlvPlatformInit.inf\r
+#\r
+#  Abstract:\r
+#\r
+#    Component description file for wrapper driver of Vlv platform init part.\r
+#\r
+#--*/\r
+\r
+\r
+[Defines]\r
+  INF_VERSION                    = 0x00010005\r
+  BASE_NAME                      = VlvPlatformInitDxe\r
+  FILE_GUID                      = 1EC0EFC9-C93A-4b62-9B27-C059ABD80E92\r
+  MODULE_TYPE                    = DXE_DRIVER\r
+  VERSION_STRING                 = 1.0\r
+  ENTRY_POINT                    = VlvPlatformInitEntryPoint\r
+\r
+[Sources]\r
+  VlvPlatformInit.c\r
+  IgdOpRegion.c\r
+\r
+\r
+[Packages]\r
+  MdePkg/MdePkg.dec\r
+  IntelFrameworkPkg/IntelFrameworkPkg.dec\r
+  Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec\r
+  Vlv2TbltDevicePkg/PlatformPkg.dec\r
+\r
+[LibraryClasses]\r
+  UefiDriverEntryPoint\r
+  DebugLib\r
+  UefiBootServicesTableLib\r
+  S3BootScriptLib\r
+  DxeServicesTableLib\r
+  PchPlatformLib\r
+  S3PciLib\r
+  S3IoLib\r
+  PciLib\r
+  IoLib\r
+\r
+[Guids]\r
+  gBmpImageGuid\r
+  gEfiDxeServicesTableGuid\r
+\r
+[Protocols]\r
+  gDxeVlvPlatformPolicyGuid\r
+  gEfiDxeSmmReadyToLockProtocolGuid\r
+  gIgdOpRegionProtocolGuid\r
+  gEfiGlobalNvsAreaProtocolGuid\r
+  gEfiPciIoProtocolGuid\r
+  gEfiFirmwareVolumeProtocolGuid\r
+  gEfiCpuIoProtocolGuid\r
+\r
+[Depex]\r
+  gDxeVlvPlatformPolicyGuid              AND\r
+  gEfiPciRootBridgeIoProtocolGuid     AND\r
+  gEfiCpuIoProtocolGuid                      AND\r
+  gEfiDataHubProtocolGuid                 AND\r
+  gEfiGlobalNvsAreaProtocolGuid       AND\r
+  gEfiFirmwareVolumeProtocolGuid   AND\r
+  gEfiHiiDatabaseProtocolGuid\r
+\r

diff --git a/Vlv2TbltDevicePkg/Wpce791/LpcDriver.c b/Vlv2TbltDevicePkg/Wpce791/LpcDriver.c
new file mode 100644 (file)
index 0000000..be99b4c
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Wpce791/LpcDriver.c
@@ -0,0 +1,349 @@
+/** @file\r
+\r
+  Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+\r
+Module Name:\r
+\r
+    LpcDriver.c\r
+\r
+Abstract:\r
+\r
+    EFI Lpc Driver for a Generic PC Platform\r
+\r
+\r
+\r
+--*/\r
+\r
+#include "LpcDriver.h"\r
+#include "IndustryStandard/Pci22.h"\r
+\r
+//\r
+// This driver is for ACPI(PNP0A03,0)/PCI(0x1f,0)\r
+//\r
+\r
+//\r
+//  Lpc Driver Global Variables\r
+//\r
+\r
+EFI_DRIVER_BINDING_PROTOCOL gLpcDriver = {\r
+  LpcDriverSupported,\r
+  LpcDriverStart,\r
+  LpcDriverStop,\r
+  0x10,\r
+  NULL,\r
+  NULL\r
+};\r
+\r
+LPC_DEV mLpc = {\r
+  LPC_DEV_SIGNATURE,\r
+  NULL,\r
+  {\r
+    IsaDeviceEnumerate,\r
+    IsaDeviceSetPower,\r
+    IsaGetCurrentResource,\r
+    IsaGetPossibleResource,\r
+    IsaSetResource,\r
+    IsaEnableDevice,\r
+    IsaInitDevice,\r
+    LpcInterfaceInit\r
+  },\r
+  NULL\r
+};\r
+\r
+BOOLEAN  InitExecuted = FALSE;\r
+\r
+/**\r
+    the entry point of the Lpc driver\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+LpcDriverEntryPoint(\r
+  IN EFI_HANDLE           ImageHandle,\r
+  IN EFI_SYSTEM_TABLE     *SystemTable\r
+  )\r
+{\r
+\r
+\r
+  return EfiLibInstallDriverBinding (ImageHandle, SystemTable, &gLpcDriver, ImageHandle);\r
+}\r
+\r
+/**\r
+\r
+  ControllerDriver Protocol Method\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+LpcDriverSupported (\r
+  IN EFI_DRIVER_BINDING_PROTOCOL    *This,\r
+  IN EFI_HANDLE                     Controller,\r
+  IN EFI_DEVICE_PATH_PROTOCOL       *RemainingDevicePath\r
+  )\r
+{\r
+  EFI_STATUS                Status;\r
+  EFI_PCI_IO_PROTOCOL       *PciIo;\r
+  EFI_DEVICE_PATH_PROTOCOL  *IsaBridgeDevicePath;\r
+\r
+  ACPI_HID_DEVICE_PATH      *AcpiNode;\r
+  PCI_DEVICE_PATH           *PciNode;\r
+  PCI_TYPE00                Pci;\r
+\r
+  //\r
+  // Get the ISA bridge's Device Path and test it\r
+  // the following code is specific\r
+  //\r
+  Status = gBS->OpenProtocol (\r
+                  Controller,\r
+                  &gEfiDevicePathProtocolGuid,\r
+                  (VOID **)&IsaBridgeDevicePath,\r
+                  This->DriverBindingHandle,\r
+                  Controller,\r
+                  EFI_OPEN_PROTOCOL_BY_DRIVER\r
+                  );\r
+\r
+  if (EFI_ERROR (Status)) {\r
+    return Status;\r
+  }\r
+\r
+  Status = EFI_SUCCESS;\r
+  AcpiNode =  (ACPI_HID_DEVICE_PATH *)IsaBridgeDevicePath;\r
+  if (AcpiNode->Header.Type != ACPI_DEVICE_PATH ||\r
+      AcpiNode->Header.SubType != ACPI_DP ||\r
+      DevicePathNodeLength (&AcpiNode->Header) != sizeof(ACPI_HID_DEVICE_PATH) ||\r
+      AcpiNode -> HID != EISA_PNP_ID(0x0A03) ||\r
+      AcpiNode -> UID != 0 ) {\r
+    Status = EFI_UNSUPPORTED;\r
+  } else {\r
+    //\r
+    // Get the next node\r
+    //\r
+    IsaBridgeDevicePath = NextDevicePathNode (IsaBridgeDevicePath);\r
+    PciNode  = (PCI_DEVICE_PATH *)IsaBridgeDevicePath;\r
+    if (PciNode->Header.Type != HARDWARE_DEVICE_PATH ||\r
+        PciNode->Header.SubType != HW_PCI_DP ||\r
+        DevicePathNodeLength (&PciNode->Header) != sizeof (PCI_DEVICE_PATH) ||\r
+        PciNode -> Function != 0x00 ||\r
+        PciNode -> Device != 0x1f ) {\r
+      Status = EFI_UNSUPPORTED;\r
+    }\r
+  }\r
+\r
+  gBS->CloseProtocol (\r
+         Controller,\r
+         &gEfiDevicePathProtocolGuid,\r
+         This->DriverBindingHandle,\r
+         Controller\r
+         );\r
+\r
+  if (EFI_ERROR (Status)) {\r
+    return EFI_UNSUPPORTED;\r
+  }\r
+\r
+  //\r
+  // Get PciIo protocol instance\r
+  //\r
+  Status = gBS->OpenProtocol (\r
+                  Controller,\r
+                  &gEfiPciIoProtocolGuid,\r
+                  (VOID **)&PciIo,\r
+                  This->DriverBindingHandle,\r
+                  Controller,\r
+                  EFI_OPEN_PROTOCOL_BY_DRIVER\r
+                  );\r
+\r
+  if (EFI_ERROR(Status)) {\r
+    return Status;\r
+  }\r
+\r
+  Status = PciIo->Pci.Read (\r
+                        PciIo,\r
+                        EfiPciIoWidthUint32,\r
+                        0,\r
+                        sizeof(Pci) / sizeof(UINT32),\r
+                        &Pci\r
+                        );\r
+\r
+  if (!EFI_ERROR (Status)) {\r
+    Status = EFI_SUCCESS; //TODO: force return success as temp solution EFI_UNSUPPORTED;\r
+    if ((Pci.Hdr.Command & 0x03) == 0x03) {\r
+      if (Pci.Hdr.ClassCode[2] == PCI_CLASS_BRIDGE) {\r
+        //\r
+        // See if this is a standard PCI to ISA Bridge from the Base Code\r
+        // and Class Code\r
+        //\r
+        if (Pci.Hdr.ClassCode[1] == PCI_CLASS_BRIDGE_ISA) {\r
+          Status = EFI_SUCCESS;\r
+        } else {\r
+        }\r
+\r
+        //\r
+        // See if this is an Intel PCI to ISA bridge in Positive Decode Mode\r
+        //\r
+        if (Pci.Hdr.ClassCode[1] == PCI_CLASS_BRIDGE_ISA_PDECODE &&\r
+            Pci.Hdr.VendorId == 0x8086 &&\r
+            Pci.Hdr.DeviceId == 0x7110) {\r
+          Status = EFI_SUCCESS;\r
+        } else {\r
+        }\r
+      } else {\r
+      }\r
+    }\r
+    else {\r
+    }\r
+  }\r
+\r
+  gBS->CloseProtocol (\r
+         Controller,\r
+         &gEfiPciIoProtocolGuid,\r
+         This->DriverBindingHandle,\r
+         Controller\r
+         );\r
+  return Status;\r
+}\r
+\r
+\r
+/**\r
+  Install EFI_ISA_ACPI_PROTOCOL\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+LpcDriverStart (\r
+  IN EFI_DRIVER_BINDING_PROTOCOL    *This,\r
+  IN EFI_HANDLE                     Controller,\r
+  IN EFI_DEVICE_PATH_PROTOCOL       *RemainingDevicePath\r
+  )\r
+{\r
+  EFI_STATUS             Status;\r
+  EFI_PCI_IO_PROTOCOL    *PciIo;\r
+  LPC_DEV                *LpcDev;\r
+\r
+\r
+  LpcDev = NULL;\r
+\r
+  //\r
+  // Get Pci IO\r
+  //\r
+  Status = gBS->OpenProtocol (\r
+                  Controller,\r
+                  &gEfiPciIoProtocolGuid,\r
+                  (VOID **)&PciIo,\r
+                  This->DriverBindingHandle,\r
+                  Controller,\r
+                  EFI_OPEN_PROTOCOL_BY_DRIVER\r
+                  );\r
+\r
+  if (EFI_ERROR (Status) && Status != EFI_ALREADY_STARTED) {\r
+    return Status;\r
+  }\r
+\r
+  mLpc.PciIo = PciIo;\r
+\r
+  //\r
+  // Install IsaAcpi interface, the Sio interface is not installed!\r
+  //\r
+  Status = gBS->InstallMultipleProtocolInterfaces (\r
+                  &Controller,\r
+                  &gEfiIsaAcpiProtocolGuid,\r
+                  &mLpc.IsaAcpi,\r
+                  NULL\r
+                  );\r
+  return Status;\r
+}\r
+\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+LpcDriverStop (\r
+  IN  EFI_DRIVER_BINDING_PROTOCOL    *This,\r
+  IN  EFI_HANDLE                     Controller,\r
+  IN  UINTN                          NumberOfChildren,\r
+  IN  EFI_HANDLE                     *ChildHandleBuffer\r
+  )\r
+{\r
+  EFI_STATUS             Status;\r
+  EFI_ISA_ACPI_PROTOCOL  *IsaAcpi;\r
+  LPC_DEV                *LpcDev;\r
+\r
+  //\r
+  // Get EFI_ISA_ACPI_PROTOCOL interface\r
+  //\r
+  Status = gBS->OpenProtocol (\r
+                  Controller,\r
+                  &gEfiIsaAcpiProtocolGuid,\r
+                  (VOID **)&IsaAcpi,\r
+                  This->DriverBindingHandle,\r
+                  Controller,\r
+                  EFI_OPEN_PROTOCOL_GET_PROTOCOL\r
+                  );\r
+  if (EFI_ERROR (Status)) {\r
+    return Status;\r
+  }\r
+\r
+  LpcDev = LPC_ISA_ACPI_FROM_THIS (IsaAcpi);\r
+\r
+  //\r
+  // Uninstall protocol interface: EFI_ISA_ACPI_PROTOCOL\r
+  //\r
+  Status = gBS->UninstallProtocolInterface (\r
+                  Controller,\r
+                  &gEfiIsaAcpiProtocolGuid,\r
+                  &LpcDev->IsaAcpi\r
+                  );\r
+  if (EFI_ERROR (Status)) {\r
+    return Status;\r
+  }\r
+\r
+  gBS->CloseProtocol (\r
+         Controller,\r
+         &gEfiPciIoProtocolGuid,\r
+         This->DriverBindingHandle,\r
+         Controller\r
+         );\r
+\r
+  return EFI_SUCCESS;\r
+}\r
+\r
+VOID\r
+LpcIoRead8 (\r
+  IN  UINT16  Port,\r
+  OUT UINT8   *Data\r
+  )\r
+{\r
+  mLpc.PciIo->Io.Read(\r
+                   mLpc.PciIo,\r
+                   EfiPciWidthUint8,\r
+                   EFI_PCI_IO_PASS_THROUGH_BAR,\r
+                   Port,\r
+                   1,\r
+                   Data\r
+                   );\r
+}\r
+\r
+VOID\r
+LpcIoWrite8 (\r
+  IN  UINT16  Port,\r
+  IN  UINT8   Data\r
+  )\r
+{\r
+  mLpc.PciIo->Io.Write(\r
+                   mLpc.PciIo,\r
+                   EfiPciWidthUint8,\r
+                   EFI_PCI_IO_PASS_THROUGH_BAR,\r
+                   Port,\r
+                   1,\r
+                   &Data\r
+                   );\r
+}\r
+\r

diff --git a/Vlv2TbltDevicePkg/Wpce791/LpcDriver.h b/Vlv2TbltDevicePkg/Wpce791/LpcDriver.h
new file mode 100644 (file)
index 0000000..d85c081
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Wpce791/LpcDriver.h
@@ -0,0 +1,117 @@
+/*++\r
+\r
+  Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+Module Name:\r
+\r
+    LpcDriver.h\r
+\r
+Abstract:\r
+\r
+    EFI Lpc Driver for a Generic PC Platform\r
+\r
+\r
+\r
+--*/\r
+\r
+#ifndef _LPC_DRIVER_H\r
+#define _LPC_DRIVER_H\r
+\r
+ #include "LpcSio.h"\r
+ #include "LpcIsaAcpi.h"\r
+\r
+#include "Protocol/IsaAcpi.h"\r
+#include "Protocol/PciIo.h"\r
+#include "Protocol/DriverBinding.h"\r
+#include "Library/UefiBootServicesTableLib.h"\r
+#include "IsaAcpiDxe/PcatIsaAcpi.h"\r
+#include "IndustryStandard/Pci22.h"\r
+#include "Protocol/LpcWpce791Policy.h"\r
+\r
+#include <Library/DebugLib.h>\r
+\r
+#define ICH_LPC_BRIDGE_BUS_DEV_FUNC 0x1F0000\r
+\r
+//\r
+// LPC device private data structure\r
+//\r
+//#define LPC_DEV_SIGNATURE 'W87X'\r
+#define LPC_DEV_SIGNATURE SIGNATURE_32('X', '7', '8', 'W') //'W87X'\r
+#define EFI_WPCE791_PS2_KEYBOARD_ENABLE       0x01\r
+#define EFI_WPCE791_PS2_KEYBOARD_DISABLE      0x00\r
+\r
+#define EFI_WPCE791_PS2_MOUSE_ENABLE       0x01\r
+#define EFI_WPCE791_PS2_MOUSE_DISABLE      0x00\r
+\r
+\r
+\r
+typedef struct {\r
+  UINTN                 Signature;\r
+  EFI_HANDLE            Handle;\r
+  EFI_ISA_ACPI_PROTOCOL IsaAcpi;\r
+  EFI_PCI_IO_PROTOCOL   *PciIo;\r
+\r
+} LPC_DEV;\r
+\r
+#define LPC_ISA_ACPI_FROM_THIS(a) BASE_CR (a, LPC_DEV, IsaAcpi)\r
+\r
+//\r
+// Driver entry point\r
+//\r
+EFI_STATUS\r
+EFIAPI\r
+LpcDriverEntryPoint (\r
+  IN EFI_HANDLE           ImageHandle,\r
+  IN EFI_SYSTEM_TABLE     *SystemTable\r
+  );\r
+\r
+//\r
+// Prototypes for Driver model protocol interface\r
+//\r
+EFI_STATUS\r
+EFIAPI\r
+LpcDriverSupported (\r
+  IN EFI_DRIVER_BINDING_PROTOCOL    *This,\r
+  IN EFI_HANDLE                     Controller,\r
+  IN EFI_DEVICE_PATH_PROTOCOL       *RemainingDevicePath\r
+  );\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+LpcDriverStart (\r
+  IN EFI_DRIVER_BINDING_PROTOCOL    *This,\r
+  IN EFI_HANDLE                     Controller,\r
+  IN EFI_DEVICE_PATH_PROTOCOL       *RemainingDevicePath\r
+  );\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+LpcDriverStop (\r
+  IN  EFI_DRIVER_BINDING_PROTOCOL    *This,\r
+  IN  EFI_HANDLE                     Controller,\r
+  IN  UINTN                          NumberOfChildren,\r
+  IN  EFI_HANDLE                     *ChildHandleBuffer\r
+  );\r
+\r
+VOID\r
+LpcIoRead8 (\r
+  IN  UINT16  Port,\r
+  OUT UINT8   *Data\r
+  );\r
+\r
+VOID\r
+LpcIoWrite8 (\r
+  IN  UINT16  Port,\r
+  IN  UINT8   Data\r
+  );\r
+\r
+#endif\r

diff --git a/Vlv2TbltDevicePkg/Wpce791/LpcIsaAcpi.c b/Vlv2TbltDevicePkg/Wpce791/LpcIsaAcpi.c
new file mode 100644 (file)
index 0000000..eeffced
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Wpce791/LpcIsaAcpi.c
@@ -0,0 +1,371 @@
+/** @file\r
+\r
+  Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+Module Name:\r
+\r
+    LpcIsaAcpi.c\r
+\r
+Abstract: IsaAcpi implementation\r
+\r
+\r
+\r
+--*/\r
+\r
+#include "LpcDriver.h"\r
+\r
+//\r
+// PS/2 Keyboard Controller\r
+//\r
+static EFI_ISA_ACPI_RESOURCE  mLpcWpce791Ps2KeyboardDeviceResources[] = {\r
+  {EfiIsaAcpiResourceIo,        0, 0x60, 0x64},\r
+  {EfiIsaAcpiResourceInterrupt, 0, 1,     0},\r
+  {EfiIsaAcpiResourceEndOfList, 0, 0,     0}\r
+};\r
+\r
+//\r
+// PS/2 Mouse Controller\r
+//\r
+static EFI_ISA_ACPI_RESOURCE  mLpcWpce791Ps2MouseDeviceResources[] = {\r
+  {EfiIsaAcpiResourceIo,        0, 0x60, 0x64},\r
+  {EfiIsaAcpiResourceInterrupt, 0, 12,     0},\r
+  {EfiIsaAcpiResourceEndOfList, 0, 0,     0}\r
+};\r
+\r
+//\r
+// COM\r
+//\r
+static EFI_ISA_ACPI_RESOURCE  mLpcWpce791ComDeviceResources[] = {\r
+  {EfiIsaAcpiResourceIo,        0, 0x3f8, 0x3ff},\r
+  {EfiIsaAcpiResourceInterrupt, 0, 4,     0},\r
+  {EfiIsaAcpiResourceEndOfList, 0, 0,     0}\r
+};\r
+\r
+//\r
+// Table of ISA Controllers\r
+//\r
+EFI_ISA_ACPI_RESOURCE_LIST mLpcWpce791DeviceList[] = {\r
+  {{EISA_PNP_ID(0x303), 0}, mLpcWpce791Ps2KeyboardDeviceResources }, // PS/2 Keyboard Controller\r
+  {{EISA_PNP_ID(0xF03), 0}, mLpcWpce791Ps2MouseDeviceResources   }, // PS/2 Mouse Controller\r
+  {{EISA_PNP_ID(0x501), 0}, mLpcWpce791ComDeviceResources            }, // COM\r
+  {{0,                  0}, NULL                                  }  // End\r
+};\r
+\r
+static ICH_DMA_INIT  mIchDmaInitTable [] = {\r
+//\r
+//Register OFFSET,           Value\r
+//\r
+\r
+            0x0D8,           0x000,   // Reset DMA Controller 2\r
+            0x0D0,           0x000,   // Enable DMA controller 2\r
+            0x00C,           0x000,   // Reset DMA Controller 1\r
+            0x008,           0x000,   // Enable DMA controller 1\r
+\r
+            //\r
+            // Channel 4\r
+            //\r
+            0x0D6,           0x0c0,   // DMA contr. 2 Cascade mode, addr. increment, disable auto init.\r
+            0x0D2,           0x000,   // Clear write request register\r
+            0x0d4,           0x000,   // Enable DREQs for channel\r
+\r
+            //\r
+            // Channel 0\r
+            //\r
+            0x00B,           0x040,   // DMA contr. 1 single mode, addr. increment, disable auto init.\r
+            0x009,           0x000,   // Clear write request register\r
+            0x00A,           0x000,   // Enable DREQs for channel\r
+\r
+            //\r
+            // Channel 1\r
+            //\r
+            0x00B,           0x041,   // DMA contr. 1 single mode, addr. increment, disable auto init.\r
+            0x009,           0x001,   // Clear write request register\r
+            0x00A,           0x001,   // Enable DREQs for channel\r
+\r
+            //\r
+            // Channel 2\r
+            //\r
+            0x00B,           0x042,   // DMA contr. 1 single mode, addr. increment, disable auto init.\r
+            0x009,           0x002,   // Clear write request register\r
+            0x00A,           0x002,   // Enable DREQs for channel\r
+\r
+            //\r
+            // Channel 3\r
+            //\r
+            0x00B,           0x043,   // DMA contr. 1 single mode, addr. increment, disable auto init.\r
+            0x009,           0x003,   // Clear write request register\r
+            0x00A,           0x003,   // Enable DREQs for channel\r
+\r
+            //\r
+            // Channel 5\r
+            //\r
+            0x0D6,           0x041,   // DMA contr. 2 single mode, addr. increment, disable auto init.\r
+            0x0D2,           0x001,   // Clear write request register\r
+            0x0D4,           0x001,   // Enable DREQs for channel\r
+\r
+            //\r
+            // Channel 6\r
+            //\r
+            0x0D6,           0x042,   // DMA contr. 2 single mode, addr. increment, disable auto init.\r
+            0x0D2,           0x002,   // Clear write request register\r
+            0x0D4,           0x002,   // Enable DREQs for channel\r
+\r
+            //\r
+            // Channel 7\r
+            //\r
+            0x0D6,           0x043,   // DMA contr. 2 single mode, addr. increment, disable auto init.\r
+            0x0D2,           0x003,   // Clear write request register\r
+            0x0D4,           0x003    // Enable DREQs for channel\r
+\r
+};\r
+\r
+//\r
+// ISA ACPI Protocol Functions\r
+//\r
+/**\r
+\r
+  Enumerate the ISA devices on the ISA bus\r
+\r
+**/\r
+VOID\r
+IsaDeviceLookup (\r
+  IN  EFI_ISA_ACPI_DEVICE_ID      *Device,\r
+  OUT EFI_ISA_ACPI_RESOURCE_LIST  **IsaAcpiDevice,\r
+  OUT EFI_ISA_ACPI_RESOURCE_LIST  **NextIsaAcpiDevice\r
+  )\r
+{\r
+  UINTN  Index;\r
+\r
+  *IsaAcpiDevice = NULL;\r
+  if (NextIsaAcpiDevice != NULL) {\r
+    *NextIsaAcpiDevice = NULL;\r
+  }\r
+  if (Device == NULL) {\r
+    Index = 0;\r
+  } else {\r
+    for(Index = 0; mLpcWpce791DeviceList[Index].Device.HID != 0; Index++) {\r
+      if (Device->HID == mLpcWpce791DeviceList[Index].Device.HID &&\r
+          Device->UID == mLpcWpce791DeviceList[Index].Device.UID    ) {\r
+        break;\r
+      }\r
+    }\r
+    if (mLpcWpce791DeviceList[Index].Device.HID == 0) {\r
+      return;\r
+    }\r
+    *IsaAcpiDevice = &(mLpcWpce791DeviceList[Index]);\r
+    Index++;\r
+  }\r
+  if (NextIsaAcpiDevice != NULL && mLpcWpce791DeviceList[Index].Device.HID != 0){\r
+    *NextIsaAcpiDevice = &(mLpcWpce791DeviceList[Index]);\r
+  }\r
+}\r
+\r
+\r
+/**\r
+  Enumerate the ISA devices on the ISA bus\r
+  It is hard code now and future it will get from ACPI table\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+IsaDeviceEnumerate (\r
+  IN     EFI_ISA_ACPI_PROTOCOL       *This,\r
+  OUT    EFI_ISA_ACPI_DEVICE_ID      **Device\r
+  )\r
+{\r
+  EFI_ISA_ACPI_RESOURCE_LIST  *IsaAcpiDevice;\r
+  EFI_ISA_ACPI_RESOURCE_LIST  *NextIsaAcpiDevice;\r
+\r
+  IsaDeviceLookup (*Device, &IsaAcpiDevice, &NextIsaAcpiDevice);\r
+  if (NextIsaAcpiDevice == NULL) {\r
+    return EFI_NOT_FOUND;\r
+  }\r
+  *Device = &(NextIsaAcpiDevice->Device);\r
+  return EFI_SUCCESS;\r
+}\r
+\r
+/**\r
+  Set ISA device power use sio\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+IsaDeviceSetPower (\r
+  IN     EFI_ISA_ACPI_PROTOCOL       *This,\r
+  IN     EFI_ISA_ACPI_DEVICE_ID      *Device,\r
+  IN     BOOLEAN                     OnOff\r
+  )\r
+{\r
+  return EFI_UNSUPPORTED;\r
+}\r
+\r
+\r
+/**\r
+  Get current Resource of the specific ISA device\r
+  It is hardcode now and future will get from ACPI table\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+IsaGetCurrentResource (\r
+  IN     EFI_ISA_ACPI_PROTOCOL        *This,\r
+  IN     EFI_ISA_ACPI_DEVICE_ID       *Device,\r
+  OUT    EFI_ISA_ACPI_RESOURCE_LIST   **ResourceList\r
+  )\r
+{\r
+  IsaDeviceLookup (Device, ResourceList, NULL);\r
+  if (*ResourceList == NULL || (*ResourceList)->ResourceItem == NULL) {\r
+    return EFI_NOT_FOUND;\r
+  }\r
+  return EFI_SUCCESS;\r
+}\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+IsaGetPossibleResource (\r
+  IN     EFI_ISA_ACPI_PROTOCOL       *This,\r
+  IN     EFI_ISA_ACPI_DEVICE_ID      *Device,\r
+  OUT    EFI_ISA_ACPI_RESOURCE_LIST  **ResourceList\r
+  )\r
+{\r
+  //\r
+  // Not supported yet\r
+  //\r
+  return EFI_UNSUPPORTED;\r
+}\r
+\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+IsaSetResource (\r
+  IN     EFI_ISA_ACPI_PROTOCOL       *This,\r
+  IN     EFI_ISA_ACPI_DEVICE_ID      *Device,\r
+  IN     EFI_ISA_ACPI_RESOURCE_LIST  *ResourceList\r
+  )\r
+{\r
+  return EFI_UNSUPPORTED;\r
+}\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+IsaEnableDevice (\r
+  IN    EFI_ISA_ACPI_PROTOCOL        *This,\r
+  IN    EFI_ISA_ACPI_DEVICE_ID       *Device,\r
+  IN    BOOLEAN                      Enable\r
+  )\r
+{\r
+\r
+  return EFI_UNSUPPORTED;\r
+}\r
+\r
+/**\r
+\r
+  Clear out Resource List if device is set to disable by platform policy\r
+\r
+**/\r
+VOID\r
+EmptyResourceList (\r
+  IN  UINT32      DeviceHid\r
+  )\r
+{\r
+  UINT8     Index;\r
+  for (Index = 0; mLpcWpce791DeviceList[Index].Device.HID != 0; Index++) {\r
+    if (DeviceHid == mLpcWpce791DeviceList[Index].Device.HID) {\r
+      mLpcWpce791DeviceList[Index].ResourceItem = NULL;\r
+    }\r
+  }\r
+  return;\r
+}\r
+\r
+/**\r
+\r
+  Clear out Resource List if device is set to disable by platform policy\r
+\r
+**/\r
+VOID\r
+EmptyResourceListHidUid (\r
+  IN  UINT32      DeviceHid,\r
+  IN  UINT32      DeviceUid\r
+  )\r
+{\r
+  UINT8     Index;\r
+  for (Index = 0; mLpcWpce791DeviceList[Index].Device.HID != 0; Index++) {\r
+    if ((DeviceHid == mLpcWpce791DeviceList[Index].Device.HID) &&\r
+        (DeviceUid == mLpcWpce791DeviceList[Index].Device.UID)) {\r
+      mLpcWpce791DeviceList[Index].ResourceItem = NULL;\r
+    }\r
+  }\r
+  return;\r
+}\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+IsaInitDevice (\r
+  IN    EFI_ISA_ACPI_PROTOCOL        *This,\r
+  IN    EFI_ISA_ACPI_DEVICE_ID       *Device\r
+  )\r
+{\r
+  EFI_WPCE791_POLICY_PROTOCOL      *LpcWpce791Policy;\r
+  EFI_STATUS                      Status;\r
+\r
+  //\r
+  // Disable configuration according to platform protocol\r
+  //\r
+  Status = gBS->LocateProtocol (\r
+                  &gEfiLpcWpce791PolicyProtocolGuid,\r
+                  NULL,\r
+                  (VOID **) &LpcWpce791Policy\r
+                  );\r
+  if (!EFI_ERROR(Status)) {\r
+    if (LpcWpce791Policy->DeviceEnables.Ps2Keyboard == EFI_WPCE791_PS2_KEYBOARD_DISABLE) {\r
+      EmptyResourceList(EISA_PNP_ID(0x303));\r
+      DisableLogicalDevice (SIO_KEYBOARD);\r
+      EmptyResourceList(EISA_PNP_ID(0xF03));\r
+      DisableLogicalDevice (SIO_KEYBOARD);\r
+    }\r
+    if (LpcWpce791Policy->DeviceEnables.Ps2Mouse == EFI_WPCE791_PS2_MOUSE_DISABLE) {\r
+      EmptyResourceList(EISA_PNP_ID(0xF03));\r
+      DisableLogicalDevice (SIO_MOUSE);\r
+    }\r
+  }\r
+\r
+  return EFI_SUCCESS;\r
+}\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+LpcInterfaceInit (\r
+  IN    EFI_ISA_ACPI_PROTOCOL        *This\r
+  )\r
+{\r
+  EFI_PCI_IO_PROTOCOL             *PciIo;\r
+  UINTN                           Index;\r
+\r
+  PciIo = (LPC_ISA_ACPI_FROM_THIS (This))->PciIo;\r
+\r
+  //\r
+  // DMA controller initialize\r
+  //\r
+  for (Index=0; Index < (sizeof(mIchDmaInitTable)/sizeof(ICH_DMA_INIT)); Index++) {\r
+    PciIo->Io.Write (\r
+                PciIo,\r
+                EfiPciIoWidthUint8,\r
+                EFI_PCI_IO_PASS_THROUGH_BAR,\r
+                mIchDmaInitTable[Index].Register,\r
+                1,\r
+                &mIchDmaInitTable[Index].Value\r
+                );\r
+  }\r
+\r
+  return EFI_SUCCESS;\r
+}\r
+\r

diff --git a/Vlv2TbltDevicePkg/Wpce791/LpcIsaAcpi.h b/Vlv2TbltDevicePkg/Wpce791/LpcIsaAcpi.h
new file mode 100644 (file)
index 0000000..54bbba8
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Wpce791/LpcIsaAcpi.h
@@ -0,0 +1,108 @@
+/*++\r
+\r
+  Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+Module Name:\r
+\r
+    LpcIsaAcpi.h\r
+\r
+Abstract:\r
+\r
+    Isa Acpi interface\r
+\r
+\r
+\r
+--*/\r
+\r
+#ifndef _LPC_ISA_ACPI_H\r
+#define _LPC_ISA_ACPI_H\r
+\r
+\r
+\r
+#include "Protocol/IsaAcpi.h"\r
+#include "Library/DevicePathLib.h"\r
+\r
+\r
+typedef struct {\r
+  UINT8  Register;\r
+  UINT8  Value;\r
+} ICH_DMA_INIT;\r
+\r
+//\r
+// Prototypes for the ISA ACPI protocol interface\r
+//\r
+EFI_STATUS\r
+EFIAPI\r
+IsaDeviceEnumerate (\r
+  IN     EFI_ISA_ACPI_PROTOCOL       *This,\r
+  OUT    EFI_ISA_ACPI_DEVICE_ID      **Device\r
+  );\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+IsaDeviceSetPower (\r
+  IN     EFI_ISA_ACPI_PROTOCOL       *This,\r
+  IN     EFI_ISA_ACPI_DEVICE_ID      *Device,\r
+  IN     BOOLEAN                     OnOff\r
+  );\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+IsaGetCurrentResource (\r
+  IN     EFI_ISA_ACPI_PROTOCOL       *This,\r
+  IN     EFI_ISA_ACPI_DEVICE_ID      *Device,\r
+  OUT    EFI_ISA_ACPI_RESOURCE_LIST  **ResourceList\r
+  );\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+IsaGetPossibleResource (\r
+  IN     EFI_ISA_ACPI_PROTOCOL       *This,\r
+  IN     EFI_ISA_ACPI_DEVICE_ID      *Device,\r
+  OUT    EFI_ISA_ACPI_RESOURCE_LIST  **ResourceList\r
+  );\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+IsaSetResource (\r
+  IN     EFI_ISA_ACPI_PROTOCOL       *This,\r
+  IN     EFI_ISA_ACPI_DEVICE_ID      *Device,\r
+  IN     EFI_ISA_ACPI_RESOURCE_LIST  *ResourceList\r
+  );\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+IsaEnableDevice (\r
+  IN    EFI_ISA_ACPI_PROTOCOL        *This,\r
+  IN    EFI_ISA_ACPI_DEVICE_ID       *Device,\r
+  IN    BOOLEAN                      Enable\r
+  );\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+IsaInitDevice (\r
+  IN    EFI_ISA_ACPI_PROTOCOL        *This,\r
+  IN    EFI_ISA_ACPI_DEVICE_ID       *Device\r
+  );\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+LpcInterfaceInit (\r
+  IN    EFI_ISA_ACPI_PROTOCOL        *This\r
+);\r
+\r
+VOID\r
+EmptyResourceList (\r
+  IN    UINT32      DeviceHid\r
+);\r
+\r
+#endif\r

diff --git a/Vlv2TbltDevicePkg/Wpce791/LpcSio.c b/Vlv2TbltDevicePkg/Wpce791/LpcSio.c
new file mode 100644 (file)
index 0000000..8446d38
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Wpce791/LpcSio.c
@@ -0,0 +1,131 @@
+/** @file\r
+\r
+  Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+Module Name:\r
+\r
+Module Name:\r
+\r
+    LpcSio.c\r
+\r
+Abstract: Sio implementation\r
+\r
+Revision History\r
+\r
+--*/\r
+\r
+#include "LpcDriver.h"\r
+#include <Library/S3BootScriptLib.h>\r
+\r
+VOID\r
+WriteRegister (\r
+  IN  UINT8   Index,\r
+  IN  UINT8   Data\r
+  );\r
+\r
+typedef struct {\r
+  UINT8 Register;\r
+  UINT8 Value;\r
+} EFI_SIO_TABLE;\r
+\r
+EFI_SIO_TABLE mSioTable[] = {\r
+  //\r
+  // Init keyboard controller\r
+  //\r
+  { REG_LOGICAL_DEVICE, SIO_KEYBOARD },\r
+  { BASE_ADDRESS_HIGH, 0x00 },\r
+  { BASE_ADDRESS_LOW, 0x60 },\r
+  { BASE_ADDRESS_HIGH2, 0x00 },\r
+  { BASE_ADDRESS_LOW2, 0x64 },\r
+  { PRIMARY_INTERRUPT_SELECT, 0x01 },\r
+  { ACTIVATE, 0x1 },\r
+\r
+  //\r
+  // Init Mouse controller\r
+  //\r
+  { REG_LOGICAL_DEVICE, SIO_MOUSE },\r
+  { BASE_ADDRESS_HIGH, 0x00 },\r
+  { BASE_ADDRESS_LOW, 0x60 },\r
+  { BASE_ADDRESS_HIGH2, 0x00 },\r
+  { BASE_ADDRESS_LOW2, 0x64 },\r
+  { PRIMARY_INTERRUPT_SELECT, 0x0c },\r
+  { ACTIVATE, 0x1 },\r
+\r
+  { REG_LOGICAL_DEVICE, SIO_COM },\r
+  { BASE_ADDRESS_HIGH, 0x03 },\r
+  { BASE_ADDRESS_LOW, 0xf8 },\r
+  { PRIMARY_INTERRUPT_SELECT, 0x04 },\r
+  { ACTIVATE, 0x1 },\r
+\r
+\r
+};\r
+\r
+VOID\r
+LPCWPCE791SetDefault ()\r
+{\r
+  UINT8           Index;\r
+\r
+  for (Index = 0; Index < sizeof(mSioTable)/sizeof(EFI_SIO_TABLE); Index++) {\r
+    WriteRegisterAndSaveToScript (mSioTable[Index].Register, mSioTable[Index].Value);\r
+  }\r
+\r
+  return;\r
+}\r
+\r
+VOID\r
+DisableLogicalDevice (\r
+  UINT8       DeviceId\r
+  )\r
+{\r
+  WriteRegisterAndSaveToScript (REG_LOGICAL_DEVICE, DeviceId);\r
+  WriteRegisterAndSaveToScript (ACTIVATE, 0);\r
+  WriteRegisterAndSaveToScript (BASE_ADDRESS_HIGH, 0);\r
+  WriteRegisterAndSaveToScript (BASE_ADDRESS_LOW, 0);\r
+\r
+  return;\r
+}\r
+\r
+VOID\r
+WriteRegister (\r
+  IN  UINT8   Index,\r
+  IN  UINT8   Data\r
+  )\r
+{\r
+  LpcIoWrite8(CONFIG_PORT, Index);\r
+  LpcIoWrite8(DATA_PORT, Data);\r
+\r
+  return;\r
+}\r
+\r
+VOID\r
+WriteRegisterAndSaveToScript (\r
+  IN  UINT8   Index,\r
+  IN  UINT8   Data\r
+  )\r
+{\r
+  UINT8  Buffer[2];\r
+\r
+  LpcIoWrite8(CONFIG_PORT, Index);\r
+  LpcIoWrite8(DATA_PORT, Data);\r
+\r
+  Buffer[0] = Index;\r
+  Buffer[1] = Data;\r
+  S3BootScriptSaveIoWrite (\r
+    EfiBootScriptWidthUint8,\r
+    INDEX_PORT,\r
+    2,\r
+    Buffer\r
+    );\r
+\r
+  return;\r
+}\r
+\r

diff --git a/Vlv2TbltDevicePkg/Wpce791/LpcSio.h b/Vlv2TbltDevicePkg/Wpce791/LpcSio.h
new file mode 100644 (file)
index 0000000..f54bc7a
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Wpce791/LpcSio.h
@@ -0,0 +1,106 @@
+/*++\r
+\r
+  Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>\r
+                                                                                   \r\r
+  This program and the accompanying materials are licensed and made available under\r\r
+  the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+  The full text of the license may be found at                                     \r\r
+  http://opensource.org/licenses/bsd-license.php.                                  \r\r
+                                                                                   \r\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+                                                                                   \r\r
+\r
+Module Name:\r
+\r
+    LpcSio.h\r
+\r
+Abstract:\r
+\r
+    Lpc driver's sio interface\r
+\r
+\r
+\r
+--*/\r
+\r
+#ifndef _LPC_SIO_H\r
+#define _LPC_SIO_H\r
+\r
+#include "Protocol/PciRootBridgeIo.h"\r
+\r
+#define VARSIOINSTALLED L"VarSIOProcotolInstalled"\r
+\r
+//\r
+// Port address\r
+//\r
+#define CONFIG_PORT               0x04E\r
+#define INDEX_PORT                0x04E\r
+#define DATA_PORT                 INDEX_PORT + 1\r
+\r
+//\r
+// Logical Device\r
+//\r
+#define SIO_COM                   0x3\r
+#define SIO_MSWC                  0x4\r
+#define SIO_MOUSE                 0x5\r
+#define SIO_KEYBOARD              0x6\r
+#define SIO_SHM                   0xF\r
+#define SIO_PM1                   0x11\r
+#define SIO_PM2                   0x12\r
+#define SIO_PM3                   0x17\r
+#define SIO_ESHM                  0x1D\r
+\r
+//\r
+// Global register\r
+//\r
+#define REG_LOGICAL_DEVICE        0x07\r
+#define REG_DEVICE_ID             0x20\r
+#define SIO_CONFIG_1              0x21\r
+#define REG_CHIP_REV              0x24\r
+#define SIO_CONFIG_5              0x25\r
+#define SIO_CONFIG_6              0x26\r
+#define REG_DEVICE_REV            0x27\r
+#define SIO_CONFIG_9              0x29\r
+#define SIO_CONFIG_D              0x2D\r
+\r
+#define ACTIVATE                  0x30\r
+#define BASE_ADDRESS_HIGH         0x60\r
+#define BASE_ADDRESS_LOW          0x61\r
+#define BASE_ADDRESS_HIGH2        0x62\r
+#define BASE_ADDRESS_LOW2         0x63\r
+#define PRIMARY_INTERRUPT_SELECT  0x70\r
+#define DMA_CHANNEL_SELECT        0x74\r
+\r
+EFI_STATUS\r
+InitializeLpcSio (\r
+  IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL  *RootBridgeIo\r
+  );\r
+\r
+//\r
+// Prototypes for the sio internal function\r
+//\r
+//\r
+// Internal function\r
+//\r
+VOID\r
+LPCWPCE791SetDefault (\r
+  VOID\r
+  );\r
+\r
+VOID\r
+WriteRegisterAndSaveToScript (\r
+  IN  UINT8   Index,\r
+  IN  UINT8   Data\r
+  );\r
+\r
+VOID\r
+FloppyWriteProtect (\r
+  VOID\r
+  );\r
+\r
+VOID\r
+DisableLogicalDevice (\r
+  UINT8       DeviceId\r
+  );\r
+\r
+#endif\r

diff --git a/Vlv2TbltDevicePkg/Wpce791/Wpce791.inf b/Vlv2TbltDevicePkg/Wpce791/Wpce791.inf
new file mode 100644 (file)
index 0000000..0296d09
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Wpce791/Wpce791.inf
@@ -0,0 +1,68 @@
+#\r
+#\r
+# Copyright (c)  1999  - 2014, Intel Corporation. All rights reserved\r
+#                                                                                  \r\r
+# This program and the accompanying materials are licensed and made available under\r\r
+# the terms and conditions of the BSD License that accompanies this distribution.  \r\r
+# The full text of the license may be found at                                     \r\r
+# http://opensource.org/licenses/bsd-license.php.                                  \r\r
+#                                                                                  \r\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,            \r\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    \r\r
+#                                                                                  \r\r
+#\r
+#\r
+#\r
+#  Module Name:\r
+#\r
+#    SiO791.inf\r
+#\r
+#  Abstract:\r
+#\r
+#    Component description file for SIO791 module.\r
+#\r
+--*/\r
+\r
+[defines]\r
+  INF_VERSION                    = 0x00010005\r
+  BASE_NAME                      = SIO791\r
+  FILE_GUID                      = 04A76C80-06B9-445e-B73E-CB8C61A6A964\r
+  MODULE_TYPE                    = DXE_DRIVER\r
+  VERSION_STRING                 = 1.0\r
+  ENTRY_POINT                    = LpcDriverEntryPoint\r
+\r
+[sources.common]\r
+ LpcIsaAcpi.h\r
+ LpcSio.h\r
+ LpcDriver.h\r
+ LpcIsaAcpi.c\r
+ LpcSio.c\r
+ LpcDriver.c\r
+\r
+[Packages]\r
+  MdePkg/MdePkg.dec\r
+  Vlv2TbltDevicePkg/PlatformPkg.dec\r
+  IntelFrameworkPkg/IntelFrameworkPkg.dec\r
+  IntelFrameworkModulePkg/IntelFrameworkModulePkg.dec\r
+  PcAtChipsetPkg/PcAtChipsetPkg.dec\r
+\r
+\r
+[LibraryClasses]\r
+  UefiDriverEntryPoint\r
+  UefiBootServicesTableLib\r
+  DevicePathLib\r
+  UefiLib\r
+  S3BootScriptLib\r
+  DebugLib\r
+\r
+[Ppis]\r
+\r
+[Protocols]\r
+  gEfiPciIoProtocolGuid\r
+  gEfiIsaAcpiProtocolGuid\r
+  gEfiLpcWpce791PolicyProtocolGuid\r
+\r
+[Guids]\r
+\r
+[Depex]\r
+  TRUE\r

diff --git a/Vlv2TbltDevicePkg/bldX64.bat b/Vlv2TbltDevicePkg/bldX64.bat
new file mode 100644 (file)
index 0000000..afda8c8
--- /dev/null
+++ b/Vlv2TbltDevicePkg/bldX64.bat
@@ -0,0 +1,222 @@
+@REM @file\r
+@REM   Windows batch file to build BIOS ROM\r
+@REM\r
+@REM Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>\r
+@REM This program and the accompanying materials\r
+@REM are licensed and made available under the terms and conditions of the BSD License\r
+@REM which accompanies this distribution.  The full text of the license may be found at\r
+@REM http://opensource.org/licenses/bsd-license.php\r
+@REM\r
+@REM THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+@REM WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+@REM\r
+\r
+@echo off\r
+@echo.\r
+@time /t\r
+\r
+@if exist %WORKSPACE%\edk2.log del %WORKSPACE%\edk2.log\r
+@if exist %WORKSPACE%\unitool.log del %WORKSPACE%\unitool.log\r
+@if exist %WORKSPACE%\Conf\build_rule.txt del %WORKSPACE%\Conf\build_rule.txt\r
+@if exist %WORKSPACE%\Conf\FrameworkDatabase.db del %WORKSPACE%\Conf\FrameworkDatabase.db\r
+@if exist %WORKSPACE%\Conf\target.txt del %WORKSPACE%\Conf\target.txt\r
+@if exist %WORKSPACE%\Conf\tools_def.txt del %WORKSPACE%\Conf\tools_def.txt\r
+@if exist conf\.cache rmdir /q /s conf\.cache\r
+\r
+@set target=DEBUG\r
+\r
+@if /i "%1" == "release" set TARGET=RELEASE\r
+@if /i "%2" == "release" set TARGET=RELEASE\r
+@if /i "%3" == "release" set TARGET=RELEASE\r
+@if /i "%4" == "release" set TARGET=RELEASE\r
+@if /i "%5" == "release" set TARGET=RELEASE\r
+\r
+@set PlatformType=NO_PLATFORM\r
+@set config_file=.\Vlv2TbltDevicePkg\PlatformPkgConfig.dsc\r
+@set EVN_debug_file=.\Vlv2TbltDevicePkg\BiosIdx64D.env\r
+@set EVN_release_file=.\Vlv2TbltDevicePkg\BiosIdx64R.env\r
+@set auto_config_inc=.\Vlv2TbltDevicePkg\AutoPlatformCFG.txt\r
+\r
+@if  "%1" == "MNW2" (\r
+  set %PlatformType% = MNW2\r
+  @echo  Setting Baley Bay platform configration and BIOS ID ...\r
+  findstr /b /v BOARD_ID %EVN_debug_file% > newfile.env\r
+  echo BOARD_ID = MNW2MAX >> newfile.env\r
+  type newfile.env > %EVN_debug_file%\r
+  findstr /b /v BOARD_ID %EVN_release_file% > newfile.env\r
+  echo BOARD_ID = MNW2MAX >> newfile.env\r
+  type newfile.env > %EVN_release_file%\r
+  echo DEFINE ENBDT_PF_BUILD = TRUE  >> %auto_config_inc%\r
+  echo DEFINE X64_CONFIG = TRUE  >> %auto_config_inc%\r
+  goto PLATFORM_SETTING_DONE\r
+)  \r
+\r
+@if  "%PlatformType%" == "NO_PLATFORM" (\r
+  goto BldFail\r
+)\r
+\r
+rem clearup the temp file\r
+:PLATFORM_SETTING_DONE\r
+@DEL NEWFILE.ENV\r
+@DEL NEWFILE.CFG\r
+\r
+@REM Define platform specific environment variables.\r
+@REM\r
+@set PLATFORM_PACKAGE=Vlv2TbltDevicePkg\r
+@set SCRIPT_ERROR=0\r
+\r
+@REM Set basic environment.\r
+@echo.\r
+@echo Run edksetup.bat batch file.\r
+@echo.\r
+@del Conf\build_rule.txt\r
+@REM @del Conf\tools_def.txt\r
+@call edksetup.bat\r
+\r
+\r
+@echo.\r
+@echo Set the VS2008 environment.\r
+@echo.\r
+@if defined VS90COMNTOOLS (\r
+  if not defined VSINSTALLDIR call "%VS90COMNTOOLS%\vsvars32.bat"\r
+  if /I "%VS90COMNTOOLS%" == "C:\Program Files\Microsoft Visual Studio 9.0\Common7\Tools\" (\r
+    set TOOL_CHAIN_TAG=VS2008\r
+  ) else (\r
+    set TOOL_CHAIN_TAG=VS2008x86\r
+  )\r
+) else (\r
+  echo.\r
+  echo !!! ERROR !!! VS2008 not installed correctly. VS90COMNTOOLS not defined. !!!\r
+  echo.\r
+  set SCRIPT_ERROR=1\r
+  goto :BldEnd\r
+)\r
+\r
+@echo.\r
+@echo Set build environment.\r
+@echo.\r
+@if not exist Build\%PLATFORM_PACKAGE%\%TARGET%_%TOOL_CHAIN_TAG% (\r
+  mkdir Build\%PLATFORM_PACKAGE%\%TARGET%_%TOOL_CHAIN_TAG%\r
+)\r
+\r
+\r
+@REM Set clean build option\r
+@set CLEAN_BUILD_OPTION=-e\r
+\r
+@findstr /V "ACTIVE_PLATFORM TARGET TARGET_ARCH TOOL_CHAIN_TAG BUILD_RULE_CONF" Conf\target.txt > Build\%PLATFORM_PACKAGE%\%TARGET%_%TOOL_CHAIN_TAG%\target.txt\r
+\r
+@echo ACTIVE_PLATFORM = %PLATFORM_PACKAGE%/PlatformPkgX64.dsc     >> Build\%PLATFORM_PACKAGE%\%TARGET%_%TOOL_CHAIN_TAG%\target.txt\r
+@echo TARGET          = %TARGET%                                  >> Build\%PLATFORM_PACKAGE%\%TARGET%_%TOOL_CHAIN_TAG%\target.txt\r
+@echo TARGET_ARCH     = IA32 X64                                  >> Build\%PLATFORM_PACKAGE%\%TARGET%_%TOOL_CHAIN_TAG%\target.txt\r
+@echo TOOL_CHAIN_TAG  = %TOOL_CHAIN_TAG%                          >> Build\%PLATFORM_PACKAGE%\%TARGET%_%TOOL_CHAIN_TAG%\target.txt\r
+@echo BUILD_RULE_CONF = Conf/build_rule.txt                       >> Build\%PLATFORM_PACKAGE%\%TARGET%_%TOOL_CHAIN_TAG%\target.txt\r
+@move /Y Build\%PLATFORM_PACKAGE%\%TARGET%_%TOOL_CHAIN_TAG%\target.txt Conf\r
+\r
+\r
+\r
+@echo.\r
+@echo Create BiosIdx64.\r
+@echo.\r
+@if not exist Build\%PLATFORM_PACKAGE%\%TARGET%_%TOOL_CHAIN_TAG%\X64 (\r
+  mkdir Build\%PLATFORM_PACKAGE%\%TARGET%_%TOOL_CHAIN_TAG%\X64\r
+)\r
+\r
+@if "%TARGET%" == "DEBUG" (\r
+  set BIOS_ID_FILE=BiosIdx64D.env\r
+\r
+) else (\r
+  set BIOS_ID_FILE=BiosIdx64R.env\r
+\r
+)\r
+\r
+\r
+GenBiosId.exe -i %PLATFORM_PACKAGE%\%BIOS_ID_FILE% -o Build\%PLATFORM_PACKAGE%\%TARGET%_%TOOL_CHAIN_TAG%\X64\BiosId.bin\r
+@if %ERRORLEVEL% NEQ 0 goto BldFail\r
+\r
+@echo off\r
+echo Copy reference code ASL files.\r
+\r
+\r
+@if /i "/s" == "%1" goto BldSilent\r
+@if /i "/s" == "%2" goto BldSilent\r
+@if /i "/s" == "%3" goto BldSilent\r
+@if /i "/s" == "%4" goto BldSilent\r
+@if /i "/s" == "%5" goto BldSilent\r
+\r
+build -n %NUMBER_OF_PROCESSORS%\r
+@if %ERRORLEVEL% NEQ 0 goto BldFail\r
+\r
+@If %SCRIPT_ERROR% EQU 1 goto BldFail\r
+@goto BldSuccess\r
+\r
+:BldSilent\r
+\r
+build -n %NUMBER_OF_PROCESSORS% 1>>EDK2.log 2>&1\r
+@if %ERRORLEVEL% NEQ 0 goto BldFail\r
+\r
+\r
+@If %SCRIPT_ERROR% EQU 1 goto BldFail\r
+\r
+:BldSuccess\r
+@echo off\r
+del Build\%PLATFORM_PACKAGE%\%TARGET%_%TOOL_CHAIN_TAG%\FV\VlvX64.beforeconfig.fd 1>>EDK2.log 2>&1\r
+del Build\%PLATFORM_PACKAGE%\%TARGET%_%TOOL_CHAIN_TAG%\FV\HiiDefaultData.txt 1>>EDK2.log 2>&1\r
+copy /y Build\%PLATFORM_PACKAGE%\%TARGET%_%TOOL_CHAIN_TAG%\FV\Vlv.fd     Build\%PLATFORM_PACKAGE%\%TARGET%_%TOOL_CHAIN_TAG%\FV\VlvX64.beforeconfig.fd 1>>EDK2.log 2>&1\r
+\r
+@echo.\r
+@echo Extract setup default value from VFR (Build\%PLATFORM_PACKAGE%\%TARGET%_%TOOL_CHAIN_TAG%\FV\HiiDefaultData.txt)\r
+@echo.\r
+fce read -i Build\%PLATFORM_PACKAGE%\%TARGET%_%TOOL_CHAIN_TAG%\FV\VlvX64.beforeconfig.fd > Build\%PLATFORM_PACKAGE%\%TARGET%_%TOOL_CHAIN_TAG%\FV\HiiDefaultData.txt\r
+\r
+\r
+@echo Update FD with default Hii value successfully! (both 'Setup' and 'SetupDefault')\r
+@echo.\r
+fce mirror -i Build\%PLATFORM_PACKAGE%\%TARGET%_%TOOL_CHAIN_TAG%\FV\VlvX64.beforeconfig.fd -o Build\%PLATFORM_PACKAGE%\%TARGET%_%TOOL_CHAIN_TAG%\FV\VlvX64.fd Setup SetupDefault 1>>EDK2.log 2>&1\r
+\r
+@echo off\r
+del Build\%PLATFORM_PACKAGE%\%TARGET%_%TOOL_CHAIN_TAG%\FV\Vlv.fd\r
+del Vlv2TbltDevicePkg\RomImage\bios.rom\r
+if not exist Build\%PLATFORM_PACKAGE%\%TARGET%_%TOOL_CHAIN_TAG%\ROM goto Gen8MImage\r
+del /q /f Build\%PLATFORM_PACKAGE%\%TARGET%_%TOOL_CHAIN_TAG%\ROM\*\r
+rd /Q Build\%PLATFORM_PACKAGE%\%TARGET%_%TOOL_CHAIN_TAG%\ROM\r
+:Gen8MImage\r
+\r
+copy /b Build\%PLATFORM_PACKAGE%\%TARGET%_%TOOL_CHAIN_TAG%\FV\VlvX64.fd Vlv2TbltDevicePkg\RomImage\bios.rom\r
+\r
+pushd Vlv2TbltDevicePkg\RomImage\\r
+@if "%TARGET%" == "DEBUG" (\r
+    call signbiosX64_debug.bat\r
+) else (\r
+    call signbiosX64_release.bat\r
+)\r
+\r
+call ftoolbuild.bat\r
+call ftoolbuild_sec_enable.bat\r
+popd\r
+\r
+@echo off\r
+mkdir Build\%PLATFORM_PACKAGE%\%TARGET%_%TOOL_CHAIN_TAG%\ROM\r
+move Vlv2TbltDevicePkg\RomImage\SPI_Image\* Build\%PLATFORM_PACKAGE%\%TARGET%_%TOOL_CHAIN_TAG%\ROM\ > NUL\r
+\r
+call GenBIOS.bat X64\r
+\r
+@echo on\r
+\r
+@echo TARGET:               %TARGET%\r
+@echo TOOL_CHAIN_TAG:       %TOOL_CHAIN_TAG%\r
+@echo BIOS location:        Build\%PLATFORM_PACKAGE%\%TARGET%_%TOOL_CHAIN_TAG%\FV\r
+@echo SPI Images location:  Build\%PLATFORM_PACKAGE%\%TARGET%_%TOOL_CHAIN_TAG%\ROM\r
+@echo.\r
+@echo The EDKII BIOS build has successfully completed!\r
+@echo.\r
+@goto BldEnd\r
+\r
+:BldFail\r
+@echo.\r
+@echo The EDKII BIOS Build has failed!\r
+@echo.\r
+exit /b 1\r
+\r
+:BldEnd\r
+@time /t\r
+exit /b 0\r

diff --git a/Vlv2TbltDevicePkg/bld_vlv.bat b/Vlv2TbltDevicePkg/bld_vlv.bat
new file mode 100644 (file)
index 0000000..b9c86e3
--- /dev/null
+++ b/Vlv2TbltDevicePkg/bld_vlv.bat
@@ -0,0 +1,263 @@
+@REM @file\r
+@REM   Windows batch file to build BIOS ROM\r
+@REM\r
+@REM Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>\r
+@REM This program and the accompanying materials\r
+@REM are licensed and made available under the terms and conditions of the BSD License\r
+@REM which accompanies this distribution.  The full text of the license may be found at\r
+@REM http://opensource.org/licenses/bsd-license.php\r
+@REM\r
+@REM THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+@REM WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+@REM\r
+\r
+@echo off\r
+setlocal EnableDelayedExpansion EnableExtensions\r
+echo.\r
+echo %date%  %time%\r
+echo.\r
+\r
+::**********************************************************************\r
+:: Initial Setup\r
+::**********************************************************************\r
+set WORKSPACE=%CD%\r
+if %WORKSPACE:~-1%==\ set WORKSPACE=%WORKSPACE:~0,-1%\r
+set /a build_threads=1\r
+set "Build_Flags= "\r
+set exitCode=0\r
+set Arch=X64\r
+set Source=0\r
+\r
+:: Clean up previous build files.\r
+if exist %WORKSPACE%\edk2.log del %WORKSPACE%\edk2.log\r
+if exist %WORKSPACE%\unitool.log del %WORKSPACE%\unitool.log\r
+if exist %WORKSPACE%\Conf\target.txt del %WORKSPACE%\Conf\target.txt\r
+if exist %WORKSPACE%\Conf\tools_def.txt del %WORKSPACE%\Conf\tools_def.txt\r
+if exist %WORKSPACE%\Conf\build_rule.txt del %WORKSPACE%\Conf\build_rule.txt\r
+if exist %WORKSPACE%\Conf\FrameworkDatabase.db del %WORKSPACE%\Conf\FrameworkDatabase.db\r
+if exist conf\.cache rmdir /q/s conf\.cache\r
+\r
+:: Setup EDK environment. Edksetup puts new copies of target.txt, tools_def.txt, build_rule.txt in WorkSpace\Conf\r
+:: Also run edksetup as soon as possible to avoid it from changing environment variables we're overriding\r
+call edksetup.bat > nul\r
+@echo off\r
+\r
+:: Define platform specific environment variables.\r
+set PLATFORM_PACKAGE=Vlv2TbltDevicePkg\r
+set config_file=.\%PLATFORM_PACKAGE%\PlatformPkgConfig.dsc\r
+set auto_config_inc=.\%PLATFORM_PACKAGE%\AutoPlatformCFG.txt\r
+\r
+set EDK_SOURCE=%WORKSPACE%\EdkCompatibilityPkg\r
+\r
+::create new AutoPlatformCFG.txt file\r
+copy /y nul %auto_config_inc% >nul\r
+\r
+::**********************************************************************\r
+:: Parse command line arguments\r
+::**********************************************************************\r
+\r
+:: Optional arguments\r
+:OptLoop\r
+if /i "%~1"=="/?" goto Usage\r
+\r
+if /i "%~1"=="/l" (\r
+    set Build_Flags=%Build_Flags% -j EDK2.log\r
+    shift\r
+    goto OptLoop\r
+)\r
+if /i "%~1" == "/c" (\r
+    echo Removing previous build files ...\r
+    if exist build (\r
+        del /f/s/q build > null\r
+        rmdir /s/q build\r
+    )\r
+    if exist conf\.cache (\r
+        del /f/s/q conf\.cache > null\r
+        rmdir /s/q conf\.cache\r
+    )\r
+    echo.\r
+    shift\r
+    goto OptLoop\r
+)\r
+\r
+if /i "%~1"=="/x64" (\r
+    set Arch=X64\r
+    shift\r
+    goto OptLoop\r
+)\r
+if /i "%~1"=="/IA32" (\r
+    set Arch=IA32\r
+    shift\r
+    goto OptLoop\r
+)\r
+\r
+:: Required argument(s)\r
+if "%~1"=="" goto Usage\r
+\r
+::Remove the values for Platform_Type and Build_Target from BiosIdX.env and stage in Conf\\r
+if "%Arch%"=="IA32" (\r
+    findstr /b /v "BOARD_ID  BUILD_TYPE" %PLATFORM_PACKAGE%\BiosIdR.env > Conf\BiosId.env\r
+    echo DEFINE X64_CONFIG = FALSE  >> %auto_config_inc%\r
+) else if "%Arch%"=="X64" (\r
+    findstr /b /v "BOARD_ID  BUILD_TYPE" %PLATFORM_PACKAGE%\BiosIdx64R.env > Conf\BiosId.env\r
+    echo DEFINE X64_CONFIG = TRUE  >> %auto_config_inc%\r
+)\r
+\r
+:: -- Build flags settings for each Platform --\r
+echo Setting  %1  platform configuration and BIOS ID...\r
+if /i "%~1" == "MNW2" (\r
+    echo BOARD_ID = MNW2MAX >> %Conf\BiosId.env\r
+    echo DEFINE ENBDT_PF_BUILD = TRUE   >> %auto_config_inc%\r
+    \r
+) else (\r
+    echo Error - Unsupported PlatformType: %1\r
+    goto Usage\r
+)\r
+set Platform_Type=%~1\r
+\r
+if /i "%~2" == "RELEASE" (\r
+    set target=RELEASE\r
+    echo BUILD_TYPE = R >> Conf\BiosId.env\r
+) else (\r
+    set target=DEBUG\r
+    echo BUILD_TYPE = D >> Conf\BiosId.env\r
+)\r
+\r
+::**********************************************************************\r
+:: Additional EDK Build Setup/Configuration\r
+::**********************************************************************\r
+echo.\r
+echo Setting the Build environment for VS2008/VS2010...\r
+if defined VS90COMNTOOLS (\r
+   if not defined VSINSTALLDIR call "%VS90COMNTOOLS%\vsvars32.bat"\r
+   if /I "%VS90COMNTOOLS%" == "C:\Program Files\Microsoft Visual Studio 9.0\Common7\Tools\" (\r
+      set TOOL_CHAIN_TAG=VS2008\r
+   ) else (\r
+      set TOOL_CHAIN_TAG=VS2008x86\r
+   )\r
+ ) else if defined VS100COMNTOOLS (\r
+  if not defined VSINSTALLDIR call "%VS100COMNTOOLS%\vsvars32.bat"\r
+  if /I "%VS100COMNTOOLS%" == "C:\Program Files\Microsoft Visual Studio 10.0\Common7\Tools\" (\r
+    set TOOL_CHAIN_TAG=VS2010\r
+) else (\r
+    set TOOL_CHAIN_TAG=VS2010x86\r
+ )\r
+) else (\r
+   echo  --ERROR: VS2008/VS2010 not installed correctly. VS90COMNTOOLS/VS100COMNTOOLS not defined ^^!\r
+   echo.\r
+   goto :BldFail\r
+)\r
+\r
+echo Ensuring correct build directory is present for GenBiosId...\r
+set BUILD_PATH=Build\%PLATFORM_PACKAGE%\%TARGET%_%TOOL_CHAIN_TAG%\r
+\r
+echo Modifing Conf files for this build...\r
+:: Remove lines with these tags from target.txt\r
+findstr /V "TARGET  TARGET_ARCH  TOOL_CHAIN_TAG  BUILD_RULE_CONF  ACTIVE_PLATFORM  MAX_CONCURRENT_THREAD_NUMBER" Conf\target.txt > Conf\target.txt.tmp\r
+\r
+echo TARGET          = %TARGET%                                  >> Conf\target.txt.tmp\r
+if "%Arch%"=="IA32" (\r
+    echo TARGET_ARCH = IA32                                      >> Conf\target.txt.tmp\r
+) else if "%Arch%"=="X64" (\r
+    echo TARGET_ARCH = IA32 X64                                  >> Conf\target.txt.tmp\r
+)\r
+echo TOOL_CHAIN_TAG  = %TOOL_CHAIN_TAG%                                  >> Conf\target.txt.tmp\r
+echo BUILD_RULE_CONF = Conf/build_rule.txt                               >> Conf\target.txt.tmp\r
+if %Source% == 0 (\r
+  echo ACTIVE_PLATFORM = %PLATFORM_PACKAGE%/PlatformPkg%Arch%.dsc        >> Conf\target.txt.tmp\r
+) else (\r
+  echo ACTIVE_PLATFORM = %PLATFORM_PACKAGE%/PlatformPkg%Arch%Source.dsc  >> Conf\target.txt.tmp\r
+)\r
+echo MAX_CONCURRENT_THREAD_NUMBER = %build_threads%                      >> Conf\target.txt.tmp\r
+\r
+move /Y Conf\target.txt.tmp Conf\target.txt >nul\r
+\r
+::**********************************************************************\r
+:: Build BIOS\r
+::**********************************************************************\r
+\r
+echo Creating BiosId...\r
+pushd %PLATFORM_PACKAGE%\r
+if not exist ..\%BUILD_PATH%\IA32  mkdir ..\%BUILD_PATH%\IA32\r
+  GenBiosId.exe -i ..\Conf\BiosId.env -o ..\%BUILD_PATH%\IA32\BiosId.bin -ob ..\Conf\BiosId.bat\r
+if "%Arch%"=="X64" (\r
+   if not exist ..\%BUILD_PATH%\X64  mkdir ..\%BUILD_PATH%\X64\r
+   GenBiosId.exe -i ..\Conf\BiosId.env -o ..\%BUILD_PATH%\X64\BiosId.bin -ob ..\Conf\BiosId.bat\r
+)\r
+popd\r
+\r
+\r
+if %ERRORLEVEL% NEQ 0 goto BldFail\r
+\r
+echo.\r
+echo Invoking EDK2 build...\r
+build %Build_Flags%\r
+\r
+if %ERRORLEVEL% NEQ 0 goto BldFail\r
+\r
+::**********************************************************************\r
+:: Post Build processing and cleanup\r
+::**********************************************************************\r
+\r
+echo Running fce...\r
+\r
+pushd %PLATFORM_PACKAGE%\r
+:: Extract Hii data from build and store in HiiDefaultData.txt\r
+fce read -i ..\%BUILD_PATH%\FV\Vlv.fd > ..\%BUILD_PATH%\FV\HiiDefaultData.txt 1>>EDK2.log 2>&1\r
+\r
+:: copy the Setup variable to the SetupDefault variable and save changes to VlvXXX.fd\r
+fce mirror -i ..\%BUILD_PATH%\FV\Vlv.fd -o ..\%BUILD_PATH%\FV\Vlv%Arch%.fd Setup SetupDefault 1>>EDK2.log 2>&1\r
+\r
+popd\r
+\r
+if %ERRORLEVEL% NEQ 0 goto BldFail\r
+::echo FD successfully updated with default Hii values.\r
+\r
+:: Set the Board_Id, Build_Type, Version_Major, and Version_Minor environment variables\r
+find /v "#" Conf\BiosId.env > ver_strings\r
+for /f "tokens=1,3" %%i in (ver_strings) do set %%i=%%j\r
+del /f/q ver_strings >nul\r
+\r
+set BIOS_Name=%BOARD_ID%_%Arch%_%BUILD_TYPE%_%VERSION_MAJOR%_%VERSION_MINOR%.ROM\r
+copy /y/b %BUILD_PATH%\FV\Vlv%Arch%.fd  %WORKSPACE%\%BIOS_Name% >nul\r
+\r
+echo.\r
+echo Build location:     %BUILD_PATH%\r
+echo BIOS ROM Created:   %BIOS_Name%\r
+echo.\r
+echo -------------------- The EDKII BIOS build has successfully completed. --------------------\r
+echo.\r
+goto Exit\r
+\r
+:Usage\r
+echo.\r
+echo ***************************************************************************\r
+echo Build BIOS rom for VLV platforms.\r
+echo.\r
+echo Usage: bld_vlv.bat [options] PlatformType [Build Target]\r
+echo.\r
+echo    /c    CleanAll before building\r
+echo    /IA32 Set Arch to IA32 (default: X64)\r
+echo    /X64  Set Arch to X64 (default: X64)\r
+echo.\r
+echo        Platform Types:  MNW2\r
+echo        Build Targets:   Debug, Release  (default: Debug)\r
+echo.\r
+echo Examples:\r
+echo    bld_vlv.bat MNW2                 : X64 Debug build for MinnowMax\r
+echo    bld_vlv.bat /IA32 MNW2 release   : IA32 Release build for MinnowMax\r
+echo.\r
+echo ***************************************************************************\r
+set exitCode=1\r
+goto Exit\r
+\r
+:BldFail\r
+set exitCode=1\r
+echo  -- Error:  EDKII BIOS Build has failed!\r
+echo See EDK2.log for more details\r
+\r
+:Exit\r
+echo %date%  %time%\r
+exit /b %exitCode%\r
+\r
+EndLocal\r

diff --git a/Vlv2TbltDevicePkg/bld_vlv.sh b/Vlv2TbltDevicePkg/bld_vlv.sh
new file mode 100644 (file)
index 0000000..4c01b1c
--- /dev/null
+++ b/Vlv2TbltDevicePkg/bld_vlv.sh
@@ -0,0 +1,235 @@
+##**********************************************************************
+## Function define
+##**********************************************************************
+function Usage() {
+  echo
+  echo "***************************************************************************"
+  echo "Build BIOS rom for VLV platforms."
+  echo
+  echo "Usage: bld_vlv.bat  PlatformType [Build Target]"
+  echo
+  echo
+  echo "       Platform Types:  MNW2"
+  echo "       Build Targets:   Debug, Release  (default: Debug)"
+  echo
+  echo "***************************************************************************"
+  echo "Press any key......"
+  read
+  exit 0
+}
+
+
+echo -e $(date)
+##**********************************************************************
+## Initial Setup
+##**********************************************************************
+#WORKSPACE=$(pwd)
+#build_threads=($NUMBER_OF_PROCESSORS)+1
+Build_Flags=
+exitCode=0
+Arch=X64
+
+## Clean up previous build files.
+if [ -e $(pwd)/EDK2.log ]; then
+  rm $(pwd)/EDK2.log
+fi
+
+if [ -e $(pwd)/Unitool.log ]; then
+  rm $(pwd)/Unitool.log
+fi
+
+if [ -e $(pwd)/Conf/target.txt ]; then
+  rm $(pwd)/Conf/target.txt
+fi
+
+if [ -e $(pwd)/Conf/BiosId.env ]; then
+  rm $(pwd)/Conf/BiosId.env
+fi
+
+if [ -e $(pwd)/Conf/tools_def.txt ]; then
+  rm $(pwd)/Conf/tools_def.txt
+fi
+
+if [ -e $(pwd)/Conf/build_rule.txt ]; then
+  rm $(pwd)/Conf/build_rule.txt
+fi
+
+
+## Setup EDK environment. Edksetup puts new copies of target.txt, tools_def.txt, build_rule.txt in WorkSpace\Conf
+## Also run edksetup as soon as possible to avoid it from changing environment variables we're overriding
+. edksetup.sh
+make -C BaseTools
+
+## Define platform specific environment variables.
+PLATFORM_PACKAGE=Vlv2TbltDevicePkg
+config_file=$WORKSPACE/$PLATFORM_PACKAGE/PlatformPkgConfig.dsc
+auto_config_inc=$WORKSPACE/$PLATFORM_PACKAGE/AutoPlatformCFG.txt
+
+## default ECP (override with /ECP flag)
+EDK_SOURCE=$WORKSPACE/EdkCompatibilityPkg
+
+## create new AutoPlatformCFG.txt file
+if [ -f "$auto_config_inc" ]; then
+  rm $auto_config_inc
+fi
+touch $auto_config_inc
+
+##**********************************************************************
+## Parse command line arguments
+##**********************************************************************
+
+## Optional arguments
+for (( i=1; i<=$#; ))
+  do
+    if [ "$1" == "/?" ]; then
+      Usage
+    elif [ "$(echo $1 | tr 'a-z' 'A-Z')" == "/Q" ]; then
+      Build_Flags="$Build_Flags --quiet"
+      shift
+    elif [ "$(echo $1 | tr 'a-z' 'A-Z')" == "/L" ]; then
+      Build_Flags="$Build_Flags -j EKD2.log"
+      shift
+    elif [ "$(echo $1 | tr 'a-z' 'A-Z')" == "/C" ]; then
+      echo Removing previous build files ...
+      if [ -d "Build" ]; then
+        rm -r Build
+      fi
+      shift
+    elif [ "$(echo $1 | tr 'a-z' 'A-Z')" == "/ECP" ]; then
+      ECP_SOURCE=$WORKSPACE/EdkCompatibilityPkgEcp
+      EDK_SOURCE=$WORKSPACE/EdkCompatibilityPkgEcp
+      echo DEFINE ECP_BUILD_ENABLE = TRUE >> $auto_config_inc
+      shift
+    elif [ "$(echo $1 | tr 'a-z' 'A-Z')" == "/X64" ]; then
+      Arch=X64
+      shift
+    else
+      break
+    fi
+  done
+
+
+
+
+
+## Required argument(s)
+if [ "$2" == "" ]; then
+  Usage
+fi
+
+## Remove the values for Platform_Type and Build_Target from BiosIdX.env and stage in Conf
+if [ $Arch == "IA32" ]; then
+  cp $PLATFORM_PACKAGE/BiosIdR.env    Conf/BiosId.env
+  echo DEFINE X64_CONFIG = FALSE      >> $auto_config_inc
+else
+  cp $PLATFORM_PACKAGE/BiosIdx64R.env  Conf/BiosId.env
+  echo DEFINE X64_CONFIG = TRUE       >> $auto_config_inc
+fi
+sed -i '/^BOARD_ID/d' Conf/BiosId.env
+sed -i '/^BUILD_TYPE/d' Conf/BiosId.env
+
+
+
+## -- Build flags settings for each Platform --
+##    AlpineValley (ALPV):  SVP_PF_BUILD = TRUE,   ENBDT_PF_BUILD = FALSE,  TABLET_PF_BUILD = FALSE,  BYTI_PF_BUILD = FALSE, IVI_PF_BUILD = FALSE
+##       BayleyBay (BBAY):  SVP_PF_BUILD = FALSE,  ENBDT_PF_BUILD = TRUE,   TABLET_PF_BUILD = FALSE,  BYTI_PF_BUILD = FALSE, IVI_PF_BUILD = FALSE
+##         BayLake (BLAK):  SVP_PF_BUILD = FALSE,  ENBDT_PF_BUILD = FALSE,  TABLET_PF_BUILD = TRUE,   BYTI_PF_BUILD = FALSE, IVI_PF_BUILD = FALSE
+##      Bakersport (BYTI):  SVP_PF_BUILD = FALSE,  ENBDT_PF_BUILD = FALSE,  TABLET_PF_BUILD = FALSE,  BYTI_PF_BUILD = TRUE, IVI_PF_BUILD = FALSE
+## Crestview Hills (CVHS):  SVP_PF_BUILD = FALSE,  ENBDT_PF_BUILD = FALSE,  TABLET_PF_BUILD = FALSE,  BYTI_PF_BUILD = TRUE, IVI_PF_BUILD = TRUE
+##            FFD8 (BLAK):  SVP_PF_BUILD = FALSE,  ENBDT_PF_BUILD = FALSE,  TABLET_PF_BUILD = TRUE,   BYTI_PF_BUILD = FALSE, IVI_PF_BUILD = FALSE
+echo "Setting  $1  platform configuration and BIOS ID..."
+if [ "$(echo $1 | tr 'a-z' 'A-Z')" == "MNW2" ]; then
+  echo BOARD_ID = MNW2MAX             >> Conf/BiosId.env
+  echo DEFINE ENBDT_PF_BUILD = TRUE  >> $auto_config_inc
+else
+  echo "Error - Unsupported PlatformType: $1"
+  Usage
+fi
+
+Platform_Type=$1
+
+if [ "$(echo $2 | tr 'a-z' 'A-Z')" == "RELEASE" ]; then
+  TARGET=RELEASE
+  BUILD_TYPE=R
+  echo BUILD_TYPE = R >> Conf/BiosId.env
+else
+  TARGET=DEBUG
+  BUILD_TYPE=D
+  echo BUILD_TYPE = D >> Conf/BiosId.env
+fi
+
+
+##**********************************************************************
+## Additional EDK Build Setup/Configuration
+##**********************************************************************
+echo "Ensuring correct build directory is present for GenBiosId..."
+
+echo Modifing Conf files for this build...
+## Remove lines with these tags from target.txt
+sed -i '/^ACTIVE_PLATFORM/d' Conf/target.txt
+sed -i '/^TARGET /d' Conf/target.txt
+sed -i '/^TARGET_ARCH/d' Conf/target.txt
+sed -i '/^TOOL_CHAIN_TAG/d' Conf/target.txt
+sed -i '/^MAX_CONCURRENT_THREAD_NUMBER/d' Conf/target.txt
+
+ACTIVE_PLATFORM=$PLATFORM_PACKAGE/PlatformPkgGcc"$Arch".dsc
+TOOL_CHAIN_TAG=GCC46
+MAX_CONCURRENT_THREAD_NUMBER=1
+echo ACTIVE_PLATFORM = $ACTIVE_PLATFORM                           >> Conf/target.txt
+echo TARGET          = $TARGET                                    >> Conf/target.txt
+echo TOOL_CHAIN_TAG  = $TOOL_CHAIN_TAG                            >> Conf/target.txt
+echo MAX_CONCURRENT_THREAD_NUMBER = $MAX_CONCURRENT_THREAD_NUMBER >> Conf/target.txt
+if [ $Arch == "IA32" ]; then
+  echo TARGET_ARCH   = IA32                                       >> Conf/target.txt
+else
+  echo TARGET_ARCH   = IA32 X64                                   >> Conf/target.txt
+fi
+
+##**********************************************************************
+## Build BIOS
+##**********************************************************************
+echo Skip "Running UniTool..."
+echo "Make GenBiosId Tool..."
+BUILD_PATH=Build/$PLATFORM_PACKAGE/"$TARGET"_"$TOOL_CHAIN_TAG"
+if [ ! -d "$BUILD_PATH/$Arch" ]; then
+  mkdir -p $BUILD_PATH/$Arch
+fi
+if [ -e "$BUILD_PATH/$Arch/BiosId.bin" ]; then
+  rm -f $BUILD_PATH/$Arch/BiosId.bin
+fi
+
+
+./$PLATFORM_PACKAGE/GenBiosId -i Conf/BiosId.env -o $BUILD_PATH/$Arch/BiosId.bin
+
+
+echo "Invoking EDK2 build..."
+build
+
+
+##**********************************************************************
+## Post Build processing and cleanup
+##**********************************************************************
+
+echo Skip "Running fce..."
+
+echo Skip "Running KeyEnroll..."
+
+## Set the Board_Id, Build_Type, Version_Major, and Version_Minor environment variables
+VERSION_MAJOR=$(grep '^VERSION_MAJOR' Conf/BiosId.env | cut -d ' ' -f 3 | cut -c 1-4)
+VERSION_MINOR=$(grep '^VERSION_MINOR' Conf/BiosId.env | cut -d ' ' -f 3 | cut -c 1-2)
+BOARD_ID=$(grep '^BOARD_ID' Conf/BiosId.env | cut -d ' ' -f 3 | cut -c 1-7)
+BIOS_Name="$BOARD_ID"_"$Arch"_"$BUILD_TYPE"_"$VERSION_MAJOR"_"$VERSION_MINOR".ROM
+BIOS_ID="$BOARD_ID"_"$Arch"_"$BUILD_TYPE"_"$VERSION_MAJOR"_"$VERSION_MINOR"_GCC.bin
+cp -f $BUILD_PATH/FV/VLV.fd  $WORKSPACE/$BIOS_Name
+SEC_VERSION=1.0.2.1060v5
+cat ./$PLATFORM_PACKAGE/Stitch/IFWIHeader/IFWI_HEADER.bin ./Vlv2MiscBinariesPkg/SEC/$SEC_VERSION/VLV_SEC_REGION.bin ./$PLATFORM_PACKAGE/Stitch/IFWIHeader/Vacant.bin $BIOS_Name > ./$PLATFORM_PACKAGE/Stitch/$BIOS_ID
+
+
+echo Skip "Running BIOS_Signing ..."
+
+echo
+echo Build location:     $BUILD_PATH
+echo BIOS ROM Created:   $BIOS_Name
+echo
+echo -------------------- The EDKII BIOS build has successfully completed. --------------------
+echo

diff --git a/Vlv2TbltDevicePkg/cln.sh b/Vlv2TbltDevicePkg/cln.sh
new file mode 100644 (file)
index 0000000..a0c7f0c
--- /dev/null
+++ b/Vlv2TbltDevicePkg/cln.sh
@@ -0,0 +1,59 @@
+echo
+echo Run build cleanall...
+echo
+
+echo
+echo Directories to clean...
+echo
+
+if [ -d "Build" ]; then
+  rm -r Build
+fi
+
+if [ -d "Conf/.cache" ]; then
+  rm -r Conf/.cache
+fi
+
+if [ -d "RomImages" ]; then
+  rm -r RomImages
+fi
+
+echo
+echo Files to clean...
+echo
+
+if [ -e $(pwd)/EDK2.log ]; then
+  rm $(pwd)/EDK2.log
+fi
+
+if [ -e $(pwd)/Unitool.log ]; then
+  rm $(pwd)/Unitool.log
+fi
+
+if [ -e $(pwd)/Conf/target.txt ]; then
+  rm $(pwd)/Conf/target.txt
+fi
+
+if [ -e $(pwd)/Conf/BiosId.env ]; then
+  rm $(pwd)/Conf/BiosId.env
+fi
+
+if [ -e $(pwd)/Conf/tools_def.txt ]; then
+  rm $(pwd)/Conf/tools_def.txt
+fi
+
+if [ -e $(pwd)/Conf/build_rule.txt ]; then
+  rm $(pwd)/Conf/build_rule.txt
+fi
+
+if [ -e $(pwd)/Conf/BuildEnv.sh ]; then
+  rm $(pwd)/Conf/BuildEnv.sh
+fi
+
+if [ -e $(pwd)/Vlv2TbltDevicePkg/AutoPlatformCFG.txt ]; then
+  rm $(pwd)/Vlv2TbltDevicePkg/AutoPlatformCFG.txt
+fi
+
+echo
+echo All done...
+echo