Vlv2TbltDevicePkg/Include/Guid/PlatformInfo.h

   1 /*++
   2
   3   Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>
   4
   5   This program and the accompanying materials are licensed and made available under
   6   the terms and conditions of the BSD License that accompanies this distribution.
   7   The full text of the license may be found at
   8   http://opensource.org/licenses/bsd-license.php.
   9
  10   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12
  13
  14
  15
  16 Module Name:
  17
  18   PlatformInfo.h
  19
  20 Abstract:
  21
  22   GUID used for Platform Info Data entries in the HOB list.
  23
  24 --*/
  25
  26 #ifndef _PLATFORM_INFO_GUID_H_
  27 #define _PLATFORM_INFO_GUID_H_
  28
  29 #ifndef ECP_FLAG
  30 #include <PiPei.h>
  31
  32 #include <Library/HobLib.h>
  33 #include <Library/IoLib.h>
  34 #include <Library/DebugLib.h>
  35 #include <Library/SmbusLib.h>
  36 #include <IndustryStandard/SmBus.h>
  37 #endif
  38
  39 #define PLATFORM_INFO_REVISION = 1      // Revision id for current platform information struct.
  40
  41 //
  42 // Start::BayLake Board Defines
  43 //
  44 #define BOARD_REVISION_DEFAULT = 0xff
  45 #define UNKNOWN_FABID           0x0F
  46 #define FAB_ID_MASK                     0x0F
  47 #define BOARD_ID_2   0x01
  48 #define BOARD_ID_1   0x40
  49 #define BOARD_ID_0   0x04
  50
  51 #define BOARD_ID_DT_CRB     0x0
  52 #define BOARD_ID_DT_VLVR    0x1
  53 #define BOARD_ID_SVP_VLV    0xC
  54 #define BOARD_ID_SVP_EV_VLV 0xD
  55 //
  56 // End::BayLake Board Defines
  57 //
  58
  59 //
  60 // Start::Alpine Valley Board Defines
  61 //
  62 #define DC_ID_DDR3L      0x00
  63 #define DC_ID_DDR3       0x04
  64 #define DC_ID_LPDDR3     0x02
  65 #define DC_ID_LPDDR2     0x06
  66 #define DC_ID_DDR4       0x01
  67 #define DC_ID_DDR3L_ECC  0x05
  68 #define DC_ID_NO_MEM     0x07
  69 //
  70 // End::Alpine Valley Board Defines
  71 //
  72
  73 #define MAX_FAB_ID_RETRY_COUNT  100
  74 #define MAX_FAB_ID_CHECK_COUNT  3
  75
  76 #define PLATFORM_INFO_HOB_REVISION      0x1
  77
  78 #define EFI_PLATFORM_INFO_GUID \
  79   { \
  80     0x1e2acc41, 0xe26a, 0x483d, 0xaf, 0xc7, 0xa0, 0x56, 0xc3, 0x4e, 0x8, 0x7b \
  81   }
  82
  83 extern EFI_GUID gEfiPlatformInfoGuid;
  84
  85 typedef enum {
  86   FlavorUnknown = 0,
  87
  88   //
  89   // Mobile
  90   //
  91   FlavorMobile = 1,
  92
  93   //
  94   // Desktop
  95   //
  96   FlavorDesktop = 2,
  97
  98   //
  99   // Tablet
 100   //
 101   FlavorTablet = 3
 102 } PLATFORM_FLAVOR;
 103
 104 #pragma pack(1)
 105
 106 typedef struct {
 107   UINT16  PciResourceIoBase;
 108   UINT16  PciResourceIoLimit;
 109   UINT32  PciResourceMem32Base;
 110   UINT32  PciResourceMem32Limit;
 111   UINT64  PciResourceMem64Base;
 112   UINT64  PciResourceMem64Limit;
 113   UINT64  PciExpressBase;
 114   UINT32  PciExpressSize;
 115   UINT8   PciHostAddressWidth;
 116   UINT8   PciResourceMinSecBus;
 117 } EFI_PLATFORM_PCI_DATA;
 118
 119 typedef struct {
 120   UINT8 CpuAddressWidth;
 121   UINT32 CpuFamilyStepping;
 122 } EFI_PLATFORM_CPU_DATA;
 123
 124 typedef struct {
 125   UINT8 SysIoApicEnable;
 126   UINT8 SysSioExist;
 127 } EFI_PLATFORM_SYS_DATA;
 128
 129 typedef struct {
 130   UINT32  MemTolm;
 131   UINT32  MemMaxTolm;
 132   UINT32  MemTsegSize;
 133   UINT32  MemTsegBase;
 134   UINT32  MemIedSize;
 135   UINT32  MemIgdSize;
 136   UINT32  MemIgdBase;
 137   UINT32  MemIgdGttSize;
 138   UINT32  MemIgdGttBase;
 139   UINT64  MemMir0;
 140   UINT64  MemMir1;
 141   UINT32  MemConfigSize;
 142   UINT16  MmioSize;
 143   UINT8   DdrFreq;
 144   UINT8   DdrType;
 145   UINT32  MemSize;
 146   BOOLEAN EccSupport;
 147   UINT8   Reserved[3];
 148   UINT16  DimmSize[2];
 149 } EFI_PLATFORM_MEM_DATA;
 150
 151
 152 typedef struct {
 153   UINT32 IgdOpRegionAddress;    // IGD OpRegion Starting Address
 154   UINT8  IgdBootType;           // IGD Boot Display Device
 155   UINT8  IgdPanelType;          // IGD Panel Type CMOs option
 156   UINT8  IgdTvFormat;           // IGD TV Format CMOS option
 157   UINT8  IgdTvMinor;            // IGD TV Minor Format CMOS option
 158   UINT8  IgdPanelScaling;       // IGD Panel Scaling
 159   UINT8  IgdBlcConfig;          // IGD BLC Configuration
 160   UINT8  IgdBiaConfig;          // IGD BIA Configuration
 161   UINT8  IgdSscConfig;          // IGD SSC Configuration
 162   UINT8  IgdDvmtMemSize;        // IGD DVMT Memory Size
 163   UINT8  IgdFunc1Enable;        // IGD Function 1 Enable
 164   UINT8  IgdHpllVco;            // HPLL VCO
 165   UINT8  IgdSciSmiMode;         // GMCH SMI/SCI mode (0=SCI)
 166   UINT8  IgdPAVP;               // IGD PAVP data
 167 } EFI_PLATFORM_IGD_DATA;
 168
 169 typedef enum {
 170   BOARD_ID_AV_SVP   = 0x0,    // Alpine Valley Board
 171   BOARD_ID_BL_RVP   = 0x2,    // BayLake Board (RVP)
 172   BOARD_ID_BL_FFRD8 = 0x3,    // FFRD8 b'0011
 173   BOARD_ID_BL_FFRD  = 0x4,    // BayLake Board (FFRD)
 174   BOARD_ID_BL_RVP_DDR3L  = 0x5,    // BayLake Board (RVP DDR3L)
 175   BOARD_ID_BL_STHI  = 0x7,    // PPV- STHI Board
 176   BOARD_ID_BB_RVP   = 0x20,   // Bayley Bay Board
 177   BOARD_ID_BS_RVP   = 0x30,   // Bakersport Board
 178   BOARD_ID_CVH      = 0x90,   // Crestview Hills
 179   BOARD_ID_MINNOW2  = 0xA0    // Minnow2
 180
 181 } BOARD_ID_LIST;
 182
 183 typedef enum {
 184   FAB1 = 0,
 185   FAB2 = 1,
 186   FAB3 = 2
 187 } FAB_ID_LIST;
 188
 189 typedef enum {
 190     PR0  = 0,   // FFRD PR0
 191     PR05 = 1,   // FFRD PR0.3 and PR 0.5
 192     PR1  = 2,   // FFRD PR1
 193     PR11 = 3    // FFRD PR1.1
 194 } FFRD_ID_LIST;
 195
 196
 197 //
 198 // VLV2 GPIO GROUP OFFSET
 199 //
 200 #define GPIO_SCORE_OFFSET       0x0000
 201 #define GPIO_NCORE_OFFSET       0x1000
 202 #define GPIO_SSUS_OFFSET        0x2000
 203
 204 //
 205 // GPIO Initialization Data Structure for BayLake.
 206 // SC = SCORE, SS= SSUS
 207 // Note: NC doesn't support GPIO functionality in IO access mode, only support in MMIO access mode.
 208 //
 209
 210 //
 211 // IO space
 212 //
 213 typedef struct{
 214   UINT32  Use_Sel_SC0;
 215   UINT32  Use_Sel_SC1;
 216   UINT32  Use_Sel_SC2;
 217   UINT32  Use_Sel_SS;
 218
 219   UINT32  Io_Sel_SC0;
 220   UINT32  Io_Sel_SC1;
 221   UINT32  Io_Sel_SC2;
 222   UINT32  Io_Sel_SS;
 223
 224   UINT32  GP_Lvl_SC0;
 225   UINT32  GP_Lvl_SC1;
 226   UINT32  GP_Lvl_SC2;
 227   UINT32  GP_Lvl_SS;
 228
 229   UINT32  TPE_SC0;
 230   UINT32  TPE_SS;
 231
 232   UINT32  TNE_SC0;
 233   UINT32  TNE_SS;
 234
 235   UINT32  TS_SC0;
 236   UINT32  TS_SS;
 237
 238   UINT32  WE_SS;
 239 } CFIO_INIT_STRUCT;
 240
 241
 242
 243 //
 244 // CFIO PAD configuration Registers
 245 //
 246 //
 247 // Memory space
 248 //
 249 typedef union {
 250   UINT32 dw;
 251   struct {
 252     UINT32 Func_Pin_Mux:3;  // 0:2 Function of CFIO selection
 253     UINT32 ipslew:2; // 3:4 Pad (P) Slew Rate Controls PAD slew rate check Width
 254     UINT32 inslew:2; // 5:6 Pad (N) Slew Rate Controls PAD slew rate
 255     UINT32 Pull_assign:2; // 7:8 Pull assignment
 256     UINT32 Pull_strength:2; // 9:10 Pull strength
 257     UINT32 Bypass_flop:1; // 11 Bypass flop
 258     UINT32 Filter_en:1; // 12 Filter Enable
 259     UINT32 Hist_ctrl:2; // 13:14 hysteresis control
 260     UINT32 Hist_enb:1; // 15 Hysteresis enable, active low
 261     UINT32 Delay_line:6; // 16:21 Delay line values - Delay values for input or output
 262     UINT32 Reserved:3; // 22:24 Reserved
 263     UINT32 TPE:1; // 25 Trigger Positive Edge Enable
 264     UINT32 TNE:1; // 26 Trigger Negative Edge Enable
 265     UINT32 Reserved2:3; // 27:29 Reserved
 266     UINT32 i1p5sel:1; // 30
 267     UINT32 IODEN:1; // 31 : Open Drain enable. Active high
 268         } r;
 269 } PAD_CONF0;
 270
 271 typedef union{
 272   UINT32 dw;
 273   struct {
 274     UINT32 instr:16; // 0:15 Pad (N) strength.
 275     UINT32 ipstr:16; // 16:31 Pad (P) strength.
 276   }r;
 277 } PAD_CONF1;
 278
 279 typedef union{
 280   UINT32 dw;
 281   struct {
 282     UINT32 pad_val:1; // 0 These registers are implemented as dual read/write with dedicated storage each.
 283     UINT32 ioutenb:1; // 1 output enable
 284     UINT32 iinenb:1; // 2 input enable
 285     UINT32 Reserved:29; // 3:31 Reserved
 286   }r;
 287 } PAD_VAL;
 288
 289 typedef union{
 290   UINT32 GPI;
 291   struct {
 292     UINT32 ihbpen:1; // 0 Pad high by pass enable
 293     UINT32 ihbpinen:1; // 1 Pad high by pass input
 294     UINT32 instaticen:1; // 2 TBD
 295     UINT32 ipstaticen:1; // 3 TBD
 296     UINT32 Overide_strap_pin :1; // 4 DFX indicates if it wants to override the strap pin value on this pad, if exists.
 297     UINT32 Overide_strap_pin_val:1; // 5 In case DFX need to override strap pin value and it exist for the specific pad, this value will be used.
 298     UINT32 TestMode_Pin_Mux:3; // 6:9 DFX Pin Muxing
 299   }r;
 300 } PAD_DFT;
 301
 302 //
 303 // GPIO_USAGE value need to matche the PAD_VAL input/output enable bits.
 304 //
 305 typedef enum {
 306   Native = 0xFF,  // Native, no need to set PAD_VALUE
 307   GPI = 2,    // GPI, input only in PAD_VALUE
 308   GPO = 4,    // GPO, output only in PAD_VALUE
 309   GPIO = 0,      // GPIO, input & output
 310   TRISTS = 6,      // Tri-State
 311   GPIO_NONE
 312 } GPIO_USAGE;
 313
 314 typedef enum {
 315   LO = 0,
 316   HI = 1,
 317   NA = 0xFF
 318 } GPO_D4;
 319
 320 typedef enum {
 321   F0 = 0,
 322   F1 = 1,
 323   F2 = 2,
 324   F3 = 3,
 325   F4 = 4,
 326   F5 = 5,
 327   F6 = 6,
 328   F7 = 7
 329 } GPIO_FUNC_NUM;
 330
 331 //
 332 // Mapping to CONF0 bit 27:24
 333 // Note: Assume "Direct Irq En" is not set, unless specially notified.
 334 //
 335 typedef enum {
 336   TRIG_ = 0,
 337   TRIG_Edge_High = /*BIT3 |*/ BIT1,     // Positive Edge (Rasing)
 338   TRIG_Edge_Low  = /*BIT3 |*/ BIT2,     // Negative Edge (Falling)
 339   TRIG_Edge_Both = /*BIT3 |*/ BIT2 | BIT1,      // Both Edge
 340   TRIG_Level_High= /*BIT3 |*/ BIT1 | BIT0,      // Level High
 341   TRIG_Level_Low = /*BIT3 |*/ BIT2 | BIT0,      // Level Low
 342 } INT_TYPE;
 343
 344 typedef enum {
 345   P_20K_H,      // Pull Up 20K
 346   P_20K_L,      // Pull Down 20K
 347   P_10K_H,      // Pull Up 10K
 348   P_10K_L,      // Pull Down 10K
 349   P_2K_H,       // Pull Up 2K
 350   P_2K_L,       // Pull Down 2K
 351   P_NONE      // Pull None
 352 } PULL_TYPE;
 353
 354 #ifdef EFI_DEBUG
 355   #define GPIO_INIT_ITEM(pad_name, usage, gpod4, func, int_cap, int_type, pull, offset) {pad_name, usage, gpod4, func, /*int_cap,*/ TRIG_##int_type, P_##pull, offset}
 356 #else
 357   #define GPIO_INIT_ITEM(pad_name, usage, gpod4, func, int_cap, int_type, pull, offset) {          usage, gpod4, func, /*int_cap,*/ TRIG_##int_type, P_##pull, offset}
 358 #endif
 359
 360 //
 361 // GPIO CONF & PAD Initialization Data Structure for BayLake GPIOs bits.
 362 // NC = NCORE, SC = SCORE, SS= SSUS
 363 //
 364 typedef struct {
 365
 366 #ifdef EFI_DEBUG
 367   char         pad_name[32];// GPIO Pin Name for debug purpose
 368 #endif
 369
 370   GPIO_USAGE     usage;     // GPIO pin used as Native mode or GPI/GPO/GPIO mode
 371   GPO_D4         gpod4;     // GPO default value
 372   GPIO_FUNC_NUM  func;      // Function Number (F0~F7)
 373   INT_TYPE       int_type;  // Edge or Level trigger, low or high active
 374   PULL_TYPE      pull;      // Pull Up or Down
 375   UINT8          offset;    // Equal with (PCONF0 register offset >> 4 bits)
 376 } GPIO_CONF_PAD_INIT;
 377
 378 //
 379 //typedef UINT64 BOARD_FEATURES
 380 //
 381 typedef struct _EFI_PLATFORM_INFO_HOB {
 382   UINT16                      PlatformType; // Platform Type
 383   UINT8                       BoardId;             // Board ID
 384   UINT8                       BoardRev;            // Board Revision
 385   PLATFORM_FLAVOR             PlatformFlavor;      // Platform Flavor
 386   UINT8                       DDRDaughterCardCh0Id;// DDR daughter card channel 0 id
 387   UINT8                       DDRDaughterCardCh1Id;// DDR daughter card channel 1 id
 388   UINT8                       ECOId;               // ECO applied on platform
 389   UINT16                      IohSku;
 390   UINT8                       IohRevision;
 391   UINT16                      IchSku;
 392   UINT8                       IchRevision;
 393   EFI_PLATFORM_PCI_DATA       PciData;
 394   EFI_PLATFORM_CPU_DATA       CpuData;
 395   EFI_PLATFORM_MEM_DATA       MemData;
 396   EFI_PLATFORM_SYS_DATA       SysData;
 397   EFI_PLATFORM_IGD_DATA       IgdData;
 398   UINT8                       RevisonId;           // Structure Revision ID
 399   EFI_PHYSICAL_ADDRESS        PlatformCfioData;
 400   EFI_PHYSICAL_ADDRESS        PlatformGpioData_NC;
 401   EFI_PHYSICAL_ADDRESS        PlatformGpioData_SC;
 402   EFI_PHYSICAL_ADDRESS        PlatformGpioData_SUS;
 403   EFI_PHYSICAL_ADDRESS        PlatformGpioData_NC_TRI;
 404   EFI_PHYSICAL_ADDRESS        PlatformGpioData_SC_TRI;
 405   EFI_PHYSICAL_ADDRESS        PlatformGpioData_SUS_TRI;
 406   EFI_PHYSICAL_ADDRESS        PlatformGpioData_SUS_PR1;
 407   EFI_PHYSICAL_ADDRESS        PlatformGpioData_SC_PR1_1;
 408   EFI_PHYSICAL_ADDRESS        PlatformGpioData_SUS_PR1_1;
 409
 410   UINT8                       CfioEnabled;
 411   UINT32                      SsidSvid;
 412   UINT16                      AudioSubsystemDeviceId;
 413   UINT64                      AcpiOemId;
 414   UINT64                      AcpiOemTableId;
 415   UINT16                      MemCfgID;
 416 } EFI_PLATFORM_INFO_HOB;
 417
 418 #pragma pack()
 419
 420 EFI_STATUS
 421 GetPlatformInfoHob (
 422   IN CONST EFI_PEI_SERVICES           **PeiServices,
 423   OUT EFI_PLATFORM_INFO_HOB           **PlatformInfoHob
 424   );
 425
 426
 427 EFI_STATUS
 428 InstallPlatformClocksNotify (
 429   IN CONST EFI_PEI_SERVICES           **PeiServices
 430   );
 431
 432 EFI_STATUS
 433 InstallPlatformSysCtrlGPIONotify (
 434   IN CONST EFI_PEI_SERVICES           **PeiServices
 435   );
 436
 437 #endif