Vlv2TbltDevicePkg/Include/Guid/PlatformCpuInfo.h

   1 /*++
   2
   3   Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>
   4
   5   This program and the accompanying materials are licensed and made available under
   6   the terms and conditions of the BSD License that accompanies this distribution.
   7   The full text of the license may be found at
   8   http://opensource.org/licenses/bsd-license.php.
   9
  10   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12
  13
  14
  15 Module Name:
  16
  17   PlatformCpuInfo.h
  18
  19 Abstract:
  20
  21   GUID used for Platform CPU Info Data entries in the HOB list.
  22
  23 --*/
  24
  25 #ifndef _PLATFORM_CPU_INFO_GUID_H_
  26 #define _PLATFORM_CPU_INFO_GUID_H_
  27
  28 #include "CpuType.h"
  29 #include <Library/CpuIA32.h>
  30
  31 #define EFI_PLATFORM_CPU_INFO_GUID \
  32   {\
  33     0xbb9c7ab7, 0xb8d9, 0x4bf3, 0x9c, 0x29, 0x9b, 0xf3, 0x41, 0xe2, 0x17, 0xbc \
  34   }
  35
  36 extern EFI_GUID gEfiPlatformCpuInfoGuid;
  37 extern CHAR16   EfiPlatformCpuInfoVariable[];
  38
  39 //
  40 // Tri-state for feature capabilities and enable/disable.
  41 // [0] clear=feature isn't capable
  42 // [0] set  =feature is capable
  43 // [1] clear=feature is disabled
  44 // [1] set  =feature is enabled
  45 //
  46 #define CPU_FEATURES_CAPABLE      BIT0
  47 #define CPU_FEATURES_ENABLE       BIT1
  48
  49 #define MAX_CACHE_DESCRIPTORS     64
  50 #define MAXIMUM_CPU_BRAND_STRING_LENGTH 48
  51
  52 #pragma pack(1)
  53
  54 typedef struct {
  55   UINT32              FullCpuId;                // [31:0] & 0x0FFF0FFF
  56   UINT32              FullFamilyModelId;        // [31:0] & 0x0FFF0FF0
  57   UINT8               ExtendedFamilyId;         // [27:20]
  58   UINT8               ExtendedModelId;          // [19:16]
  59   UINT8               ProcessorType;            // [13:11]
  60   UINT8               FamilyId;                 // [11:8]
  61   UINT8               Model;                    // [7:4]
  62   UINT8               SteppingId;               // [3:0]
  63 } EFI_CPU_VERSION_INFO; // CPUID.1.EAX
  64
  65 typedef struct {
  66   UINT32              L1InstructionCacheSize;
  67   UINT32              L1DataCacheSize;
  68   UINT32              L2CacheSize;
  69   UINT32              L3CacheSize;
  70   UINT32              TraceCacheSize;
  71   UINT8               CacheDescriptor[MAX_CACHE_DESCRIPTORS];
  72 } EFI_CPU_CACHE_INFO; // CPUID.2.EAX
  73
  74 typedef struct {
  75   UINT8               PhysicalPackages;
  76   UINT8               LogicalProcessorsPerPhysicalPackage;
  77   UINT8               CoresPerPhysicalPackage;
  78   UINT8               ThreadsPerCore;
  79 } EFI_CPU_PACKAGE_INFO; // CPUID.4.EAX
  80
  81 typedef struct {
  82   UINT32              RegEdx;                   // CPUID.5.EAX
  83   UINT8               MaxCState;
  84   UINT8               C0SubCStatesMwait;        // EDX [3:0]
  85   UINT8               C1SubCStatesMwait;        // EDX [7:4]
  86   UINT8               C2SubCStatesMwait;        // EDX [11:8]
  87   UINT8               C3SubCStatesMwait;        // EDX [15:12]
  88   UINT8               C4SubCStatesMwait;        // EDX [19:16]
  89   UINT8               C5SubCStatesMwait;        // EDX [23:20]
  90   UINT8               C6SubCStatesMwait;        // EDX [27:24]
  91   UINT8               C7SubCStatesMwait;        // EDX [31:28]
  92   UINT8               MonitorMwaitSupport;      // ECX [0]
  93   UINT8               InterruptsBreakMwait;     // ECX [1]
  94 } EFI_CPU_CSTATE_INFO; // CPUID.5.EAX
  95
  96 typedef struct {
  97   UINT8               Turbo;                    // EAX [1]
  98   UINT8               PECI;                     // EAX [0]
  99   UINT8               NumIntThresholds;         // EBX [3:0]
 100   UINT8               HwCoordinationFeedback;   // ECX [0]
 101 } EFI_CPU_POWER_MANAGEMENT; // CPUID.6.EAX
 102
 103 //
 104 // IMPORTANT: Each CPU feature enabling entry is assumed a tri-state variable.
 105 //   - Keep the respective feature entry variable as default value (0x00)
 106 //     if the CPU is not capable for the feature.
 107 //   - Use the specially defined programming convention to update the variable
 108 //     to indicate capable, enable or disable.
 109 //     ie. F_CAPABLE for feature available
 110 //         F_ENABLE for feature enable
 111 //         F_DISABLE for feature disable
 112 //
 113 typedef struct {
 114   EFI_CPUID_REGISTER  Regs;                     // CPUID.1.EAX
 115   UINT8               Xapic;                    // ECX [21]
 116   UINT8               SSE4_2;                   // ECX [20]
 117   UINT8               SSE4_1;                   // ECX [19]
 118   UINT8               Dca;                      // ECX [18]
 119   UINT8               SupSSE3;                  // ECX [9]
 120   UINT8               Tm2;                      // ECX [8]
 121   UINT8               Eist;                     // ECX [7]
 122   UINT8               Lt;                       // ECX [6]
 123   UINT8               Vt;                       // ECX [5]
 124   UINT8               Mwait;                    // ECX [3]
 125   UINT8               SSE3;                     // ECX [0]
 126   UINT8               Tcc;                      // EDX [29]
 127   UINT8               Mt;                       // EDX [28]
 128   UINT8               SSE2;                     // EDX [26]
 129   UINT8               SSE;                      // EDX [25]
 130   UINT8               MMX;                      // EDX [23]
 131   EFI_CPUID_REGISTER  ExtRegs;                  // CPUID.80000001.EAX
 132   UINT8               ExtLahfSahf64;            // ECX [0]
 133   UINT8               ExtIntel64;               // EDX [29]
 134   UINT8               ExtXd;                    // EDX [20]
 135   UINT8               ExtSysCallRet64;          // EDX [11]
 136   UINT16              Ht;                       // CPUID.0B.EAX EBX [15:0]
 137 } EFI_CPU_FEATURES; // CPUID.1.EAX, CPUID.0B.EAX, CPUID.80000001.EAX
 138
 139 typedef struct {
 140   UINT8               PhysicalBits;
 141   UINT8               VirtualBits;
 142 } EFI_CPU_ADDRESS_BITS; // CPUID.80000008.EAX
 143
 144 typedef struct {
 145   UINT8               PlatformID;               // MSR 0x17 [52:50]
 146   UINT32              MicrocodeRevision;        // MSR 0x8B [63:32]
 147   UINT8               MaxEfficiencyRatio;       // MSR 0xCE [47:40]
 148   UINT8               DdrRatioUnlockCap;        // MSR 0xCE [30]
 149   UINT8               TdcTdpLimitsTurbo;        // MSR 0xCE [29]
 150   UINT8               RatioLimitsTurbo;         // MSR 0xCE [28]
 151   UINT8               PreProduction;            // MSR 0xCE [27]
 152   UINT8               DcuModeSelect;            // MSR 0xCE [26]
 153   UINT8               MaxNonTurboRatio;         // MSR 0xCE [15:8]
 154   UINT8               Emrr;                     // MSR 0xFE [12]
 155   UINT8               Smrr;                     // MSR 0xFE [11]
 156   UINT8               VariableMtrrCount;        // MSR 0xFE [7:0]
 157   UINT16              PState;                   // MSR 0x198 [15:0]
 158   UINT8               TccActivationTemperature; // MSR 0x1A2 [23:16]
 159   UINT8               TemperatureControlOffset; // MSR 0x1A2 [15:8]
 160   UINT32              PCIeBar;                  // MSR 0x300 [39:20]
 161   UINT8               PCIeBarSizeMB;            // MSR 0x300 [3:1]
 162 } EFI_MSR_FEATURES;
 163
 164 typedef struct {
 165   BOOLEAN                            IsIntelProcessor;
 166   UINT8                              BrandString[MAXIMUM_CPU_BRAND_STRING_LENGTH + 1];
 167   UINT32                             CpuidMaxInputValue;
 168   UINT32                             CpuidMaxExtInputValue;
 169   EFI_CPU_UARCH                      CpuUarch;
 170   EFI_CPU_FAMILY                     CpuFamily;
 171   EFI_CPU_PLATFORM                   CpuPlatform;
 172   EFI_CPU_TYPE                       CpuType;
 173   EFI_CPU_VERSION_INFO               CpuVersion;
 174   EFI_CPU_CACHE_INFO                 CpuCache;
 175   EFI_CPU_FEATURES                   CpuFeatures;
 176   EFI_CPU_CSTATE_INFO                CpuCState;
 177   EFI_CPU_PACKAGE_INFO               CpuPackage;
 178   EFI_CPU_POWER_MANAGEMENT           CpuPowerManagement;
 179   EFI_CPU_ADDRESS_BITS               CpuAddress;
 180   EFI_MSR_FEATURES                   Msr;
 181 } EFI_PLATFORM_CPU_INFO;
 182
 183 #pragma pack()
 184
 185 #endif