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1 | /**\r |
2 | \r | |
3 | Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved\r | |
4 | \r | |
5 | This program and the accompanying materials are licensed and made available under\r | |
6 | the terms and conditions of the BSD License that accompanies this distribution.\r | |
7 | The full text of the license may be found at\r | |
8 | http://opensource.org/licenses/bsd-license.php.\r | |
9 | \r | |
10 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
11 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
12 | \r | |
13 | \r | |
14 | \r | |
15 | @file\r | |
16 | PchAccess.h\r | |
17 | \r | |
18 | @brief\r | |
19 | Macros that simplify accessing PCH devices's PCI registers.\r | |
20 | \r | |
21 | ** NOTE ** these macros assume the PCH device is on BUS 0\r | |
22 | \r | |
23 | **/\r | |
24 | #ifndef _PCH_ACCESS_H_\r | |
25 | #define _PCH_ACCESS_H_\r | |
26 | \r | |
27 | #include "PchRegs.h"\r | |
28 | #include "PchCommonDefinitions.h"\r | |
29 | \r | |
30 | #ifndef STALL_ONE_MICRO_SECOND\r | |
31 | #define STALL_ONE_MICRO_SECOND 1\r | |
32 | #endif\r | |
33 | #ifndef STALL_ONE_SECOND\r | |
34 | #define STALL_ONE_SECOND 1000000\r | |
35 | #endif\r | |
36 | \r | |
37 | ///\r | |
38 | /// Memory Mapped PCI Access macros\r | |
39 | ///\r | |
40 | ///\r | |
41 | /// PCI Device MM Base\r | |
42 | ///\r | |
43 | #ifndef MmPciAddress\r | |
44 | #define MmPciAddress(Segment, Bus, Device, Function, Register) \\r | |
45 | ((UINTN) PatchPcdGet64 (PcdPciExpressBaseAddress) + \\r | |
46 | (UINTN) (Bus << 20) + \\r | |
47 | (UINTN) (Device << 15) + \\r | |
48 | (UINTN) (Function << 12) + \\r | |
49 | (UINTN) (Register) \\r | |
50 | )\r | |
51 | #endif\r | |
52 | ///\r | |
53 | /// Pch Controller PCI access macros\r | |
54 | ///\r | |
55 | #define PCH_RCRB_BASE ( \\r | |
56 | MmioRead32 (MmPciAddress (0, \\r | |
57 | DEFAULT_PCI_BUS_NUMBER_PCH, \\r | |
58 | PCI_DEVICE_NUMBER_PCH_LPC, \\r | |
59 | PCI_FUNCTION_NUMBER_PCH_LPC), \\r | |
60 | R_PCH_LPC_RCBA)) & B_PCH_LPC_RCBA_BAR \\r | |
61 | )\r | |
62 | \r | |
63 | ///\r | |
64 | /// Device 0x1b, Function 0\r | |
65 | ///\r | |
66 | #define PchAzaliaPciCfg32(Register) \\r | |
67 | MmioRead32 ( \\r | |
68 | MmPciAddress (0, \\r | |
69 | DEFAULT_PCI_BUS_NUMBER_PCH, \\r | |
70 | PCI_DEVICE_NUMBER_PCH_AZALIA, \\r | |
71 | 0, \\r | |
72 | Register) \\r | |
73 | )\r | |
74 | \r | |
75 | #define PchAzaliaPciCfg32Or(Register, OrData) \\r | |
76 | MmioOr32 ( \\r | |
77 | MmPciAddress (0, \\r | |
78 | DEFAULT_PCI_BUS_NUMBER_PCH, \\r | |
79 | PCI_DEVICE_NUMBER_PCH_AZALIA, \\r | |
80 | 0, \\r | |
81 | Register), \\r | |
82 | OrData \\r | |
83 | )\r | |
84 | \r | |
85 | #define PchAzaliaPciCfg32And(Register, AndData) \\r | |
86 | MmioAnd32 ( \\r | |
87 | MmPciAddress (0, \\r | |
88 | DEFAULT_PCI_BUS_NUMBER_PCH, \\r | |
89 | PCI_DEVICE_NUMBER_PCH_AZALIA, \\r | |
90 | 0, \\r | |
91 | Register), \\r | |
92 | AndData \\r | |
93 | )\r | |
94 | \r | |
95 | #define PchAzaliaPciCfg32AndThenOr(Register, AndData, OrData) \\r | |
96 | MmioAndThenOr32 ( \\r | |
97 | MmPciAddress (0, \\r | |
98 | DEFAULT_PCI_BUS_NUMBER_PCH, \\r | |
99 | PCI_DEVICE_NUMBER_PCH_AZALIA, \\r | |
100 | 0, \\r | |
101 | Register), \\r | |
102 | OrData \\r | |
103 | )\r | |
104 | \r | |
105 | #define PchAzaliaPciCfg16(Register) \\r | |
106 | MmioRead16 ( \\r | |
107 | MmPciAddress (0, \\r | |
108 | DEFAULT_PCI_BUS_NUMBER_PCH, \\r | |
109 | PCI_DEVICE_NUMBER_PCH_AZALIA, \\r | |
110 | 0, \\r | |
111 | Register) \\r | |
112 | )\r | |
113 | \r | |
114 | #define PchAzaliaPciCfg16Or(Register, OrData) \\r | |
115 | MmioOr16 ( \\r | |
116 | MmPciAddress (0, \\r | |
117 | DEFAULT_PCI_BUS_NUMBER_PCH, \\r | |
118 | PCI_DEVICE_NUMBER_PCH_AZALIA, \\r | |
119 | 0, \\r | |
120 | Register), \\r | |
121 | OrData \\r | |
122 | )\r | |
123 | \r | |
124 | #define PchAzaliaPciCfg16And(Register, AndData) \\r | |
125 | MmioAnd16 ( \\r | |
126 | MmPciAddress (0, \\r | |
127 | DEFAULT_PCI_BUS_NUMBER_PCH, \\r | |
128 | PCI_DEVICE_NUMBER_PCH_AZALIA, \\r | |
129 | 0, \\r | |
130 | Register), \\r | |
131 | AndData \\r | |
132 | )\r | |
133 | \r | |
134 | #define PchAzaliaPciCfg16AndThenOr(Register, AndData, OrData) \\r | |
135 | MmioAndThenOr16 ( \\r | |
136 | MmPciAddress (0, \\r | |
137 | DEFAULT_PCI_BUS_NUMBER_PCH, \\r | |
138 | PCI_DEVICE_NUMBER_PCH_AZALIA, \\r | |
139 | 0, \\r | |
140 | Register), \\r | |
141 | AndData, \\r | |
142 | OrData \\r | |
143 | )\r | |
144 | \r | |
145 | #define PchAzaliaPciCfg8(Register) MmioRead8 (MmPciAddress (0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_AZALIA, 0, Register))\r | |
146 | \r | |
147 | #define PchAzaliaPciCfg8Or(Register, OrData) \\r | |
148 | MmioOr8 ( \\r | |
149 | MmPciAddress (0, \\r | |
150 | DEFAULT_PCI_BUS_NUMBER_PCH, \\r | |
151 | PCI_DEVICE_NUMBER_PCH_AZALIA, \\r | |
152 | 0, \\r | |
153 | Register), \\r | |
154 | OrData \\r | |
155 | )\r | |
156 | \r | |
157 | #define PchAzaliaPciCfg8And(Register, AndData) \\r | |
158 | MmioAnd8 ( \\r | |
159 | MmPciAddress (0, \\r | |
160 | DEFAULT_PCI_BUS_NUMBER_PCH, \\r | |
161 | PCI_DEVICE_NUMBER_PCH_AZALIA, \\r | |
162 | 0, \\r | |
163 | Register), \\r | |
164 | AndData \\r | |
165 | )\r | |
166 | \r | |
167 | #define PchAzaliaPciCfg8AndThenOr(Register, AndData, OrData) \\r | |
168 | MmioAndThenOr8 ( \\r | |
169 | MmPciAddress (0, \\r | |
170 | DEFAULT_PCI_BUS_NUMBER_PCH, \\r | |
171 | PCI_DEVICE_NUMBER_PCH_AZALIA, \\r | |
172 | 0, \\r | |
173 | Register), \\r | |
174 | AndData, \\r | |
175 | OrData \\r | |
176 | )\r | |
177 | \r | |
178 | ///\r | |
179 | /// Device 0x1f, Function 0\r | |
180 | ///\r | |
181 | #define PchLpcPciCfg32(Register) MmioRead32 (MmPciAddress (0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_LPC, 0, Register))\r | |
182 | \r | |
183 | #define PchLpcMmioOr32 (Register, OrData) \\r | |
184 | MmioOr32 ( \\r | |
185 | MmPciAddress (0, \\r | |
186 | DEFAULT_PCI_BUS_NUMBER_PCH, \\r | |
187 | PCI_DEVICE_NUMBER_PCH_LPC, \\r | |
188 | 0, \\r | |
189 | Register), \\r | |
190 | OrData \\r | |
191 | )\r | |
192 | \r | |
193 | #define PchLpcPciCfg32And(Register, AndData) \\r | |
194 | MmioAnd32 ( \\r | |
195 | MmPciAddress (0, \\r | |
196 | DEFAULT_PCI_BUS_NUMBER_PCH, \\r | |
197 | PCI_DEVICE_NUMBER_PCH_LPC, \\r | |
198 | 0, \\r | |
199 | Register), \\r | |
200 | AndData \\r | |
201 | )\r | |
202 | \r | |
203 | #define PchLpcPciCfg32AndThenOr(Register, AndData, OrData) \\r | |
204 | MmioAndThenOr32 ( \\r | |
205 | MmPciAddress (0, \\r | |
206 | DEFAULT_PCI_BUS_NUMBER_PCH, \\r | |
207 | PCI_DEVICE_NUMBER_PCH_LPC, \\r | |
208 | 0, \\r | |
209 | Register), \\r | |
210 | AndData, \\r | |
211 | OrData \\r | |
212 | )\r | |
213 | \r | |
214 | #define PchLpcPciCfg16(Register) MmioRead16 (MmPciAddress (0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_LPC, 0, Register))\r | |
215 | \r | |
216 | #define PchLpcPciCfg16Or(Register, OrData) \\r | |
217 | MmioOr16 ( \\r | |
218 | MmPciAddress (0, \\r | |
219 | DEFAULT_PCI_BUS_NUMBER_PCH, \\r | |
220 | PCI_DEVICE_NUMBER_PCH_LPC, \\r | |
221 | 0, \\r | |
222 | Register), \\r | |
223 | OrData \\r | |
224 | )\r | |
225 | \r | |
226 | #define PchLpcPciCfg16And(Register, AndData) \\r | |
227 | MmioAndThenOr16 ( \\r | |
228 | MmPciAddress (0, \\r | |
229 | DEFAULT_PCI_BUS_NUMBER_PCH, \\r | |
230 | PCI_DEVICE_NUMBER_PCH_LPC, \\r | |
231 | 0, \\r | |
232 | Register), \\r | |
233 | AndData \\r | |
234 | )\r | |
235 | \r | |
236 | #define PchLpcPciCfg16AndThenOr(Register, AndData, OrData) \\r | |
237 | MmioAndThenOr16 ( \\r | |
238 | MmPciAddress (0, \\r | |
239 | DEFAULT_PCI_BUS_NUMBER_PCH, \\r | |
240 | PCI_DEVICE_NUMBER_PCH_LPC, \\r | |
241 | 0, \\r | |
242 | Register), \\r | |
243 | AndData, \\r | |
244 | OrData \\r | |
245 | )\r | |
246 | \r | |
247 | #define PchLpcPciCfg8(Register) MmioRead8 (MmPciAddress (0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_LPC, 0, Register))\r | |
248 | \r | |
249 | #define PchLpcPciCfg8Or(Register, OrData) \\r | |
250 | MmioOr8 ( \\r | |
251 | MmPciAddress (0, \\r | |
252 | DEFAULT_PCI_BUS_NUMBER_PCH, \\r | |
253 | PCI_DEVICE_NUMBER_PCH_LPC, \\r | |
254 | 0, \\r | |
255 | Register), \\r | |
256 | OrData \\r | |
257 | )\r | |
258 | \r | |
259 | #define PchLpcPciCfg8And(Register, AndData) \\r | |
260 | MmioAnd8 ( \\r | |
261 | MmPciAddress (0, \\r | |
262 | DEFAULT_PCI_BUS_NUMBER_PCH, \\r | |
263 | PCI_DEVICE_NUMBER_PCH_LPC, \\r | |
264 | 0, \\r | |
265 | Register), \\r | |
266 | AndData \\r | |
267 | )\r | |
268 | \r | |
269 | #define PchLpcPciCfg8AndThenOr(Register, AndData, OrData) \\r | |
270 | MmioAndThenOr8 ( \\r | |
271 | MmPciAddress (0, \\r | |
272 | DEFAULT_PCI_BUS_NUMBER_PCH, \\r | |
273 | PCI_DEVICE_NUMBER_PCH_LPC, \\r | |
274 | 0, \\r | |
275 | Register), \\r | |
276 | AndData, \\r | |
277 | OrData \\r | |
278 | )\r | |
279 | \r | |
280 | \r | |
281 | ///\r | |
282 | /// SATA device 0x13, Function 0\r | |
283 | ///\r | |
284 | #define PchSataPciCfg32(Register) MmioRead32 (MmPciAddress (0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_SATA, PCI_FUNCTION_NUMBER_PCH_SATA, Register))\r | |
285 | \r | |
286 | #define PchSataPciCfg32Or(Register, OrData) \\r | |
287 | MmioOr32 ( \\r | |
288 | MmPciAddress (0, \\r | |
289 | DEFAULT_PCI_BUS_NUMBER_PCH, \\r | |
290 | PCI_DEVICE_NUMBER_PCH_SATA, \\r | |
291 | PCI_FUNCTION_NUMBER_PCH_SATA, \\r | |
292 | Register), \\r | |
293 | OrData \\r | |
294 | )\r | |
295 | \r | |
296 | #define PchSataPciCfg32And(Register, AndData) \\r | |
297 | MmioAnd32 ( \\r | |
298 | MmPciAddress (0, \\r | |
299 | DEFAULT_PCI_BUS_NUMBER_PCH, \\r | |
300 | PCI_DEVICE_NUMBER_PCH_SATA, \\r | |
301 | PCI_FUNCTION_NUMBER_PCH_SATA, \\r | |
302 | Register), \\r | |
303 | AndData \\r | |
304 | )\r | |
305 | \r | |
306 | #define PchSataPciCfg32AndThenOr(Register, AndData, OrData) \\r | |
307 | MmioAndThenOr32 ( \\r | |
308 | MmPciAddress (0, \\r | |
309 | DEFAULT_PCI_BUS_NUMBER_PCH, \\r | |
310 | PCI_DEVICE_NUMBER_PCH_SATA, \\r | |
311 | PCI_FUNCTION_NUMBER_PCH_SATA, \\r | |
312 | Register), \\r | |
313 | AndData, \\r | |
314 | OrData \\r | |
315 | )\r | |
316 | \r | |
317 | #define PchSataPciCfg16(Register) MmioRead16 (MmPciAddress (0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_SATA, PCI_FUNCTION_NUMBER_PCH_SATA, Register))\r | |
318 | \r | |
319 | #define PchSataPciCfg16Or(Register, OrData) \\r | |
320 | MmioOr16 ( \\r | |
321 | MmPciAddress (0, \\r | |
322 | DEFAULT_PCI_BUS_NUMBER_PCH, \\r | |
323 | PCI_DEVICE_NUMBER_PCH_SATA, \\r | |
324 | PCI_FUNCTION_NUMBER_PCH_SATA, \\r | |
325 | Register), \\r | |
326 | OrData \\r | |
327 | )\r | |
328 | \r | |
329 | #define PchSataPciCfg16And(Register, AndData) \\r | |
330 | MmioAndThenOr16 ( \\r | |
331 | MmPciAddress (0, \\r | |
332 | DEFAULT_PCI_BUS_NUMBER_PCH, \\r | |
333 | PCI_DEVICE_NUMBER_PCH_SATA, \\r | |
334 | PCI_FUNCTION_NUMBER_PCH_SATA, \\r | |
335 | Register), \\r | |
336 | AndData \\r | |
337 | )\r | |
338 | \r | |
339 | #define PchSataPciCfg16AndThenOr(Register, AndData, OrData) \\r | |
340 | MmioAndThenOr16 ( \\r | |
341 | MmPciAddress (0, \\r | |
342 | DEFAULT_PCI_BUS_NUMBER_PCH, \\r | |
343 | PCI_DEVICE_NUMBER_PCH_SATA, \\r | |
344 | PCI_FUNCTION_NUMBER_PCH_SATA, \\r | |
345 | Register), \\r | |
346 | AndData, \\r | |
347 | OrData \\r | |
348 | )\r | |
349 | \r | |
350 | #define PchSataPciCfg8(Register) MmioRead8 (MmPciAddress (0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_SATA, PCI_FUNCTION_NUMBER_PCH_SATA, Register))\r | |
351 | \r | |
352 | #define PchSataPciCfg8Or(Register, OrData) \\r | |
353 | MmioOr8 ( \\r | |
354 | MmPciAddress (0, \\r | |
355 | DEFAULT_PCI_BUS_NUMBER_PCH, \\r | |
356 | PCI_DEVICE_NUMBER_PCH_SATA, \\r | |
357 | PCI_FUNCTION_NUMBER_PCH_SATA, \\r | |
358 | Register), \\r | |
359 | OrData \\r | |
360 | )\r | |
361 | \r | |
362 | #define PchSataPciCfg8And(Register, AndData) \\r | |
363 | MmioAnd8 ( \\r | |
364 | MmPciAddress (0, \\r | |
365 | DEFAULT_PCI_BUS_NUMBER_PCH, \\r | |
366 | PCI_DEVICE_NUMBER_PCH_SATA, \\r | |
367 | PCI_FUNCTION_NUMBER_PCH_SATA, \\r | |
368 | Register), \\r | |
369 | AndData \\r | |
370 | )\r | |
371 | \r | |
372 | #define PchSataPciCfg8AndThenOr(Register, AndData, OrData) \\r | |
373 | MmioAndThenOr8 ( \\r | |
374 | MmPciAddress (0, \\r | |
375 | DEFAULT_PCI_BUS_NUMBER_PCH, \\r | |
376 | PCI_DEVICE_NUMBER_PCH_SATA, \\r | |
377 | PCI_FUNCTION_NUMBER_PCH_SATA, \\r | |
378 | Register), \\r | |
379 | AndData, \\r | |
380 | OrData \\r | |
381 | )\r | |
382 | \r | |
383 | \r | |
384 | ///\r | |
385 | /// Root Complex Register Block\r | |
386 | ///\r | |
387 | #define PchMmRcrb32(Register) MmioRead32 (PCH_RCRB_BASE + Register)\r | |
388 | \r | |
389 | #define PchMmRcrb32Or(Register, OrData) MmioOr32 (PCH_RCRB_BASE + Register, OrData)\r | |
390 | \r | |
391 | #define PchMmRcrb32And(Register, AndData) MmioAnd32 (PCH_RCRB_BASE + Register, AndData)\r | |
392 | \r | |
393 | #define PchMmRcrb32AndThenOr(Register, AndData, OrData) MmioAndThenOr32 (PCH_RCRB_BASE + Register, AndData, OrData)\r | |
394 | \r | |
395 | #define PchMmRcrb16(Register) MmioRead16 (PCH_RCRB_BASE + Register)\r | |
396 | \r | |
397 | #define PchMmRcrb16Or(Register, OrData) MmioOr16 (PCH_RCRB_BASE + Register, OrData)\r | |
398 | \r | |
399 | #define PchMmRcrb16And(Register, AndData) MmioAnd16 (PCH_RCRB_BASE + Register, AndData)\r | |
400 | \r | |
401 | #define PchMmRcrb16AndThenOr(Register, AndData, OrData) MmioAndThenOr16 (PCH_RCRB_BASE + Register, AndData, OrData)\r | |
402 | \r | |
403 | #define PchMmRcrb8(Register) MmioRead8 (PCH_RCRB_BASE + Register)\r | |
404 | \r | |
405 | #define PchMmRcrb8Or(Register, OrData) MmioOr8 (PCH_RCRB_BASE + Register, OrData)\r | |
406 | \r | |
407 | #define PchMmRcrb8And(Register, AndData) MmioAnd8 (PCH_RCRB_BASE + Register, AndData)\r | |
408 | \r | |
409 | #define PchMmRcrb8AndThenOr(Register, AndData, OrData) MmioAndThenOr8 (PCH_RCRB_BASE + Register, AndData, OrData)\r | |
410 | \r | |
411 | \r | |
412 | ///\r | |
413 | /// Message Bus\r | |
414 | ///\r | |
415 | \r | |
416 | ///\r | |
417 | /// Message Bus Registers\r | |
418 | ///\r | |
419 | #define MC_MCR 0x000000D0 // Cunit Message Control Register\r | |
420 | #define MC_MDR 0x000000D4 // Cunit Message Data Register\r | |
421 | #define MC_MCRX 0x000000D8 // Cunit Message Control Register Extension\r | |
422 | \r | |
423 | ///\r | |
424 | /// Message Bus API\r | |
425 | ///\r | |
426 | #define MSG_BUS_ENABLED 0x000000F0\r | |
427 | #define MSGBUS_MASKHI 0xFFFFFF00\r | |
428 | #define MSGBUS_MASKLO 0x000000FF\r | |
429 | #define MESSAGE_DWORD_EN BIT4 | BIT5 | BIT6 | BIT7\r | |
430 | \r | |
431 | #define PchMsgBusRead32(PortId, Register, Dbuff, ReadOpCode, WriteOpCode) \\r | |
432 | { \\r | |
433 | MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCRX), (UINT32) (Register & MSGBUS_MASKHI)); \\r | |
434 | MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCR ), (UINT32) ((ReadOpCode << 24) | (PortId << 16) | ((Register & MSGBUS_MASKLO) << 8) | MESSAGE_DWORD_EN)); \\r | |
435 | (Dbuff) = MmioRead32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MDR)); \\r | |
436 | }\r | |
437 | \r | |
438 | #define PchMsgBusAnd32(PortId, Register, Dbuff, AndData, ReadOpCode, WriteOpCode) \\r | |
439 | { \\r | |
440 | MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCRX), (UINT32) (Register & MSGBUS_MASKHI)); \\r | |
441 | MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCR ), (UINT32) ((ReadOpCode << 24) | (PortId << 16) | ((Register & MSGBUS_MASKLO) << 8) | MESSAGE_DWORD_EN)); \\r | |
442 | (Dbuff) = MmioRead32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MDR)); \\r | |
443 | MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCRX), (UINT32) (Register & MSGBUS_MASKHI)); \\r | |
444 | MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MDR ), (UINT32) (Dbuff & AndData)); \\r | |
445 | MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCR ), (UINT32) ((WriteOpCode << 24) | (PortId << 16) | ((Register & MSGBUS_MASKLO) << 8) | MESSAGE_DWORD_EN)); \\r | |
446 | }\r | |
447 | \r | |
448 | #define PchMsgBusOr32(PortId, Register, Dbuff, OrData, ReadOpCode, WriteOpCode) \\r | |
449 | { \\r | |
450 | MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCRX), (UINT32) (Register & MSGBUS_MASKHI)); \\r | |
451 | MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCR ), (UINT32) ((ReadOpCode << 24) | (PortId << 16) | ((Register & MSGBUS_MASKLO) << 8) | MESSAGE_DWORD_EN)); \\r | |
452 | (Dbuff) = MmioRead32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MDR)); \\r | |
453 | MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCRX), (UINT32) (Register & MSGBUS_MASKHI)); \\r | |
454 | MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MDR ), (UINT32) (Dbuff | OrData)); \\r | |
455 | MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCR ), (UINT32) ((WriteOpCode << 24) | (PortId << 16) | ((Register & MSGBUS_MASKLO) << 8) | MESSAGE_DWORD_EN)); \\r | |
456 | }\r | |
457 | \r | |
458 | #define PchMsgBusAndThenOr32(PortId, Register, Dbuff, AndData, OrData, ReadOpCode, WriteOpCode) \\r | |
459 | { \\r | |
460 | MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCRX), (UINT32) (Register & MSGBUS_MASKHI)); \\r | |
461 | MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCR ), (UINT32) ((ReadOpCode << 24) | (PortId << 16) | ((Register & MSGBUS_MASKLO) << 8) | MESSAGE_DWORD_EN)); \\r | |
462 | (Dbuff) = MmioRead32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MDR)); \\r | |
463 | MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCRX), (UINT32) (Register & MSGBUS_MASKHI)); \\r | |
464 | MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MDR ), (UINT32) ((Dbuff & AndData) | OrData)); \\r | |
465 | MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCR ), (UINT32) ((WriteOpCode << 24) | (PortId << 16) | ((Register & MSGBUS_MASKLO) << 8) | MESSAGE_DWORD_EN)); \\r | |
466 | }\r | |
467 | \r | |
468 | typedef struct _PCH_MSG_BUS_TABLE_STRUCT {\r | |
469 | UINT32 PortId;\r | |
470 | UINT32 Address;\r | |
471 | UINT32 AndMask;\r | |
472 | UINT32 OrMask;\r | |
473 | UINT32 ReadOpCode;\r | |
474 | UINT32 WriteOpCode;\r | |
475 | } PCH_MSG_BUS_TABLE_STRUCT_TABLE_STRUCT;\r | |
476 | \r | |
3cbfba02 | 477 | #endif\r |