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1 | /**\r |
2 | **/\r | |
3 | /**\r | |
4 | \r | |
5 | Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved\r | |
6 | \r | |
7 | This program and the accompanying materials are licensed and made available under\r | |
8 | the terms and conditions of the BSD License that accompanies this distribution.\r | |
9 | The full text of the license may be found at\r | |
10 | http://opensource.org/licenses/bsd-license.php.\r | |
11 | \r | |
12 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
13 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
14 | \r | |
15 | \r | |
16 | \r | |
17 | @file\r | |
18 | PchUsbPolicy.h\r | |
19 | \r | |
20 | @brief\r | |
21 | PCH Usb policy PPI produced by a platform driver specifying\r | |
22 | various expected PCH Usb settings. This PPI is consumed by the\r | |
23 | PCH PEI drivers.\r | |
24 | \r | |
25 | **/\r | |
26 | #ifndef _PCH_USB_POLICY_H_\r | |
27 | #define _PCH_USB_POLICY_H_\r | |
28 | \r | |
29 | //\r | |
30 | // PCH Usb policy provided by platform for PEI phase\r | |
31 | //\r | |
32 | \r | |
33 | #ifndef ECP_FLAG\r | |
34 | #include <PiPei.h>\r | |
35 | #endif\r | |
36 | \r | |
37 | #include "PchRegs.h"\r | |
38 | #include <Protocol/PchPlatformPolicy.h>\r | |
39 | \r | |
40 | #define PCH_USB_POLICY_PPI_GUID \\r | |
41 | { \\r | |
42 | 0xc02b0573, 0x2b4e, 0x4a31, 0xa3, 0x1a, 0x94, 0x56, 0x7b, 0x50, 0x44, 0x2c \\r | |
43 | }\r | |
44 | \r | |
45 | extern EFI_GUID gPchUsbPolicyPpiGuid;\r | |
46 | \r | |
47 | typedef struct _PCH_USB_POLICY_PPI PCH_USB_POLICY_PPI;\r | |
48 | \r | |
49 | ///\r | |
50 | /// PPI revision number\r | |
51 | /// Any backwards compatible changes to this PPI will result in an update in the revision number\r | |
52 | /// Major changes will require publication of a new PPI\r | |
53 | ///\r | |
54 | /// Revision 1: Original version\r | |
55 | ///\r | |
56 | #define PCH_USB_POLICY_PPI_REVISION_1 1\r | |
57 | \r | |
58 | ///\r | |
59 | /// Generic definitions for device enabling/disabling used by PCH code.\r | |
60 | ///\r | |
61 | #define PCH_DEVICE_ENABLE 1\r | |
62 | #define PCH_DEVICE_DISABLE 0\r | |
63 | \r | |
64 | #define EHCI_MODE 1\r | |
65 | \r | |
66 | struct _PCH_USB_POLICY_PPI {\r | |
67 | UINT8 Revision;\r | |
68 | PCH_USB_CONFIG *UsbConfig;\r | |
69 | UINT8 Mode;\r | |
70 | UINTN EhciMemBaseAddr;\r | |
71 | UINT32 EhciMemLength;\r | |
72 | UINTN XhciMemBaseAddr;\r | |
73 | };\r | |
74 | \r | |
75 | #endif\r |