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1 | /*++\r |
2 | \r | |
3 | Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved\r | |
4 | \r | |
5 | This program and the accompanying materials are licensed and made available under\r | |
6 | the terms and conditions of the BSD License that accompanies this distribution.\r | |
7 | The full text of the license may be found at\r | |
8 | http://opensource.org/licenses/bsd-license.php.\r | |
9 | \r | |
10 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
11 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
12 | \r | |
13 | \r | |
14 | \r | |
15 | Module Name:\r | |
16 | \r | |
17 | Gpio.h\r | |
18 | \r | |
19 | Abstract:\r | |
20 | \r | |
21 | EFI 2.0 PEIM to provide platform specific information to other\r | |
22 | modules and to do some platform specific initialization.\r | |
23 | \r | |
24 | --*/\r | |
25 | \r | |
26 | #ifndef _PEI_GPIO_H\r | |
27 | #define _PEI_GPIO_H\r | |
28 | \r | |
29 | //#include "Efi.h"\r | |
30 | //#include "EfiCommonLib.h"\r | |
31 | //#include "Pei.h"\r | |
32 | //#include "Numbers.h"\r | |
33 | \r | |
34 | ////\r | |
35 | //// GPIO Register Settings for BeaverBridge (FFVS) (Cedarview/Tigerpoint)\r | |
36 | ////\r | |
37 | //// Field Descriptions:\r | |
38 | //// USE: Defines the pin's usage model: GPIO (G) or Native (N) mode.\r | |
39 | //// I/O: Defines whether GPIOs are inputs (I) or outputs (O).\r | |
40 | //// (Note: Only meaningful for pins used as GPIOs.)\r | |
41 | //// LVL: This field gives you the initial value for "output" GPIO's.\r | |
42 | //// (Note: The output level is dependent upon whether the pin is inverted.)\r | |
43 | //// INV: Defines whether Input GPIOs activation level is inverted.\r | |
44 | //// (Note: Only affects the level sent to the GPE logic and does not\r | |
45 | //// affect the level read through the GPIO registers.)\r | |
46 | ////\r | |
47 | //// Notes:\r | |
48 | //// 1. BoardID is GPIO [8:38:34]\r | |
49 | ////\r | |
50 | ////Signal UsedAs USE I/O LVL INV\r | |
51 | ////--------------------------------------------------------------------------\r | |
52 | ////GPIO0 Nonfunction G O H -\r | |
53 | ////GPIO1 SMC_RUNTIME_SCI# G I - I\r | |
54 | ////PIRQE#/GPIO2 Nonfunction G O H -\r | |
55 | ////PIRQF#/GPIO3 Nonfunction G O H -\r | |
56 | ////PIRQG#/GPIO4 Nonfunction G O H -\r | |
57 | ////PIRQH#/GPIO5 Nonfunction G O H -\r | |
58 | ////GPIO6 unused G O L -\r | |
59 | ////GPIO7 unused G O L -\r | |
60 | ////GPIO8 BOARD ID2 G I - -\r | |
61 | ////GPIO9 unused G O L -\r | |
62 | ////GPIO10 SMC_EXTSMI# G I - I\r | |
63 | ////GPIO11 Nonfunction G O H -\r | |
64 | ////GPIO12 unused G O L -\r | |
65 | ////GPIO13 SMC_WAKE_SCI# G I - I\r | |
66 | ////GPIO14 unused G O L -\r | |
67 | ////GPIO15 unused G O L -\r | |
68 | ////GPIO16 PM_DPRSLPVR N - - -\r | |
69 | ////GNT5#/GPIO17 GNT5# N - - -\r | |
70 | ////STPPCI#/GPIO18 PM_STPPCI# N - - -\r | |
71 | ////STPCPU#/GPIO20 PM_STPCPU# N - - -\r | |
72 | ////GPIO22 CRT_RefClk G I - -\r | |
73 | ////GPIO23 unused G O L -\r | |
74 | ////GPIO24 unused G O L -\r | |
75 | ////GPIO25 DMI strap G O L -\r | |
76 | ////GPIO26 unused G O L -\r | |
77 | ////GPIO27 unused G O L -\r | |
78 | ////GPIO28 RF_KILL# G O H -\r | |
79 | ////OC5#/GPIO29 OC N - - -\r | |
80 | ////OC6#/GPIO30 OC N - - -\r | |
81 | ////OC7#/GPIO31 OC N - - -\r | |
82 | ////CLKRUN#/GPIO32 PM_CLKRUN# N - - -\r | |
83 | ////GPIO33 NC G O L -\r | |
84 | ////GPIO34 BOARD ID0 G I - -\r | |
85 | ////GPIO36 unused G O L -\r | |
86 | ////GPIO38 BOARD ID1 G I - -\r | |
87 | ////GPIO39 unused G O L -\r | |
88 | ////GPIO48 unused G O L -\r | |
89 | ////CPUPWRGD/GPIO49 H_PWRGD N - - -\r | |
90 | //\r | |
91 | //#define GPIO_USE_SEL_VAL 0x1FC0FFFF //GPIO1, 10, 13 is EC signal\r | |
92 | //#define GPIO_USE_SEL2_VAL 0x000100D6\r | |
93 | //#define GPIO_IO_SEL_VAL 0x00402502\r | |
94 | //#define GPIO_IO_SEL2_VAL 0x00000044\r | |
95 | //#define GPIO_LVL_VAL 0x1800083D\r | |
96 | //#define GPIO_LVL2_VAL 0x00000000\r | |
97 | //#define GPIO_INV_VAL 0x00002402\r | |
98 | //#define GPIO_BLNK_VAL 0x00000000\r | |
99 | //#define ICH_GPI_ROUTE (ICH_GPI_ROUTE_SCI(13) | ICH_GPI_ROUTE_SCI(1))\r | |
100 | \r | |
101 | //\r | |
102 | // GPIO Register Settings for CedarRock and CedarFalls platforms\r | |
103 | //\r | |
104 | // GPIO Register Settings for NB10_CRB\r | |
105 | //---------------------------------------------------------------------------------\r | |
106 | //Signal Used As USE I/O LVL\r | |
107 | //---------------------------------------------------------------------------------\r | |
108 | //\r | |
109 | // GPIO0 FP_AUDIO_DETECT G I\r | |
110 | // GPIO1 SMC_RUNTIME_SCI# G I\r | |
111 | // GPIO2 INT_PIRQE_N N I\r | |
112 | // GPIO3 INT_PIRQF_N N I\r | |
113 | // GPIO4 INT_PIRQG_N N I\r | |
114 | // GPIO5 INT_PIRQH_N N I\r | |
115 | // GPIO6\r | |
116 | // GPIO7\r | |
117 | // GPIO8\r | |
118 | // GPIO9 LPC_SIO_PME G I\r | |
119 | // GPIO10 SMC_EXTSMI_N G I\r | |
120 | // GPIO11 SMBALERT- pullup N\r | |
121 | // GPIO12 ICH_GP12 G I\r | |
122 | // GPIO13 SMC_WAKE_SCI_N G I\r | |
123 | // GPIO14 LCD_PID0 G O H\r | |
124 | // GPIO15 CONFIG_MODE_N G I\r | |
125 | // GPIO16 PM_DPRSLPVR N\r | |
126 | // GPIO17 SPI_SELECT_STRAP1\r | |
127 | // /L_BKLTSEL0_N G I\r | |
128 | // GPIO18 PM_STPPCI_N N\r | |
129 | // GPIO19\r | |
130 | // GPIO20 PM_STPCPU_N N\r | |
131 | // GPIO21\r | |
132 | // GPIO22 REQ4B G I\r | |
133 | // GPIO23 L_DRQ1_N N\r | |
134 | // GPIO24 CRB_SV_DET_N G O H\r | |
135 | // GPIO25 DMI strap\r | |
136 | // / L_BKLTSEL1_N G O H\r | |
137 | // GPIO26 LCD_PID1 G O H\r | |
138 | // GPIO27 TPEV_DDR3L_DETECT G O H\r | |
139 | // GPIO28 RF_KILL G O H:enable\r | |
140 | // GPIO29 OC N\r | |
141 | // GPIO30 OC N\r | |
142 | // GPIO31 OC N\r | |
143 | // GPIO32 PM_CLKRUN_N Native\r | |
144 | // GPIO33 MFG_MODE_N G I\r | |
145 | // GPIO34 BOARD ID0 G I\r | |
146 | // GPIO35\r | |
147 | // GPIO36 SV_SET_UP G O H\r | |
148 | // GPIO37\r | |
149 | // GPIO38 BOARD ID1 G I\r | |
150 | // GPIO39 BOARD ID2 G I\r | |
151 | // GPIO48 FLASH_SEL0 N\r | |
152 | // GPIO49 H_PWRGD N\r | |
153 | \r | |
154 | #define ICH_GPI_ROUTE_SMI(Gpio) ((( 0 << ((Gpio * 2) + 1)) | (1 << (Gpio * 2))))\r | |
155 | #define ICH_GPI_ROUTE_SCI(Gpio) ((( 1 << ((Gpio * 2) + 1)) | (0 << (Gpio * 2))))\r | |
156 | \r | |
157 | #define GPIO_USE_SEL_VAL 0X1F42F7C3\r | |
158 | #define GPIO_USE_SEL2_VAL 0X000000D6\r | |
159 | #define GPIO_IO_SEL_VAL 0X1042B73F\r | |
160 | #define GPIO_IO_SEL2_VAL 0X000100C6\r | |
161 | #define GPIO_LVL_VAL 0X1F15F601\r | |
162 | #define GPIO_LVL2_VAL 0X000200D7\r | |
163 | #define GPIO_INV_VAL 0x00002602\r | |
164 | #define GPIO_BLNK_VAL 0x00040000\r | |
165 | #define ICH_GPI_ROUTE (ICH_GPI_ROUTE_SCI(13) | ICH_GPI_ROUTE_SCI(1))\r | |
166 | \r | |
167 | #endif\r |